+20150201 4.1
+ - Rewrite of the SD card interface to fix compatibility problems.
+ This fixes write issues with Samsung SD cards.
+ - Workaround for SCSI hosts that set 250ms timeouts. Some NCR53C80/53C9X
+ drivers (openbsd, netbsd, and others) set a byte-to-byte timeout which
+ can be exceeded by SD card latency.
+ - Upgrade to PSoC Creator 3.1 and gcc 4.8.4.
+
20150108 4.0
- Fix handling requests for LUNs other than 0 from SCSI-2 hosts.
- Handle glitches of the scsi signals to improve stability and operate with
\r
#include "device.h"\r
#include "config.h"\r
+#include "debug.h"\r
#include "USBFS.h"\r
#include "led.h"\r
\r
\r
#include <string.h>\r
\r
-static const uint16_t FIRMWARE_VERSION = 0x0403;\r
+static const uint16_t FIRMWARE_VERSION = 0x0410;\r
\r
enum USB_ENDPOINTS\r
{\r
}\r
else\r
{\r
- uint8_t spcBuffer[CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE];\r
- CyFlash_Start();\r
- CySetFlashEEBuffer(spcBuffer);\r
CySetTemp();\r
int status = CyWriteRowData(flashArray, flashRow, cmd + 1);\r
- CyFlash_Stop();\r
\r
uint8_t response[] =\r
{\r
hidPacket_send(response, sizeof(response));\r
}\r
\r
+static void\r
+sdInfoCommand()\r
+{\r
+ uint8_t response[sizeof(sdDev.csd) + sizeof(sdDev.cid)];\r
+ memcpy(response, sdDev.csd, sizeof(sdDev.csd));\r
+ memcpy(response + sizeof(sdDev.csd), sdDev.cid, sizeof(sdDev.cid));\r
+\r
+ hidPacket_send(response, sizeof(response));\r
+}\r
static void\r
processCommand(const uint8_t* cmd, size_t cmdSize)\r
{\r
Bootloadable_1_Load();\r
break;\r
\r
+ case CONFIG_SDINFO:\r
+ sdInfoCommand();\r
+ break;\r
+\r
case CONFIG_NONE: // invalid\r
default:\r
break;\r
hidBuffer[24] = scsiDev.cmdCount;\r
hidBuffer[25] = scsiDev.watchdogTick;\r
hidBuffer[26] = blockDev.state;\r
- \r
+ hidBuffer[27] = scsiDev.lastSenseASC >> 8;\r
+ hidBuffer[28] = scsiDev.lastSenseASC;\r
+\r
+\r
hidBuffer[58] = sdDev.capacity >> 24;\r
hidBuffer[59] = sdDev.capacity >> 16;\r
hidBuffer[60] = sdDev.capacity >> 8;\r
Debug_Timer_Start();\r
}\r
\r
+void debugPause()\r
+{\r
+ Debug_Timer_Stop();\r
+}\r
+\r
+void debugResume()\r
+{\r
+ Debug_Timer_Start();\r
+}\r
+\r
// Public method for storing MODE SELECT results.\r
void configSave(int scsiId, uint16_t bytesPerSector)\r
{\r
memcpy(rowCfgData, tgt, sizeof(rowData));\r
rowCfgData->bytesPerSector = bytesPerSector;\r
\r
-\r
- uint8_t spcBuffer[CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE];\r
- CyFlash_Start();\r
- CySetFlashEEBuffer(spcBuffer);\r
CySetTemp();\r
CyWriteRowData(\r
SCSI_CONFIG_ARRAY,\r
SCSI_CONFIG_0_ROW + (cfgIdx * SCSI_CONFIG_ROWS),\r
(uint8_t*)rowCfgData);\r
- CyFlash_Stop();\r
return;\r
}\r
}\r
--- /dev/null
+// Copyright (C) 2015 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+#ifndef Debug_H
+#define Debug_H
+
+void debugInit(void);
+void debugPause(void);
+void debugResume(void);
+
+#endif
+
#include "scsi.h"\r
#include "scsiPhy.h"\r
#include "config.h"\r
+#include "debug.h"\r
+#include "debug.h"\r
#include "disk.h"\r
#include "sd.h"\r
#include "time.h"\r
\r
void scsiDiskPoll()\r
{\r
+ debugPause(); // TODO comment re. timeouts.\r
+\r
if (scsiDev.phase == DATA_IN &&\r
transfer.currentBlock != transfer.blocks)\r
{\r
int prep = 0;\r
int i = 0;\r
int scsiDisconnected = 0;\r
- volatile uint32_t lastActivityTime = getTime_ms();\r
+ int scsiComplete = 0;\r
+ uint32_t lastActivityTime = getTime_ms();\r
int scsiActive = 0;\r
int sdActive = 0;\r
- \r
+\r
while ((i < totalSDSectors) &&\r
- (scsiDev.phase == DATA_OUT) && // scsiDisconnect keeps our phase.\r
+ ((scsiDev.phase == DATA_OUT) || // scsiDisconnect keeps our phase.\r
+ scsiComplete) &&\r
!scsiDev.resetFlag)\r
{\r
- if ((sdActive == 1) && sdWriteSectorDMAPoll())\r
+ if ((sdActive == 1) && sdWriteSectorDMAPoll(i == (totalSDSectors - 1)))\r
{\r
sdActive = 0;\r
i++;\r
sdActive = 1;\r
}\r
\r
+ uint32_t now = getTime_ms();\r
+\r
if ((scsiActive == 1) && scsiReadDMAPoll())\r
{\r
scsiActive = 0;\r
++prep;\r
- lastActivityTime = getTime_ms();\r
+ lastActivityTime = now;\r
}\r
else if ((scsiActive == 0) &&\r
((prep - i) < buffers) &&\r
(scsiActive == 0) &&\r
!scsiDisconnected &&\r
scsiDev.discPriv &&\r
- (diffTime_ms(lastActivityTime, getTime_ms()) >= 20) &&\r
+ (diffTime_ms(lastActivityTime, now) >= 20) &&\r
(scsiDev.phase == DATA_OUT))\r
{\r
// We're transferring over the SCSI bus faster than the SD card\r
(prep == i) || // Buffers empty.\r
// Send some messages every 100ms so we don't timeout.\r
// At a minimum, a reselection involves an IDENTIFY message.\r
- (diffTime_ms(lastActivityTime, getTime_ms()) >= 100)\r
+ (diffTime_ms(lastActivityTime, now) >= 100)\r
))\r
{\r
int reconnected = scsiReconnect();\r
scsiDev.resetFlag = 1;\r
}\r
}\r
+ else if (\r
+ !scsiComplete &&\r
+ (sdActive == 1) &&\r
+ (prep == totalSDSectors) && // All scsi data read and buffered\r
+ !scsiDev.discPriv && // Prefer disconnect where possible.\r
+ (diffTime_ms(lastActivityTime, now) >= 150) &&\r
+\r
+ (scsiDev.phase == DATA_OUT) &&\r
+ !(scsiDev.cdb[scsiDev.cdbLen - 1] & 0x01) // Not linked command\r
+ )\r
+ {\r
+ // We're transferring over the SCSI bus faster than the SD card\r
+ // can write. All data is buffered, and we're just waiting for\r
+ // the SD card to complete. The host won't let us disconnect.\r
+ // Some drivers set a 250ms timeout on transfers to complete.\r
+ // SD card writes are supposed to complete\r
+ // within 200ms, but sometimes they don'to.\r
+ // Just pretend we're finished.\r
+ scsiComplete = 1;\r
+\r
+ process_Status();\r
+ process_MessageIn(); // Will go to BUS_FREE state\r
+\r
+ // Try and prevent anyone else using the SCSI bus while we're not ready.\r
+ SCSI_SetPin(SCSI_Out_BSY); \r
+ }\r
}\r
\r
+ if (scsiComplete)\r
+ {\r
+ SCSI_ClearPin(SCSI_Out_BSY);\r
+ }\r
while (\r
!scsiDev.resetFlag &&\r
scsiDisconnected &&\r
}\r
scsiDiskReset();\r
}\r
+ debugResume(); // TODO comment re. timeouts.\r
}\r
\r
void scsiDiskReset()\r
}\r
transfer.inProgress = 0;\r
transfer.multiBlock = 0;\r
+ // SD_CS_Write(1);\r
+\r
}\r
\r
void scsiDiskInit()\r
\r
const char* Notice = "Copyright (C) 2014 Michael McMaster <michael@codesrc.com>";\r
\r
+uint8_t testData[512];\r
+\r
int main()\r
{\r
timeInit();\r
\r
scsiInit();\r
scsiDiskInit();\r
- \r
+\r
uint32_t lastSDPoll = getTime_ms();\r
sdPoll();\r
- \r
+\r
+\r
+\r
+\r
while (1)\r
{\r
scsiDev.watchdogTick++;\r
scsiPoll();\r
scsiDiskPoll();\r
configPoll();\r
- \r
+\r
uint32_t now = getTime_ms();\r
if (diffTime_ms(lastSDPoll, now) > 200)\r
{\r
static void process_SelectionPhase(void);\r
static void enter_BusFree(void);\r
static void enter_MessageIn(uint8 message);\r
-static void process_MessageIn(void);\r
static void enter_Status(uint8 status);\r
-static void process_Status(void);\r
static void enter_DataIn(int len);\r
static void process_DataIn(void);\r
static void process_DataOut(void);\r
scsiDev.phase = MESSAGE_IN;\r
}\r
\r
-static void process_MessageIn()\r
+void process_MessageIn()\r
{\r
scsiEnterPhase(MESSAGE_IN);\r
scsiWriteByte(scsiDev.msgIn);\r
\r
scsiDev.lastStatus = scsiDev.status;\r
scsiDev.lastSense = scsiDev.target->sense.code;\r
+ scsiDev.lastSenseASC = scsiDev.target->sense.asc;\r
}\r
\r
-static void process_Status()\r
+void process_Status()\r
{\r
scsiEnterPhase(STATUS);\r
\r
\r
scsiDev.lastStatus = scsiDev.status;\r
scsiDev.lastSense = scsiDev.target->sense.code;\r
+ scsiDev.lastSenseASC = scsiDev.target->sense.asc;\r
+\r
\r
// Command Complete occurs AFTER a valid status has been\r
// sent. then we go bus-free.\r
// There is no guarantee that the RST line will be negated by then.\r
// NOTE: We could be connected and powered by USB for configuration,\r
// in which case TERMPWR cannot be supplied, and reset will ALWAYS\r
- // be true.\r
- CyDelay(10); // 10ms.\r
+ // be true. Therefore, the sleep here must be slow to avoid slowing\r
+ // USB comms\r
+ CyDelay(1); // 1ms.\r
}\r
\r
static void enter_SelectionPhase()\r
int phase;
- uint8 data[MAX_SECTOR_SIZE];
+ uint8 data[MAX_SECTOR_SIZE * 2];
int dataPtr; // Index into data, reset on [re]selection to savedDataPtr
int savedDataPtr; // Index into data, initially 0.
int dataLen;
uint8 watchdogTick;
uint8 lastStatus;
uint8 lastSense;
+ uint16_t lastSenseASC;
} ScsiDevice;
extern ScsiDevice scsiDev;
+void process_Status(void);
+void process_MessageIn(void);
+
void scsiInit(void);
void scsiPoll(void);
void scsiDisconnect(void);
// Global\r
SdDevice sdDev;\r
\r
+enum SD_IO_STATE { SD_DMA, SD_ACCEPTED, SD_BUSY, SD_IDLE };\r
+static int sdIOState = SD_IDLE;\r
+\r
// Private DMA variables.\r
-static int dmaInProgress = 0;\r
static uint8 sdDMARxChan = CY_DMA_INVALID_CHANNEL;\r
static uint8 sdDMATxChan = CY_DMA_INVALID_CHANNEL;\r
\r
// DMA descriptors\r
static uint8 sdDMARxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };\r
-static uint8 sdDMATxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };\r
+static uint8 sdDMATxTd[3] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };\r
\r
// Dummy location for DMA to send unchecked CRC bytes to\r
static uint8 discardBuffer;\r
\r
+// 2 bytes CRC, response, 8bits to close the clock..\r
+// "NCR" time is up to 8 bytes.\r
+static uint8_t writeResponseBuffer[8];\r
+\r
+static uint8_t writeStartToken = 0xFC;\r
+\r
// Source of dummy SPI bytes for DMA\r
static uint8 dummyBuffer = 0xFF;\r
\r
}\r
\r
// Read and write 1 byte.\r
-static uint8 sdSpiByte(uint8 value)\r
+static uint8_t sdSpiByte(uint8_t value)\r
{\r
SDCard_WriteTxData(value);\r
while (!(SDCard_ReadRxStatus() & SDCard_STS_RX_FIFO_NOT_EMPTY)) {}\r
return SDCard_ReadRxData();\r
}\r
\r
-static void sdSendCRCCommand(uint8 cmd, uint32 param)\r
+static uint16_t sdDoCommand(\r
+ uint8_t cmd,\r
+ uint32_t param,\r
+ int useCRC,\r
+ int use2byteResponse)\r
{\r
- uint8 send[6];\r
+ uint8_t send[7];\r
\r
send[0] = cmd | 0x40;\r
send[1] = param >> 24;\r
send[2] = param >> 16;\r
send[3] = param >> 8;\r
send[4] = param;\r
- send[5] = (sdCrc7(send, 5, 0) << 1) | 1;\r
-\r
- for(cmd = 0; cmd < sizeof(send); cmd++)\r
+ if (useCRC)\r
{\r
- sdSpiByte(send[cmd]);\r
+ send[5] = (sdCrc7(send, 5, 0) << 1) | 1;\r
}\r
- // Allow command to process before reading result code.\r
- sdSpiByte(0xFF);\r
-}\r
+ else\r
+ {\r
+ send[5] = 1; // stop bit\r
+ }\r
+ send[6] = 0xFF; // Result code or stuff byte.\r
\r
-static void sdSendCommand(uint8 cmd, uint32 param)\r
-{\r
- uint8 send[6];\r
+ CyDmaTdSetConfiguration(sdDMATxTd[0], sizeof(send), CY_DMA_DISABLE_TD, TD_INC_SRC_ADR|SD_TX_DMA__TD_TERMOUT_EN);\r
+ CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&send), LO16((uint32)SDCard_TXDATA_PTR));\r
+ CyDmaTdSetConfiguration(sdDMARxTd[0], sizeof(send), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);\r
+ CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));\r
+ // The DMA controller is a bit trigger-happy. It will retain\r
+ // a drq request that was triggered while the channel was\r
+ // disabled.\r
+ CyDmaClearPendingDrq(sdDMATxChan);\r
+ CyDmaClearPendingDrq(sdDMARxChan);\r
\r
- send[0] = cmd | 0x40;\r
- send[1] = param >> 24;\r
- send[2] = param >> 16;\r
- send[3] = param >> 8;\r
- send[4] = param;\r
- send[5] = 1; // 7:1 CRC, 0: Stop bit.\r
+ txDMAComplete = 0;\r
+ rxDMAComplete = 0;\r
\r
- for(cmd = 0; cmd < sizeof(send); cmd++)\r
+ CyDmaChSetInitialTd(sdDMARxChan, sdDMARxTd[0]);\r
+ CyDmaChSetInitialTd(sdDMATxChan, sdDMATxTd[0]);\r
+\r
+ // There is no flow control, so we must ensure we can read the bytes\r
+ // before we start transmitting\r
+ CyDmaChEnable(sdDMARxChan, 1);\r
+ CyDmaChEnable(sdDMATxChan, 1);\r
+\r
+ while (!(txDMAComplete && rxDMAComplete)) {}\r
+\r
+ uint16_t response = discardBuffer;\r
+ if (cmd == SD_STOP_TRANSMISSION)\r
{\r
- sdSpiByte(send[cmd]);\r
+ // Stuff byte is required for this command only.\r
+ // Part 1 Simplified standard 3.01\r
+ // "The stop command has an execution delay due to the serial command\r
+ // transmission."\r
+ response = sdSpiByte(0xFF);\r
}\r
- // Allow command to process before reading result code.\r
- sdSpiByte(0xFF);\r
-}\r
\r
-static uint8 sdReadResp()\r
-{\r
- uint8 v;\r
- uint8 i = 128;\r
- do\r
+ uint32_t start = getTime_ms();\r
+ while ((response & 0x80) && (diffTime_ms(start, getTime_ms()) <= 200))\r
+ {\r
+ response = sdSpiByte(0xFF);\r
+ }\r
+ if (use2byteResponse)\r
{\r
- v = sdSpiByte(0xFF);\r
- } while(i-- && (v & 0x80));\r
- return v;\r
+ response = (response << 8) | sdSpiByte(0xFF);\r
+ }\r
+ return response;\r
}\r
\r
-static uint8 sdCommandAndResponse(uint8 cmd, uint32 param)\r
+\r
+static uint16_t sdCommandAndResponse(uint8_t cmd, uint32_t param)\r
{\r
- sdSpiByte(0xFF);\r
- sdSendCommand(cmd, param);\r
- return sdReadResp();\r
+ // Some Samsung cards enter a busy-state after single-sector reads.\r
+ // But we also need to wait for R1B to complete from the multi-sector\r
+ // reads.\r
+ while (sdSpiByte(0xFF) == 0x00) {}\r
+ return sdDoCommand(cmd, param, 0, 0);\r
}\r
\r
-static uint8 sdCRCCommandAndResponse(uint8 cmd, uint32 param)\r
+static uint16_t sdCRCCommandAndResponse(uint8_t cmd, uint32_t param)\r
{\r
- sdSpiByte(0xFF);\r
- sdSendCRCCommand(cmd, param);\r
- return sdReadResp();\r
+ // Some Samsung cards enter a busy-state after single-sector reads.\r
+ // But we also need to wait for R1B to complete from the multi-sector\r
+ // reads.\r
+ while (sdSpiByte(0xFF) == 0x00) {}\r
+ return sdDoCommand(cmd, param, 1, 0);\r
}\r
\r
// Clear the sticky status bits on error.\r
static void sdClearStatus()\r
{\r
- uint8 r2hi = sdCRCCommandAndResponse(SD_SEND_STATUS, 0);\r
- uint8 r2lo = sdSpiByte(0xFF);\r
- (void) r2hi; (void) r2lo;\r
+ sdSpiByte(0xFF);\r
+ uint16_t r2 = sdDoCommand(SD_SEND_STATUS, 0, 1, 1);\r
+ (void) r2;\r
}\r
\r
-\r
void\r
sdReadMultiSectorPrep()\r
{\r
\r
scsiDev.status = CHECK_CONDITION;\r
scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
+ scsiDev.target->sense.asc = LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE;\r
scsiDev.phase = STATUS;\r
}\r
else\r
dmaReadSector(uint8_t* outputBuffer)\r
{\r
// Wait for a start-block token.\r
- // Don't wait more than 200ms.\r
- // The standard recommends 100ms.\r
+ // Don't wait more than 200ms. The standard recommends 100ms.\r
uint32_t start = getTime_ms();\r
- uint8 token = sdSpiByte(0xFF);\r
+ uint8_t token = sdSpiByte(0xFF);\r
while (token != 0xFE && (diffTime_ms(start, getTime_ms()) <= 200))\r
{\r
+ if (token && ((token & 0xE0) == 0))\r
+ {\r
+ // Error token!\r
+ break;\r
+ }\r
token = sdSpiByte(0xFF);\r
}\r
if (token != 0xFE)\r
{\r
scsiDev.status = CHECK_CONDITION;\r
scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR;\r
+ scsiDev.target->sense.asc = 0x4400 | token;\r
scsiDev.phase = STATUS;\r
}\r
+ sdClearStatus();\r
return;\r
}\r
\r
CyDmaTdSetConfiguration(sdDMATxTd[0], SD_SECTOR_SIZE + 2, CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);\r
CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
\r
- dmaInProgress = 1;\r
- // The DMA controller is a bit trigger-happy. It will retain\r
- // a drq request that was triggered while the channel was\r
- // disabled.\r
- CyDmaClearPendingDrq(sdDMATxChan);\r
- CyDmaClearPendingDrq(sdDMARxChan);\r
-\r
+ sdIOState = SD_DMA;\r
txDMAComplete = 0;\r
rxDMAComplete = 0;\r
\r
CyDmaChSetInitialTd(sdDMARxChan, sdDMARxTd[0]);\r
CyDmaChSetInitialTd(sdDMATxChan, sdDMATxTd[0]);\r
\r
+ // The DMA controller is a bit trigger-happy. It will retain\r
+ // a drq request that was triggered while the channel was\r
+ // disabled.\r
+ CyDmaClearPendingDrq(sdDMATxChan);\r
+ CyDmaClearPendingDrq(sdDMARxChan);\r
+\r
// There is no flow control, so we must ensure we can read the bytes\r
// before we start transmitting\r
CyDmaChEnable(sdDMARxChan, 1);\r
if (rxDMAComplete && txDMAComplete)\r
{\r
// DMA transfer is complete\r
- dmaInProgress = 0;\r
+ sdIOState = SD_IDLE;\r
return 1;\r
}\r
else\r
\r
scsiDev.status = CHECK_CONDITION;\r
scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
+ scsiDev.target->sense.asc = LOGICAL_UNIT_DOES_NOT_RESPOND_TO_SELECTION;\r
scsiDev.phase = STATUS;\r
}\r
else\r
\r
void sdCompleteRead()\r
{\r
- if (dmaInProgress)\r
+ if (sdIOState != SD_IDLE)\r
{\r
// Not much choice but to wait until we've completed the transfer.\r
// Cancelling the transfer can't be done as we have no way to reset\r
// the SD card.\r
while (!sdReadSectorDMAPoll()) { /* spin */ }\r
}\r
-\r
transfer.inProgress = 0;\r
\r
// We cannot send even a single "padding" byte, as we normally would when\r
// an error condition as we're trying to read past-the-end of the storage\r
// device.\r
// ie. do not use sdCommandAndResponse here.\r
- uint8 r1b;\r
- sdSendCommand(SD_STOP_TRANSMISSION, 0);\r
- r1b = sdReadResp();\r
+ uint8 r1b = sdDoCommand(SD_STOP_TRANSMISSION, 0, 0, 0);\r
\r
if (r1b)\r
{\r
- // Try very hard to make sure the transmission stops\r
- int retries = 255;\r
- while (r1b && retries)\r
- {\r
- r1b = sdCommandAndResponse(SD_STOP_TRANSMISSION, 0);\r
- retries--;\r
- }\r
-\r
scsiDev.status = CHECK_CONDITION;\r
scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR;\r
+ scsiDev.target->sense.asc = UNRECOVERED_READ_ERROR | r1b;\r
scsiDev.phase = STATUS;\r
}\r
\r
- // R1b has an optional trailing "busy" signal.\r
- {\r
- uint8 busy;\r
- do\r
- {\r
- busy = sdSpiByte(0xFF);\r
- } while (busy == 0);\r
- }\r
+ // R1b has an optional trailing "busy" signal, but we defer waiting on this.\r
+ // The next call so sdCommandAndResponse will wait for the busy state to\r
+ // clear.\r
}\r
\r
static void sdWaitWriteBusy()\r
void\r
sdWriteMultiSectorDMA(uint8_t* outputBuffer)\r
{\r
- sdSpiByte(0xFC); // MULTIPLE byte start token\r
+ // Transmit 512 bytes of data and then 2 bytes CRC, and then get the response byte\r
+ // We need to do this without stopping the clock\r
+ CyDmaTdSetConfiguration(sdDMATxTd[0], 1, sdDMATxTd[1], TD_INC_SRC_ADR);\r
+ CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)&writeStartToken), LO16((uint32)SDCard_TXDATA_PTR));\r
\r
- // Transmit 512 bytes of data and then 2 bytes CRC.\r
- CyDmaTdSetConfiguration(sdDMATxTd[0], SD_SECTOR_SIZE, sdDMATxTd[1], TD_INC_SRC_ADR);\r
- CyDmaTdSetAddress(sdDMATxTd[0], LO16((uint32)outputBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
- CyDmaTdSetConfiguration(sdDMATxTd[1], 2, CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);\r
- CyDmaTdSetAddress(sdDMATxTd[1], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
+ CyDmaTdSetConfiguration(sdDMATxTd[1], SD_SECTOR_SIZE, sdDMATxTd[2], TD_INC_SRC_ADR);\r
+ CyDmaTdSetAddress(sdDMATxTd[1], LO16((uint32)outputBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
\r
- CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE + 2, CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN);\r
- CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));\r
+ CyDmaTdSetConfiguration(sdDMATxTd[2], 2 + sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_TX_DMA__TD_TERMOUT_EN);\r
+ CyDmaTdSetAddress(sdDMATxTd[2], LO16((uint32)&dummyBuffer), LO16((uint32)SDCard_TXDATA_PTR));\r
\r
+ CyDmaTdSetConfiguration(sdDMARxTd[0], SD_SECTOR_SIZE + 3, sdDMARxTd[1], 0);\r
+ CyDmaTdSetAddress(sdDMARxTd[0], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&discardBuffer));\r
+ CyDmaTdSetConfiguration(sdDMARxTd[1], sizeof(writeResponseBuffer), CY_DMA_DISABLE_TD, SD_RX_DMA__TD_TERMOUT_EN|TD_INC_DST_ADR);\r
+ CyDmaTdSetAddress(sdDMARxTd[1], LO16((uint32)SDCard_RXDATA_PTR), LO16((uint32)&writeResponseBuffer));\r
\r
- dmaInProgress = 1;\r
+ sdIOState = SD_DMA;\r
// The DMA controller is a bit trigger-happy. It will retain\r
// a drq request that was triggered while the channel was\r
// disabled.\r
}\r
\r
int\r
-sdWriteSectorDMAPoll()\r
+sdWriteSectorDMAPoll(int sendStopToken)\r
{\r
if (rxDMAComplete && txDMAComplete)\r
{\r
- uint8_t dataToken = sdSpiByte(0xFF); // Response\r
- if (dataToken == 0x0FF)\r
+ if (sdIOState == SD_DMA)\r
{\r
- return 0; // Write has not completed.\r
- }\r
- else if (((dataToken & 0x1F) >> 1) != 0x2) // Accepted.\r
- {\r
- uint8 r1b, busy;\r
- \r
- sdWaitWriteBusy();\r
-\r
- r1b = sdCommandAndResponse(SD_STOP_TRANSMISSION, 0);\r
- (void) r1b;\r
- sdSpiByte(0xFF);\r
-\r
- // R1b has an optional trailing "busy" signal.\r
+ // Retry a few times. The data token format is:\r
+ // XXX0AAA1\r
+ int i = 0;\r
+ uint8_t dataToken;\r
do\r
{\r
- busy = sdSpiByte(0xFF);\r
- } while (busy == 0);\r
+ dataToken = writeResponseBuffer[i]; // Response\r
+ ++i;\r
+ } while (((dataToken & 0x0101) != 1) && (i < sizeof(writeResponseBuffer)));\r
+\r
+ // At this point we should either have an accepted token, or we'll\r
+ // timeout and proceed into the error case below.\r
+ if (((dataToken & 0x1F) >> 1) != 0x2) // Accepted.\r
+ {\r
+ sdIOState = SD_IDLE;\r
\r
- // Wait for the card to come out of busy.\r
- sdWaitWriteBusy();\r
+ sdWaitWriteBusy();\r
+ sdSpiByte(0xFD); // STOP TOKEN\r
+ sdWaitWriteBusy();\r
\r
- transfer.inProgress = 0;\r
- scsiDiskReset();\r
- sdClearStatus();\r
+ transfer.inProgress = 0;\r
+ scsiDiskReset();\r
+ sdClearStatus();\r
\r
- scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
- scsiDev.phase = STATUS;\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.target->sense.code = HARDWARE_ERROR;\r
+ scsiDev.target->sense.asc = 0x6900 | dataToken;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+ else\r
+ {\r
+ sdIOState = SD_ACCEPTED;\r
+ }\r
}\r
- else\r
+\r
+ if (sdIOState == SD_ACCEPTED)\r
{\r
- sdWaitWriteBusy();\r
+ // Wait while the SD card is busy\r
+ if (sdSpiByte(0xFF) == 0xFF)\r
+ {\r
+ if (sendStopToken)\r
+ {\r
+ sdIOState = SD_BUSY;\r
+ transfer.inProgress = 0;\r
+\r
+ sdSpiByte(0xFD); // STOP TOKEN\r
+ }\r
+ else\r
+ {\r
+ sdIOState = SD_IDLE;\r
+ }\r
+ }\r
}\r
- // DMA transfer is complete and the SD card has accepted the write.\r
- dmaInProgress = 0;\r
\r
- return 1;\r
+ if (sdIOState == SD_BUSY)\r
+ {\r
+ // Wait while the SD card is busy\r
+ if (sdSpiByte(0xFF) == 0xFF)\r
+ {\r
+ sdIOState = SD_IDLE;\r
+ }\r
+ }\r
+\r
+ return sdIOState == SD_IDLE;\r
}\r
else\r
{\r
\r
void sdCompleteWrite()\r
{\r
- if (dmaInProgress)\r
+ if (sdIOState != SD_IDLE)\r
{\r
// Not much choice but to wait until we've completed the transfer.\r
// Cancelling the transfer can't be done as we have no way to reset\r
// the SD card.\r
- while (!sdWriteSectorDMAPoll()) { /* spin */ }\r
+ while (!sdWriteSectorDMAPoll(1)) { /* spin */ }\r
}\r
- \r
- transfer.inProgress = 0;\r
\r
- uint8 r1, r2;\r
-\r
- sdSpiByte(0xFD); // STOP TOKEN\r
- // Wait for the card to come out of busy.\r
- sdWaitWriteBusy();\r
+ transfer.inProgress = 0;\r
\r
- r1 = sdCommandAndResponse(13, 0); // send status\r
- r2 = sdSpiByte(0xFF);\r
- if (r1 || r2)\r
+ if (scsiDev.phase == DATA_OUT)\r
{\r
- sdClearStatus();\r
- scsiDev.status = CHECK_CONDITION;\r
- scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = WRITE_ERROR_AUTO_REALLOCATION_FAILED;\r
- scsiDev.phase = STATUS;\r
+ sdSpiByte(0xFF);\r
+ uint16_t r2 = sdDoCommand(SD_SEND_STATUS, 0, 0, 1);\r
+ if (r2)\r
+ {\r
+ sdClearStatus();\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.target->sense.code = HARDWARE_ERROR;\r
+ scsiDev.target->sense.asc = WRITE_ERROR_AUTO_REALLOCATION_FAILED;\r
+ scsiDev.phase = STATUS;\r
+ }\r
}\r
}\r
\r
uint32_t start = getTime_ms();\r
int complete;\r
uint8 status;\r
- \r
+\r
do\r
{\r
uint8 buf[4];\r
return (status == 0) && complete;\r
}\r
\r
+static void sdReadCID()\r
+{\r
+ uint8 startToken;\r
+ int maxWait, i;\r
+\r
+ uint8 status = sdCRCCommandAndResponse(SD_SEND_CID, 0);\r
+ if(status){return;}\r
+\r
+ maxWait = 1023;\r
+ do\r
+ {\r
+ startToken = sdSpiByte(0xFF);\r
+ } while(maxWait-- && (startToken != 0xFE));\r
+ if (startToken != 0xFE) { return; }\r
+\r
+ for (i = 0; i < 16; ++i)\r
+ {\r
+ sdDev.cid[i] = sdSpiByte(0xFF);\r
+ }\r
+ sdSpiByte(0xFF); // CRC\r
+ sdSpiByte(0xFF); // CRC\r
+}\r
+\r
static int sdReadCSD()\r
{\r
uint8 startToken;\r
int maxWait, i;\r
- uint8 buf[16];\r
\r
uint8 status = sdCRCCommandAndResponse(SD_SEND_CSD, 0);\r
if(status){goto bad;}\r
\r
for (i = 0; i < 16; ++i)\r
{\r
- buf[i] = sdSpiByte(0xFF);\r
+ sdDev.csd[i] = sdSpiByte(0xFF);\r
}\r
sdSpiByte(0xFF); // CRC\r
sdSpiByte(0xFF); // CRC\r
\r
- if ((buf[0] >> 6) == 0x00)\r
+ if ((sdDev.csd[0] >> 6) == 0x00)\r
{\r
// CSD version 1\r
// C_SIZE in bits [73:62]\r
- uint32 c_size = (((((uint32)buf[6]) & 0x3) << 16) | (((uint32)buf[7]) << 8) | buf[8]) >> 6;\r
- uint32 c_mult = (((((uint32)buf[9]) & 0x3) << 8) | ((uint32)buf[0xa])) >> 7;\r
- uint32 sectorSize = buf[5] & 0x0F;\r
+ uint32 c_size = (((((uint32)sdDev.csd[6]) & 0x3) << 16) | (((uint32)sdDev.csd[7]) << 8) | sdDev.csd[8]) >> 6;\r
+ uint32 c_mult = (((((uint32)sdDev.csd[9]) & 0x3) << 8) | ((uint32)sdDev.csd[0xa])) >> 7;\r
+ uint32 sectorSize = sdDev.csd[5] & 0x0F;\r
sdDev.capacity = ((c_size+1) * ((uint64)1 << (c_mult+2)) * ((uint64)1 << sectorSize)) / SD_SECTOR_SIZE;\r
}\r
- else if ((buf[0] >> 6) == 0x01)\r
+ else if ((sdDev.csd[0] >> 6) == 0x01)\r
{\r
// CSD version 2\r
// C_SIZE in bits [69:48]\r
\r
uint32 c_size =\r
- ((((uint32)buf[7]) & 0x3F) << 16) |\r
- (((uint32)buf[8]) << 8) |\r
- ((uint32)buf[7]);\r
+ ((((uint32)sdDev.csd[7]) & 0x3F) << 16) |\r
+ (((uint32)sdDev.csd[8]) << 8) |\r
+ ((uint32)sdDev.csd[7]);\r
sdDev.capacity = (c_size + 1) * 1024;\r
}\r
else\r
sdDMARxTd[1] = CyDmaTdAllocate();\r
sdDMATxTd[0] = CyDmaTdAllocate();\r
sdDMATxTd[1] = CyDmaTdAllocate();\r
+ sdDMATxTd[2] = CyDmaTdAllocate();\r
\r
SD_RX_DMA_COMPLETE_StartEx(sdRxISR);\r
SD_TX_DMA_COMPLETE_StartEx(sdTxISR);\r
sdDev.version = 0;\r
sdDev.ccs = 0;\r
sdDev.capacity = 0;\r
+ memset(sdDev.csd, 0, sizeof(sdDev.csd));\r
+ memset(sdDev.cid, 0, sizeof(sdDev.cid));\r
\r
sdInitDMA();\r
\r
SD_CS_Write(0); // Set CS active (active low)\r
CyDelayUs(1);\r
\r
- v = sdCRCCommandAndResponse(SD_GO_IDLE_STATE, 0);\r
+ sdSpiByte(0xFF);\r
+ v = sdDoCommand(SD_GO_IDLE_STATE, 0, 1, 0);\r
if(v != 1){goto bad;}\r
\r
ledOn();\r
SDCard_ClearFIFO();\r
\r
if (!sdReadCSD()) goto bad;\r
+ sdReadCID();\r
\r
result = 1;\r
goto out;\r
void sdWriteMultiSectorPrep()\r
{\r
uint8 v;\r
- \r
+\r
// Set the number of blocks to pre-erase by the multiple block write command\r
// We don't care about the response - if the command is not accepted, writes\r
// will just be a bit slower.\r
{\r
sdLBA = sdLBA * SD_SECTOR_SIZE;\r
}\r
- v = sdCommandAndResponse(25, sdLBA);\r
+ v = sdCommandAndResponse(SD_WRITE_MULTIPLE_BLOCK, sdLBA);\r
if (v)\r
{\r
scsiDiskReset();\r
sdClearStatus();\r
scsiDev.status = CHECK_CONDITION;\r
scsiDev.target->sense.code = HARDWARE_ERROR;\r
- scsiDev.target->sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
+ scsiDev.target->sense.asc = 0x8800 | v;\r
scsiDev.phase = STATUS;\r
}\r
else\r
{\r
// Check if there's an SD card present.\r
if ((scsiDev.phase == BUS_FREE) &&\r
- !dmaInProgress)\r
+ (sdIOState == SD_IDLE))\r
{\r
// The CS line is pulled high by the SD card.\r
// De-assert the line, and check if it's high.\r
SD_SEND_OP_COND = 1,
SD_SEND_IF_COND = 8, // SD V2
SD_SEND_CSD = 9,
+ SD_SEND_CID = 10,
SD_STOP_TRANSMISSION = 12,
SD_SEND_STATUS = 13,
SD_SET_BLOCKLEN = 16,
SD_READ_SINGLE_BLOCK = 17,
SD_READ_MULTIPLE_BLOCK = 18,
SD_APP_SET_WR_BLK_ERASE_COUNT = 23,
+ SD_WRITE_MULTIPLE_BLOCK = 25,
SD_APP_SEND_OP_COND = 41,
SD_APP_CMD = 55,
SD_READ_OCR = 58,
int version; // SDHC = version 2.
int ccs; // Card Capacity Status. 1 = SDHC or SDXC
uint32 capacity; // in 512 byte blocks
+
+ uint8_t csd[16]; // Unparsed CSD
+ uint8_t cid[16]; // Unparsed CID
} SdDevice;
extern SdDevice sdDev;
void sdWriteMultiSectorPrep(void);
void sdWriteMultiSectorDMA(uint8_t* outputBuffer);
-int sdWriteSectorDMAPoll();
+int sdWriteSectorDMAPoll(int sendStopToken);
void sdCompleteWrite(void);
void sdReadMultiSectorPrep(void);
/*******************************************************************************\r
* File Name: Bootloadable_1.c\r
-* Version 1.20\r
+* Version 1.30\r
*\r
* Description:\r
* Provides an API for the Bootloadable application. The API includes a\r
-* single function for starting bootloader.\r
+* single function for starting the bootloader.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
* Function Name: Bootloadable_1_Load\r
********************************************************************************\r
* Summary:\r
-* Begins the bootloading algorithm, downloading a new ACD image from the host.\r
+* Begins the bootloading algorithm downloading a new ACD image from the host.\r
*\r
* Parameters:\r
* None\r
\r
\r
/*******************************************************************************\r
-* Function Name: Bootloadable_1_SetFlashByte\r
-********************************************************************************\r
-* Summary:\r
-* Sets byte at specified address in Flash.\r
-*\r
-* Parameters:\r
-* None\r
-*\r
-* Returns:\r
-* None\r
-*\r
+* The following code is OBSOLETE and must not be used.\r
*******************************************************************************/\r
void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) \r
{\r
uint32 flsAddr = address - CYDEV_FLASH_BASE;\r
- uint8 rowData[CYDEV_FLS_ROW_SIZE];\r
+ uint8 rowData[CYDEV_FLS_ROW_SIZE];\r
\r
#if !(CY_PSOC4)\r
- uint8 arrayId = (uint8)(flsAddr / CYDEV_FLS_SECTOR_SIZE);\r
+ uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE);\r
#endif /* !(CY_PSOC4) */\r
\r
- uint16 rowNum = (uint16)((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);\r
+ #if (CY_PSOC4)\r
+ uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE);\r
+ #else\r
+ uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);\r
+ #endif /* (CY_PSOC4) */\r
+\r
uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE);\r
uint16 idx;\r
\r
}\r
rowData[address % CYDEV_FLS_ROW_SIZE] = runType;\r
\r
-\r
#if(CY_PSOC4)\r
- (void) CySysFlashWriteRow((uint32)rowNum, rowData);\r
+ (void) CySysFlashWriteRow((uint32) rowNum, rowData);\r
#else\r
(void) CyWriteRowData(arrayId, rowNum, rowData);\r
#endif /* (CY_PSOC4) */\r
+\r
+ #if(CY_PSOC5)\r
+ /***************************************************************************\r
+ * When writing Flash, data in the instruction cache can become stale.\r
+ * Therefore, the cache data does not correlate to the data just written to\r
+ * Flash. A call to CyFlushCache() is required to invalidate the data in the\r
+ * cache and force fresh information to be loaded from Flash.\r
+ ***************************************************************************/\r
+ CyFlushCache();\r
+ #endif /* (CY_PSOC5) */\r
}\r
\r
\r
/*******************************************************************************\r
* File Name: Bootloadable_1.h\r
-* Version 1.20\r
+* Version 1.30\r
*\r
* Description:\r
* Provides an API for the Bootloadable application. The API includes a\r
* single function for starting bootloader.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
/* Check to see if required defines such as CY_PSOC5LP are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5LP)\r
- #error Component Bootloadable_v1_20 requires cy_boot v3.0 or later\r
+ #error Component Bootloadable_v1_30 requires cy_boot v3.0 or later\r
#endif /* !defined (CY_PSOC5LP) */\r
\r
\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from version 1.10\r
+* The following code is OBSOLETE and must not be used starting from version 1.10\r
*******************************************************************************/\r
#define CYBTDLR_SET_RUN_TYPE(x) Bootloadable_1_SET_RUN_TYPE(x)\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from version 1.20\r
+* The following code is OBSOLETE and must not be used starting from version 1.20\r
*******************************************************************************/\r
#define Bootloadable_1_START_APP (0x80u)\r
#define Bootloadable_1_START_BTLDR (0x40u)\r
#define Bootloadable_1_SetFlashRunType(runType) \\r
Bootloadable_1_SetFlashByte(Bootloadable_1_MD_APP_RUN_ADDR(0), (runType))\r
\r
-void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) ;\r
\r
+/*******************************************************************************\r
+* The following code is OBSOLETE and must not be used.\r
+*\r
+* If the obsoleted macro definitions intended for use in the application use the\r
+* following scheme, redefine your own versions of these definitions:\r
+* #ifdef <OBSOLETED_DEFINE>\r
+* #undef <OBSOLETED_DEFINE>\r
+* #define <OBSOLETED_DEFINE> (<New Value>)\r
+* #endif\r
+*\r
+* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* used in the application and their modification might lead to unexpected\r
+* consequences.\r
+*******************************************************************************/\r
+void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) ;\r
#if(CY_PSOC4)\r
- #define Bootloadable_1_SOFTWARE_RESET CY_SET_REG32(CYREG_CM0_AIRCR, 0x05FA0004u)\r
+ #define Bootloadable_1_SOFTWARE_RESET CySoftwareReset()\r
#else\r
- #define Bootloadable_1_SOFTWARE_RESET CY_SET_REG8(CYREG_RESET_CR2, 0x01u)\r
+ #define Bootloadable_1_SOFTWARE_RESET CySoftwareReset()\r
#endif /* (CY_PSOC4) */\r
\r
#if(CY_PSOC4)\r
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (32768 / 2);\r
define symbol __ICFEDIT_region_RAM_end__ = 0x20000000 + (32768 / 2) - 1;\r
/*-Sizes-*/\r
-define symbol __ICFEDIT_size_cstack__ = 0x2000;\r
+define symbol __ICFEDIT_size_cstack__ = 0x1000;\r
define symbol __ICFEDIT_size_heap__ = 0x0400;\r
/**** End of ICF editor section. ###ICF###*/\r
\r
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
define block HSTACK {block HEAP, last block CSTACK};\r
\r
+if (CY_APPL_LOADABLE)\r
+{\r
define block LOADER { readonly section .cybootloader };\r
+}\r
define block APPL with fixed order {readonly section .romvectors, readonly};\r
\r
/* The address of Flash row next after Bootloader image */\r
do not initialize { readwrite section .ramvectors };\r
\r
/******** Placements *********/\r
+if (CY_APPL_LOADABLE)\r
+{\r
".cybootloader" : place at start of ROM_region {block LOADER};\r
+}\r
+\r
"APPL" : place at start of APPL_region {block APPL};\r
\r
"RAMVEC" : place at start of RAM_region { readwrite section .ramvectors };\r
section .cymeta };\r
\r
".cyloadermeta" : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };\r
+if (CY_APPL_LOADABLE)\r
+{\r
".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };\r
+}\r
".cyconfigecc" : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc };\r
".cycustnvl" : place at address mem : 0x90000000 { readonly section .cycustnvl };\r
".cywolatch" : place at address mem : 0x90100000 { readonly section .cywolatch };\r
\r
;********************************************************************************\r
;* File Name: Cm3RealView.scat\r
-;* Version 4.0\r
+;* Version 4.20\r
;*\r
;* Description:\r
;* This Linker Descriptor file describes the memory layout of the PSoC5\r
;*\r
;* Note:\r
;*\r
-;* romvectors: Cypress default Interrupt sevice routine vector table.\r
+;* romvectors: Cypress default Interrupt service routine vector table.\r
;*\r
;* This is the ISR vector table at bootup. Used only for the reset vector.\r
;*\r
;*\r
;*\r
;********************************************************************************\r
-;* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+;* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
;* You may use this file only in accordance with the license, terms, conditions,\r
;* disclaimers, and limitations in the end user license agreement accompanying\r
;* the software package with which this file was provided.\r
.ANY (+RW, +ZI)\r
}\r
\r
- ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0400 - 0x2000) EMPTY 0x0400\r
+ ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0400 - 0x1000) EMPTY 0x0400\r
{\r
}\r
\r
- ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x2000\r
+ ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x1000\r
{\r
}\r
}\r
/*******************************************************************************\r
* File Name: Cm3Start.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Startup code for the ARM CM3.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
extern void __iar_data_init3 (void);\r
#endif /* (__ARMCC_VERSION) */\r
\r
+#if defined(__GNUC__)\r
+ #include <errno.h>\r
+ extern int errno;\r
+ extern int end;\r
+#endif /* defined(__GNUC__) */\r
+\r
/* Global variables */\r
#if !defined (__ICCARM__)\r
CY_NOINIT static uint32 cySysNoInitDataValid;\r
********************************************************************************\r
*\r
* Summary:\r
-* This function is called for all interrupts, other than reset, that get\r
+* This function is called for all interrupts, other than a reset that gets\r
* called before the system is setup.\r
*\r
* Parameters:\r
while(1)\r
{\r
/***********************************************************************\r
- * We should never get here. If we do, a serious problem occured, so go\r
+ * We must not get here. If we do, a serious problem occurs, so go\r
* into an infinite loop.\r
***********************************************************************/\r
}\r
\r
#if defined(__ARMCC_VERSION)\r
\r
-/* Local function for the device reset. */\r
+/* Local function for device reset. */\r
extern void Reset(void);\r
\r
/* Application entry point. */\r
********************************************************************************\r
*\r
* Summary:\r
-* This function is called imediatly before the users main\r
+* This function is called immediately before the users main\r
*\r
* Parameters:\r
* None\r
\r
while (1)\r
{\r
- /* If main returns it is undefined what we should do. */\r
+ /* If main returns, it is undefined what we should do. */\r
}\r
}\r
\r
/* Application entry point. */\r
extern int main(void);\r
\r
-/* The static objects constructors initializer */\r
+/* Static objects constructors initializer */\r
extern void __libc_init_array(void);\r
\r
typedef unsigned char __cy_byte_align8 __attribute ((aligned (8)));\r
#define __cy_region_num ((size_t)&__cy_region_num)\r
\r
\r
+/*******************************************************************************\r
+* System Calls of the Red Hat newlib C Library\r
+*******************************************************************************/\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: _exit\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Exit a program without cleaning up files. If your system doesn't provide\r
+* this, it is best to avoid linking with subroutines that require it (exit,\r
+* system).\r
+*\r
+* Parameters:\r
+* status: Status caused program exit.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+__attribute__((weak))\r
+void _exit(int status)\r
+{\r
+ /* Cause divide by 0 exception */\r
+ int x = status / (int) INT_MAX;\r
+ x = 4 / x;\r
+\r
+ while(1)\r
+ {\r
+\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: _sbrk\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Increase program data space. As malloc and related functions depend on this,\r
+* it is useful to have a working implementation. The following suffices for a\r
+* standalone system; it exploits the symbol end automatically defined by the\r
+* GNU linker.\r
+*\r
+* Parameters:\r
+* nbytes: The number of bytes requested (if the parameter value is positive)\r
+* from the heap or returned back to the heap (if the parameter value is\r
+* negative).\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+__attribute__((weak))\r
+void * _sbrk (int nbytes)\r
+{\r
+ extern int end; /* Symbol defined by linker map. Start of free memory (as symbol). */\r
+ void * returnValue;\r
+\r
+ /* The statically held previous end of the heap, with its initialization. */\r
+ static void *heapPointer = (void *) &end; /* Previous end */\r
+\r
+ if (((heapPointer + nbytes) - (void *) &end) <= CYDEV_HEAP_SIZE)\r
+ {\r
+ returnValue = heapPointer;\r
+ heapPointer += nbytes;\r
+ }\r
+ else\r
+ {\r
+ errno = ENOMEM;\r
+ returnValue = (void *) -1;\r
+ }\r
+\r
+ return (returnValue);\r
+}\r
+\r
+\r
/*******************************************************************************\r
* Function Name: Reset\r
********************************************************************************\r
Start_c();\r
}\r
\r
-__attribute__((weak))\r
-void _exit(int status)\r
-{\r
- /* Cause a divide by 0 exception */\r
- int x = status / INT_MAX;\r
- x = 4 / x;\r
-\r
- while(1)\r
- {\r
- }\r
-}\r
\r
/*******************************************************************************\r
* Function Name: Start_c\r
*\r
* Summary:\r
* This function handles initializing the .data and .bss sections in\r
-* preperation for running standard C code. Once initialization is complete\r
+* preparation for running the standard C code. Once initialization is complete\r
* it will call main(). This function will never return.\r
*\r
* Parameters:\r
const struct __cy_region *rptr = __cy_regions;\r
\r
/* Initialize memory */\r
- for (regions = __cy_region_num, rptr = __cy_regions; regions--; rptr++)\r
+ for (regions = __cy_region_num; regions != 0u; regions--)\r
{\r
uint32 *src = (uint32 *)rptr->init;\r
uint32 *dst = (uint32 *)rptr->data;\r
\r
for (count = 0u; count != limit; count += sizeof (uint32))\r
{\r
- *dst++ = *src++;\r
+ *dst = *src;\r
+ dst++;\r
+ src++;\r
}\r
limit = rptr->zero_size;\r
for (count = 0u; count != limit; count += sizeof (uint32))\r
{\r
- *dst++ = 0u;\r
+ *dst = 0u;\r
+ dst++;\r
}\r
+\r
+ rptr++;\r
}\r
\r
/* Invoke static objects constructors */\r
********************************************************************************\r
*\r
* Summary:\r
-* This function perform early initializations for the IAR Embedded\r
-* Workbench IDE. It is executed in the context of reset interrupt handler\r
+* This function performs early initializations for the IAR Embedded\r
+* Workbench IDE. It is executed in the context of a reset interrupt handler\r
* before the data sections are initialized.\r
*\r
* Parameters:\r
const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] =\r
#endif /* defined (__ICCARM__) */\r
{\r
- INITIAL_STACK_POINTER, /* The initial stack pointer 0 */\r
- #if defined (__ICCARM__) /* The reset handler 1 */\r
+ INITIAL_STACK_POINTER, /* Initial stack pointer 0 */\r
+ #if defined (__ICCARM__) /* Reset handler 1 */\r
__iar_program_start,\r
#else\r
(cyisraddress)&Reset,\r
#endif /* defined (__ICCARM__) */\r
- &IntDefaultHandler, /* The NMI handler 2 */\r
- &IntDefaultHandler, /* The hard fault handler 3 */\r
+ &IntDefaultHandler, /* NMI handler 2 */\r
+ &IntDefaultHandler, /* Hard fault handler 3 */\r
};\r
\r
#if defined(__ARMCC_VERSION)\r
/* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */\r
CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1);\r
\r
- /* Point NVIC at the RAM vector table. */\r
+ /* Point NVIC at RAM vector table. */\r
*CYINT_VECT_TABLE = CyRamVectors;\r
\r
/* Initialize the configuration registers. */\r
\r
#if(0u != DMA_CHANNELS_USED__MASK0)\r
\r
- /* Setup DMA - only necessary if the design contains a DMA component. */\r
+ /* Setup DMA - only necessary if design contains DMA component. */\r
CyDmacConfigure();\r
\r
#endif /* (0u != DMA_CHANNELS_USED__MASK0) */\r
/*******************************************************************************\r
* File Name: CyBootAsmGnu.s\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Assembly routines for GNU as.\r
*\r
********************************************************************************\r
-* Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2010-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
;-------------------------------------------------------------------------------\r
; FILENAME: CyBootAsmIar.s\r
-; Version 4.0\r
+; Version 4.20\r
;\r
; DESCRIPTION:\r
; Assembly routines for IAR Embedded Workbench IDE.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions,\r
; disclaimers, and limitations in the end user license agreement accompanying\r
; the software package with which this file was provided.\r
;\r
; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit\r
; with interrupts still enabled. The test and set of the interrupt bits is not\r
-; atomic. Therefore, to avoid corrupting processor state, it must be the policy \r
+; atomic. Therefore, to avoid a corrupting processor state, it must be the policy \r
; that all interrupt routines restore the interrupt enable bits as they were \r
; found on entry.\r
;\r
;-------------------------------------------------------------------------------\r
; FILENAME: CyBootAsmRv.s\r
-; Version 4.0\r
+; Version 4.20\r
;\r
; DESCRIPTION:\r
; Assembly routines for RealView.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright 2010-2014, Cypress Semiconductor Corporation. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions,\r
; disclaimers, and limitations in the end user license agreement accompanying\r
; the software package with which this file was provided.\r
;\r
; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit\r
; with interrupts still enabled. The test and set of the interrupt bits is not\r
-; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid\r
+; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a\r
; corrupting processor state, it must be the policy that all interrupt routines\r
; restore the interrupt enable bits as they were found on entry.\r
;\r
/*******************************************************************************\r
* File Name: CyDmac.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides an API for the DMAC component. The API includes functions for the\r
* not being used.\r
*\r
* This code uses the first byte of each TD to manage the free list of TD's.\r
-* The user can over write this once the TD is allocated.\r
+* The user can overwrite this once the TD is allocated.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
* are initialized. To avoid zeroing, these variables should be initialized\r
* properly during segments initialization as well.\r
*******************************************************************************/\r
-static uint8 CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; /* Current Number of free elements in the list */\r
-static uint8 CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of the first available TD */\r
+static uint8 CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; /* Current Number of free elements on list */\r
+static uint8 CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of first available TD */\r
static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0; /* Bit map of DMA channel ownership */\r
\r
\r
*\r
* Summary:\r
* Creates a linked list of all the TDs to be allocated. This function is called\r
-* by the startup code; you do not normally need to call it. You could call this\r
+* by the startup code; you do not normally need to call it. You can call this\r
* function if all of the DMA channels are inactive.\r
*\r
* Parameters:\r
CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u);\r
}\r
\r
- /* Make the last one point to zero. */\r
+ /* Make last one point to zero. */\r
CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = 0u;\r
}\r
\r
* are determined by the BUS_TIMEOUT field in the PHUBCFG register.\r
*\r
* Theory:\r
-* Once an error occurs the error bits are sticky and are only cleared by a\r
-* write 1 to the error register.\r
+* Once an error occurs the error bits are sticky and are only cleared by \r
+* writing 1 to the error register.\r
*\r
*******************************************************************************/\r
uint8 CyDmacError(void) \r
* Set to 1 when an access is attempted to an invalid address.\r
*\r
* DMAC_BUS_TIMEOUT:\r
-* Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values\r
+* Set to 1 when a bus timeout occurs. Cleared by writing 1. Timeout values\r
* are determined by the BUS_TIMEOUT field in the PHUBCFG register.\r
*\r
* Return:\r
* None\r
*\r
* Theory:\r
-* Once an error occurs the error bits are sticky and are only cleared by a\r
-* write 1 to the error register.\r
+* Once an error occurs the error bits are sticky and are only cleared by \r
+* writing 1 to the error register.\r
*\r
*******************************************************************************/\r
void CyDmacClearError(uint8 error) \r
********************************************************************************\r
*\r
* Summary:\r
-* When an DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC and DMAC_PERIPH_ERR occurs the\r
+* When DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC, and DMAC_PERIPH_ERR occur the\r
* address of the error is written to the error address register and can be read\r
* with this function.\r
*\r
/* Enter critical section! */\r
interruptState = CyEnterCriticalSection();\r
\r
- /* Look for a free channel. */\r
+ /* Look for free channel. */\r
for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++)\r
{\r
if(0uL == (CyDmaChannels & channel))\r
{\r
- /* Mark the channel as used. */\r
+ /* Mark channel as used. */\r
CyDmaChannels |= channel;\r
break;\r
}\r
/* Enter critical section */\r
interruptState = CyEnterCriticalSection();\r
\r
- /* Clear the bit mask that keeps track of ownership. */\r
+ /* Clear bit mask that keeps track of ownership. */\r
CyDmaChannels &= ~(((uint32) 1u) << chHandle);\r
\r
/* Exit critical section */\r
* Preserves the original TD state when the TD has completed. This parameter\r
* applies to all TDs in the channel.\r
*\r
-* 0 - When a TD is completed, the DMAC leaves the TD configuration values in\r
+* 0 - When TD is completed, the DMAC leaves the TD configuration values in\r
* their current state, and does not restore them to their original state.\r
*\r
-* 1 - When a TD is completed, the DMAC restores the original configuration\r
+* 1 - When TD is completed, the DMAC restores the original configuration\r
* values of the TD.\r
*\r
* When preserveTds is set, the TD slot that equals the channel number becomes\r
{\r
if (0u != preserveTds)\r
{\r
- /* Store the intermediate TD states separately in CHn_SEP_TD0/1 to\r
- * preserve the original TD chain\r
+ /* Store intermediate TD states separately in CHn_SEP_TD0/1 to\r
+ * preserve original TD chain\r
*/\r
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP;\r
}\r
else\r
{\r
- /* Store the intermediate and final TD states on top of the original TD chain */\r
+ /* Store intermediate and final TD states on top of original TD chain */\r
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP);\r
}\r
\r
/* Disable channel */\r
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN));\r
\r
- /* Store the intermediate and final TD states on top of the original TD chain */\r
+ /* Store intermediate and final TD states on top of original TD chain */\r
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP));\r
status = CYRET_SUCCESS;\r
}\r
********************************************************************************\r
*\r
* Summary:\r
-* Clears pending DMA data request.\r
+* Clears pending the DMA data request.\r
*\r
* Parameters:\r
* uint8 chHandle:\r
* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().\r
*\r
* uint8 startTd:\r
-* The index of TD to set as the first TD associated with the channel. Zero is\r
+* Set the TD index as the first TD associated with the channel. Zero is\r
* a valid TD index.\r
*\r
* Return:\r
\r
if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS)\r
{\r
- /* Get pointer to the Next available. */\r
+ /* Get pointer to Next available. */\r
element = CyDmaTdFreeIndex;\r
\r
/* Decrement the count. */\r
CyDmaTdCurrentNumber--;\r
\r
- /* Update the next available pointer. */\r
+ /* Update next available pointer. */\r
CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0];\r
}\r
\r
/* Enter critical section! */\r
uint8 interruptState = CyEnterCriticalSection();\r
\r
- /* Get pointer to the Next available. */\r
+ /* Get pointer to Next available. */\r
CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex;\r
\r
/* Set new Next Available. */\r
* CYRET_BAD_PARAM if tdHandle is invalid.\r
*\r
* Side Effects:\r
-* If a TD has a transfer count of N and is executed, the transfer count becomes\r
+* If TD has a transfer count of N and is executed, the transfer count becomes\r
* 0. If it is reexecuted, the Transfer count of zero will be interpreted as a\r
-* request for indefinite transfer. Be careful when requesting a TD with a\r
+* request for indefinite transfer. Be careful when requesting TD with a\r
* transfer count of zero.\r
*\r
*******************************************************************************/\r
\r
if(tdHandle < CY_DMA_NUMBEROF_TDS)\r
{\r
- /* If we have a pointer */\r
+ /* If we have pointer */\r
if(NULL != transferCount)\r
{\r
- /* Get the 12 bits of the transfer count */\r
+ /* Get 12 bits of transfer count */\r
reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0];\r
*transferCount = 0x0FFFu & CY_GET_REG16(convert);\r
}\r
\r
- /* If we have a pointer */\r
+ /* If we have pointer */\r
if(NULL != nextTd)\r
{\r
- /* Get the Next TD pointer */\r
+ /* Get Next TD pointer */\r
*nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u];\r
}\r
\r
- /* If we have a pointer */\r
+ /* If we have pointer */\r
if(NULL != configuration)\r
{\r
- /* Get the configuration the TD */\r
+ /* Get configuration TD */\r
*configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u];\r
}\r
\r
/*******************************************************************************\r
* File Name: CyDmac.h\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides the function definitions for the DMA Controller.\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
#define CY_DMA_TD_SIZE 0x08u\r
\r
-/* The "u" was removed as workaround for Keil compiler bug */\r
+/* "u" was removed as workaround for Keil compiler bug */\r
#define CY_DMA_TD_SWAP_EN 0x80\r
#define CY_DMA_TD_SWAP_SIZE4 0x40\r
#define CY_DMA_TD_AUTO_EXEC_NEXT 0x20\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0\r
+* The following code is OBSOLETE and must not be used.\r
+*\r
+* If the obsoleted macro definitions intended for use in the application use the\r
+* following scheme, redefine your own versions of these definitions:\r
+* #ifdef <OBSOLETED_DEFINE>\r
+* #undef <OBSOLETED_DEFINE>\r
+* #define <OBSOLETED_DEFINE> (<New Value>)\r
+* #endif\r
+*\r
+* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* used in the application and their modification might lead to unexpected\r
+* consequences.\r
*******************************************************************************/\r
#define DMA_INVALID_CHANNEL (CY_DMA_INVALID_CHANNEL)\r
#define DMA_INVALID_TD (CY_DMA_INVALID_TD)\r
/*******************************************************************************\r
* File Name: CyFlash.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides an API for the FLASH/EEPROM.\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
#include "CyFlash.h"\r
\r
+/* The number of EEPROM arrays */\r
+#define CY_FLASH_EEPROM_NUMBER_ARRAYS (1u)\r
+\r
\r
/*******************************************************************************\r
-* Holds die temperature, updated by CySetTemp(). Used for flash writting.\r
+* Holds the die temperature, updated by CySetTemp(). Used for flash writing.\r
* The first byte is the sign of the temperature (0 = negative, 1 = positive).\r
* The second byte is the magnitude.\r
*******************************************************************************/\r
\r
\r
static cystatus CySetTempInt(void);\r
+static cystatus CyFlashGetSpcAlgorithm(void);\r
\r
\r
/*******************************************************************************\r
*******************************************************************************/\r
void CyFlash_Start(void) \r
{\r
- /* Active Power Mode */\r
- *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;\r
+ uint8 interruptState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+\r
+ /***************************************************************************\r
+ * Enable SPC clock. This also internally enables the 36MHz IMO, since this\r
+ * is required for the SPC to function.\r
+ ***************************************************************************/\r
+ CY_FLASH_PM_ACT_CFG0_REG |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;\r
+ CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;\r
+\r
\r
- /* Standby Power Mode */\r
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;\r
+ /***************************************************************************\r
+ * The wake count defines the number of Bus Clock cycles it takes for the\r
+ * flash or eeprom to wake up from a low power mode independent of the chip\r
+ * power mode. Wake up time for these blocks is 5 us.\r
+ * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E\r
+ * (30d) defines the wake up time as 60 cycles of the Bus Clock.\r
+ * This register needs to be written with a value dependent on the Bus Clock\r
+ * frequency so that the duration of the cycles is equal to or greater than\r
+ * the 5 us delay required.\r
+ ***************************************************************************/\r
+ CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;\r
+\r
+\r
+ /***************************************************************************\r
+ * Enable flash. Active flash macros consume current, but re-enabling a\r
+ * disabled flash macro takes 5us. If the CPU attempts to fetch out of the\r
+ * macro during that time, it will be stalled. This bit allows the flash to\r
+ * be enabled even if the CPU is disabled, which allows a quicker return to\r
+ * code execution.\r
+ ***************************************************************************/\r
+ CY_FLASH_PM_ACT_CFG12_REG |= CY_FLASH_PM_ACT_CFG12_EN_FM;\r
+ CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_FM;\r
+\r
+ while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))\r
+ {\r
+ /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */\r
+ }\r
\r
- CyDelayUs(CY_FLASH_EE_STARTUP_DELAY);\r
+ CyExitCriticalSection(interruptState);\r
}\r
\r
\r
*******************************************************************************/\r
void CyFlash_Stop(void) \r
{\r
- /* Active Power Mode */\r
- *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));\r
+ uint8 interruptState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ CY_FLASH_PM_ACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_FM));\r
+ CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_FM));\r
\r
- /* Standby Power Mode */\r
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));\r
+ CyExitCriticalSection(interruptState);\r
}\r
\r
\r
*\r
* Summary:\r
* Sends a command to the SPC to read the die temperature. Sets a global value\r
-* used by the Write functions. This function must be called once before\r
+* used by the Write function. This function must be called once before\r
* executing a series of Flash writing functions.\r
*\r
* Parameters:\r
}\r
\r
\r
+/*******************************************************************************\r
+* Function Name: CyFlashGetSpcAlgorithm\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sends a command to the SPC to download code into RAM.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* status:\r
+* CYRET_SUCCESS - if successful\r
+* CYRET_LOCKED - if Flash writing already in use\r
+* CYRET_UNKNOWN - if there was an SPC error\r
+*\r
+*******************************************************************************/\r
+static cystatus CyFlashGetSpcAlgorithm(void) \r
+{\r
+ cystatus status;\r
+\r
+ /* Make sure SPC is powered */\r
+ CySpcStart();\r
+\r
+ if(CySpcLock() == CYRET_SUCCESS)\r
+ {\r
+ status = CySpcGetAlgorithm();\r
+\r
+ if(CYRET_STARTED == status)\r
+ {\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Spin until idle. */\r
+ CyDelayUs(1u);\r
+ }\r
+\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ }\r
+ }\r
+ CySpcUnlock();\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+\r
+ return (status);\r
+}\r
+\r
+\r
/*******************************************************************************\r
* Function Name: CySetTemp\r
********************************************************************************\r
*\r
* Summary:\r
-* This is a wraparound for CySetTempInt(). It is used to return second\r
-* successful read of temperature value.\r
+* This is a wraparound for CySetTempInt(). It is used to return the second\r
+* successful read of the temperature value.\r
*\r
* Parameters:\r
* None\r
* CYRET_UNKNOWN if there was an SPC error.\r
*\r
* uint8 dieTemperature[2]:\r
-* Holds die temperature for the flash writting algorithm. The first byte is\r
+* Holds the die temperature for the flash writing algorithm. The first byte is\r
* the sign of the temperature (0 = negative, 1 = positive). The second byte is\r
* the magnitude.\r
*\r
*******************************************************************************/\r
cystatus CySetTemp(void) \r
{\r
- cystatus status = CySetTempInt();\r
+ cystatus status = CyFlashGetSpcAlgorithm();\r
\r
if(status == CYRET_SUCCESS)\r
{\r
*\r
* Summary:\r
* Sets the user supplied temporary buffer to store SPC data while performing\r
-* flash and EEPROM commands. This buffer is only necessary when Flash ECC is\r
+* Flash and EEPROM commands. This buffer is only necessary when the Flash ECC is\r
* disabled.\r
*\r
* Parameters:\r
* buffer:\r
-* Address of block of memory to store temporary memory. The size of the block\r
+* The address of a block of memory to store temporary memory. The size of the block\r
* of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE.\r
*\r
* Return:\r
\r
if(NULL == buffer)\r
{\r
+ rowBuffer = rowBuffer;\r
status = CYRET_BAD_PARAM;\r
}\r
else if(CySpcLock() != CYRET_SUCCESS)\r
{\r
+ rowBuffer = rowBuffer;\r
status = CYRET_LOCKED;\r
}\r
else\r
\r
#else\r
\r
- /* To supress the warning */\r
+ /* To suppress warning */\r
buffer = buffer;\r
\r
#endif /* (CYDEV_ECC_ENABLE == 0u) */\r
}\r
\r
\r
-#if(CYDEV_ECC_ENABLE == 1)\r
-\r
- /*******************************************************************************\r
- * Function Name: CyWriteRowData\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Sends a command to the SPC to load and program a row of data in\r
- * Flash or EEPROM.\r
- *\r
- * Parameters:\r
- * arrayID: ID of the array to write.\r
- * The type of write, Flash or EEPROM, is determined from the array ID.\r
- * The arrays in the part are sequential starting at the first ID for the\r
- * specific memory type. The array ID for the Flash memory lasts from 0x00 to\r
- * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.\r
- * rowAddress: rowAddress of flash row to program.\r
- * rowData: Array of bytes to write.\r
- *\r
- * Return:\r
- * status:\r
- * CYRET_SUCCESS if successful.\r
- * CYRET_LOCKED if the SPC is already in use.\r
- * CYRET_CANCELED if command not accepted\r
- * CYRET_UNKNOWN if there was an SPC error.\r
- *\r
- *******************************************************************************/\r
- cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) \r
- {\r
- uint16 rowSize;\r
- cystatus status;\r
-\r
- rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;\r
- status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);\r
-\r
- return(status);\r
- }\r
-\r
-#else\r
-\r
- /*******************************************************************************\r
- * Function Name: CyWriteRowData\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Sends a command to the SPC to load and program a row of data in\r
- * Flash or EEPROM.\r
- *\r
- * Parameters:\r
- * arrayID : ID of the array to write.\r
- * The type of write, Flash or EEPROM, is determined from the array ID.\r
- * The arrays in the part are sequential starting at the first ID for the\r
- * specific memory type. The array ID for the Flash memory lasts from 0x00 to\r
- * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.\r
- * rowAddress : rowAddress of flash row to program.\r
- * rowData : Array of bytes to write.\r
- *\r
- * Return:\r
- * status:\r
- * CYRET_SUCCESS if successful.\r
- * CYRET_LOCKED if the SPC is already in use.\r
- * CYRET_CANCELED if command not accepted\r
- * CYRET_UNKNOWN if there was an SPC error.\r
- *\r
- *******************************************************************************/\r
- cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) \r
- {\r
- uint8 i;\r
- uint32 offset;\r
- uint16 rowSize;\r
- cystatus status;\r
-\r
- /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */\r
- if(NULL != rowBuffer)\r
- {\r
- if(arrayId > CY_SPC_LAST_FLASH_ARRAYID)\r
- {\r
- rowSize = CYDEV_EEPROM_ROW_SIZE;\r
- }\r
- else\r
- {\r
- rowSize = CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE;\r
-\r
- /* Save the ECC area. */\r
- offset = CYDEV_ECC_BASE +\r
- ((uint32)arrayId * CYDEV_ECC_SECTOR_SIZE) +\r
- ((uint32)rowAddress * CYDEV_ECC_ROW_SIZE);\r
-\r
- for(i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)\r
- {\r
- *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i));\r
- }\r
- }\r
-\r
- /* Copy the rowdata to the temporary buffer. */\r
- #if(CY_PSOC3)\r
- (void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE);\r
- #else\r
- (void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE);\r
- #endif /* (CY_PSOC3) */\r
-\r
- status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize);\r
- }\r
- else\r
- {\r
- status = CYRET_UNKNOWN;\r
- }\r
+/*******************************************************************************\r
+* Function Name: CyWriteRowData\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sends a command to the SPC to load and program a row of data in\r
+* Flash or EEPROM.\r
+*\r
+* Parameters:\r
+* arrayID: ID of the array to write.\r
+* The type of write, Flash or EEPROM, is determined from the array ID.\r
+* The arrays in the part are sequential starting at the first ID for the\r
+* specific memory type. The array ID for the Flash memory lasts from 0x00 to\r
+* 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.\r
+* rowAddress: rowAddress of flash row to program.\r
+* rowData: Array of bytes to write.\r
+*\r
+* Return:\r
+* status:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_LOCKED if the SPC is already in use.\r
+* CYRET_CANCELED if command not accepted\r
+* CYRET_UNKNOWN if there was an SPC error.\r
+*\r
+*******************************************************************************/\r
+cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) \r
+{\r
+ uint16 rowSize;\r
+ cystatus status;\r
\r
- return(status);\r
- }\r
+ rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;\r
+ status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);\r
\r
-#endif /* (CYDEV_ECC_ENABLE == 0u) */\r
+ return(status);\r
+}\r
\r
\r
+/*******************************************************************\r
+* If "Enable Error Correcting Code (ECC)" and "Store Configuration\r
+* Data in ECC" DWR options are disabled, ECC section is available\r
+* for user data.\r
+*******************************************************************/\r
#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))\r
\r
/*******************************************************************************\r
********************************************************************************\r
*\r
* Summary:\r
- * Sends a command to the SPC to load and program a row of config data in flash.\r
+ * Sends a command to the SPC to load and program a row of config data in the Flash.\r
* This function is only valid for Flash array IDs (not for EEPROM).\r
*\r
* Parameters:\r
* The arrays in the part are sequential starting at the first ID for the\r
* specific memory type. The array ID for the Flash memory lasts\r
* from 0x00 to 0x3F.\r
- * rowAddress: Address of the sector to erase.\r
- * rowECC: Array of bytes to write.\r
+ * rowAddress: The address of the sector to erase.\r
+ * rowECC: The array of bytes to write.\r
*\r
* Return:\r
* status:\r
cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\\r
\r
{\r
- uint32 offset;\r
- uint16 i;\r
cystatus status;\r
\r
- /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */\r
- if(NULL != rowBuffer)\r
- {\r
- /* Read the existing flash data. */\r
- offset = ((uint32)arrayId * CYDEV_FLS_SECTOR_SIZE) +\r
- ((uint32)rowAddress * CYDEV_FLS_ROW_SIZE);\r
-\r
- #if (CYDEV_FLS_BASE != 0u)\r
- offset += CYDEV_FLS_BASE;\r
- #endif /* (CYDEV_FLS_BASE != 0u) */\r
-\r
- for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)\r
- {\r
- rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i));\r
- }\r
-\r
- #if(CY_PSOC3)\r
- (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],\r
- (void *)(uint32)rowECC,\r
- (int16)CYDEV_ECC_ROW_SIZE);\r
- #else\r
- (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],\r
- (const void *)rowECC,\r
- CYDEV_ECC_ROW_SIZE);\r
- #endif /* (CY_PSOC3) */\r
-\r
- status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);\r
- }\r
- else\r
- {\r
- status = CYRET_UNKNOWN;\r
- }\r
+ status = CyWriteRowFull(arrayId, rowAddress, rowECC, CYDEV_ECC_ROW_SIZE);\r
\r
return (status);\r
}\r
* Function Name: CyWriteRowFull\r
********************************************************************************\r
* Summary:\r
-* Sends a command to the SPC to load and program a row of data in flash.\r
+* Sends a command to the SPC to load and program a row of data in the Flash.\r
* rowData array is expected to contain Flash and ECC data if needed.\r
*\r
* Parameters:\r
cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \\r
\r
{\r
- cystatus status;\r
+ cystatus status = CYRET_SUCCESS;\r
\r
- if(CySpcLock() == CYRET_SUCCESS)\r
+ if((arrayId <= CY_SPC_LAST_FLASH_ARRAYID) && (arrayId > (CY_FLASH_NUMBER_ARRAYS + CY_SPC_FIRST_FLASH_ARRAYID)))\r
{\r
- /* Load row data into SPC internal latch */\r
- status = CySpcLoadRow(arrayId, rowData, rowSize);\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
\r
- if(CYRET_STARTED == status)\r
+ if(arrayId > CY_SPC_LAST_EE_ARRAYID)\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+\r
+ if((arrayId >= CY_SPC_FIRST_EE_ARRAYID) && (arrayId > (CY_FLASH_EEPROM_NUMBER_ARRAYS + CY_SPC_FIRST_EE_ARRAYID)))\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+\r
+ if(arrayId <= CY_SPC_LAST_FLASH_ARRAYID)\r
+ {\r
+ /* Flash */\r
+ if(rowNumber > (CY_FLASH_NUMBER_ROWS/CY_FLASH_NUMBER_ARRAYS))\r
{\r
- while(CY_SPC_BUSY)\r
- {\r
- /* Wait for SPC to finish and get SPC status */\r
- CyDelayUs(1u);\r
- }\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* EEPROM */\r
+ if(rowNumber > (CY_EEPROM_NUMBER_ROWS/CY_FLASH_EEPROM_NUMBER_ARRAYS))\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
\r
- /* Hide SPC status */\r
- if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
- {\r
- status = CYRET_SUCCESS;\r
- }\r
- else\r
- {\r
- status = CYRET_UNKNOWN;\r
- }\r
+ if(CY_EEPROM_SIZEOF_ROW != rowSize)\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+ }\r
\r
- if(CYRET_SUCCESS == status)\r
+ if(rowData == NULL)\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+\r
+\r
+ if(status == CYRET_SUCCESS)\r
+ {\r
+ if(CySpcLock() == CYRET_SUCCESS)\r
+ {\r
+ /* Load row data into SPC internal latch */\r
+ status = CySpcLoadRowFull(arrayId, rowNumber, rowData, rowSize);\r
+\r
+ if(CYRET_STARTED == status)\r
{\r
- /* Erase and program flash with the data from SPC interval latch */\r
- status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Wait for SPC to finish and get SPC status */\r
+ CyDelayUs(1u);\r
+ }\r
\r
- if(CYRET_STARTED == status)\r
+ /* Hide SPC status */\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
{\r
- while(CY_SPC_BUSY)\r
- {\r
- /* Wait for SPC to finish and get SPC status */\r
- CyDelayUs(1u);\r
- }\r
+ status = CYRET_SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
\r
- /* Hide SPC status */\r
- if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
- {\r
- status = CYRET_SUCCESS;\r
- }\r
- else\r
+ if(CYRET_SUCCESS == status)\r
+ {\r
+ /* Erase and program flash with data from SPC interval latch */\r
+ status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);\r
+\r
+ if(CYRET_STARTED == status)\r
{\r
- status = CYRET_UNKNOWN;\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Wait for SPC to finish and get SPC status */\r
+ CyDelayUs(1u);\r
+ }\r
+\r
+ /* Hide SPC status */\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
}\r
}\r
}\r
-\r
+ CySpcUnlock();\r
+ } /* if(CySpcLock() == CYRET_SUCCESS) */\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
}\r
-\r
- CySpcUnlock();\r
- }\r
- else\r
- {\r
- status = CYRET_LOCKED;\r
}\r
\r
return(status);\r
*\r
* Summary:\r
* Sets the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash. This function must be called before increasing CPU\r
-* clock frequency. It can optionally be called after lowering CPU clock\r
-* frequency in order to improve CPU performance.\r
+* coming back from the Flash. This function must be called before increasing the CPU\r
+* clock frequency. It can optionally be called after lowering the CPU clock\r
+* frequency in order to improve the CPU performance.\r
*\r
* Parameters:\r
* uint8 freq:\r
\r
/***************************************************************************\r
* The number of clock cycles the cache will wait before it samples data\r
- * coming back from Flash must be equal or greater to to the CPU frequency\r
+ * coming back from the Flash must be equal or greater to to the CPU frequency\r
* outlined in clock cycles.\r
***************************************************************************/\r
\r
- #if (CY_PSOC3)\r
-\r
- if (freq <= 22u)\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_22MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
- else if (freq <= 44u)\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
- else\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_GREATER_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
-\r
- #endif /* (CY_PSOC3) */\r
-\r
-\r
- #if (CY_PSOC5)\r
-\r
- if (freq <= 16u)\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
- else if (freq <= 33u)\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
- else if (freq <= 50u)\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
- else\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
-\r
- #endif /* (CY_PSOC5) */\r
+ if (freq < CY_FLASH_CACHE_WS_1_FREQ_MAX)\r
+ {\r
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |\r
+ CY_FLASH_CACHE_WS_1_VALUE_MASK;\r
+ }\r
+ else if (freq < CY_FLASH_CACHE_WS_2_FREQ_MAX)\r
+ {\r
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |\r
+ CY_FLASH_CACHE_WS_2_VALUE_MASK;\r
+ }\r
+ else if (freq < CY_FLASH_CACHE_WS_3_FREQ_MAX)\r
+ {\r
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |\r
+ CY_FLASH_CACHE_WS_3_VALUE_MASK;\r
+ }\r
+#if (CY_PSOC5)\r
+ else if (freq < CY_FLASH_CACHE_WS_4_FREQ_MAX)\r
+ {\r
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |\r
+ CY_FLASH_CACHE_WS_4_VALUE_MASK;\r
+ }\r
+ else if (freq <= CY_FLASH_CACHE_WS_5_FREQ_MAX)\r
+ {\r
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |\r
+ CY_FLASH_CACHE_WS_5_VALUE_MASK;\r
+ }\r
+#endif /* (CY_PSOC5) */\r
+ else\r
+ {\r
+ /* Halt CPU in debug mode if frequency is invalid */\r
+ CYASSERT(0u != 0u);\r
+ }\r
\r
/* Restore global interrupt enable state */\r
CyExitCriticalSection(interruptState);\r
*******************************************************************************/\r
void CyEEPROM_Start(void) \r
{\r
- /* Active Power Mode */\r
- *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;\r
+ uint8 interruptState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+\r
+ /***************************************************************************\r
+ * Enable SPC clock. This also internally enables the 36MHz IMO, since this\r
+ * is required for the SPC to function.\r
+ ***************************************************************************/\r
+ CY_FLASH_PM_ACT_CFG0_REG |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;\r
+ CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;\r
\r
- /* Standby Power Mode */\r
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;\r
+\r
+ /***************************************************************************\r
+ * The wake count defines the number of Bus Clock cycles it takes for the\r
+ * flash or EEPROM to wake up from a low power mode independent of the chip\r
+ * power mode. Wake up time for these blocks is 5 us.\r
+ * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E\r
+ * (30d) defines the wake up time as 60 cycles of the Bus Clock.\r
+ * This register needs to be written with a value dependent on the Bus Clock\r
+ * frequency so that the duration of the cycles is equal to or greater than\r
+ * the 5 us delay required.\r
+ ***************************************************************************/\r
+ CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;\r
+\r
+\r
+ /***************************************************************************\r
+ * Enable EEPROM. Re-enabling an EEPROM macro takes 5us. During this time,\r
+ * the EE will not acknowledge a PHUB request.\r
+ ***************************************************************************/\r
+ CY_FLASH_PM_ACT_CFG12_REG |= CY_FLASH_PM_ACT_CFG12_EN_EE;\r
+ CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_EE;\r
+\r
+ while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))\r
+ {\r
+ /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */\r
+ }\r
+\r
+ CyExitCriticalSection(interruptState);\r
}\r
\r
\r
*******************************************************************************/\r
void CyEEPROM_Stop (void) \r
{\r
- /* Active Power Mode */\r
- *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));\r
+ uint8 interruptState;\r
\r
- /* Standby Power Mode */\r
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ CY_FLASH_PM_ACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_EE));\r
+ CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_EE));\r
+\r
+ CyExitCriticalSection(interruptState);\r
}\r
\r
\r
*******************************************************************************/\r
void CyEEPROM_ReadReserve(void) \r
{\r
- /* Make a request for PHUB to have access */\r
- *CY_FLASH_EE_SCR_PTR |= CY_FLASH_EE_SCR_AHB_EE_REQ;\r
+ /* Make request for PHUB to have access */\r
+ CY_FLASH_EE_SCR_REG |= CY_FLASH_EE_SCR_AHB_EE_REQ;\r
\r
- while (0u == (*CY_FLASH_EE_SCR_PTR & CY_FLASH_EE_SCR_AHB_EE_ACK))\r
+ while (0u == (CY_FLASH_EE_SCR_REG & CY_FLASH_EE_SCR_AHB_EE_ACK))\r
{\r
- /* Wait for acknowledgement from PHUB */\r
+ /* Wait for acknowledgment from PHUB */\r
}\r
}\r
\r
*******************************************************************************/\r
void CyEEPROM_ReadRelease(void) \r
{\r
- *CY_FLASH_EE_SCR_PTR |= 0x00u;\r
+ CY_FLASH_EE_SCR_REG &= (uint8)(~CY_FLASH_EE_SCR_AHB_EE_REQ);\r
}\r
\r
\r
/*******************************************************************************\r
* File Name: CyFlash.h\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides the function definitions for the FLASH/EEPROM.\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#define CY_FLASH_NUMBER_ROWS (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE)\r
#define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE)\r
\r
+#if(CYDEV_ECC_ENABLE == 0)\r
+ #define CY_FLASH_SIZEOF_FULL_ROW (CY_FLASH_SIZEOF_ROW + CY_FLASH_SIZEOF_ECC_ROW)\r
+#else\r
+ #define CY_FLASH_SIZEOF_FULL_ROW (CY_FLASH_SIZEOF_ROW)\r
+#endif /* (CYDEV_ECC_ENABLE == 0) */\r
#define CY_EEPROM_BASE (CYDEV_EE_BASE)\r
#define CY_EEPROM_SIZE (CYDEV_EE_SIZE)\r
#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EEPROM_SECTOR_SIZE)\r
#define CY_EEPROM_SIZEOF_ROW (CYDEV_EEPROM_ROW_SIZE)\r
-#define CY_EEPROM_NUMBER_ROWS (EEPROM_SIZE / CYDEV_EEPROM_ROW_SIZE)\r
+#define CY_EEPROM_NUMBER_ROWS (CYDEV_EE_SIZE / CYDEV_EEPROM_ROW_SIZE)\r
#define CY_EEPROM_NUMBER_ARRAYS (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY)\r
-\r
+#define CY_EEPROM_NUMBER_SECTORS (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)\r
+#define CY_EEPROM_SIZEOF_SECTOR (CYDEV_EEPROM_SECTOR_SIZE)\r
\r
#if !defined(CYDEV_FLS_BASE)\r
#define CYDEV_FLS_BASE CYDEV_FLASH_BASE\r
/***************************************\r
* Registers\r
***************************************/\r
+/* Active Power Mode Configuration Register 0 */\r
+#define CY_FLASH_PM_ACT_CFG0_REG (* (reg8 *) CYREG_PM_ACT_CFG0)\r
+#define CY_FLASH_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)\r
+\r
+/* Alternate Active Power Mode Configuration Register 0 */\r
+#define CY_FLASH_PM_ALTACT_CFG0_REG (* (reg8 *) CYREG_PM_STBY_CFG0)\r
+#define CY_FLASH_PM_ALTACT_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0)\r
+\r
/* Active Power Mode Configuration Register 12 */\r
-#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12)\r
-#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)\r
+#define CY_FLASH_PM_ACT_CFG12_REG (* (reg8 *) CYREG_PM_ACT_CFG12)\r
+#define CY_FLASH_PM_ACT_CFG12_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)\r
\r
/* Alternate Active Power Mode Configuration Register 12 */\r
-#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12)\r
-#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)\r
+#define CY_FLASH_PM_ALTACT_CFG12_REG (* (reg8 *) CYREG_PM_STBY_CFG12)\r
+#define CY_FLASH_PM_ALTACT_CFG12_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)\r
+\r
+/* Wake count (BUS_CLK cycles) it takes for the Flash and EEPROM to wake up */\r
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_REG (* (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)\r
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_PTR ( (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)\r
+\r
+/* Flash macro control register */\r
+#define CY_FLASH_SPC_FM_EE_CR_REG (* (reg8 *) CYREG_SPC_FM_EE_CR)\r
+#define CY_FLASH_SPC_FM_EE_CR_PTR ( (reg8 *) CYREG_SPC_FM_EE_CR)\r
\r
\r
/* Cache Control Register */\r
***************************************/\r
\r
/* Power Mode Masks */\r
-#define CY_FLASH_PM_EE_MASK (0x10u)\r
-#define CY_FLASH_PM_FLASH_MASK (0x01u)\r
\r
-/* Frequency Constants */\r
+/* Enable EEPROM */\r
+#define CY_FLASH_PM_ACT_CFG12_EN_EE (0x10u)\r
+#define CY_FLASH_PM_ALTACT_CFG12_EN_EE (0x10u)\r
+\r
+/* Enable Flash */\r
#if (CY_PSOC3)\r
+ #define CY_FLASH_PM_ACT_CFG12_EN_FM (0x01u)\r
+ #define CY_FLASH_PM_ALTACT_CFG12_EN_FM (0x01u)\r
+#else\r
+ #define CY_FLASH_PM_ACT_CFG12_EN_FM (0x0Fu)\r
+ #define CY_FLASH_PM_ALTACT_CFG12_EN_FM (0x0Fu)\r
+#endif /* (CY_PSOC3) */\r
+\r
\r
- #define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u)\r
- #define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u)\r
- #define CY_FLASH_GREATER_44MHz (0x03u)\r
\r
+/* Frequency Constants */\r
+#if (CY_PSOC3)\r
+ #define CY_FLASH_CACHE_WS_VALUE_MASK (0xC0u)\r
+ #define CY_FLASH_CACHE_WS_1_VALUE_MASK (0x40u)\r
+ #define CY_FLASH_CACHE_WS_2_VALUE_MASK (0x80u)\r
+ #define CY_FLASH_CACHE_WS_3_VALUE_MASK (0xC0u)\r
+\r
+ #define CY_FLASH_CACHE_WS_1_FREQ_MAX (22u)\r
+ #define CY_FLASH_CACHE_WS_2_FREQ_MAX (44u)\r
+ #define CY_FLASH_CACHE_WS_3_FREQ_MAX (67u)\r
#endif /* (CY_PSOC3) */\r
\r
#if (CY_PSOC5)\r
-\r
- #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u)\r
- #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u)\r
- #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u)\r
- #define CY_FLASH_GREATER_51MHz (0x00u)\r
-\r
+ #define CY_FLASH_CACHE_WS_VALUE_MASK (0xE0u)\r
+ #define CY_FLASH_CACHE_WS_1_VALUE_MASK (0x40u)\r
+ #define CY_FLASH_CACHE_WS_2_VALUE_MASK (0x80u)\r
+ #define CY_FLASH_CACHE_WS_3_VALUE_MASK (0xC0u)\r
+ #define CY_FLASH_CACHE_WS_4_VALUE_MASK (0x00u)\r
+ #define CY_FLASH_CACHE_WS_5_VALUE_MASK (0x20u)\r
+\r
+ #define CY_FLASH_CACHE_WS_1_FREQ_MAX (16u)\r
+ #define CY_FLASH_CACHE_WS_2_FREQ_MAX (33u)\r
+ #define CY_FLASH_CACHE_WS_3_FREQ_MAX (50u)\r
+ #define CY_FLASH_CACHE_WS_4_FREQ_MAX (67u)\r
+ #define CY_FLASH_CACHE_WS_5_FREQ_MAX (83u)\r
#endif /* (CY_PSOC5) */\r
\r
#define CY_FLASH_CYCLES_MASK_SHIFT (0x06u)\r
#define CY_FLASH_CYCLES_MASK ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT)))\r
-#define CY_FLASH_EE_STARTUP_DELAY (5u)\r
\r
#define CY_FLASH_EE_SCR_AHB_EE_REQ (0x01u)\r
#define CY_FLASH_EE_SCR_AHB_EE_ACK (0x02u)\r
\r
\r
+#define CY_FLASH_EE_EE_AWAKE (0x20u)\r
+\r
+/* 5(us) * BUS_CLK(80 MHz) / granularity(2) */\r
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ (0xC8u)\r
+\r
+/* Enable clk_spc. This also internally enables the 36MHz IMO. */\r
+#define CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC (0x08u)\r
+#define CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC (0x08u)\r
\r
/* Default values for getting temperature. */\r
\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0\r
+* Thne following code is OBSOLETE and must not be used starting with cy_boot\r
+* 4.20.\r
+*\r
+* If the obsoleted macro definitions intended for use in the application use the\r
+* following scheme, redefine your own versions of these definitions:\r
+* #ifdef <OBSOLETED_DEFINE>\r
+* #undef <OBSOLETED_DEFINE>\r
+* #define <OBSOLETED_DEFINE> (<New Value>)\r
+* #endif\r
+*\r
+* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* used in the application and their modification might lead to unexpected\r
+* consequences.\r
+*******************************************************************************/\r
+#if (CY_PSOC5)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u)\r
+ #define CY_FLASH_GREATER_51MHz (0x00u)\r
+#endif /* (CY_PSOC5) */\r
+\r
+#if (CY_PSOC3)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u)\r
+ #define CY_FLASH_GREATER_44MHz (0x03u)\r
+#endif /* (CY_PSOC3) */\r
+\r
+#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12)\r
+#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)\r
+#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12)\r
+#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)\r
+#define CY_FLASH_PM_EE_MASK (0x10u)\r
+#define CY_FLASH_PM_FLASH_MASK (0x01u)\r
+\r
+/*******************************************************************************\r
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.0\r
*******************************************************************************/\r
#define FLASH_SIZE (CY_FLASH_SIZE)\r
#define FLASH_SIZEOF_SECTOR (CY_FLASH_SIZEOF_ARRAY)\r
#define EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY)\r
#define EEPROM_NUMBER_ROWS (CY_EEPROM_NUMBER_ROWS)\r
#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS)\r
-#define CY_EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS)\r
-#define CY_EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY)\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30\r
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.30\r
*******************************************************************************/\r
#define FLASH_CYCLES_PTR (CY_FLASH_CONTROL_PTR)\r
\r
/*******************************************************************************\r
* File Name: CyLib.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
-* Provides system API for the clocking, interrupts and watchdog timer.\r
+* Provides a system API for the clocking, interrupts and watchdog timer.\r
*\r
* Note:\r
* Documentation of the API's in this file is located in the\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
static void CyIMO_SetTrimValue(uint8 freq) ;\r
static void CyBusClk_Internal_SetDivider(uint16 divider);\r
\r
+#if(CY_PSOC5)\r
+ static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS];\r
+ static void CySysTickServiceCallbacks(void);\r
+ uint32 CySysTickInitVar = 0u;\r
+#endif /* (CY_PSOC5) */\r
+\r
\r
/*******************************************************************************\r
* Function Name: CyPLL_OUT_Start\r
* clock can still be used.\r
*\r
* Side Effects:\r
-* If wait is enabled: This function wses the Fast Time Wheel to time the wait.\r
+* If wait is enabled: This function uses the Fast Time Wheel to time the wait.\r
* Any other use of the Fast Time Wheel will be stopped during the period of\r
* this function and then restored. This function also uses the 100 KHz ILO.\r
* If not enabled, this function will enable the 100 KHz ILO for the period of\r
uint8 pmTwCfg2State;\r
\r
\r
- /* Enables the PLL circuit */\r
+ /* Enables PLL circuit */\r
CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE;\r
\r
if(wait != 0u)\r
\r
while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))\r
{\r
- /* Wait for the interrupt status */\r
+ /* Wait for interrupt status */\r
if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))\r
{\r
if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))\r
* None\r
*\r
* Side Effects:\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution results in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
* None\r
*\r
* Side Effects:\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution results in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the3 Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
* None\r
*\r
* Side Effects:\r
-* If wait is enabled: This function wses the Fast Time Wheel to time the wait.\r
+* If wait is enabled: This function uses the Fast Time Wheel to time the wait.\r
* Any other use of the Fast Time Wheel will be stopped during the period of\r
* this function and then restored. This function also uses the 100 KHz ILO.\r
* If not enabled, this function will enable the 100 KHz ILO for the period of\r
\r
if(0u != wait)\r
{\r
- /* Need to turn on the 100KHz ILO if it happens to not already be running.*/\r
+ /* Need to turn on 100KHz ILO if it happens to not already be running.*/\r
ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;\r
pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG;\r
pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG;\r
\r
while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))\r
{\r
- /* Wait for the interrupt status */\r
+ /* Wait for interrupt status */\r
}\r
\r
if(0u == ilo100KhzEnable)\r
/* If USB is powered */\r
if(usbPowerOn == 1u)\r
{\r
- /* Lock the USB Oscillator */\r
+ /* Lock USB Oscillator */\r
CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN;\r
}\r
break;\r
* None\r
*\r
* Side Effects:\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution results in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
* When the USB setting is chosen, the USB clock locking circuit is enabled.\r
uint8 nextFreq;\r
\r
/***************************************************************************\r
- * When changing the IMO frequency the Trim values must also be set\r
+ * If the IMO frequency is changed,the Trim values must also be set\r
* accordingly.This requires reading the current frequency. If the new\r
- * frequency is faster, then set the new trim and then change the frequency,\r
- * otherwise change the frequency and then set the new trim values.\r
+ * frequency is faster, then set a new trim and then change the frequency,\r
+ * otherwise change the frequency and then set new trim values.\r
***************************************************************************/\r
\r
currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK));\r
\r
- /* Check if the requested frequency is USB. */\r
+ /* Check if requested frequency is USB. */\r
nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq;\r
\r
switch (currentFreq)\r
\r
if (nextFreq >= currentFreq)\r
{\r
- /* Set the new trim first */\r
+ /* Set new trim first */\r
CyIMO_SetTrimValue(freq);\r
}\r
\r
- /* Set the usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */\r
+ /* Set usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */\r
switch(freq)\r
{\r
case CY_IMO_FREQ_3MHZ:\r
break;\r
}\r
\r
- /* Turn on the IMO Doubler, if switching to CY_IMO_FREQ_USB */\r
+ /* Tu rn onIMO Doubler, if switching to CY_IMO_FREQ_USB */\r
if (freq == CY_IMO_FREQ_USB)\r
{\r
CyIMO_EnableDoubler();\r
\r
if (nextFreq < currentFreq)\r
{\r
- /* Set the new trim after setting the frequency */\r
+ /* Set the trim after setting frequency */\r
CyIMO_SetTrimValue(freq);\r
}\r
}\r
* Sets the source of the clock output from the IMO block.\r
*\r
* The output from the IMO is by default the IMO itself. Optionally the MHz\r
-* Crystal or a DSI input can be the source of the IMO output instead.\r
+* Crystal or DSI input can be the source of the IMO output instead.\r
*\r
* Parameters:\r
* source: CY_IMO_SOURCE_DSI to set the DSI as source.\r
* None\r
*\r
* Side Effects:\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
*******************************************************************************/\r
void CyIMO_EnableDoubler(void) \r
{\r
- /* Set the FASTCLK_IMO_CR_PTR regigster's 4th bit */\r
+ /* Set FASTCLK_IMO_CR_PTR regigster's 4th bit */\r
CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER;\r
}\r
\r
* The current source and the new source must both be running and stable before\r
* calling this function.\r
*\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
*\r
* Parameters:\r
* uint8 divider:\r
-* Valid range [0-255]. The clock will be divided by this value + 1.\r
-* For example to divide by 2 this parameter should be set to 1.\r
+* The valid range is [0-255]. The clock will be divided by this value + 1.\r
+* For example to divide this parameter by two should be set to 1.\r
*\r
* Return:\r
* None\r
*\r
* Side Effects:\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
* When changing the Master or Bus clock divider value from div-by-n to div-by-1\r
********************************************************************************\r
*\r
* Summary:\r
-* Function used by CyBusClk_SetDivider(). For internal use only.\r
+* The function used by CyBusClk_SetDivider(). For internal use only.\r
*\r
* Parameters:\r
* divider: Valid range [0-65535].\r
* The clock will be divided by this value + 1.\r
-* For example to divide by 2 this parameter should be set to 1.\r
+* For example, to divide this parameter by two should be set to 1.\r
*\r
* Return:\r
* None\r
/* Enable mask bits to enable shadow loads */\r
CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK;\r
\r
- /* Update Shadow Divider Value Register with the new divider */\r
+ /* Update Shadow Divider Value Register with new divider */\r
CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider);\r
CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider);\r
\r
********************************************************************************\r
*\r
* Summary:\r
-* Sets the divider value used to generate Bus Clock.\r
+* Sets the divider value used to generate the Bus Clock.\r
*\r
* Parameters:\r
* divider: Valid range [0-65535]. The clock will be divided by this value + 1.\r
-* For example to divide by 2 this parameter should be set to 1.\r
+* For example, to divide this parameter by two should be set to 1.\r
*\r
* Return:\r
* None\r
*\r
* Side Effects:\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
\r
interruptState = CyEnterCriticalSection();\r
\r
- /* Work around to set the bus clock divider value */\r
+ /* Work around to set bus clock divider value */\r
busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u);\r
busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG;\r
\r
if ((divider == 0u) || (busClkDiv == 0u))\r
{\r
- /* Save away the master clock divider value */\r
+ /* Save away master clock divider value */\r
masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG;\r
\r
if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV)\r
\r
if (divider == 0u)\r
{\r
- /* Set the SSS bit and the divider register desired value */\r
+ /* Set SSS bit and divider register desired value */\r
CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS;\r
CyBusClk_Internal_SetDivider(divider);\r
}\r
CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS));\r
}\r
\r
- /* Restore the master clock */\r
+ /* Restore master clock */\r
CyMasterClk_SetDivider(masterClkDiv);\r
}\r
else\r
*\r
* Parameters:\r
* divider: Valid range [0-15]. The clock will be divided by this value + 1.\r
- * For example to divide by 2 this parameter should be set to 1.\r
+ * For example, to divide this parameter by two should be set to 1.\r
*\r
* Return:\r
* None\r
*\r
* Side Effects:\r
- * If as result of this function execution the CPU clock frequency is increased\r
- * then the number of clock cycles the cache will wait before it samples data\r
- * coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
- * with appropriate parameter. It can be optionally called if CPU clock\r
- * frequency is lowered in order to improve CPU performance.\r
+ * If this function execution resulted in the CPU clock frequency increasing,\r
+* then the number of clock cycles the cache will wait before it samples data\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
*******************************************************************************/\r
void CyILO_Start1K(void) \r
{\r
- /* Set the bit 1 of ILO RS */\r
+ /* Set bit 1 of ILO RS */\r
CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ;\r
}\r
\r
* Summary:\r
* Disables the ILO 1 KHz oscillator.\r
*\r
-* Note The ILO 1 KHz oscillator must be enabled if Sleep or Hibernate low power\r
+* Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low power\r
* mode APIs are expected to be used. For more information, refer to the Power\r
* Management section of this document.\r
*\r
*******************************************************************************/\r
void CyILO_Stop1K(void) \r
{\r
- /* Clear the bit 1 of ILO RS */\r
+ /* Clear bit 1 of ILO RS */\r
CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ));\r
}\r
\r
*******************************************************************************/\r
void CyILO_Enable33K(void) \r
{\r
- /* Set the bit 5 of ILO RS */\r
+ /* Set bit 5 of ILO RS */\r
CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ;\r
}\r
\r
/* Get current state. */\r
state = CY_LIB_SLOWCLK_ILO_CR0_REG;\r
\r
- /* Set the the oscillator power mode. */\r
+ /* Set the oscillator power mode. */\r
if(mode != CY_ILO_FAST_START)\r
{\r
CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE);\r
CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE)));\r
}\r
\r
- /* Return the old mode. */\r
+ /* Return old mode. */\r
return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION);\r
}\r
\r
CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN;\r
#endif /* (CY_PSOC3) */\r
\r
- /* Enable operation of the 32K Crystal Oscillator */\r
+ /* Enable operation of 32K Crystal Oscillator */\r
CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN;\r
\r
for (i = 1000u; i > 0u; i--)\r
{\r
if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT))\r
{\r
- /* Ready - switch to the hign power mode */\r
+ /* Ready - switch to high power mode */\r
(void) CyXTAL_32KHZ_SetPowerMode(0u);\r
\r
break;\r
********************************************************************************\r
*\r
* Summary:\r
-* Sets the power mode for the 32 KHz oscillator used during sleep mode.\r
+* Sets the power mode for the 32 KHz oscillator used during the sleep mode.\r
* Allows for lower power during sleep when there are fewer sources of noise.\r
-* During active mode the oscillator is always run in high power mode.\r
+* During the active mode the oscillator is always run in the high power mode.\r
*\r
* Parameters:\r
* uint8 mode\r
uint8 pmTwCfg2Tmp;\r
\r
\r
- /* Enables the MHz crystal oscillator circuit */\r
+ /* Enables MHz crystal oscillator circuit */\r
CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE;\r
\r
\r
/* Read XERR bit to clear it */\r
(void) CY_CLK_XMHZ_CSR_REG;\r
\r
- /* Wait for a millisecond - 4 x 250 us */\r
+ /* Wait for 1 millisecond - 4 x 250 us */\r
for(count = 4u; count > 0u; count--)\r
{\r
while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))\r
{\r
- /* Wait for the FTW interrupt event */\r
+ /* Wait for FTW interrupt event */\r
}\r
}\r
\r
\r
/*******************************************************************\r
- * High output indicates oscillator failure.\r
- * Only can be used after start-up interval (1 ms) is completed.\r
+ * High output indicates an oscillator failure.\r
+ * Only can be used after a start-up interval (1 ms) is completed.\r
*******************************************************************/\r
if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR))\r
{\r
*******************************************************************************/\r
void CyXTAL_Stop(void) \r
{\r
- /* Disable the the oscillator. */\r
+ /* Disable oscillator. */\r
FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE));\r
}\r
\r
*\r
* Summary:\r
* Reads the XERR status bit for the megahertz crystal. This status bit is a\r
-* sticky clear on read value. This function is not available for PSoC5.\r
+* sticky, clear on read. This function is not available for PSoC5.\r
*\r
* Parameters:\r
* None\r
uint8 CyXTAL_ReadStatus(void) \r
{\r
/***************************************************************************\r
- * High output indicates oscillator failure. Only use this after start-up\r
- * interval is completed. This can be used for status and failure recovery.\r
+ * High output indicates an oscillator failure. Only use this after a start-up\r
+ * interval is completed. This can be used for the status and failure recovery.\r
***************************************************************************/\r
return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u);\r
}\r
* Enables the fault recovery circuit which will switch to the IMO in the case\r
* of a fault in the megahertz crystal circuit. The crystal must be up and\r
* running with the XERR bit at 0, before calling this function to prevent\r
-* immediate fault switchover. This function is not available for PSoC5.\r
+* an immediate fault switchover. This function is not available for PSoC5.\r
*\r
* Parameters:\r
* None\r
********************************************************************************\r
*\r
* Summary:\r
-* Sets the startup settings for the crystal. Logic model outputs a frequency\r
+* Sets the startup settings for the crystal. The logic model outputs a frequency\r
* (setting + 4) MHz when enabled.\r
*\r
* This is artificial as the actual frequency is determined by an attached\r
*\r
* Parameters:\r
* setting: Valid range [0-31].\r
-* Value is dependent on the frequency and quality of the crystal being used.\r
+* The value is dependent on the frequency and quality of the crystal being used.\r
* Refer to the device TRM and datasheet for more information.\r
*\r
* Return:\r
********************************************************************************\r
*\r
* Summary:\r
-* Forces a software reset of the device.\r
+* Forces a device software reset.\r
*\r
* Parameters:\r
* None\r
*\r
* Note:\r
* CyDelay has been implemented with the instruction cache assumed enabled. When\r
-* instruction cache is disabled on PSoC5, CyDelay will be two times larger. For\r
-* example, with instruction cache disabled CyDelay(100) would result in about\r
-* 200 ms delay instead of 100 ms.\r
+* the instruction cache is disabled on PSoC5, CyDelay will be two times larger.\r
+* For example, with instruction cache disabled CyDelay(100) would result in\r
+* about 200 ms delay instead of 100 ms.\r
*\r
* Parameters:\r
* milliseconds: number of milliseconds to delay.\r
*\r
* Side Effects:\r
* CyDelayUS has been implemented with the instruction cache assumed enabled.\r
- * When instruction cache is disabled on PSoC 5, CyDelayUs will be two times\r
- * larger. For example, with instruction cache disabled CyDelayUs(100) would\r
+ * When the instruction cache is disabled on PSoC 5, CyDelayUs will be two times\r
+ * larger. For example, with the instruction cache disabled CyDelayUs(100) would\r
* result in about 200 us delay instead of 100 us.\r
*\r
* If the bus clock frequency is a small non-integer number, the actual delay\r
********************************************************************************\r
*\r
* Summary:\r
-* Sets clock frequency for CyDelay.\r
+* Sets the clock frequency for CyDelay.\r
*\r
* Parameters:\r
-* freq: Frequency of bus clock in Hertz.\r
+* freq: The frequency of the bus clock in Hertz.\r
*\r
* Return:\r
* None\r
* Enables the watchdog timer.\r
*\r
* The timer is configured for the specified count interval, the central\r
-* timewheel is cleared, the setting for low power mode is configured and the\r
+* timewheel is cleared, the setting for the low power mode is configured and the\r
* watchdog timer is enabled.\r
*\r
* Once enabled the watchdog cannot be disabled. The watchdog counts each time\r
CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET;\r
CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET));\r
\r
- /* Setting the low power mode */\r
+ /* Setting low power mode */\r
CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) |\r
(CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK)));\r
\r
- /* Enables the watchdog reset */\r
+ /* Enables watchdog reset */\r
CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN;\r
}\r
\r
*\r
* Summary:\r
* Enables the digital low voltage monitors to generate interrupt on Vddd\r
-* archives specified threshold and optionally resets device.\r
+* archives specified threshold and optionally resets the device.\r
*\r
* Parameters:\r
-* reset: Option to reset device at a specified Vddd threshold:\r
+* reset: The option to reset the device at a specified Vddd threshold:\r
* 0 - Device is not reset.\r
* 1 - Device is reset.\r
*\r
* threshold: Sets the trip level for the voltage monitor.\r
-* Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV\r
-* interval.\r
+* Values from 1.70 V to 5.45 V are accepted with an interval of approximately\r
+* 250 mV.\r
*\r
* Return:\r
* None\r
(CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK)));\r
CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN;\r
\r
- /* Timeout to eliminate glitches on the LVI/HVI when enabling */\r
+ /* Timeout to eliminate glitches on LVI/HVI when enabling */\r
CyDelayUs(1u);\r
\r
(void)CY_VD_PERSISTENT_STATUS_REG;\r
*\r
* Summary:\r
* Enables the analog low voltage monitors to generate interrupt on Vdda\r
-* archives specified threshold and optionally resets device.\r
+* archives specified threshold and optionally resets the device.\r
*\r
* Parameters:\r
-* reset: Option to reset device at a specified Vdda threshold:\r
+* reset: The option to reset the device at a specified Vdda threshold:\r
* 0 - Device is not reset.\r
* 1 - Device is reset.\r
*\r
CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu);\r
CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN;\r
\r
- /* Timeout to eliminate glitches on the LVI/HVI when enabling */\r
+ /* Timeout to eliminate glitches on LVI/HVI when enabling */\r
CyDelayUs(1u);\r
\r
(void)CY_VD_PERSISTENT_STATUS_REG;\r
CY_NOP;\r
CY_NOP;\r
\r
- /* All entries in the cache are invalidated on the next clock cycle. */\r
+ /* All entries in cache are invalidated on next clock cycle. */\r
CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH;\r
\r
+ /* Once this is executed it's guaranteed the cache has been flushed */\r
+ (void) CY_CACHE_CONTROL_REG;\r
\r
- /***********************************************************************\r
- * The prefetch unit could/would be filled with the instructions that\r
- * succeed the flush. Since a flush is desired then theoretically those\r
- * instructions might be considered stale/invalid.\r
- ***********************************************************************/\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
+ /* Flush the pipeline */\r
+ CY_SYS_ISB;\r
\r
/* Restore global interrupt enable state */\r
CyExitCriticalSection(interruptState);\r
* SysTick, PendSV and others.\r
*\r
* Parameters:\r
- * number: Interrupt number, valid range [0-15].\r
- address: Pointer to an interrupt service routine.\r
+ * number: System interrupt number:\r
+ * CY_INT_NMI_IRQN - Non Maskable Interrupt\r
+ * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt\r
+ * CY_INT_MEM_MANAGE_IRQN - Memory Management Interrupt\r
+ * CY_INT_BUS_FAULT_IRQN - Bus Fault Interrupt\r
+ * CY_INT_USAGE_FAULT_IRQN - Usage Fault Interrupt\r
+ * CY_INT_SVCALL_IRQN - SV Call Interrupt\r
+ * CY_INT_DEBUG_MONITOR_IRQN - Debug Monitor Interrupt\r
+ * CY_INT_PEND_SV_IRQN - Pend SV Interrupt\r
+ * CY_INT_SYSTICK_IRQN - System Tick Interrupt\r
+ *\r
+ * address: Pointer to an interrupt service routine.\r
*\r
* Return:\r
* The old ISR vector at this location.\r
* SysTick, PendSV and others.\r
*\r
* Parameters:\r
- * number: The interrupt number, valid range [0-15].\r
+ * number: System interrupt number:\r
+ * CY_INT_NMI_IRQN - Non Maskable Interrupt\r
+ * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt\r
+ * CY_INT_MEMORY_MANAGEMENT_IRQN - Memory Management Interrupt\r
+ * CY_INT_BUS_FAULT_IRQN - Bus Fault Interrupt\r
+ * CY_INT_USAGE_FAULT_IRQN - Usage Fault Interrupt\r
+ * CY_INT_SVCALL_IRQN - SV Call Interrupt\r
+ * CY_INT_DEBUG_MONITOR_IRQN - Debug Monitor Interrupt\r
+ * CY_INT_PEND_SV_IRQN - Pend SV Interrupt\r
+ * CY_INT_SYSTICK_IRQN - System Tick Interrupt\r
*\r
* Return:\r
* Address of the ISR in the interrupt vector table.\r
* number: Valid range [0-31]. Interrupt number\r
*\r
* Return:\r
- * Address of the ISR in the interrupt vector table.\r
+ * The address of the ISR in the interrupt vector table.\r
*\r
*******************************************************************************/\r
cyisraddress CyIntGetVector(uint8 number)\r
\r
CYASSERT(number <= CY_INT_NUMBER_MAX);\r
\r
- /* Get a pointer to the Interrupt enable register. */\r
+ /* Get pointer to Interrupt enable register. */\r
stateReg = CY_INT_ENABLE_PTR;\r
\r
- /* Get the state of the interrupt. */\r
+ /* Get state of interrupt. */\r
return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u));\r
}\r
\r
\r
CYASSERT(number <= CY_INT_NUMBER_MAX);\r
\r
- /* Get a pointer to the Interrupt enable register. */\r
+ /* Get pointer to Interrupt enable register. */\r
stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u);\r
\r
- /* Get the state of the interrupt. */\r
+ /* Get state of interrupt. */\r
return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u)));\r
}\r
\r
* If 1 is passed as a parameter:\r
* - if any of the SC blocks are used - enable pumps for the SC blocks and\r
* start boost clock.\r
- * - For the each enabled SC block set boost clock index and enable boost\r
+ * - For each enabled SC block set a boost clock index and enable the boost\r
* clock.\r
*\r
* If non-1 value is passed as a parameter:\r
* - If all SC blocks are not used - disable pumps for the SC blocks and\r
- * stop boost clock.\r
- * - For the each enabled SC block clear boost clock index and disable boost\r
+ * stop the boost clock.\r
+ * - For each enabled SC block clear the boost clock index and disable the boost\r
* clock.\r
*\r
- * The global variable CyScPumpEnabled is updated to be equal to passed\r
+ * The global variable CyScPumpEnabled is updated to be equal to passed the\r
* parameter.\r
*\r
* Parameters:\r
- * uint8 enable: Enable/disable SC pumps and boost clock for enabled SC block.\r
+ * uint8 enable: Enable/disable SC pumps and the boost clock for the enabled SC block.\r
* 1 - Enable\r
* 0 - Disable\r
*\r
#endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
\r
\r
+#if(CY_PSOC5)\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickStart\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Configures the SysTick timer to generate interrupt every 1 ms by call to the\r
+ * CySysTickInit() function and starts it by calling CySysTickEnable() function.\r
+ * Refer to the corresponding function description for the details.\r
+\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickStart(void)\r
+ {\r
+ if (0u == CySysTickInitVar)\r
+ {\r
+ CySysTickInit();\r
+ CySysTickInitVar = 1u;\r
+ }\r
+\r
+ CySysTickEnable();\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickInit\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Initializes the callback addresses with pointers to NULL, associates the\r
+ * SysTick system vector with the function that is responsible for calling\r
+ * registered callback functions, configures SysTick timer to generate interrupt\r
+ * every 1 ms.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set.\r
+ *\r
+ * The 1 ms interrupt interval is configured based on the frequency determined\r
+ * by PSoC Creator at build time. If System clock frequency is changed in\r
+ * runtime, the CyDelayFreq() with the appropriate parameter should be called.\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickInit(void)\r
+ {\r
+ uint32 i;\r
+\r
+ for (i = 0u; i<CY_SYS_SYST_NUM_OF_CALLBACKS; i++)\r
+ {\r
+ CySysTickCallbacks[i] = (void *) 0;\r
+ }\r
+\r
+ (void) CyIntSetSysVector(CY_INT_SYSTICK_IRQN, &CySysTickServiceCallbacks);\r
+ CySysTickSetClockSource(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK);\r
+ CySysTickSetReload(cydelay_freq_hz/1000u);\r
+ CySysTickClear();\r
+ CyIntEnable(CY_INT_SYSTICK_IRQN);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickEnable\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Enables the SysTick timer and its interrupt.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickEnable(void)\r
+ {\r
+ CySysTickEnableInterrupt();\r
+ CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE;\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickStop\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Stops the system timer (SysTick).\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickStop(void)\r
+ {\r
+ CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE));\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickEnableInterrupt\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Enables the SysTick interrupt.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickEnableInterrupt(void)\r
+ {\r
+ CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE_INT;\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickDisableInterrupt\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Disables the SysTick interrupt.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickDisableInterrupt(void)\r
+ {\r
+ CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE_INT));\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickSetReload\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Sets value the counter is set to on startup and after it reaches zero. This\r
+ * function do not change or reset current sysTick counter value, so it should\r
+ * be cleared using CySysTickClear() API.\r
+ *\r
+ * Parameters:\r
+ * value: Valid range [0x0-0x00FFFFFF]. Counter reset value.\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickSetReload(uint32 value)\r
+ {\r
+ CY_SYS_SYST_RVR_REG = (value & CY_SYS_SYST_RVR_CNT_MASK);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickGetReload\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Sets value the counter is set to on startup and after it reaches zero.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * Counter reset value\r
+ *\r
+ *******************************************************************************/\r
+ uint32 CySysTickGetReload(void)\r
+ {\r
+ return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_RVR_CNT_MASK);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickGetValue\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Gets current SysTick counter value.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * Current SysTick counter value\r
+ *\r
+ *******************************************************************************/\r
+ uint32 CySysTickGetValue(void)\r
+ {\r
+ return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_CVR_REG);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickSetClockSource\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Sets the clock source for the SysTick counter.\r
+ *\r
+ * Parameters:\r
+ * clockSource: Clock source for SysTick counter\r
+ * Define Clock Source\r
+ * CY_SYS_SYST_CSR_CLK_SRC_SYSCLK SysTick is clocked by CPU clock.\r
+ * CY_SYS_SYST_CSR_CLK_SRC_LFCLK SysTick is clocked by the low frequency\r
+ * clock (ILO 100 KHz for PSoC 5LP, LFCLK for PSoC 4).\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set. If clock source is not ready this\r
+ * function call will have no effect. After changing clock source to the low frequency\r
+ * clock the counter and reload register values will remain unchanged so time to\r
+ * the interrupt will be significantly bigger and vice versa.\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickSetClockSource(uint32 clockSource)\r
+ {\r
+ if (clockSource == CY_SYS_SYST_CSR_CLK_SRC_SYSCLK)\r
+ {\r
+ CY_SYS_SYST_CSR_REG |= (uint32)(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT);\r
+ }\r
+ else\r
+ {\r
+ CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT));\r
+ }\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickGetCountFlag\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * The count flag is set once SysTick counter reaches zero.\r
+ * The flag cleared on read.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * Returns non-zero value if counter is set, otherwise zero is returned.\r
+ *\r
+ *******************************************************************************/\r
+ uint32 CySysTickGetCountFlag(void)\r
+ {\r
+ return ((CY_SYS_SYST_CSR_REG>>CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickClear\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Clears the SysTick counter for well-defined startup.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickClear(void)\r
+ {\r
+ CY_SYS_SYST_CVR_REG = 0u;\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickSetCallback\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * The function set the pointers to the functions that will be called on\r
+ * SysTick interrupt.\r
+ *\r
+ * Parameters:\r
+ * number: The number of callback function address to be set.\r
+ * The valid range is from 0 to 4.\r
+ * CallbackFunction: Function address.\r
+ *\r
+ * Return:\r
+ * Returns the address of the previous callback function.\r
+ * The NULL is returned if the specified address in not set.\r
+ *\r
+ *******************************************************************************/\r
+ cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function)\r
+ {\r
+ cySysTickCallback retVal;\r
+\r
+ retVal = CySysTickCallbacks[number];\r
+ CySysTickCallbacks[number] = function;\r
+ return (retVal);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickGetCallback\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * The function get the specified callback pointer.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ cySysTickCallback CySysTickGetCallback(uint32 number)\r
+ {\r
+ return ((cySysTickCallback) CySysTickCallbacks[number]);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickServiceCallbacks\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * System Tick timer interrupt routine\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ static void CySysTickServiceCallbacks(void)\r
+ {\r
+ uint32 i;\r
+\r
+ /* Verify that tick timer flag was set */\r
+ if (1u == CySysTickGetCountFlag())\r
+ {\r
+ for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++)\r
+ {\r
+ if (CySysTickCallbacks[i] != (void *) 0)\r
+ {\r
+ (void)(CySysTickCallbacks[i])();\r
+ }\r
+ }\r
+ }\r
+ }\r
+#endif /* (CY_PSOC5) */\r
+\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: CyLib.h\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides the function definitions for the system, clocking, interrupts and\r
* Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
void CySetScPumps(uint8 enable) ;\r
\r
+#if(CY_PSOC5)\r
+ /* Default interrupt handler */\r
+ CY_ISR_PROTO(IntDefaultHandler);\r
+#endif /* (CY_PSOC5) */\r
+\r
+#if(CY_PSOC5)\r
+ /* System tick timer APIs */\r
+ typedef void (*cySysTickCallback)(void);\r
+\r
+ void CySysTickStart(void);\r
+ void CySysTickInit(void);\r
+ void CySysTickEnable(void);\r
+ void CySysTickStop(void);\r
+ void CySysTickEnableInterrupt(void);\r
+ void CySysTickDisableInterrupt(void);\r
+ void CySysTickSetReload(uint32 value);\r
+ uint32 CySysTickGetReload(void);\r
+ uint32 CySysTickGetValue(void);\r
+ cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function);\r
+ cySysTickCallback CySysTickGetCallback(uint32 number);\r
+ void CySysTickSetClockSource(uint32 clockSource);\r
+ uint32 CySysTickGetCountFlag(void);\r
+ void CySysTickClear(void);\r
+#endif /* (CY_PSOC5) */\r
\r
/***************************************\r
* API Constants\r
#define CY_ALT_ACT_USB_ENABLED (0x01u)\r
\r
\r
+#if(CY_PSOC5)\r
+\r
+ /***************************************************************************\r
+ * Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ * so that all instructions following the ISB are fetched from cache or\r
+ * memory, after the instruction has been completed.\r
+ ***************************************************************************/\r
+\r
+ #if defined(__ARMCC_VERSION)\r
+ #define CY_SYS_ISB __isb(0x0f)\r
+ #else /* ASM for GCC & IAR */\r
+ #define CY_SYS_ISB asm volatile ("isb \n")\r
+ #endif /* (__ARMCC_VERSION) */\r
+\r
+#endif /* (CY_PSOC5) */\r
+\r
+\r
/***************************************\r
* Registers\r
***************************************/\r
#define CY_CACHE_CONTROL_REG (* (reg16 *) CYREG_CACHE_CC_CTL )\r
#define CY_CACHE_CONTROL_PTR ( (reg16 *) CYREG_CACHE_CC_CTL )\r
\r
+ /* System tick registers */\r
+ #define CY_SYS_SYST_CSR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CTL)\r
+ #define CY_SYS_SYST_CSR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CTL)\r
+\r
+ #define CY_SYS_SYST_RVR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_RELOAD)\r
+ #define CY_SYS_SYST_RVR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_RELOAD)\r
+\r
+ #define CY_SYS_SYST_CVR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CURRENT)\r
+ #define CY_SYS_SYST_CVR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CURRENT)\r
+\r
+ #define CY_SYS_SYST_CALIB_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CAL)\r
+ #define CY_SYS_SYST_CALIB_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CAL)\r
+\r
#elif (CY_PSOC3)\r
\r
/* Interrupt Address Vector registers */\r
#define CY_INT_VECT_TABLE ((cyisraddress CYXDATA *) CYREG_INTC_VECT_MBASE)\r
\r
- /* Interrrupt Controller Priority Registers */\r
+ /* Interrupt Controller Priority Registers */\r
#define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_INTC_PRIOR0)\r
#define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_INTC_PRIOR0)\r
\r
- /* Interrrupt Controller Set Enable Registers */\r
+ /* Interrupt Controller Set Enable Registers */\r
#define CY_INT_ENABLE_REG (* (reg8 *) CYREG_INTC_SET_EN0)\r
#define CY_INT_ENABLE_PTR ( (reg8 *) CYREG_INTC_SET_EN0)\r
\r
#define CY_INT_SET_EN3_REG (* (reg8 *) CYREG_INTC_SET_EN3)\r
#define CY_INT_SET_EN3_PTR ( (reg8 *) CYREG_INTC_SET_EN3)\r
\r
- /* Interrrupt Controller Clear Enable Registers */\r
+ /* Interrupt Controller Clear Enable Registers */\r
#define CY_INT_CLEAR_REG (* (reg8 *) CYREG_INTC_CLR_EN0)\r
#define CY_INT_CLEAR_PTR ( (reg8 *) CYREG_INTC_CLR_EN0)\r
\r
#define CY_INT_CLR_EN3_PTR ( (reg8 *) CYREG_INTC_CLR_EN3)\r
\r
\r
- /* Interrrupt Controller Set Pend Registers */\r
+ /* Interrupt Controller Set Pend Registers */\r
#define CY_INT_SET_PEND_REG (* (reg8 *) CYREG_INTC_SET_PD0)\r
#define CY_INT_SET_PEND_PTR ( (reg8 *) CYREG_INTC_SET_PD0)\r
\r
- /* Interrrupt Controller Clear Pend Registers */\r
+ /* Interrupt Controller Clear Pend Registers */\r
#define CY_INT_CLR_PEND_REG (* (reg8 *) CYREG_INTC_CLR_PD0)\r
#define CY_INT_CLR_PEND_PTR ( (reg8 *) CYREG_INTC_CLR_PD0)\r
\r
* Macro Name: CyAssert\r
********************************************************************************\r
* Summary:\r
-* Macro that evaluates the expression and if it is false (evaluates to 0) then\r
-* the processor is halted.\r
+* The macro that evaluates the expression and if it is false (evaluates to 0)\r
+* then the processor is halted.\r
*\r
* This macro is evaluated unless NDEBUG is defined.\r
*\r
#define CY_RESET_GPIO1 (0x80u)\r
\r
\r
-/* Interrrupt Controller Configuration and Status Register */\r
+/* Interrupt Controller Configuration and Status Register */\r
#if(CY_PSOC3)\r
#define INTERRUPT_CSR ((reg8 *) CYREG_INTC_CSR_EN)\r
#define DISABLE_IRQ_SET ((uint8)(0x01u << 1u)) /* INTC_CSR_EN */\r
#define CY_CACHE_CONTROL_FLUSH (0x0004u)\r
#define CY_LIB_RESET_CR2_RESET (0x01u)\r
\r
+#if(CY_PSOC5)\r
+ /* System tick API constants */\r
+ #define CY_SYS_SYST_CSR_ENABLE ((uint32) (0x01u))\r
+ #define CY_SYS_SYST_CSR_ENABLE_INT ((uint32) (0x02u))\r
+ #define CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT ((uint32) (0x02u))\r
+ #define CY_SYS_SYST_CSR_COUNTFLAG_SHIFT ((uint32) (16u))\r
+ #define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ((uint32) (1u))\r
+ #define CY_SYS_SYST_CSR_CLK_SRC_LFCLK ((uint32) (0u))\r
+ #define CY_SYS_SYST_RVR_CNT_MASK ((uint32) (0x00FFFFFFu))\r
+ #define CY_SYS_SYST_NUM_OF_CALLBACKS ((uint32) (5u))\r
+#endif /* (CY_PSOC5) */\r
+\r
+\r
\r
/*******************************************************************************\r
* Interrupt API constants\r
/* Mask to get valid range of system interrupt 0-15 */\r
#define CY_INT_SYS_NUMBER_MASK (0xFu)\r
\r
+#if(CY_PSOC5)\r
+\r
+ /* CyIntSetSysVector()/CyIntGetSysVector() - parameter definitions */\r
+ #define CY_INT_NMI_IRQN ( 2u) /* Non Maskable Interrupt */\r
+ #define CY_INT_HARD_FAULT_IRQN ( 3u) /* Hard Fault Interrupt */\r
+ #define CY_INT_MEM_MANAGE_IRQN ( 4u) /* Memory Management Interrupt */\r
+ #define CY_INT_BUS_FAULT_IRQN ( 5u) /* Bus Fault Interrupt */\r
+ #define CY_INT_USAGE_FAULT_IRQN ( 6u) /* Usage Fault Interrupt */\r
+ #define CY_INT_SVCALL_IRQN (11u) /* SV Call Interrupt */\r
+ #define CY_INT_DEBUG_MONITOR_IRQN (12u) /* Debug Monitor Interrupt */\r
+ #define CY_INT_PEND_SV_IRQN (14u) /* Pend SV Interrupt */\r
+ #define CY_INT_SYSTICK_IRQN (15u) /* System Tick Interrupt */\r
+\r
+#endif /* (CY_PSOC5) */\r
\r
/*******************************************************************************\r
* Interrupt Macros\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used.\r
+* The following code is OBSOLETE and must not be used.\r
+*\r
+* If the obsoleted macro definitions intended for use in the application use the\r
+* following scheme, redefine your own versions of these definitions:\r
+* #ifdef <OBSOLETED_DEFINE>\r
+* #undef <OBSOLETED_DEFINE>\r
+* #define <OBSOLETED_DEFINE> (<New Value>)\r
+* #endif\r
+*\r
+* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* used in the application and their modification might lead to unexpected\r
+* consequences.\r
*******************************************************************************/\r
+\r
#define CYGlobalIntEnable CyGlobalIntEnable\r
#define CYGlobalIntDisable CyGlobalIntDisable\r
\r
#define cymemset(s,c,n) memset((s),(c),(n))\r
#define cymemcpy(d,s,n) memcpy((d),(s),(n))\r
\r
-\r
-/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0\r
-*******************************************************************************/\r
#define MFGCFG_X32_TR_PTR (CY_CLK_XTAL32_TR_PTR)\r
#define MFGCFG_X32_TR (CY_CLK_XTAL32_TR_REG)\r
#define SLOWCLK_X32_TST_PTR (CY_CLK_XTAL32_TST_PTR)\r
#define CY_VD_PRESISTENT_STATUS_PTR (CY_VD_PERSISTENT_STATUS_PTR)\r
\r
\r
-/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.20\r
-*******************************************************************************/\r
-\r
#if(CY_PSOC5)\r
\r
#define CYINT_IRQ_BASE (CY_INT_IRQ_BASE)\r
#endif /* (CY_PSOC5) */\r
\r
\r
-/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30\r
-*******************************************************************************/\r
+\r
#define BUS_AMASK_CLEAR (0xF0u)\r
#define BUS_DMASK_CLEAR (0x00u)\r
#define CLKDIST_LD_LOAD_SET (0x01u)\r
#define CLKDIST_CR (*(reg8 *) CYREG_CLKDIST_CR)\r
\r
\r
-/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.50\r
-*******************************************************************************/\r
#define IMO_PM_ENABLE (0x10u)\r
#define PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)\r
#define PM_ACT_CFG0 (*(reg8 *) CYREG_PM_ACT_CFG0)\r
/*******************************************************************************\r
* File Name: CySpc.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides an API for the System Performance Component.\r
* application.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
* Summary:\r
* Loads a row of data into the row latch of a Flash/EEPROM array.\r
*\r
+* The buffer pointer should point to the data that should be written to the\r
+* flash row directly (no data in ECC/flash will be preserved). It is Flash API\r
+* responsibility to prepare data: the preserved data are copied from flash into\r
+* array with the modified data.\r
+*\r
* Parameters:\r
* uint8 array:\r
* Id of the array.\r
}\r
\r
\r
+/*******************************************************************************\r
+* Function Name: CySpcLoadRowFull\r
+********************************************************************************\r
+* Summary:\r
+* Loads a row of data into the row latch of a Flash/EEPROM array.\r
+*\r
+* The only data that are going to be changed should be passed. The function\r
+* will handle unmodified data preservation based on DWR settings and input\r
+* parameters.\r
+*\r
+* Parameters:\r
+* uint8 array:\r
+* Id of the array.\r
+*\r
+* uint16 row:\r
+* Flash row number to be loaded.\r
+*\r
+* uint8* buffer:\r
+* Data to be loaded to the row latch\r
+*\r
+* uint8 size:\r
+* The number of data bytes that the SPC expects to be written. Depends on the\r
+* type of the array and, if the array is Flash, whether ECC is being enabled\r
+* or not. There are following values: flash row latch size with ECC enabled,\r
+* flash row latch size with ECC disabled and EEPROM row latch size.\r
+*\r
+* Return:\r
+* CYRET_STARTED\r
+* CYRET_CANCELED\r
+* CYRET_LOCKED\r
+*\r
+*******************************************************************************/\r
+cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\\r
+\r
+{\r
+ cystatus status = CYRET_STARTED;\r
+ uint16 i;\r
+\r
+ #if (CYDEV_ECC_ENABLE == 0)\r
+ uint32 offset;\r
+ #endif /* (CYDEV_ECC_ENABLE == 0) */\r
+\r
+ /* Make sure the SPC is ready to accept command */\r
+ if(CY_SPC_IDLE)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW);\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW;\r
+\r
+ /* Make sure the command was accepted */\r
+ if(CY_SPC_BUSY)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = array;\r
+\r
+ /*******************************************************************\r
+ * If "Enable Error Correcting Code (ECC)" and "Store Configuration\r
+ * Data in ECC" DWR options are disabled, ECC section is available\r
+ * for user data.\r
+ *******************************************************************/\r
+ #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))\r
+\r
+ /*******************************************************************\r
+ * If size parameter equals size of the ECC row and selected array\r
+ * identification corresponds to the flash array (but not to EEPROM\r
+ * array) then data are going to be written to the ECC section.\r
+ * In this case flash data must be preserved. The flash data copied\r
+ * from flash data section to the SPC data register.\r
+ *******************************************************************/\r
+ if ((size == CYDEV_ECC_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))\r
+ {\r
+ offset = CYDEV_FLS_BASE +\r
+ ((uint32) array * CYDEV_FLS_SECTOR_SIZE) +\r
+ ((uint32) row * CYDEV_FLS_ROW_SIZE );\r
+\r
+ for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));\r
+ }\r
+ }\r
+\r
+ #endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */\r
+\r
+\r
+ for(i = 0u; i < size; i++)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = buffer[i];\r
+ }\r
+\r
+\r
+ /*******************************************************************\r
+ * If "Enable Error Correcting Code (ECC)" DWR option is disabled,\r
+ * ECC section can be used for storing device configuration data\r
+ * ("Store Configuration Data in ECC" DWR option is enabled) or for\r
+ * storing user data in the ECC section ("Store Configuration Data in\r
+ * ECC" DWR option is enabled). In both cases, the data in the ECC\r
+ * section must be preserved if flash data is written.\r
+ *******************************************************************/\r
+ #if (CYDEV_ECC_ENABLE == 0)\r
+\r
+\r
+ /*******************************************************************\r
+ * If size parameter equals size of the flash row and selected array\r
+ * identification corresponds to the flash array (but not to EEPROM\r
+ * array) then data are going to be written to the flash data\r
+ * section. In this case, ECC section data must be preserved.\r
+ * The ECC section data copied from ECC section to the SPC data\r
+ * register.\r
+ *******************************************************************/\r
+ if ((size == CYDEV_FLS_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))\r
+ {\r
+ offset = CYDEV_ECC_BASE +\r
+ ((uint32) array * CYDEV_ECC_SECTOR_SIZE) +\r
+ ((uint32) row * CYDEV_ECC_ROW_SIZE );\r
+\r
+ for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));\r
+ }\r
+ }\r
+\r
+ #else\r
+\r
+ if(0u != row)\r
+ {\r
+ /* To remove unreferenced local variable warning */\r
+ }\r
+\r
+ #endif /* (CYDEV_ECC_ENABLE == 0) */\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_CANCELED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
/*******************************************************************************\r
* Function Name: CySpcWriteRow\r
********************************************************************************\r
}\r
\r
\r
+/*******************************************************************************\r
+* Function Name: CySpcGetAlgorithm\r
+********************************************************************************\r
+* Summary:\r
+* Downloads SPC algorithm from SPC SROM into SRAM.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* CYRET_STARTED\r
+* CYRET_LOCKED\r
+*\r
+*******************************************************************************/\r
+cystatus CySpcGetAlgorithm(void)\r
+{\r
+ cystatus status = CYRET_STARTED;\r
+\r
+ /* Make sure the SPC is ready to accept command */\r
+ if(CY_SPC_IDLE)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_DWNLD_ALGORITHM);\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_CMD_DWNLD_ALGORITHM;\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
/* [] END OF FILE */\r
+\r
/*******************************************************************************\r
* File Name: CySpc.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides definitions for the System Performance Component API.\r
* application.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\\r
;\r
cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size);\r
+cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\\r
+;\r
cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\\r
;\r
cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber);\r
cystatus CySpcGetTemp(uint8 numSamples);\r
+cystatus CySpcGetAlgorithm(void);\r
cystatus CySpcLock(void);\r
void CySpcUnlock(void);\r
\r
#define CY_SPC_STATUS_CODE_MASK (0xFCu)\r
#define CY_SPC_STATUS_CODE_SHIFT (0x02u)\r
\r
-/* Status codes for the SPC. */\r
+/* Status codes for SPC. */\r
#define CY_SPC_STATUS_SUCCESS (0x00u) /* Operation Successful */\r
#define CY_SPC_STATUS_INVALID_ARRAY_ID (0x01u) /* Invalid Array ID for given command */\r
#define CY_SPC_STATUS_INVALID_2BYTEKEY (0x02u) /* Invalid 2-byte key */\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0\r
+* The following code is OBSOLETE and must not be used.\r
+*\r
+* If the obsoleted macro definitions intended for use in the application use the\r
+* following scheme, redefine your own versions of these definitions:\r
+* #ifdef <OBSOLETED_DEFINE>\r
+* #undef <OBSOLETED_DEFINE>\r
+* #define <OBSOLETED_DEFINE> (<New Value>)\r
+* #endif\r
+*\r
+* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* used in the application and their modification might lead to unexpected\r
+* consequences.\r
*******************************************************************************/\r
#define FIRST_FLASH_ARRAYID (CY_SPC_FIRST_FLASH_ARRAYID)\r
#define LAST_FLASH_ARRAYID (CY_SPC_LAST_FLASH_ARRAYID)\r
/*******************************************************************************
* File Name: Debug_Timer.c
-* Version 2.50
+* Version 2.70
*
* Description:
* The Timer component consists of a 8, 16, 24 or 32-bit timer with
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#endif /* Set Capture Mode for UDB implementation if capture mode is software controlled */
#if (Debug_Timer_SoftwareTriggerMode)
- if (0u == (Debug_Timer_CONTROL & Debug_Timer__B_TIMER__TM_SOFTWARE))
- {
- Debug_Timer_SetTriggerMode(Debug_Timer_INIT_TRIGGER_MODE);
- }
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+ if (0u == (Debug_Timer_CONTROL & Debug_Timer__B_TIMER__TM_SOFTWARE))
+ {
+ Debug_Timer_SetTriggerMode(Debug_Timer_INIT_TRIGGER_MODE);
+ }
+ #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
#endif /* Set trigger mode for UDB Implementation if trigger mode is software controlled */
/* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
#if (Debug_Timer_EnableTriggerMode)
Debug_Timer_EnableTrigger();
#endif /* Set Trigger enable bit for UDB implementation in the control register*/
-
- #if (Debug_Timer_InterruptOnCaptureCount)
- #if (!Debug_Timer_ControlRegRemoved)
- Debug_Timer_SetInterruptCount(Debug_Timer_INIT_INT_CAPTURE_COUNT);
- #endif /* Set interrupt count in control register if control register is not removed */
- #endif /*Set interrupt count in UDB implementation if interrupt count feature is checked.*/
+
+
+ #if (Debug_Timer_InterruptOnCaptureCount && !Debug_Timer_UDB_CONTROL_REG_REMOVED)
+ Debug_Timer_SetInterruptCount(Debug_Timer_INIT_INT_CAPTURE_COUNT);
+ #endif /* Set interrupt count in UDB implementation if interrupt count feature is checked.*/
Debug_Timer_ClearFIFO();
#endif /* Configure additional features of UDB implementation */
#endif /* Set Enable bit for enabling Fixed function timer*/
/* Remove assignment if control register is removed */
- #if (!Debug_Timer_ControlRegRemoved || Debug_Timer_UsingFixedFunction)
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED || Debug_Timer_UsingFixedFunction)
Debug_Timer_CONTROL |= Debug_Timer_CTRL_ENABLE;
#endif /* Remove assignment if control register is removed */
}
void Debug_Timer_Stop(void)
{
/* Disable Timer */
- #if(!Debug_Timer_ControlRegRemoved || Debug_Timer_UsingFixedFunction)
+ #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED || Debug_Timer_UsingFixedFunction)
Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_ENABLE));
#endif /* Remove assignment if control register is removed */
void Debug_Timer_SoftwareCapture(void)
{
/* Generate a software capture by reading the counter register */
- (void)Debug_Timer_COUNTER_LSB;
+ #if(Debug_Timer_UsingFixedFunction)
+ (void)CY_GET_REG16(Debug_Timer_COUNTER_LSB_PTR);
+ #else
+ (void)CY_GET_REG8(Debug_Timer_COUNTER_LSB_PTR_8BIT);
+ #endif/* (Debug_Timer_UsingFixedFunction) */
/* Capture Data is now in the FIFO */
}
}
-#if (!Debug_Timer_ControlRegRemoved) /* Remove API if control register is removed */
+#if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) /* Remove API if control register is unused */
/*******************************************************************************
*******************************************************************************/
uint8 Debug_Timer_ReadControlRegister(void)
{
- return ((uint8)Debug_Timer_CONTROL);
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+ return ((uint8)Debug_Timer_CONTROL);
+ #else
+ return (0);
+ #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
}
*******************************************************************************/
void Debug_Timer_WriteControlRegister(uint8 control)
{
- Debug_Timer_CONTROL = control;
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+ Debug_Timer_CONTROL = control;
+ #else
+ control = 0u;
+ #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
}
-#endif /* Remove API if control register is removed */
+
+#endif /* Remove API if control register is unused */
/*******************************************************************************
* void
*
*******************************************************************************/
-void Debug_Timer_WriteCounter(uint16 counter) \
-
+void Debug_Timer_WriteCounter(uint16 counter)
{
#if(Debug_Timer_UsingFixedFunction)
/* This functionality is removed until a FixedFunction HW update to
*******************************************************************************/
uint16 Debug_Timer_ReadCounter(void)
{
-
/* Force capture by reading Accumulator */
/* Must first do a software capture to be able to read the counter */
/* It is up to the user code to make sure there isn't already captured data in the FIFO */
- (void)Debug_Timer_COUNTER_LSB;
+ #if(Debug_Timer_UsingFixedFunction)
+ (void)CY_GET_REG16(Debug_Timer_COUNTER_LSB_PTR);
+ #else
+ (void)CY_GET_REG8(Debug_Timer_COUNTER_LSB_PTR_8BIT);
+ #endif/* (Debug_Timer_UsingFixedFunction) */
/* Read the data from the FIFO (or capture register for Fixed Function)*/
#if(Debug_Timer_UsingFixedFunction)
#if(!Debug_Timer_UsingFixedFunction) /* UDB Specific Functions */
+
/*******************************************************************************
* The functions below this point are only available using the UDB
* implementation. If a feature is selected, then the API is enabled.
captureMode = ((uint8)((uint8)captureMode << Debug_Timer_CTRL_CAP_MODE_SHIFT));
captureMode &= (Debug_Timer_CTRL_CAP_MODE_MASK);
- /* Clear the Current Setting */
- Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_CAP_MODE_MASK));
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+ /* Clear the Current Setting */
+ Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_CAP_MODE_MASK));
- /* Write The New Setting */
- Debug_Timer_CONTROL |= captureMode;
+ /* Write The New Setting */
+ Debug_Timer_CONTROL |= captureMode;
+ #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
}
#endif /* Remove API if Capture Mode is not Software Controlled */
/* This must only set to two bits of the control register associated */
triggerMode &= Debug_Timer_CTRL_TRIG_MODE_MASK;
- /* Clear the Current Setting */
- Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_MODE_MASK));
-
- /* Write The New Setting */
- Debug_Timer_CONTROL |= (triggerMode | Debug_Timer__B_TIMER__TM_SOFTWARE);
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) /* Remove assignment if control register is removed */
+
+ /* Clear the Current Setting */
+ Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_MODE_MASK));
+ /* Write The New Setting */
+ Debug_Timer_CONTROL |= (triggerMode | Debug_Timer__B_TIMER__TM_SOFTWARE);
+ #endif /* Remove code section if control register is not used */
}
#endif /* Remove API if Trigger Mode is not Software Controlled */
*******************************************************************************/
void Debug_Timer_EnableTrigger(void)
{
- #if (!Debug_Timer_ControlRegRemoved) /* Remove assignment if control register is removed */
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) /* Remove assignment if control register is removed */
Debug_Timer_CONTROL |= Debug_Timer_CTRL_TRIG_EN;
#endif /* Remove code section if control register is not used */
}
*******************************************************************************/
void Debug_Timer_DisableTrigger(void)
{
- #if (!Debug_Timer_ControlRegRemoved) /* Remove assignment if control register is removed */
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED ) /* Remove assignment if control register is removed */
Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_EN));
#endif /* Remove code section if control register is not used */
}
#endif /* Remove API is Trigger Mode is set to None */
-
#if(Debug_Timer_InterruptOnCaptureCount)
-#if (!Debug_Timer_ControlRegRemoved) /* Remove API if control register is removed */
/*******************************************************************************
/* This must only set to two bits of the control register associated */
interruptCount &= Debug_Timer_CTRL_INTCNT_MASK;
- /* Clear the Current Setting */
- Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_INTCNT_MASK));
- /* Write The New Setting */
- Debug_Timer_CONTROL |= interruptCount;
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+ /* Clear the Current Setting */
+ Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_INTCNT_MASK));
+ /* Write The New Setting */
+ Debug_Timer_CONTROL |= interruptCount;
+ #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
}
-#endif /* Remove API if control register is removed */
#endif /* Debug_Timer_InterruptOnCaptureCount */
/*******************************************************************************
* File Name: Debug_Timer.h
-* Version 2.50
+* Version 2.70
*
* Description:
* Contains the function prototypes and constants available to the timer
* None
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
-#if !defined(CY_Timer_v2_30_Debug_Timer_H)
-#define CY_Timer_v2_30_Debug_Timer_H
+#if !defined(CY_Timer_v2_60_Debug_Timer_H)
+#define CY_Timer_v2_60_Debug_Timer_H
#include "cytypes.h"
#include "cyfitter.h"
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
- #error Component Timer_v2_50 requires cy_boot v3.0 or later
+ #error Component Timer_v2_70 requires cy_boot v3.0 or later
#endif /* (CY_ PSOC5LP) */
#define Debug_Timer_RunModeUsed 0u
#define Debug_Timer_ControlRegRemoved 0u
+#if defined(Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG)
+ #define Debug_Timer_UDB_CONTROL_REG_REMOVED (0u)
+#elif (Debug_Timer_UsingFixedFunction)
+ #define Debug_Timer_UDB_CONTROL_REG_REMOVED (0u)
+#else
+ #define Debug_Timer_UDB_CONTROL_REG_REMOVED (1u)
+#endif /* End Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG */
+
/***************************************
* Type defines
{
uint8 TimerEnableState;
#if(!Debug_Timer_UsingFixedFunction)
- #if (CY_UDB_V0)
- uint16 TimerUdb; /* Timer internal counter value */
- uint16 TimerPeriod; /* Timer Period value */
- uint8 InterruptMaskValue; /* Timer Compare Value */
- #if (Debug_Timer_UsingHWCaptureCounter)
- uint8 TimerCaptureCounter; /* Timer Capture Counter Value */
- #endif /* variable declaration for backing up Capture Counter value*/
- #endif /* variables for non retention registers in CY_UDB_V0 */
-
- #if (CY_UDB_V1)
- uint16 TimerUdb;
- uint8 InterruptMaskValue;
- #if (Debug_Timer_UsingHWCaptureCounter)
- uint8 TimerCaptureCounter;
- #endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */
- #endif /* (CY_UDB_V1) */
-
- #if (!Debug_Timer_ControlRegRemoved)
+
+ uint16 TimerUdb;
+ uint8 InterruptMaskValue;
+ #if (Debug_Timer_UsingHWCaptureCounter)
+ uint8 TimerCaptureCounter;
+ #endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */
+
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
uint8 TimerControlRegister;
#endif /* variable declaration for backing up enable state of the Timer */
#endif /* define backup variables only for UDB implementation. Fixed function registers are all retention */
+
}Debug_Timer_backupStruct;
/* Deprecated function. Do not use this in future. Retained for backward compatibility */
#define Debug_Timer_GetInterruptSource() Debug_Timer_ReadStatusRegister()
-#if(!Debug_Timer_ControlRegRemoved)
+#if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
uint8 Debug_Timer_ReadControlRegister(void) ;
- void Debug_Timer_WriteControlRegister(uint8 control) \
- ;
-#endif /* (!Debug_Timer_ControlRegRemoved) */
+ void Debug_Timer_WriteControlRegister(uint8 control) ;
+#endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
uint16 Debug_Timer_ReadPeriod(void) ;
-void Debug_Timer_WritePeriod(uint16 period) \
- ;
+void Debug_Timer_WritePeriod(uint16 period) ;
uint16 Debug_Timer_ReadCounter(void) ;
-void Debug_Timer_WriteCounter(uint16 counter) \
- ;
+void Debug_Timer_WriteCounter(uint16 counter) ;
uint16 Debug_Timer_ReadCapture(void) ;
void Debug_Timer_SoftwareCapture(void) ;
-
#if(!Debug_Timer_UsingFixedFunction) /* UDB Prototypes */
#if (Debug_Timer_SoftwareCaptureMode)
void Debug_Timer_SetCaptureMode(uint8 captureMode) ;
#if (Debug_Timer_SoftwareTriggerMode)
void Debug_Timer_SetTriggerMode(uint8 triggerMode) ;
#endif /* (Debug_Timer_SoftwareTriggerMode) */
+
#if (Debug_Timer_EnableTriggerMode)
void Debug_Timer_EnableTrigger(void) ;
void Debug_Timer_DisableTrigger(void) ;
#endif /* (Debug_Timer_EnableTriggerMode) */
+
#if(Debug_Timer_InterruptOnCaptureCount)
- #if(!Debug_Timer_ControlRegRemoved)
- void Debug_Timer_SetInterruptCount(uint8 interruptCount) \
- ;
- #endif /* (!Debug_Timer_ControlRegRemoved) */
+ void Debug_Timer_SetInterruptCount(uint8 interruptCount) ;
#endif /* (Debug_Timer_InterruptOnCaptureCount) */
#if (Debug_Timer_UsingHWCaptureCounter)
- void Debug_Timer_SetCaptureCount(uint8 captureCount) \
- ;
+ void Debug_Timer_SetCaptureCount(uint8 captureCount) ;
uint8 Debug_Timer_ReadCaptureCount(void) ;
#endif /* (Debug_Timer_UsingHWCaptureCounter) */
#if (CY_PSOC5A)
/* Use CFG1 Mode bits to set run mode */
/* As defined by Verilog Implementation */
- #define Debug_Timer_CTRL_MODE_SHIFT 0x01u
- #define Debug_Timer_CTRL_MODE_MASK ((uint8)((uint8)0x07u << Debug_Timer_CTRL_MODE_SHIFT))
+ #define Debug_Timer_CTRL_MODE_SHIFT 0x01u
+ #define Debug_Timer_CTRL_MODE_MASK ((uint8)((uint8)0x07u << Debug_Timer_CTRL_MODE_SHIFT))
#endif /* (CY_PSOC5A) */
#if (CY_PSOC3 || CY_PSOC5LP)
/* Control3 Register Bit Locations */
#endif /* CY_PSOC3 || CY_PSOC5 */
#endif
+ #define Debug_Timer_COUNTER_LSB_PTR_8BIT ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+
#if (Debug_Timer_UsingHWCaptureCounter)
#define Debug_Timer_CAP_COUNT (*(reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
#define Debug_Timer_CAP_COUNT_PTR ( (reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
/*******************************************************************************
* File Name: Debug_Timer_PM.c
-* Version 2.50
+* Version 2.70
*
* Description:
* This file provides the power management source code to API for the
* None
*
*******************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#include "Debug_Timer.h"
+
static Debug_Timer_backupStruct Debug_Timer_backup;
void Debug_Timer_SaveConfig(void)
{
#if (!Debug_Timer_UsingFixedFunction)
- /* Backup the UDB non-rentention registers for CY_UDB_V0 */
- #if (CY_UDB_V0)
- Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter();
- Debug_Timer_backup.TimerPeriod = Debug_Timer_ReadPeriod();
- Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK;
- #if (Debug_Timer_UsingHWCaptureCounter)
- Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount();
- #endif /* Backup the UDB non-rentention register capture counter for CY_UDB_V0 */
- #endif /* Backup the UDB non-rentention registers for CY_UDB_V0 */
-
- #if (CY_UDB_V1)
- Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter();
- Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK;
- #if (Debug_Timer_UsingHWCaptureCounter)
- Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount();
- #endif /* Back Up capture counter register */
- #endif /* Backup non retention registers, interrupt mask and capture counter for CY_UDB_V1 */
+ Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter();
+ Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK;
+ #if (Debug_Timer_UsingHWCaptureCounter)
+ Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount();
+ #endif /* Back Up capture counter register */
- #if(!Debug_Timer_ControlRegRemoved)
+ #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
Debug_Timer_backup.TimerControlRegister = Debug_Timer_ReadControlRegister();
#endif /* Backup the enable state of the Timer component */
#endif /* Backup non retention registers in UDB implementation. All fixed function registers are retention */
void Debug_Timer_RestoreConfig(void)
{
#if (!Debug_Timer_UsingFixedFunction)
- /* Restore the UDB non-rentention registers for CY_UDB_V0 */
- #if (CY_UDB_V0)
- /* Interrupt State Backup for Critical Region*/
- uint8 Debug_Timer_interruptState;
-
- Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb);
- Debug_Timer_WritePeriod(Debug_Timer_backup.TimerPeriod);
- /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
- /* Enter Critical Region*/
- Debug_Timer_interruptState = CyEnterCriticalSection();
- /* Use the interrupt output of the status register for IRQ output */
- Debug_Timer_STATUS_AUX_CTRL |= Debug_Timer_STATUS_ACTL_INT_EN_MASK;
- /* Exit Critical Region*/
- CyExitCriticalSection(Debug_Timer_interruptState);
- Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue;
- #if (Debug_Timer_UsingHWCaptureCounter)
- Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter);
- #endif /* Restore the UDB non-rentention register capture counter for CY_UDB_V0 */
- #endif /* Restore the UDB non-rentention registers for CY_UDB_V0 */
- #if (CY_UDB_V1)
- Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb);
- Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue;
- #if (Debug_Timer_UsingHWCaptureCounter)
- Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter);
- #endif /* Restore Capture counter register*/
- #endif /* Restore up non retention registers, interrupt mask and capture counter for CY_UDB_V1 */
+ Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb);
+ Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue;
+ #if (Debug_Timer_UsingHWCaptureCounter)
+ Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter);
+ #endif /* Restore Capture counter register*/
- #if(!Debug_Timer_ControlRegRemoved)
+ #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
Debug_Timer_WriteControlRegister(Debug_Timer_backup.TimerControlRegister);
#endif /* Restore the enable state of the Timer component */
#endif /* Restore non retention registers in the UDB implementation only */
*******************************************************************************/
void Debug_Timer_Sleep(void)
{
- #if(!Debug_Timer_ControlRegRemoved)
+ #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
/* Save Counter's enable state */
if(Debug_Timer_CTRL_ENABLE == (Debug_Timer_CONTROL & Debug_Timer_CTRL_ENABLE))
{
void Debug_Timer_Wakeup(void)
{
Debug_Timer_RestoreConfig();
- #if(!Debug_Timer_ControlRegRemoved)
+ #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
if(Debug_Timer_backup.TimerEnableState == 1u)
{ /* Enable Timer's operation */
Debug_Timer_Enable();
/*******************************************************************************\r
* File Name: LED1.c \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
* Change the drive mode on the pins of the port.\r
* \r
* Parameters: \r
-* mode: Change the pins to this drive mode.\r
+* mode: Change the pins to one of the following drive modes.\r
+*\r
+* LED1_DM_STRONG Strong Drive \r
+* LED1_DM_OD_HI Open Drain, Drives High \r
+* LED1_DM_OD_LO Open Drain, Drives Low \r
+* LED1_DM_RES_UP Resistive Pull Up \r
+* LED1_DM_RES_DWN Resistive Pull Down \r
+* LED1_DM_RES_UPDWN Resistive Pull Up/Down \r
+* LED1_DM_DIG_HIZ High Impedance Digital \r
+* LED1_DM_ALG_HIZ High Impedance Analog \r
*\r
* Return: \r
* None\r
/*******************************************************************************\r
* File Name: LED1.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/* Check to see if required defines such as CY_PSOC5A are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
#endif /* (CY_PSOC5A) */\r
\r
/* APIs are not generated for P15[7:6] */\r
/*******************************************************************************\r
* File Name: LED1.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/***************************************\r
* Constants \r
***************************************/\r
-#define LED1_0 LED1__0__PC\r
+#define LED1_0 (LED1__0__PC)\r
\r
#endif /* End Pins LED1_ALIASES_H */\r
\r
/*******************************************************************************
* File Name: SCSI_CLK.c
-* Version 2.10
+* Version 2.20
*
* Description:
* This file provides the source code to the API for the clock component.
/*******************************************************************************
* File Name: SCSI_CLK.h
-* Version 2.10
+* Version 2.20
*
* Description:
* Provides the function and constant definitions for the clock component.
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
- #error Component cy_clock_v2_10 requires cy_boot v3.0 or later
+ #error Component cy_clock_v2_20 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5LP) */
/*******************************************************************************\r
* File Name: SCSI_In_DBx.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SCSI_In_DBx_0 SCSI_In_DBx__0__PC\r
-#define SCSI_In_DBx_1 SCSI_In_DBx__1__PC\r
-#define SCSI_In_DBx_2 SCSI_In_DBx__2__PC\r
-#define SCSI_In_DBx_3 SCSI_In_DBx__3__PC\r
-#define SCSI_In_DBx_4 SCSI_In_DBx__4__PC\r
-#define SCSI_In_DBx_5 SCSI_In_DBx__5__PC\r
-#define SCSI_In_DBx_6 SCSI_In_DBx__6__PC\r
-#define SCSI_In_DBx_7 SCSI_In_DBx__7__PC\r
-\r
-#define SCSI_In_DBx_DB0 SCSI_In_DBx__DB0__PC\r
-#define SCSI_In_DBx_DB1 SCSI_In_DBx__DB1__PC\r
-#define SCSI_In_DBx_DB2 SCSI_In_DBx__DB2__PC\r
-#define SCSI_In_DBx_DB3 SCSI_In_DBx__DB3__PC\r
-#define SCSI_In_DBx_DB4 SCSI_In_DBx__DB4__PC\r
-#define SCSI_In_DBx_DB5 SCSI_In_DBx__DB5__PC\r
-#define SCSI_In_DBx_DB6 SCSI_In_DBx__DB6__PC\r
-#define SCSI_In_DBx_DB7 SCSI_In_DBx__DB7__PC\r
+#define SCSI_In_DBx_0 (SCSI_In_DBx__0__PC)\r
+#define SCSI_In_DBx_1 (SCSI_In_DBx__1__PC)\r
+#define SCSI_In_DBx_2 (SCSI_In_DBx__2__PC)\r
+#define SCSI_In_DBx_3 (SCSI_In_DBx__3__PC)\r
+#define SCSI_In_DBx_4 (SCSI_In_DBx__4__PC)\r
+#define SCSI_In_DBx_5 (SCSI_In_DBx__5__PC)\r
+#define SCSI_In_DBx_6 (SCSI_In_DBx__6__PC)\r
+#define SCSI_In_DBx_7 (SCSI_In_DBx__7__PC)\r
+\r
+#define SCSI_In_DBx_DB0 (SCSI_In_DBx__DB0__PC)\r
+#define SCSI_In_DBx_DB1 (SCSI_In_DBx__DB1__PC)\r
+#define SCSI_In_DBx_DB2 (SCSI_In_DBx__DB2__PC)\r
+#define SCSI_In_DBx_DB3 (SCSI_In_DBx__DB3__PC)\r
+#define SCSI_In_DBx_DB4 (SCSI_In_DBx__DB4__PC)\r
+#define SCSI_In_DBx_DB5 (SCSI_In_DBx__DB5__PC)\r
+#define SCSI_In_DBx_DB6 (SCSI_In_DBx__DB6__PC)\r
+#define SCSI_In_DBx_DB7 (SCSI_In_DBx__DB7__PC)\r
\r
#endif /* End Pins SCSI_In_DBx_ALIASES_H */\r
\r
/*******************************************************************************\r
* File Name: SCSI_In.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SCSI_In_0 SCSI_In__0__PC\r
-#define SCSI_In_1 SCSI_In__1__PC\r
-#define SCSI_In_2 SCSI_In__2__PC\r
-#define SCSI_In_3 SCSI_In__3__PC\r
-#define SCSI_In_4 SCSI_In__4__PC\r
-\r
-#define SCSI_In_DBP SCSI_In__DBP__PC\r
-#define SCSI_In_MSG SCSI_In__MSG__PC\r
-#define SCSI_In_CD SCSI_In__CD__PC\r
-#define SCSI_In_REQ SCSI_In__REQ__PC\r
-#define SCSI_In_IO SCSI_In__IO__PC\r
+#define SCSI_In_0 (SCSI_In__0__PC)\r
+#define SCSI_In_1 (SCSI_In__1__PC)\r
+#define SCSI_In_2 (SCSI_In__2__PC)\r
+#define SCSI_In_3 (SCSI_In__3__PC)\r
+#define SCSI_In_4 (SCSI_In__4__PC)\r
+\r
+#define SCSI_In_DBP (SCSI_In__DBP__PC)\r
+#define SCSI_In_MSG (SCSI_In__MSG__PC)\r
+#define SCSI_In_CD (SCSI_In__CD__PC)\r
+#define SCSI_In_REQ (SCSI_In__REQ__PC)\r
+#define SCSI_In_IO (SCSI_In__IO__PC)\r
\r
#endif /* End Pins SCSI_In_ALIASES_H */\r
\r
/*******************************************************************************
* File Name: SCSI_Noise.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define SCSI_Noise_0 SCSI_Noise__0__PC
-#define SCSI_Noise_1 SCSI_Noise__1__PC
-#define SCSI_Noise_2 SCSI_Noise__2__PC
-#define SCSI_Noise_3 SCSI_Noise__3__PC
-#define SCSI_Noise_4 SCSI_Noise__4__PC
-
-#define SCSI_Noise_ATN SCSI_Noise__ATN__PC
-#define SCSI_Noise_BSY SCSI_Noise__BSY__PC
-#define SCSI_Noise_SEL SCSI_Noise__SEL__PC
-#define SCSI_Noise_RST SCSI_Noise__RST__PC
-#define SCSI_Noise_ACK SCSI_Noise__ACK__PC
+#define SCSI_Noise_0 (SCSI_Noise__0__PC)
+#define SCSI_Noise_1 (SCSI_Noise__1__PC)
+#define SCSI_Noise_2 (SCSI_Noise__2__PC)
+#define SCSI_Noise_3 (SCSI_Noise__3__PC)
+#define SCSI_Noise_4 (SCSI_Noise__4__PC)
+
+#define SCSI_Noise_ATN (SCSI_Noise__ATN__PC)
+#define SCSI_Noise_BSY (SCSI_Noise__BSY__PC)
+#define SCSI_Noise_SEL (SCSI_Noise__SEL__PC)
+#define SCSI_Noise_RST (SCSI_Noise__RST__PC)
+#define SCSI_Noise_ACK (SCSI_Noise__ACK__PC)
#endif /* End Pins SCSI_Noise_ALIASES_H */
/*******************************************************************************\r
* File Name: SCSI_Out_DBx.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SCSI_Out_DBx_0 SCSI_Out_DBx__0__PC\r
-#define SCSI_Out_DBx_1 SCSI_Out_DBx__1__PC\r
-#define SCSI_Out_DBx_2 SCSI_Out_DBx__2__PC\r
-#define SCSI_Out_DBx_3 SCSI_Out_DBx__3__PC\r
-#define SCSI_Out_DBx_4 SCSI_Out_DBx__4__PC\r
-#define SCSI_Out_DBx_5 SCSI_Out_DBx__5__PC\r
-#define SCSI_Out_DBx_6 SCSI_Out_DBx__6__PC\r
-#define SCSI_Out_DBx_7 SCSI_Out_DBx__7__PC\r
-\r
-#define SCSI_Out_DBx_DB0 SCSI_Out_DBx__DB0__PC\r
-#define SCSI_Out_DBx_DB1 SCSI_Out_DBx__DB1__PC\r
-#define SCSI_Out_DBx_DB2 SCSI_Out_DBx__DB2__PC\r
-#define SCSI_Out_DBx_DB3 SCSI_Out_DBx__DB3__PC\r
-#define SCSI_Out_DBx_DB4 SCSI_Out_DBx__DB4__PC\r
-#define SCSI_Out_DBx_DB5 SCSI_Out_DBx__DB5__PC\r
-#define SCSI_Out_DBx_DB6 SCSI_Out_DBx__DB6__PC\r
-#define SCSI_Out_DBx_DB7 SCSI_Out_DBx__DB7__PC\r
+#define SCSI_Out_DBx_0 (SCSI_Out_DBx__0__PC)\r
+#define SCSI_Out_DBx_1 (SCSI_Out_DBx__1__PC)\r
+#define SCSI_Out_DBx_2 (SCSI_Out_DBx__2__PC)\r
+#define SCSI_Out_DBx_3 (SCSI_Out_DBx__3__PC)\r
+#define SCSI_Out_DBx_4 (SCSI_Out_DBx__4__PC)\r
+#define SCSI_Out_DBx_5 (SCSI_Out_DBx__5__PC)\r
+#define SCSI_Out_DBx_6 (SCSI_Out_DBx__6__PC)\r
+#define SCSI_Out_DBx_7 (SCSI_Out_DBx__7__PC)\r
+\r
+#define SCSI_Out_DBx_DB0 (SCSI_Out_DBx__DB0__PC)\r
+#define SCSI_Out_DBx_DB1 (SCSI_Out_DBx__DB1__PC)\r
+#define SCSI_Out_DBx_DB2 (SCSI_Out_DBx__DB2__PC)\r
+#define SCSI_Out_DBx_DB3 (SCSI_Out_DBx__DB3__PC)\r
+#define SCSI_Out_DBx_DB4 (SCSI_Out_DBx__DB4__PC)\r
+#define SCSI_Out_DBx_DB5 (SCSI_Out_DBx__DB5__PC)\r
+#define SCSI_Out_DBx_DB6 (SCSI_Out_DBx__DB6__PC)\r
+#define SCSI_Out_DBx_DB7 (SCSI_Out_DBx__DB7__PC)\r
\r
#endif /* End Pins SCSI_Out_DBx_ALIASES_H */\r
\r
/*******************************************************************************\r
* File Name: SCSI_Out.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SCSI_Out_0 SCSI_Out__0__PC\r
-#define SCSI_Out_1 SCSI_Out__1__PC\r
-#define SCSI_Out_2 SCSI_Out__2__PC\r
-#define SCSI_Out_3 SCSI_Out__3__PC\r
-#define SCSI_Out_4 SCSI_Out__4__PC\r
-#define SCSI_Out_5 SCSI_Out__5__PC\r
-#define SCSI_Out_6 SCSI_Out__6__PC\r
-#define SCSI_Out_7 SCSI_Out__7__PC\r
-#define SCSI_Out_8 SCSI_Out__8__PC\r
-#define SCSI_Out_9 SCSI_Out__9__PC\r
-\r
-#define SCSI_Out_DBP_raw SCSI_Out__DBP_raw__PC\r
-#define SCSI_Out_ATN SCSI_Out__ATN__PC\r
-#define SCSI_Out_BSY SCSI_Out__BSY__PC\r
-#define SCSI_Out_ACK SCSI_Out__ACK__PC\r
-#define SCSI_Out_RST SCSI_Out__RST__PC\r
-#define SCSI_Out_MSG_raw SCSI_Out__MSG_raw__PC\r
-#define SCSI_Out_SEL SCSI_Out__SEL__PC\r
-#define SCSI_Out_CD_raw SCSI_Out__CD_raw__PC\r
-#define SCSI_Out_REQ SCSI_Out__REQ__PC\r
-#define SCSI_Out_IO_raw SCSI_Out__IO_raw__PC\r
+#define SCSI_Out_0 (SCSI_Out__0__PC)\r
+#define SCSI_Out_1 (SCSI_Out__1__PC)\r
+#define SCSI_Out_2 (SCSI_Out__2__PC)\r
+#define SCSI_Out_3 (SCSI_Out__3__PC)\r
+#define SCSI_Out_4 (SCSI_Out__4__PC)\r
+#define SCSI_Out_5 (SCSI_Out__5__PC)\r
+#define SCSI_Out_6 (SCSI_Out__6__PC)\r
+#define SCSI_Out_7 (SCSI_Out__7__PC)\r
+#define SCSI_Out_8 (SCSI_Out__8__PC)\r
+#define SCSI_Out_9 (SCSI_Out__9__PC)\r
+\r
+#define SCSI_Out_DBP_raw (SCSI_Out__DBP_raw__PC)\r
+#define SCSI_Out_ATN (SCSI_Out__ATN__PC)\r
+#define SCSI_Out_BSY (SCSI_Out__BSY__PC)\r
+#define SCSI_Out_ACK (SCSI_Out__ACK__PC)\r
+#define SCSI_Out_RST (SCSI_Out__RST__PC)\r
+#define SCSI_Out_MSG_raw (SCSI_Out__MSG_raw__PC)\r
+#define SCSI_Out_SEL (SCSI_Out__SEL__PC)\r
+#define SCSI_Out_CD_raw (SCSI_Out__CD_raw__PC)\r
+#define SCSI_Out_REQ (SCSI_Out__REQ__PC)\r
+#define SCSI_Out_IO_raw (SCSI_Out__IO_raw__PC)\r
\r
#endif /* End Pins SCSI_Out_ALIASES_H */\r
\r
/*******************************************************************************\r
* File Name: SD_CD.c \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
* Change the drive mode on the pins of the port.\r
* \r
* Parameters: \r
-* mode: Change the pins to this drive mode.\r
+* mode: Change the pins to one of the following drive modes.\r
+*\r
+* SD_CD_DM_STRONG Strong Drive \r
+* SD_CD_DM_OD_HI Open Drain, Drives High \r
+* SD_CD_DM_OD_LO Open Drain, Drives Low \r
+* SD_CD_DM_RES_UP Resistive Pull Up \r
+* SD_CD_DM_RES_DWN Resistive Pull Down \r
+* SD_CD_DM_RES_UPDWN Resistive Pull Up/Down \r
+* SD_CD_DM_DIG_HIZ High Impedance Digital \r
+* SD_CD_DM_ALG_HIZ High Impedance Analog \r
*\r
* Return: \r
* None\r
/*******************************************************************************\r
* File Name: SD_CD.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/* Check to see if required defines such as CY_PSOC5A are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
#endif /* (CY_PSOC5A) */\r
\r
/* APIs are not generated for P15[7:6] */\r
/*******************************************************************************\r
* File Name: SD_CD.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SD_CD_0 SD_CD__0__PC\r
+#define SD_CD_0 (SD_CD__0__PC)\r
\r
#endif /* End Pins SD_CD_ALIASES_H */\r
\r
/*******************************************************************************\r
* File Name: SD_CS.c \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
* Change the drive mode on the pins of the port.\r
* \r
* Parameters: \r
-* mode: Change the pins to this drive mode.\r
+* mode: Change the pins to one of the following drive modes.\r
+*\r
+* SD_CS_DM_STRONG Strong Drive \r
+* SD_CS_DM_OD_HI Open Drain, Drives High \r
+* SD_CS_DM_OD_LO Open Drain, Drives Low \r
+* SD_CS_DM_RES_UP Resistive Pull Up \r
+* SD_CS_DM_RES_DWN Resistive Pull Down \r
+* SD_CS_DM_RES_UPDWN Resistive Pull Up/Down \r
+* SD_CS_DM_DIG_HIZ High Impedance Digital \r
+* SD_CS_DM_ALG_HIZ High Impedance Analog \r
*\r
* Return: \r
* None\r
/*******************************************************************************\r
* File Name: SD_CS.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/* Check to see if required defines such as CY_PSOC5A are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
#endif /* (CY_PSOC5A) */\r
\r
/* APIs are not generated for P15[7:6] */\r
/*******************************************************************************\r
* File Name: SD_CS.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SD_CS_0 SD_CS__0__PC\r
+#define SD_CS_0 (SD_CS__0__PC)\r
\r
#endif /* End Pins SD_CS_ALIASES_H */\r
\r
/*******************************************************************************\r
* File Name: SD_DAT1.c \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
* Change the drive mode on the pins of the port.\r
* \r
* Parameters: \r
-* mode: Change the pins to this drive mode.\r
+* mode: Change the pins to one of the following drive modes.\r
+*\r
+* SD_DAT1_DM_STRONG Strong Drive \r
+* SD_DAT1_DM_OD_HI Open Drain, Drives High \r
+* SD_DAT1_DM_OD_LO Open Drain, Drives Low \r
+* SD_DAT1_DM_RES_UP Resistive Pull Up \r
+* SD_DAT1_DM_RES_DWN Resistive Pull Down \r
+* SD_DAT1_DM_RES_UPDWN Resistive Pull Up/Down \r
+* SD_DAT1_DM_DIG_HIZ High Impedance Digital \r
+* SD_DAT1_DM_ALG_HIZ High Impedance Analog \r
*\r
* Return: \r
* None\r
/*******************************************************************************\r
* File Name: SD_DAT1.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/* Check to see if required defines such as CY_PSOC5A are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
#endif /* (CY_PSOC5A) */\r
\r
/* APIs are not generated for P15[7:6] */\r
/*******************************************************************************\r
* File Name: SD_DAT1.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SD_DAT1_0 SD_DAT1__0__PC\r
+#define SD_DAT1_0 (SD_DAT1__0__PC)\r
\r
#endif /* End Pins SD_DAT1_ALIASES_H */\r
\r
/*******************************************************************************\r
* File Name: SD_DAT2.c \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
* Change the drive mode on the pins of the port.\r
* \r
* Parameters: \r
-* mode: Change the pins to this drive mode.\r
+* mode: Change the pins to one of the following drive modes.\r
+*\r
+* SD_DAT2_DM_STRONG Strong Drive \r
+* SD_DAT2_DM_OD_HI Open Drain, Drives High \r
+* SD_DAT2_DM_OD_LO Open Drain, Drives Low \r
+* SD_DAT2_DM_RES_UP Resistive Pull Up \r
+* SD_DAT2_DM_RES_DWN Resistive Pull Down \r
+* SD_DAT2_DM_RES_UPDWN Resistive Pull Up/Down \r
+* SD_DAT2_DM_DIG_HIZ High Impedance Digital \r
+* SD_DAT2_DM_ALG_HIZ High Impedance Analog \r
*\r
* Return: \r
* None\r
/*******************************************************************************\r
* File Name: SD_DAT2.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/* Check to see if required defines such as CY_PSOC5A are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
#endif /* (CY_PSOC5A) */\r
\r
/* APIs are not generated for P15[7:6] */\r
/*******************************************************************************\r
* File Name: SD_DAT2.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SD_DAT2_0 SD_DAT2__0__PC\r
+#define SD_DAT2_0 (SD_DAT2__0__PC)\r
\r
#endif /* End Pins SD_DAT2_ALIASES_H */\r
\r
/*******************************************************************************\r
* File Name: SD_Data_Clk.c\r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* This file provides the source code to the API for the clock component.\r
/*******************************************************************************\r
* File Name: SD_Data_Clk.h\r
-* Version 2.10\r
+* Version 2.20\r
*\r
* Description:\r
* Provides the function and constant definitions for the clock component.\r
/* Check to see if required defines such as CY_PSOC5LP are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5LP)\r
- #error Component cy_clock_v2_10 requires cy_boot v3.0 or later\r
+ #error Component cy_clock_v2_20 requires cy_boot v3.0 or later\r
#endif /* (CY_PSOC5LP) */\r
\r
\r
/*******************************************************************************\r
* File Name: SD_MISO.c \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
* Change the drive mode on the pins of the port.\r
* \r
* Parameters: \r
-* mode: Change the pins to this drive mode.\r
+* mode: Change the pins to one of the following drive modes.\r
+*\r
+* SD_MISO_DM_STRONG Strong Drive \r
+* SD_MISO_DM_OD_HI Open Drain, Drives High \r
+* SD_MISO_DM_OD_LO Open Drain, Drives Low \r
+* SD_MISO_DM_RES_UP Resistive Pull Up \r
+* SD_MISO_DM_RES_DWN Resistive Pull Down \r
+* SD_MISO_DM_RES_UPDWN Resistive Pull Up/Down \r
+* SD_MISO_DM_DIG_HIZ High Impedance Digital \r
+* SD_MISO_DM_ALG_HIZ High Impedance Analog \r
*\r
* Return: \r
* None\r
/*******************************************************************************\r
* File Name: SD_MISO.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/* Check to see if required defines such as CY_PSOC5A are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
#endif /* (CY_PSOC5A) */\r
\r
/* APIs are not generated for P15[7:6] */\r
/*******************************************************************************\r
* File Name: SD_MISO.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SD_MISO_0 SD_MISO__0__PC\r
+#define SD_MISO_0 (SD_MISO__0__PC)\r
\r
#endif /* End Pins SD_MISO_ALIASES_H */\r
\r
/*******************************************************************************\r
* File Name: SD_MOSI.c \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
* Change the drive mode on the pins of the port.\r
* \r
* Parameters: \r
-* mode: Change the pins to this drive mode.\r
+* mode: Change the pins to one of the following drive modes.\r
+*\r
+* SD_MOSI_DM_STRONG Strong Drive \r
+* SD_MOSI_DM_OD_HI Open Drain, Drives High \r
+* SD_MOSI_DM_OD_LO Open Drain, Drives Low \r
+* SD_MOSI_DM_RES_UP Resistive Pull Up \r
+* SD_MOSI_DM_RES_DWN Resistive Pull Down \r
+* SD_MOSI_DM_RES_UPDWN Resistive Pull Up/Down \r
+* SD_MOSI_DM_DIG_HIZ High Impedance Digital \r
+* SD_MOSI_DM_ALG_HIZ High Impedance Analog \r
*\r
* Return: \r
* None\r
/*******************************************************************************\r
* File Name: SD_MOSI.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/* Check to see if required defines such as CY_PSOC5A are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
#endif /* (CY_PSOC5A) */\r
\r
/* APIs are not generated for P15[7:6] */\r
/*******************************************************************************\r
* File Name: SD_MOSI.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SD_MOSI_0 SD_MOSI__0__PC\r
+#define SD_MOSI_0 (SD_MOSI__0__PC)\r
\r
#endif /* End Pins SD_MOSI_ALIASES_H */\r
\r
/*******************************************************************************\r
* File Name: SD_SCK.c \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
* Change the drive mode on the pins of the port.\r
* \r
* Parameters: \r
-* mode: Change the pins to this drive mode.\r
+* mode: Change the pins to one of the following drive modes.\r
+*\r
+* SD_SCK_DM_STRONG Strong Drive \r
+* SD_SCK_DM_OD_HI Open Drain, Drives High \r
+* SD_SCK_DM_OD_LO Open Drain, Drives Low \r
+* SD_SCK_DM_RES_UP Resistive Pull Up \r
+* SD_SCK_DM_RES_DWN Resistive Pull Down \r
+* SD_SCK_DM_RES_UPDWN Resistive Pull Up/Down \r
+* SD_SCK_DM_DIG_HIZ High Impedance Digital \r
+* SD_SCK_DM_ALG_HIZ High Impedance Analog \r
*\r
* Return: \r
* None\r
/*******************************************************************************\r
* File Name: SD_SCK.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/* Check to see if required defines such as CY_PSOC5A are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
#endif /* (CY_PSOC5A) */\r
\r
/* APIs are not generated for P15[7:6] */\r
/*******************************************************************************\r
* File Name: SD_SCK.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SD_SCK_0 SD_SCK__0__PC\r
+#define SD_SCK_0 (SD_SCK__0__PC)\r
\r
#endif /* End Pins SD_SCK_ALIASES_H */\r
\r
/*******************************************************************************\r
* File Name: USBFS.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* API for USBFS Component.\r
* registers are indexed by variations of epNumber - 1.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#include "USBFS_hid.h"\r
#if(USBFS_DMA1_REMOVE == 0u)\r
#include "USBFS_ep1_dma.h"\r
-#endif /* End USBFS_DMA1_REMOVE */\r
+#endif /* USBFS_DMA1_REMOVE */\r
#if(USBFS_DMA2_REMOVE == 0u)\r
#include "USBFS_ep2_dma.h"\r
-#endif /* End USBFS_DMA2_REMOVE */\r
+#endif /* USBFS_DMA2_REMOVE */\r
#if(USBFS_DMA3_REMOVE == 0u)\r
#include "USBFS_ep3_dma.h"\r
-#endif /* End USBFS_DMA3_REMOVE */\r
+#endif /* USBFS_DMA3_REMOVE */\r
#if(USBFS_DMA4_REMOVE == 0u)\r
#include "USBFS_ep4_dma.h"\r
-#endif /* End USBFS_DMA4_REMOVE */\r
+#endif /* USBFS_DMA4_REMOVE */\r
#if(USBFS_DMA5_REMOVE == 0u)\r
#include "USBFS_ep5_dma.h"\r
-#endif /* End USBFS_DMA5_REMOVE */\r
+#endif /* USBFS_DMA5_REMOVE */\r
#if(USBFS_DMA6_REMOVE == 0u)\r
#include "USBFS_ep6_dma.h"\r
-#endif /* End USBFS_DMA6_REMOVE */\r
+#endif /* USBFS_DMA6_REMOVE */\r
#if(USBFS_DMA7_REMOVE == 0u)\r
#include "USBFS_ep7_dma.h"\r
-#endif /* End USBFS_DMA7_REMOVE */\r
+#endif /* USBFS_DMA7_REMOVE */\r
#if(USBFS_DMA8_REMOVE == 0u)\r
#include "USBFS_ep8_dma.h"\r
-#endif /* End USBFS_DMA8_REMOVE */\r
+#endif /* USBFS_DMA8_REMOVE */\r
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ #include "USBFS_EP_DMA_Done_isr.h"\r
+ #include "USBFS_EP8_DMA_Done_SR.h"\r
+ #include "USBFS_EP17_DMA_Done_SR.h"\r
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
\r
\r
/***************************************\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
uint8 USBFS_DmaChan[USBFS_MAX_EP];\r
uint8 USBFS_DmaTd[USBFS_MAX_EP];\r
-#endif /* End USBFS_EP_MM */\r
+#endif /* USBFS_EP_MM */\r
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ static uint8 clearInDataRdyStatus = USBFS_ARB_EPX_CFG_DEFAULT;\r
+ uint8 USBFS_DmaNextTd[USBFS_MAX_EP];\r
+ const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP] =\r
+ { 0u,\r
+ USBFS_ep1_TD_TERMOUT_EN,\r
+ USBFS_ep2_TD_TERMOUT_EN,\r
+ USBFS_ep3_TD_TERMOUT_EN,\r
+ USBFS_ep4_TD_TERMOUT_EN,\r
+ USBFS_ep5_TD_TERMOUT_EN,\r
+ USBFS_ep6_TD_TERMOUT_EN,\r
+ USBFS_ep7_TD_TERMOUT_EN,\r
+ USBFS_ep8_TD_TERMOUT_EN\r
+ };\r
+ volatile uint16 USBFS_inLength[USBFS_MAX_EP];\r
+ const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];\r
+ volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];\r
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
\r
\r
/*******************************************************************************\r
uint8 enableInterrupts;\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
uint16 i;\r
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
enableInterrupts = CyEnterCriticalSection();\r
\r
for (i = 0u; i < USBFS_MAX_EP; i++)\r
{\r
USBFS_DmaTd[i] = DMA_INVALID_TD;\r
+ #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ USBFS_DmaNextTd[i] = DMA_INVALID_TD;\r
+ #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
}\r
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
CyExitCriticalSection(enableInterrupts);\r
\r
#if(USBFS_SOF_ISR_REMOVE == 0u)\r
(void) CyIntSetVector(USBFS_SOF_VECT_NUM, &USBFS_SOF_ISR);\r
CyIntSetPriority(USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR);\r
- #endif /* End USBFS_SOF_ISR_REMOVE */\r
+ #endif /* USBFS_SOF_ISR_REMOVE */\r
\r
/* Set the Control Endpoint Interrupt. */\r
(void) CyIntSetVector(USBFS_EP_0_VECT_NUM, &USBFS_EP_0_ISR);\r
#if(USBFS_EP1_ISR_REMOVE == 0u)\r
(void) CyIntSetVector(USBFS_EP_1_VECT_NUM, &USBFS_EP_1_ISR);\r
CyIntSetPriority(USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR);\r
- #endif /* End USBFS_EP1_ISR_REMOVE */\r
+ #endif /* USBFS_EP1_ISR_REMOVE */\r
\r
/* Set the Data Endpoint 2 Interrupt. */\r
#if(USBFS_EP2_ISR_REMOVE == 0u)\r
(void) CyIntSetVector(USBFS_EP_2_VECT_NUM, &USBFS_EP_2_ISR);\r
CyIntSetPriority(USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR);\r
- #endif /* End USBFS_EP2_ISR_REMOVE */\r
+ #endif /* USBFS_EP2_ISR_REMOVE */\r
\r
/* Set the Data Endpoint 3 Interrupt. */\r
#if(USBFS_EP3_ISR_REMOVE == 0u)\r
(void) CyIntSetVector(USBFS_EP_3_VECT_NUM, &USBFS_EP_3_ISR);\r
CyIntSetPriority(USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR);\r
- #endif /* End USBFS_EP3_ISR_REMOVE */\r
+ #endif /* USBFS_EP3_ISR_REMOVE */\r
\r
/* Set the Data Endpoint 4 Interrupt. */\r
#if(USBFS_EP4_ISR_REMOVE == 0u)\r
(void) CyIntSetVector(USBFS_EP_4_VECT_NUM, &USBFS_EP_4_ISR);\r
CyIntSetPriority(USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR);\r
- #endif /* End USBFS_EP4_ISR_REMOVE */\r
+ #endif /* USBFS_EP4_ISR_REMOVE */\r
\r
/* Set the Data Endpoint 5 Interrupt. */\r
#if(USBFS_EP5_ISR_REMOVE == 0u)\r
(void) CyIntSetVector(USBFS_EP_5_VECT_NUM, &USBFS_EP_5_ISR);\r
CyIntSetPriority(USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR);\r
- #endif /* End USBFS_EP5_ISR_REMOVE */\r
+ #endif /* USBFS_EP5_ISR_REMOVE */\r
\r
/* Set the Data Endpoint 6 Interrupt. */\r
#if(USBFS_EP6_ISR_REMOVE == 0u)\r
(void) CyIntSetVector(USBFS_EP_6_VECT_NUM, &USBFS_EP_6_ISR);\r
CyIntSetPriority(USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR);\r
- #endif /* End USBFS_EP6_ISR_REMOVE */\r
+ #endif /* USBFS_EP6_ISR_REMOVE */\r
\r
/* Set the Data Endpoint 7 Interrupt. */\r
#if(USBFS_EP7_ISR_REMOVE == 0u)\r
(void) CyIntSetVector(USBFS_EP_7_VECT_NUM, &USBFS_EP_7_ISR);\r
CyIntSetPriority(USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR);\r
- #endif /* End USBFS_EP7_ISR_REMOVE */\r
+ #endif /* USBFS_EP7_ISR_REMOVE */\r
\r
/* Set the Data Endpoint 8 Interrupt. */\r
#if(USBFS_EP8_ISR_REMOVE == 0u)\r
(void) CyIntSetVector(USBFS_EP_8_VECT_NUM, &USBFS_EP_8_ISR);\r
CyIntSetPriority(USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR);\r
- #endif /* End USBFS_EP8_ISR_REMOVE */\r
+ #endif /* USBFS_EP8_ISR_REMOVE */\r
\r
#if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))\r
/* Set the ARB Interrupt. */\r
(void) CyIntSetVector(USBFS_ARB_VECT_NUM, &USBFS_ARB_ISR);\r
CyIntSetPriority(USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR);\r
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
}\r
\r
CyIntEnable(USBFS_EP_0_VECT_NUM);\r
#if(USBFS_EP1_ISR_REMOVE == 0u)\r
CyIntEnable(USBFS_EP_1_VECT_NUM);\r
- #endif /* End USBFS_EP1_ISR_REMOVE */\r
+ #endif /* USBFS_EP1_ISR_REMOVE */\r
#if(USBFS_EP2_ISR_REMOVE == 0u)\r
CyIntEnable(USBFS_EP_2_VECT_NUM);\r
- #endif /* End USBFS_EP2_ISR_REMOVE */\r
+ #endif /* USBFS_EP2_ISR_REMOVE */\r
#if(USBFS_EP3_ISR_REMOVE == 0u)\r
CyIntEnable(USBFS_EP_3_VECT_NUM);\r
- #endif /* End USBFS_EP3_ISR_REMOVE */\r
+ #endif /* USBFS_EP3_ISR_REMOVE */\r
#if(USBFS_EP4_ISR_REMOVE == 0u)\r
CyIntEnable(USBFS_EP_4_VECT_NUM);\r
- #endif /* End USBFS_EP4_ISR_REMOVE */\r
+ #endif /* USBFS_EP4_ISR_REMOVE */\r
#if(USBFS_EP5_ISR_REMOVE == 0u)\r
CyIntEnable(USBFS_EP_5_VECT_NUM);\r
- #endif /* End USBFS_EP5_ISR_REMOVE */\r
+ #endif /* USBFS_EP5_ISR_REMOVE */\r
#if(USBFS_EP6_ISR_REMOVE == 0u)\r
CyIntEnable(USBFS_EP_6_VECT_NUM);\r
- #endif /* End USBFS_EP6_ISR_REMOVE */\r
+ #endif /* USBFS_EP6_ISR_REMOVE */\r
#if(USBFS_EP7_ISR_REMOVE == 0u)\r
CyIntEnable(USBFS_EP_7_VECT_NUM);\r
- #endif /* End USBFS_EP7_ISR_REMOVE */\r
+ #endif /* USBFS_EP7_ISR_REMOVE */\r
#if(USBFS_EP8_ISR_REMOVE == 0u)\r
CyIntEnable(USBFS_EP_8_VECT_NUM);\r
- #endif /* End USBFS_EP8_ISR_REMOVE */\r
+ #endif /* USBFS_EP8_ISR_REMOVE */\r
#if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))\r
/* usb arb interrupt enable */\r
USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;\r
CyIntEnable(USBFS_ARB_VECT_NUM);\r
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
/* Arbiter configuration for DMA transfers */\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
-\r
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
/*Set cfg cmplt this rises DMA request when the full configuration is done */\r
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #if(USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ /* Init interrupt which handles verification of the successful DMA transaction */\r
+ USBFS_EP_DMA_Done_isr_StartEx(&USBFS_EP_DMA_DONE_ISR);\r
+ USBFS_EP17_DMA_Done_SR_InterruptEnable();\r
+ USBFS_EP8_DMA_Done_SR_InterruptEnable();\r
+ #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
USBFS_transferState = USBFS_TRANS_STATE_IDLE;\r
\r
USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;\r
#else\r
USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE;\r
- #endif /* End USBFS_VDDD_MV < USBFS_3500MV */\r
+ #endif /* USBFS_VDDD_MV < USBFS_3500MV */\r
break;\r
}\r
\r
\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */\r
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
/* Disable the SIE */\r
USBFS_CR0_REG &= (uint8)(~USBFS_CR0_ENABLE);\r
CyIntDisable(USBFS_EP_0_VECT_NUM);\r
#if(USBFS_EP1_ISR_REMOVE == 0u)\r
CyIntDisable(USBFS_EP_1_VECT_NUM);\r
- #endif /* End USBFS_EP1_ISR_REMOVE */\r
+ #endif /* USBFS_EP1_ISR_REMOVE */\r
#if(USBFS_EP2_ISR_REMOVE == 0u)\r
CyIntDisable(USBFS_EP_2_VECT_NUM);\r
- #endif /* End USBFS_EP2_ISR_REMOVE */\r
+ #endif /* USBFS_EP2_ISR_REMOVE */\r
#if(USBFS_EP3_ISR_REMOVE == 0u)\r
CyIntDisable(USBFS_EP_3_VECT_NUM);\r
- #endif /* End USBFS_EP3_ISR_REMOVE */\r
+ #endif /* USBFS_EP3_ISR_REMOVE */\r
#if(USBFS_EP4_ISR_REMOVE == 0u)\r
CyIntDisable(USBFS_EP_4_VECT_NUM);\r
- #endif /* End USBFS_EP4_ISR_REMOVE */\r
+ #endif /* USBFS_EP4_ISR_REMOVE */\r
#if(USBFS_EP5_ISR_REMOVE == 0u)\r
CyIntDisable(USBFS_EP_5_VECT_NUM);\r
- #endif /* End USBFS_EP5_ISR_REMOVE */\r
+ #endif /* USBFS_EP5_ISR_REMOVE */\r
#if(USBFS_EP6_ISR_REMOVE == 0u)\r
CyIntDisable(USBFS_EP_6_VECT_NUM);\r
- #endif /* End USBFS_EP6_ISR_REMOVE */\r
+ #endif /* USBFS_EP6_ISR_REMOVE */\r
#if(USBFS_EP7_ISR_REMOVE == 0u)\r
CyIntDisable(USBFS_EP_7_VECT_NUM);\r
- #endif /* End USBFS_EP7_ISR_REMOVE */\r
+ #endif /* USBFS_EP7_ISR_REMOVE */\r
#if(USBFS_EP8_ISR_REMOVE == 0u)\r
CyIntDisable(USBFS_EP_8_VECT_NUM);\r
- #endif /* End USBFS_EP8_ISR_REMOVE */\r
+ #endif /* USBFS_EP8_ISR_REMOVE */\r
\r
/* Clear all of the component data */\r
USBFS_configuration = 0u;\r
* No.\r
*\r
*******************************************************************************/\r
- void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData)\r
+ void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)\r
\r
{\r
uint16 src;\r
src = HI16(CYDEV_PERIPH_BASE);\r
dst = HI16(pData);\r
}\r
- #endif /* End C51 */\r
+ #endif /* C51 */\r
switch(epNumber)\r
{\r
case USBFS_EP1:\r
#if(USBFS_DMA1_REMOVE == 0u)\r
USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize(\r
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_DMA1_REMOVE */\r
+ #endif /* USBFS_DMA1_REMOVE */\r
break;\r
case USBFS_EP2:\r
#if(USBFS_DMA2_REMOVE == 0u)\r
USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize(\r
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_DMA2_REMOVE */\r
+ #endif /* USBFS_DMA2_REMOVE */\r
break;\r
case USBFS_EP3:\r
#if(USBFS_DMA3_REMOVE == 0u)\r
USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize(\r
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_DMA3_REMOVE */\r
+ #endif /* USBFS_DMA3_REMOVE */\r
break;\r
case USBFS_EP4:\r
#if(USBFS_DMA4_REMOVE == 0u)\r
USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize(\r
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_DMA4_REMOVE */\r
+ #endif /* USBFS_DMA4_REMOVE */\r
break;\r
case USBFS_EP5:\r
#if(USBFS_DMA5_REMOVE == 0u)\r
USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize(\r
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_DMA5_REMOVE */\r
+ #endif /* USBFS_DMA5_REMOVE */\r
break;\r
case USBFS_EP6:\r
#if(USBFS_DMA6_REMOVE == 0u)\r
USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize(\r
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_DMA6_REMOVE */\r
+ #endif /* USBFS_DMA6_REMOVE */\r
break;\r
case USBFS_EP7:\r
#if(USBFS_DMA7_REMOVE == 0u)\r
USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize(\r
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_DMA7_REMOVE */\r
+ #endif /* USBFS_DMA7_REMOVE */\r
break;\r
case USBFS_EP8:\r
#if(USBFS_DMA8_REMOVE == 0u)\r
USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize(\r
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_DMA8_REMOVE */\r
+ #endif /* USBFS_DMA8_REMOVE */\r
break;\r
default:\r
/* Do not support EP0 DMA transfers */\r
if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
USBFS_DmaTd[epNumber] = CyDmaTdAllocate();\r
+ #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ USBFS_DmaNextTd[epNumber] = CyDmaTdAllocate();\r
+ #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+\r
}\r
}\r
\r
CyDmaTdFree(USBFS_DmaTd[i]);\r
USBFS_DmaTd[i] = DMA_INVALID_TD;\r
}\r
+ #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ if(USBFS_DmaNextTd[i] != DMA_INVALID_TD)\r
+ {\r
+ CyDmaTdFree(USBFS_DmaNextTd[i]);\r
+ USBFS_DmaNextTd[i] = DMA_INVALID_TD;\r
+ }\r
+ #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
i++;\r
}while((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP));\r
}\r
\r
-#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+#endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
+\r
+\r
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: USBFS_LoadNextInEP\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * This internal function is used for IN endpoint DMA reconfiguration in\r
+ * Auto DMA mode.\r
+ *\r
+ * Parameters:\r
+ * epNumber: Contains the data endpoint number.\r
+ * mode: 0 - Configure DMA to send the the rest of data.\r
+ * 1 - Configure DMA to repeat 2 last bytes of the first burst.\r
+ *\r
+ * Return:\r
+ * None.\r
+ *\r
+ *******************************************************************************/\r
+ void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) \r
+ {\r
+ reg16 *convert;\r
+\r
+ if(mode == 0u)\r
+ {\r
+ /* Configure DMA to send the the rest of data */\r
+ /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */\r
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];\r
+ /* Set transfer length */\r
+ CY_SET_REG16(convert, USBFS_inLength[epNumber] - USBFS_DMA_BYTES_PER_BURST);\r
+ /* CyDmaTdSetAddress API is optimized to change only source address */\r
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];\r
+ CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] +\r
+ USBFS_DMA_BYTES_PER_BURST));\r
+ USBFS_inBufFull[epNumber] = 1u;\r
+ }\r
+ else\r
+ {\r
+ /* Configure DMA to repeat 2 last bytes of the first burst. */\r
+ /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */\r
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];\r
+ /* Set transfer length */\r
+ CY_SET_REG16(convert, USBFS_DMA_BYTES_REPEAT);\r
+ /* CyDmaTdSetAddress API is optimized to change only source address */\r
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];\r
+ CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] +\r
+ USBFS_DMA_BYTES_PER_BURST - USBFS_DMA_BYTES_REPEAT));\r
+ }\r
+\r
+ /* CyDmaChSetInitialTd API is optimised to init TD */\r
+ CY_DMA_CH_STRUCT_PTR[USBFS_DmaChan[epNumber]].basic_status[1u] = USBFS_DmaTd[epNumber];\r
+ }\r
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
\r
\r
/*******************************************************************************\r
********************************************************************************\r
*\r
* Summary:\r
-* Loads and enables the specified USB data endpoint for an IN interrupt or bulk\r
-* transfer.\r
+* Loads and enables the specified USB data endpoint for an IN transfer.\r
*\r
* Parameters:\r
* epNumber: Contains the data endpoint number.\r
reg8 *p;\r
#if(USBFS_EP_MM == USBFS__EP_MANUAL)\r
uint16 i;\r
- #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */\r
\r
if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
{\r
length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset;\r
}\r
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
\r
/* Set the count and data toggle */\r
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri),\r
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);\r
#else\r
/* Init DMA if it was not initialized */\r
- if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD)\r
+ if (USBFS_DmaTd[epNumber] == DMA_INVALID_TD)\r
{\r
USBFS_InitEP_DMA(epNumber, pData);\r
}\r
- #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */\r
\r
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
- if((pData != NULL) && (length > 0u))\r
+ if ((pData != NULL) && (length > 0u))\r
{\r
/* Enable DMA in mode2 for transferring data */\r
(void) CyDmaChDisable(USBFS_DmaChan[epNumber]);\r
/* When zero-length packet - write the Mode register directly */\r
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);\r
}\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- if(pData != NULL)\r
+ if (pData != NULL)\r
{\r
/* Enable DMA in mode3 for transferring data */\r
(void) CyDmaChDisable(USBFS_DmaChan[epNumber]);\r
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ USBFS_inLength[epNumber] = length;\r
+ USBFS_inDataPointer[epNumber] = pData;\r
+ /* Configure DMA to send the data only for the first burst */\r
+ (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber],\r
+ (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length,\r
+ USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);\r
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));\r
+ /* The second TD will be executed only when the first one fails.\r
+ * The intention of this TD is to generate NRQ interrupt\r
+ * and repeat 2 last bytes of the first burst.\r
+ */\r
+ (void) CyDmaTdSetConfiguration(USBFS_DmaNextTd[epNumber], 1u,\r
+ USBFS_DmaNextTd[epNumber],\r
+ USBFS_epX_TD_TERMOUT_EN[epNumber]);\r
+ /* Configure DmaNextTd to clear Data ready status */\r
+ (void) CyDmaTdSetAddress(USBFS_DmaNextTd[epNumber], LO16((uint32)&clearInDataRdyStatus),\r
+ LO16((uint32)(USBFS_ARB_EP1_CFG_IND + ri)));\r
+ #else /* Configure DMA to send all data*/\r
(void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length,\r
USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);\r
(void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));\r
+ #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */\r
+\r
/* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */\r
(void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);\r
/* Enable the DMA */\r
USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
if(length > 0u)\r
{\r
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ USBFS_inLength[epNumber] = length;\r
+ USBFS_inBufFull[epNumber] = 0u;\r
+ (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);\r
+ /* Configure DMA to send the data only for the first burst */\r
+ (void) CyDmaTdSetConfiguration(\r
+ USBFS_DmaTd[epNumber], (length > USBFS_DMA_BYTES_PER_BURST) ?\r
+ USBFS_DMA_BYTES_PER_BURST : length,\r
+ USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR );\r
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],\r
+ LO16((uint32)USBFS_inDataPointer[epNumber]), LO16((uint32)p));\r
+ /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */\r
+ (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);\r
+ /* Enable the DMA */\r
+ (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);\r
+ (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);\r
+ #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+\r
/* Set Data ready status, This will generate DMA request */\r
- * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+ #ifndef USBFS_MANUAL_IN_EP_ARM\r
+ * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+ #endif /* USBFS_MANUAL_IN_EP_ARM */\r
/* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */\r
}\r
else\r
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);\r
}\r
}\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
-\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
}\r
}\r
\r
reg8 *p;\r
#if(USBFS_EP_MM == USBFS__EP_MANUAL)\r
uint16 i;\r
- #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */\r
#if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
uint16 xferCount;\r
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
\r
if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL))\r
{\r
{\r
length = xferCount;\r
}\r
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
\r
#if(USBFS_EP_MM == USBFS__EP_MANUAL)\r
/* Copy the data using the arbiter data register */\r
{\r
USBFS_InitEP_DMA(epNumber, pData);\r
}\r
- #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */\r
+\r
+ #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */\r
\r
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
/* Enable DMA in mode2 for transferring data */\r
* (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ;\r
* (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ));\r
/* Out EP will be (re)armed in arb ISR after transfer complete */\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
/* Enable DMA in mode3 for transferring data */\r
(void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);\r
(void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);\r
/* Out EP will be (re)armed in arb ISR after transfer complete */\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
\r
}\r
else\r
/*******************************************************************************\r
* File Name: USBFS.h\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
-* Header File for the USFS component. Contains prototypes and constant values.\r
+* Header File for the USBFS component. Contains prototypes and constant values.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
#include "CyLib.h"\r
\r
+/* User supplied definitions. */\r
+/* `#START USER_DEFINITIONS` Place your declaration here */\r
+\r
+/* `#END` */\r
+\r
\r
/***************************************\r
* Conditional Compilation Parameters\r
/* Check to see if required defines such as CY_PSOC5LP are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5LP)\r
- #error Component USBFS_v2_60 requires cy_boot v3.0 or later\r
+ #error Component USBFS_v2_80 requires cy_boot v3.0 or later\r
#endif /* (CY_PSOC5LP) */\r
\r
\r
#else\r
#define USBFS_DATA\r
#define USBFS_XDATA\r
-#endif /* End __C51__ */\r
+#endif /* __C51__ */\r
#define USBFS_NULL NULL\r
\r
\r
#define USBFS_EP8_ISR_REMOVE (1u)\r
#define USBFS_EP_MM (0u)\r
#define USBFS_EP_MA (0u)\r
+#define USBFS_EP_DMA_AUTO_OPT (0u)\r
#define USBFS_DMA1_REMOVE (1u)\r
#define USBFS_DMA2_REMOVE (1u)\r
#define USBFS_DMA3_REMOVE (1u)\r
#endif /* USBFS_ENABLE_FWSN_STRING */\r
#if (USBFS_MON_VBUS == 1u)\r
uint8 USBFS_VBusPresent(void) ;\r
-#endif /* End USBFS_MON_VBUS */\r
+#endif /* USBFS_MON_VBUS */\r
\r
#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \\r
(CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))\r
void USBFS_CyBtldrCommStart(void) ;\r
void USBFS_CyBtldrCommStop(void) ;\r
void USBFS_CyBtldrCommReset(void) ;\r
- cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
+ cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
;\r
- cystatus USBFS_CyBtldrCommRead( uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
+ cystatus USBFS_CyBtldrCommRead (uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
;\r
\r
- #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* EP 1 OUT */\r
- #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* EP 2 IN */\r
- #define USBFS_BTLDR_MAX_PACKET_SIZE USBFS_BTLDR_SIZEOF_WRITE_BUFFER\r
+ #define USBFS_BTLDR_OUT_EP (0x01u)\r
+ #define USBFS_BTLDR_IN_EP (0x02u)\r
+\r
+ #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* EP 1 OUT */\r
+ #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* EP 2 IN */\r
+ #define USBFS_BTLDR_MAX_PACKET_SIZE USBFS_BTLDR_SIZEOF_WRITE_BUFFER\r
+\r
+ #define USBFS_BTLDR_WAIT_1_MS (1u) /* Time Out quantity equal 1mS */\r
\r
/* These defines active if used USBFS interface as an\r
* IO Component for bootloading. When Custom_Interface selected\r
* in Bootloder configuration as the IO Component, user must\r
- * provide these functions\r
+ * provide these functions.\r
*/\r
#if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS)\r
#define CyBtldrCommStart USBFS_CyBtldrCommStart\r
#define CyBtldrCommRead USBFS_CyBtldrCommRead\r
#endif /*End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */\r
\r
-#endif /* End CYDEV_BOOTLOADER_IO_COMP */\r
+#endif /* CYDEV_BOOTLOADER_IO_COMP */\r
\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData)\r
+ void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)\r
;\r
void USBFS_Stop_DMA(uint8 epNumber) ;\r
-#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL) */\r
+#endif /* USBFS_EP_MM != USBFS__EP_MANUAL) */\r
\r
#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)\r
void USBFS_MIDI_EP_Init(void) ;\r
void USBFS_MIDI_OUT_EP_Service(void) ;\r
#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */\r
\r
-#endif /* End USBFS_ENABLE_MIDI_API != 0u */\r
+#endif /* USBFS_ENABLE_MIDI_API != 0u */\r
\r
/* Renamed Functions for backward compatibility.\r
* Should not be used in new designs.\r
#define USBFS_EP_USAGE_TYPE_RESERVED (0x30u)\r
#define USBFS_EP_USAGE_TYPE_MASK (0x30u)\r
\r
-/* Endpoint Status defines */\r
+/* point Status defines */\r
#define USBFS_EP_STATUS_LENGTH (0x02u)\r
\r
-/* Endpoint Device defines */\r
+/* point Device defines */\r
#define USBFS_DEVICE_STATUS_LENGTH (0x02u)\r
\r
#define USBFS_STATUS_LENGTH_MAX \\r
/* DMA manual mode defines */\r
#define USBFS_DMA_BYTES_PER_BURST (0u)\r
#define USBFS_DMA_REQUEST_PER_BURST (0u)\r
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
+#endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
/* DMA automatic mode defines */\r
#define USBFS_DMA_BYTES_PER_BURST (32u)\r
+ #define USBFS_DMA_BYTES_REPEAT (2u)\r
/* BUF_SIZE-BYTES_PER_BURST examples: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */\r
#define USBFS_DMA_BUF_SIZE (0x55u)\r
#define USBFS_DMA_REQUEST_PER_BURST (1u)\r
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+\r
+ #if(USBFS_DMA1_REMOVE == 0u)\r
+ #define USBFS_ep1_TD_TERMOUT_EN USBFS_ep1__TD_TERMOUT_EN\r
+ #else\r
+ #define USBFS_ep1_TD_TERMOUT_EN (0u)\r
+ #endif /* USBFS_DMA1_REMOVE == 0u */\r
+ #if(USBFS_DMA2_REMOVE == 0u)\r
+ #define USBFS_ep2_TD_TERMOUT_EN USBFS_ep2__TD_TERMOUT_EN\r
+ #else\r
+ #define USBFS_ep2_TD_TERMOUT_EN (0u)\r
+ #endif /* USBFS_DMA2_REMOVE == 0u */\r
+ #if(USBFS_DMA3_REMOVE == 0u)\r
+ #define USBFS_ep3_TD_TERMOUT_EN USBFS_ep3__TD_TERMOUT_EN\r
+ #else\r
+ #define USBFS_ep3_TD_TERMOUT_EN (0u)\r
+ #endif /* USBFS_DMA3_REMOVE == 0u */\r
+ #if(USBFS_DMA4_REMOVE == 0u)\r
+ #define USBFS_ep4_TD_TERMOUT_EN USBFS_ep4__TD_TERMOUT_EN\r
+ #else\r
+ #define USBFS_ep4_TD_TERMOUT_EN (0u)\r
+ #endif /* USBFS_DMA4_REMOVE == 0u */\r
+ #if(USBFS_DMA5_REMOVE == 0u)\r
+ #define USBFS_ep5_TD_TERMOUT_EN USBFS_ep5__TD_TERMOUT_EN\r
+ #else\r
+ #define USBFS_ep5_TD_TERMOUT_EN (0u)\r
+ #endif /* USBFS_DMA5_REMOVE == 0u */\r
+ #if(USBFS_DMA6_REMOVE == 0u)\r
+ #define USBFS_ep6_TD_TERMOUT_EN USBFS_ep6__TD_TERMOUT_EN\r
+ #else\r
+ #define USBFS_ep6_TD_TERMOUT_EN (0u)\r
+ #endif /* USBFS_DMA6_REMOVE == 0u */\r
+ #if(USBFS_DMA7_REMOVE == 0u)\r
+ #define USBFS_ep7_TD_TERMOUT_EN USBFS_ep7__TD_TERMOUT_EN\r
+ #else\r
+ #define USBFS_ep7_TD_TERMOUT_EN (0u)\r
+ #endif /* USBFS_DMA7_REMOVE == 0u */\r
+ #if(USBFS_DMA8_REMOVE == 0u)\r
+ #define USBFS_ep8_TD_TERMOUT_EN USBFS_ep8__TD_TERMOUT_EN\r
+ #else\r
+ #define USBFS_ep8_TD_TERMOUT_EN (0u)\r
+ #endif /* USBFS_DMA8_REMOVE == 0u */\r
+\r
+ #define USBFS_EP17_SR_MASK (0x7fu)\r
+ #define USBFS_EP8_SR_MASK (0x03u)\r
+\r
+#endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
\r
/* DIE ID string descriptor defines */\r
#if defined(USBFS_ENABLE_IDSN_STRING)\r
#if(!CY_PSOC5LP)\r
#define USBFS_USBIO_CR2_PTR ( (reg8 *) USBFS_USB__USBIO_CR2)\r
#define USBFS_USBIO_CR2_REG (* (reg8 *) USBFS_USB__USBIO_CR2)\r
-#endif /* End CY_PSOC5LP */\r
+#endif /* CY_PSOC5LP */\r
\r
#define USBFS_DIE_ID CYDEV_FLSHID_CUST_TABLES_BASE\r
\r
#else\r
#define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG )\r
#define USBFS_VBUS_MASK (0x01u)\r
- #endif /* End USBFS_EXTERN_VBUS == 0u */\r
-#endif /* End USBFS_MON_VBUS */\r
+ #endif /* USBFS_EXTERN_VBUS == 0u */\r
+#endif /* USBFS_MON_VBUS */\r
\r
/* Renamed Registers for backward compatibility.\r
* Should not be used in new designs.\r
#define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0)\r
#define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0)\r
#define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET)\r
-#endif /* End CYDEV_CHIP_DIE_EXPECT */\r
+#endif /* CYDEV_CHIP_DIE_EXPECT */\r
\r
\r
/***************************************\r
#define USBFS_ARB_EPX_CFG_CRC_BYPASS (0x04u)\r
#define USBFS_ARB_EPX_CFG_DMA_REQ (0x02u)\r
#define USBFS_ARB_EPX_CFG_IN_DATA_RDY (0x01u)\r
+#define USBFS_ARB_EPX_CFG_DEFAULT (USBFS_ARB_EPX_CFG_RESET | \\r
+ USBFS_ARB_EPX_CFG_CRC_BYPASS)\r
\r
#define USBFS_ARB_EPX_SR_IN_BUF_FULL (0x01u)\r
#define USBFS_ARB_EPX_SR_DMA_GNT (0x02u)\r
#define USBFS_ARB_EPX_INT_MASK (0x1Du)\r
#else\r
#define USBFS_ARB_EPX_INT_MASK (0x1Fu)\r
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+#endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
#define USBFS_ARB_INT_MASK (uint8)((USBFS_DMA1_REMOVE ^ 1u) | \\r
(uint8)((USBFS_DMA2_REMOVE ^ 1u) << 1u) | \\r
(uint8)((USBFS_DMA3_REMOVE ^ 1u) << 2u) | \\r
#define USBFS_DYN_RECONFIG_RDY_STS (0x10u)\r
\r
\r
-#endif /* End CY_USBFS_USBFS_H */\r
+#endif /* CY_USBFS_USBFS_H */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_Dm.c \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
* Change the drive mode on the pins of the port.\r
* \r
* Parameters: \r
-* mode: Change the pins to this drive mode.\r
+* mode: Change the pins to one of the following drive modes.\r
+*\r
+* USBFS_Dm_DM_STRONG Strong Drive \r
+* USBFS_Dm_DM_OD_HI Open Drain, Drives High \r
+* USBFS_Dm_DM_OD_LO Open Drain, Drives Low \r
+* USBFS_Dm_DM_RES_UP Resistive Pull Up \r
+* USBFS_Dm_DM_RES_DWN Resistive Pull Down \r
+* USBFS_Dm_DM_RES_UPDWN Resistive Pull Up/Down \r
+* USBFS_Dm_DM_DIG_HIZ High Impedance Digital \r
+* USBFS_Dm_DM_ALG_HIZ High Impedance Analog \r
*\r
* Return: \r
* None\r
/*******************************************************************************\r
* File Name: USBFS_Dm.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/* Check to see if required defines such as CY_PSOC5A are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
#endif /* (CY_PSOC5A) */\r
\r
/* APIs are not generated for P15[7:6] */\r
/*******************************************************************************\r
* File Name: USBFS_Dm.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/***************************************\r
* Constants \r
***************************************/\r
-#define USBFS_Dm_0 USBFS_Dm__0__PC\r
+#define USBFS_Dm_0 (USBFS_Dm__0__PC)\r
\r
#endif /* End Pins USBFS_Dm_ALIASES_H */\r
\r
/*******************************************************************************\r
* File Name: USBFS_Dp.c \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
* Change the drive mode on the pins of the port.\r
* \r
* Parameters: \r
-* mode: Change the pins to this drive mode.\r
+* mode: Change the pins to one of the following drive modes.\r
+*\r
+* USBFS_Dp_DM_STRONG Strong Drive \r
+* USBFS_Dp_DM_OD_HI Open Drain, Drives High \r
+* USBFS_Dp_DM_OD_LO Open Drain, Drives Low \r
+* USBFS_Dp_DM_RES_UP Resistive Pull Up \r
+* USBFS_Dp_DM_RES_DWN Resistive Pull Down \r
+* USBFS_Dp_DM_RES_UPDWN Resistive Pull Up/Down \r
+* USBFS_Dp_DM_DIG_HIZ High Impedance Digital \r
+* USBFS_Dp_DM_ALG_HIZ High Impedance Analog \r
*\r
* Return: \r
* None\r
/*******************************************************************************\r
* File Name: USBFS_Dp.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/* Check to see if required defines such as CY_PSOC5A are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
#endif /* (CY_PSOC5A) */\r
\r
/* APIs are not generated for P15[7:6] */\r
/*******************************************************************************\r
* File Name: USBFS_Dp.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/***************************************\r
* Constants \r
***************************************/\r
-#define USBFS_Dp_0 USBFS_Dp__0__PC\r
+#define USBFS_Dp_0 (USBFS_Dp__0__PC)\r
\r
#endif /* End Pins USBFS_Dp_ALIASES_H */\r
\r
/*******************************************************************************\r
* File Name: USBFS_audio.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* USB AUDIO Class request handler.\r
*\r
-* Note:\r
+* Related Document:\r
+* Universal Serial Bus Device Class Definition for Audio Devices Release 1.0\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
#include "USBFS_audio.h"\r
#include "USBFS_pvt.h"\r
-#if defined(USBFS_ENABLE_MIDI_STREAMING) \r
+#if defined(USBFS_ENABLE_MIDI_STREAMING)\r
#include "USBFS_midi.h"\r
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/\r
+#endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
\r
\r
/***************************************\r
USBFS_VOL_MAX_MSB};\r
volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_RES_LSB,\r
USBFS_VOL_RES_MSB};\r
-#endif /* End USBFS_ENABLE_AUDIO_STREAMING */\r
+#endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
\r
\r
/*******************************************************************************\r
uint8 USBFS_DispatchAUDIOClassRqst(void) \r
{\r
uint8 requestHandled = USBFS_FALSE;\r
+ uint8 bmRequestType = CY_GET_REG8(USBFS_bmRequestType);\r
\r
#if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
uint8 epNumber;\r
epNumber = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED;\r
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */\r
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
\r
- if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)\r
+\r
+ if ((bmRequestType & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)\r
{\r
/* Control Read */\r
- if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \\r
- USBFS_RQST_RCPT_EP)\r
+ if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)\r
{\r
/* Endpoint */\r
switch (CY_GET_REG8(USBFS_bRequest))\r
#if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)\r
{\r
- /* Endpoint Control Selector is Sampling Frequency */\r
+ /* point Control Selector is Sampling Frequency */\r
USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;\r
USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber];\r
requestHandled = USBFS_InitControlRead();\r
}\r
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */\r
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
\r
/* `#START AUDIO_READ_REQUESTS` Place other request handler here */\r
\r
break;\r
}\r
}\r
- else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \\r
- USBFS_RQST_RCPT_IFC)\r
+ else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)\r
{\r
/* Interface or Entity ID */\r
switch (CY_GET_REG8(USBFS_bRequest))\r
/* `#START MUTE_CONTROL_GET_REQUEST` Place multi-channel handler here */\r
\r
/* `#END` */\r
- \r
+\r
/* Entity ID Control Selector is MUTE */\r
USBFS_currentTD.wCount = 1u;\r
USBFS_currentTD.pData = &USBFS_currentMute;\r
USBFS_currentTD.wCount = 0u;\r
requestHandled = USBFS_InitControlWrite();\r
\r
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */\r
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
\r
/* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */\r
\r
{ /* USBFS_RQST_RCPT_OTHER */\r
}\r
}\r
- else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == \\r
- USBFS_RQST_DIR_H2D)\r
+ else\r
{\r
/* Control Write */\r
- if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \\r
- USBFS_RQST_RCPT_EP)\r
+ if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)\r
{\r
- /* Endpoint */\r
+ /* point */\r
switch (CY_GET_REG8(USBFS_bRequest))\r
{\r
case USBFS_SET_CUR:\r
#if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)\r
{\r
- /* Endpoint Control Selector is Sampling Frequency */\r
+ /* point Control Selector is Sampling Frequency */\r
USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;\r
USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber];\r
requestHandled = USBFS_InitControlWrite();\r
USBFS_frequencyChanged = epNumber;\r
}\r
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */\r
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
\r
/* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */\r
\r
break;\r
}\r
}\r
- else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \\r
- USBFS_RQST_RCPT_IFC)\r
+ else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)\r
{\r
/* Interface or Entity ID */\r
switch (CY_GET_REG8(USBFS_bRequest))\r
\r
/* `#END` */\r
}\r
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */\r
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
\r
/* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */\r
\r
}\r
}\r
else\r
- { /* USBFS_RQST_RCPT_OTHER */\r
+ {\r
+ /* USBFS_RQST_RCPT_OTHER */\r
}\r
}\r
- else\r
- { /* requestHandled is initialized as FALSE by default */\r
- }\r
\r
return(requestHandled);\r
}\r
\r
-\r
#endif /* USER_SUPPLIED_AUDIO_HANDLER */\r
\r
\r
\r
/* `#END` */\r
\r
-#endif /* End USBFS_ENABLE_AUDIO_CLASS*/\r
+#endif /* USBFS_ENABLE_AUDIO_CLASS */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_audio.h\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
-* Header File for the USFS component. Contains prototypes and constant values.\r
+* Header File for the USBFS component. Contains prototypes and constant values.\r
+*\r
+* Related Document:\r
+* Universal Serial Bus Device Class Definition for Audio Devices Release 1.0\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#define USBFS_GET_MEM (0x85u)\r
#define USBFS_GET_STAT (0xFFu)\r
\r
-/* Endpoint Control Selectors (AUDIO Table A-19) */\r
+/* point Control Selectors (AUDIO Table A-19) */\r
#define USBFS_EP_CONTROL_UNDEFINED (0x00u)\r
#define USBFS_SAMPLING_FREQ_CONTROL (0x01u)\r
#define USBFS_PITCH_CONTROL (0x02u)\r
extern volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN];\r
extern volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN];\r
\r
-#endif /* End CY_USBFS_USBFS_audio_H */\r
+#endif /* CY_USBFS_USBFS_audio_H */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_boot.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* Boot loader API for USBFS Component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
(CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))\r
\r
\r
-/***************************************\r
-* Bootloader defines\r
-***************************************/\r
-\r
-#define USBFS_CyBtLdrStarttimer(X, T) {USBFS_universalTime = T * 10; X = 0u;}\r
-#define USBFS_CyBtLdrChecktimer(X) ((X++ < USBFS_universalTime) ? 1u : 0u)\r
-\r
-#define USBFS_BTLDR_OUT_EP (0x01u)\r
-#define USBFS_BTLDR_IN_EP (0x02u)\r
-\r
-\r
/***************************************\r
* Bootloader Variables\r
***************************************/\r
\r
-static uint16 USBFS_universalTime;\r
-static uint8 USBFS_started = 0u;\r
+static uint8 USBFS_started = 0u;\r
\r
\r
/*******************************************************************************\r
\r
/* USB component started, the correct enumeration will be checked in first Read operation */\r
USBFS_started = 1u;\r
-\r
}\r
\r
\r
* Resets the receive and transmit communication Buffers.\r
*\r
* Parameters:\r
-* None.\r
+* None\r
*\r
* Return:\r
-* None.\r
+* None\r
*\r
* Reentrant:\r
-* No.\r
+* No\r
*\r
*******************************************************************************/\r
void USBFS_CyBtldrCommReset(void) \r
* Returns the value that best describes the problem.\r
*\r
* Reentrant:\r
-* No.\r
+* No\r
*\r
*******************************************************************************/\r
-cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
+cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
\r
{\r
- uint16 time;\r
- cystatus status;\r
+ cystatus retCode;\r
+ uint16 timeoutMs;\r
+\r
+ timeoutMs = ((uint16) 10u * timeOut); /* Convert from 10mS check to number 1mS checks */\r
\r
/* Enable IN transfer */\r
USBFS_LoadInEP(USBFS_BTLDR_IN_EP, pData, USBFS_BTLDR_SIZEOF_READ_BUFFER);\r
\r
- /* Start a timer to wait on. */\r
- USBFS_CyBtLdrStarttimer(time, timeOut);\r
-\r
/* Wait for the master to read it. */\r
- while((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) && \\r
- USBFS_CyBtLdrChecktimer(time))\r
+ while ((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) &&\r
+ (0u != timeoutMs))\r
{\r
- CyDelay(1u); /* 1ms delay */\r
+ CyDelay(USBFS_BTLDR_WAIT_1_MS);\r
+ timeoutMs--;\r
}\r
\r
if (USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL)\r
{\r
- status = CYRET_TIMEOUT;\r
+ retCode = CYRET_TIMEOUT;\r
}\r
else\r
{\r
*count = size;\r
- status = CYRET_SUCCESS;\r
+ retCode = CYRET_SUCCESS;\r
}\r
\r
- return(status);\r
+ return(retCode);\r
}\r
\r
\r
* Returns the value that best describes the problem.\r
*\r
* Reentrant:\r
-* No.\r
+* No\r
*\r
*******************************************************************************/\r
-cystatus USBFS_CyBtldrCommRead(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
+cystatus USBFS_CyBtldrCommRead(uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
\r
{\r
- cystatus status;\r
- uint16 time;\r
+ cystatus retCode;\r
+ uint16 timeoutMs;\r
+\r
+ timeoutMs = ((uint16) 10u * timeOut); /* Convert from 10mS check to number 1mS checks */\r
\r
- if(size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER)\r
+ if (size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER)\r
{\r
size = USBFS_BTLDR_SIZEOF_WRITE_BUFFER;\r
}\r
- /* Start a timer to wait on. */\r
- USBFS_CyBtLdrStarttimer(time, timeOut);\r
\r
/* Wait on enumeration in first time */\r
- if(USBFS_started)\r
+ if (0u != USBFS_started)\r
{\r
/* Wait for Device to enumerate */\r
- while(!USBFS_GetConfiguration() && USBFS_CyBtLdrChecktimer(time))\r
+ while ((0u ==USBFS_GetConfiguration()) && (0u != timeoutMs))\r
{\r
- CyDelay(1u); /* 1ms delay */\r
+ CyDelay(USBFS_BTLDR_WAIT_1_MS);\r
+ timeoutMs--;\r
}\r
+\r
/* Enable first OUT, if enumeration complete */\r
- if(USBFS_GetConfiguration())\r
+ if (0u != USBFS_GetConfiguration())\r
{\r
- USBFS_IsConfigurationChanged(); /* Clear configuration changes state status */\r
+ (void) USBFS_IsConfigurationChanged(); /* Clear configuration changes state status */\r
USBFS_CyBtldrCommReset();\r
USBFS_started = 0u;\r
}\r
}\r
else /* Check for configuration changes, has been done by Host */\r
{\r
- if(USBFS_IsConfigurationChanged() != 0u) /* Host could send double SET_INTERFACE request or RESET */\r
+ if (0u != USBFS_IsConfigurationChanged()) /* Host could send double SET_INTERFACE request or RESET */\r
{\r
- if(USBFS_GetConfiguration() != 0u) /* Init OUT endpoints when device reconfigured */\r
+ if (0u != USBFS_GetConfiguration()) /* Init OUT endpoints when device reconfigured */\r
{\r
USBFS_CyBtldrCommReset();\r
}\r
}\r
}\r
+\r
+ timeoutMs = ((uint16) 10u * timeOut); /* Re-arm timeout */\r
+\r
/* Wait on next packet */\r
while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \\r
- USBFS_CyBtLdrChecktimer(time))\r
+ (0u != timeoutMs))\r
{\r
- CyDelay(1u); /* 1ms delay */\r
+ CyDelay(USBFS_BTLDR_WAIT_1_MS);\r
+ timeoutMs--;\r
}\r
\r
/* OUT EP has completed */\r
if (USBFS_GetEPState(USBFS_BTLDR_OUT_EP) == USBFS_OUT_BUFFER_FULL)\r
{\r
*count = USBFS_ReadOutEP(USBFS_BTLDR_OUT_EP, pData, size);\r
- status = CYRET_SUCCESS;\r
+ retCode = CYRET_SUCCESS;\r
}\r
else\r
{\r
*count = 0u;\r
- status = CYRET_TIMEOUT;\r
+ retCode = CYRET_TIMEOUT;\r
}\r
- return(status);\r
+\r
+ return(retCode);\r
}\r
\r
-#endif /* End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */\r
+#endif /* CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_cdc.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
-* USB HID Class request handler.\r
+* USB CDC class request handler.\r
*\r
-* Note:\r
+* Related Document:\r
+* Universal Serial Bus Class Definitions for Communication Devices Version 1.1\r
*\r
********************************************************************************\r
-* Copyright 2012-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2012-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
* CDC Variables\r
***************************************/\r
\r
-volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE];\r
+volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE] =\r
+{\r
+ 0x00u, 0xC2u, 0x01u, 0x00u, /* Data terminal rate 115200 */\r
+ 0x00u, /* 1 Stop bit */\r
+ 0x00u, /* None parity */\r
+ 0x08u /* 8 data bits */\r
+};\r
volatile uint8 USBFS_lineChanged;\r
volatile uint16 USBFS_lineControlBitmap;\r
volatile uint8 USBFS_cdc_data_in_ep;\r
/***************************************\r
* Static Function Prototypes\r
***************************************/\r
-static uint16 USBFS_StrLen(const char8 string[]) ;\r
+#if (USBFS_ENABLE_CDC_CLASS_API != 0u)\r
+ static uint16 USBFS_StrLen(const char8 string[]) ;\r
+#endif /* (USBFS_ENABLE_CDC_CLASS_API != 0u) */\r
\r
\r
/***************************************\r
***************************************/\r
#if (USBFS_ENABLE_CDC_CLASS_API != 0u)\r
\r
-\r
/*******************************************************************************\r
* Function Name: USBFS_CDC_Init\r
********************************************************************************\r
********************************************************************************\r
*\r
* Summary:\r
- * Sends a specified number of bytes from the location specified by a\r
- * pointer to the PC.\r
+ * This function sends a specified number of bytes from the location specified\r
+ * by a pointer to the PC. The USBFS_CDCIsReady() function should be\r
+ * called before sending new data, to be sure that the previous data has\r
+ * finished sending.\r
+ * If the last sent packet is less than maximum packet size the USB transfer\r
+ * of this short packet will identify the end of the segment. If the last sent\r
+ * packet is exactly maximum packet size, it shall be followed by a zero-length\r
+ * packet (which is a short packet) to assure the end of segment is properly\r
+ * identified. To send zero-length packet, use USBFS_PutData() API\r
+ * with length parameter set to zero.\r
*\r
* Parameters:\r
* pData: pointer to the buffer containing data to be sent.\r
* length: Specifies the number of bytes to send from the pData\r
* buffer. Maximum length will be limited by the maximum packet\r
- * size for the endpoint.\r
+ * size for the endpoint. Data will be lost if length is greater than Max\r
+ * Packet Size.\r
*\r
* Return:\r
* None.\r
********************************************************************************\r
*\r
* Summary:\r
- * Sends a null terminated string to the PC.\r
+ * This function sends a null terminated string to the PC. This function will\r
+ * block if there is not enough memory to place the whole string. It will block\r
+ * until the entire string has been written to the transmit buffer.\r
+ * The USBUART_CDCIsReady() function should be called before sending data with\r
+ * a new call to USBFS_PutString(), to be sure that the previous data\r
+ * has finished sending.\r
*\r
* Parameters:\r
- * string: pointer to the string to be sent to the PC\r
+ * string: pointer to the string to be sent to the PC.\r
*\r
* Return:\r
* None.\r
* Reentrant:\r
* No.\r
*\r
- * Theory:\r
- * This function will block if there is not enough memory to place the whole\r
- * string, it will block until the entire string has been written to the\r
- * transmit buffer.\r
- *\r
*******************************************************************************/\r
void USBFS_PutString(const char8 string[]) \r
{\r
- uint16 str_length;\r
- uint16 send_length;\r
- uint16 buf_index = 0u;\r
+ uint16 strLength;\r
+ uint16 sendLength;\r
+ uint16 bufIndex = 0u;\r
\r
/* Get length of the null terminated string */\r
- str_length = USBFS_StrLen(string);\r
+ strLength = USBFS_StrLen(string);\r
do\r
{\r
/* Limits length to maximum packet size for the EP */\r
- send_length = (str_length > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ?\r
- USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : str_length;\r
+ sendLength = (strLength > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ?\r
+ USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : strLength;\r
/* Enable IN transfer */\r
- USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[buf_index], send_length);\r
- str_length -= send_length;\r
+ USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[bufIndex], sendLength);\r
+ strLength -= sendLength;\r
\r
- /* If more data are present to send */\r
- if(str_length > 0u)\r
+ /* If more data are present to send or full packet was sent */\r
+ if((strLength > 0u) || (sendLength == USBFS_EP[USBFS_cdc_data_in_ep].bufferSize))\r
{\r
- buf_index += send_length;\r
+ bufIndex += sendLength;\r
/* Wait for the Host to read it. */\r
while(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState ==\r
USBFS_IN_BUFFER_FULL)\r
{\r
;\r
}\r
+ /* If the last sent packet is exactly maximum packet size,\r
+ * it shall be followed by a zero-length packet to assure the\r
+ * end of segment is properly identified by the terminal.\r
+ */\r
+ if(strLength == 0u)\r
+ {\r
+ USBFS_LoadInEP(USBFS_cdc_data_in_ep, NULL, 0u);\r
+ }\r
}\r
- }while(str_length > 0u);\r
+ }while(strLength > 0u);\r
}\r
\r
\r
*\r
* Summary:\r
* This function returns the number of bytes that were received from the PC.\r
+ * The returned length value should be passed to USBFS_GetData() as\r
+ * a parameter to read all received data. If all of the received data is not\r
+ * read at one time by the USBFS_GetData() API, the unread data will\r
+ * be lost.\r
*\r
* Parameters:\r
* None.\r
*\r
* Return:\r
- * Returns the number of received bytes.\r
+ * Returns the number of received bytes. The maximum amount of received data at\r
+ * a time is limited by the maximum packet size for the endpoint.\r
*\r
* Global variables:\r
* USBFS_cdc_data_out_ep: CDC OUT endpoint number used.\r
*******************************************************************************/\r
uint16 USBFS_GetCount(void) \r
{\r
- uint16 bytesCount = 0u;\r
+ uint16 bytesCount;\r
\r
if (USBFS_EP[USBFS_cdc_data_out_ep].apiEpState == USBFS_OUT_BUFFER_FULL)\r
{\r
bytesCount = USBFS_GetEPCount(USBFS_cdc_data_out_ep);\r
}\r
+ else\r
+ {\r
+ bytesCount = 0u;\r
+ }\r
\r
return(bytesCount);\r
}\r
*\r
* Summary:\r
* Returns a nonzero value if the component received data or received\r
- * zero-length packet. The GetAll() or GetData() API should be called to read\r
- * data from the buffer and re-init OUT endpoint even when zero-length packet\r
- * received.\r
+ * zero-length packet. The USBFS_GetAll() or\r
+ * USBFS_GetData() API should be called to read data from the buffer\r
+ * and re-init OUT endpoint even when zero-length packet received.\r
*\r
* Parameters:\r
* None.\r
********************************************************************************\r
*\r
* Summary:\r
- * Returns a nonzero value if the component is ready to send more data to the\r
- * PC. Otherwise returns zero. Should be called before sending new data to\r
- * ensure the previous data has finished sending.This function returns the\r
- * number of bytes that were received from the PC.\r
+ * This function returns a nonzero value if the component is ready to send more\r
+ * data to the PC; otherwise, it returns zero. The function should be called\r
+ * before sending new data when using any of the following APIs:\r
+ * USBFS_PutData(),USBFS_PutString(),\r
+ * USBFS_PutChar or USBFS_PutCRLF(),\r
+ * to be sure that the previous data has finished sending.\r
*\r
* Parameters:\r
* None.\r
*\r
* Return:\r
- * If the buffer can accept new data then this function returns a nonzero value.\r
- * Otherwise zero is returned.\r
+ * If the buffer can accept new data, this function returns a nonzero value.\r
+ * Otherwise, it returns zero.\r
*\r
* Global variables:\r
* USBFS_cdc_data_in_ep: CDC IN endpoint number used.\r
********************************************************************************\r
*\r
* Summary:\r
- * Gets a specified number of bytes from the input buffer and places it in a\r
- * data array specified by the passed pointer.\r
- * USBFS_DataIsReady() API should be called before, to be sure\r
- * that data is received from the Host.\r
+ * This function gets a specified number of bytes from the input buffer and\r
+ * places them in a data array specified by the passed pointer.\r
+ * The USBFS_DataIsReady() API should be called first, to be sure\r
+ * that data is received from the host. If all received data will not be read at\r
+ * once, the unread data will be lost. The USBFS_GetData() API should\r
+ * be called to get the number of bytes that were received.\r
*\r
* Parameters:\r
* pData: Pointer to the data array where data will be placed.\r
********************************************************************************\r
*\r
* Summary:\r
- * Reads one byte of received data from the buffer.\r
+ * This function reads one byte of received data from the buffer. If more than\r
+ * one byte has been received from the host, the rest of the data will be lost.\r
*\r
* Parameters:\r
* None.\r
********************************************************************************\r
*\r
* Summary:\r
- * This function returns clear on read status of the line.\r
+ * This function returns clear on read status of the line. It returns not zero\r
+ * value when the host sends updated coding or control information to the\r
+ * device. The USBFS_GetDTERate(), USBFS_GetCharFormat()\r
+ * or USBFS_GetParityType() or USBFS_GetDataBits() API\r
+ * should be called to read data coding information.\r
+ * The USBFS_GetLineControl() API should be called to read line\r
+ * control information.\r
*\r
* Parameters:\r
* None.\r
*\r
* Return:\r
- * If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE request received then not\r
- * zero value returned. Otherwise zero is returned.\r
+ * If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE requests are received, it\r
+ * returns a nonzero value. Otherwise, it returns zero.\r
*\r
* Global variables:\r
- * USBFS_transferState - it is checked to be sure then OUT data\r
+ * USBFS_transferState: it is checked to be sure then OUT data\r
* phase has been complete, and data written to the lineCoding or Control\r
* Bitmap buffer.\r
* USBFS_lineChanged: used as a flag to be aware that Host has been\r
return(USBFS_lineControlBitmap);\r
}\r
\r
-#endif /* End USBFS_ENABLE_CDC_CLASS_API*/\r
+#endif /* USBFS_ENABLE_CDC_CLASS_API*/\r
\r
\r
/*******************************************************************************\r
\r
/* `#END` */\r
\r
-#endif /* End USBFS_ENABLE_CDC_CLASS*/\r
+#endif /* USBFS_ENABLE_CDC_CLASS*/\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_cdc.h\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
-* Header File for the USFS component.\r
+* Header File for the USBFS component.\r
* Contains CDC class prototypes and constant values.\r
*\r
+* Related Document:\r
+* Universal Serial Bus Class Definitions for Communication Devices Version 1.1\r
+*\r
********************************************************************************\r
-* Copyright 2012-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2012-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
uint8 USBFS_GetParityType(void) ;\r
uint8 USBFS_GetDataBits(void) ;\r
uint16 USBFS_GetLineControl(void) ;\r
-#endif /* End USBFS_ENABLE_CDC_CLASS_API*/\r
+#endif /* USBFS_ENABLE_CDC_CLASS_API */\r
\r
\r
/***************************************\r
extern volatile uint8 USBFS_cdc_data_in_ep;\r
extern volatile uint8 USBFS_cdc_data_out_ep;\r
\r
-#endif /* End CY_USBFS_USBFS_cdc_H */\r
+#endif /* CY_USBFS_USBFS_cdc_H */\r
\r
\r
/* [] END OF FILE */\r
;******************************************************************************\r
; File Name: USBFS_cdc.inf\r
-; Version 2.60\r
+; Version 2.80\r
;\r
; Description:\r
; Windows USB CDC setup file for USBUART Device.\r
;\r
;******************************************************************************\r
-; Copyright 2007-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright 2007-2014, Cypress Semiconductor Corporation. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions,\r
; disclaimers, and limitations in the end user license agreement accompanying\r
; the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: USBFS_cls.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* USB Class request handler.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
break;\r
case USBFS_RQST_RCPT_EP: /* Class-specific request directed to the endpoint */\r
/* Find related interface to the endpoint, wIndexLo contain EP number */\r
- interfaceNumber =\r
- USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].interface;\r
+ interfaceNumber = USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) &\r
+ USBFS_DIR_UNUSED].interface;\r
break;\r
default: /* RequestHandled is initialized as FALSE by default */\r
break;\r
case USBFS_CLASS_AUDIO:\r
#if defined(USBFS_ENABLE_AUDIO_CLASS)\r
requestHandled = USBFS_DispatchAUDIOClassRqst();\r
- #endif /* USBFS_ENABLE_HID_CLASS */\r
+ #endif /* USBFS_CLASS_AUDIO */\r
break;\r
case USBFS_CLASS_CDC:\r
#if defined(USBFS_ENABLE_CDC_CLASS)\r
/*******************************************************************************\r
* File Name: USBFS_descr.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* USB descriptors and storage.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
/*****************************************************************************\r
* User supplied descriptors. If you want to specify your own descriptors,\r
-* remove the comments around the define USER_SUPPLIED_DESCRIPTORS below and\r
-* add your descriptors.\r
+* define USER_SUPPLIED_DESCRIPTORS below and add your descriptors.\r
*****************************************************************************/\r
/* `#START USER_DESCRIPTORS_DECLARATIONS` Place your declaration here */\r
\r
/*******************************************************************************\r
* File Name: USBFS_drv.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* Endpoint 0 Driver for the USBFS Component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: USBFS_episr.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* Data endpoint Interrupt Service Routines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
#include "USBFS.h"\r
#include "USBFS_pvt.h"\r
-#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)\r
+#if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u))\r
#include "USBFS_midi.h"\r
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/\r
+#endif /* (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)) */\r
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ #include "USBFS_EP8_DMA_Done_SR.h"\r
+ #include "USBFS_EP17_DMA_Done_SR.h"\r
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
\r
\r
/***************************************\r
******************************************************************************/\r
CY_ISR(USBFS_EP_1_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
uint8 int_en;\r
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
int_en = EA;\r
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) &\r
(uint8)~USBFS_SIE_EP_INT_EP1_MASK);\r
\r
- #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT )\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP1)\r
{\r
USBFS_MIDI_OUT_EP_Service();\r
}\r
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
/* `#START EP1_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 )\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
EA = int_en;\r
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
}\r
\r
-#endif /* End USBFS_EP1_ISR_REMOVE */\r
+#endif /* USBFS_EP1_ISR_REMOVE */\r
\r
\r
#if(USBFS_EP2_ISR_REMOVE == 0u)\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_2_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
uint8 int_en;\r
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 )\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
int_en = EA;\r
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
& (uint8)~USBFS_SIE_EP_INT_EP2_MASK);\r
\r
- #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT )\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP2)\r
{\r
USBFS_MIDI_OUT_EP_Service();\r
}\r
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
/* `#START EP2_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
EA = int_en;\r
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
}\r
\r
-#endif /* End USBFS_EP2_ISR_REMOVE */\r
+#endif /* USBFS_EP2_ISR_REMOVE */\r
\r
\r
#if(USBFS_EP3_ISR_REMOVE == 0u)\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_3_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
uint8 int_en;\r
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
int_en = EA;\r
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
& (uint8)~USBFS_SIE_EP_INT_EP3_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP3)\r
{\r
USBFS_MIDI_OUT_EP_Service();\r
}\r
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
/* `#START EP3_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
EA = int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
}\r
\r
-#endif /* End USBFS_EP3_ISR_REMOVE */\r
+#endif /* USBFS_EP3_ISR_REMOVE */\r
\r
\r
#if(USBFS_EP4_ISR_REMOVE == 0u)\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_4_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
uint8 int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
int_en = EA;\r
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
& (uint8)~USBFS_SIE_EP_INT_EP4_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP4)\r
{\r
USBFS_MIDI_OUT_EP_Service();\r
}\r
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
/* `#START EP4_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
EA = int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
}\r
\r
-#endif /* End USBFS_EP4_ISR_REMOVE */\r
+#endif /* USBFS_EP4_ISR_REMOVE */\r
\r
\r
#if(USBFS_EP5_ISR_REMOVE == 0u)\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_5_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
uint8 int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
int_en = EA;\r
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
& (uint8)~USBFS_SIE_EP_INT_EP5_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP5)\r
{\r
USBFS_MIDI_OUT_EP_Service();\r
}\r
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
/* `#START EP5_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
EA = int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
}\r
-#endif /* End USBFS_EP5_ISR_REMOVE */\r
+#endif /* USBFS_EP5_ISR_REMOVE */\r
\r
\r
#if(USBFS_EP6_ISR_REMOVE == 0u)\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_6_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
uint8 int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
int_en = EA;\r
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
& (uint8)~USBFS_SIE_EP_INT_EP6_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP6)\r
{\r
USBFS_MIDI_OUT_EP_Service();\r
}\r
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
/* `#START EP6_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
EA = int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
}\r
\r
-#endif /* End USBFS_EP6_ISR_REMOVE */\r
+#endif /* USBFS_EP6_ISR_REMOVE */\r
\r
\r
#if(USBFS_EP7_ISR_REMOVE == 0u)\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_7_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
uint8 int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
int_en = EA;\r
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
& (uint8)~USBFS_SIE_EP_INT_EP7_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP7)\r
{\r
USBFS_MIDI_OUT_EP_Service();\r
}\r
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
/* `#START EP7_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
EA = int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
}\r
\r
-#endif /* End USBFS_EP7_ISR_REMOVE */\r
+#endif /* USBFS_EP7_ISR_REMOVE */\r
\r
\r
#if(USBFS_EP8_ISR_REMOVE == 0u)\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_8_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
uint8 int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
int_en = EA;\r
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
& (uint8)~USBFS_SIE_EP_INT_EP8_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP8)\r
{\r
USBFS_MIDI_OUT_EP_Service();\r
}\r
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
/* `#START EP8_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
EA = int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
}\r
\r
-#endif /* End USBFS_EP8_ISR_REMOVE */\r
+#endif /* USBFS_EP8_ISR_REMOVE */\r
\r
\r
/*******************************************************************************\r
/* Clear Data ready status */\r
*(reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) &=\r
(uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+ #if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ /* Setup common area DMA with rest of the data */\r
+ if(USBFS_inLength[ep] > USBFS_DMA_BYTES_PER_BURST)\r
+ {\r
+ USBFS_LoadNextInEP(ep, 0u);\r
+ }\r
+ else\r
+ {\r
+ USBFS_inBufFull[ep] = 1u;\r
+ }\r
+ #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
/* Write the Mode register */\r
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), USBFS_EP[ep].epMode);\r
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN)\r
{ /* Clear MIDI input pointer */\r
USBFS_midiInPointer = 0u;\r
}\r
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/\r
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
}\r
}\r
/* (re)arm Out EP only for mode2 */\r
USBFS_EP[ep].epMode);\r
}\r
}\r
- #endif /* End USBFS_EP_MM */\r
+ #endif /* USBFS_EP_MM */\r
\r
/* `#START ARB_USER_CODE` Place your code here for handle Buffer Underflow/Overflow */\r
\r
/* `#END` */\r
}\r
\r
-#endif /* End USBFS_EP_MM */\r
+#endif /* USBFS_EP_MM */\r
+\r
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP_DMA_DONE_ISR\r
+ *******************************************************************************\r
+ *\r
+ * Summary:\r
+ * Endpoint 1 DMA Done Interrupt Service Routine\r
+ *\r
+ * Parameters:\r
+ * None.\r
+ *\r
+ * Return:\r
+ * None.\r
+ *\r
+ ******************************************************************************/\r
+ CY_ISR(USBFS_EP_DMA_DONE_ISR)\r
+ {\r
+ uint8 int8Status;\r
+ uint8 int17Status;\r
+ uint8 ep_status;\r
+ uint8 ep = USBFS_EP1;\r
+ uint8 ptr = 0u;\r
+\r
+ /* `#START EP_DMA_DONE_BEGIN_USER_CODE` Place your code here */\r
+\r
+ /* `#END` */\r
+\r
+ /* Read clear on read status register with the EP source of interrupt */\r
+ int17Status = USBFS_EP17_DMA_Done_SR_Read() & USBFS_EP17_SR_MASK;\r
+ int8Status = USBFS_EP8_DMA_Done_SR_Read() & USBFS_EP8_SR_MASK;\r
+\r
+ while(int8Status != 0u)\r
+ {\r
+ while(int17Status != 0u)\r
+ {\r
+ if((int17Status & 1u) != 0u) /* If EpX interrupt present */\r
+ {\r
+ /* Read Endpoint Status Register */\r
+ ep_status = CY_GET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr));\r
+ if( ((ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL) == 0u) &&\r
+ (USBFS_inBufFull[ep] == 0u))\r
+ {\r
+ /* `#START EP_DMA_DONE_USER_CODE` Place your code here */\r
+\r
+ /* `#END` */\r
+\r
+ CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ptr), 0x00u);\r
+ /* repeat 2 last bytes to prefetch endpoint area */\r
+ CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ptr),\r
+ USBFS_DMA_BYTES_PER_BURST * ep - USBFS_DMA_BYTES_REPEAT);\r
+ USBFS_LoadNextInEP(ep, 1);\r
+ /* Set Data ready status, This will generate DMA request */\r
+ * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+ }\r
+ }\r
+ ptr += USBFS_EPX_CNTX_ADDR_OFFSET; /* prepare pointer for next EP */\r
+ ep++;\r
+ int17Status >>= 1u;\r
+ }\r
+ int8Status >>= 1u;\r
+ if(int8Status != 0u)\r
+ {\r
+ /* Prepare pointer for EP8 */\r
+ ptr = ((USBFS_EP8 - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
+ ep = USBFS_EP8;\r
+ int17Status = int8Status & 0x01u;\r
+ }\r
+ }\r
+\r
+ /* `#START EP_DMA_DONE_END_USER_CODE` Place your code here */\r
+\r
+ /* `#END` */\r
+ }\r
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_hid.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* USB HID Class request handler.\r
*\r
+* Related Document:\r
+* Device Class Definition for Human Interface Devices (HID) Version 1.11\r
+*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
/* `#END` */\r
\r
-#endif /* End USBFS_ENABLE_HID_CLASS */\r
+#endif /* USBFS_ENABLE_HID_CLASS */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_hid.h\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
-* Header File for the USFS component. Contains prototypes and constant values.\r
+* Header File for the USBFS component. Contains prototypes and constant values.\r
+*\r
+* Related Document:\r
+* Device Class Definition for Human Interface Devices (HID) Version 1.11\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#define USBFS_HID_GET_REPORT_OUTPUT (0x02u)\r
#define USBFS_HID_GET_REPORT_FEATURE (0x03u)\r
\r
-#endif /* End CY_USBFS_USBFS_hid_H */\r
+#endif /* CY_USBFS_USBFS_hid_H */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_midi.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* MIDI Streaming request handler.\r
* This file contains routines for sending and receiving MIDI\r
* messages, and handles running status in both directions.\r
*\r
+* Related Document:\r
+* Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0\r
+* MIDI 1.0 Detailed Specification Document Version 4.2\r
+*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */\r
#else\r
volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */\r
- #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */\r
+ #endif /* (USBFS_MIDI_IN_BUFF_SIZE >= 256) */\r
volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */\r
uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */\r
-#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */\r
+#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
\r
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */\r
uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */\r
-#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */\r
+#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
static USBFS_MIDI_RX_STATUS USBFS_MIDI1_Event; /* MIDI RX status structure */\r
static USBFS_MIDI_RX_STATUS USBFS_MIDI2_Event; /* MIDI RX status structure */\r
static volatile uint8 USBFS_MIDI2_TxRunStat; /* MIDI Output running status */\r
volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
\r
/***************************************\r
{\r
#if (USBFS_MIDI_IN_BUFF_SIZE > 0)\r
USBFS_midiInPointer = 0u;\r
- #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */\r
+ #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
#if (USBFS_MIDI_IN_BUFF_SIZE > 0)\r
/* Init DMA configurations for IN EP*/\r
USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer,\r
USBFS_MIDI_IN_BUFF_SIZE);\r
- \r
- #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */\r
+\r
+ #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
/* Init DMA configurations for OUT EP*/\r
(void)USBFS_ReadOutEP(USBFS_midi_out_ep, USBFS_midiOutBuffer,\r
USBFS_MIDI_OUT_BUFF_SIZE);\r
- #endif /*USBFS_MIDI_OUT_BUFF_SIZE > 0 */\r
- #endif /* End USBFS__EP_DMAAUTO */\r
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
+ #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */\r
\r
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
USBFS_EnableOutEP(USBFS_midi_out_ep);\r
- #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */\r
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
\r
/* Initialize the MIDI port(s) */\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
USBFS_MIDI_Init();\r
- #endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
}\r
\r
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
#else\r
uint8 outLength;\r
uint8 outPointer;\r
- #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >=256 */\r
+ #endif /* USBFS_MIDI_OUT_BUFF_SIZE >=256 */\r
\r
uint8 dmaState = 0u;\r
\r
/* Service the USB MIDI output endpoint */\r
if (USBFS_GetEPState(USBFS_midi_out_ep) == USBFS_OUT_BUFFER_FULL)\r
{\r
- #if USBFS_MIDI_OUT_BUFF_SIZE >= 256\r
+ #if(USBFS_MIDI_OUT_BUFF_SIZE >= 256)\r
outLength = USBFS_GetEPCount(USBFS_midi_out_ep);\r
#else\r
outLength = (uint8)USBFS_GetEPCount(USBFS_midi_out_ep);\r
- #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */\r
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */\r
+\r
#if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
- #if USBFS_MIDI_OUT_BUFF_SIZE >= 256\r
+ #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256)\r
outLength = USBFS_ReadOutEP(USBFS_midi_out_ep,\r
USBFS_midiOutBuffer, outLength);\r
#else\r
outLength = (uint8)USBFS_ReadOutEP(USBFS_midi_out_ep,\r
USBFS_midiOutBuffer, (uint16)outLength);\r
- #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */\r
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */\r
+\r
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
do /* wait for DMA transfer complete */\r
{\r
- (void)CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState);\r
- }while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u);\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ (void) CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState);\r
+ }\r
+ while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u);\r
+ #endif /* (USBFS_EP_MM == USBFS__EP_DMAMANUAL) */\r
+\r
+ #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */\r
+\r
if(dmaState != 0u)\r
{\r
/* Suppress compiler warning */\r
}\r
+\r
if (outLength >= USBFS_EVENT_LENGTH)\r
{\r
outPointer = 0u;\r
{\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
USBFS_MIDI2_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]);\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
}\r
else\r
{\r
\r
/* `#END` */\r
}\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
/* Process any local MIDI output functions */\r
USBFS_callbackLocalMidiEvent(\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
/* Enable Out EP*/\r
USBFS_EnableOutEP(USBFS_midi_out_ep);\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */\r
}\r
}\r
\r
#else /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
/* rearm IN EP */\r
USBFS_LoadInEP(USBFS_midi_in_ep, NULL, (uint16)USBFS_midiInPointer);\r
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO*/\r
+ #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */\r
\r
/* Clear the midiInPointer. For DMA mode, clear this pointer in the ARB ISR when data are moved by DMA */\r
#if(USBFS_EP_MM == USBFS__EP_MANUAL)\r
USBFS_midiInPointer = 0u;\r
- #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */\r
+ #endif /* (USBFS_EP_MM == USBFS__EP_MANUAL) */\r
}\r
}\r
}\r
uint8 m2 = 0u;\r
do\r
{\r
- if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))\r
+ if (USBFS_midiInPointer <=\r
+ (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))\r
{\r
/* Check MIDI1 input port for a complete event */\r
m1 = USBFS_MIDI1_GetEvent();\r
}\r
\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
- if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))\r
+ if (USBFS_midiInPointer <=\r
+ (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))\r
{\r
/* Check MIDI2 input port for a complete event */\r
m2 = USBFS_MIDI2_GetEvent();\r
USBFS_MIDI2_Event.size, USBFS_MIDI_CABLE_01);\r
}\r
}\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
\r
- }while( (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))\r
- && ((m1 != 0u) || (m2 != 0u)) );\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ }while( (USBFS_midiInPointer <=\r
+ (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) &&\r
+ ((m1 != 0u) || (m2 != 0u)) );\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
/* Service the USB MIDI input endpoint */\r
USBFS_MIDI_IN_EP_Service();\r
MIDI1_UART_DisableRxInt();\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
MIDI2_UART_DisableRxInt();\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
if (USBFS_midiInPointer >\r
(USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))\r
(USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))\r
{\r
USBFS_MIDI_IN_EP_Service();\r
- if (USBFS_midiInPointer >\r
- (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))\r
+ if(USBFS_midiInPointer >\r
+ (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))\r
{\r
/* Error condition. HOST is not ready to receive this packet. */\r
retError = USBFS_TRUE;\r
break;\r
}\r
}\r
- }while(ic > USBFS_EVENT_BYTE3);\r
+ }\r
+ while(ic > USBFS_EVENT_BYTE3);\r
\r
if(retError == USBFS_FALSE)\r
{\r
MIDI1_UART_EnableRxInt();\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
MIDI2_UART_EnableRxInt();\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
return (retError);\r
}\r
/* Change the priority of the UART TX interrupt */\r
CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM);\r
CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM);\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/\r
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/\r
\r
/* `#START MIDI_INIT_CUSTOM` Init other extended UARTs here */\r
\r
uint8 rxData;\r
#if (MIDI1_UART_RXBUFFERSIZE >= 256u)\r
uint16 rxBufferRead;\r
- #if CY_PSOC3 /* This local variable is required only for PSOC3 and large buffer */\r
+ #if (CY_PSOC3) /* This local variable is required only for PSOC3 and large buffer */\r
uint16 rxBufferWrite;\r
- #endif /* end CY_PSOC3 */\r
+ #endif /* (CY_PSOC3) */\r
#else\r
uint8 rxBufferRead;\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* (MIDI1_UART_RXBUFFERSIZE >= 256u) */\r
+\r
uint8 rxBufferLoopDetect;\r
/* Read buffer loop condition to the local variable */\r
rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect;\r
/* Protect variables that could change on interrupt by disabling Rx interrupt.*/\r
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntDisable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
rxBufferRead = MIDI1_UART_rxBufferRead;\r
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
rxBufferWrite = MIDI1_UART_rxBufferWrite;\r
CyIntEnable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
\r
/* Stay here until either the buffer is empty or we have a complete message\r
* in the message buffer. Note that we must use a temporary buffer pointer\r
while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )\r
#else\r
while ( ((rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */\r
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
{\r
rxData = MIDI1_UART_rxBuffer[rxBufferRead];\r
/* Increment pointer with a wrap */\r
MIDI1_UART_rxBufferLoopDetect = 0u;\r
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntDisable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */\r
MIDI1_UART_rxBufferRead = rxBufferRead;\r
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntEnable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */\r
}\r
\r
msgRtn = USBFS_ProcessMidiIn(rxData,\r
*/\r
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntDisable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
MIDI1_UART_rxBufferRead = rxBufferRead;\r
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntEnable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
}\r
\r
return (msgRtn);\r
/* `#END` */\r
}\r
\r
+\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
\r
\r
uint8 rxData;\r
#if (MIDI2_UART_RXBUFFERSIZE >= 256u)\r
uint16 rxBufferRead;\r
- #if CY_PSOC3 /* This local variable required only for PSOC3 and large buffer */\r
+ #if (CY_PSOC3) /* This local variable required only for PSOC3 and large buffer */\r
uint16 rxBufferWrite;\r
- #endif /* end CY_PSOC3 */\r
+ #endif /* (CY_PSOC3) */\r
#else\r
uint8 rxBufferRead;\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* (MIDI2_UART_RXBUFFERSIZE >= 256) */\r
+\r
uint8 rxBufferLoopDetect;\r
/* Read buffer loop condition to the local variable */\r
rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect;\r
/* Protect variables that could change on interrupt by disabling Rx interrupt.*/\r
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntDisable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
rxBufferRead = MIDI2_UART_rxBufferRead;\r
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
rxBufferWrite = MIDI2_UART_rxBufferWrite;\r
CyIntEnable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
\r
/* Stay here until either the buffer is empty or we have a complete message\r
* in the message buffer. Note that we must use a temporary output pointer to\r
while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )\r
#else\r
while ( ((rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
{\r
rxData = MIDI2_UART_rxBuffer[rxBufferRead];\r
rxBufferRead++;\r
MIDI2_UART_rxBufferLoopDetect = 0u;\r
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntDisable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
MIDI2_UART_rxBufferRead = rxBufferRead;\r
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntEnable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
}\r
\r
msgRtn = USBFS_ProcessMidiIn(rxData,\r
*/\r
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntDisable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
MIDI2_UART_rxBufferRead = rxBufferRead;\r
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntEnable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
}\r
\r
return (msgRtn);\r
\r
/* `#END` */\r
}\r
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
-#endif /* End (USBFS_ENABLE_MIDI_API != 0u) */\r
+#endif /* (USBFS_ENABLE_MIDI_API != 0u) */\r
\r
\r
/* `#START MIDI_FUNCTIONS` Place any additional functions here */\r
\r
/* `#END` */\r
\r
-#endif /* End defined(USBFS_ENABLE_MIDI_STREAMING) */\r
+#endif /* defined(USBFS_ENABLE_MIDI_STREAMING) */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_midi.h\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* Header File for the USBFS MIDI module.\r
* Contains prototypes and constant values.\r
*\r
+* Related Document:\r
+* Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0\r
+* MIDI 1.0 Detailed Specification Document Version 4.2\r
+*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
\r
/***************************************\r
-* Data Struct Definition\r
+* Data Structure Definition\r
***************************************/\r
\r
/* The following structure is used to hold status information for\r
#define USBFS_CUSTOM_UART_TX_PRIOR_NUM (0x04u)\r
#define USBFS_CUSTOM_UART_RX_PRIOR_NUM (0x02u)\r
\r
-#define USBFS_ISR_SERVICE_MIDI_OUT \\r
+#define USBFS_ISR_SERVICE_MIDI_OUT \\r
( (USBFS_ENABLE_MIDI_API != 0u) && \\r
- (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO) )\r
+ (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO))\r
#define USBFS_ISR_SERVICE_MIDI_IN \\r
( (USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_IN_BUFF_SIZE > 0) )\r
\r
+\r
/***************************************\r
* External function references\r
***************************************/\r
\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
#include "MIDI1_UART.h"\r
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
#include "MIDI2_UART.h"\r
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
+#endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
#include <CyDmac.h>\r
-#endif /* End USBFS_EP_MM */\r
+#endif /* USBFS_EP_MM */\r
\r
\r
/***************************************\r
uint8 USBFS_MIDI2_GetEvent(void) ;\r
void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[])\r
;\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
+#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
\r
\r
/***************************************\r
extern volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */\r
#else\r
extern volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */\r
- #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */\r
+ #endif /* USBFS_MIDI_IN_BUFF_SIZE >=256 */\r
extern volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */\r
extern uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */\r
#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */\r
extern volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
extern volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
+#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
\r
#endif /* USBFS_ENABLE_MIDI_STREAMING */\r
\r
\r
-#endif /* End CY_USBFS_USBFS_midi_H */\r
+#endif /* CY_USBFS_USBFS_midi_H */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_pm.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* This file provides Suspend/Resume APIs functionality.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
#if(USBFS_DP_ISR_REMOVE == 0u)\r
\r
-\r
/*******************************************************************************\r
* Function Name: USBFS_DP_Interrupt\r
********************************************************************************\r
********************************************************************************\r
*\r
* Summary:\r
-* This function disables the USBFS block and prepares for power donwn mode.\r
+* This function disables the USBFS block and prepares for power down mode.\r
*\r
* Parameters:\r
* None.\r
\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */\r
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
/* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */\r
USBFS_USBIO_CR0_REG &= (uint8)~USBFS_USBIO_CR0_TEN;\r
/* Disable the SIE */\r
USBFS_CR0_REG &= (uint8)~USBFS_CR0_ENABLE;\r
\r
- CyDelayUs(0u); /*~50ns delay */\r
+ CyDelayUs(0u); /* ~50ns delay */\r
/* Store mode and Disable VRegulator*/\r
USBFS_backup.mode = USBFS_CR1_REG & USBFS_CR1_REG_ENABLE;\r
USBFS_CR1_REG &= (uint8)~USBFS_CR1_REG_ENABLE;\r
{\r
USBFS_backup.enableState = 0u;\r
}\r
+\r
CyExitCriticalSection(enableInterrupts);\r
\r
/* Set the DP Interrupt for wake-up from sleep mode. */\r
#if(USBFS_DP_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR);\r
+ (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR);\r
CyIntSetPriority(USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIOR);\r
CyIntClearPending(USBFS_DP_INTC_VECT_NUM);\r
CyIntEnable(USBFS_DP_INTC_VECT_NUM);\r
#endif /* (USBFS_DP_ISR_REMOVE == 0u) */\r
-\r
}\r
\r
\r
{\r
#if(USBFS_DP_ISR_REMOVE == 0u)\r
CyIntDisable(USBFS_DP_INTC_VECT_NUM);\r
- #endif /* End USBFS_DP_ISR_REMOVE */\r
+ #endif /* USBFS_DP_ISR_REMOVE */\r
\r
/* Enable USB block */\r
USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB;\r
/* Set the USBIO pull-up enable */\r
USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N;\r
\r
- /* Reinit Arbiter configuration for DMA transfers */\r
+ /* Re-init Arbiter configuration for DMA transfers */\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- /* usb arb interrupt enable */\r
+ /* Usb arb interrupt enable */\r
USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;\r
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
/*Set cfg cmplt this rises DMA request when the full configuration is done */\r
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
/* STALL_IN_OUT */\r
CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT);\r
\r
/* Restore USB register settings */\r
USBFS_RestoreConfig();\r
-\r
}\r
+\r
CyExitCriticalSection(enableInterrupts);\r
}\r
\r
/*******************************************************************************\r
* File Name: .h\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* This private file provides constants and parameter values for the\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
extern uint8 USBFS_DmaChan[USBFS_MAX_EP];\r
extern uint8 USBFS_DmaTd[USBFS_MAX_EP];\r
-#endif /* End USBFS_EP_MM */\r
+#endif /* USBFS_EP_MM */\r
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ extern uint8 USBFS_DmaNextTd[USBFS_MAX_EP];\r
+ extern const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP];\r
+ extern volatile uint16 USBFS_inLength[USBFS_MAX_EP];\r
+ extern const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];\r
+ extern volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];\r
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
\r
extern volatile uint8 USBFS_ep0Toggle;\r
extern volatile uint8 USBFS_lastPacketSize;\r
void USBFS_ConfigAltChanged(void) ;\r
void USBFS_ConfigReg(void) ;\r
\r
-const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)\r
+const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)\r
;\r
const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void)\r
;\r
void USBFS_SaveConfig(void) ;\r
void USBFS_RestoreConfig(void) ;\r
\r
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) ;\r
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+\r
#if defined(USBFS_ENABLE_IDSN_STRING)\r
void USBFS_ReadDieID(uint8 descr[]) ;\r
#endif /* USBFS_ENABLE_IDSN_STRING */\r
\r
#if defined(USBFS_ENABLE_HID_CLASS)\r
uint8 USBFS_DispatchHIDClassRqst(void);\r
-#endif /* End USBFS_ENABLE_HID_CLASS */\r
+#endif /* USBFS_ENABLE_HID_CLASS */\r
#if defined(USBFS_ENABLE_AUDIO_CLASS)\r
uint8 USBFS_DispatchAUDIOClassRqst(void);\r
-#endif /* End USBFS_ENABLE_HID_CLASS */\r
+#endif /* USBFS_ENABLE_HID_CLASS */\r
#if defined(USBFS_ENABLE_CDC_CLASS)\r
uint8 USBFS_DispatchCDCClassRqst(void);\r
-#endif /* End USBFS_ENABLE_CDC_CLASS */\r
+#endif /* USBFS_ENABLE_CDC_CLASS */\r
\r
CY_ISR_PROTO(USBFS_EP_0_ISR);\r
#if(USBFS_EP1_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_EP_1_ISR);\r
-#endif /* End USBFS_EP1_ISR_REMOVE */\r
+#endif /* USBFS_EP1_ISR_REMOVE */\r
#if(USBFS_EP2_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_EP_2_ISR);\r
-#endif /* End USBFS_EP2_ISR_REMOVE */\r
+#endif /* USBFS_EP2_ISR_REMOVE */\r
#if(USBFS_EP3_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_EP_3_ISR);\r
-#endif /* End USBFS_EP3_ISR_REMOVE */\r
+#endif /* USBFS_EP3_ISR_REMOVE */\r
#if(USBFS_EP4_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_EP_4_ISR);\r
-#endif /* End USBFS_EP4_ISR_REMOVE */\r
+#endif /* USBFS_EP4_ISR_REMOVE */\r
#if(USBFS_EP5_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_EP_5_ISR);\r
-#endif /* End USBFS_EP5_ISR_REMOVE */\r
+#endif /* USBFS_EP5_ISR_REMOVE */\r
#if(USBFS_EP6_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_EP_6_ISR);\r
-#endif /* End USBFS_EP6_ISR_REMOVE */\r
+#endif /* USBFS_EP6_ISR_REMOVE */\r
#if(USBFS_EP7_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_EP_7_ISR);\r
-#endif /* End USBFS_EP7_ISR_REMOVE */\r
+#endif /* USBFS_EP7_ISR_REMOVE */\r
#if(USBFS_EP8_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_EP_8_ISR);\r
-#endif /* End USBFS_EP8_ISR_REMOVE */\r
+#endif /* USBFS_EP8_ISR_REMOVE */\r
CY_ISR_PROTO(USBFS_BUS_RESET_ISR);\r
#if(USBFS_SOF_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_SOF_ISR);\r
-#endif /* End USBFS_SOF_ISR_REMOVE */\r
+#endif /* USBFS_SOF_ISR_REMOVE */\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
CY_ISR_PROTO(USBFS_ARB_ISR);\r
-#endif /* End USBFS_EP_MM */\r
+#endif /* USBFS_EP_MM */\r
#if(USBFS_DP_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_DP_ISR);\r
-#endif /* End USBFS_DP_ISR_REMOVE */\r
-\r
+#endif /* USBFS_DP_ISR_REMOVE */\r
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ CY_ISR_PROTO(USBFS_EP_DMA_DONE_ISR);\r
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
\r
/***************************************\r
* Request Handlers\r
/***************************************\r
* HID Internal references\r
***************************************/\r
+\r
#if defined(USBFS_ENABLE_HID_CLASS)\r
void USBFS_FindReport(void) ;\r
void USBFS_FindReportDescriptor(void) ;\r
/***************************************\r
* MIDI Internal references\r
***************************************/\r
+\r
#if defined(USBFS_ENABLE_MIDI_STREAMING)\r
void USBFS_MIDI_IN_EP_Service(void) ;\r
#endif /* USBFS_ENABLE_MIDI_STREAMING */\r
/*******************************************************************************\r
* File Name: USBFS_std.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* USB Standard request handler.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#include "USBFS.h"\r
#include "USBFS_cdc.h"\r
#include "USBFS_pvt.h"\r
-#if defined(USBFS_ENABLE_MIDI_STREAMING) \r
+#if defined(USBFS_ENABLE_MIDI_STREAMING)\r
#include "USBFS_midi.h"\r
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/\r
+#endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
\r
\r
/***************************************\r
\r
#if defined(USBFS_ENABLE_FWSN_STRING)\r
\r
-\r
/*******************************************************************************\r
* Function Name: USBFS_SerialNumString\r
********************************************************************************\r
USBFS_snStringConfirm = USBFS_FALSE;\r
if(snString != NULL)\r
{\r
- USBFS_fwSerialNumberStringDescriptor = snString;\r
/* Check descriptor validation */\r
if( (snString[0u] > 1u ) && (snString[1u] == USBFS_DESCR_STRING) )\r
{\r
+ USBFS_fwSerialNumberStringDescriptor = snString;\r
USBFS_snStringConfirm = USBFS_TRUE;\r
}\r
}\r
{\r
uint8 requestHandled = USBFS_FALSE;\r
uint8 interfaceNumber;\r
+ uint8 configurationN;\r
#if defined(USBFS_ENABLE_STRINGS)\r
volatile uint8 *pStr = 0u;\r
#if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS)\r
else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_CONFIG)\r
{\r
pTmp = USBFS_GetConfigTablePtr(CY_GET_REG8(USBFS_wValueLo));\r
- USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;\r
- USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \\r
- USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \\r
- (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];\r
- requestHandled = USBFS_InitControlRead();\r
+ if( pTmp != NULL ) /* Verify that requested descriptor exists */\r
+ {\r
+ USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;\r
+ USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \\r
+ USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \\r
+ (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];\r
+ requestHandled = USBFS_InitControlRead();\r
+ }\r
}\r
#if defined(USBFS_ENABLE_STRINGS)\r
else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_STRING)\r
pStr = &pStr[descrLength];\r
nStr++;\r
}\r
- #endif /* End USBFS_ENABLE_DESCRIPTOR_STRINGS */\r
+ #endif /* USBFS_ENABLE_DESCRIPTOR_STRINGS */\r
/* Microsoft OS String*/\r
#if defined(USBFS_ENABLE_MSOS_STRING)\r
if( CY_GET_REG8(USBFS_wValueLo) == USBFS_STRING_MSOS )\r
{\r
pStr = (volatile uint8 *)&USBFS_MSOS_DESCRIPTOR[0u];\r
}\r
- #endif /* End USBFS_ENABLE_MSOS_STRING*/\r
+ #endif /* USBFS_ENABLE_MSOS_STRING*/\r
/* SN string */\r
#if defined(USBFS_ENABLE_SN_STRING)\r
if( (CY_GET_REG8(USBFS_wValueLo) != 0u) &&\r
(CY_GET_REG8(USBFS_wValueLo) ==\r
USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT]) )\r
{\r
- pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];\r
- #if defined(USBFS_ENABLE_FWSN_STRING)\r
- if(USBFS_snStringConfirm != USBFS_FALSE)\r
- {\r
- pStr = USBFS_fwSerialNumberStringDescriptor;\r
- }\r
- #endif /* USBFS_ENABLE_FWSN_STRING */\r
+\r
#if defined(USBFS_ENABLE_IDSN_STRING)\r
/* Read DIE ID and generate string descriptor in RAM */\r
USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor);\r
pStr = USBFS_idSerialNumberStringDescriptor;\r
- #endif /* End USBFS_ENABLE_IDSN_STRING */\r
+ #elif defined(USBFS_ENABLE_FWSN_STRING)\r
+ if(USBFS_snStringConfirm != USBFS_FALSE)\r
+ {\r
+ pStr = USBFS_fwSerialNumberStringDescriptor;\r
+ }\r
+ else\r
+ {\r
+ pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];\r
+ }\r
+ #else\r
+ pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];\r
+ #endif /* defined(USBFS_ENABLE_IDSN_STRING) */\r
}\r
- #endif /* End USBFS_ENABLE_SN_STRING */\r
+ #endif /* USBFS_ENABLE_SN_STRING */\r
if (*pStr != 0u)\r
{\r
USBFS_currentTD.count = *pStr;\r
requestHandled = USBFS_InitControlRead();\r
}\r
}\r
- #endif /* End USBFS_ENABLE_STRINGS */\r
+ #endif /* USBFS_ENABLE_STRINGS */\r
else\r
{\r
requestHandled = USBFS_DispatchClassRqst();\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
break;\r
case USBFS_SET_CONFIGURATION:\r
- USBFS_configuration = CY_GET_REG8(USBFS_wValueLo);\r
- USBFS_configurationChanged = USBFS_TRUE;\r
- USBFS_Config(USBFS_TRUE);\r
- requestHandled = USBFS_InitNoDataControlTransfer();\r
+ configurationN = CY_GET_REG8(USBFS_wValueLo);\r
+ if(configurationN > 0u)\r
+ { /* Verify that configuration descriptor exists */\r
+ pTmp = USBFS_GetConfigTablePtr(configurationN - 1u);\r
+ }\r
+ /* Responds with a Request Error when configuration number is invalid */\r
+ if (((configurationN > 0u) && (pTmp != NULL)) || (configurationN == 0u))\r
+ {\r
+ /* Set new configuration if it has been changed */\r
+ if(configurationN != USBFS_configuration)\r
+ {\r
+ USBFS_configuration = configurationN;\r
+ USBFS_configurationChanged = USBFS_TRUE;\r
+ USBFS_Config(USBFS_TRUE);\r
+ }\r
+ requestHandled = USBFS_InitNoDataControlTransfer();\r
+ }\r
break;\r
case USBFS_SET_INTERFACE:\r
if (USBFS_ValidateAlternateSetting() != 0u)\r
USBFS_Config(USBFS_FALSE);\r
#else\r
USBFS_ConfigAltChanged();\r
- #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */\r
+ #endif /* (USBFS_EP_MA == USBFS__MA_DYNAMIC) */\r
/* Update handled Alt setting changes status */\r
USBFS_interfaceSetting_last[interfaceNumber] =\r
USBFS_interfaceSetting[interfaceNumber];\r
uint8 value;\r
const char8 CYCODE hex[16u] = "0123456789ABCDEF";\r
\r
-\r
/* Check descriptor validation */\r
if( descr != NULL)\r
{\r
}\r
}\r
\r
-#endif /* End USBFS_ENABLE_IDSN_STRING */\r
+#endif /* USBFS_ENABLE_IDSN_STRING */\r
\r
\r
/*******************************************************************************\r
uint8 ep;\r
uint8 i;\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- uint8 ep_type = 0u;\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ uint8 epType = 0u;\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
\r
/* Set the endpoint buffer addresses */\r
ep = USBFS_EP1;\r
for (i = 0u; i < 0x80u; i+= 0x10u)\r
{\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_CRC_BYPASS |\r
- USBFS_ARB_EPX_CFG_RESET);\r
-\r
+ CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_DEFAULT);\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
/* Enable all Arbiter EP Interrupts : err, buf under, buf over, dma gnt(mode2 only), in buf full */\r
CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_INT_EN_IND + i), USBFS_ARB_EPX_INT_MASK);\r
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
if(USBFS_EP[ep].epMode != USBFS_MODE_DISABLE)\r
{\r
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_OUT);\r
/* Prepare EP type mask for automatic memory allocation */\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- ep_type |= (uint8)(0x01u << (ep - USBFS_EP1));\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ epType |= (uint8)(0x01u << (ep - USBFS_EP1));\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
}\r
}\r
else\r
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);\r
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu);\r
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);\r
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
\r
ep++;\r
}\r
USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST; /* DMA burst threshold */\r
USBFS_DMA_THRES_MSB_REG = 0u;\r
USBFS_EP_ACTIVE_REG = USBFS_ARB_INT_MASK;\r
- USBFS_EP_TYPE_REG = ep_type;\r
+ USBFS_EP_TYPE_REG = epType;\r
/* Cfg_cmp bit set to 1 once configuration is complete. */\r
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM |\r
USBFS_ARB_CFG_CFG_CPM;\r
/* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */\r
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
\r
CY_SET_REG8(USBFS_SIE_EP_INT_EN_PTR, 0xFFu);\r
}\r
uint8 ep;\r
uint8 cur_ep;\r
uint8 i;\r
- uint8 ep_type;\r
+ uint8 epType;\r
const uint8 *pDescr;\r
#if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
uint16 buffCount = 0u;\r
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
\r
const T_USBFS_LUT CYCODE *pTmp;\r
const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP;\r
pEP = (T_USBFS_EP_SETTINGS_BLOCK *) pTmp->p_list;\r
for (i = 0u; i < ep; i++)\r
{\r
- /* Compare current Alternate setting with EP Alt*/\r
+ /* Compare current Alternate setting with EP Alt */\r
if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)\r
{\r
cur_ep = pEP->addr & USBFS_DIR_UNUSED;\r
- ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;\r
+ epType = pEP->attributes & USBFS_EP_TYPE_MASK;\r
if (pEP->addr & USBFS_DIR_IN)\r
{\r
/* IN Endpoint */\r
USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;\r
- USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?\r
+ USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;\r
#if defined(USBFS_ENABLE_CDC_CLASS)\r
if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||\r
(pEP->bMisc == USBFS_CLASS_CDC)) &&\r
- (ep_type != USBFS_EP_TYPE_INT))\r
+ (epType != USBFS_EP_TYPE_INT))\r
{\r
USBFS_cdc_data_in_ep = cur_ep;\r
}\r
- #endif /* End USBFS_ENABLE_CDC_CLASS*/\r
+ #endif /* USBFS_ENABLE_CDC_CLASS*/\r
#if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
(USBFS_MIDI_IN_BUFF_SIZE > 0) )\r
if((pEP->bMisc == USBFS_CLASS_AUDIO) &&\r
- (ep_type == USBFS_EP_TYPE_BULK))\r
+ (epType == USBFS_EP_TYPE_BULK))\r
{\r
USBFS_midi_in_ep = cur_ep;\r
}\r
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/\r
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
}\r
else\r
{\r
/* OUT Endpoint */\r
USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;\r
- USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?\r
+ USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;\r
#if defined(USBFS_ENABLE_CDC_CLASS)\r
if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||\r
(pEP->bMisc == USBFS_CLASS_CDC)) &&\r
- (ep_type != USBFS_EP_TYPE_INT))\r
+ (epType != USBFS_EP_TYPE_INT))\r
{\r
USBFS_cdc_data_out_ep = cur_ep;\r
}\r
- #endif /* End USBFS_ENABLE_CDC_CLASS*/\r
+ #endif /* USBFS_ENABLE_CDC_CLASS*/\r
#if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
(USBFS_MIDI_OUT_BUFF_SIZE > 0) )\r
if((pEP->bMisc == USBFS_CLASS_AUDIO) &&\r
- (ep_type == USBFS_EP_TYPE_BULK))\r
+ (epType == USBFS_EP_TYPE_BULK))\r
{\r
USBFS_midi_out_ep = cur_ep;\r
}\r
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/\r
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
}\r
USBFS_EP[cur_ep].bufferSize = pEP->bufferSize;\r
USBFS_EP[cur_ep].addr = pEP->addr;\r
}\r
pEP = &pEP[1u];\r
}\r
- #else /* Config for static EP memory allocation */\r
+ #else /* Configure for static EP memory allocation */\r
for (i = USBFS_EP1; i < USBFS_MAX_EP; i++)\r
{\r
/* p_list points the endpoint setting table. */\r
/* Compare current Alternate setting with EP Alt*/\r
if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)\r
{\r
- ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;\r
+ epType = pEP->attributes & USBFS_EP_TYPE_MASK;\r
if ((pEP->addr & USBFS_DIR_IN) != 0u)\r
{\r
/* IN Endpoint */\r
USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING;\r
- USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?\r
+ USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;\r
- /* Find and init CDC IN endpoint number */\r
+ /* Find and initialize CDC IN endpoint number */\r
#if defined(USBFS_ENABLE_CDC_CLASS)\r
if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||\r
(pEP->bMisc == USBFS_CLASS_CDC)) &&\r
- (ep_type != USBFS_EP_TYPE_INT))\r
+ (epType != USBFS_EP_TYPE_INT))\r
{\r
USBFS_cdc_data_in_ep = i;\r
}\r
- #endif /* End USBFS_ENABLE_CDC_CLASS*/\r
+ #endif /* USBFS_ENABLE_CDC_CLASS*/\r
#if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
(USBFS_MIDI_IN_BUFF_SIZE > 0) )\r
if((pEP->bMisc == USBFS_CLASS_AUDIO) &&\r
- (ep_type == USBFS_EP_TYPE_BULK))\r
+ (epType == USBFS_EP_TYPE_BULK))\r
{\r
USBFS_midi_in_ep = i;\r
}\r
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/\r
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
}\r
else\r
{\r
/* OUT Endpoint */\r
USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING;\r
- USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?\r
+ USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;\r
- /* Find and init CDC IN endpoint number */\r
+ /* Find and initialize CDC IN endpoint number */\r
#if defined(USBFS_ENABLE_CDC_CLASS)\r
if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||\r
(pEP->bMisc == USBFS_CLASS_CDC)) &&\r
- (ep_type != USBFS_EP_TYPE_INT))\r
+ (epType != USBFS_EP_TYPE_INT))\r
{\r
USBFS_cdc_data_out_ep = i;\r
}\r
- #endif /* End USBFS_ENABLE_CDC_CLASS*/\r
+ #endif /* USBFS_ENABLE_CDC_CLASS*/\r
#if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
(USBFS_MIDI_OUT_BUFF_SIZE > 0) )\r
if((pEP->bMisc == USBFS_CLASS_AUDIO) &&\r
- (ep_type == USBFS_EP_TYPE_BULK))\r
+ (epType == USBFS_EP_TYPE_BULK))\r
{\r
USBFS_midi_out_ep = i;\r
}\r
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/\r
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
}\r
USBFS_EP[i].addr = pEP->addr;\r
USBFS_EP[i].attrib = pEP->attributes;\r
\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
break; /* use first EP setting in Auto memory managment */\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
}\r
}\r
pEP = &pEP[1u];\r
}\r
}\r
- #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */\r
+ #endif /* (USBFS_EP_MA == USBFS__MA_DYNAMIC) */\r
\r
/* Init class array for each interface and interface number for each EP.\r
* It is used for handling Class specific requests directed to either an\r
USBFS_EP[ep].buffOffset = buffCount;\r
buffCount += USBFS_EP[ep].bufferSize;\r
}\r
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
\r
/* Configure hardware registers */\r
USBFS_ConfigReg();\r
uint8 ep;\r
uint8 cur_ep;\r
uint8 i;\r
- uint8 ep_type;\r
+ uint8 epType;\r
uint8 ri;\r
\r
const T_USBFS_LUT CYCODE *pTmp;\r
{\r
cur_ep = pEP->addr & USBFS_DIR_UNUSED;\r
ri = ((cur_ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
- ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;\r
+ epType = pEP->attributes & USBFS_EP_TYPE_MASK;\r
if ((pEP->addr & USBFS_DIR_IN) != 0u)\r
{\r
/* IN Endpoint */\r
USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;\r
- USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?\r
+ USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;\r
}\r
else\r
{\r
/* OUT Endpoint */\r
USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;\r
- USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?\r
+ USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;\r
}\r
/* Change the SIE mode for the selected EP to NAK ALL */\r
USBFS_EP[cur_ep].buffOffset & 0xFFu);\r
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ri),\r
USBFS_EP[cur_ep].buffOffset >> 8u);\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
}\r
/* Get next EP element */\r
pEP = &pEP[1u];\r
* This routine returns a pointer a configuration table entry\r
*\r
* Parameters:\r
-* c: Configuration Index\r
+* confIndex: Configuration Index\r
*\r
* Return:\r
-* Device Descriptor pointer.\r
+* Device Descriptor pointer or NULL when descriptor isn't exists.\r
*\r
*******************************************************************************/\r
-const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)\r
+const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)\r
\r
{\r
/* Device Table */\r
\r
/* The first entry points to the Device Descriptor,\r
* the rest configuration entries.\r
- */\r
- return( (const T_USBFS_LUT CYCODE *) pTmp[c + 1u].p_list );\r
+ * Set pointer to the first Configuration Descriptor\r
+ */\r
+ pTmp = &pTmp[1u];\r
+ /* For this table, c is the number of configuration descriptors */\r
+ if(confIndex >= pTmp->c) /* Verify that required configuration descriptor exists */\r
+ {\r
+ pTmp = (const T_USBFS_LUT CYCODE *) NULL;\r
+ }\r
+ else\r
+ {\r
+ pTmp = (const T_USBFS_LUT CYCODE *) pTmp[confIndex].p_list;\r
+ }\r
+\r
+ return( pTmp );\r
}\r
\r
\r
\r
{\r
const T_USBFS_LUT CYCODE *pTmp;\r
+ const uint8 CYCODE *pInterfaceClass;\r
uint8 currentInterfacesNum;\r
\r
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);\r
- currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];\r
- /* Third entry in the LUT starts the Interface Table pointers */\r
- /* The INTERFACE_CLASS table is located after all interfaces */\r
- pTmp = &pTmp[currentInterfacesNum + 2u];\r
- return( (const uint8 CYCODE *) pTmp->p_list );\r
+ if( pTmp != NULL )\r
+ {\r
+ currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];\r
+ /* Third entry in the LUT starts the Interface Table pointers */\r
+ /* The INTERFACE_CLASS table is located after all interfaces */\r
+ pTmp = &pTmp[currentInterfacesNum + 2u];\r
+ pInterfaceClass = (const uint8 CYCODE *) pTmp->p_list;\r
+ }\r
+ else\r
+ {\r
+ pInterfaceClass = (const uint8 CYCODE *) NULL;\r
+ }\r
+\r
+ return( pInterfaceClass );\r
}\r
\r
\r
/*******************************************************************************\r
* File Name: USBFS_vnd.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* USB vendor request handler.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
********************************************************************************\r
*\r
* Summary:\r
-* This routine provide users with a method to implement vendor specifc\r
+* This routine provide users with a method to implement vendor specific\r
* requests.\r
*\r
* To implement vendor specific requests, add your code in this function to\r
USBFS_currentTD.pData = (volatile uint8 *)&USBFS_MSOS_CONFIGURATION_DESCR[0u];\r
USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u];\r
requestHandled = USBFS_InitControlRead();\r
- #endif /* End USBFS_ENABLE_MSOS_STRING */\r
+ #endif /* USBFS_ENABLE_MSOS_STRING */\r
break;\r
default:\r
break;\r
*/\r
EXTERN(Reset)\r
\r
-/* Bring in the interrupt routines & vector */\r
+/* Bring in interrupt routines & vector */\r
EXTERN(main)\r
\r
-/* Bring in the meta data */\r
+/* Bring in meta data */\r
EXTERN(cy_meta_loader cy_bootloader cy_meta_loadable cy_meta_bootloader)\r
EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata)\r
\r
PROVIDE(__cy_heap_start = _end);\r
PROVIDE(__cy_region_num = (__cy_regions_end - __cy_regions) / 16);\r
PROVIDE(__cy_stack = ORIGIN(ram) + LENGTH(ram));\r
-PROVIDE(__cy_heap_end = __cy_stack - 0x2000);\r
+PROVIDE(__cy_heap_end = __cy_stack - 0x1000);\r
\r
\r
SECTIONS\r
/* Make sure we pulled in some reset code. */\r
ASSERT (. != __cy_reset, "No reset code");\r
\r
- /* Place the DMA initialization before text to ensure it gets placed in first 64K of flash */\r
+ /* Place DMA initialization before text to ensure it gets placed in first 64K of flash */\r
*(.dma_init)\r
ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash");\r
\r
__cy_heap_limit = .;\r
} >ram\r
\r
- .stack (__cy_stack - 0x2000) (NOLOAD) :\r
+ .stack (__cy_stack - 0x1000) (NOLOAD) :\r
{\r
__cy_stack_limit = .;\r
- . += 0x2000;\r
+ . += 0x1000;\r
} >ram\r
\r
/* Check if data + heap + stack exceeds RAM limit */\r
/*******************************************************************************\r
* File Name: core_cm3_psoc5.h\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides important type information for the PSoC5. This includes types\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: cyPm.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides an API for the power management.\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
\r
/*******************************************************************\r
-* Place your includes, defines and code here. Do not use merge\r
-* region below unless any component datasheet suggest to do so.\r
+* Place your includes, defines, and code here. Do not use the merge\r
+* region below unless any component datasheet suggests doing so.\r
*******************************************************************/\r
/* `#START CY_PM_HEADER_INCLUDE` */\r
\r
*\r
* Summary:\r
* This function is called in preparation for entering sleep or hibernate low\r
-* power modes. Saves all state of the clocking system that does not persist\r
-* during sleep/hibernate or that needs to be altered in preparation for\r
+* power modes. Saves all the states of the clocking system that do not persist\r
+* during sleep/hibernate or that need to be altered in preparation for\r
* sleep/hibernate. Shutdowns all the digital and analog clock dividers for the\r
* active power mode configuration.\r
*\r
cyPmClockBackup.imo2x = CY_PM_DISABLED;\r
}\r
\r
+ /* Master clock - save source */\r
+ cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK;\r
+\r
+ /* Switch Master clock's source from PLL's output to PLL's source */\r
+ if(CY_MASTER_SOURCE_PLL == cyPmClockBackup.masterClkSrc)\r
+ {\r
+ switch (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_PLL_SRC_MASK)\r
+ {\r
+ case CY_PM_CLKDIST_PLL_SRC_IMO:\r
+ CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO);\r
+ break;\r
+\r
+ case CY_PM_CLKDIST_PLL_SRC_XTAL:\r
+ CyMasterClk_SetSource(CY_MASTER_SOURCE_XTAL);\r
+ break;\r
+\r
+ case CY_PM_CLKDIST_PLL_SRC_DSI:\r
+ CyMasterClk_SetSource(CY_MASTER_SOURCE_DSI);\r
+ break;\r
+\r
+ default:\r
+ CYASSERT(0u != 0u);\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* PLL - check enable state, disable if needed */\r
+ if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE))\r
+ {\r
+ /* PLL is enabled - save state and disable */\r
+ cyPmClockBackup.pllEnableState = CY_PM_ENABLED;\r
+ CyPLL_OUT_Stop();\r
+ }\r
+ else\r
+ {\r
+ /* PLL is disabled - save state */\r
+ cyPmClockBackup.pllEnableState = CY_PM_DISABLED;\r
+ }\r
+\r
/* IMO - set appropriate frequency for LPM */\r
CyIMO_SetFreq(CY_PM_IMO_FREQ_LPM);\r
\r
/* IMO - save disabled state */\r
cyPmClockBackup.imoEnable = CY_PM_DISABLED;\r
\r
- /* IMO - enable */\r
+ /* Enable the IMO. Use software delay instead of the FTW-based inside */\r
CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE);\r
+\r
+ /* Settling time of the IMO is of the order of less than 6us */\r
+ CyDelayUs(6u);\r
}\r
\r
/* IMO - save the current IMOCLK source and set to IMO if not yet */\r
cyPmClockBackup.imoClkSrc =\r
(0u == (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO2X_SRC)) ? CY_IMO_SOURCE_DSI : CY_IMO_SOURCE_XTAL;\r
\r
- /* IMO - set IMOCLK source to MHz OSC */\r
+ /* IMO - set IMOCLK source to IMO */\r
CyIMO_SetSource(CY_IMO_SOURCE_IMO);\r
}\r
else\r
if(CY_PM_DIV_BY_ONE != cyPmClockBackup.clkSyncDiv)\r
{\r
CyMasterClk_SetDivider(CY_PM_DIV_BY_ONE);\r
- } /* Need to change nothing if master clock divider is 1 */\r
-\r
- /* Master clock - save current source */\r
- cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK;\r
+ } /* No change if master clock divider is 1 */\r
\r
/* Master clock source - set it to IMO if not yet. */\r
if(CY_MASTER_SOURCE_IMO != cyPmClockBackup.masterClkSrc)\r
{\r
CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO);\r
- } /* Need to change nothing if master clock source is IMO */\r
+ } /* No change if master clock source is IMO */\r
\r
/* Bus clock - save divider and set it, if needed, to divide-by-one */\r
cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u);\r
CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE);\r
} /* Do nothing if saved and actual values are equal */\r
\r
- /* Set number of wait cycles for the flash according CPU frequency in MHz */\r
+ /* Set number of wait cycles for flash according to CPU frequency in MHz */\r
CyFlash_SetWaitCycles((uint8)CY_PM_GET_CPU_FREQ_MHZ);\r
\r
- /* PLL - check enable state, disable if needed */\r
- if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE))\r
- {\r
- /* PLL is enabled - save state and disable */\r
- cyPmClockBackup.pllEnableState = CY_PM_ENABLED;\r
- CyPLL_OUT_Stop();\r
- }\r
- else\r
- {\r
- /* PLL is disabled - save state */\r
- cyPmClockBackup.pllEnableState = CY_PM_DISABLED;\r
- }\r
-\r
/* MHz ECO - check enable state and disable if needed */\r
if(0u != (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_ENABLE))\r
{\r
\r
\r
/***************************************************************************\r
- * Save enable state of delay between the system bus clock and each of the\r
- * 4 individual analog clocks. This bit non-retention and it's value should\r
+ * Save the enable state of delay between the system bus clock and each of the\r
+ * 4 individual analog clocks. This bit non-retention and its value should\r
* be restored on wakeup.\r
***************************************************************************/\r
if(0u != (CY_PM_CLKDIST_DELAY_REG & CY_PM_CLKDIST_DELAY_EN))\r
*\r
* PSoC 3 and PSoC 5LP:\r
* The merge region could be used to process state when the megahertz crystal is\r
-* not ready after the hold-off timeout.\r
+* not ready after a hold-off timeout.\r
*\r
* PSoC 5:\r
-* The 130 ms is given for the megahertz crystal to stabilize. It's readiness is\r
-* not verified after the hold-off timeout.\r
+* The 130 ms is given for the megahertz crystal to stabilize. Its readiness is\r
+* not verified after a hold-off timeout.\r
*\r
* Parameters:\r
* None\r
CY_IMO_FREQ_12MHZ, CY_IMO_FREQ_6MHZ, CY_IMO_FREQ_24MHZ, CY_IMO_FREQ_3MHZ,\r
CY_IMO_FREQ_48MHZ, 5u, 6u};\r
\r
- /* Restore enable state of delay between the system bus clock and ACLKs. */\r
+ /* Restore enable state of delay between system bus clock and ACLKs. */\r
if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay)\r
{\r
- /* Delay for both the bandgap and the delay line to settle out */\r
+ /* Delay for both bandgap and delay line to settle out */\r
CyDelayCycles((uint32)(CY_PM_CLK_DELAY_BANDGAP_SETTLE_US + CY_PM_CLK_DELAY_BIAS_SETTLE_US) *\r
CY_PM_GET_CPU_FREQ_MHZ);\r
\r
if(CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState)\r
{\r
/***********************************************************************\r
- * Enabling XMHZ XTAL. The actual CyXTAL_Start() with non zero wait\r
+ * Enabling XMHZ XTAL. The actual CyXTAL_Start() with a non zero wait\r
* period uses FTW for period measurement. This could cause a problem\r
* if CTW/FTW is used as a wake up time in the low power modes APIs.\r
* So, the XTAL wait procedure is implemented with a software delay.\r
{\r
/*******************************************************************\r
* Process the situation when megahertz crystal is not ready.\r
- * Time to stabialize value is crystal specific.\r
+ * Time to stabilize the value is crystal specific.\r
*******************************************************************/\r
/* `#START_MHZ_ECO_TIMEOUT` */\r
\r
} /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */\r
\r
\r
- /* Temprorary set the maximum flash wait cycles */\r
+ /* Temprorary set maximum flash wait cycles */\r
CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES);\r
\r
- /* The XTAL and DSI clocks are ready to be source for Master clock. */\r
+ /* XTAL and DSI clocks are ready to be source for Master clock. */\r
if((CY_PM_MASTER_CLK_SRC_XTAL == cyPmClockBackup.masterClkSrc) ||\r
(CY_PM_MASTER_CLK_SRC_DSI == cyPmClockBackup.masterClkSrc))\r
{\r
CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE);\r
}\r
\r
- /* IMO - restore disable state if needed */\r
- if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) &&\r
- (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)))\r
- {\r
- CyIMO_Stop();\r
- }\r
-\r
/* IMO - restore IMOCLK source */\r
CyIMO_SetSource(cyPmClockBackup.imoClkSrc);\r
\r
cyPmClockBackup.clkImoSrc;\r
}\r
\r
+\r
/* PLL restore state */\r
if(CY_PM_ENABLED == cyPmClockBackup.pllEnableState)\r
{\r
* as a wakeup time in the low power modes APIs. To omit this issue PLL\r
* wait procedure is implemented with a software delay.\r
***********************************************************************/\r
+ status = CYRET_TIMEOUT;\r
\r
/* Enable PLL */\r
(void) CyPLL_OUT_Start(CY_PM_PLL_OUT_NO_WAIT);\r
\r
- /* Make a 250 us delay */\r
- CyDelayCycles((uint32)CY_PM_WAIT_250_US * CY_PM_GET_CPU_FREQ_MHZ);\r
+ /* Read to clear lock status after delay */\r
+ CyDelayUs((uint32)80u);\r
+ (void) CY_PM_FASTCLK_PLL_SR_REG;\r
+\r
+ /* It should take 250 us lock: 251-80 = 171 */\r
+ for(i = 171u; i > 0u; i--)\r
+ {\r
+ CyDelayUs((uint32)1u);\r
+\r
+ /* Accept PLL is OK after two consecutive polls indicate PLL lock */\r
+ if((0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED)) &&\r
+ (0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED)))\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ break;\r
+ }\r
+ }\r
+\r
+ if(CYRET_TIMEOUT == status)\r
+ {\r
+ /*******************************************************************\r
+ * Process the situation when PLL is not ready.\r
+ *******************************************************************/\r
+ /* `#START_PLL_TIMEOUT` */\r
+\r
+ /* `#END` */\r
+ }\r
} /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */\r
\r
\r
CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc);\r
}\r
\r
+ /* IMO - disable if it was originally disabled */\r
+ if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) &&\r
+ (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)))\r
+ {\r
+ CyIMO_Stop();\r
+ }\r
+\r
/* Bus clock - restore divider, if needed */\r
clkBusDivTmp = (uint16) ((uint16)CY_PM_CLK_BUS_MSB_DIV_REG << 8u);\r
clkBusDivTmp |= CY_PM_CLK_BUS_LSB_DIV_REG;\r
* Sleep Timer component and one second interval should be configured with the\r
* RTC component.\r
*\r
-* The wakeup behavior depends on wakeupSource parameter in the following\r
+* The wakeup behavior depends on the wakeupSource parameter in the following\r
* manner: upon function execution the device will be switched from Active to\r
* Alternate Active mode and then the CPU will be halted. When an enabled wakeup\r
* event occurs the device will return to Active mode. Similarly when an\r
For PSoC 3 silicon the valid range of values is 1 to 256.\r
*\r
* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if\r
-* a wakeupTime has been specified the associated timer will be\r
+* a wakeupTime has been specified, the associated timer will be\r
* included as a wakeup source.\r
*\r
* Define Source\r
* *Note : FTW and HVI/LVI wakeup signals are in the same mask bit.\r
* **Note: CTW and One PPS wakeup signals are in the same mask bit.\r
*\r
-* When specifying a Comparator as the wakeupSource an instance specific define\r
-* should be used that will track with the specific comparator that the instance\r
-* is placed into. As an example, for a Comparator instance named MyComp the\r
+* When specifying a Comparator as the wakeupSource, an instance specific define\r
+* that will track with the specific comparator that the instance\r
+* is placed into should be used. As an example, for a Comparator instance named MyComp the\r
* value to OR into the mask is: MyComp_ctComp__CMP_MASK.\r
*\r
* When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus()\r
-* function must be called upon wakeup with corresponding parameter. Please\r
+* function must be called upon wakeup with a corresponding parameter. Please\r
* refer to the CyPmReadStatus() API in the System Reference Guide for more\r
* information.\r
*\r
* If a wakeupTime other than NONE is specified, then upon exit the state of the\r
* specified timer will be left as specified by wakeupTime with the timer\r
* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is\r
-* used as wakeup time) or ILO 100 KHz (if FTW timer is used as wakeup time)\r
+* used as wakeup time) or ILO 100 KHz (if the FTW timer is used as wakeup time)\r
* will be left started.\r
*\r
*******************************************************************************/\r
{\r
CyPmFtwSetInterval(PM_ALT_ACT_FTW_INTERVAL(wakeupTime));\r
\r
- /* Include associated timer to the wakeupSource */\r
+ /* Include associated timer to wakeupSource */\r
wakeupSource |= PM_ALT_ACT_SRC_FTW;\r
}\r
\r
/* Save current CTW configuration and set new one */\r
CyPmCtwSetInterval((uint8)(wakeupTime - 1u));\r
\r
- /* Include associated timer to the wakeupSource */\r
+ /* Include associated timer to wakeupSource */\r
wakeupSource |= PM_ALT_ACT_SRC_CTW;\r
}\r
\r
/* Save current 1PPS configuration and set new one */\r
CyPmOppsSet();\r
\r
- /* Include associated timer to the wakeupSource */\r
+ /* Include associated timer to wakeupSource */\r
wakeupSource |= PM_ALT_ACT_SRC_ONE_PPS;\r
}\r
\r
* Puts the part into the Sleep state.\r
*\r
* Note Before calling this function, you must manually configure the power\r
-* mode of the source clocks for the timer that is used as wakeup timer.\r
+* mode of the source clocks for the timer that is used as the wakeup timer.\r
*\r
* Note Before calling this function, you must prepare clock tree configuration\r
* for the low power mode by calling CyPmSaveClocks(). And restore clock\r
* PSoC 3:\r
* Before switching to Sleep, if a wakeupTime other than NONE is specified,\r
* then the appropriate timer state is configured as specified with the\r
-* interrupt for that timer disabled. The wakeup source will be the combination\r
+* interrupt for that timer disabled. The wakeup source will be a combination\r
* of the values specified in the wakeupSource and any timer specified in the\r
* wakeupTime argument. Once the wakeup condition is satisfied, then all saved\r
* state is restored and the function returns in the Active state.\r
* The wakeupTime parameter is not used and the only NONE can be specified.\r
* The wakeup time must be configured with the component, SleepTimer for CTW\r
* intervals and RTC for 1PPS interval. The component must be configured to\r
-* generate an interrrupt.\r
+* generate interrupt.\r
*\r
* Parameters:\r
* wakeupTime: Specifies a timer wakeup source and the frequency of that\r
* detect (power supply supervising capabilities) are required in a design\r
* during sleep, use the Central Time Wheel (CTW) to periodically wake the\r
* device, perform software buzz, and refresh the supervisory services. If LVI,\r
-* HVI, or Brown Out is not required, then use of the CTW is not required.\r
+* HVI, or Brown Out is not required, then CTW is not required.\r
* Refer to the device errata for more information.\r
*\r
*******************************************************************************/\r
\r
/***********************************************************************\r
* PSoC3 < TO6:\r
- * - Hardware buzz must be disabled before sleep mode entry.\r
+ * - Hardware buzz must be disabled before the sleep mode entry.\r
* - Voltage supervision (HVI/LVI) requires hardware buzz, so they must\r
- * be aslo disabled.\r
+ * be also disabled.\r
*\r
* PSoC3 >= TO6:\r
- * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware buzz must be\r
- * enabled before sleep mode entry and restored on wakeup.\r
+ * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware\r
+ * buzz must be enabled before the sleep mode entry and restored on\r
+ * the wakeup.\r
***********************************************************************/\r
#if(CY_PSOC3)\r
\r
\r
\r
/*******************************************************************************\r
- * For ARM-based devices, an interrupt is required for the CPU to wake up. The\r
+ * For ARM-based devices,interrupt is required for the CPU to wake up. The\r
* Power Management implementation assumes that wakeup time is configured with a\r
- * separate component (component-based wakeup time configuration) for an\r
+ * separate component (component-based wakeup time configuration) for\r
* interrupt to be issued on terminal count. For more information, refer to the\r
* Wakeup Time Configuration section of System Reference Guide.\r
*******************************************************************************/\r
/* CTW - save current and set new configuration */\r
if((wakeupTime >= PM_SLEEP_TIME_CTW_2MS) && (wakeupTime <= PM_SLEEP_TIME_CTW_4096MS))\r
{\r
- /* Save current and set new configuration of the CTW */\r
+ /* Save current and set new configuration of CTW */\r
CyPmCtwSetInterval((uint8)(wakeupTime - 1u));\r
\r
- /* Include associated timer to the wakeupSource */\r
+ /* Include associated timer to wakeupSource */\r
wakeupSource |= PM_SLEEP_SRC_CTW;\r
}\r
\r
/* Save current and set new configuration of the 1PPS */\r
CyPmOppsSet();\r
\r
- /* Include associated timer to the wakeupSource */\r
+ /* Include associated timer to wakeupSource */\r
wakeupSource |= PM_SLEEP_SRC_ONE_PPS;\r
}\r
\r
\r
\r
/*******************************************************************\r
- * Do not use merge region below unless any component datasheet\r
- * suggest to do so.\r
+ * Do not use the merge region below unless any component datasheet\r
+ * suggests doing so.\r
*******************************************************************/\r
/* `#START CY_PM_JUST_BEFORE_SLEEP` */\r
\r
CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK));\r
}\r
\r
- /* Switch to the Sleep mode */\r
+ /* Switch to Sleep mode */\r
CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_SLEEP);\r
\r
/* Recommended readback. */\r
(void) CY_PM_MODE_CSR_REG;\r
\r
- /* Two recommended NOPs to get into the mode. */\r
+ /* Two recommended NOPs to get into mode. */\r
CY_NOP;\r
CY_NOP;\r
\r
* PSoC 3 and PSoC 5LP:\r
* Before switching to Hibernate, the current status of the PICU wakeup source\r
* bit is saved and then set. This configures the device to wake up from the\r
-* PICU. Make sure you have at least one pin configured to generate a PICU\r
+* PICU. Make sure you have at least one pin configured to generate PICU\r
* interrupt. For pin Px.y, the register "PICU_INTTYPE_PICUx_INTTYPEy" controls\r
* the PICU behavior. In the TRM, this register is "PICU[0..15]_INTTYPE[0..7]."\r
* In the Pins component datasheet, this register is referred to as the IRQ\r
* requirement begins when the device wakes up. There is no hardware check that\r
* this requirement is met. The specified delay should be done on ISR entry.\r
*\r
-* After wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is\r
+* After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is\r
* instance name of the Pins component) function must be called to clear the\r
-* latched pin events to allow proper Hibernate mode entry andd to enable\r
+* latched pin events to allow the proper Hibernate mode entry and to enable\r
* detection of future events.\r
*\r
* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to\r
* measure Hibernate/Sleep regulator settling time after a reset. The holdoff\r
-* delay is measured using rising edges of the 1 kHz ILO.\r
+* delay is measured using the rising edges of the 1 kHz ILO.\r
*\r
*******************************************************************************/\r
void CyPmHibernate(void) \r
\r
/***********************************************************************\r
* The Hibernate/Sleep regulator has a settling time after a reset.\r
- * During this time, the system ignores requests to enter Sleep and\r
- * Hibernate modes. The holdoff delay is measured using rising edges of\r
+ * During this time, the system ignores requests to enter the Sleep and\r
+ * Hibernate modes. The holdoff delay is measured using the rising edges of\r
* the 1 kHz ILO.\r
***********************************************************************/\r
if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q))\r
/* Recommended readback. */\r
(void) CY_PM_MODE_CSR_REG;\r
\r
- /* Two recommended NOPs to get into the mode. */\r
+ /* Two recommended NOPs to get into mode. */\r
CY_NOP;\r
CY_NOP;\r
\r
/* Enter critical section */\r
interruptState = CyEnterCriticalSection();\r
\r
- /* Save value of the register, copy it and clear desired bit */\r
+ /* Save value of register, copy it and clear desired bit */\r
interruptStatus |= CY_PM_INT_SR_REG;\r
tmpStatus = interruptStatus;\r
interruptStatus &= ((uint8)(~mask));\r
if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP))\r
{\r
/***********************************************************************\r
- * If I2C backup regulator is enabled, all the fixed-function registers\r
- * store their values while device is in low power mode, otherwise their\r
+ * If the I2C backup regulator is enabled, all the fixed-function registers\r
+ * store their values while the device is in the low power mode, otherwise their\r
* configuration is lost. The I2C API makes a decision to restore or not\r
* to restore I2C registers based on this. If this regulator will be\r
- * disabled and then enabled, I2C API will suppose that I2C block\r
+ * disabled and then enabled, I2C API will suppose that the I2C block\r
* registers preserved their values, while this is not true. So, the\r
* backup regulator is disabled. The I2C sleep APIs is responsible for\r
* restoration.\r
\r
\r
/***************************************************************************\r
- * Save and set power mode wakeup trim registers\r
+ * Save and set the power mode wakeup trim registers\r
***************************************************************************/\r
cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG;\r
cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG;\r
********************************************************************************\r
*\r
* Summary:\r
-* Restore device for proper Hibernate mode exit:\r
-* - Restore LVI/HVI configuration - call CyPmHviLviRestore()\r
+* Restores the device for the proper Hibernate mode exit:\r
+* - Restores LVI/HVI configuration - calsl CyPmHviLviRestore()\r
* - CyPmHibSlpSaveRestore() function is called\r
-* - Restores ILO power down mode state and enable it\r
-* - Restores state of 1 kHz and 100 kHz ILO and disable them\r
-* - Restores sleep regulator settings\r
+* - Restores ILO power down mode state and enables it\r
+* - Restores the state of 1 kHz and 100 kHz ILO and disables them\r
+* - Restores the sleep regulator settings\r
*\r
* Parameters:\r
* None\r
\r
\r
/***************************************************************************\r
- * Restore power mode wakeup trim registers\r
+ * Restore the power mode wakeup trim registers\r
***************************************************************************/\r
CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0;\r
CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1;\r
********************************************************************************\r
*\r
* Summary:\r
-* Performs CTW configuration:\r
-* - Disables CTW interrupt\r
+* Performs the CTW configuration:\r
+* - Disables the CTW interrupt\r
* - Enables 1 kHz ILO\r
-* - Sets new CTW interval\r
+* - Sets a new CTW interval\r
*\r
* Parameters:\r
* ctwInterval: the CTW interval to be set.\r
/* Set CTW interval if needed */\r
if(CY_PM_TW_CFG1_REG != ctwInterval)\r
{\r
- /* Set the new CTW interval. Could be changed if CTW is disabled */\r
+ /* Set new CTW interval. Could be changed if CTW is disabled */\r
CY_PM_TW_CFG1_REG = ctwInterval;\r
} /* Required interval is already set */\r
\r
- /* Enable the CTW */\r
+ /* Enable CTW */\r
CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN;\r
}\r
}\r
* Summary:\r
* Performs 1PPS configuration:\r
* - Starts 32 KHz XTAL\r
-* - Disables 1PPS interupts\r
+* - Disables 1PPS interrupts\r
* - Enables 1PPS\r
*\r
* Parameters:\r
********************************************************************************\r
*\r
* Summary:\r
-* Performs FTW configuration:\r
-* - Disables FTW interrupt\r
+* Performs the FTW configuration:\r
+* - Disables the FTW interrupt\r
* - Enables 100 kHz ILO\r
-* - Sets new FTW interval.\r
+* - Sets a new FTW interval.\r
*\r
* Parameters:\r
* ftwInterval - FTW counter interval.\r
* None\r
*\r
* Side Effects:\r
-* Enables ILO 100 KHz clock and leaves it enabled.\r
+* Enables the ILO 100 KHz clock and leaves it enabled.\r
*\r
*******************************************************************************/\r
void CyPmFtwSetInterval(uint8 ftwInterval) \r
/* Enable 100kHz ILO */\r
CyILO_Start100K();\r
\r
- /* Iterval could be set only while FTW is disabled */\r
+ /* Interval could be set only while FTW is disabled */\r
if(0u != (CY_PM_TW_CFG2_REG & CY_PM_FTW_EN))\r
{\r
/* Disable FTW, set new FTW interval if needed and enable it again */\r
if(CY_PM_TW_CFG0_REG != ftwInterval)\r
{\r
- /* Disable the CTW, set new CTW interval and enable it again */\r
+ /* Disable CTW, set new CTW interval and enable it again */\r
CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_EN));\r
CY_PM_TW_CFG0_REG = ftwInterval;\r
CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN;\r
/* Set new FTW counter interval if needed. FTW is disabled. */\r
if(CY_PM_TW_CFG0_REG != ftwInterval)\r
{\r
- /* Set the new CTW interval. Could be changed if CTW is disabled */\r
+ /* Set new CTW interval. Could be changed if CTW is disabled */\r
CY_PM_TW_CFG0_REG = ftwInterval;\r
} /* Required interval is already set */\r
\r
- /* Enable the FTW */\r
+ /* Enable FTW */\r
CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN;\r
}\r
}\r
********************************************************************************\r
*\r
* Summary:\r
-* This API is used for preparing device for Sleep and Hibernate low power\r
+* This API is used for preparing the device for the Sleep and Hibernate low power\r
* modes entry:\r
-* - Saves COMP, VIDAC, DSM and SAR routing connections (PSoC 5)\r
-* - Saves SC/CT routing connections (PSoC 3/5/5LP)\r
-* - Disables Serial Wire Viewer (SWV) (PSoC 3)\r
-* - Save boost reference selection and set it to internal\r
+* - Saves the COMP, VIDAC, DSM, and SAR routing connections (PSoC 5)\r
+* - Saves the SC/CT routing connections (PSoC 3/5/5LP)\r
+* - Disables the Serial Wire Viewer (SWV) (PSoC 3)\r
+* - Saves the boost reference selection and sets it to internal\r
*\r
* Parameters:\r
* None\r
********************************************************************************\r
*\r
* Summary:\r
-* This API is used for restoring device configurations after wakeup from Sleep\r
+* This API is used for restoring the device configurations after wakeup from the Sleep\r
* and Hibernate low power modes:\r
-* - Restores SC/CT routing connections\r
-* - Restores enable state of Serial Wire Viewer (SWV) (PSoC 3)\r
-* - Restore boost reference selection\r
+* - Restores the SC/CT routing connections\r
+* - Restores the enable state of the Serial Wire Viewer (SWV) (PSoC 3)\r
+* - Restores the boost reference selection\r
*\r
* Parameters:\r
* None\r
cyPmBackup.lvidEn = CY_PM_ENABLED;\r
cyPmBackup.lvidTrip = CY_VD_LVI_TRIP_REG & CY_VD_LVI_TRIP_LVID_MASK;\r
\r
- /* Save state of reset device at a specified Vddd threshold */\r
+ /* Save state of reset device at specified Vddd threshold */\r
cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \\r
CY_PM_DISABLED : CY_PM_ENABLED;\r
\r
cyPmBackup.lviaEn = CY_PM_ENABLED;\r
cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u;\r
\r
- /* Save state of reset device at a specified Vdda threshold */\r
+ /* Save state of reset device at specified Vdda threshold */\r
cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \\r
CY_PM_DISABLED : CY_PM_ENABLED;\r
\r
********************************************************************************\r
*\r
* Summary:\r
-* Restores analog and digital LVI and HVI configuration.\r
+* Restores the analog and digital LVI and HVI configuration.\r
*\r
* Parameters:\r
* None\r
/*******************************************************************************\r
* File Name: cyPm.h\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides the function definitions for the power management API.\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
#if(CY_PSOC3)\r
\r
- /* Wake up time for the Sleep mode */\r
+ /* Wake up time for Sleep mode */\r
#define PM_SLEEP_TIME_ONE_PPS (0x01u)\r
#define PM_SLEEP_TIME_CTW_2MS (0x02u)\r
#define PM_SLEEP_TIME_CTW_4MS (0x03u)\r
/* Difference between parameter's value and register's one */\r
#define CY_PM_FTW_INTERVAL_SHIFT (0x000Eu)\r
\r
- /* Wake up time for the Alternate Active mode */\r
+ /* Wake up time for Alternate Active mode */\r
#define PM_ALT_ACT_TIME_ONE_PPS (0x0001u)\r
#define PM_ALT_ACT_TIME_CTW_2MS (0x0002u)\r
#define PM_ALT_ACT_TIME_CTW_4MS (0x0003u)\r
#endif /* (CY_PSOC3) */\r
\r
\r
-/* Wake up sources for the Sleep mode */\r
+/* Wake up sources for Sleep mode */\r
#define PM_SLEEP_SRC_COMPARATOR0 (0x0001u)\r
#define PM_SLEEP_SRC_COMPARATOR1 (0x0002u)\r
#define PM_SLEEP_SRC_COMPARATOR2 (0x0004u)\r
#define PM_SLEEP_SRC_ONE_PPS (0x0800u)\r
#define PM_SLEEP_SRC_LCD (0x1000u)\r
\r
-/* Wake up sources for the Alternate Active mode */\r
+/* Wake up sources for Alternate Active mode */\r
#define PM_ALT_ACT_SRC_COMPARATOR0 (0x0001u)\r
#define PM_ALT_ACT_SRC_COMPARATOR1 (0x0002u)\r
#define PM_ALT_ACT_SRC_COMPARATOR2 (0x0004u)\r
#define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (5u)\r
\r
\r
-/* Delay line bandgap current settling time starting from a wakeup event */\r
+/* Delay line bandgap current settling time starting from wakeup event */\r
#define CY_PM_CLK_DELAY_BANDGAP_SETTLE_US (50u)\r
\r
/* Delay line internal bias settling */\r
\r
#if(CY_PSOC5)\r
\r
- /* The CPU clock is directly derived from bus clock */\r
+ /* CPU clock is directly derived from bus clock */\r
#define CY_PM_GET_CPU_FREQ_MHZ (cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK])\r
\r
#endif /* (CY_PSOC5) */\r
/*******************************************************************************\r
* The low power mode entry is different for PSoC 3 and PSoC 5 devices. The low\r
* power modes in PSoC 5 devices are invoked by Wait-For-Interrupt (WFI)\r
-* instruction. The ARM compilers has __wfi() instristic that inserts a WFI\r
+* instruction. The ARM compilers has __wfi() intrinsic that inserts a WFI\r
* instruction into the instruction stream generated by the compiler. The GCC\r
* compiler has to execute assembly language instruction.\r
*******************************************************************************/\r
/*******************************************************************************\r
* This macro defines the IMO frequency that will be set by CyPmSaveClocks()\r
* function based on Enable Fast IMO during Startup option from the DWR file.\r
-* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering\r
+* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering the\r
* low power mode and restore IMO back to the value set by CyPmSaveClocks()\r
* immediately on wakeup.\r
*******************************************************************************/\r
/* CyPmSaveClocks()/CyPmRestoreClocks() */\r
uint8 enClkA; /* Analog clocks enable */\r
uint8 enClkD; /* Digital clocks enable */\r
- uint8 masterClkSrc; /* The Master clock source */\r
+ uint8 masterClkSrc; /* Master clock source */\r
uint8 imoFreq; /* IMO frequency (reg's value) */\r
uint8 imoUsbClk; /* IMO USB CLK (reg's value) */\r
uint8 flashWaitCycles; /* Flash wait cycles */\r
uint8 clkImoSrc;\r
uint8 imo2x; /* IMO doubler enable state */\r
uint8 clkSyncDiv; /* Master clk divider */\r
- uint16 clkBusDiv; /* The clk_bus divider */\r
+ uint16 clkBusDiv; /* clk_bus divider */\r
uint8 pllEnableState; /* PLL enable state */\r
uint8 xmhzEnableState; /* XM HZ enable state */\r
uint8 clkDistDelay; /* Delay for clk_bus and ACLKs */\r
#define CY_PM_BOOST_CR2_REG (* (reg8 *) CYREG_BOOST_CR2 )\r
#define CY_PM_BOOST_CR2_PTR ( (reg8 *) CYREG_BOOST_CR2 )\r
\r
+#if(CY_PSOC3)\r
+\r
+ /* Interrrupt Controller Configuration and Status Register */\r
+ #define CY_PM_INTC_CSR_EN_REG (* (reg8 *) CYREG_INTC_CSR_EN )\r
+ #define CY_PM_INTC_CSR_EN_PTR ( (reg8 *) CYREG_INTC_CSR_EN )\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
\r
/***************************************\r
* Register Constants\r
#define CY_PM_CLKDIST_IMO_OUT_IMO (0x00u)\r
#define CY_PM_CLKDIST_IMO2X_SRC (0x40u)\r
\r
-/* Waiting for the hibernate/sleep regulator to stabilize */\r
+#define CY_PM_CLKDIST_PLL_SRC_MASK (0x03u)\r
+#define CY_PM_CLKDIST_PLL_SRC_IMO (0x00u)\r
+#define CY_PM_CLKDIST_PLL_SRC_XTAL (0x01u)\r
+#define CY_PM_CLKDIST_PLL_SRC_DSI (0x02u)\r
+\r
+/* Waiting for hibernate/sleep regulator to stabilize */\r
#define CY_PM_MODE_CSR_PWRUP_PULSE_Q (0x08u)\r
\r
#define CY_PM_MODE_CSR_ACTIVE (0x00u) /* Active power mode */\r
/* I2C regulator backup enable */\r
#define CY_PM_PWRSYS_CR1_I2CREG_BACKUP (0x04u)\r
\r
-/* When set, prepares the system to disable the LDO-A */\r
+/* When set, prepares system to disable LDO-A */\r
#define CY_PM_PWRSYS_CR1_LDOA_ISO (0x01u)\r
\r
-/* When set, disables the analog LDO regulator */\r
+/* When set, disables analog LDO regulator */\r
#define CY_PM_PWRSYS_CR1_LDOA_DIS (0x02u)\r
\r
#define CY_PM_PWRSYS_WAKE_TR2_VCCD_CLK_DET (0x04u)\r
/* Bus Clock divider to divide-by-one */\r
#define CY_PM_BUS_CLK_DIV_BY_ONE (0x00u)\r
\r
-/* HVI/LVI feature on the external analog and digital supply mask */\r
+/* HVI/LVI feature on external analog and digital supply mask */\r
#define CY_PM_RESET_CR1_HVI_LVI_EN_MASK (0x07u)\r
\r
-/* The high-voltage-interrupt feature on the external analog supply */\r
+/* High-voltage-interrupt feature on external analog supply */\r
#define CY_PM_RESET_CR1_HVIA_EN (0x04u)\r
\r
-/* The low-voltage-interrupt feature on the external analog supply */\r
+/* Low-voltage-interrupt feature on external analog supply */\r
#define CY_PM_RESET_CR1_LVIA_EN (0x02u)\r
\r
-/* The low-voltage-interrupt feature on the external digital supply */\r
+/* Low-voltage-interrupt feature on external digital supply */\r
#define CY_PM_RESET_CR1_LVID_EN (0x01u)\r
\r
-/* Allows the system to program delays on clk_sync_d */\r
+/* Allows system to program delays on clk_sync_d */\r
#define CY_PM_CLKDIST_DELAY_EN (0x04u)\r
\r
\r
#endif /* (CY_PSOC3) */\r
\r
\r
-/* Disable the sleep regulator and shorts vccd to vpwrsleep */\r
+/* Disables sleep regulator and shorts vccd to vpwrsleep */\r
#define CY_PM_PWRSYS_SLP_TR_BYPASS (0x10u)\r
\r
/* Boost Control 2: Select external precision reference */\r
\r
#endif /* (CY_PSOC5) */\r
\r
+#if(CY_PSOC3)\r
+\r
+ /* Interrrupt Controller Configuration and Status Register */\r
+ #define CY_PM_INTC_CSR_EN_CLK (0x01u)\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
+/*******************************************************************************\r
+* Lock Status Flag. If lock is acquired this flag will stay set (regardless of\r
+* whether lock is subsequently lost) until it is read. Upon reading it will\r
+* clear. If lock is still true then the bit will simply set again. If lock\r
+* happens to be false when the clear on read occurs then the bit will stay\r
+* cleared until the next lock event.\r
+*******************************************************************************/\r
+#define CY_PM_FASTCLK_PLL_LOCKED (0x01u)\r
+\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30\r
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.30\r
+*\r
+* If the obsoleted macro definitions intended for use in the application use the\r
+* following scheme, redefine your own versions of these definitions:\r
+* #ifdef <OBSOLETED_DEFINE>\r
+* #undef <OBSOLETED_DEFINE>\r
+* #define <OBSOLETED_DEFINE> (<New Value>)\r
+* #endif\r
+*\r
+* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* used in the application and their modification might lead to unexpected\r
+* consequences.\r
*******************************************************************************/\r
#if(CY_PSOC3)\r
\r
#endif\r
const uint8 cy_bootloader[] = {\r
0x00u, 0x40u, 0x00u, 0x20u, 0x11u, 0x00u, 0x00u, 0x00u,\r
- 0x61u, 0x01u, 0x00u, 0x00u, 0x61u, 0x01u, 0x00u, 0x00u,\r
- 0x08u, 0xB5u, 0x04u, 0x4Bu, 0x04u, 0x48u, 0x1Au, 0x68u,\r
- 0x02u, 0x60u, 0x00u, 0xF0u, 0x7Bu, 0xFCu, 0x00u, 0xF0u,\r
- 0xA1u, 0xF8u, 0x00u, 0xBFu, 0xFAu, 0x46u, 0x00u, 0x40u,\r
- 0xBCu, 0x76u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x05u, 0x4Cu,\r
- 0x23u, 0x78u, 0x33u, 0xB9u, 0x04u, 0x48u, 0x10u, 0xB1u,\r
- 0x04u, 0x48u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x01u, 0x21u,\r
- 0x21u, 0x70u, 0x10u, 0xBDu, 0x28u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x20u, 0x00u, 0x00u,\r
+ 0x5Du, 0x01u, 0x00u, 0x00u, 0x5Du, 0x01u, 0x00u, 0x00u,\r
+ 0x08u, 0xB5u, 0x05u, 0x4Bu, 0x1Au, 0x68u, 0x03u, 0xF5u,\r
+ 0x3Fu, 0x53u, 0x02u, 0x33u, 0x1Au, 0x60u, 0x00u, 0xF0u,\r
+ 0x43u, 0xFAu, 0x00u, 0xF0u, 0x9Du, 0xF8u, 0x00u, 0xBFu,\r
+ 0xFAu, 0x46u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x05u, 0x4Cu,\r
+ 0x23u, 0x78u, 0x33u, 0xB9u, 0x04u, 0x4Bu, 0x13u, 0xB1u,\r
+ 0x04u, 0x48u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x01u, 0x23u,\r
+ 0x23u, 0x70u, 0x10u, 0xBDu, 0x28u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0xC4u, 0x20u, 0x00u, 0x00u,\r
0x08u, 0xB5u, 0x06u, 0x4Bu, 0x1Bu, 0xB1u, 0x06u, 0x48u,\r
0x06u, 0x49u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x06u, 0x48u,\r
- 0x01u, 0x68u, 0x11u, 0xB1u, 0x05u, 0x4Au, 0x02u, 0xB1u,\r
- 0x90u, 0x47u, 0x08u, 0xBDu, 0x00u, 0x00u, 0x00u, 0x00u,\r
- 0x0Cu, 0x20u, 0x00u, 0x00u, 0x2Cu, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x03u, 0x68u, 0x13u, 0xB1u, 0x05u, 0x4Bu, 0x03u, 0xB1u,\r
+ 0x98u, 0x47u, 0x08u, 0xBDu, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0xC4u, 0x20u, 0x00u, 0x00u, 0x2Cu, 0xC1u, 0xFFu, 0x1Fu,\r
0x08u, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u,\r
- 0x08u, 0xB5u, 0x36u, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u,\r
- 0xFEu, 0x00u, 0x18u, 0x70u, 0x93u, 0xF8u, 0x22u, 0x10u,\r
- 0x01u, 0xF0u, 0xFEu, 0x02u, 0x83u, 0xF8u, 0x22u, 0x20u,\r
- 0x07u, 0x33u, 0x18u, 0x78u, 0x00u, 0xF0u, 0xFEu, 0x01u,\r
- 0x19u, 0x70u, 0x13u, 0xF8u, 0x01u, 0x2Cu, 0x02u, 0xF0u,\r
- 0xFEu, 0x00u, 0x03u, 0xF8u, 0x01u, 0x0Cu, 0x13u, 0xF8u,\r
- 0x02u, 0x1Cu, 0x01u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u,\r
- 0x02u, 0x2Cu, 0x13u, 0xF8u, 0x04u, 0x0Cu, 0x00u, 0xF0u,\r
- 0xFEu, 0x01u, 0x03u, 0xF8u, 0x04u, 0x1Cu, 0x13u, 0xF8u,\r
- 0x06u, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x00u, 0x03u, 0xF8u,\r
- 0x06u, 0x0Cu, 0x13u, 0xF8u, 0x03u, 0x1Cu, 0x01u, 0xF0u,\r
- 0xFEu, 0x02u, 0x03u, 0xF8u, 0x03u, 0x2Cu, 0x13u, 0xF8u,\r
- 0x05u, 0x0Cu, 0x00u, 0xF0u, 0xFEu, 0x01u, 0x03u, 0xF8u,\r
- 0x05u, 0x1Cu, 0x93u, 0xF8u, 0x2Cu, 0x20u, 0x02u, 0xF0u,\r
- 0xFEu, 0x00u, 0x83u, 0xF8u, 0x2Cu, 0x00u, 0x2Bu, 0x33u,\r
- 0x19u, 0x78u, 0x01u, 0xF0u, 0xFEu, 0x02u, 0x1Au, 0x70u,\r
- 0x13u, 0xF8u, 0x01u, 0x0Cu, 0x00u, 0xF0u, 0xFEu, 0x01u,\r
- 0x03u, 0xF8u, 0x01u, 0x1Cu, 0x13u, 0xF8u, 0x02u, 0x2Cu,\r
- 0x02u, 0xF0u, 0xFEu, 0x00u, 0x03u, 0xF8u, 0x02u, 0x0Cu,\r
- 0x13u, 0xF8u, 0x0Bu, 0x1Cu, 0x01u, 0xF0u, 0xFEu, 0x02u,\r
- 0x03u, 0xF8u, 0x0Bu, 0x2Cu, 0x13u, 0xF8u, 0x0Cu, 0x0Cu,\r
- 0x00u, 0xF0u, 0xFEu, 0x01u, 0x03u, 0xF8u, 0x0Cu, 0x1Cu,\r
- 0x13u, 0xF8u, 0x0Du, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x00u,\r
- 0x03u, 0xF8u, 0x0Du, 0x0Cu, 0x13u, 0xF8u, 0x0Eu, 0x1Cu,\r
- 0x01u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x0Eu, 0x2Cu,\r
- 0x13u, 0xF8u, 0x0Fu, 0x0Cu, 0x00u, 0xF0u, 0xFEu, 0x01u,\r
- 0x03u, 0xF8u, 0x0Fu, 0x1Cu, 0x00u, 0xF0u, 0x9Eu, 0xFBu,\r
- 0xFEu, 0xE7u, 0x00u, 0xBFu, 0x00u, 0x50u, 0x00u, 0x40u,\r
- 0xFEu, 0xE7u, 0x00u, 0x00u, 0x08u, 0xB5u, 0x12u, 0x49u,\r
- 0x12u, 0x4Bu, 0x4Au, 0x1Cu, 0x1Au, 0xD0u, 0x53u, 0xF8u,\r
- 0x10u, 0x6Cu, 0x53u, 0xF8u, 0x0Cu, 0x0Cu, 0x53u, 0xF8u,\r
- 0x08u, 0x5Cu, 0x00u, 0x22u, 0xAAu, 0x42u, 0x00u, 0xEBu,\r
- 0x02u, 0x04u, 0x03u, 0xD0u, 0xB4u, 0x58u, 0x84u, 0x50u,\r
- 0x04u, 0x32u, 0xF7u, 0xE7u, 0x53u, 0xF8u, 0x04u, 0x0Cu,\r
- 0x00u, 0x22u, 0x82u, 0x42u, 0x03u, 0xD0u, 0x00u, 0x25u,\r
- 0xA5u, 0x50u, 0x04u, 0x32u, 0xF9u, 0xE7u, 0x01u, 0x39u,\r
- 0x10u, 0x33u, 0xE2u, 0xE7u, 0x01u, 0xF0u, 0xF6u, 0xFEu,\r
- 0xFFu, 0xF7u, 0x6Au, 0xFFu, 0xFEu, 0xE7u, 0x00u, 0xBFu,\r
- 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0x22u, 0x00u, 0x00u,\r
- 0x08u, 0xB5u, 0x10u, 0x4Au, 0x10u, 0x4Bu, 0x1Au, 0x60u,\r
- 0x98u, 0x68u, 0x40u, 0xF4u, 0x00u, 0x72u, 0x9Au, 0x60u,\r
- 0x00u, 0x23u, 0x03u, 0x2Bu, 0x96u, 0xBFu, 0x0Du, 0x4Au,\r
- 0x0Du, 0x49u, 0x52u, 0xF8u, 0x23u, 0x10u, 0x0Du, 0x4Au,\r
- 0x42u, 0xF8u, 0x23u, 0x10u, 0x01u, 0x33u, 0x30u, 0x2Bu,\r
- 0xF3u, 0xD1u, 0x0Bu, 0x49u, 0x0Bu, 0x4Bu, 0x08u, 0x78u,\r
- 0x0Bu, 0x49u, 0x18u, 0x70u, 0x0Au, 0x60u, 0x00u, 0xF0u,\r
- 0x17u, 0xF8u, 0x0Au, 0x48u, 0x00u, 0x22u, 0x02u, 0x60u,\r
+ 0x08u, 0xB5u, 0x35u, 0x4Bu, 0x1Au, 0x78u, 0x07u, 0x33u,\r
+ 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x07u, 0x2Cu,\r
+ 0xDAu, 0x7Eu, 0x02u, 0xF0u, 0xFEu, 0x02u, 0xDAu, 0x76u,\r
+ 0x1Au, 0x78u, 0x02u, 0xF0u, 0xFEu, 0x02u, 0x1Au, 0x70u,\r
+ 0x13u, 0xF8u, 0x01u, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u,\r
+ 0x03u, 0xF8u, 0x01u, 0x2Cu, 0x13u, 0xF8u, 0x02u, 0x2Cu,\r
+ 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x02u, 0x2Cu,\r
+ 0x13u, 0xF8u, 0x04u, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u,\r
+ 0x03u, 0xF8u, 0x04u, 0x2Cu, 0x13u, 0xF8u, 0x06u, 0x2Cu,\r
+ 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x06u, 0x2Cu,\r
+ 0x13u, 0xF8u, 0x03u, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u,\r
+ 0x03u, 0xF8u, 0x03u, 0x2Cu, 0x13u, 0xF8u, 0x05u, 0x2Cu,\r
+ 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x05u, 0x2Cu,\r
+ 0x93u, 0xF8u, 0x2Cu, 0x20u, 0x02u, 0xF0u, 0xFEu, 0x02u,\r
+ 0x83u, 0xF8u, 0x2Cu, 0x20u, 0x2Bu, 0x33u, 0x1Au, 0x78u,\r
+ 0x02u, 0xF0u, 0xFEu, 0x02u, 0x1Au, 0x70u, 0x13u, 0xF8u,\r
+ 0x01u, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u,\r
+ 0x01u, 0x2Cu, 0x13u, 0xF8u, 0x02u, 0x2Cu, 0x02u, 0xF0u,\r
+ 0xFEu, 0x02u, 0x03u, 0xF8u, 0x02u, 0x2Cu, 0x13u, 0xF8u,\r
+ 0x0Bu, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u,\r
+ 0x0Bu, 0x2Cu, 0x13u, 0xF8u, 0x0Cu, 0x2Cu, 0x02u, 0xF0u,\r
+ 0xFEu, 0x02u, 0x03u, 0xF8u, 0x0Cu, 0x2Cu, 0x13u, 0xF8u,\r
+ 0x0Du, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u,\r
+ 0x0Du, 0x2Cu, 0x13u, 0xF8u, 0x0Eu, 0x2Cu, 0x02u, 0xF0u,\r
+ 0xFEu, 0x02u, 0x03u, 0xF8u, 0x0Eu, 0x2Cu, 0x13u, 0xF8u,\r
+ 0x0Fu, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u,\r
+ 0x0Fu, 0x2Cu, 0x00u, 0xF0u, 0xE1u, 0xFBu, 0xFEu, 0xE7u,\r
+ 0x00u, 0x50u, 0x00u, 0x40u, 0xFEu, 0xE7u, 0x00u, 0x00u,\r
+ 0x08u, 0xB5u, 0x12u, 0x49u, 0x12u, 0x4Bu, 0x4Au, 0x1Cu,\r
+ 0x1Au, 0xD0u, 0x53u, 0xF8u, 0x10u, 0x6Cu, 0x53u, 0xF8u,\r
+ 0x0Cu, 0x0Cu, 0x53u, 0xF8u, 0x08u, 0x5Cu, 0x00u, 0x22u,\r
+ 0xAAu, 0x42u, 0x00u, 0xEBu, 0x02u, 0x04u, 0x03u, 0xD0u,\r
+ 0xB4u, 0x58u, 0x84u, 0x50u, 0x04u, 0x32u, 0xF7u, 0xE7u,\r
+ 0x53u, 0xF8u, 0x04u, 0x0Cu, 0x00u, 0x22u, 0x82u, 0x42u,\r
+ 0x03u, 0xD0u, 0x00u, 0x25u, 0xA5u, 0x50u, 0x04u, 0x32u,\r
+ 0xF9u, 0xE7u, 0x10u, 0x33u, 0x01u, 0x39u, 0xE2u, 0xE7u,\r
+ 0x01u, 0xF0u, 0x54u, 0xFFu, 0xFFu, 0xF7u, 0x6Cu, 0xFFu,\r
+ 0xFEu, 0xE7u, 0x00u, 0xBFu, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x14u, 0x23u, 0x00u, 0x00u, 0x08u, 0xB5u, 0x11u, 0x4Au,\r
+ 0x11u, 0x4Bu, 0x1Au, 0x60u, 0x9Au, 0x68u, 0x42u, 0xF4u,\r
+ 0x00u, 0x72u, 0x9Au, 0x60u, 0x00u, 0x23u, 0x03u, 0x2Bu,\r
+ 0x98u, 0xBFu, 0x0Eu, 0x4Au, 0x4Fu, 0xEAu, 0x83u, 0x00u,\r
+ 0x94u, 0xBFu, 0x52u, 0xF8u, 0x23u, 0x10u, 0x0Cu, 0x49u,\r
+ 0x0Cu, 0x4Au, 0x01u, 0x33u, 0x30u, 0x2Bu, 0x11u, 0x50u,\r
+ 0xF1u, 0xD1u, 0x0Bu, 0x4Bu, 0x19u, 0x78u, 0x0Bu, 0x4Bu,\r
+ 0x19u, 0x70u, 0x0Bu, 0x4Bu, 0x1Au, 0x60u, 0x00u, 0xF0u,\r
+ 0x17u, 0xF8u, 0x0Au, 0x4Bu, 0x00u, 0x22u, 0x1Au, 0x60u,\r
0x08u, 0xBDu, 0x00u, 0xBFu, 0x00u, 0x04u, 0xFAu, 0x05u,\r
0x0Cu, 0xEDu, 0x00u, 0xE0u, 0x00u, 0x00u, 0x00u, 0x00u,\r
- 0x61u, 0x01u, 0x00u, 0x00u, 0x00u, 0xC0u, 0xFFu, 0x1Fu,\r
+ 0x5Du, 0x01u, 0x00u, 0x00u, 0x00u, 0xC0u, 0xFFu, 0x1Fu,\r
0xBCu, 0x76u, 0x00u, 0x40u, 0x04u, 0xC1u, 0xFFu, 0x1Fu,\r
0x08u, 0xEDu, 0x00u, 0xE0u, 0x00u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0xF8u, 0xB5u, 0x72u, 0xB6u, 0x5Fu, 0x4Bu, 0x01u, 0x22u,\r
- 0xA3u, 0xF5u, 0xA0u, 0x61u, 0xA1u, 0xF5u, 0x80u, 0x75u,\r
- 0x06u, 0x20u, 0x52u, 0x24u, 0x5Cu, 0x4Eu, 0x1Au, 0x70u,\r
- 0x08u, 0x70u, 0x2Cu, 0x70u, 0x37u, 0x78u, 0x5Bu, 0x4Bu,\r
- 0x5Bu, 0x4Au, 0x40u, 0xF6u, 0x18u, 0x00u, 0x41u, 0xF2u,\r
- 0x51u, 0x21u, 0x17u, 0x70u, 0x19u, 0x25u, 0x18u, 0x80u,\r
- 0x00u, 0x24u, 0x23u, 0xF8u, 0x02u, 0x1Cu, 0x57u, 0x4Eu,\r
- 0x4Fu, 0xF4u, 0xF0u, 0x70u, 0x37u, 0x78u, 0x07u, 0xF0u,\r
- 0x01u, 0x02u, 0x42u, 0xEAu, 0x44u, 0x04u, 0x00u, 0xF0u,\r
- 0x6Fu, 0xFBu, 0x01u, 0x3Du, 0x04u, 0xF0u, 0x03u, 0x04u,\r
- 0x17u, 0xD0u, 0x03u, 0x2Cu, 0xEFu, 0xD1u, 0x50u, 0x48u,\r
- 0x50u, 0x4Fu, 0x00u, 0x26u, 0x4Fu, 0xF4u, 0x80u, 0x73u,\r
- 0x4Fu, 0x4Du, 0x07u, 0x21u, 0x48u, 0x22u, 0x02u, 0x24u,\r
- 0x03u, 0x80u, 0x01u, 0x70u, 0x3Eu, 0x70u, 0xBAu, 0x70u,\r
- 0x06u, 0x70u, 0x46u, 0x71u, 0x00u, 0xF8u, 0x03u, 0x4Cu,\r
- 0x28u, 0x78u, 0x40u, 0xF0u, 0x04u, 0x03u, 0x2Bu, 0x70u,\r
- 0x00u, 0xE0u, 0xFEu, 0xE7u, 0x47u, 0x4Fu, 0x06u, 0x21u,\r
- 0x01u, 0xFBu, 0x06u, 0x72u, 0x00u, 0x21u, 0x10u, 0x68u,\r
- 0x01u, 0x36u, 0x92u, 0x88u, 0x01u, 0xF0u, 0x9Du, 0xFEu,\r
- 0x08u, 0x2Eu, 0xF3u, 0xD1u, 0x00u, 0x23u, 0x19u, 0x46u,\r
- 0x41u, 0x4Cu, 0x00u, 0x22u, 0x18u, 0x59u, 0x30u, 0x34u,\r
- 0xC6u, 0xB2u, 0x20u, 0xF0u, 0xFFu, 0x07u, 0x04u, 0xEBu,\r
- 0x41u, 0x04u, 0xD5u, 0xB2u, 0xAEu, 0x42u, 0x09u, 0xD0u,\r
- 0x04u, 0xEBu, 0x42u, 0x0Cu, 0x14u, 0xF8u, 0x12u, 0x50u,\r
- 0x9Cu, 0xF8u, 0x01u, 0xE0u, 0x01u, 0x32u, 0x05u, 0xF8u,\r
- 0x07u, 0xE0u, 0xF2u, 0xE7u, 0x04u, 0x33u, 0xC0u, 0xB2u,\r
- 0x30u, 0x2Bu, 0x01u, 0x44u, 0xE4u, 0xD1u, 0x35u, 0x4Cu,\r
- 0x22u, 0x78u, 0x42u, 0xF0u, 0x02u, 0x00u, 0x20u, 0x70u,\r
- 0x21u, 0x7Cu, 0x33u, 0x48u, 0x41u, 0xF0u, 0x02u, 0x03u,\r
- 0x32u, 0x49u, 0x23u, 0x74u, 0x0Cu, 0x78u, 0x44u, 0xF0u,\r
- 0x40u, 0x02u, 0x0Au, 0x70u, 0x03u, 0x78u, 0x30u, 0x4Au,\r
- 0x43u, 0xF0u, 0x10u, 0x04u, 0x2Fu, 0x4Bu, 0x04u, 0x70u,\r
- 0x18u, 0x68u, 0x5Cu, 0x68u, 0x10u, 0x60u, 0x54u, 0x60u,\r
- 0x1Au, 0x46u, 0x2Du, 0x48u, 0x52u, 0xF8u, 0x08u, 0x4Fu,\r
- 0x04u, 0x60u, 0x54u, 0x68u, 0x12u, 0x89u, 0x44u, 0x60u,\r
- 0x02u, 0x81u, 0x1Au, 0x46u, 0x52u, 0xF8u, 0x12u, 0x4Fu,\r
- 0x40u, 0xF8u, 0xC0u, 0x4Cu, 0x54u, 0x68u, 0x12u, 0x89u,\r
- 0x40u, 0xF8u, 0xBCu, 0x4Cu, 0x20u, 0xF8u, 0xB8u, 0x2Cu,\r
- 0x1Au, 0x46u, 0x52u, 0xF8u, 0x1Cu, 0x4Fu, 0x52u, 0x68u,\r
- 0x40u, 0xF8u, 0xAEu, 0x4Cu, 0x40u, 0xF8u, 0xAAu, 0x2Cu,\r
- 0x53u, 0xF8u, 0x24u, 0x0Fu, 0x1Fu, 0x4Au, 0x5Bu, 0x68u,\r
- 0x10u, 0x60u, 0x1Fu, 0x48u, 0x53u, 0x60u, 0x02u, 0x78u,\r
- 0x42u, 0xF0u, 0x08u, 0x03u, 0x03u, 0x70u, 0x1Du, 0x48u,\r
- 0x1Du, 0x4Au, 0x03u, 0x78u, 0x03u, 0xF0u, 0x07u, 0x00u,\r
- 0x1Bu, 0x09u, 0x10u, 0x70u, 0x53u, 0x70u, 0x1Bu, 0x4Au,\r
- 0x44u, 0x20u, 0x10u, 0x70u, 0x1Au, 0x4Au, 0x0Bu, 0x46u,\r
- 0x0Cu, 0x31u, 0x53u, 0xF8u, 0x04u, 0x0Bu, 0x8Bu, 0x42u,\r
- 0x42u, 0xF8u, 0x04u, 0x0Bu, 0xF9u, 0xD1u, 0x19u, 0x88u,\r
- 0x11u, 0x80u, 0xF8u, 0xBDu, 0x00u, 0x48u, 0x00u, 0x40u,\r
- 0x0Fu, 0x01u, 0x00u, 0x49u, 0x22u, 0x42u, 0x00u, 0x40u,\r
- 0xA1u, 0x46u, 0x00u, 0x40u, 0x25u, 0x42u, 0x00u, 0x40u,\r
- 0x04u, 0x40u, 0x00u, 0x40u, 0x06u, 0x40u, 0x00u, 0x40u,\r
- 0xE8u, 0x46u, 0x00u, 0x40u, 0x10u, 0x20u, 0x00u, 0x00u,\r
- 0x40u, 0x20u, 0x00u, 0x00u, 0x03u, 0x50u, 0x01u, 0x40u,\r
- 0xC2u, 0x43u, 0x00u, 0x40u, 0xA0u, 0x43u, 0x00u, 0x40u,\r
- 0x02u, 0x51u, 0x00u, 0x40u, 0x9Eu, 0x20u, 0x00u, 0x00u,\r
- 0xF0u, 0x51u, 0x00u, 0x40u, 0x62u, 0x51u, 0x00u, 0x40u,\r
- 0x22u, 0x43u, 0x00u, 0x40u, 0xCFu, 0x01u, 0x00u, 0x49u,\r
- 0x6Eu, 0x58u, 0x00u, 0x40u, 0x76u, 0x58u, 0x00u, 0x40u,\r
- 0xB0u, 0x43u, 0x00u, 0x40u, 0x00u, 0x47u, 0x00u, 0x00u,\r
- 0x43u, 0x1Eu, 0x10u, 0xB5u, 0x02u, 0x46u, 0x06u, 0x2Bu,\r
- 0x0Du, 0xD8u, 0xDFu, 0xE8u, 0x03u, 0xF0u, 0x06u, 0x0Eu,\r
- 0x23u, 0x04u, 0x08u, 0x0Au, 0x21u, 0x00u, 0x16u, 0x48u,\r
- 0x08u, 0xE0u, 0x16u, 0x4Bu, 0x1Bu, 0xE0u, 0x16u, 0x48u,\r
- 0x04u, 0xE0u, 0x16u, 0x48u, 0x02u, 0xE0u, 0x00u, 0x20u,\r
- 0x00u, 0xE0u, 0x15u, 0x48u, 0x41u, 0x78u, 0x00u, 0x78u,\r
- 0x41u, 0xEAu, 0x00u, 0x20u, 0x02u, 0x2Au, 0x04u, 0xD0u,\r
- 0x03u, 0x2Au, 0x07u, 0xD0u, 0x01u, 0x2Au, 0x15u, 0xD1u,\r
- 0x04u, 0xE0u, 0x02u, 0x02u, 0x42u, 0xEAu, 0x10u, 0x23u,\r
- 0x98u, 0xB2u, 0x10u, 0xBDu, 0x00u, 0xBAu, 0x10u, 0xBDu,\r
- 0x0Cu, 0x4Bu, 0x00u, 0xE0u, 0x0Cu, 0x4Bu, 0xD8u, 0x78u,\r
- 0x9Cu, 0x78u, 0x59u, 0x78u, 0x1Bu, 0x78u, 0x40u, 0xEAu,\r
- 0x03u, 0x60u, 0x40u, 0xEAu, 0x04u, 0x23u, 0x43u, 0xEAu,\r
- 0x01u, 0x40u, 0xE3u, 0xE7u, 0x10u, 0xBDu, 0x00u, 0xBFu,\r
- 0xD2u, 0xFFu, 0x01u, 0x00u, 0xC1u, 0xFFu, 0x01u, 0x00u,\r
- 0xD6u, 0xFFu, 0x01u, 0x00u, 0xD4u, 0xFFu, 0x01u, 0x00u,\r
- 0xC5u, 0xFFu, 0x01u, 0x00u, 0xD8u, 0xFFu, 0x01u, 0x00u,\r
- 0xC9u, 0xFFu, 0x01u, 0x00u, 0x70u, 0xB5u, 0x02u, 0x20u,\r
- 0xFFu, 0xF7u, 0xB6u, 0xFFu, 0x06u, 0x46u, 0x03u, 0x20u,\r
- 0xFFu, 0xF7u, 0xB2u, 0xFFu, 0x71u, 0x1Cu, 0x00u, 0xEBu,\r
- 0x01u, 0x26u, 0x02u, 0x20u, 0xFFu, 0xF7u, 0xACu, 0xFFu,\r
- 0x00u, 0x24u, 0x01u, 0x30u, 0x01u, 0x02u, 0x25u, 0x46u,\r
- 0xB1u, 0x42u, 0x09u, 0xD2u, 0x11u, 0xF8u, 0x01u, 0x0Bu,\r
- 0x42u, 0x1Eu, 0xD3u, 0xB2u, 0x04u, 0x19u, 0xFDu, 0x2Bu,\r
- 0x98u, 0xBFu, 0x01u, 0x25u, 0xE4u, 0xB2u, 0xF3u, 0xE7u,\r
- 0x02u, 0x20u, 0xFFu, 0xF7u, 0x99u, 0xFFu, 0x0Fu, 0x49u,\r
- 0x42u, 0x1Cu, 0x13u, 0x02u, 0xDBu, 0x08u, 0x8Eu, 0x42u,\r
- 0x01u, 0xD0u, 0xF6u, 0x08u, 0x01u, 0xE0u, 0x4Fu, 0xF4u,\r
- 0x80u, 0x46u, 0xB3u, 0x42u, 0x06u, 0xD2u, 0x03u, 0xF1u,\r
- 0x90u, 0x41u, 0x08u, 0x78u, 0x01u, 0x33u, 0x02u, 0x19u,\r
- 0xD4u, 0xB2u, 0xF6u, 0xE7u, 0x05u, 0x48u, 0x64u, 0x42u,\r
- 0x02u, 0x78u, 0xE4u, 0xB2u, 0x94u, 0x42u, 0x01u, 0xD0u,\r
- 0x06u, 0x20u, 0x70u, 0xBDu, 0x00u, 0x2Du, 0xFBu, 0xD0u,\r
- 0x00u, 0x20u, 0x70u, 0xBDu, 0xC0u, 0xFFu, 0x01u, 0x00u,\r
- 0x2Du, 0xE9u, 0xF0u, 0x4Fu, 0xADu, 0xF5u, 0x61u, 0x7Du,\r
- 0x80u, 0x46u, 0x00u, 0xF0u, 0xE5u, 0xFBu, 0x62u, 0xB6u,\r
- 0x00u, 0x26u, 0xB2u, 0x46u, 0x4Fu, 0xF0u, 0x0Au, 0x09u,\r
- 0x37u, 0x46u, 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x01u, 0xD1u,\r
- 0xFFu, 0x23u, 0x00u, 0xE0u, 0x43u, 0x46u, 0x4Au, 0xA8u,\r
- 0x4Fu, 0xF4u, 0x96u, 0x71u, 0x01u, 0xAAu, 0x00u, 0xF0u,\r
- 0x0Du, 0xFCu, 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x03u, 0xD0u,\r
- 0x09u, 0xF1u, 0xFFu, 0x39u, 0x5Fu, 0xFAu, 0x89u, 0xF9u,\r
- 0xB9u, 0xF1u, 0x00u, 0x0Fu, 0x02u, 0xD0u, 0x00u, 0x28u,\r
- 0xE7u, 0xD1u, 0x01u, 0xE0u, 0x00u, 0x28u, 0x71u, 0xD1u,\r
- 0xBDu, 0xF8u, 0x04u, 0x20u, 0x06u, 0x2Au, 0x40u, 0xF2u,\r
- 0x7Bu, 0x81u, 0x9Du, 0xF8u, 0x28u, 0x31u, 0x01u, 0x2Bu,\r
- 0x40u, 0xF0u, 0x76u, 0x81u, 0x9Du, 0xF8u, 0x2Au, 0x01u,\r
- 0x9Du, 0xF8u, 0x2Bu, 0x51u, 0x4Au, 0xA9u, 0x40u, 0xEAu,\r
- 0x05u, 0x25u, 0xECu, 0x1Du, 0x4Bu, 0x19u, 0x94u, 0x42u,\r
- 0x58u, 0x79u, 0x19u, 0x79u, 0x00u, 0xF2u, 0x66u, 0x81u,\r
- 0x9Au, 0x79u, 0x17u, 0x2Au, 0x40u, 0xF0u, 0x64u, 0x81u,\r
- 0x2Bu, 0x1Du, 0x9Bu, 0xB2u, 0x00u, 0x22u, 0x3Bu, 0xB1u,\r
- 0x0Du, 0xF2u, 0x27u, 0x14u, 0xE4u, 0x5Cu, 0x01u, 0x3Bu,\r
- 0x12u, 0x19u, 0x92u, 0xB2u, 0x9Bu, 0xB2u, 0xF6u, 0xE7u,\r
- 0x52u, 0x42u, 0x41u, 0xEAu, 0x00u, 0x20u, 0x91u, 0xB2u,\r
- 0x88u, 0x42u, 0x40u, 0xF0u, 0x53u, 0x81u, 0x4Au, 0xE0u,\r
- 0x00u, 0x2Eu, 0x00u, 0xF0u, 0x4Du, 0x81u, 0x01u, 0x2Du,\r
- 0x4Fu, 0xF0u, 0x00u, 0x04u, 0x40u, 0xF0u, 0x3Cu, 0x81u,\r
- 0xBBu, 0xF1u, 0x01u, 0x0Fu, 0x00u, 0xF2u, 0x38u, 0x81u,\r
- 0xFFu, 0x23u, 0x8Du, 0xF8u, 0x2Cu, 0x41u, 0x8Du, 0xF8u,\r
- 0x2Du, 0x41u, 0x25u, 0x46u, 0x8Du, 0xF8u, 0x2Eu, 0x31u,\r
- 0x8Du, 0xF8u, 0x2Fu, 0x61u, 0x04u, 0x24u, 0x01u, 0x20u,\r
- 0x00u, 0x22u, 0x21u, 0x1Du, 0xADu, 0xF8u, 0x06u, 0x40u,\r
- 0x8Du, 0xF8u, 0x28u, 0x01u, 0x8Du, 0xF8u, 0x29u, 0x51u,\r
- 0x8Du, 0xF8u, 0x2Au, 0x41u, 0x8Du, 0xF8u, 0x2Bu, 0x21u,\r
- 0x8Bu, 0xB2u, 0x0Du, 0xF2u, 0x27u, 0x10u, 0xC1u, 0x5Cu,\r
- 0x01u, 0x3Bu, 0x52u, 0x18u, 0x9Bu, 0xB2u, 0x92u, 0xB2u,\r
- 0x00u, 0x2Bu, 0xF6u, 0xD1u, 0x50u, 0x42u, 0x81u, 0xB2u,\r
- 0x08u, 0x0Au, 0x4Bu, 0xAAu, 0x0Du, 0xF2u, 0x2Du, 0x13u,\r
- 0x11u, 0x55u, 0x18u, 0x55u, 0x17u, 0x21u, 0x0Du, 0xF5u,\r
- 0x97u, 0x72u, 0xE3u, 0x1Du, 0x11u, 0x55u, 0x4Au, 0xA8u,\r
- 0x99u, 0xB2u, 0x0Du, 0xF1u, 0x06u, 0x02u, 0x96u, 0x23u,\r
- 0x00u, 0xF0u, 0x62u, 0xFBu, 0xB8u, 0xF1u, 0x00u, 0x0Fu,\r
- 0x3Fu, 0xF4u, 0x72u, 0xAFu, 0x00u, 0x2Eu, 0x00u, 0xF0u,\r
- 0x12u, 0x81u, 0x01u, 0x26u, 0x69u, 0xE7u, 0x9Du, 0xF8u,\r
- 0x29u, 0x21u, 0x9Du, 0xF8u, 0x2Cu, 0xB1u, 0xA2u, 0xF1u,\r
- 0x31u, 0x03u, 0x0Au, 0x2Bu, 0x00u, 0xF2u, 0xF7u, 0x80u,\r
- 0x01u, 0xA1u, 0x51u, 0xF8u, 0x23u, 0xF0u, 0x00u, 0xBFu,\r
- 0x9Du, 0x06u, 0x00u, 0x00u, 0xC1u, 0x05u, 0x00u, 0x00u,\r
- 0x57u, 0x08u, 0x00u, 0x00u, 0xBBu, 0x06u, 0x00u, 0x00u,\r
- 0x6Du, 0x07u, 0x00u, 0x00u, 0x57u, 0x08u, 0x00u, 0x00u,\r
- 0x73u, 0x07u, 0x00u, 0x00u, 0x91u, 0x07u, 0x00u, 0x00u,\r
- 0xBBu, 0x06u, 0x00u, 0x00u, 0xABu, 0x07u, 0x00u, 0x00u,\r
- 0x37u, 0x08u, 0x00u, 0x00u, 0x00u, 0x2Eu, 0x00u, 0xF0u,\r
- 0xDFu, 0x80u, 0x00u, 0x2Du, 0x40u, 0xF0u, 0xDCu, 0x80u,\r
- 0xFFu, 0xF7u, 0xF0u, 0xFEu, 0xD0u, 0xF1u, 0x01u, 0x02u,\r
- 0x38u, 0xBFu, 0x00u, 0x22u, 0x8Du, 0xF8u, 0x2Cu, 0x21u,\r
- 0xBBu, 0xE0u, 0x34u, 0x2Au, 0x12u, 0xD1u, 0x00u, 0x2Eu,\r
- 0x00u, 0xF0u, 0xCEu, 0x80u, 0x03u, 0x2Du, 0x40u, 0xF0u,\r
- 0xCBu, 0x80u, 0xABu, 0xF1u, 0x40u, 0x07u, 0x3Fu, 0x2Fu,\r
- 0x8Cu, 0xBFu, 0x4Fu, 0xF4u, 0x90u, 0x77u, 0x10u, 0x27u,\r
- 0x95u, 0xA8u, 0x00u, 0x21u, 0x3Au, 0x46u, 0x01u, 0xF0u,\r
- 0x88u, 0xFCu, 0x05u, 0xE0u, 0x00u, 0x2Eu, 0x00u, 0xF0u,\r
- 0xBBu, 0x80u, 0x02u, 0x2Du, 0x40u, 0xF2u, 0xB8u, 0x80u,\r
- 0x03u, 0x3Du, 0x95u, 0xABu, 0x2Au, 0x46u, 0xD8u, 0x19u,\r
- 0x0Du, 0xF2u, 0x2Fu, 0x11u, 0x01u, 0xF0u, 0x70u, 0xFCu,\r
- 0xABu, 0xF1u, 0x40u, 0x00u, 0x7Au, 0x19u, 0x3Fu, 0x28u,\r
- 0x96u, 0xB2u, 0x03u, 0xD8u, 0x00u, 0xF0u, 0xD4u, 0xF9u,\r
- 0x10u, 0x24u, 0x01u, 0xE0u, 0x4Fu, 0xF4u, 0x90u, 0x74u,\r
- 0xA6u, 0x42u, 0x40u, 0xF0u, 0x97u, 0x80u, 0x9Du, 0xF8u,\r
- 0x2Eu, 0x11u, 0x9Du, 0xF8u, 0x2Du, 0x71u, 0xBBu, 0xF1u,\r
- 0x3Fu, 0x0Fu, 0x47u, 0xEAu, 0x01u, 0x25u, 0x11u, 0xD8u,\r
- 0xBAu, 0xF1u, 0x00u, 0x0Fu, 0x0Eu, 0xD1u, 0x51u, 0x46u,\r
- 0x4Fu, 0xF4u, 0x90u, 0x72u, 0x02u, 0xA8u, 0x01u, 0xF0u,\r
- 0x58u, 0xFCu, 0x01u, 0x20u, 0xFFu, 0x21u, 0x02u, 0xAAu,\r
- 0x4Fu, 0xF4u, 0x90u, 0x73u, 0x00u, 0xF0u, 0x64u, 0xF9u,\r
- 0x4Fu, 0xF0u, 0x01u, 0x0Au, 0x33u, 0x46u, 0x58u, 0x46u,\r
- 0x29u, 0x46u, 0x95u, 0xAAu, 0x00u, 0xF0u, 0x5Cu, 0xF9u,\r
- 0x01u, 0x26u, 0x00u, 0x28u, 0x75u, 0xD0u, 0x00u, 0x27u,\r
- 0x0Au, 0x25u, 0x75u, 0xE0u, 0x00u, 0x2Eu, 0x77u, 0xD0u,\r
- 0x7Au, 0xE0u, 0x00u, 0x2Eu, 0x74u, 0xD0u, 0x7Cu, 0x19u,\r
- 0xB4u, 0xF5u, 0x96u, 0x7Fu, 0x6Eu, 0xD8u, 0x95u, 0xA9u,\r
- 0xC8u, 0x19u, 0x2Au, 0x46u, 0x4Bu, 0xA9u, 0x01u, 0xF0u,\r
- 0x2Bu, 0xFCu, 0xA7u, 0xB2u, 0x00u, 0x25u, 0x63u, 0xE0u,\r
- 0x00u, 0x2Du, 0x65u, 0xD1u, 0x3Au, 0x48u, 0x02u, 0xAEu,\r
- 0x4Bu, 0xACu, 0x03u, 0xC8u, 0x86u, 0xE8u, 0x03u, 0x00u,\r
- 0x84u, 0xE8u, 0x03u, 0x00u, 0x01u, 0x26u, 0x08u, 0x24u,\r
- 0x21u, 0xE7u, 0x00u, 0x2Eu, 0x58u, 0xD0u, 0x03u, 0x2Du,\r
- 0x56u, 0xD1u, 0x9Du, 0xF8u, 0x2Eu, 0x01u, 0x9Du, 0xF8u,\r
- 0x2Du, 0x11u, 0xABu, 0xF1u, 0x40u, 0x02u, 0x3Fu, 0x2Au,\r
- 0x41u, 0xEAu, 0x00u, 0x25u, 0x0Au, 0xD8u, 0x2Du, 0x01u,\r
- 0x00u, 0x23u, 0x10u, 0x22u, 0x2Du, 0x48u, 0x11u, 0x18u,\r
- 0x4Cu, 0x5Du, 0x01u, 0x3Au, 0x23u, 0x44u, 0xDBu, 0xB2u,\r
- 0xF8u, 0xD1u, 0x26u, 0xE0u, 0x05u, 0xEBu, 0x0Bu, 0x23u,\r
- 0x1Cu, 0x02u, 0x4Fu, 0xF4u, 0x80u, 0x72u, 0x00u, 0x23u,\r
- 0x01u, 0x3Au, 0x10u, 0x5Du, 0x19u, 0x18u, 0xCBu, 0xB2u,\r
- 0x00u, 0x2Au, 0xF9u, 0xD1u, 0xBBu, 0xF1u, 0x3Fu, 0x0Fu,\r
- 0x17u, 0xD8u, 0x0Bu, 0xF5u, 0x10u, 0x34u, 0x05u, 0xEBu,\r
- 0x04u, 0x20u, 0x41u, 0x01u, 0x54u, 0x5Cu, 0x01u, 0x32u,\r
- 0x1Bu, 0x19u, 0x20u, 0x2Au, 0xDBu, 0xB2u, 0xF9u, 0xD1u,\r
- 0xBBu, 0xF1u, 0x01u, 0x0Fu, 0x09u, 0xD1u, 0xFFu, 0x2Du,\r
- 0x07u, 0xD1u, 0x1Bu, 0x4Du, 0x1Bu, 0x4Cu, 0x28u, 0x78u,\r
- 0x19u, 0x1Au, 0x23u, 0x78u, 0xCAu, 0x1Au, 0x02u, 0xF0u,\r
- 0xFFu, 0x03u, 0x5Du, 0x42u, 0x8Du, 0xF8u, 0x2Cu, 0x51u,\r
- 0x00u, 0x25u, 0x01u, 0x24u, 0xDBu, 0xE6u, 0xFFu, 0xF7u,\r
- 0x29u, 0xFEu, 0x10u, 0xB9u, 0x14u, 0x4Du, 0x80u, 0x24u,\r
- 0x2Cu, 0x70u, 0x00u, 0xF0u, 0x47u, 0xF9u, 0x0Bu, 0xE0u,\r
- 0x04u, 0x25u, 0xD0u, 0xE6u, 0x01u, 0x26u, 0x00u, 0x27u,\r
- 0x04u, 0xE0u, 0x07u, 0x46u, 0x9Au, 0xE7u, 0x05u, 0x25u,\r
- 0x00u, 0x24u, 0xC8u, 0xE6u, 0x03u, 0x25u, 0xFBu, 0xE7u,\r
- 0x04u, 0x25u, 0xF9u, 0xE7u, 0x08u, 0x25u, 0xF7u, 0xE7u,\r
- 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x01u, 0xD1u, 0x47u, 0x46u,\r
- 0x5Eu, 0xE6u, 0x00u, 0x27u, 0xEDu, 0xE6u, 0x0Du, 0xF5u,\r
- 0x61u, 0x7Du, 0xBDu, 0xE8u, 0xF0u, 0x8Fu, 0x00u, 0xBFu,\r
- 0xCCu, 0x20u, 0x00u, 0x00u, 0xFFu, 0x7Fu, 0x00u, 0x40u,\r
- 0xD0u, 0xFFu, 0x01u, 0x00u, 0xD1u, 0xFFu, 0x01u, 0x00u,\r
- 0xFAu, 0x46u, 0x00u, 0x40u, 0x10u, 0xB5u, 0xC8u, 0xB0u,\r
- 0x00u, 0xF0u, 0x94u, 0xF8u, 0x10u, 0xB1u, 0x00u, 0x20u,\r
- 0x00u, 0xF0u, 0x16u, 0xF9u, 0x68u, 0x46u, 0x00u, 0xF0u,\r
- 0xA1u, 0xF8u, 0x10u, 0xB1u, 0x00u, 0x20u, 0x00u, 0xF0u,\r
- 0x0Fu, 0xF9u, 0x16u, 0x48u, 0x03u, 0x68u, 0x19u, 0x68u,\r
- 0x00u, 0x23u, 0x0Au, 0x46u, 0x22u, 0xB1u, 0x12u, 0xF8u,\r
- 0x01u, 0x4Du, 0xE3u, 0x18u, 0xDBu, 0xB2u, 0xF9u, 0xE7u,\r
- 0x42u, 0x68u, 0x10u, 0x78u, 0xC4u, 0x1Au, 0x04u, 0xF0u,\r
- 0xFFu, 0x03u, 0x83u, 0x42u, 0x00u, 0xD1u, 0x11u, 0xB9u,\r
- 0x00u, 0x20u, 0x00u, 0xF0u, 0xF9u, 0xF8u, 0x0Cu, 0x4Cu,\r
- 0xFFu, 0xF7u, 0xD4u, 0xFDu, 0x21u, 0x78u, 0x01u, 0xF0u,\r
- 0xC0u, 0x02u, 0x40u, 0x2Au, 0x00u, 0xD0u, 0x18u, 0xB1u,\r
- 0x00u, 0x20u, 0x20u, 0x70u, 0xFFu, 0xF7u, 0x0Cu, 0xFEu,\r
- 0x14u, 0x20u, 0xFFu, 0xF7u, 0x09u, 0xFEu, 0x80u, 0x20u,\r
- 0x20u, 0x70u, 0x00u, 0xF0u, 0xE7u, 0xF8u, 0x48u, 0xB0u,\r
- 0x10u, 0xBDu, 0x00u, 0xBFu, 0x0Cu, 0xC1u, 0xFFu, 0x1Fu,\r
- 0xFAu, 0x46u, 0x00u, 0x40u, 0x08u, 0xB5u, 0x0Au, 0x4Bu,\r
- 0x1Au, 0x78u, 0x02u, 0xF0u, 0xC0u, 0x00u, 0x80u, 0x28u,\r
- 0x0Cu, 0xD1u, 0x00u, 0x21u, 0x19u, 0x70u, 0x01u, 0x20u,\r
- 0xFFu, 0xF7u, 0x6Au, 0xFDu, 0x30u, 0xB1u, 0x01u, 0x20u,\r
- 0xFFu, 0xF7u, 0x66u, 0xFDu, 0xBDu, 0xE8u, 0x08u, 0x40u,\r
- 0xFFu, 0xF7u, 0x60u, 0xBDu, 0x08u, 0xBDu, 0x00u, 0xBFu,\r
- 0xFAu, 0x46u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0xF8u, 0xB5u, 0x72u, 0xB6u, 0x5Bu, 0x4Bu, 0x01u, 0x22u,\r
+ 0x1Au, 0x70u, 0x06u, 0x22u, 0xA3u, 0xF5u, 0xA0u, 0x63u,\r
+ 0x1Au, 0x70u, 0x52u, 0x22u, 0xA3u, 0xF5u, 0x80u, 0x73u,\r
+ 0x1Au, 0x70u, 0x57u, 0x4Bu, 0x19u, 0x25u, 0x1Au, 0x78u,\r
+ 0x56u, 0x4Bu, 0xD2u, 0xB2u, 0x1Au, 0x70u, 0x40u, 0xF6u,\r
+ 0x18u, 0x02u, 0xA3u, 0xF2u, 0x7Fu, 0x43u, 0x1Au, 0x80u,\r
+ 0x41u, 0xF2u, 0x51u, 0x22u, 0x23u, 0xF8u, 0x02u, 0x2Cu,\r
+ 0x00u, 0x24u, 0x51u, 0x4Bu, 0x4Fu, 0xF4u, 0xF0u, 0x70u,\r
+ 0x1Bu, 0x78u, 0x03u, 0xF0u, 0x01u, 0x03u, 0x43u, 0xEAu,\r
+ 0x44u, 0x04u, 0x00u, 0xF0u, 0x89u, 0xFBu, 0x01u, 0x3Du,\r
+ 0x04u, 0xF0u, 0x03u, 0x04u, 0x18u, 0xD0u, 0x03u, 0x2Cu,\r
+ 0xEFu, 0xD1u, 0x4Au, 0x4Bu, 0x4Fu, 0xF4u, 0x80u, 0x72u,\r
+ 0x1Au, 0x80u, 0x07u, 0x22u, 0x1Au, 0x70u, 0x48u, 0x4Au,\r
+ 0x00u, 0x24u, 0x48u, 0x21u, 0x14u, 0x70u, 0x91u, 0x70u,\r
+ 0x02u, 0x22u, 0x1Cu, 0x70u, 0x5Cu, 0x71u, 0x03u, 0xF8u,\r
+ 0x03u, 0x2Cu, 0x93u, 0xF8u, 0xE4u, 0x26u, 0x42u, 0xF0u,\r
+ 0x04u, 0x02u, 0x83u, 0xF8u, 0xE4u, 0x26u, 0x00u, 0xE0u,\r
+ 0xFEu, 0xE7u, 0x40u, 0x4Bu, 0x00u, 0x21u, 0x23u, 0x44u,\r
+ 0x18u, 0x68u, 0x9Au, 0x88u, 0x06u, 0x34u, 0x01u, 0xF0u,\r
+ 0xF8u, 0xFEu, 0x30u, 0x2Cu, 0xF5u, 0xD1u, 0x00u, 0x23u,\r
+ 0x19u, 0x46u, 0x3Bu, 0x4Cu, 0x00u, 0x22u, 0x18u, 0x59u,\r
+ 0x30u, 0x34u, 0x20u, 0xF0u, 0xFFu, 0x06u, 0xC0u, 0xB2u,\r
+ 0x45u, 0x00u, 0x04u, 0xEBu, 0x41u, 0x04u, 0xAAu, 0x42u,\r
+ 0x08u, 0xD0u, 0x04u, 0xEBu, 0x02u, 0x0Cu, 0xA7u, 0x5Cu,\r
+ 0x9Cu, 0xF8u, 0x01u, 0xC0u, 0x02u, 0x32u, 0x07u, 0xF8u,\r
+ 0x06u, 0xC0u, 0xF4u, 0xE7u, 0x04u, 0x33u, 0x30u, 0x2Bu,\r
+ 0x01u, 0x44u, 0xE6u, 0xD1u, 0x2Fu, 0x4Bu, 0x30u, 0x48u,\r
+ 0x1Au, 0x78u, 0x30u, 0x4Cu, 0x42u, 0xF0u, 0x02u, 0x02u,\r
+ 0x1Au, 0x70u, 0x1Au, 0x7Cu, 0x42u, 0xF0u, 0x02u, 0x02u,\r
+ 0x1Au, 0x74u, 0xA3u, 0xF5u, 0x86u, 0x33u, 0x63u, 0x3Bu,\r
+ 0x1Au, 0x78u, 0x42u, 0xF0u, 0x40u, 0x02u, 0x1Au, 0x70u,\r
+ 0x29u, 0x4Au, 0x11u, 0x78u, 0x41u, 0xF0u, 0x10u, 0x01u,\r
+ 0x11u, 0x70u, 0x28u, 0x4Au, 0x11u, 0x68u, 0x15u, 0x46u,\r
+ 0x01u, 0x60u, 0x51u, 0x68u, 0x41u, 0x60u, 0x55u, 0xF8u,\r
+ 0x08u, 0x0Fu, 0x69u, 0x68u, 0x03u, 0xC4u, 0x29u, 0x89u,\r
+ 0x15u, 0x46u, 0x55u, 0xF8u, 0x12u, 0x0Fu, 0x21u, 0x80u,\r
+ 0x69u, 0x68u, 0xC8u, 0x3Cu, 0x03u, 0xC4u, 0x29u, 0x89u,\r
+ 0x10u, 0x46u, 0x21u, 0x80u, 0x50u, 0xF8u, 0x1Cu, 0x1Fu,\r
+ 0xA4u, 0xF6u, 0x88u, 0x54u, 0xC4u, 0xF8u, 0x92u, 0x1Du,\r
+ 0x41u, 0x68u, 0x1Bu, 0x48u, 0xC4u, 0xF8u, 0x96u, 0x1Du,\r
+ 0x52u, 0xF8u, 0x24u, 0x1Fu, 0x01u, 0x60u, 0x51u, 0x68u,\r
+ 0x18u, 0x4Au, 0x41u, 0x60u, 0x11u, 0x78u, 0x41u, 0xF0u,\r
+ 0x08u, 0x01u, 0x11u, 0x70u, 0x16u, 0x4Au, 0x17u, 0x49u,\r
+ 0x12u, 0x78u, 0xD2u, 0xB2u, 0x02u, 0xF0u, 0x07u, 0x00u,\r
+ 0x12u, 0x09u, 0x08u, 0x70u, 0x4Au, 0x70u, 0x14u, 0x4Au,\r
+ 0x44u, 0x21u, 0x11u, 0x70u, 0x0Fu, 0xCBu, 0x07u, 0xC4u,\r
+ 0x23u, 0x80u, 0xF8u, 0xBDu, 0x00u, 0x48u, 0x00u, 0x40u,\r
+ 0x0Fu, 0x01u, 0x00u, 0x49u, 0xA1u, 0x46u, 0x00u, 0x40u,\r
+ 0x25u, 0x42u, 0x00u, 0x40u, 0x04u, 0x40u, 0x00u, 0x40u,\r
+ 0x06u, 0x40u, 0x00u, 0x40u, 0xC8u, 0x20u, 0x00u, 0x00u,\r
+ 0xF8u, 0x20u, 0x00u, 0x00u, 0x03u, 0x50u, 0x01u, 0x40u,\r
+ 0x02u, 0x51u, 0x00u, 0x40u, 0xF0u, 0x51u, 0x00u, 0x40u,\r
+ 0xC2u, 0x43u, 0x00u, 0x40u, 0x56u, 0x21u, 0x00u, 0x00u,\r
+ 0x62u, 0x51u, 0x00u, 0x40u, 0x22u, 0x43u, 0x00u, 0x40u,\r
+ 0xCFu, 0x01u, 0x00u, 0x49u, 0x6Eu, 0x58u, 0x00u, 0x40u,\r
+ 0x76u, 0x58u, 0x00u, 0x40u, 0x00u, 0x47u, 0x10u, 0xB5u,\r
+ 0x00u, 0x23u, 0x2Au, 0xB1u, 0x01u, 0x3Au, 0x44u, 0x18u,\r
+ 0xA4u, 0x5Cu, 0x23u, 0x44u, 0xDBu, 0xB2u, 0xF8u, 0xE7u,\r
+ 0x18u, 0x46u, 0x10u, 0xBDu, 0x01u, 0x38u, 0x09u, 0x28u,\r
+ 0x42u, 0xD8u, 0xDFu, 0xE8u, 0x00u, 0xF0u, 0x05u, 0x0Bu,\r
+ 0x11u, 0x17u, 0x1Du, 0x23u, 0x2Fu, 0x29u, 0x35u, 0x3Bu,\r
+ 0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF5u,\r
+ 0xE0u, 0x71u, 0x3Bu, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u,\r
+ 0xFFu, 0x31u, 0x01u, 0xF2u, 0xC1u, 0x11u, 0x38u, 0xE0u,\r
+ 0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF2u,\r
+ 0xC5u, 0x11u, 0x2Au, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u,\r
+ 0xFFu, 0x31u, 0x01u, 0xF2u, 0xC9u, 0x11u, 0x2Cu, 0xE0u,\r
+ 0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF5u,\r
+ 0xE8u, 0x71u, 0x23u, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u,\r
+ 0xFFu, 0x31u, 0x01u, 0xF2u, 0xD1u, 0x11u, 0x1Du, 0xE0u,\r
+ 0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF5u,\r
+ 0xEBu, 0x71u, 0x12u, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u,\r
+ 0xFFu, 0x31u, 0x01u, 0xF5u, 0xE9u, 0x71u, 0x0Cu, 0xE0u,\r
+ 0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF5u,\r
+ 0xEAu, 0x71u, 0x06u, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u,\r
+ 0xFFu, 0x31u, 0x01u, 0xF5u, 0xECu, 0x71u, 0x08u, 0xE0u,\r
+ 0x00u, 0x21u, 0x0Bu, 0x78u, 0x48u, 0x78u, 0x43u, 0xEAu,\r
+ 0x00u, 0x20u, 0x70u, 0x47u, 0x08u, 0x78u, 0xC0u, 0xB2u,\r
+ 0x70u, 0x47u, 0x0Bu, 0x78u, 0x4Au, 0x78u, 0x88u, 0x78u,\r
+ 0x00u, 0x04u, 0x40u, 0xEAu, 0x02u, 0x20u, 0x18u, 0x43u,\r
+ 0xCBu, 0x78u, 0x40u, 0xEAu, 0x03u, 0x60u, 0x70u, 0x47u,\r
+ 0x10u, 0xB5u, 0x0Bu, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u,\r
+ 0xC0u, 0x02u, 0x80u, 0x2Au, 0x0Eu, 0xD1u, 0x00u, 0x24u,\r
+ 0x1Cu, 0x70u, 0x02u, 0x20u, 0x21u, 0x46u, 0xFFu, 0xF7u,\r
+ 0x99u, 0xFFu, 0x38u, 0xB1u, 0x21u, 0x46u, 0x02u, 0x20u,\r
+ 0xFFu, 0xF7u, 0x94u, 0xFFu, 0xBDu, 0xE8u, 0x10u, 0x40u,\r
+ 0xFFu, 0xF7u, 0x84u, 0xBFu, 0x10u, 0xBDu, 0x00u, 0xBFu,\r
+ 0xFAu, 0x46u, 0x00u, 0x40u, 0xF8u, 0xB5u, 0x05u, 0x46u,\r
+ 0x29u, 0x46u, 0x03u, 0x20u, 0xFFu, 0xF7u, 0x86u, 0xFFu,\r
+ 0x29u, 0x46u, 0x07u, 0x46u, 0x04u, 0x20u, 0xFFu, 0xF7u,\r
+ 0x81u, 0xFFu, 0x01u, 0x37u, 0x00u, 0xEBu, 0x07u, 0x27u,\r
+ 0x29u, 0x46u, 0x03u, 0x20u, 0xFFu, 0xF7u, 0x7Au, 0xFFu,\r
+ 0x00u, 0x24u, 0x01u, 0x30u, 0x00u, 0x02u, 0x26u, 0x46u,\r
+ 0xB8u, 0x42u, 0x09u, 0xD2u, 0x10u, 0xF8u, 0x01u, 0x3Bu,\r
+ 0x5Au, 0x1Eu, 0xD2u, 0xB2u, 0xFDu, 0x2Au, 0x1Cu, 0x44u,\r
+ 0x98u, 0xBFu, 0x01u, 0x26u, 0xE4u, 0xB2u, 0xF3u, 0xE7u,\r
+ 0x03u, 0x20u, 0x29u, 0x46u, 0xFFu, 0xF7u, 0x66u, 0xFFu,\r
+ 0x11u, 0x4Au, 0x01u, 0x30u, 0x97u, 0x42u, 0x4Fu, 0xEAu,\r
+ 0x00u, 0x23u, 0x4Fu, 0xEAu, 0xD3u, 0x03u, 0x14u, 0xBFu,\r
+ 0xFFu, 0x08u, 0x4Fu, 0xF4u, 0x80u, 0x47u, 0xBBu, 0x42u,\r
+ 0x06u, 0xD2u, 0x03u, 0xF1u, 0x90u, 0x42u, 0x12u, 0x78u,\r
+ 0x01u, 0x33u, 0x14u, 0x44u, 0xE4u, 0xB2u, 0xF6u, 0xE7u,\r
+ 0x01u, 0x20u, 0x29u, 0x46u, 0xFFu, 0xF7u, 0x4Eu, 0xFFu,\r
+ 0x64u, 0x42u, 0xE4u, 0xB2u, 0x84u, 0x42u, 0x04u, 0xD1u,\r
+ 0x00u, 0x2Eu, 0x14u, 0xBFu, 0x00u, 0x20u, 0x06u, 0x20u,\r
+ 0xF8u, 0xBDu, 0x06u, 0x20u, 0xF8u, 0xBDu, 0x00u, 0xBFu,\r
+ 0xC0u, 0xFFu, 0x01u, 0x00u, 0x2Du, 0xE9u, 0xF0u, 0x4Fu,\r
+ 0xADu, 0xF5u, 0x1Bu, 0x7Du, 0x80u, 0x46u, 0x00u, 0xF0u,\r
+ 0x13u, 0xFAu, 0x10u, 0xB1u, 0x00u, 0x20u, 0x00u, 0xF0u,\r
+ 0xDFu, 0xFAu, 0x00u, 0xF0u, 0x39u, 0xFCu, 0x62u, 0xB6u,\r
+ 0x00u, 0x26u, 0x4Fu, 0xF0u, 0x0Au, 0x09u, 0x35u, 0x46u,\r
+ 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x14u, 0xBFu, 0x43u, 0x46u,\r
+ 0xFFu, 0x23u, 0x04u, 0xA8u, 0x4Fu, 0xF4u, 0x96u, 0x71u,\r
+ 0x01u, 0xAAu, 0x00u, 0xF0u, 0x59u, 0xFCu, 0xB8u, 0xF1u,\r
+ 0x00u, 0x0Fu, 0x03u, 0xD0u, 0x09u, 0xF1u, 0xFFu, 0x39u,\r
+ 0x5Fu, 0xFAu, 0x89u, 0xF9u, 0xB9u, 0xF1u, 0x00u, 0x0Fu,\r
+ 0x02u, 0xD0u, 0x00u, 0x28u, 0xE8u, 0xD1u, 0x01u, 0xE0u,\r
+ 0x00u, 0x28u, 0x78u, 0xD1u, 0xBDu, 0xF8u, 0x04u, 0x20u,\r
+ 0x06u, 0x2Au, 0x40u, 0xF2u, 0x89u, 0x81u, 0x9Du, 0xF8u,\r
+ 0x10u, 0x30u, 0x01u, 0x2Bu, 0x40u, 0xF0u, 0x84u, 0x81u,\r
+ 0x9Du, 0xF8u, 0x12u, 0x30u, 0x9Du, 0xF8u, 0x13u, 0x40u,\r
+ 0x43u, 0xEAu, 0x04u, 0x24u, 0xE7u, 0x1Du, 0x04u, 0xABu,\r
+ 0x23u, 0x44u, 0x97u, 0x42u, 0x58u, 0x79u, 0x19u, 0x79u,\r
+ 0x00u, 0xF2u, 0x74u, 0x81u, 0x9Bu, 0x79u, 0x17u, 0x2Bu,\r
+ 0x40u, 0xF0u, 0x72u, 0x81u, 0x23u, 0x1Du, 0x9Bu, 0xB2u,\r
+ 0x00u, 0x22u, 0x3Bu, 0xB1u, 0x0Du, 0xF1u, 0x0Fu, 0x07u,\r
+ 0xFFu, 0x5Cu, 0x01u, 0x3Bu, 0x3Au, 0x44u, 0x92u, 0xB2u,\r
+ 0x9Bu, 0xB2u, 0xF6u, 0xE7u, 0x52u, 0x42u, 0x41u, 0xEAu,\r
+ 0x00u, 0x23u, 0x92u, 0xB2u, 0x93u, 0x42u, 0x40u, 0xF0u,\r
+ 0x61u, 0x81u, 0x51u, 0xE0u, 0x00u, 0x2Eu, 0x00u, 0xF0u,\r
+ 0x5Bu, 0x81u, 0x01u, 0x2Cu, 0x40u, 0xF0u, 0x58u, 0x81u,\r
+ 0x01u, 0x2Fu, 0x00u, 0xF2u, 0x55u, 0x81u, 0xB2u, 0x4Bu,\r
+ 0x1Bu, 0x68u, 0x1Bu, 0x68u, 0xC3u, 0xF3u, 0x07u, 0x42u,\r
+ 0x97u, 0x42u, 0x73u, 0xD1u, 0xC3u, 0xF3u, 0x07u, 0x23u,\r
+ 0x8Du, 0xF8u, 0x14u, 0x30u, 0x1Bu, 0x0Au, 0x8Du, 0xF8u,\r
+ 0x15u, 0x30u, 0x00u, 0x24u, 0xFFu, 0x23u, 0x8Du, 0xF8u,\r
+ 0x16u, 0x30u, 0x8Du, 0xF8u, 0x17u, 0x40u, 0x04u, 0x21u,\r
+ 0x01u, 0x23u, 0x8Du, 0xF8u, 0x10u, 0x30u, 0x00u, 0x22u,\r
+ 0x0Bu, 0x1Du, 0xADu, 0xF8u, 0x06u, 0x10u, 0x8Du, 0xF8u,\r
+ 0x11u, 0x40u, 0x8Du, 0xF8u, 0x12u, 0x10u, 0x8Du, 0xF8u,\r
+ 0x13u, 0x20u, 0x9Bu, 0xB2u, 0x0Du, 0xF1u, 0x0Fu, 0x00u,\r
+ 0xC0u, 0x5Cu, 0x01u, 0x3Bu, 0x02u, 0x44u, 0x9Bu, 0xB2u,\r
+ 0x92u, 0xB2u, 0x00u, 0x2Bu, 0xF6u, 0xD1u, 0x52u, 0x42u,\r
+ 0x92u, 0xB2u, 0x05u, 0xABu, 0x5Au, 0x54u, 0x12u, 0x0Au,\r
+ 0x0Du, 0xF1u, 0x15u, 0x03u, 0x5Au, 0x54u, 0x17u, 0x22u,\r
+ 0x0Du, 0xF1u, 0x16u, 0x03u, 0x5Au, 0x54u, 0x07u, 0x31u,\r
+ 0x04u, 0xA8u, 0x89u, 0xB2u, 0x0Du, 0xF1u, 0x06u, 0x02u,\r
+ 0x96u, 0x23u, 0x00u, 0xF0u, 0xB0u, 0xFBu, 0xB8u, 0xF1u,\r
+ 0x00u, 0x0Fu, 0x3Fu, 0xF4u, 0x69u, 0xAFu, 0x00u, 0x2Eu,\r
+ 0x00u, 0xF0u, 0x19u, 0x81u, 0x01u, 0x26u, 0x63u, 0xE7u,\r
+ 0x9Du, 0xF8u, 0x11u, 0x20u, 0x9Du, 0xF8u, 0x14u, 0x70u,\r
+ 0xA2u, 0xF1u, 0x31u, 0x03u, 0x0Au, 0x2Bu, 0x00u, 0xF2u,\r
+ 0xFEu, 0x80u, 0x01u, 0xA1u, 0x51u, 0xF8u, 0x23u, 0xF0u,\r
+ 0x15u, 0x07u, 0x00u, 0x00u, 0x2Du, 0x06u, 0x00u, 0x00u,\r
+ 0xDFu, 0x08u, 0x00u, 0x00u, 0x3Fu, 0x07u, 0x00u, 0x00u,\r
+ 0xEFu, 0x07u, 0x00u, 0x00u, 0xDFu, 0x08u, 0x00u, 0x00u,\r
+ 0xF5u, 0x07u, 0x00u, 0x00u, 0x13u, 0x08u, 0x00u, 0x00u,\r
+ 0x3Fu, 0x07u, 0x00u, 0x00u, 0x2Fu, 0x08u, 0x00u, 0x00u,\r
+ 0xBDu, 0x08u, 0x00u, 0x00u, 0x00u, 0x2Eu, 0x00u, 0xF0u,\r
+ 0xE7u, 0x80u, 0x00u, 0x2Cu, 0x40u, 0xF0u, 0xE4u, 0x80u,\r
+ 0x20u, 0x46u, 0xFFu, 0xF7u, 0xDBu, 0xFEu, 0xD0u, 0xF1u,\r
+ 0x01u, 0x00u, 0x38u, 0xBFu, 0x00u, 0x20u, 0x8Du, 0xF8u,\r
+ 0x14u, 0x00u, 0xC1u, 0xE0u, 0x8Cu, 0xBFu, 0x00u, 0x23u,\r
+ 0x4Fu, 0xF4u, 0x80u, 0x73u, 0x88u, 0xE7u, 0x34u, 0x2Au,\r
+ 0x12u, 0xD1u, 0x00u, 0x2Eu, 0x00u, 0xF0u, 0xD0u, 0x80u,\r
+ 0x03u, 0x2Cu, 0x40u, 0xF0u, 0xCDu, 0x80u, 0xA7u, 0xF1u,\r
+ 0x40u, 0x03u, 0x3Fu, 0x2Bu, 0x8Cu, 0xBFu, 0x4Fu, 0xF4u,\r
+ 0x90u, 0x75u, 0x10u, 0x25u, 0x4Fu, 0xA8u, 0x00u, 0x21u,\r
+ 0x2Au, 0x46u, 0x01u, 0xF0u, 0xA2u, 0xFCu, 0x05u, 0xE0u,\r
+ 0x00u, 0x2Eu, 0x00u, 0xF0u, 0xBDu, 0x80u, 0x02u, 0x2Cu,\r
+ 0x40u, 0xF2u, 0xBAu, 0x80u, 0x03u, 0x3Cu, 0x4Fu, 0xA8u,\r
+ 0x28u, 0x44u, 0x0Du, 0xF1u, 0x17u, 0x01u, 0x22u, 0x46u,\r
+ 0x01u, 0xF0u, 0x8Au, 0xFCu, 0xA7u, 0xF1u, 0x40u, 0x03u,\r
+ 0x25u, 0x44u, 0x3Fu, 0x2Bu, 0xADu, 0xB2u, 0x03u, 0xD8u,\r
+ 0x00u, 0xF0u, 0xB4u, 0xF9u, 0x10u, 0x23u, 0x01u, 0xE0u,\r
+ 0x4Fu, 0xF4u, 0x90u, 0x73u, 0x9Du, 0x42u, 0x40u, 0xF0u,\r
+ 0x97u, 0x80u, 0x9Du, 0xF8u, 0x16u, 0x10u, 0x9Du, 0xF8u,\r
+ 0x15u, 0x30u, 0x3Fu, 0x2Fu, 0x43u, 0xEAu, 0x01u, 0x21u,\r
+ 0x0Fu, 0xD8u, 0x55u, 0x4Bu, 0x01u, 0xEBu, 0x07u, 0x22u,\r
+ 0x1Bu, 0x68u, 0x92u, 0xB2u, 0x1Bu, 0x68u, 0xC3u, 0xF3u,\r
+ 0x0Fu, 0x20u, 0x13u, 0xF0u, 0xFFu, 0x0Fu, 0x1Cu, 0xBFu,\r
+ 0x01u, 0x30u, 0x80u, 0xB2u, 0x82u, 0x42u, 0xC0u, 0xF0u,\r
+ 0x82u, 0x80u, 0x2Bu, 0x46u, 0x4Fu, 0xAAu, 0x38u, 0x46u,\r
+ 0x00u, 0xF0u, 0x2Eu, 0xF9u, 0x00u, 0x28u, 0x0Cu, 0xBFu,\r
+ 0x00u, 0x24u, 0x0Au, 0x24u, 0x01u, 0x26u, 0x00u, 0xF0u,\r
+ 0xD5u, 0xF9u, 0x00u, 0x25u, 0x78u, 0xE0u, 0x00u, 0x2Eu,\r
+ 0x7Au, 0xD0u, 0x7Du, 0xE0u, 0x00u, 0x2Eu, 0x77u, 0xD0u,\r
+ 0x2Fu, 0x19u, 0xB7u, 0xF5u, 0x96u, 0x7Fu, 0x71u, 0xD8u,\r
+ 0x4Fu, 0xA8u, 0x28u, 0x44u, 0x22u, 0x46u, 0x05u, 0xA9u,\r
+ 0x01u, 0xF0u, 0x46u, 0xFCu, 0xBDu, 0xB2u, 0x00u, 0x24u,\r
+ 0x66u, 0xE0u, 0x00u, 0x2Cu, 0x68u, 0xD1u, 0x3Du, 0x4Au,\r
+ 0x02u, 0xABu, 0x92u, 0xE8u, 0x03u, 0x00u, 0x05u, 0xAAu,\r
+ 0x83u, 0xE8u, 0x03u, 0x00u, 0x82u, 0xE8u, 0x03u, 0x00u,\r
+ 0x01u, 0x26u, 0x08u, 0x21u, 0x1Cu, 0xE7u, 0x00u, 0x2Eu,\r
+ 0x5Au, 0xD0u, 0x03u, 0x2Cu, 0x58u, 0xD1u, 0x9Du, 0xF8u,\r
+ 0x15u, 0x30u, 0x9Du, 0xF8u, 0x16u, 0xA0u, 0x43u, 0xEAu,\r
+ 0x0Au, 0x2Au, 0xA7u, 0xF1u, 0x40u, 0x03u, 0x3Fu, 0x2Bu,\r
+ 0x07u, 0xD8u, 0x31u, 0x48u, 0x4Fu, 0xEAu, 0x0Au, 0x11u,\r
+ 0x10u, 0x22u, 0xFFu, 0xF7u, 0xC4u, 0xFDu, 0x04u, 0x46u,\r
+ 0x2Au, 0xE0u, 0x4Fu, 0xEAu, 0x07u, 0x2Bu, 0x0Au, 0xEBu,\r
+ 0x0Bu, 0x01u, 0x00u, 0x20u, 0x09u, 0x02u, 0x4Fu, 0xF4u,\r
+ 0x80u, 0x72u, 0xFFu, 0xF7u, 0xB8u, 0xFDu, 0x3Fu, 0x2Fu,\r
+ 0x04u, 0x46u, 0x1Du, 0xD8u, 0x0Bu, 0xF1u, 0x10u, 0x7Bu,\r
+ 0xD3u, 0x44u, 0x4Fu, 0xEAu, 0x4Bu, 0x1Bu, 0x00u, 0x23u,\r
+ 0x13u, 0xF8u, 0x0Bu, 0x20u, 0x01u, 0x33u, 0x14u, 0x44u,\r
+ 0x20u, 0x2Bu, 0xE4u, 0xB2u, 0xF8u, 0xD1u, 0x01u, 0x2Fu,\r
+ 0x0Eu, 0xD1u, 0xBAu, 0xF1u, 0xFFu, 0x0Fu, 0x0Bu, 0xD1u,\r
+ 0x00u, 0x21u, 0x05u, 0x20u, 0xFFu, 0xF7u, 0xAAu, 0xFDu,\r
+ 0x20u, 0x1Au, 0xC4u, 0xB2u, 0x00u, 0x21u, 0x06u, 0x20u,\r
+ 0xFFu, 0xF7u, 0xA4u, 0xFDu, 0x20u, 0x1Au, 0xC4u, 0xB2u,\r
+ 0x64u, 0x42u, 0x8Du, 0xF8u, 0x14u, 0x40u, 0x00u, 0x24u,\r
+ 0x01u, 0x21u, 0xD5u, 0xE6u, 0x00u, 0x20u, 0xFFu, 0xF7u,\r
+ 0x0Du, 0xFEu, 0x10u, 0xB9u, 0x13u, 0x4Bu, 0x80u, 0x22u,\r
+ 0x1Au, 0x70u, 0x00u, 0xF0u, 0x3Fu, 0xF9u, 0x0Bu, 0xE0u,\r
+ 0x01u, 0x26u, 0x00u, 0x25u, 0x06u, 0xE0u, 0x01u, 0x26u,\r
+ 0x00u, 0x25u, 0x0Au, 0x24u, 0x00u, 0xE0u, 0x05u, 0x24u,\r
+ 0x00u, 0x21u, 0xC1u, 0xE6u, 0x03u, 0x24u, 0xFBu, 0xE7u,\r
+ 0x04u, 0x24u, 0xF9u, 0xE7u, 0x08u, 0x24u, 0xF7u, 0xE7u,\r
+ 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x01u, 0xD1u, 0x45u, 0x46u,\r
+ 0x4Eu, 0xE6u, 0x00u, 0x25u, 0xE6u, 0xE6u, 0x0Du, 0xF5u,\r
+ 0x1Bu, 0x7Du, 0xBDu, 0xE8u, 0xF0u, 0x8Fu, 0x00u, 0xBFu,\r
+ 0x0Cu, 0xC1u, 0xFFu, 0x1Fu, 0x84u, 0x21u, 0x00u, 0x00u,\r
+ 0x00u, 0x80u, 0x00u, 0x40u, 0xFAu, 0x46u, 0x00u, 0x40u,\r
+ 0x70u, 0xB5u, 0x00u, 0x20u, 0xFFu, 0xF7u, 0xDEu, 0xFDu,\r
+ 0x15u, 0x4Du, 0x00u, 0x28u, 0x2Bu, 0x68u, 0x4Fu, 0xF0u,\r
+ 0x00u, 0x00u, 0x1Cu, 0x68u, 0x01u, 0x46u, 0x22u, 0x46u,\r
+ 0x0Cu, 0xBFu, 0x00u, 0x26u, 0x06u, 0x26u, 0xFFu, 0xF7u,\r
+ 0x52u, 0xFDu, 0x6Bu, 0x68u, 0x1Bu, 0x78u, 0x18u, 0x1Au,\r
+ 0x00u, 0xF0u, 0xFFu, 0x00u, 0x98u, 0x42u, 0x00u, 0xD1u,\r
+ 0x14u, 0xB9u, 0x00u, 0x20u, 0x00u, 0xF0u, 0xFCu, 0xF8u,\r
+ 0x0Au, 0x4Cu, 0x23u, 0x78u, 0x03u, 0xF0u, 0xC0u, 0x03u,\r
+ 0x40u, 0x2Bu, 0x00u, 0xD0u, 0x1Eu, 0xB1u, 0x00u, 0x20u,\r
+ 0x20u, 0x70u, 0xFFu, 0xF7u, 0x07u, 0xFEu, 0x14u, 0x20u,\r
+ 0xFFu, 0xF7u, 0x04u, 0xFEu, 0x80u, 0x23u, 0x23u, 0x70u,\r
+ 0xBDu, 0xE8u, 0x70u, 0x40u, 0x00u, 0xF0u, 0xEAu, 0xB8u,\r
+ 0x0Cu, 0xC1u, 0xFFu, 0x1Fu, 0xFAu, 0x46u, 0x00u, 0x40u,\r
0x02u, 0x30u, 0x80u, 0x08u, 0x00u, 0xF0u, 0x05u, 0x80u,\r
0x00u, 0xBFu, 0x01u, 0x38u, 0x00u, 0x46u, 0x7Fu, 0xF4u,\r
0xFCu, 0xAFu, 0x70u, 0x47u, 0xEFu, 0xF3u, 0x10u, 0x80u,\r
0x72u, 0xB6u, 0x70u, 0x47u, 0x80u, 0xF3u, 0x10u, 0x88u,\r
0x70u, 0x47u, 0x00u, 0xBFu, 0xAFu, 0xF3u, 0x00u, 0x80u,\r
- 0x01u, 0x20u, 0x10u, 0xB5u, 0x00u, 0xF0u, 0x60u, 0xF9u,\r
- 0x07u, 0x28u, 0x09u, 0xD0u, 0x4Fu, 0xF0u, 0xFFu, 0x34u,\r
- 0x17u, 0xE0u, 0x0Eu, 0x4Bu, 0x18u, 0x78u, 0x00u, 0xF0u,\r
- 0x02u, 0x01u, 0xCAu, 0xB2u, 0x00u, 0x2Au, 0xF5u, 0xD1u,\r
- 0x02u, 0x21u, 0x0Bu, 0x48u, 0x00u, 0xF0u, 0xECu, 0xF8u,\r
- 0x02u, 0x28u, 0xF2u, 0xD1u, 0x07u, 0x4Cu, 0x23u, 0x78u,\r
- 0x03u, 0xF0u, 0x02u, 0x00u, 0xC1u, 0xB2u, 0x19u, 0xB9u,\r
- 0x01u, 0x20u, 0x00u, 0xF0u, 0xAFu, 0xF8u, 0xF5u, 0xE7u,\r
- 0x00u, 0x24u, 0x00u, 0xF0u, 0x7Fu, 0xF9u, 0x20u, 0x46u,\r
- 0x10u, 0xBDu, 0x00u, 0xBFu, 0x22u, 0x47u, 0x00u, 0x40u,\r
- 0x57u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x00u, 0xF0u,\r
- 0xC1u, 0xF8u, 0x00u, 0xF0u, 0x53u, 0xF9u, 0x58u, 0xB9u,\r
- 0xFFu, 0xF7u, 0xCEu, 0xFFu, 0x48u, 0xB9u, 0x00u, 0xF0u,\r
- 0xB9u, 0xF8u, 0x00u, 0xF0u, 0x4Bu, 0xF9u, 0x18u, 0xB9u,\r
- 0xBDu, 0xE8u, 0x08u, 0x40u, 0xFFu, 0xF7u, 0xC4u, 0xBFu,\r
- 0x04u, 0x20u, 0x08u, 0xBDu, 0x38u, 0xB5u, 0x04u, 0x46u,\r
- 0x00u, 0xF0u, 0xACu, 0xF8u, 0x4Cu, 0xB1u, 0x00u, 0xF0u,\r
- 0x3Du, 0xF9u, 0x05u, 0x46u, 0x38u, 0xB9u, 0x05u, 0x4Bu,\r
- 0x1Cu, 0x60u, 0x00u, 0xF0u, 0x57u, 0xF9u, 0x28u, 0x46u,\r
- 0x38u, 0xBDu, 0x01u, 0x20u, 0x38u, 0xBDu, 0x04u, 0x20u,\r
- 0x38u, 0xBDu, 0x00u, 0xBFu, 0x44u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0xF8u, 0xB5u, 0x05u, 0x46u, 0x0Eu, 0x46u, 0x17u, 0x46u,\r
- 0x1Cu, 0x46u, 0x00u, 0xF0u, 0x27u, 0xF9u, 0xF0u, 0xB9u,\r
- 0x22u, 0x46u, 0x28u, 0x46u, 0x39u, 0x46u, 0x00u, 0xF0u,\r
- 0xB9u, 0xF8u, 0x07u, 0x28u, 0x04u, 0x46u, 0x13u, 0xD1u,\r
- 0x1Du, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u, 0x02u, 0x00u,\r
- 0xC1u, 0xB2u, 0x19u, 0xB9u, 0x01u, 0x20u, 0x00u, 0xF0u,\r
- 0x61u, 0xF8u, 0xF5u, 0xE7u, 0x1Cu, 0x78u, 0x04u, 0xF0u,\r
- 0x02u, 0x02u, 0xD0u, 0xB2u, 0x10u, 0xB1u, 0x1Bu, 0x78u,\r
- 0x9Bu, 0x08u, 0x06u, 0xD0u, 0x4Fu, 0xF0u, 0xFFu, 0x34u,\r
- 0x00u, 0xF0u, 0x28u, 0xF9u, 0x22u, 0xE0u, 0x04u, 0x24u,\r
- 0x20u, 0xE0u, 0x12u, 0x4Cu, 0x28u, 0x46u, 0x22u, 0x78u,\r
- 0x63u, 0x78u, 0x31u, 0x46u, 0x00u, 0xF0u, 0xBCu, 0xF8u,\r
- 0x07u, 0x28u, 0x04u, 0x46u, 0xF0u, 0xD1u, 0x0Cu, 0x49u,\r
- 0x0Au, 0x78u, 0x02u, 0xF0u, 0x02u, 0x00u, 0xC3u, 0xB2u,\r
- 0x1Bu, 0xB9u, 0x01u, 0x20u, 0x00u, 0xF0u, 0x3Eu, 0xF8u,\r
- 0xF5u, 0xE7u, 0x0Cu, 0x78u, 0x04u, 0xF0u, 0x02u, 0x02u,\r
- 0xD0u, 0xB2u, 0x00u, 0x28u, 0xDEu, 0xD0u, 0x09u, 0x78u,\r
- 0x8Bu, 0x08u, 0x14u, 0xBFu, 0x4Fu, 0xF0u, 0xFFu, 0x34u,\r
- 0x00u, 0x24u, 0xD9u, 0xE7u, 0x20u, 0x46u, 0xF8u, 0xBDu,\r
- 0x22u, 0x47u, 0x00u, 0x40u, 0x57u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x04u, 0x4Bu, 0x1Au, 0x78u, 0x42u, 0xF0u, 0x10u, 0x00u,\r
- 0x18u, 0x70u, 0x19u, 0x7Cu, 0x41u, 0xF0u, 0x10u, 0x02u,\r
- 0x1Au, 0x74u, 0x70u, 0x47u, 0xACu, 0x43u, 0x00u, 0x40u,\r
+ 0x38u, 0xB5u, 0x00u, 0xF0u, 0x2Du, 0xF9u, 0x00u, 0xF0u,\r
+ 0xD9u, 0xF9u, 0x00u, 0x28u, 0x38u, 0xD1u, 0x00u, 0xF0u,\r
+ 0x0Fu, 0xFAu, 0x07u, 0x28u, 0x04u, 0x46u, 0x0Fu, 0xD1u,\r
+ 0x1Bu, 0x4Bu, 0x1Au, 0x78u, 0x90u, 0x07u, 0x03u, 0xD4u,\r
+ 0x01u, 0x20u, 0x00u, 0xF0u, 0xDBu, 0xF8u, 0xF7u, 0xE7u,\r
+ 0x1Au, 0x78u, 0x91u, 0x07u, 0x04u, 0xD5u, 0x1Bu, 0x78u,\r
+ 0x9Bu, 0x08u, 0x14u, 0xBFu, 0x07u, 0x24u, 0x00u, 0x24u,\r
+ 0x00u, 0xF0u, 0xE0u, 0xF9u, 0x0Cu, 0xBBu, 0x00u, 0xF0u,\r
+ 0x0Fu, 0xF9u, 0x00u, 0xF0u, 0xBBu, 0xF9u, 0xD8u, 0xB9u,\r
+ 0x01u, 0x20u, 0x00u, 0xF0u, 0x9Du, 0xF9u, 0x07u, 0x28u,\r
+ 0x05u, 0xD0u, 0x4Fu, 0xF0u, 0xFFu, 0x34u, 0x10u, 0xE0u,\r
+ 0x2Bu, 0x78u, 0x9Bu, 0x07u, 0xF9u, 0xD4u, 0x0Bu, 0x48u,\r
+ 0x02u, 0x21u, 0x00u, 0xF0u, 0x0Fu, 0xF9u, 0x02u, 0x28u,\r
+ 0x07u, 0x4Du, 0xF5u, 0xD1u, 0x2Bu, 0x78u, 0x9Au, 0x07u,\r
+ 0x03u, 0xD4u, 0x01u, 0x20u, 0x00u, 0xF0u, 0xB2u, 0xF8u,\r
+ 0xF8u, 0xE7u, 0x00u, 0xF0u, 0xBFu, 0xF9u, 0x00u, 0xE0u,\r
+ 0x04u, 0x24u, 0x20u, 0x46u, 0x38u, 0xBDu, 0x00u, 0xBFu,\r
+ 0x22u, 0x47u, 0x00u, 0x40u, 0x50u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x41u, 0x28u, 0xF8u, 0xB5u, 0x05u, 0x46u, 0x0Eu, 0x46u,\r
+ 0x17u, 0x46u, 0x1Cu, 0x46u, 0x0Au, 0xD8u, 0xC1u, 0x1Eu,\r
+ 0x3Cu, 0x29u, 0x8Cu, 0xBFu, 0x00u, 0x21u, 0x01u, 0x21u,\r
+ 0x3Fu, 0x28u, 0x04u, 0xD8u, 0xB6u, 0xF5u, 0x80u, 0x7Fu,\r
+ 0x29u, 0xD8u, 0x05u, 0xE0u, 0x01u, 0x21u, 0x81u, 0x2Eu,\r
+ 0x28u, 0xBFu, 0x01u, 0x21u, 0x10u, 0x2Cu, 0x22u, 0xD1u,\r
+ 0x0Fu, 0xB3u, 0x01u, 0xBBu, 0x00u, 0xF0u, 0x7Au, 0xF9u,\r
+ 0xF8u, 0xB9u, 0x23u, 0x46u, 0x28u, 0x46u, 0x31u, 0x46u,\r
+ 0x3Au, 0x46u, 0x00u, 0xF0u, 0xF1u, 0xF8u, 0x07u, 0x28u,\r
+ 0x04u, 0x46u, 0x11u, 0xD1u, 0x1Bu, 0x4Bu, 0x1Au, 0x78u,\r
+ 0x1Fu, 0x46u, 0x12u, 0xF0u, 0x02u, 0x0Fu, 0x03u, 0xD1u,\r
+ 0x01u, 0x20u, 0x00u, 0xF0u, 0x77u, 0xF8u, 0xF5u, 0xE7u,\r
+ 0x1Au, 0x78u, 0x90u, 0x07u, 0x02u, 0xD5u, 0x1Bu, 0x78u,\r
+ 0x9Bu, 0x08u, 0x08u, 0xD0u, 0x4Fu, 0xF0u, 0xFFu, 0x34u,\r
+ 0x00u, 0xF0u, 0x7Cu, 0xF9u, 0x1Fu, 0xE0u, 0x01u, 0x24u,\r
+ 0x1Du, 0xE0u, 0x04u, 0x24u, 0x1Bu, 0xE0u, 0x10u, 0x4Bu,\r
+ 0x28u, 0x46u, 0x1Au, 0x78u, 0x31u, 0x46u, 0x5Bu, 0x78u,\r
+ 0x00u, 0xF0u, 0x16u, 0xF9u, 0x07u, 0x28u, 0x04u, 0x46u,\r
+ 0xEEu, 0xD1u, 0x3Au, 0x78u, 0x09u, 0x4Bu, 0x91u, 0x07u,\r
+ 0x03u, 0xD4u, 0x01u, 0x20u, 0x00u, 0xF0u, 0x56u, 0xF8u,\r
+ 0xF7u, 0xE7u, 0x1Au, 0x78u, 0x92u, 0x07u, 0xE1u, 0xD5u,\r
+ 0x1Bu, 0x78u, 0x9Bu, 0x08u, 0x0Cu, 0xBFu, 0x00u, 0x24u,\r
+ 0x6Fu, 0xF0u, 0x00u, 0x04u, 0xDCu, 0xE7u, 0x20u, 0x46u,\r
+ 0xF8u, 0xBDu, 0x00u, 0xBFu, 0x22u, 0x47u, 0x00u, 0x40u,\r
+ 0x50u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0xFFu, 0xF7u,\r
+ 0x49u, 0xFFu, 0x0Fu, 0x4Bu, 0x1Au, 0x78u, 0x0Cu, 0x33u,\r
+ 0x42u, 0xF0u, 0x08u, 0x02u, 0x03u, 0xF8u, 0x0Cu, 0x2Cu,\r
+ 0x1Au, 0x79u, 0x42u, 0xF0u, 0x08u, 0x02u, 0x1Au, 0x71u,\r
+ 0xC8u, 0x22u, 0x83u, 0xF8u, 0x55u, 0x23u, 0x1Au, 0x78u,\r
+ 0x42u, 0xF0u, 0x10u, 0x02u, 0x1Au, 0x70u, 0x1Au, 0x7Cu,\r
+ 0x42u, 0xF0u, 0x10u, 0x02u, 0x1Au, 0x74u, 0x05u, 0x4Bu,\r
+ 0x1Bu, 0x78u, 0x9Bu, 0x06u, 0xFBu, 0xD5u, 0xBDu, 0xE8u,\r
+ 0x08u, 0x40u, 0xFFu, 0xF7u, 0x2Fu, 0xBFu, 0x00u, 0xBFu,\r
+ 0xA0u, 0x43u, 0x00u, 0x40u, 0x00u, 0x47u, 0x00u, 0x40u,\r
0x01u, 0xBEu, 0x70u, 0x47u, 0x02u, 0x4Bu, 0x1Au, 0x78u,\r
- 0x42u, 0xF0u, 0x01u, 0x00u, 0x18u, 0x70u, 0x70u, 0x47u,\r
+ 0x42u, 0xF0u, 0x01u, 0x02u, 0x1Au, 0x70u, 0x70u, 0x47u,\r
0xF6u, 0x46u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x04u, 0x46u,\r
0xB4u, 0xF5u, 0x00u, 0x4Fu, 0x06u, 0x4Bu, 0x05u, 0xD9u,\r
- 0x18u, 0x68u, 0xFFu, 0xF7u, 0x29u, 0xFFu, 0xA4u, 0xF5u,\r
+ 0x18u, 0x68u, 0xFFu, 0xF7u, 0x09u, 0xFFu, 0xA4u, 0xF5u,\r
0x00u, 0x44u, 0xF5u, 0xE7u, 0x58u, 0x68u, 0x60u, 0x43u,\r
- 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x20u, 0xBFu,\r
- 0x14u, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x4Bu, 0x19u, 0x7Au,\r
- 0x48u, 0x43u, 0xFFu, 0xF7u, 0x19u, 0xBFu, 0x00u, 0xBFu,\r
- 0x14u, 0xC1u, 0xFFu, 0x1Fu, 0x05u, 0x4Bu, 0x00u, 0xF0u,\r
- 0x1Fu, 0x00u, 0x1Bu, 0x68u, 0x00u, 0xF1u, 0x10u, 0x02u,\r
- 0x53u, 0xF8u, 0x22u, 0x00u, 0x43u, 0xF8u, 0x22u, 0x10u,\r
- 0x70u, 0x47u, 0x00u, 0xBFu, 0x08u, 0xEDu, 0x00u, 0xE0u,\r
- 0x00u, 0xF0u, 0x1Fu, 0x00u, 0x00u, 0xF1u, 0x60u, 0x43u,\r
- 0x49u, 0x01u, 0x03u, 0xF5u, 0x64u, 0x42u, 0xC8u, 0xB2u,\r
- 0x10u, 0x70u, 0x70u, 0x47u, 0x08u, 0xB5u, 0xFFu, 0xF7u,\r
- 0x05u, 0xFFu, 0x06u, 0x4Bu, 0x1Au, 0x78u, 0x42u, 0xF0u,\r
- 0x08u, 0x01u, 0x19u, 0x70u, 0x1Au, 0x7Cu, 0x42u, 0xF0u,\r
- 0x08u, 0x01u, 0x19u, 0x74u, 0xBDu, 0xE8u, 0x08u, 0x40u,\r
- 0xFFu, 0xF7u, 0xFCu, 0xBEu, 0xA0u, 0x43u, 0x00u, 0x40u,\r
- 0x70u, 0xB5u, 0x06u, 0x46u, 0x0Du, 0x46u, 0x00u, 0x24u,\r
- 0xE3u, 0xB2u, 0xABu, 0x42u, 0x0Cu, 0xD2u, 0x07u, 0x48u,\r
- 0x01u, 0x78u, 0xCBu, 0x07u, 0x03u, 0xD4u, 0x01u, 0x20u,\r
- 0xFFu, 0xF7u, 0xC0u, 0xFFu, 0xF7u, 0xE7u, 0x04u, 0x4Au,\r
- 0x13u, 0x78u, 0x33u, 0x55u, 0x01u, 0x34u, 0xEFu, 0xE7u,\r
- 0x28u, 0x46u, 0x70u, 0xBDu, 0x22u, 0x47u, 0x00u, 0x40u,\r
- 0x20u, 0x47u, 0x00u, 0x40u, 0x30u, 0xB5u, 0x10u, 0x4Bu,\r
- 0x1Cu, 0x78u, 0x04u, 0xF0u, 0x02u, 0x04u, 0xE4u, 0xB2u,\r
- 0xACu, 0xB1u, 0x0Eu, 0x4Cu, 0xB6u, 0x25u, 0x25u, 0x70u,\r
- 0xD5u, 0x25u, 0x25u, 0x70u, 0x02u, 0x25u, 0x25u, 0x70u,\r
- 0x1Bu, 0x78u, 0x2Bu, 0x40u, 0xDBu, 0xB2u, 0x63u, 0xB9u,\r
- 0x20u, 0x70u, 0x98u, 0xB2u, 0x90u, 0x42u, 0x04u, 0xD2u,\r
- 0xCCu, 0x5Cu, 0x06u, 0x48u, 0x01u, 0x33u, 0x04u, 0x70u,\r
- 0xF7u, 0xE7u, 0x07u, 0x20u, 0x30u, 0xBDu, 0x04u, 0x20u,\r
- 0x30u, 0xBDu, 0x09u, 0x20u, 0x30u, 0xBDu, 0x00u, 0xBFu,\r
+ 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x00u, 0xBFu,\r
+ 0x14u, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x4Bu, 0x1Bu, 0x7Au,\r
+ 0x58u, 0x43u, 0xFFu, 0xF7u, 0xF9u, 0xBEu, 0x00u, 0xBFu,\r
+ 0x14u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0xFFu, 0xF7u,\r
+ 0xFDu, 0xFEu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu,\r
+ 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu,\r
+ 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu,\r
+ 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu,\r
+ 0x00u, 0xBFu, 0x06u, 0x4Bu, 0x1Au, 0x88u, 0x92u, 0xB2u,\r
+ 0x42u, 0xF0u, 0x04u, 0x02u, 0x1Au, 0x80u, 0x1Bu, 0x88u,\r
+ 0xBFu, 0xF3u, 0x6Fu, 0x8Fu, 0xBDu, 0xE8u, 0x08u, 0x40u,\r
+ 0xFFu, 0xF7u, 0xE4u, 0xBEu, 0x00u, 0x48u, 0x00u, 0x40u,\r
+ 0x05u, 0x4Bu, 0x00u, 0xF0u, 0x1Fu, 0x00u, 0x1Bu, 0x68u,\r
+ 0x00u, 0xF1u, 0x10u, 0x02u, 0x53u, 0xF8u, 0x22u, 0x00u,\r
+ 0x43u, 0xF8u, 0x22u, 0x10u, 0x70u, 0x47u, 0x00u, 0xBFu,\r
+ 0x08u, 0xEDu, 0x00u, 0xE0u, 0x00u, 0xF0u, 0x1Fu, 0x00u,\r
+ 0x00u, 0xF1u, 0x60u, 0x40u, 0x49u, 0x01u, 0x00u, 0xF5u,\r
+ 0x64u, 0x40u, 0xC9u, 0xB2u, 0x01u, 0x70u, 0x70u, 0x47u,\r
+ 0x08u, 0xB5u, 0xFFu, 0xF7u, 0xC3u, 0xFEu, 0x06u, 0x4Bu,\r
+ 0x1Au, 0x78u, 0x42u, 0xF0u, 0x08u, 0x02u, 0x1Au, 0x70u,\r
+ 0x1Au, 0x7Cu, 0x42u, 0xF0u, 0x08u, 0x02u, 0x1Au, 0x74u,\r
+ 0xBDu, 0xE8u, 0x08u, 0x40u, 0xFFu, 0xF7u, 0xBAu, 0xBEu,\r
+ 0xA0u, 0x43u, 0x00u, 0x40u, 0x70u, 0xB5u, 0x06u, 0x46u,\r
+ 0x0Du, 0x46u, 0x00u, 0x24u, 0xE3u, 0xB2u, 0xABu, 0x42u,\r
+ 0x0Cu, 0xD2u, 0x07u, 0x4Bu, 0x1Bu, 0x78u, 0xDBu, 0x07u,\r
+ 0x03u, 0xD4u, 0x01u, 0x20u, 0xFFu, 0xF7u, 0x9Eu, 0xFFu,\r
+ 0xF7u, 0xE7u, 0x04u, 0x4Bu, 0x1Bu, 0x78u, 0x33u, 0x55u,\r
+ 0x01u, 0x34u, 0xEFu, 0xE7u, 0x28u, 0x46u, 0x70u, 0xBDu,\r
+ 0x22u, 0x47u, 0x00u, 0x40u, 0x20u, 0x47u, 0x00u, 0x40u,\r
+ 0xF0u, 0xB5u, 0x21u, 0x4Du, 0x2Cu, 0x78u, 0xA4u, 0x07u,\r
+ 0x39u, 0xD5u, 0x20u, 0x4Cu, 0xB6u, 0x26u, 0x26u, 0x70u,\r
+ 0xD5u, 0x26u, 0x26u, 0x70u, 0x02u, 0x26u, 0x26u, 0x70u,\r
+ 0x2Eu, 0x78u, 0x06u, 0xF0u, 0x02u, 0x06u, 0x06u, 0xF0u,\r
+ 0xFFu, 0x05u, 0x76u, 0xBBu, 0x20u, 0x2Bu, 0x20u, 0x70u,\r
+ 0x01u, 0xD0u, 0x00u, 0x25u, 0x0Cu, 0xE0u, 0x3Fu, 0x28u,\r
+ 0xFBu, 0xD8u, 0x01u, 0xEBu, 0x00u, 0x27u, 0x3Fu, 0x02u,\r
+ 0xEEu, 0x5Du, 0x01u, 0x35u, 0xF6u, 0xB2u, 0xB5u, 0xF5u,\r
+ 0x80u, 0x7Fu, 0x26u, 0x70u, 0xF8u, 0xD1u, 0xF0u, 0xE7u,\r
+ 0xAEu, 0xB2u, 0x9Eu, 0x42u, 0x03u, 0xD2u, 0x56u, 0x5Du,\r
+ 0x01u, 0x35u, 0x26u, 0x70u, 0xF8u, 0xE7u, 0xB3u, 0xF5u,\r
+ 0x80u, 0x7Fu, 0x01u, 0xD0u, 0x07u, 0x20u, 0xF0u, 0xBDu,\r
+ 0x3Fu, 0x28u, 0xFBu, 0xD8u, 0x00u, 0xF5u, 0x10u, 0x30u,\r
+ 0x01u, 0xEBu, 0x00u, 0x21u, 0x49u, 0x01u, 0x00u, 0x23u,\r
+ 0x5Au, 0x5Cu, 0x01u, 0x33u, 0xD2u, 0xB2u, 0x20u, 0x2Bu,\r
+ 0x22u, 0x70u, 0xF9u, 0xD1u, 0xEEu, 0xE7u, 0x04u, 0x20u,\r
+ 0xF0u, 0xBDu, 0x09u, 0x20u, 0xF0u, 0xBDu, 0x00u, 0xBFu,\r
0x22u, 0x47u, 0x00u, 0x40u, 0x20u, 0x47u, 0x00u, 0x40u,\r
- 0x70u, 0xB5u, 0x0Fu, 0x4Du, 0x2Cu, 0x78u, 0x04u, 0xF0u,\r
- 0x02u, 0x04u, 0xE4u, 0xB2u, 0xA4u, 0xB1u, 0x0Du, 0x4Cu,\r
- 0xB6u, 0x26u, 0x26u, 0x70u, 0xD8u, 0x26u, 0x26u, 0x70u,\r
- 0x05u, 0x26u, 0x26u, 0x70u, 0x2Du, 0x78u, 0x05u, 0xF0u,\r
- 0x02u, 0x05u, 0xEDu, 0xB2u, 0x55u, 0xB9u, 0x20u, 0x70u,\r
+ 0x70u, 0xB5u, 0x0Du, 0x4Du, 0x2Cu, 0x78u, 0xA6u, 0x07u,\r
+ 0x12u, 0xD5u, 0x0Cu, 0x4Cu, 0xB6u, 0x26u, 0x26u, 0x70u,\r
+ 0xD8u, 0x26u, 0x26u, 0x70u, 0x05u, 0x26u, 0x26u, 0x70u,\r
+ 0x2Du, 0x78u, 0xADu, 0x07u, 0x0Au, 0xD4u, 0x20u, 0x70u,\r
0x08u, 0x0Au, 0xC9u, 0xB2u, 0x20u, 0x70u, 0x21u, 0x70u,\r
- 0x07u, 0x20u, 0x22u, 0x70u, 0x23u, 0x70u, 0x70u, 0xBDu,\r
+ 0x22u, 0x70u, 0x23u, 0x70u, 0x07u, 0x20u, 0x70u, 0xBDu,\r
0x04u, 0x20u, 0x70u, 0xBDu, 0x09u, 0x20u, 0x70u, 0xBDu,\r
0x22u, 0x47u, 0x00u, 0x40u, 0x20u, 0x47u, 0x00u, 0x40u,\r
- 0x0Cu, 0x4Au, 0x13u, 0x78u, 0x03u, 0xF0u, 0x02u, 0x01u,\r
- 0xCBu, 0xB2u, 0x73u, 0xB1u, 0x0Au, 0x4Bu, 0xB6u, 0x21u,\r
- 0x19u, 0x70u, 0xE1u, 0x21u, 0x19u, 0x70u, 0x0Eu, 0x21u,\r
- 0x19u, 0x70u, 0x12u, 0x78u, 0x02u, 0xF0u, 0x02u, 0x01u,\r
- 0xCAu, 0xB2u, 0x22u, 0xB9u, 0x18u, 0x70u, 0x07u, 0x20u,\r
+ 0x0Au, 0x4Au, 0x13u, 0x78u, 0x99u, 0x07u, 0x0Cu, 0xD5u,\r
+ 0x09u, 0x4Bu, 0xB6u, 0x21u, 0x19u, 0x70u, 0xE1u, 0x21u,\r
+ 0x19u, 0x70u, 0x0Eu, 0x21u, 0x19u, 0x70u, 0x12u, 0x78u,\r
+ 0x92u, 0x07u, 0x04u, 0xD4u, 0x18u, 0x70u, 0x07u, 0x20u,\r
0x70u, 0x47u, 0x04u, 0x20u, 0x70u, 0x47u, 0x09u, 0x20u,\r
0x70u, 0x47u, 0x00u, 0xBFu, 0x22u, 0x47u, 0x00u, 0x40u,\r
0x20u, 0x47u, 0x00u, 0x40u, 0x38u, 0xB5u, 0xFFu, 0xF7u,\r
- 0x71u, 0xFEu, 0x0Cu, 0x4Bu, 0x19u, 0x78u, 0x79u, 0xB9u,\r
+ 0x15u, 0xFEu, 0x0Cu, 0x4Bu, 0x19u, 0x78u, 0x79u, 0xB9u,\r
0x01u, 0x25u, 0x0Bu, 0x4Au, 0x1Du, 0x70u, 0x14u, 0x68u,\r
0x2Cu, 0x40u, 0x0Au, 0xD0u, 0x14u, 0x68u, 0x24u, 0xF0u,\r
0x01u, 0x04u, 0x14u, 0x60u, 0x00u, 0xBFu, 0x00u, 0xBFu,\r
0x00u, 0xBFu, 0x5Du, 0x60u, 0x0Cu, 0x46u, 0x00u, 0xE0u,\r
- 0x04u, 0x24u, 0xFFu, 0xF7u, 0x5Fu, 0xFEu, 0x20u, 0x46u,\r
- 0x38u, 0xBDu, 0x00u, 0xBFu, 0x48u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x04u, 0x24u, 0xFFu, 0xF7u, 0x03u, 0xFEu, 0x20u, 0x46u,\r
+ 0x38u, 0xBDu, 0x00u, 0xBFu, 0x44u, 0xC1u, 0xFFu, 0x1Fu,\r
0x04u, 0x00u, 0x08u, 0x40u, 0x10u, 0xB5u, 0xFFu, 0xF7u,\r
- 0x51u, 0xFEu, 0x09u, 0x4Bu, 0x00u, 0x22u, 0x59u, 0x68u,\r
+ 0xF5u, 0xFDu, 0x09u, 0x4Bu, 0x00u, 0x22u, 0x59u, 0x68u,\r
0x1Au, 0x70u, 0x01u, 0x29u, 0x08u, 0xD1u, 0x07u, 0x49u,\r
0x0Cu, 0x68u, 0x44u, 0xF0u, 0x01u, 0x04u, 0x0Cu, 0x60u,\r
0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x5Au, 0x60u,\r
- 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x42u, 0xBEu,\r
- 0x48u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x00u, 0x08u, 0x40u,\r
+ 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0xE6u, 0xBDu,\r
+ 0x44u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x00u, 0x08u, 0x40u,\r
+ 0x07u, 0x4Bu, 0x1Bu, 0x78u, 0x9Bu, 0x07u, 0x08u, 0xD5u,\r
+ 0x06u, 0x4Bu, 0xB6u, 0x22u, 0x1Au, 0x70u, 0xE0u, 0x22u,\r
+ 0x1Au, 0x70u, 0x0Du, 0x22u, 0x1Au, 0x70u, 0x07u, 0x20u,\r
+ 0x70u, 0x47u, 0x04u, 0x20u, 0x70u, 0x47u, 0x00u, 0xBFu,\r
+ 0x22u, 0x47u, 0x00u, 0x40u, 0x20u, 0x47u, 0x00u, 0x40u,\r
0x08u, 0xB5u, 0x62u, 0xB6u, 0x00u, 0x20u, 0x02u, 0x21u,\r
- 0x00u, 0xF0u, 0x62u, 0xF9u, 0x01u, 0x4Bu, 0x01u, 0x22u,\r
- 0x1Au, 0x70u, 0x08u, 0xBDu, 0x50u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x01u, 0x20u, 0x00u, 0xF0u, 0x03u, 0xBAu, 0x00u, 0x00u,\r
- 0xF8u, 0xB5u, 0x07u, 0x46u, 0x0Eu, 0x46u, 0x02u, 0x20u,\r
- 0x15u, 0x46u, 0x39u, 0x46u, 0x40u, 0x22u, 0x1Cu, 0x46u,\r
- 0x00u, 0xF0u, 0xBAu, 0xF9u, 0x0Au, 0x23u, 0x5Cu, 0x43u,\r
- 0x0Du, 0x48u, 0x44u, 0x80u, 0x00u, 0x24u, 0x02u, 0x20u,\r
- 0x00u, 0xF0u, 0x94u, 0xF9u, 0x50u, 0xB9u, 0x0Au, 0x49u,\r
- 0x67u, 0x1Cu, 0x4Au, 0x88u, 0xBFu, 0xB2u, 0xA2u, 0x42u,\r
- 0x04u, 0xD9u, 0x01u, 0x20u, 0xFFu, 0xF7u, 0xD2u, 0xFEu,\r
- 0x3Cu, 0x46u, 0xF0u, 0xE7u, 0x02u, 0x20u, 0x00u, 0xF0u,\r
- 0x85u, 0xF9u, 0x10u, 0xB1u, 0x2Eu, 0x80u, 0x00u, 0x20u,\r
- 0xF8u, 0xBDu, 0x10u, 0x20u, 0xF8u, 0xBDu, 0x00u, 0xBFu,\r
- 0x50u, 0xC1u, 0xFFu, 0x1Fu, 0x2Du, 0xE9u, 0xF0u, 0x41u,\r
- 0x15u, 0x46u, 0x0Au, 0x22u, 0x53u, 0x43u, 0x28u, 0x4Cu,\r
- 0x80u, 0x46u, 0x63u, 0x80u, 0x24u, 0x78u, 0x0Fu, 0x46u,\r
- 0xD4u, 0xB1u, 0x00u, 0x24u, 0x00u, 0xF0u, 0x5Eu, 0xF9u,\r
- 0x58u, 0xB9u, 0x23u, 0x4Bu, 0x66u, 0x1Cu, 0x58u, 0x88u,\r
- 0xB6u, 0xB2u, 0xA0u, 0x42u, 0x04u, 0xD9u, 0x01u, 0x20u,\r
- 0xFFu, 0xF7u, 0xACu, 0xFEu, 0x34u, 0x46u, 0xF1u, 0xE7u,\r
- 0x34u, 0x46u, 0x00u, 0xF0u, 0x4Fu, 0xF9u, 0xE0u, 0xB1u,\r
- 0x00u, 0xF0u, 0x52u, 0xF9u, 0xFFu, 0xF7u, 0xB0u, 0xFFu,\r
- 0x19u, 0x4Au, 0x00u, 0x21u, 0x11u, 0x70u, 0x14u, 0xE0u,\r
- 0x00u, 0xF0u, 0x4Au, 0xF9u, 0x08u, 0xB9u, 0x00u, 0x24u,\r
- 0x0Fu, 0xE0u, 0x00u, 0xF0u, 0x3Fu, 0xF9u, 0x00u, 0x28u,\r
- 0xF9u, 0xD0u, 0xFFu, 0xF7u, 0xA1u, 0xFFu, 0x08u, 0xE0u,\r
- 0x11u, 0x4Bu, 0x66u, 0x1Cu, 0x59u, 0x88u, 0xB6u, 0xB2u,\r
- 0xA1u, 0x42u, 0x09u, 0xD9u, 0xFFu, 0xF7u, 0x8Au, 0xFEu,\r
- 0x34u, 0x46u, 0x01u, 0x20u, 0x00u, 0xF0u, 0x3Eu, 0xF9u,\r
- 0x01u, 0x28u, 0x4Fu, 0xF0u, 0x01u, 0x00u, 0xEFu, 0xD1u,\r
- 0x00u, 0xF0u, 0x38u, 0xF9u, 0x01u, 0x28u, 0x0Au, 0xD1u,\r
- 0x41u, 0x46u, 0x40u, 0x2Fu, 0x34u, 0xBFu, 0x3Au, 0x46u,\r
- 0x40u, 0x22u, 0x00u, 0xF0u, 0x9Fu, 0xF9u, 0x28u, 0x80u,\r
- 0x00u, 0x20u, 0xBDu, 0xE8u, 0xF0u, 0x81u, 0x00u, 0x20u,\r
- 0x28u, 0x80u, 0x10u, 0x20u, 0xBDu, 0xE8u, 0xF0u, 0x81u,\r
- 0x50u, 0xC1u, 0xFFu, 0x1Fu, 0xF8u, 0xB5u, 0xFFu, 0xF7u,\r
- 0xA5u, 0xFDu, 0x38u, 0x4Bu, 0x07u, 0x46u, 0x1Au, 0x78u,\r
- 0x01u, 0x25u, 0x42u, 0xF0u, 0x01u, 0x00u, 0x18u, 0x70u,\r
- 0x19u, 0x7Cu, 0x02u, 0x26u, 0x41u, 0xF0u, 0x01u, 0x04u,\r
- 0x1Cu, 0x74u, 0x33u, 0x4Bu, 0x33u, 0x4Cu, 0x1Du, 0x70u,\r
- 0x03u, 0xF8u, 0x94u, 0x6Cu, 0x13u, 0xF8u, 0x8Du, 0x2Cu,\r
- 0x02u, 0xF0u, 0x7Fu, 0x00u, 0x03u, 0xF8u, 0x8Du, 0x0Cu,\r
- 0x00u, 0x20u, 0xFFu, 0xF7u, 0x63u, 0xFEu, 0x21u, 0x78u,\r
- 0x2Du, 0x48u, 0x01u, 0xF0u, 0xF9u, 0x03u, 0x23u, 0x70u,\r
- 0x02u, 0x78u, 0x02u, 0xF0u, 0xDFu, 0x01u, 0x01u, 0x70u,\r
- 0x23u, 0x78u, 0x28u, 0x46u, 0x2Bu, 0x43u, 0x23u, 0x70u,\r
- 0xFFu, 0xF7u, 0x54u, 0xFEu, 0x28u, 0x20u, 0xFFu, 0xF7u,\r
- 0x51u, 0xFEu, 0x26u, 0x48u, 0x02u, 0x78u, 0x02u, 0xF0u,\r
- 0x7Fu, 0x01u, 0x01u, 0x70u, 0x03u, 0x78u, 0x03u, 0xF0u,\r
- 0xBFu, 0x02u, 0x02u, 0x70u, 0x20u, 0x78u, 0x30u, 0x43u,\r
- 0x20u, 0x70u, 0x30u, 0x46u, 0xFFu, 0xF7u, 0x42u, 0xFEu,\r
- 0x21u, 0x78u, 0x1Fu, 0x4Au, 0x41u, 0xF0u, 0x04u, 0x03u,\r
- 0x23u, 0x70u, 0x00u, 0x24u, 0x14u, 0x70u, 0x38u, 0x46u,\r
- 0x54u, 0x70u, 0xFFu, 0xF7u, 0x63u, 0xFDu, 0x17u, 0x20u,\r
- 0x1Au, 0x49u, 0xFFu, 0xF7u, 0x3Bu, 0xFEu, 0x17u, 0x20u,\r
- 0x07u, 0x21u, 0xFFu, 0xF7u, 0x45u, 0xFEu, 0x15u, 0x20u,\r
- 0x17u, 0x49u, 0xFFu, 0xF7u, 0x33u, 0xFEu, 0x15u, 0x20u,\r
- 0x07u, 0x21u, 0xFFu, 0xF7u, 0x3Du, 0xFEu, 0x18u, 0x20u,\r
- 0x14u, 0x49u, 0xFFu, 0xF7u, 0x2Bu, 0xFEu, 0x18u, 0x20u,\r
- 0x07u, 0x21u, 0xFFu, 0xF7u, 0x35u, 0xFEu, 0x20u, 0x46u,\r
- 0x11u, 0x49u, 0xFFu, 0xF7u, 0x23u, 0xFEu, 0x20u, 0x46u,\r
- 0x07u, 0x21u, 0xFFu, 0xF7u, 0x2Du, 0xFEu, 0x28u, 0x46u,\r
- 0x0Eu, 0x49u, 0xFFu, 0xF7u, 0x1Bu, 0xFEu, 0x28u, 0x46u,\r
- 0x07u, 0x21u, 0xBDu, 0xE8u, 0xF8u, 0x40u, 0xFFu, 0xF7u,\r
- 0x23u, 0xBEu, 0x00u, 0xBFu, 0xA5u, 0x43u, 0x00u, 0x40u,\r
- 0x9Du, 0x60u, 0x00u, 0x40u, 0x94u, 0x43u, 0x00u, 0x40u,\r
+ 0x00u, 0xF0u, 0x4Eu, 0xF9u, 0x01u, 0x4Bu, 0x01u, 0x22u,\r
+ 0x1Au, 0x70u, 0x08u, 0xBDu, 0x4Cu, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x01u, 0x20u, 0x00u, 0xF0u, 0xF1u, 0xB9u, 0xF8u, 0xB5u,\r
+ 0x07u, 0x46u, 0x0Eu, 0x46u, 0x15u, 0x46u, 0x03u, 0xEBu,\r
+ 0x83u, 0x03u, 0x02u, 0x20u, 0x39u, 0x46u, 0x40u, 0x22u,\r
+ 0x5Cu, 0x00u, 0x00u, 0xF0u, 0xA7u, 0xF9u, 0x02u, 0x20u,\r
+ 0x00u, 0xF0u, 0x86u, 0xF9u, 0x30u, 0xB9u, 0x2Cu, 0xB1u,\r
+ 0x01u, 0x20u, 0x01u, 0x3Cu, 0xFFu, 0xF7u, 0x8Au, 0xFEu,\r
+ 0xA4u, 0xB2u, 0xF4u, 0xE7u, 0x02u, 0x20u, 0x00u, 0xF0u,\r
+ 0x7Bu, 0xF9u, 0x10u, 0xB1u, 0x2Eu, 0x80u, 0x00u, 0x20u,\r
+ 0xF8u, 0xBDu, 0x10u, 0x20u, 0xF8u, 0xBDu, 0x00u, 0x00u,\r
+ 0x2Du, 0xE9u, 0xF8u, 0x43u, 0x03u, 0xEBu, 0x83u, 0x03u,\r
+ 0x5Cu, 0x00u, 0x23u, 0x4Bu, 0x16u, 0x46u, 0x1Au, 0x78u,\r
+ 0x80u, 0x46u, 0x0Fu, 0x46u, 0x99u, 0x46u, 0xAAu, 0xB1u,\r
+ 0x25u, 0x46u, 0x00u, 0xF0u, 0x53u, 0xF9u, 0x30u, 0xB9u,\r
+ 0x2Du, 0xB1u, 0x01u, 0x20u, 0x01u, 0x3Du, 0xFFu, 0xF7u,\r
+ 0x69u, 0xFEu, 0xADu, 0xB2u, 0xF5u, 0xE7u, 0x00u, 0xF0u,\r
+ 0x49u, 0xF9u, 0xA8u, 0xB1u, 0x00u, 0xF0u, 0x4Cu, 0xF9u,\r
+ 0xFFu, 0xF7u, 0xBEu, 0xFFu, 0x00u, 0x23u, 0x89u, 0xF8u,\r
+ 0x00u, 0x30u, 0x0Du, 0xE0u, 0x00u, 0xF0u, 0x44u, 0xF9u,\r
+ 0x50u, 0xB1u, 0x00u, 0xF0u, 0x3Bu, 0xF9u, 0x38u, 0xB1u,\r
+ 0xFFu, 0xF7u, 0xB2u, 0xFFu, 0x04u, 0xE0u, 0x54u, 0xB1u,\r
+ 0xFFu, 0xF7u, 0x50u, 0xFEu, 0x01u, 0x3Cu, 0xA4u, 0xB2u,\r
+ 0x01u, 0x20u, 0x00u, 0xF0u, 0x41u, 0xF9u, 0x01u, 0x28u,\r
+ 0x4Fu, 0xF0u, 0x01u, 0x00u, 0xF3u, 0xD1u, 0x00u, 0xF0u,\r
+ 0x3Bu, 0xF9u, 0x01u, 0x28u, 0x0Au, 0xD1u, 0x41u, 0x46u,\r
+ 0x40u, 0x2Fu, 0x34u, 0xBFu, 0x3Au, 0x46u, 0x40u, 0x22u,\r
+ 0x00u, 0xF0u, 0xA4u, 0xF9u, 0x30u, 0x80u, 0x00u, 0x20u,\r
+ 0xBDu, 0xE8u, 0xF8u, 0x83u, 0x00u, 0x23u, 0x33u, 0x80u,\r
+ 0x10u, 0x20u, 0xBDu, 0xE8u, 0xF8u, 0x83u, 0x00u, 0xBFu,\r
+ 0x4Cu, 0xC1u, 0xFFu, 0x1Fu, 0xF8u, 0xB5u, 0xFFu, 0xF7u,\r
+ 0x49u, 0xFDu, 0x39u, 0x4Bu, 0x01u, 0x25u, 0x1Au, 0x78u,\r
+ 0x02u, 0x26u, 0x42u, 0xF0u, 0x01u, 0x02u, 0x1Au, 0x70u,\r
+ 0x1Au, 0x7Cu, 0x36u, 0x4Cu, 0x42u, 0xF0u, 0x01u, 0x02u,\r
+ 0x1Au, 0x74u, 0x03u, 0xF5u, 0xE7u, 0x53u, 0x18u, 0x33u,\r
+ 0x1Du, 0x70u, 0x03u, 0xF8u, 0x94u, 0x6Cu, 0x13u, 0xF8u,\r
+ 0x8Du, 0x2Cu, 0x07u, 0x46u, 0x02u, 0xF0u, 0x7Fu, 0x02u,\r
+ 0x03u, 0xF8u, 0x8Du, 0x2Cu, 0x00u, 0x20u, 0xFFu, 0xF7u,\r
+ 0x25u, 0xFEu, 0x23u, 0x78u, 0x28u, 0x46u, 0x03u, 0xF0u,\r
+ 0xF9u, 0x03u, 0x23u, 0x70u, 0x2Au, 0x4Bu, 0x1Au, 0x78u,\r
+ 0x02u, 0xF0u, 0xDFu, 0x02u, 0x1Au, 0x70u, 0x23u, 0x78u,\r
+ 0x2Bu, 0x43u, 0x23u, 0x70u, 0xFFu, 0xF7u, 0x16u, 0xFEu,\r
+ 0x28u, 0x20u, 0xFFu, 0xF7u, 0x13u, 0xFEu, 0x25u, 0x4Bu,\r
+ 0x30u, 0x46u, 0x1Au, 0x78u, 0x02u, 0xF0u, 0x7Fu, 0x02u,\r
+ 0x1Au, 0x70u, 0x1Au, 0x78u, 0x02u, 0xF0u, 0xBFu, 0x02u,\r
+ 0x1Au, 0x70u, 0x23u, 0x78u, 0x33u, 0x43u, 0x23u, 0x70u,\r
+ 0xFFu, 0xF7u, 0x04u, 0xFEu, 0x23u, 0x78u, 0x38u, 0x46u,\r
+ 0x43u, 0xF0u, 0x04u, 0x03u, 0x23u, 0x70u, 0x1Cu, 0x4Bu,\r
+ 0x00u, 0x24u, 0x1Cu, 0x70u, 0x5Cu, 0x70u, 0xFFu, 0xF7u,\r
+ 0x05u, 0xFDu, 0x1Au, 0x49u, 0x17u, 0x20u, 0xFFu, 0xF7u,\r
+ 0x1Fu, 0xFEu, 0x17u, 0x20u, 0x07u, 0x21u, 0xFFu, 0xF7u,\r
+ 0x29u, 0xFEu, 0x17u, 0x49u, 0x15u, 0x20u, 0xFFu, 0xF7u,\r
+ 0x17u, 0xFEu, 0x15u, 0x20u, 0x07u, 0x21u, 0xFFu, 0xF7u,\r
+ 0x21u, 0xFEu, 0x14u, 0x49u, 0x18u, 0x20u, 0xFFu, 0xF7u,\r
+ 0x0Fu, 0xFEu, 0x18u, 0x20u, 0x07u, 0x21u, 0xFFu, 0xF7u,\r
+ 0x19u, 0xFEu, 0x20u, 0x46u, 0x10u, 0x49u, 0xFFu, 0xF7u,\r
+ 0x07u, 0xFEu, 0x20u, 0x46u, 0x07u, 0x21u, 0xFFu, 0xF7u,\r
+ 0x11u, 0xFEu, 0x28u, 0x46u, 0x0Du, 0x49u, 0xFFu, 0xF7u,\r
+ 0xFFu, 0xFDu, 0x28u, 0x46u, 0x07u, 0x21u, 0xBDu, 0xE8u,\r
+ 0xF8u, 0x40u, 0xFFu, 0xF7u, 0x07u, 0xBEu, 0x00u, 0xBFu,\r
+ 0xA5u, 0x43u, 0x00u, 0x40u, 0x94u, 0x43u, 0x00u, 0x40u,\r
0x12u, 0x60u, 0x00u, 0x40u, 0xF8u, 0x51u, 0x00u, 0x40u,\r
- 0x84u, 0x60u, 0x00u, 0x40u, 0x0Bu, 0x16u, 0x00u, 0x00u,\r
- 0x09u, 0x16u, 0x00u, 0x00u, 0x49u, 0x14u, 0x00u, 0x00u,\r
- 0xA1u, 0x15u, 0x00u, 0x00u, 0xD5u, 0x15u, 0x00u, 0x00u,\r
+ 0x84u, 0x60u, 0x00u, 0x40u, 0xF3u, 0x16u, 0x00u, 0x00u,\r
+ 0xF1u, 0x16u, 0x00u, 0x00u, 0x45u, 0x15u, 0x00u, 0x00u,\r
+ 0x89u, 0x16u, 0x00u, 0x00u, 0xBDu, 0x16u, 0x00u, 0x00u,\r
0x18u, 0x4Bu, 0x01u, 0x22u, 0x10u, 0xB5u, 0x1Au, 0x70u,\r
0x17u, 0x4Bu, 0x4Fu, 0xF4u, 0x00u, 0x04u, 0x1Cu, 0x60u,\r
0x4Fu, 0xF0u, 0x80u, 0x74u, 0x1Cu, 0x60u, 0x1Au, 0x60u,\r
0x02u, 0x22u, 0x1Au, 0x60u, 0x13u, 0x4Bu, 0x00u, 0x24u,\r
0x1Cu, 0x70u, 0x13u, 0x4Bu, 0x01u, 0xB1u, 0x03u, 0x22u,\r
- 0x12u, 0x49u, 0x1Au, 0x70u, 0x12u, 0x4Bu, 0x08u, 0x70u,\r
- 0x12u, 0x4Au, 0x00u, 0x20u, 0x12u, 0x49u, 0x18u, 0x70u,\r
- 0x12u, 0x4Bu, 0x10u, 0x70u, 0x08u, 0x70u, 0x12u, 0x4Au,\r
- 0x12u, 0x49u, 0x18u, 0x70u, 0x12u, 0x4Bu, 0x10u, 0x70u,\r
- 0x08u, 0x70u, 0x80u, 0x22u, 0x03u, 0x20u, 0x18u, 0x70u,\r
- 0x01u, 0x20u, 0x03u, 0xF8u, 0x20u, 0x2Cu, 0xFFu, 0xF7u,\r
- 0xE7u, 0xFCu, 0x0Eu, 0x48u, 0x04u, 0x21u, 0x01u, 0x70u,\r
- 0x10u, 0xBDu, 0x00u, 0xBFu, 0xECu, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x00u, 0xE1u, 0x00u, 0xE0u, 0x72u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x09u, 0x60u, 0x00u, 0x40u, 0x6Cu, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x6Du, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x6Fu, 0xC1u, 0xFFu, 0x1Fu, 0xE5u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x1Au, 0x70u, 0x12u, 0x4Bu, 0x12u, 0x4Au, 0x18u, 0x70u,\r
+ 0x00u, 0x23u, 0x13u, 0x70u, 0x11u, 0x4Au, 0x01u, 0x20u,\r
+ 0x13u, 0x70u, 0x11u, 0x4Au, 0x13u, 0x70u, 0x11u, 0x4Au,\r
+ 0x13u, 0x70u, 0x11u, 0x4Au, 0x13u, 0x70u, 0x11u, 0x4Au,\r
+ 0x13u, 0x70u, 0x11u, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u,\r
+ 0x80u, 0x22u, 0x03u, 0xF8u, 0x20u, 0x2Cu, 0xFFu, 0xF7u,\r
+ 0x8Bu, 0xFCu, 0x0Eu, 0x4Bu, 0x04u, 0x22u, 0x1Au, 0x70u,\r
+ 0x10u, 0xBDu, 0x00u, 0xBFu, 0xE4u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x00u, 0xE1u, 0x00u, 0xE0u, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x09u, 0x60u, 0x00u, 0x40u, 0x64u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x65u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x68u, 0xC1u, 0xFFu, 0x1Fu, 0x54u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x67u, 0xC1u, 0xFFu, 0x1Fu, 0xDDu, 0xC1u, 0xFFu, 0x1Fu,\r
0x28u, 0x60u, 0x00u, 0x40u, 0x12u, 0x60u, 0x00u, 0x40u,\r
0x70u, 0xB5u, 0x07u, 0x4Cu, 0x06u, 0x46u, 0x23u, 0x78u,\r
0x0Du, 0x46u, 0x1Bu, 0xB9u, 0xFFu, 0xF7u, 0x22u, 0xFFu,\r
- 0x01u, 0x20u, 0x20u, 0x70u, 0x30u, 0x46u, 0x29u, 0x46u,\r
+ 0x01u, 0x23u, 0x23u, 0x70u, 0x30u, 0x46u, 0x29u, 0x46u,\r
0xBDu, 0xE8u, 0x70u, 0x40u, 0xFFu, 0xF7u, 0xA4u, 0xBFu,\r
- 0x54u, 0xC1u, 0xFFu, 0x1Fu, 0x0Cu, 0x4Bu, 0x01u, 0x22u,\r
- 0x0Cu, 0x49u, 0x1Au, 0x70u, 0x00u, 0x20u, 0x0Cu, 0x4Au,\r
- 0x0Cu, 0x4Bu, 0x08u, 0x70u, 0x0Cu, 0x49u, 0x10u, 0x70u,\r
- 0x18u, 0x70u, 0x0Cu, 0x4Au, 0x0Cu, 0x4Bu, 0x08u, 0x70u,\r
- 0x0Cu, 0x49u, 0x10u, 0x70u, 0x18u, 0x70u, 0x0Cu, 0x4Bu,\r
- 0x08u, 0x70u, 0x80u, 0x22u, 0x03u, 0x20u, 0x18u, 0x70u,\r
+ 0x4Du, 0xC1u, 0xFFu, 0x1Fu, 0x0Cu, 0x4Bu, 0x01u, 0x22u,\r
+ 0x1Au, 0x70u, 0x0Cu, 0x4Au, 0x00u, 0x23u, 0x13u, 0x70u,\r
+ 0x0Bu, 0x4Au, 0x13u, 0x70u, 0x0Bu, 0x4Au, 0x13u, 0x70u,\r
+ 0x0Bu, 0x4Au, 0x13u, 0x70u, 0x0Bu, 0x4Au, 0x13u, 0x70u,\r
+ 0x0Bu, 0x4Au, 0x13u, 0x70u, 0x0Bu, 0x4Au, 0x13u, 0x70u,\r
+ 0x0Bu, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u, 0x80u, 0x22u,\r
0x03u, 0xF8u, 0x20u, 0x2Cu, 0x70u, 0x47u, 0x00u, 0xBFu,\r
- 0xECu, 0xC1u, 0xFFu, 0x1Fu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x6Du, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x6Fu, 0xC1u, 0xFFu, 0x1Fu, 0xE5u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0xE4u, 0xC1u, 0xFFu, 0x1Fu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x65u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x68u, 0xC1u, 0xFFu, 0x1Fu, 0x54u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x67u, 0xC1u, 0xFFu, 0x1Fu, 0xDDu, 0xC1u, 0xFFu, 0x1Fu,\r
0x28u, 0x60u, 0x00u, 0x40u, 0x01u, 0x4Bu, 0x18u, 0x78u,\r
- 0x70u, 0x47u, 0x00u, 0xBFu, 0x71u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x03u, 0x4Bu, 0x18u, 0x78u, 0x10u, 0xB1u, 0x00u, 0x22u,\r
- 0x18u, 0x78u, 0x1Au, 0x70u, 0x70u, 0x47u, 0x00u, 0xBFu,\r
- 0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x4Bu, 0x0Cu, 0x22u,\r
- 0x02u, 0xFBu, 0x00u, 0x30u, 0x40u, 0x78u, 0x70u, 0x47u,\r
- 0x78u, 0xC1u, 0xFFu, 0x1Fu, 0x01u, 0x38u, 0xC3u, 0xB2u,\r
- 0x07u, 0x2Bu, 0x0Cu, 0xD8u, 0x19u, 0x01u, 0x07u, 0x4Au,\r
- 0xCBu, 0xB2u, 0x98u, 0x5Cu, 0x51u, 0x1Cu, 0x5Bu, 0x5Cu,\r
- 0x00u, 0xF0u, 0x0Fu, 0x02u, 0x43u, 0xEAu, 0x02u, 0x20u,\r
- 0x81u, 0x1Eu, 0x88u, 0xB2u, 0x70u, 0x47u, 0x00u, 0x20u,\r
- 0x70u, 0x47u, 0x00u, 0xBFu, 0x0Cu, 0x60u, 0x00u, 0x40u,\r
- 0x43u, 0x1Eu, 0xDBu, 0xB2u, 0x07u, 0x2Bu, 0xF0u, 0xB5u,\r
- 0x2Fu, 0xD8u, 0x18u, 0x4Eu, 0x1Cu, 0x01u, 0x0Cu, 0x27u,\r
- 0xE3u, 0xB2u, 0x07u, 0xFBu, 0x00u, 0x64u, 0xE7u, 0x88u,\r
- 0x15u, 0x4Du, 0xBFu, 0xB2u, 0xC7u, 0xF5u, 0x00u, 0x77u,\r
- 0xBAu, 0x42u, 0x1Du, 0x44u, 0x03u, 0xD9u, 0xE2u, 0x88u,\r
- 0xC2u, 0xF5u, 0x00u, 0x74u, 0xA2u, 0xB2u, 0x0Cu, 0x24u,\r
- 0x04u, 0xFBu, 0x00u, 0x66u, 0xF4u, 0x78u, 0x44u, 0xEAu,\r
- 0x12u, 0x26u, 0x0Eu, 0x4Cu, 0x1Eu, 0x55u, 0xD6u, 0xB2u,\r
- 0x01u, 0x34u, 0x1Eu, 0x55u, 0x49u, 0xB9u, 0x09u, 0x4Au,\r
- 0x0Cu, 0x21u, 0x01u, 0xFBu, 0x00u, 0x20u, 0x00u, 0x21u,\r
- 0x41u, 0x70u, 0x40u, 0x79u, 0x08u, 0x4Au, 0x98u, 0x54u,\r
- 0xF0u, 0xBDu, 0x00u, 0x24u, 0xA6u, 0xB2u, 0x96u, 0x42u,\r
- 0xF1u, 0xD2u, 0x0Eu, 0x5Du, 0x01u, 0x34u, 0x2Eu, 0x70u,\r
- 0xF8u, 0xE7u, 0xF0u, 0xBDu, 0x78u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x88u, 0x60u, 0x00u, 0x40u, 0x0Cu, 0x60u, 0x00u, 0x40u,\r
- 0x0Eu, 0x60u, 0x00u, 0x40u, 0x43u, 0x1Eu, 0xDBu, 0xB2u,\r
- 0x07u, 0x2Bu, 0x0Au, 0xD8u, 0x05u, 0x4Au, 0x0Cu, 0x21u,\r
- 0x01u, 0xFBu, 0x00u, 0x20u, 0x00u, 0x21u, 0x41u, 0x70u,\r
- 0x1Bu, 0x01u, 0x40u, 0x79u, 0x02u, 0x4Au, 0xDBu, 0xB2u,\r
- 0x98u, 0x54u, 0x70u, 0x47u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x70u, 0x47u, 0x00u, 0xBFu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x04u, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u, 0xFFu, 0x00u,\r
+ 0x1Au, 0xB1u, 0x18u, 0x78u, 0x00u, 0x22u, 0xC0u, 0xB2u,\r
+ 0x1Au, 0x70u, 0x70u, 0x47u, 0x68u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x02u, 0x4Bu, 0x0Cu, 0x22u, 0x02u, 0xFBu, 0x00u, 0x30u,\r
+ 0x40u, 0x78u, 0x70u, 0x47u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x01u, 0x38u, 0xC3u, 0xB2u, 0x07u, 0x2Bu, 0x0Cu, 0xD8u,\r
+ 0x07u, 0x4Au, 0x1Bu, 0x01u, 0xDBu, 0xB2u, 0x98u, 0x5Cu,\r
+ 0x01u, 0x32u, 0x9Bu, 0x5Cu, 0x00u, 0xF0u, 0x0Fu, 0x00u,\r
+ 0x43u, 0xEAu, 0x00u, 0x20u, 0x02u, 0x38u, 0x80u, 0xB2u,\r
+ 0x70u, 0x47u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0xBFu,\r
+ 0x0Cu, 0x60u, 0x00u, 0x40u, 0x43u, 0x1Eu, 0xDBu, 0xB2u,\r
+ 0x07u, 0x2Bu, 0xF0u, 0xB5u, 0x2Fu, 0xD8u, 0x18u, 0x4Eu,\r
+ 0x0Cu, 0x24u, 0x04u, 0xFBu, 0x00u, 0x64u, 0xE7u, 0x88u,\r
+ 0x1Bu, 0x01u, 0xBFu, 0xB2u, 0x15u, 0x4Du, 0xC7u, 0xF5u,\r
+ 0x00u, 0x77u, 0xDBu, 0xB2u, 0xBAu, 0x42u, 0x1Du, 0x44u,\r
+ 0x03u, 0xD9u, 0xE2u, 0x88u, 0xC2u, 0xF5u, 0x00u, 0x72u,\r
+ 0x92u, 0xB2u, 0x0Cu, 0x24u, 0x04u, 0xFBu, 0x00u, 0x64u,\r
+ 0xE7u, 0x78u, 0x0Fu, 0x4Cu, 0x47u, 0xEAu, 0x12u, 0x27u,\r
+ 0x1Fu, 0x55u, 0xD7u, 0xB2u, 0x01u, 0x34u, 0x1Fu, 0x55u,\r
+ 0x49u, 0xB9u, 0x0Cu, 0x22u, 0x02u, 0xFBu, 0x00u, 0x60u,\r
+ 0x00u, 0x22u, 0x42u, 0x70u, 0x41u, 0x79u, 0x09u, 0x4Au,\r
+ 0xC9u, 0xB2u, 0x99u, 0x54u, 0xF0u, 0xBDu, 0x00u, 0x24u,\r
+ 0xA7u, 0xB2u, 0x97u, 0x42u, 0xF1u, 0xD2u, 0x0Fu, 0x5Du,\r
+ 0x01u, 0x34u, 0x2Fu, 0x70u, 0xF8u, 0xE7u, 0xF0u, 0xBDu,\r
+ 0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x88u, 0x60u, 0x00u, 0x40u,\r
+ 0x0Cu, 0x60u, 0x00u, 0x40u, 0x0Eu, 0x60u, 0x00u, 0x40u,\r
+ 0x43u, 0x1Eu, 0xDBu, 0xB2u, 0x07u, 0x2Bu, 0x0Bu, 0xD8u,\r
+ 0x06u, 0x4Au, 0x0Cu, 0x21u, 0x01u, 0xFBu, 0x00u, 0x20u,\r
+ 0x00u, 0x22u, 0x42u, 0x70u, 0x41u, 0x79u, 0x1Bu, 0x01u,\r
+ 0x03u, 0x4Au, 0xDBu, 0xB2u, 0xC9u, 0xB2u, 0x99u, 0x54u,\r
+ 0x70u, 0x47u, 0x00u, 0xBFu, 0x70u, 0xC1u, 0xFFu, 0x1Fu,\r
0x0Eu, 0x60u, 0x00u, 0x40u, 0xF8u, 0xB5u, 0x43u, 0x1Eu,\r
- 0x0Du, 0x46u, 0xD9u, 0xB2u, 0x07u, 0x29u, 0x07u, 0x46u,\r
- 0x14u, 0x46u, 0x16u, 0xD8u, 0xBDu, 0xB1u, 0x0Au, 0x01u,\r
- 0x0Cu, 0x4Eu, 0xD3u, 0xB2u, 0x9Eu, 0x19u, 0xFFu, 0xF7u,\r
- 0x89u, 0xFFu, 0xA0u, 0x42u, 0x28u, 0xBFu, 0x20u, 0x46u,\r
- 0x84u, 0xB2u, 0x00u, 0x22u, 0x90u, 0xB2u, 0xA0u, 0x42u,\r
- 0x03u, 0xD2u, 0x31u, 0x78u, 0xA9u, 0x54u, 0x01u, 0x32u,\r
- 0xF8u, 0xE7u, 0x38u, 0x46u, 0xFFu, 0xF7u, 0xCEu, 0xFFu,\r
- 0x02u, 0xE0u, 0x00u, 0x24u, 0x00u, 0xE0u, 0x2Cu, 0x46u,\r
+ 0xDBu, 0xB2u, 0x07u, 0x2Bu, 0x07u, 0x46u, 0x0Du, 0x46u,\r
+ 0x14u, 0x46u, 0x16u, 0xD8u, 0xB9u, 0xB1u, 0x1Bu, 0x01u,\r
+ 0x0Cu, 0x4Eu, 0xDBu, 0xB2u, 0x1Eu, 0x44u, 0xFFu, 0xF7u,\r
+ 0x87u, 0xFFu, 0xA0u, 0x42u, 0x28u, 0xBFu, 0x20u, 0x46u,\r
+ 0x84u, 0xB2u, 0x00u, 0x23u, 0x9Au, 0xB2u, 0xA2u, 0x42u,\r
+ 0x03u, 0xD2u, 0x32u, 0x78u, 0xEAu, 0x54u, 0x01u, 0x33u,\r
+ 0xF8u, 0xE7u, 0x38u, 0x46u, 0xFFu, 0xF7u, 0xCCu, 0xFFu,\r
+ 0x02u, 0xE0u, 0x00u, 0x24u, 0x00u, 0xE0u, 0x0Cu, 0x46u,\r
0x20u, 0x46u, 0xF8u, 0xBDu, 0x88u, 0x60u, 0x00u, 0x40u,\r
- 0x1Bu, 0x4Bu, 0x1Cu, 0x49u, 0x1Au, 0x88u, 0x08u, 0x78u,\r
- 0x82u, 0x18u, 0x91u, 0xB2u, 0x19u, 0x80u, 0x1Au, 0x49u,\r
- 0x1Au, 0x4Bu, 0xCAu, 0xB2u, 0x18u, 0x88u, 0x80u, 0xB2u,\r
- 0x78u, 0xB1u, 0x19u, 0x4Au, 0x91u, 0x42u, 0x0Bu, 0xD0u,\r
- 0x5Au, 0x68u, 0x10u, 0x78u, 0x01u, 0xF8u, 0x01u, 0x0Bu,\r
- 0x5Au, 0x68u, 0x50u, 0x1Cu, 0x58u, 0x60u, 0x1Au, 0x88u,\r
- 0x50u, 0x1Eu, 0x82u, 0xB2u, 0x1Au, 0x80u, 0xEBu, 0xE7u,\r
- 0x08u, 0x22u, 0x0Eu, 0x49u, 0x0Bu, 0x78u, 0x08u, 0x2Bu,\r
- 0x00u, 0xD0u, 0x5Au, 0xB1u, 0x0Fu, 0x48u, 0x01u, 0x78u,\r
- 0x81u, 0xF0u, 0x80u, 0x03u, 0x0Eu, 0x49u, 0x03u, 0x70u,\r
- 0x0Fu, 0x20u, 0x0Eu, 0x4Bu, 0x08u, 0x70u, 0x02u, 0x20u,\r
- 0x18u, 0x70u, 0x04u, 0xE0u, 0x0Au, 0x49u, 0x0Bu, 0x4Bu,\r
- 0x02u, 0x20u, 0x08u, 0x70u, 0x18u, 0x70u, 0x03u, 0x49u,\r
- 0x09u, 0x48u, 0x0Au, 0x70u, 0x02u, 0x70u, 0x70u, 0x47u,\r
- 0xE8u, 0xC1u, 0xFFu, 0x1Fu, 0xE5u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x00u, 0x60u, 0x00u, 0x40u, 0x60u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x08u, 0x60u, 0x00u, 0x40u, 0x6Eu, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0xE6u, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x4Bu, 0x02u, 0x22u,\r
- 0x1Au, 0x70u, 0x07u, 0x49u, 0x07u, 0x4Bu, 0x80u, 0x20u,\r
- 0x0Fu, 0x22u, 0x08u, 0x70u, 0x1Au, 0x70u, 0x06u, 0x49u,\r
- 0x06u, 0x4Au, 0x00u, 0x20u, 0x08u, 0x70u, 0x10u, 0x70u,\r
- 0x01u, 0x20u, 0x70u, 0x47u, 0x72u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x6Eu, 0xC1u, 0xFFu, 0x1Fu, 0x5Du, 0xC1u, 0xFFu, 0x1Fu,\r
- 0xE5u, 0xC1u, 0xFFu, 0x1Fu, 0xE6u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x10u, 0xB5u, 0x15u, 0x4Bu, 0x1Au, 0x78u, 0x15u, 0x4Bu,\r
- 0x02u, 0xF0u, 0x0Fu, 0x00u, 0x81u, 0x1Eu, 0x18u, 0x88u,\r
- 0xCAu, 0xB2u, 0x11u, 0x18u, 0x88u, 0xB2u, 0x12u, 0x49u,\r
- 0x18u, 0x80u, 0x12u, 0x4Bu, 0x18u, 0x88u, 0x80u, 0xB2u,\r
- 0x70u, 0xB1u, 0x6Au, 0xB1u, 0x58u, 0x68u, 0x11u, 0xF8u,\r
- 0x01u, 0x4Bu, 0x01u, 0x3Au, 0x04u, 0x70u, 0x58u, 0x68u,\r
- 0xD2u, 0xB2u, 0x01u, 0x30u, 0x58u, 0x60u, 0x18u, 0x88u,\r
- 0x01u, 0x38u, 0x80u, 0xB2u, 0x18u, 0x80u, 0xECu, 0xE7u,\r
- 0x09u, 0x49u, 0x0Au, 0x4Bu, 0x0Au, 0x70u, 0x1Au, 0x78u,\r
- 0x0Bu, 0x21u, 0x82u, 0xF0u, 0x80u, 0x00u, 0x18u, 0x70u,\r
- 0x07u, 0x4Bu, 0x19u, 0x70u, 0x10u, 0xBDu, 0x00u, 0xBFu,\r
- 0x29u, 0x60u, 0x00u, 0x40u, 0xE8u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x00u, 0x60u, 0x00u, 0x40u, 0x60u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0xE6u, 0xC1u, 0xFFu, 0x1Fu, 0x6Eu, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x06u, 0x4Au, 0x07u, 0x48u,\r
- 0x06u, 0x23u, 0x13u, 0x70u, 0x03u, 0x70u, 0x06u, 0x4Bu,\r
- 0x06u, 0x48u, 0x80u, 0x21u, 0x00u, 0x22u, 0x19u, 0x70u,\r
- 0x02u, 0x70u, 0x01u, 0x20u, 0x70u, 0x47u, 0x00u, 0xBFu,\r
- 0x72u, 0xC1u, 0xFFu, 0x1Fu, 0x5Du, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x6Eu, 0xC1u, 0xFFu, 0x1Fu, 0xE6u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x05u, 0x4Bu, 0x9Au, 0x68u, 0x3Au, 0xB1u, 0x99u, 0x68u,\r
- 0x04u, 0x4Au, 0x08u, 0x70u, 0x98u, 0x68u, 0x11u, 0x88u,\r
- 0x41u, 0x80u, 0x00u, 0x20u, 0x98u, 0x60u, 0x70u, 0x47u,\r
- 0x60u, 0xC1u, 0xFFu, 0x1Fu, 0xE8u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x08u, 0xB5u, 0x0Au, 0x4Bu, 0x1Au, 0x78u, 0x32u, 0xB1u,\r
- 0x19u, 0x78u, 0x09u, 0x4Au, 0x41u, 0xF0u, 0x80u, 0x00u,\r
- 0x00u, 0x21u, 0x10u, 0x70u, 0x19u, 0x70u, 0x07u, 0x4Bu,\r
- 0x00u, 0x20u, 0x18u, 0x70u, 0x01u, 0x20u, 0xFFu, 0xF7u,\r
- 0xDFu, 0xFFu, 0x05u, 0x49u, 0x03u, 0x22u, 0x0Au, 0x70u,\r
- 0x08u, 0xBDu, 0x00u, 0xBFu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x08u, 0x60u, 0x00u, 0x40u, 0x72u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x05u, 0x4Bu,\r
+ 0x30u, 0xB5u, 0x1Au, 0x4Bu, 0x1Au, 0x48u, 0x1Au, 0x88u,\r
+ 0x01u, 0x78u, 0x0Au, 0x44u, 0x92u, 0xB2u, 0x19u, 0x49u,\r
+ 0x1Au, 0x80u, 0x19u, 0x4Bu, 0xCAu, 0xB2u, 0x1Cu, 0x88u,\r
+ 0xA4u, 0xB2u, 0x84u, 0xB1u, 0x17u, 0x4Au, 0x91u, 0x42u,\r
+ 0x0Cu, 0xD0u, 0x5Au, 0x68u, 0x12u, 0x78u, 0xD2u, 0xB2u,\r
+ 0x01u, 0xF8u, 0x01u, 0x2Bu, 0x5Au, 0x68u, 0x01u, 0x32u,\r
+ 0x5Au, 0x60u, 0x1Au, 0x88u, 0x01u, 0x3Au, 0x92u, 0xB2u,\r
+ 0x1Au, 0x80u, 0xEAu, 0xE7u, 0x08u, 0x22u, 0x03u, 0x78u,\r
+ 0x0Fu, 0x4Cu, 0x08u, 0x2Bu, 0x0Fu, 0x4Bu, 0x00u, 0xD0u,\r
+ 0x42u, 0xB1u, 0x0Fu, 0x49u, 0x0Du, 0x78u, 0x85u, 0xF0u,\r
+ 0x80u, 0x05u, 0x0Du, 0x70u, 0x0Fu, 0x21u, 0x21u, 0x70u,\r
+ 0x02u, 0x21u, 0x01u, 0xE0u, 0x02u, 0x21u, 0x21u, 0x70u,\r
+ 0x19u, 0x70u, 0x0Au, 0x4Bu, 0x02u, 0x70u, 0x1Au, 0x70u,\r
+ 0x30u, 0xBDu, 0x00u, 0xBFu, 0xE0u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0xDDu, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x60u, 0x00u, 0x40u,\r
+ 0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0x60u, 0x00u, 0x40u,\r
+ 0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x66u, 0xC1u, 0xFFu, 0x1Fu, 0xDEu, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x07u, 0x4Bu, 0x02u, 0x22u, 0x1Au, 0x70u, 0x07u, 0x4Bu,\r
+ 0x80u, 0x22u, 0x1Au, 0x70u, 0x06u, 0x4Bu, 0x0Fu, 0x22u,\r
+ 0x1Au, 0x70u, 0x06u, 0x4Au, 0x00u, 0x23u, 0x13u, 0x70u,\r
+ 0x05u, 0x4Au, 0x01u, 0x20u, 0x13u, 0x70u, 0x70u, 0x47u,\r
+ 0x6Au, 0xC1u, 0xFFu, 0x1Fu, 0x66u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x55u, 0xC1u, 0xFFu, 0x1Fu, 0xDDu, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0xDEu, 0xC1u, 0xFFu, 0x1Fu, 0x10u, 0xB5u, 0x15u, 0x4Bu,\r
+ 0x1Au, 0x78u, 0x15u, 0x4Bu, 0x02u, 0xF0u, 0x0Fu, 0x02u,\r
+ 0x19u, 0x88u, 0x02u, 0x3Au, 0xD2u, 0xB2u, 0x11u, 0x44u,\r
+ 0x89u, 0xB2u, 0x19u, 0x80u, 0x11u, 0x49u, 0x12u, 0x4Bu,\r
+ 0x18u, 0x88u, 0x80u, 0xB2u, 0x78u, 0xB1u, 0x72u, 0xB1u,\r
+ 0x58u, 0x68u, 0x11u, 0xF8u, 0x01u, 0x4Bu, 0x01u, 0x3Au,\r
+ 0xE4u, 0xB2u, 0x04u, 0x70u, 0x58u, 0x68u, 0xD2u, 0xB2u,\r
+ 0x01u, 0x30u, 0x58u, 0x60u, 0x18u, 0x88u, 0x01u, 0x38u,\r
+ 0x80u, 0xB2u, 0x18u, 0x80u, 0xEBu, 0xE7u, 0x09u, 0x4Bu,\r
+ 0x1Au, 0x70u, 0x09u, 0x4Bu, 0x1Au, 0x78u, 0x82u, 0xF0u,\r
+ 0x80u, 0x02u, 0x1Au, 0x70u, 0x07u, 0x4Bu, 0x0Bu, 0x22u,\r
+ 0x1Au, 0x70u, 0x10u, 0xBDu, 0x29u, 0x60u, 0x00u, 0x40u,\r
+ 0xE0u, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x60u, 0x00u, 0x40u,\r
+ 0x58u, 0xC1u, 0xFFu, 0x1Fu, 0xDEu, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x66u, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x06u, 0x4Au, 0x06u, 0x23u, 0x13u, 0x70u, 0x06u, 0x4Au,\r
+ 0x01u, 0x20u, 0x13u, 0x70u, 0x05u, 0x4Bu, 0x80u, 0x22u,\r
+ 0x1Au, 0x70u, 0x05u, 0x4Bu, 0x00u, 0x22u, 0x1Au, 0x70u,\r
+ 0x70u, 0x47u, 0x00u, 0xBFu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x66u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0xDEu, 0xC1u, 0xFFu, 0x1Fu, 0x05u, 0x4Bu, 0x9Au, 0x68u,\r
+ 0x3Au, 0xB1u, 0x9Au, 0x68u, 0x04u, 0x49u, 0x10u, 0x70u,\r
+ 0x9Au, 0x68u, 0x09u, 0x88u, 0x51u, 0x80u, 0x00u, 0x22u,\r
+ 0x9Au, 0x60u, 0x70u, 0x47u, 0x58u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0xE0u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x12u, 0x4Bu,\r
+ 0x1Au, 0x78u, 0xD2u, 0xB2u, 0x1Au, 0x70u, 0x1Bu, 0x78u,\r
+ 0xDBu, 0xB2u, 0x1Au, 0x06u, 0x02u, 0xD5u, 0x0Fu, 0x4Au,\r
+ 0x13u, 0x70u, 0x08u, 0xBDu, 0x02u, 0x20u, 0xFFu, 0xF7u,\r
+ 0xE1u, 0xFFu, 0x0Du, 0x4Bu, 0x1Bu, 0x78u, 0x03u, 0xF0u,\r
+ 0x60u, 0x03u, 0x20u, 0x2Bu, 0x05u, 0xD0u, 0x40u, 0x2Bu,\r
+ 0x06u, 0xD0u, 0x43u, 0xB9u, 0x00u, 0xF0u, 0x94u, 0xFCu,\r
+ 0x04u, 0xE0u, 0x00u, 0xF0u, 0xE1u, 0xFDu, 0x01u, 0xE0u,\r
+ 0x00u, 0xF0u, 0xD2u, 0xFDu, 0x10u, 0xB9u, 0x03u, 0x4Bu,\r
+ 0x03u, 0x22u, 0x1Au, 0x70u, 0x08u, 0xBDu, 0x00u, 0xBFu,\r
+ 0x28u, 0x60u, 0x00u, 0x40u, 0x55u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x00u, 0x60u, 0x00u, 0x40u, 0x08u, 0xB5u, 0x08u, 0x49u,\r
+ 0x08u, 0x4Bu, 0x01u, 0x20u, 0x1Au, 0x88u, 0x09u, 0x78u,\r
+ 0x0Au, 0x44u, 0x92u, 0xB2u, 0x1Au, 0x80u, 0x06u, 0x4Bu,\r
+ 0x00u, 0x22u, 0x1Au, 0x70u, 0xFFu, 0xF7u, 0xB6u, 0xFFu,\r
+ 0x04u, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u, 0x08u, 0xBDu,\r
+ 0xDDu, 0xC1u, 0xFFu, 0x1Fu, 0xE0u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x6Au, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x08u, 0xB5u, 0x0Cu, 0x4Bu, 0x1Bu, 0x78u, 0xDBu, 0xB2u,\r
+ 0x04u, 0x2Bu, 0x07u, 0xD0u, 0x06u, 0x2Bu, 0x09u, 0xD0u,\r
+ 0x02u, 0x2Bu, 0x0Du, 0xD1u, 0xBDu, 0xE8u, 0x08u, 0x40u,\r
+ 0xFFu, 0xF7u, 0xD8u, 0xBFu, 0xBDu, 0xE8u, 0x08u, 0x40u,\r
+ 0xFFu, 0xF7u, 0x48u, 0xBFu, 0x03u, 0x20u, 0xFFu, 0xF7u,\r
+ 0x95u, 0xFFu, 0x03u, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u,\r
+ 0x08u, 0xBDu, 0x00u, 0xBFu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x05u, 0x4Bu,\r
0x00u, 0x22u, 0x01u, 0x20u, 0x1Au, 0x70u, 0xFFu, 0xF7u,\r
- 0xCBu, 0xFFu, 0x03u, 0x49u, 0x03u, 0x20u, 0x08u, 0x70u,\r
- 0x08u, 0xBDu, 0x00u, 0xBFu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x4Bu, 0x18u, 0x78u,\r
- 0x04u, 0x28u, 0x05u, 0xD0u, 0x06u, 0x28u, 0x05u, 0xD0u,\r
- 0x02u, 0x28u, 0x05u, 0xD1u, 0xFFu, 0xF7u, 0x04u, 0xBFu,\r
- 0xFFu, 0xF7u, 0xE4u, 0xBFu, 0xFFu, 0xF7u, 0xC4u, 0xBFu,\r
- 0x70u, 0x47u, 0x00u, 0xBFu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x08u, 0xB5u, 0x08u, 0x49u, 0x08u, 0x4Bu, 0x1Au, 0x88u,\r
- 0x08u, 0x78u, 0x82u, 0x18u, 0x91u, 0xB2u, 0x19u, 0x80u,\r
- 0x06u, 0x4Bu, 0x00u, 0x20u, 0x18u, 0x70u, 0x01u, 0x20u,\r
- 0xFFu, 0xF7u, 0xA2u, 0xFFu, 0x04u, 0x49u, 0x03u, 0x22u,\r
- 0x0Au, 0x70u, 0x08u, 0xBDu, 0xE5u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0xE8u, 0xC1u, 0xFFu, 0x1Fu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x0Bu, 0x4Bu,\r
- 0x18u, 0x78u, 0x04u, 0x28u, 0x07u, 0xD0u, 0x06u, 0x28u,\r
- 0x09u, 0xD0u, 0x02u, 0x28u, 0x0Du, 0xD1u, 0xBDu, 0xE8u,\r
- 0x08u, 0x40u, 0xFFu, 0xF7u, 0xD9u, 0xBFu, 0xBDu, 0xE8u,\r
- 0x08u, 0x40u, 0xFFu, 0xF7u, 0x35u, 0xBFu, 0x03u, 0x20u,\r
- 0xFFu, 0xF7u, 0x82u, 0xFFu, 0x02u, 0x49u, 0x03u, 0x22u,\r
- 0x0Au, 0x70u, 0x08u, 0xBDu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x11u, 0x4Bu,\r
- 0x1Au, 0x78u, 0x1Au, 0x70u, 0x18u, 0x78u, 0x02u, 0x06u,\r
- 0x02u, 0xD5u, 0x0Fu, 0x4Bu, 0x18u, 0x70u, 0x08u, 0xBDu,\r
- 0x02u, 0x20u, 0xFFu, 0xF7u, 0x6Du, 0xFFu, 0x0Du, 0x49u,\r
- 0x0Bu, 0x78u, 0x03u, 0xF0u, 0x60u, 0x02u, 0x20u, 0x2Au,\r
- 0x05u, 0xD0u, 0x40u, 0x2Au, 0x06u, 0xD0u, 0x42u, 0xB9u,\r
- 0x00u, 0xF0u, 0x4Au, 0xFCu, 0x04u, 0xE0u, 0x00u, 0xF0u,\r
- 0x8Du, 0xFDu, 0x01u, 0xE0u, 0x00u, 0xF0u, 0x7Eu, 0xFDu,\r
- 0x10u, 0xB9u, 0x03u, 0x49u, 0x03u, 0x20u, 0x08u, 0x70u,\r
- 0x08u, 0xBDu, 0x00u, 0xBFu, 0x28u, 0x60u, 0x00u, 0x40u,\r
- 0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x60u, 0x00u, 0x40u,\r
- 0x08u, 0xB5u, 0x22u, 0x4Bu, 0x1Au, 0x78u, 0xD0u, 0xB2u,\r
- 0x00u, 0xF0u, 0x10u, 0x01u, 0xCBu, 0xB2u, 0x00u, 0x2Bu,\r
- 0x3Bu, 0xD0u, 0x52u, 0xB2u, 0x00u, 0x2Au, 0x0Au, 0xDAu,\r
- 0x00u, 0xF0u, 0x0Fu, 0x01u, 0x01u, 0x29u, 0x34u, 0xD1u,\r
- 0xFFu, 0xF7u, 0xC4u, 0xFFu, 0x1Au, 0x4Bu, 0x18u, 0x78u,\r
- 0x00u, 0x06u, 0x0Du, 0xD5u, 0x08u, 0xBDu, 0x00u, 0xF0u,\r
- 0x40u, 0x01u, 0xCBu, 0xB2u, 0x13u, 0xB1u, 0xFFu, 0xF7u,\r
- 0x71u, 0xFFu, 0x05u, 0xE0u, 0x00u, 0xF0u, 0x20u, 0x00u,\r
- 0xC2u, 0xB2u, 0x12u, 0xB3u, 0xFFu, 0xF7u, 0x96u, 0xFFu,\r
- 0x10u, 0x4Au, 0x11u, 0x78u, 0x09u, 0x06u, 0x1Cu, 0xD4u,\r
- 0x10u, 0x4Bu, 0x11u, 0x4Au, 0x18u, 0x78u, 0x11u, 0x78u,\r
- 0x41u, 0xEAu, 0x00u, 0x03u, 0x0Fu, 0x48u, 0x03u, 0x70u,\r
- 0x02u, 0x78u, 0x93u, 0x42u, 0x11u, 0xD1u, 0x0Au, 0x49u,\r
- 0x08u, 0x4Bu, 0x0Au, 0x78u, 0x18u, 0x78u, 0x00u, 0xF0u,\r
- 0x80u, 0x00u, 0xC0u, 0xB2u, 0x20u, 0xB9u, 0x0Au, 0x78u,\r
- 0x1Au, 0x70u, 0x19u, 0x78u, 0x01u, 0xF0u, 0x0Fu, 0x02u,\r
- 0x03u, 0x4Bu, 0x18u, 0x78u, 0x82u, 0x42u, 0xEEu, 0xD1u,\r
- 0x08u, 0xBDu, 0x08u, 0xBDu, 0x28u, 0x60u, 0x00u, 0x40u,\r
- 0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x6Eu, 0xC1u, 0xFFu, 0x1Fu,\r
- 0xE6u, 0xC1u, 0xFFu, 0x1Fu, 0x29u, 0x60u, 0x00u, 0x40u,\r
+ 0x85u, 0xFFu, 0x03u, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u,\r
+ 0x08u, 0xBDu, 0x00u, 0xBFu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x0Au, 0x4Bu,\r
+ 0x1Au, 0x78u, 0x32u, 0xB1u, 0x19u, 0x78u, 0x09u, 0x4Au,\r
+ 0x41u, 0xF0u, 0x80u, 0x01u, 0x11u, 0x70u, 0x00u, 0x22u,\r
+ 0x1Au, 0x70u, 0x07u, 0x4Bu, 0x00u, 0x22u, 0x01u, 0x20u,\r
+ 0x1Au, 0x70u, 0xFFu, 0xF7u, 0x6Bu, 0xFFu, 0x05u, 0x4Bu,\r
+ 0x03u, 0x22u, 0x1Au, 0x70u, 0x08u, 0xBDu, 0x00u, 0xBFu,\r
+ 0x54u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0x60u, 0x00u, 0x40u,\r
+ 0x6Au, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x07u, 0x4Bu, 0x1Bu, 0x78u, 0xDBu, 0xB2u, 0x04u, 0x2Bu,\r
+ 0x05u, 0xD0u, 0x06u, 0x2Bu, 0x05u, 0xD0u, 0x02u, 0x2Bu,\r
+ 0x05u, 0xD1u, 0xFFu, 0xF7u, 0xA1u, 0xBEu, 0xFFu, 0xF7u,\r
+ 0xC5u, 0xBFu, 0xFFu, 0xF7u, 0xD3u, 0xBFu, 0x70u, 0x47u,\r
+ 0x6Au, 0xC1u, 0xFFu, 0x1Fu, 0x10u, 0xB5u, 0x1Du, 0x4Cu,\r
+ 0x23u, 0x78u, 0xDBu, 0xB2u, 0xDAu, 0x06u, 0x33u, 0xD5u,\r
+ 0x18u, 0x06u, 0x0Au, 0xD5u, 0x03u, 0xF0u, 0x0Fu, 0x03u,\r
+ 0x01u, 0x2Bu, 0x2Du, 0xD1u, 0xFFu, 0xF7u, 0x4Eu, 0xFFu,\r
+ 0x17u, 0x4Bu, 0x1Bu, 0x78u, 0x19u, 0x06u, 0x09u, 0xD5u,\r
+ 0x10u, 0xBDu, 0x5Au, 0x06u, 0x02u, 0xD5u, 0xFFu, 0xF7u,\r
+ 0xD7u, 0xFFu, 0x03u, 0xE0u, 0x9Bu, 0x06u, 0x1Fu, 0xD5u,\r
+ 0xFFu, 0xF7u, 0x86u, 0xFFu, 0x23u, 0x78u, 0x1Bu, 0x06u,\r
+ 0x1Au, 0xD4u, 0x10u, 0x4Bu, 0x10u, 0x4Au, 0x1Bu, 0x78u,\r
+ 0x12u, 0x78u, 0x13u, 0x43u, 0x0Fu, 0x4Au, 0x13u, 0x70u,\r
+ 0x12u, 0x78u, 0x93u, 0x42u, 0x10u, 0xD1u, 0x0Au, 0x4Bu,\r
+ 0x08u, 0x49u, 0x1Au, 0x78u, 0x20u, 0x78u, 0xD2u, 0xB2u,\r
+ 0x00u, 0x06u, 0x05u, 0xD4u, 0x1Au, 0x78u, 0xD2u, 0xB2u,\r
+ 0x0Au, 0x70u, 0x0Au, 0x78u, 0x02u, 0xF0u, 0x0Fu, 0x02u,\r
+ 0x1Bu, 0x78u, 0x9Au, 0x42u, 0xEFu, 0xD1u, 0x10u, 0xBDu,\r
+ 0x10u, 0xBDu, 0x00u, 0xBFu, 0x28u, 0x60u, 0x00u, 0x40u,\r
+ 0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x66u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0xDEu, 0xC1u, 0xFFu, 0x1Fu, 0x29u, 0x60u, 0x00u, 0x40u,\r
0x05u, 0x4Au, 0x00u, 0x23u, 0x13u, 0x80u, 0x05u, 0x4Au,\r
0x91u, 0x68u, 0x19u, 0xB1u, 0x91u, 0x68u, 0x0Bu, 0x70u,\r
- 0x90u, 0x68u, 0x43u, 0x80u, 0x70u, 0x47u, 0x00u, 0xBFu,\r
- 0xE8u, 0xC1u, 0xFFu, 0x1Fu, 0x60u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x08u, 0xB5u, 0x0Cu, 0x49u, 0x0Cu, 0x4Bu, 0x04u, 0x22u,\r
- 0x80u, 0x20u, 0x1Au, 0x70u, 0x08u, 0x70u, 0xFFu, 0xF7u,\r
- 0xE7u, 0xFFu, 0x0Au, 0x4Bu, 0x1Au, 0x78u, 0x58u, 0x1Eu,\r
- 0x09u, 0x4Bu, 0x01u, 0x78u, 0x18u, 0x88u, 0x41u, 0xEAu,\r
- 0x02u, 0x22u, 0x81u, 0xB2u, 0x91u, 0x42u, 0x88u, 0xBFu,\r
- 0x1Au, 0x80u, 0x06u, 0x4Bu, 0x0Bu, 0x22u, 0x1Au, 0x70u,\r
- 0x01u, 0x20u, 0x08u, 0xBDu, 0x6Eu, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x72u, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x60u, 0x00u, 0x40u,\r
- 0x60u, 0xC1u, 0xFFu, 0x1Fu, 0x5Du, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x10u, 0xB5u, 0x0Fu, 0x4Cu, 0x23u, 0x88u, 0x98u, 0xB2u,\r
- 0x10u, 0xB9u, 0xFFu, 0xF7u, 0x5Bu, 0xFEu, 0x14u, 0xE0u,\r
- 0x0Cu, 0x49u, 0x0Du, 0x4Bu, 0x02u, 0x22u, 0x00u, 0x20u,\r
- 0x0Au, 0x70u, 0x18u, 0x70u, 0xFFu, 0xF7u, 0xBCu, 0xFFu,\r
- 0x0Au, 0x49u, 0x48u, 0x1Eu, 0x0Au, 0x78u, 0x03u, 0x78u,\r
- 0x43u, 0xEAu, 0x02u, 0x21u, 0x22u, 0x88u, 0x90u, 0xB2u,\r
- 0x88u, 0x42u, 0x88u, 0xBFu, 0x21u, 0x80u, 0xFFu, 0xF7u,\r
- 0xFBu, 0xFDu, 0x01u, 0x20u, 0x10u, 0xBDu, 0x00u, 0xBFu,\r
- 0x60u, 0xC1u, 0xFFu, 0x1Fu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x6Eu, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x60u, 0x00u, 0x40u,\r
- 0x09u, 0x4Bu, 0x0Au, 0x48u, 0x1Bu, 0x78u, 0x02u, 0x7Bu,\r
- 0x02u, 0xF0u, 0x03u, 0x01u, 0x01u, 0x29u, 0x03u, 0xD0u,\r
- 0xC3u, 0x7Bu, 0x83u, 0xF0u, 0x80u, 0x02u, 0xC2u, 0x73u,\r
- 0x01u, 0x21u, 0x41u, 0x73u, 0x04u, 0x48u, 0x03u, 0x78u,\r
- 0x03u, 0xF0u, 0xFEu, 0x02u, 0x02u, 0x70u, 0x70u, 0x47u,\r
- 0x0Eu, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x0Bu, 0x60u, 0x00u, 0x40u, 0x09u, 0x4Bu, 0x0Au, 0x48u,\r
- 0x1Bu, 0x78u, 0x02u, 0x7Eu, 0x02u, 0xF0u, 0x03u, 0x01u,\r
- 0x01u, 0x29u, 0x03u, 0xD0u, 0xC3u, 0x7Eu, 0x83u, 0xF0u,\r
- 0x80u, 0x02u, 0xC2u, 0x76u, 0x01u, 0x21u, 0x41u, 0x76u,\r
- 0x04u, 0x48u, 0x03u, 0x78u, 0x03u, 0xF0u, 0xFDu, 0x02u,\r
- 0x02u, 0x70u, 0x70u, 0x47u, 0x1Eu, 0x60u, 0x00u, 0x40u,\r
- 0x78u, 0xC1u, 0xFFu, 0x1Fu, 0x0Bu, 0x60u, 0x00u, 0x40u,\r
- 0x70u, 0x47u, 0xFFu, 0xF7u, 0xE7u, 0xBCu, 0x00u, 0x00u,\r
- 0x08u, 0xB5u, 0x0Bu, 0x4Bu, 0x18u, 0x78u, 0x41u, 0x1Eu,\r
- 0xC8u, 0xB2u, 0x00u, 0xF0u, 0x59u, 0xF9u, 0x09u, 0x4Au,\r
- 0x09u, 0x49u, 0x13u, 0x78u, 0x00u, 0xEBu, 0xC3u, 0x00u,\r
- 0x42u, 0x69u, 0xCBu, 0x5Cu, 0x02u, 0xEBu, 0xC3u, 0x00u,\r
- 0x42u, 0x68u, 0x06u, 0x4Bu, 0x50u, 0x6Au, 0x01u, 0x78u,\r
- 0x19u, 0x80u, 0x58u, 0x60u, 0x08u, 0xBDu, 0x00u, 0xBFu,\r
- 0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x60u, 0x00u, 0x40u,\r
- 0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0x60u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x08u, 0xB5u, 0x0Du, 0x4Bu, 0x18u, 0x78u, 0x41u, 0x1Eu,\r
- 0xC8u, 0xB2u, 0x00u, 0xF0u, 0x39u, 0xF9u, 0x0Bu, 0x4Au,\r
- 0x0Bu, 0x49u, 0x13u, 0x78u, 0x00u, 0xEBu, 0xC3u, 0x00u,\r
- 0x42u, 0x69u, 0xCBu, 0x5Cu, 0x02u, 0xEBu, 0xC3u, 0x00u,\r
- 0x42u, 0x68u, 0xD3u, 0x69u, 0x07u, 0x4Au, 0x59u, 0x78u,\r
- 0x13u, 0xF8u, 0x02u, 0x0Bu, 0x40u, 0xEAu, 0x01u, 0x21u,\r
- 0x11u, 0x80u, 0x53u, 0x60u, 0x08u, 0xBDu, 0x00u, 0xBFu,\r
- 0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x60u, 0x00u, 0x40u,\r
- 0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0x60u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x10u, 0xB5u, 0x16u, 0x4Cu, 0x00u, 0x23u, 0x16u, 0x48u,\r
- 0x23u, 0x80u, 0x01u, 0x78u, 0x4Au, 0x1Eu, 0xD0u, 0xB2u,\r
- 0x00u, 0xF0u, 0x12u, 0xF9u, 0x13u, 0x49u, 0x14u, 0x4Bu,\r
- 0x1Bu, 0x78u, 0x0Au, 0x78u, 0x00u, 0xEBu, 0xC2u, 0x00u,\r
- 0x41u, 0x69u, 0xD2u, 0xB9u, 0x11u, 0x4Au, 0x01u, 0x3Bu,\r
- 0x10u, 0x78u, 0xDAu, 0xB2u, 0x01u, 0xEBu, 0xC0u, 0x01u,\r
- 0x02u, 0x2Au, 0x49u, 0x68u, 0x11u, 0xD8u, 0x0Eu, 0x4Au,\r
- 0x01u, 0xEBu, 0xC3u, 0x00u, 0x12u, 0x78u, 0x11u, 0xF8u,\r
- 0x33u, 0x10u, 0x91u, 0x42u, 0x09u, 0xD3u, 0x0Cu, 0x23u,\r
- 0x5Au, 0x43u, 0x41u, 0x68u, 0x8Bu, 0x18u, 0x58u, 0x68u,\r
- 0x8Au, 0x5Au, 0x99u, 0x68u, 0x60u, 0x60u, 0x22u, 0x80u,\r
- 0xA1u, 0x60u, 0x10u, 0xBDu, 0x60u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x60u, 0x00u, 0x40u,\r
- 0x03u, 0x60u, 0x00u, 0x40u, 0x5Eu, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x02u, 0x60u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x3Au, 0x4Bu,\r
- 0x3Au, 0x4Au, 0x18u, 0x78u, 0x11u, 0x78u, 0x09u, 0x06u,\r
- 0x34u, 0xD5u, 0x51u, 0x1Cu, 0x0Bu, 0x78u, 0x5Au, 0x1Eu,\r
- 0x05u, 0x2Au, 0x67u, 0xD8u, 0xDFu, 0xE8u, 0x02u, 0xF0u,\r
- 0x10u, 0x18u, 0x27u, 0x66u, 0x66u, 0x03u, 0x34u, 0x48u,\r
- 0x01u, 0x78u, 0x21u, 0x29u, 0x02u, 0xD1u, 0xFFu, 0xF7u,\r
- 0x6Bu, 0xFFu, 0x07u, 0xE0u, 0x03u, 0x78u, 0x22u, 0x2Bu,\r
- 0x58u, 0xD1u, 0xFFu, 0xF7u, 0x85u, 0xFFu, 0x01u, 0xE0u,\r
- 0xFFu, 0xF7u, 0xA6u, 0xFFu, 0x2Du, 0x49u, 0x0Bu, 0x88u,\r
- 0x98u, 0xB2u, 0x00u, 0x28u, 0x4Eu, 0xD0u, 0x0Au, 0xE0u,\r
- 0x00u, 0x28u, 0x4Bu, 0xD1u, 0x2Au, 0x4Bu, 0x18u, 0x78u,\r
- 0x00u, 0x28u, 0x47u, 0xD1u, 0x27u, 0x48u, 0x01u, 0x22u,\r
- 0x28u, 0x49u, 0x02u, 0x80u, 0x41u, 0x60u, 0xBDu, 0xE8u,\r
- 0x10u, 0x40u, 0xFFu, 0xF7u, 0xEDu, 0xBEu, 0x00u, 0x28u,\r
- 0x3Cu, 0xD1u, 0x22u, 0x48u, 0x01u, 0x22u, 0x02u, 0x80u,\r
- 0x23u, 0x49u, 0xF3u, 0xE7u, 0x13u, 0x78u, 0x1Au, 0x06u,\r
- 0x34u, 0xD4u, 0x22u, 0x4Au, 0x11u, 0x78u, 0x09u, 0x29u,\r
- 0x05u, 0xD0u, 0x2Fu, 0xD3u, 0x0Au, 0x29u, 0x0Du, 0xD0u,\r
- 0x0Bu, 0x29u, 0x2Bu, 0xD1u, 0x22u, 0xE0u, 0xFFu, 0xF7u,\r
- 0x7Bu, 0xFFu, 0x18u, 0x4Bu, 0x1Au, 0x88u, 0x90u, 0xB2u,\r
- 0x00u, 0x28u, 0x23u, 0xD0u, 0xBDu, 0xE8u, 0x10u, 0x40u,\r
- 0xFFu, 0xF7u, 0xAAu, 0xBEu, 0xF0u, 0xB9u, 0x14u, 0x48u,\r
- 0x01u, 0x78u, 0xD9u, 0xB9u, 0x44u, 0x1Cu, 0x23u, 0x78u,\r
- 0x12u, 0x4Au, 0x13u, 0x70u, 0x14u, 0x4Bu, 0x14u, 0x78u,\r
- 0x18u, 0x78u, 0x84u, 0x42u, 0x01u, 0xD2u, 0x19u, 0x70u,\r
- 0x04u, 0xE0u, 0x19u, 0x78u, 0x01u, 0x29u, 0x01u, 0xD9u,\r
- 0x12u, 0x78u, 0x1Au, 0x70u, 0xBDu, 0xE8u, 0x10u, 0x40u,\r
- 0xFFu, 0xF7u, 0x6Cu, 0xBDu, 0x30u, 0xB9u, 0x08u, 0x48u,\r
- 0x03u, 0x78u, 0x01u, 0x2Bu, 0x02u, 0xD8u, 0x02u, 0x78u,\r
- 0x07u, 0x4Bu, 0xF2u, 0xE7u, 0x00u, 0x20u, 0x10u, 0xBDu,\r
+ 0x92u, 0x68u, 0x53u, 0x80u, 0x70u, 0x47u, 0x00u, 0xBFu,\r
+ 0xE0u, 0xC1u, 0xFFu, 0x1Fu, 0x58u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x10u, 0xB5u, 0x0Fu, 0x4Cu, 0x23u, 0x88u, 0x9Bu, 0xB2u,\r
+ 0x13u, 0xB9u, 0xFFu, 0xF7u, 0x85u, 0xFEu, 0x14u, 0xE0u,\r
+ 0x0Cu, 0x4Bu, 0x02u, 0x22u, 0x1Au, 0x70u, 0x0Cu, 0x4Bu,\r
+ 0x00u, 0x22u, 0x1Au, 0x70u, 0xFFu, 0xF7u, 0xE0u, 0xFFu,\r
+ 0x0Au, 0x4Bu, 0x1Au, 0x78u, 0x01u, 0x3Bu, 0x1Bu, 0x78u,\r
+ 0x43u, 0xEAu, 0x02u, 0x23u, 0x22u, 0x88u, 0x92u, 0xB2u,\r
+ 0x9Au, 0x42u, 0x88u, 0xBFu, 0x23u, 0x80u, 0xFFu, 0xF7u,\r
+ 0x27u, 0xFEu, 0x01u, 0x20u, 0x10u, 0xBDu, 0x00u, 0xBFu,\r
+ 0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x66u, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x60u, 0x00u, 0x40u,\r
+ 0x08u, 0xB5u, 0x0Cu, 0x4Bu, 0x04u, 0x22u, 0x1Au, 0x70u,\r
+ 0x0Bu, 0x4Bu, 0x80u, 0x22u, 0x1Au, 0x70u, 0xFFu, 0xF7u,\r
+ 0xBFu, 0xFFu, 0x0Au, 0x4Bu, 0x01u, 0x20u, 0x1Au, 0x78u,\r
+ 0x01u, 0x3Bu, 0x1Bu, 0x78u, 0x43u, 0xEAu, 0x02u, 0x22u,\r
+ 0x07u, 0x4Bu, 0x19u, 0x88u, 0x89u, 0xB2u, 0x91u, 0x42u,\r
+ 0x88u, 0xBFu, 0x1Au, 0x80u, 0x05u, 0x4Bu, 0x0Bu, 0x22u,\r
+ 0x1Au, 0x70u, 0x08u, 0xBDu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x66u, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x60u, 0x00u, 0x40u,\r
+ 0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x09u, 0x4Bu, 0x1Bu, 0x78u, 0x09u, 0x4Bu, 0x1Au, 0x7Bu,\r
+ 0x02u, 0xF0u, 0x03u, 0x02u, 0x01u, 0x2Au, 0x03u, 0xD0u,\r
+ 0xDAu, 0x7Bu, 0x82u, 0xF0u, 0x80u, 0x02u, 0xDAu, 0x73u,\r
+ 0x01u, 0x22u, 0x5Au, 0x73u, 0x04u, 0x4Bu, 0x1Au, 0x78u,\r
+ 0x02u, 0xF0u, 0xFEu, 0x02u, 0x1Au, 0x70u, 0x70u, 0x47u,\r
+ 0x0Eu, 0x60u, 0x00u, 0x40u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x0Bu, 0x60u, 0x00u, 0x40u, 0x09u, 0x4Bu, 0x1Bu, 0x78u,\r
+ 0x09u, 0x4Bu, 0x1Au, 0x7Eu, 0x02u, 0xF0u, 0x03u, 0x02u,\r
+ 0x01u, 0x2Au, 0x03u, 0xD0u, 0xDAu, 0x7Eu, 0x82u, 0xF0u,\r
+ 0x80u, 0x02u, 0xDAu, 0x76u, 0x01u, 0x22u, 0x5Au, 0x76u,\r
+ 0x04u, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u, 0xFDu, 0x02u,\r
+ 0x1Au, 0x70u, 0x70u, 0x47u, 0x1Eu, 0x60u, 0x00u, 0x40u,\r
+ 0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x0Bu, 0x60u, 0x00u, 0x40u,\r
+ 0x70u, 0x47u, 0xFFu, 0xF7u, 0xEBu, 0xBCu, 0x00u, 0x00u,\r
+ 0x08u, 0xB5u, 0x0Cu, 0x4Bu, 0x18u, 0x78u, 0x01u, 0x38u,\r
+ 0xC0u, 0xB2u, 0x00u, 0xF0u, 0x4Bu, 0xF9u, 0x0Au, 0x4Bu,\r
+ 0x0Au, 0x49u, 0x1Bu, 0x78u, 0xDBu, 0xB2u, 0x00u, 0xEBu,\r
+ 0xC3u, 0x00u, 0x42u, 0x69u, 0xCBu, 0x5Cu, 0x02u, 0xEBu,\r
+ 0xC3u, 0x03u, 0x5Bu, 0x68u, 0x5Au, 0x6Au, 0x06u, 0x4Bu,\r
+ 0x11u, 0x78u, 0xC9u, 0xB2u, 0x19u, 0x80u, 0x5Au, 0x60u,\r
+ 0x08u, 0xBDu, 0x00u, 0xBFu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x04u, 0x60u, 0x00u, 0x40u, 0x56u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x0Du, 0x4Bu,\r
+ 0x18u, 0x78u, 0x01u, 0x38u, 0xC0u, 0xB2u, 0x00u, 0xF0u,\r
+ 0x29u, 0xF9u, 0x0Bu, 0x4Bu, 0x0Bu, 0x49u, 0x1Bu, 0x78u,\r
+ 0xDBu, 0xB2u, 0x00u, 0xEBu, 0xC3u, 0x00u, 0x42u, 0x69u,\r
+ 0xCBu, 0x5Cu, 0x02u, 0xEBu, 0xC3u, 0x03u, 0x5Bu, 0x68u,\r
+ 0xDBu, 0x69u, 0x59u, 0x78u, 0x13u, 0xF8u, 0x02u, 0x2Bu,\r
+ 0x42u, 0xEAu, 0x01u, 0x21u, 0x04u, 0x4Au, 0x11u, 0x80u,\r
+ 0x53u, 0x60u, 0x08u, 0xBDu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x04u, 0x60u, 0x00u, 0x40u, 0x56u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x10u, 0xB5u, 0x19u, 0x4Cu,\r
+ 0x00u, 0x23u, 0x23u, 0x80u, 0x18u, 0x4Bu, 0x18u, 0x78u,\r
+ 0x01u, 0x38u, 0xC0u, 0xB2u, 0x00u, 0xF0u, 0x02u, 0xF9u,\r
+ 0x16u, 0x4Bu, 0x17u, 0x4Au, 0x1Bu, 0x78u, 0x12u, 0x78u,\r
+ 0xDBu, 0xB2u, 0xD2u, 0xB2u, 0x00u, 0xEBu, 0xC2u, 0x00u,\r
+ 0x41u, 0x69u, 0xEAu, 0xB9u, 0x13u, 0x4Au, 0x12u, 0x78u,\r
+ 0x01u, 0xEBu, 0xC2u, 0x02u, 0x51u, 0x68u, 0x5Au, 0x1Eu,\r
+ 0x02u, 0x2Au, 0x15u, 0xD8u, 0x10u, 0x4Au, 0x03u, 0xF1u,\r
+ 0x00u, 0x53u, 0x01u, 0x3Bu, 0x12u, 0x78u, 0x01u, 0xEBu,\r
+ 0xC3u, 0x00u, 0x11u, 0xF8u, 0x33u, 0x30u, 0xD2u, 0xB2u,\r
+ 0x93u, 0x42u, 0x09u, 0xD3u, 0x0Cu, 0x23u, 0x5Au, 0x43u,\r
+ 0x41u, 0x68u, 0x8Bu, 0x18u, 0x58u, 0x68u, 0x8Au, 0x5Au,\r
+ 0x9Bu, 0x68u, 0x60u, 0x60u, 0x22u, 0x80u, 0xA3u, 0x60u,\r
+ 0x10u, 0xBDu, 0x00u, 0xBFu, 0x58u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x03u, 0x60u, 0x00u, 0x40u,\r
+ 0x04u, 0x60u, 0x00u, 0x40u, 0x56u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x02u, 0x60u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x3Cu, 0x4Bu,\r
+ 0x3Cu, 0x4Au, 0x1Bu, 0x78u, 0x11u, 0x78u, 0xDBu, 0xB2u,\r
+ 0x09u, 0x06u, 0x34u, 0xD5u, 0x01u, 0x32u, 0x12u, 0x78u,\r
+ 0x01u, 0x3Au, 0x05u, 0x2Au, 0x6Au, 0xD8u, 0xDFu, 0xE8u,\r
+ 0x02u, 0xF0u, 0x10u, 0x18u, 0x27u, 0x69u, 0x69u, 0x03u,\r
+ 0x35u, 0x4Bu, 0x1Au, 0x78u, 0x21u, 0x2Au, 0x02u, 0xD1u,\r
+ 0xFFu, 0xF7u, 0x62u, 0xFFu, 0x07u, 0xE0u, 0x1Bu, 0x78u,\r
+ 0x22u, 0x2Bu, 0x5Bu, 0xD1u, 0xFFu, 0xF7u, 0x7Eu, 0xFFu,\r
+ 0x01u, 0xE0u, 0xFFu, 0xF7u, 0x9Fu, 0xFFu, 0x2Fu, 0x4Bu,\r
+ 0x1Bu, 0x88u, 0x9Bu, 0xB2u, 0x00u, 0x2Bu, 0x51u, 0xD0u,\r
+ 0x0Au, 0xE0u, 0x00u, 0x2Bu, 0x4Eu, 0xD1u, 0x2Cu, 0x4Bu,\r
+ 0x1Bu, 0x78u, 0x00u, 0x2Bu, 0x4Au, 0xD1u, 0x29u, 0x4Bu,\r
+ 0x01u, 0x22u, 0x1Au, 0x80u, 0x29u, 0x4Au, 0x5Au, 0x60u,\r
+ 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0xC0u, 0xBEu,\r
+ 0x00u, 0x2Bu, 0x3Fu, 0xD1u, 0x23u, 0x4Bu, 0x01u, 0x22u,\r
+ 0x1Au, 0x80u, 0x25u, 0x4Au, 0xF3u, 0xE7u, 0x12u, 0x78u,\r
+ 0x12u, 0x06u, 0x37u, 0xD4u, 0x23u, 0x4Au, 0x12u, 0x78u,\r
+ 0xD2u, 0xB2u, 0x0Au, 0x2Au, 0x0Du, 0xD0u, 0x0Bu, 0x2Au,\r
+ 0x27u, 0xD0u, 0x09u, 0x2Au, 0x2Eu, 0xD1u, 0xFFu, 0xF7u,\r
+ 0x75u, 0xFFu, 0x1Au, 0x4Bu, 0x1Bu, 0x88u, 0x9Bu, 0xB2u,\r
+ 0x43u, 0xB3u, 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u,\r
+ 0xCBu, 0xBEu, 0x1Bu, 0xBBu, 0x16u, 0x4Bu, 0x1Bu, 0x78u,\r
+ 0x03u, 0xF0u, 0xFFu, 0x01u, 0xF3u, 0xB9u, 0x12u, 0x4Bu,\r
+ 0x14u, 0x4Au, 0x1Bu, 0x78u, 0xDBu, 0xB2u, 0x13u, 0x70u,\r
+ 0x15u, 0x4Bu, 0x14u, 0x78u, 0x18u, 0x78u, 0x84u, 0x42u,\r
+ 0x01u, 0xD2u, 0x19u, 0x70u, 0x05u, 0xE0u, 0x19u, 0x78u,\r
+ 0x01u, 0x29u, 0x02u, 0xD9u, 0x12u, 0x78u, 0xD2u, 0xB2u,\r
+ 0x1Au, 0x70u, 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u,\r
+ 0x67u, 0xBDu, 0x3Bu, 0xB9u, 0x08u, 0x4Bu, 0x1Au, 0x78u,\r
+ 0x01u, 0x2Au, 0x03u, 0xD8u, 0x1Au, 0x78u, 0x08u, 0x4Bu,\r
+ 0xD2u, 0xB2u, 0xF1u, 0xE7u, 0x00u, 0x20u, 0x10u, 0xBDu,\r
0x04u, 0x60u, 0x00u, 0x40u, 0x00u, 0x60u, 0x00u, 0x40u,\r
- 0x03u, 0x60u, 0x00u, 0x40u, 0x60u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x02u, 0x60u, 0x00u, 0x40u, 0xEAu, 0xC1u, 0xFFu, 0x1Fu,\r
- 0xECu, 0xC1u, 0xFFu, 0x1Fu, 0x01u, 0x60u, 0x00u, 0x40u,\r
- 0xEBu, 0xC1u, 0xFFu, 0x1Fu, 0x30u, 0xB5u, 0x01u, 0x22u,\r
- 0x02u, 0xF1u, 0x0Fu, 0x03u, 0x18u, 0x01u, 0x09u, 0x2Au,\r
- 0xC3u, 0xB2u, 0x3Bu, 0xD0u, 0x1Fu, 0x49u, 0x03u, 0xF1u,\r
- 0x80u, 0x44u, 0x0Cu, 0x20u, 0x04u, 0xF5u, 0xC1u, 0x45u,\r
- 0x00u, 0xFBu, 0x02u, 0x14u, 0x28u, 0x70u, 0x1Cu, 0x49u,\r
- 0x65u, 0x79u, 0x59u, 0x18u, 0x25u, 0xB1u, 0x24u, 0x79u,\r
- 0x24u, 0x06u, 0x58u, 0xBFu, 0x08u, 0x20u, 0x00u, 0xE0u,\r
- 0x80u, 0x20u, 0x08u, 0x70u, 0x17u, 0x49u, 0x0Cu, 0x24u,\r
- 0x58u, 0x18u, 0x14u, 0x49u, 0x04u, 0xFBu, 0x02u, 0x11u,\r
- 0x0Cu, 0x89u, 0x01u, 0x32u, 0xC4u, 0xF3u, 0x07u, 0x24u,\r
- 0x04u, 0x70u, 0x0Cu, 0x89u, 0x12u, 0x48u, 0xE4u, 0xB2u,\r
- 0x18u, 0x18u, 0x04u, 0x70u, 0xCCu, 0x88u, 0x11u, 0x48u,\r
- 0xE4u, 0xB2u, 0x18u, 0x18u, 0x04u, 0x70u, 0xCCu, 0x88u,\r
- 0x0Fu, 0x48u, 0xC4u, 0xF3u, 0x07u, 0x24u, 0x18u, 0x18u,\r
- 0x04u, 0x70u, 0xCCu, 0x88u, 0x0Du, 0x48u, 0xE4u, 0xB2u,\r
- 0x18u, 0x18u, 0x04u, 0x70u, 0x0Cu, 0x48u, 0xD2u, 0xB2u,\r
- 0x18u, 0x18u, 0xCBu, 0x88u, 0xC3u, 0xF3u, 0x07u, 0x21u,\r
- 0x01u, 0x70u, 0xBDu, 0xE7u, 0x09u, 0x49u, 0xFFu, 0x22u,\r
- 0x0Au, 0x70u, 0x30u, 0xBDu, 0x78u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x03u, 0x60u, 0x00u, 0x40u, 0x58u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x02u, 0x60u, 0x00u, 0x40u, 0xE2u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0xE4u, 0xC1u, 0xFFu, 0x1Fu, 0x01u, 0x60u, 0x00u, 0x40u,\r
+ 0xE3u, 0xC1u, 0xFFu, 0x1Fu, 0x30u, 0xB5u, 0x1Cu, 0x4Bu,\r
+ 0x01u, 0x21u, 0x1Cu, 0x4Au, 0x0Cu, 0x20u, 0x00u, 0xFBu,\r
+ 0x01u, 0x24u, 0x83u, 0xF8u, 0x72u, 0x00u, 0x65u, 0x79u,\r
+ 0x25u, 0xB1u, 0x24u, 0x79u, 0x24u, 0x06u, 0x58u, 0xBFu,\r
+ 0x08u, 0x20u, 0x00u, 0xE0u, 0x80u, 0x20u, 0x18u, 0x70u,\r
+ 0x0Cu, 0x20u, 0x00u, 0xFBu, 0x01u, 0x22u, 0x10u, 0x89u,\r
+ 0x01u, 0x31u, 0xC0u, 0xF3u, 0x07u, 0x20u, 0x03u, 0xF8u,\r
+ 0x02u, 0x0Cu, 0x10u, 0x89u, 0x09u, 0x29u, 0xC0u, 0xB2u,\r
+ 0x03u, 0xF8u, 0x01u, 0x0Cu, 0xD0u, 0x88u, 0x03u, 0xF1u,\r
+ 0x10u, 0x03u, 0xC0u, 0xB2u, 0x83u, 0xF8u, 0x68u, 0x00u,\r
+ 0xD0u, 0x88u, 0xC0u, 0xF3u, 0x07u, 0x20u, 0x83u, 0xF8u,\r
+ 0x69u, 0x00u, 0xD0u, 0x88u, 0xC0u, 0xB2u, 0x83u, 0xF8u,\r
+ 0x66u, 0x00u, 0xD2u, 0x88u, 0xC2u, 0xF3u, 0x07u, 0x22u,\r
+ 0x83u, 0xF8u, 0x67u, 0x20u, 0xCDu, 0xD1u, 0x04u, 0x4Bu,\r
+ 0xFFu, 0x22u, 0x1Au, 0x70u, 0x30u, 0xBDu, 0x00u, 0xBFu,\r
+ 0x0Eu, 0x60u, 0x00u, 0x40u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x0Au, 0x60u, 0x00u, 0x40u, 0x07u, 0x4Bu, 0x1Au, 0x78u,\r
+ 0x07u, 0x4Bu, 0x03u, 0xEBu, 0xC2u, 0x03u, 0x5Bu, 0x68u,\r
+ 0x03u, 0xF1u, 0x08u, 0x02u, 0x1Bu, 0x7Au, 0x83u, 0x42u,\r
+ 0x86u, 0xBFu, 0x02u, 0xEBu, 0xC0u, 0x00u, 0x40u, 0x68u,\r
+ 0x00u, 0x20u, 0x70u, 0x47u, 0x64u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x8Cu, 0x21u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x39u, 0x4Bu,\r
+ 0x1Au, 0x78u, 0x00u, 0x2Au, 0x6Cu, 0xD0u, 0x18u, 0x78u,\r
+ 0x01u, 0x38u, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0xE2u, 0xFFu,\r
+ 0xC3u, 0x68u, 0x04u, 0x7Au, 0x08u, 0x33u, 0x03u, 0xEBu,\r
+ 0xC4u, 0x04u, 0xA3u, 0x42u, 0x60u, 0xD0u, 0x13u, 0xF8u,\r
+ 0x08u, 0x2Cu, 0x31u, 0x49u, 0x31u, 0x48u, 0x8Du, 0x5Cu,\r
+ 0x80u, 0x5Cu, 0x85u, 0x42u, 0x56u, 0xD0u, 0x89u, 0x5Cu,\r
+ 0x13u, 0xF8u, 0x07u, 0x0Cu, 0x88u, 0x42u, 0x51u, 0xD1u,\r
+ 0x2Du, 0x49u, 0x09u, 0x78u, 0x8Au, 0x42u, 0x4Du, 0xD1u,\r
+ 0x13u, 0xF8u, 0x06u, 0x0Cu, 0x13u, 0xF8u, 0x05u, 0x6Cu,\r
+ 0x00u, 0xF0u, 0x7Fu, 0x02u, 0x51u, 0x1Eu, 0x10u, 0xF0u,\r
+ 0x80u, 0x0Fu, 0x28u, 0x48u, 0x4Fu, 0xEAu, 0x01u, 0x11u,\r
+ 0x4Fu, 0xF0u, 0x0Cu, 0x05u, 0xC9u, 0xB2u, 0x06u, 0xF0u,\r
+ 0x03u, 0x06u, 0x05u, 0xFBu, 0x02u, 0x05u, 0x06u, 0xD0u,\r
+ 0x01u, 0x27u, 0xBEu, 0x42u, 0x6Fu, 0x70u, 0x14u, 0xBFu,\r
+ 0x0Du, 0x26u, 0x07u, 0x26u, 0x05u, 0xE0u, 0x00u, 0x27u,\r
+ 0x01u, 0x2Eu, 0x6Fu, 0x70u, 0x14u, 0xBFu, 0x09u, 0x26u,\r
+ 0x05u, 0x26u, 0x6Eu, 0x71u, 0x1Cu, 0x4Du, 0x01u, 0x26u,\r
+ 0x6Eu, 0x54u, 0x0Cu, 0x25u, 0x55u, 0x43u, 0x33u, 0xF8u,\r
+ 0x04u, 0x6Cu, 0x42u, 0x19u, 0x16u, 0x81u, 0x13u, 0xF8u,\r
+ 0x06u, 0x6Cu, 0x16u, 0x71u, 0x13u, 0xF8u, 0x05u, 0x6Cu,\r
+ 0x46u, 0x55u, 0x00u, 0x20u, 0xD0u, 0x70u, 0x15u, 0x89u,\r
+ 0x14u, 0x48u, 0xC5u, 0xF3u, 0x07u, 0x25u, 0x45u, 0x54u,\r
+ 0x15u, 0x89u, 0x01u, 0x30u, 0xEDu, 0xB2u, 0x45u, 0x54u,\r
+ 0xD5u, 0x88u, 0x79u, 0x30u, 0xEDu, 0xB2u, 0x45u, 0x54u,\r
+ 0xD5u, 0x88u, 0x01u, 0x30u, 0xC5u, 0xF3u, 0x07u, 0x25u,\r
+ 0x45u, 0x54u, 0xD5u, 0x88u, 0x03u, 0x38u, 0xEDu, 0xB2u,\r
+ 0x45u, 0x54u, 0xD2u, 0x88u, 0x01u, 0x30u, 0xC2u, 0xF3u,\r
+ 0x07u, 0x22u, 0x42u, 0x54u, 0x08u, 0x33u, 0x9Cu, 0xE7u,\r
+ 0xF8u, 0xBDu, 0x00u, 0xBFu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x56u, 0xC1u, 0xFFu, 0x1Fu, 0xDCu, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x04u, 0x60u, 0x00u, 0x40u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,\r
0x0Eu, 0x60u, 0x00u, 0x40u, 0x0Cu, 0x60u, 0x00u, 0x40u,\r
- 0x0Du, 0x60u, 0x00u, 0x40u, 0x86u, 0x60u, 0x00u, 0x40u,\r
- 0x87u, 0x60u, 0x00u, 0x40u, 0x84u, 0x60u, 0x00u, 0x40u,\r
- 0x85u, 0x60u, 0x00u, 0x40u, 0x0Au, 0x60u, 0x00u, 0x40u,\r
- 0x04u, 0x4Bu, 0x05u, 0x49u, 0x1Au, 0x78u, 0x01u, 0xEBu,\r
- 0xC2u, 0x03u, 0x5Au, 0x68u, 0x02u, 0xEBu, 0xC0u, 0x00u,\r
- 0xC0u, 0x68u, 0x70u, 0x47u, 0x6Cu, 0xC1u, 0xFFu, 0x1Fu,\r
- 0xD4u, 0x20u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x3Du, 0x4Bu,\r
- 0x1Au, 0x78u, 0x00u, 0x2Au, 0x74u, 0xD0u, 0x18u, 0x78u,\r
- 0x41u, 0x1Eu, 0xC8u, 0xB2u, 0xFFu, 0xF7u, 0xE8u, 0xFFu,\r
- 0xC3u, 0x68u, 0x05u, 0x7Au, 0x08u, 0x33u, 0x00u, 0x20u,\r
- 0xA8u, 0x42u, 0x69u, 0xD0u, 0x13u, 0xF8u, 0x08u, 0x2Cu,\r
- 0x35u, 0x49u, 0x36u, 0x4Cu, 0x8Eu, 0x5Cu, 0xA4u, 0x5Cu,\r
- 0xA6u, 0x42u, 0x5Du, 0xD0u, 0x89u, 0x5Cu, 0x13u, 0xF8u,\r
- 0x07u, 0x4Cu, 0x8Cu, 0x42u, 0x58u, 0xD1u, 0x32u, 0x49u,\r
- 0x09u, 0x78u, 0x8Au, 0x42u, 0x54u, 0xD1u, 0x13u, 0xF8u,\r
- 0x06u, 0x7Cu, 0x07u, 0xF0u, 0x7Fu, 0x02u, 0x56u, 0x1Eu,\r
- 0x34u, 0x01u, 0xE1u, 0xB2u, 0x13u, 0xF8u, 0x05u, 0x6Cu,\r
- 0x2Cu, 0x4Cu, 0x17u, 0xF0u, 0x80u, 0x0Fu, 0x4Fu, 0xF0u,\r
- 0x0Cu, 0x07u, 0x06u, 0xF0u, 0x03u, 0x06u, 0x07u, 0xFBu,\r
- 0x02u, 0x44u, 0x06u, 0xD0u, 0x01u, 0x27u, 0x67u, 0x70u,\r
- 0xBEu, 0x42u, 0x14u, 0xBFu, 0x0Du, 0x26u, 0x07u, 0x26u,\r
- 0x05u, 0xE0u, 0x00u, 0x27u, 0x67u, 0x70u, 0x01u, 0x2Eu,\r
- 0x14u, 0xBFu, 0x09u, 0x26u, 0x05u, 0x26u, 0x66u, 0x71u,\r
- 0x21u, 0x4Cu, 0x01u, 0x26u, 0x0Fu, 0x19u, 0x0Cu, 0x24u,\r
- 0x54u, 0x43u, 0x3Eu, 0x70u, 0x1Du, 0x4Eu, 0x33u, 0xF8u,\r
- 0x04u, 0x7Cu, 0x32u, 0x19u, 0x17u, 0x81u, 0x13u, 0xF8u,\r
- 0x06u, 0x7Cu, 0x17u, 0x71u, 0x13u, 0xF8u, 0x05u, 0x7Cu,\r
- 0x37u, 0x55u, 0x00u, 0x26u, 0xD6u, 0x70u, 0x16u, 0x89u,\r
- 0x18u, 0x4Cu, 0xC6u, 0xF3u, 0x07u, 0x26u, 0x0Cu, 0x19u,\r
- 0x26u, 0x70u, 0x16u, 0x89u, 0x16u, 0x4Cu, 0xF6u, 0xB2u,\r
- 0x0Cu, 0x19u, 0x26u, 0x70u, 0xD6u, 0x88u, 0x15u, 0x4Cu,\r
- 0xF6u, 0xB2u, 0x0Cu, 0x19u, 0x26u, 0x70u, 0xD6u, 0x88u,\r
- 0x13u, 0x4Cu, 0xC6u, 0xF3u, 0x07u, 0x26u, 0x0Cu, 0x19u,\r
- 0x26u, 0x70u, 0xD6u, 0x88u, 0x11u, 0x4Cu, 0xF6u, 0xB2u,\r
- 0x0Cu, 0x19u, 0x26u, 0x70u, 0x10u, 0x4Cu, 0x0Cu, 0x19u,\r
- 0xD1u, 0x88u, 0xC1u, 0xF3u, 0x07u, 0x22u, 0x22u, 0x70u,\r
- 0x01u, 0x30u, 0xC0u, 0xB2u, 0x08u, 0x33u, 0x93u, 0xE7u,\r
- 0xF8u, 0xBDu, 0x00u, 0xBFu, 0x71u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0xE4u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x04u, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x0Eu, 0x60u, 0x00u, 0x40u, 0x0Cu, 0x60u, 0x00u, 0x40u,\r
- 0x0Du, 0x60u, 0x00u, 0x40u, 0x86u, 0x60u, 0x00u, 0x40u,\r
- 0x87u, 0x60u, 0x00u, 0x40u, 0x84u, 0x60u, 0x00u, 0x40u,\r
- 0x85u, 0x60u, 0x00u, 0x40u, 0x08u, 0xB5u, 0x06u, 0x4Bu,\r
- 0x18u, 0x78u, 0x41u, 0x1Eu, 0xC8u, 0xB2u, 0xFFu, 0xF7u,\r
- 0x57u, 0xFFu, 0x42u, 0x68u, 0x13u, 0x79u, 0x00u, 0xEBu,\r
- 0xC3u, 0x00u, 0x40u, 0x69u, 0x08u, 0xBDu, 0x00u, 0xBFu,\r
- 0x71u, 0xC1u, 0xFFu, 0x1Fu, 0xF8u, 0xB5u, 0x00u, 0x21u,\r
- 0x0Cu, 0x24u, 0x4Cu, 0x43u, 0x51u, 0x4Du, 0x01u, 0x31u,\r
- 0x00u, 0x23u, 0x2Au, 0x19u, 0x09u, 0x29u, 0x2Bu, 0x55u,\r
- 0x93u, 0x70u, 0x02u, 0xF1u, 0x08u, 0x04u, 0x53u, 0x70u,\r
+ 0x08u, 0xB5u, 0x06u, 0x4Bu, 0x18u, 0x78u, 0x01u, 0x38u,\r
+ 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x63u, 0xFFu, 0x20u, 0xB1u,\r
+ 0x43u, 0x68u, 0x1Bu, 0x79u, 0x00u, 0xEBu, 0xC3u, 0x00u,\r
+ 0x40u, 0x69u, 0x08u, 0xBDu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0xF8u, 0xB5u, 0x00u, 0x21u, 0x0Cu, 0x25u, 0x4Du, 0x43u,\r
+ 0x4Cu, 0x4Cu, 0x01u, 0x31u, 0x00u, 0x23u, 0x62u, 0x19u,\r
+ 0x09u, 0x29u, 0x63u, 0x55u, 0x93u, 0x70u, 0x53u, 0x70u,\r
0xD3u, 0x70u, 0x53u, 0x71u, 0x13u, 0x81u, 0x93u, 0x72u,\r
- 0xEEu, 0xD1u, 0x18u, 0xB1u, 0x4Au, 0x48u, 0x4Bu, 0x4Au,\r
- 0x03u, 0x70u, 0x13u, 0x70u, 0x4Au, 0x4Bu, 0x19u, 0x78u,\r
- 0x00u, 0x29u, 0x00u, 0xF0u, 0x8Au, 0x80u, 0x1Cu, 0x78u,\r
- 0x60u, 0x1Eu, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x2Cu, 0xFFu,\r
- 0x42u, 0x68u, 0xD3u, 0x79u, 0x03u, 0xF0u, 0x40u, 0x01u,\r
- 0xCCu, 0xB2u, 0x44u, 0x4Bu, 0x1Cu, 0xB1u, 0x1Cu, 0x78u,\r
- 0x44u, 0xF0u, 0x01u, 0x01u, 0x02u, 0xE0u, 0x1Au, 0x78u,\r
- 0x02u, 0xF0u, 0xFEu, 0x01u, 0x04u, 0x7Au, 0x19u, 0x70u,\r
- 0x01u, 0x22u, 0xC3u, 0x68u, 0x00u, 0x21u, 0x08u, 0x33u,\r
- 0xA1u, 0x42u, 0x43u, 0xD0u, 0x13u, 0xF8u, 0x06u, 0x5Cu,\r
- 0x05u, 0xF0u, 0x7Fu, 0x06u, 0xB2u, 0x42u, 0x39u, 0xD1u,\r
- 0x34u, 0x4Eu, 0x0Cu, 0x27u, 0x07u, 0xFBu, 0x02u, 0x66u,\r
- 0xB6u, 0xF8u, 0x08u, 0xE0u, 0x33u, 0xF8u, 0x04u, 0x7Cu,\r
- 0x1Fu, 0xFAu, 0x8Eu, 0xFCu, 0xBCu, 0x45u, 0x38u, 0xBFu,\r
- 0x37u, 0x81u, 0x13u, 0xF8u, 0x08u, 0x6Cu, 0x2Eu, 0x4Fu,\r
- 0xBEu, 0x5Du, 0x13u, 0xF8u, 0x07u, 0x7Cu, 0xB7u, 0x42u,\r
- 0x24u, 0xD1u, 0x13u, 0xF8u, 0x05u, 0x6Cu, 0x15u, 0xF0u,\r
- 0x80u, 0x0Fu, 0x28u, 0x4Du, 0x4Fu, 0xF0u, 0x0Cu, 0x07u,\r
- 0x06u, 0xF0u, 0x03u, 0x06u, 0x07u, 0xFBu, 0x02u, 0x55u,\r
- 0x06u, 0xD0u, 0x01u, 0x27u, 0x6Fu, 0x70u, 0xBEu, 0x42u,\r
- 0x14u, 0xBFu, 0x0Du, 0x26u, 0x07u, 0x26u, 0x05u, 0xE0u,\r
- 0x00u, 0x27u, 0x6Fu, 0x70u, 0x01u, 0x2Eu, 0x14u, 0xBFu,\r
- 0x09u, 0x26u, 0x05u, 0x26u, 0x6Eu, 0x71u, 0x0Cu, 0x25u,\r
- 0x55u, 0x43u, 0x1Cu, 0x4Eu, 0x13u, 0xF8u, 0x06u, 0xECu,\r
- 0x77u, 0x19u, 0x87u, 0xF8u, 0x04u, 0xE0u, 0x13u, 0xF8u,\r
- 0x05u, 0x7Cu, 0x77u, 0x55u, 0x01u, 0x31u, 0xC9u, 0xB2u,\r
- 0x08u, 0x33u, 0xB9u, 0xE7u, 0x01u, 0x32u, 0x09u, 0x2Au,\r
- 0xB3u, 0xD1u, 0xC3u, 0x68u, 0x00u, 0x22u, 0x08u, 0x33u,\r
- 0xA2u, 0x42u, 0x0Du, 0xD0u, 0x13u, 0xF8u, 0x06u, 0x5Cu,\r
- 0x0Cu, 0x26u, 0x05u, 0xF0u, 0x7Fu, 0x01u, 0x0Fu, 0x4Du,\r
- 0x13u, 0xF8u, 0x08u, 0x0Cu, 0x06u, 0xFBu, 0x01u, 0x51u,\r
- 0x01u, 0x32u, 0x88u, 0x72u, 0xD2u, 0xB2u, 0xEEu, 0xE7u,\r
- 0xFFu, 0xF7u, 0x5Cu, 0xFFu, 0x0Eu, 0x4Bu, 0x00u, 0x22u,\r
- 0x18u, 0x60u, 0x01u, 0x23u, 0x07u, 0x49u, 0x0Cu, 0x20u,\r
- 0x00u, 0xFBu, 0x03u, 0x10u, 0xC2u, 0x80u, 0x01u, 0x89u,\r
- 0x01u, 0x33u, 0x52u, 0x18u, 0x09u, 0x2Bu, 0x92u, 0xB2u,\r
- 0xF4u, 0xD1u, 0xBDu, 0xE8u, 0xF8u, 0x40u, 0xFFu, 0xF7u,\r
- 0x4Du, 0xBEu, 0xF8u, 0xBDu, 0x78u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0xE4u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x6Fu, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x74u, 0xC1u, 0xFFu, 0x1Fu, 0x12u, 0x4Bu, 0x19u, 0x78u,\r
- 0x01u, 0xF0u, 0x7Fu, 0x01u, 0x4Au, 0x1Eu, 0xD0u, 0xB2u,\r
- 0x07u, 0x28u, 0x1Au, 0xD8u, 0x03u, 0x01u, 0xDAu, 0xB2u,\r
- 0x0Eu, 0x4Bu, 0x0Cu, 0x20u, 0x00u, 0xFBu, 0x01u, 0x30u,\r
- 0x81u, 0x78u, 0x41u, 0xF0u, 0x01u, 0x03u, 0x00u, 0x21u,\r
- 0x83u, 0x70u, 0xC1u, 0x70u, 0x43u, 0x78u, 0x43u, 0xF0u,\r
- 0x02u, 0x01u, 0x41u, 0x70u, 0x00u, 0x79u, 0x08u, 0x4Bu,\r
- 0x10u, 0xF0u, 0x80u, 0x0Fu, 0x01u, 0xD0u, 0x8Du, 0x21u,\r
- 0x00u, 0xE0u, 0x89u, 0x21u, 0xD1u, 0x54u, 0xFFu, 0xF7u,\r
- 0x6Du, 0xBBu, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0xBFu,\r
- 0x04u, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x0Eu, 0x60u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x1Au, 0x4Bu,\r
- 0x18u, 0x78u, 0x00u, 0xF0u, 0x7Fu, 0x03u, 0x5Au, 0x1Eu,\r
- 0xD2u, 0xB2u, 0x07u, 0x2Au, 0x2Au, 0xD8u, 0x17u, 0x49u,\r
- 0x0Cu, 0x20u, 0x00u, 0xFBu, 0x03u, 0x13u, 0x9Cu, 0x78u,\r
- 0x12u, 0x01u, 0x04u, 0xF0u, 0xFEu, 0x01u, 0x99u, 0x70u,\r
- 0x00u, 0x24u, 0x13u, 0x49u, 0xDCu, 0x70u, 0xD2u, 0xB2u,\r
- 0x54u, 0x5Cu, 0x04u, 0xF0u, 0x7Fu, 0x04u, 0x54u, 0x54u,\r
- 0x59u, 0x78u, 0x01u, 0xF0u, 0xFDu, 0x01u, 0x59u, 0x70u,\r
- 0x19u, 0x79u, 0x5Bu, 0x78u, 0x11u, 0xF0u, 0x80u, 0x0Fu,\r
- 0x0Cu, 0x49u, 0x05u, 0xD0u, 0x01u, 0x2Bu, 0x01u, 0xD1u,\r
- 0x50u, 0x54u, 0x07u, 0xE0u, 0x0Du, 0x20u, 0x04u, 0xE0u,\r
- 0x01u, 0x2Bu, 0x01u, 0xD1u, 0x08u, 0x20u, 0x00u, 0xE0u,\r
- 0x09u, 0x20u, 0x50u, 0x54u, 0xBDu, 0xE8u, 0x10u, 0x40u,\r
- 0xFFu, 0xF7u, 0x30u, 0xBBu, 0x00u, 0x20u, 0x10u, 0xBDu,\r
- 0x04u, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x0Cu, 0x60u, 0x00u, 0x40u, 0x0Eu, 0x60u, 0x00u, 0x40u,\r
- 0x10u, 0xB5u, 0x0Cu, 0x4Bu, 0x0Cu, 0x48u, 0x1Cu, 0x78u,\r
- 0x01u, 0x78u, 0x4Au, 0x1Eu, 0xD0u, 0xB2u, 0xFFu, 0xF7u,\r
- 0x27u, 0xFEu, 0x43u, 0x68u, 0x18u, 0x79u, 0xA0u, 0x42u,\r
- 0x09u, 0xD9u, 0x44u, 0xB9u, 0x07u, 0x4Bu, 0x08u, 0x4Au,\r
- 0x19u, 0x78u, 0x08u, 0x48u, 0x11u, 0x70u, 0x01u, 0x78u,\r
- 0x01u, 0x20u, 0x19u, 0x70u, 0x10u, 0xBDu, 0x00u, 0x20u,\r
+ 0xF0u, 0xD1u, 0x18u, 0xB1u, 0x46u, 0x4Au, 0x13u, 0x70u,\r
+ 0x46u, 0x4Au, 0x13u, 0x70u, 0x46u, 0x4Bu, 0x1Au, 0x78u,\r
+ 0x00u, 0x2Au, 0x00u, 0xF0u, 0x81u, 0x80u, 0x18u, 0x78u,\r
+ 0x01u, 0x38u, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x3Au, 0xFFu,\r
+ 0x43u, 0x68u, 0x01u, 0x7Au, 0xDBu, 0x79u, 0xC9u, 0x00u,\r
+ 0x13u, 0xF0u, 0x40u, 0x0Fu, 0x3Fu, 0x4Bu, 0x1Au, 0x78u,\r
+ 0x14u, 0xBFu, 0x42u, 0xF0u, 0x01u, 0x02u, 0x02u, 0xF0u,\r
+ 0xFEu, 0x02u, 0x1Au, 0x70u, 0x01u, 0x22u, 0xC3u, 0x68u,\r
+ 0x08u, 0x33u, 0x03u, 0xEBu, 0x01u, 0x0Eu, 0x73u, 0x45u,\r
+ 0x3Du, 0xD0u, 0x13u, 0xF8u, 0x06u, 0x5Cu, 0x05u, 0xF0u,\r
+ 0x7Fu, 0x06u, 0xB2u, 0x42u, 0x35u, 0xD1u, 0x0Cu, 0x26u,\r
+ 0x06u, 0xFBu, 0x02u, 0x46u, 0xB6u, 0xF8u, 0x08u, 0xC0u,\r
+ 0x33u, 0xF8u, 0x04u, 0x7Cu, 0x1Fu, 0xFAu, 0x8Cu, 0xFCu,\r
+ 0xBCu, 0x45u, 0x38u, 0xBFu, 0x37u, 0x81u, 0x13u, 0xF8u,\r
+ 0x08u, 0x6Cu, 0x2Bu, 0x4Fu, 0xBEu, 0x5Du, 0x13u, 0xF8u,\r
+ 0x07u, 0x7Cu, 0xB7u, 0x42u, 0x21u, 0xD1u, 0x13u, 0xF8u,\r
+ 0x05u, 0x6Cu, 0x15u, 0xF0u, 0x80u, 0x0Fu, 0x4Fu, 0xF0u,\r
+ 0x0Cu, 0x05u, 0x06u, 0xF0u, 0x03u, 0x06u, 0x05u, 0xFBu,\r
+ 0x02u, 0x45u, 0x06u, 0xD0u, 0x01u, 0x27u, 0xBEu, 0x42u,\r
+ 0x6Fu, 0x70u, 0x14u, 0xBFu, 0x0Du, 0x26u, 0x07u, 0x26u,\r
+ 0x05u, 0xE0u, 0x00u, 0x27u, 0x01u, 0x2Eu, 0x6Fu, 0x70u,\r
+ 0x14u, 0xBFu, 0x09u, 0x26u, 0x05u, 0x26u, 0x6Eu, 0x71u,\r
+ 0x0Cu, 0x25u, 0x55u, 0x43u, 0x13u, 0xF8u, 0x06u, 0x7Cu,\r
+ 0x66u, 0x19u, 0x37u, 0x71u, 0x13u, 0xF8u, 0x05u, 0x6Cu,\r
+ 0x66u, 0x55u, 0x08u, 0x33u, 0xBFu, 0xE7u, 0x01u, 0x32u,\r
+ 0x09u, 0x2Au, 0xB8u, 0xD1u, 0xC3u, 0x68u, 0x03u, 0xF1u,\r
+ 0x08u, 0x02u, 0x11u, 0x44u, 0x08u, 0x33u, 0x8Bu, 0x42u,\r
+ 0x0Au, 0xD0u, 0x13u, 0xF8u, 0x06u, 0x2Cu, 0x0Cu, 0x25u,\r
+ 0x02u, 0xF0u, 0x7Fu, 0x02u, 0x05u, 0xFBu, 0x02u, 0x42u,\r
+ 0x13u, 0xF8u, 0x08u, 0x0Cu, 0x90u, 0x72u, 0xF1u, 0xE7u,\r
+ 0xFFu, 0xF7u, 0x66u, 0xFFu, 0x0Eu, 0x4Bu, 0x00u, 0x22u,\r
+ 0x18u, 0x60u, 0x01u, 0x23u, 0x0Cu, 0x21u, 0x01u, 0xFBu,\r
+ 0x03u, 0x41u, 0xCAu, 0x80u, 0x09u, 0x89u, 0x01u, 0x33u,\r
+ 0x0Au, 0x44u, 0x09u, 0x2Bu, 0x92u, 0xB2u, 0xF5u, 0xD1u,\r
+ 0xBDu, 0xE8u, 0xF8u, 0x40u, 0xFFu, 0xF7u, 0x7Eu, 0xBEu,\r
+ 0xF8u, 0xBDu, 0x00u, 0xBFu, 0x70u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x56u, 0xC1u, 0xFFu, 0x1Fu, 0xDCu, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x67u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x6Cu, 0xC1u, 0xFFu, 0x1Fu, 0x11u, 0x4Bu, 0x19u, 0x78u,\r
+ 0x01u, 0xF0u, 0x7Fu, 0x01u, 0x4Au, 0x1Eu, 0xD2u, 0xB2u,\r
+ 0x07u, 0x2Au, 0x19u, 0xD8u, 0x0Eu, 0x4Bu, 0x0Cu, 0x20u,\r
+ 0x00u, 0xFBu, 0x01u, 0x33u, 0x99u, 0x78u, 0x12u, 0x01u,\r
+ 0x41u, 0xF0u, 0x01u, 0x01u, 0x99u, 0x70u, 0x00u, 0x21u,\r
+ 0xD9u, 0x70u, 0x59u, 0x78u, 0xD2u, 0xB2u, 0x41u, 0xF0u,\r
+ 0x02u, 0x01u, 0x59u, 0x70u, 0x1Bu, 0x79u, 0x13u, 0xF0u,\r
+ 0x80u, 0x0Fu, 0x06u, 0x4Bu, 0x14u, 0xBFu, 0x8Du, 0x21u,\r
+ 0x89u, 0x21u, 0xD1u, 0x54u, 0xFFu, 0xF7u, 0x98u, 0xBBu,\r
+ 0x00u, 0x20u, 0x70u, 0x47u, 0x04u, 0x60u, 0x00u, 0x40u,\r
+ 0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x0Eu, 0x60u, 0x00u, 0x40u,\r
+ 0x10u, 0xB5u, 0x1Au, 0x4Bu, 0x1Bu, 0x78u, 0x03u, 0xF0u,\r
+ 0x7Fu, 0x03u, 0x5Au, 0x1Eu, 0xD2u, 0xB2u, 0x07u, 0x2Au,\r
+ 0x29u, 0xD8u, 0x17u, 0x49u, 0x0Cu, 0x20u, 0x00u, 0xFBu,\r
+ 0x03u, 0x13u, 0x99u, 0x78u, 0x12u, 0x01u, 0x01u, 0xF0u,\r
+ 0xFEu, 0x01u, 0x99u, 0x70u, 0x00u, 0x21u, 0xD9u, 0x70u,\r
+ 0x12u, 0x49u, 0xD2u, 0xB2u, 0x54u, 0x5Cu, 0x04u, 0xF0u,\r
+ 0x7Fu, 0x04u, 0x54u, 0x54u, 0x59u, 0x78u, 0x01u, 0xF0u,\r
+ 0xFDu, 0x01u, 0x59u, 0x70u, 0x19u, 0x79u, 0x5Bu, 0x78u,\r
+ 0x11u, 0xF0u, 0x80u, 0x0Fu, 0x0Cu, 0x49u, 0x05u, 0xD0u,\r
+ 0x01u, 0x2Bu, 0x01u, 0xD1u, 0x50u, 0x54u, 0x06u, 0xE0u,\r
+ 0x0Du, 0x23u, 0x03u, 0xE0u, 0x01u, 0x2Bu, 0x0Cu, 0xBFu,\r
+ 0x08u, 0x23u, 0x09u, 0x23u, 0x53u, 0x54u, 0xBDu, 0xE8u,\r
+ 0x10u, 0x40u, 0xFFu, 0xF7u, 0x5Du, 0xBBu, 0x00u, 0x20u,\r
0x10u, 0xBDu, 0x00u, 0xBFu, 0x04u, 0x60u, 0x00u, 0x40u,\r
- 0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x5Eu, 0xC1u, 0xFFu, 0x1Fu,\r
- 0xE4u, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x60u, 0x00u, 0x40u,\r
- 0x10u, 0xB5u, 0x7Cu, 0x4Bu, 0x00u, 0x22u, 0x1Au, 0x80u,\r
- 0x7Bu, 0x4Au, 0x7Cu, 0x48u, 0x11u, 0x78u, 0x11u, 0xF0u,\r
- 0x80u, 0x0Fu, 0x00u, 0xF0u, 0x8Au, 0x80u, 0x01u, 0x78u,\r
- 0x0Au, 0x29u, 0x00u, 0xF2u, 0x22u, 0x81u, 0xDFu, 0xE8u,\r
- 0x11u, 0xF0u, 0x58u, 0x00u, 0x20u, 0x01u, 0x20u, 0x01u,\r
- 0x20u, 0x01u, 0x20u, 0x01u, 0x20u, 0x01u, 0x0Bu, 0x00u,\r
- 0x20u, 0x01u, 0x78u, 0x00u, 0x20u, 0x01u, 0x7Cu, 0x00u,\r
- 0x71u, 0x4Bu, 0x19u, 0x78u, 0x01u, 0x29u, 0x0Au, 0xD1u,\r
- 0x70u, 0x48u, 0x71u, 0x49u, 0x02u, 0x78u, 0x01u, 0xEBu,\r
- 0xC2u, 0x03u, 0x58u, 0x68u, 0x12u, 0x23u, 0x42u, 0x68u,\r
- 0x68u, 0x48u, 0x42u, 0x60u, 0x0Fu, 0xE0u, 0x18u, 0x78u,\r
- 0x02u, 0x28u, 0x11u, 0xD1u, 0x6Bu, 0x4Bu, 0x18u, 0x78u,\r
- 0xFFu, 0xF7u, 0xDAu, 0xFDu, 0x42u, 0x68u, 0x63u, 0x48u,\r
- 0x42u, 0x60u, 0x41u, 0x68u, 0xCBu, 0x78u, 0x42u, 0x68u,\r
- 0x91u, 0x78u, 0x41u, 0xEAu, 0x03u, 0x23u, 0x03u, 0x80u,\r
- 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x0Cu, 0xBCu,\r
- 0x1Au, 0x78u, 0x03u, 0x2Au, 0x21u, 0xD1u, 0x62u, 0x4Bu,\r
- 0x00u, 0x22u, 0x60u, 0x49u, 0x08u, 0x78u, 0x90u, 0x42u,\r
- 0x0Au, 0xD8u, 0x0Au, 0x78u, 0x82u, 0xB1u, 0x5Du, 0x49u,\r
- 0x5Eu, 0x48u, 0x09u, 0x78u, 0x5Eu, 0x4Au, 0x00u, 0x7Cu,\r
- 0x88u, 0x42u, 0x08u, 0xBFu, 0x13u, 0x46u, 0x07u, 0xE0u,\r
- 0x18u, 0x78u, 0x00u, 0x28u, 0xF1u, 0xD0u, 0x19u, 0x78u,\r
- 0x50u, 0x1Cu, 0x5Bu, 0x18u, 0xC2u, 0xB2u, 0xE8u, 0xE7u,\r
- 0x19u, 0x78u, 0x00u, 0x29u, 0x00u, 0xF0u, 0xD1u, 0x80u,\r
- 0x18u, 0x78u, 0x4Cu, 0x4Au, 0x10u, 0x80u, 0x53u, 0x60u,\r
- 0xD6u, 0xE7u, 0xBDu, 0xE8u, 0x10u, 0x40u, 0x00u, 0xF0u,\r
- 0xDDu, 0xB8u, 0x11u, 0x78u, 0x11u, 0xF0u, 0x03u, 0x02u,\r
- 0x11u, 0xD0u, 0x02u, 0x2Au, 0x40u, 0xF0u, 0xC1u, 0x80u,\r
- 0x44u, 0x49u, 0x4Eu, 0x4Bu, 0x0Au, 0x80u, 0x18u, 0x78u,\r
- 0x4Du, 0x4Au, 0x00u, 0xF0u, 0x7Fu, 0x03u, 0x0Cu, 0x20u,\r
- 0x00u, 0xFBu, 0x03u, 0x23u, 0x98u, 0x78u, 0x4Bu, 0x4Bu,\r
- 0x00u, 0x22u, 0x18u, 0x70u, 0x06u, 0xE0u, 0x3Du, 0x49u,\r
- 0x02u, 0x23u, 0x49u, 0x48u, 0x0Bu, 0x80u, 0x00u, 0x78u,\r
- 0x46u, 0x4Bu, 0x18u, 0x70u, 0x5Au, 0x70u, 0x4Bu, 0x60u,\r
- 0xB2u, 0xE7u, 0x01u, 0x22u, 0x1Au, 0x80u, 0x45u, 0x48u,\r
- 0x05u, 0xE0u, 0x01u, 0x22u, 0x3Fu, 0x48u, 0x1Au, 0x80u,\r
- 0x02u, 0x78u, 0x43u, 0x49u, 0x88u, 0x18u, 0x58u, 0x60u,\r
- 0xA6u, 0xE7u, 0x03u, 0x78u, 0x58u, 0x1Eu, 0x0Au, 0x28u,\r
- 0x00u, 0xF2u, 0x97u, 0x80u, 0xDFu, 0xE8u, 0x10u, 0xF0u,\r
- 0x2Bu, 0x00u, 0x95u, 0x00u, 0x44u, 0x00u, 0x95u, 0x00u,\r
- 0x0Bu, 0x00u, 0x95u, 0x00u, 0x95u, 0x00u, 0x95u, 0x00u,\r
- 0x0Fu, 0x00u, 0x95u, 0x00u, 0x19u, 0x00u, 0x2Fu, 0x4Bu,\r
- 0x38u, 0x49u, 0x18u, 0x78u, 0x4Cu, 0xE0u, 0x2Du, 0x4Bu,\r
- 0x34u, 0x4Au, 0x18u, 0x78u, 0x36u, 0x49u, 0x10u, 0x70u,\r
- 0x01u, 0x20u, 0x08u, 0x70u, 0xFFu, 0xF7u, 0x0Au, 0xFEu,\r
- 0x77u, 0xE0u, 0xFFu, 0xF7u, 0x25u, 0xFFu, 0x00u, 0x28u,\r
- 0x77u, 0xD0u, 0x2Au, 0x4Cu, 0x31u, 0x4Au, 0x24u, 0x78u,\r
- 0x2Fu, 0x4Bu, 0x01u, 0x21u, 0x14u, 0x70u, 0x19u, 0x70u,\r
- 0xFFu, 0xF7u, 0x58u, 0xFDu, 0x2Au, 0x48u, 0x2Eu, 0x49u,\r
- 0x02u, 0x5Du, 0x0Au, 0x55u, 0x65u, 0xE0u, 0x12u, 0x78u,\r
- 0x02u, 0xF0u, 0x03u, 0x01u, 0x01u, 0x29u, 0x55u, 0xD0u,\r
- 0x09u, 0xD3u, 0x02u, 0x29u, 0x61u, 0xD1u, 0x1Bu, 0x4Bu,\r
- 0x18u, 0x78u, 0x00u, 0x28u, 0x5Du, 0xD1u, 0xBDu, 0xE8u,\r
- 0x10u, 0x40u, 0xFFu, 0xF7u, 0xC7u, 0xBEu, 0x17u, 0x4Au,\r
- 0x11u, 0x78u, 0x01u, 0x29u, 0x55u, 0xD1u, 0x1Cu, 0x49u,\r
- 0x0Bu, 0x78u, 0x03u, 0xF0u, 0xFDu, 0x00u, 0x17u, 0xE0u,\r
- 0x10u, 0x78u, 0x00u, 0xF0u, 0x03u, 0x02u, 0x01u, 0x2Au,\r
- 0x3Cu, 0xD0u, 0x09u, 0xD3u, 0x02u, 0x2Au, 0x48u, 0xD1u,\r
- 0x0Eu, 0x49u, 0x0Bu, 0x78u, 0x00u, 0x2Bu, 0x44u, 0xD1u,\r
- 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x82u, 0xBEu,\r
- 0x0Au, 0x48u, 0x02u, 0x78u, 0x01u, 0x2Au, 0x3Cu, 0xD1u,\r
- 0x0Fu, 0x49u, 0x0Bu, 0x78u, 0x43u, 0xF0u, 0x02u, 0x00u,\r
- 0x08u, 0x70u, 0x32u, 0xE0u, 0x60u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x0Cu, 0x60u, 0x00u, 0x40u,\r
+ 0x0Eu, 0x60u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x0Du, 0x4Bu,\r
+ 0x1Cu, 0x78u, 0x0Du, 0x4Bu, 0xE4u, 0xB2u, 0x18u, 0x78u,\r
+ 0x01u, 0x38u, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x3Eu, 0xFEu,\r
+ 0x43u, 0x68u, 0x1Bu, 0x79u, 0xA3u, 0x42u, 0x0Bu, 0xD9u,\r
+ 0x54u, 0xB9u, 0x08u, 0x4Bu, 0x08u, 0x4Au, 0x19u, 0x78u,\r
+ 0x01u, 0x20u, 0xC9u, 0xB2u, 0x11u, 0x70u, 0x07u, 0x4Au,\r
+ 0x12u, 0x78u, 0xD2u, 0xB2u, 0x1Au, 0x70u, 0x10u, 0xBDu,\r
+ 0x00u, 0x20u, 0x10u, 0xBDu, 0x04u, 0x60u, 0x00u, 0x40u,\r
+ 0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x56u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0xDCu, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x60u, 0x00u, 0x40u,\r
+ 0x38u, 0xB5u, 0x8Cu, 0x4Cu, 0x00u, 0x23u, 0x23u, 0x80u,\r
+ 0x8Bu, 0x4Bu, 0x1Au, 0x78u, 0x12u, 0xF0u, 0x80u, 0x0Fu,\r
+ 0x8Au, 0x4Au, 0x12u, 0x78u, 0x00u, 0xF0u, 0x88u, 0x80u,\r
+ 0x0Au, 0x2Au, 0x00u, 0xF2u, 0x08u, 0x81u, 0xDFu, 0xE8u,\r
+ 0x12u, 0xF0u, 0x58u, 0x00u, 0x06u, 0x01u, 0x06u, 0x01u,\r
+ 0x06u, 0x01u, 0x06u, 0x01u, 0x06u, 0x01u, 0x0Bu, 0x00u,\r
+ 0x06u, 0x01u, 0x78u, 0x00u, 0x06u, 0x01u, 0x7Cu, 0x00u,\r
+ 0x81u, 0x4Bu, 0x1Au, 0x78u, 0x01u, 0x2Au, 0x09u, 0xD1u,\r
+ 0x80u, 0x4Bu, 0x1Au, 0x78u, 0x80u, 0x4Bu, 0x03u, 0xEBu,\r
+ 0xC2u, 0x03u, 0x5Bu, 0x68u, 0x5Bu, 0x68u, 0x63u, 0x60u,\r
+ 0x12u, 0x23u, 0x11u, 0xE0u, 0x1Au, 0x78u, 0x02u, 0x2Au,\r
+ 0x13u, 0xD1u, 0x7Cu, 0x4Bu, 0x18u, 0x78u, 0xFFu, 0xF7u,\r
+ 0xF1u, 0xFDu, 0x00u, 0x28u, 0x00u, 0xF0u, 0xE3u, 0x80u,\r
+ 0x43u, 0x68u, 0x63u, 0x60u, 0x63u, 0x68u, 0xDAu, 0x78u,\r
+ 0x63u, 0x68u, 0x9Bu, 0x78u, 0x43u, 0xEAu, 0x02u, 0x23u,\r
+ 0x23u, 0x80u, 0xBDu, 0xE8u, 0x38u, 0x40u, 0xFFu, 0xF7u,\r
+ 0x0Bu, 0xBCu, 0x1Bu, 0x78u, 0x03u, 0x2Bu, 0x20u, 0xD1u,\r
+ 0x71u, 0x4Bu, 0x00u, 0x22u, 0x6Fu, 0x49u, 0xD0u, 0xB2u,\r
+ 0x0Du, 0x78u, 0x85u, 0x42u, 0x0Au, 0xD8u, 0x0Au, 0x78u,\r
+ 0x7Au, 0xB1u, 0x6Cu, 0x4Au, 0x6Du, 0x48u, 0x11u, 0x78u,\r
+ 0x00u, 0x7Cu, 0x6Du, 0x4Au, 0x88u, 0x42u, 0x08u, 0xBFu,\r
+ 0x13u, 0x46u, 0x06u, 0xE0u, 0x18u, 0x78u, 0x01u, 0x32u,\r
+ 0x00u, 0x28u, 0xF0u, 0xD0u, 0x19u, 0x78u, 0x0Bu, 0x44u,\r
+ 0xE8u, 0xE7u, 0x1Au, 0x78u, 0x00u, 0x2Au, 0x00u, 0xF0u,\r
+ 0xB6u, 0x80u, 0x1Au, 0x78u, 0xD2u, 0xB2u, 0x22u, 0x80u,\r
+ 0x19u, 0xE0u, 0xBDu, 0xE8u, 0x38u, 0x40u, 0x00u, 0xF0u,\r
+ 0xE7u, 0xB8u, 0x1Au, 0x78u, 0x12u, 0xF0u, 0x03u, 0x02u,\r
+ 0x13u, 0xD0u, 0x02u, 0x2Au, 0x40u, 0xF0u, 0xA7u, 0x80u,\r
+ 0x5Eu, 0x4Bu, 0x22u, 0x80u, 0x1Bu, 0x78u, 0x5Eu, 0x4Au,\r
+ 0x03u, 0xF0u, 0x7Fu, 0x03u, 0x0Cu, 0x21u, 0x01u, 0xFBu,\r
+ 0x03u, 0x23u, 0x9Au, 0x78u, 0x5Bu, 0x4Bu, 0xD2u, 0xB2u,\r
+ 0x1Au, 0x70u, 0x00u, 0x22u, 0x5Au, 0x70u, 0x63u, 0x60u,\r
+ 0xBBu, 0xE7u, 0x02u, 0x23u, 0x23u, 0x80u, 0x58u, 0x4Bu,\r
+ 0x19u, 0x78u, 0x56u, 0x4Bu, 0xC9u, 0xB2u, 0x19u, 0x70u,\r
+ 0xF4u, 0xE7u, 0x01u, 0x23u, 0x23u, 0x80u, 0x55u, 0x4Bu,\r
+ 0xF1u, 0xE7u, 0x01u, 0x23u, 0x23u, 0x80u, 0x4Fu, 0x4Bu,\r
+ 0x53u, 0x4Au, 0x1Bu, 0x78u, 0x13u, 0x44u, 0xEAu, 0xE7u,\r
+ 0x01u, 0x3Au, 0x0Au, 0x2Au, 0x7Fu, 0xD8u, 0xDFu, 0xE8u,\r
+ 0x02u, 0xF0u, 0x36u, 0x7Eu, 0x52u, 0x7Eu, 0x06u, 0x7Eu,\r
+ 0x7Eu, 0x7Eu, 0x0Bu, 0x7Eu, 0x22u, 0x00u, 0x43u, 0x4Bu,\r
+ 0x1Au, 0x78u, 0x4Cu, 0x4Bu, 0xD2u, 0xB2u, 0x60u, 0xE0u,\r
+ 0x40u, 0x4Bu, 0x1Bu, 0x78u, 0x03u, 0xF0u, 0xFFu, 0x04u,\r
+ 0x53u, 0xB9u, 0x46u, 0x4Bu, 0x1Au, 0x78u, 0x94u, 0x42u,\r
+ 0x65u, 0xD0u, 0x1Cu, 0x70u, 0x46u, 0x4Bu, 0x01u, 0x20u,\r
+ 0x18u, 0x70u, 0xFFu, 0xF7u, 0x15u, 0xFEu, 0x5Eu, 0xE0u,\r
+ 0x60u, 0x1Eu, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x6Au, 0xFDu,\r
+ 0x00u, 0x28u, 0xEEu, 0xD1u, 0x5Bu, 0xE0u, 0xFFu, 0xF7u,\r
+ 0x1Du, 0xFFu, 0x00u, 0x28u, 0x57u, 0xD0u, 0x37u, 0x4Bu,\r
+ 0x01u, 0x22u, 0x1Cu, 0x78u, 0x3Du, 0x4Bu, 0xE4u, 0xB2u,\r
+ 0x1Cu, 0x70u, 0x3Bu, 0x4Bu, 0x1Au, 0x70u, 0xFFu, 0xF7u,\r
+ 0x6Du, 0xFDu, 0x37u, 0x4Bu, 0x1Au, 0x5Du, 0x3Au, 0x4Bu,\r
+ 0xD2u, 0xB2u, 0x1Au, 0x55u, 0x43u, 0xE0u, 0x1Bu, 0x78u,\r
+ 0x03u, 0xF0u, 0x03u, 0x03u, 0x01u, 0x2Bu, 0x32u, 0xD0u,\r
+ 0x0Cu, 0xD3u, 0x02u, 0x2Bu, 0x3Fu, 0xD1u, 0x03u, 0xF1u,\r
+ 0x80u, 0x43u, 0x03u, 0xF5u, 0xC0u, 0x43u, 0x1Bu, 0x78u,\r
+ 0x00u, 0x2Bu, 0x38u, 0xD1u, 0xBDu, 0xE8u, 0x38u, 0x40u,\r
+ 0xFFu, 0xF7u, 0xBAu, 0xBEu, 0x21u, 0x4Bu, 0x1Bu, 0x78u,\r
+ 0x01u, 0x2Bu, 0x30u, 0xD1u, 0x26u, 0x4Bu, 0x1Au, 0x78u,\r
+ 0x02u, 0xF0u, 0xFDu, 0x02u, 0x19u, 0xE0u, 0x1Bu, 0x78u,\r
+ 0x03u, 0xF0u, 0x03u, 0x03u, 0x01u, 0x2Bu, 0x16u, 0xD0u,\r
+ 0x0Bu, 0xD3u, 0x02u, 0x2Bu, 0x23u, 0xD1u, 0x03u, 0xF1u,\r
+ 0x80u, 0x43u, 0x03u, 0xF5u, 0xC0u, 0x43u, 0x1Bu, 0x78u,\r
+ 0xEBu, 0xB9u, 0xBDu, 0xE8u, 0x38u, 0x40u, 0xFFu, 0xF7u,\r
+ 0x75u, 0xBEu, 0x14u, 0x4Bu, 0x1Bu, 0x78u, 0x01u, 0x2Bu,\r
+ 0x15u, 0xD1u, 0x19u, 0x4Bu, 0x1Au, 0x78u, 0x42u, 0xF0u,\r
+ 0x02u, 0x02u, 0x1Au, 0x70u, 0x0Bu, 0xE0u, 0x13u, 0x4Bu,\r
+ 0x1Au, 0x78u, 0x62u, 0xB9u, 0x1Bu, 0x78u, 0x1Bu, 0x4Au,\r
+ 0x0Cu, 0x48u, 0xDBu, 0xB2u, 0xD1u, 0x5Cu, 0x00u, 0x78u,\r
+ 0x21u, 0xEAu, 0x00u, 0x01u, 0xD1u, 0x54u, 0xBDu, 0xE8u,\r
+ 0x38u, 0x40u, 0xFFu, 0xF7u, 0x15u, 0xBAu, 0x00u, 0x20u,\r
+ 0x38u, 0xBDu, 0x00u, 0xBFu, 0x58u, 0xC1u, 0xFFu, 0x1Fu,\r
0x00u, 0x60u, 0x00u, 0x40u, 0x01u, 0x60u, 0x00u, 0x40u,\r
- 0x03u, 0x60u, 0x00u, 0x40u, 0x6Cu, 0xC1u, 0xFFu, 0x1Fu,\r
- 0xD4u, 0x20u, 0x00u, 0x00u, 0x02u, 0x60u, 0x00u, 0x40u,\r
- 0x9Au, 0x21u, 0x00u, 0x00u, 0x16u, 0x22u, 0x00u, 0x00u,\r
- 0x90u, 0x21u, 0x00u, 0x00u, 0x04u, 0x60u, 0x00u, 0x40u,\r
- 0x78u, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x6Fu, 0xC1u, 0xFFu, 0x1Fu, 0x71u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x6Du, 0xC1u, 0xFFu, 0x1Fu,\r
- 0xE4u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0x48u, 0x02u, 0x78u,\r
- 0x5Au, 0xB9u, 0x03u, 0x78u, 0x07u, 0x4Au, 0x08u, 0x48u,\r
- 0xD1u, 0x5Cu, 0x00u, 0x78u, 0x21u, 0xEAu, 0x00u, 0x01u,\r
- 0xD1u, 0x54u, 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u,\r
- 0xD1u, 0xB9u, 0x00u, 0x20u, 0x10u, 0xBDu, 0x00u, 0xBFu,\r
- 0x04u, 0x60u, 0x00u, 0x40u, 0x73u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x02u, 0x60u, 0x00u, 0x40u, 0x03u, 0x4Bu, 0x18u, 0x78u,\r
- 0x01u, 0x06u, 0x44u, 0xBFu, 0x02u, 0x49u, 0x09u, 0x78u,\r
- 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x60u, 0x00u, 0x40u,\r
- 0x01u, 0x60u, 0x00u, 0x40u, 0x0Fu, 0x4Bu, 0x18u, 0x78u,\r
- 0x00u, 0xF0u, 0x03u, 0x01u, 0x01u, 0x29u, 0x0Cu, 0xD0u,\r
- 0x02u, 0x29u, 0x0Du, 0xD1u, 0x0Cu, 0x4Au, 0x0Cu, 0x21u,\r
- 0x10u, 0x78u, 0x0Cu, 0x4Au, 0x00u, 0xF0u, 0x7Fu, 0x03u,\r
- 0x01u, 0xFBu, 0x03u, 0x20u, 0x08u, 0x30u, 0x83u, 0x78u,\r
- 0x03u, 0xE0u, 0x07u, 0x4Bu, 0x1Bu, 0x78u, 0x00u, 0xE0u,\r
- 0x00u, 0x23u, 0x07u, 0x49u, 0x0Au, 0x68u, 0xD0u, 0x5Cu,\r
- 0x03u, 0x28u, 0x01u, 0xD1u, 0xFFu, 0xF7u, 0xC6u, 0xBBu,\r
- 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x60u, 0x00u, 0x40u,\r
- 0x04u, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,\r
- 0x74u, 0xC1u, 0xFFu, 0x1Fu, 0x38u, 0xB5u, 0x0Eu, 0x4Du,\r
- 0x0Eu, 0x4Bu, 0x00u, 0x24u, 0xE8u, 0x1Au, 0x85u, 0x10u,\r
- 0xACu, 0x42u, 0x05u, 0xD0u, 0x0Bu, 0x49u, 0x51u, 0xF8u,\r
- 0x24u, 0x20u, 0x90u, 0x47u, 0x01u, 0x34u, 0xF7u, 0xE7u,\r
- 0x00u, 0xF0u, 0x3Au, 0xF9u, 0x08u, 0x49u, 0x09u, 0x4Au,\r
- 0x54u, 0x1Au, 0xA5u, 0x10u, 0x00u, 0x24u, 0xACu, 0x42u,\r
- 0x05u, 0xD0u, 0x05u, 0x4Bu, 0x53u, 0xF8u, 0x24u, 0x00u,\r
- 0x80u, 0x47u, 0x01u, 0x34u, 0xF7u, 0xE7u, 0x38u, 0xBDu,\r
- 0x34u, 0x22u, 0x00u, 0x00u, 0x34u, 0x22u, 0x00u, 0x00u,\r
- 0x34u, 0x22u, 0x00u, 0x00u, 0x3Cu, 0x22u, 0x00u, 0x00u,\r
+ 0x03u, 0x60u, 0x00u, 0x40u, 0x64u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x8Cu, 0x21u, 0x00u, 0x00u, 0x02u, 0x60u, 0x00u, 0x40u,\r
+ 0x52u, 0x22u, 0x00u, 0x00u, 0xCEu, 0x22u, 0x00u, 0x00u,\r
+ 0x48u, 0x22u, 0x00u, 0x00u, 0x04u, 0x60u, 0x00u, 0x40u,\r
+ 0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x4Eu, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x67u, 0xC1u, 0xFFu, 0x1Fu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x56u, 0xC1u, 0xFFu, 0x1Fu, 0x54u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x68u, 0xC1u, 0xFFu, 0x1Fu, 0x65u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0xDCu, 0xC1u, 0xFFu, 0x1Fu, 0x6Bu, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x03u, 0x4Bu, 0x00u, 0x20u, 0x1Bu, 0x78u, 0x1Bu, 0x06u,\r
+ 0x44u, 0xBFu, 0x02u, 0x4Bu, 0x1Bu, 0x78u, 0x70u, 0x47u,\r
+ 0x00u, 0x60u, 0x00u, 0x40u, 0x01u, 0x60u, 0x00u, 0x40u,\r
+ 0x10u, 0x4Bu, 0x1Bu, 0x78u, 0x03u, 0xF0u, 0x03u, 0x03u,\r
+ 0x01u, 0x2Bu, 0x0Cu, 0xD0u, 0x02u, 0x2Bu, 0x0Eu, 0xD1u,\r
+ 0x0Du, 0x4Bu, 0x0Eu, 0x4Au, 0x1Bu, 0x78u, 0x0Cu, 0x21u,\r
+ 0x03u, 0xF0u, 0x7Fu, 0x03u, 0x01u, 0xFBu, 0x03u, 0x23u,\r
+ 0x08u, 0x33u, 0x9Bu, 0x78u, 0x01u, 0xE0u, 0x08u, 0x4Bu,\r
+ 0x1Bu, 0x78u, 0xDBu, 0xB2u, 0x00u, 0xE0u, 0x00u, 0x23u,\r
+ 0x07u, 0x4Au, 0x12u, 0x68u, 0xD3u, 0x5Cu, 0x03u, 0x2Bu,\r
+ 0x01u, 0xD1u, 0xFFu, 0xF7u, 0xE7u, 0xBBu, 0x00u, 0x20u,\r
+ 0x70u, 0x47u, 0x00u, 0xBFu, 0x00u, 0x60u, 0x00u, 0x40u,\r
+ 0x04u, 0x60u, 0x00u, 0x40u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x6Cu, 0xC1u, 0xFFu, 0x1Fu, 0x70u, 0xB5u, 0x0Eu, 0x4Bu,\r
+ 0x0Eu, 0x4Du, 0x00u, 0x24u, 0xEDu, 0x1Au, 0xADu, 0x10u,\r
+ 0x1Eu, 0x46u, 0xACu, 0x42u, 0x04u, 0xD0u, 0x56u, 0xF8u,\r
+ 0x24u, 0x20u, 0x90u, 0x47u, 0x01u, 0x34u, 0xF8u, 0xE7u,\r
+ 0x00u, 0xF0u, 0x3Au, 0xF9u, 0x08u, 0x4Du, 0x09u, 0x4Bu,\r
+ 0x00u, 0x24u, 0xEDu, 0x1Au, 0xADu, 0x10u, 0x1Eu, 0x46u,\r
+ 0xACu, 0x42u, 0x04u, 0xD0u, 0x56u, 0xF8u, 0x24u, 0x20u,\r
+ 0x90u, 0x47u, 0x01u, 0x34u, 0xF8u, 0xE7u, 0x70u, 0xBDu,\r
+ 0xECu, 0x22u, 0x00u, 0x00u, 0xECu, 0x22u, 0x00u, 0x00u,\r
+ 0xF4u, 0x22u, 0x00u, 0x00u, 0xECu, 0x22u, 0x00u, 0x00u,\r
0x10u, 0xB5u, 0x00u, 0x23u, 0x93u, 0x42u, 0x03u, 0xD0u,\r
0xCCu, 0x5Cu, 0xC4u, 0x54u, 0x01u, 0x33u, 0xF9u, 0xE7u,\r
- 0x10u, 0xBDu, 0x82u, 0x18u, 0x03u, 0x46u, 0x93u, 0x42u,\r
+ 0x10u, 0xBDu, 0x02u, 0x44u, 0x03u, 0x46u, 0x93u, 0x42u,\r
0x02u, 0xD0u, 0x03u, 0xF8u, 0x01u, 0x1Bu, 0xFAu, 0xE7u,\r
- 0x70u, 0x47u, 0x00u, 0x00u, 0x80u, 0x22u, 0x00u, 0x00u,\r
- 0x40u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x70u, 0x47u, 0x00u, 0x00u, 0x38u, 0x23u, 0x00u, 0x00u,\r
+ 0xF2u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x10u, 0x51u, 0x00u, 0x40u, 0x20u, 0x00u, 0x50u, 0x51u,\r
0x00u, 0x40u, 0x10u, 0x00u, 0xC0u, 0x51u, 0x00u, 0x40u,\r
0x10u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u, 0x00u, 0x10u,\r
0x00u, 0x00u, 0x00u, 0xFCu, 0xFCu, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x0Fu, 0x0Fu, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x69u, 0x30u, 0x13u, 0x2Eu,\r
- 0x00u, 0x14u, 0x01u, 0x01u, 0x01u, 0x00u, 0x00u, 0x00u,\r
- 0xDCu, 0x20u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,\r
- 0x16u, 0x22u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,\r
- 0xECu, 0x20u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,\r
- 0xEDu, 0x21u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u,\r
- 0x0Eu, 0x21u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,\r
- 0x20u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
- 0x0Cu, 0x21u, 0x00u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x1Eu, 0x01u, 0x01u, 0x01u, 0x00u, 0x00u, 0x00u,\r
+ 0x94u, 0x21u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,\r
+ 0xCEu, 0x22u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,\r
+ 0xA4u, 0x21u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,\r
+ 0xA5u, 0x22u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u,\r
+ 0xC6u, 0x21u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,\r
+ 0xD8u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0xC4u, 0x21u, 0x00u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u,\r
0x01u, 0x03u, 0x40u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u,\r
0x82u, 0x03u, 0x40u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u,\r
- 0x01u, 0x00u, 0x00u, 0x00u, 0x28u, 0x21u, 0x00u, 0x00u,\r
- 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0x21u, 0x00u, 0x00u,\r
- 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x21u, 0x00u, 0x00u,\r
+ 0x01u, 0x00u, 0x00u, 0x00u, 0xE0u, 0x21u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x14u, 0x22u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x22u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
- 0x01u, 0x00u, 0x00u, 0x00u, 0x68u, 0x21u, 0x00u, 0x00u,\r
- 0x01u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x21u, 0x00u, 0x00u,\r
- 0x41u, 0x00u, 0x00u, 0x00u, 0x33u, 0xC2u, 0xFFu, 0x1Fu,\r
- 0x74u, 0xC2u, 0xFFu, 0x1Fu, 0x41u, 0x00u, 0x00u, 0x00u,\r
- 0xF2u, 0xC1u, 0xFFu, 0x1Fu, 0xEEu, 0xC1u, 0xFFu, 0x1Fu,\r
+ 0x01u, 0x00u, 0x00u, 0x00u, 0x20u, 0x22u, 0x00u, 0x00u,\r
+ 0x01u, 0x00u, 0x00u, 0x00u, 0xB7u, 0x22u, 0x00u, 0x00u,\r
+ 0x41u, 0x00u, 0x00u, 0x00u, 0x2Bu, 0xC2u, 0xFFu, 0x1Fu,\r
+ 0x6Cu, 0xC2u, 0xFFu, 0x1Fu, 0x41u, 0x00u, 0x00u, 0x00u,\r
+ 0xEAu, 0xC1u, 0xFFu, 0x1Fu, 0xE6u, 0xC1u, 0xFFu, 0x1Fu,\r
0x24u, 0x00u, 0x05u, 0x01u, 0x09u, 0x00u, 0xA1u, 0x00u,\r
0x09u, 0x00u, 0xA1u, 0x00u, 0x09u, 0x00u, 0x15u, 0x00u,\r
0x25u, 0xFFu, 0x75u, 0x08u, 0x95u, 0x40u, 0x91u, 0x02u,\r
0x1Du, 0xB7u, 0x01u, 0x30u, 0x01u, 0x02u, 0x80u, 0x01u,\r
0xF8u, 0xB5u, 0x00u, 0xBFu, 0xF8u, 0xBCu, 0x08u, 0xBCu,\r
0x9Eu, 0x46u, 0x70u, 0x47u, 0x51u, 0x00u, 0x00u, 0x00u,\r
- 0xB9u, 0x01u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x00u, 0xBFu,\r
+ 0xB5u, 0x01u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x00u, 0xBFu,\r
0xF8u, 0xBCu, 0x08u, 0xBCu, 0x9Eu, 0x46u, 0x70u, 0x47u,\r
- 0x2Du, 0x00u, 0x00u, 0x00u, 0x60u, 0x22u, 0x00u, 0x00u,\r
+ 0x2Du, 0x00u, 0x00u, 0x00u, 0x18u, 0x23u, 0x00u, 0x00u,\r
0x08u, 0xC1u, 0xFFu, 0x1Fu, 0x20u, 0x00u, 0x00u, 0x00u,\r
- 0x50u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
- 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x20u, 0x00u, 0x00u,\r
- 0x08u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x7Du,\r
+ 0x48u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0xBCu, 0x20u, 0x00u, 0x00u,\r
+ 0xC0u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x7Du,\r
0x00u, 0xFAu, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x90u, 0xD0u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
\r
#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
#endif\r
const uint8 cy_metadata[] = {\r
0x00u, 0x01u, 0x2Eu, 0x13u, 0x30u, 0x69u, 0x00u, 0x01u,\r
- 0x2Eu, 0x1Fu, 0x8Cu, 0x6Bu};\r
+ 0x2Eu, 0x20u, 0x2Bu, 0x6Bu};\r
\r
#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
__attribute__ ((__section__(".cycustnvl"), used))\r
/* GENERATED CODE -- CHANGES WILL BE OVERWRITTEN */\r
\r
-define symbol CYDEV_BTLDR_SIZE = 0x00002300;\r
+define symbol CYDEV_BTLDR_SIZE = 0x00002400;\r
/*******************************************************************************\r
* FILENAME: cydevice.h\r
* OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator 3.0 Component Pack 7\r
+* PSoC Creator 3.1\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
/*******************************************************************************\r
* FILENAME: cydevice_trm.h\r
* \r
-* PSoC Creator 3.0 Component Pack 7\r
+* PSoC Creator 3.1\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
/*******************************************************************************\r
* FILENAME: cydevicegnu.inc\r
* OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator 3.0 Component Pack 7\r
+* PSoC Creator 3.1\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
/*******************************************************************************\r
* FILENAME: cydevicegnu_trm.inc\r
* \r
-* PSoC Creator 3.0 Component Pack 7\r
+* PSoC Creator 3.1\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
;\r
; FILENAME: cydeviceiar.inc\r
; OBSOLETE: Do not use this file. Use the _trm version instead.\r
-; PSoC Creator 3.0 Component Pack 7\r
+; PSoC Creator 3.1\r
;\r
; DESCRIPTION:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
; FILENAME: cydeviceiar_trm.inc\r
; \r
-; PSoC Creator 3.0 Component Pack 7\r
+; PSoC Creator 3.1\r
;\r
; DESCRIPTION:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
; FILENAME: cydevicerv.inc\r
; OBSOLETE: Do not use this file. Use the _trm version instead.\r
-; PSoC Creator 3.0 Component Pack 7\r
+; PSoC Creator 3.1\r
;\r
; DESCRIPTION:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
; FILENAME: cydevicerv_trm.inc\r
; \r
-; PSoC Creator 3.0 Component Pack 7\r
+; PSoC Creator 3.1\r
;\r
; DESCRIPTION:\r
; This file provides all of the address values for the entire PSoC device.\r
#include <cydevice.h>\r
#include <cydevice_trm.h>\r
\r
-/* Debug_Timer_Interrupt */\r
-#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define Debug_Timer_Interrupt__INTC_MASK 0x02u\r
-#define Debug_Timer_Interrupt__INTC_NUMBER 1u\r
-#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u\r
-#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
-#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_RX_DMA_COMPLETE */\r
-#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u\r
-#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u\r
-#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
-#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_TX_DMA_COMPLETE */\r
-#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x08u\r
-#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 3u\r
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
-#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* Debug_Timer_TimerHW */\r
-#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0\r
-#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1\r
-#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0\r
-#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1\r
-#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2\r
-#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0\r
-#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1\r
-#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0\r
-#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1\r
-#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3\r
-#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u\r
-#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3\r
-#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u\r
-#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0\r
-#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1\r
-#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0\r
+/* LED1 */\r
+#define LED1__0__MASK 0x08u\r
+#define LED1__0__PC CYREG_PRT12_PC3\r
+#define LED1__0__PORT 12u\r
+#define LED1__0__SHIFT 3\r
+#define LED1__AG CYREG_PRT12_AG\r
+#define LED1__BIE CYREG_PRT12_BIE\r
+#define LED1__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define LED1__BYP CYREG_PRT12_BYP\r
+#define LED1__DM0 CYREG_PRT12_DM0\r
+#define LED1__DM1 CYREG_PRT12_DM1\r
+#define LED1__DM2 CYREG_PRT12_DM2\r
+#define LED1__DR CYREG_PRT12_DR\r
+#define LED1__INP_DIS CYREG_PRT12_INP_DIS\r
+#define LED1__MASK 0x08u\r
+#define LED1__PORT 12u\r
+#define LED1__PRT CYREG_PRT12_PRT\r
+#define LED1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define LED1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define LED1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define LED1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define LED1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define LED1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define LED1__PS CYREG_PRT12_PS\r
+#define LED1__SHIFT 3\r
+#define LED1__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define LED1__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define LED1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define LED1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define LED1__SLW CYREG_PRT12_SLW\r
\r
-/* SD_RX_DMA_COMPLETE */\r
-#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SD_RX_DMA_COMPLETE__INTC_MASK 0x10u\r
-#define SD_RX_DMA_COMPLETE__INTC_NUMBER 4u\r
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
-#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+/* SD_CD */\r
+#define SD_CD__0__MASK 0x40u\r
+#define SD_CD__0__PC CYREG_PRT3_PC6\r
+#define SD_CD__0__PORT 3u\r
+#define SD_CD__0__SHIFT 6\r
+#define SD_CD__AG CYREG_PRT3_AG\r
+#define SD_CD__AMUX CYREG_PRT3_AMUX\r
+#define SD_CD__BIE CYREG_PRT3_BIE\r
+#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_CD__BYP CYREG_PRT3_BYP\r
+#define SD_CD__CTL CYREG_PRT3_CTL\r
+#define SD_CD__DM0 CYREG_PRT3_DM0\r
+#define SD_CD__DM1 CYREG_PRT3_DM1\r
+#define SD_CD__DM2 CYREG_PRT3_DM2\r
+#define SD_CD__DR CYREG_PRT3_DR\r
+#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_CD__MASK 0x40u\r
+#define SD_CD__PORT 3u\r
+#define SD_CD__PRT CYREG_PRT3_PRT\r
+#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_CD__PS CYREG_PRT3_PS\r
+#define SD_CD__SHIFT 6\r
+#define SD_CD__SLW CYREG_PRT3_SLW\r
\r
-/* SD_TX_DMA_COMPLETE */\r
-#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SD_TX_DMA_COMPLETE__INTC_MASK 0x20u\r
-#define SD_TX_DMA_COMPLETE__INTC_NUMBER 5u\r
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5\r
-#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+/* SD_CS */\r
+#define SD_CS__0__MASK 0x10u\r
+#define SD_CS__0__PC CYREG_PRT3_PC4\r
+#define SD_CS__0__PORT 3u\r
+#define SD_CS__0__SHIFT 4\r
+#define SD_CS__AG CYREG_PRT3_AG\r
+#define SD_CS__AMUX CYREG_PRT3_AMUX\r
+#define SD_CS__BIE CYREG_PRT3_BIE\r
+#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_CS__BYP CYREG_PRT3_BYP\r
+#define SD_CS__CTL CYREG_PRT3_CTL\r
+#define SD_CS__DM0 CYREG_PRT3_DM0\r
+#define SD_CS__DM1 CYREG_PRT3_DM1\r
+#define SD_CS__DM2 CYREG_PRT3_DM2\r
+#define SD_CS__DR CYREG_PRT3_DR\r
+#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_CS__MASK 0x10u\r
+#define SD_CS__PORT 3u\r
+#define SD_CS__PRT CYREG_PRT3_PRT\r
+#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_CS__PS CYREG_PRT3_PS\r
+#define SD_CS__SHIFT 4\r
+#define SD_CS__SLW CYREG_PRT3_SLW\r
\r
-/* SCSI_Parity_Error */\r
-#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST\r
+/* USBFS_arb_int */\r
+#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_arb_int__INTC_MASK 0x400000u\r
+#define USBFS_arb_int__INTC_NUMBER 22u\r
+#define USBFS_arb_int__INTC_PRIOR_NUM 7u\r
+#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22\r
+#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* USBFS_bus_reset */\r
#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
-/* SCSI_CTL_PHASE */\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB00_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB00_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB00_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL\r
-\r
-/* SCSI_Filtered */\r
-#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u\r
-#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB14_15_ST\r
-#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
-#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
-#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
-#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
-#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
-#define SCSI_Filtered_sts_sts_reg__3__POS 3\r
-#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
-#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
-#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB14_MSK\r
-#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB14_ACTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB14_ST_CTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB14_ST_CTL\r
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB14_ST\r
-\r
-/* SCSI_Out_Bits */\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
-\r
-/* USBFS_arb_int */\r
-#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_arb_int__INTC_MASK 0x400000u\r
-#define USBFS_arb_int__INTC_NUMBER 22u\r
-#define USBFS_arb_int__INTC_PRIOR_NUM 7u\r
-#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22\r
-#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+/* USBFS_Dm */\r
+#define USBFS_Dm__0__MASK 0x80u\r
+#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1\r
+#define USBFS_Dm__0__PORT 15u\r
+#define USBFS_Dm__0__SHIFT 7\r
+#define USBFS_Dm__AG CYREG_PRT15_AG\r
+#define USBFS_Dm__AMUX CYREG_PRT15_AMUX\r
+#define USBFS_Dm__BIE CYREG_PRT15_BIE\r
+#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK\r
+#define USBFS_Dm__BYP CYREG_PRT15_BYP\r
+#define USBFS_Dm__CTL CYREG_PRT15_CTL\r
+#define USBFS_Dm__DM0 CYREG_PRT15_DM0\r
+#define USBFS_Dm__DM1 CYREG_PRT15_DM1\r
+#define USBFS_Dm__DM2 CYREG_PRT15_DM2\r
+#define USBFS_Dm__DR CYREG_PRT15_DR\r
+#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS\r
+#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
+#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN\r
+#define USBFS_Dm__MASK 0x80u\r
+#define USBFS_Dm__PORT 15u\r
+#define USBFS_Dm__PRT CYREG_PRT15_PRT\r
+#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
+#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
+#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
+#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
+#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
+#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
+#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
+#define USBFS_Dm__PS CYREG_PRT15_PS\r
+#define USBFS_Dm__SHIFT 7\r
+#define USBFS_Dm__SLW CYREG_PRT15_SLW\r
+\r
+/* USBFS_Dp */\r
+#define USBFS_Dp__0__MASK 0x40u\r
+#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0\r
+#define USBFS_Dp__0__PORT 15u\r
+#define USBFS_Dp__0__SHIFT 6\r
+#define USBFS_Dp__AG CYREG_PRT15_AG\r
+#define USBFS_Dp__AMUX CYREG_PRT15_AMUX\r
+#define USBFS_Dp__BIE CYREG_PRT15_BIE\r
+#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK\r
+#define USBFS_Dp__BYP CYREG_PRT15_BYP\r
+#define USBFS_Dp__CTL CYREG_PRT15_CTL\r
+#define USBFS_Dp__DM0 CYREG_PRT15_DM0\r
+#define USBFS_Dp__DM1 CYREG_PRT15_DM1\r
+#define USBFS_Dp__DM2 CYREG_PRT15_DM2\r
+#define USBFS_Dp__DR CYREG_PRT15_DR\r
+#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS\r
+#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT\r
+#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
+#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN\r
+#define USBFS_Dp__MASK 0x40u\r
+#define USBFS_Dp__PORT 15u\r
+#define USBFS_Dp__PRT CYREG_PRT15_PRT\r
+#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
+#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
+#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
+#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
+#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
+#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
+#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
+#define USBFS_Dp__PS CYREG_PRT15_PS\r
+#define USBFS_Dp__SHIFT 6\r
+#define USBFS_Dp__SLW CYREG_PRT15_SLW\r
+#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15\r
+\r
+/* USBFS_dp_int */\r
+#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_dp_int__INTC_MASK 0x1000u\r
+#define USBFS_dp_int__INTC_NUMBER 12u\r
+#define USBFS_dp_int__INTC_PRIOR_NUM 7u\r
+#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12\r
+#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_0 */\r
+#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_0__INTC_MASK 0x1000000u\r
+#define USBFS_ep_0__INTC_NUMBER 24u\r
+#define USBFS_ep_0__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24\r
+#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_1 */\r
+#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_1__INTC_MASK 0x40u\r
+#define USBFS_ep_1__INTC_NUMBER 6u\r
+#define USBFS_ep_1__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_6\r
+#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_2 */\r
+#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_2__INTC_MASK 0x80u\r
+#define USBFS_ep_2__INTC_NUMBER 7u\r
+#define USBFS_ep_2__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_7\r
+#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_3 */\r
+#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_3__INTC_MASK 0x100u\r
+#define USBFS_ep_3__INTC_NUMBER 8u\r
+#define USBFS_ep_3__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_8\r
+#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_4 */\r
+#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_4__INTC_MASK 0x200u\r
+#define USBFS_ep_4__INTC_NUMBER 9u\r
+#define USBFS_ep_4__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_9\r
+#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* USBFS_sof_int */\r
#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
-/* SCSI_Out_Ctl */\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
+/* USBFS_USB */\r
+#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG\r
+#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG\r
+#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN\r
+#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR\r
+#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG\r
+#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN\r
+#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR\r
+#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG\r
+#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN\r
+#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR\r
+#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG\r
+#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN\r
+#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR\r
+#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG\r
+#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN\r
+#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR\r
+#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG\r
+#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN\r
+#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR\r
+#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG\r
+#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN\r
+#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR\r
+#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG\r
+#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN\r
+#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR\r
+#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN\r
+#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR\r
+#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR\r
+#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA\r
+#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB\r
+#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA\r
+#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB\r
+#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR\r
+#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA\r
+#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB\r
+#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA\r
+#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB\r
+#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR\r
+#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA\r
+#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB\r
+#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA\r
+#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB\r
+#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR\r
+#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA\r
+#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB\r
+#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA\r
+#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB\r
+#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR\r
+#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA\r
+#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB\r
+#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA\r
+#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB\r
+#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR\r
+#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA\r
+#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB\r
+#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA\r
+#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB\r
+#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR\r
+#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA\r
+#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB\r
+#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA\r
+#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB\r
+#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR\r
+#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA\r
+#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB\r
+#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA\r
+#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB\r
+#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE\r
+#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT\r
+#define USBFS_USB__CR0 CYREG_USB_CR0\r
+#define USBFS_USB__CR1 CYREG_USB_CR1\r
+#define USBFS_USB__CWA CYREG_USB_CWA\r
+#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB\r
+#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES\r
+#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB\r
+#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG\r
+#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE\r
+#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE\r
+#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT\r
+#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR\r
+#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0\r
+#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1\r
+#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2\r
+#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3\r
+#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4\r
+#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5\r
+#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6\r
+#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7\r
+#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE\r
+#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5\r
+#define USBFS_USB__PM_ACT_MSK 0x01u\r
+#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5\r
+#define USBFS_USB__PM_STBY_MSK 0x01u\r
+#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN\r
+#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR\r
+#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0\r
+#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1\r
+#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0\r
+#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0\r
+#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1\r
+#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0\r
+#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0\r
+#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1\r
+#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0\r
+#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0\r
+#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1\r
+#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0\r
+#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0\r
+#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1\r
+#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0\r
+#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0\r
+#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1\r
+#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0\r
+#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0\r
+#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1\r
+#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0\r
+#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0\r
+#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1\r
+#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0\r
+#define USBFS_USB__SOF0 CYREG_USB_SOF0\r
+#define USBFS_USB__SOF1 CYREG_USB_SOF1\r
+#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN\r
+#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0\r
+#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
\r
-/* SCSI_Out_DBx */\r
-#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__0__MASK 0x08u\r
-#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC3\r
-#define SCSI_Out_DBx__0__PORT 6u\r
-#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__0__SHIFT 3\r
-#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__1__MASK 0x04u\r
-#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC2\r
-#define SCSI_Out_DBx__1__PORT 6u\r
-#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__1__SHIFT 2\r
-#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__2__MASK 0x02u\r
-#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC1\r
-#define SCSI_Out_DBx__2__PORT 6u\r
-#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__2__SHIFT 1\r
-#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__3__MASK 0x01u\r
-#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC0\r
-#define SCSI_Out_DBx__3__PORT 6u\r
-#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__3__SHIFT 0\r
-#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__4__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__4__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__4__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__4__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__4__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__4__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__4__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__4__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__4__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__4__MASK 0x80u\r
-#define SCSI_Out_DBx__4__PC CYREG_PRT4_PC7\r
-#define SCSI_Out_DBx__4__PORT 4u\r
-#define SCSI_Out_DBx__4__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__4__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__4__SHIFT 7\r
-#define SCSI_Out_DBx__4__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__5__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__5__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__5__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__5__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__5__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__5__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__5__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__5__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__5__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__5__MASK 0x40u\r
-#define SCSI_Out_DBx__5__PC CYREG_PRT4_PC6\r
-#define SCSI_Out_DBx__5__PORT 4u\r
-#define SCSI_Out_DBx__5__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__5__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__5__SHIFT 6\r
-#define SCSI_Out_DBx__5__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__6__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__6__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__6__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__6__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__6__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__6__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__6__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__6__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__6__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__6__MASK 0x20u\r
-#define SCSI_Out_DBx__6__PC CYREG_PRT4_PC5\r
-#define SCSI_Out_DBx__6__PORT 4u\r
-#define SCSI_Out_DBx__6__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__6__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__6__SHIFT 5\r
-#define SCSI_Out_DBx__6__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__7__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__7__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__7__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__7__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__7__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__7__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__7__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__7__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__7__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__7__MASK 0x10u\r
-#define SCSI_Out_DBx__7__PC CYREG_PRT4_PC4\r
-#define SCSI_Out_DBx__7__PORT 4u\r
-#define SCSI_Out_DBx__7__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__7__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__7__SHIFT 4\r
-#define SCSI_Out_DBx__7__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__DB0__MASK 0x08u\r
-#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC3\r
-#define SCSI_Out_DBx__DB0__PORT 6u\r
-#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB0__SHIFT 3\r
-#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__DB1__MASK 0x04u\r
-#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC2\r
-#define SCSI_Out_DBx__DB1__PORT 6u\r
-#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB1__SHIFT 2\r
-#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__DB2__MASK 0x02u\r
-#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC1\r
-#define SCSI_Out_DBx__DB2__PORT 6u\r
-#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB2__SHIFT 1\r
-#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__DB3__MASK 0x01u\r
-#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC0\r
-#define SCSI_Out_DBx__DB3__PORT 6u\r
-#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB3__SHIFT 0\r
-#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__DB4__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__DB4__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__DB4__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__DB4__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__DB4__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__DB4__MASK 0x80u\r
-#define SCSI_Out_DBx__DB4__PC CYREG_PRT4_PC7\r
-#define SCSI_Out_DBx__DB4__PORT 4u\r
-#define SCSI_Out_DBx__DB4__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__DB4__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB4__SHIFT 7\r
-#define SCSI_Out_DBx__DB4__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__DB5__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__DB5__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__DB5__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__DB5__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__DB5__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__DB5__MASK 0x40u\r
-#define SCSI_Out_DBx__DB5__PC CYREG_PRT4_PC6\r
-#define SCSI_Out_DBx__DB5__PORT 4u\r
-#define SCSI_Out_DBx__DB5__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__DB5__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB5__SHIFT 6\r
-#define SCSI_Out_DBx__DB5__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__DB6__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__DB6__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__DB6__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__DB6__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__DB6__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__DB6__MASK 0x20u\r
-#define SCSI_Out_DBx__DB6__PC CYREG_PRT4_PC5\r
-#define SCSI_Out_DBx__DB6__PORT 4u\r
-#define SCSI_Out_DBx__DB6__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__DB6__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB6__SHIFT 5\r
-#define SCSI_Out_DBx__DB6__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__DB7__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__DB7__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__DB7__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__DB7__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__DB7__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__DB7__MASK 0x10u\r
-#define SCSI_Out_DBx__DB7__PC CYREG_PRT4_PC4\r
-#define SCSI_Out_DBx__DB7__PORT 4u\r
-#define SCSI_Out_DBx__DB7__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__DB7__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB7__SHIFT 4\r
-#define SCSI_Out_DBx__DB7__SLW CYREG_PRT4_SLW\r
-\r
-/* SCSI_RST_ISR */\r
-#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define SCSI_RST_ISR__INTC_MASK 0x04u\r
-#define SCSI_RST_ISR__INTC_NUMBER 2u\r
-#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u\r
-#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
-#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SDCard_BSPIM */\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK\r
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK\r
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL\r
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL\r
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL\r
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK\r
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
-#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
-#define SDCard_BSPIM_RxStsReg__4__POS 4\r
-#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
-#define SDCard_BSPIM_RxStsReg__5__POS 5\r
-#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
-#define SDCard_BSPIM_RxStsReg__6__POS 6\r
-#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST\r
-#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
-#define SDCard_BSPIM_TxStsReg__0__POS 0\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
-#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
-#define SDCard_BSPIM_TxStsReg__1__POS 1\r
-#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
-#define SDCard_BSPIM_TxStsReg__2__POS 2\r
-#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
-#define SDCard_BSPIM_TxStsReg__3__POS 3\r
-#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
-#define SDCard_BSPIM_TxStsReg__4__POS 4\r
-#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL\r
-\r
-/* USBFS_dp_int */\r
-#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_dp_int__INTC_MASK 0x1000u\r
-#define USBFS_dp_int__INTC_NUMBER 12u\r
-#define USBFS_dp_int__INTC_PRIOR_NUM 7u\r
-#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12\r
-#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_In_DBx */\r
-#define SCSI_In_DBx__0__AG CYREG_PRT12_AG\r
-#define SCSI_In_DBx__0__BIE CYREG_PRT12_BIE\r
-#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT12_BIT_MASK\r
-#define SCSI_In_DBx__0__BYP CYREG_PRT12_BYP\r
-#define SCSI_In_DBx__0__DM0 CYREG_PRT12_DM0\r
-#define SCSI_In_DBx__0__DM1 CYREG_PRT12_DM1\r
-#define SCSI_In_DBx__0__DM2 CYREG_PRT12_DM2\r
-#define SCSI_In_DBx__0__DR CYREG_PRT12_DR\r
-#define SCSI_In_DBx__0__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_In_DBx__0__MASK 0x10u\r
-#define SCSI_In_DBx__0__PC CYREG_PRT12_PC4\r
-#define SCSI_In_DBx__0__PORT 12u\r
-#define SCSI_In_DBx__0__PRT CYREG_PRT12_PRT\r
-#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
-#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
-#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
-#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
-#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
-#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
-#define SCSI_In_DBx__0__PS CYREG_PRT12_PS\r
-#define SCSI_In_DBx__0__SHIFT 4\r
-#define SCSI_In_DBx__0__SIO_CFG CYREG_PRT12_SIO_CFG\r
-#define SCSI_In_DBx__0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
-#define SCSI_In_DBx__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
-#define SCSI_In_DBx__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
-#define SCSI_In_DBx__0__SLW CYREG_PRT12_SLW\r
-#define SCSI_In_DBx__1__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__1__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__1__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__1__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__1__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__1__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__1__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__1__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__1__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__1__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__1__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__1__MASK 0x80u\r
-#define SCSI_In_DBx__1__PC CYREG_PRT2_PC7\r
-#define SCSI_In_DBx__1__PORT 2u\r
-#define SCSI_In_DBx__1__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__1__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__1__SHIFT 7\r
-#define SCSI_In_DBx__1__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__2__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__2__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__2__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__2__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__2__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__2__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__2__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__2__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__2__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__2__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__2__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__2__MASK 0x40u\r
-#define SCSI_In_DBx__2__PC CYREG_PRT2_PC6\r
-#define SCSI_In_DBx__2__PORT 2u\r
-#define SCSI_In_DBx__2__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__2__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__2__SHIFT 6\r
-#define SCSI_In_DBx__2__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__3__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__3__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__3__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__3__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__3__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__3__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__3__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__3__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__3__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__3__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__3__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__3__MASK 0x20u\r
-#define SCSI_In_DBx__3__PC CYREG_PRT2_PC5\r
-#define SCSI_In_DBx__3__PORT 2u\r
-#define SCSI_In_DBx__3__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__3__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__3__SHIFT 5\r
-#define SCSI_In_DBx__3__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__4__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__4__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__4__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__4__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__4__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__4__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__4__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__4__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__4__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__4__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__4__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__4__MASK 0x10u\r
-#define SCSI_In_DBx__4__PC CYREG_PRT2_PC4\r
-#define SCSI_In_DBx__4__PORT 2u\r
-#define SCSI_In_DBx__4__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__4__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__4__SHIFT 4\r
-#define SCSI_In_DBx__4__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__5__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__5__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__5__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__5__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__5__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__5__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__5__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__5__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__5__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__5__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__5__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__5__MASK 0x08u\r
-#define SCSI_In_DBx__5__PC CYREG_PRT2_PC3\r
-#define SCSI_In_DBx__5__PORT 2u\r
-#define SCSI_In_DBx__5__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__5__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__5__SHIFT 3\r
-#define SCSI_In_DBx__5__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__6__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__6__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__6__MASK 0x04u\r
-#define SCSI_In_DBx__6__PC CYREG_PRT2_PC2\r
-#define SCSI_In_DBx__6__PORT 2u\r
-#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__6__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__6__SHIFT 2\r
-#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__7__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__7__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__7__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__7__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__7__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__7__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__7__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__7__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__7__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__7__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__7__MASK 0x02u\r
-#define SCSI_In_DBx__7__PC CYREG_PRT2_PC1\r
-#define SCSI_In_DBx__7__PORT 2u\r
-#define SCSI_In_DBx__7__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__7__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__7__SHIFT 1\r
-#define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB0__AG CYREG_PRT12_AG\r
-#define SCSI_In_DBx__DB0__BIE CYREG_PRT12_BIE\r
-#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT12_BIT_MASK\r
-#define SCSI_In_DBx__DB0__BYP CYREG_PRT12_BYP\r
-#define SCSI_In_DBx__DB0__DM0 CYREG_PRT12_DM0\r
-#define SCSI_In_DBx__DB0__DM1 CYREG_PRT12_DM1\r
-#define SCSI_In_DBx__DB0__DM2 CYREG_PRT12_DM2\r
-#define SCSI_In_DBx__DB0__DR CYREG_PRT12_DR\r
-#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_In_DBx__DB0__MASK 0x10u\r
-#define SCSI_In_DBx__DB0__PC CYREG_PRT12_PC4\r
-#define SCSI_In_DBx__DB0__PORT 12u\r
-#define SCSI_In_DBx__DB0__PRT CYREG_PRT12_PRT\r
-#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
-#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
-#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
-#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
-#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
-#define SCSI_In_DBx__DB0__PS CYREG_PRT12_PS\r
-#define SCSI_In_DBx__DB0__SHIFT 4\r
-#define SCSI_In_DBx__DB0__SIO_CFG CYREG_PRT12_SIO_CFG\r
-#define SCSI_In_DBx__DB0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
-#define SCSI_In_DBx__DB0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
-#define SCSI_In_DBx__DB0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
-#define SCSI_In_DBx__DB0__SLW CYREG_PRT12_SLW\r
-#define SCSI_In_DBx__DB1__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB1__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB1__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB1__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB1__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB1__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB1__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB1__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB1__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB1__MASK 0x80u\r
-#define SCSI_In_DBx__DB1__PC CYREG_PRT2_PC7\r
-#define SCSI_In_DBx__DB1__PORT 2u\r
-#define SCSI_In_DBx__DB1__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB1__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB1__SHIFT 7\r
-#define SCSI_In_DBx__DB1__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB2__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB2__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB2__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB2__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB2__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB2__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB2__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB2__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB2__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB2__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB2__MASK 0x40u\r
-#define SCSI_In_DBx__DB2__PC CYREG_PRT2_PC6\r
-#define SCSI_In_DBx__DB2__PORT 2u\r
-#define SCSI_In_DBx__DB2__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB2__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB2__SHIFT 6\r
-#define SCSI_In_DBx__DB2__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB3__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB3__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB3__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB3__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB3__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB3__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB3__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB3__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB3__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB3__MASK 0x20u\r
-#define SCSI_In_DBx__DB3__PC CYREG_PRT2_PC5\r
-#define SCSI_In_DBx__DB3__PORT 2u\r
-#define SCSI_In_DBx__DB3__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB3__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB3__SHIFT 5\r
-#define SCSI_In_DBx__DB3__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB4__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB4__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB4__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB4__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB4__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB4__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB4__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB4__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB4__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB4__MASK 0x10u\r
-#define SCSI_In_DBx__DB4__PC CYREG_PRT2_PC4\r
-#define SCSI_In_DBx__DB4__PORT 2u\r
-#define SCSI_In_DBx__DB4__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB4__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB4__SHIFT 4\r
-#define SCSI_In_DBx__DB4__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB5__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB5__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB5__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB5__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB5__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB5__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB5__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB5__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB5__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB5__MASK 0x08u\r
-#define SCSI_In_DBx__DB5__PC CYREG_PRT2_PC3\r
-#define SCSI_In_DBx__DB5__PORT 2u\r
-#define SCSI_In_DBx__DB5__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB5__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB5__SHIFT 3\r
-#define SCSI_In_DBx__DB5__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB6__MASK 0x04u\r
-#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC2\r
-#define SCSI_In_DBx__DB6__PORT 2u\r
-#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB6__SHIFT 2\r
-#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW\r
-#define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG\r
-#define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX\r
-#define SCSI_In_DBx__DB7__BIE CYREG_PRT2_BIE\r
-#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK\r
-#define SCSI_In_DBx__DB7__BYP CYREG_PRT2_BYP\r
-#define SCSI_In_DBx__DB7__CTL CYREG_PRT2_CTL\r
-#define SCSI_In_DBx__DB7__DM0 CYREG_PRT2_DM0\r
-#define SCSI_In_DBx__DB7__DM1 CYREG_PRT2_DM1\r
-#define SCSI_In_DBx__DB7__DM2 CYREG_PRT2_DM2\r
-#define SCSI_In_DBx__DB7__DR CYREG_PRT2_DR\r
-#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS\r
-#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
-#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN\r
-#define SCSI_In_DBx__DB7__MASK 0x02u\r
-#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC1\r
-#define SCSI_In_DBx__DB7__PORT 2u\r
-#define SCSI_In_DBx__DB7__PRT CYREG_PRT2_PRT\r
-#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
-#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
-#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
-#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
-#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
-#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
-#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
-#define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS\r
-#define SCSI_In_DBx__DB7__SHIFT 1\r
-#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW\r
-\r
-/* SCSI_RX_DMA */\r
-#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
-#define SCSI_RX_DMA__DRQ_NUMBER 0u\r
-#define SCSI_RX_DMA__NUMBEROF_TDS 0u\r
-#define SCSI_RX_DMA__PRIORITY 2u\r
-#define SCSI_RX_DMA__TERMIN_EN 0u\r
-#define SCSI_RX_DMA__TERMIN_SEL 0u\r
-#define SCSI_RX_DMA__TERMOUT0_EN 1u\r
-#define SCSI_RX_DMA__TERMOUT0_SEL 0u\r
-#define SCSI_RX_DMA__TERMOUT1_EN 0u\r
-#define SCSI_RX_DMA__TERMOUT1_SEL 0u\r
-\r
-/* SCSI_TX_DMA */\r
-#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
-#define SCSI_TX_DMA__DRQ_NUMBER 1u\r
-#define SCSI_TX_DMA__NUMBEROF_TDS 0u\r
-#define SCSI_TX_DMA__PRIORITY 2u\r
-#define SCSI_TX_DMA__TERMIN_EN 0u\r
-#define SCSI_TX_DMA__TERMIN_SEL 0u\r
-#define SCSI_TX_DMA__TERMOUT0_EN 1u\r
-#define SCSI_TX_DMA__TERMOUT0_SEL 1u\r
-#define SCSI_TX_DMA__TERMOUT1_EN 0u\r
-#define SCSI_TX_DMA__TERMOUT1_SEL 0u\r
-\r
-/* SD_Data_Clk */\r
-#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0\r
-#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1\r
-#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2\r
-#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u\r
-#define SD_Data_Clk__INDEX 0x00u\r
-#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
-#define SD_Data_Clk__PM_ACT_MSK 0x01u\r
-#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
-#define SD_Data_Clk__PM_STBY_MSK 0x01u\r
-\r
-/* timer_clock */\r
-#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0\r
-#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1\r
-#define timer_clock__CFG2 CYREG_CLKDIST_DCFG2_CFG2\r
-#define timer_clock__CFG2_SRC_SEL_MASK 0x07u\r
-#define timer_clock__INDEX 0x02u\r
-#define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
-#define timer_clock__PM_ACT_MSK 0x04u\r
-#define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
-#define timer_clock__PM_STBY_MSK 0x04u\r
-\r
-/* SCSI_Noise */\r
-#define SCSI_Noise__0__AG CYREG_PRT12_AG\r
-#define SCSI_Noise__0__BIE CYREG_PRT12_BIE\r
-#define SCSI_Noise__0__BIT_MASK CYREG_PRT12_BIT_MASK\r
-#define SCSI_Noise__0__BYP CYREG_PRT12_BYP\r
-#define SCSI_Noise__0__DM0 CYREG_PRT12_DM0\r
-#define SCSI_Noise__0__DM1 CYREG_PRT12_DM1\r
-#define SCSI_Noise__0__DM2 CYREG_PRT12_DM2\r
-#define SCSI_Noise__0__DR CYREG_PRT12_DR\r
-#define SCSI_Noise__0__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_Noise__0__MASK 0x20u\r
-#define SCSI_Noise__0__PC CYREG_PRT12_PC5\r
-#define SCSI_Noise__0__PORT 12u\r
-#define SCSI_Noise__0__PRT CYREG_PRT12_PRT\r
-#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
-#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
-#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
-#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
-#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
-#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
-#define SCSI_Noise__0__PS CYREG_PRT12_PS\r
-#define SCSI_Noise__0__SHIFT 5\r
-#define SCSI_Noise__0__SIO_CFG CYREG_PRT12_SIO_CFG\r
-#define SCSI_Noise__0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
-#define SCSI_Noise__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
-#define SCSI_Noise__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
-#define SCSI_Noise__0__SLW CYREG_PRT12_SLW\r
-#define SCSI_Noise__1__AG CYREG_PRT6_AG\r
-#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Noise__1__BIE CYREG_PRT6_BIE\r
-#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Noise__1__BYP CYREG_PRT6_BYP\r
-#define SCSI_Noise__1__CTL CYREG_PRT6_CTL\r
-#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Noise__1__DR CYREG_PRT6_DR\r
-#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Noise__1__MASK 0x10u\r
-#define SCSI_Noise__1__PC CYREG_PRT6_PC4\r
-#define SCSI_Noise__1__PORT 6u\r
-#define SCSI_Noise__1__PRT CYREG_PRT6_PRT\r
-#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Noise__1__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__1__SHIFT 4\r
-#define SCSI_Noise__1__SLW CYREG_PRT6_SLW\r
-#define SCSI_Noise__2__AG CYREG_PRT5_AG\r
-#define SCSI_Noise__2__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_Noise__2__BIE CYREG_PRT5_BIE\r
-#define SCSI_Noise__2__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_Noise__2__BYP CYREG_PRT5_BYP\r
-#define SCSI_Noise__2__CTL CYREG_PRT5_CTL\r
-#define SCSI_Noise__2__DM0 CYREG_PRT5_DM0\r
-#define SCSI_Noise__2__DM1 CYREG_PRT5_DM1\r
-#define SCSI_Noise__2__DM2 CYREG_PRT5_DM2\r
-#define SCSI_Noise__2__DR CYREG_PRT5_DR\r
-#define SCSI_Noise__2__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_Noise__2__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_Noise__2__MASK 0x01u\r
-#define SCSI_Noise__2__PC CYREG_PRT5_PC0\r
-#define SCSI_Noise__2__PORT 5u\r
-#define SCSI_Noise__2__PRT CYREG_PRT5_PRT\r
-#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_Noise__2__PS CYREG_PRT5_PS\r
-#define SCSI_Noise__2__SHIFT 0\r
-#define SCSI_Noise__2__SLW CYREG_PRT5_SLW\r
-#define SCSI_Noise__3__AG CYREG_PRT6_AG\r
-#define SCSI_Noise__3__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Noise__3__BIE CYREG_PRT6_BIE\r
-#define SCSI_Noise__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Noise__3__BYP CYREG_PRT6_BYP\r
-#define SCSI_Noise__3__CTL CYREG_PRT6_CTL\r
-#define SCSI_Noise__3__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Noise__3__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Noise__3__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Noise__3__DR CYREG_PRT6_DR\r
-#define SCSI_Noise__3__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Noise__3__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Noise__3__MASK 0x40u\r
-#define SCSI_Noise__3__PC CYREG_PRT6_PC6\r
-#define SCSI_Noise__3__PORT 6u\r
-#define SCSI_Noise__3__PRT CYREG_PRT6_PRT\r
-#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Noise__3__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__3__SHIFT 6\r
-#define SCSI_Noise__3__SLW CYREG_PRT6_SLW\r
-#define SCSI_Noise__4__AG CYREG_PRT6_AG\r
-#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Noise__4__BIE CYREG_PRT6_BIE\r
-#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Noise__4__BYP CYREG_PRT6_BYP\r
-#define SCSI_Noise__4__CTL CYREG_PRT6_CTL\r
-#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Noise__4__DR CYREG_PRT6_DR\r
-#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Noise__4__MASK 0x20u\r
-#define SCSI_Noise__4__PC CYREG_PRT6_PC5\r
-#define SCSI_Noise__4__PORT 6u\r
-#define SCSI_Noise__4__PRT CYREG_PRT6_PRT\r
-#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Noise__4__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__4__SHIFT 5\r
-#define SCSI_Noise__4__SLW CYREG_PRT6_SLW\r
-#define SCSI_Noise__ACK__AG CYREG_PRT6_AG\r
-#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE\r
-#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP\r
-#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL\r
-#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Noise__ACK__DR CYREG_PRT6_DR\r
-#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Noise__ACK__MASK 0x20u\r
-#define SCSI_Noise__ACK__PC CYREG_PRT6_PC5\r
-#define SCSI_Noise__ACK__PORT 6u\r
-#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT\r
-#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Noise__ACK__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__ACK__SHIFT 5\r
-#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW\r
-#define SCSI_Noise__ATN__AG CYREG_PRT12_AG\r
-#define SCSI_Noise__ATN__BIE CYREG_PRT12_BIE\r
-#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT12_BIT_MASK\r
-#define SCSI_Noise__ATN__BYP CYREG_PRT12_BYP\r
-#define SCSI_Noise__ATN__DM0 CYREG_PRT12_DM0\r
-#define SCSI_Noise__ATN__DM1 CYREG_PRT12_DM1\r
-#define SCSI_Noise__ATN__DM2 CYREG_PRT12_DM2\r
-#define SCSI_Noise__ATN__DR CYREG_PRT12_DR\r
-#define SCSI_Noise__ATN__INP_DIS CYREG_PRT12_INP_DIS\r
-#define SCSI_Noise__ATN__MASK 0x20u\r
-#define SCSI_Noise__ATN__PC CYREG_PRT12_PC5\r
-#define SCSI_Noise__ATN__PORT 12u\r
-#define SCSI_Noise__ATN__PRT CYREG_PRT12_PRT\r
-#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
-#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
-#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
-#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
-#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
-#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
-#define SCSI_Noise__ATN__PS CYREG_PRT12_PS\r
-#define SCSI_Noise__ATN__SHIFT 5\r
-#define SCSI_Noise__ATN__SIO_CFG CYREG_PRT12_SIO_CFG\r
-#define SCSI_Noise__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
-#define SCSI_Noise__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
-#define SCSI_Noise__ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
-#define SCSI_Noise__ATN__SLW CYREG_PRT12_SLW\r
-#define SCSI_Noise__BSY__AG CYREG_PRT6_AG\r
-#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE\r
-#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP\r
-#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL\r
-#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Noise__BSY__DR CYREG_PRT6_DR\r
-#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Noise__BSY__MASK 0x10u\r
-#define SCSI_Noise__BSY__PC CYREG_PRT6_PC4\r
-#define SCSI_Noise__BSY__PORT 6u\r
-#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT\r
-#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Noise__BSY__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__BSY__SHIFT 4\r
-#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW\r
-#define SCSI_Noise__RST__AG CYREG_PRT6_AG\r
-#define SCSI_Noise__RST__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Noise__RST__BIE CYREG_PRT6_BIE\r
-#define SCSI_Noise__RST__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Noise__RST__BYP CYREG_PRT6_BYP\r
-#define SCSI_Noise__RST__CTL CYREG_PRT6_CTL\r
-#define SCSI_Noise__RST__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Noise__RST__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Noise__RST__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Noise__RST__DR CYREG_PRT6_DR\r
-#define SCSI_Noise__RST__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Noise__RST__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Noise__RST__MASK 0x40u\r
-#define SCSI_Noise__RST__PC CYREG_PRT6_PC6\r
-#define SCSI_Noise__RST__PORT 6u\r
-#define SCSI_Noise__RST__PRT CYREG_PRT6_PRT\r
-#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Noise__RST__PS CYREG_PRT6_PS\r
-#define SCSI_Noise__RST__SHIFT 6\r
-#define SCSI_Noise__RST__SLW CYREG_PRT6_SLW\r
-#define SCSI_Noise__SEL__AG CYREG_PRT5_AG\r
-#define SCSI_Noise__SEL__AMUX CYREG_PRT5_AMUX\r
-#define SCSI_Noise__SEL__BIE CYREG_PRT5_BIE\r
-#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT5_BIT_MASK\r
-#define SCSI_Noise__SEL__BYP CYREG_PRT5_BYP\r
-#define SCSI_Noise__SEL__CTL CYREG_PRT5_CTL\r
-#define SCSI_Noise__SEL__DM0 CYREG_PRT5_DM0\r
-#define SCSI_Noise__SEL__DM1 CYREG_PRT5_DM1\r
-#define SCSI_Noise__SEL__DM2 CYREG_PRT5_DM2\r
-#define SCSI_Noise__SEL__DR CYREG_PRT5_DR\r
-#define SCSI_Noise__SEL__INP_DIS CYREG_PRT5_INP_DIS\r
-#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
-#define SCSI_Noise__SEL__LCD_EN CYREG_PRT5_LCD_EN\r
-#define SCSI_Noise__SEL__MASK 0x01u\r
-#define SCSI_Noise__SEL__PC CYREG_PRT5_PC0\r
-#define SCSI_Noise__SEL__PORT 5u\r
-#define SCSI_Noise__SEL__PRT CYREG_PRT5_PRT\r
-#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
-#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
-#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
-#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
-#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
-#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
-#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
-#define SCSI_Noise__SEL__PS CYREG_PRT5_PS\r
-#define SCSI_Noise__SEL__SHIFT 0\r
-#define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW\r
-\r
-/* scsiTarget */\r
-#define scsiTarget_StatusReg__0__MASK 0x01u\r
-#define scsiTarget_StatusReg__0__POS 0\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
-#define scsiTarget_StatusReg__1__MASK 0x02u\r
-#define scsiTarget_StatusReg__1__POS 1\r
-#define scsiTarget_StatusReg__2__MASK 0x04u\r
-#define scsiTarget_StatusReg__2__POS 2\r
-#define scsiTarget_StatusReg__3__MASK 0x08u\r
-#define scsiTarget_StatusReg__3__POS 3\r
-#define scsiTarget_StatusReg__4__MASK 0x10u\r
-#define scsiTarget_StatusReg__4__POS 4\r
-#define scsiTarget_StatusReg__MASK 0x1Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB05_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB05_ST\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST\r
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB01_MSK\r
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB01_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB01_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB01_ST\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL\r
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK\r
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB01_CTL\r
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL\r
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB01_CTL\r
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL\r
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB01_MSK\r
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB01_02_A0\r
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB01_02_A1\r
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB01_02_D0\r
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB01_02_D1\r
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB01_02_F0\r
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB01_02_F1\r
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB01_A0_A1\r
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB01_A0\r
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB01_A1\r
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB01_D0_D1\r
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB01_D0\r
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB01_D1\r
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB01_F0_F1\r
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB01_F0\r
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB01_F1\r
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
-\r
-/* USBFS_ep_0 */\r
-#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_0__INTC_MASK 0x1000000u\r
-#define USBFS_ep_0__INTC_NUMBER 24u\r
-#define USBFS_ep_0__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24\r
-#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_1 */\r
-#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_1__INTC_MASK 0x40u\r
-#define USBFS_ep_1__INTC_NUMBER 6u\r
-#define USBFS_ep_1__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_6\r
-#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_2 */\r
-#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_2__INTC_MASK 0x80u\r
-#define USBFS_ep_2__INTC_NUMBER 7u\r
-#define USBFS_ep_2__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_7\r
-#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_3 */\r
-#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_3__INTC_MASK 0x100u\r
-#define USBFS_ep_3__INTC_NUMBER 8u\r
-#define USBFS_ep_3__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_8\r
-#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_4 */\r
-#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_4__INTC_MASK 0x200u\r
-#define USBFS_ep_4__INTC_NUMBER 9u\r
-#define USBFS_ep_4__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_9\r
-#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SD_RX_DMA */\r
-#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
-#define SD_RX_DMA__DRQ_NUMBER 2u\r
-#define SD_RX_DMA__NUMBEROF_TDS 0u\r
-#define SD_RX_DMA__PRIORITY 1u\r
-#define SD_RX_DMA__TERMIN_EN 0u\r
-#define SD_RX_DMA__TERMIN_SEL 0u\r
-#define SD_RX_DMA__TERMOUT0_EN 1u\r
-#define SD_RX_DMA__TERMOUT0_SEL 2u\r
-#define SD_RX_DMA__TERMOUT1_EN 0u\r
-#define SD_RX_DMA__TERMOUT1_SEL 0u\r
-\r
-/* SD_TX_DMA */\r
-#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
-#define SD_TX_DMA__DRQ_NUMBER 3u\r
-#define SD_TX_DMA__NUMBEROF_TDS 0u\r
-#define SD_TX_DMA__PRIORITY 2u\r
-#define SD_TX_DMA__TERMIN_EN 0u\r
-#define SD_TX_DMA__TERMIN_SEL 0u\r
-#define SD_TX_DMA__TERMOUT0_EN 1u\r
-#define SD_TX_DMA__TERMOUT0_SEL 3u\r
-#define SD_TX_DMA__TERMOUT1_EN 0u\r
-#define SD_TX_DMA__TERMOUT1_SEL 0u\r
-\r
-/* USBFS_USB */\r
-#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG\r
-#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG\r
-#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN\r
-#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR\r
-#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG\r
-#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN\r
-#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR\r
-#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG\r
-#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN\r
-#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR\r
-#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG\r
-#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN\r
-#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR\r
-#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG\r
-#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN\r
-#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR\r
-#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG\r
-#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN\r
-#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR\r
-#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG\r
-#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN\r
-#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR\r
-#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG\r
-#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN\r
-#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR\r
-#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN\r
-#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR\r
-#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR\r
-#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA\r
-#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB\r
-#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA\r
-#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB\r
-#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR\r
-#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA\r
-#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB\r
-#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA\r
-#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB\r
-#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR\r
-#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA\r
-#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB\r
-#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA\r
-#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB\r
-#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR\r
-#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA\r
-#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB\r
-#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA\r
-#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB\r
-#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR\r
-#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA\r
-#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB\r
-#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA\r
-#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB\r
-#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR\r
-#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA\r
-#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB\r
-#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA\r
-#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB\r
-#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR\r
-#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA\r
-#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB\r
-#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA\r
-#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB\r
-#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR\r
-#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA\r
-#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB\r
-#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA\r
-#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB\r
-#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE\r
-#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT\r
-#define USBFS_USB__CR0 CYREG_USB_CR0\r
-#define USBFS_USB__CR1 CYREG_USB_CR1\r
-#define USBFS_USB__CWA CYREG_USB_CWA\r
-#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB\r
-#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES\r
-#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB\r
-#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG\r
-#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT\r
-#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR\r
-#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0\r
-#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1\r
-#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2\r
-#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3\r
-#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4\r
-#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5\r
-#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6\r
-#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7\r
-#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE\r
-#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE\r
-#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE\r
-#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5\r
-#define USBFS_USB__PM_ACT_MSK 0x01u\r
-#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5\r
-#define USBFS_USB__PM_STBY_MSK 0x01u\r
-#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0\r
-#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1\r
-#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0\r
-#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0\r
-#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1\r
-#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0\r
-#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0\r
-#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1\r
-#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0\r
-#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0\r
-#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1\r
-#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0\r
-#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0\r
-#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1\r
-#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0\r
-#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0\r
-#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1\r
-#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0\r
-#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0\r
-#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1\r
-#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0\r
-#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0\r
-#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1\r
-#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0\r
-#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN\r
-#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR\r
-#define USBFS_USB__SOF0 CYREG_USB_SOF0\r
-#define USBFS_USB__SOF1 CYREG_USB_SOF1\r
-#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0\r
-#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
-#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN\r
-\r
-/* SCSI_CLK */\r
-#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0\r
-#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1\r
-#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2\r
-#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u\r
-#define SCSI_CLK__INDEX 0x01u\r
-#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
-#define SCSI_CLK__PM_ACT_MSK 0x02u\r
-#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
-#define SCSI_CLK__PM_STBY_MSK 0x02u\r
-\r
-/* SCSI_Out */\r
-#define SCSI_Out__0__AG CYREG_PRT4_AG\r
-#define SCSI_Out__0__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out__0__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out__0__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out__0__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out__0__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out__0__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out__0__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out__0__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out__0__DR CYREG_PRT4_DR\r
-#define SCSI_Out__0__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out__0__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out__0__MASK 0x08u\r
-#define SCSI_Out__0__PC CYREG_PRT4_PC3\r
-#define SCSI_Out__0__PORT 4u\r
-#define SCSI_Out__0__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out__0__PS CYREG_PRT4_PS\r
-#define SCSI_Out__0__SHIFT 3\r
-#define SCSI_Out__0__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out__1__AG CYREG_PRT4_AG\r
-#define SCSI_Out__1__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out__1__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out__1__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out__1__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out__1__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out__1__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out__1__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out__1__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out__1__DR CYREG_PRT4_DR\r
-#define SCSI_Out__1__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out__1__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out__1__MASK 0x04u\r
-#define SCSI_Out__1__PC CYREG_PRT4_PC2\r
-#define SCSI_Out__1__PORT 4u\r
-#define SCSI_Out__1__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out__1__PS CYREG_PRT4_PS\r
-#define SCSI_Out__1__SHIFT 2\r
-#define SCSI_Out__1__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out__2__AG CYREG_PRT0_AG\r
-#define SCSI_Out__2__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__2__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__2__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__2__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__2__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__2__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__2__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__2__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__2__DR CYREG_PRT0_DR\r
-#define SCSI_Out__2__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__2__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__2__MASK 0x80u\r
-#define SCSI_Out__2__PC CYREG_PRT0_PC7\r
-#define SCSI_Out__2__PORT 0u\r
-#define SCSI_Out__2__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__2__PS CYREG_PRT0_PS\r
-#define SCSI_Out__2__SHIFT 7\r
-#define SCSI_Out__2__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__3__AG CYREG_PRT0_AG\r
-#define SCSI_Out__3__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__3__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__3__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__3__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__3__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__3__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__3__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__3__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__3__DR CYREG_PRT0_DR\r
-#define SCSI_Out__3__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__3__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__3__MASK 0x40u\r
-#define SCSI_Out__3__PC CYREG_PRT0_PC6\r
-#define SCSI_Out__3__PORT 0u\r
-#define SCSI_Out__3__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__3__PS CYREG_PRT0_PS\r
-#define SCSI_Out__3__SHIFT 6\r
-#define SCSI_Out__3__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__4__AG CYREG_PRT0_AG\r
-#define SCSI_Out__4__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__4__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__4__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__4__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__4__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__4__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__4__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__4__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__4__DR CYREG_PRT0_DR\r
-#define SCSI_Out__4__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__4__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__4__MASK 0x20u\r
-#define SCSI_Out__4__PC CYREG_PRT0_PC5\r
-#define SCSI_Out__4__PORT 0u\r
-#define SCSI_Out__4__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__4__PS CYREG_PRT0_PS\r
-#define SCSI_Out__4__SHIFT 5\r
-#define SCSI_Out__4__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__5__AG CYREG_PRT0_AG\r
-#define SCSI_Out__5__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__5__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__5__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__5__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__5__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__5__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__5__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__5__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__5__DR CYREG_PRT0_DR\r
-#define SCSI_Out__5__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__5__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__5__MASK 0x10u\r
-#define SCSI_Out__5__PC CYREG_PRT0_PC4\r
-#define SCSI_Out__5__PORT 0u\r
-#define SCSI_Out__5__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__5__PS CYREG_PRT0_PS\r
-#define SCSI_Out__5__SHIFT 4\r
-#define SCSI_Out__5__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__6__AG CYREG_PRT0_AG\r
-#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__6__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__6__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__6__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__6__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__6__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__6__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__6__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__6__DR CYREG_PRT0_DR\r
-#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__6__MASK 0x08u\r
-#define SCSI_Out__6__PC CYREG_PRT0_PC3\r
-#define SCSI_Out__6__PORT 0u\r
-#define SCSI_Out__6__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__6__PS CYREG_PRT0_PS\r
-#define SCSI_Out__6__SHIFT 3\r
-#define SCSI_Out__6__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__7__AG CYREG_PRT0_AG\r
-#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__7__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__7__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__7__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__7__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__7__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__7__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__7__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__7__DR CYREG_PRT0_DR\r
-#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__7__MASK 0x04u\r
-#define SCSI_Out__7__PC CYREG_PRT0_PC2\r
-#define SCSI_Out__7__PORT 0u\r
-#define SCSI_Out__7__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__7__PS CYREG_PRT0_PS\r
-#define SCSI_Out__7__SHIFT 2\r
-#define SCSI_Out__7__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__8__AG CYREG_PRT0_AG\r
-#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__8__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__8__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__8__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__8__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__8__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__8__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__8__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__8__DR CYREG_PRT0_DR\r
-#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__8__MASK 0x02u\r
-#define SCSI_Out__8__PC CYREG_PRT0_PC1\r
-#define SCSI_Out__8__PORT 0u\r
-#define SCSI_Out__8__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__8__PS CYREG_PRT0_PS\r
-#define SCSI_Out__8__SHIFT 1\r
-#define SCSI_Out__8__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__9__AG CYREG_PRT0_AG\r
-#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__9__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__9__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__9__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__9__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__9__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__9__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__9__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__9__DR CYREG_PRT0_DR\r
-#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__9__MASK 0x01u\r
-#define SCSI_Out__9__PC CYREG_PRT0_PC0\r
-#define SCSI_Out__9__PORT 0u\r
-#define SCSI_Out__9__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__9__PS CYREG_PRT0_PS\r
-#define SCSI_Out__9__SHIFT 0\r
-#define SCSI_Out__9__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__ACK__AG CYREG_PRT0_AG\r
-#define SCSI_Out__ACK__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__ACK__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__ACK__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__ACK__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__ACK__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__ACK__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__ACK__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__ACK__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__ACK__DR CYREG_PRT0_DR\r
-#define SCSI_Out__ACK__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__ACK__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__ACK__MASK 0x40u\r
-#define SCSI_Out__ACK__PC CYREG_PRT0_PC6\r
-#define SCSI_Out__ACK__PORT 0u\r
-#define SCSI_Out__ACK__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__ACK__PS CYREG_PRT0_PS\r
-#define SCSI_Out__ACK__SHIFT 6\r
-#define SCSI_Out__ACK__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__ATN__AG CYREG_PRT4_AG\r
-#define SCSI_Out__ATN__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out__ATN__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out__ATN__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out__ATN__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out__ATN__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out__ATN__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out__ATN__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out__ATN__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out__ATN__DR CYREG_PRT4_DR\r
-#define SCSI_Out__ATN__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out__ATN__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out__ATN__MASK 0x04u\r
-#define SCSI_Out__ATN__PC CYREG_PRT4_PC2\r
-#define SCSI_Out__ATN__PORT 4u\r
-#define SCSI_Out__ATN__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out__ATN__PS CYREG_PRT4_PS\r
-#define SCSI_Out__ATN__SHIFT 2\r
-#define SCSI_Out__ATN__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out__BSY__AG CYREG_PRT0_AG\r
-#define SCSI_Out__BSY__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__BSY__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__BSY__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__BSY__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__BSY__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__BSY__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__BSY__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__BSY__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__BSY__DR CYREG_PRT0_DR\r
-#define SCSI_Out__BSY__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__BSY__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__BSY__MASK 0x80u\r
-#define SCSI_Out__BSY__PC CYREG_PRT0_PC7\r
-#define SCSI_Out__BSY__PORT 0u\r
-#define SCSI_Out__BSY__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__BSY__PS CYREG_PRT0_PS\r
-#define SCSI_Out__BSY__SHIFT 7\r
-#define SCSI_Out__BSY__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG\r
-#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR\r
-#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__CD_raw__MASK 0x04u\r
-#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC2\r
-#define SCSI_Out__CD_raw__PORT 0u\r
-#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS\r
-#define SCSI_Out__CD_raw__SHIFT 2\r
-#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__DBP_raw__AG CYREG_PRT4_AG\r
-#define SCSI_Out__DBP_raw__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out__DBP_raw__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out__DBP_raw__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out__DBP_raw__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out__DBP_raw__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out__DBP_raw__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out__DBP_raw__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out__DBP_raw__DR CYREG_PRT4_DR\r
-#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out__DBP_raw__MASK 0x08u\r
-#define SCSI_Out__DBP_raw__PC CYREG_PRT4_PC3\r
-#define SCSI_Out__DBP_raw__PORT 4u\r
-#define SCSI_Out__DBP_raw__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out__DBP_raw__PS CYREG_PRT4_PS\r
-#define SCSI_Out__DBP_raw__SHIFT 3\r
-#define SCSI_Out__DBP_raw__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG\r
-#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__IO_raw__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__IO_raw__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__IO_raw__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__IO_raw__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__IO_raw__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR\r
-#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__IO_raw__MASK 0x01u\r
-#define SCSI_Out__IO_raw__PC CYREG_PRT0_PC0\r
-#define SCSI_Out__IO_raw__PORT 0u\r
-#define SCSI_Out__IO_raw__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS\r
-#define SCSI_Out__IO_raw__SHIFT 0\r
-#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__MSG_raw__AG CYREG_PRT0_AG\r
-#define SCSI_Out__MSG_raw__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__MSG_raw__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__MSG_raw__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__MSG_raw__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__MSG_raw__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__MSG_raw__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__MSG_raw__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__MSG_raw__DR CYREG_PRT0_DR\r
-#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__MSG_raw__MASK 0x10u\r
-#define SCSI_Out__MSG_raw__PC CYREG_PRT0_PC4\r
-#define SCSI_Out__MSG_raw__PORT 0u\r
-#define SCSI_Out__MSG_raw__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__MSG_raw__PS CYREG_PRT0_PS\r
-#define SCSI_Out__MSG_raw__SHIFT 4\r
-#define SCSI_Out__MSG_raw__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__REQ__AG CYREG_PRT0_AG\r
-#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__REQ__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__REQ__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__REQ__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__REQ__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__REQ__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__REQ__DR CYREG_PRT0_DR\r
-#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__REQ__MASK 0x02u\r
-#define SCSI_Out__REQ__PC CYREG_PRT0_PC1\r
-#define SCSI_Out__REQ__PORT 0u\r
-#define SCSI_Out__REQ__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__REQ__PS CYREG_PRT0_PS\r
-#define SCSI_Out__REQ__SHIFT 1\r
-#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__RST__AG CYREG_PRT0_AG\r
-#define SCSI_Out__RST__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__RST__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__RST__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__RST__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__RST__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__RST__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__RST__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__RST__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__RST__DR CYREG_PRT0_DR\r
-#define SCSI_Out__RST__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__RST__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__RST__MASK 0x20u\r
-#define SCSI_Out__RST__PC CYREG_PRT0_PC5\r
-#define SCSI_Out__RST__PORT 0u\r
-#define SCSI_Out__RST__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__RST__PS CYREG_PRT0_PS\r
-#define SCSI_Out__RST__SHIFT 5\r
-#define SCSI_Out__RST__SLW CYREG_PRT0_SLW\r
-#define SCSI_Out__SEL__AG CYREG_PRT0_AG\r
-#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX\r
-#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE\r
-#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK\r
-#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP\r
-#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL\r
-#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0\r
-#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1\r
-#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2\r
-#define SCSI_Out__SEL__DR CYREG_PRT0_DR\r
-#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS\r
-#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
-#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN\r
-#define SCSI_Out__SEL__MASK 0x08u\r
-#define SCSI_Out__SEL__PC CYREG_PRT0_PC3\r
-#define SCSI_Out__SEL__PORT 0u\r
-#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT\r
-#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
-#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
-#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
-#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
-#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
-#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
-#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
-#define SCSI_Out__SEL__PS CYREG_PRT0_PS\r
-#define SCSI_Out__SEL__SHIFT 3\r
-#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW\r
-\r
-/* USBFS_Dm */\r
-#define USBFS_Dm__0__MASK 0x80u\r
-#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1\r
-#define USBFS_Dm__0__PORT 15u\r
-#define USBFS_Dm__0__SHIFT 7\r
-#define USBFS_Dm__AG CYREG_PRT15_AG\r
-#define USBFS_Dm__AMUX CYREG_PRT15_AMUX\r
-#define USBFS_Dm__BIE CYREG_PRT15_BIE\r
-#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK\r
-#define USBFS_Dm__BYP CYREG_PRT15_BYP\r
-#define USBFS_Dm__CTL CYREG_PRT15_CTL\r
-#define USBFS_Dm__DM0 CYREG_PRT15_DM0\r
-#define USBFS_Dm__DM1 CYREG_PRT15_DM1\r
-#define USBFS_Dm__DM2 CYREG_PRT15_DM2\r
-#define USBFS_Dm__DR CYREG_PRT15_DR\r
-#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS\r
-#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
-#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN\r
-#define USBFS_Dm__MASK 0x80u\r
-#define USBFS_Dm__PORT 15u\r
-#define USBFS_Dm__PRT CYREG_PRT15_PRT\r
-#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
-#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
-#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
-#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
-#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
-#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
-#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
-#define USBFS_Dm__PS CYREG_PRT15_PS\r
-#define USBFS_Dm__SHIFT 7\r
-#define USBFS_Dm__SLW CYREG_PRT15_SLW\r
+/* SDCard_BSPIM */\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
+#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
+#define SDCard_BSPIM_RxStsReg__4__POS 4\r
+#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
+#define SDCard_BSPIM_RxStsReg__5__POS 5\r
+#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
+#define SDCard_BSPIM_RxStsReg__6__POS 6\r
+#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB07_08_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB07_08_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB07_08_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB07_08_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB07_08_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB07_08_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB07_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB07_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB07_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB07_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB07_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB07_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB07_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB07_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB07_F1\r
+#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
+#define SDCard_BSPIM_TxStsReg__0__POS 0\r
+#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
+#define SDCard_BSPIM_TxStsReg__1__POS 1\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
+#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
+#define SDCard_BSPIM_TxStsReg__2__POS 2\r
+#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
+#define SDCard_BSPIM_TxStsReg__3__POS 3\r
+#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
+#define SDCard_BSPIM_TxStsReg__4__POS 4\r
+#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB04_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB04_ST\r
\r
-/* USBFS_Dp */\r
-#define USBFS_Dp__0__MASK 0x40u\r
-#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0\r
-#define USBFS_Dp__0__PORT 15u\r
-#define USBFS_Dp__0__SHIFT 6\r
-#define USBFS_Dp__AG CYREG_PRT15_AG\r
-#define USBFS_Dp__AMUX CYREG_PRT15_AMUX\r
-#define USBFS_Dp__BIE CYREG_PRT15_BIE\r
-#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK\r
-#define USBFS_Dp__BYP CYREG_PRT15_BYP\r
-#define USBFS_Dp__CTL CYREG_PRT15_CTL\r
-#define USBFS_Dp__DM0 CYREG_PRT15_DM0\r
-#define USBFS_Dp__DM1 CYREG_PRT15_DM1\r
-#define USBFS_Dp__DM2 CYREG_PRT15_DM2\r
-#define USBFS_Dp__DR CYREG_PRT15_DR\r
-#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS\r
-#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT\r
-#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
-#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN\r
-#define USBFS_Dp__MASK 0x40u\r
-#define USBFS_Dp__PORT 15u\r
-#define USBFS_Dp__PRT CYREG_PRT15_PRT\r
-#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
-#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
-#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
-#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
-#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
-#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
-#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
-#define USBFS_Dp__PS CYREG_PRT15_PS\r
-#define USBFS_Dp__SHIFT 6\r
-#define USBFS_Dp__SLW CYREG_PRT15_SLW\r
-#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15\r
+/* SD_SCK */\r
+#define SD_SCK__0__MASK 0x04u\r
+#define SD_SCK__0__PC CYREG_PRT3_PC2\r
+#define SD_SCK__0__PORT 3u\r
+#define SD_SCK__0__SHIFT 2\r
+#define SD_SCK__AG CYREG_PRT3_AG\r
+#define SD_SCK__AMUX CYREG_PRT3_AMUX\r
+#define SD_SCK__BIE CYREG_PRT3_BIE\r
+#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_SCK__BYP CYREG_PRT3_BYP\r
+#define SD_SCK__CTL CYREG_PRT3_CTL\r
+#define SD_SCK__DM0 CYREG_PRT3_DM0\r
+#define SD_SCK__DM1 CYREG_PRT3_DM1\r
+#define SD_SCK__DM2 CYREG_PRT3_DM2\r
+#define SD_SCK__DR CYREG_PRT3_DR\r
+#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_SCK__MASK 0x04u\r
+#define SD_SCK__PORT 3u\r
+#define SD_SCK__PRT CYREG_PRT3_PRT\r
+#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_SCK__PS CYREG_PRT3_PS\r
+#define SD_SCK__SHIFT 2\r
+#define SD_SCK__SLW CYREG_PRT3_SLW\r
\r
/* SCSI_In */\r
#define SCSI_In__0__AG CYREG_PRT2_AG\r
#define SCSI_In__REQ__SHIFT 2\r
#define SCSI_In__REQ__SLW CYREG_PRT5_SLW\r
\r
-/* SD_DAT1 */\r
-#define SD_DAT1__0__MASK 0x01u\r
-#define SD_DAT1__0__PC CYREG_PRT3_PC0\r
-#define SD_DAT1__0__PORT 3u\r
-#define SD_DAT1__0__SHIFT 0\r
-#define SD_DAT1__AG CYREG_PRT3_AG\r
-#define SD_DAT1__AMUX CYREG_PRT3_AMUX\r
-#define SD_DAT1__BIE CYREG_PRT3_BIE\r
-#define SD_DAT1__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_DAT1__BYP CYREG_PRT3_BYP\r
-#define SD_DAT1__CTL CYREG_PRT3_CTL\r
-#define SD_DAT1__DM0 CYREG_PRT3_DM0\r
-#define SD_DAT1__DM1 CYREG_PRT3_DM1\r
-#define SD_DAT1__DM2 CYREG_PRT3_DM2\r
-#define SD_DAT1__DR CYREG_PRT3_DR\r
-#define SD_DAT1__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_DAT1__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_DAT1__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_DAT1__MASK 0x01u\r
-#define SD_DAT1__PORT 3u\r
-#define SD_DAT1__PRT CYREG_PRT3_PRT\r
-#define SD_DAT1__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_DAT1__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_DAT1__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_DAT1__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_DAT1__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_DAT1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_DAT1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_DAT1__PS CYREG_PRT3_PS\r
-#define SD_DAT1__SHIFT 0\r
-#define SD_DAT1__SLW CYREG_PRT3_SLW\r
+/* SCSI_In_DBx */\r
+#define SCSI_In_DBx__0__AG CYREG_PRT12_AG\r
+#define SCSI_In_DBx__0__BIE CYREG_PRT12_BIE\r
+#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_In_DBx__0__BYP CYREG_PRT12_BYP\r
+#define SCSI_In_DBx__0__DM0 CYREG_PRT12_DM0\r
+#define SCSI_In_DBx__0__DM1 CYREG_PRT12_DM1\r
+#define SCSI_In_DBx__0__DM2 CYREG_PRT12_DM2\r
+#define SCSI_In_DBx__0__DR CYREG_PRT12_DR\r
+#define SCSI_In_DBx__0__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_In_DBx__0__MASK 0x10u\r
+#define SCSI_In_DBx__0__PC CYREG_PRT12_PC4\r
+#define SCSI_In_DBx__0__PORT 12u\r
+#define SCSI_In_DBx__0__PRT CYREG_PRT12_PRT\r
+#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_In_DBx__0__PS CYREG_PRT12_PS\r
+#define SCSI_In_DBx__0__SHIFT 4\r
+#define SCSI_In_DBx__0__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_In_DBx__0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_In_DBx__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_In_DBx__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_In_DBx__0__SLW CYREG_PRT12_SLW\r
+#define SCSI_In_DBx__1__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__1__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__1__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__1__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__1__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__1__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__1__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__1__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__1__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__1__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__1__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__1__MASK 0x80u\r
+#define SCSI_In_DBx__1__PC CYREG_PRT2_PC7\r
+#define SCSI_In_DBx__1__PORT 2u\r
+#define SCSI_In_DBx__1__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__1__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__1__SHIFT 7\r
+#define SCSI_In_DBx__1__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__2__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__2__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__2__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__2__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__2__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__2__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__2__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__2__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__2__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__2__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__2__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__2__MASK 0x40u\r
+#define SCSI_In_DBx__2__PC CYREG_PRT2_PC6\r
+#define SCSI_In_DBx__2__PORT 2u\r
+#define SCSI_In_DBx__2__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__2__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__2__SHIFT 6\r
+#define SCSI_In_DBx__2__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__3__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__3__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__3__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__3__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__3__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__3__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__3__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__3__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__3__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__3__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__3__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__3__MASK 0x20u\r
+#define SCSI_In_DBx__3__PC CYREG_PRT2_PC5\r
+#define SCSI_In_DBx__3__PORT 2u\r
+#define SCSI_In_DBx__3__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__3__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__3__SHIFT 5\r
+#define SCSI_In_DBx__3__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__4__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__4__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__4__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__4__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__4__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__4__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__4__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__4__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__4__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__4__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__4__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__4__MASK 0x10u\r
+#define SCSI_In_DBx__4__PC CYREG_PRT2_PC4\r
+#define SCSI_In_DBx__4__PORT 2u\r
+#define SCSI_In_DBx__4__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__4__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__4__SHIFT 4\r
+#define SCSI_In_DBx__4__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__5__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__5__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__5__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__5__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__5__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__5__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__5__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__5__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__5__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__5__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__5__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__5__MASK 0x08u\r
+#define SCSI_In_DBx__5__PC CYREG_PRT2_PC3\r
+#define SCSI_In_DBx__5__PORT 2u\r
+#define SCSI_In_DBx__5__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__5__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__5__SHIFT 3\r
+#define SCSI_In_DBx__5__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__6__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__6__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__6__MASK 0x04u\r
+#define SCSI_In_DBx__6__PC CYREG_PRT2_PC2\r
+#define SCSI_In_DBx__6__PORT 2u\r
+#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__6__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__6__SHIFT 2\r
+#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__7__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__7__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__7__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__7__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__7__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__7__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__7__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__7__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__7__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__7__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__7__MASK 0x02u\r
+#define SCSI_In_DBx__7__PC CYREG_PRT2_PC1\r
+#define SCSI_In_DBx__7__PORT 2u\r
+#define SCSI_In_DBx__7__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__7__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__7__SHIFT 1\r
+#define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB0__AG CYREG_PRT12_AG\r
+#define SCSI_In_DBx__DB0__BIE CYREG_PRT12_BIE\r
+#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_In_DBx__DB0__BYP CYREG_PRT12_BYP\r
+#define SCSI_In_DBx__DB0__DM0 CYREG_PRT12_DM0\r
+#define SCSI_In_DBx__DB0__DM1 CYREG_PRT12_DM1\r
+#define SCSI_In_DBx__DB0__DM2 CYREG_PRT12_DM2\r
+#define SCSI_In_DBx__DB0__DR CYREG_PRT12_DR\r
+#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_In_DBx__DB0__MASK 0x10u\r
+#define SCSI_In_DBx__DB0__PC CYREG_PRT12_PC4\r
+#define SCSI_In_DBx__DB0__PORT 12u\r
+#define SCSI_In_DBx__DB0__PRT CYREG_PRT12_PRT\r
+#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_In_DBx__DB0__PS CYREG_PRT12_PS\r
+#define SCSI_In_DBx__DB0__SHIFT 4\r
+#define SCSI_In_DBx__DB0__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_In_DBx__DB0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_In_DBx__DB0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_In_DBx__DB0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_In_DBx__DB0__SLW CYREG_PRT12_SLW\r
+#define SCSI_In_DBx__DB1__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB1__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB1__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB1__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB1__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB1__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB1__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB1__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB1__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB1__MASK 0x80u\r
+#define SCSI_In_DBx__DB1__PC CYREG_PRT2_PC7\r
+#define SCSI_In_DBx__DB1__PORT 2u\r
+#define SCSI_In_DBx__DB1__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB1__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB1__SHIFT 7\r
+#define SCSI_In_DBx__DB1__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB2__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB2__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB2__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB2__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB2__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB2__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB2__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB2__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB2__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB2__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB2__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB2__MASK 0x40u\r
+#define SCSI_In_DBx__DB2__PC CYREG_PRT2_PC6\r
+#define SCSI_In_DBx__DB2__PORT 2u\r
+#define SCSI_In_DBx__DB2__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB2__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB2__SHIFT 6\r
+#define SCSI_In_DBx__DB2__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB3__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB3__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB3__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB3__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB3__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB3__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB3__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB3__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB3__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB3__MASK 0x20u\r
+#define SCSI_In_DBx__DB3__PC CYREG_PRT2_PC5\r
+#define SCSI_In_DBx__DB3__PORT 2u\r
+#define SCSI_In_DBx__DB3__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB3__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB3__SHIFT 5\r
+#define SCSI_In_DBx__DB3__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB4__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB4__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB4__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB4__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB4__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB4__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB4__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB4__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB4__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB4__MASK 0x10u\r
+#define SCSI_In_DBx__DB4__PC CYREG_PRT2_PC4\r
+#define SCSI_In_DBx__DB4__PORT 2u\r
+#define SCSI_In_DBx__DB4__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB4__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB4__SHIFT 4\r
+#define SCSI_In_DBx__DB4__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB5__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB5__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB5__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB5__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB5__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB5__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB5__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB5__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB5__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB5__MASK 0x08u\r
+#define SCSI_In_DBx__DB5__PC CYREG_PRT2_PC3\r
+#define SCSI_In_DBx__DB5__PORT 2u\r
+#define SCSI_In_DBx__DB5__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB5__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB5__SHIFT 3\r
+#define SCSI_In_DBx__DB5__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB6__MASK 0x04u\r
+#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC2\r
+#define SCSI_In_DBx__DB6__PORT 2u\r
+#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB6__SHIFT 2\r
+#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW\r
+#define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__DB7__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__DB7__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__DB7__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DB7__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DB7__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DB7__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DB7__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__DB7__MASK 0x02u\r
+#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC1\r
+#define SCSI_In_DBx__DB7__PORT 2u\r
+#define SCSI_In_DBx__DB7__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__DB7__SHIFT 1\r
+#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW\r
+\r
+/* SD_DAT1 */\r
+#define SD_DAT1__0__MASK 0x01u\r
+#define SD_DAT1__0__PC CYREG_PRT3_PC0\r
+#define SD_DAT1__0__PORT 3u\r
+#define SD_DAT1__0__SHIFT 0\r
+#define SD_DAT1__AG CYREG_PRT3_AG\r
+#define SD_DAT1__AMUX CYREG_PRT3_AMUX\r
+#define SD_DAT1__BIE CYREG_PRT3_BIE\r
+#define SD_DAT1__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_DAT1__BYP CYREG_PRT3_BYP\r
+#define SD_DAT1__CTL CYREG_PRT3_CTL\r
+#define SD_DAT1__DM0 CYREG_PRT3_DM0\r
+#define SD_DAT1__DM1 CYREG_PRT3_DM1\r
+#define SD_DAT1__DM2 CYREG_PRT3_DM2\r
+#define SD_DAT1__DR CYREG_PRT3_DR\r
+#define SD_DAT1__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_DAT1__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_DAT1__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_DAT1__MASK 0x01u\r
+#define SD_DAT1__PORT 3u\r
+#define SD_DAT1__PRT CYREG_PRT3_PRT\r
+#define SD_DAT1__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_DAT1__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_DAT1__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_DAT1__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_DAT1__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_DAT1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_DAT1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_DAT1__PS CYREG_PRT3_PS\r
+#define SD_DAT1__SHIFT 0\r
+#define SD_DAT1__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_DAT2 */\r
+#define SD_DAT2__0__MASK 0x20u\r
+#define SD_DAT2__0__PC CYREG_PRT3_PC5\r
+#define SD_DAT2__0__PORT 3u\r
+#define SD_DAT2__0__SHIFT 5\r
+#define SD_DAT2__AG CYREG_PRT3_AG\r
+#define SD_DAT2__AMUX CYREG_PRT3_AMUX\r
+#define SD_DAT2__BIE CYREG_PRT3_BIE\r
+#define SD_DAT2__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_DAT2__BYP CYREG_PRT3_BYP\r
+#define SD_DAT2__CTL CYREG_PRT3_CTL\r
+#define SD_DAT2__DM0 CYREG_PRT3_DM0\r
+#define SD_DAT2__DM1 CYREG_PRT3_DM1\r
+#define SD_DAT2__DM2 CYREG_PRT3_DM2\r
+#define SD_DAT2__DR CYREG_PRT3_DR\r
+#define SD_DAT2__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_DAT2__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_DAT2__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_DAT2__MASK 0x20u\r
+#define SD_DAT2__PORT 3u\r
+#define SD_DAT2__PRT CYREG_PRT3_PRT\r
+#define SD_DAT2__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_DAT2__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_DAT2__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_DAT2__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_DAT2__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_DAT2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_DAT2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_DAT2__PS CYREG_PRT3_PS\r
+#define SD_DAT2__SHIFT 5\r
+#define SD_DAT2__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_MISO */\r
+#define SD_MISO__0__MASK 0x02u\r
+#define SD_MISO__0__PC CYREG_PRT3_PC1\r
+#define SD_MISO__0__PORT 3u\r
+#define SD_MISO__0__SHIFT 1\r
+#define SD_MISO__AG CYREG_PRT3_AG\r
+#define SD_MISO__AMUX CYREG_PRT3_AMUX\r
+#define SD_MISO__BIE CYREG_PRT3_BIE\r
+#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_MISO__BYP CYREG_PRT3_BYP\r
+#define SD_MISO__CTL CYREG_PRT3_CTL\r
+#define SD_MISO__DM0 CYREG_PRT3_DM0\r
+#define SD_MISO__DM1 CYREG_PRT3_DM1\r
+#define SD_MISO__DM2 CYREG_PRT3_DM2\r
+#define SD_MISO__DR CYREG_PRT3_DR\r
+#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_MISO__MASK 0x02u\r
+#define SD_MISO__PORT 3u\r
+#define SD_MISO__PRT CYREG_PRT3_PRT\r
+#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_MISO__PS CYREG_PRT3_PS\r
+#define SD_MISO__SHIFT 1\r
+#define SD_MISO__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_MOSI */\r
+#define SD_MOSI__0__MASK 0x08u\r
+#define SD_MOSI__0__PC CYREG_PRT3_PC3\r
+#define SD_MOSI__0__PORT 3u\r
+#define SD_MOSI__0__SHIFT 3\r
+#define SD_MOSI__AG CYREG_PRT3_AG\r
+#define SD_MOSI__AMUX CYREG_PRT3_AMUX\r
+#define SD_MOSI__BIE CYREG_PRT3_BIE\r
+#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_MOSI__BYP CYREG_PRT3_BYP\r
+#define SD_MOSI__CTL CYREG_PRT3_CTL\r
+#define SD_MOSI__DM0 CYREG_PRT3_DM0\r
+#define SD_MOSI__DM1 CYREG_PRT3_DM1\r
+#define SD_MOSI__DM2 CYREG_PRT3_DM2\r
+#define SD_MOSI__DR CYREG_PRT3_DR\r
+#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_MOSI__MASK 0x08u\r
+#define SD_MOSI__PORT 3u\r
+#define SD_MOSI__PRT CYREG_PRT3_PRT\r
+#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_MOSI__PS CYREG_PRT3_PS\r
+#define SD_MOSI__SHIFT 3\r
+#define SD_MOSI__SLW CYREG_PRT3_SLW\r
+\r
+/* SCSI_CLK */\r
+#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0\r
+#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1\r
+#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2\r
+#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u\r
+#define SCSI_CLK__INDEX 0x01u\r
+#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
+#define SCSI_CLK__PM_ACT_MSK 0x02u\r
+#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
+#define SCSI_CLK__PM_STBY_MSK 0x02u\r
+\r
+/* SCSI_Out */\r
+#define SCSI_Out__0__AG CYREG_PRT4_AG\r
+#define SCSI_Out__0__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__0__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__0__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__0__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__0__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__0__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__0__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__0__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__0__DR CYREG_PRT4_DR\r
+#define SCSI_Out__0__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__0__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__0__MASK 0x08u\r
+#define SCSI_Out__0__PC CYREG_PRT4_PC3\r
+#define SCSI_Out__0__PORT 4u\r
+#define SCSI_Out__0__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__0__PS CYREG_PRT4_PS\r
+#define SCSI_Out__0__SHIFT 3\r
+#define SCSI_Out__0__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__1__AG CYREG_PRT4_AG\r
+#define SCSI_Out__1__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__1__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__1__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__1__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__1__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__1__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__1__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__1__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__1__DR CYREG_PRT4_DR\r
+#define SCSI_Out__1__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__1__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__1__MASK 0x04u\r
+#define SCSI_Out__1__PC CYREG_PRT4_PC2\r
+#define SCSI_Out__1__PORT 4u\r
+#define SCSI_Out__1__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__1__PS CYREG_PRT4_PS\r
+#define SCSI_Out__1__SHIFT 2\r
+#define SCSI_Out__1__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__2__AG CYREG_PRT0_AG\r
+#define SCSI_Out__2__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__2__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__2__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__2__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__2__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__2__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__2__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__2__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__2__DR CYREG_PRT0_DR\r
+#define SCSI_Out__2__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__2__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__2__MASK 0x80u\r
+#define SCSI_Out__2__PC CYREG_PRT0_PC7\r
+#define SCSI_Out__2__PORT 0u\r
+#define SCSI_Out__2__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__2__PS CYREG_PRT0_PS\r
+#define SCSI_Out__2__SHIFT 7\r
+#define SCSI_Out__2__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__3__AG CYREG_PRT0_AG\r
+#define SCSI_Out__3__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__3__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__3__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__3__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__3__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__3__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__3__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__3__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__3__DR CYREG_PRT0_DR\r
+#define SCSI_Out__3__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__3__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__3__MASK 0x40u\r
+#define SCSI_Out__3__PC CYREG_PRT0_PC6\r
+#define SCSI_Out__3__PORT 0u\r
+#define SCSI_Out__3__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__3__PS CYREG_PRT0_PS\r
+#define SCSI_Out__3__SHIFT 6\r
+#define SCSI_Out__3__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__4__AG CYREG_PRT0_AG\r
+#define SCSI_Out__4__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__4__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__4__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__4__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__4__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__4__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__4__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__4__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__4__DR CYREG_PRT0_DR\r
+#define SCSI_Out__4__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__4__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__4__MASK 0x20u\r
+#define SCSI_Out__4__PC CYREG_PRT0_PC5\r
+#define SCSI_Out__4__PORT 0u\r
+#define SCSI_Out__4__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__4__PS CYREG_PRT0_PS\r
+#define SCSI_Out__4__SHIFT 5\r
+#define SCSI_Out__4__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__5__AG CYREG_PRT0_AG\r
+#define SCSI_Out__5__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__5__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__5__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__5__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__5__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__5__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__5__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__5__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__5__DR CYREG_PRT0_DR\r
+#define SCSI_Out__5__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__5__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__5__MASK 0x10u\r
+#define SCSI_Out__5__PC CYREG_PRT0_PC4\r
+#define SCSI_Out__5__PORT 0u\r
+#define SCSI_Out__5__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__5__PS CYREG_PRT0_PS\r
+#define SCSI_Out__5__SHIFT 4\r
+#define SCSI_Out__5__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__6__AG CYREG_PRT0_AG\r
+#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__6__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__6__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__6__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__6__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__6__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__6__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__6__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__6__DR CYREG_PRT0_DR\r
+#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__6__MASK 0x08u\r
+#define SCSI_Out__6__PC CYREG_PRT0_PC3\r
+#define SCSI_Out__6__PORT 0u\r
+#define SCSI_Out__6__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__6__PS CYREG_PRT0_PS\r
+#define SCSI_Out__6__SHIFT 3\r
+#define SCSI_Out__6__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__7__AG CYREG_PRT0_AG\r
+#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__7__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__7__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__7__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__7__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__7__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__7__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__7__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__7__DR CYREG_PRT0_DR\r
+#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__7__MASK 0x04u\r
+#define SCSI_Out__7__PC CYREG_PRT0_PC2\r
+#define SCSI_Out__7__PORT 0u\r
+#define SCSI_Out__7__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__7__PS CYREG_PRT0_PS\r
+#define SCSI_Out__7__SHIFT 2\r
+#define SCSI_Out__7__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__8__AG CYREG_PRT0_AG\r
+#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__8__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__8__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__8__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__8__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__8__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__8__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__8__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__8__DR CYREG_PRT0_DR\r
+#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__8__MASK 0x02u\r
+#define SCSI_Out__8__PC CYREG_PRT0_PC1\r
+#define SCSI_Out__8__PORT 0u\r
+#define SCSI_Out__8__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__8__PS CYREG_PRT0_PS\r
+#define SCSI_Out__8__SHIFT 1\r
+#define SCSI_Out__8__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__9__AG CYREG_PRT0_AG\r
+#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__9__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__9__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__9__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__9__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__9__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__9__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__9__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__9__DR CYREG_PRT0_DR\r
+#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__9__MASK 0x01u\r
+#define SCSI_Out__9__PC CYREG_PRT0_PC0\r
+#define SCSI_Out__9__PORT 0u\r
+#define SCSI_Out__9__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__9__PS CYREG_PRT0_PS\r
+#define SCSI_Out__9__SHIFT 0\r
+#define SCSI_Out__9__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__ACK__AG CYREG_PRT0_AG\r
+#define SCSI_Out__ACK__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__ACK__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__ACK__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__ACK__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__ACK__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__ACK__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__ACK__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__ACK__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__ACK__DR CYREG_PRT0_DR\r
+#define SCSI_Out__ACK__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__ACK__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__ACK__MASK 0x40u\r
+#define SCSI_Out__ACK__PC CYREG_PRT0_PC6\r
+#define SCSI_Out__ACK__PORT 0u\r
+#define SCSI_Out__ACK__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__ACK__PS CYREG_PRT0_PS\r
+#define SCSI_Out__ACK__SHIFT 6\r
+#define SCSI_Out__ACK__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__ATN__AG CYREG_PRT4_AG\r
+#define SCSI_Out__ATN__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__ATN__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__ATN__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__ATN__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__ATN__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__ATN__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__ATN__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__ATN__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__ATN__DR CYREG_PRT4_DR\r
+#define SCSI_Out__ATN__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__ATN__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__ATN__MASK 0x04u\r
+#define SCSI_Out__ATN__PC CYREG_PRT4_PC2\r
+#define SCSI_Out__ATN__PORT 4u\r
+#define SCSI_Out__ATN__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__ATN__PS CYREG_PRT4_PS\r
+#define SCSI_Out__ATN__SHIFT 2\r
+#define SCSI_Out__ATN__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__BSY__AG CYREG_PRT0_AG\r
+#define SCSI_Out__BSY__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__BSY__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__BSY__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__BSY__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__BSY__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__BSY__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__BSY__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__BSY__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__BSY__DR CYREG_PRT0_DR\r
+#define SCSI_Out__BSY__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__BSY__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__BSY__MASK 0x80u\r
+#define SCSI_Out__BSY__PC CYREG_PRT0_PC7\r
+#define SCSI_Out__BSY__PORT 0u\r
+#define SCSI_Out__BSY__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__BSY__PS CYREG_PRT0_PS\r
+#define SCSI_Out__BSY__SHIFT 7\r
+#define SCSI_Out__BSY__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG\r
+#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR\r
+#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__CD_raw__MASK 0x04u\r
+#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC2\r
+#define SCSI_Out__CD_raw__PORT 0u\r
+#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS\r
+#define SCSI_Out__CD_raw__SHIFT 2\r
+#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__DBP_raw__AG CYREG_PRT4_AG\r
+#define SCSI_Out__DBP_raw__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__DBP_raw__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__DBP_raw__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__DBP_raw__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__DBP_raw__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__DBP_raw__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__DBP_raw__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__DBP_raw__DR CYREG_PRT4_DR\r
+#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__DBP_raw__MASK 0x08u\r
+#define SCSI_Out__DBP_raw__PC CYREG_PRT4_PC3\r
+#define SCSI_Out__DBP_raw__PORT 4u\r
+#define SCSI_Out__DBP_raw__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__DBP_raw__PS CYREG_PRT4_PS\r
+#define SCSI_Out__DBP_raw__SHIFT 3\r
+#define SCSI_Out__DBP_raw__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG\r
+#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__IO_raw__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__IO_raw__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__IO_raw__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__IO_raw__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__IO_raw__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR\r
+#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__IO_raw__MASK 0x01u\r
+#define SCSI_Out__IO_raw__PC CYREG_PRT0_PC0\r
+#define SCSI_Out__IO_raw__PORT 0u\r
+#define SCSI_Out__IO_raw__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS\r
+#define SCSI_Out__IO_raw__SHIFT 0\r
+#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__MSG_raw__AG CYREG_PRT0_AG\r
+#define SCSI_Out__MSG_raw__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__MSG_raw__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__MSG_raw__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__MSG_raw__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__MSG_raw__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__MSG_raw__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__MSG_raw__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__MSG_raw__DR CYREG_PRT0_DR\r
+#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__MSG_raw__MASK 0x10u\r
+#define SCSI_Out__MSG_raw__PC CYREG_PRT0_PC4\r
+#define SCSI_Out__MSG_raw__PORT 0u\r
+#define SCSI_Out__MSG_raw__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__MSG_raw__PS CYREG_PRT0_PS\r
+#define SCSI_Out__MSG_raw__SHIFT 4\r
+#define SCSI_Out__MSG_raw__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__REQ__AG CYREG_PRT0_AG\r
+#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__REQ__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__REQ__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__REQ__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__REQ__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__REQ__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__REQ__DR CYREG_PRT0_DR\r
+#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__REQ__MASK 0x02u\r
+#define SCSI_Out__REQ__PC CYREG_PRT0_PC1\r
+#define SCSI_Out__REQ__PORT 0u\r
+#define SCSI_Out__REQ__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__REQ__PS CYREG_PRT0_PS\r
+#define SCSI_Out__REQ__SHIFT 1\r
+#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__RST__AG CYREG_PRT0_AG\r
+#define SCSI_Out__RST__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__RST__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__RST__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__RST__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__RST__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__RST__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__RST__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__RST__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__RST__DR CYREG_PRT0_DR\r
+#define SCSI_Out__RST__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__RST__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__RST__MASK 0x20u\r
+#define SCSI_Out__RST__PC CYREG_PRT0_PC5\r
+#define SCSI_Out__RST__PORT 0u\r
+#define SCSI_Out__RST__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__RST__PS CYREG_PRT0_PS\r
+#define SCSI_Out__RST__SHIFT 5\r
+#define SCSI_Out__RST__SLW CYREG_PRT0_SLW\r
+#define SCSI_Out__SEL__AG CYREG_PRT0_AG\r
+#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out__SEL__DR CYREG_PRT0_DR\r
+#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out__SEL__MASK 0x08u\r
+#define SCSI_Out__SEL__PC CYREG_PRT0_PC3\r
+#define SCSI_Out__SEL__PORT 0u\r
+#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out__SEL__PS CYREG_PRT0_PS\r
+#define SCSI_Out__SEL__SHIFT 3\r
+#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW\r
+\r
+/* SCSI_Out_Bits */\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
+\r
+/* SCSI_Out_Ctl */\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK\r
+\r
+/* SCSI_Out_DBx */\r
+#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__0__MASK 0x08u\r
+#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC3\r
+#define SCSI_Out_DBx__0__PORT 6u\r
+#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__0__SHIFT 3\r
+#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__1__MASK 0x04u\r
+#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC2\r
+#define SCSI_Out_DBx__1__PORT 6u\r
+#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__1__SHIFT 2\r
+#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__2__MASK 0x02u\r
+#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC1\r
+#define SCSI_Out_DBx__2__PORT 6u\r
+#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__2__SHIFT 1\r
+#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__3__MASK 0x01u\r
+#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC0\r
+#define SCSI_Out_DBx__3__PORT 6u\r
+#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__3__SHIFT 0\r
+#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__4__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__4__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__4__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__4__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__4__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__4__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__4__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__4__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__4__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__4__MASK 0x80u\r
+#define SCSI_Out_DBx__4__PC CYREG_PRT4_PC7\r
+#define SCSI_Out_DBx__4__PORT 4u\r
+#define SCSI_Out_DBx__4__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__4__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__4__SHIFT 7\r
+#define SCSI_Out_DBx__4__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__5__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__5__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__5__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__5__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__5__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__5__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__5__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__5__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__5__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__5__MASK 0x40u\r
+#define SCSI_Out_DBx__5__PC CYREG_PRT4_PC6\r
+#define SCSI_Out_DBx__5__PORT 4u\r
+#define SCSI_Out_DBx__5__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__5__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__5__SHIFT 6\r
+#define SCSI_Out_DBx__5__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__6__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__6__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__6__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__6__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__6__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__6__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__6__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__6__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__6__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__6__MASK 0x20u\r
+#define SCSI_Out_DBx__6__PC CYREG_PRT4_PC5\r
+#define SCSI_Out_DBx__6__PORT 4u\r
+#define SCSI_Out_DBx__6__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__6__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__6__SHIFT 5\r
+#define SCSI_Out_DBx__6__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__7__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__7__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__7__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__7__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__7__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__7__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__7__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__7__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__7__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__7__MASK 0x10u\r
+#define SCSI_Out_DBx__7__PC CYREG_PRT4_PC4\r
+#define SCSI_Out_DBx__7__PORT 4u\r
+#define SCSI_Out_DBx__7__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__7__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__7__SHIFT 4\r
+#define SCSI_Out_DBx__7__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__DB0__MASK 0x08u\r
+#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC3\r
+#define SCSI_Out_DBx__DB0__PORT 6u\r
+#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__DB0__SHIFT 3\r
+#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__DB1__MASK 0x04u\r
+#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC2\r
+#define SCSI_Out_DBx__DB1__PORT 6u\r
+#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__DB1__SHIFT 2\r
+#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__DB2__MASK 0x02u\r
+#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC1\r
+#define SCSI_Out_DBx__DB2__PORT 6u\r
+#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__DB2__SHIFT 1\r
+#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__DB3__MASK 0x01u\r
+#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC0\r
+#define SCSI_Out_DBx__DB3__PORT 6u\r
+#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__DB3__SHIFT 0\r
+#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__DB4__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__DB4__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__DB4__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__DB4__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__DB4__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__DB4__MASK 0x80u\r
+#define SCSI_Out_DBx__DB4__PC CYREG_PRT4_PC7\r
+#define SCSI_Out_DBx__DB4__PORT 4u\r
+#define SCSI_Out_DBx__DB4__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__DB4__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__DB4__SHIFT 7\r
+#define SCSI_Out_DBx__DB4__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__DB5__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__DB5__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__DB5__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__DB5__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__DB5__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__DB5__MASK 0x40u\r
+#define SCSI_Out_DBx__DB5__PC CYREG_PRT4_PC6\r
+#define SCSI_Out_DBx__DB5__PORT 4u\r
+#define SCSI_Out_DBx__DB5__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__DB5__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__DB5__SHIFT 6\r
+#define SCSI_Out_DBx__DB5__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__DB6__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__DB6__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__DB6__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__DB6__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__DB6__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__DB6__MASK 0x20u\r
+#define SCSI_Out_DBx__DB6__PC CYREG_PRT4_PC5\r
+#define SCSI_Out_DBx__DB6__PORT 4u\r
+#define SCSI_Out_DBx__DB6__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__DB6__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__DB6__SHIFT 5\r
+#define SCSI_Out_DBx__DB6__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__DB7__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__DB7__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__DB7__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__DB7__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__DB7__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__DB7__MASK 0x10u\r
+#define SCSI_Out_DBx__DB7__PC CYREG_PRT4_PC4\r
+#define SCSI_Out_DBx__DB7__PORT 4u\r
+#define SCSI_Out_DBx__DB7__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__DB7__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__DB7__SHIFT 4\r
+#define SCSI_Out_DBx__DB7__SLW CYREG_PRT4_SLW\r
+\r
+/* SD_RX_DMA */\r
+#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SD_RX_DMA__DRQ_NUMBER 2u\r
+#define SD_RX_DMA__NUMBEROF_TDS 0u\r
+#define SD_RX_DMA__PRIORITY 2u\r
+#define SD_RX_DMA__TERMIN_EN 0u\r
+#define SD_RX_DMA__TERMIN_SEL 0u\r
+#define SD_RX_DMA__TERMOUT0_EN 1u\r
+#define SD_RX_DMA__TERMOUT0_SEL 2u\r
+#define SD_RX_DMA__TERMOUT1_EN 0u\r
+#define SD_RX_DMA__TERMOUT1_SEL 0u\r
+\r
+/* SD_RX_DMA_COMPLETE */\r
+#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SD_RX_DMA_COMPLETE__INTC_MASK 0x10u\r
+#define SD_RX_DMA_COMPLETE__INTC_NUMBER 4u\r
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4\r
+#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SD_TX_DMA */\r
+#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SD_TX_DMA__DRQ_NUMBER 3u\r
+#define SD_TX_DMA__NUMBEROF_TDS 0u\r
+#define SD_TX_DMA__PRIORITY 2u\r
+#define SD_TX_DMA__TERMIN_EN 0u\r
+#define SD_TX_DMA__TERMIN_SEL 0u\r
+#define SD_TX_DMA__TERMOUT0_EN 1u\r
+#define SD_TX_DMA__TERMOUT0_SEL 3u\r
+#define SD_TX_DMA__TERMOUT1_EN 0u\r
+#define SD_TX_DMA__TERMOUT1_SEL 0u\r
+\r
+/* SD_TX_DMA_COMPLETE */\r
+#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SD_TX_DMA_COMPLETE__INTC_MASK 0x20u\r
+#define SD_TX_DMA_COMPLETE__INTC_NUMBER 5u\r
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5\r
+#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_Noise */\r
+#define SCSI_Noise__0__AG CYREG_PRT12_AG\r
+#define SCSI_Noise__0__BIE CYREG_PRT12_BIE\r
+#define SCSI_Noise__0__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_Noise__0__BYP CYREG_PRT12_BYP\r
+#define SCSI_Noise__0__DM0 CYREG_PRT12_DM0\r
+#define SCSI_Noise__0__DM1 CYREG_PRT12_DM1\r
+#define SCSI_Noise__0__DM2 CYREG_PRT12_DM2\r
+#define SCSI_Noise__0__DR CYREG_PRT12_DR\r
+#define SCSI_Noise__0__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_Noise__0__MASK 0x20u\r
+#define SCSI_Noise__0__PC CYREG_PRT12_PC5\r
+#define SCSI_Noise__0__PORT 12u\r
+#define SCSI_Noise__0__PRT CYREG_PRT12_PRT\r
+#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_Noise__0__PS CYREG_PRT12_PS\r
+#define SCSI_Noise__0__SHIFT 5\r
+#define SCSI_Noise__0__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_Noise__0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_Noise__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_Noise__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_Noise__0__SLW CYREG_PRT12_SLW\r
+#define SCSI_Noise__1__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__1__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__1__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__1__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__1__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__1__MASK 0x10u\r
+#define SCSI_Noise__1__PC CYREG_PRT6_PC4\r
+#define SCSI_Noise__1__PORT 6u\r
+#define SCSI_Noise__1__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__1__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__1__SHIFT 4\r
+#define SCSI_Noise__1__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__2__AG CYREG_PRT5_AG\r
+#define SCSI_Noise__2__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_Noise__2__BIE CYREG_PRT5_BIE\r
+#define SCSI_Noise__2__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_Noise__2__BYP CYREG_PRT5_BYP\r
+#define SCSI_Noise__2__CTL CYREG_PRT5_CTL\r
+#define SCSI_Noise__2__DM0 CYREG_PRT5_DM0\r
+#define SCSI_Noise__2__DM1 CYREG_PRT5_DM1\r
+#define SCSI_Noise__2__DM2 CYREG_PRT5_DM2\r
+#define SCSI_Noise__2__DR CYREG_PRT5_DR\r
+#define SCSI_Noise__2__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_Noise__2__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_Noise__2__MASK 0x01u\r
+#define SCSI_Noise__2__PC CYREG_PRT5_PC0\r
+#define SCSI_Noise__2__PORT 5u\r
+#define SCSI_Noise__2__PRT CYREG_PRT5_PRT\r
+#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_Noise__2__PS CYREG_PRT5_PS\r
+#define SCSI_Noise__2__SHIFT 0\r
+#define SCSI_Noise__2__SLW CYREG_PRT5_SLW\r
+#define SCSI_Noise__3__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__3__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__3__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__3__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__3__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__3__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__3__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__3__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__3__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__3__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__3__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__3__MASK 0x40u\r
+#define SCSI_Noise__3__PC CYREG_PRT6_PC6\r
+#define SCSI_Noise__3__PORT 6u\r
+#define SCSI_Noise__3__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__3__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__3__SHIFT 6\r
+#define SCSI_Noise__3__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__4__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__4__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__4__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__4__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__4__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__4__MASK 0x20u\r
+#define SCSI_Noise__4__PC CYREG_PRT6_PC5\r
+#define SCSI_Noise__4__PORT 6u\r
+#define SCSI_Noise__4__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__4__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__4__SHIFT 5\r
+#define SCSI_Noise__4__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__ACK__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__ACK__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__ACK__MASK 0x20u\r
+#define SCSI_Noise__ACK__PC CYREG_PRT6_PC5\r
+#define SCSI_Noise__ACK__PORT 6u\r
+#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__ACK__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__ACK__SHIFT 5\r
+#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__ATN__AG CYREG_PRT12_AG\r
+#define SCSI_Noise__ATN__BIE CYREG_PRT12_BIE\r
+#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_Noise__ATN__BYP CYREG_PRT12_BYP\r
+#define SCSI_Noise__ATN__DM0 CYREG_PRT12_DM0\r
+#define SCSI_Noise__ATN__DM1 CYREG_PRT12_DM1\r
+#define SCSI_Noise__ATN__DM2 CYREG_PRT12_DM2\r
+#define SCSI_Noise__ATN__DR CYREG_PRT12_DR\r
+#define SCSI_Noise__ATN__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_Noise__ATN__MASK 0x20u\r
+#define SCSI_Noise__ATN__PC CYREG_PRT12_PC5\r
+#define SCSI_Noise__ATN__PORT 12u\r
+#define SCSI_Noise__ATN__PRT CYREG_PRT12_PRT\r
+#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_Noise__ATN__PS CYREG_PRT12_PS\r
+#define SCSI_Noise__ATN__SHIFT 5\r
+#define SCSI_Noise__ATN__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_Noise__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_Noise__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_Noise__ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_Noise__ATN__SLW CYREG_PRT12_SLW\r
+#define SCSI_Noise__BSY__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__BSY__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__BSY__MASK 0x10u\r
+#define SCSI_Noise__BSY__PC CYREG_PRT6_PC4\r
+#define SCSI_Noise__BSY__PORT 6u\r
+#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__BSY__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__BSY__SHIFT 4\r
+#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__RST__AG CYREG_PRT6_AG\r
+#define SCSI_Noise__RST__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Noise__RST__BIE CYREG_PRT6_BIE\r
+#define SCSI_Noise__RST__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Noise__RST__BYP CYREG_PRT6_BYP\r
+#define SCSI_Noise__RST__CTL CYREG_PRT6_CTL\r
+#define SCSI_Noise__RST__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Noise__RST__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Noise__RST__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Noise__RST__DR CYREG_PRT6_DR\r
+#define SCSI_Noise__RST__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Noise__RST__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Noise__RST__MASK 0x40u\r
+#define SCSI_Noise__RST__PC CYREG_PRT6_PC6\r
+#define SCSI_Noise__RST__PORT 6u\r
+#define SCSI_Noise__RST__PRT CYREG_PRT6_PRT\r
+#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Noise__RST__PS CYREG_PRT6_PS\r
+#define SCSI_Noise__RST__SHIFT 6\r
+#define SCSI_Noise__RST__SLW CYREG_PRT6_SLW\r
+#define SCSI_Noise__SEL__AG CYREG_PRT5_AG\r
+#define SCSI_Noise__SEL__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_Noise__SEL__BIE CYREG_PRT5_BIE\r
+#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_Noise__SEL__BYP CYREG_PRT5_BYP\r
+#define SCSI_Noise__SEL__CTL CYREG_PRT5_CTL\r
+#define SCSI_Noise__SEL__DM0 CYREG_PRT5_DM0\r
+#define SCSI_Noise__SEL__DM1 CYREG_PRT5_DM1\r
+#define SCSI_Noise__SEL__DM2 CYREG_PRT5_DM2\r
+#define SCSI_Noise__SEL__DR CYREG_PRT5_DR\r
+#define SCSI_Noise__SEL__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_Noise__SEL__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_Noise__SEL__MASK 0x01u\r
+#define SCSI_Noise__SEL__PC CYREG_PRT5_PC0\r
+#define SCSI_Noise__SEL__PORT 5u\r
+#define SCSI_Noise__SEL__PRT CYREG_PRT5_PRT\r
+#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_Noise__SEL__PS CYREG_PRT5_PS\r
+#define SCSI_Noise__SEL__SHIFT 0\r
+#define SCSI_Noise__SEL__SLW CYREG_PRT5_SLW\r
+\r
+/* scsiTarget */\r
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB05_06_A0\r
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB05_06_A1\r
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB05_06_D0\r
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB05_06_D1\r
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB05_06_F0\r
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB05_06_F1\r
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB05_A0_A1\r
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB05_A0\r
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB05_A1\r
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB05_D0_D1\r
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB05_D0\r
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB05_D1\r
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB05_F0_F1\r
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB05_F0\r
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB05_F1\r
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB05_MSK\r
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB05_ST\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB05_CTL\r
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB05_CTL\r
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB05_MSK\r
+#define scsiTarget_StatusReg__0__MASK 0x01u\r
+#define scsiTarget_StatusReg__0__POS 0\r
+#define scsiTarget_StatusReg__1__MASK 0x02u\r
+#define scsiTarget_StatusReg__1__POS 1\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
+#define scsiTarget_StatusReg__2__MASK 0x04u\r
+#define scsiTarget_StatusReg__2__POS 2\r
+#define scsiTarget_StatusReg__3__MASK 0x08u\r
+#define scsiTarget_StatusReg__3__POS 3\r
+#define scsiTarget_StatusReg__4__MASK 0x10u\r
+#define scsiTarget_StatusReg__4__POS 4\r
+#define scsiTarget_StatusReg__MASK 0x1Fu\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK\r
+#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST\r
\r
-/* SD_DAT2 */\r
-#define SD_DAT2__0__MASK 0x20u\r
-#define SD_DAT2__0__PC CYREG_PRT3_PC5\r
-#define SD_DAT2__0__PORT 3u\r
-#define SD_DAT2__0__SHIFT 5\r
-#define SD_DAT2__AG CYREG_PRT3_AG\r
-#define SD_DAT2__AMUX CYREG_PRT3_AMUX\r
-#define SD_DAT2__BIE CYREG_PRT3_BIE\r
-#define SD_DAT2__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_DAT2__BYP CYREG_PRT3_BYP\r
-#define SD_DAT2__CTL CYREG_PRT3_CTL\r
-#define SD_DAT2__DM0 CYREG_PRT3_DM0\r
-#define SD_DAT2__DM1 CYREG_PRT3_DM1\r
-#define SD_DAT2__DM2 CYREG_PRT3_DM2\r
-#define SD_DAT2__DR CYREG_PRT3_DR\r
-#define SD_DAT2__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_DAT2__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_DAT2__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_DAT2__MASK 0x20u\r
-#define SD_DAT2__PORT 3u\r
-#define SD_DAT2__PRT CYREG_PRT3_PRT\r
-#define SD_DAT2__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_DAT2__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_DAT2__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_DAT2__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_DAT2__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_DAT2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_DAT2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_DAT2__PS CYREG_PRT3_PS\r
-#define SD_DAT2__SHIFT 5\r
-#define SD_DAT2__SLW CYREG_PRT3_SLW\r
+/* Debug_Timer_Interrupt */\r
+#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define Debug_Timer_Interrupt__INTC_MASK 0x02u\r
+#define Debug_Timer_Interrupt__INTC_NUMBER 1u\r
+#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u\r
+#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
+#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
-/* SD_MISO */\r
-#define SD_MISO__0__MASK 0x02u\r
-#define SD_MISO__0__PC CYREG_PRT3_PC1\r
-#define SD_MISO__0__PORT 3u\r
-#define SD_MISO__0__SHIFT 1\r
-#define SD_MISO__AG CYREG_PRT3_AG\r
-#define SD_MISO__AMUX CYREG_PRT3_AMUX\r
-#define SD_MISO__BIE CYREG_PRT3_BIE\r
-#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_MISO__BYP CYREG_PRT3_BYP\r
-#define SD_MISO__CTL CYREG_PRT3_CTL\r
-#define SD_MISO__DM0 CYREG_PRT3_DM0\r
-#define SD_MISO__DM1 CYREG_PRT3_DM1\r
-#define SD_MISO__DM2 CYREG_PRT3_DM2\r
-#define SD_MISO__DR CYREG_PRT3_DR\r
-#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_MISO__MASK 0x02u\r
-#define SD_MISO__PORT 3u\r
-#define SD_MISO__PRT CYREG_PRT3_PRT\r
-#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_MISO__PS CYREG_PRT3_PS\r
-#define SD_MISO__SHIFT 1\r
-#define SD_MISO__SLW CYREG_PRT3_SLW\r
+/* Debug_Timer_TimerHW */\r
+#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0\r
+#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1\r
+#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0\r
+#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1\r
+#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2\r
+#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0\r
+#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1\r
+#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0\r
+#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1\r
+#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3\r
+#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u\r
+#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3\r
+#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u\r
+#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0\r
+#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1\r
+#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0\r
+\r
+/* SCSI_RX_DMA */\r
+#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SCSI_RX_DMA__DRQ_NUMBER 0u\r
+#define SCSI_RX_DMA__NUMBEROF_TDS 0u\r
+#define SCSI_RX_DMA__PRIORITY 2u\r
+#define SCSI_RX_DMA__TERMIN_EN 0u\r
+#define SCSI_RX_DMA__TERMIN_SEL 0u\r
+#define SCSI_RX_DMA__TERMOUT0_EN 1u\r
+#define SCSI_RX_DMA__TERMOUT0_SEL 0u\r
+#define SCSI_RX_DMA__TERMOUT1_EN 0u\r
+#define SCSI_RX_DMA__TERMOUT1_SEL 0u\r
+\r
+/* SCSI_RX_DMA_COMPLETE */\r
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_TX_DMA */\r
+#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0\r
+#define SCSI_TX_DMA__DRQ_NUMBER 1u\r
+#define SCSI_TX_DMA__NUMBEROF_TDS 0u\r
+#define SCSI_TX_DMA__PRIORITY 2u\r
+#define SCSI_TX_DMA__TERMIN_EN 0u\r
+#define SCSI_TX_DMA__TERMIN_SEL 0u\r
+#define SCSI_TX_DMA__TERMOUT0_EN 1u\r
+#define SCSI_TX_DMA__TERMOUT0_SEL 1u\r
+#define SCSI_TX_DMA__TERMOUT1_EN 0u\r
+#define SCSI_TX_DMA__TERMOUT1_SEL 0u\r
+\r
+/* SCSI_TX_DMA_COMPLETE */\r
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x08u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 3u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u\r
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3\r
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SD_Data_Clk */\r
+#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0\r
+#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1\r
+#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2\r
+#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u\r
+#define SD_Data_Clk__INDEX 0x00u\r
+#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
+#define SD_Data_Clk__PM_ACT_MSK 0x01u\r
+#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
+#define SD_Data_Clk__PM_STBY_MSK 0x01u\r
\r
-/* SD_MOSI */\r
-#define SD_MOSI__0__MASK 0x08u\r
-#define SD_MOSI__0__PC CYREG_PRT3_PC3\r
-#define SD_MOSI__0__PORT 3u\r
-#define SD_MOSI__0__SHIFT 3\r
-#define SD_MOSI__AG CYREG_PRT3_AG\r
-#define SD_MOSI__AMUX CYREG_PRT3_AMUX\r
-#define SD_MOSI__BIE CYREG_PRT3_BIE\r
-#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_MOSI__BYP CYREG_PRT3_BYP\r
-#define SD_MOSI__CTL CYREG_PRT3_CTL\r
-#define SD_MOSI__DM0 CYREG_PRT3_DM0\r
-#define SD_MOSI__DM1 CYREG_PRT3_DM1\r
-#define SD_MOSI__DM2 CYREG_PRT3_DM2\r
-#define SD_MOSI__DR CYREG_PRT3_DR\r
-#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_MOSI__MASK 0x08u\r
-#define SD_MOSI__PORT 3u\r
-#define SD_MOSI__PRT CYREG_PRT3_PRT\r
-#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_MOSI__PS CYREG_PRT3_PS\r
-#define SD_MOSI__SHIFT 3\r
-#define SD_MOSI__SLW CYREG_PRT3_SLW\r
+/* timer_clock */\r
+#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0\r
+#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1\r
+#define timer_clock__CFG2 CYREG_CLKDIST_DCFG2_CFG2\r
+#define timer_clock__CFG2_SRC_SEL_MASK 0x07u\r
+#define timer_clock__INDEX 0x02u\r
+#define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
+#define timer_clock__PM_ACT_MSK 0x04u\r
+#define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
+#define timer_clock__PM_STBY_MSK 0x04u\r
\r
-/* SD_SCK */\r
-#define SD_SCK__0__MASK 0x04u\r
-#define SD_SCK__0__PC CYREG_PRT3_PC2\r
-#define SD_SCK__0__PORT 3u\r
-#define SD_SCK__0__SHIFT 2\r
-#define SD_SCK__AG CYREG_PRT3_AG\r
-#define SD_SCK__AMUX CYREG_PRT3_AMUX\r
-#define SD_SCK__BIE CYREG_PRT3_BIE\r
-#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_SCK__BYP CYREG_PRT3_BYP\r
-#define SD_SCK__CTL CYREG_PRT3_CTL\r
-#define SD_SCK__DM0 CYREG_PRT3_DM0\r
-#define SD_SCK__DM1 CYREG_PRT3_DM1\r
-#define SD_SCK__DM2 CYREG_PRT3_DM2\r
-#define SD_SCK__DR CYREG_PRT3_DR\r
-#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_SCK__MASK 0x04u\r
-#define SD_SCK__PORT 3u\r
-#define SD_SCK__PRT CYREG_PRT3_PRT\r
-#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_SCK__PS CYREG_PRT3_PS\r
-#define SD_SCK__SHIFT 2\r
-#define SD_SCK__SLW CYREG_PRT3_SLW\r
+/* SCSI_RST_ISR */\r
+#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SCSI_RST_ISR__INTC_MASK 0x04u\r
+#define SCSI_RST_ISR__INTC_NUMBER 2u\r
+#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u\r
+#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2\r
+#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
-/* SD_CD */\r
-#define SD_CD__0__MASK 0x40u\r
-#define SD_CD__0__PC CYREG_PRT3_PC6\r
-#define SD_CD__0__PORT 3u\r
-#define SD_CD__0__SHIFT 6\r
-#define SD_CD__AG CYREG_PRT3_AG\r
-#define SD_CD__AMUX CYREG_PRT3_AMUX\r
-#define SD_CD__BIE CYREG_PRT3_BIE\r
-#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_CD__BYP CYREG_PRT3_BYP\r
-#define SD_CD__CTL CYREG_PRT3_CTL\r
-#define SD_CD__DM0 CYREG_PRT3_DM0\r
-#define SD_CD__DM1 CYREG_PRT3_DM1\r
-#define SD_CD__DM2 CYREG_PRT3_DM2\r
-#define SD_CD__DR CYREG_PRT3_DR\r
-#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_CD__MASK 0x40u\r
-#define SD_CD__PORT 3u\r
-#define SD_CD__PRT CYREG_PRT3_PRT\r
-#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_CD__PS CYREG_PRT3_PS\r
-#define SD_CD__SHIFT 6\r
-#define SD_CD__SLW CYREG_PRT3_SLW\r
+/* SCSI_Filtered */\r
+#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u\r
+#define SCSI_Filtered_sts_sts_reg__0__POS 0\r
+#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u\r
+#define SCSI_Filtered_sts_sts_reg__1__POS 1\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST\r
+#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u\r
+#define SCSI_Filtered_sts_sts_reg__2__POS 2\r
+#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u\r
+#define SCSI_Filtered_sts_sts_reg__3__POS 3\r
+#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u\r
+#define SCSI_Filtered_sts_sts_reg__4__POS 4\r
+#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu\r
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB12_MSK\r
+#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB12_ST\r
\r
-/* SD_CS */\r
-#define SD_CS__0__MASK 0x10u\r
-#define SD_CS__0__PC CYREG_PRT3_PC4\r
-#define SD_CS__0__PORT 3u\r
-#define SD_CS__0__SHIFT 4\r
-#define SD_CS__AG CYREG_PRT3_AG\r
-#define SD_CS__AMUX CYREG_PRT3_AMUX\r
-#define SD_CS__BIE CYREG_PRT3_BIE\r
-#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_CS__BYP CYREG_PRT3_BYP\r
-#define SD_CS__CTL CYREG_PRT3_CTL\r
-#define SD_CS__DM0 CYREG_PRT3_DM0\r
-#define SD_CS__DM1 CYREG_PRT3_DM1\r
-#define SD_CS__DM2 CYREG_PRT3_DM2\r
-#define SD_CS__DR CYREG_PRT3_DR\r
-#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_CS__MASK 0x10u\r
-#define SD_CS__PORT 3u\r
-#define SD_CS__PRT CYREG_PRT3_PRT\r
-#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_CS__PS CYREG_PRT3_PS\r
-#define SD_CS__SHIFT 4\r
-#define SD_CS__SLW CYREG_PRT3_SLW\r
+/* SCSI_CTL_PHASE */\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK\r
\r
-/* LED1 */\r
-#define LED1__0__MASK 0x08u\r
-#define LED1__0__PC CYREG_PRT12_PC3\r
-#define LED1__0__PORT 12u\r
-#define LED1__0__SHIFT 3\r
-#define LED1__AG CYREG_PRT12_AG\r
-#define LED1__BIE CYREG_PRT12_BIE\r
-#define LED1__BIT_MASK CYREG_PRT12_BIT_MASK\r
-#define LED1__BYP CYREG_PRT12_BYP\r
-#define LED1__DM0 CYREG_PRT12_DM0\r
-#define LED1__DM1 CYREG_PRT12_DM1\r
-#define LED1__DM2 CYREG_PRT12_DM2\r
-#define LED1__DR CYREG_PRT12_DR\r
-#define LED1__INP_DIS CYREG_PRT12_INP_DIS\r
-#define LED1__MASK 0x08u\r
-#define LED1__PORT 12u\r
-#define LED1__PRT CYREG_PRT12_PRT\r
-#define LED1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
-#define LED1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
-#define LED1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
-#define LED1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
-#define LED1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
-#define LED1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
-#define LED1__PS CYREG_PRT12_PS\r
-#define LED1__SHIFT 3\r
-#define LED1__SIO_CFG CYREG_PRT12_SIO_CFG\r
-#define LED1__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
-#define LED1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
-#define LED1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
-#define LED1__SLW CYREG_PRT12_SLW\r
+/* SCSI_Parity_Error */\r
+#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
+#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB06_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB06_ST\r
\r
/* Miscellaneous */\r
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */\r
-#define CYDEV_DEBUGGING_DPS_SWD_SWV 6\r
-#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0\r
-#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0\r
-#define CYDEV_CONFIG_FASTBOOT_ENABLED 1\r
-#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u\r
-#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u\r
-#define CYDEV_CHIP_MEMBER_5B 4u\r
-#define CYDEV_CHIP_FAMILY_PSOC5 3u\r
-#define CYDEV_CHIP_DIE_PSOC5LP 4u\r
-#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP\r
#define BCLK__BUS_CLK__HZ 50000000U\r
#define BCLK__BUS_CLK__KHZ 50000U\r
#define BCLK__BUS_CLK__MHZ 50U\r
-#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT\r
+#define CY_VERSION "PSoC Creator 3.1"\r
#define CYDEV_CHIP_DIE_LEOPARD 1u\r
-#define CYDEV_CHIP_DIE_PANTHER 3u\r
-#define CYDEV_CHIP_DIE_PSOC4A 2u\r
+#define CYDEV_CHIP_DIE_PANTHER 6u\r
+#define CYDEV_CHIP_DIE_PSOC4A 3u\r
+#define CYDEV_CHIP_DIE_PSOC5LP 5u\r
#define CYDEV_CHIP_DIE_UNKNOWN 0u\r
#define CYDEV_CHIP_FAMILY_PSOC3 1u\r
#define CYDEV_CHIP_FAMILY_PSOC4 2u\r
+#define CYDEV_CHIP_FAMILY_PSOC5 3u\r
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u\r
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5\r
#define CYDEV_CHIP_JTAG_ID 0x2E133069u\r
#define CYDEV_CHIP_MEMBER_3A 1u\r
-#define CYDEV_CHIP_MEMBER_4A 2u\r
-#define CYDEV_CHIP_MEMBER_5A 3u\r
+#define CYDEV_CHIP_MEMBER_4A 3u\r
+#define CYDEV_CHIP_MEMBER_4D 2u\r
+#define CYDEV_CHIP_MEMBER_4F 4u\r
+#define CYDEV_CHIP_MEMBER_5A 6u\r
+#define CYDEV_CHIP_MEMBER_5B 5u\r
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u\r
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B\r
+#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED\r
+#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT\r
+#define CYDEV_CHIP_REV_LEOPARD_ES1 0u\r
+#define CYDEV_CHIP_REV_LEOPARD_ES2 1u\r
+#define CYDEV_CHIP_REV_LEOPARD_ES3 3u\r
+#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u\r
+#define CYDEV_CHIP_REV_PANTHER_ES0 0u\r
+#define CYDEV_CHIP_REV_PANTHER_ES1 1u\r
+#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u\r
+#define CYDEV_CHIP_REV_PSOC4A_ES0 17u\r
+#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u\r
+#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u\r
+#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_3A_ES1 0u\r
#define CYDEV_CHIP_REVISION_3A_ES2 1u\r
#define CYDEV_CHIP_REVISION_3A_ES3 3u\r
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u\r
#define CYDEV_CHIP_REVISION_4A_ES0 17u\r
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u\r
+#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_5A_ES0 0u\r
#define CYDEV_CHIP_REVISION_5A_ES1 1u\r
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u\r
#define CYDEV_CHIP_REVISION_5B_ES0 0u\r
+#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION\r
-#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REV_PSOC5LP_PRODUCTION\r
-#define CYDEV_CHIP_REV_LEOPARD_ES1 0u\r
-#define CYDEV_CHIP_REV_LEOPARD_ES2 1u\r
-#define CYDEV_CHIP_REV_LEOPARD_ES3 3u\r
-#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u\r
-#define CYDEV_CHIP_REV_PANTHER_ES0 0u\r
-#define CYDEV_CHIP_REV_PANTHER_ES1 1u\r
-#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u\r
-#define CYDEV_CHIP_REV_PSOC4A_ES0 17u\r
-#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u\r
-#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u\r
+#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED\r
+#define CYDEV_CONFIG_FASTBOOT_ENABLED 1\r
+#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0\r
+#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
+#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1\r
+#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2\r
#define CYDEV_CONFIGURATION_COMPRESSED 1\r
#define CYDEV_CONFIGURATION_DMA 0\r
#define CYDEV_CONFIGURATION_ECC 0\r
#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED\r
+#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0\r
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED\r
#define CYDEV_CONFIGURATION_MODE_DMA 2\r
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1\r
-#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
-#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1\r
-#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2\r
-#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV\r
+#define CYDEV_DEBUG_ENABLE_MASK 0x20u\r
+#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG\r
#define CYDEV_DEBUGGING_DPS_Disable 3\r
#define CYDEV_DEBUGGING_DPS_JTAG_4 1\r
#define CYDEV_DEBUGGING_DPS_JTAG_5 0\r
#define CYDEV_DEBUGGING_DPS_SWD 2\r
+#define CYDEV_DEBUGGING_DPS_SWD_SWV 6\r
+#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV\r
#define CYDEV_DEBUGGING_ENABLE 1\r
#define CYDEV_DEBUGGING_XRES 0\r
-#define CYDEV_DEBUG_ENABLE_MASK 0x20u\r
-#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG\r
#define CYDEV_DMA_CHANNELS_AVAILABLE 24u\r
#define CYDEV_ECC_ENABLE 0\r
#define CYDEV_HEAP_SIZE 0x0400\r
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3\r
#define CYDEV_PROJ_TYPE_STANDARD 0\r
#define CYDEV_PROTECTION_ENABLE 0\r
-#define CYDEV_STACK_SIZE 0x2000\r
+#define CYDEV_STACK_SIZE 0x1000\r
#define CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP \r
#define CYDEV_USE_BUNDLED_CMSIS 1\r
#define CYDEV_VARIABLE_VDDA 0\r
#define CYDEV_VDDIO2_MV 5000\r
#define CYDEV_VDDIO3 3.3\r
#define CYDEV_VDDIO3_MV 3300\r
-#define CYDEV_VIO0 5\r
+#define CYDEV_VIO0 5.0\r
#define CYDEV_VIO0_MV 5000\r
-#define CYDEV_VIO1 5\r
+#define CYDEV_VIO1 5.0\r
#define CYDEV_VIO1_MV 5000\r
-#define CYDEV_VIO2 5\r
+#define CYDEV_VIO2 5.0\r
#define CYDEV_VIO2_MV 5000\r
#define CYDEV_VIO3 3.3\r
#define CYDEV_VIO3_MV 3300\r
+#define CYIPBLOCK_ARM_CM3_VERSION 0\r
+#define CYIPBLOCK_P3_ANAIF_VERSION 0\r
+#define CYIPBLOCK_P3_CAPSENSE_VERSION 0\r
+#define CYIPBLOCK_P3_COMP_VERSION 0\r
+#define CYIPBLOCK_P3_DMA_VERSION 0\r
+#define CYIPBLOCK_P3_DRQ_VERSION 0\r
+#define CYIPBLOCK_P3_EMIF_VERSION 0\r
+#define CYIPBLOCK_P3_I2C_VERSION 0\r
+#define CYIPBLOCK_P3_LCD_VERSION 0\r
+#define CYIPBLOCK_P3_LPF_VERSION 0\r
+#define CYIPBLOCK_P3_PM_VERSION 0\r
+#define CYIPBLOCK_P3_TIMER_VERSION 0\r
+#define CYIPBLOCK_P3_USB_VERSION 0\r
+#define CYIPBLOCK_P3_VIDAC_VERSION 0\r
+#define CYIPBLOCK_P3_VREF_VERSION 0\r
+#define CYIPBLOCK_S8_GPIO_VERSION 0\r
+#define CYIPBLOCK_S8_IRQ_VERSION 0\r
+#define CYIPBLOCK_S8_SAR_VERSION 0\r
+#define CYIPBLOCK_S8_SIO_VERSION 0\r
+#define CYIPBLOCK_S8_UDB_VERSION 0\r
#define DMA_CHANNELS_USED__MASK0 0x0000000Fu\r
#define CYDEV_BOOTLOADER_ENABLE 0\r
\r
/*******************************************************************************\r
* FILENAME: cyfitter_cfg.c\r
-* PSoC Creator 3.0 Component Pack 7\r
+* PSoC Creator 3.1\r
*\r
* Description:\r
* This file is automatically generated by PSoC Creator with device \r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 40u\r
+#define CY_CFG_BASE_ADDR_COUNT 41u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
0x4000520Bu, /* Base address: 0x40005200 Count: 11 */\r
0x40006401u, /* Base address: 0x40006400 Count: 1 */\r
0x40006501u, /* Base address: 0x40006500 Count: 1 */\r
- 0x4001003Bu, /* Base address: 0x40010000 Count: 59 */\r
- 0x40010136u, /* Base address: 0x40010100 Count: 54 */\r
- 0x40010244u, /* Base address: 0x40010200 Count: 68 */\r
- 0x40010358u, /* Base address: 0x40010300 Count: 88 */\r
- 0x40010445u, /* Base address: 0x40010400 Count: 69 */\r
- 0x40010551u, /* Base address: 0x40010500 Count: 81 */\r
- 0x40010653u, /* Base address: 0x40010600 Count: 83 */\r
- 0x40010755u, /* Base address: 0x40010700 Count: 85 */\r
- 0x4001090Du, /* Base address: 0x40010900 Count: 13 */\r
- 0x40010A47u, /* Base address: 0x40010A00 Count: 71 */\r
- 0x40010B47u, /* Base address: 0x40010B00 Count: 71 */\r
- 0x40010C51u, /* Base address: 0x40010C00 Count: 81 */\r
- 0x40010D54u, /* Base address: 0x40010D00 Count: 84 */\r
- 0x40010E4Au, /* Base address: 0x40010E00 Count: 74 */\r
- 0x40010F34u, /* Base address: 0x40010F00 Count: 52 */\r
- 0x4001141Eu, /* Base address: 0x40011400 Count: 30 */\r
- 0x40011555u, /* Base address: 0x40011500 Count: 85 */\r
- 0x40011655u, /* Base address: 0x40011600 Count: 85 */\r
- 0x40011746u, /* Base address: 0x40011700 Count: 70 */\r
- 0x40011907u, /* Base address: 0x40011900 Count: 7 */\r
- 0x40011B09u, /* Base address: 0x40011B00 Count: 9 */\r
- 0x40014018u, /* Base address: 0x40014000 Count: 24 */\r
- 0x40014122u, /* Base address: 0x40014100 Count: 34 */\r
- 0x40014209u, /* Base address: 0x40014200 Count: 9 */\r
- 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */\r
- 0x4001440Fu, /* Base address: 0x40014400 Count: 15 */\r
- 0x4001451Cu, /* Base address: 0x40014500 Count: 28 */\r
+ 0x4001004Eu, /* Base address: 0x40010000 Count: 78 */\r
+ 0x40010137u, /* Base address: 0x40010100 Count: 55 */\r
+ 0x4001024Du, /* Base address: 0x40010200 Count: 77 */\r
+ 0x40010353u, /* Base address: 0x40010300 Count: 83 */\r
+ 0x40010439u, /* Base address: 0x40010400 Count: 57 */\r
+ 0x4001054Cu, /* Base address: 0x40010500 Count: 76 */\r
+ 0x40010621u, /* Base address: 0x40010600 Count: 33 */\r
+ 0x40010754u, /* Base address: 0x40010700 Count: 84 */\r
+ 0x40010918u, /* Base address: 0x40010900 Count: 24 */\r
+ 0x40010A42u, /* Base address: 0x40010A00 Count: 66 */\r
+ 0x40010B4Eu, /* Base address: 0x40010B00 Count: 78 */\r
+ 0x40010C43u, /* Base address: 0x40010C00 Count: 67 */\r
+ 0x40010D53u, /* Base address: 0x40010D00 Count: 83 */\r
+ 0x40010E55u, /* Base address: 0x40010E00 Count: 85 */\r
+ 0x40010F35u, /* Base address: 0x40010F00 Count: 53 */\r
+ 0x40011451u, /* Base address: 0x40011400 Count: 81 */\r
+ 0x4001154Bu, /* Base address: 0x40011500 Count: 75 */\r
+ 0x4001164Cu, /* Base address: 0x40011600 Count: 76 */\r
+ 0x40011750u, /* Base address: 0x40011700 Count: 80 */\r
+ 0x40011804u, /* Base address: 0x40011800 Count: 4 */\r
+ 0x40011910u, /* Base address: 0x40011900 Count: 16 */\r
+ 0x40011B07u, /* Base address: 0x40011B00 Count: 7 */\r
+ 0x40014016u, /* Base address: 0x40014000 Count: 22 */\r
+ 0x4001411Cu, /* Base address: 0x40014100 Count: 28 */\r
+ 0x4001420Cu, /* Base address: 0x40014200 Count: 12 */\r
+ 0x4001430Du, /* Base address: 0x40014300 Count: 13 */\r
+ 0x40014411u, /* Base address: 0x40014400 Count: 17 */\r
+ 0x4001451Au, /* Base address: 0x40014500 Count: 26 */\r
0x4001460Eu, /* Base address: 0x40014600 Count: 14 */\r
- 0x4001470Cu, /* Base address: 0x40014700 Count: 12 */\r
- 0x40014806u, /* Base address: 0x40014800 Count: 6 */\r
- 0x4001490Bu, /* Base address: 0x40014900 Count: 11 */\r
+ 0x4001470Bu, /* Base address: 0x40014700 Count: 11 */\r
+ 0x4001480Bu, /* Base address: 0x40014800 Count: 11 */\r
+ 0x4001490Cu, /* Base address: 0x40014900 Count: 12 */\r
0x40014C05u, /* Base address: 0x40014C00 Count: 5 */\r
- 0x40014D0Au, /* Base address: 0x40014D00 Count: 10 */\r
+ 0x40014D03u, /* Base address: 0x40014D00 Count: 3 */\r
0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
};\r
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {\r
{0x7Eu, 0x02u},\r
{0x01u, 0x20u},\r
- {0x0Au, 0x4Bu},\r
- {0x00u, 0x11u},\r
- {0x01u, 0x02u},\r
- {0x18u, 0x04u},\r
+ {0x0Au, 0x36u},\r
+ {0x00u, 0x12u},\r
+ {0x01u, 0x04u},\r
+ {0x19u, 0x04u},\r
{0x1Cu, 0x71u},\r
{0x20u, 0x58u},\r
- {0x21u, 0xC8u},\r
+ {0x21u, 0x98u},\r
{0x2Cu, 0x0Eu},\r
- {0x30u, 0x05u},\r
- {0x31u, 0x06u},\r
+ {0x30u, 0x0Au},\r
+ {0x31u, 0x0Cu},\r
{0x34u, 0x80u},\r
{0x7Cu, 0x40u},\r
- {0x21u, 0x02u},\r
- {0x84u, 0x0Fu},\r
- {0x00u, 0x01u},\r
- {0x10u, 0x04u},\r
- {0x11u, 0x01u},\r
- {0x19u, 0x02u},\r
- {0x28u, 0x02u},\r
- {0x30u, 0x04u},\r
- {0x31u, 0x02u},\r
- {0x33u, 0x01u},\r
- {0x34u, 0x01u},\r
- {0x36u, 0x02u},\r
- {0x3Eu, 0x51u},\r
- {0x3Fu, 0x05u},\r
+ {0x25u, 0x02u},\r
+ {0x87u, 0x0Fu},\r
+ {0x01u, 0x30u},\r
+ {0x02u, 0x08u},\r
+ {0x03u, 0xC0u},\r
+ {0x05u, 0x06u},\r
+ {0x07u, 0x09u},\r
+ {0x09u, 0x0Fu},\r
+ {0x0Bu, 0xF0u},\r
+ {0x11u, 0x05u},\r
+ {0x12u, 0x80u},\r
+ {0x13u, 0x0Au},\r
+ {0x16u, 0x17u},\r
+ {0x19u, 0x03u},\r
+ {0x1Au, 0x40u},\r
+ {0x1Bu, 0x0Cu},\r
+ {0x1Eu, 0x20u},\r
+ {0x20u, 0x0Au},\r
+ {0x22u, 0x05u},\r
+ {0x24u, 0x50u},\r
+ {0x25u, 0x50u},\r
+ {0x26u, 0xA0u},\r
+ {0x27u, 0xA0u},\r
+ {0x28u, 0x09u},\r
+ {0x2Au, 0x02u},\r
+ {0x2Cu, 0x04u},\r
+ {0x2Du, 0x60u},\r
+ {0x2Eu, 0x08u},\r
+ {0x2Fu, 0x90u},\r
+ {0x32u, 0x0Fu},\r
+ {0x34u, 0xC0u},\r
+ {0x36u, 0x30u},\r
+ {0x37u, 0xFFu},\r
+ {0x3Eu, 0x50u},\r
+ {0x3Fu, 0x40u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
+ {0x5Cu, 0x01u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x04u},\r
- {0x83u, 0x10u},\r
- {0x8Bu, 0x1Cu},\r
- {0x8Fu, 0x08u},\r
- {0x91u, 0x04u},\r
- {0x93u, 0x08u},\r
- {0x99u, 0x18u},\r
- {0x9Bu, 0x04u},\r
- {0x9Cu, 0x01u},\r
- {0xA9u, 0x01u},\r
- {0xADu, 0x02u},\r
- {0xB0u, 0x01u},\r
- {0xB1u, 0x1Cu},\r
- {0xB3u, 0x02u},\r
- {0xB5u, 0x01u},\r
- {0xBEu, 0x01u},\r
- {0xBFu, 0x14u},\r
- {0xC0u, 0x53u},\r
- {0xC1u, 0x04u},\r
- {0xC2u, 0x20u},\r
- {0xC5u, 0xECu},\r
- {0xC6u, 0xD2u},\r
- {0xC7u, 0xF0u},\r
- {0xC8u, 0x2Fu},\r
- {0xC9u, 0xFFu},\r
- {0xCAu, 0xFFu},\r
- {0xCBu, 0xFFu},\r
- {0xCFu, 0x2Cu},\r
- {0xD6u, 0x01u},\r
+ {0x81u, 0x0Fu},\r
+ {0x82u, 0x70u},\r
+ {0x83u, 0xF0u},\r
+ {0x84u, 0x90u},\r
+ {0x86u, 0x2Fu},\r
+ {0x87u, 0xFFu},\r
+ {0x8Bu, 0xFFu},\r
+ {0x8Cu, 0xC0u},\r
+ {0x8Du, 0x55u},\r
+ {0x8Eu, 0x1Fu},\r
+ {0x8Fu, 0xAAu},\r
+ {0x91u, 0xFFu},\r
+ {0x92u, 0x80u},\r
+ {0x94u, 0x06u},\r
+ {0x95u, 0xFFu},\r
+ {0x96u, 0x09u},\r
+ {0x9Cu, 0x05u},\r
+ {0x9Eu, 0x0Au},\r
+ {0x9Fu, 0xFFu},\r
+ {0xA0u, 0xA0u},\r
+ {0xA2u, 0x4Fu},\r
+ {0xA6u, 0x80u},\r
+ {0xA8u, 0x0Fu},\r
+ {0xA9u, 0x69u},\r
+ {0xABu, 0x96u},\r
+ {0xACu, 0x03u},\r
+ {0xADu, 0x33u},\r
+ {0xAEu, 0x0Cu},\r
+ {0xAFu, 0xCCu},\r
+ {0xB0u, 0x7Fu},\r
+ {0xB1u, 0xFFu},\r
+ {0xB2u, 0x80u},\r
+ {0xBBu, 0x02u},\r
+ {0xBEu, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDAu, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x10u},\r
- {0xDDu, 0x01u},\r
+ {0xDCu, 0x11u},\r
{0xDFu, 0x01u},\r
- {0xE2u, 0xC0u},\r
- {0xE6u, 0x80u},\r
- {0xE8u, 0x40u},\r
- {0xE9u, 0x40u},\r
- {0xEEu, 0x08u},\r
- {0x00u, 0x01u},\r
+ {0x00u, 0x02u},\r
+ {0x05u, 0x41u},\r
+ {0x07u, 0x20u},\r
{0x08u, 0x02u},\r
- {0x0Fu, 0x02u},\r
- {0x12u, 0x04u},\r
- {0x19u, 0x62u},\r
- {0x1Eu, 0x80u},\r
- {0x23u, 0x50u},\r
+ {0x09u, 0x40u},\r
+ {0x0Au, 0x24u},\r
+ {0x0Bu, 0x05u},\r
+ {0x0Du, 0x04u},\r
+ {0x0Eu, 0x01u},\r
+ {0x0Fu, 0x80u},\r
+ {0x10u, 0x01u},\r
+ {0x11u, 0x28u},\r
+ {0x13u, 0x02u},\r
+ {0x16u, 0x08u},\r
+ {0x17u, 0x4Au},\r
+ {0x18u, 0x08u},\r
+ {0x1Au, 0x22u},\r
+ {0x1Du, 0x01u},\r
+ {0x1Eu, 0x50u},\r
+ {0x21u, 0x80u},\r
{0x25u, 0x01u},\r
- {0x26u, 0x16u},\r
{0x27u, 0x40u},\r
- {0x2Fu, 0x05u},\r
- {0x31u, 0x11u},\r
- {0x37u, 0x11u},\r
- {0x38u, 0xC0u},\r
- {0x3Du, 0x02u},\r
- {0x3Eu, 0xA0u},\r
- {0x45u, 0x28u},\r
- {0x47u, 0x01u},\r
- {0x4Cu, 0x40u},\r
- {0x4Du, 0x08u},\r
- {0x4Eu, 0x02u},\r
- {0x54u, 0x01u},\r
- {0x56u, 0x80u},\r
- {0x57u, 0x22u},\r
- {0x58u, 0x40u},\r
- {0x5Du, 0x02u},\r
- {0x5Eu, 0xA8u},\r
- {0x63u, 0x02u},\r
- {0x65u, 0x60u},\r
- {0x67u, 0x50u},\r
- {0x68u, 0x02u},\r
- {0x6Au, 0x24u},\r
- {0x6Du, 0x19u},\r
- {0x6Eu, 0x40u},\r
- {0x75u, 0x80u},\r
- {0x76u, 0x58u},\r
- {0x82u, 0x02u},\r
- {0x85u, 0x04u},\r
- {0x86u, 0x04u},\r
- {0x88u, 0x02u},\r
- {0x8Cu, 0x40u},\r
- {0xC0u, 0x08u},\r
- {0xC2u, 0x88u},\r
- {0xC4u, 0x02u},\r
- {0xCAu, 0x30u},\r
- {0xCCu, 0xA5u},\r
- {0xCEu, 0xB0u},\r
- {0xD0u, 0xE0u},\r
- {0xD2u, 0x10u},\r
- {0xD6u, 0xF8u},\r
- {0xD8u, 0xF8u},\r
- {0xE0u, 0x01u},\r
- {0xE4u, 0x02u},\r
- {0xE6u, 0x90u},\r
- {0x03u, 0x2Cu},\r
- {0x04u, 0xC0u},\r
- {0x05u, 0x10u},\r
- {0x07u, 0x01u},\r
- {0x08u, 0x23u},\r
- {0x0Au, 0x44u},\r
- {0x0Bu, 0x7Fu},\r
- {0x0Cu, 0x1Au},\r
- {0x0Du, 0x08u},\r
- {0x0Fu, 0x03u},\r
- {0x10u, 0x04u},\r
- {0x11u, 0x37u},\r
- {0x12u, 0x1Au},\r
- {0x13u, 0x40u},\r
- {0x14u, 0x1Au},\r
- {0x15u, 0x03u},\r
- {0x18u, 0x1Au},\r
- {0x19u, 0x4Fu},\r
- {0x1Bu, 0x30u},\r
- {0x1Cu, 0x1Au},\r
- {0x24u, 0x25u},\r
- {0x25u, 0x02u},\r
- {0x26u, 0x88u},\r
- {0x28u, 0x45u},\r
- {0x2Au, 0x30u},\r
- {0x2Cu, 0x1Au},\r
- {0x30u, 0x1Eu},\r
- {0x32u, 0xE0u},\r
- {0x33u, 0x0Fu},\r
- {0x36u, 0x01u},\r
- {0x37u, 0x70u},\r
- {0x38u, 0x08u},\r
- {0x3Au, 0x02u},\r
- {0x3Eu, 0x40u},\r
+ {0x28u, 0x02u},\r
+ {0x2Bu, 0x10u},\r
+ {0x2Du, 0x20u},\r
+ {0x2Eu, 0x80u},\r
+ {0x32u, 0x12u},\r
+ {0x35u, 0x40u},\r
+ {0x37u, 0x0Au},\r
+ {0x38u, 0x20u},\r
+ {0x3Bu, 0x05u},\r
+ {0x3Du, 0x22u},\r
+ {0x3Fu, 0x48u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x10u},\r
+ {0x5Au, 0x80u},\r
+ {0x61u, 0x08u},\r
+ {0x62u, 0x50u},\r
+ {0x81u, 0x90u},\r
+ {0x85u, 0x40u},\r
+ {0x86u, 0x40u},\r
+ {0x88u, 0x10u},\r
+ {0x8Eu, 0x40u},\r
+ {0xC0u, 0xB8u},\r
+ {0xC2u, 0xBFu},\r
+ {0xC4u, 0xFFu},\r
+ {0xCAu, 0x3Au},\r
+ {0xCCu, 0xD5u},\r
+ {0xCEu, 0xF7u},\r
+ {0xD6u, 0x0Eu},\r
+ {0xD8u, 0x0Eu},\r
+ {0xE0u, 0x08u},\r
+ {0xE2u, 0x02u},\r
+ {0xE4u, 0x01u},\r
+ {0xE6u, 0xC4u},\r
+ {0x01u, 0x02u},\r
+ {0x02u, 0x07u},\r
+ {0x07u, 0x20u},\r
+ {0x09u, 0x57u},\r
+ {0x0Bu, 0xA0u},\r
+ {0x0Cu, 0x06u},\r
+ {0x0Du, 0x03u},\r
+ {0x0Eu, 0x01u},\r
+ {0x11u, 0x6Fu},\r
+ {0x13u, 0x90u},\r
+ {0x15u, 0x08u},\r
+ {0x17u, 0x03u},\r
+ {0x19u, 0x30u},\r
+ {0x1Au, 0x02u},\r
+ {0x1Bu, 0xC0u},\r
+ {0x1Cu, 0x01u},\r
+ {0x1Du, 0x70u},\r
+ {0x1Eu, 0x04u},\r
+ {0x1Fu, 0x8Cu},\r
+ {0x20u, 0x10u},\r
+ {0x23u, 0x3Fu},\r
+ {0x24u, 0x08u},\r
+ {0x25u, 0x10u},\r
+ {0x27u, 0x01u},\r
+ {0x28u, 0x01u},\r
+ {0x2Au, 0x02u},\r
+ {0x30u, 0x10u},\r
+ {0x32u, 0x08u},\r
+ {0x33u, 0xF0u},\r
+ {0x36u, 0x07u},\r
+ {0x37u, 0x0Fu},\r
+ {0x3Bu, 0x08u},\r
+ {0x3Eu, 0x05u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x10u},\r
+ {0x5Cu, 0x11u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x01u},\r
- {0x85u, 0x01u},\r
+ {0x80u, 0x01u},\r
+ {0x81u, 0x02u},\r
+ {0x82u, 0x02u},\r
+ {0x83u, 0x01u},\r
+ {0x85u, 0x02u},\r
+ {0x87u, 0x01u},\r
{0x89u, 0x02u},\r
- {0x8Au, 0x04u},\r
- {0x8Bu, 0x04u},\r
- {0x8Eu, 0x01u},\r
- {0x94u, 0x05u},\r
- {0x96u, 0x0Au},\r
- {0x97u, 0x04u},\r
- {0x9Au, 0x08u},\r
+ {0x8Bu, 0x05u},\r
+ {0x90u, 0x02u},\r
+ {0x92u, 0x01u},\r
+ {0x94u, 0x02u},\r
+ {0x96u, 0x09u},\r
+ {0x97u, 0x08u},\r
+ {0x98u, 0x02u},\r
+ {0x99u, 0x01u},\r
+ {0x9Au, 0x01u},\r
{0x9Bu, 0x02u},\r
- {0xA1u, 0x01u},\r
- {0xA5u, 0x01u},\r
- {0xAEu, 0x02u},\r
- {0xB2u, 0x0Cu},\r
- {0xB4u, 0x03u},\r
- {0xB5u, 0x06u},\r
- {0xB7u, 0x01u},\r
- {0xB9u, 0x80u},\r
- {0xBEu, 0x14u},\r
- {0xBFu, 0x50u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Eu, 0x05u},\r
+ {0xA1u, 0x02u},\r
+ {0xA3u, 0x11u},\r
+ {0xB0u, 0x03u},\r
+ {0xB1u, 0x04u},\r
+ {0xB3u, 0x10u},\r
+ {0xB4u, 0x04u},\r
+ {0xB5u, 0x03u},\r
+ {0xB6u, 0x08u},\r
+ {0xB7u, 0x08u},\r
+ {0xBAu, 0x02u},\r
+ {0xBBu, 0x20u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
+ {0xDCu, 0x99u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x80u},\r
- {0x03u, 0x04u},\r
- {0x04u, 0x20u},\r
- {0x05u, 0x04u},\r
- {0x06u, 0x02u},\r
- {0x0Bu, 0x14u},\r
- {0x0Cu, 0x90u},\r
- {0x0Du, 0x04u},\r
- {0x0Eu, 0x80u},\r
- {0x13u, 0x40u},\r
- {0x14u, 0x04u},\r
- {0x15u, 0x40u},\r
- {0x17u, 0x08u},\r
- {0x1Au, 0x08u},\r
- {0x1Bu, 0x08u},\r
- {0x1Du, 0x84u},\r
- {0x1Eu, 0xA0u},\r
- {0x21u, 0x50u},\r
- {0x25u, 0x48u},\r
- {0x27u, 0x11u},\r
- {0x2Bu, 0x90u},\r
- {0x2Fu, 0x20u},\r
- {0x30u, 0x08u},\r
- {0x32u, 0x10u},\r
- {0x35u, 0x08u},\r
- {0x37u, 0x11u},\r
+ {0x01u, 0x02u},\r
+ {0x04u, 0x02u},\r
+ {0x07u, 0x02u},\r
+ {0x09u, 0x08u},\r
+ {0x0Au, 0x8Au},\r
+ {0x0Du, 0x80u},\r
+ {0x0Fu, 0x08u},\r
+ {0x16u, 0x50u},\r
+ {0x17u, 0x20u},\r
+ {0x19u, 0x02u},\r
+ {0x1Au, 0x0Au},\r
+ {0x1Du, 0xC4u},\r
+ {0x1Fu, 0x01u},\r
+ {0x21u, 0x01u},\r
+ {0x22u, 0x70u},\r
+ {0x23u, 0x18u},\r
+ {0x27u, 0x12u},\r
+ {0x28u, 0x40u},\r
+ {0x2Eu, 0x08u},\r
+ {0x2Fu, 0x80u},\r
+ {0x32u, 0x14u},\r
+ {0x35u, 0x40u},\r
+ {0x37u, 0x1Au},\r
{0x38u, 0x08u},\r
{0x39u, 0x02u},\r
{0x3Bu, 0x10u},\r
- {0x3Du, 0x02u},\r
- {0x3Eu, 0x24u},\r
- {0x3Fu, 0x80u},\r
- {0x58u, 0x08u},\r
- {0x59u, 0x22u},\r
- {0x5Au, 0x80u},\r
- {0x5Fu, 0xA0u},\r
- {0x60u, 0x12u},\r
- {0x61u, 0x11u},\r
- {0x62u, 0x04u},\r
- {0x67u, 0x0Au},\r
- {0x81u, 0x20u},\r
- {0x83u, 0x80u},\r
- {0x85u, 0x10u},\r
- {0x88u, 0x0Au},\r
- {0x8Bu, 0x80u},\r
- {0x8Cu, 0x10u},\r
- {0x8Du, 0x19u},\r
- {0x90u, 0x48u},\r
- {0x91u, 0x13u},\r
- {0x92u, 0x44u},\r
- {0x94u, 0x01u},\r
- {0x95u, 0x84u},\r
- {0x96u, 0x08u},\r
- {0x97u, 0x0Au},\r
- {0x99u, 0x88u},\r
- {0x9Au, 0xD8u},\r
- {0x9Bu, 0x40u},\r
- {0x9Cu, 0x02u},\r
- {0x9Du, 0x11u},\r
- {0x9Eu, 0x24u},\r
- {0x9Fu, 0x11u},\r
- {0xA0u, 0x01u},\r
- {0xA1u, 0x15u},\r
- {0xA3u, 0x21u},\r
- {0xA5u, 0x28u},\r
- {0xA7u, 0x08u},\r
- {0xA8u, 0x04u},\r
- {0xA9u, 0x10u},\r
- {0xAAu, 0x10u},\r
- {0xADu, 0x01u},\r
- {0xAEu, 0x04u},\r
- {0xB0u, 0x40u},\r
- {0xB3u, 0x08u},\r
- {0xB5u, 0x40u},\r
- {0xB7u, 0x02u},\r
- {0xC0u, 0xE3u},\r
- {0xC2u, 0xF6u},\r
- {0xC4u, 0xE1u},\r
- {0xCAu, 0x43u},\r
- {0xCCu, 0xE6u},\r
+ {0x3Du, 0x21u},\r
+ {0x3Fu, 0x88u},\r
+ {0x44u, 0x01u},\r
+ {0x45u, 0x80u},\r
+ {0x58u, 0x24u},\r
+ {0x5Au, 0x01u},\r
+ {0x5Bu, 0x80u},\r
+ {0x5Du, 0x80u},\r
+ {0x5Eu, 0x20u},\r
+ {0x60u, 0x08u},\r
+ {0x62u, 0x89u},\r
+ {0x63u, 0x40u},\r
+ {0x65u, 0x20u},\r
+ {0x66u, 0x80u},\r
+ {0x80u, 0x04u},\r
+ {0x82u, 0x10u},\r
+ {0x84u, 0x04u},\r
+ {0x86u, 0x19u},\r
+ {0x89u, 0x02u},\r
+ {0x8Au, 0x08u},\r
+ {0x8Cu, 0x08u},\r
+ {0x8Fu, 0x98u},\r
+ {0x90u, 0x02u},\r
+ {0x92u, 0x50u},\r
+ {0x95u, 0x08u},\r
+ {0x96u, 0x04u},\r
+ {0x97u, 0x40u},\r
+ {0x9Au, 0x50u},\r
+ {0x9Cu, 0x03u},\r
+ {0x9Du, 0x60u},\r
+ {0x9Eu, 0x88u},\r
+ {0x9Fu, 0x2Au},\r
+ {0xA1u, 0x08u},\r
+ {0xA3u, 0x80u},\r
+ {0xA4u, 0x11u},\r
+ {0xA5u, 0x10u},\r
+ {0xA6u, 0x02u},\r
+ {0xA7u, 0x50u},\r
+ {0xA8u, 0x15u},\r
+ {0xA9u, 0x04u},\r
+ {0xABu, 0x84u},\r
+ {0xAEu, 0x01u},\r
+ {0xB0u, 0x04u},\r
+ {0xB2u, 0x11u},\r
+ {0xC0u, 0x98u},\r
+ {0xC2u, 0xCFu},\r
+ {0xC4u, 0x70u},\r
+ {0xCAu, 0xC1u},\r
+ {0xCCu, 0xF6u},\r
{0xCEu, 0xF7u},\r
{0xD6u, 0x3Fu},\r
{0xD8u, 0x3Fu},\r
- {0xE2u, 0x08u},\r
- {0xE6u, 0x0Fu},\r
- {0xE8u, 0x02u},\r
- {0xEAu, 0x21u},\r
- {0xEEu, 0x53u},\r
- {0x03u, 0x70u},\r
- {0x04u, 0x05u},\r
- {0x06u, 0x0Au},\r
- {0x08u, 0x06u},\r
- {0x0Au, 0x09u},\r
- {0x0Bu, 0x08u},\r
- {0x0Cu, 0x03u},\r
- {0x0Eu, 0x0Cu},\r
- {0x0Fu, 0x80u},\r
- {0x10u, 0x30u},\r
- {0x11u, 0x99u},\r
- {0x12u, 0xC0u},\r
- {0x13u, 0x22u},\r
- {0x14u, 0x0Fu},\r
- {0x15u, 0xAAu},\r
- {0x16u, 0xF0u},\r
- {0x17u, 0x55u},\r
- {0x18u, 0x60u},\r
- {0x1Au, 0x90u},\r
- {0x1Bu, 0x07u},\r
- {0x1Du, 0x44u},\r
- {0x1Fu, 0x88u},\r
- {0x28u, 0x50u},\r
- {0x2Au, 0xA0u},\r
- {0x31u, 0xF0u},\r
- {0x35u, 0x0Fu},\r
- {0x36u, 0xFFu},\r
- {0x3Eu, 0x40u},\r
- {0x56u, 0x08u},\r
- {0x58u, 0x04u},\r
- {0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
- {0x5Cu, 0x10u},\r
- {0x5Du, 0x90u},\r
- {0x5Fu, 0x01u},\r
- {0x80u, 0x3Au},\r
- {0x81u, 0x44u},\r
- {0x82u, 0x45u},\r
- {0x83u, 0x88u},\r
- {0x86u, 0x19u},\r
- {0x87u, 0x80u},\r
- {0x88u, 0x01u},\r
- {0x8Au, 0x06u},\r
- {0x8Cu, 0x2Au},\r
- {0x8Du, 0x99u},\r
- {0x8Eu, 0x55u},\r
- {0x8Fu, 0x22u},\r
- {0x90u, 0x01u},\r
- {0x97u, 0x70u},\r
- {0x98u, 0x08u},\r
- {0x99u, 0xAAu},\r
- {0x9Bu, 0x55u},\r
- {0x9Cu, 0x18u},\r
- {0x9Eu, 0x60u},\r
- {0x9Fu, 0x07u},\r
- {0xA2u, 0x10u},\r
- {0xA3u, 0x08u},\r
- {0xA8u, 0x33u},\r
- {0xAAu, 0x4Cu},\r
- {0xB4u, 0x07u},\r
- {0xB5u, 0xF0u},\r
- {0xB6u, 0x78u},\r
- {0xB7u, 0x0Fu},\r
- {0xBAu, 0xA0u},\r
- {0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDCu, 0x11u},\r
- {0xDFu, 0x01u},\r
- {0x00u, 0x84u},\r
- {0x03u, 0x04u},\r
- {0x05u, 0x10u},\r
- {0x06u, 0x20u},\r
- {0x07u, 0x41u},\r
- {0x0Bu, 0x54u},\r
- {0x0Eu, 0x06u},\r
- {0x0Fu, 0x80u},\r
- {0x10u, 0x08u},\r
- {0x16u, 0x80u},\r
- {0x17u, 0x10u},\r
- {0x1Au, 0x02u},\r
- {0x1Du, 0x30u},\r
- {0x1Eu, 0x02u},\r
- {0x20u, 0x84u},\r
- {0x21u, 0x01u},\r
- {0x22u, 0x10u},\r
- {0x24u, 0x02u},\r
- {0x26u, 0x80u},\r
- {0x27u, 0x04u},\r
- {0x2Du, 0x01u},\r
- {0x31u, 0x08u},\r
- {0x32u, 0x10u},\r
- {0x33u, 0x41u},\r
- {0x36u, 0x80u},\r
- {0x37u, 0x14u},\r
- {0x39u, 0x02u},\r
- {0x3Au, 0x50u},\r
- {0x3Du, 0x82u},\r
- {0x3Eu, 0x08u},\r
- {0x58u, 0x80u},\r
- {0x5Cu, 0x60u},\r
- {0x5Du, 0x0Au},\r
- {0x60u, 0x01u},\r
- {0x64u, 0x01u},\r
- {0x68u, 0x04u},\r
- {0x69u, 0x84u},\r
- {0x6Au, 0x81u},\r
- {0x70u, 0x08u},\r
- {0x73u, 0x45u},\r
- {0x88u, 0xA1u},\r
- {0x8Eu, 0x40u},\r
- {0x90u, 0x40u},\r
- {0x91u, 0x11u},\r
- {0x92u, 0x44u},\r
- {0x93u, 0x0Au},\r
- {0x94u, 0x21u},\r
- {0x95u, 0x4Cu},\r
- {0x96u, 0x20u},\r
- {0x97u, 0x54u},\r
- {0x99u, 0x88u},\r
- {0x9Au, 0xD8u},\r
- {0x9Bu, 0x51u},\r
- {0x9Cu, 0x14u},\r
- {0x9Eu, 0x22u},\r
- {0x9Fu, 0x0Cu},\r
- {0xA0u, 0x01u},\r
- {0xA1u, 0xDDu},\r
- {0xA2u, 0x18u},\r
- {0xA3u, 0x63u},\r
- {0xA4u, 0xC8u},\r
- {0xA5u, 0x20u},\r
- {0xA7u, 0x10u},\r
- {0xA8u, 0x01u},\r
- {0xA9u, 0x02u},\r
- {0xABu, 0x02u},\r
- {0xAEu, 0x08u},\r
- {0xB3u, 0x01u},\r
- {0xB6u, 0x40u},\r
- {0xB7u, 0x60u},\r
- {0xC0u, 0xF7u},\r
- {0xC2u, 0xDEu},\r
- {0xC4u, 0x52u},\r
- {0xCAu, 0x80u},\r
- {0xCCu, 0x7Fu},\r
- {0xCEu, 0xDDu},\r
- {0xD6u, 0xF8u},\r
- {0xD8u, 0x18u},\r
- {0xE8u, 0x01u},\r
- {0xEAu, 0x0Cu},\r
+ {0xE2u, 0x38u},\r
+ {0xE4u, 0x04u},\r
+ {0xE6u, 0x4Bu},\r
+ {0xEAu, 0x2Cu},\r
{0xEEu, 0x04u},\r
- {0x01u, 0x33u},\r
- {0x03u, 0xCCu},\r
- {0x06u, 0x12u},\r
- {0x08u, 0x88u},\r
- {0x0Au, 0x03u},\r
- {0x0Bu, 0xFFu},\r
- {0x0Eu, 0x01u},\r
- {0x0Fu, 0xFFu},\r
- {0x14u, 0xE0u},\r
- {0x15u, 0xFFu},\r
- {0x18u, 0x21u},\r
- {0x19u, 0xFFu},\r
- {0x1Au, 0x02u},\r
- {0x1Du, 0x0Fu},\r
- {0x1Eu, 0xECu},\r
- {0x1Fu, 0xF0u},\r
- {0x23u, 0xFFu},\r
- {0x24u, 0x04u},\r
- {0x26u, 0x43u},\r
- {0x29u, 0x55u},\r
- {0x2Bu, 0xAAu},\r
- {0x2Du, 0x69u},\r
- {0x2Fu, 0x96u},\r
- {0x30u, 0x10u},\r
- {0x34u, 0xE0u},\r
- {0x36u, 0x0Fu},\r
- {0x37u, 0xFFu},\r
+ {0x00u, 0x02u},\r
+ {0x01u, 0x02u},\r
+ {0x03u, 0x0Du},\r
+ {0x05u, 0x0Du},\r
+ {0x0Bu, 0x10u},\r
+ {0x0Du, 0x0Du},\r
+ {0x11u, 0x02u},\r
+ {0x13u, 0x54u},\r
+ {0x15u, 0x0Du},\r
+ {0x19u, 0x01u},\r
+ {0x1Bu, 0x32u},\r
+ {0x1Du, 0x0Du},\r
+ {0x21u, 0x0Du},\r
+ {0x25u, 0x62u},\r
+ {0x27u, 0x08u},\r
+ {0x28u, 0x01u},\r
+ {0x29u, 0x80u},\r
+ {0x30u, 0x01u},\r
+ {0x33u, 0x70u},\r
+ {0x35u, 0x80u},\r
+ {0x36u, 0x02u},\r
+ {0x37u, 0x0Fu},\r
{0x3Bu, 0x80u},\r
- {0x3Eu, 0x10u},\r
- {0x54u, 0x01u},\r
+ {0x3Eu, 0x41u},\r
+ {0x3Fu, 0x10u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
- {0x5Cu, 0x10u},\r
- {0x5Du, 0x10u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x03u},\r
- {0x81u, 0x22u},\r
- {0x82u, 0x0Cu},\r
- {0x83u, 0x10u},\r
- {0x84u, 0x20u},\r
- {0x85u, 0x29u},\r
- {0x86u, 0x4Fu},\r
- {0x87u, 0x16u},\r
- {0x89u, 0x17u},\r
- {0x8Au, 0x70u},\r
- {0x8Bu, 0x28u},\r
- {0x8Cu, 0x05u},\r
- {0x8Du, 0x06u},\r
- {0x8Eu, 0x0Au},\r
- {0x8Fu, 0x50u},\r
- {0x95u, 0x52u},\r
- {0x97u, 0x04u},\r
- {0x98u, 0x0Fu},\r
- {0x99u, 0x50u},\r
- {0x9Bu, 0x06u},\r
- {0x9Cu, 0x10u},\r
- {0x9Du, 0x56u},\r
- {0x9Eu, 0x2Fu},\r
- {0xA0u, 0x40u},\r
- {0xA1u, 0x56u},\r
- {0xA2u, 0x1Fu},\r
- {0xA5u, 0x04u},\r
- {0xA8u, 0x06u},\r
- {0xA9u, 0x31u},\r
- {0xAAu, 0x09u},\r
- {0xABu, 0x0Eu},\r
- {0xAFu, 0x40u},\r
- {0xB1u, 0x30u},\r
- {0xB2u, 0x7Fu},\r
- {0xB3u, 0x40u},\r
- {0xB5u, 0x0Fu},\r
- {0xB7u, 0x08u},\r
- {0xB9u, 0x20u},\r
- {0xBBu, 0x02u},\r
- {0xBFu, 0x44u},\r
- {0xD4u, 0x09u},\r
- {0xD6u, 0x04u},\r
+ {0x80u, 0x02u},\r
+ {0x88u, 0x04u},\r
+ {0xACu, 0x01u},\r
+ {0xB0u, 0x02u},\r
+ {0xB2u, 0x01u},\r
+ {0xB4u, 0x04u},\r
+ {0xBEu, 0x15u},\r
+ {0xC0u, 0x14u},\r
+ {0xC1u, 0x02u},\r
+ {0xC2u, 0x30u},\r
+ {0xC5u, 0xD2u},\r
+ {0xC6u, 0xECu},\r
+ {0xC7u, 0x0Fu},\r
+ {0xC8u, 0x1Fu},\r
+ {0xC9u, 0xFFu},\r
+ {0xCAu, 0xFFu},\r
+ {0xCBu, 0xFFu},\r
+ {0xCFu, 0x2Cu},\r
+ {0xD6u, 0x01u},\r
{0xD8u, 0x04u},\r
- {0xD9u, 0x04u},\r
+ {0xDAu, 0x04u},\r
{0xDBu, 0x04u},\r
- {0xDCu, 0x01u},\r
+ {0xDDu, 0x01u},\r
{0xDFu, 0x01u},\r
+ {0xE2u, 0xC0u},\r
+ {0xE6u, 0x80u},\r
+ {0xE8u, 0x40u},\r
+ {0xE9u, 0x40u},\r
+ {0xEEu, 0x08u},\r
{0x02u, 0x80u},\r
- {0x03u, 0x1Au},\r
- {0x04u, 0x40u},\r
- {0x05u, 0x18u},\r
- {0x09u, 0x40u},\r
- {0x0Au, 0x04u},\r
- {0x0Bu, 0x04u},\r
- {0x0Eu, 0x22u},\r
- {0x0Fu, 0x08u},\r
- {0x11u, 0x23u},\r
- {0x15u, 0x80u},\r
+ {0x05u, 0x20u},\r
+ {0x06u, 0x80u},\r
+ {0x12u, 0x08u},\r
{0x16u, 0x01u},\r
- {0x17u, 0x08u},\r
- {0x1Bu, 0x08u},\r
+ {0x19u, 0x01u},\r
+ {0x1Au, 0x01u},\r
{0x1Cu, 0x40u},\r
- {0x1Eu, 0x02u},\r
- {0x1Fu, 0x10u},\r
- {0x20u, 0x04u},\r
- {0x21u, 0x09u},\r
- {0x22u, 0x42u},\r
- {0x23u, 0x08u},\r
- {0x26u, 0x80u},\r
- {0x28u, 0x24u},\r
- {0x29u, 0x10u},\r
- {0x2Au, 0x46u},\r
- {0x2Du, 0x01u},\r
- {0x2Fu, 0x05u},\r
- {0x30u, 0x90u},\r
- {0x32u, 0x14u},\r
+ {0x1Eu, 0x28u},\r
+ {0x20u, 0x11u},\r
+ {0x23u, 0x04u},\r
+ {0x28u, 0x28u},\r
+ {0x2Au, 0x02u},\r
+ {0x30u, 0x08u},\r
+ {0x31u, 0x10u},\r
+ {0x32u, 0x01u},\r
{0x33u, 0x40u},\r
- {0x36u, 0x88u},\r
- {0x37u, 0x10u},\r
- {0x38u, 0x24u},\r
- {0x39u, 0x42u},\r
- {0x3Du, 0x80u},\r
- {0x3Eu, 0x20u},\r
- {0x3Fu, 0x02u},\r
- {0x58u, 0x28u},\r
- {0x59u, 0x01u},\r
- {0x5Au, 0x80u},\r
- {0x5Fu, 0x40u},\r
- {0x61u, 0x80u},\r
- {0x63u, 0x80u},\r
- {0x83u, 0x40u},\r
- {0x87u, 0x10u},\r
- {0x8Bu, 0x48u},\r
- {0x90u, 0x02u},\r
- {0x91u, 0x94u},\r
- {0x92u, 0x47u},\r
- {0x93u, 0x0Bu},\r
- {0x94u, 0x20u},\r
- {0x95u, 0x48u},\r
- {0x97u, 0x10u},\r
- {0x99u, 0x80u},\r
- {0x9Au, 0x20u},\r
- {0x9Bu, 0x10u},\r
- {0x9Cu, 0x14u},\r
- {0x9Eu, 0x02u},\r
- {0x9Fu, 0x08u},\r
- {0xA0u, 0x04u},\r
- {0xA1u, 0xD5u},\r
- {0xA2u, 0x18u},\r
- {0xA3u, 0x03u},\r
- {0xA4u, 0x80u},\r
- {0xA7u, 0x10u},\r
- {0xA9u, 0x08u},\r
- {0xAAu, 0x20u},\r
- {0xACu, 0x04u},\r
- {0xB0u, 0x01u},\r
- {0xB1u, 0x02u},\r
- {0xB2u, 0x01u},\r
- {0xB3u, 0x20u},\r
- {0xB6u, 0x01u},\r
- {0xC0u, 0xEFu},\r
- {0xC2u, 0xE3u},\r
- {0xC4u, 0x2Au},\r
- {0xCAu, 0xBFu},\r
- {0xCCu, 0x7Eu},\r
- {0xCEu, 0xBFu},\r
- {0xD6u, 0x1Fu},\r
- {0xD8u, 0x09u},\r
- {0xE2u, 0x09u},\r
- {0xEAu, 0x14u},\r
- {0xECu, 0x06u},\r
- {0xEEu, 0x10u},\r
- {0x9Cu, 0x20u},\r
- {0x9Eu, 0x02u},\r
- {0xA0u, 0x02u},\r
- {0xA5u, 0x11u},\r
- {0xA6u, 0x04u},\r
- {0xA9u, 0x03u},\r
- {0xABu, 0x50u},\r
- {0xADu, 0x04u},\r
- {0xB2u, 0x44u},\r
- {0xB4u, 0x40u},\r
- {0xE2u, 0x09u},\r
- {0xE8u, 0x20u},\r
- {0xEEu, 0x31u},\r
- {0x00u, 0x10u},\r
- {0x02u, 0x08u},\r
- {0x04u, 0x10u},\r
- {0x06u, 0x08u},\r
+ {0x38u, 0x11u},\r
+ {0x39u, 0x44u},\r
+ {0x44u, 0x41u},\r
+ {0x45u, 0x90u},\r
+ {0x47u, 0x26u},\r
+ {0x4Du, 0x01u},\r
+ {0x4Fu, 0x08u},\r
+ {0x54u, 0x10u},\r
+ {0x57u, 0x68u},\r
+ {0x5Cu, 0x40u},\r
+ {0x5Eu, 0x29u},\r
+ {0x65u, 0x05u},\r
+ {0x67u, 0x06u},\r
+ {0x6Cu, 0x24u},\r
+ {0x6Eu, 0x02u},\r
+ {0x6Fu, 0x01u},\r
+ {0x74u, 0x01u},\r
+ {0x75u, 0x80u},\r
+ {0x76u, 0x08u},\r
+ {0x77u, 0x10u},\r
+ {0x84u, 0x02u},\r
+ {0x89u, 0x04u},\r
+ {0x8Fu, 0x10u},\r
+ {0x92u, 0x50u},\r
+ {0x93u, 0x02u},\r
+ {0x95u, 0x09u},\r
+ {0x96u, 0x04u},\r
+ {0x98u, 0x08u},\r
+ {0x99u, 0x24u},\r
+ {0x9Au, 0x81u},\r
+ {0x9Bu, 0x02u},\r
+ {0x9Cu, 0x02u},\r
+ {0x9Fu, 0x20u},\r
+ {0xA0u, 0x04u},\r
+ {0xA1u, 0x80u},\r
+ {0xA2u, 0xA8u},\r
+ {0xA3u, 0x80u},\r
+ {0xA4u, 0x11u},\r
+ {0xA5u, 0x10u},\r
+ {0xA6u, 0x02u},\r
+ {0xA7u, 0x5Cu},\r
+ {0xA9u, 0x80u},\r
+ {0xAAu, 0x80u},\r
+ {0xACu, 0x44u},\r
+ {0xB0u, 0x20u},\r
+ {0xB3u, 0x02u},\r
+ {0xB5u, 0x80u},\r
+ {0xC0u, 0x58u},\r
+ {0xC4u, 0x82u},\r
+ {0xCAu, 0x07u},\r
+ {0xCCu, 0x0Fu},\r
+ {0xCEu, 0x0Fu},\r
+ {0xD0u, 0xF0u},\r
+ {0xD6u, 0xF0u},\r
+ {0xD8u, 0xF0u},\r
+ {0xE6u, 0x02u},\r
+ {0xEAu, 0x19u},\r
+ {0xECu, 0x05u},\r
+ {0xEEu, 0x08u},\r
+ {0x02u, 0x70u},\r
+ {0x05u, 0x01u},\r
+ {0x09u, 0x13u},\r
+ {0x0Bu, 0x2Cu},\r
+ {0x0Cu, 0xAAu},\r
+ {0x0Eu, 0x55u},\r
+ {0x10u, 0x44u},\r
+ {0x11u, 0x1Cu},\r
+ {0x12u, 0x88u},\r
+ {0x13u, 0x23u},\r
+ {0x15u, 0x08u},\r
+ {0x16u, 0x07u},\r
+ {0x17u, 0x30u},\r
+ {0x19u, 0x08u},\r
+ {0x1Eu, 0x80u},\r
+ {0x22u, 0x08u},\r
+ {0x23u, 0x0Fu},\r
+ {0x28u, 0x99u},\r
+ {0x2Au, 0x22u},\r
+ {0x2Du, 0x10u},\r
+ {0x2Fu, 0x2Au},\r
+ {0x30u, 0xF0u},\r
+ {0x32u, 0x0Fu},\r
+ {0x33u, 0x07u},\r
+ {0x35u, 0x38u},\r
+ {0x3Bu, 0x20u},\r
+ {0x54u, 0x01u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x11u},\r
+ {0x5Du, 0x10u},\r
+ {0x5Fu, 0x01u},\r
+ {0x00u, 0x05u},\r
+ {0x05u, 0x01u},\r
{0x07u, 0x02u},\r
- {0x08u, 0x08u},\r
- {0x0Au, 0x10u},\r
- {0x0Bu, 0x08u},\r
+ {0x0Bu, 0x09u},\r
{0x0Cu, 0x01u},\r
- {0x0Eu, 0x02u},\r
- {0x10u, 0x10u},\r
- {0x12u, 0x08u},\r
- {0x14u, 0x10u},\r
- {0x16u, 0x08u},\r
- {0x17u, 0x01u},\r
- {0x1Au, 0x04u},\r
- {0x1Bu, 0x04u},\r
- {0x20u, 0x02u},\r
- {0x22u, 0x01u},\r
- {0x24u, 0x02u},\r
- {0x26u, 0x01u},\r
- {0x28u, 0x02u},\r
- {0x2Au, 0x01u},\r
- {0x2Cu, 0x02u},\r
- {0x2Eu, 0x01u},\r
- {0x30u, 0x04u},\r
- {0x31u, 0x01u},\r
- {0x33u, 0x04u},\r
- {0x34u, 0x18u},\r
- {0x35u, 0x02u},\r
- {0x36u, 0x03u},\r
- {0x37u, 0x08u},\r
- {0x3Au, 0xA0u},\r
+ {0x0Eu, 0x12u},\r
+ {0x13u, 0x08u},\r
+ {0x17u, 0x21u},\r
+ {0x1Au, 0x08u},\r
+ {0x1Bu, 0x28u},\r
+ {0x1Du, 0x01u},\r
+ {0x1Eu, 0x10u},\r
+ {0x20u, 0x04u},\r
+ {0x24u, 0x30u},\r
+ {0x26u, 0x08u},\r
+ {0x27u, 0x24u},\r
+ {0x29u, 0x20u},\r
+ {0x2Au, 0x02u},\r
+ {0x2Bu, 0x01u},\r
+ {0x2Cu, 0x01u},\r
+ {0x2Fu, 0x80u},\r
+ {0x30u, 0x08u},\r
+ {0x32u, 0x01u},\r
+ {0x33u, 0x60u},\r
+ {0x36u, 0x20u},\r
+ {0x37u, 0x06u},\r
+ {0x39u, 0x46u},\r
+ {0x3Bu, 0x10u},\r
+ {0x3Cu, 0x18u},\r
+ {0x40u, 0x28u},\r
+ {0x41u, 0x08u},\r
+ {0x43u, 0x02u},\r
+ {0x49u, 0x38u},\r
+ {0x4Au, 0x80u},\r
+ {0x4Bu, 0x40u},\r
+ {0x50u, 0x02u},\r
+ {0x51u, 0x21u},\r
+ {0x52u, 0x44u},\r
+ {0x5Eu, 0x40u},\r
+ {0x60u, 0x80u},\r
+ {0x61u, 0x20u},\r
+ {0x62u, 0x40u},\r
+ {0x63u, 0x20u},\r
+ {0x83u, 0x01u},\r
+ {0x8Du, 0x01u},\r
+ {0x8Eu, 0x10u},\r
+ {0x90u, 0x08u},\r
+ {0x92u, 0x40u},\r
+ {0x95u, 0x44u},\r
+ {0x96u, 0x06u},\r
+ {0x98u, 0x41u},\r
+ {0x99u, 0x80u},\r
+ {0x9Au, 0x08u},\r
+ {0x9Bu, 0x13u},\r
+ {0x9Cu, 0x20u},\r
+ {0x9Du, 0x10u},\r
+ {0x9Eu, 0x02u},\r
+ {0x9Fu, 0x64u},\r
+ {0xA0u, 0x24u},\r
+ {0xA2u, 0x21u},\r
+ {0xA3u, 0x80u},\r
+ {0xA4u, 0x08u},\r
+ {0xA6u, 0x02u},\r
+ {0xABu, 0x40u},\r
+ {0xB1u, 0x01u},\r
+ {0xB3u, 0x08u},\r
+ {0xB4u, 0x10u},\r
+ {0xB6u, 0x10u},\r
+ {0xB7u, 0x20u},\r
+ {0xC0u, 0x9Cu},\r
+ {0xC2u, 0xB3u},\r
+ {0xC4u, 0x54u},\r
+ {0xCAu, 0x9Du},\r
+ {0xCCu, 0xEFu},\r
+ {0xCEu, 0x6Fu},\r
+ {0xD0u, 0x07u},\r
+ {0xD2u, 0x0Cu},\r
+ {0xD6u, 0x10u},\r
+ {0xD8u, 0x0Fu},\r
+ {0xE2u, 0x01u},\r
+ {0xE6u, 0x02u},\r
+ {0xE8u, 0x04u},\r
+ {0xEAu, 0x19u},\r
+ {0xEEu, 0x08u},\r
+ {0x82u, 0x10u},\r
+ {0x8Du, 0x10u},\r
+ {0x8Fu, 0x40u},\r
+ {0x92u, 0x50u},\r
+ {0x95u, 0x10u},\r
+ {0x96u, 0x08u},\r
+ {0x99u, 0x04u},\r
+ {0x9Au, 0x02u},\r
+ {0x9Fu, 0x14u},\r
+ {0xA1u, 0x04u},\r
+ {0xA5u, 0x10u},\r
+ {0xA6u, 0x0Au},\r
+ {0xA7u, 0x40u},\r
+ {0xA8u, 0x05u},\r
+ {0xB1u, 0x20u},\r
+ {0xB2u, 0x01u},\r
+ {0xB5u, 0x40u},\r
+ {0xB7u, 0x01u},\r
+ {0xE4u, 0x50u},\r
+ {0xE6u, 0x02u},\r
+ {0xE8u, 0x60u},\r
+ {0xEAu, 0x08u},\r
+ {0xECu, 0x90u},\r
+ {0xEEu, 0x08u},\r
+ {0x01u, 0xFFu},\r
+ {0x05u, 0x06u},\r
+ {0x06u, 0xFFu},\r
+ {0x07u, 0x09u},\r
+ {0x08u, 0x03u},\r
+ {0x0Au, 0x0Cu},\r
+ {0x0Bu, 0xFFu},\r
+ {0x10u, 0x0Fu},\r
+ {0x11u, 0x60u},\r
+ {0x12u, 0xF0u},\r
+ {0x13u, 0x90u},\r
+ {0x14u, 0x50u},\r
+ {0x15u, 0x05u},\r
+ {0x16u, 0xA0u},\r
+ {0x17u, 0x0Au},\r
+ {0x18u, 0x05u},\r
+ {0x19u, 0x50u},\r
+ {0x1Au, 0x0Au},\r
+ {0x1Bu, 0xA0u},\r
+ {0x1Du, 0x0Fu},\r
+ {0x1Eu, 0xFFu},\r
+ {0x1Fu, 0xF0u},\r
+ {0x21u, 0x03u},\r
+ {0x22u, 0xFFu},\r
+ {0x23u, 0x0Cu},\r
+ {0x24u, 0x30u},\r
+ {0x25u, 0x30u},\r
+ {0x26u, 0xC0u},\r
+ {0x27u, 0xC0u},\r
+ {0x28u, 0x09u},\r
+ {0x2Au, 0x06u},\r
+ {0x2Cu, 0x90u},\r
+ {0x2Eu, 0x60u},\r
+ {0x2Fu, 0xFFu},\r
+ {0x31u, 0xFFu},\r
+ {0x32u, 0xFFu},\r
+ {0x3Eu, 0x04u},\r
+ {0x3Fu, 0x01u},\r
{0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x99u},\r
{0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x82u, 0x08u},\r
- {0x83u, 0x01u},\r
- {0x86u, 0x04u},\r
- {0x89u, 0x04u},\r
- {0x8Bu, 0x02u},\r
- {0x8Du, 0x04u},\r
- {0x8Eu, 0x01u},\r
- {0x8Fu, 0x02u},\r
- {0x90u, 0x08u},\r
- {0x96u, 0x02u},\r
- {0x98u, 0x08u},\r
- {0x99u, 0x02u},\r
- {0x9Bu, 0x04u},\r
- {0x9Cu, 0x08u},\r
- {0x9Du, 0x04u},\r
- {0x9Fu, 0x02u},\r
- {0xA6u, 0x08u},\r
- {0xA9u, 0x04u},\r
- {0xABu, 0x02u},\r
- {0xB0u, 0x04u},\r
- {0xB2u, 0x02u},\r
- {0xB3u, 0x06u},\r
- {0xB4u, 0x08u},\r
- {0xB5u, 0x01u},\r
- {0xB6u, 0x01u},\r
- {0xBBu, 0x08u},\r
- {0xBEu, 0x10u},\r
+ {0x82u, 0xFFu},\r
+ {0x84u, 0x55u},\r
+ {0x86u, 0xAAu},\r
+ {0x8Au, 0xFFu},\r
+ {0x8Cu, 0x0Fu},\r
+ {0x8Eu, 0xF0u},\r
+ {0x90u, 0xFFu},\r
+ {0x91u, 0x01u},\r
+ {0x96u, 0xFFu},\r
+ {0xA4u, 0x96u},\r
+ {0xA6u, 0x69u},\r
+ {0xA8u, 0xFFu},\r
+ {0xACu, 0x33u},\r
+ {0xAEu, 0xCCu},\r
+ {0xB0u, 0xFFu},\r
+ {0xB7u, 0x01u},\r
+ {0xBAu, 0x02u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDCu, 0x99u},\r
+ {0xDBu, 0x04u},\r
+ {0xDCu, 0x91u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x0Eu},\r
- {0x01u, 0xA0u},\r
+ {0x01u, 0x04u},\r
+ {0x02u, 0x18u},\r
{0x04u, 0x40u},\r
- {0x05u, 0x06u},\r
- {0x08u, 0x02u},\r
- {0x09u, 0x20u},\r
- {0x0Au, 0x20u},\r
- {0x0Cu, 0x20u},\r
- {0x0Du, 0x02u},\r
- {0x0Fu, 0x21u},\r
- {0x12u, 0xAAu},\r
+ {0x05u, 0x02u},\r
+ {0x07u, 0x24u},\r
+ {0x09u, 0x80u},\r
+ {0x0Au, 0xF8u},\r
+ {0x0Bu, 0x02u},\r
+ {0x0Fu, 0x60u},\r
+ {0x10u, 0x11u},\r
+ {0x11u, 0xAAu},\r
+ {0x12u, 0x44u},\r
+ {0x14u, 0x0Au},\r
{0x15u, 0x08u},\r
- {0x19u, 0xB0u},\r
- {0x1Au, 0x40u},\r
+ {0x1Bu, 0x08u},\r
{0x1Cu, 0x40u},\r
- {0x1Du, 0x44u},\r
- {0x1Eu, 0x04u},\r
- {0x1Fu, 0x08u},\r
- {0x20u, 0x02u},\r
- {0x21u, 0x10u},\r
- {0x22u, 0x1Au},\r
- {0x24u, 0x20u},\r
- {0x25u, 0x04u},\r
- {0x26u, 0x20u},\r
- {0x27u, 0x10u},\r
- {0x2Fu, 0x08u},\r
- {0x32u, 0x28u},\r
- {0x35u, 0x40u},\r
- {0x37u, 0x10u},\r
- {0x38u, 0x04u},\r
- {0x39u, 0x20u},\r
- {0x3Cu, 0x40u},\r
- {0x3Fu, 0x22u},\r
- {0x58u, 0x28u},\r
- {0x5Bu, 0x40u},\r
- {0x61u, 0x20u},\r
- {0x62u, 0x80u},\r
- {0x63u, 0x22u},\r
- {0x8Eu, 0x01u},\r
- {0x90u, 0x80u},\r
- {0x91u, 0x08u},\r
- {0x93u, 0x01u},\r
- {0x94u, 0x20u},\r
- {0x95u, 0x04u},\r
- {0x96u, 0x40u},\r
- {0x98u, 0x0Au},\r
- {0x9Du, 0x91u},\r
- {0x9Eu, 0x02u},\r
- {0xA0u, 0x26u},\r
- {0xA1u, 0x02u},\r
- {0xA5u, 0x35u},\r
- {0xA6u, 0x45u},\r
- {0xAAu, 0xC0u},\r
- {0xABu, 0x08u},\r
- {0xADu, 0x04u},\r
- {0xB0u, 0x28u},\r
- {0xB2u, 0x02u},\r
- {0xB6u, 0x08u},\r
- {0xC0u, 0xBFu},\r
- {0xC2u, 0xFEu},\r
- {0xC4u, 0x2Fu},\r
- {0xCAu, 0x20u},\r
- {0xCCu, 0x36u},\r
- {0xCEu, 0xB6u},\r
- {0xD6u, 0x0Eu},\r
- {0xD8u, 0x0Eu},\r
- {0xE0u, 0x10u},\r
- {0xE2u, 0x20u},\r
- {0xEAu, 0x10u},\r
- {0xECu, 0x20u},\r
- {0xEEu, 0x55u},\r
- {0x03u, 0xFFu},\r
- {0x04u, 0x09u},\r
- {0x06u, 0x06u},\r
+ {0x1Fu, 0x02u},\r
+ {0x22u, 0x01u},\r
+ {0x24u, 0x01u},\r
+ {0x28u, 0x10u},\r
+ {0x29u, 0x01u},\r
+ {0x2Au, 0x40u},\r
+ {0x30u, 0x01u},\r
+ {0x32u, 0x54u},\r
+ {0x35u, 0x02u},\r
+ {0x3Au, 0x14u},\r
+ {0x3Bu, 0x02u},\r
+ {0x58u, 0x40u},\r
+ {0x5Cu, 0x04u},\r
+ {0x5Du, 0x60u},\r
+ {0x5Eu, 0x01u},\r
+ {0x60u, 0x02u},\r
+ {0x67u, 0x01u},\r
+ {0x6Du, 0x89u},\r
+ {0x6Eu, 0x10u},\r
+ {0x75u, 0x04u},\r
+ {0x76u, 0x8Au},\r
+ {0x86u, 0x08u},\r
+ {0x88u, 0x40u},\r
+ {0x8Bu, 0x02u},\r
+ {0x8Du, 0x05u},\r
+ {0x8Eu, 0x08u},\r
+ {0x91u, 0x0Cu},\r
+ {0x92u, 0x40u},\r
+ {0x93u, 0x40u},\r
+ {0x95u, 0x11u},\r
+ {0x96u, 0x12u},\r
+ {0x98u, 0x08u},\r
+ {0x99u, 0x02u},\r
+ {0x9Bu, 0x20u},\r
+ {0x9Cu, 0x11u},\r
+ {0x9Du, 0x01u},\r
+ {0x9Eu, 0x86u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA1u, 0x81u},\r
+ {0xA3u, 0x10u},\r
+ {0xA5u, 0x40u},\r
+ {0xA6u, 0x02u},\r
+ {0xA7u, 0x48u},\r
+ {0xA8u, 0x28u},\r
+ {0xAAu, 0x08u},\r
+ {0xABu, 0x10u},\r
+ {0xADu, 0x20u},\r
+ {0xAFu, 0x04u},\r
+ {0xB3u, 0x40u},\r
+ {0xC0u, 0xF6u},\r
+ {0xC2u, 0x3Fu},\r
+ {0xC4u, 0xEFu},\r
+ {0xCAu, 0x0Bu},\r
+ {0xCCu, 0x8Fu},\r
+ {0xCEu, 0x07u},\r
+ {0xD6u, 0xF8u},\r
+ {0xD8u, 0x18u},\r
+ {0xE2u, 0x10u},\r
+ {0xE6u, 0x80u},\r
+ {0xE8u, 0x20u},\r
+ {0xEAu, 0x98u},\r
+ {0xEEu, 0x42u},\r
{0x07u, 0xFFu},\r
- {0x08u, 0x30u},\r
- {0x09u, 0x55u},\r
- {0x0Au, 0xC0u},\r
- {0x0Bu, 0xAAu},\r
- {0x0Cu, 0x90u},\r
- {0x0Eu, 0x60u},\r
- {0x10u, 0xFFu},\r
+ {0x09u, 0x0Fu},\r
+ {0x0Bu, 0xF0u},\r
+ {0x0Du, 0xFFu},\r
+ {0x10u, 0x08u},\r
+ {0x12u, 0x05u},\r
{0x13u, 0xFFu},\r
{0x15u, 0xFFu},\r
- {0x19u, 0x0Fu},\r
- {0x1Au, 0xFFu},\r
- {0x1Bu, 0xF0u},\r
- {0x1Cu, 0x03u},\r
- {0x1Eu, 0x0Cu},\r
- {0x20u, 0x05u},\r
- {0x22u, 0x0Au},\r
- {0x24u, 0x50u},\r
- {0x25u, 0x33u},\r
- {0x26u, 0xA0u},\r
- {0x27u, 0xCCu},\r
- {0x28u, 0xFFu},\r
- {0x29u, 0xFFu},\r
- {0x2Cu, 0x0Fu},\r
- {0x2Du, 0x69u},\r
- {0x2Eu, 0xF0u},\r
- {0x2Fu, 0x96u},\r
- {0x30u, 0xFFu},\r
+ {0x19u, 0x33u},\r
+ {0x1Bu, 0xCCu},\r
+ {0x1Cu, 0x0Du},\r
+ {0x1Eu, 0x32u},\r
+ {0x20u, 0x20u},\r
+ {0x22u, 0x12u},\r
+ {0x23u, 0xFFu},\r
+ {0x25u, 0x69u},\r
+ {0x26u, 0x40u},\r
+ {0x27u, 0x96u},\r
+ {0x28u, 0x04u},\r
+ {0x2Au, 0x08u},\r
+ {0x2Cu, 0x10u},\r
+ {0x2Du, 0x55u},\r
+ {0x2Eu, 0x20u},\r
+ {0x2Fu, 0xAAu},\r
+ {0x32u, 0x40u},\r
+ {0x34u, 0x03u},\r
{0x35u, 0xFFu},\r
- {0x39u, 0x02u},\r
+ {0x36u, 0x3Cu},\r
{0x3Bu, 0x20u},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x01u},\r
+ {0x3Eu, 0x50u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Cu, 0x10u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x19u},\r
{0x5Fu, 0x01u},\r
- {0x82u, 0x10u},\r
- {0x84u, 0x02u},\r
- {0x86u, 0x01u},\r
- {0x87u, 0x04u},\r
- {0x88u, 0x01u},\r
- {0x89u, 0x02u},\r
- {0x8Au, 0x02u},\r
- {0x8Bu, 0x01u},\r
- {0x8Cu, 0x02u},\r
- {0x8Eu, 0x01u},\r
- {0x90u, 0x02u},\r
- {0x91u, 0x02u},\r
- {0x92u, 0x01u},\r
- {0x93u, 0x01u},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x01u},\r
- {0x97u, 0x02u},\r
- {0x98u, 0x02u},\r
- {0x99u, 0x02u},\r
- {0x9Au, 0x01u},\r
- {0x9Bu, 0x01u},\r
- {0xA1u, 0x02u},\r
- {0xA3u, 0x01u},\r
- {0xA6u, 0x08u},\r
- {0xAFu, 0x08u},\r
- {0xB0u, 0x08u},\r
- {0xB1u, 0x04u},\r
- {0xB2u, 0x03u},\r
- {0xB3u, 0x03u},\r
+ {0x80u, 0x01u},\r
+ {0x82u, 0x02u},\r
+ {0x89u, 0x04u},\r
+ {0x8Bu, 0x08u},\r
+ {0x92u, 0x04u},\r
+ {0x95u, 0x08u},\r
+ {0x97u, 0x04u},\r
+ {0x99u, 0x08u},\r
+ {0x9Bu, 0x05u},\r
+ {0x9Du, 0x08u},\r
+ {0x9Eu, 0x02u},\r
+ {0x9Fu, 0x04u},\r
+ {0xA2u, 0x08u},\r
+ {0xAAu, 0x01u},\r
+ {0xABu, 0x02u},\r
+ {0xADu, 0x08u},\r
+ {0xAFu, 0x04u},\r
+ {0xB0u, 0x03u},\r
+ {0xB2u, 0x08u},\r
+ {0xB3u, 0x02u},\r
{0xB4u, 0x04u},\r
- {0xB5u, 0x08u},\r
- {0xB6u, 0x10u},\r
- {0xBAu, 0x08u},\r
- {0xBBu, 0x08u},\r
+ {0xB5u, 0x0Cu},\r
+ {0xB7u, 0x01u},\r
+ {0xBBu, 0x20u},\r
+ {0xBEu, 0x01u},\r
{0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDCu, 0x99u},\r
{0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x94u},\r
- {0x01u, 0x02u},\r
- {0x03u, 0x04u},\r
- {0x05u, 0x20u},\r
- {0x06u, 0x20u},\r
- {0x07u, 0x02u},\r
- {0x09u, 0x24u},\r
- {0x0Au, 0x40u},\r
- {0x0Eu, 0x81u},\r
- {0x0Fu, 0x04u},\r
- {0x12u, 0x10u},\r
- {0x14u, 0x44u},\r
- {0x15u, 0x44u},\r
- {0x18u, 0x10u},\r
- {0x19u, 0x02u},\r
- {0x1Au, 0x02u},\r
- {0x1Bu, 0x20u},\r
- {0x1Fu, 0x01u},\r
- {0x20u, 0x88u},\r
- {0x21u, 0x04u},\r
- {0x22u, 0x08u},\r
- {0x24u, 0x80u},\r
- {0x26u, 0x20u},\r
- {0x27u, 0x08u},\r
+ {0x00u, 0x02u},\r
+ {0x08u, 0x02u},\r
+ {0x09u, 0x40u},\r
+ {0x0Du, 0x40u},\r
+ {0x0Fu, 0x80u},\r
+ {0x12u, 0x84u},\r
+ {0x15u, 0x01u},\r
+ {0x16u, 0x12u},\r
+ {0x17u, 0x10u},\r
+ {0x18u, 0x80u},\r
+ {0x19u, 0x14u},\r
+ {0x1Du, 0x80u},\r
+ {0x1Eu, 0x05u},\r
+ {0x1Fu, 0x04u},\r
+ {0x21u, 0x18u},\r
+ {0x22u, 0x80u},\r
+ {0x23u, 0x08u},\r
+ {0x25u, 0x30u},\r
{0x28u, 0x02u},\r
- {0x29u, 0x02u},\r
- {0x2Cu, 0x08u},\r
- {0x2Eu, 0x80u},\r
- {0x2Fu, 0x10u},\r
- {0x32u, 0x19u},\r
- {0x36u, 0x2Au},\r
- {0x38u, 0x04u},\r
- {0x3Au, 0x10u},\r
- {0x3Du, 0x08u},\r
- {0x3Fu, 0x21u},\r
+ {0x2Bu, 0x04u},\r
+ {0x2Du, 0x8Au},\r
+ {0x31u, 0x14u},\r
+ {0x32u, 0x80u},\r
+ {0x34u, 0x28u},\r
+ {0x36u, 0x02u},\r
+ {0x39u, 0x20u},\r
+ {0x3Du, 0x20u},\r
+ {0x3Eu, 0x08u},\r
+ {0x3Fu, 0x40u},\r
+ {0x59u, 0x20u},\r
{0x5Au, 0x80u},\r
- {0x5Bu, 0x10u},\r
+ {0x5Du, 0x42u},\r
+ {0x5Eu, 0x20u},\r
+ {0x5Fu, 0x08u},\r
{0x60u, 0x02u},\r
- {0x62u, 0x10u},\r
- {0x83u, 0x11u},\r
- {0x87u, 0x20u},\r
- {0x8Bu, 0x10u},\r
- {0x8Cu, 0x28u},\r
- {0x8Du, 0x02u},\r
- {0x8Eu, 0x01u},\r
- {0x8Fu, 0x10u},\r
- {0x90u, 0x04u},\r
+ {0x62u, 0x30u},\r
+ {0x67u, 0x02u},\r
+ {0x68u, 0x01u},\r
+ {0x69u, 0x80u},\r
+ {0x6Au, 0x40u},\r
+ {0x6Cu, 0x08u},\r
+ {0x6Du, 0x04u},\r
+ {0x6Eu, 0x80u},\r
+ {0x80u, 0x08u},\r
+ {0x82u, 0x20u},\r
+ {0x83u, 0x01u},\r
+ {0x85u, 0x04u},\r
+ {0x89u, 0x04u},\r
+ {0x8Au, 0x54u},\r
+ {0x8Du, 0x08u},\r
+ {0x8Eu, 0x40u},\r
{0x91u, 0x40u},\r
- {0x92u, 0x21u},\r
- {0x93u, 0x05u},\r
- {0x94u, 0x20u},\r
- {0x95u, 0x0Cu},\r
- {0x96u, 0x42u},\r
- {0x98u, 0x44u},\r
- {0x99u, 0x20u},\r
- {0x9Au, 0x20u},\r
- {0x9Bu, 0x02u},\r
- {0x9Cu, 0x20u},\r
- {0x9Du, 0x91u},\r
- {0x9Eu, 0x03u},\r
- {0x9Fu, 0x04u},\r
- {0xA0u, 0x02u},\r
- {0xA4u, 0x20u},\r
- {0xA5u, 0x13u},\r
- {0xA6u, 0x45u},\r
- {0xA8u, 0x40u},\r
- {0xA9u, 0x40u},\r
- {0xABu, 0x40u},\r
- {0xADu, 0x80u},\r
- {0xAFu, 0x04u},\r
- {0xC0u, 0xEFu},\r
- {0xC2u, 0xDEu},\r
- {0xC4u, 0xF4u},\r
- {0xCAu, 0x79u},\r
- {0xCCu, 0xE7u},\r
- {0xCEu, 0xE6u},\r
- {0xD6u, 0x0Cu},\r
- {0xD8u, 0x0Cu},\r
- {0xE0u, 0x70u},\r
- {0xE2u, 0x8Cu},\r
- {0xE4u, 0x50u},\r
- {0xE6u, 0x23u},\r
- {0xEAu, 0x80u},\r
- {0xEEu, 0x04u},\r
- {0x01u, 0x33u},\r
- {0x03u, 0xCCu},\r
- {0x05u, 0xFFu},\r
- {0x0Bu, 0xFFu},\r
- {0x0Du, 0x0Fu},\r
- {0x0Fu, 0xF0u},\r
- {0x11u, 0xFFu},\r
- {0x12u, 0x04u},\r
- {0x17u, 0xFFu},\r
- {0x1Bu, 0xFFu},\r
- {0x1Eu, 0x08u},\r
- {0x21u, 0x55u},\r
- {0x22u, 0x01u},\r
- {0x23u, 0xAAu},\r
- {0x25u, 0x96u},\r
- {0x26u, 0x02u},\r
- {0x27u, 0x69u},\r
- {0x2Cu, 0x01u},\r
- {0x2Eu, 0x02u},\r
+ {0x94u, 0x80u},\r
+ {0x95u, 0x14u},\r
+ {0x96u, 0x53u},\r
+ {0x99u, 0x82u},\r
+ {0x9Bu, 0x20u},\r
+ {0x9Cu, 0x11u},\r
+ {0x9Du, 0x01u},\r
+ {0x9Eu, 0x84u},\r
+ {0xA1u, 0x01u},\r
+ {0xA3u, 0x04u},\r
+ {0xA5u, 0x28u},\r
+ {0xA7u, 0x08u},\r
+ {0xA9u, 0x02u},\r
+ {0xAAu, 0x40u},\r
+ {0xADu, 0x20u},\r
+ {0xB0u, 0x20u},\r
+ {0xB3u, 0x20u},\r
+ {0xC0u, 0x08u},\r
+ {0xC2u, 0x99u},\r
+ {0xC4u, 0xFAu},\r
+ {0xCAu, 0xDCu},\r
+ {0xCCu, 0xEEu},\r
+ {0xCEu, 0x74u},\r
+ {0xD6u, 0xFCu},\r
+ {0xD8u, 0x1Cu},\r
+ {0xE0u, 0xC0u},\r
+ {0xE2u, 0x28u},\r
+ {0xE4u, 0x80u},\r
+ {0xE6u, 0x18u},\r
+ {0xECu, 0x20u},\r
+ {0xEEu, 0x80u},\r
+ {0x00u, 0x01u},\r
+ {0x02u, 0x02u},\r
+ {0x04u, 0x02u},\r
+ {0x05u, 0x02u},\r
+ {0x06u, 0x01u},\r
+ {0x09u, 0x02u},\r
+ {0x0Du, 0x08u},\r
+ {0x0Fu, 0x05u},\r
+ {0x11u, 0x02u},\r
+ {0x12u, 0x08u},\r
+ {0x14u, 0x02u},\r
+ {0x15u, 0x02u},\r
+ {0x16u, 0x01u},\r
+ {0x18u, 0x02u},\r
+ {0x19u, 0x08u},\r
+ {0x1Au, 0x05u},\r
+ {0x1Bu, 0x04u},\r
+ {0x1Du, 0x04u},\r
+ {0x1Fu, 0x08u},\r
+ {0x21u, 0x08u},\r
+ {0x23u, 0x14u},\r
+ {0x24u, 0x02u},\r
+ {0x26u, 0x11u},\r
+ {0x2Du, 0x08u},\r
+ {0x2Fu, 0x04u},\r
{0x30u, 0x03u},\r
- {0x32u, 0x08u},\r
- {0x34u, 0x04u},\r
- {0x37u, 0xFFu},\r
+ {0x31u, 0x10u},\r
+ {0x32u, 0x04u},\r
+ {0x33u, 0x02u},\r
+ {0x34u, 0x10u},\r
+ {0x35u, 0x01u},\r
+ {0x36u, 0x08u},\r
+ {0x37u, 0x0Cu},\r
+ {0x39u, 0x08u},\r
+ {0x3Au, 0x02u},\r
{0x3Bu, 0x80u},\r
- {0x3Eu, 0x01u},\r
+ {0x3Fu, 0x04u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x19u},\r
+ {0x5Cu, 0x99u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x03u},\r
- {0x83u, 0x0Cu},\r
- {0x84u, 0x06u},\r
- {0x86u, 0x09u},\r
+ {0x80u, 0x03u},\r
+ {0x81u, 0xFFu},\r
+ {0x82u, 0x0Cu},\r
+ {0x84u, 0xFFu},\r
{0x87u, 0xFFu},\r
- {0x88u, 0x30u},\r
- {0x89u, 0x06u},\r
- {0x8Au, 0xC0u},\r
- {0x8Bu, 0x09u},\r
- {0x8Cu, 0x60u},\r
+ {0x88u, 0x06u},\r
+ {0x89u, 0x05u},\r
+ {0x8Au, 0x09u},\r
+ {0x8Bu, 0x0Au},\r
{0x8Du, 0x0Fu},\r
- {0x8Eu, 0x90u},\r
{0x8Fu, 0xF0u},\r
- {0x91u, 0x60u},\r
- {0x92u, 0xFFu},\r
- {0x93u, 0x90u},\r
- {0x97u, 0xFFu},\r
- {0x9Au, 0xFFu},\r
- {0x9Cu, 0x03u},\r
- {0x9Du, 0xFFu},\r
- {0x9Eu, 0x0Cu},\r
- {0xA0u, 0x05u},\r
- {0xA1u, 0x05u},\r
- {0xA2u, 0x0Au},\r
- {0xA3u, 0x0Au},\r
- {0xA4u, 0x50u},\r
- {0xA5u, 0x50u},\r
- {0xA6u, 0xA0u},\r
- {0xA7u, 0xA0u},\r
- {0xA8u, 0xFFu},\r
- {0xA9u, 0x30u},\r
- {0xABu, 0xC0u},\r
- {0xACu, 0x0Fu},\r
- {0xAEu, 0xF0u},\r
- {0xB1u, 0xFFu},\r
- {0xB6u, 0xFFu},\r
- {0xBEu, 0x40u},\r
- {0xBFu, 0x01u},\r
- {0xD6u, 0x08u},\r
+ {0x90u, 0x0Fu},\r
+ {0x91u, 0x90u},\r
+ {0x92u, 0xF0u},\r
+ {0x93u, 0x60u},\r
+ {0x94u, 0x50u},\r
+ {0x96u, 0xA0u},\r
+ {0x98u, 0x30u},\r
+ {0x99u, 0x30u},\r
+ {0x9Au, 0xC0u},\r
+ {0x9Bu, 0xC0u},\r
+ {0x9Du, 0x03u},\r
+ {0x9Eu, 0xFFu},\r
+ {0x9Fu, 0x0Cu},\r
+ {0xA1u, 0xFFu},\r
+ {0xA5u, 0x09u},\r
+ {0xA6u, 0xFFu},\r
+ {0xA7u, 0x06u},\r
+ {0xA8u, 0x05u},\r
+ {0xA9u, 0x50u},\r
+ {0xAAu, 0x0Au},\r
+ {0xABu, 0xA0u},\r
+ {0xACu, 0x60u},\r
+ {0xAEu, 0x90u},\r
+ {0xB2u, 0xFFu},\r
+ {0xB3u, 0xFFu},\r
+ {0xBEu, 0x04u},\r
+ {0xBFu, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDBu, 0x04u},\r
- {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x05u, 0x20u},\r
- {0x06u, 0x20u},\r
- {0x07u, 0x02u},\r
- {0x0Au, 0x42u},\r
- {0x0Eu, 0x81u},\r
- {0x0Fu, 0x04u},\r
- {0x10u, 0x40u},\r
- {0x11u, 0x44u},\r
- {0x14u, 0x44u},\r
- {0x15u, 0x44u},\r
- {0x18u, 0x04u},\r
- {0x19u, 0x02u},\r
- {0x1Au, 0x20u},\r
- {0x1Du, 0x80u},\r
+ {0x01u, 0x0Au},\r
+ {0x04u, 0x08u},\r
+ {0x05u, 0x01u},\r
+ {0x06u, 0x0Cu},\r
+ {0x07u, 0x40u},\r
+ {0x08u, 0x02u},\r
+ {0x09u, 0x08u},\r
+ {0x0Au, 0x04u},\r
+ {0x0Cu, 0x10u},\r
+ {0x0Eu, 0x51u},\r
+ {0x12u, 0x10u},\r
+ {0x14u, 0x01u},\r
+ {0x15u, 0x14u},\r
+ {0x19u, 0x0Au},\r
+ {0x1Au, 0x04u},\r
+ {0x1Bu, 0x84u},\r
+ {0x1Fu, 0x04u},\r
{0x21u, 0x40u},\r
- {0x27u, 0x40u},\r
- {0x28u, 0x20u},\r
- {0x2Au, 0x01u},\r
- {0x2Cu, 0x40u},\r
- {0x2Du, 0x24u},\r
- {0x2Eu, 0x02u},\r
- {0x30u, 0x28u},\r
- {0x31u, 0x02u},\r
- {0x34u, 0x04u},\r
- {0x36u, 0x45u},\r
- {0x37u, 0x02u},\r
+ {0x22u, 0x58u},\r
+ {0x23u, 0x40u},\r
+ {0x24u, 0x20u},\r
+ {0x28u, 0x02u},\r
+ {0x2Bu, 0x80u},\r
+ {0x2Eu, 0x19u},\r
+ {0x32u, 0x51u},\r
+ {0x33u, 0x08u},\r
+ {0x34u, 0x11u},\r
+ {0x37u, 0x40u},\r
{0x38u, 0x20u},\r
- {0x39u, 0x88u},\r
- {0x3Bu, 0x0Au},\r
- {0x3Du, 0x62u},\r
- {0x3Eu, 0x21u},\r
- {0x3Fu, 0x04u},\r
- {0x59u, 0x91u},\r
+ {0x3Bu, 0x48u},\r
+ {0x3Du, 0x16u},\r
+ {0x3Eu, 0x40u},\r
+ {0x58u, 0xA0u},\r
+ {0x60u, 0x02u},\r
+ {0x62u, 0x10u},\r
+ {0x79u, 0xC0u},\r
+ {0x80u, 0x44u},\r
+ {0x81u, 0x01u},\r
+ {0x84u, 0x80u},\r
+ {0x85u, 0x80u},\r
+ {0x86u, 0x80u},\r
+ {0x8Eu, 0x08u},\r
+ {0xC0u, 0x7Cu},\r
+ {0xC2u, 0xFEu},\r
+ {0xC4u, 0xE4u},\r
+ {0xCAu, 0xE9u},\r
+ {0xCCu, 0xBFu},\r
+ {0xCEu, 0xFEu},\r
+ {0xD6u, 0x0Cu},\r
+ {0xD8u, 0x0Cu},\r
+ {0xE0u, 0x01u},\r
+ {0xE2u, 0x10u},\r
+ {0xE6u, 0x46u},\r
+ {0x00u, 0x0Cu},\r
+ {0x02u, 0x10u},\r
+ {0x04u, 0x11u},\r
+ {0x06u, 0x62u},\r
+ {0x08u, 0xC0u},\r
+ {0x0Cu, 0x1Cu},\r
+ {0x0Du, 0x04u},\r
+ {0x0Fu, 0x03u},\r
+ {0x10u, 0x24u},\r
+ {0x11u, 0x23u},\r
+ {0x12u, 0x10u},\r
+ {0x13u, 0x04u},\r
+ {0x14u, 0x70u},\r
+ {0x15u, 0x25u},\r
+ {0x16u, 0x0Fu},\r
+ {0x17u, 0x02u},\r
+ {0x1Bu, 0x08u},\r
+ {0x1Cu, 0x1Cu},\r
+ {0x20u, 0x08u},\r
+ {0x21u, 0x08u},\r
+ {0x23u, 0x10u},\r
+ {0x24u, 0x14u},\r
+ {0x26u, 0x08u},\r
+ {0x28u, 0x10u},\r
+ {0x29u, 0x21u},\r
+ {0x2Au, 0x0Cu},\r
+ {0x2Bu, 0x06u},\r
+ {0x2Cu, 0x21u},\r
+ {0x2Eu, 0x9Eu},\r
+ {0x2Fu, 0x10u},\r
+ {0x30u, 0x30u},\r
+ {0x31u, 0x07u},\r
+ {0x32u, 0xC1u},\r
+ {0x34u, 0x0Fu},\r
+ {0x35u, 0x18u},\r
+ {0x37u, 0x20u},\r
+ {0x38u, 0x08u},\r
+ {0x3Au, 0x02u},\r
+ {0x3Bu, 0x02u},\r
+ {0x3Fu, 0x50u},\r
+ {0x54u, 0x09u},\r
+ {0x56u, 0x04u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x40u},\r
- {0x61u, 0x40u},\r
- {0x67u, 0x02u},\r
- {0x68u, 0x02u},\r
- {0x69u, 0x40u},\r
- {0x80u, 0x08u},\r
- {0x83u, 0x01u},\r
- {0x85u, 0x60u},\r
- {0x87u, 0x04u},\r
- {0x89u, 0x02u},\r
- {0xC0u, 0xE0u},\r
- {0xC2u, 0xD9u},\r
- {0xC4u, 0xFDu},\r
- {0xCAu, 0xE3u},\r
- {0xCCu, 0xD7u},\r
- {0xCEu, 0xFFu},\r
- {0xD6u, 0x1Fu},\r
- {0xD8u, 0x18u},\r
- {0x80u, 0x02u},\r
- {0x81u, 0x44u},\r
- {0x82u, 0x41u},\r
- {0x83u, 0x88u},\r
- {0x8Bu, 0x80u},\r
- {0x8Du, 0x99u},\r
- {0x8Fu, 0x22u},\r
- {0x94u, 0x53u},\r
- {0x96u, 0xACu},\r
- {0x97u, 0x07u},\r
- {0x98u, 0x01u},\r
- {0x99u, 0xAAu},\r
- {0x9Au, 0x12u},\r
- {0x9Bu, 0x55u},\r
- {0x9Cu, 0x08u},\r
- {0x9Eu, 0x84u},\r
- {0x9Fu, 0x70u},\r
- {0xA8u, 0x04u},\r
- {0xAAu, 0x28u},\r
- {0xAFu, 0x08u},\r
- {0xB2u, 0xC0u},\r
- {0xB3u, 0x0Fu},\r
- {0xB4u, 0x30u},\r
- {0xB6u, 0x0Fu},\r
- {0xB7u, 0xF0u},\r
- {0xBEu, 0x54u},\r
+ {0x5Fu, 0x01u},\r
+ {0x83u, 0x17u},\r
+ {0x87u, 0x40u},\r
+ {0x88u, 0x21u},\r
+ {0x8Au, 0x02u},\r
+ {0x91u, 0x04u},\r
+ {0x92u, 0x01u},\r
+ {0x93u, 0x08u},\r
+ {0x94u, 0x88u},\r
+ {0x95u, 0x09u},\r
+ {0x96u, 0x03u},\r
+ {0x97u, 0x02u},\r
+ {0x9Au, 0xECu},\r
+ {0x9Bu, 0x08u},\r
+ {0x9Du, 0x0Au},\r
+ {0x9Fu, 0x05u},\r
+ {0xA1u, 0x50u},\r
+ {0xA2u, 0x12u},\r
+ {0xA3u, 0xA0u},\r
+ {0xA4u, 0xE0u},\r
+ {0xA7u, 0x20u},\r
+ {0xACu, 0x04u},\r
+ {0xAEu, 0x43u},\r
+ {0xAFu, 0x80u},\r
+ {0xB0u, 0x10u},\r
+ {0xB1u, 0x0Fu},\r
+ {0xB4u, 0x0Fu},\r
+ {0xB5u, 0xC0u},\r
+ {0xB6u, 0xE0u},\r
+ {0xB7u, 0x30u},\r
+ {0xBEu, 0x40u},\r
+ {0xBFu, 0x50u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDCu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x08u},\r
- {0x02u, 0x01u},\r
- {0x03u, 0x84u},\r
- {0x04u, 0x02u},\r
- {0x08u, 0x02u},\r
- {0x0Au, 0x02u},\r
- {0x0Bu, 0x14u},\r
- {0x0Eu, 0x09u},\r
- {0x0Fu, 0x10u},\r
- {0x10u, 0x10u},\r
+ {0x00u, 0x82u},\r
+ {0x03u, 0x2Cu},\r
+ {0x05u, 0x20u},\r
+ {0x09u, 0x08u},\r
+ {0x0Au, 0x41u},\r
+ {0x0Du, 0x0Au},\r
+ {0x0Eu, 0x08u},\r
+ {0x10u, 0x08u},\r
{0x11u, 0x04u},\r
{0x12u, 0x80u},\r
- {0x17u, 0x20u},\r
- {0x1Bu, 0x10u},\r
- {0x1Eu, 0x04u},\r
- {0x1Fu, 0x84u},\r
- {0x21u, 0x08u},\r
- {0x22u, 0x20u},\r
- {0x23u, 0x40u},\r
- {0x26u, 0x84u},\r
- {0x28u, 0x12u},\r
- {0x2Au, 0x01u},\r
- {0x2Bu, 0x08u},\r
- {0x2Du, 0x80u},\r
- {0x32u, 0x20u},\r
- {0x33u, 0x04u},\r
- {0x36u, 0x84u},\r
+ {0x13u, 0x80u},\r
+ {0x15u, 0x02u},\r
+ {0x17u, 0x84u},\r
+ {0x19u, 0x20u},\r
+ {0x1Au, 0x40u},\r
+ {0x1Bu, 0x29u},\r
+ {0x1Du, 0x02u},\r
+ {0x1Eu, 0x0Au},\r
+ {0x20u, 0x48u},\r
+ {0x21u, 0x80u},\r
+ {0x24u, 0x02u},\r
+ {0x25u, 0x11u},\r
+ {0x26u, 0x02u},\r
+ {0x29u, 0x20u},\r
+ {0x2Au, 0x03u},\r
+ {0x2Bu, 0x02u},\r
+ {0x2Eu, 0x0Au},\r
+ {0x2Fu, 0x01u},\r
+ {0x31u, 0x08u},\r
+ {0x32u, 0x21u},\r
+ {0x34u, 0x41u},\r
+ {0x36u, 0x08u},\r
{0x37u, 0x10u},\r
- {0x38u, 0x44u},\r
- {0x3Bu, 0x10u},\r
- {0x3Du, 0x92u},\r
- {0x40u, 0x04u},\r
- {0x43u, 0x0Au},\r
- {0x49u, 0x1Au},\r
- {0x4Au, 0x01u},\r
- {0x51u, 0x20u},\r
- {0x52u, 0x44u},\r
- {0x62u, 0x20u},\r
- {0x69u, 0x48u},\r
- {0x6Au, 0x28u},\r
- {0x6Bu, 0x40u},\r
- {0x72u, 0x02u},\r
- {0x73u, 0x01u},\r
- {0x83u, 0x80u},\r
- {0x86u, 0x04u},\r
- {0x88u, 0x08u},\r
- {0x89u, 0x0Au},\r
- {0x8Bu, 0x40u},\r
- {0x8Cu, 0x40u},\r
+ {0x38u, 0x40u},\r
+ {0x3Du, 0x0Au},\r
+ {0x59u, 0x1Au},\r
+ {0x5Au, 0x80u},\r
+ {0x61u, 0x80u},\r
+ {0x63u, 0x80u},\r
+ {0x82u, 0x08u},\r
+ {0x83u, 0x40u},\r
{0x8Du, 0x10u},\r
- {0x8Eu, 0x01u},\r
- {0x90u, 0x06u},\r
- {0x91u, 0x14u},\r
- {0x92u, 0x03u},\r
- {0x93u, 0x14u},\r
- {0x95u, 0x48u},\r
- {0x96u, 0x28u},\r
- {0x97u, 0x09u},\r
- {0x98u, 0x02u},\r
- {0x99u, 0x90u},\r
+ {0x8Eu, 0x81u},\r
+ {0x8Fu, 0x02u},\r
+ {0x91u, 0x06u},\r
+ {0x92u, 0x83u},\r
+ {0x93u, 0x02u},\r
+ {0x94u, 0x42u},\r
+ {0x96u, 0x40u},\r
+ {0x98u, 0x41u},\r
+ {0x99u, 0x0Au},\r
{0x9Au, 0x01u},\r
- {0x9Bu, 0x34u},\r
- {0x9Cu, 0x08u},\r
- {0x9Du, 0x08u},\r
- {0x9Eu, 0x46u},\r
- {0x9Fu, 0x40u},\r
- {0xA0u, 0x04u},\r
- {0xA1u, 0x41u},\r
- {0xA3u, 0x0Au},\r
- {0xA5u, 0x20u},\r
- {0xA6u, 0x80u},\r
- {0xA7u, 0x10u},\r
- {0xB2u, 0x80u},\r
- {0xB6u, 0x01u},\r
- {0xC0u, 0x1Fu},\r
- {0xC2u, 0xEFu},\r
- {0xC4u, 0x4Cu},\r
- {0xCAu, 0x1Fu},\r
- {0xCCu, 0x76u},\r
- {0xCEu, 0xBEu},\r
- {0xD0u, 0x07u},\r
- {0xD2u, 0x0Cu},\r
- {0xD8u, 0x04u},\r
- {0xE0u, 0x10u},\r
- {0xE4u, 0x04u},\r
- {0x00u, 0x01u},\r
- {0x01u, 0x44u},\r
- {0x03u, 0x88u},\r
- {0x04u, 0x10u},\r
- {0x07u, 0x80u},\r
- {0x08u, 0xA2u},\r
- {0x0Au, 0x08u},\r
- {0x0Cu, 0x04u},\r
- {0x0Du, 0x99u},\r
- {0x0Fu, 0x22u},\r
- {0x12u, 0x40u},\r
- {0x13u, 0x70u},\r
- {0x14u, 0x01u},\r
- {0x17u, 0x07u},\r
- {0x18u, 0x07u},\r
- {0x19u, 0xAAu},\r
- {0x1Au, 0xD8u},\r
- {0x1Bu, 0x55u},\r
- {0x1Cu, 0x01u},\r
- {0x20u, 0x01u},\r
- {0x24u, 0x08u},\r
- {0x26u, 0x61u},\r
- {0x2Cu, 0x01u},\r
+ {0x9Bu, 0x90u},\r
+ {0x9Du, 0x20u},\r
+ {0xA0u, 0x49u},\r
+ {0xA1u, 0x0Cu},\r
+ {0xA2u, 0xA8u},\r
+ {0xA4u, 0x04u},\r
+ {0xA5u, 0x10u},\r
+ {0xA6u, 0x02u},\r
+ {0xA7u, 0x21u},\r
+ {0xA9u, 0x04u},\r
+ {0xAFu, 0x08u},\r
+ {0xB4u, 0x08u},\r
+ {0xC0u, 0x4Fu},\r
+ {0xC2u, 0x7Du},\r
+ {0xC4u, 0xBFu},\r
+ {0xCAu, 0xDDu},\r
+ {0xCCu, 0xF7u},\r
+ {0xCEu, 0xC8u},\r
+ {0xD6u, 0x0Fu},\r
+ {0xD8u, 0x09u},\r
+ {0xE2u, 0x10u},\r
+ {0xE6u, 0x01u},\r
+ {0xE8u, 0x4Cu},\r
+ {0x06u, 0x08u},\r
+ {0x07u, 0x07u},\r
+ {0x08u, 0x99u},\r
+ {0x0Au, 0x22u},\r
+ {0x11u, 0x44u},\r
+ {0x13u, 0x88u},\r
+ {0x16u, 0x07u},\r
+ {0x17u, 0x70u},\r
+ {0x19u, 0x99u},\r
+ {0x1Au, 0x70u},\r
+ {0x1Bu, 0x22u},\r
+ {0x1Du, 0xAAu},\r
+ {0x1Fu, 0x55u},\r
+ {0x20u, 0xAAu},\r
+ {0x22u, 0x55u},\r
+ {0x27u, 0x80u},\r
+ {0x2Au, 0x80u},\r
+ {0x2Cu, 0x44u},\r
+ {0x2Eu, 0x88u},\r
{0x2Fu, 0x08u},\r
- {0x30u, 0xE0u},\r
- {0x31u, 0xF0u},\r
- {0x35u, 0x0Fu},\r
- {0x36u, 0x3Fu},\r
- {0x38u, 0x80u},\r
- {0x3Eu, 0x40u},\r
+ {0x32u, 0x0Fu},\r
+ {0x33u, 0x0Fu},\r
+ {0x34u, 0xF0u},\r
+ {0x35u, 0xF0u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Cu, 0x10u},\r
+ {0x5Cu, 0x11u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0xE4u},\r
- {0x81u, 0x80u},\r
- {0x86u, 0x75u},\r
- {0x87u, 0xFFu},\r
- {0x88u, 0x07u},\r
- {0x89u, 0x1Fu},\r
- {0x8Au, 0x10u},\r
- {0x8Bu, 0x20u},\r
- {0x8Cu, 0x64u},\r
- {0x8Du, 0x90u},\r
- {0x8Eu, 0x80u},\r
- {0x8Fu, 0x40u},\r
- {0x90u, 0x08u},\r
- {0x94u, 0x80u},\r
- {0x95u, 0xC0u},\r
- {0x96u, 0x64u},\r
- {0x97u, 0x04u},\r
- {0x98u, 0xA4u},\r
- {0x99u, 0xC0u},\r
- {0x9Au, 0x40u},\r
- {0x9Bu, 0x08u},\r
+ {0x80u, 0xC1u},\r
+ {0x81u, 0x34u},\r
+ {0x84u, 0x07u},\r
+ {0x85u, 0x14u},\r
+ {0x86u, 0x18u},\r
+ {0x87u, 0x20u},\r
+ {0x8Au, 0x80u},\r
+ {0x8Bu, 0x34u},\r
+ {0x8Cu, 0x01u},\r
+ {0x8Du, 0x34u},\r
+ {0x8Eu, 0xC0u},\r
+ {0x90u, 0x01u},\r
+ {0x91u, 0x4Bu},\r
+ {0x93u, 0x30u},\r
+ {0x94u, 0x22u},\r
+ {0x95u, 0x08u},\r
+ {0x96u, 0x08u},\r
+ {0x97u, 0x75u},\r
+ {0x98u, 0x04u},\r
{0x9Cu, 0x08u},\r
- {0x9Du, 0xC0u},\r
+ {0x9Du, 0x20u},\r
+ {0x9Eu, 0x21u},\r
{0x9Fu, 0x02u},\r
- {0xA0u, 0xE4u},\r
- {0xA1u, 0xC0u},\r
- {0xA3u, 0x01u},\r
- {0xA4u, 0x03u},\r
- {0xA6u, 0x70u},\r
- {0xA7u, 0x9Fu},\r
- {0xA8u, 0x40u},\r
- {0xA9u, 0x7Fu},\r
- {0xAAu, 0x02u},\r
- {0xABu, 0x80u},\r
- {0xACu, 0x24u},\r
- {0xAFu, 0x60u},\r
- {0xB0u, 0x80u},\r
- {0xB2u, 0x71u},\r
- {0xB4u, 0x07u},\r
- {0xB6u, 0x08u},\r
- {0xB7u, 0xFFu},\r
+ {0xA0u, 0xC1u},\r
+ {0xA1u, 0x34u},\r
+ {0xA4u, 0xC1u},\r
+ {0xA8u, 0xC0u},\r
+ {0xA9u, 0x3Fu},\r
+ {0xABu, 0x40u},\r
+ {0xACu, 0x10u},\r
+ {0xADu, 0x14u},\r
+ {0xB0u, 0x40u},\r
+ {0xB1u, 0x78u},\r
+ {0xB3u, 0x07u},\r
+ {0xB4u, 0x80u},\r
+ {0xB6u, 0x3Fu},\r
+ {0xB7u, 0x40u},\r
{0xB8u, 0x80u},\r
- {0xBAu, 0x30u},\r
- {0xBEu, 0x01u},\r
+ {0xB9u, 0x02u},\r
+ {0xBBu, 0x0Cu},\r
+ {0xBEu, 0x51u},\r
{0xBFu, 0x40u},\r
- {0xD4u, 0x40u},\r
- {0xD6u, 0x04u},\r
+ {0xD6u, 0x02u},\r
+ {0xD7u, 0x2Cu},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
{0xDFu, 0x01u},\r
{0x01u, 0x40u},\r
- {0x03u, 0x68u},\r
- {0x05u, 0x58u},\r
- {0x07u, 0x40u},\r
- {0x09u, 0x80u},\r
- {0x0Au, 0x28u},\r
- {0x0Bu, 0x80u},\r
- {0x0Du, 0x04u},\r
- {0x0Eu, 0x80u},\r
- {0x0Fu, 0x09u},\r
- {0x12u, 0x06u},\r
- {0x13u, 0x09u},\r
- {0x15u, 0x42u},\r
- {0x17u, 0x08u},\r
- {0x18u, 0x20u},\r
- {0x19u, 0x51u},\r
- {0x1Bu, 0x2Eu},\r
- {0x1Eu, 0x80u},\r
- {0x1Fu, 0x40u},\r
- {0x21u, 0x80u},\r
- {0x26u, 0x01u},\r
- {0x27u, 0x04u},\r
- {0x29u, 0x58u},\r
+ {0x02u, 0x04u},\r
+ {0x03u, 0x60u},\r
+ {0x04u, 0x28u},\r
+ {0x0Au, 0x4Au},\r
+ {0x0Bu, 0x10u},\r
+ {0x0Eu, 0x28u},\r
+ {0x10u, 0x8Au},\r
+ {0x11u, 0x04u},\r
+ {0x14u, 0x41u},\r
+ {0x16u, 0x08u},\r
+ {0x18u, 0x01u},\r
+ {0x19u, 0x02u},\r
+ {0x1Bu, 0x12u},\r
+ {0x1Eu, 0x2Cu},\r
+ {0x21u, 0x08u},\r
+ {0x22u, 0x41u},\r
+ {0x23u, 0xD0u},\r
+ {0x25u, 0x04u},\r
+ {0x26u, 0x20u},\r
+ {0x27u, 0x08u},\r
+ {0x29u, 0x20u},\r
{0x2Au, 0x02u},\r
- {0x2Eu, 0x40u},\r
- {0x32u, 0x14u},\r
- {0x33u, 0x40u},\r
- {0x34u, 0x02u},\r
- {0x36u, 0x01u},\r
- {0x37u, 0x14u},\r
- {0x38u, 0x24u},\r
- {0x39u, 0x42u},\r
- {0x3Du, 0x8Au},\r
- {0x61u, 0x28u},\r
- {0x62u, 0x40u},\r
- {0x63u, 0x40u},\r
- {0x87u, 0x40u},\r
- {0x8Au, 0x40u},\r
- {0x8Bu, 0x04u},\r
- {0x90u, 0x06u},\r
- {0x91u, 0x16u},\r
- {0x92u, 0x43u},\r
- {0x93u, 0x14u},\r
- {0x94u, 0x20u},\r
- {0x95u, 0x48u},\r
- {0x96u, 0x28u},\r
- {0x99u, 0x80u},\r
- {0x9Au, 0x01u},\r
- {0x9Bu, 0x38u},\r
+ {0x2Bu, 0x01u},\r
+ {0x2Cu, 0x20u},\r
+ {0x2Du, 0x80u},\r
+ {0x31u, 0x08u},\r
+ {0x32u, 0x81u},\r
+ {0x34u, 0x41u},\r
+ {0x37u, 0x28u},\r
+ {0x39u, 0x55u},\r
+ {0x3Du, 0x08u},\r
+ {0x60u, 0x40u},\r
+ {0x68u, 0x49u},\r
+ {0x69u, 0x55u},\r
+ {0x6Bu, 0x40u},\r
+ {0x70u, 0x80u},\r
+ {0x72u, 0x03u},\r
+ {0x83u, 0x01u},\r
+ {0x88u, 0x04u},\r
+ {0x8Cu, 0x01u},\r
+ {0x8Du, 0x10u},\r
+ {0x90u, 0x28u},\r
+ {0x91u, 0x02u},\r
+ {0x92u, 0x08u},\r
+ {0x94u, 0x01u},\r
+ {0x95u, 0x44u},\r
+ {0x96u, 0x06u},\r
+ {0x97u, 0x50u},\r
+ {0x98u, 0x41u},\r
+ {0x99u, 0x88u},\r
+ {0x9Au, 0x0Du},\r
+ {0x9Bu, 0x30u},\r
{0x9Cu, 0x08u},\r
- {0x9Du, 0x19u},\r
- {0x9Eu, 0x46u},\r
- {0x9Fu, 0x44u},\r
- {0xA0u, 0x04u},\r
- {0xA1u, 0x4Du},\r
- {0xA2u, 0x02u},\r
- {0xA7u, 0x14u},\r
- {0xABu, 0x04u},\r
- {0xAFu, 0x10u},\r
- {0xB7u, 0x21u},\r
- {0xC0u, 0xFFu},\r
- {0xC2u, 0xFFu},\r
- {0xC4u, 0xBFu},\r
- {0xCAu, 0x1Fu},\r
- {0xCCu, 0xEEu},\r
- {0xCEu, 0xDFu},\r
- {0xD8u, 0x0Fu},\r
- {0xE2u, 0x20u},\r
- {0xE8u, 0x01u},\r
- {0xEAu, 0x08u},\r
- {0x9Cu, 0x20u},\r
+ {0x9Du, 0x20u},\r
{0x9Eu, 0x02u},\r
- {0xA5u, 0x01u},\r
- {0xA6u, 0x04u},\r
- {0xA9u, 0x10u},\r
- {0xACu, 0x02u},\r
- {0xE0u, 0x80u},\r
- {0x82u, 0x04u},\r
- {0x8Cu, 0x20u},\r
- {0x9Cu, 0x20u},\r
- {0xA6u, 0x04u},\r
- {0xB2u, 0x02u},\r
- {0xB5u, 0x01u},\r
+ {0x9Fu, 0x40u},\r
+ {0xA0u, 0x22u},\r
+ {0xA2u, 0x88u},\r
+ {0xA4u, 0x08u},\r
+ {0xA5u, 0x08u},\r
+ {0xA6u, 0x12u},\r
+ {0xA7u, 0x13u},\r
+ {0xABu, 0x08u},\r
+ {0xB0u, 0x80u},\r
+ {0xB2u, 0x10u},\r
+ {0xB3u, 0x04u},\r
+ {0xB6u, 0x01u},\r
+ {0xB7u, 0x28u},\r
+ {0xC0u, 0x6Fu},\r
+ {0xC2u, 0x6Fu},\r
+ {0xC4u, 0xDFu},\r
+ {0xCAu, 0x5Du},\r
+ {0xCCu, 0xFBu},\r
+ {0xCEu, 0x4Fu},\r
+ {0xD8u, 0x01u},\r
+ {0xE2u, 0x48u},\r
+ {0xE6u, 0x14u},\r
+ {0xEAu, 0x20u},\r
+ {0xECu, 0x01u},\r
+ {0x39u, 0x20u},\r
+ {0x3Fu, 0x10u},\r
+ {0x59u, 0x04u},\r
+ {0x5Fu, 0x01u},\r
+ {0x27u, 0x08u},\r
+ {0x82u, 0x02u},\r
+ {0x87u, 0x08u},\r
+ {0x99u, 0x04u},\r
+ {0x9Au, 0x02u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA1u, 0x04u},\r
+ {0xA6u, 0x08u},\r
+ {0xB1u, 0x10u},\r
+ {0xB2u, 0x04u},\r
+ {0xB6u, 0x42u},\r
+ {0xB7u, 0x04u},\r
{0xE0u, 0x20u},\r
- {0xE4u, 0x20u},\r
- {0xE8u, 0x90u},\r
+ {0xE8u, 0x80u},\r
+ {0xECu, 0x11u},\r
+ {0xEEu, 0x40u},\r
+ {0x81u, 0x04u},\r
+ {0x8Du, 0x04u},\r
+ {0x99u, 0x04u},\r
+ {0xA1u, 0x04u},\r
+ {0xABu, 0x10u},\r
+ {0xAEu, 0x08u},\r
+ {0xE6u, 0x40u},\r
{0x13u, 0x40u},\r
{0x17u, 0x48u},\r
- {0x32u, 0x04u},\r
+ {0x32u, 0x02u},\r
{0x36u, 0x80u},\r
{0x37u, 0x08u},\r
- {0x38u, 0x01u},\r
+ {0x39u, 0x01u},\r
{0x3Bu, 0x40u},\r
- {0x3Eu, 0x28u},\r
+ {0x3Du, 0x04u},\r
+ {0x3Fu, 0x20u},\r
{0x43u, 0x10u},\r
- {0x58u, 0x01u},\r
- {0x5Fu, 0x20u},\r
- {0x63u, 0x04u},\r
- {0x65u, 0x40u},\r
- {0x67u, 0x20u},\r
- {0x85u, 0x40u},\r
+ {0x58u, 0x08u},\r
+ {0x5Eu, 0x42u},\r
+ {0x61u, 0x08u},\r
+ {0x66u, 0x08u},\r
{0x89u, 0x01u},\r
- {0x8Cu, 0x01u},\r
+ {0x8Eu, 0x40u},\r
{0xC4u, 0xE0u},\r
{0xCCu, 0xE0u},\r
{0xCEu, 0xF0u},\r
{0xD0u, 0x10u},\r
{0xD6u, 0xE0u},\r
{0xD8u, 0xC0u},\r
- {0xE6u, 0x10u},\r
- {0x30u, 0x04u},\r
+ {0x32u, 0x04u},\r
{0x33u, 0x40u},\r
- {0x36u, 0x20u},\r
- {0x37u, 0x04u},\r
- {0x3Au, 0x40u},\r
- {0x53u, 0x20u},\r
- {0x55u, 0x08u},\r
- {0x58u, 0x80u},\r
- {0x5Du, 0x01u},\r
- {0x84u, 0x01u},\r
- {0x86u, 0x64u},\r
- {0x91u, 0x01u},\r
- {0x96u, 0x08u},\r
- {0x97u, 0x04u},\r
+ {0x34u, 0x10u},\r
+ {0x36u, 0x01u},\r
+ {0x3Bu, 0x10u},\r
+ {0x52u, 0x20u},\r
+ {0x56u, 0x20u},\r
+ {0x5Bu, 0x20u},\r
+ {0x5Fu, 0x02u},\r
+ {0x86u, 0x20u},\r
+ {0x8Bu, 0x02u},\r
+ {0x8Eu, 0x20u},\r
+ {0x8Fu, 0x10u},\r
+ {0x95u, 0x04u},\r
{0x9Bu, 0x40u},\r
- {0x9Cu, 0x01u},\r
- {0x9Eu, 0x08u},\r
+ {0x9Cu, 0x08u},\r
{0x9Fu, 0x10u},\r
- {0xA1u, 0x08u},\r
- {0xA3u, 0x20u},\r
- {0xA6u, 0x80u},\r
- {0xABu, 0x20u},\r
- {0xADu, 0x08u},\r
- {0xB3u, 0x10u},\r
- {0xB6u, 0x20u},\r
- {0xB7u, 0x20u},\r
+ {0xA5u, 0x08u},\r
+ {0xA6u, 0x82u},\r
+ {0xA7u, 0x10u},\r
+ {0xAAu, 0x01u},\r
+ {0xB2u, 0x08u},\r
{0xCCu, 0xF0u},\r
{0xCEu, 0x10u},\r
{0xD4u, 0xE0u},\r
{0xD6u, 0x80u},\r
- {0xE2u, 0x50u},\r
- {0xE6u, 0x50u},\r
- {0xEAu, 0x40u},\r
- {0xEEu, 0x20u},\r
+ {0xE6u, 0x40u},\r
+ {0xEEu, 0x80u},\r
{0x12u, 0x80u},\r
- {0x63u, 0x01u},\r
- {0x97u, 0x04u},\r
- {0x9Cu, 0x84u},\r
- {0x9Eu, 0x08u},\r
- {0x9Fu, 0x14u},\r
- {0xA6u, 0x80u},\r
+ {0x95u, 0x04u},\r
+ {0x96u, 0x08u},\r
+ {0x97u, 0x10u},\r
+ {0x9Cu, 0x18u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA5u, 0x08u},\r
+ {0xA6u, 0x82u},\r
+ {0xABu, 0x20u},\r
+ {0xB6u, 0x01u},\r
{0xC4u, 0x10u},\r
- {0xD6u, 0x40u},\r
- {0x83u, 0x14u},\r
- {0x84u, 0x04u},\r
- {0x85u, 0x80u},\r
- {0x97u, 0x04u},\r
- {0x9Cu, 0x04u},\r
- {0x9Eu, 0x08u},\r
- {0x9Fu, 0x14u},\r
- {0xB4u, 0x80u},\r
- {0xB7u, 0x01u},\r
- {0xE2u, 0xB0u},\r
+ {0xEAu, 0x80u},\r
+ {0x84u, 0x10u},\r
+ {0x95u, 0x04u},\r
+ {0x99u, 0x20u},\r
+ {0x9Cu, 0x18u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA5u, 0x08u},\r
+ {0xAAu, 0x02u},\r
+ {0xAEu, 0x04u},\r
+ {0xAFu, 0x10u},\r
+ {0xB5u, 0x20u},\r
{0xE6u, 0x40u},\r
- {0x08u, 0x02u},\r
- {0x0Bu, 0x08u},\r
- {0x0Fu, 0x80u},\r
- {0x12u, 0x80u},\r
- {0x17u, 0x02u},\r
- {0x52u, 0x10u},\r
- {0x57u, 0x80u},\r
- {0x58u, 0x10u},\r
- {0x5Eu, 0x20u},\r
- {0x8Au, 0x10u},\r
+ {0xEAu, 0x90u},\r
+ {0xEEu, 0x10u},\r
+ {0x08u, 0x44u},\r
+ {0x0Fu, 0x40u},\r
+ {0x11u, 0x08u},\r
+ {0x14u, 0x10u},\r
+ {0x51u, 0x08u},\r
+ {0x56u, 0x08u},\r
+ {0x5Bu, 0x40u},\r
+ {0x5Fu, 0x80u},\r
+ {0x80u, 0x40u},\r
+ {0x83u, 0x80u},\r
+ {0x84u, 0x10u},\r
+ {0x8Eu, 0x40u},\r
{0xC2u, 0x0Eu},\r
{0xC4u, 0x0Cu},\r
{0xD4u, 0x07u},\r
{0xD6u, 0x04u},\r
- {0xE0u, 0x01u},\r
+ {0xE2u, 0x08u},\r
{0x00u, 0x40u},\r
- {0x01u, 0x08u},\r
- {0x04u, 0x08u},\r
- {0x05u, 0x20u},\r
- {0x08u, 0x08u},\r
- {0x09u, 0x40u},\r
- {0x0Fu, 0x21u},\r
- {0x80u, 0x04u},\r
- {0x83u, 0x40u},\r
+ {0x03u, 0x80u},\r
+ {0x05u, 0x40u},\r
+ {0x06u, 0x40u},\r
+ {0x08u, 0x20u},\r
+ {0x0Au, 0x80u},\r
+ {0x0Eu, 0x11u},\r
+ {0x84u, 0x20u},\r
{0x86u, 0x01u},\r
- {0x87u, 0x10u},\r
- {0x88u, 0x08u},\r
- {0x89u, 0x40u},\r
- {0x93u, 0x08u},\r
- {0x98u, 0x02u},\r
- {0x9Bu, 0x02u},\r
- {0x9Cu, 0x10u},\r
- {0x9Du, 0x08u},\r
- {0x9Eu, 0x10u},\r
- {0xA3u, 0x40u},\r
- {0xA7u, 0x80u},\r
- {0xA9u, 0x08u},\r
- {0xB2u, 0x80u},\r
+ {0x89u, 0x08u},\r
+ {0x8Eu, 0x30u},\r
+ {0x93u, 0x40u},\r
+ {0x94u, 0x40u},\r
+ {0x96u, 0x80u},\r
+ {0x9Eu, 0x08u},\r
+ {0x9Fu, 0x40u},\r
+ {0xA1u, 0x04u},\r
+ {0xA5u, 0x08u},\r
+ {0xB0u, 0x44u},\r
{0xC0u, 0x0Fu},\r
{0xC2u, 0x0Fu},\r
- {0xE2u, 0x01u},\r
- {0xE6u, 0x04u},\r
+ {0xE2u, 0x08u},\r
+ {0xE4u, 0x04u},\r
+ {0xE6u, 0x08u},\r
{0xEAu, 0x01u},\r
- {0x89u, 0x20u},\r
- {0x96u, 0x01u},\r
- {0x97u, 0x20u},\r
- {0x99u, 0x20u},\r
- {0x9Bu, 0x02u},\r
- {0x9Cu, 0x10u},\r
- {0x9Eu, 0x10u},\r
- {0xA7u, 0x80u},\r
- {0xA8u, 0x42u},\r
- {0xB3u, 0x04u},\r
- {0xB7u, 0x11u},\r
- {0xE2u, 0x04u},\r
+ {0xEEu, 0x01u},\r
+ {0x8Bu, 0x80u},\r
+ {0x9Cu, 0x80u},\r
+ {0x9Eu, 0x08u},\r
+ {0x9Fu, 0x40u},\r
+ {0xA3u, 0x80u},\r
+ {0xA6u, 0x20u},\r
+ {0xAEu, 0x40u},\r
+ {0xAFu, 0x40u},\r
+ {0xB1u, 0x40u},\r
+ {0xB4u, 0x80u},\r
+ {0xB5u, 0x04u},\r
+ {0xE2u, 0x01u},\r
{0xEAu, 0x09u},\r
- {0xEEu, 0x08u},\r
- {0x0Bu, 0x21u},\r
- {0x0Cu, 0x02u},\r
- {0x0Eu, 0x01u},\r
- {0x83u, 0x01u},\r
- {0x84u, 0x02u},\r
+ {0xEEu, 0x02u},\r
+ {0x08u, 0x80u},\r
+ {0x0Bu, 0x20u},\r
+ {0x0Eu, 0x21u},\r
+ {0x87u, 0x10u},\r
{0x96u, 0x01u},\r
- {0x97u, 0x20u},\r
- {0x9Cu, 0x10u},\r
- {0x9Eu, 0x10u},\r
- {0xA7u, 0x80u},\r
- {0xABu, 0x02u},\r
- {0xC2u, 0x0Fu},\r
- {0x86u, 0x08u},\r
- {0x8Bu, 0x08u},\r
- {0x97u, 0x04u},\r
+ {0x9Cu, 0x80u},\r
{0x9Eu, 0x08u},\r
- {0xA1u, 0x80u},\r
- {0xE6u, 0x40u},\r
- {0x04u, 0x08u},\r
- {0x51u, 0x80u},\r
- {0x57u, 0x08u},\r
- {0x87u, 0x04u},\r
+ {0x9Fu, 0x40u},\r
+ {0xA6u, 0x30u},\r
+ {0xAEu, 0x11u},\r
+ {0xC2u, 0x0Fu},\r
+ {0x67u, 0x80u},\r
+ {0x87u, 0x40u},\r
+ {0x8Cu, 0x08u},\r
+ {0x8Du, 0x08u},\r
+ {0x99u, 0x20u},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Fu, 0x10u},\r
+ {0xA5u, 0x08u},\r
+ {0xB1u, 0x04u},\r
+ {0xD8u, 0x80u},\r
+ {0xE2u, 0x10u},\r
+ {0x04u, 0x02u},\r
+ {0x50u, 0x04u},\r
+ {0x59u, 0x20u},\r
+ {0x83u, 0x10u},\r
{0x8Cu, 0x04u},\r
- {0x97u, 0x04u},\r
- {0xA1u, 0x80u},\r
- {0xA3u, 0x08u},\r
+ {0x94u, 0x02u},\r
+ {0x99u, 0x20u},\r
+ {0x9Fu, 0x10u},\r
+ {0xB4u, 0x01u},\r
{0xC0u, 0x20u},\r
- {0xD4u, 0x60u},\r
- {0xE2u, 0x40u},\r
- {0x8Bu, 0x80u},\r
- {0x9Cu, 0x10u},\r
- {0x9Eu, 0x10u},\r
- {0xA7u, 0x80u},\r
- {0xE0u, 0x01u},\r
- {0x01u, 0x02u},\r
- {0x88u, 0x10u},\r
- {0x8Au, 0x10u},\r
- {0x8Du, 0x02u},\r
- {0x9Cu, 0x10u},\r
- {0x9Eu, 0x10u},\r
- {0xC0u, 0x08u},\r
+ {0xD4u, 0xA0u},\r
+ {0xE2u, 0x20u},\r
+ {0x8Au, 0x08u},\r
+ {0x9Eu, 0x08u},\r
+ {0xA6u, 0x20u},\r
+ {0xABu, 0x40u},\r
{0xE0u, 0x04u},\r
- {0xE2u, 0x02u},\r
- {0xE4u, 0x04u},\r
+ {0x02u, 0x20u},\r
+ {0xA6u, 0x20u},\r
+ {0xC0u, 0x08u},\r
{0x10u, 0x03u},\r
{0x1Au, 0x03u},\r
{0x00u, 0xFDu},\r
/* address, size */\r
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
{(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
- {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1664u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P3_ROUTE_BASE), 2304u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
{(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},\r
};\r
\r
- /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */\r
- static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {\r
- 0x00u, 0x00u, 0xFFu, 0x00u, 0x50u, 0x03u, 0xA0u, 0x04u, 0x09u, 0x28u, 0x06u, 0x50u, 0x90u, 0x05u, 0x60u, 0x02u, \r
- 0x03u, 0x00u, 0x0Cu, 0x00u, 0x0Fu, 0x00u, 0xF0u, 0x08u, 0x00u, 0x04u, 0xFFu, 0x03u, 0x00u, 0x00u, 0xFFu, 0x00u, \r
- 0x05u, 0x00u, 0x0Au, 0x10u, 0x30u, 0x00u, 0xC0u, 0x40u, 0x00u, 0x01u, 0x00u, 0x06u, 0x00u, 0x00u, 0x00u, 0x20u, \r
- 0x00u, 0x60u, 0x00u, 0x18u, 0xFFu, 0x07u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x00u, 0x00u, 0x10u, 0x05u, \r
- 0x26u, 0x03u, 0x40u, 0x00u, 0x05u, 0xEBu, 0xFDu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, \r
+ /* UDB_1_2_0_CONFIG Address: CYDEV_UCFG_B0_P3_U1_BASE Size (bytes): 128 */\r
+ static const uint8 CYCODE BS_UDB_1_2_0_CONFIG_VAL[] = {\r
+ 0x04u, 0x00u, 0x00u, 0x9Fu, 0x04u, 0xC0u, 0x00u, 0x04u, 0x00u, 0x7Fu, 0x00u, 0x80u, 0x00u, 0x90u, 0x00u, 0x40u, \r
+ 0x00u, 0x00u, 0x00u, 0xFFu, 0x00u, 0xC0u, 0x00u, 0x08u, 0x00u, 0x00u, 0x01u, 0x60u, 0x00u, 0xC0u, 0x02u, 0x02u, \r
+ 0x00u, 0xC0u, 0x00u, 0x01u, 0x01u, 0x00u, 0x02u, 0x00u, 0x00u, 0x1Fu, 0x00u, 0x20u, 0x00u, 0x80u, 0x00u, 0x00u, \r
+ 0x00u, 0x00u, 0x03u, 0x00u, 0x04u, 0xFFu, 0x00u, 0x00u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x10u, \r
+ 0x53u, 0x06u, 0x40u, 0x00u, 0x02u, 0xCEu, 0xFDu, 0xBDu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x40u, 0x00u, 0x04u, 0x00u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, \r
0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
\r
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */\r
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {\r
- 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x01u, 0x00u, 0x01u, 0x02u, 0x01u};\r
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x00u, 0x02u, 0x01u, 0x02u, 0x01u};\r
\r
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
/* dest, src, size */\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), BS_UDB_1_2_0_CONFIG_VAL, 128u},\r
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},\r
};\r
\r
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)\r
{\r
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];\r
- CYMEMZERO(ms->address, (uint32)(ms->size));\r
+ CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));\r
}\r
\r
/* Copy device configuration data into registers */\r
/*******************************************************************************\r
* FILENAME: cyfitter_cfg.h\r
-* PSoC Creator 3.0 Component Pack 7\r
+* PSoC Creator 3.1\r
*\r
* Description:\r
* This file is automatically generated by PSoC Creator.\r
.include "cydevicegnu.inc"\r
.include "cydevicegnu_trm.inc"\r
\r
-/* Debug_Timer_Interrupt */\r
-.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set Debug_Timer_Interrupt__INTC_MASK, 0x02\r
-.set Debug_Timer_Interrupt__INTC_NUMBER, 1\r
-.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7\r
-.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
-.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_RX_DMA_COMPLETE */\r
-.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x01\r
-.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 0\r
-.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
-.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_TX_DMA_COMPLETE */\r
-.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x08\r
-.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 3\r
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
-.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* Debug_Timer_TimerHW */\r
-.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0\r
-.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1\r
-.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0\r
-.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1\r
-.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2\r
-.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0\r
-.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1\r
-.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0\r
-.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1\r
-.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3\r
-.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01\r
-.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3\r
-.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01\r
-.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0\r
-.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1\r
-.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0\r
+/* LED1 */\r
+.set LED1__0__MASK, 0x08\r
+.set LED1__0__PC, CYREG_PRT12_PC3\r
+.set LED1__0__PORT, 12\r
+.set LED1__0__SHIFT, 3\r
+.set LED1__AG, CYREG_PRT12_AG\r
+.set LED1__BIE, CYREG_PRT12_BIE\r
+.set LED1__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set LED1__BYP, CYREG_PRT12_BYP\r
+.set LED1__DM0, CYREG_PRT12_DM0\r
+.set LED1__DM1, CYREG_PRT12_DM1\r
+.set LED1__DM2, CYREG_PRT12_DM2\r
+.set LED1__DR, CYREG_PRT12_DR\r
+.set LED1__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set LED1__MASK, 0x08\r
+.set LED1__PORT, 12\r
+.set LED1__PRT, CYREG_PRT12_PRT\r
+.set LED1__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set LED1__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set LED1__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set LED1__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set LED1__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set LED1__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set LED1__PS, CYREG_PRT12_PS\r
+.set LED1__SHIFT, 3\r
+.set LED1__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set LED1__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set LED1__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set LED1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set LED1__SLW, CYREG_PRT12_SLW\r
\r
-/* SD_RX_DMA_COMPLETE */\r
-.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x10\r
-.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 4\r
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
-.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+/* SD_CD */\r
+.set SD_CD__0__MASK, 0x40\r
+.set SD_CD__0__PC, CYREG_PRT3_PC6\r
+.set SD_CD__0__PORT, 3\r
+.set SD_CD__0__SHIFT, 6\r
+.set SD_CD__AG, CYREG_PRT3_AG\r
+.set SD_CD__AMUX, CYREG_PRT3_AMUX\r
+.set SD_CD__BIE, CYREG_PRT3_BIE\r
+.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_CD__BYP, CYREG_PRT3_BYP\r
+.set SD_CD__CTL, CYREG_PRT3_CTL\r
+.set SD_CD__DM0, CYREG_PRT3_DM0\r
+.set SD_CD__DM1, CYREG_PRT3_DM1\r
+.set SD_CD__DM2, CYREG_PRT3_DM2\r
+.set SD_CD__DR, CYREG_PRT3_DR\r
+.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_CD__MASK, 0x40\r
+.set SD_CD__PORT, 3\r
+.set SD_CD__PRT, CYREG_PRT3_PRT\r
+.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_CD__PS, CYREG_PRT3_PS\r
+.set SD_CD__SHIFT, 6\r
+.set SD_CD__SLW, CYREG_PRT3_SLW\r
\r
-/* SD_TX_DMA_COMPLETE */\r
-.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x20\r
-.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 5\r
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5\r
-.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+/* SD_CS */\r
+.set SD_CS__0__MASK, 0x10\r
+.set SD_CS__0__PC, CYREG_PRT3_PC4\r
+.set SD_CS__0__PORT, 3\r
+.set SD_CS__0__SHIFT, 4\r
+.set SD_CS__AG, CYREG_PRT3_AG\r
+.set SD_CS__AMUX, CYREG_PRT3_AMUX\r
+.set SD_CS__BIE, CYREG_PRT3_BIE\r
+.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_CS__BYP, CYREG_PRT3_BYP\r
+.set SD_CS__CTL, CYREG_PRT3_CTL\r
+.set SD_CS__DM0, CYREG_PRT3_DM0\r
+.set SD_CS__DM1, CYREG_PRT3_DM1\r
+.set SD_CS__DM2, CYREG_PRT3_DM2\r
+.set SD_CS__DR, CYREG_PRT3_DR\r
+.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_CS__MASK, 0x10\r
+.set SD_CS__PORT, 3\r
+.set SD_CS__PRT, CYREG_PRT3_PRT\r
+.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_CS__PS, CYREG_PRT3_PS\r
+.set SD_CS__SHIFT, 4\r
+.set SD_CS__SLW, CYREG_PRT3_SLW\r
\r
-/* SCSI_Parity_Error */\r
-.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB06_MSK\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB06_ST\r
+/* USBFS_arb_int */\r
+.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_arb_int__INTC_MASK, 0x400000\r
+.set USBFS_arb_int__INTC_NUMBER, 22\r
+.set USBFS_arb_int__INTC_PRIOR_NUM, 7\r
+.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22\r
+.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* USBFS_bus_reset */\r
.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
-/* SCSI_CTL_PHASE */\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB00_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB00_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB00_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL\r
-\r
-/* SCSI_Filtered */\r
-.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01\r
-.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB14_15_ST\r
-.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
-.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
-.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
-.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
-.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
-.set SCSI_Filtered_sts_sts_reg__3__POS, 3\r
-.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
-.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
-.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB14_MSK\r
-.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB14_ACTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB14_ST_CTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB14_ST_CTL\r
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB14_ST\r
-\r
-/* SCSI_Out_Bits */\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__3__POS, 3\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__4__MASK, 0x10\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__4__POS, 4\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__5__MASK, 0x20\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__5__POS, 5\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__6__MASK, 0x40\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
-\r
-/* USBFS_arb_int */\r
-.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_arb_int__INTC_MASK, 0x400000\r
-.set USBFS_arb_int__INTC_NUMBER, 22\r
-.set USBFS_arb_int__INTC_PRIOR_NUM, 7\r
-.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22\r
-.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+/* USBFS_Dm */\r
+.set USBFS_Dm__0__MASK, 0x80\r
+.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1\r
+.set USBFS_Dm__0__PORT, 15\r
+.set USBFS_Dm__0__SHIFT, 7\r
+.set USBFS_Dm__AG, CYREG_PRT15_AG\r
+.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX\r
+.set USBFS_Dm__BIE, CYREG_PRT15_BIE\r
+.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK\r
+.set USBFS_Dm__BYP, CYREG_PRT15_BYP\r
+.set USBFS_Dm__CTL, CYREG_PRT15_CTL\r
+.set USBFS_Dm__DM0, CYREG_PRT15_DM0\r
+.set USBFS_Dm__DM1, CYREG_PRT15_DM1\r
+.set USBFS_Dm__DM2, CYREG_PRT15_DM2\r
+.set USBFS_Dm__DR, CYREG_PRT15_DR\r
+.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS\r
+.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
+.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN\r
+.set USBFS_Dm__MASK, 0x80\r
+.set USBFS_Dm__PORT, 15\r
+.set USBFS_Dm__PRT, CYREG_PRT15_PRT\r
+.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
+.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
+.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
+.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
+.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
+.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
+.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
+.set USBFS_Dm__PS, CYREG_PRT15_PS\r
+.set USBFS_Dm__SHIFT, 7\r
+.set USBFS_Dm__SLW, CYREG_PRT15_SLW\r
+\r
+/* USBFS_Dp */\r
+.set USBFS_Dp__0__MASK, 0x40\r
+.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0\r
+.set USBFS_Dp__0__PORT, 15\r
+.set USBFS_Dp__0__SHIFT, 6\r
+.set USBFS_Dp__AG, CYREG_PRT15_AG\r
+.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX\r
+.set USBFS_Dp__BIE, CYREG_PRT15_BIE\r
+.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK\r
+.set USBFS_Dp__BYP, CYREG_PRT15_BYP\r
+.set USBFS_Dp__CTL, CYREG_PRT15_CTL\r
+.set USBFS_Dp__DM0, CYREG_PRT15_DM0\r
+.set USBFS_Dp__DM1, CYREG_PRT15_DM1\r
+.set USBFS_Dp__DM2, CYREG_PRT15_DM2\r
+.set USBFS_Dp__DR, CYREG_PRT15_DR\r
+.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS\r
+.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT\r
+.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
+.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN\r
+.set USBFS_Dp__MASK, 0x40\r
+.set USBFS_Dp__PORT, 15\r
+.set USBFS_Dp__PRT, CYREG_PRT15_PRT\r
+.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
+.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
+.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
+.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
+.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
+.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
+.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
+.set USBFS_Dp__PS, CYREG_PRT15_PS\r
+.set USBFS_Dp__SHIFT, 6\r
+.set USBFS_Dp__SLW, CYREG_PRT15_SLW\r
+.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15\r
+\r
+/* USBFS_dp_int */\r
+.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_dp_int__INTC_MASK, 0x1000\r
+.set USBFS_dp_int__INTC_NUMBER, 12\r
+.set USBFS_dp_int__INTC_PRIOR_NUM, 7\r
+.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12\r
+.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_0 */\r
+.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_0__INTC_MASK, 0x1000000\r
+.set USBFS_ep_0__INTC_NUMBER, 24\r
+.set USBFS_ep_0__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24\r
+.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_1 */\r
+.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_1__INTC_MASK, 0x40\r
+.set USBFS_ep_1__INTC_NUMBER, 6\r
+.set USBFS_ep_1__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_6\r
+.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_2 */\r
+.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_2__INTC_MASK, 0x80\r
+.set USBFS_ep_2__INTC_NUMBER, 7\r
+.set USBFS_ep_2__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_7\r
+.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_3 */\r
+.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_3__INTC_MASK, 0x100\r
+.set USBFS_ep_3__INTC_NUMBER, 8\r
+.set USBFS_ep_3__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_8\r
+.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_4 */\r
+.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_4__INTC_MASK, 0x200\r
+.set USBFS_ep_4__INTC_NUMBER, 9\r
+.set USBFS_ep_4__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_9\r
+.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* USBFS_sof_int */\r
.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
-/* SCSI_Out_Ctl */\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
+/* USBFS_USB */\r
+.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG\r
+.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG\r
+.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN\r
+.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR\r
+.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG\r
+.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN\r
+.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR\r
+.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG\r
+.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN\r
+.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR\r
+.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG\r
+.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN\r
+.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR\r
+.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG\r
+.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN\r
+.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR\r
+.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG\r
+.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN\r
+.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR\r
+.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG\r
+.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN\r
+.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR\r
+.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG\r
+.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN\r
+.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR\r
+.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN\r
+.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR\r
+.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR\r
+.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA\r
+.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB\r
+.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA\r
+.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB\r
+.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR\r
+.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA\r
+.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB\r
+.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA\r
+.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB\r
+.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR\r
+.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA\r
+.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB\r
+.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA\r
+.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB\r
+.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR\r
+.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA\r
+.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB\r
+.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA\r
+.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB\r
+.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR\r
+.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA\r
+.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB\r
+.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA\r
+.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB\r
+.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR\r
+.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA\r
+.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB\r
+.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA\r
+.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB\r
+.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR\r
+.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA\r
+.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB\r
+.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA\r
+.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB\r
+.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR\r
+.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA\r
+.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB\r
+.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA\r
+.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB\r
+.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE\r
+.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT\r
+.set USBFS_USB__CR0, CYREG_USB_CR0\r
+.set USBFS_USB__CR1, CYREG_USB_CR1\r
+.set USBFS_USB__CWA, CYREG_USB_CWA\r
+.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB\r
+.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES\r
+.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB\r
+.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG\r
+.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE\r
+.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE\r
+.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT\r
+.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR\r
+.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0\r
+.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1\r
+.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2\r
+.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3\r
+.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4\r
+.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5\r
+.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6\r
+.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7\r
+.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE\r
+.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5\r
+.set USBFS_USB__PM_ACT_MSK, 0x01\r
+.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5\r
+.set USBFS_USB__PM_STBY_MSK, 0x01\r
+.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN\r
+.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR\r
+.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0\r
+.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1\r
+.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0\r
+.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0\r
+.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1\r
+.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0\r
+.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0\r
+.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1\r
+.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0\r
+.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0\r
+.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1\r
+.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0\r
+.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0\r
+.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1\r
+.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0\r
+.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0\r
+.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1\r
+.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0\r
+.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0\r
+.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1\r
+.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0\r
+.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0\r
+.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1\r
+.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0\r
+.set USBFS_USB__SOF0, CYREG_USB_SOF0\r
+.set USBFS_USB__SOF1, CYREG_USB_SOF1\r
+.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN\r
+.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0\r
+.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1\r
\r
-/* SCSI_Out_DBx */\r
-.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__0__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__0__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__0__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__0__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__0__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__0__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__0__MASK, 0x08\r
-.set SCSI_Out_DBx__0__PC, CYREG_PRT6_PC3\r
-.set SCSI_Out_DBx__0__PORT, 6\r
-.set SCSI_Out_DBx__0__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__0__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__0__SHIFT, 3\r
-.set SCSI_Out_DBx__0__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__1__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__1__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__1__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__1__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__1__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__1__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__1__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__1__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__1__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__1__MASK, 0x04\r
-.set SCSI_Out_DBx__1__PC, CYREG_PRT6_PC2\r
-.set SCSI_Out_DBx__1__PORT, 6\r
-.set SCSI_Out_DBx__1__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__1__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__1__SHIFT, 2\r
-.set SCSI_Out_DBx__1__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__2__MASK, 0x02\r
-.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC1\r
-.set SCSI_Out_DBx__2__PORT, 6\r
-.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__2__SHIFT, 1\r
-.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__3__MASK, 0x01\r
-.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC0\r
-.set SCSI_Out_DBx__3__PORT, 6\r
-.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__3__SHIFT, 0\r
-.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__4__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__4__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__4__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__4__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__4__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__4__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__4__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__4__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__4__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__4__MASK, 0x80\r
-.set SCSI_Out_DBx__4__PC, CYREG_PRT4_PC7\r
-.set SCSI_Out_DBx__4__PORT, 4\r
-.set SCSI_Out_DBx__4__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__4__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__4__SHIFT, 7\r
-.set SCSI_Out_DBx__4__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__5__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__5__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__5__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__5__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__5__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__5__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__5__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__5__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__5__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__5__MASK, 0x40\r
-.set SCSI_Out_DBx__5__PC, CYREG_PRT4_PC6\r
-.set SCSI_Out_DBx__5__PORT, 4\r
-.set SCSI_Out_DBx__5__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__5__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__5__SHIFT, 6\r
-.set SCSI_Out_DBx__5__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__6__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__6__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__6__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__6__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__6__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__6__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__6__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__6__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__6__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__6__MASK, 0x20\r
-.set SCSI_Out_DBx__6__PC, CYREG_PRT4_PC5\r
-.set SCSI_Out_DBx__6__PORT, 4\r
-.set SCSI_Out_DBx__6__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__6__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__6__SHIFT, 5\r
-.set SCSI_Out_DBx__6__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__7__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__7__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__7__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__7__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__7__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__7__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__7__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__7__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__7__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__7__MASK, 0x10\r
-.set SCSI_Out_DBx__7__PC, CYREG_PRT4_PC4\r
-.set SCSI_Out_DBx__7__PORT, 4\r
-.set SCSI_Out_DBx__7__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__7__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__7__SHIFT, 4\r
-.set SCSI_Out_DBx__7__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__DB0__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__DB0__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__DB0__MASK, 0x08\r
-.set SCSI_Out_DBx__DB0__PC, CYREG_PRT6_PC3\r
-.set SCSI_Out_DBx__DB0__PORT, 6\r
-.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__DB0__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__DB0__SHIFT, 3\r
-.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__DB1__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__DB1__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__DB1__MASK, 0x04\r
-.set SCSI_Out_DBx__DB1__PC, CYREG_PRT6_PC2\r
-.set SCSI_Out_DBx__DB1__PORT, 6\r
-.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__DB1__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__DB1__SHIFT, 2\r
-.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__DB2__MASK, 0x02\r
-.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC1\r
-.set SCSI_Out_DBx__DB2__PORT, 6\r
-.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__DB2__SHIFT, 1\r
-.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__DB3__MASK, 0x01\r
-.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC0\r
-.set SCSI_Out_DBx__DB3__PORT, 6\r
-.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__DB3__SHIFT, 0\r
-.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__DB4__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__DB4__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__DB4__MASK, 0x80\r
-.set SCSI_Out_DBx__DB4__PC, CYREG_PRT4_PC7\r
-.set SCSI_Out_DBx__DB4__PORT, 4\r
-.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__DB4__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__DB4__SHIFT, 7\r
-.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__DB5__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__DB5__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__DB5__MASK, 0x40\r
-.set SCSI_Out_DBx__DB5__PC, CYREG_PRT4_PC6\r
-.set SCSI_Out_DBx__DB5__PORT, 4\r
-.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__DB5__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__DB5__SHIFT, 6\r
-.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__DB6__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__DB6__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__DB6__MASK, 0x20\r
-.set SCSI_Out_DBx__DB6__PC, CYREG_PRT4_PC5\r
-.set SCSI_Out_DBx__DB6__PORT, 4\r
-.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__DB6__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__DB6__SHIFT, 5\r
-.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__DB7__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__DB7__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__DB7__MASK, 0x10\r
-.set SCSI_Out_DBx__DB7__PC, CYREG_PRT4_PC4\r
-.set SCSI_Out_DBx__DB7__PORT, 4\r
-.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__DB7__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__DB7__SHIFT, 4\r
-.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT4_SLW\r
-\r
-/* SCSI_RST_ISR */\r
-.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set SCSI_RST_ISR__INTC_MASK, 0x04\r
-.set SCSI_RST_ISR__INTC_NUMBER, 2\r
-.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7\r
-.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
-.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SDCard_BSPIM */\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK\r
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK\r
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL\r
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL\r
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL\r
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK\r
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
-.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
-.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
-.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
-.set SDCard_BSPIM_RxStsReg__5__POS, 5\r
-.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
-.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
-.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST\r
-.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
-.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
-.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
-.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
-.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
-.set SDCard_BSPIM_TxStsReg__2__POS, 2\r
-.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08\r
-.set SDCard_BSPIM_TxStsReg__3__POS, 3\r
-.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
-.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
-.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL\r
-\r
-/* USBFS_dp_int */\r
-.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_dp_int__INTC_MASK, 0x1000\r
-.set USBFS_dp_int__INTC_NUMBER, 12\r
-.set USBFS_dp_int__INTC_PRIOR_NUM, 7\r
-.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12\r
-.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_In_DBx */\r
-.set SCSI_In_DBx__0__AG, CYREG_PRT12_AG\r
-.set SCSI_In_DBx__0__BIE, CYREG_PRT12_BIE\r
-.set SCSI_In_DBx__0__BIT_MASK, CYREG_PRT12_BIT_MASK\r
-.set SCSI_In_DBx__0__BYP, CYREG_PRT12_BYP\r
-.set SCSI_In_DBx__0__DM0, CYREG_PRT12_DM0\r
-.set SCSI_In_DBx__0__DM1, CYREG_PRT12_DM1\r
-.set SCSI_In_DBx__0__DM2, CYREG_PRT12_DM2\r
-.set SCSI_In_DBx__0__DR, CYREG_PRT12_DR\r
-.set SCSI_In_DBx__0__INP_DIS, CYREG_PRT12_INP_DIS\r
-.set SCSI_In_DBx__0__MASK, 0x10\r
-.set SCSI_In_DBx__0__PC, CYREG_PRT12_PC4\r
-.set SCSI_In_DBx__0__PORT, 12\r
-.set SCSI_In_DBx__0__PRT, CYREG_PRT12_PRT\r
-.set SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
-.set SCSI_In_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
-.set SCSI_In_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
-.set SCSI_In_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
-.set SCSI_In_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
-.set SCSI_In_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
-.set SCSI_In_DBx__0__PS, CYREG_PRT12_PS\r
-.set SCSI_In_DBx__0__SHIFT, 4\r
-.set SCSI_In_DBx__0__SIO_CFG, CYREG_PRT12_SIO_CFG\r
-.set SCSI_In_DBx__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
-.set SCSI_In_DBx__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
-.set SCSI_In_DBx__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
-.set SCSI_In_DBx__0__SLW, CYREG_PRT12_SLW\r
-.set SCSI_In_DBx__1__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__1__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__1__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__1__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__1__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__1__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__1__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__1__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__1__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__1__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__1__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__1__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__1__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__1__MASK, 0x80\r
-.set SCSI_In_DBx__1__PC, CYREG_PRT2_PC7\r
-.set SCSI_In_DBx__1__PORT, 2\r
-.set SCSI_In_DBx__1__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__1__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__1__SHIFT, 7\r
-.set SCSI_In_DBx__1__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__2__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__2__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__2__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__2__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__2__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__2__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__2__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__2__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__2__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__2__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__2__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__2__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__2__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__2__MASK, 0x40\r
-.set SCSI_In_DBx__2__PC, CYREG_PRT2_PC6\r
-.set SCSI_In_DBx__2__PORT, 2\r
-.set SCSI_In_DBx__2__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__2__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__2__SHIFT, 6\r
-.set SCSI_In_DBx__2__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__3__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__3__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__3__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__3__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__3__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__3__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__3__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__3__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__3__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__3__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__3__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__3__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__3__MASK, 0x20\r
-.set SCSI_In_DBx__3__PC, CYREG_PRT2_PC5\r
-.set SCSI_In_DBx__3__PORT, 2\r
-.set SCSI_In_DBx__3__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__3__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__3__SHIFT, 5\r
-.set SCSI_In_DBx__3__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__4__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__4__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__4__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__4__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__4__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__4__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__4__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__4__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__4__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__4__MASK, 0x10\r
-.set SCSI_In_DBx__4__PC, CYREG_PRT2_PC4\r
-.set SCSI_In_DBx__4__PORT, 2\r
-.set SCSI_In_DBx__4__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__4__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__4__SHIFT, 4\r
-.set SCSI_In_DBx__4__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__5__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__5__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__5__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__5__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__5__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__5__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__5__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__5__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__5__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__5__MASK, 0x08\r
-.set SCSI_In_DBx__5__PC, CYREG_PRT2_PC3\r
-.set SCSI_In_DBx__5__PORT, 2\r
-.set SCSI_In_DBx__5__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__5__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__5__SHIFT, 3\r
-.set SCSI_In_DBx__5__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__6__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__6__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__6__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__6__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__6__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__6__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__6__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__6__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__6__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__6__MASK, 0x04\r
-.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC2\r
-.set SCSI_In_DBx__6__PORT, 2\r
-.set SCSI_In_DBx__6__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__6__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__6__SHIFT, 2\r
-.set SCSI_In_DBx__6__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__7__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__7__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__7__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__7__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__7__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__7__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__7__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__7__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__7__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__7__MASK, 0x02\r
-.set SCSI_In_DBx__7__PC, CYREG_PRT2_PC1\r
-.set SCSI_In_DBx__7__PORT, 2\r
-.set SCSI_In_DBx__7__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__7__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__7__SHIFT, 1\r
-.set SCSI_In_DBx__7__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB0__AG, CYREG_PRT12_AG\r
-.set SCSI_In_DBx__DB0__BIE, CYREG_PRT12_BIE\r
-.set SCSI_In_DBx__DB0__BIT_MASK, CYREG_PRT12_BIT_MASK\r
-.set SCSI_In_DBx__DB0__BYP, CYREG_PRT12_BYP\r
-.set SCSI_In_DBx__DB0__DM0, CYREG_PRT12_DM0\r
-.set SCSI_In_DBx__DB0__DM1, CYREG_PRT12_DM1\r
-.set SCSI_In_DBx__DB0__DM2, CYREG_PRT12_DM2\r
-.set SCSI_In_DBx__DB0__DR, CYREG_PRT12_DR\r
-.set SCSI_In_DBx__DB0__INP_DIS, CYREG_PRT12_INP_DIS\r
-.set SCSI_In_DBx__DB0__MASK, 0x10\r
-.set SCSI_In_DBx__DB0__PC, CYREG_PRT12_PC4\r
-.set SCSI_In_DBx__DB0__PORT, 12\r
-.set SCSI_In_DBx__DB0__PRT, CYREG_PRT12_PRT\r
-.set SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
-.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
-.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
-.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
-.set SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
-.set SCSI_In_DBx__DB0__PS, CYREG_PRT12_PS\r
-.set SCSI_In_DBx__DB0__SHIFT, 4\r
-.set SCSI_In_DBx__DB0__SIO_CFG, CYREG_PRT12_SIO_CFG\r
-.set SCSI_In_DBx__DB0__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
-.set SCSI_In_DBx__DB0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
-.set SCSI_In_DBx__DB0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
-.set SCSI_In_DBx__DB0__SLW, CYREG_PRT12_SLW\r
-.set SCSI_In_DBx__DB1__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB1__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB1__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB1__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB1__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB1__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB1__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB1__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB1__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB1__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB1__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB1__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB1__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB1__MASK, 0x80\r
-.set SCSI_In_DBx__DB1__PC, CYREG_PRT2_PC7\r
-.set SCSI_In_DBx__DB1__PORT, 2\r
-.set SCSI_In_DBx__DB1__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB1__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB1__SHIFT, 7\r
-.set SCSI_In_DBx__DB1__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB2__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB2__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB2__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB2__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB2__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB2__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB2__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB2__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB2__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB2__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB2__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB2__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB2__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB2__MASK, 0x40\r
-.set SCSI_In_DBx__DB2__PC, CYREG_PRT2_PC6\r
-.set SCSI_In_DBx__DB2__PORT, 2\r
-.set SCSI_In_DBx__DB2__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB2__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB2__SHIFT, 6\r
-.set SCSI_In_DBx__DB2__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB3__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB3__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB3__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB3__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB3__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB3__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB3__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB3__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB3__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB3__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB3__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB3__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB3__MASK, 0x20\r
-.set SCSI_In_DBx__DB3__PC, CYREG_PRT2_PC5\r
-.set SCSI_In_DBx__DB3__PORT, 2\r
-.set SCSI_In_DBx__DB3__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB3__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB3__SHIFT, 5\r
-.set SCSI_In_DBx__DB3__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB4__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB4__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB4__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB4__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB4__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB4__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB4__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB4__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB4__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB4__MASK, 0x10\r
-.set SCSI_In_DBx__DB4__PC, CYREG_PRT2_PC4\r
-.set SCSI_In_DBx__DB4__PORT, 2\r
-.set SCSI_In_DBx__DB4__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB4__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB4__SHIFT, 4\r
-.set SCSI_In_DBx__DB4__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB5__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB5__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB5__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB5__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB5__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB5__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB5__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB5__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB5__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB5__MASK, 0x08\r
-.set SCSI_In_DBx__DB5__PC, CYREG_PRT2_PC3\r
-.set SCSI_In_DBx__DB5__PORT, 2\r
-.set SCSI_In_DBx__DB5__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB5__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB5__SHIFT, 3\r
-.set SCSI_In_DBx__DB5__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB6__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB6__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB6__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB6__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB6__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB6__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB6__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB6__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB6__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB6__MASK, 0x04\r
-.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC2\r
-.set SCSI_In_DBx__DB6__PORT, 2\r
-.set SCSI_In_DBx__DB6__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB6__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB6__SHIFT, 2\r
-.set SCSI_In_DBx__DB6__SLW, CYREG_PRT2_SLW\r
-.set SCSI_In_DBx__DB7__AG, CYREG_PRT2_AG\r
-.set SCSI_In_DBx__DB7__AMUX, CYREG_PRT2_AMUX\r
-.set SCSI_In_DBx__DB7__BIE, CYREG_PRT2_BIE\r
-.set SCSI_In_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
-.set SCSI_In_DBx__DB7__BYP, CYREG_PRT2_BYP\r
-.set SCSI_In_DBx__DB7__CTL, CYREG_PRT2_CTL\r
-.set SCSI_In_DBx__DB7__DM0, CYREG_PRT2_DM0\r
-.set SCSI_In_DBx__DB7__DM1, CYREG_PRT2_DM1\r
-.set SCSI_In_DBx__DB7__DM2, CYREG_PRT2_DM2\r
-.set SCSI_In_DBx__DB7__DR, CYREG_PRT2_DR\r
-.set SCSI_In_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS\r
-.set SCSI_In_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
-.set SCSI_In_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN\r
-.set SCSI_In_DBx__DB7__MASK, 0x02\r
-.set SCSI_In_DBx__DB7__PC, CYREG_PRT2_PC1\r
-.set SCSI_In_DBx__DB7__PORT, 2\r
-.set SCSI_In_DBx__DB7__PRT, CYREG_PRT2_PRT\r
-.set SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
-.set SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
-.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
-.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
-.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
-.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
-.set SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
-.set SCSI_In_DBx__DB7__PS, CYREG_PRT2_PS\r
-.set SCSI_In_DBx__DB7__SHIFT, 1\r
-.set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW\r
-\r
-/* SCSI_RX_DMA */\r
-.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
-.set SCSI_RX_DMA__DRQ_NUMBER, 0\r
-.set SCSI_RX_DMA__NUMBEROF_TDS, 0\r
-.set SCSI_RX_DMA__PRIORITY, 2\r
-.set SCSI_RX_DMA__TERMIN_EN, 0\r
-.set SCSI_RX_DMA__TERMIN_SEL, 0\r
-.set SCSI_RX_DMA__TERMOUT0_EN, 1\r
-.set SCSI_RX_DMA__TERMOUT0_SEL, 0\r
-.set SCSI_RX_DMA__TERMOUT1_EN, 0\r
-.set SCSI_RX_DMA__TERMOUT1_SEL, 0\r
-\r
-/* SCSI_TX_DMA */\r
-.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
-.set SCSI_TX_DMA__DRQ_NUMBER, 1\r
-.set SCSI_TX_DMA__NUMBEROF_TDS, 0\r
-.set SCSI_TX_DMA__PRIORITY, 2\r
-.set SCSI_TX_DMA__TERMIN_EN, 0\r
-.set SCSI_TX_DMA__TERMIN_SEL, 0\r
-.set SCSI_TX_DMA__TERMOUT0_EN, 1\r
-.set SCSI_TX_DMA__TERMOUT0_SEL, 1\r
-.set SCSI_TX_DMA__TERMOUT1_EN, 0\r
-.set SCSI_TX_DMA__TERMOUT1_SEL, 0\r
-\r
-/* SD_Data_Clk */\r
-.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0\r
-.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1\r
-.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2\r
-.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07\r
-.set SD_Data_Clk__INDEX, 0x00\r
-.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
-.set SD_Data_Clk__PM_ACT_MSK, 0x01\r
-.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
-.set SD_Data_Clk__PM_STBY_MSK, 0x01\r
-\r
-/* timer_clock */\r
-.set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0\r
-.set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1\r
-.set timer_clock__CFG2, CYREG_CLKDIST_DCFG2_CFG2\r
-.set timer_clock__CFG2_SRC_SEL_MASK, 0x07\r
-.set timer_clock__INDEX, 0x02\r
-.set timer_clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
-.set timer_clock__PM_ACT_MSK, 0x04\r
-.set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
-.set timer_clock__PM_STBY_MSK, 0x04\r
-\r
-/* SCSI_Noise */\r
-.set SCSI_Noise__0__AG, CYREG_PRT12_AG\r
-.set SCSI_Noise__0__BIE, CYREG_PRT12_BIE\r
-.set SCSI_Noise__0__BIT_MASK, CYREG_PRT12_BIT_MASK\r
-.set SCSI_Noise__0__BYP, CYREG_PRT12_BYP\r
-.set SCSI_Noise__0__DM0, CYREG_PRT12_DM0\r
-.set SCSI_Noise__0__DM1, CYREG_PRT12_DM1\r
-.set SCSI_Noise__0__DM2, CYREG_PRT12_DM2\r
-.set SCSI_Noise__0__DR, CYREG_PRT12_DR\r
-.set SCSI_Noise__0__INP_DIS, CYREG_PRT12_INP_DIS\r
-.set SCSI_Noise__0__MASK, 0x20\r
-.set SCSI_Noise__0__PC, CYREG_PRT12_PC5\r
-.set SCSI_Noise__0__PORT, 12\r
-.set SCSI_Noise__0__PRT, CYREG_PRT12_PRT\r
-.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
-.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
-.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
-.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
-.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
-.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
-.set SCSI_Noise__0__PS, CYREG_PRT12_PS\r
-.set SCSI_Noise__0__SHIFT, 5\r
-.set SCSI_Noise__0__SIO_CFG, CYREG_PRT12_SIO_CFG\r
-.set SCSI_Noise__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
-.set SCSI_Noise__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
-.set SCSI_Noise__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
-.set SCSI_Noise__0__SLW, CYREG_PRT12_SLW\r
-.set SCSI_Noise__1__AG, CYREG_PRT6_AG\r
-.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Noise__1__DR, CYREG_PRT6_DR\r
-.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Noise__1__MASK, 0x10\r
-.set SCSI_Noise__1__PC, CYREG_PRT6_PC4\r
-.set SCSI_Noise__1__PORT, 6\r
-.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Noise__1__PS, CYREG_PRT6_PS\r
-.set SCSI_Noise__1__SHIFT, 4\r
-.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Noise__2__AG, CYREG_PRT5_AG\r
-.set SCSI_Noise__2__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_Noise__2__BIE, CYREG_PRT5_BIE\r
-.set SCSI_Noise__2__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_Noise__2__BYP, CYREG_PRT5_BYP\r
-.set SCSI_Noise__2__CTL, CYREG_PRT5_CTL\r
-.set SCSI_Noise__2__DM0, CYREG_PRT5_DM0\r
-.set SCSI_Noise__2__DM1, CYREG_PRT5_DM1\r
-.set SCSI_Noise__2__DM2, CYREG_PRT5_DM2\r
-.set SCSI_Noise__2__DR, CYREG_PRT5_DR\r
-.set SCSI_Noise__2__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_Noise__2__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_Noise__2__MASK, 0x01\r
-.set SCSI_Noise__2__PC, CYREG_PRT5_PC0\r
-.set SCSI_Noise__2__PORT, 5\r
-.set SCSI_Noise__2__PRT, CYREG_PRT5_PRT\r
-.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_Noise__2__PS, CYREG_PRT5_PS\r
-.set SCSI_Noise__2__SHIFT, 0\r
-.set SCSI_Noise__2__SLW, CYREG_PRT5_SLW\r
-.set SCSI_Noise__3__AG, CYREG_PRT6_AG\r
-.set SCSI_Noise__3__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Noise__3__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Noise__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Noise__3__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Noise__3__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Noise__3__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Noise__3__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Noise__3__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Noise__3__DR, CYREG_PRT6_DR\r
-.set SCSI_Noise__3__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Noise__3__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Noise__3__MASK, 0x40\r
-.set SCSI_Noise__3__PC, CYREG_PRT6_PC6\r
-.set SCSI_Noise__3__PORT, 6\r
-.set SCSI_Noise__3__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Noise__3__PS, CYREG_PRT6_PS\r
-.set SCSI_Noise__3__SHIFT, 6\r
-.set SCSI_Noise__3__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Noise__4__AG, CYREG_PRT6_AG\r
-.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Noise__4__DR, CYREG_PRT6_DR\r
-.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Noise__4__MASK, 0x20\r
-.set SCSI_Noise__4__PC, CYREG_PRT6_PC5\r
-.set SCSI_Noise__4__PORT, 6\r
-.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Noise__4__PS, CYREG_PRT6_PS\r
-.set SCSI_Noise__4__SHIFT, 5\r
-.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG\r
-.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR\r
-.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Noise__ACK__MASK, 0x20\r
-.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC5\r
-.set SCSI_Noise__ACK__PORT, 6\r
-.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS\r
-.set SCSI_Noise__ACK__SHIFT, 5\r
-.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Noise__ATN__AG, CYREG_PRT12_AG\r
-.set SCSI_Noise__ATN__BIE, CYREG_PRT12_BIE\r
-.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT12_BIT_MASK\r
-.set SCSI_Noise__ATN__BYP, CYREG_PRT12_BYP\r
-.set SCSI_Noise__ATN__DM0, CYREG_PRT12_DM0\r
-.set SCSI_Noise__ATN__DM1, CYREG_PRT12_DM1\r
-.set SCSI_Noise__ATN__DM2, CYREG_PRT12_DM2\r
-.set SCSI_Noise__ATN__DR, CYREG_PRT12_DR\r
-.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT12_INP_DIS\r
-.set SCSI_Noise__ATN__MASK, 0x20\r
-.set SCSI_Noise__ATN__PC, CYREG_PRT12_PC5\r
-.set SCSI_Noise__ATN__PORT, 12\r
-.set SCSI_Noise__ATN__PRT, CYREG_PRT12_PRT\r
-.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
-.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
-.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
-.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
-.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
-.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
-.set SCSI_Noise__ATN__PS, CYREG_PRT12_PS\r
-.set SCSI_Noise__ATN__SHIFT, 5\r
-.set SCSI_Noise__ATN__SIO_CFG, CYREG_PRT12_SIO_CFG\r
-.set SCSI_Noise__ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
-.set SCSI_Noise__ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
-.set SCSI_Noise__ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
-.set SCSI_Noise__ATN__SLW, CYREG_PRT12_SLW\r
-.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG\r
-.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR\r
-.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Noise__BSY__MASK, 0x10\r
-.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC4\r
-.set SCSI_Noise__BSY__PORT, 6\r
-.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS\r
-.set SCSI_Noise__BSY__SHIFT, 4\r
-.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Noise__RST__AG, CYREG_PRT6_AG\r
-.set SCSI_Noise__RST__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Noise__RST__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Noise__RST__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Noise__RST__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Noise__RST__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Noise__RST__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Noise__RST__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Noise__RST__DR, CYREG_PRT6_DR\r
-.set SCSI_Noise__RST__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Noise__RST__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Noise__RST__MASK, 0x40\r
-.set SCSI_Noise__RST__PC, CYREG_PRT6_PC6\r
-.set SCSI_Noise__RST__PORT, 6\r
-.set SCSI_Noise__RST__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Noise__RST__PS, CYREG_PRT6_PS\r
-.set SCSI_Noise__RST__SHIFT, 6\r
-.set SCSI_Noise__RST__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Noise__SEL__AG, CYREG_PRT5_AG\r
-.set SCSI_Noise__SEL__AMUX, CYREG_PRT5_AMUX\r
-.set SCSI_Noise__SEL__BIE, CYREG_PRT5_BIE\r
-.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT5_BIT_MASK\r
-.set SCSI_Noise__SEL__BYP, CYREG_PRT5_BYP\r
-.set SCSI_Noise__SEL__CTL, CYREG_PRT5_CTL\r
-.set SCSI_Noise__SEL__DM0, CYREG_PRT5_DM0\r
-.set SCSI_Noise__SEL__DM1, CYREG_PRT5_DM1\r
-.set SCSI_Noise__SEL__DM2, CYREG_PRT5_DM2\r
-.set SCSI_Noise__SEL__DR, CYREG_PRT5_DR\r
-.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT5_INP_DIS\r
-.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
-.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT5_LCD_EN\r
-.set SCSI_Noise__SEL__MASK, 0x01\r
-.set SCSI_Noise__SEL__PC, CYREG_PRT5_PC0\r
-.set SCSI_Noise__SEL__PORT, 5\r
-.set SCSI_Noise__SEL__PRT, CYREG_PRT5_PRT\r
-.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
-.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
-.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
-.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
-.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
-.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
-.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
-.set SCSI_Noise__SEL__PS, CYREG_PRT5_PS\r
-.set SCSI_Noise__SEL__SHIFT, 0\r
-.set SCSI_Noise__SEL__SLW, CYREG_PRT5_SLW\r
-\r
-/* scsiTarget */\r
-.set scsiTarget_StatusReg__0__MASK, 0x01\r
-.set scsiTarget_StatusReg__0__POS, 0\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
-.set scsiTarget_StatusReg__1__MASK, 0x02\r
-.set scsiTarget_StatusReg__1__POS, 1\r
-.set scsiTarget_StatusReg__2__MASK, 0x04\r
-.set scsiTarget_StatusReg__2__POS, 2\r
-.set scsiTarget_StatusReg__3__MASK, 0x08\r
-.set scsiTarget_StatusReg__3__POS, 3\r
-.set scsiTarget_StatusReg__4__MASK, 0x10\r
-.set scsiTarget_StatusReg__4__POS, 4\r
-.set scsiTarget_StatusReg__MASK, 0x1F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB05_MSK\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB05_ST\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST\r
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB01_MSK\r
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB01_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB01_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB01_ST\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK\r
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB01_CTL\r
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL\r
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB01_CTL\r
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL\r
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB01_MSK\r
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB01_02_A0\r
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB01_02_A1\r
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB01_02_D0\r
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB01_02_D1\r
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB01_02_F0\r
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB01_02_F1\r
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB01_A0_A1\r
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB01_A0\r
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB01_A1\r
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB01_D0_D1\r
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB01_D0\r
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB01_D1\r
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB01_F0_F1\r
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB01_F0\r
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB01_F1\r
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
-\r
-/* USBFS_ep_0 */\r
-.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_0__INTC_MASK, 0x1000000\r
-.set USBFS_ep_0__INTC_NUMBER, 24\r
-.set USBFS_ep_0__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24\r
-.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_1 */\r
-.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_1__INTC_MASK, 0x40\r
-.set USBFS_ep_1__INTC_NUMBER, 6\r
-.set USBFS_ep_1__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_6\r
-.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_2 */\r
-.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_2__INTC_MASK, 0x80\r
-.set USBFS_ep_2__INTC_NUMBER, 7\r
-.set USBFS_ep_2__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_7\r
-.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_3 */\r
-.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_3__INTC_MASK, 0x100\r
-.set USBFS_ep_3__INTC_NUMBER, 8\r
-.set USBFS_ep_3__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_8\r
-.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_4 */\r
-.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_4__INTC_MASK, 0x200\r
-.set USBFS_ep_4__INTC_NUMBER, 9\r
-.set USBFS_ep_4__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_9\r
-.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SD_RX_DMA */\r
-.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
-.set SD_RX_DMA__DRQ_NUMBER, 2\r
-.set SD_RX_DMA__NUMBEROF_TDS, 0\r
-.set SD_RX_DMA__PRIORITY, 1\r
-.set SD_RX_DMA__TERMIN_EN, 0\r
-.set SD_RX_DMA__TERMIN_SEL, 0\r
-.set SD_RX_DMA__TERMOUT0_EN, 1\r
-.set SD_RX_DMA__TERMOUT0_SEL, 2\r
-.set SD_RX_DMA__TERMOUT1_EN, 0\r
-.set SD_RX_DMA__TERMOUT1_SEL, 0\r
-\r
-/* SD_TX_DMA */\r
-.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
-.set SD_TX_DMA__DRQ_NUMBER, 3\r
-.set SD_TX_DMA__NUMBEROF_TDS, 0\r
-.set SD_TX_DMA__PRIORITY, 2\r
-.set SD_TX_DMA__TERMIN_EN, 0\r
-.set SD_TX_DMA__TERMIN_SEL, 0\r
-.set SD_TX_DMA__TERMOUT0_EN, 1\r
-.set SD_TX_DMA__TERMOUT0_SEL, 3\r
-.set SD_TX_DMA__TERMOUT1_EN, 0\r
-.set SD_TX_DMA__TERMOUT1_SEL, 0\r
-\r
-/* USBFS_USB */\r
-.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG\r
-.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG\r
-.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN\r
-.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR\r
-.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG\r
-.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN\r
-.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR\r
-.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG\r
-.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN\r
-.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR\r
-.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG\r
-.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN\r
-.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR\r
-.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG\r
-.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN\r
-.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR\r
-.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG\r
-.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN\r
-.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR\r
-.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG\r
-.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN\r
-.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR\r
-.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG\r
-.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN\r
-.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR\r
-.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN\r
-.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR\r
-.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR\r
-.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA\r
-.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB\r
-.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA\r
-.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB\r
-.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR\r
-.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA\r
-.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB\r
-.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA\r
-.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB\r
-.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR\r
-.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA\r
-.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB\r
-.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA\r
-.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB\r
-.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR\r
-.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA\r
-.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB\r
-.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA\r
-.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB\r
-.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR\r
-.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA\r
-.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB\r
-.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA\r
-.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB\r
-.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR\r
-.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA\r
-.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB\r
-.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA\r
-.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB\r
-.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR\r
-.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA\r
-.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB\r
-.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA\r
-.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB\r
-.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR\r
-.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA\r
-.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB\r
-.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA\r
-.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB\r
-.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE\r
-.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT\r
-.set USBFS_USB__CR0, CYREG_USB_CR0\r
-.set USBFS_USB__CR1, CYREG_USB_CR1\r
-.set USBFS_USB__CWA, CYREG_USB_CWA\r
-.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB\r
-.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES\r
-.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB\r
-.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG\r
-.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT\r
-.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR\r
-.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0\r
-.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1\r
-.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2\r
-.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3\r
-.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4\r
-.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5\r
-.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6\r
-.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7\r
-.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE\r
-.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE\r
-.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE\r
-.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5\r
-.set USBFS_USB__PM_ACT_MSK, 0x01\r
-.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5\r
-.set USBFS_USB__PM_STBY_MSK, 0x01\r
-.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0\r
-.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1\r
-.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0\r
-.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0\r
-.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1\r
-.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0\r
-.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0\r
-.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1\r
-.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0\r
-.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0\r
-.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1\r
-.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0\r
-.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0\r
-.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1\r
-.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0\r
-.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0\r
-.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1\r
-.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0\r
-.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0\r
-.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1\r
-.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0\r
-.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0\r
-.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1\r
-.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0\r
-.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN\r
-.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR\r
-.set USBFS_USB__SOF0, CYREG_USB_SOF0\r
-.set USBFS_USB__SOF1, CYREG_USB_SOF1\r
-.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0\r
-.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1\r
-.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN\r
-\r
-/* SCSI_CLK */\r
-.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0\r
-.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1\r
-.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2\r
-.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07\r
-.set SCSI_CLK__INDEX, 0x01\r
-.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
-.set SCSI_CLK__PM_ACT_MSK, 0x02\r
-.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
-.set SCSI_CLK__PM_STBY_MSK, 0x02\r
-\r
-/* SCSI_Out */\r
-.set SCSI_Out__0__AG, CYREG_PRT4_AG\r
-.set SCSI_Out__0__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out__0__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out__0__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out__0__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out__0__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out__0__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out__0__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out__0__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out__0__DR, CYREG_PRT4_DR\r
-.set SCSI_Out__0__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out__0__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out__0__MASK, 0x08\r
-.set SCSI_Out__0__PC, CYREG_PRT4_PC3\r
-.set SCSI_Out__0__PORT, 4\r
-.set SCSI_Out__0__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out__0__PS, CYREG_PRT4_PS\r
-.set SCSI_Out__0__SHIFT, 3\r
-.set SCSI_Out__0__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out__1__AG, CYREG_PRT4_AG\r
-.set SCSI_Out__1__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out__1__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out__1__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out__1__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out__1__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out__1__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out__1__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out__1__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out__1__DR, CYREG_PRT4_DR\r
-.set SCSI_Out__1__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out__1__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out__1__MASK, 0x04\r
-.set SCSI_Out__1__PC, CYREG_PRT4_PC2\r
-.set SCSI_Out__1__PORT, 4\r
-.set SCSI_Out__1__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out__1__PS, CYREG_PRT4_PS\r
-.set SCSI_Out__1__SHIFT, 2\r
-.set SCSI_Out__1__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out__2__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__2__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__2__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__2__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__2__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__2__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__2__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__2__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__2__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__2__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__2__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__2__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__2__MASK, 0x80\r
-.set SCSI_Out__2__PC, CYREG_PRT0_PC7\r
-.set SCSI_Out__2__PORT, 0\r
-.set SCSI_Out__2__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__2__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__2__SHIFT, 7\r
-.set SCSI_Out__2__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__3__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__3__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__3__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__3__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__3__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__3__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__3__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__3__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__3__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__3__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__3__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__3__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__3__MASK, 0x40\r
-.set SCSI_Out__3__PC, CYREG_PRT0_PC6\r
-.set SCSI_Out__3__PORT, 0\r
-.set SCSI_Out__3__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__3__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__3__SHIFT, 6\r
-.set SCSI_Out__3__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__4__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__4__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__4__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__4__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__4__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__4__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__4__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__4__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__4__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__4__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__4__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__4__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__4__MASK, 0x20\r
-.set SCSI_Out__4__PC, CYREG_PRT0_PC5\r
-.set SCSI_Out__4__PORT, 0\r
-.set SCSI_Out__4__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__4__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__4__SHIFT, 5\r
-.set SCSI_Out__4__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__5__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__5__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__5__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__5__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__5__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__5__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__5__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__5__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__5__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__5__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__5__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__5__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__5__MASK, 0x10\r
-.set SCSI_Out__5__PC, CYREG_PRT0_PC4\r
-.set SCSI_Out__5__PORT, 0\r
-.set SCSI_Out__5__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__5__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__5__SHIFT, 4\r
-.set SCSI_Out__5__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__6__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__6__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__6__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__6__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__6__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__6__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__6__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__6__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__6__MASK, 0x08\r
-.set SCSI_Out__6__PC, CYREG_PRT0_PC3\r
-.set SCSI_Out__6__PORT, 0\r
-.set SCSI_Out__6__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__6__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__6__SHIFT, 3\r
-.set SCSI_Out__6__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__7__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__7__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__7__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__7__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__7__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__7__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__7__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__7__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__7__MASK, 0x04\r
-.set SCSI_Out__7__PC, CYREG_PRT0_PC2\r
-.set SCSI_Out__7__PORT, 0\r
-.set SCSI_Out__7__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__7__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__7__SHIFT, 2\r
-.set SCSI_Out__7__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__8__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__8__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__8__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__8__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__8__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__8__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__8__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__8__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__8__MASK, 0x02\r
-.set SCSI_Out__8__PC, CYREG_PRT0_PC1\r
-.set SCSI_Out__8__PORT, 0\r
-.set SCSI_Out__8__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__8__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__8__SHIFT, 1\r
-.set SCSI_Out__8__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__9__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__9__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__9__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__9__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__9__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__9__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__9__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__9__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__9__MASK, 0x01\r
-.set SCSI_Out__9__PC, CYREG_PRT0_PC0\r
-.set SCSI_Out__9__PORT, 0\r
-.set SCSI_Out__9__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__9__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__9__SHIFT, 0\r
-.set SCSI_Out__9__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__ACK__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__ACK__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__ACK__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__ACK__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__ACK__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__ACK__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__ACK__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__ACK__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__ACK__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__ACK__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__ACK__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__ACK__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__ACK__MASK, 0x40\r
-.set SCSI_Out__ACK__PC, CYREG_PRT0_PC6\r
-.set SCSI_Out__ACK__PORT, 0\r
-.set SCSI_Out__ACK__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__ACK__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__ACK__SHIFT, 6\r
-.set SCSI_Out__ACK__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__ATN__AG, CYREG_PRT4_AG\r
-.set SCSI_Out__ATN__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out__ATN__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out__ATN__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out__ATN__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out__ATN__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out__ATN__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out__ATN__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out__ATN__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out__ATN__DR, CYREG_PRT4_DR\r
-.set SCSI_Out__ATN__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out__ATN__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out__ATN__MASK, 0x04\r
-.set SCSI_Out__ATN__PC, CYREG_PRT4_PC2\r
-.set SCSI_Out__ATN__PORT, 4\r
-.set SCSI_Out__ATN__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out__ATN__PS, CYREG_PRT4_PS\r
-.set SCSI_Out__ATN__SHIFT, 2\r
-.set SCSI_Out__ATN__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out__BSY__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__BSY__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__BSY__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__BSY__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__BSY__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__BSY__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__BSY__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__BSY__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__BSY__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__BSY__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__BSY__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__BSY__MASK, 0x80\r
-.set SCSI_Out__BSY__PC, CYREG_PRT0_PC7\r
-.set SCSI_Out__BSY__PORT, 0\r
-.set SCSI_Out__BSY__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__BSY__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__BSY__SHIFT, 7\r
-.set SCSI_Out__BSY__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__CD_raw__MASK, 0x04\r
-.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC2\r
-.set SCSI_Out__CD_raw__PORT, 0\r
-.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__CD_raw__SHIFT, 2\r
-.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__DBP_raw__AG, CYREG_PRT4_AG\r
-.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out__DBP_raw__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out__DBP_raw__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out__DBP_raw__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out__DBP_raw__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out__DBP_raw__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out__DBP_raw__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out__DBP_raw__DR, CYREG_PRT4_DR\r
-.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out__DBP_raw__MASK, 0x08\r
-.set SCSI_Out__DBP_raw__PC, CYREG_PRT4_PC3\r
-.set SCSI_Out__DBP_raw__PORT, 4\r
-.set SCSI_Out__DBP_raw__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out__DBP_raw__PS, CYREG_PRT4_PS\r
-.set SCSI_Out__DBP_raw__SHIFT, 3\r
-.set SCSI_Out__DBP_raw__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__IO_raw__MASK, 0x01\r
-.set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC0\r
-.set SCSI_Out__IO_raw__PORT, 0\r
-.set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__IO_raw__SHIFT, 0\r
-.set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__MSG_raw__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__MSG_raw__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__MSG_raw__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__MSG_raw__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__MSG_raw__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__MSG_raw__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__MSG_raw__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__MSG_raw__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__MSG_raw__MASK, 0x10\r
-.set SCSI_Out__MSG_raw__PC, CYREG_PRT0_PC4\r
-.set SCSI_Out__MSG_raw__PORT, 0\r
-.set SCSI_Out__MSG_raw__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__MSG_raw__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__MSG_raw__SHIFT, 4\r
-.set SCSI_Out__MSG_raw__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__REQ__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__REQ__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__REQ__MASK, 0x02\r
-.set SCSI_Out__REQ__PC, CYREG_PRT0_PC1\r
-.set SCSI_Out__REQ__PORT, 0\r
-.set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__REQ__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__REQ__SHIFT, 1\r
-.set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__RST__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__RST__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__RST__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__RST__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__RST__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__RST__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__RST__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__RST__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__RST__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__RST__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__RST__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__RST__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__RST__MASK, 0x20\r
-.set SCSI_Out__RST__PC, CYREG_PRT0_PC5\r
-.set SCSI_Out__RST__PORT, 0\r
-.set SCSI_Out__RST__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__RST__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__RST__SHIFT, 5\r
-.set SCSI_Out__RST__SLW, CYREG_PRT0_SLW\r
-.set SCSI_Out__SEL__AG, CYREG_PRT0_AG\r
-.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX\r
-.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE\r
-.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK\r
-.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP\r
-.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL\r
-.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0\r
-.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1\r
-.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2\r
-.set SCSI_Out__SEL__DR, CYREG_PRT0_DR\r
-.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS\r
-.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
-.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN\r
-.set SCSI_Out__SEL__MASK, 0x08\r
-.set SCSI_Out__SEL__PC, CYREG_PRT0_PC3\r
-.set SCSI_Out__SEL__PORT, 0\r
-.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT\r
-.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
-.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
-.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
-.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
-.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
-.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
-.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
-.set SCSI_Out__SEL__PS, CYREG_PRT0_PS\r
-.set SCSI_Out__SEL__SHIFT, 3\r
-.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW\r
-\r
-/* USBFS_Dm */\r
-.set USBFS_Dm__0__MASK, 0x80\r
-.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1\r
-.set USBFS_Dm__0__PORT, 15\r
-.set USBFS_Dm__0__SHIFT, 7\r
-.set USBFS_Dm__AG, CYREG_PRT15_AG\r
-.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX\r
-.set USBFS_Dm__BIE, CYREG_PRT15_BIE\r
-.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK\r
-.set USBFS_Dm__BYP, CYREG_PRT15_BYP\r
-.set USBFS_Dm__CTL, CYREG_PRT15_CTL\r
-.set USBFS_Dm__DM0, CYREG_PRT15_DM0\r
-.set USBFS_Dm__DM1, CYREG_PRT15_DM1\r
-.set USBFS_Dm__DM2, CYREG_PRT15_DM2\r
-.set USBFS_Dm__DR, CYREG_PRT15_DR\r
-.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS\r
-.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
-.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN\r
-.set USBFS_Dm__MASK, 0x80\r
-.set USBFS_Dm__PORT, 15\r
-.set USBFS_Dm__PRT, CYREG_PRT15_PRT\r
-.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
-.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
-.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
-.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
-.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
-.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
-.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
-.set USBFS_Dm__PS, CYREG_PRT15_PS\r
-.set USBFS_Dm__SHIFT, 7\r
-.set USBFS_Dm__SLW, CYREG_PRT15_SLW\r
+/* SDCard_BSPIM */\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
+.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
+.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
+.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
+.set SDCard_BSPIM_RxStsReg__5__POS, 5\r
+.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
+.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
+.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB07_08_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB07_08_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB07_08_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB07_08_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB07_08_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB07_08_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB07_A0_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB07_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB07_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB07_D0_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB07_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB07_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB07_F0_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB07_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB07_F1\r
+.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
+.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
+.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
+.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
+.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
+.set SDCard_BSPIM_TxStsReg__2__POS, 2\r
+.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08\r
+.set SDCard_BSPIM_TxStsReg__3__POS, 3\r
+.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
+.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
+.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB04_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB04_ST\r
\r
-/* USBFS_Dp */\r
-.set USBFS_Dp__0__MASK, 0x40\r
-.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0\r
-.set USBFS_Dp__0__PORT, 15\r
-.set USBFS_Dp__0__SHIFT, 6\r
-.set USBFS_Dp__AG, CYREG_PRT15_AG\r
-.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX\r
-.set USBFS_Dp__BIE, CYREG_PRT15_BIE\r
-.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK\r
-.set USBFS_Dp__BYP, CYREG_PRT15_BYP\r
-.set USBFS_Dp__CTL, CYREG_PRT15_CTL\r
-.set USBFS_Dp__DM0, CYREG_PRT15_DM0\r
-.set USBFS_Dp__DM1, CYREG_PRT15_DM1\r
-.set USBFS_Dp__DM2, CYREG_PRT15_DM2\r
-.set USBFS_Dp__DR, CYREG_PRT15_DR\r
-.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS\r
-.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT\r
-.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
-.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN\r
-.set USBFS_Dp__MASK, 0x40\r
-.set USBFS_Dp__PORT, 15\r
-.set USBFS_Dp__PRT, CYREG_PRT15_PRT\r
-.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
-.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
-.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
-.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
-.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
-.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
-.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
-.set USBFS_Dp__PS, CYREG_PRT15_PS\r
-.set USBFS_Dp__SHIFT, 6\r
-.set USBFS_Dp__SLW, CYREG_PRT15_SLW\r
-.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15\r
+/* SD_SCK */\r
+.set SD_SCK__0__MASK, 0x04\r
+.set SD_SCK__0__PC, CYREG_PRT3_PC2\r
+.set SD_SCK__0__PORT, 3\r
+.set SD_SCK__0__SHIFT, 2\r
+.set SD_SCK__AG, CYREG_PRT3_AG\r
+.set SD_SCK__AMUX, CYREG_PRT3_AMUX\r
+.set SD_SCK__BIE, CYREG_PRT3_BIE\r
+.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_SCK__BYP, CYREG_PRT3_BYP\r
+.set SD_SCK__CTL, CYREG_PRT3_CTL\r
+.set SD_SCK__DM0, CYREG_PRT3_DM0\r
+.set SD_SCK__DM1, CYREG_PRT3_DM1\r
+.set SD_SCK__DM2, CYREG_PRT3_DM2\r
+.set SD_SCK__DR, CYREG_PRT3_DR\r
+.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_SCK__MASK, 0x04\r
+.set SD_SCK__PORT, 3\r
+.set SD_SCK__PRT, CYREG_PRT3_PRT\r
+.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_SCK__PS, CYREG_PRT3_PS\r
+.set SD_SCK__SHIFT, 2\r
+.set SD_SCK__SLW, CYREG_PRT3_SLW\r
\r
/* SCSI_In */\r
.set SCSI_In__0__AG, CYREG_PRT2_AG\r
.set SCSI_In__REQ__SHIFT, 2\r
.set SCSI_In__REQ__SLW, CYREG_PRT5_SLW\r
\r
-/* SD_DAT1 */\r
-.set SD_DAT1__0__MASK, 0x01\r
-.set SD_DAT1__0__PC, CYREG_PRT3_PC0\r
-.set SD_DAT1__0__PORT, 3\r
-.set SD_DAT1__0__SHIFT, 0\r
-.set SD_DAT1__AG, CYREG_PRT3_AG\r
-.set SD_DAT1__AMUX, CYREG_PRT3_AMUX\r
-.set SD_DAT1__BIE, CYREG_PRT3_BIE\r
-.set SD_DAT1__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_DAT1__BYP, CYREG_PRT3_BYP\r
-.set SD_DAT1__CTL, CYREG_PRT3_CTL\r
-.set SD_DAT1__DM0, CYREG_PRT3_DM0\r
-.set SD_DAT1__DM1, CYREG_PRT3_DM1\r
-.set SD_DAT1__DM2, CYREG_PRT3_DM2\r
-.set SD_DAT1__DR, CYREG_PRT3_DR\r
-.set SD_DAT1__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_DAT1__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_DAT1__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_DAT1__MASK, 0x01\r
-.set SD_DAT1__PORT, 3\r
-.set SD_DAT1__PRT, CYREG_PRT3_PRT\r
-.set SD_DAT1__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_DAT1__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_DAT1__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_DAT1__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_DAT1__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_DAT1__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_DAT1__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_DAT1__PS, CYREG_PRT3_PS\r
-.set SD_DAT1__SHIFT, 0\r
-.set SD_DAT1__SLW, CYREG_PRT3_SLW\r
+/* SCSI_In_DBx */\r
+.set SCSI_In_DBx__0__AG, CYREG_PRT12_AG\r
+.set SCSI_In_DBx__0__BIE, CYREG_PRT12_BIE\r
+.set SCSI_In_DBx__0__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_In_DBx__0__BYP, CYREG_PRT12_BYP\r
+.set SCSI_In_DBx__0__DM0, CYREG_PRT12_DM0\r
+.set SCSI_In_DBx__0__DM1, CYREG_PRT12_DM1\r
+.set SCSI_In_DBx__0__DM2, CYREG_PRT12_DM2\r
+.set SCSI_In_DBx__0__DR, CYREG_PRT12_DR\r
+.set SCSI_In_DBx__0__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_In_DBx__0__MASK, 0x10\r
+.set SCSI_In_DBx__0__PC, CYREG_PRT12_PC4\r
+.set SCSI_In_DBx__0__PORT, 12\r
+.set SCSI_In_DBx__0__PRT, CYREG_PRT12_PRT\r
+.set SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_In_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_In_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_In_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_In_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_In_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_In_DBx__0__PS, CYREG_PRT12_PS\r
+.set SCSI_In_DBx__0__SHIFT, 4\r
+.set SCSI_In_DBx__0__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_In_DBx__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_In_DBx__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_In_DBx__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_In_DBx__0__SLW, CYREG_PRT12_SLW\r
+.set SCSI_In_DBx__1__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__1__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__1__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__1__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__1__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__1__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__1__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__1__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__1__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__1__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__1__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__1__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__1__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__1__MASK, 0x80\r
+.set SCSI_In_DBx__1__PC, CYREG_PRT2_PC7\r
+.set SCSI_In_DBx__1__PORT, 2\r
+.set SCSI_In_DBx__1__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__1__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__1__SHIFT, 7\r
+.set SCSI_In_DBx__1__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__2__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__2__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__2__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__2__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__2__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__2__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__2__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__2__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__2__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__2__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__2__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__2__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__2__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__2__MASK, 0x40\r
+.set SCSI_In_DBx__2__PC, CYREG_PRT2_PC6\r
+.set SCSI_In_DBx__2__PORT, 2\r
+.set SCSI_In_DBx__2__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__2__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__2__SHIFT, 6\r
+.set SCSI_In_DBx__2__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__3__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__3__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__3__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__3__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__3__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__3__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__3__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__3__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__3__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__3__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__3__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__3__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__3__MASK, 0x20\r
+.set SCSI_In_DBx__3__PC, CYREG_PRT2_PC5\r
+.set SCSI_In_DBx__3__PORT, 2\r
+.set SCSI_In_DBx__3__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__3__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__3__SHIFT, 5\r
+.set SCSI_In_DBx__3__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__4__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__4__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__4__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__4__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__4__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__4__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__4__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__4__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__4__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__4__MASK, 0x10\r
+.set SCSI_In_DBx__4__PC, CYREG_PRT2_PC4\r
+.set SCSI_In_DBx__4__PORT, 2\r
+.set SCSI_In_DBx__4__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__4__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__4__SHIFT, 4\r
+.set SCSI_In_DBx__4__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__5__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__5__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__5__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__5__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__5__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__5__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__5__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__5__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__5__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__5__MASK, 0x08\r
+.set SCSI_In_DBx__5__PC, CYREG_PRT2_PC3\r
+.set SCSI_In_DBx__5__PORT, 2\r
+.set SCSI_In_DBx__5__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__5__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__5__SHIFT, 3\r
+.set SCSI_In_DBx__5__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__6__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__6__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__6__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__6__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__6__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__6__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__6__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__6__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__6__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__6__MASK, 0x04\r
+.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC2\r
+.set SCSI_In_DBx__6__PORT, 2\r
+.set SCSI_In_DBx__6__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__6__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__6__SHIFT, 2\r
+.set SCSI_In_DBx__6__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__7__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__7__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__7__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__7__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__7__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__7__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__7__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__7__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__7__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__7__MASK, 0x02\r
+.set SCSI_In_DBx__7__PC, CYREG_PRT2_PC1\r
+.set SCSI_In_DBx__7__PORT, 2\r
+.set SCSI_In_DBx__7__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__7__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__7__SHIFT, 1\r
+.set SCSI_In_DBx__7__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB0__AG, CYREG_PRT12_AG\r
+.set SCSI_In_DBx__DB0__BIE, CYREG_PRT12_BIE\r
+.set SCSI_In_DBx__DB0__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_In_DBx__DB0__BYP, CYREG_PRT12_BYP\r
+.set SCSI_In_DBx__DB0__DM0, CYREG_PRT12_DM0\r
+.set SCSI_In_DBx__DB0__DM1, CYREG_PRT12_DM1\r
+.set SCSI_In_DBx__DB0__DM2, CYREG_PRT12_DM2\r
+.set SCSI_In_DBx__DB0__DR, CYREG_PRT12_DR\r
+.set SCSI_In_DBx__DB0__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_In_DBx__DB0__MASK, 0x10\r
+.set SCSI_In_DBx__DB0__PC, CYREG_PRT12_PC4\r
+.set SCSI_In_DBx__DB0__PORT, 12\r
+.set SCSI_In_DBx__DB0__PRT, CYREG_PRT12_PRT\r
+.set SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_In_DBx__DB0__PS, CYREG_PRT12_PS\r
+.set SCSI_In_DBx__DB0__SHIFT, 4\r
+.set SCSI_In_DBx__DB0__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_In_DBx__DB0__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_In_DBx__DB0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_In_DBx__DB0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_In_DBx__DB0__SLW, CYREG_PRT12_SLW\r
+.set SCSI_In_DBx__DB1__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB1__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB1__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB1__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB1__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB1__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB1__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB1__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB1__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB1__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB1__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB1__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB1__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB1__MASK, 0x80\r
+.set SCSI_In_DBx__DB1__PC, CYREG_PRT2_PC7\r
+.set SCSI_In_DBx__DB1__PORT, 2\r
+.set SCSI_In_DBx__DB1__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB1__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB1__SHIFT, 7\r
+.set SCSI_In_DBx__DB1__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB2__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB2__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB2__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB2__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB2__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB2__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB2__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB2__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB2__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB2__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB2__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB2__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB2__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB2__MASK, 0x40\r
+.set SCSI_In_DBx__DB2__PC, CYREG_PRT2_PC6\r
+.set SCSI_In_DBx__DB2__PORT, 2\r
+.set SCSI_In_DBx__DB2__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB2__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB2__SHIFT, 6\r
+.set SCSI_In_DBx__DB2__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB3__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB3__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB3__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB3__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB3__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB3__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB3__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB3__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB3__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB3__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB3__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB3__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB3__MASK, 0x20\r
+.set SCSI_In_DBx__DB3__PC, CYREG_PRT2_PC5\r
+.set SCSI_In_DBx__DB3__PORT, 2\r
+.set SCSI_In_DBx__DB3__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB3__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB3__SHIFT, 5\r
+.set SCSI_In_DBx__DB3__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB4__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB4__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB4__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB4__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB4__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB4__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB4__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB4__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB4__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB4__MASK, 0x10\r
+.set SCSI_In_DBx__DB4__PC, CYREG_PRT2_PC4\r
+.set SCSI_In_DBx__DB4__PORT, 2\r
+.set SCSI_In_DBx__DB4__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB4__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB4__SHIFT, 4\r
+.set SCSI_In_DBx__DB4__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB5__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB5__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB5__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB5__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB5__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB5__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB5__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB5__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB5__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB5__MASK, 0x08\r
+.set SCSI_In_DBx__DB5__PC, CYREG_PRT2_PC3\r
+.set SCSI_In_DBx__DB5__PORT, 2\r
+.set SCSI_In_DBx__DB5__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB5__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB5__SHIFT, 3\r
+.set SCSI_In_DBx__DB5__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB6__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB6__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB6__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB6__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB6__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB6__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB6__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB6__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB6__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB6__MASK, 0x04\r
+.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC2\r
+.set SCSI_In_DBx__DB6__PORT, 2\r
+.set SCSI_In_DBx__DB6__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB6__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB6__SHIFT, 2\r
+.set SCSI_In_DBx__DB6__SLW, CYREG_PRT2_SLW\r
+.set SCSI_In_DBx__DB7__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__DB7__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__DB7__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__DB7__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__DB7__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DB7__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DB7__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DB7__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DB7__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__DB7__MASK, 0x02\r
+.set SCSI_In_DBx__DB7__PC, CYREG_PRT2_PC1\r
+.set SCSI_In_DBx__DB7__PORT, 2\r
+.set SCSI_In_DBx__DB7__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__DB7__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__DB7__SHIFT, 1\r
+.set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW\r
+\r
+/* SD_DAT1 */\r
+.set SD_DAT1__0__MASK, 0x01\r
+.set SD_DAT1__0__PC, CYREG_PRT3_PC0\r
+.set SD_DAT1__0__PORT, 3\r
+.set SD_DAT1__0__SHIFT, 0\r
+.set SD_DAT1__AG, CYREG_PRT3_AG\r
+.set SD_DAT1__AMUX, CYREG_PRT3_AMUX\r
+.set SD_DAT1__BIE, CYREG_PRT3_BIE\r
+.set SD_DAT1__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_DAT1__BYP, CYREG_PRT3_BYP\r
+.set SD_DAT1__CTL, CYREG_PRT3_CTL\r
+.set SD_DAT1__DM0, CYREG_PRT3_DM0\r
+.set SD_DAT1__DM1, CYREG_PRT3_DM1\r
+.set SD_DAT1__DM2, CYREG_PRT3_DM2\r
+.set SD_DAT1__DR, CYREG_PRT3_DR\r
+.set SD_DAT1__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_DAT1__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_DAT1__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_DAT1__MASK, 0x01\r
+.set SD_DAT1__PORT, 3\r
+.set SD_DAT1__PRT, CYREG_PRT3_PRT\r
+.set SD_DAT1__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_DAT1__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_DAT1__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_DAT1__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_DAT1__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_DAT1__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_DAT1__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_DAT1__PS, CYREG_PRT3_PS\r
+.set SD_DAT1__SHIFT, 0\r
+.set SD_DAT1__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_DAT2 */\r
+.set SD_DAT2__0__MASK, 0x20\r
+.set SD_DAT2__0__PC, CYREG_PRT3_PC5\r
+.set SD_DAT2__0__PORT, 3\r
+.set SD_DAT2__0__SHIFT, 5\r
+.set SD_DAT2__AG, CYREG_PRT3_AG\r
+.set SD_DAT2__AMUX, CYREG_PRT3_AMUX\r
+.set SD_DAT2__BIE, CYREG_PRT3_BIE\r
+.set SD_DAT2__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_DAT2__BYP, CYREG_PRT3_BYP\r
+.set SD_DAT2__CTL, CYREG_PRT3_CTL\r
+.set SD_DAT2__DM0, CYREG_PRT3_DM0\r
+.set SD_DAT2__DM1, CYREG_PRT3_DM1\r
+.set SD_DAT2__DM2, CYREG_PRT3_DM2\r
+.set SD_DAT2__DR, CYREG_PRT3_DR\r
+.set SD_DAT2__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_DAT2__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_DAT2__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_DAT2__MASK, 0x20\r
+.set SD_DAT2__PORT, 3\r
+.set SD_DAT2__PRT, CYREG_PRT3_PRT\r
+.set SD_DAT2__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_DAT2__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_DAT2__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_DAT2__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_DAT2__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_DAT2__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_DAT2__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_DAT2__PS, CYREG_PRT3_PS\r
+.set SD_DAT2__SHIFT, 5\r
+.set SD_DAT2__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_MISO */\r
+.set SD_MISO__0__MASK, 0x02\r
+.set SD_MISO__0__PC, CYREG_PRT3_PC1\r
+.set SD_MISO__0__PORT, 3\r
+.set SD_MISO__0__SHIFT, 1\r
+.set SD_MISO__AG, CYREG_PRT3_AG\r
+.set SD_MISO__AMUX, CYREG_PRT3_AMUX\r
+.set SD_MISO__BIE, CYREG_PRT3_BIE\r
+.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_MISO__BYP, CYREG_PRT3_BYP\r
+.set SD_MISO__CTL, CYREG_PRT3_CTL\r
+.set SD_MISO__DM0, CYREG_PRT3_DM0\r
+.set SD_MISO__DM1, CYREG_PRT3_DM1\r
+.set SD_MISO__DM2, CYREG_PRT3_DM2\r
+.set SD_MISO__DR, CYREG_PRT3_DR\r
+.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_MISO__MASK, 0x02\r
+.set SD_MISO__PORT, 3\r
+.set SD_MISO__PRT, CYREG_PRT3_PRT\r
+.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_MISO__PS, CYREG_PRT3_PS\r
+.set SD_MISO__SHIFT, 1\r
+.set SD_MISO__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_MOSI */\r
+.set SD_MOSI__0__MASK, 0x08\r
+.set SD_MOSI__0__PC, CYREG_PRT3_PC3\r
+.set SD_MOSI__0__PORT, 3\r
+.set SD_MOSI__0__SHIFT, 3\r
+.set SD_MOSI__AG, CYREG_PRT3_AG\r
+.set SD_MOSI__AMUX, CYREG_PRT3_AMUX\r
+.set SD_MOSI__BIE, CYREG_PRT3_BIE\r
+.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_MOSI__BYP, CYREG_PRT3_BYP\r
+.set SD_MOSI__CTL, CYREG_PRT3_CTL\r
+.set SD_MOSI__DM0, CYREG_PRT3_DM0\r
+.set SD_MOSI__DM1, CYREG_PRT3_DM1\r
+.set SD_MOSI__DM2, CYREG_PRT3_DM2\r
+.set SD_MOSI__DR, CYREG_PRT3_DR\r
+.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_MOSI__MASK, 0x08\r
+.set SD_MOSI__PORT, 3\r
+.set SD_MOSI__PRT, CYREG_PRT3_PRT\r
+.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_MOSI__PS, CYREG_PRT3_PS\r
+.set SD_MOSI__SHIFT, 3\r
+.set SD_MOSI__SLW, CYREG_PRT3_SLW\r
+\r
+/* SCSI_CLK */\r
+.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0\r
+.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1\r
+.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2\r
+.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07\r
+.set SCSI_CLK__INDEX, 0x01\r
+.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
+.set SCSI_CLK__PM_ACT_MSK, 0x02\r
+.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
+.set SCSI_CLK__PM_STBY_MSK, 0x02\r
+\r
+/* SCSI_Out */\r
+.set SCSI_Out__0__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__0__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__0__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__0__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__0__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__0__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__0__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__0__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__0__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__0__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__0__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__0__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__0__MASK, 0x08\r
+.set SCSI_Out__0__PC, CYREG_PRT4_PC3\r
+.set SCSI_Out__0__PORT, 4\r
+.set SCSI_Out__0__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__0__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__0__SHIFT, 3\r
+.set SCSI_Out__0__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__1__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__1__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__1__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__1__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__1__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__1__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__1__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__1__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__1__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__1__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__1__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__1__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__1__MASK, 0x04\r
+.set SCSI_Out__1__PC, CYREG_PRT4_PC2\r
+.set SCSI_Out__1__PORT, 4\r
+.set SCSI_Out__1__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__1__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__1__SHIFT, 2\r
+.set SCSI_Out__1__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__2__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__2__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__2__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__2__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__2__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__2__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__2__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__2__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__2__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__2__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__2__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__2__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__2__MASK, 0x80\r
+.set SCSI_Out__2__PC, CYREG_PRT0_PC7\r
+.set SCSI_Out__2__PORT, 0\r
+.set SCSI_Out__2__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__2__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__2__SHIFT, 7\r
+.set SCSI_Out__2__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__3__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__3__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__3__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__3__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__3__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__3__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__3__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__3__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__3__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__3__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__3__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__3__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__3__MASK, 0x40\r
+.set SCSI_Out__3__PC, CYREG_PRT0_PC6\r
+.set SCSI_Out__3__PORT, 0\r
+.set SCSI_Out__3__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__3__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__3__SHIFT, 6\r
+.set SCSI_Out__3__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__4__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__4__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__4__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__4__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__4__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__4__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__4__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__4__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__4__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__4__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__4__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__4__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__4__MASK, 0x20\r
+.set SCSI_Out__4__PC, CYREG_PRT0_PC5\r
+.set SCSI_Out__4__PORT, 0\r
+.set SCSI_Out__4__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__4__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__4__SHIFT, 5\r
+.set SCSI_Out__4__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__5__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__5__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__5__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__5__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__5__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__5__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__5__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__5__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__5__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__5__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__5__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__5__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__5__MASK, 0x10\r
+.set SCSI_Out__5__PC, CYREG_PRT0_PC4\r
+.set SCSI_Out__5__PORT, 0\r
+.set SCSI_Out__5__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__5__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__5__SHIFT, 4\r
+.set SCSI_Out__5__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__6__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__6__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__6__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__6__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__6__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__6__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__6__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__6__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__6__MASK, 0x08\r
+.set SCSI_Out__6__PC, CYREG_PRT0_PC3\r
+.set SCSI_Out__6__PORT, 0\r
+.set SCSI_Out__6__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__6__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__6__SHIFT, 3\r
+.set SCSI_Out__6__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__7__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__7__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__7__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__7__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__7__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__7__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__7__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__7__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__7__MASK, 0x04\r
+.set SCSI_Out__7__PC, CYREG_PRT0_PC2\r
+.set SCSI_Out__7__PORT, 0\r
+.set SCSI_Out__7__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__7__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__7__SHIFT, 2\r
+.set SCSI_Out__7__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__8__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__8__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__8__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__8__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__8__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__8__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__8__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__8__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__8__MASK, 0x02\r
+.set SCSI_Out__8__PC, CYREG_PRT0_PC1\r
+.set SCSI_Out__8__PORT, 0\r
+.set SCSI_Out__8__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__8__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__8__SHIFT, 1\r
+.set SCSI_Out__8__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__9__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__9__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__9__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__9__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__9__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__9__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__9__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__9__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__9__MASK, 0x01\r
+.set SCSI_Out__9__PC, CYREG_PRT0_PC0\r
+.set SCSI_Out__9__PORT, 0\r
+.set SCSI_Out__9__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__9__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__9__SHIFT, 0\r
+.set SCSI_Out__9__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__ACK__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__ACK__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__ACK__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__ACK__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__ACK__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__ACK__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__ACK__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__ACK__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__ACK__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__ACK__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__ACK__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__ACK__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__ACK__MASK, 0x40\r
+.set SCSI_Out__ACK__PC, CYREG_PRT0_PC6\r
+.set SCSI_Out__ACK__PORT, 0\r
+.set SCSI_Out__ACK__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__ACK__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__ACK__SHIFT, 6\r
+.set SCSI_Out__ACK__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__ATN__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__ATN__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__ATN__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__ATN__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__ATN__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__ATN__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__ATN__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__ATN__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__ATN__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__ATN__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__ATN__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__ATN__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__ATN__MASK, 0x04\r
+.set SCSI_Out__ATN__PC, CYREG_PRT4_PC2\r
+.set SCSI_Out__ATN__PORT, 4\r
+.set SCSI_Out__ATN__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__ATN__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__ATN__SHIFT, 2\r
+.set SCSI_Out__ATN__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__BSY__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__BSY__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__BSY__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__BSY__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__BSY__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__BSY__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__BSY__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__BSY__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__BSY__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__BSY__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__BSY__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__BSY__MASK, 0x80\r
+.set SCSI_Out__BSY__PC, CYREG_PRT0_PC7\r
+.set SCSI_Out__BSY__PORT, 0\r
+.set SCSI_Out__BSY__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__BSY__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__BSY__SHIFT, 7\r
+.set SCSI_Out__BSY__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__CD_raw__MASK, 0x04\r
+.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC2\r
+.set SCSI_Out__CD_raw__PORT, 0\r
+.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__CD_raw__SHIFT, 2\r
+.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__DBP_raw__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__DBP_raw__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__DBP_raw__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__DBP_raw__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__DBP_raw__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__DBP_raw__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__DBP_raw__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__DBP_raw__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__DBP_raw__MASK, 0x08\r
+.set SCSI_Out__DBP_raw__PC, CYREG_PRT4_PC3\r
+.set SCSI_Out__DBP_raw__PORT, 4\r
+.set SCSI_Out__DBP_raw__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__DBP_raw__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__DBP_raw__SHIFT, 3\r
+.set SCSI_Out__DBP_raw__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__IO_raw__MASK, 0x01\r
+.set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC0\r
+.set SCSI_Out__IO_raw__PORT, 0\r
+.set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__IO_raw__SHIFT, 0\r
+.set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__MSG_raw__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__MSG_raw__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__MSG_raw__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__MSG_raw__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__MSG_raw__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__MSG_raw__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__MSG_raw__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__MSG_raw__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__MSG_raw__MASK, 0x10\r
+.set SCSI_Out__MSG_raw__PC, CYREG_PRT0_PC4\r
+.set SCSI_Out__MSG_raw__PORT, 0\r
+.set SCSI_Out__MSG_raw__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__MSG_raw__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__MSG_raw__SHIFT, 4\r
+.set SCSI_Out__MSG_raw__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__REQ__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__REQ__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__REQ__MASK, 0x02\r
+.set SCSI_Out__REQ__PC, CYREG_PRT0_PC1\r
+.set SCSI_Out__REQ__PORT, 0\r
+.set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__REQ__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__REQ__SHIFT, 1\r
+.set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__RST__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__RST__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__RST__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__RST__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__RST__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__RST__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__RST__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__RST__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__RST__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__RST__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__RST__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__RST__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__RST__MASK, 0x20\r
+.set SCSI_Out__RST__PC, CYREG_PRT0_PC5\r
+.set SCSI_Out__RST__PORT, 0\r
+.set SCSI_Out__RST__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__RST__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__RST__SHIFT, 5\r
+.set SCSI_Out__RST__SLW, CYREG_PRT0_SLW\r
+.set SCSI_Out__SEL__AG, CYREG_PRT0_AG\r
+.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out__SEL__DR, CYREG_PRT0_DR\r
+.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out__SEL__MASK, 0x08\r
+.set SCSI_Out__SEL__PC, CYREG_PRT0_PC3\r
+.set SCSI_Out__SEL__PORT, 0\r
+.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out__SEL__PS, CYREG_PRT0_PS\r
+.set SCSI_Out__SEL__SHIFT, 3\r
+.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW\r
+\r
+/* SCSI_Out_Bits */\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__3__POS, 3\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__4__MASK, 0x10\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__4__POS, 4\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__5__MASK, 0x20\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__5__POS, 5\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__6__MASK, 0x40\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK\r
+\r
+/* SCSI_Out_Ctl */\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK\r
+\r
+/* SCSI_Out_DBx */\r
+.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__0__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__0__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__0__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__0__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__0__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__0__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__0__MASK, 0x08\r
+.set SCSI_Out_DBx__0__PC, CYREG_PRT6_PC3\r
+.set SCSI_Out_DBx__0__PORT, 6\r
+.set SCSI_Out_DBx__0__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__0__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__0__SHIFT, 3\r
+.set SCSI_Out_DBx__0__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__1__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__1__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__1__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__1__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__1__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__1__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__1__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__1__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__1__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__1__MASK, 0x04\r
+.set SCSI_Out_DBx__1__PC, CYREG_PRT6_PC2\r
+.set SCSI_Out_DBx__1__PORT, 6\r
+.set SCSI_Out_DBx__1__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__1__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__1__SHIFT, 2\r
+.set SCSI_Out_DBx__1__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__2__MASK, 0x02\r
+.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC1\r
+.set SCSI_Out_DBx__2__PORT, 6\r
+.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__2__SHIFT, 1\r
+.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__3__MASK, 0x01\r
+.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC0\r
+.set SCSI_Out_DBx__3__PORT, 6\r
+.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__3__SHIFT, 0\r
+.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__4__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__4__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__4__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__4__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__4__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__4__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__4__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__4__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__4__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__4__MASK, 0x80\r
+.set SCSI_Out_DBx__4__PC, CYREG_PRT4_PC7\r
+.set SCSI_Out_DBx__4__PORT, 4\r
+.set SCSI_Out_DBx__4__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__4__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__4__SHIFT, 7\r
+.set SCSI_Out_DBx__4__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__5__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__5__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__5__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__5__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__5__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__5__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__5__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__5__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__5__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__5__MASK, 0x40\r
+.set SCSI_Out_DBx__5__PC, CYREG_PRT4_PC6\r
+.set SCSI_Out_DBx__5__PORT, 4\r
+.set SCSI_Out_DBx__5__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__5__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__5__SHIFT, 6\r
+.set SCSI_Out_DBx__5__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__6__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__6__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__6__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__6__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__6__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__6__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__6__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__6__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__6__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__6__MASK, 0x20\r
+.set SCSI_Out_DBx__6__PC, CYREG_PRT4_PC5\r
+.set SCSI_Out_DBx__6__PORT, 4\r
+.set SCSI_Out_DBx__6__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__6__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__6__SHIFT, 5\r
+.set SCSI_Out_DBx__6__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__7__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__7__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__7__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__7__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__7__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__7__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__7__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__7__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__7__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__7__MASK, 0x10\r
+.set SCSI_Out_DBx__7__PC, CYREG_PRT4_PC4\r
+.set SCSI_Out_DBx__7__PORT, 4\r
+.set SCSI_Out_DBx__7__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__7__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__7__SHIFT, 4\r
+.set SCSI_Out_DBx__7__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__DB0__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__DB0__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__DB0__MASK, 0x08\r
+.set SCSI_Out_DBx__DB0__PC, CYREG_PRT6_PC3\r
+.set SCSI_Out_DBx__DB0__PORT, 6\r
+.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__DB0__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__DB0__SHIFT, 3\r
+.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__DB1__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__DB1__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__DB1__MASK, 0x04\r
+.set SCSI_Out_DBx__DB1__PC, CYREG_PRT6_PC2\r
+.set SCSI_Out_DBx__DB1__PORT, 6\r
+.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__DB1__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__DB1__SHIFT, 2\r
+.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__DB2__MASK, 0x02\r
+.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC1\r
+.set SCSI_Out_DBx__DB2__PORT, 6\r
+.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__DB2__SHIFT, 1\r
+.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__DB3__MASK, 0x01\r
+.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC0\r
+.set SCSI_Out_DBx__DB3__PORT, 6\r
+.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__DB3__SHIFT, 0\r
+.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__DB4__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__DB4__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__DB4__MASK, 0x80\r
+.set SCSI_Out_DBx__DB4__PC, CYREG_PRT4_PC7\r
+.set SCSI_Out_DBx__DB4__PORT, 4\r
+.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__DB4__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__DB4__SHIFT, 7\r
+.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__DB5__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__DB5__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__DB5__MASK, 0x40\r
+.set SCSI_Out_DBx__DB5__PC, CYREG_PRT4_PC6\r
+.set SCSI_Out_DBx__DB5__PORT, 4\r
+.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__DB5__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__DB5__SHIFT, 6\r
+.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__DB6__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__DB6__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__DB6__MASK, 0x20\r
+.set SCSI_Out_DBx__DB6__PC, CYREG_PRT4_PC5\r
+.set SCSI_Out_DBx__DB6__PORT, 4\r
+.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__DB6__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__DB6__SHIFT, 5\r
+.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__DB7__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__DB7__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__DB7__MASK, 0x10\r
+.set SCSI_Out_DBx__DB7__PC, CYREG_PRT4_PC4\r
+.set SCSI_Out_DBx__DB7__PORT, 4\r
+.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__DB7__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__DB7__SHIFT, 4\r
+.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT4_SLW\r
+\r
+/* SD_RX_DMA */\r
+.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SD_RX_DMA__DRQ_NUMBER, 2\r
+.set SD_RX_DMA__NUMBEROF_TDS, 0\r
+.set SD_RX_DMA__PRIORITY, 2\r
+.set SD_RX_DMA__TERMIN_EN, 0\r
+.set SD_RX_DMA__TERMIN_SEL, 0\r
+.set SD_RX_DMA__TERMOUT0_EN, 1\r
+.set SD_RX_DMA__TERMOUT0_SEL, 2\r
+.set SD_RX_DMA__TERMOUT1_EN, 0\r
+.set SD_RX_DMA__TERMOUT1_SEL, 0\r
+\r
+/* SD_RX_DMA_COMPLETE */\r
+.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x10\r
+.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 4\r
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4\r
+.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SD_TX_DMA */\r
+.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SD_TX_DMA__DRQ_NUMBER, 3\r
+.set SD_TX_DMA__NUMBEROF_TDS, 0\r
+.set SD_TX_DMA__PRIORITY, 2\r
+.set SD_TX_DMA__TERMIN_EN, 0\r
+.set SD_TX_DMA__TERMIN_SEL, 0\r
+.set SD_TX_DMA__TERMOUT0_EN, 1\r
+.set SD_TX_DMA__TERMOUT0_SEL, 3\r
+.set SD_TX_DMA__TERMOUT1_EN, 0\r
+.set SD_TX_DMA__TERMOUT1_SEL, 0\r
+\r
+/* SD_TX_DMA_COMPLETE */\r
+.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x20\r
+.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 5\r
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5\r
+.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_Noise */\r
+.set SCSI_Noise__0__AG, CYREG_PRT12_AG\r
+.set SCSI_Noise__0__BIE, CYREG_PRT12_BIE\r
+.set SCSI_Noise__0__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_Noise__0__BYP, CYREG_PRT12_BYP\r
+.set SCSI_Noise__0__DM0, CYREG_PRT12_DM0\r
+.set SCSI_Noise__0__DM1, CYREG_PRT12_DM1\r
+.set SCSI_Noise__0__DM2, CYREG_PRT12_DM2\r
+.set SCSI_Noise__0__DR, CYREG_PRT12_DR\r
+.set SCSI_Noise__0__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_Noise__0__MASK, 0x20\r
+.set SCSI_Noise__0__PC, CYREG_PRT12_PC5\r
+.set SCSI_Noise__0__PORT, 12\r
+.set SCSI_Noise__0__PRT, CYREG_PRT12_PRT\r
+.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_Noise__0__PS, CYREG_PRT12_PS\r
+.set SCSI_Noise__0__SHIFT, 5\r
+.set SCSI_Noise__0__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_Noise__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_Noise__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_Noise__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_Noise__0__SLW, CYREG_PRT12_SLW\r
+.set SCSI_Noise__1__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__1__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__1__MASK, 0x10\r
+.set SCSI_Noise__1__PC, CYREG_PRT6_PC4\r
+.set SCSI_Noise__1__PORT, 6\r
+.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__1__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__1__SHIFT, 4\r
+.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__2__AG, CYREG_PRT5_AG\r
+.set SCSI_Noise__2__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_Noise__2__BIE, CYREG_PRT5_BIE\r
+.set SCSI_Noise__2__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_Noise__2__BYP, CYREG_PRT5_BYP\r
+.set SCSI_Noise__2__CTL, CYREG_PRT5_CTL\r
+.set SCSI_Noise__2__DM0, CYREG_PRT5_DM0\r
+.set SCSI_Noise__2__DM1, CYREG_PRT5_DM1\r
+.set SCSI_Noise__2__DM2, CYREG_PRT5_DM2\r
+.set SCSI_Noise__2__DR, CYREG_PRT5_DR\r
+.set SCSI_Noise__2__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_Noise__2__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_Noise__2__MASK, 0x01\r
+.set SCSI_Noise__2__PC, CYREG_PRT5_PC0\r
+.set SCSI_Noise__2__PORT, 5\r
+.set SCSI_Noise__2__PRT, CYREG_PRT5_PRT\r
+.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_Noise__2__PS, CYREG_PRT5_PS\r
+.set SCSI_Noise__2__SHIFT, 0\r
+.set SCSI_Noise__2__SLW, CYREG_PRT5_SLW\r
+.set SCSI_Noise__3__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__3__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__3__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__3__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__3__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__3__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__3__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__3__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__3__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__3__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__3__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__3__MASK, 0x40\r
+.set SCSI_Noise__3__PC, CYREG_PRT6_PC6\r
+.set SCSI_Noise__3__PORT, 6\r
+.set SCSI_Noise__3__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__3__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__3__SHIFT, 6\r
+.set SCSI_Noise__3__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__4__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__4__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__4__MASK, 0x20\r
+.set SCSI_Noise__4__PC, CYREG_PRT6_PC5\r
+.set SCSI_Noise__4__PORT, 6\r
+.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__4__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__4__SHIFT, 5\r
+.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__ACK__MASK, 0x20\r
+.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC5\r
+.set SCSI_Noise__ACK__PORT, 6\r
+.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__ACK__SHIFT, 5\r
+.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__ATN__AG, CYREG_PRT12_AG\r
+.set SCSI_Noise__ATN__BIE, CYREG_PRT12_BIE\r
+.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_Noise__ATN__BYP, CYREG_PRT12_BYP\r
+.set SCSI_Noise__ATN__DM0, CYREG_PRT12_DM0\r
+.set SCSI_Noise__ATN__DM1, CYREG_PRT12_DM1\r
+.set SCSI_Noise__ATN__DM2, CYREG_PRT12_DM2\r
+.set SCSI_Noise__ATN__DR, CYREG_PRT12_DR\r
+.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_Noise__ATN__MASK, 0x20\r
+.set SCSI_Noise__ATN__PC, CYREG_PRT12_PC5\r
+.set SCSI_Noise__ATN__PORT, 12\r
+.set SCSI_Noise__ATN__PRT, CYREG_PRT12_PRT\r
+.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_Noise__ATN__PS, CYREG_PRT12_PS\r
+.set SCSI_Noise__ATN__SHIFT, 5\r
+.set SCSI_Noise__ATN__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_Noise__ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_Noise__ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_Noise__ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_Noise__ATN__SLW, CYREG_PRT12_SLW\r
+.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__BSY__MASK, 0x10\r
+.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC4\r
+.set SCSI_Noise__BSY__PORT, 6\r
+.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__BSY__SHIFT, 4\r
+.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__RST__AG, CYREG_PRT6_AG\r
+.set SCSI_Noise__RST__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Noise__RST__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Noise__RST__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Noise__RST__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Noise__RST__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Noise__RST__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Noise__RST__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Noise__RST__DR, CYREG_PRT6_DR\r
+.set SCSI_Noise__RST__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Noise__RST__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Noise__RST__MASK, 0x40\r
+.set SCSI_Noise__RST__PC, CYREG_PRT6_PC6\r
+.set SCSI_Noise__RST__PORT, 6\r
+.set SCSI_Noise__RST__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Noise__RST__PS, CYREG_PRT6_PS\r
+.set SCSI_Noise__RST__SHIFT, 6\r
+.set SCSI_Noise__RST__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Noise__SEL__AG, CYREG_PRT5_AG\r
+.set SCSI_Noise__SEL__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_Noise__SEL__BIE, CYREG_PRT5_BIE\r
+.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_Noise__SEL__BYP, CYREG_PRT5_BYP\r
+.set SCSI_Noise__SEL__CTL, CYREG_PRT5_CTL\r
+.set SCSI_Noise__SEL__DM0, CYREG_PRT5_DM0\r
+.set SCSI_Noise__SEL__DM1, CYREG_PRT5_DM1\r
+.set SCSI_Noise__SEL__DM2, CYREG_PRT5_DM2\r
+.set SCSI_Noise__SEL__DR, CYREG_PRT5_DR\r
+.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_Noise__SEL__MASK, 0x01\r
+.set SCSI_Noise__SEL__PC, CYREG_PRT5_PC0\r
+.set SCSI_Noise__SEL__PORT, 5\r
+.set SCSI_Noise__SEL__PRT, CYREG_PRT5_PRT\r
+.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_Noise__SEL__PS, CYREG_PRT5_PS\r
+.set SCSI_Noise__SEL__SHIFT, 0\r
+.set SCSI_Noise__SEL__SLW, CYREG_PRT5_SLW\r
+\r
+/* scsiTarget */\r
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB05_06_A0\r
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB05_06_A1\r
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB05_06_D0\r
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB05_06_D1\r
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB05_06_F0\r
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB05_06_F1\r
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB05_A0_A1\r
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB05_A0\r
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB05_A1\r
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB05_D0_D1\r
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB05_D0\r
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB05_D1\r
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB05_F0_F1\r
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB05_F0\r
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB05_F1\r
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB05_MSK\r
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB05_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB05_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB05_ST\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB05_CTL\r
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB05_CTL\r
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB05_MSK\r
+.set scsiTarget_StatusReg__0__MASK, 0x01\r
+.set scsiTarget_StatusReg__0__POS, 0\r
+.set scsiTarget_StatusReg__1__MASK, 0x02\r
+.set scsiTarget_StatusReg__1__POS, 1\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST\r
+.set scsiTarget_StatusReg__2__MASK, 0x04\r
+.set scsiTarget_StatusReg__2__POS, 2\r
+.set scsiTarget_StatusReg__3__MASK, 0x08\r
+.set scsiTarget_StatusReg__3__POS, 3\r
+.set scsiTarget_StatusReg__4__MASK, 0x10\r
+.set scsiTarget_StatusReg__4__POS, 4\r
+.set scsiTarget_StatusReg__MASK, 0x1F\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK\r
+.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL\r
+.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST\r
\r
-/* SD_DAT2 */\r
-.set SD_DAT2__0__MASK, 0x20\r
-.set SD_DAT2__0__PC, CYREG_PRT3_PC5\r
-.set SD_DAT2__0__PORT, 3\r
-.set SD_DAT2__0__SHIFT, 5\r
-.set SD_DAT2__AG, CYREG_PRT3_AG\r
-.set SD_DAT2__AMUX, CYREG_PRT3_AMUX\r
-.set SD_DAT2__BIE, CYREG_PRT3_BIE\r
-.set SD_DAT2__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_DAT2__BYP, CYREG_PRT3_BYP\r
-.set SD_DAT2__CTL, CYREG_PRT3_CTL\r
-.set SD_DAT2__DM0, CYREG_PRT3_DM0\r
-.set SD_DAT2__DM1, CYREG_PRT3_DM1\r
-.set SD_DAT2__DM2, CYREG_PRT3_DM2\r
-.set SD_DAT2__DR, CYREG_PRT3_DR\r
-.set SD_DAT2__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_DAT2__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_DAT2__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_DAT2__MASK, 0x20\r
-.set SD_DAT2__PORT, 3\r
-.set SD_DAT2__PRT, CYREG_PRT3_PRT\r
-.set SD_DAT2__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_DAT2__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_DAT2__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_DAT2__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_DAT2__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_DAT2__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_DAT2__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_DAT2__PS, CYREG_PRT3_PS\r
-.set SD_DAT2__SHIFT, 5\r
-.set SD_DAT2__SLW, CYREG_PRT3_SLW\r
+/* Debug_Timer_Interrupt */\r
+.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set Debug_Timer_Interrupt__INTC_MASK, 0x02\r
+.set Debug_Timer_Interrupt__INTC_NUMBER, 1\r
+.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7\r
+.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
+.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
-/* SD_MISO */\r
-.set SD_MISO__0__MASK, 0x02\r
-.set SD_MISO__0__PC, CYREG_PRT3_PC1\r
-.set SD_MISO__0__PORT, 3\r
-.set SD_MISO__0__SHIFT, 1\r
-.set SD_MISO__AG, CYREG_PRT3_AG\r
-.set SD_MISO__AMUX, CYREG_PRT3_AMUX\r
-.set SD_MISO__BIE, CYREG_PRT3_BIE\r
-.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_MISO__BYP, CYREG_PRT3_BYP\r
-.set SD_MISO__CTL, CYREG_PRT3_CTL\r
-.set SD_MISO__DM0, CYREG_PRT3_DM0\r
-.set SD_MISO__DM1, CYREG_PRT3_DM1\r
-.set SD_MISO__DM2, CYREG_PRT3_DM2\r
-.set SD_MISO__DR, CYREG_PRT3_DR\r
-.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_MISO__MASK, 0x02\r
-.set SD_MISO__PORT, 3\r
-.set SD_MISO__PRT, CYREG_PRT3_PRT\r
-.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_MISO__PS, CYREG_PRT3_PS\r
-.set SD_MISO__SHIFT, 1\r
-.set SD_MISO__SLW, CYREG_PRT3_SLW\r
+/* Debug_Timer_TimerHW */\r
+.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0\r
+.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1\r
+.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0\r
+.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1\r
+.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2\r
+.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0\r
+.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1\r
+.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0\r
+.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1\r
+.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3\r
+.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01\r
+.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3\r
+.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01\r
+.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0\r
+.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1\r
+.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0\r
+\r
+/* SCSI_RX_DMA */\r
+.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SCSI_RX_DMA__DRQ_NUMBER, 0\r
+.set SCSI_RX_DMA__NUMBEROF_TDS, 0\r
+.set SCSI_RX_DMA__PRIORITY, 2\r
+.set SCSI_RX_DMA__TERMIN_EN, 0\r
+.set SCSI_RX_DMA__TERMIN_SEL, 0\r
+.set SCSI_RX_DMA__TERMOUT0_EN, 1\r
+.set SCSI_RX_DMA__TERMOUT0_SEL, 0\r
+.set SCSI_RX_DMA__TERMOUT1_EN, 0\r
+.set SCSI_RX_DMA__TERMOUT1_SEL, 0\r
+\r
+/* SCSI_RX_DMA_COMPLETE */\r
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x01\r
+.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_TX_DMA */\r
+.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0\r
+.set SCSI_TX_DMA__DRQ_NUMBER, 1\r
+.set SCSI_TX_DMA__NUMBEROF_TDS, 0\r
+.set SCSI_TX_DMA__PRIORITY, 2\r
+.set SCSI_TX_DMA__TERMIN_EN, 0\r
+.set SCSI_TX_DMA__TERMIN_SEL, 0\r
+.set SCSI_TX_DMA__TERMOUT0_EN, 1\r
+.set SCSI_TX_DMA__TERMOUT0_SEL, 1\r
+.set SCSI_TX_DMA__TERMOUT1_EN, 0\r
+.set SCSI_TX_DMA__TERMOUT1_SEL, 0\r
+\r
+/* SCSI_TX_DMA_COMPLETE */\r
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x08\r
+.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 3\r
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7\r
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3\r
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SD_Data_Clk */\r
+.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0\r
+.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1\r
+.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2\r
+.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07\r
+.set SD_Data_Clk__INDEX, 0x00\r
+.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
+.set SD_Data_Clk__PM_ACT_MSK, 0x01\r
+.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
+.set SD_Data_Clk__PM_STBY_MSK, 0x01\r
\r
-/* SD_MOSI */\r
-.set SD_MOSI__0__MASK, 0x08\r
-.set SD_MOSI__0__PC, CYREG_PRT3_PC3\r
-.set SD_MOSI__0__PORT, 3\r
-.set SD_MOSI__0__SHIFT, 3\r
-.set SD_MOSI__AG, CYREG_PRT3_AG\r
-.set SD_MOSI__AMUX, CYREG_PRT3_AMUX\r
-.set SD_MOSI__BIE, CYREG_PRT3_BIE\r
-.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_MOSI__BYP, CYREG_PRT3_BYP\r
-.set SD_MOSI__CTL, CYREG_PRT3_CTL\r
-.set SD_MOSI__DM0, CYREG_PRT3_DM0\r
-.set SD_MOSI__DM1, CYREG_PRT3_DM1\r
-.set SD_MOSI__DM2, CYREG_PRT3_DM2\r
-.set SD_MOSI__DR, CYREG_PRT3_DR\r
-.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_MOSI__MASK, 0x08\r
-.set SD_MOSI__PORT, 3\r
-.set SD_MOSI__PRT, CYREG_PRT3_PRT\r
-.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_MOSI__PS, CYREG_PRT3_PS\r
-.set SD_MOSI__SHIFT, 3\r
-.set SD_MOSI__SLW, CYREG_PRT3_SLW\r
+/* timer_clock */\r
+.set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0\r
+.set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1\r
+.set timer_clock__CFG2, CYREG_CLKDIST_DCFG2_CFG2\r
+.set timer_clock__CFG2_SRC_SEL_MASK, 0x07\r
+.set timer_clock__INDEX, 0x02\r
+.set timer_clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
+.set timer_clock__PM_ACT_MSK, 0x04\r
+.set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
+.set timer_clock__PM_STBY_MSK, 0x04\r
\r
-/* SD_SCK */\r
-.set SD_SCK__0__MASK, 0x04\r
-.set SD_SCK__0__PC, CYREG_PRT3_PC2\r
-.set SD_SCK__0__PORT, 3\r
-.set SD_SCK__0__SHIFT, 2\r
-.set SD_SCK__AG, CYREG_PRT3_AG\r
-.set SD_SCK__AMUX, CYREG_PRT3_AMUX\r
-.set SD_SCK__BIE, CYREG_PRT3_BIE\r
-.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_SCK__BYP, CYREG_PRT3_BYP\r
-.set SD_SCK__CTL, CYREG_PRT3_CTL\r
-.set SD_SCK__DM0, CYREG_PRT3_DM0\r
-.set SD_SCK__DM1, CYREG_PRT3_DM1\r
-.set SD_SCK__DM2, CYREG_PRT3_DM2\r
-.set SD_SCK__DR, CYREG_PRT3_DR\r
-.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_SCK__MASK, 0x04\r
-.set SD_SCK__PORT, 3\r
-.set SD_SCK__PRT, CYREG_PRT3_PRT\r
-.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_SCK__PS, CYREG_PRT3_PS\r
-.set SD_SCK__SHIFT, 2\r
-.set SD_SCK__SLW, CYREG_PRT3_SLW\r
+/* SCSI_RST_ISR */\r
+.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SCSI_RST_ISR__INTC_MASK, 0x04\r
+.set SCSI_RST_ISR__INTC_NUMBER, 2\r
+.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7\r
+.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_2\r
+.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
-/* SD_CD */\r
-.set SD_CD__0__MASK, 0x40\r
-.set SD_CD__0__PC, CYREG_PRT3_PC6\r
-.set SD_CD__0__PORT, 3\r
-.set SD_CD__0__SHIFT, 6\r
-.set SD_CD__AG, CYREG_PRT3_AG\r
-.set SD_CD__AMUX, CYREG_PRT3_AMUX\r
-.set SD_CD__BIE, CYREG_PRT3_BIE\r
-.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_CD__BYP, CYREG_PRT3_BYP\r
-.set SD_CD__CTL, CYREG_PRT3_CTL\r
-.set SD_CD__DM0, CYREG_PRT3_DM0\r
-.set SD_CD__DM1, CYREG_PRT3_DM1\r
-.set SD_CD__DM2, CYREG_PRT3_DM2\r
-.set SD_CD__DR, CYREG_PRT3_DR\r
-.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_CD__MASK, 0x40\r
-.set SD_CD__PORT, 3\r
-.set SD_CD__PRT, CYREG_PRT3_PRT\r
-.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_CD__PS, CYREG_PRT3_PS\r
-.set SD_CD__SHIFT, 6\r
-.set SD_CD__SLW, CYREG_PRT3_SLW\r
+/* SCSI_Filtered */\r
+.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01\r
+.set SCSI_Filtered_sts_sts_reg__0__POS, 0\r
+.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02\r
+.set SCSI_Filtered_sts_sts_reg__1__POS, 1\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST\r
+.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04\r
+.set SCSI_Filtered_sts_sts_reg__2__POS, 2\r
+.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08\r
+.set SCSI_Filtered_sts_sts_reg__3__POS, 3\r
+.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10\r
+.set SCSI_Filtered_sts_sts_reg__4__POS, 4\r
+.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F\r
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB12_MSK\r
+.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB12_ST\r
\r
-/* SD_CS */\r
-.set SD_CS__0__MASK, 0x10\r
-.set SD_CS__0__PC, CYREG_PRT3_PC4\r
-.set SD_CS__0__PORT, 3\r
-.set SD_CS__0__SHIFT, 4\r
-.set SD_CS__AG, CYREG_PRT3_AG\r
-.set SD_CS__AMUX, CYREG_PRT3_AMUX\r
-.set SD_CS__BIE, CYREG_PRT3_BIE\r
-.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_CS__BYP, CYREG_PRT3_BYP\r
-.set SD_CS__CTL, CYREG_PRT3_CTL\r
-.set SD_CS__DM0, CYREG_PRT3_DM0\r
-.set SD_CS__DM1, CYREG_PRT3_DM1\r
-.set SD_CS__DM2, CYREG_PRT3_DM2\r
-.set SD_CS__DR, CYREG_PRT3_DR\r
-.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_CS__MASK, 0x10\r
-.set SD_CS__PORT, 3\r
-.set SD_CS__PRT, CYREG_PRT3_PRT\r
-.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_CS__PS, CYREG_PRT3_PS\r
-.set SD_CS__SHIFT, 4\r
-.set SD_CS__SLW, CYREG_PRT3_SLW\r
+/* SCSI_CTL_PHASE */\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK\r
\r
-/* LED1 */\r
-.set LED1__0__MASK, 0x08\r
-.set LED1__0__PC, CYREG_PRT12_PC3\r
-.set LED1__0__PORT, 12\r
-.set LED1__0__SHIFT, 3\r
-.set LED1__AG, CYREG_PRT12_AG\r
-.set LED1__BIE, CYREG_PRT12_BIE\r
-.set LED1__BIT_MASK, CYREG_PRT12_BIT_MASK\r
-.set LED1__BYP, CYREG_PRT12_BYP\r
-.set LED1__DM0, CYREG_PRT12_DM0\r
-.set LED1__DM1, CYREG_PRT12_DM1\r
-.set LED1__DM2, CYREG_PRT12_DM2\r
-.set LED1__DR, CYREG_PRT12_DR\r
-.set LED1__INP_DIS, CYREG_PRT12_INP_DIS\r
-.set LED1__MASK, 0x08\r
-.set LED1__PORT, 12\r
-.set LED1__PRT, CYREG_PRT12_PRT\r
-.set LED1__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
-.set LED1__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
-.set LED1__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
-.set LED1__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
-.set LED1__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
-.set LED1__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
-.set LED1__PS, CYREG_PRT12_PS\r
-.set LED1__SHIFT, 3\r
-.set LED1__SIO_CFG, CYREG_PRT12_SIO_CFG\r
-.set LED1__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
-.set LED1__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
-.set LED1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
-.set LED1__SLW, CYREG_PRT12_SLW\r
+/* SCSI_Parity_Error */\r
+.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
+.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB06_MSK\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB06_ST\r
\r
/* Miscellaneous */\r
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */\r
-.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6\r
-.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0\r
-.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0\r
-.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1\r
-.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0\r
-.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0\r
-.set CYDEV_CHIP_MEMBER_5B, 4\r
-.set CYDEV_CHIP_FAMILY_PSOC5, 3\r
-.set CYDEV_CHIP_DIE_PSOC5LP, 4\r
-.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP\r
.set BCLK__BUS_CLK__HZ, 50000000\r
.set BCLK__BUS_CLK__KHZ, 50000\r
.set BCLK__BUS_CLK__MHZ, 50\r
-.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT\r
.set CYDEV_CHIP_DIE_LEOPARD, 1\r
-.set CYDEV_CHIP_DIE_PANTHER, 3\r
-.set CYDEV_CHIP_DIE_PSOC4A, 2\r
+.set CYDEV_CHIP_DIE_PANTHER, 6\r
+.set CYDEV_CHIP_DIE_PSOC4A, 3\r
+.set CYDEV_CHIP_DIE_PSOC5LP, 5\r
.set CYDEV_CHIP_DIE_UNKNOWN, 0\r
.set CYDEV_CHIP_FAMILY_PSOC3, 1\r
.set CYDEV_CHIP_FAMILY_PSOC4, 2\r
+.set CYDEV_CHIP_FAMILY_PSOC5, 3\r
.set CYDEV_CHIP_FAMILY_UNKNOWN, 0\r
.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5\r
.set CYDEV_CHIP_JTAG_ID, 0x2E133069\r
.set CYDEV_CHIP_MEMBER_3A, 1\r
-.set CYDEV_CHIP_MEMBER_4A, 2\r
-.set CYDEV_CHIP_MEMBER_5A, 3\r
+.set CYDEV_CHIP_MEMBER_4A, 3\r
+.set CYDEV_CHIP_MEMBER_4D, 2\r
+.set CYDEV_CHIP_MEMBER_4F, 4\r
+.set CYDEV_CHIP_MEMBER_5A, 6\r
+.set CYDEV_CHIP_MEMBER_5B, 5\r
.set CYDEV_CHIP_MEMBER_UNKNOWN, 0\r
.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B\r
+.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED\r
+.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT\r
+.set CYDEV_CHIP_REV_LEOPARD_ES1, 0\r
+.set CYDEV_CHIP_REV_LEOPARD_ES2, 1\r
+.set CYDEV_CHIP_REV_LEOPARD_ES3, 3\r
+.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3\r
+.set CYDEV_CHIP_REV_PANTHER_ES0, 0\r
+.set CYDEV_CHIP_REV_PANTHER_ES1, 1\r
+.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1\r
+.set CYDEV_CHIP_REV_PSOC4A_ES0, 17\r
+.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17\r
+.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0\r
+.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_3A_ES1, 0\r
.set CYDEV_CHIP_REVISION_3A_ES2, 1\r
.set CYDEV_CHIP_REVISION_3A_ES3, 3\r
.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3\r
.set CYDEV_CHIP_REVISION_4A_ES0, 17\r
.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17\r
+.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_5A_ES0, 0\r
.set CYDEV_CHIP_REVISION_5A_ES1, 1\r
.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1\r
.set CYDEV_CHIP_REVISION_5B_ES0, 0\r
+.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION\r
-.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REV_PSOC5LP_PRODUCTION\r
-.set CYDEV_CHIP_REV_LEOPARD_ES1, 0\r
-.set CYDEV_CHIP_REV_LEOPARD_ES2, 1\r
-.set CYDEV_CHIP_REV_LEOPARD_ES3, 3\r
-.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3\r
-.set CYDEV_CHIP_REV_PANTHER_ES0, 0\r
-.set CYDEV_CHIP_REV_PANTHER_ES1, 1\r
-.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1\r
-.set CYDEV_CHIP_REV_PSOC4A_ES0, 17\r
-.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17\r
-.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0\r
+.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED\r
+.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1\r
+.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0\r
+.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
+.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1\r
+.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2\r
.set CYDEV_CONFIGURATION_COMPRESSED, 1\r
.set CYDEV_CONFIGURATION_DMA, 0\r
.set CYDEV_CONFIGURATION_ECC, 0\r
.set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED\r
+.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0\r
.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED\r
.set CYDEV_CONFIGURATION_MODE_DMA, 2\r
.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1\r
-.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
-.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1\r
-.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2\r
-.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV\r
+.set CYDEV_DEBUG_ENABLE_MASK, 0x20\r
+.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG\r
.set CYDEV_DEBUGGING_DPS_Disable, 3\r
.set CYDEV_DEBUGGING_DPS_JTAG_4, 1\r
.set CYDEV_DEBUGGING_DPS_JTAG_5, 0\r
.set CYDEV_DEBUGGING_DPS_SWD, 2\r
+.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6\r
+.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV\r
.set CYDEV_DEBUGGING_ENABLE, 1\r
.set CYDEV_DEBUGGING_XRES, 0\r
-.set CYDEV_DEBUG_ENABLE_MASK, 0x20\r
-.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG\r
.set CYDEV_DMA_CHANNELS_AVAILABLE, 24\r
.set CYDEV_ECC_ENABLE, 0\r
.set CYDEV_HEAP_SIZE, 0x0400\r
.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3\r
.set CYDEV_PROJ_TYPE_STANDARD, 0\r
.set CYDEV_PROTECTION_ENABLE, 0\r
-.set CYDEV_STACK_SIZE, 0x2000\r
+.set CYDEV_STACK_SIZE, 0x1000\r
.set CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP, 1\r
.set CYDEV_USE_BUNDLED_CMSIS, 1\r
.set CYDEV_VARIABLE_VDDA, 0\r
.set CYDEV_VDDIO1_MV, 5000\r
.set CYDEV_VDDIO2_MV, 5000\r
.set CYDEV_VDDIO3_MV, 3300\r
-.set CYDEV_VIO0, 5\r
.set CYDEV_VIO0_MV, 5000\r
-.set CYDEV_VIO1, 5\r
.set CYDEV_VIO1_MV, 5000\r
-.set CYDEV_VIO2, 5\r
.set CYDEV_VIO2_MV, 5000\r
.set CYDEV_VIO3_MV, 3300\r
+.set CYIPBLOCK_ARM_CM3_VERSION, 0\r
+.set CYIPBLOCK_P3_ANAIF_VERSION, 0\r
+.set CYIPBLOCK_P3_CAPSENSE_VERSION, 0\r
+.set CYIPBLOCK_P3_COMP_VERSION, 0\r
+.set CYIPBLOCK_P3_DMA_VERSION, 0\r
+.set CYIPBLOCK_P3_DRQ_VERSION, 0\r
+.set CYIPBLOCK_P3_EMIF_VERSION, 0\r
+.set CYIPBLOCK_P3_I2C_VERSION, 0\r
+.set CYIPBLOCK_P3_LCD_VERSION, 0\r
+.set CYIPBLOCK_P3_LPF_VERSION, 0\r
+.set CYIPBLOCK_P3_PM_VERSION, 0\r
+.set CYIPBLOCK_P3_TIMER_VERSION, 0\r
+.set CYIPBLOCK_P3_USB_VERSION, 0\r
+.set CYIPBLOCK_P3_VIDAC_VERSION, 0\r
+.set CYIPBLOCK_P3_VREF_VERSION, 0\r
+.set CYIPBLOCK_S8_GPIO_VERSION, 0\r
+.set CYIPBLOCK_S8_IRQ_VERSION, 0\r
+.set CYIPBLOCK_S8_SAR_VERSION, 0\r
+.set CYIPBLOCK_S8_SIO_VERSION, 0\r
+.set CYIPBLOCK_S8_UDB_VERSION, 0\r
.set DMA_CHANNELS_USED__MASK0, 0x0000000F\r
.set CYDEV_BOOTLOADER_ENABLE, 0\r
.endif\r
INCLUDE cydeviceiar.inc\r
INCLUDE cydeviceiar_trm.inc\r
\r
-/* Debug_Timer_Interrupt */\r
-Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-Debug_Timer_Interrupt__INTC_MASK EQU 0x02\r
-Debug_Timer_Interrupt__INTC_NUMBER EQU 1\r
-Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
-Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
-Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_RX_DMA_COMPLETE */\r
-SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01\r
-SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0\r
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
-SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_TX_DMA_COMPLETE */\r
-SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08\r
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
-SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* Debug_Timer_TimerHW */\r
-Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
-Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
-Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
-Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
-Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
-Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
-Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
-Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
-Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
-Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
-Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01\r
-Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
-Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01\r
-Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
-Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
-Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
+/* LED1 */\r
+LED1__0__MASK EQU 0x08\r
+LED1__0__PC EQU CYREG_PRT12_PC3\r
+LED1__0__PORT EQU 12\r
+LED1__0__SHIFT EQU 3\r
+LED1__AG EQU CYREG_PRT12_AG\r
+LED1__BIE EQU CYREG_PRT12_BIE\r
+LED1__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+LED1__BYP EQU CYREG_PRT12_BYP\r
+LED1__DM0 EQU CYREG_PRT12_DM0\r
+LED1__DM1 EQU CYREG_PRT12_DM1\r
+LED1__DM2 EQU CYREG_PRT12_DM2\r
+LED1__DR EQU CYREG_PRT12_DR\r
+LED1__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+LED1__MASK EQU 0x08\r
+LED1__PORT EQU 12\r
+LED1__PRT EQU CYREG_PRT12_PRT\r
+LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+LED1__PS EQU CYREG_PRT12_PS\r
+LED1__SHIFT EQU 3\r
+LED1__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+LED1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+LED1__SLW EQU CYREG_PRT12_SLW\r
\r
-/* SD_RX_DMA_COMPLETE */\r
-SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
-SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+/* SD_CD */\r
+SD_CD__0__MASK EQU 0x40\r
+SD_CD__0__PC EQU CYREG_PRT3_PC6\r
+SD_CD__0__PORT EQU 3\r
+SD_CD__0__SHIFT EQU 6\r
+SD_CD__AG EQU CYREG_PRT3_AG\r
+SD_CD__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CD__BIE EQU CYREG_PRT3_BIE\r
+SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CD__BYP EQU CYREG_PRT3_BYP\r
+SD_CD__CTL EQU CYREG_PRT3_CTL\r
+SD_CD__DM0 EQU CYREG_PRT3_DM0\r
+SD_CD__DM1 EQU CYREG_PRT3_DM1\r
+SD_CD__DM2 EQU CYREG_PRT3_DM2\r
+SD_CD__DR EQU CYREG_PRT3_DR\r
+SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CD__MASK EQU 0x40\r
+SD_CD__PORT EQU 3\r
+SD_CD__PRT EQU CYREG_PRT3_PRT\r
+SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CD__PS EQU CYREG_PRT3_PS\r
+SD_CD__SHIFT EQU 6\r
+SD_CD__SLW EQU CYREG_PRT3_SLW\r
\r
-/* SD_TX_DMA_COMPLETE */\r
-SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
-SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+/* SD_CS */\r
+SD_CS__0__MASK EQU 0x10\r
+SD_CS__0__PC EQU CYREG_PRT3_PC4\r
+SD_CS__0__PORT EQU 3\r
+SD_CS__0__SHIFT EQU 4\r
+SD_CS__AG EQU CYREG_PRT3_AG\r
+SD_CS__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CS__BIE EQU CYREG_PRT3_BIE\r
+SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CS__BYP EQU CYREG_PRT3_BYP\r
+SD_CS__CTL EQU CYREG_PRT3_CTL\r
+SD_CS__DM0 EQU CYREG_PRT3_DM0\r
+SD_CS__DM1 EQU CYREG_PRT3_DM1\r
+SD_CS__DM2 EQU CYREG_PRT3_DM2\r
+SD_CS__DR EQU CYREG_PRT3_DR\r
+SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CS__MASK EQU 0x10\r
+SD_CS__PORT EQU 3\r
+SD_CS__PRT EQU CYREG_PRT3_PRT\r
+SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CS__PS EQU CYREG_PRT3_PS\r
+SD_CS__SHIFT EQU 4\r
+SD_CS__SLW EQU CYREG_PRT3_SLW\r
\r
-/* SCSI_Parity_Error */\r
-SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
-SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
+/* USBFS_arb_int */\r
+USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_arb_int__INTC_MASK EQU 0x400000\r
+USBFS_arb_int__INTC_NUMBER EQU 22\r
+USBFS_arb_int__INTC_PRIOR_NUM EQU 7\r
+USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22\r
+USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* USBFS_bus_reset */\r
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
-/* SCSI_CTL_PHASE */\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
-\r
-/* SCSI_Filtered */\r
-SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
-SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST\r
-SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
-SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
-SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
-SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
-SCSI_Filtered_sts_sts_reg__3__POS EQU 3\r
-SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
-SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
-SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB14_MSK\r
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB14_ST_CTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB14_ST_CTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB14_ST\r
-\r
-/* SCSI_Out_Bits */\r
-SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
-SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
-SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
-SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3\r
-SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10\r
-SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4\r
-SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20\r
-SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5\r
-SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40\r
-SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
-SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
-SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-\r
-/* USBFS_arb_int */\r
-USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_arb_int__INTC_MASK EQU 0x400000\r
-USBFS_arb_int__INTC_NUMBER EQU 22\r
-USBFS_arb_int__INTC_PRIOR_NUM EQU 7\r
-USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22\r
-USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+/* USBFS_Dm */\r
+USBFS_Dm__0__MASK EQU 0x80\r
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1\r
+USBFS_Dm__0__PORT EQU 15\r
+USBFS_Dm__0__SHIFT EQU 7\r
+USBFS_Dm__AG EQU CYREG_PRT15_AG\r
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX\r
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE\r
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP\r
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL\r
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0\r
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1\r
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2\r
+USBFS_Dm__DR EQU CYREG_PRT15_DR\r
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+USBFS_Dm__MASK EQU 0x80\r
+USBFS_Dm__PORT EQU 15\r
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT\r
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+USBFS_Dm__PS EQU CYREG_PRT15_PS\r
+USBFS_Dm__SHIFT EQU 7\r
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW\r
+\r
+/* USBFS_Dp */\r
+USBFS_Dp__0__MASK EQU 0x40\r
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0\r
+USBFS_Dp__0__PORT EQU 15\r
+USBFS_Dp__0__SHIFT EQU 6\r
+USBFS_Dp__AG EQU CYREG_PRT15_AG\r
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX\r
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE\r
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP\r
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL\r
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0\r
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1\r
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2\r
+USBFS_Dp__DR EQU CYREG_PRT15_DR\r
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT\r
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+USBFS_Dp__MASK EQU 0x40\r
+USBFS_Dp__PORT EQU 15\r
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT\r
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+USBFS_Dp__PS EQU CYREG_PRT15_PS\r
+USBFS_Dp__SHIFT EQU 6\r
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW\r
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15\r
+\r
+/* USBFS_dp_int */\r
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_dp_int__INTC_MASK EQU 0x1000\r
+USBFS_dp_int__INTC_NUMBER EQU 12\r
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7\r
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12\r
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_0 */\r
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_0__INTC_MASK EQU 0x1000000\r
+USBFS_ep_0__INTC_NUMBER EQU 24\r
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24\r
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_1 */\r
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_1__INTC_MASK EQU 0x40\r
+USBFS_ep_1__INTC_NUMBER EQU 6\r
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_2 */\r
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_2__INTC_MASK EQU 0x80\r
+USBFS_ep_2__INTC_NUMBER EQU 7\r
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_3 */\r
+USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_3__INTC_MASK EQU 0x100\r
+USBFS_ep_3__INTC_NUMBER EQU 8\r
+USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
+USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_4 */\r
+USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_4__INTC_MASK EQU 0x200\r
+USBFS_ep_4__INTC_NUMBER EQU 9\r
+USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9\r
+USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* USBFS_sof_int */\r
USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
-/* SCSI_Out_Ctl */\r
-SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+/* USBFS_USB */\r
+USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG\r
+USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG\r
+USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN\r
+USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR\r
+USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG\r
+USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN\r
+USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR\r
+USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG\r
+USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN\r
+USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR\r
+USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG\r
+USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN\r
+USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR\r
+USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG\r
+USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN\r
+USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR\r
+USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG\r
+USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN\r
+USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR\r
+USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG\r
+USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN\r
+USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR\r
+USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG\r
+USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN\r
+USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR\r
+USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN\r
+USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR\r
+USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR\r
+USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA\r
+USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB\r
+USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA\r
+USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB\r
+USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR\r
+USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA\r
+USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB\r
+USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA\r
+USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB\r
+USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR\r
+USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA\r
+USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB\r
+USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA\r
+USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB\r
+USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR\r
+USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA\r
+USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB\r
+USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA\r
+USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB\r
+USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR\r
+USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA\r
+USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB\r
+USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA\r
+USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB\r
+USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR\r
+USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA\r
+USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB\r
+USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA\r
+USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB\r
+USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR\r
+USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA\r
+USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB\r
+USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA\r
+USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB\r
+USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR\r
+USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA\r
+USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB\r
+USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA\r
+USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB\r
+USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE\r
+USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT\r
+USBFS_USB__CR0 EQU CYREG_USB_CR0\r
+USBFS_USB__CR1 EQU CYREG_USB_CR1\r
+USBFS_USB__CWA EQU CYREG_USB_CWA\r
+USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB\r
+USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES\r
+USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB\r
+USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG\r
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE\r
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE\r
+USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT\r
+USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR\r
+USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0\r
+USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1\r
+USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2\r
+USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3\r
+USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4\r
+USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5\r
+USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6\r
+USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7\r
+USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE\r
+USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5\r
+USBFS_USB__PM_ACT_MSK EQU 0x01\r
+USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5\r
+USBFS_USB__PM_STBY_MSK EQU 0x01\r
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN\r
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR\r
+USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0\r
+USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1\r
+USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0\r
+USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0\r
+USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1\r
+USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0\r
+USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0\r
+USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1\r
+USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0\r
+USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0\r
+USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1\r
+USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0\r
+USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0\r
+USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1\r
+USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0\r
+USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0\r
+USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1\r
+USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0\r
+USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0\r
+USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1\r
+USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0\r
+USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0\r
+USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1\r
+USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0\r
+USBFS_USB__SOF0 EQU CYREG_USB_SOF0\r
+USBFS_USB__SOF1 EQU CYREG_USB_SOF1\r
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN\r
+USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0\r
+USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
\r
-/* SCSI_Out_DBx */\r
-SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__0__MASK EQU 0x08\r
-SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out_DBx__0__PORT EQU 6\r
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__0__SHIFT EQU 3\r
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__1__MASK EQU 0x04\r
-SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2\r
-SCSI_Out_DBx__1__PORT EQU 6\r
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__1__SHIFT EQU 2\r
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__2__MASK EQU 0x02\r
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out_DBx__2__PORT EQU 6\r
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__2__SHIFT EQU 1\r
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__3__MASK EQU 0x01\r
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out_DBx__3__PORT EQU 6\r
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__3__SHIFT EQU 0\r
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__4__MASK EQU 0x80\r
-SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7\r
-SCSI_Out_DBx__4__PORT EQU 4\r
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__4__SHIFT EQU 7\r
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__5__MASK EQU 0x40\r
-SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6\r
-SCSI_Out_DBx__5__PORT EQU 4\r
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__5__SHIFT EQU 6\r
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__6__MASK EQU 0x20\r
-SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out_DBx__6__PORT EQU 4\r
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__6__SHIFT EQU 5\r
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__7__MASK EQU 0x10\r
-SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out_DBx__7__PORT EQU 4\r
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__7__SHIFT EQU 4\r
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB0__MASK EQU 0x08\r
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out_DBx__DB0__PORT EQU 6\r
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB0__SHIFT EQU 3\r
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB1__MASK EQU 0x04\r
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2\r
-SCSI_Out_DBx__DB1__PORT EQU 6\r
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB1__SHIFT EQU 2\r
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB2__MASK EQU 0x02\r
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out_DBx__DB2__PORT EQU 6\r
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB2__SHIFT EQU 1\r
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB3__MASK EQU 0x01\r
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out_DBx__DB3__PORT EQU 6\r
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB3__SHIFT EQU 0\r
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB4__MASK EQU 0x80\r
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7\r
-SCSI_Out_DBx__DB4__PORT EQU 4\r
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB4__SHIFT EQU 7\r
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB5__MASK EQU 0x40\r
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6\r
-SCSI_Out_DBx__DB5__PORT EQU 4\r
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB5__SHIFT EQU 6\r
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB6__MASK EQU 0x20\r
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out_DBx__DB6__PORT EQU 4\r
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB6__SHIFT EQU 5\r
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB7__MASK EQU 0x10\r
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out_DBx__DB7__PORT EQU 4\r
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB7__SHIFT EQU 4\r
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW\r
-\r
-/* SCSI_RST_ISR */\r
-SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_RST_ISR__INTC_MASK EQU 0x04\r
-SCSI_RST_ISR__INTC_NUMBER EQU 2\r
-SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
-SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SDCard_BSPIM */\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
-SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
-SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
-SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
-SDCard_BSPIM_RxStsReg__5__POS EQU 5\r
-SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
-SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
-SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
-SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
-SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
-SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
-SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
-SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
-SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
-SDCard_BSPIM_TxStsReg__3__POS EQU 3\r
-SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
-SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
-SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-\r
-/* USBFS_dp_int */\r
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_dp_int__INTC_MASK EQU 0x1000\r
-USBFS_dp_int__INTC_NUMBER EQU 12\r
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7\r
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12\r
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SCSI_In_DBx */\r
-SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__0__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__0__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__0__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__0__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__0__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__0__MASK EQU 0x10\r
-SCSI_In_DBx__0__PC EQU CYREG_PRT12_PC4\r
-SCSI_In_DBx__0__PORT EQU 12\r
-SCSI_In_DBx__0__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__0__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__0__SHIFT EQU 4\r
-SCSI_In_DBx__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__0__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__1__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__1__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__1__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__1__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__1__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__1__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__1__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__1__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__1__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__1__MASK EQU 0x80\r
-SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC7\r
-SCSI_In_DBx__1__PORT EQU 2\r
-SCSI_In_DBx__1__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__1__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__1__SHIFT EQU 7\r
-SCSI_In_DBx__1__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__2__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__2__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__2__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__2__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__2__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__2__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__2__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__2__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__2__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__2__MASK EQU 0x40\r
-SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC6\r
-SCSI_In_DBx__2__PORT EQU 2\r
-SCSI_In_DBx__2__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__2__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__2__SHIFT EQU 6\r
-SCSI_In_DBx__2__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__3__MASK EQU 0x20\r
-SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC5\r
-SCSI_In_DBx__3__PORT EQU 2\r
-SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__3__SHIFT EQU 5\r
-SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__4__MASK EQU 0x10\r
-SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4\r
-SCSI_In_DBx__4__PORT EQU 2\r
-SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__4__SHIFT EQU 4\r
-SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__5__MASK EQU 0x08\r
-SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC3\r
-SCSI_In_DBx__5__PORT EQU 2\r
-SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__5__SHIFT EQU 3\r
-SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__6__MASK EQU 0x04\r
-SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC2\r
-SCSI_In_DBx__6__PORT EQU 2\r
-SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__6__SHIFT EQU 2\r
-SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__7__MASK EQU 0x02\r
-SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC1\r
-SCSI_In_DBx__7__PORT EQU 2\r
-SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__7__SHIFT EQU 1\r
-SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB0__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__DB0__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__DB0__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__DB0__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__DB0__MASK EQU 0x10\r
-SCSI_In_DBx__DB0__PC EQU CYREG_PRT12_PC4\r
-SCSI_In_DBx__DB0__PORT EQU 12\r
-SCSI_In_DBx__DB0__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__DB0__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__DB0__SHIFT EQU 4\r
-SCSI_In_DBx__DB0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__DB0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__DB0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__DB0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__DB0__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__DB1__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB1__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB1__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB1__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB1__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB1__MASK EQU 0x80\r
-SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC7\r
-SCSI_In_DBx__DB1__PORT EQU 2\r
-SCSI_In_DBx__DB1__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB1__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB1__SHIFT EQU 7\r
-SCSI_In_DBx__DB1__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB2__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB2__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB2__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB2__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB2__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB2__MASK EQU 0x40\r
-SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC6\r
-SCSI_In_DBx__DB2__PORT EQU 2\r
-SCSI_In_DBx__DB2__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB2__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB2__SHIFT EQU 6\r
-SCSI_In_DBx__DB2__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB3__MASK EQU 0x20\r
-SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC5\r
-SCSI_In_DBx__DB3__PORT EQU 2\r
-SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB3__SHIFT EQU 5\r
-SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB4__MASK EQU 0x10\r
-SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4\r
-SCSI_In_DBx__DB4__PORT EQU 2\r
-SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB4__SHIFT EQU 4\r
-SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB5__MASK EQU 0x08\r
-SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC3\r
-SCSI_In_DBx__DB5__PORT EQU 2\r
-SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB5__SHIFT EQU 3\r
-SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB6__MASK EQU 0x04\r
-SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC2\r
-SCSI_In_DBx__DB6__PORT EQU 2\r
-SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB6__SHIFT EQU 2\r
-SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB7__MASK EQU 0x02\r
-SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC1\r
-SCSI_In_DBx__DB7__PORT EQU 2\r
-SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB7__SHIFT EQU 1\r
-SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
-\r
-/* SCSI_RX_DMA */\r
-SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SCSI_RX_DMA__DRQ_NUMBER EQU 0\r
-SCSI_RX_DMA__NUMBEROF_TDS EQU 0\r
-SCSI_RX_DMA__PRIORITY EQU 2\r
-SCSI_RX_DMA__TERMIN_EN EQU 0\r
-SCSI_RX_DMA__TERMIN_SEL EQU 0\r
-SCSI_RX_DMA__TERMOUT0_EN EQU 1\r
-SCSI_RX_DMA__TERMOUT0_SEL EQU 0\r
-SCSI_RX_DMA__TERMOUT1_EN EQU 0\r
-SCSI_RX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-/* SCSI_TX_DMA */\r
-SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SCSI_TX_DMA__DRQ_NUMBER EQU 1\r
-SCSI_TX_DMA__NUMBEROF_TDS EQU 0\r
-SCSI_TX_DMA__PRIORITY EQU 2\r
-SCSI_TX_DMA__TERMIN_EN EQU 0\r
-SCSI_TX_DMA__TERMIN_SEL EQU 0\r
-SCSI_TX_DMA__TERMOUT0_EN EQU 1\r
-SCSI_TX_DMA__TERMOUT0_SEL EQU 1\r
-SCSI_TX_DMA__TERMOUT1_EN EQU 0\r
-SCSI_TX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-/* SD_Data_Clk */\r
-SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
-SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
-SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2\r
-SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
-SD_Data_Clk__INDEX EQU 0x00\r
-SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SD_Data_Clk__PM_ACT_MSK EQU 0x01\r
-SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
-\r
-/* timer_clock */\r
-timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0\r
-timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1\r
-timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2\r
-timer_clock__CFG2_SRC_SEL_MASK EQU 0x07\r
-timer_clock__INDEX EQU 0x02\r
-timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-timer_clock__PM_ACT_MSK EQU 0x04\r
-timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-timer_clock__PM_STBY_MSK EQU 0x04\r
-\r
-/* SCSI_Noise */\r
-SCSI_Noise__0__AG EQU CYREG_PRT12_AG\r
-SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE\r
-SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP\r
-SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_Noise__0__DR EQU CYREG_PRT12_DR\r
-SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_Noise__0__MASK EQU 0x20\r
-SCSI_Noise__0__PC EQU CYREG_PRT12_PC5\r
-SCSI_Noise__0__PORT EQU 12\r
-SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT\r
-SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_Noise__0__PS EQU CYREG_PRT12_PS\r
-SCSI_Noise__0__SHIFT EQU 5\r
-SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW\r
-SCSI_Noise__1__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__1__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__1__MASK EQU 0x10\r
-SCSI_Noise__1__PC EQU CYREG_PRT6_PC4\r
-SCSI_Noise__1__PORT EQU 6\r
-SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__1__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__1__SHIFT EQU 4\r
-SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__2__AG EQU CYREG_PRT5_AG\r
-SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE\r
-SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP\r
-SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL\r
-SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_Noise__2__DR EQU CYREG_PRT5_DR\r
-SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_Noise__2__MASK EQU 0x01\r
-SCSI_Noise__2__PC EQU CYREG_PRT5_PC0\r
-SCSI_Noise__2__PORT EQU 5\r
-SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT\r
-SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_Noise__2__PS EQU CYREG_PRT5_PS\r
-SCSI_Noise__2__SHIFT EQU 0\r
-SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW\r
-SCSI_Noise__3__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__3__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__3__MASK EQU 0x40\r
-SCSI_Noise__3__PC EQU CYREG_PRT6_PC6\r
-SCSI_Noise__3__PORT EQU 6\r
-SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__3__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__3__SHIFT EQU 6\r
-SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__4__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__4__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__4__MASK EQU 0x20\r
-SCSI_Noise__4__PC EQU CYREG_PRT6_PC5\r
-SCSI_Noise__4__PORT EQU 6\r
-SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__4__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__4__SHIFT EQU 5\r
-SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__ACK__MASK EQU 0x20\r
-SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5\r
-SCSI_Noise__ACK__PORT EQU 6\r
-SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__ACK__SHIFT EQU 5\r
-SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG\r
-SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE\r
-SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP\r
-SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR\r
-SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_Noise__ATN__MASK EQU 0x20\r
-SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5\r
-SCSI_Noise__ATN__PORT EQU 12\r
-SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT\r
-SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS\r
-SCSI_Noise__ATN__SHIFT EQU 5\r
-SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW\r
-SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__BSY__MASK EQU 0x10\r
-SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4\r
-SCSI_Noise__BSY__PORT EQU 6\r
-SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__BSY__SHIFT EQU 4\r
-SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__RST__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__RST__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__RST__MASK EQU 0x40\r
-SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6\r
-SCSI_Noise__RST__PORT EQU 6\r
-SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__RST__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__RST__SHIFT EQU 6\r
-SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG\r
-SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE\r
-SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP\r
-SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL\r
-SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR\r
-SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_Noise__SEL__MASK EQU 0x01\r
-SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0\r
-SCSI_Noise__SEL__PORT EQU 5\r
-SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT\r
-SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS\r
-SCSI_Noise__SEL__SHIFT EQU 0\r
-SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW\r
-\r
-/* scsiTarget */\r
-scsiTarget_StatusReg__0__MASK EQU 0x01\r
-scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
-scsiTarget_StatusReg__1__MASK EQU 0x02\r
-scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__2__MASK EQU 0x04\r
-scsiTarget_StatusReg__2__POS EQU 2\r
-scsiTarget_StatusReg__3__MASK EQU 0x08\r
-scsiTarget_StatusReg__3__POS EQU 3\r
-scsiTarget_StatusReg__4__MASK EQU 0x10\r
-scsiTarget_StatusReg__4__POS EQU 4\r
-scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST\r
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB01_MSK\r
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB01_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB01_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB01_ST\r
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB01_02_A0\r
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB01_02_A1\r
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB01_02_D0\r
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB01_02_D1\r
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB01_02_F0\r
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB01_02_F1\r
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB01_A0_A1\r
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB01_A0\r
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB01_A1\r
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB01_D0_D1\r
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB01_D0\r
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB01_D1\r
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB01_F0_F1\r
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB01_F0\r
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB01_F1\r
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-\r
-/* USBFS_ep_0 */\r
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_0__INTC_MASK EQU 0x1000000\r
-USBFS_ep_0__INTC_NUMBER EQU 24\r
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24\r
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_1 */\r
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x40\r
-USBFS_ep_1__INTC_NUMBER EQU 6\r
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_2 */\r
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x80\r
-USBFS_ep_2__INTC_NUMBER EQU 7\r
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_3 */\r
-USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_3__INTC_MASK EQU 0x100\r
-USBFS_ep_3__INTC_NUMBER EQU 8\r
-USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
-USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_4 */\r
-USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_4__INTC_MASK EQU 0x200\r
-USBFS_ep_4__INTC_NUMBER EQU 9\r
-USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9\r
-USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SD_RX_DMA */\r
-SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SD_RX_DMA__DRQ_NUMBER EQU 2\r
-SD_RX_DMA__NUMBEROF_TDS EQU 0\r
-SD_RX_DMA__PRIORITY EQU 1\r
-SD_RX_DMA__TERMIN_EN EQU 0\r
-SD_RX_DMA__TERMIN_SEL EQU 0\r
-SD_RX_DMA__TERMOUT0_EN EQU 1\r
-SD_RX_DMA__TERMOUT0_SEL EQU 2\r
-SD_RX_DMA__TERMOUT1_EN EQU 0\r
-SD_RX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-/* SD_TX_DMA */\r
-SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SD_TX_DMA__DRQ_NUMBER EQU 3\r
-SD_TX_DMA__NUMBEROF_TDS EQU 0\r
-SD_TX_DMA__PRIORITY EQU 2\r
-SD_TX_DMA__TERMIN_EN EQU 0\r
-SD_TX_DMA__TERMIN_SEL EQU 0\r
-SD_TX_DMA__TERMOUT0_EN EQU 1\r
-SD_TX_DMA__TERMOUT0_SEL EQU 3\r
-SD_TX_DMA__TERMOUT1_EN EQU 0\r
-SD_TX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-/* USBFS_USB */\r
-USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG\r
-USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG\r
-USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN\r
-USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR\r
-USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG\r
-USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN\r
-USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR\r
-USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG\r
-USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN\r
-USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR\r
-USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG\r
-USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN\r
-USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR\r
-USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG\r
-USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN\r
-USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR\r
-USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG\r
-USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN\r
-USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR\r
-USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG\r
-USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN\r
-USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR\r
-USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG\r
-USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN\r
-USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR\r
-USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN\r
-USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR\r
-USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR\r
-USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA\r
-USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB\r
-USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA\r
-USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB\r
-USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR\r
-USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA\r
-USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB\r
-USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA\r
-USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB\r
-USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR\r
-USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA\r
-USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB\r
-USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA\r
-USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB\r
-USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR\r
-USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA\r
-USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB\r
-USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA\r
-USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB\r
-USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR\r
-USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA\r
-USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB\r
-USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA\r
-USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB\r
-USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR\r
-USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA\r
-USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB\r
-USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA\r
-USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB\r
-USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR\r
-USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA\r
-USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB\r
-USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA\r
-USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB\r
-USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR\r
-USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA\r
-USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB\r
-USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA\r
-USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB\r
-USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE\r
-USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT\r
-USBFS_USB__CR0 EQU CYREG_USB_CR0\r
-USBFS_USB__CR1 EQU CYREG_USB_CR1\r
-USBFS_USB__CWA EQU CYREG_USB_CWA\r
-USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB\r
-USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES\r
-USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB\r
-USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG\r
-USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT\r
-USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR\r
-USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0\r
-USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1\r
-USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2\r
-USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3\r
-USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4\r
-USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5\r
-USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6\r
-USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7\r
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE\r
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE\r
-USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE\r
-USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5\r
-USBFS_USB__PM_ACT_MSK EQU 0x01\r
-USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5\r
-USBFS_USB__PM_STBY_MSK EQU 0x01\r
-USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0\r
-USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1\r
-USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0\r
-USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0\r
-USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1\r
-USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0\r
-USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0\r
-USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1\r
-USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0\r
-USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0\r
-USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1\r
-USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0\r
-USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0\r
-USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1\r
-USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0\r
-USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0\r
-USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1\r
-USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0\r
-USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0\r
-USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1\r
-USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0\r
-USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0\r
-USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1\r
-USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0\r
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN\r
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR\r
-USBFS_USB__SOF0 EQU CYREG_USB_SOF0\r
-USBFS_USB__SOF1 EQU CYREG_USB_SOF1\r
-USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0\r
-USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN\r
-\r
-/* SCSI_CLK */\r
-SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
-SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
-SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
-SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07\r
-SCSI_CLK__INDEX EQU 0x01\r
-SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SCSI_CLK__PM_ACT_MSK EQU 0x02\r
-SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SCSI_CLK__PM_STBY_MSK EQU 0x02\r
-\r
-/* SCSI_Out */\r
-SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__0__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__0__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__0__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__0__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__0__MASK EQU 0x08\r
-SCSI_Out__0__PC EQU CYREG_PRT4_PC3\r
-SCSI_Out__0__PORT EQU 4\r
-SCSI_Out__0__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__0__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__0__SHIFT EQU 3\r
-SCSI_Out__0__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__1__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__1__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__1__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__1__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__1__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__1__MASK EQU 0x04\r
-SCSI_Out__1__PC EQU CYREG_PRT4_PC2\r
-SCSI_Out__1__PORT EQU 4\r
-SCSI_Out__1__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__1__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__1__SHIFT EQU 2\r
-SCSI_Out__1__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__2__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__2__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__2__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__2__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__2__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__2__MASK EQU 0x80\r
-SCSI_Out__2__PC EQU CYREG_PRT0_PC7\r
-SCSI_Out__2__PORT EQU 0\r
-SCSI_Out__2__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__2__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__2__SHIFT EQU 7\r
-SCSI_Out__2__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__3__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__3__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__3__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__3__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__3__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__3__MASK EQU 0x40\r
-SCSI_Out__3__PC EQU CYREG_PRT0_PC6\r
-SCSI_Out__3__PORT EQU 0\r
-SCSI_Out__3__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__3__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__3__SHIFT EQU 6\r
-SCSI_Out__3__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__4__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__4__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__4__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__4__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__4__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__4__MASK EQU 0x20\r
-SCSI_Out__4__PC EQU CYREG_PRT0_PC5\r
-SCSI_Out__4__PORT EQU 0\r
-SCSI_Out__4__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__4__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__4__SHIFT EQU 5\r
-SCSI_Out__4__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__5__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__5__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__5__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__5__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__5__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__5__MASK EQU 0x10\r
-SCSI_Out__5__PC EQU CYREG_PRT0_PC4\r
-SCSI_Out__5__PORT EQU 0\r
-SCSI_Out__5__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__5__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__5__SHIFT EQU 4\r
-SCSI_Out__5__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__6__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__6__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__6__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__6__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__6__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__6__MASK EQU 0x08\r
-SCSI_Out__6__PC EQU CYREG_PRT0_PC3\r
-SCSI_Out__6__PORT EQU 0\r
-SCSI_Out__6__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__6__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__6__SHIFT EQU 3\r
-SCSI_Out__6__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__7__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__7__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__7__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__7__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__7__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__7__MASK EQU 0x04\r
-SCSI_Out__7__PC EQU CYREG_PRT0_PC2\r
-SCSI_Out__7__PORT EQU 0\r
-SCSI_Out__7__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__7__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__7__SHIFT EQU 2\r
-SCSI_Out__7__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__8__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__8__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__8__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__8__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__8__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__8__MASK EQU 0x02\r
-SCSI_Out__8__PC EQU CYREG_PRT0_PC1\r
-SCSI_Out__8__PORT EQU 0\r
-SCSI_Out__8__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__8__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__8__SHIFT EQU 1\r
-SCSI_Out__8__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__9__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__9__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__9__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__9__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__9__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__9__MASK EQU 0x01\r
-SCSI_Out__9__PC EQU CYREG_PRT0_PC0\r
-SCSI_Out__9__PORT EQU 0\r
-SCSI_Out__9__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__9__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__9__SHIFT EQU 0\r
-SCSI_Out__9__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__ACK__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__ACK__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__ACK__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__ACK__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__ACK__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__ACK__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__ACK__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__ACK__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__ACK__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__ACK__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__ACK__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__ACK__MASK EQU 0x40\r
-SCSI_Out__ACK__PC EQU CYREG_PRT0_PC6\r
-SCSI_Out__ACK__PORT EQU 0\r
-SCSI_Out__ACK__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__ACK__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__ACK__SHIFT EQU 6\r
-SCSI_Out__ACK__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__ATN__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__ATN__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__ATN__MASK EQU 0x04\r
-SCSI_Out__ATN__PC EQU CYREG_PRT4_PC2\r
-SCSI_Out__ATN__PORT EQU 4\r
-SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__ATN__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__ATN__SHIFT EQU 2\r
-SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__BSY__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__BSY__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__BSY__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__BSY__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__BSY__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__BSY__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__BSY__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__BSY__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__BSY__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__BSY__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__BSY__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__BSY__MASK EQU 0x80\r
-SCSI_Out__BSY__PC EQU CYREG_PRT0_PC7\r
-SCSI_Out__BSY__PORT EQU 0\r
-SCSI_Out__BSY__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__BSY__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__BSY__SHIFT EQU 7\r
-SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__CD_raw__MASK EQU 0x04\r
-SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2\r
-SCSI_Out__CD_raw__PORT EQU 0\r
-SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__CD_raw__SHIFT EQU 2\r
-SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__DBP_raw__MASK EQU 0x08\r
-SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC3\r
-SCSI_Out__DBP_raw__PORT EQU 4\r
-SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__DBP_raw__SHIFT EQU 3\r
-SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__IO_raw__MASK EQU 0x01\r
-SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC0\r
-SCSI_Out__IO_raw__PORT EQU 0\r
-SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__IO_raw__SHIFT EQU 0\r
-SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__MSG_raw__MASK EQU 0x10\r
-SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4\r
-SCSI_Out__MSG_raw__PORT EQU 0\r
-SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__MSG_raw__SHIFT EQU 4\r
-SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__REQ__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__REQ__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__REQ__MASK EQU 0x02\r
-SCSI_Out__REQ__PC EQU CYREG_PRT0_PC1\r
-SCSI_Out__REQ__PORT EQU 0\r
-SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__REQ__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__REQ__SHIFT EQU 1\r
-SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__RST__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__RST__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__RST__MASK EQU 0x20\r
-SCSI_Out__RST__PC EQU CYREG_PRT0_PC5\r
-SCSI_Out__RST__PORT EQU 0\r
-SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__RST__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__RST__SHIFT EQU 5\r
-SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__SEL__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__SEL__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__SEL__MASK EQU 0x08\r
-SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3\r
-SCSI_Out__SEL__PORT EQU 0\r
-SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__SEL__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__SEL__SHIFT EQU 3\r
-SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
-\r
-/* USBFS_Dm */\r
-USBFS_Dm__0__MASK EQU 0x80\r
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1\r
-USBFS_Dm__0__PORT EQU 15\r
-USBFS_Dm__0__SHIFT EQU 7\r
-USBFS_Dm__AG EQU CYREG_PRT15_AG\r
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX\r
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE\r
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP\r
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL\r
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0\r
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1\r
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2\r
-USBFS_Dm__DR EQU CYREG_PRT15_DR\r
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-USBFS_Dm__MASK EQU 0x80\r
-USBFS_Dm__PORT EQU 15\r
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT\r
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-USBFS_Dm__PS EQU CYREG_PRT15_PS\r
-USBFS_Dm__SHIFT EQU 7\r
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW\r
+/* SDCard_BSPIM */\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
+SDCard_BSPIM_RxStsReg__5__POS EQU 5\r
+SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
+SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
+SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1\r
+SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
+SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
+SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
+SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
+SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
+SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
+SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
+SDCard_BSPIM_TxStsReg__3__POS EQU 3\r
+SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST\r
\r
-/* USBFS_Dp */\r
-USBFS_Dp__0__MASK EQU 0x40\r
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0\r
-USBFS_Dp__0__PORT EQU 15\r
-USBFS_Dp__0__SHIFT EQU 6\r
-USBFS_Dp__AG EQU CYREG_PRT15_AG\r
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX\r
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE\r
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP\r
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL\r
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0\r
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1\r
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2\r
-USBFS_Dp__DR EQU CYREG_PRT15_DR\r
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT\r
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-USBFS_Dp__MASK EQU 0x40\r
-USBFS_Dp__PORT EQU 15\r
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT\r
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-USBFS_Dp__PS EQU CYREG_PRT15_PS\r
-USBFS_Dp__SHIFT EQU 6\r
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW\r
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15\r
+/* SD_SCK */\r
+SD_SCK__0__MASK EQU 0x04\r
+SD_SCK__0__PC EQU CYREG_PRT3_PC2\r
+SD_SCK__0__PORT EQU 3\r
+SD_SCK__0__SHIFT EQU 2\r
+SD_SCK__AG EQU CYREG_PRT3_AG\r
+SD_SCK__AMUX EQU CYREG_PRT3_AMUX\r
+SD_SCK__BIE EQU CYREG_PRT3_BIE\r
+SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_SCK__BYP EQU CYREG_PRT3_BYP\r
+SD_SCK__CTL EQU CYREG_PRT3_CTL\r
+SD_SCK__DM0 EQU CYREG_PRT3_DM0\r
+SD_SCK__DM1 EQU CYREG_PRT3_DM1\r
+SD_SCK__DM2 EQU CYREG_PRT3_DM2\r
+SD_SCK__DR EQU CYREG_PRT3_DR\r
+SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_SCK__MASK EQU 0x04\r
+SD_SCK__PORT EQU 3\r
+SD_SCK__PRT EQU CYREG_PRT3_PRT\r
+SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_SCK__PS EQU CYREG_PRT3_PS\r
+SD_SCK__SHIFT EQU 2\r
+SD_SCK__SLW EQU CYREG_PRT3_SLW\r
\r
/* SCSI_In */\r
SCSI_In__0__AG EQU CYREG_PRT2_AG\r
SCSI_In__REQ__SHIFT EQU 2\r
SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW\r
\r
-/* SD_DAT1 */\r
-SD_DAT1__0__MASK EQU 0x01\r
-SD_DAT1__0__PC EQU CYREG_PRT3_PC0\r
-SD_DAT1__0__PORT EQU 3\r
-SD_DAT1__0__SHIFT EQU 0\r
-SD_DAT1__AG EQU CYREG_PRT3_AG\r
-SD_DAT1__AMUX EQU CYREG_PRT3_AMUX\r
-SD_DAT1__BIE EQU CYREG_PRT3_BIE\r
-SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_DAT1__BYP EQU CYREG_PRT3_BYP\r
-SD_DAT1__CTL EQU CYREG_PRT3_CTL\r
-SD_DAT1__DM0 EQU CYREG_PRT3_DM0\r
-SD_DAT1__DM1 EQU CYREG_PRT3_DM1\r
-SD_DAT1__DM2 EQU CYREG_PRT3_DM2\r
-SD_DAT1__DR EQU CYREG_PRT3_DR\r
-SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_DAT1__MASK EQU 0x01\r
-SD_DAT1__PORT EQU 3\r
-SD_DAT1__PRT EQU CYREG_PRT3_PRT\r
-SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_DAT1__PS EQU CYREG_PRT3_PS\r
-SD_DAT1__SHIFT EQU 0\r
-SD_DAT1__SLW EQU CYREG_PRT3_SLW\r
+/* SCSI_In_DBx */\r
+SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__0__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__0__MASK EQU 0x10\r
+SCSI_In_DBx__0__PC EQU CYREG_PRT12_PC4\r
+SCSI_In_DBx__0__PORT EQU 12\r
+SCSI_In_DBx__0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__0__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__0__SHIFT EQU 4\r
+SCSI_In_DBx__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__1__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__1__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__1__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__1__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__1__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__1__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__1__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__1__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__1__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__1__MASK EQU 0x80\r
+SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC7\r
+SCSI_In_DBx__1__PORT EQU 2\r
+SCSI_In_DBx__1__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__1__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__1__SHIFT EQU 7\r
+SCSI_In_DBx__1__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__2__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__2__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__2__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__2__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__2__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__2__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__2__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__2__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__2__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__2__MASK EQU 0x40\r
+SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC6\r
+SCSI_In_DBx__2__PORT EQU 2\r
+SCSI_In_DBx__2__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__2__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__2__SHIFT EQU 6\r
+SCSI_In_DBx__2__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__3__MASK EQU 0x20\r
+SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__3__PORT EQU 2\r
+SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__3__SHIFT EQU 5\r
+SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__4__MASK EQU 0x10\r
+SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__4__PORT EQU 2\r
+SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__4__SHIFT EQU 4\r
+SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__5__MASK EQU 0x08\r
+SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC3\r
+SCSI_In_DBx__5__PORT EQU 2\r
+SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__5__SHIFT EQU 3\r
+SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__6__MASK EQU 0x04\r
+SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC2\r
+SCSI_In_DBx__6__PORT EQU 2\r
+SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__6__SHIFT EQU 2\r
+SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__7__MASK EQU 0x02\r
+SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC1\r
+SCSI_In_DBx__7__PORT EQU 2\r
+SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__7__SHIFT EQU 1\r
+SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB0__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__DB0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__DB0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__DB0__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__DB0__MASK EQU 0x10\r
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT12_PC4\r
+SCSI_In_DBx__DB0__PORT EQU 12\r
+SCSI_In_DBx__DB0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__DB0__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__DB0__SHIFT EQU 4\r
+SCSI_In_DBx__DB0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__DB0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__DB0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__DB0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__DB0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__DB1__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB1__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB1__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB1__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB1__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB1__MASK EQU 0x80\r
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC7\r
+SCSI_In_DBx__DB1__PORT EQU 2\r
+SCSI_In_DBx__DB1__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB1__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB1__SHIFT EQU 7\r
+SCSI_In_DBx__DB1__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB2__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB2__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB2__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB2__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB2__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB2__MASK EQU 0x40\r
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC6\r
+SCSI_In_DBx__DB2__PORT EQU 2\r
+SCSI_In_DBx__DB2__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB2__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB2__SHIFT EQU 6\r
+SCSI_In_DBx__DB2__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB3__MASK EQU 0x20\r
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__DB3__PORT EQU 2\r
+SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB3__SHIFT EQU 5\r
+SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB4__MASK EQU 0x10\r
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__DB4__PORT EQU 2\r
+SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB4__SHIFT EQU 4\r
+SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB5__MASK EQU 0x08\r
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC3\r
+SCSI_In_DBx__DB5__PORT EQU 2\r
+SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB5__SHIFT EQU 3\r
+SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB6__MASK EQU 0x04\r
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC2\r
+SCSI_In_DBx__DB6__PORT EQU 2\r
+SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB6__SHIFT EQU 2\r
+SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB7__MASK EQU 0x02\r
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC1\r
+SCSI_In_DBx__DB7__PORT EQU 2\r
+SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB7__SHIFT EQU 1\r
+SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
+\r
+/* SD_DAT1 */\r
+SD_DAT1__0__MASK EQU 0x01\r
+SD_DAT1__0__PC EQU CYREG_PRT3_PC0\r
+SD_DAT1__0__PORT EQU 3\r
+SD_DAT1__0__SHIFT EQU 0\r
+SD_DAT1__AG EQU CYREG_PRT3_AG\r
+SD_DAT1__AMUX EQU CYREG_PRT3_AMUX\r
+SD_DAT1__BIE EQU CYREG_PRT3_BIE\r
+SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_DAT1__BYP EQU CYREG_PRT3_BYP\r
+SD_DAT1__CTL EQU CYREG_PRT3_CTL\r
+SD_DAT1__DM0 EQU CYREG_PRT3_DM0\r
+SD_DAT1__DM1 EQU CYREG_PRT3_DM1\r
+SD_DAT1__DM2 EQU CYREG_PRT3_DM2\r
+SD_DAT1__DR EQU CYREG_PRT3_DR\r
+SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_DAT1__MASK EQU 0x01\r
+SD_DAT1__PORT EQU 3\r
+SD_DAT1__PRT EQU CYREG_PRT3_PRT\r
+SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_DAT1__PS EQU CYREG_PRT3_PS\r
+SD_DAT1__SHIFT EQU 0\r
+SD_DAT1__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_DAT2 */\r
+SD_DAT2__0__MASK EQU 0x20\r
+SD_DAT2__0__PC EQU CYREG_PRT3_PC5\r
+SD_DAT2__0__PORT EQU 3\r
+SD_DAT2__0__SHIFT EQU 5\r
+SD_DAT2__AG EQU CYREG_PRT3_AG\r
+SD_DAT2__AMUX EQU CYREG_PRT3_AMUX\r
+SD_DAT2__BIE EQU CYREG_PRT3_BIE\r
+SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_DAT2__BYP EQU CYREG_PRT3_BYP\r
+SD_DAT2__CTL EQU CYREG_PRT3_CTL\r
+SD_DAT2__DM0 EQU CYREG_PRT3_DM0\r
+SD_DAT2__DM1 EQU CYREG_PRT3_DM1\r
+SD_DAT2__DM2 EQU CYREG_PRT3_DM2\r
+SD_DAT2__DR EQU CYREG_PRT3_DR\r
+SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_DAT2__MASK EQU 0x20\r
+SD_DAT2__PORT EQU 3\r
+SD_DAT2__PRT EQU CYREG_PRT3_PRT\r
+SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_DAT2__PS EQU CYREG_PRT3_PS\r
+SD_DAT2__SHIFT EQU 5\r
+SD_DAT2__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_MISO */\r
+SD_MISO__0__MASK EQU 0x02\r
+SD_MISO__0__PC EQU CYREG_PRT3_PC1\r
+SD_MISO__0__PORT EQU 3\r
+SD_MISO__0__SHIFT EQU 1\r
+SD_MISO__AG EQU CYREG_PRT3_AG\r
+SD_MISO__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MISO__BIE EQU CYREG_PRT3_BIE\r
+SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MISO__BYP EQU CYREG_PRT3_BYP\r
+SD_MISO__CTL EQU CYREG_PRT3_CTL\r
+SD_MISO__DM0 EQU CYREG_PRT3_DM0\r
+SD_MISO__DM1 EQU CYREG_PRT3_DM1\r
+SD_MISO__DM2 EQU CYREG_PRT3_DM2\r
+SD_MISO__DR EQU CYREG_PRT3_DR\r
+SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MISO__MASK EQU 0x02\r
+SD_MISO__PORT EQU 3\r
+SD_MISO__PRT EQU CYREG_PRT3_PRT\r
+SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MISO__PS EQU CYREG_PRT3_PS\r
+SD_MISO__SHIFT EQU 1\r
+SD_MISO__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SD_MOSI */\r
+SD_MOSI__0__MASK EQU 0x08\r
+SD_MOSI__0__PC EQU CYREG_PRT3_PC3\r
+SD_MOSI__0__PORT EQU 3\r
+SD_MOSI__0__SHIFT EQU 3\r
+SD_MOSI__AG EQU CYREG_PRT3_AG\r
+SD_MOSI__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MOSI__BIE EQU CYREG_PRT3_BIE\r
+SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MOSI__BYP EQU CYREG_PRT3_BYP\r
+SD_MOSI__CTL EQU CYREG_PRT3_CTL\r
+SD_MOSI__DM0 EQU CYREG_PRT3_DM0\r
+SD_MOSI__DM1 EQU CYREG_PRT3_DM1\r
+SD_MOSI__DM2 EQU CYREG_PRT3_DM2\r
+SD_MOSI__DR EQU CYREG_PRT3_DR\r
+SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MOSI__MASK EQU 0x08\r
+SD_MOSI__PORT EQU 3\r
+SD_MOSI__PRT EQU CYREG_PRT3_PRT\r
+SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MOSI__PS EQU CYREG_PRT3_PS\r
+SD_MOSI__SHIFT EQU 3\r
+SD_MOSI__SLW EQU CYREG_PRT3_SLW\r
+\r
+/* SCSI_CLK */\r
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07\r
+SCSI_CLK__INDEX EQU 0x01\r
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SCSI_CLK__PM_ACT_MSK EQU 0x02\r
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SCSI_CLK__PM_STBY_MSK EQU 0x02\r
+\r
+/* SCSI_Out */\r
+SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__0__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__0__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__0__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__0__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__0__MASK EQU 0x08\r
+SCSI_Out__0__PC EQU CYREG_PRT4_PC3\r
+SCSI_Out__0__PORT EQU 4\r
+SCSI_Out__0__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__0__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__0__SHIFT EQU 3\r
+SCSI_Out__0__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__1__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__1__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__1__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__1__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__1__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__1__MASK EQU 0x04\r
+SCSI_Out__1__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__1__PORT EQU 4\r
+SCSI_Out__1__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__1__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__1__SHIFT EQU 2\r
+SCSI_Out__1__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__2__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__2__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__2__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__2__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__2__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__2__MASK EQU 0x80\r
+SCSI_Out__2__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out__2__PORT EQU 0\r
+SCSI_Out__2__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__2__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__2__SHIFT EQU 7\r
+SCSI_Out__2__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__3__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__3__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__3__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__3__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__3__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__3__MASK EQU 0x40\r
+SCSI_Out__3__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out__3__PORT EQU 0\r
+SCSI_Out__3__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__3__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__3__SHIFT EQU 6\r
+SCSI_Out__3__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__4__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__4__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__4__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__4__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__4__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__4__MASK EQU 0x20\r
+SCSI_Out__4__PC EQU CYREG_PRT0_PC5\r
+SCSI_Out__4__PORT EQU 0\r
+SCSI_Out__4__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__4__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__4__SHIFT EQU 5\r
+SCSI_Out__4__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__5__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__5__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__5__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__5__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__5__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__5__MASK EQU 0x10\r
+SCSI_Out__5__PC EQU CYREG_PRT0_PC4\r
+SCSI_Out__5__PORT EQU 0\r
+SCSI_Out__5__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__5__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__5__SHIFT EQU 4\r
+SCSI_Out__5__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__6__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__6__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__6__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__6__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__6__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__6__MASK EQU 0x08\r
+SCSI_Out__6__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out__6__PORT EQU 0\r
+SCSI_Out__6__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__6__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__6__SHIFT EQU 3\r
+SCSI_Out__6__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__7__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__7__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__7__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__7__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__7__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__7__MASK EQU 0x04\r
+SCSI_Out__7__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out__7__PORT EQU 0\r
+SCSI_Out__7__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__7__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__7__SHIFT EQU 2\r
+SCSI_Out__7__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__8__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__8__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__8__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__8__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__8__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__8__MASK EQU 0x02\r
+SCSI_Out__8__PC EQU CYREG_PRT0_PC1\r
+SCSI_Out__8__PORT EQU 0\r
+SCSI_Out__8__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__8__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__8__SHIFT EQU 1\r
+SCSI_Out__8__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__9__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__9__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__9__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__9__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__9__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__9__MASK EQU 0x01\r
+SCSI_Out__9__PC EQU CYREG_PRT0_PC0\r
+SCSI_Out__9__PORT EQU 0\r
+SCSI_Out__9__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__9__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__9__SHIFT EQU 0\r
+SCSI_Out__9__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__ACK__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__ACK__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__ACK__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__ACK__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__ACK__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__ACK__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__ACK__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__ACK__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__ACK__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__ACK__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__ACK__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__ACK__MASK EQU 0x40\r
+SCSI_Out__ACK__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out__ACK__PORT EQU 0\r
+SCSI_Out__ACK__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__ACK__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__ACK__SHIFT EQU 6\r
+SCSI_Out__ACK__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__ATN__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__ATN__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__ATN__MASK EQU 0x04\r
+SCSI_Out__ATN__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__ATN__PORT EQU 4\r
+SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__ATN__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__ATN__SHIFT EQU 2\r
+SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__BSY__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__BSY__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__BSY__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__BSY__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__BSY__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__BSY__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__BSY__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__BSY__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__BSY__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__BSY__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__BSY__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__BSY__MASK EQU 0x80\r
+SCSI_Out__BSY__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out__BSY__PORT EQU 0\r
+SCSI_Out__BSY__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__BSY__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__BSY__SHIFT EQU 7\r
+SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__CD_raw__MASK EQU 0x04\r
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out__CD_raw__PORT EQU 0\r
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__CD_raw__SHIFT EQU 2\r
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__DBP_raw__MASK EQU 0x08\r
+SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC3\r
+SCSI_Out__DBP_raw__PORT EQU 4\r
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__DBP_raw__SHIFT EQU 3\r
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__IO_raw__MASK EQU 0x01\r
+SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC0\r
+SCSI_Out__IO_raw__PORT EQU 0\r
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__IO_raw__SHIFT EQU 0\r
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__MSG_raw__MASK EQU 0x10\r
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4\r
+SCSI_Out__MSG_raw__PORT EQU 0\r
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__MSG_raw__SHIFT EQU 4\r
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__REQ__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__REQ__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__REQ__MASK EQU 0x02\r
+SCSI_Out__REQ__PC EQU CYREG_PRT0_PC1\r
+SCSI_Out__REQ__PORT EQU 0\r
+SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__REQ__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__REQ__SHIFT EQU 1\r
+SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__RST__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__RST__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__RST__MASK EQU 0x20\r
+SCSI_Out__RST__PC EQU CYREG_PRT0_PC5\r
+SCSI_Out__RST__PORT EQU 0\r
+SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__RST__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__RST__SHIFT EQU 5\r
+SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__SEL__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__SEL__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__SEL__MASK EQU 0x08\r
+SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out__SEL__PORT EQU 0\r
+SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__SEL__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__SEL__SHIFT EQU 3\r
+SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
+\r
+/* SCSI_Out_Bits */\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+\r
+/* SCSI_Out_Ctl */\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK\r
+\r
+/* SCSI_Out_DBx */\r
+SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__0__MASK EQU 0x08\r
+SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out_DBx__0__PORT EQU 6\r
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__0__SHIFT EQU 3\r
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__1__MASK EQU 0x04\r
+SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out_DBx__1__PORT EQU 6\r
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__1__SHIFT EQU 2\r
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__2__MASK EQU 0x02\r
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out_DBx__2__PORT EQU 6\r
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__2__SHIFT EQU 1\r
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__3__MASK EQU 0x01\r
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out_DBx__3__PORT EQU 6\r
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__3__SHIFT EQU 0\r
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__4__MASK EQU 0x80\r
+SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out_DBx__4__PORT EQU 4\r
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__4__SHIFT EQU 7\r
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__5__MASK EQU 0x40\r
+SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out_DBx__5__PORT EQU 4\r
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__5__SHIFT EQU 6\r
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__6__MASK EQU 0x20\r
+SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out_DBx__6__PORT EQU 4\r
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__6__SHIFT EQU 5\r
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__7__MASK EQU 0x10\r
+SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out_DBx__7__PORT EQU 4\r
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__7__SHIFT EQU 4\r
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB0__MASK EQU 0x08\r
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out_DBx__DB0__PORT EQU 6\r
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB0__SHIFT EQU 3\r
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB1__MASK EQU 0x04\r
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out_DBx__DB1__PORT EQU 6\r
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB1__SHIFT EQU 2\r
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB2__MASK EQU 0x02\r
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out_DBx__DB2__PORT EQU 6\r
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB2__SHIFT EQU 1\r
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB3__MASK EQU 0x01\r
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out_DBx__DB3__PORT EQU 6\r
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB3__SHIFT EQU 0\r
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB4__MASK EQU 0x80\r
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out_DBx__DB4__PORT EQU 4\r
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB4__SHIFT EQU 7\r
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB5__MASK EQU 0x40\r
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out_DBx__DB5__PORT EQU 4\r
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB5__SHIFT EQU 6\r
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB6__MASK EQU 0x20\r
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out_DBx__DB6__PORT EQU 4\r
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB6__SHIFT EQU 5\r
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB7__MASK EQU 0x10\r
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out_DBx__DB7__PORT EQU 4\r
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB7__SHIFT EQU 4\r
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW\r
+\r
+/* SD_RX_DMA */\r
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_RX_DMA__DRQ_NUMBER EQU 2\r
+SD_RX_DMA__NUMBEROF_TDS EQU 0\r
+SD_RX_DMA__PRIORITY EQU 2\r
+SD_RX_DMA__TERMIN_EN EQU 0\r
+SD_RX_DMA__TERMIN_SEL EQU 0\r
+SD_RX_DMA__TERMOUT0_EN EQU 1\r
+SD_RX_DMA__TERMOUT0_SEL EQU 2\r
+SD_RX_DMA__TERMOUT1_EN EQU 0\r
+SD_RX_DMA__TERMOUT1_SEL EQU 0\r
+\r
+/* SD_RX_DMA_COMPLETE */\r
+SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
+SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SD_TX_DMA */\r
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_TX_DMA__DRQ_NUMBER EQU 3\r
+SD_TX_DMA__NUMBEROF_TDS EQU 0\r
+SD_TX_DMA__PRIORITY EQU 2\r
+SD_TX_DMA__TERMIN_EN EQU 0\r
+SD_TX_DMA__TERMIN_SEL EQU 0\r
+SD_TX_DMA__TERMOUT0_EN EQU 1\r
+SD_TX_DMA__TERMOUT0_SEL EQU 3\r
+SD_TX_DMA__TERMOUT1_EN EQU 0\r
+SD_TX_DMA__TERMOUT1_SEL EQU 0\r
+\r
+/* SD_TX_DMA_COMPLETE */\r
+SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
+SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_Noise */\r
+SCSI_Noise__0__AG EQU CYREG_PRT12_AG\r
+SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_Noise__0__DR EQU CYREG_PRT12_DR\r
+SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_Noise__0__MASK EQU 0x20\r
+SCSI_Noise__0__PC EQU CYREG_PRT12_PC5\r
+SCSI_Noise__0__PORT EQU 12\r
+SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_Noise__0__PS EQU CYREG_PRT12_PS\r
+SCSI_Noise__0__SHIFT EQU 5\r
+SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_Noise__1__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__1__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__1__MASK EQU 0x10\r
+SCSI_Noise__1__PC EQU CYREG_PRT6_PC4\r
+SCSI_Noise__1__PORT EQU 6\r
+SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__1__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__1__SHIFT EQU 4\r
+SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__2__AG EQU CYREG_PRT5_AG\r
+SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Noise__2__DR EQU CYREG_PRT5_DR\r
+SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Noise__2__MASK EQU 0x01\r
+SCSI_Noise__2__PC EQU CYREG_PRT5_PC0\r
+SCSI_Noise__2__PORT EQU 5\r
+SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Noise__2__PS EQU CYREG_PRT5_PS\r
+SCSI_Noise__2__SHIFT EQU 0\r
+SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW\r
+SCSI_Noise__3__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__3__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__3__MASK EQU 0x40\r
+SCSI_Noise__3__PC EQU CYREG_PRT6_PC6\r
+SCSI_Noise__3__PORT EQU 6\r
+SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__3__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__3__SHIFT EQU 6\r
+SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__4__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__4__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__4__MASK EQU 0x20\r
+SCSI_Noise__4__PC EQU CYREG_PRT6_PC5\r
+SCSI_Noise__4__PORT EQU 6\r
+SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__4__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__4__SHIFT EQU 5\r
+SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__ACK__MASK EQU 0x20\r
+SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5\r
+SCSI_Noise__ACK__PORT EQU 6\r
+SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__ACK__SHIFT EQU 5\r
+SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG\r
+SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE\r
+SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP\r
+SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR\r
+SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_Noise__ATN__MASK EQU 0x20\r
+SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5\r
+SCSI_Noise__ATN__PORT EQU 12\r
+SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT\r
+SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS\r
+SCSI_Noise__ATN__SHIFT EQU 5\r
+SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW\r
+SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__BSY__MASK EQU 0x10\r
+SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4\r
+SCSI_Noise__BSY__PORT EQU 6\r
+SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__BSY__SHIFT EQU 4\r
+SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__RST__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__RST__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__RST__MASK EQU 0x40\r
+SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6\r
+SCSI_Noise__RST__PORT EQU 6\r
+SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__RST__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__RST__SHIFT EQU 6\r
+SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG\r
+SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR\r
+SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Noise__SEL__MASK EQU 0x01\r
+SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0\r
+SCSI_Noise__SEL__PORT EQU 5\r
+SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS\r
+SCSI_Noise__SEL__SHIFT EQU 0\r
+SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW\r
+\r
+/* scsiTarget */\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB05_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB05_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB05_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB05_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB05_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB05_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
+scsiTarget_StatusReg__0__MASK EQU 0x01\r
+scsiTarget_StatusReg__0__POS EQU 0\r
+scsiTarget_StatusReg__1__MASK EQU 0x02\r
+scsiTarget_StatusReg__1__POS EQU 1\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
+scsiTarget_StatusReg__2__MASK EQU 0x04\r
+scsiTarget_StatusReg__2__POS EQU 2\r
+scsiTarget_StatusReg__3__MASK EQU 0x08\r
+scsiTarget_StatusReg__3__POS EQU 3\r
+scsiTarget_StatusReg__4__MASK EQU 0x10\r
+scsiTarget_StatusReg__4__POS EQU 4\r
+scsiTarget_StatusReg__MASK EQU 0x1F\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL\r
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
\r
-/* SD_DAT2 */\r
-SD_DAT2__0__MASK EQU 0x20\r
-SD_DAT2__0__PC EQU CYREG_PRT3_PC5\r
-SD_DAT2__0__PORT EQU 3\r
-SD_DAT2__0__SHIFT EQU 5\r
-SD_DAT2__AG EQU CYREG_PRT3_AG\r
-SD_DAT2__AMUX EQU CYREG_PRT3_AMUX\r
-SD_DAT2__BIE EQU CYREG_PRT3_BIE\r
-SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_DAT2__BYP EQU CYREG_PRT3_BYP\r
-SD_DAT2__CTL EQU CYREG_PRT3_CTL\r
-SD_DAT2__DM0 EQU CYREG_PRT3_DM0\r
-SD_DAT2__DM1 EQU CYREG_PRT3_DM1\r
-SD_DAT2__DM2 EQU CYREG_PRT3_DM2\r
-SD_DAT2__DR EQU CYREG_PRT3_DR\r
-SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_DAT2__MASK EQU 0x20\r
-SD_DAT2__PORT EQU 3\r
-SD_DAT2__PRT EQU CYREG_PRT3_PRT\r
-SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_DAT2__PS EQU CYREG_PRT3_PS\r
-SD_DAT2__SHIFT EQU 5\r
-SD_DAT2__SLW EQU CYREG_PRT3_SLW\r
+/* Debug_Timer_Interrupt */\r
+Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+Debug_Timer_Interrupt__INTC_MASK EQU 0x02\r
+Debug_Timer_Interrupt__INTC_NUMBER EQU 1\r
+Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
+Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
-/* SD_MISO */\r
-SD_MISO__0__MASK EQU 0x02\r
-SD_MISO__0__PC EQU CYREG_PRT3_PC1\r
-SD_MISO__0__PORT EQU 3\r
-SD_MISO__0__SHIFT EQU 1\r
-SD_MISO__AG EQU CYREG_PRT3_AG\r
-SD_MISO__AMUX EQU CYREG_PRT3_AMUX\r
-SD_MISO__BIE EQU CYREG_PRT3_BIE\r
-SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_MISO__BYP EQU CYREG_PRT3_BYP\r
-SD_MISO__CTL EQU CYREG_PRT3_CTL\r
-SD_MISO__DM0 EQU CYREG_PRT3_DM0\r
-SD_MISO__DM1 EQU CYREG_PRT3_DM1\r
-SD_MISO__DM2 EQU CYREG_PRT3_DM2\r
-SD_MISO__DR EQU CYREG_PRT3_DR\r
-SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_MISO__MASK EQU 0x02\r
-SD_MISO__PORT EQU 3\r
-SD_MISO__PRT EQU CYREG_PRT3_PRT\r
-SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_MISO__PS EQU CYREG_PRT3_PS\r
-SD_MISO__SHIFT EQU 1\r
-SD_MISO__SLW EQU CYREG_PRT3_SLW\r
+/* Debug_Timer_TimerHW */\r
+Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
+Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
+Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
+Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
+Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
+Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
+Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
+Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
+Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
+Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
+Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01\r
+Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
+Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01\r
+Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
+Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
+Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
+\r
+/* SCSI_RX_DMA */\r
+SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_RX_DMA__DRQ_NUMBER EQU 0\r
+SCSI_RX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_RX_DMA__PRIORITY EQU 2\r
+SCSI_RX_DMA__TERMIN_EN EQU 0\r
+SCSI_RX_DMA__TERMIN_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_RX_DMA__TERMOUT0_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_RX_DMA__TERMOUT1_SEL EQU 0\r
+\r
+/* SCSI_RX_DMA_COMPLETE */\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01\r
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_TX_DMA */\r
+SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_TX_DMA__DRQ_NUMBER EQU 1\r
+SCSI_TX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_TX_DMA__PRIORITY EQU 2\r
+SCSI_TX_DMA__TERMIN_EN EQU 0\r
+SCSI_TX_DMA__TERMIN_SEL EQU 0\r
+SCSI_TX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_TX_DMA__TERMOUT0_SEL EQU 1\r
+SCSI_TX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_TX_DMA__TERMOUT1_SEL EQU 0\r
+\r
+/* SCSI_TX_DMA_COMPLETE */\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08\r
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* SD_Data_Clk */\r
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2\r
+SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
+SD_Data_Clk__INDEX EQU 0x00\r
+SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SD_Data_Clk__PM_ACT_MSK EQU 0x01\r
+SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
\r
-/* SD_MOSI */\r
-SD_MOSI__0__MASK EQU 0x08\r
-SD_MOSI__0__PC EQU CYREG_PRT3_PC3\r
-SD_MOSI__0__PORT EQU 3\r
-SD_MOSI__0__SHIFT EQU 3\r
-SD_MOSI__AG EQU CYREG_PRT3_AG\r
-SD_MOSI__AMUX EQU CYREG_PRT3_AMUX\r
-SD_MOSI__BIE EQU CYREG_PRT3_BIE\r
-SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_MOSI__BYP EQU CYREG_PRT3_BYP\r
-SD_MOSI__CTL EQU CYREG_PRT3_CTL\r
-SD_MOSI__DM0 EQU CYREG_PRT3_DM0\r
-SD_MOSI__DM1 EQU CYREG_PRT3_DM1\r
-SD_MOSI__DM2 EQU CYREG_PRT3_DM2\r
-SD_MOSI__DR EQU CYREG_PRT3_DR\r
-SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_MOSI__MASK EQU 0x08\r
-SD_MOSI__PORT EQU 3\r
-SD_MOSI__PRT EQU CYREG_PRT3_PRT\r
-SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_MOSI__PS EQU CYREG_PRT3_PS\r
-SD_MOSI__SHIFT EQU 3\r
-SD_MOSI__SLW EQU CYREG_PRT3_SLW\r
+/* timer_clock */\r
+timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0\r
+timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1\r
+timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2\r
+timer_clock__CFG2_SRC_SEL_MASK EQU 0x07\r
+timer_clock__INDEX EQU 0x02\r
+timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+timer_clock__PM_ACT_MSK EQU 0x04\r
+timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+timer_clock__PM_STBY_MSK EQU 0x04\r
\r
-/* SD_SCK */\r
-SD_SCK__0__MASK EQU 0x04\r
-SD_SCK__0__PC EQU CYREG_PRT3_PC2\r
-SD_SCK__0__PORT EQU 3\r
-SD_SCK__0__SHIFT EQU 2\r
-SD_SCK__AG EQU CYREG_PRT3_AG\r
-SD_SCK__AMUX EQU CYREG_PRT3_AMUX\r
-SD_SCK__BIE EQU CYREG_PRT3_BIE\r
-SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_SCK__BYP EQU CYREG_PRT3_BYP\r
-SD_SCK__CTL EQU CYREG_PRT3_CTL\r
-SD_SCK__DM0 EQU CYREG_PRT3_DM0\r
-SD_SCK__DM1 EQU CYREG_PRT3_DM1\r
-SD_SCK__DM2 EQU CYREG_PRT3_DM2\r
-SD_SCK__DR EQU CYREG_PRT3_DR\r
-SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_SCK__MASK EQU 0x04\r
-SD_SCK__PORT EQU 3\r
-SD_SCK__PRT EQU CYREG_PRT3_PRT\r
-SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_SCK__PS EQU CYREG_PRT3_PS\r
-SD_SCK__SHIFT EQU 2\r
-SD_SCK__SLW EQU CYREG_PRT3_SLW\r
+/* SCSI_RST_ISR */\r
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RST_ISR__INTC_MASK EQU 0x04\r
+SCSI_RST_ISR__INTC_NUMBER EQU 2\r
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
-/* SD_CD */\r
-SD_CD__0__MASK EQU 0x40\r
-SD_CD__0__PC EQU CYREG_PRT3_PC6\r
-SD_CD__0__PORT EQU 3\r
-SD_CD__0__SHIFT EQU 6\r
-SD_CD__AG EQU CYREG_PRT3_AG\r
-SD_CD__AMUX EQU CYREG_PRT3_AMUX\r
-SD_CD__BIE EQU CYREG_PRT3_BIE\r
-SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_CD__BYP EQU CYREG_PRT3_BYP\r
-SD_CD__CTL EQU CYREG_PRT3_CTL\r
-SD_CD__DM0 EQU CYREG_PRT3_DM0\r
-SD_CD__DM1 EQU CYREG_PRT3_DM1\r
-SD_CD__DM2 EQU CYREG_PRT3_DM2\r
-SD_CD__DR EQU CYREG_PRT3_DR\r
-SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_CD__MASK EQU 0x40\r
-SD_CD__PORT EQU 3\r
-SD_CD__PRT EQU CYREG_PRT3_PRT\r
-SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_CD__PS EQU CYREG_PRT3_PS\r
-SD_CD__SHIFT EQU 6\r
-SD_CD__SLW EQU CYREG_PRT3_SLW\r
+/* SCSI_Filtered */\r
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3\r
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
+SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
\r
-/* SD_CS */\r
-SD_CS__0__MASK EQU 0x10\r
-SD_CS__0__PC EQU CYREG_PRT3_PC4\r
-SD_CS__0__PORT EQU 3\r
-SD_CS__0__SHIFT EQU 4\r
-SD_CS__AG EQU CYREG_PRT3_AG\r
-SD_CS__AMUX EQU CYREG_PRT3_AMUX\r
-SD_CS__BIE EQU CYREG_PRT3_BIE\r
-SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_CS__BYP EQU CYREG_PRT3_BYP\r
-SD_CS__CTL EQU CYREG_PRT3_CTL\r
-SD_CS__DM0 EQU CYREG_PRT3_DM0\r
-SD_CS__DM1 EQU CYREG_PRT3_DM1\r
-SD_CS__DM2 EQU CYREG_PRT3_DM2\r
-SD_CS__DR EQU CYREG_PRT3_DR\r
-SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_CS__MASK EQU 0x10\r
-SD_CS__PORT EQU 3\r
-SD_CS__PRT EQU CYREG_PRT3_PRT\r
-SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_CS__PS EQU CYREG_PRT3_PS\r
-SD_CS__SHIFT EQU 4\r
-SD_CS__SLW EQU CYREG_PRT3_SLW\r
+/* SCSI_CTL_PHASE */\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
\r
-/* LED1 */\r
-LED1__0__MASK EQU 0x08\r
-LED1__0__PC EQU CYREG_PRT12_PC3\r
-LED1__0__PORT EQU 12\r
-LED1__0__SHIFT EQU 3\r
-LED1__AG EQU CYREG_PRT12_AG\r
-LED1__BIE EQU CYREG_PRT12_BIE\r
-LED1__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-LED1__BYP EQU CYREG_PRT12_BYP\r
-LED1__DM0 EQU CYREG_PRT12_DM0\r
-LED1__DM1 EQU CYREG_PRT12_DM1\r
-LED1__DM2 EQU CYREG_PRT12_DM2\r
-LED1__DR EQU CYREG_PRT12_DR\r
-LED1__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-LED1__MASK EQU 0x08\r
-LED1__PORT EQU 12\r
-LED1__PRT EQU CYREG_PRT12_PRT\r
-LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-LED1__PS EQU CYREG_PRT12_PS\r
-LED1__SHIFT EQU 3\r
-LED1__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-LED1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-LED1__SLW EQU CYREG_PRT12_SLW\r
+/* SCSI_Parity_Error */\r
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
\r
/* Miscellaneous */\r
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */\r
-CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6\r
-CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0\r
-CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0\r
-CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1\r
-CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0\r
-CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
-CYDEV_CHIP_MEMBER_5B EQU 4\r
-CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
-CYDEV_CHIP_DIE_PSOC5LP EQU 4\r
-CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP\r
BCLK__BUS_CLK__HZ EQU 50000000\r
BCLK__BUS_CLK__KHZ EQU 50000\r
BCLK__BUS_CLK__MHZ EQU 50\r
-CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT\r
CYDEV_CHIP_DIE_LEOPARD EQU 1\r
-CYDEV_CHIP_DIE_PANTHER EQU 3\r
-CYDEV_CHIP_DIE_PSOC4A EQU 2\r
+CYDEV_CHIP_DIE_PANTHER EQU 6\r
+CYDEV_CHIP_DIE_PSOC4A EQU 3\r
+CYDEV_CHIP_DIE_PSOC5LP EQU 5\r
CYDEV_CHIP_DIE_UNKNOWN EQU 0\r
CYDEV_CHIP_FAMILY_PSOC3 EQU 1\r
CYDEV_CHIP_FAMILY_PSOC4 EQU 2\r
+CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0\r
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5\r
CYDEV_CHIP_JTAG_ID EQU 0x2E133069\r
CYDEV_CHIP_MEMBER_3A EQU 1\r
-CYDEV_CHIP_MEMBER_4A EQU 2\r
-CYDEV_CHIP_MEMBER_5A EQU 3\r
+CYDEV_CHIP_MEMBER_4A EQU 3\r
+CYDEV_CHIP_MEMBER_4D EQU 2\r
+CYDEV_CHIP_MEMBER_4F EQU 4\r
+CYDEV_CHIP_MEMBER_5A EQU 6\r
+CYDEV_CHIP_MEMBER_5B EQU 5\r
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0\r
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B\r
+CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED\r
+CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT\r
+CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0\r
+CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1\r
+CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3\r
+CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3\r
+CYDEV_CHIP_REV_PANTHER_ES0 EQU 0\r
+CYDEV_CHIP_REV_PANTHER_ES1 EQU 1\r
+CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1\r
+CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17\r
+CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17\r
+CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0\r
+CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_3A_ES1 EQU 0\r
CYDEV_CHIP_REVISION_3A_ES2 EQU 1\r
CYDEV_CHIP_REVISION_3A_ES3 EQU 3\r
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3\r
CYDEV_CHIP_REVISION_4A_ES0 EQU 17\r
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17\r
+CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_5A_ES0 EQU 0\r
CYDEV_CHIP_REVISION_5A_ES1 EQU 1\r
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1\r
CYDEV_CHIP_REVISION_5B_ES0 EQU 0\r
+CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION\r
-CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION\r
-CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0\r
-CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1\r
-CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3\r
-CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3\r
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0\r
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1\r
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1\r
-CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17\r
-CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17\r
-CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0\r
+CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED\r
+CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1\r
+CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0\r
+CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
+CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1\r
+CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2\r
CYDEV_CONFIGURATION_COMPRESSED EQU 1\r
CYDEV_CONFIGURATION_DMA EQU 0\r
CYDEV_CONFIGURATION_ECC EQU 0\r
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED\r
+CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0\r
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED\r
CYDEV_CONFIGURATION_MODE_DMA EQU 2\r
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1\r
-CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
-CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1\r
-CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2\r
-CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV\r
+CYDEV_DEBUG_ENABLE_MASK EQU 0x20\r
+CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG\r
CYDEV_DEBUGGING_DPS_Disable EQU 3\r
CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1\r
CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0\r
CYDEV_DEBUGGING_DPS_SWD EQU 2\r
+CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6\r
+CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV\r
CYDEV_DEBUGGING_ENABLE EQU 1\r
CYDEV_DEBUGGING_XRES EQU 0\r
-CYDEV_DEBUG_ENABLE_MASK EQU 0x20\r
-CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG\r
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24\r
CYDEV_ECC_ENABLE EQU 0\r
CYDEV_HEAP_SIZE EQU 0x0400\r
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3\r
CYDEV_PROJ_TYPE_STANDARD EQU 0\r
CYDEV_PROTECTION_ENABLE EQU 0\r
-CYDEV_STACK_SIZE EQU 0x2000\r
+CYDEV_STACK_SIZE EQU 0x1000\r
CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1\r
CYDEV_USE_BUNDLED_CMSIS EQU 1\r
CYDEV_VARIABLE_VDDA EQU 0\r
CYDEV_VDDIO1_MV EQU 5000\r
CYDEV_VDDIO2_MV EQU 5000\r
CYDEV_VDDIO3_MV EQU 3300\r
-CYDEV_VIO0 EQU 5\r
CYDEV_VIO0_MV EQU 5000\r
-CYDEV_VIO1 EQU 5\r
CYDEV_VIO1_MV EQU 5000\r
-CYDEV_VIO2 EQU 5\r
CYDEV_VIO2_MV EQU 5000\r
CYDEV_VIO3_MV EQU 3300\r
+CYIPBLOCK_ARM_CM3_VERSION EQU 0\r
+CYIPBLOCK_P3_ANAIF_VERSION EQU 0\r
+CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0\r
+CYIPBLOCK_P3_COMP_VERSION EQU 0\r
+CYIPBLOCK_P3_DMA_VERSION EQU 0\r
+CYIPBLOCK_P3_DRQ_VERSION EQU 0\r
+CYIPBLOCK_P3_EMIF_VERSION EQU 0\r
+CYIPBLOCK_P3_I2C_VERSION EQU 0\r
+CYIPBLOCK_P3_LCD_VERSION EQU 0\r
+CYIPBLOCK_P3_LPF_VERSION EQU 0\r
+CYIPBLOCK_P3_PM_VERSION EQU 0\r
+CYIPBLOCK_P3_TIMER_VERSION EQU 0\r
+CYIPBLOCK_P3_USB_VERSION EQU 0\r
+CYIPBLOCK_P3_VIDAC_VERSION EQU 0\r
+CYIPBLOCK_P3_VREF_VERSION EQU 0\r
+CYIPBLOCK_S8_GPIO_VERSION EQU 0\r
+CYIPBLOCK_S8_IRQ_VERSION EQU 0\r
+CYIPBLOCK_S8_SAR_VERSION EQU 0\r
+CYIPBLOCK_S8_SIO_VERSION EQU 0\r
+CYIPBLOCK_S8_UDB_VERSION EQU 0\r
DMA_CHANNELS_USED__MASK0 EQU 0x0000000F\r
CYDEV_BOOTLOADER_ENABLE EQU 0\r
\r
GET cydevicerv.inc\r
GET cydevicerv_trm.inc\r
\r
-; Debug_Timer_Interrupt\r
-Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-Debug_Timer_Interrupt__INTC_MASK EQU 0x02\r
-Debug_Timer_Interrupt__INTC_NUMBER EQU 1\r
-Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
-Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
-Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SCSI_RX_DMA_COMPLETE\r
-SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01\r
-SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0\r
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
-SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SCSI_TX_DMA_COMPLETE\r
-SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08\r
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
-SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; Debug_Timer_TimerHW\r
-Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
-Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
-Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
-Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
-Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
-Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
-Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
-Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
-Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
-Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
-Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01\r
-Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
-Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01\r
-Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
-Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
-Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
+; LED1\r
+LED1__0__MASK EQU 0x08\r
+LED1__0__PC EQU CYREG_PRT12_PC3\r
+LED1__0__PORT EQU 12\r
+LED1__0__SHIFT EQU 3\r
+LED1__AG EQU CYREG_PRT12_AG\r
+LED1__BIE EQU CYREG_PRT12_BIE\r
+LED1__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+LED1__BYP EQU CYREG_PRT12_BYP\r
+LED1__DM0 EQU CYREG_PRT12_DM0\r
+LED1__DM1 EQU CYREG_PRT12_DM1\r
+LED1__DM2 EQU CYREG_PRT12_DM2\r
+LED1__DR EQU CYREG_PRT12_DR\r
+LED1__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+LED1__MASK EQU 0x08\r
+LED1__PORT EQU 12\r
+LED1__PRT EQU CYREG_PRT12_PRT\r
+LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+LED1__PS EQU CYREG_PRT12_PS\r
+LED1__SHIFT EQU 3\r
+LED1__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+LED1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+LED1__SLW EQU CYREG_PRT12_SLW\r
\r
-; SD_RX_DMA_COMPLETE\r
-SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
-SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+; SD_CD\r
+SD_CD__0__MASK EQU 0x40\r
+SD_CD__0__PC EQU CYREG_PRT3_PC6\r
+SD_CD__0__PORT EQU 3\r
+SD_CD__0__SHIFT EQU 6\r
+SD_CD__AG EQU CYREG_PRT3_AG\r
+SD_CD__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CD__BIE EQU CYREG_PRT3_BIE\r
+SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CD__BYP EQU CYREG_PRT3_BYP\r
+SD_CD__CTL EQU CYREG_PRT3_CTL\r
+SD_CD__DM0 EQU CYREG_PRT3_DM0\r
+SD_CD__DM1 EQU CYREG_PRT3_DM1\r
+SD_CD__DM2 EQU CYREG_PRT3_DM2\r
+SD_CD__DR EQU CYREG_PRT3_DR\r
+SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CD__MASK EQU 0x40\r
+SD_CD__PORT EQU 3\r
+SD_CD__PRT EQU CYREG_PRT3_PRT\r
+SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CD__PS EQU CYREG_PRT3_PS\r
+SD_CD__SHIFT EQU 6\r
+SD_CD__SLW EQU CYREG_PRT3_SLW\r
\r
-; SD_TX_DMA_COMPLETE\r
-SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
-SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+; SD_CS\r
+SD_CS__0__MASK EQU 0x10\r
+SD_CS__0__PC EQU CYREG_PRT3_PC4\r
+SD_CS__0__PORT EQU 3\r
+SD_CS__0__SHIFT EQU 4\r
+SD_CS__AG EQU CYREG_PRT3_AG\r
+SD_CS__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CS__BIE EQU CYREG_PRT3_BIE\r
+SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CS__BYP EQU CYREG_PRT3_BYP\r
+SD_CS__CTL EQU CYREG_PRT3_CTL\r
+SD_CS__DM0 EQU CYREG_PRT3_DM0\r
+SD_CS__DM1 EQU CYREG_PRT3_DM1\r
+SD_CS__DM2 EQU CYREG_PRT3_DM2\r
+SD_CS__DR EQU CYREG_PRT3_DR\r
+SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CS__MASK EQU 0x10\r
+SD_CS__PORT EQU 3\r
+SD_CS__PRT EQU CYREG_PRT3_PRT\r
+SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CS__PS EQU CYREG_PRT3_PS\r
+SD_CS__SHIFT EQU 4\r
+SD_CS__SLW EQU CYREG_PRT3_SLW\r
\r
-; SCSI_Parity_Error\r
-SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
-SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
+; USBFS_arb_int\r
+USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_arb_int__INTC_MASK EQU 0x400000\r
+USBFS_arb_int__INTC_NUMBER EQU 22\r
+USBFS_arb_int__INTC_PRIOR_NUM EQU 7\r
+USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22\r
+USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; USBFS_bus_reset\r
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
-; SCSI_CTL_PHASE\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB00_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB00_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB00_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL\r
-\r
-; SCSI_Filtered\r
-SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
-SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST\r
-SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
-SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
-SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
-SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
-SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
-SCSI_Filtered_sts_sts_reg__3__POS EQU 3\r
-SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
-SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
-SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB14_MSK\r
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB14_ST_CTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB14_ST_CTL\r
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB14_ST\r
-\r
-; SCSI_Out_Bits\r
-SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
-SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
-SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
-SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
-SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3\r
-SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10\r
-SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4\r
-SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20\r
-SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5\r
-SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40\r
-SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
-SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
-SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
-\r
-; USBFS_arb_int\r
-USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_arb_int__INTC_MASK EQU 0x400000\r
-USBFS_arb_int__INTC_NUMBER EQU 22\r
-USBFS_arb_int__INTC_PRIOR_NUM EQU 7\r
-USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22\r
-USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+; USBFS_Dm\r
+USBFS_Dm__0__MASK EQU 0x80\r
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1\r
+USBFS_Dm__0__PORT EQU 15\r
+USBFS_Dm__0__SHIFT EQU 7\r
+USBFS_Dm__AG EQU CYREG_PRT15_AG\r
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX\r
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE\r
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP\r
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL\r
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0\r
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1\r
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2\r
+USBFS_Dm__DR EQU CYREG_PRT15_DR\r
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+USBFS_Dm__MASK EQU 0x80\r
+USBFS_Dm__PORT EQU 15\r
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT\r
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+USBFS_Dm__PS EQU CYREG_PRT15_PS\r
+USBFS_Dm__SHIFT EQU 7\r
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW\r
+\r
+; USBFS_Dp\r
+USBFS_Dp__0__MASK EQU 0x40\r
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0\r
+USBFS_Dp__0__PORT EQU 15\r
+USBFS_Dp__0__SHIFT EQU 6\r
+USBFS_Dp__AG EQU CYREG_PRT15_AG\r
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX\r
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE\r
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP\r
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL\r
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0\r
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1\r
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2\r
+USBFS_Dp__DR EQU CYREG_PRT15_DR\r
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT\r
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+USBFS_Dp__MASK EQU 0x40\r
+USBFS_Dp__PORT EQU 15\r
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT\r
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+USBFS_Dp__PS EQU CYREG_PRT15_PS\r
+USBFS_Dp__SHIFT EQU 6\r
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW\r
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15\r
+\r
+; USBFS_dp_int\r
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_dp_int__INTC_MASK EQU 0x1000\r
+USBFS_dp_int__INTC_NUMBER EQU 12\r
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7\r
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12\r
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; USBFS_ep_0\r
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_0__INTC_MASK EQU 0x1000000\r
+USBFS_ep_0__INTC_NUMBER EQU 24\r
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24\r
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; USBFS_ep_1\r
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_1__INTC_MASK EQU 0x40\r
+USBFS_ep_1__INTC_NUMBER EQU 6\r
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; USBFS_ep_2\r
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_2__INTC_MASK EQU 0x80\r
+USBFS_ep_2__INTC_NUMBER EQU 7\r
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; USBFS_ep_3\r
+USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_3__INTC_MASK EQU 0x100\r
+USBFS_ep_3__INTC_NUMBER EQU 8\r
+USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
+USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; USBFS_ep_4\r
+USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_4__INTC_MASK EQU 0x200\r
+USBFS_ep_4__INTC_NUMBER EQU 9\r
+USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9\r
+USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; USBFS_sof_int\r
USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
-; SCSI_Out_Ctl\r
-SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+; USBFS_USB\r
+USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG\r
+USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG\r
+USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN\r
+USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR\r
+USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG\r
+USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN\r
+USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR\r
+USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG\r
+USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN\r
+USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR\r
+USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG\r
+USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN\r
+USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR\r
+USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG\r
+USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN\r
+USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR\r
+USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG\r
+USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN\r
+USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR\r
+USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG\r
+USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN\r
+USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR\r
+USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG\r
+USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN\r
+USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR\r
+USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN\r
+USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR\r
+USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR\r
+USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA\r
+USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB\r
+USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA\r
+USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB\r
+USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR\r
+USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA\r
+USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB\r
+USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA\r
+USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB\r
+USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR\r
+USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA\r
+USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB\r
+USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA\r
+USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB\r
+USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR\r
+USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA\r
+USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB\r
+USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA\r
+USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB\r
+USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR\r
+USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA\r
+USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB\r
+USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA\r
+USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB\r
+USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR\r
+USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA\r
+USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB\r
+USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA\r
+USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB\r
+USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR\r
+USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA\r
+USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB\r
+USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA\r
+USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB\r
+USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR\r
+USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA\r
+USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB\r
+USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA\r
+USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB\r
+USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE\r
+USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT\r
+USBFS_USB__CR0 EQU CYREG_USB_CR0\r
+USBFS_USB__CR1 EQU CYREG_USB_CR1\r
+USBFS_USB__CWA EQU CYREG_USB_CWA\r
+USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB\r
+USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES\r
+USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB\r
+USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG\r
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE\r
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE\r
+USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT\r
+USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR\r
+USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0\r
+USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1\r
+USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2\r
+USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3\r
+USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4\r
+USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5\r
+USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6\r
+USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7\r
+USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE\r
+USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5\r
+USBFS_USB__PM_ACT_MSK EQU 0x01\r
+USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5\r
+USBFS_USB__PM_STBY_MSK EQU 0x01\r
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN\r
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR\r
+USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0\r
+USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1\r
+USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0\r
+USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0\r
+USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1\r
+USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0\r
+USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0\r
+USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1\r
+USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0\r
+USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0\r
+USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1\r
+USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0\r
+USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0\r
+USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1\r
+USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0\r
+USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0\r
+USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1\r
+USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0\r
+USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0\r
+USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1\r
+USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0\r
+USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0\r
+USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1\r
+USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0\r
+USBFS_USB__SOF0 EQU CYREG_USB_SOF0\r
+USBFS_USB__SOF1 EQU CYREG_USB_SOF1\r
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN\r
+USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0\r
+USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
\r
-; SCSI_Out_DBx\r
-SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__0__MASK EQU 0x08\r
-SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out_DBx__0__PORT EQU 6\r
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__0__SHIFT EQU 3\r
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__1__MASK EQU 0x04\r
-SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2\r
-SCSI_Out_DBx__1__PORT EQU 6\r
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__1__SHIFT EQU 2\r
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__2__MASK EQU 0x02\r
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out_DBx__2__PORT EQU 6\r
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__2__SHIFT EQU 1\r
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__3__MASK EQU 0x01\r
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out_DBx__3__PORT EQU 6\r
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__3__SHIFT EQU 0\r
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__4__MASK EQU 0x80\r
-SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7\r
-SCSI_Out_DBx__4__PORT EQU 4\r
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__4__SHIFT EQU 7\r
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__5__MASK EQU 0x40\r
-SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6\r
-SCSI_Out_DBx__5__PORT EQU 4\r
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__5__SHIFT EQU 6\r
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__6__MASK EQU 0x20\r
-SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out_DBx__6__PORT EQU 4\r
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__6__SHIFT EQU 5\r
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__7__MASK EQU 0x10\r
-SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out_DBx__7__PORT EQU 4\r
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__7__SHIFT EQU 4\r
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB0__MASK EQU 0x08\r
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out_DBx__DB0__PORT EQU 6\r
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB0__SHIFT EQU 3\r
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB1__MASK EQU 0x04\r
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2\r
-SCSI_Out_DBx__DB1__PORT EQU 6\r
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB1__SHIFT EQU 2\r
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB2__MASK EQU 0x02\r
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out_DBx__DB2__PORT EQU 6\r
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB2__SHIFT EQU 1\r
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB3__MASK EQU 0x01\r
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out_DBx__DB3__PORT EQU 6\r
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB3__SHIFT EQU 0\r
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB4__MASK EQU 0x80\r
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7\r
-SCSI_Out_DBx__DB4__PORT EQU 4\r
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB4__SHIFT EQU 7\r
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB5__MASK EQU 0x40\r
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6\r
-SCSI_Out_DBx__DB5__PORT EQU 4\r
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB5__SHIFT EQU 6\r
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB6__MASK EQU 0x20\r
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out_DBx__DB6__PORT EQU 4\r
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB6__SHIFT EQU 5\r
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB7__MASK EQU 0x10\r
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out_DBx__DB7__PORT EQU 4\r
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB7__SHIFT EQU 4\r
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW\r
-\r
-; SCSI_RST_ISR\r
-SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-SCSI_RST_ISR__INTC_MASK EQU 0x04\r
-SCSI_RST_ISR__INTC_NUMBER EQU 2\r
-SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
-SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SDCard_BSPIM\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK\r
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL\r
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL\r
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK\r
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
-SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
-SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
-SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
-SDCard_BSPIM_RxStsReg__5__POS EQU 5\r
-SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
-SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
-SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST\r
-SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
-SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
-SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
-SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
-SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
-SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
-SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
-SDCard_BSPIM_TxStsReg__3__POS EQU 3\r
-SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
-SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
-SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL\r
-\r
-; USBFS_dp_int\r
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_dp_int__INTC_MASK EQU 0x1000\r
-USBFS_dp_int__INTC_NUMBER EQU 12\r
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7\r
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12\r
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SCSI_In_DBx\r
-SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__0__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__0__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__0__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__0__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__0__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__0__MASK EQU 0x10\r
-SCSI_In_DBx__0__PC EQU CYREG_PRT12_PC4\r
-SCSI_In_DBx__0__PORT EQU 12\r
-SCSI_In_DBx__0__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__0__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__0__SHIFT EQU 4\r
-SCSI_In_DBx__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__0__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__1__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__1__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__1__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__1__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__1__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__1__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__1__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__1__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__1__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__1__MASK EQU 0x80\r
-SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC7\r
-SCSI_In_DBx__1__PORT EQU 2\r
-SCSI_In_DBx__1__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__1__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__1__SHIFT EQU 7\r
-SCSI_In_DBx__1__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__2__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__2__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__2__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__2__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__2__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__2__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__2__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__2__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__2__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__2__MASK EQU 0x40\r
-SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC6\r
-SCSI_In_DBx__2__PORT EQU 2\r
-SCSI_In_DBx__2__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__2__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__2__SHIFT EQU 6\r
-SCSI_In_DBx__2__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__3__MASK EQU 0x20\r
-SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC5\r
-SCSI_In_DBx__3__PORT EQU 2\r
-SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__3__SHIFT EQU 5\r
-SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__4__MASK EQU 0x10\r
-SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4\r
-SCSI_In_DBx__4__PORT EQU 2\r
-SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__4__SHIFT EQU 4\r
-SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__5__MASK EQU 0x08\r
-SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC3\r
-SCSI_In_DBx__5__PORT EQU 2\r
-SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__5__SHIFT EQU 3\r
-SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__6__MASK EQU 0x04\r
-SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC2\r
-SCSI_In_DBx__6__PORT EQU 2\r
-SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__6__SHIFT EQU 2\r
-SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__7__MASK EQU 0x02\r
-SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC1\r
-SCSI_In_DBx__7__PORT EQU 2\r
-SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__7__SHIFT EQU 1\r
-SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB0__AG EQU CYREG_PRT12_AG\r
-SCSI_In_DBx__DB0__BIE EQU CYREG_PRT12_BIE\r
-SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_In_DBx__DB0__BYP EQU CYREG_PRT12_BYP\r
-SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_In_DBx__DB0__DR EQU CYREG_PRT12_DR\r
-SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_In_DBx__DB0__MASK EQU 0x10\r
-SCSI_In_DBx__DB0__PC EQU CYREG_PRT12_PC4\r
-SCSI_In_DBx__DB0__PORT EQU 12\r
-SCSI_In_DBx__DB0__PRT EQU CYREG_PRT12_PRT\r
-SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_In_DBx__DB0__PS EQU CYREG_PRT12_PS\r
-SCSI_In_DBx__DB0__SHIFT EQU 4\r
-SCSI_In_DBx__DB0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_In_DBx__DB0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_In_DBx__DB0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_In_DBx__DB0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_In_DBx__DB0__SLW EQU CYREG_PRT12_SLW\r
-SCSI_In_DBx__DB1__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB1__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB1__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB1__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB1__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB1__MASK EQU 0x80\r
-SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC7\r
-SCSI_In_DBx__DB1__PORT EQU 2\r
-SCSI_In_DBx__DB1__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB1__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB1__SHIFT EQU 7\r
-SCSI_In_DBx__DB1__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB2__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB2__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB2__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB2__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB2__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB2__MASK EQU 0x40\r
-SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC6\r
-SCSI_In_DBx__DB2__PORT EQU 2\r
-SCSI_In_DBx__DB2__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB2__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB2__SHIFT EQU 6\r
-SCSI_In_DBx__DB2__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB3__MASK EQU 0x20\r
-SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC5\r
-SCSI_In_DBx__DB3__PORT EQU 2\r
-SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB3__SHIFT EQU 5\r
-SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB4__MASK EQU 0x10\r
-SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4\r
-SCSI_In_DBx__DB4__PORT EQU 2\r
-SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB4__SHIFT EQU 4\r
-SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB5__MASK EQU 0x08\r
-SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC3\r
-SCSI_In_DBx__DB5__PORT EQU 2\r
-SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB5__SHIFT EQU 3\r
-SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB6__MASK EQU 0x04\r
-SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC2\r
-SCSI_In_DBx__DB6__PORT EQU 2\r
-SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB6__SHIFT EQU 2\r
-SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
-SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG\r
-SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
-SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
-SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
-SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
-SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
-SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
-SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
-SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
-SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR\r
-SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
-SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
-SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
-SCSI_In_DBx__DB7__MASK EQU 0x02\r
-SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC1\r
-SCSI_In_DBx__DB7__PORT EQU 2\r
-SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
-SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
-SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
-SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
-SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS\r
-SCSI_In_DBx__DB7__SHIFT EQU 1\r
-SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
-\r
-; SCSI_RX_DMA\r
-SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SCSI_RX_DMA__DRQ_NUMBER EQU 0\r
-SCSI_RX_DMA__NUMBEROF_TDS EQU 0\r
-SCSI_RX_DMA__PRIORITY EQU 2\r
-SCSI_RX_DMA__TERMIN_EN EQU 0\r
-SCSI_RX_DMA__TERMIN_SEL EQU 0\r
-SCSI_RX_DMA__TERMOUT0_EN EQU 1\r
-SCSI_RX_DMA__TERMOUT0_SEL EQU 0\r
-SCSI_RX_DMA__TERMOUT1_EN EQU 0\r
-SCSI_RX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-; SCSI_TX_DMA\r
-SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SCSI_TX_DMA__DRQ_NUMBER EQU 1\r
-SCSI_TX_DMA__NUMBEROF_TDS EQU 0\r
-SCSI_TX_DMA__PRIORITY EQU 2\r
-SCSI_TX_DMA__TERMIN_EN EQU 0\r
-SCSI_TX_DMA__TERMIN_SEL EQU 0\r
-SCSI_TX_DMA__TERMOUT0_EN EQU 1\r
-SCSI_TX_DMA__TERMOUT0_SEL EQU 1\r
-SCSI_TX_DMA__TERMOUT1_EN EQU 0\r
-SCSI_TX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-; SD_Data_Clk\r
-SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
-SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
-SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2\r
-SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
-SD_Data_Clk__INDEX EQU 0x00\r
-SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SD_Data_Clk__PM_ACT_MSK EQU 0x01\r
-SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
-\r
-; timer_clock\r
-timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0\r
-timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1\r
-timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2\r
-timer_clock__CFG2_SRC_SEL_MASK EQU 0x07\r
-timer_clock__INDEX EQU 0x02\r
-timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-timer_clock__PM_ACT_MSK EQU 0x04\r
-timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-timer_clock__PM_STBY_MSK EQU 0x04\r
-\r
-; SCSI_Noise\r
-SCSI_Noise__0__AG EQU CYREG_PRT12_AG\r
-SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE\r
-SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP\r
-SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_Noise__0__DR EQU CYREG_PRT12_DR\r
-SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_Noise__0__MASK EQU 0x20\r
-SCSI_Noise__0__PC EQU CYREG_PRT12_PC5\r
-SCSI_Noise__0__PORT EQU 12\r
-SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT\r
-SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_Noise__0__PS EQU CYREG_PRT12_PS\r
-SCSI_Noise__0__SHIFT EQU 5\r
-SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW\r
-SCSI_Noise__1__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__1__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__1__MASK EQU 0x10\r
-SCSI_Noise__1__PC EQU CYREG_PRT6_PC4\r
-SCSI_Noise__1__PORT EQU 6\r
-SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__1__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__1__SHIFT EQU 4\r
-SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__2__AG EQU CYREG_PRT5_AG\r
-SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE\r
-SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP\r
-SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL\r
-SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_Noise__2__DR EQU CYREG_PRT5_DR\r
-SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_Noise__2__MASK EQU 0x01\r
-SCSI_Noise__2__PC EQU CYREG_PRT5_PC0\r
-SCSI_Noise__2__PORT EQU 5\r
-SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT\r
-SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_Noise__2__PS EQU CYREG_PRT5_PS\r
-SCSI_Noise__2__SHIFT EQU 0\r
-SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW\r
-SCSI_Noise__3__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__3__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__3__MASK EQU 0x40\r
-SCSI_Noise__3__PC EQU CYREG_PRT6_PC6\r
-SCSI_Noise__3__PORT EQU 6\r
-SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__3__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__3__SHIFT EQU 6\r
-SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__4__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__4__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__4__MASK EQU 0x20\r
-SCSI_Noise__4__PC EQU CYREG_PRT6_PC5\r
-SCSI_Noise__4__PORT EQU 6\r
-SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__4__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__4__SHIFT EQU 5\r
-SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__ACK__MASK EQU 0x20\r
-SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5\r
-SCSI_Noise__ACK__PORT EQU 6\r
-SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__ACK__SHIFT EQU 5\r
-SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG\r
-SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE\r
-SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP\r
-SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0\r
-SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1\r
-SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2\r
-SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR\r
-SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-SCSI_Noise__ATN__MASK EQU 0x20\r
-SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5\r
-SCSI_Noise__ATN__PORT EQU 12\r
-SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT\r
-SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS\r
-SCSI_Noise__ATN__SHIFT EQU 5\r
-SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW\r
-SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__BSY__MASK EQU 0x10\r
-SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4\r
-SCSI_Noise__BSY__PORT EQU 6\r
-SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__BSY__SHIFT EQU 4\r
-SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__RST__AG EQU CYREG_PRT6_AG\r
-SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Noise__RST__DR EQU CYREG_PRT6_DR\r
-SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Noise__RST__MASK EQU 0x40\r
-SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6\r
-SCSI_Noise__RST__PORT EQU 6\r
-SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Noise__RST__PS EQU CYREG_PRT6_PS\r
-SCSI_Noise__RST__SHIFT EQU 6\r
-SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG\r
-SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX\r
-SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE\r
-SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
-SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP\r
-SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL\r
-SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0\r
-SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1\r
-SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2\r
-SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR\r
-SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS\r
-SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
-SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN\r
-SCSI_Noise__SEL__MASK EQU 0x01\r
-SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0\r
-SCSI_Noise__SEL__PORT EQU 5\r
-SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT\r
-SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
-SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
-SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
-SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
-SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
-SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
-SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
-SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS\r
-SCSI_Noise__SEL__SHIFT EQU 0\r
-SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW\r
-\r
-; scsiTarget\r
-scsiTarget_StatusReg__0__MASK EQU 0x01\r
-scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
-scsiTarget_StatusReg__1__MASK EQU 0x02\r
-scsiTarget_StatusReg__1__POS EQU 1\r
-scsiTarget_StatusReg__2__MASK EQU 0x04\r
-scsiTarget_StatusReg__2__POS EQU 2\r
-scsiTarget_StatusReg__3__MASK EQU 0x08\r
-scsiTarget_StatusReg__3__POS EQU 3\r
-scsiTarget_StatusReg__4__MASK EQU 0x10\r
-scsiTarget_StatusReg__4__POS EQU 4\r
-scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST\r
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB01_MSK\r
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB01_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB01_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB01_ST\r
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB01_02_A0\r
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB01_02_A1\r
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB01_02_D0\r
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB01_02_D1\r
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB01_02_F0\r
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB01_02_F1\r
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB01_A0_A1\r
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB01_A0\r
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB01_A1\r
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB01_D0_D1\r
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB01_D0\r
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB01_D1\r
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB01_F0_F1\r
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB01_F0\r
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB01_F1\r
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
-\r
-; USBFS_ep_0\r
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_0__INTC_MASK EQU 0x1000000\r
-USBFS_ep_0__INTC_NUMBER EQU 24\r
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24\r
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_ep_1\r
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x40\r
-USBFS_ep_1__INTC_NUMBER EQU 6\r
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6\r
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_ep_2\r
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x80\r
-USBFS_ep_2__INTC_NUMBER EQU 7\r
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7\r
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_ep_3\r
-USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_3__INTC_MASK EQU 0x100\r
-USBFS_ep_3__INTC_NUMBER EQU 8\r
-USBFS_ep_3__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8\r
-USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_ep_4\r
-USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_4__INTC_MASK EQU 0x200\r
-USBFS_ep_4__INTC_NUMBER EQU 9\r
-USBFS_ep_4__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9\r
-USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SD_RX_DMA\r
-SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SD_RX_DMA__DRQ_NUMBER EQU 2\r
-SD_RX_DMA__NUMBEROF_TDS EQU 0\r
-SD_RX_DMA__PRIORITY EQU 1\r
-SD_RX_DMA__TERMIN_EN EQU 0\r
-SD_RX_DMA__TERMIN_SEL EQU 0\r
-SD_RX_DMA__TERMOUT0_EN EQU 1\r
-SD_RX_DMA__TERMOUT0_SEL EQU 2\r
-SD_RX_DMA__TERMOUT1_EN EQU 0\r
-SD_RX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-; SD_TX_DMA\r
-SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
-SD_TX_DMA__DRQ_NUMBER EQU 3\r
-SD_TX_DMA__NUMBEROF_TDS EQU 0\r
-SD_TX_DMA__PRIORITY EQU 2\r
-SD_TX_DMA__TERMIN_EN EQU 0\r
-SD_TX_DMA__TERMIN_SEL EQU 0\r
-SD_TX_DMA__TERMOUT0_EN EQU 1\r
-SD_TX_DMA__TERMOUT0_SEL EQU 3\r
-SD_TX_DMA__TERMOUT1_EN EQU 0\r
-SD_TX_DMA__TERMOUT1_SEL EQU 0\r
-\r
-; USBFS_USB\r
-USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG\r
-USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG\r
-USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN\r
-USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR\r
-USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG\r
-USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN\r
-USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR\r
-USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG\r
-USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN\r
-USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR\r
-USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG\r
-USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN\r
-USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR\r
-USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG\r
-USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN\r
-USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR\r
-USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG\r
-USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN\r
-USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR\r
-USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG\r
-USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN\r
-USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR\r
-USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG\r
-USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN\r
-USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR\r
-USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN\r
-USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR\r
-USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR\r
-USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA\r
-USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB\r
-USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA\r
-USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB\r
-USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR\r
-USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA\r
-USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB\r
-USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA\r
-USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB\r
-USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR\r
-USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA\r
-USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB\r
-USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA\r
-USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB\r
-USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR\r
-USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA\r
-USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB\r
-USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA\r
-USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB\r
-USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR\r
-USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA\r
-USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB\r
-USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA\r
-USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB\r
-USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR\r
-USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA\r
-USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB\r
-USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA\r
-USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB\r
-USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR\r
-USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA\r
-USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB\r
-USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA\r
-USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB\r
-USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR\r
-USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA\r
-USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB\r
-USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA\r
-USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB\r
-USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE\r
-USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT\r
-USBFS_USB__CR0 EQU CYREG_USB_CR0\r
-USBFS_USB__CR1 EQU CYREG_USB_CR1\r
-USBFS_USB__CWA EQU CYREG_USB_CWA\r
-USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB\r
-USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES\r
-USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB\r
-USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG\r
-USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT\r
-USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR\r
-USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0\r
-USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1\r
-USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2\r
-USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3\r
-USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4\r
-USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5\r
-USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6\r
-USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7\r
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE\r
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE\r
-USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE\r
-USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5\r
-USBFS_USB__PM_ACT_MSK EQU 0x01\r
-USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5\r
-USBFS_USB__PM_STBY_MSK EQU 0x01\r
-USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0\r
-USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1\r
-USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0\r
-USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0\r
-USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1\r
-USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0\r
-USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0\r
-USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1\r
-USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0\r
-USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0\r
-USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1\r
-USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0\r
-USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0\r
-USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1\r
-USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0\r
-USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0\r
-USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1\r
-USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0\r
-USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0\r
-USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1\r
-USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0\r
-USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0\r
-USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1\r
-USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0\r
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN\r
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR\r
-USBFS_USB__SOF0 EQU CYREG_USB_SOF0\r
-USBFS_USB__SOF1 EQU CYREG_USB_SOF1\r
-USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0\r
-USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN\r
-\r
-; SCSI_CLK\r
-SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
-SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
-SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
-SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07\r
-SCSI_CLK__INDEX EQU 0x01\r
-SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
-SCSI_CLK__PM_ACT_MSK EQU 0x02\r
-SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
-SCSI_CLK__PM_STBY_MSK EQU 0x02\r
-\r
-; SCSI_Out\r
-SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__0__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__0__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__0__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__0__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__0__MASK EQU 0x08\r
-SCSI_Out__0__PC EQU CYREG_PRT4_PC3\r
-SCSI_Out__0__PORT EQU 4\r
-SCSI_Out__0__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__0__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__0__SHIFT EQU 3\r
-SCSI_Out__0__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__1__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__1__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__1__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__1__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__1__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__1__MASK EQU 0x04\r
-SCSI_Out__1__PC EQU CYREG_PRT4_PC2\r
-SCSI_Out__1__PORT EQU 4\r
-SCSI_Out__1__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__1__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__1__SHIFT EQU 2\r
-SCSI_Out__1__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__2__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__2__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__2__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__2__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__2__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__2__MASK EQU 0x80\r
-SCSI_Out__2__PC EQU CYREG_PRT0_PC7\r
-SCSI_Out__2__PORT EQU 0\r
-SCSI_Out__2__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__2__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__2__SHIFT EQU 7\r
-SCSI_Out__2__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__3__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__3__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__3__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__3__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__3__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__3__MASK EQU 0x40\r
-SCSI_Out__3__PC EQU CYREG_PRT0_PC6\r
-SCSI_Out__3__PORT EQU 0\r
-SCSI_Out__3__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__3__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__3__SHIFT EQU 6\r
-SCSI_Out__3__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__4__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__4__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__4__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__4__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__4__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__4__MASK EQU 0x20\r
-SCSI_Out__4__PC EQU CYREG_PRT0_PC5\r
-SCSI_Out__4__PORT EQU 0\r
-SCSI_Out__4__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__4__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__4__SHIFT EQU 5\r
-SCSI_Out__4__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__5__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__5__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__5__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__5__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__5__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__5__MASK EQU 0x10\r
-SCSI_Out__5__PC EQU CYREG_PRT0_PC4\r
-SCSI_Out__5__PORT EQU 0\r
-SCSI_Out__5__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__5__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__5__SHIFT EQU 4\r
-SCSI_Out__5__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__6__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__6__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__6__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__6__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__6__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__6__MASK EQU 0x08\r
-SCSI_Out__6__PC EQU CYREG_PRT0_PC3\r
-SCSI_Out__6__PORT EQU 0\r
-SCSI_Out__6__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__6__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__6__SHIFT EQU 3\r
-SCSI_Out__6__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__7__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__7__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__7__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__7__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__7__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__7__MASK EQU 0x04\r
-SCSI_Out__7__PC EQU CYREG_PRT0_PC2\r
-SCSI_Out__7__PORT EQU 0\r
-SCSI_Out__7__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__7__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__7__SHIFT EQU 2\r
-SCSI_Out__7__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__8__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__8__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__8__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__8__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__8__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__8__MASK EQU 0x02\r
-SCSI_Out__8__PC EQU CYREG_PRT0_PC1\r
-SCSI_Out__8__PORT EQU 0\r
-SCSI_Out__8__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__8__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__8__SHIFT EQU 1\r
-SCSI_Out__8__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__9__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__9__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__9__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__9__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__9__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__9__MASK EQU 0x01\r
-SCSI_Out__9__PC EQU CYREG_PRT0_PC0\r
-SCSI_Out__9__PORT EQU 0\r
-SCSI_Out__9__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__9__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__9__SHIFT EQU 0\r
-SCSI_Out__9__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__ACK__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__ACK__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__ACK__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__ACK__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__ACK__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__ACK__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__ACK__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__ACK__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__ACK__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__ACK__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__ACK__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__ACK__MASK EQU 0x40\r
-SCSI_Out__ACK__PC EQU CYREG_PRT0_PC6\r
-SCSI_Out__ACK__PORT EQU 0\r
-SCSI_Out__ACK__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__ACK__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__ACK__SHIFT EQU 6\r
-SCSI_Out__ACK__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__ATN__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__ATN__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__ATN__MASK EQU 0x04\r
-SCSI_Out__ATN__PC EQU CYREG_PRT4_PC2\r
-SCSI_Out__ATN__PORT EQU 4\r
-SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__ATN__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__ATN__SHIFT EQU 2\r
-SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__BSY__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__BSY__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__BSY__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__BSY__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__BSY__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__BSY__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__BSY__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__BSY__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__BSY__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__BSY__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__BSY__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__BSY__MASK EQU 0x80\r
-SCSI_Out__BSY__PC EQU CYREG_PRT0_PC7\r
-SCSI_Out__BSY__PORT EQU 0\r
-SCSI_Out__BSY__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__BSY__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__BSY__SHIFT EQU 7\r
-SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__CD_raw__MASK EQU 0x04\r
-SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2\r
-SCSI_Out__CD_raw__PORT EQU 0\r
-SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__CD_raw__SHIFT EQU 2\r
-SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG\r
-SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR\r
-SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out__DBP_raw__MASK EQU 0x08\r
-SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC3\r
-SCSI_Out__DBP_raw__PORT EQU 4\r
-SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS\r
-SCSI_Out__DBP_raw__SHIFT EQU 3\r
-SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__IO_raw__MASK EQU 0x01\r
-SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC0\r
-SCSI_Out__IO_raw__PORT EQU 0\r
-SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__IO_raw__SHIFT EQU 0\r
-SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__MSG_raw__MASK EQU 0x10\r
-SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4\r
-SCSI_Out__MSG_raw__PORT EQU 0\r
-SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__MSG_raw__SHIFT EQU 4\r
-SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__REQ__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__REQ__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__REQ__MASK EQU 0x02\r
-SCSI_Out__REQ__PC EQU CYREG_PRT0_PC1\r
-SCSI_Out__REQ__PORT EQU 0\r
-SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__REQ__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__REQ__SHIFT EQU 1\r
-SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__RST__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__RST__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__RST__MASK EQU 0x20\r
-SCSI_Out__RST__PC EQU CYREG_PRT0_PC5\r
-SCSI_Out__RST__PORT EQU 0\r
-SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__RST__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__RST__SHIFT EQU 5\r
-SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW\r
-SCSI_Out__SEL__AG EQU CYREG_PRT0_AG\r
-SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX\r
-SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE\r
-SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
-SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP\r
-SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL\r
-SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0\r
-SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1\r
-SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2\r
-SCSI_Out__SEL__DR EQU CYREG_PRT0_DR\r
-SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS\r
-SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
-SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN\r
-SCSI_Out__SEL__MASK EQU 0x08\r
-SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3\r
-SCSI_Out__SEL__PORT EQU 0\r
-SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT\r
-SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
-SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
-SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
-SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
-SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
-SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
-SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
-SCSI_Out__SEL__PS EQU CYREG_PRT0_PS\r
-SCSI_Out__SEL__SHIFT EQU 3\r
-SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
-\r
-; USBFS_Dm\r
-USBFS_Dm__0__MASK EQU 0x80\r
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1\r
-USBFS_Dm__0__PORT EQU 15\r
-USBFS_Dm__0__SHIFT EQU 7\r
-USBFS_Dm__AG EQU CYREG_PRT15_AG\r
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX\r
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE\r
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP\r
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL\r
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0\r
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1\r
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2\r
-USBFS_Dm__DR EQU CYREG_PRT15_DR\r
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-USBFS_Dm__MASK EQU 0x80\r
-USBFS_Dm__PORT EQU 15\r
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT\r
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-USBFS_Dm__PS EQU CYREG_PRT15_PS\r
-USBFS_Dm__SHIFT EQU 7\r
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW\r
+; SDCard_BSPIM\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
+SDCard_BSPIM_RxStsReg__5__POS EQU 5\r
+SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
+SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
+SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB07_08_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB07_08_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB07_08_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB07_08_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB07_08_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB07_08_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB07_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB07_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB07_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB07_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB07_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB07_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB07_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB07_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB07_F1\r
+SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
+SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
+SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
+SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
+SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
+SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
+SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
+SDCard_BSPIM_TxStsReg__3__POS EQU 3\r
+SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST\r
\r
-; USBFS_Dp\r
-USBFS_Dp__0__MASK EQU 0x40\r
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0\r
-USBFS_Dp__0__PORT EQU 15\r
-USBFS_Dp__0__SHIFT EQU 6\r
-USBFS_Dp__AG EQU CYREG_PRT15_AG\r
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX\r
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE\r
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP\r
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL\r
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0\r
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1\r
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2\r
-USBFS_Dp__DR EQU CYREG_PRT15_DR\r
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT\r
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-USBFS_Dp__MASK EQU 0x40\r
-USBFS_Dp__PORT EQU 15\r
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT\r
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-USBFS_Dp__PS EQU CYREG_PRT15_PS\r
-USBFS_Dp__SHIFT EQU 6\r
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW\r
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15\r
+; SD_SCK\r
+SD_SCK__0__MASK EQU 0x04\r
+SD_SCK__0__PC EQU CYREG_PRT3_PC2\r
+SD_SCK__0__PORT EQU 3\r
+SD_SCK__0__SHIFT EQU 2\r
+SD_SCK__AG EQU CYREG_PRT3_AG\r
+SD_SCK__AMUX EQU CYREG_PRT3_AMUX\r
+SD_SCK__BIE EQU CYREG_PRT3_BIE\r
+SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_SCK__BYP EQU CYREG_PRT3_BYP\r
+SD_SCK__CTL EQU CYREG_PRT3_CTL\r
+SD_SCK__DM0 EQU CYREG_PRT3_DM0\r
+SD_SCK__DM1 EQU CYREG_PRT3_DM1\r
+SD_SCK__DM2 EQU CYREG_PRT3_DM2\r
+SD_SCK__DR EQU CYREG_PRT3_DR\r
+SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_SCK__MASK EQU 0x04\r
+SD_SCK__PORT EQU 3\r
+SD_SCK__PRT EQU CYREG_PRT3_PRT\r
+SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_SCK__PS EQU CYREG_PRT3_PS\r
+SD_SCK__SHIFT EQU 2\r
+SD_SCK__SLW EQU CYREG_PRT3_SLW\r
\r
; SCSI_In\r
SCSI_In__0__AG EQU CYREG_PRT2_AG\r
SCSI_In__REQ__SHIFT EQU 2\r
SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW\r
\r
-; SD_DAT1\r
-SD_DAT1__0__MASK EQU 0x01\r
-SD_DAT1__0__PC EQU CYREG_PRT3_PC0\r
-SD_DAT1__0__PORT EQU 3\r
-SD_DAT1__0__SHIFT EQU 0\r
-SD_DAT1__AG EQU CYREG_PRT3_AG\r
-SD_DAT1__AMUX EQU CYREG_PRT3_AMUX\r
-SD_DAT1__BIE EQU CYREG_PRT3_BIE\r
-SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_DAT1__BYP EQU CYREG_PRT3_BYP\r
-SD_DAT1__CTL EQU CYREG_PRT3_CTL\r
-SD_DAT1__DM0 EQU CYREG_PRT3_DM0\r
-SD_DAT1__DM1 EQU CYREG_PRT3_DM1\r
-SD_DAT1__DM2 EQU CYREG_PRT3_DM2\r
-SD_DAT1__DR EQU CYREG_PRT3_DR\r
-SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_DAT1__MASK EQU 0x01\r
-SD_DAT1__PORT EQU 3\r
-SD_DAT1__PRT EQU CYREG_PRT3_PRT\r
-SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_DAT1__PS EQU CYREG_PRT3_PS\r
-SD_DAT1__SHIFT EQU 0\r
-SD_DAT1__SLW EQU CYREG_PRT3_SLW\r
+; SCSI_In_DBx\r
+SCSI_In_DBx__0__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__0__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__0__MASK EQU 0x10\r
+SCSI_In_DBx__0__PC EQU CYREG_PRT12_PC4\r
+SCSI_In_DBx__0__PORT EQU 12\r
+SCSI_In_DBx__0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__0__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__0__SHIFT EQU 4\r
+SCSI_In_DBx__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__1__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__1__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__1__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__1__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__1__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__1__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__1__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__1__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__1__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__1__MASK EQU 0x80\r
+SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC7\r
+SCSI_In_DBx__1__PORT EQU 2\r
+SCSI_In_DBx__1__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__1__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__1__SHIFT EQU 7\r
+SCSI_In_DBx__1__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__2__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__2__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__2__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__2__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__2__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__2__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__2__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__2__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__2__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__2__MASK EQU 0x40\r
+SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC6\r
+SCSI_In_DBx__2__PORT EQU 2\r
+SCSI_In_DBx__2__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__2__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__2__SHIFT EQU 6\r
+SCSI_In_DBx__2__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__3__MASK EQU 0x20\r
+SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__3__PORT EQU 2\r
+SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__3__SHIFT EQU 5\r
+SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__4__MASK EQU 0x10\r
+SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__4__PORT EQU 2\r
+SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__4__SHIFT EQU 4\r
+SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__5__MASK EQU 0x08\r
+SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC3\r
+SCSI_In_DBx__5__PORT EQU 2\r
+SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__5__SHIFT EQU 3\r
+SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__6__MASK EQU 0x04\r
+SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC2\r
+SCSI_In_DBx__6__PORT EQU 2\r
+SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__6__SHIFT EQU 2\r
+SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__7__MASK EQU 0x02\r
+SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC1\r
+SCSI_In_DBx__7__PORT EQU 2\r
+SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__7__SHIFT EQU 1\r
+SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB0__AG EQU CYREG_PRT12_AG\r
+SCSI_In_DBx__DB0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In_DBx__DB0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In_DBx__DB0__DR EQU CYREG_PRT12_DR\r
+SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In_DBx__DB0__MASK EQU 0x10\r
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT12_PC4\r
+SCSI_In_DBx__DB0__PORT EQU 12\r
+SCSI_In_DBx__DB0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In_DBx__DB0__PS EQU CYREG_PRT12_PS\r
+SCSI_In_DBx__DB0__SHIFT EQU 4\r
+SCSI_In_DBx__DB0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In_DBx__DB0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In_DBx__DB0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In_DBx__DB0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In_DBx__DB0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In_DBx__DB1__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB1__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB1__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB1__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB1__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB1__MASK EQU 0x80\r
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC7\r
+SCSI_In_DBx__DB1__PORT EQU 2\r
+SCSI_In_DBx__DB1__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB1__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB1__SHIFT EQU 7\r
+SCSI_In_DBx__DB1__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB2__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB2__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB2__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB2__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB2__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB2__MASK EQU 0x40\r
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC6\r
+SCSI_In_DBx__DB2__PORT EQU 2\r
+SCSI_In_DBx__DB2__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB2__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB2__SHIFT EQU 6\r
+SCSI_In_DBx__DB2__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB3__MASK EQU 0x20\r
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__DB3__PORT EQU 2\r
+SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB3__SHIFT EQU 5\r
+SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB4__MASK EQU 0x10\r
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__DB4__PORT EQU 2\r
+SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB4__SHIFT EQU 4\r
+SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB5__MASK EQU 0x08\r
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC3\r
+SCSI_In_DBx__DB5__PORT EQU 2\r
+SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB5__SHIFT EQU 3\r
+SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB6__MASK EQU 0x04\r
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC2\r
+SCSI_In_DBx__DB6__PORT EQU 2\r
+SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB6__SHIFT EQU 2\r
+SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW\r
+SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__DB7__MASK EQU 0x02\r
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC1\r
+SCSI_In_DBx__DB7__PORT EQU 2\r
+SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__DB7__SHIFT EQU 1\r
+SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW\r
+\r
+; SD_DAT1\r
+SD_DAT1__0__MASK EQU 0x01\r
+SD_DAT1__0__PC EQU CYREG_PRT3_PC0\r
+SD_DAT1__0__PORT EQU 3\r
+SD_DAT1__0__SHIFT EQU 0\r
+SD_DAT1__AG EQU CYREG_PRT3_AG\r
+SD_DAT1__AMUX EQU CYREG_PRT3_AMUX\r
+SD_DAT1__BIE EQU CYREG_PRT3_BIE\r
+SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_DAT1__BYP EQU CYREG_PRT3_BYP\r
+SD_DAT1__CTL EQU CYREG_PRT3_CTL\r
+SD_DAT1__DM0 EQU CYREG_PRT3_DM0\r
+SD_DAT1__DM1 EQU CYREG_PRT3_DM1\r
+SD_DAT1__DM2 EQU CYREG_PRT3_DM2\r
+SD_DAT1__DR EQU CYREG_PRT3_DR\r
+SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_DAT1__MASK EQU 0x01\r
+SD_DAT1__PORT EQU 3\r
+SD_DAT1__PRT EQU CYREG_PRT3_PRT\r
+SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_DAT1__PS EQU CYREG_PRT3_PS\r
+SD_DAT1__SHIFT EQU 0\r
+SD_DAT1__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_DAT2\r
+SD_DAT2__0__MASK EQU 0x20\r
+SD_DAT2__0__PC EQU CYREG_PRT3_PC5\r
+SD_DAT2__0__PORT EQU 3\r
+SD_DAT2__0__SHIFT EQU 5\r
+SD_DAT2__AG EQU CYREG_PRT3_AG\r
+SD_DAT2__AMUX EQU CYREG_PRT3_AMUX\r
+SD_DAT2__BIE EQU CYREG_PRT3_BIE\r
+SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_DAT2__BYP EQU CYREG_PRT3_BYP\r
+SD_DAT2__CTL EQU CYREG_PRT3_CTL\r
+SD_DAT2__DM0 EQU CYREG_PRT3_DM0\r
+SD_DAT2__DM1 EQU CYREG_PRT3_DM1\r
+SD_DAT2__DM2 EQU CYREG_PRT3_DM2\r
+SD_DAT2__DR EQU CYREG_PRT3_DR\r
+SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_DAT2__MASK EQU 0x20\r
+SD_DAT2__PORT EQU 3\r
+SD_DAT2__PRT EQU CYREG_PRT3_PRT\r
+SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_DAT2__PS EQU CYREG_PRT3_PS\r
+SD_DAT2__SHIFT EQU 5\r
+SD_DAT2__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_MISO\r
+SD_MISO__0__MASK EQU 0x02\r
+SD_MISO__0__PC EQU CYREG_PRT3_PC1\r
+SD_MISO__0__PORT EQU 3\r
+SD_MISO__0__SHIFT EQU 1\r
+SD_MISO__AG EQU CYREG_PRT3_AG\r
+SD_MISO__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MISO__BIE EQU CYREG_PRT3_BIE\r
+SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MISO__BYP EQU CYREG_PRT3_BYP\r
+SD_MISO__CTL EQU CYREG_PRT3_CTL\r
+SD_MISO__DM0 EQU CYREG_PRT3_DM0\r
+SD_MISO__DM1 EQU CYREG_PRT3_DM1\r
+SD_MISO__DM2 EQU CYREG_PRT3_DM2\r
+SD_MISO__DR EQU CYREG_PRT3_DR\r
+SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MISO__MASK EQU 0x02\r
+SD_MISO__PORT EQU 3\r
+SD_MISO__PRT EQU CYREG_PRT3_PRT\r
+SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MISO__PS EQU CYREG_PRT3_PS\r
+SD_MISO__SHIFT EQU 1\r
+SD_MISO__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_MOSI\r
+SD_MOSI__0__MASK EQU 0x08\r
+SD_MOSI__0__PC EQU CYREG_PRT3_PC3\r
+SD_MOSI__0__PORT EQU 3\r
+SD_MOSI__0__SHIFT EQU 3\r
+SD_MOSI__AG EQU CYREG_PRT3_AG\r
+SD_MOSI__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MOSI__BIE EQU CYREG_PRT3_BIE\r
+SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MOSI__BYP EQU CYREG_PRT3_BYP\r
+SD_MOSI__CTL EQU CYREG_PRT3_CTL\r
+SD_MOSI__DM0 EQU CYREG_PRT3_DM0\r
+SD_MOSI__DM1 EQU CYREG_PRT3_DM1\r
+SD_MOSI__DM2 EQU CYREG_PRT3_DM2\r
+SD_MOSI__DR EQU CYREG_PRT3_DR\r
+SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MOSI__MASK EQU 0x08\r
+SD_MOSI__PORT EQU 3\r
+SD_MOSI__PRT EQU CYREG_PRT3_PRT\r
+SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MOSI__PS EQU CYREG_PRT3_PS\r
+SD_MOSI__SHIFT EQU 3\r
+SD_MOSI__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SCSI_CLK\r
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07\r
+SCSI_CLK__INDEX EQU 0x01\r
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SCSI_CLK__PM_ACT_MSK EQU 0x02\r
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SCSI_CLK__PM_STBY_MSK EQU 0x02\r
+\r
+; SCSI_Out\r
+SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__0__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__0__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__0__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__0__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__0__MASK EQU 0x08\r
+SCSI_Out__0__PC EQU CYREG_PRT4_PC3\r
+SCSI_Out__0__PORT EQU 4\r
+SCSI_Out__0__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__0__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__0__SHIFT EQU 3\r
+SCSI_Out__0__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__1__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__1__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__1__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__1__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__1__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__1__MASK EQU 0x04\r
+SCSI_Out__1__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__1__PORT EQU 4\r
+SCSI_Out__1__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__1__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__1__SHIFT EQU 2\r
+SCSI_Out__1__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__2__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__2__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__2__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__2__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__2__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__2__MASK EQU 0x80\r
+SCSI_Out__2__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out__2__PORT EQU 0\r
+SCSI_Out__2__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__2__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__2__SHIFT EQU 7\r
+SCSI_Out__2__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__3__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__3__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__3__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__3__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__3__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__3__MASK EQU 0x40\r
+SCSI_Out__3__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out__3__PORT EQU 0\r
+SCSI_Out__3__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__3__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__3__SHIFT EQU 6\r
+SCSI_Out__3__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__4__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__4__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__4__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__4__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__4__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__4__MASK EQU 0x20\r
+SCSI_Out__4__PC EQU CYREG_PRT0_PC5\r
+SCSI_Out__4__PORT EQU 0\r
+SCSI_Out__4__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__4__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__4__SHIFT EQU 5\r
+SCSI_Out__4__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__5__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__5__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__5__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__5__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__5__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__5__MASK EQU 0x10\r
+SCSI_Out__5__PC EQU CYREG_PRT0_PC4\r
+SCSI_Out__5__PORT EQU 0\r
+SCSI_Out__5__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__5__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__5__SHIFT EQU 4\r
+SCSI_Out__5__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__6__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__6__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__6__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__6__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__6__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__6__MASK EQU 0x08\r
+SCSI_Out__6__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out__6__PORT EQU 0\r
+SCSI_Out__6__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__6__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__6__SHIFT EQU 3\r
+SCSI_Out__6__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__7__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__7__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__7__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__7__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__7__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__7__MASK EQU 0x04\r
+SCSI_Out__7__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out__7__PORT EQU 0\r
+SCSI_Out__7__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__7__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__7__SHIFT EQU 2\r
+SCSI_Out__7__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__8__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__8__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__8__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__8__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__8__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__8__MASK EQU 0x02\r
+SCSI_Out__8__PC EQU CYREG_PRT0_PC1\r
+SCSI_Out__8__PORT EQU 0\r
+SCSI_Out__8__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__8__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__8__SHIFT EQU 1\r
+SCSI_Out__8__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__9__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__9__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__9__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__9__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__9__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__9__MASK EQU 0x01\r
+SCSI_Out__9__PC EQU CYREG_PRT0_PC0\r
+SCSI_Out__9__PORT EQU 0\r
+SCSI_Out__9__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__9__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__9__SHIFT EQU 0\r
+SCSI_Out__9__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__ACK__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__ACK__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__ACK__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__ACK__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__ACK__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__ACK__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__ACK__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__ACK__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__ACK__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__ACK__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__ACK__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__ACK__MASK EQU 0x40\r
+SCSI_Out__ACK__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out__ACK__PORT EQU 0\r
+SCSI_Out__ACK__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__ACK__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__ACK__SHIFT EQU 6\r
+SCSI_Out__ACK__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__ATN__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__ATN__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__ATN__MASK EQU 0x04\r
+SCSI_Out__ATN__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__ATN__PORT EQU 4\r
+SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__ATN__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__ATN__SHIFT EQU 2\r
+SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__BSY__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__BSY__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__BSY__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__BSY__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__BSY__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__BSY__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__BSY__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__BSY__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__BSY__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__BSY__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__BSY__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__BSY__MASK EQU 0x80\r
+SCSI_Out__BSY__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out__BSY__PORT EQU 0\r
+SCSI_Out__BSY__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__BSY__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__BSY__SHIFT EQU 7\r
+SCSI_Out__BSY__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__CD_raw__MASK EQU 0x04\r
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out__CD_raw__PORT EQU 0\r
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__CD_raw__SHIFT EQU 2\r
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__DBP_raw__MASK EQU 0x08\r
+SCSI_Out__DBP_raw__PC EQU CYREG_PRT4_PC3\r
+SCSI_Out__DBP_raw__PORT EQU 4\r
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__DBP_raw__SHIFT EQU 3\r
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__IO_raw__MASK EQU 0x01\r
+SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC0\r
+SCSI_Out__IO_raw__PORT EQU 0\r
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__IO_raw__SHIFT EQU 0\r
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__MSG_raw__MASK EQU 0x10\r
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC4\r
+SCSI_Out__MSG_raw__PORT EQU 0\r
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__MSG_raw__SHIFT EQU 4\r
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__REQ__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__REQ__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__REQ__MASK EQU 0x02\r
+SCSI_Out__REQ__PC EQU CYREG_PRT0_PC1\r
+SCSI_Out__REQ__PORT EQU 0\r
+SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__REQ__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__REQ__SHIFT EQU 1\r
+SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__RST__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__RST__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__RST__MASK EQU 0x20\r
+SCSI_Out__RST__PC EQU CYREG_PRT0_PC5\r
+SCSI_Out__RST__PORT EQU 0\r
+SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__RST__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__RST__SHIFT EQU 5\r
+SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW\r
+SCSI_Out__SEL__AG EQU CYREG_PRT0_AG\r
+SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out__SEL__DR EQU CYREG_PRT0_DR\r
+SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out__SEL__MASK EQU 0x08\r
+SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out__SEL__PORT EQU 0\r
+SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out__SEL__PS EQU CYREG_PRT0_PS\r
+SCSI_Out__SEL__SHIFT EQU 3\r
+SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
+\r
+; SCSI_Out_Bits\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08\r
+SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10\r
+SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20\r
+SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40\r
+SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
+SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+\r
+; SCSI_Out_Ctl\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK\r
+\r
+; SCSI_Out_DBx\r
+SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__0__MASK EQU 0x08\r
+SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out_DBx__0__PORT EQU 6\r
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__0__SHIFT EQU 3\r
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__1__MASK EQU 0x04\r
+SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out_DBx__1__PORT EQU 6\r
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__1__SHIFT EQU 2\r
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__2__MASK EQU 0x02\r
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out_DBx__2__PORT EQU 6\r
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__2__SHIFT EQU 1\r
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__3__MASK EQU 0x01\r
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out_DBx__3__PORT EQU 6\r
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__3__SHIFT EQU 0\r
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__4__MASK EQU 0x80\r
+SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out_DBx__4__PORT EQU 4\r
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__4__SHIFT EQU 7\r
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__5__MASK EQU 0x40\r
+SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out_DBx__5__PORT EQU 4\r
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__5__SHIFT EQU 6\r
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__6__MASK EQU 0x20\r
+SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out_DBx__6__PORT EQU 4\r
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__6__SHIFT EQU 5\r
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__7__MASK EQU 0x10\r
+SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out_DBx__7__PORT EQU 4\r
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__7__SHIFT EQU 4\r
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB0__MASK EQU 0x08\r
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out_DBx__DB0__PORT EQU 6\r
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB0__SHIFT EQU 3\r
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB1__MASK EQU 0x04\r
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out_DBx__DB1__PORT EQU 6\r
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB1__SHIFT EQU 2\r
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB2__MASK EQU 0x02\r
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out_DBx__DB2__PORT EQU 6\r
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB2__SHIFT EQU 1\r
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB3__MASK EQU 0x01\r
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out_DBx__DB3__PORT EQU 6\r
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB3__SHIFT EQU 0\r
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB4__MASK EQU 0x80\r
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out_DBx__DB4__PORT EQU 4\r
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB4__SHIFT EQU 7\r
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB5__MASK EQU 0x40\r
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out_DBx__DB5__PORT EQU 4\r
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB5__SHIFT EQU 6\r
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB6__MASK EQU 0x20\r
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out_DBx__DB6__PORT EQU 4\r
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB6__SHIFT EQU 5\r
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB7__MASK EQU 0x10\r
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out_DBx__DB7__PORT EQU 4\r
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB7__SHIFT EQU 4\r
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW\r
+\r
+; SD_RX_DMA\r
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_RX_DMA__DRQ_NUMBER EQU 2\r
+SD_RX_DMA__NUMBEROF_TDS EQU 0\r
+SD_RX_DMA__PRIORITY EQU 2\r
+SD_RX_DMA__TERMIN_EN EQU 0\r
+SD_RX_DMA__TERMIN_SEL EQU 0\r
+SD_RX_DMA__TERMOUT0_EN EQU 1\r
+SD_RX_DMA__TERMOUT0_SEL EQU 2\r
+SD_RX_DMA__TERMOUT1_EN EQU 0\r
+SD_RX_DMA__TERMOUT1_SEL EQU 0\r
+\r
+; SD_RX_DMA_COMPLETE\r
+SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10\r
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4\r
+SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SD_TX_DMA\r
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SD_TX_DMA__DRQ_NUMBER EQU 3\r
+SD_TX_DMA__NUMBEROF_TDS EQU 0\r
+SD_TX_DMA__PRIORITY EQU 2\r
+SD_TX_DMA__TERMIN_EN EQU 0\r
+SD_TX_DMA__TERMIN_SEL EQU 0\r
+SD_TX_DMA__TERMOUT0_EN EQU 1\r
+SD_TX_DMA__TERMOUT0_SEL EQU 3\r
+SD_TX_DMA__TERMOUT1_EN EQU 0\r
+SD_TX_DMA__TERMOUT1_SEL EQU 0\r
+\r
+; SD_TX_DMA_COMPLETE\r
+SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20\r
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5\r
+SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SCSI_Noise\r
+SCSI_Noise__0__AG EQU CYREG_PRT12_AG\r
+SCSI_Noise__0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_Noise__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_Noise__0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_Noise__0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_Noise__0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_Noise__0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_Noise__0__DR EQU CYREG_PRT12_DR\r
+SCSI_Noise__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_Noise__0__MASK EQU 0x20\r
+SCSI_Noise__0__PC EQU CYREG_PRT12_PC5\r
+SCSI_Noise__0__PORT EQU 12\r
+SCSI_Noise__0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_Noise__0__PS EQU CYREG_PRT12_PS\r
+SCSI_Noise__0__SHIFT EQU 5\r
+SCSI_Noise__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_Noise__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_Noise__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_Noise__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_Noise__0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_Noise__1__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__1__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__1__MASK EQU 0x10\r
+SCSI_Noise__1__PC EQU CYREG_PRT6_PC4\r
+SCSI_Noise__1__PORT EQU 6\r
+SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__1__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__1__SHIFT EQU 4\r
+SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__2__AG EQU CYREG_PRT5_AG\r
+SCSI_Noise__2__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Noise__2__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Noise__2__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Noise__2__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Noise__2__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Noise__2__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Noise__2__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Noise__2__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Noise__2__DR EQU CYREG_PRT5_DR\r
+SCSI_Noise__2__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Noise__2__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Noise__2__MASK EQU 0x01\r
+SCSI_Noise__2__PC EQU CYREG_PRT5_PC0\r
+SCSI_Noise__2__PORT EQU 5\r
+SCSI_Noise__2__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Noise__2__PS EQU CYREG_PRT5_PS\r
+SCSI_Noise__2__SHIFT EQU 0\r
+SCSI_Noise__2__SLW EQU CYREG_PRT5_SLW\r
+SCSI_Noise__3__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__3__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__3__MASK EQU 0x40\r
+SCSI_Noise__3__PC EQU CYREG_PRT6_PC6\r
+SCSI_Noise__3__PORT EQU 6\r
+SCSI_Noise__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__3__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__3__SHIFT EQU 6\r
+SCSI_Noise__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__4__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__4__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__4__MASK EQU 0x20\r
+SCSI_Noise__4__PC EQU CYREG_PRT6_PC5\r
+SCSI_Noise__4__PORT EQU 6\r
+SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__4__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__4__SHIFT EQU 5\r
+SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__ACK__MASK EQU 0x20\r
+SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC5\r
+SCSI_Noise__ACK__PORT EQU 6\r
+SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__ACK__SHIFT EQU 5\r
+SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__ATN__AG EQU CYREG_PRT12_AG\r
+SCSI_Noise__ATN__BIE EQU CYREG_PRT12_BIE\r
+SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_Noise__ATN__BYP EQU CYREG_PRT12_BYP\r
+SCSI_Noise__ATN__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_Noise__ATN__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_Noise__ATN__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_Noise__ATN__DR EQU CYREG_PRT12_DR\r
+SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_Noise__ATN__MASK EQU 0x20\r
+SCSI_Noise__ATN__PC EQU CYREG_PRT12_PC5\r
+SCSI_Noise__ATN__PORT EQU 12\r
+SCSI_Noise__ATN__PRT EQU CYREG_PRT12_PRT\r
+SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_Noise__ATN__PS EQU CYREG_PRT12_PS\r
+SCSI_Noise__ATN__SHIFT EQU 5\r
+SCSI_Noise__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_Noise__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_Noise__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_Noise__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_Noise__ATN__SLW EQU CYREG_PRT12_SLW\r
+SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__BSY__MASK EQU 0x10\r
+SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC4\r
+SCSI_Noise__BSY__PORT EQU 6\r
+SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__BSY__SHIFT EQU 4\r
+SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__RST__AG EQU CYREG_PRT6_AG\r
+SCSI_Noise__RST__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Noise__RST__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Noise__RST__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Noise__RST__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Noise__RST__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Noise__RST__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Noise__RST__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Noise__RST__DR EQU CYREG_PRT6_DR\r
+SCSI_Noise__RST__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Noise__RST__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Noise__RST__MASK EQU 0x40\r
+SCSI_Noise__RST__PC EQU CYREG_PRT6_PC6\r
+SCSI_Noise__RST__PORT EQU 6\r
+SCSI_Noise__RST__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Noise__RST__PS EQU CYREG_PRT6_PS\r
+SCSI_Noise__RST__SHIFT EQU 6\r
+SCSI_Noise__RST__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Noise__SEL__AG EQU CYREG_PRT5_AG\r
+SCSI_Noise__SEL__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_Noise__SEL__BIE EQU CYREG_PRT5_BIE\r
+SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_Noise__SEL__BYP EQU CYREG_PRT5_BYP\r
+SCSI_Noise__SEL__CTL EQU CYREG_PRT5_CTL\r
+SCSI_Noise__SEL__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_Noise__SEL__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_Noise__SEL__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_Noise__SEL__DR EQU CYREG_PRT5_DR\r
+SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_Noise__SEL__MASK EQU 0x01\r
+SCSI_Noise__SEL__PC EQU CYREG_PRT5_PC0\r
+SCSI_Noise__SEL__PORT EQU 5\r
+SCSI_Noise__SEL__PRT EQU CYREG_PRT5_PRT\r
+SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_Noise__SEL__PS EQU CYREG_PRT5_PS\r
+SCSI_Noise__SEL__SHIFT EQU 0\r
+SCSI_Noise__SEL__SLW EQU CYREG_PRT5_SLW\r
+\r
+; scsiTarget\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB05_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB05_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB05_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB05_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB05_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB05_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
+scsiTarget_StatusReg__0__MASK EQU 0x01\r
+scsiTarget_StatusReg__0__POS EQU 0\r
+scsiTarget_StatusReg__1__MASK EQU 0x02\r
+scsiTarget_StatusReg__1__POS EQU 1\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
+scsiTarget_StatusReg__2__MASK EQU 0x04\r
+scsiTarget_StatusReg__2__POS EQU 2\r
+scsiTarget_StatusReg__3__MASK EQU 0x08\r
+scsiTarget_StatusReg__3__POS EQU 3\r
+scsiTarget_StatusReg__4__MASK EQU 0x10\r
+scsiTarget_StatusReg__4__POS EQU 4\r
+scsiTarget_StatusReg__MASK EQU 0x1F\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL\r
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
\r
-; SD_DAT2\r
-SD_DAT2__0__MASK EQU 0x20\r
-SD_DAT2__0__PC EQU CYREG_PRT3_PC5\r
-SD_DAT2__0__PORT EQU 3\r
-SD_DAT2__0__SHIFT EQU 5\r
-SD_DAT2__AG EQU CYREG_PRT3_AG\r
-SD_DAT2__AMUX EQU CYREG_PRT3_AMUX\r
-SD_DAT2__BIE EQU CYREG_PRT3_BIE\r
-SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_DAT2__BYP EQU CYREG_PRT3_BYP\r
-SD_DAT2__CTL EQU CYREG_PRT3_CTL\r
-SD_DAT2__DM0 EQU CYREG_PRT3_DM0\r
-SD_DAT2__DM1 EQU CYREG_PRT3_DM1\r
-SD_DAT2__DM2 EQU CYREG_PRT3_DM2\r
-SD_DAT2__DR EQU CYREG_PRT3_DR\r
-SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_DAT2__MASK EQU 0x20\r
-SD_DAT2__PORT EQU 3\r
-SD_DAT2__PRT EQU CYREG_PRT3_PRT\r
-SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_DAT2__PS EQU CYREG_PRT3_PS\r
-SD_DAT2__SHIFT EQU 5\r
-SD_DAT2__SLW EQU CYREG_PRT3_SLW\r
+; Debug_Timer_Interrupt\r
+Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+Debug_Timer_Interrupt__INTC_MASK EQU 0x02\r
+Debug_Timer_Interrupt__INTC_NUMBER EQU 1\r
+Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7\r
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
+Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
-; SD_MISO\r
-SD_MISO__0__MASK EQU 0x02\r
-SD_MISO__0__PC EQU CYREG_PRT3_PC1\r
-SD_MISO__0__PORT EQU 3\r
-SD_MISO__0__SHIFT EQU 1\r
-SD_MISO__AG EQU CYREG_PRT3_AG\r
-SD_MISO__AMUX EQU CYREG_PRT3_AMUX\r
-SD_MISO__BIE EQU CYREG_PRT3_BIE\r
-SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_MISO__BYP EQU CYREG_PRT3_BYP\r
-SD_MISO__CTL EQU CYREG_PRT3_CTL\r
-SD_MISO__DM0 EQU CYREG_PRT3_DM0\r
-SD_MISO__DM1 EQU CYREG_PRT3_DM1\r
-SD_MISO__DM2 EQU CYREG_PRT3_DM2\r
-SD_MISO__DR EQU CYREG_PRT3_DR\r
-SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_MISO__MASK EQU 0x02\r
-SD_MISO__PORT EQU 3\r
-SD_MISO__PRT EQU CYREG_PRT3_PRT\r
-SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_MISO__PS EQU CYREG_PRT3_PS\r
-SD_MISO__SHIFT EQU 1\r
-SD_MISO__SLW EQU CYREG_PRT3_SLW\r
+; Debug_Timer_TimerHW\r
+Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0\r
+Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1\r
+Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0\r
+Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1\r
+Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2\r
+Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0\r
+Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1\r
+Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0\r
+Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1\r
+Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3\r
+Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01\r
+Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3\r
+Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01\r
+Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0\r
+Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1\r
+Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0\r
+\r
+; SCSI_RX_DMA\r
+SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_RX_DMA__DRQ_NUMBER EQU 0\r
+SCSI_RX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_RX_DMA__PRIORITY EQU 2\r
+SCSI_RX_DMA__TERMIN_EN EQU 0\r
+SCSI_RX_DMA__TERMIN_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_RX_DMA__TERMOUT0_SEL EQU 0\r
+SCSI_RX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_RX_DMA__TERMOUT1_SEL EQU 0\r
+\r
+; SCSI_RX_DMA_COMPLETE\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01\r
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SCSI_TX_DMA\r
+SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0\r
+SCSI_TX_DMA__DRQ_NUMBER EQU 1\r
+SCSI_TX_DMA__NUMBEROF_TDS EQU 0\r
+SCSI_TX_DMA__PRIORITY EQU 2\r
+SCSI_TX_DMA__TERMIN_EN EQU 0\r
+SCSI_TX_DMA__TERMIN_SEL EQU 0\r
+SCSI_TX_DMA__TERMOUT0_EN EQU 1\r
+SCSI_TX_DMA__TERMOUT0_SEL EQU 1\r
+SCSI_TX_DMA__TERMOUT1_EN EQU 0\r
+SCSI_TX_DMA__TERMOUT1_SEL EQU 0\r
+\r
+; SCSI_TX_DMA_COMPLETE\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08\r
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7\r
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SD_Data_Clk\r
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2\r
+SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
+SD_Data_Clk__INDEX EQU 0x00\r
+SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SD_Data_Clk__PM_ACT_MSK EQU 0x01\r
+SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
\r
-; SD_MOSI\r
-SD_MOSI__0__MASK EQU 0x08\r
-SD_MOSI__0__PC EQU CYREG_PRT3_PC3\r
-SD_MOSI__0__PORT EQU 3\r
-SD_MOSI__0__SHIFT EQU 3\r
-SD_MOSI__AG EQU CYREG_PRT3_AG\r
-SD_MOSI__AMUX EQU CYREG_PRT3_AMUX\r
-SD_MOSI__BIE EQU CYREG_PRT3_BIE\r
-SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_MOSI__BYP EQU CYREG_PRT3_BYP\r
-SD_MOSI__CTL EQU CYREG_PRT3_CTL\r
-SD_MOSI__DM0 EQU CYREG_PRT3_DM0\r
-SD_MOSI__DM1 EQU CYREG_PRT3_DM1\r
-SD_MOSI__DM2 EQU CYREG_PRT3_DM2\r
-SD_MOSI__DR EQU CYREG_PRT3_DR\r
-SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_MOSI__MASK EQU 0x08\r
-SD_MOSI__PORT EQU 3\r
-SD_MOSI__PRT EQU CYREG_PRT3_PRT\r
-SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_MOSI__PS EQU CYREG_PRT3_PS\r
-SD_MOSI__SHIFT EQU 3\r
-SD_MOSI__SLW EQU CYREG_PRT3_SLW\r
+; timer_clock\r
+timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0\r
+timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1\r
+timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2\r
+timer_clock__CFG2_SRC_SEL_MASK EQU 0x07\r
+timer_clock__INDEX EQU 0x02\r
+timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+timer_clock__PM_ACT_MSK EQU 0x04\r
+timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+timer_clock__PM_STBY_MSK EQU 0x04\r
\r
-; SD_SCK\r
-SD_SCK__0__MASK EQU 0x04\r
-SD_SCK__0__PC EQU CYREG_PRT3_PC2\r
-SD_SCK__0__PORT EQU 3\r
-SD_SCK__0__SHIFT EQU 2\r
-SD_SCK__AG EQU CYREG_PRT3_AG\r
-SD_SCK__AMUX EQU CYREG_PRT3_AMUX\r
-SD_SCK__BIE EQU CYREG_PRT3_BIE\r
-SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_SCK__BYP EQU CYREG_PRT3_BYP\r
-SD_SCK__CTL EQU CYREG_PRT3_CTL\r
-SD_SCK__DM0 EQU CYREG_PRT3_DM0\r
-SD_SCK__DM1 EQU CYREG_PRT3_DM1\r
-SD_SCK__DM2 EQU CYREG_PRT3_DM2\r
-SD_SCK__DR EQU CYREG_PRT3_DR\r
-SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_SCK__MASK EQU 0x04\r
-SD_SCK__PORT EQU 3\r
-SD_SCK__PRT EQU CYREG_PRT3_PRT\r
-SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_SCK__PS EQU CYREG_PRT3_PS\r
-SD_SCK__SHIFT EQU 2\r
-SD_SCK__SLW EQU CYREG_PRT3_SLW\r
+; SCSI_RST_ISR\r
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SCSI_RST_ISR__INTC_MASK EQU 0x04\r
+SCSI_RST_ISR__INTC_NUMBER EQU 2\r
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7\r
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2\r
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
-; SD_CD\r
-SD_CD__0__MASK EQU 0x40\r
-SD_CD__0__PC EQU CYREG_PRT3_PC6\r
-SD_CD__0__PORT EQU 3\r
-SD_CD__0__SHIFT EQU 6\r
-SD_CD__AG EQU CYREG_PRT3_AG\r
-SD_CD__AMUX EQU CYREG_PRT3_AMUX\r
-SD_CD__BIE EQU CYREG_PRT3_BIE\r
-SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_CD__BYP EQU CYREG_PRT3_BYP\r
-SD_CD__CTL EQU CYREG_PRT3_CTL\r
-SD_CD__DM0 EQU CYREG_PRT3_DM0\r
-SD_CD__DM1 EQU CYREG_PRT3_DM1\r
-SD_CD__DM2 EQU CYREG_PRT3_DM2\r
-SD_CD__DR EQU CYREG_PRT3_DR\r
-SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_CD__MASK EQU 0x40\r
-SD_CD__PORT EQU 3\r
-SD_CD__PRT EQU CYREG_PRT3_PRT\r
-SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_CD__PS EQU CYREG_PRT3_PS\r
-SD_CD__SHIFT EQU 6\r
-SD_CD__SLW EQU CYREG_PRT3_SLW\r
+; SCSI_Filtered\r
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0\r
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02\r
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST\r
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04\r
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2\r
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08\r
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3\r
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10\r
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4\r
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F\r
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK\r
+SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST\r
\r
-; SD_CS\r
-SD_CS__0__MASK EQU 0x10\r
-SD_CS__0__PC EQU CYREG_PRT3_PC4\r
-SD_CS__0__PORT EQU 3\r
-SD_CS__0__SHIFT EQU 4\r
-SD_CS__AG EQU CYREG_PRT3_AG\r
-SD_CS__AMUX EQU CYREG_PRT3_AMUX\r
-SD_CS__BIE EQU CYREG_PRT3_BIE\r
-SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_CS__BYP EQU CYREG_PRT3_BYP\r
-SD_CS__CTL EQU CYREG_PRT3_CTL\r
-SD_CS__DM0 EQU CYREG_PRT3_DM0\r
-SD_CS__DM1 EQU CYREG_PRT3_DM1\r
-SD_CS__DM2 EQU CYREG_PRT3_DM2\r
-SD_CS__DR EQU CYREG_PRT3_DR\r
-SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_CS__MASK EQU 0x10\r
-SD_CS__PORT EQU 3\r
-SD_CS__PRT EQU CYREG_PRT3_PRT\r
-SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_CS__PS EQU CYREG_PRT3_PS\r
-SD_CS__SHIFT EQU 4\r
-SD_CS__SLW EQU CYREG_PRT3_SLW\r
+; SCSI_CTL_PHASE\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
\r
-; LED1\r
-LED1__0__MASK EQU 0x08\r
-LED1__0__PC EQU CYREG_PRT12_PC3\r
-LED1__0__PORT EQU 12\r
-LED1__0__SHIFT EQU 3\r
-LED1__AG EQU CYREG_PRT12_AG\r
-LED1__BIE EQU CYREG_PRT12_BIE\r
-LED1__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
-LED1__BYP EQU CYREG_PRT12_BYP\r
-LED1__DM0 EQU CYREG_PRT12_DM0\r
-LED1__DM1 EQU CYREG_PRT12_DM1\r
-LED1__DM2 EQU CYREG_PRT12_DM2\r
-LED1__DR EQU CYREG_PRT12_DR\r
-LED1__INP_DIS EQU CYREG_PRT12_INP_DIS\r
-LED1__MASK EQU 0x08\r
-LED1__PORT EQU 12\r
-LED1__PRT EQU CYREG_PRT12_PRT\r
-LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
-LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
-LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
-LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
-LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
-LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
-LED1__PS EQU CYREG_PRT12_PS\r
-LED1__SHIFT EQU 3\r
-LED1__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
-LED1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
-LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
-LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
-LED1__SLW EQU CYREG_PRT12_SLW\r
+; SCSI_Parity_Error\r
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB06_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB06_ST\r
\r
; Miscellaneous\r
-; -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release\r
-CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6\r
-CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0\r
-CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0\r
-CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1\r
-CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0\r
-CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
-CYDEV_CHIP_MEMBER_5B EQU 4\r
-CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
-CYDEV_CHIP_DIE_PSOC5LP EQU 4\r
-CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP\r
BCLK__BUS_CLK__HZ EQU 50000000\r
BCLK__BUS_CLK__KHZ EQU 50000\r
BCLK__BUS_CLK__MHZ EQU 50\r
-CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT\r
CYDEV_CHIP_DIE_LEOPARD EQU 1\r
-CYDEV_CHIP_DIE_PANTHER EQU 3\r
-CYDEV_CHIP_DIE_PSOC4A EQU 2\r
+CYDEV_CHIP_DIE_PANTHER EQU 6\r
+CYDEV_CHIP_DIE_PSOC4A EQU 3\r
+CYDEV_CHIP_DIE_PSOC5LP EQU 5\r
CYDEV_CHIP_DIE_UNKNOWN EQU 0\r
CYDEV_CHIP_FAMILY_PSOC3 EQU 1\r
CYDEV_CHIP_FAMILY_PSOC4 EQU 2\r
+CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0\r
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5\r
CYDEV_CHIP_JTAG_ID EQU 0x2E133069\r
CYDEV_CHIP_MEMBER_3A EQU 1\r
-CYDEV_CHIP_MEMBER_4A EQU 2\r
-CYDEV_CHIP_MEMBER_5A EQU 3\r
+CYDEV_CHIP_MEMBER_4A EQU 3\r
+CYDEV_CHIP_MEMBER_4D EQU 2\r
+CYDEV_CHIP_MEMBER_4F EQU 4\r
+CYDEV_CHIP_MEMBER_5A EQU 6\r
+CYDEV_CHIP_MEMBER_5B EQU 5\r
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0\r
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B\r
+CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED\r
+CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT\r
+CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0\r
+CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1\r
+CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3\r
+CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3\r
+CYDEV_CHIP_REV_PANTHER_ES0 EQU 0\r
+CYDEV_CHIP_REV_PANTHER_ES1 EQU 1\r
+CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1\r
+CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17\r
+CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17\r
+CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0\r
+CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_3A_ES1 EQU 0\r
CYDEV_CHIP_REVISION_3A_ES2 EQU 1\r
CYDEV_CHIP_REVISION_3A_ES3 EQU 3\r
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3\r
CYDEV_CHIP_REVISION_4A_ES0 EQU 17\r
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17\r
+CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_5A_ES0 EQU 0\r
CYDEV_CHIP_REVISION_5A_ES1 EQU 1\r
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1\r
CYDEV_CHIP_REVISION_5B_ES0 EQU 0\r
+CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION\r
-CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION\r
-CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0\r
-CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1\r
-CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3\r
-CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3\r
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0\r
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1\r
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1\r
-CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17\r
-CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17\r
-CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0\r
+CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED\r
+CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1\r
+CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0\r
+CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
+CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1\r
+CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2\r
CYDEV_CONFIGURATION_COMPRESSED EQU 1\r
CYDEV_CONFIGURATION_DMA EQU 0\r
CYDEV_CONFIGURATION_ECC EQU 0\r
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED\r
+CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0\r
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED\r
CYDEV_CONFIGURATION_MODE_DMA EQU 2\r
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1\r
-CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
-CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1\r
-CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2\r
-CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV\r
+CYDEV_DEBUG_ENABLE_MASK EQU 0x20\r
+CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG\r
CYDEV_DEBUGGING_DPS_Disable EQU 3\r
CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1\r
CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0\r
CYDEV_DEBUGGING_DPS_SWD EQU 2\r
+CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6\r
+CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV\r
CYDEV_DEBUGGING_ENABLE EQU 1\r
CYDEV_DEBUGGING_XRES EQU 0\r
-CYDEV_DEBUG_ENABLE_MASK EQU 0x20\r
-CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG\r
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24\r
CYDEV_ECC_ENABLE EQU 0\r
CYDEV_HEAP_SIZE EQU 0x0400\r
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3\r
CYDEV_PROJ_TYPE_STANDARD EQU 0\r
CYDEV_PROTECTION_ENABLE EQU 0\r
-CYDEV_STACK_SIZE EQU 0x2000\r
+CYDEV_STACK_SIZE EQU 0x1000\r
CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1\r
CYDEV_USE_BUNDLED_CMSIS EQU 1\r
CYDEV_VARIABLE_VDDA EQU 0\r
CYDEV_VDDIO1_MV EQU 5000\r
CYDEV_VDDIO2_MV EQU 5000\r
CYDEV_VDDIO3_MV EQU 3300\r
-CYDEV_VIO0 EQU 5\r
CYDEV_VIO0_MV EQU 5000\r
-CYDEV_VIO1 EQU 5\r
CYDEV_VIO1_MV EQU 5000\r
-CYDEV_VIO2 EQU 5\r
CYDEV_VIO2_MV EQU 5000\r
CYDEV_VIO3_MV EQU 3300\r
+CYIPBLOCK_ARM_CM3_VERSION EQU 0\r
+CYIPBLOCK_P3_ANAIF_VERSION EQU 0\r
+CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0\r
+CYIPBLOCK_P3_COMP_VERSION EQU 0\r
+CYIPBLOCK_P3_DMA_VERSION EQU 0\r
+CYIPBLOCK_P3_DRQ_VERSION EQU 0\r
+CYIPBLOCK_P3_EMIF_VERSION EQU 0\r
+CYIPBLOCK_P3_I2C_VERSION EQU 0\r
+CYIPBLOCK_P3_LCD_VERSION EQU 0\r
+CYIPBLOCK_P3_LPF_VERSION EQU 0\r
+CYIPBLOCK_P3_PM_VERSION EQU 0\r
+CYIPBLOCK_P3_TIMER_VERSION EQU 0\r
+CYIPBLOCK_P3_USB_VERSION EQU 0\r
+CYIPBLOCK_P3_VIDAC_VERSION EQU 0\r
+CYIPBLOCK_P3_VREF_VERSION EQU 0\r
+CYIPBLOCK_S8_GPIO_VERSION EQU 0\r
+CYIPBLOCK_S8_IRQ_VERSION EQU 0\r
+CYIPBLOCK_S8_SAR_VERSION EQU 0\r
+CYIPBLOCK_S8_SIO_VERSION EQU 0\r
+CYIPBLOCK_S8_UDB_VERSION EQU 0\r
DMA_CHANNELS_USED__MASK0 EQU 0x0000000F\r
CYDEV_BOOTLOADER_ENABLE EQU 0\r
ENDIF\r
/*******************************************************************************\r
* FILENAME: cymetadata.c\r
* \r
-* PSoC Creator 3.0 Component Pack 7\r
+* PSoC Creator 3.1\r
*\r
* DESCRIPTION:\r
* This file defines all extra memory spaces that need to be included.\r
const uint8 cy_meta_loadable[] = {\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
- 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x01u, 0x04u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x05u, 0x04u,\r
0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
/*******************************************************************************\r
* File Name: cypins.h\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
-* This file contains the function prototypes and constants used for port/pin\r
+* This file contains the function prototypes and constants used for a port/pin\r
* in access and control.\r
*\r
* Note:\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
* Note that this only has an effect for pins configured as software pins that\r
* are not driven by hardware.\r
*\r
+* The macro operation is not atomic. It is not guaranteed that shared register\r
+* will remain uncorrupted during simultaneous read-modify-write operations\r
+* performed by two threads (main and interrupt threads). To guarantee data\r
+* integrity in such cases, the macro should be invoked while the specific\r
+* interrupt is disabled or within critical section (all interrupts are\r
+* disabled).\r
+*\r
* Parameters:\r
* pinPC: Port pin configuration register (uint16).\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
********************************************************************************\r
*\r
* Summary:\r
-* This macro sets the state of the specified pin to 0\r
+* This macro sets the state of the specified pin to 0.\r
+*\r
+* The macro operation is not atomic. It is not guaranteed that shared register\r
+* will remain uncorrupted during simultaneous read-modify-write operations\r
+* performed by two threads (main and interrupt threads). To guarantee data\r
+* integrity in such cases, the macro should be invoked while the specific\r
+* interrupt is disabled or within critical section (all interrupts are\r
+* disabled).\r
*\r
* Parameters:\r
* pinPC: address of a Pin Configuration register.\r
* Summary:\r
* Sets the drive mode for the pin (DM).\r
*\r
+* The macro operation is not atomic. It is not guaranteed that shared register\r
+* will remain uncorrupted during simultaneous read-modify-write operations\r
+* performed by two threads (main and interrupt threads). To guarantee data\r
+* integrity in such cases, the macro should be invoked while the specific\r
+* interrupt is disabled or within critical section (all interrupts are\r
+* disabled).\r
+*\r
* Parameters:\r
* pinPC: Port pin configuration register (uint16)\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
*\r
*\r
* Return:\r
-* mode: Current drive mode for the pin\r
+* mode: The current drive mode for the pin\r
*\r
* Define Source\r
* PIN_DM_ALG_HIZ Analog HiZ\r
********************************************************************************\r
*\r
* Summary:\r
-* Set the slew rate for the pin to fast edge rate.\r
+* Set the slew rate for the pin to fast the edge rate.\r
* Note that this only applies for pins in strong output drive modes,\r
* not to resistive drive modes.\r
*\r
+* The macro operation is not atomic. It is not guaranteed that shared register\r
+* will remain uncorrupted during simultaneous read-modify-write operations\r
+* performed by two threads (main and interrupt threads). To guarantee data\r
+* integrity in such cases, the macro should be invoked while the specific\r
+* interrupt is disabled or within critical section (all interrupts are\r
+* disabled).\r
+*\r
* Parameters:\r
* pinPC: address of a Pin Configuration register.\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
********************************************************************************\r
*\r
* Summary:\r
-* Set the slew rate for the pin to slow edge rate.\r
+* Set the slew rate for the pin to slow the edge rate.\r
* Note that this only applies for pins in strong output drive modes,\r
* not to resistive drive modes.\r
*\r
+* The macro operation is not atomic. It is not guaranteed that shared register\r
+* will remain uncorrupted during simultaneous read-modify-write operations\r
+* performed by two threads (main and interrupt threads). To guarantee data\r
+* integrity in such cases, the macro should be invoked while the specific\r
+* interrupt is disabled or within critical section (all interrupts are\r
+* disabled).\r
+*\r
* Parameters:\r
* pinPC: address of a Pin Configuration register.\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30\r
+* The following code is OBSOLETE and must not be used.\r
+*\r
+* If the obsoleted macro definitions intended for use in the application use the\r
+* following scheme, redefine your own versions of these definitions:\r
+* #ifdef <OBSOLETED_DEFINE>\r
+* #undef <OBSOLETED_DEFINE>\r
+* #define <OBSOLETED_DEFINE> (<New Value>)\r
+* #endif\r
+*\r
+* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* used in the application and their modification might lead to unexpected\r
+* consequences.\r
*******************************************************************************/\r
#define PC_DRIVE_MODE_SHIFT (CY_PINS_PC_DRIVE_MODE_SHIFT)\r
#define PC_DRIVE_MODE_MASK (CY_PINS_PC_DRIVE_MODE_MASK)\r
/*******************************************************************************\r
* FILENAME: cytypes.h\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* CyTypes provides register access macros and approved types for use in\r
* data the correct way.\r
*\r
* Register Access macros and functions perform their operations on an\r
-* input of type pointer to void. The arguments passed to it should be\r
+* input of the type pointer to void. The arguments passed to it should be\r
* pointers to the type associated with the register size.\r
* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value)\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
#if defined( __ICCARM__ )\r
/* Suppress warning for multiple volatile variables in an expression. */\r
- /* This is common in component code and the usage is not order dependent. */\r
+ /* This is common in component code and usage is not order dependent. */\r
#pragma diag_suppress=Pa082\r
#endif /* defined( __ICCARM__ ) */\r
\r
/*******************************************************************************\r
* MEMBER encodes both the family and the detailed architecture\r
*******************************************************************************/\r
-#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)\r
#ifdef CYDEV_CHIP_MEMBER_4D\r
- #define CY_PSOC4D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)\r
- #define CY_PSOC4SF (CY_PSOC4D)\r
+ #define CY_PSOC4_4000 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)\r
#else\r
- #define CY_PSOC4D (0u != 0u)\r
- #define CY_PSOC4SF (CY_PSOC4D)\r
+ #define CY_PSOC4_4000 (0u != 0u)\r
#endif /* CYDEV_CHIP_MEMBER_4D */\r
\r
-#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)\r
-#ifdef CYDEV_CHIP_MEMBER_5B\r
- #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)\r
+#define CY_PSOC4_4100 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)\r
+#define CY_PSOC4_4200 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)\r
+\r
+#ifdef CYDEV_CHIP_MEMBER_4F\r
+ #define CY_PSOC4_4100BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F)\r
+ #define CY_PSOC4_4200BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F)\r
#else\r
- #define CY_PSOC5LP (0u != 0u)\r
-#endif /* CYDEV_CHIP_MEMBER_5B */\r
+ #define CY_PSOC4_4100BL (0u != 0u)\r
+ #define CY_PSOC4_4200BL (0u != 0u)\r
+#endif /* CYDEV_CHIP_MEMBER_4F */\r
\r
\r
/*******************************************************************************\r
-* UDB revisions\r
+* IP blocks\r
*******************************************************************************/\r
-#define CY_UDB_V0 (CY_PSOC5A)\r
-#define CY_UDB_V1 (!CY_UDB_V0)\r
+#if (CY_PSOC4)\r
+\r
+ /* Using SRSSv2 or SRS-Lite */\r
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
+ #define CY_IP_SRSSV2 (0u == 0u)\r
+ #define CY_IP_SRSSLT (!CY_IP_SRSSV2)\r
+ #else\r
+ #define CY_IP_SRSSV2 (0u != 0u)\r
+ #define CY_IP_SRSSLT (!CY_IP_SRSSV2)\r
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+\r
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
+ #define CY_IP_CPUSSV2 (0u != 0u)\r
+ #define CY_IP_CPUSS (0u == 0u)\r
+ #else\r
+ #define CY_IP_CPUSSV2 (0u != 0u)\r
+ #define CY_IP_CPUSS (!CY_IP_CPUSSV2)\r
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+\r
+ /* Product uses FLASH-Lite or regular FLASH */\r
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
+ #define CY_IP_FMLT (0u != 0u) /* FLASH-Lite */\r
+ #define CY_IP_FM (!CY_IP_FMLT) /* Regular FLASH */\r
+ #else\r
+ #define CY_IP_FMLT (-1u != 0u)\r
+ #define CY_IP_FM (!CY_IP_FMLT)\r
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+\r
+ /* Number of interrupt request inputs to CM0 */\r
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
+ #define CY_IP_INT_NR (32u)\r
+ #else\r
+ #define CY_IP_INT_NR (-1u)\r
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+\r
+ /* Number of Flash macros used in the device (0, 1 or 2) */\r
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
+ #define CY_IP_FLASH_MACROS (1u)\r
+ #else\r
+ #define CY_IP_FLASH_MACROS (-1u)\r
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+\r
+\r
+ /* Number of Flash macros used in the device (0, 1 or 2) */\r
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
+ #define CY_IP_BLESS (0u != 0u)\r
+ #else\r
+ #define CY_IP_BLESS (0u != 0u)\r
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+\r
+ /* Watch Crystal Oscillator (WCO) is present (32kHz) */\r
+ #if (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200)\r
+ #define CY_IP_WCO (0u != 0u)\r
+ #elif CY_IP_BLESS || defined (CYIPBLOCK_s8swco_VERSION)\r
+ #define CY_IP_WCO (0u == 0u)\r
+ #elif (CY_IP_SRSSV2)\r
+ #define CY_IP_WCO (-1u)\r
+ #else\r
+ #define CY_IP_WCO (0u != 0u)\r
+ #endif /* (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+\r
+#endif /* (CY_PSOC4) */\r
+\r
+\r
+/*******************************************************************************\r
+* The components version defines. Available started from cy_boot 4.20\r
+* Use the following construction in order to identify cy_boot version:\r
+* (defined(CY_BOOT_VERSION) && CY_BOOT_VERSION >= CY_BOOT_4_20)\r
+*******************************************************************************/\r
+#define CY_BOOT_4_20 (420u)\r
+#define CY_BOOT_VERSION (CY_BOOT_4_20)\r
\r
\r
/*******************************************************************************\r
\r
#endif /* (!CY_PSOC3) */\r
\r
-/* Signed or unsigned depending on the compiler selection */\r
+/* Signed or unsigned depending on compiler selection */\r
typedef char char8;\r
\r
\r
\r
#else\r
\r
- /* Prototype for function to set a 24-bit register. Located at cyutils.c */\r
+ /* Prototype for function to set 24-bit register. Located at cyutils.c */\r
extern void CySetReg24(uint32 volatile * addr, uint32 value);\r
\r
#if(CY_PSOC4)\r
#define XDATA\r
\r
#if defined(__ARMCC_VERSION)\r
+\r
#define CY_NOINIT __attribute__ ((section(".noinit"), zero_init))\r
#define CY_NORETURN __attribute__ ((noreturn))\r
#define CY_SECTION(name) __attribute__ ((section(name)))\r
+\r
+ /* Specifies a minimum alignment (in bytes) for variables of the\r
+ * specified type.\r
+ */\r
#define CY_ALIGN(align) __align(align)\r
+\r
+\r
+ /* Attached to an enum, struct, or union type definition, specified that\r
+ * the minimum required memory be used to represent the type.\r
+ */\r
+ #define CY_PACKED\r
+ #define CY_PACKED_ATTR __attribute__ ((packed))\r
+ #define CY_INLINE __inline\r
#elif defined (__GNUC__)\r
+\r
#define CY_NOINIT __attribute__ ((section(".noinit")))\r
#define CY_NORETURN __attribute__ ((noreturn))\r
#define CY_SECTION(name) __attribute__ ((section(name)))\r
#define CY_ALIGN(align) __attribute__ ((aligned(align)))\r
+ #define CY_PACKED\r
+ #define CY_PACKED_ATTR __attribute__ ((packed))\r
+ #define CY_INLINE inline\r
#elif defined (__ICCARM__)\r
+\r
#define CY_NOINIT __no_init\r
#define CY_NORETURN __noreturn\r
+ #define CY_PACKED __packed\r
+ #define CY_PACKED_ATTR\r
+ #define CY_INLINE inline\r
#endif /* (__ARMCC_VERSION) */\r
\r
#endif /* (CY_PSOC3) */\r
\r
#if(CY_PSOC3)\r
\r
- /* 8051 naturally returns an 8 bit value. */\r
+ /* 8051 naturally returns 8 bit value. */\r
typedef unsigned char cystatus;\r
\r
#else\r
\r
- /* ARM naturally returns a 32 bit value. */\r
+ /* ARM naturally returns 32 bit value. */\r
typedef unsigned long cystatus;\r
\r
#endif /* (CY_PSOC3) */\r
* KEIL for the 8051 is a big endian compiler This causes problems as the on chip\r
* registers are little endian. Byte swapping for two and four byte registers is\r
* implemented in the functions below. This will require conditional compilation\r
- * of function prototypes in code.\r
+ * of function prototypes in the code.\r
*******************************************************************************/\r
\r
/* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */\r
* Data manipulation defines\r
*******************************************************************************/\r
\r
-/* Get 8 bits of a 16 bit value. */\r
+/* Get 8 bits of 16 bit value. */\r
#define LO8(x) ((uint8) ((x) & 0xFFu))\r
#define HI8(x) ((uint8) ((uint16)(x) >> 8))\r
\r
-/* Get 16 bits of a 32 bit value. */\r
+/* Get 16 bits of 32 bit value. */\r
#define LO16(x) ((uint16) ((x) & 0xFFFFu))\r
#define HI16(x) ((uint16) ((uint32)(x) >> 16))\r
\r
-/* Swap the byte ordering of a 32 bit value */\r
+/* Swap the byte ordering of 32 bit value */\r
#define CYSWAP_ENDIAN32(x) \\r
((uint32)(((x) >> 24) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24)))\r
\r
-/* Swap the byte ordering of a 16 bit value */\r
+/* Swap the byte ordering of 16 bit value */\r
#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | ((x) >> 8)))\r
\r
\r
/*******************************************************************************\r
-* Defines the standard return values used PSoC content. A function is\r
+* Defines the standard return values used in PSoC content. A function is\r
* not limited to these return values but can use them when returning standard\r
* error values. Return values can be overloaded if documented in the function\r
* header. On the 8051 a function can use a larger return type but still use the\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.10\r
+* The following code is OBSOLETE and must not be used starting from cy_boot 3.10\r
+*\r
+* If the obsoleted macro definitions intended for use in the application use the\r
+* following scheme, redefine your own versions of these definitions:\r
+* #ifdef <OBSOLETED_DEFINE>\r
+* #undef <OBSOLETED_DEFINE>\r
+* #define <OBSOLETED_DEFINE> (<New Value>)\r
+* #endif\r
+*\r
+* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* used in the application and their modification might lead to unexpected\r
+* consequences.\r
*******************************************************************************/\r
+#define CY_UDB_V0 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)\r
+#define CY_UDB_V1 (!CY_UDB_V0)\r
+#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)\r
+#ifdef CYDEV_CHIP_MEMBER_4D\r
+ #define CY_PSOC4D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)\r
+ #define CY_PSOC4SF (CY_PSOC4D)\r
+#else\r
+ #define CY_PSOC4D (0u != 0u)\r
+ #define CY_PSOC4SF (CY_PSOC4D)\r
+#endif /* CYDEV_CHIP_MEMBER_4D */\r
+#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)\r
+#ifdef CYDEV_CHIP_MEMBER_5B\r
+ #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)\r
+#else\r
+ #define CY_PSOC5LP (0u != 0u)\r
+#endif /* CYDEV_CHIP_MEMBER_5B */\r
+\r
+#if (!CY_PSOC4)\r
+\r
+ /* Device is PSoC 3 and the revision is ES2 or earlier */\r
+ #define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \\r
+ (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2))\r
\r
-/* Device is PSoC 3 and the revision is ES2 or earlier */\r
-#define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \\r
- (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2))\r
+ /* Device is PSoC 3 and the revision is ES3 or later */\r
+ #define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \\r
+ (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3))\r
\r
-/* Device is PSoC 3 and the revision is ES3 or later */\r
-#define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \\r
- (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3))\r
+ /* Device is PSoC 5 and the revision is ES1 or earlier */\r
+ #define CY_PSOC5_ES1 (CY_PSOC5A && \\r
+ (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1))\r
\r
-/* Device is PSoC 5 and the revision is ES1 or earlier */\r
-#define CY_PSOC5_ES1 (CY_PSOC5A && \\r
- (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1))\r
+ /* Device is PSoC 5 and the revision is ES2 or later */\r
+ #define CY_PSOC5_ES2 (CY_PSOC5A && \\r
+ (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1))\r
\r
-/* Device is PSoC 5 and the revision is ES2 or later */\r
-#define CY_PSOC5_ES2 (CY_PSOC5A && \\r
- (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1))\r
+#endif /* (!CY_PSOC4) */\r
\r
#endif /* CY_BOOT_CYTYPES_H */\r
\r
/*******************************************************************************\r
* FILENAME: cyutils.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
-* CyUtils provides function to handle 24-bit value writes.\r
+* CyUtils provides a function to handle 24-bit value writes.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
****************************************************************************\r
*\r
* Summary:\r
- * Writes the 24-bit value to the specified register.\r
+ * Writes a 24-bit value to the specified register.\r
*\r
* Parameters:\r
- * addr : adress where data must be written\r
- * value: data that must be written\r
+ * addr : the address where data must be written.\r
+ * value: the data that must be written.\r
*\r
* Return:\r
* None\r
* Reads the 24-bit value from the specified register.\r
*\r
* Parameters:\r
- * addr : adress where data must be read\r
+ * addr : the address where data must be read.\r
*\r
* Return:\r
* None\r
/*******************************************************************************\r
* File Name: project.h\r
- * PSoC Creator 3.0 Component Pack 7\r
+ * PSoC Creator 3.1\r
*\r
* Description:\r
* This file is automatically generated by PSoC Creator and should not \r
/*******************************************************************************
* File Name: timer_clock.c
-* Version 2.10
+* Version 2.20
*
* Description:
* This file provides the source code to the API for the clock component.
/*******************************************************************************
* File Name: timer_clock.h
-* Version 2.10
+* Version 2.20
*
* Description:
* Provides the function and constant definitions for the clock component.
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
- #error Component cy_clock_v2_10 requires cy_boot v3.0 or later
+ #error Component cy_clock_v2_20 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5LP) */
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" />\r
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />\r
</block>\r
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647E" bitWidth="8" desc="" />\r
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647D" bitWidth="8" desc="" />\r
</block>\r
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Filtered_STATUS_REG" address="0x4000646E" bitWidth="8" desc="" />\r
- <register name="SCSI_Filtered_MASK_REG" address="0x4000648E" bitWidth="8" desc="" />\r
- <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649E" bitWidth="8" desc="">\r
+ <register name="SCSI_Filtered_STATUS_REG" address="0x4000646C" bitWidth="8" desc="" />\r
+ <register name="SCSI_Filtered_MASK_REG" address="0x4000648C" bitWidth="8" desc="" />\r
+ <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649C" bitWidth="8" desc="">\r
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
<value name="ENABLED" value="1" desc="Enable counter" />\r
<value name="DISABLED" value="0" desc="Disable counter" />\r
<block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006470" bitWidth="8" desc="" />\r
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" />\r
</block>\r
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
</block>\r
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">\r
- <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="ep_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="ep_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0">\r
<field name="fsusbio_ref_en" from="0" to="0" access="RW" resetVal="" desc="" />\r
<field name="fsusbio_pd_n" from="1" to="1" access="RW" resetVal="" desc="" />\r
<register name="USBFS_EP0_DR6" address="0x40006006" bitWidth="8" desc="lengthLo" />\r
<register name="USBFS_EP0_DR7" address="0x40006007" bitWidth="8" desc="lengthHi" />\r
<register name="USBFS_CR0" address="0x40006008" bitWidth="8" desc="USB Control Register 0">\r
- <field name="device_address" from="0" to="6" access="R" resetVal="" desc="" />\r
+ <field name="device_address" from="6" to="0" access="R" resetVal="" desc="" />\r
<field name="usb_enable" from="7" to="7" access="RW" resetVal="" desc="" />\r
</register>\r
<register name="USBFS_CR1" address="0x40006009" bitWidth="8" desc="USB Control Register 1">\r
<build_action v="NONE" />\r
<PropertyDeltas />\r
</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="debug.h" persistent="..\..\src\debug.h">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="NONE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
</dependencies>\r
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
<GlobalPages />\r
<GlobalTools name="Code Generation">\r
<GlobalPages>\r
+<name_val_pair name="General@Application Type" v="Bootloadable" />\r
+<name_val_pair name="General@Custom Code Gen Options" v="" />\r
+<name_val_pair name="General@Skip Code Generation" v="False" />\r
+<name_val_pair name="General@Custom Synthesis Options" v="" />\r
+<name_val_pair name="General@Quiet Output" v="True" />\r
<name_val_pair name="General@Synthesis Goal" v="Speed" />\r
<name_val_pair name="General@Synthesis Optimization Effort" v="Exhaustive" />\r
-<name_val_pair name="General@Quiet Output" v="True" />\r
-<name_val_pair name="General@Custom Synthesis Options" v="" />\r
-<name_val_pair name="General@Skip Code Generation" v="False" />\r
-<name_val_pair name="General@Custom Code Gen Options" v="" />\r
<name_val_pair name="General@Virtual Node Substitution" v="3" />\r
-<name_val_pair name="General@Application Type" v="Bootloadable" />\r
<name_val_pair name="General@Custom Fitter Options" v="" />\r
</GlobalPages>\r
</GlobalTools>\r
</GlobalTools>\r
<GlobalTools name="Customizer">\r
<GlobalPages>\r
-<name_val_pair name="General@Customizer Build Mode" v="Release" />\r
-<name_val_pair name="General@Command Line Options" v="" />\r
<name_val_pair name="General@Assembly References" v="" />\r
+<name_val_pair name="General@Command Line Options" v="" />\r
+<name_val_pair name="General@Customizer Build Mode" v="Release" />\r
</GlobalPages>\r
</GlobalTools>\r
</name>\r
<platform>\r
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<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Additional Libraries" v="" />\r
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<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Generate Map File" v="True" />\r
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<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Use Default Libs" v="True" />\r
<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Use Nano Lib" v="True" />\r
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-<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Custom Linker Script" v="" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@General@Enable printf Float" v="True" />\r
+<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Optimization@Optimization Level" v="None" />\r
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<name_val_pair name="b98f980c-3bd1-4fc7-a887-c56a20a46fdd@Release@CortexM3@Linker@Command Line@Command Line" v="" />\r
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</name>\r
</platform>\r
<platform>\r
<name v="5bca58cd-5542-421c-b08d-9513dbb687fd">\r
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
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+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@Assembly@General@Generate Debugging Information" v="True" />\r
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+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@Assembly@General@Generate List Files" v="True" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@C/C++@General@Additional Include Directories" v="" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@C/C++@General@Generate Debugging Information" v="True" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@C/C++@Optimization@Split Sections" v="True" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@Linker@General@Additional Libraries" v="" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM0@Linker@General@Custom Linker Script" v="" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@C/C++@General@Generate Debugging Information" v="True" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@C/C++@Optimization@Inline Functions" v="False" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@C/C++@Optimization@Split Sections" v="True" />\r
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@C/C++@Command Line@Command Line" v="" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@Linker@General@Additional Libraries" v="" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@Linker@General@Generate Map File" v="True" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@Linker@General@Custom Linker Script" v="" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM0@Linker@Command Line@Command Line" v="" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Assembly@General@Additional Include Directories" v="" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Assembly@General@Generate Debugging Information" v="True" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@General@Additional Include Directories" v="" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@General@Generate Debugging Information" v="True" />\r
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-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@Optimization@Split Sections" v="True" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Assembly@General@Generate Debugging Information" v="True" />\r
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+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Assembly@General@Generate List Files" v="True" />\r
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-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@Optimization@Split Sections" v="True" />\r
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@Command Line@Command Line" v="" />\r
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-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Assembly@Command Line@Command Line" v="" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Additional Libraries" v="" />\r
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Custom Linker Script" v="" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Generate Debugging Information" v="True" />\r
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Use Default Libs" v="True" />\r
<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@Command Line@Command Line" v="" />\r
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</name>\r
</platform>\r
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<name v="fdb8e1ae-f83a-46cf-9446-1d703716f38a">\r
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+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Assembly@General@Additional Include Directories" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Assembly@General@Generate Debugging Information" v="True" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Assembly@General@Suppress Warnings" v="False" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Assembly@General@Generate List Files" v="True" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Assembly@Command Line@Command Line" v="" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@General@Additional Include Directories" v="" />\r
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+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@General@Generate List Files" v="True" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@General@Default Char Unsigned" v="False" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@General@Generate Debugging Information" v="True" />\r
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-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />\r
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />\r
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@Optimization@Split Sections" v="True" />\r
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Additional Libraries" v="" />\r
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Custom Linker Script" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Generate Debugging Information" v="True" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Use Default Libs" v="True" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@Command Line@Command Line" v="" />\r
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Assembly@General@Additional Include Directories" v="" />\r
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+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Assembly@General@Suppress Warnings" v="False" />\r
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@General@Additional Include Directories" v="" />\r
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+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@General@Default Char Unsigned" v="False" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@General@Generate Debugging Information" v="True" />\r
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@Optimization@Inline Functions" v="False" />\r
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@Optimization@Split Sections" v="True" />\r
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Additional Libraries" v="" />\r
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Generate Map File" v="True" />\r
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Custom Linker Script" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Generate Debugging Information" v="True" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Use Default Libs" v="True" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@Command Line@Command Line" v="" />\r
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Additional Include Directories" v="" />\r
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Additional Include Directories" v="" />\r
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Generate Debugging Information" v="True" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Preprocessor Definitions" v="DEBUG" />\r
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-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />\r
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Optimization@Split Sections" v="True" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Additional Include Directories" v="" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Suppress Warnings" v="False" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Generate Debugging Information" v="True" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Generate List Files" v="True" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Additional Libraries" v="" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Additional Library Directories" v="" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Generate Debugging Information" v="True" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Generate Map File" v="True" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Generate Debugging Information" v="True" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@Command Line@Command Line" v="" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Generate Debugging Information" v="True" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Suppress Warnings" v="False" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Generate List Files" v="True" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@Command Line@Command Line" v="" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Additional Include Directories" v="" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Strict Compilation" v="False" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Generate List Files" v="True" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Default Char Unsigned" v="False" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Generate Debugging Information" v="True" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Preprocessor Definitions" v="NDEBUG" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Default Char Unsigned" v="False" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Generate List Files" v="True" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Strict Compilation" v="False" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Split Sections" v="True" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Command Line@Command Line" v="" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Suppress Warnings" v="False" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Generate Debugging Information" v="True" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Generate List Files" v="True" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@Command Line@Command Line" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Libraries" v="" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Library Directories" v="" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Debugging Information" v="True" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Map File" v="True" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Use Default Libs" v="True" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Custom Linker Script" v="" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Debugging Information" v="True" />\r
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Use Default Libs" v="True" />\r
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@Command Line@Command Line" v="" />\r
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />\r
</name>\r
</platform>\r
</platforms>\r
-<project_current_platform v="b98f980c-3bd1-4fc7-a887-c56a20a46fdd" />\r
+<project_current_platform v="c9323d49-d323-40b8-9b59-cc008d68a989" />\r
<project_current_processor v="CortexM3" />\r
<component_generation v="PSoC Creator 2.2 Component Pack 6" />\r
<last_selected_tab v="Cypress" />\r
<component_dependent_projects_generation v="(69eeda1b-ded5-4da3-a74d-3a98f2d5d4ab , 2.1PR) | (b1a3f413-e018-46a5-a51c-20818b2f118e , 3.0) | (cd381074-8dad-4f43-bb88-7719b3e16126 , 2.1) | (29420278-6fcc-46a7-a651-999ec5c253d2 , 2.1) | (e95576e7-780d-474a-b944-018db0492cc9 , 2.1)" />\r
-<WriteAppVersionLastSavedWith v="3.0.0.1539" />\r
-<WriteAppMarketingVersionLastSavedWith v=" 3.0 Component Pack 7" />\r
-<project_id v="6e1f5cbb-a0ca-4f55-a1fa-7b20c5be3a3e" />\r
-<custom_data>\r
-<CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectCustomData" version="1">\r
-<CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997 type_name="CyDesigner.Common.Base.CyCustomData" version="2">\r
-<userData />\r
-</CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997>\r
-<properties />\r
-</CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111>\r
-</custom_data>\r
-</CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>\r
+<WriteAppVersionLastSavedWith v="3.1.0.1570" />\r
+<WriteAppMarketingVersionLastSavedWith v=" 3.1" />\r
+<project_id v="6e1f5cbb-a0ca-4f55-a1fa-7b20c5be3a3e" /><custom_data><CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectCustomData" version="1"><CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997 type_name="CyDesigner.Common.Base.CyCustomData" version="2"><userData /></CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997><properties /></CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111></custom_data></CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>\r
</CyGuid_60697ce6-dce2-4816-8680-4de0635742eb>\r
<top_block v="TopDesign" />\r
<selected_device v="CY8C5267AXI-LP051" />\r
<CyGuid_b0d670ad-d48f-47cb-9d0b-b1642bab195c type_name="CyDesigner.Common.Base.CyExprTypeMgr" version="1" />\r
<ignored_deps />\r
</CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>\r
-<boot_component v="cy_boot_v4_0" />\r
+<boot_component v="cy_boot_v4_20" />\r
<BootloaderTag hexFile="" elfFile="" />\r
-<current_generation v="6" />\r
+<current_generation v="7" />\r
</CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>\r
</CyXmlSerializer>
\ No newline at end of file
<peripheral>\r
<name>SCSI_Out_Bits</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006474</baseAddress>\r
+ <baseAddress>0x4000647B</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
- <size>0x1</size>\r
+ <size>0x0</size>\r
<usage>registers</usage>\r
</addressBlock>\r
<registers>\r
<peripheral>\r
<name>SCSI_Out_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000647E</baseAddress>\r
+ <baseAddress>0x4000647D</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
- <size>0x1</size>\r
+ <size>0x0</size>\r
<usage>registers</usage>\r
</addressBlock>\r
<registers>\r
<peripheral>\r
<name>Debug_Timer</name>\r
<description>No description available</description>\r
- <baseAddress>0x400043A3</baseAddress>\r
+ <baseAddress>0x0</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
- <size>0xB64</size>\r
+ <size>0x0</size>\r
<usage>registers</usage>\r
</addressBlock>\r
<registers>\r
<register>\r
<name>Debug_Timer_GLOBAL_ENABLE</name>\r
<description>PM.ACT.CFG</description>\r
- <addressOffset>0x0</addressOffset>\r
+ <addressOffset>0x400043A3</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>Debug_Timer_CONTROL</name>\r
<description>TMRx.CFG0</description>\r
- <addressOffset>0xB5D</addressOffset>\r
+ <addressOffset>0x40004F00</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>Debug_Timer_CONTROL2</name>\r
<description>TMRx.CFG1</description>\r
- <addressOffset>0xB5E</addressOffset>\r
+ <addressOffset>0x40004F01</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>Debug_Timer_CONTROL3_</name>\r
<description>TMRx.CFG2</description>\r
- <addressOffset>0xB5F</addressOffset>\r
+ <addressOffset>0x40004F02</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>Debug_Timer_PERIOD</name>\r
<description>TMRx.PER0 - Assigned Period</description>\r
- <addressOffset>0xB61</addressOffset>\r
+ <addressOffset>0x40004F04</addressOffset>\r
<size>16</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>Debug_Timer_COUNTER</name>\r
<description>TMRx.CNT_CMP0 - Current Down Counter Value</description>\r
- <addressOffset>0xB63</addressOffset>\r
+ <addressOffset>0x40004F06</addressOffset>\r
<size>16</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<peripheral>\r
<name>SCSI_Filtered</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000646E</baseAddress>\r
+ <baseAddress>0x4000646C</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
- <size>0x31</size>\r
+ <size>0x0</size>\r
<usage>registers</usage>\r
</addressBlock>\r
<registers>\r
<baseAddress>0x40006466</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
- <size>0x31</size>\r
+ <size>0x0</size>\r
<usage>registers</usage>\r
</addressBlock>\r
<registers>\r
<peripheral>\r
<name>SCSI_CTL_PHASE</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006470</baseAddress>\r
+ <baseAddress>0x4000647C</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
- <size>0x1</size>\r
+ <size>0x0</size>\r
<usage>registers</usage>\r
</addressBlock>\r
<registers>\r
<peripheral>\r
<name>USBFS</name>\r
<description>USBFS</description>\r
- <baseAddress>0x40004394</baseAddress>\r
+ <baseAddress>0x0</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
- <size>0x1D0A</size>\r
+ <size>0x0</size>\r
<usage>registers</usage>\r
</addressBlock>\r
<registers>\r
<register>\r
<name>USBFS_PM_USB_CR0</name>\r
<description>USB Power Mode Control Register 0</description>\r
- <addressOffset>0x0</addressOffset>\r
+ <addressOffset>0x40004394</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_PM_ACT_CFG</name>\r
<description>Active Power Mode Configuration Register</description>\r
- <addressOffset>0x11</addressOffset>\r
+ <addressOffset>0x400043A5</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_PM_STBY_CFG</name>\r
<description>Standby Power Mode Configuration Register</description>\r
- <addressOffset>0x21</addressOffset>\r
+ <addressOffset>0x400043B5</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_PRT_PS</name>\r
<description>Port Pin State Register</description>\r
- <addressOffset>0xE5D</addressOffset>\r
+ <addressOffset>0x400051F1</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_PRT_DM0</name>\r
<description>Port Drive Mode Register</description>\r
- <addressOffset>0xE5E</addressOffset>\r
+ <addressOffset>0x400051F2</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_PRT_DM1</name>\r
<description>Port Drive Mode Register</description>\r
- <addressOffset>0xE5F</addressOffset>\r
+ <addressOffset>0x400051F3</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_PRT_INP_DIS</name>\r
<description>Input buffer disable override</description>\r
- <addressOffset>0xE64</addressOffset>\r
+ <addressOffset>0x400051F8</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP0_DR0</name>\r
<description>bmRequestType</description>\r
- <addressOffset>0x1C6C</addressOffset>\r
+ <addressOffset>0x40006000</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP0_DR1</name>\r
<description>bRequest</description>\r
- <addressOffset>0x1C6D</addressOffset>\r
+ <addressOffset>0x40006001</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP0_DR2</name>\r
<description>wValueLo</description>\r
- <addressOffset>0x1C6E</addressOffset>\r
+ <addressOffset>0x40006002</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP0_DR3</name>\r
<description>wValueHi</description>\r
- <addressOffset>0x1C6F</addressOffset>\r
+ <addressOffset>0x40006003</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP0_DR4</name>\r
<description>wIndexLo</description>\r
- <addressOffset>0x1C70</addressOffset>\r
+ <addressOffset>0x40006004</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP0_DR5</name>\r
<description>wIndexHi</description>\r
- <addressOffset>0x1C71</addressOffset>\r
+ <addressOffset>0x40006005</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP0_DR6</name>\r
<description>lengthLo</description>\r
- <addressOffset>0x1C72</addressOffset>\r
+ <addressOffset>0x40006006</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP0_DR7</name>\r
<description>lengthHi</description>\r
- <addressOffset>0x1C73</addressOffset>\r
+ <addressOffset>0x40006007</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_CR0</name>\r
<description>USB Control Register 0</description>\r
- <addressOffset>0x1C74</addressOffset>\r
+ <addressOffset>0x40006008</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<field>\r
<name>device_address</name>\r
<description>No description available</description>\r
- <lsb>6</lsb>\r
- <msb>0</msb>\r
+ <lsb>0</lsb>\r
+ <msb>6</msb>\r
<access>read-only</access>\r
</field>\r
<field>\r
<register>\r
<name>USBFS_CR1</name>\r
<description>USB Control Register 1</description>\r
- <addressOffset>0x1C75</addressOffset>\r
+ <addressOffset>0x40006009</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_SIE_EP1_CR0</name>\r
<description>The Endpoint1 Control Register</description>\r
- <addressOffset>0x1C7A</addressOffset>\r
+ <addressOffset>0x4000600E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_USBIO_CR0</name>\r
<description>USBIO Control Register 0</description>\r
- <addressOffset>0x1C7C</addressOffset>\r
+ <addressOffset>0x40006010</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_USBIO_CR1</name>\r
<description>USBIO Control Register 1</description>\r
- <addressOffset>0x1C7E</addressOffset>\r
+ <addressOffset>0x40006012</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_SIE_EP2_CR0</name>\r
<description>The Endpoint2 Control Register</description>\r
- <addressOffset>0x1C8A</addressOffset>\r
+ <addressOffset>0x4000601E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_SIE_EP3_CR0</name>\r
<description>The Endpoint3 Control Register</description>\r
- <addressOffset>0x1C9A</addressOffset>\r
+ <addressOffset>0x4000602E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_SIE_EP4_CR0</name>\r
<description>The Endpoint4 Control Register</description>\r
- <addressOffset>0x1CAA</addressOffset>\r
+ <addressOffset>0x4000603E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_SIE_EP5_CR0</name>\r
<description>The Endpoint5 Control Register</description>\r
- <addressOffset>0x1CBA</addressOffset>\r
+ <addressOffset>0x4000604E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_SIE_EP6_CR0</name>\r
<description>The Endpoint6 Control Register</description>\r
- <addressOffset>0x1CCA</addressOffset>\r
+ <addressOffset>0x4000605E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_SIE_EP7_CR0</name>\r
<description>The Endpoint7 Control Register</description>\r
- <addressOffset>0x1CDA</addressOffset>\r
+ <addressOffset>0x4000606E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_SIE_EP8_CR0</name>\r
<description>The Endpoint8 Control Register</description>\r
- <addressOffset>0x1CEA</addressOffset>\r
+ <addressOffset>0x4000607E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_BUF_SIZE</name>\r
<description>Dedicated Endpoint Buffer Size Register</description>\r
- <addressOffset>0x1CF8</addressOffset>\r
+ <addressOffset>0x4000608C</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP_ACTIVE</name>\r
<description>Endpoint Active Indication Register</description>\r
- <addressOffset>0x1CFA</addressOffset>\r
+ <addressOffset>0x4000608E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP_TYPE</name>\r
<description>Endpoint Type (IN/OUT) Indication</description>\r
- <addressOffset>0x1CFB</addressOffset>\r
+ <addressOffset>0x4000608F</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_USB_CLK_EN</name>\r
<description>USB Block Clock Enable Register</description>\r
- <addressOffset>0x1D09</addressOffset>\r
+ <addressOffset>0x4000609D</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
/*******************************************************************************\r
* File Name: BL.c\r
-* Version 1.20\r
+* Version 1.30\r
*\r
* Description:\r
* Provides an API for the Bootloader component. The API includes functions\r
* jumping to the application.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
* The Checksum and SizeBytes are forcefully set in code. We then post process\r
* the hex file from the linker and inject their values then. When the hex file\r
* is loaded onto the device these two variables should have valid values.\r
-* Because the compiler can do optimizations remove the constant\r
+* Because the compiler can do optimizations to remove the constant\r
* accesses, these should not be accessed directly. Instead, the variables\r
* CyBtldr_ChecksumAccess & CyBtldr_SizeBytesAccess should be used to get the\r
* proper values at runtime.\r
*******************************************************************************/\r
#if defined(__ARMCC_VERSION) || defined (__GNUC__)\r
- __attribute__((section (".bootloader")))\r
+ __attribute__((section (".bootloader"), used))\r
#elif defined (__ICCARM__)\r
#pragma location=".bootloader"\r
#endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) */\r
\r
-const uint8 CYCODE BL_Checksum = 0u;\r
+#if defined(__ARMCC_VERSION) || defined (__GNUC__) || defined (__C51__)\r
+ const uint8 CYCODE BL_Checksum = 0u;\r
+#elif defined (__ICCARM__)\r
+ __root const uint8 CYCODE BL_Checksum = 0u;\r
+#endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) || defined (__C51__) */\r
const uint8 CYCODE *BL_ChecksumAccess = (const uint8 CYCODE *)(&BL_Checksum);\r
\r
#if defined(__ARMCC_VERSION) || defined (__GNUC__)\r
- __attribute__((section (".bootloader")))\r
+ __attribute__((section (".bootloader"), used))\r
#elif defined (__ICCARM__)\r
#pragma location=".bootloader"\r
#endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) */\r
static uint16 BL_CalcPacketChecksum(const uint8 buffer[], uint16 size) CYSMALL \\r
;\r
\r
-static uint8 BL_Calc8BitFlashSum(uint32 start, uint32 size) CYSMALL \\r
- ;\r
-#if(!CY_PSOC4)\r
-static uint8 BL_Calc8BitEepromSum(uint32 start, uint32 size) CYSMALL \\r
- ;\r
-#endif /* (!CY_PSOC4) */\r
-\r
static void BL_HostLink(uint8 timeOut) \\r
;\r
\r
static void BL_LaunchApplication(void) CYSMALL \\r
;\r
\r
-static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \\r
- ;\r
-\r
-static uint32 BL_GetMetadata(uint8 fieldName, uint8 appId)\\r
- ;\r
-\r
#if(!CY_PSOC3)\r
/* Implementation for the PSoC 3 resides in a BL_psoc3.a51 file. */\r
static void BL_LaunchBootloadable(uint32 appAddr);\r
* buffer:\r
* The buffer containing the data to compute the checksum for\r
* size:\r
-* The number of bytes in buffer to compute the checksum for\r
+* The number of bytes in the buffer to compute the checksum for\r
*\r
* Returns:\r
* 16 bit checksum for the provided data\r
\r
\r
/*******************************************************************************\r
-* Function Name: BL_Calc8BitFlashSum\r
+* Function Name: BL_Calc8BitSum\r
********************************************************************************\r
*\r
* Summary:\r
* This computes the 8 bit sum for the provided number of bytes contained in\r
-* flash.\r
+* FLASH (if baseAddr equals CY_FLASH_BASE) or EEPROM (if baseAddr equals\r
+* CY_EEPROM_BASE).\r
*\r
* Parameters:\r
+* baseAddr:\r
+* CY_FLASH_BASE\r
+* CY_EEPROM_BASE - applicable only for PSoC 3 / PSoC 5LP devices.\r
+*\r
* start:\r
* The starting address to start summing data for\r
* size:\r
* 8 bit sum for the provided data\r
*\r
*******************************************************************************/\r
-static uint8 BL_Calc8BitFlashSum(uint32 start, uint32 size) \\r
+uint8 BL_Calc8BitSum(uint32 baseAddr, uint32 start, uint32 size) \\r
CYSMALL \r
{\r
uint8 CYDATA sum = 0u;\r
\r
+ #if(!CY_PSOC4)\r
+ CYASSERT((baseAddr == CY_EEPROM_BASE) || (baseAddr == CY_FLASH_BASE));\r
+ #else\r
+ CYASSERT(baseAddr == CY_FLASH_BASE);\r
+ #endif /* (!CY_PSOC4) */\r
+\r
while (size > 0u)\r
{\r
size--;\r
- sum += BL_GET_CODE_BYTE(start + size);\r
+ sum += (*((uint8 *)(baseAddr + start + size)));\r
}\r
\r
return(sum);\r
}\r
\r
\r
-#if(!CY_PSOC4)\r
-\r
- /*******************************************************************************\r
- * Function Name: BL_Calc8BitEepromSum\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * This computes the 8 bit sum for the provided number of bytes contained in\r
- * EEPROM.\r
- *\r
- * Parameters:\r
- * start:\r
- * The starting address to start summing data for\r
- * size:\r
- * The number of bytes to read and compute the sum for\r
- *\r
- * Returns:\r
- * 8 bit sum for the provided data\r
- *\r
- *******************************************************************************/\r
- static uint8 BL_Calc8BitEepromSum(uint32 start, uint32 size) \\r
- CYSMALL \r
- {\r
- uint8 CYDATA sum = 0u;\r
-\r
- while (size > 0u)\r
- {\r
- size--;\r
- sum += BL_GET_EEPROM_BYTE(start + size);\r
- }\r
-\r
- return(sum);\r
- }\r
-\r
-#endif /* (!CY_PSOC4) */\r
-\r
-\r
/*******************************************************************************\r
* Function Name: BL_Start\r
********************************************************************************\r
* Summary:\r
-* This function is called in order executing following algorithm:\r
+* This function is called in order to execute the following algorithm:\r
*\r
-* - Identify active bootloadable application (applicable only to\r
-* Multi-application bootloader)\r
+* - Identify the active bootloadable application (applicable only to\r
+* the Multi-application bootloader)\r
*\r
-* - Validate bootloader application (desing-time configurable, Bootloader\r
+* - Validate the bootloader application (design-time configurable, Bootloader\r
* application validation option of the component customizer)\r
*\r
-* - Validate active bootloadable application\r
+* - Validate the active bootloadable application. If active bootloadable\r
+* application is not valid, and the other bootloadable application (inactive)\r
+* is valid, the last one is started.\r
*\r
-* - Run communication subroutine (desing-time configurable, Wait for command\r
+* - Run a communication subroutine (design-time configurable, Wait for command\r
* option of the component customizer)\r
*\r
-* - Schedule bootloadable and reset device\r
+* - Schedule the bootloadable and reset the device\r
*\r
* Parameters:\r
* None\r
*\r
* Return:\r
* This method will never return. It will either load a new application and\r
-* reset the device or it will jump directly to the existing application.\r
+* reset the device or jump directly to the existing application. The CPU is\r
+* halted, if validation failed when "Bootloader application validation" option\r
+* is enabled.\r
+* PSoC 3/PSoC 5: The CPU is halted if Flash initialization fails.\r
*\r
* Side Effects:\r
-* If this method determines that the bootloader appliation itself is corrupt,\r
-* this method will not return, instead it will simply hang the application.\r
+* If Bootloader application validation option is enabled and this method\r
+* determines that the bootloader application itself is corrupt, this method\r
+* will not return, instead it will simply hang the application.\r
*\r
*******************************************************************************/\r
void BL_Start(void) CYSMALL \r
#endif /* (0u != BL_BOOTLOADER_APP_VALIDATION) */\r
\r
#if(!CY_PSOC4)\r
- uint8 CYXDATA BL_flashBuffer[BL_FROW_SIZE];\r
+ #if(0u != BL_FAST_APP_VALIDATION)\r
+ #if !defined(CY_BOOT_VERSION)\r
+\r
+ /* Not required starting from cy_boot 4.20 */\r
+ uint8 CYXDATA BL_flashBuffer[BL_FROW_SIZE];\r
+\r
+ #endif /* !defined(CY_BOOT_VERSION) */\r
+ #endif /* (0u != BL_FAST_APP_VALIDATION) */\r
#endif /* (!CY_PSOC4) */\r
\r
- cystatus tmpStatus;\r
+ cystatus validApp = CYRET_BAD_DATA;\r
\r
\r
/* Identify active bootloadable application */\r
#if(0u != BL_DUAL_APP_BOOTLOADER)\r
\r
- if(BL_MD_BTLDB_ACTIVE_VALUE(0u) == BL_MD_BTLDB_IS_ACTIVE)\r
+ /* Assumes no active bootloadable application. Bootloader is active. */\r
+ BL_activeApp = BL_MD_BTLDB_ACTIVE_NONE;\r
+\r
+ /* Bootloadable # A is active */\r
+ if(BL_GetMetadata(BL_GET_BTLDB_ACTIVE, 0u) == BL_MD_BTLDB_IS_ACTIVE)\r
{\r
- BL_activeApp = BL_MD_BTLDB_ACTIVE_0;\r
+ /*******************************************************************\r
+ * -----------------------------------------------------------\r
+ * | | Bootloadable A | Bootloadable B | |\r
+ * | Case |---------------------------------| Action |\r
+ * | | Active | Valid | Active | Valid | |\r
+ * |------|--------------------------------------------------|\r
+ * | 9 | 1 | 0 | 0 | 0 | Bootloader |\r
+ * | 10 | 1 | 0 | 0 | 1 | Bootloadable B |\r
+ * | 11 | 1 | 0 | 1 | 0 | Bootloader |\r
+ * | 12 | 1 | 0 | 1 | 1 | Bootloadable B |\r
+ * | 13 | 1 | 1 | 0 | 0 | Bootloadable A |\r
+ * | 14 | 1 | 1 | 0 | 1 | Bootloadable A |\r
+ * | 15 | 1 | 1 | 1 | 0 | Bootloadable A |\r
+ * | 16 | 1 | 1 | 1 | 1 | Bootloadable A |\r
+ * -----------------------------------------------------------\r
+ *******************************************************************/\r
+ if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0))\r
+ {\r
+ /* Cases # 13, 14, 15, and 16 */\r
+ BL_activeApp = BL_MD_BTLDB_ACTIVE_0;\r
+ validApp = CYRET_SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_1))\r
+ {\r
+ /* Cases # 10 and 12 */\r
+ BL_activeApp = BL_MD_BTLDB_ACTIVE_1;\r
+ validApp = CYRET_SUCCESS;\r
+ }\r
+ }\r
}\r
- else if (BL_MD_BTLDB_ACTIVE_VALUE(1u) == BL_MD_BTLDB_IS_ACTIVE)\r
+\r
+ /* Active bootloadable application is not identified */\r
+ if(BL_activeApp == BL_MD_BTLDB_ACTIVE_NONE)\r
{\r
- BL_activeApp = BL_MD_BTLDB_ACTIVE_1;\r
+ /*******************************************************************\r
+ * -----------------------------------------------------------\r
+ * | | Bootloadable A | Bootloadable B | |\r
+ * | Case |---------------------------------| Action |\r
+ * | | Active | Valid | Active | Valid | |\r
+ * |------|--------------------------------------------------|\r
+ * | 1 | 0 | 0 | 0 | 0 | Bootloader |\r
+ * | 2 | 0 | 0 | 0 | 1 | Bootloader |\r
+ * | 3 | 0 | 0 | 1 | 0 | Bootloader |\r
+ * | 4 | 0 | 0 | 1 | 1 | Bootloadable B |\r
+ * | 5 | 0 | 1 | 0 | 0 | Bootloader |\r
+ * | 6 | 0 | 1 | 0 | 1 | Bootloader |\r
+ * | 7 | 0 | 1 | 1 | 0 | Bootloadable A |\r
+ * | 8 | 0 | 1 | 1 | 1 | Bootloadable B |\r
+ * -----------------------------------------------------------\r
+ *******************************************************************/\r
+ if (BL_GetMetadata(BL_GET_BTLDB_ACTIVE, 1u) ==\r
+ BL_MD_BTLDB_IS_ACTIVE)\r
+ {\r
+ /* Cases # 3, 4, 7, and 8 */\r
+ if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_1))\r
+ {\r
+ /* Cases # 4 and 8 */\r
+ BL_activeApp = BL_MD_BTLDB_ACTIVE_1;\r
+ validApp = CYRET_SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0))\r
+ {\r
+ /* Cases # 7 */\r
+ BL_activeApp = BL_MD_BTLDB_ACTIVE_0;\r
+ validApp = CYRET_SUCCESS;\r
+ }\r
+ }\r
+ }\r
}\r
- else\r
+ #else\r
+ if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0))\r
{\r
- BL_activeApp = BL_MD_BTLDB_ACTIVE_NONE;\r
+ validApp = CYRET_SUCCESS;\r
}\r
-\r
#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */\r
\r
\r
/* Initialize Flash subsystem for non-PSoC 4 devices */\r
#if(!CY_PSOC4)\r
- if (CYRET_SUCCESS != CySetTemp())\r
- {\r
- CyHalt(0x00u);\r
- }\r
+ #if(0u != BL_FAST_APP_VALIDATION)\r
\r
- if (CYRET_SUCCESS != CySetFlashEEBuffer(BL_flashBuffer))\r
- {\r
- CyHalt(0x00u);\r
- }\r
+ if (CYRET_SUCCESS != CySetTemp())\r
+ {\r
+ CyHalt(0x00u);\r
+ }\r
+\r
+ #if !defined(CY_BOOT_VERSION)\r
+\r
+ /* Not required with cy_boot 4.20 */\r
+ if (CYRET_SUCCESS != CySetFlashEEBuffer(BL_flashBuffer))\r
+ {\r
+ CyHalt(0x00u);\r
+ }\r
+\r
+ #endif /* !defined(CY_BOOT_VERSION) */\r
+ #endif /* (0u != BL_FAST_APP_VALIDATION) */\r
#endif /* (CY_PSOC4) */\r
\r
\r
/***********************************************************************\r
* Bootloader Application Validation\r
*\r
- * Halt device if:\r
- * - Calculated checksum does not much one stored in metadata section\r
- * - Invalid pointer to the place where bootloader application ends\r
- * - Flash subsystem where not initialized correctly\r
+ * Halt the device if:\r
+ * - A calculated checksum does not match the one stored in the metadata\r
+ * section.\r
+ * - There is an invalid pointer to the place where the bootloader\r
+ * application ends.\r
+ * - Flash subsystem was not initialized correctly\r
***********************************************************************/\r
#if(0u != BL_BOOTLOADER_APP_VALIDATION)\r
\r
/* Calculate Bootloader application checksum */\r
- calcedChecksum = BL_Calc8BitFlashSum(BL_MD_BTLDR_ADDR_PTR,\r
+ calcedChecksum = BL_Calc8BitSum(CY_FLASH_BASE,\r
+ BL_MD_BTLDR_ADDR_PTR,\r
*BL_SizeBytesAccess - BL_MD_BTLDR_ADDR_PTR);\r
\r
- /* we actually included the checksum, so remove it */\r
+ /* we included checksum, so remove it */\r
calcedChecksum -= *BL_ChecksumAccess;\r
calcedChecksum = ( uint8 )1u + ( uint8 )(~calcedChecksum);\r
\r
\r
\r
/***********************************************************************\r
- * Active Bootloadable Application Validation\r
- *\r
- * If active bootloadable application is invalid or bootloader\r
+ * If the active bootloadable application is invalid or a bootloader\r
* application is scheduled - do the following:\r
- * - schedule bootloader application to be run after software reset\r
- * - Go to the communication subroutine. Will wait for commands forever\r
+ * - schedule the bootloader application to be run after software reset\r
+ * - Go to the communication subroutine. The HostLink() will wait for\r
+ * the commands forever.\r
***********************************************************************/\r
- tmpStatus = BL_ValidateBootloadable(BL_activeApp);\r
-\r
if ((BL_GET_RUN_TYPE == BL_START_BTLDR) ||\r
- (CYRET_SUCCESS != tmpStatus))\r
+ (CYRET_SUCCESS != validApp))\r
{\r
BL_SET_RUN_TYPE(0u);\r
\r
}\r
\r
\r
- /* Go to the communication subroutine. Will wait for commands specifed time */\r
+ /* Go to communication subroutine. Will wait for commands for specifed time */\r
#if(0u != BL_WAIT_FOR_COMMAND)\r
\r
- /* Timeout is in 100s of miliseconds */\r
+ /* Timeout is in 100s of milliseconds */\r
BL_HostLink(BL_WAIT_FOR_COMMAND_TIME);\r
\r
#endif /* (0u != BL_WAIT_FOR_COMMAND) */\r
********************************************************************************\r
*\r
* Summary:\r
-* Jumps the PC to the start address of the user application in flash.\r
+* Schedules bootloadable application and resets device\r
*\r
* Parameters:\r
* None\r
*\r
* Returns:\r
-* This method will never return if it succesfully goes to the user application.\r
+* This method will never return.\r
*\r
*******************************************************************************/\r
static void BL_LaunchApplication(void) CYSMALL \r
}\r
\r
\r
+/*******************************************************************************\r
+* Function Name: BL_Exit\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Schedules the specified application and performs software reset to launch\r
+* a specified application.\r
+*\r
+* If the specified application is not valid, the Bootloader (the result of the\r
+* ValidateBootloadable() function execution returns other than CYRET_SUCCESS,\r
+* the bootloader application is launched.\r
+*\r
+* Parameters:\r
+* appId: application to be started:\r
+* BL_EXIT_TO_BTLDR - Bootloader application will be started on\r
+* software reset.\r
+* BL_EXIT_TO_BTLDB,\r
+* BL_EXIT_TO_BTLDB_1 - Bootloadable application # 1 will be\r
+* started on software reset.\r
+* BL_EXIT_TO_BTLDB_2 - Bootloadable application # 2 will be\r
+* started on software reset. Available only\r
+* if Multi-Application option is enabled in\r
+* the component customizer.\r
+* Returns:\r
+* This function never returns.\r
+*\r
+*******************************************************************************/\r
+void BL_Exit(uint8 appId) CYSMALL \r
+{\r
+ if(BL_EXIT_TO_BTLDR == appId)\r
+ {\r
+ BL_SET_RUN_TYPE(0x0u);\r
+ }\r
+ else\r
+ {\r
+ if(CYRET_SUCCESS == BL_ValidateBootloadable(appId))\r
+ {\r
+ /* Set active application in metadata */\r
+ uint8 CYDATA idx;\r
+ for(idx = 0u; idx < BL_MAX_NUM_OF_BTLDB; idx++)\r
+ {\r
+ BL_SetFlashByte((uint32) BL_MD_BTLDB_ACTIVE_OFFSET(idx),\r
+ (uint8 )(idx == appId));\r
+ }\r
+\r
+ #if(0u != BL_DUAL_APP_BOOTLOADER)\r
+ BL_activeApp = appId;\r
+ #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */\r
+\r
+ BL_SET_RUN_TYPE(BL_SCHEDULE_BTLDB);\r
+ }\r
+ else\r
+ {\r
+ BL_SET_RUN_TYPE(0u);\r
+ }\r
+ }\r
+\r
+ CySoftwareReset();\r
+}\r
+\r
+\r
/*******************************************************************************\r
* Function Name: CyBtldr_CheckLaunch\r
********************************************************************************\r
*\r
* Summary:\r
-* This routine checks to see if the bootloader or the bootloadable application\r
-* should be run. If the application is to be run, it will start executing.\r
-* If the bootloader is to be run, it will return so the bootloader can\r
+* This routine checks if the bootloader or the bootloadable application has to\r
+* be run. If the application has to be run, it will start executing.\r
+* If the bootloader is to be run, it will return, so the bootloader can\r
* continue starting up.\r
*\r
* Parameters:\r
* None\r
*\r
* Returns:\r
-* None\r
+* It will not return if it determines that the bootloadable application should\r
+* be run.\r
*\r
*******************************************************************************/\r
void CyBtldr_CheckLaunch(void) CYSMALL \r
#if(CY_PSOC4)\r
\r
/*******************************************************************************\r
- * Set cyBtldrRunType to zero in case of non-software reset occured. This means\r
+ * Set cyBtldrRunType to zero in case of non-software reset occurred. This means\r
* that bootloader application is scheduled - that is initial clean state. The\r
* value of cyBtldrRunType is valid only in case of software reset.\r
*******************************************************************************/\r
* application. We just check to make sure that the value at CY_APP_ADDR_ADDRESS\r
* is something other than 0.\r
*******************************************************************************/\r
- if(0u != BL_GetMetadata(BL_GET_METADATA_BTLDB_ADDR, BL_activeApp))\r
+ if(0u != BL_GetMetadata(BL_GET_BTLDB_ADDR, BL_activeApp))\r
{\r
/* Never return from this method */\r
- BL_LaunchBootloadable(BL_GetMetadata(BL_GET_METADATA_BTLDB_ADDR,\r
+ BL_LaunchBootloadable(BL_GetMetadata(BL_GET_BTLDB_ADDR,\r
BL_activeApp));\r
}\r
}\r
}\r
\r
\r
-/* Moves the arguement appAddr (RO) into PC, moving execution to the appAddr */\r
+/* Moves argument appAddr (RO) into PC, moving execution to appAddr */\r
#if defined (__ARMCC_VERSION)\r
\r
__asm static void BL_LaunchBootloadable(uint32 appAddr)\r
* Function Name: BL_ValidateBootloadable\r
********************************************************************************\r
* Summary:\r
-* This routine computes the checksum, zero check, 0xFF check of the\r
-* application area to determine whether a valid application is loaded.\r
+* Performs the bootloadable application validation by calculating the\r
+* application image checksum and comparing it with the checksum value stored\r
+* in the Bootloadable Application Checksum field of the metadata section.\r
+*\r
+* If the Fast bootloadable application validation option is enabled in the\r
+* component customizer and bootloadable application successfully passes\r
+* validation, the Bootloadable Application Verification Status field of the\r
+* metadata section is updated. Refer to the Metadata Layout section for the\r
+* details.\r
+*\r
+* If the Fast bootloadable application validation option is enabled and\r
+* Bootloadable Application Verification Status field of the metadata section\r
+* claims that bootloadable application is valid, the function returns\r
+* CYRET_SUCCESS without further checksum calculation.\r
*\r
* Parameters:\r
* appId:\r
-* The application number to verify\r
+* The number of the bootloadable application should be 0 for the normal\r
+* bootloader and 0 or 1 for the Multi-Application bootloader.\r
*\r
* Returns:\r
-* CYRET_SUCCESS - if successful\r
-* CYRET_BAD_DATA - if the bootloadable is corrupt\r
+* Returns CYRET_SUCCESS if the specified bootloadable application is valid.\r
*\r
*******************************************************************************/\r
-static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \\r
+cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \\r
\r
{\r
uint32 CYDATA idx;\r
\r
uint32 CYDATA end = BL_FIRST_APP_BYTE(appId) +\r
- BL_GetMetadata(BL_GET_METADATA_BTLDB_LENGTH,\r
+ BL_GetMetadata(BL_GET_BTLDB_LENGTH,\r
appId);\r
\r
CYBIT valid = 0u; /* Assume bad flash image */\r
\r
#if(0u != BL_FAST_APP_VALIDATION)\r
\r
- if(BL_MD_BTLDB_VERIFIED_VALUE(appId) == BL_MD_BTLDB_IS_VERIFIED)\r
+\r
+ if(BL_GetMetadata(BL_GET_BTLDB_STATUS, appId) ==\r
+ BL_MD_BTLDB_IS_VERIFIED)\r
{\r
return(CYRET_SUCCESS);\r
}\r
/* Add ECC data to checksum */\r
idx = ((BL_FIRST_APP_BYTE(appId)) >> 3u);\r
\r
- /* Flash may run into meta data, ECC does not so use full row */\r
+ /* Flash may run into meta data, so ECC does not use full row */\r
end = (end == (CY_FLASH_SIZE - BL_MD_SIZEOF))\r
? (CY_FLASH_SIZE >> 3u)\r
: (end >> 3u);\r
\r
calcedChecksum = ( uint8 )1u + ( uint8 )(~calcedChecksum);\r
\r
- if((calcedChecksum != BL_MD_BTLDB_CHECKSUM_VALUE(appId)) ||\r
+\r
+ if((calcedChecksum != BL_GetMetadata(BL_GET_BTLDB_CHECKSUM, appId)) ||\r
(0u == valid))\r
{\r
return(CYRET_BAD_DATA);\r
* Parameters:\r
* timeOut:\r
* The amount of time to listen for data before giving up. Timeout is\r
-* measured in 10s of ms. Use 0 for infinite wait.\r
+* measured in 10s of ms. Use 0 for an infinite wait.\r
*\r
* Return:\r
* None\r
uint16 CYDATA dataOffset = 0u;\r
uint8 CYDATA timeOutCnt = 10u;\r
\r
- #if(0u == BL_DUAL_APP_BOOTLOADER)\r
+ #if(0u != BL_FAST_APP_VALIDATION)\r
uint8 CYDATA clearedMetaData = 0u;\r
- #endif /* (0u == BL_DUAL_APP_BOOTLOADER) */\r
+ #endif /* (0u != BL_FAST_APP_VALIDATION) */\r
\r
CYBIT communicationState = BL_COMMUNICATION_STATE_IDLE;\r
\r
uint8 dataBuffer [BL_SIZEOF_COMMAND_BUFFER];\r
\r
\r
+ #if(!CY_PSOC4)\r
+ #if(0u == BL_FAST_APP_VALIDATION)\r
+ #if !defined(CY_BOOT_VERSION)\r
+\r
+ /* Not required with cy_boot 4.20 */\r
+ uint8 CYXDATA BL_flashBuffer[BL_FROW_SIZE];\r
+\r
+ #endif /* !defined(CY_BOOT_VERSION) */\r
+ #endif /* (0u == BL_FAST_APP_VALIDATION) */\r
+ #endif /* (CY_PSOC4) */\r
+\r
+\r
+\r
+ #if(!CY_PSOC4)\r
+ #if(0u == BL_FAST_APP_VALIDATION)\r
+\r
+ /* Initialize Flash subsystem for non-PSoC 4 devices */\r
+ if (CYRET_SUCCESS != CySetTemp())\r
+ {\r
+ CyHalt(0x00u);\r
+ }\r
+\r
+ #if !defined(CY_BOOT_VERSION)\r
+\r
+ /* Not required with cy_boot 4.20 */\r
+ if (CYRET_SUCCESS != CySetFlashEEBuffer(BL_flashBuffer))\r
+ {\r
+ CyHalt(0x00u);\r
+ }\r
+\r
+ #endif /* !defined(CY_BOOT_VERSION) */\r
+ #endif /* (0u == BL_FAST_APP_VALIDATION) */\r
+ #endif /* (CY_PSOC4) */\r
+\r
/* Initialize communications channel. */\r
CyBtldrCommStart();\r
\r
{\r
#if(CY_PSOC3)\r
(void) memcpy(&packetBuffer[BL_DATA_ADDR],\r
- ((uint8 CYCODE *) (BL_META_BASE(btldrData))), 56);\r
+ ((uint8 CYCODE *) (BL_META_BASE(btldrData))),\r
+ BL_GET_METADATA_RESPONSE_SIZE);\r
#else\r
(void) memcpy(&packetBuffer[BL_DATA_ADDR],\r
- (uint8 *) BL_META_BASE(btldrData), 56u);\r
+ (uint8 *) BL_META_BASE(btldrData),\r
+ BL_GET_METADATA_RESPONSE_SIZE);\r
#endif /* (CY_PSOC3) */\r
\r
rspSize = 56u;\r
/***************************************************************************\r
* Get flash size\r
***************************************************************************/\r
+\r
+ /* Replace BL_NUM_OF_FLASH_ARRAYS with CY_FLASH_NUMBER_ARRAYS */\r
+\r
+\r
#if(0u != BL_CMD_GET_FLASH_SIZE_AVAIL)\r
\r
case BL_COMMAND_REPORT_SIZE:\r
\r
+ /* btldrData - holds flash array ID sent by host */\r
+\r
if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u))\r
{\r
- /* btldrData holds flash array ID sent by host */\r
- if(btldrData < BL_NUM_OF_FLASH_ARRAYS)\r
+ if(btldrData < CY_FLASH_NUMBER_ARRAYS)\r
{\r
- #if (1u == BL_NUM_OF_FLASH_ARRAYS)\r
- uint16 CYDATA startRow = (uint16)*BL_SizeBytesAccess / CYDEV_FLS_ROW_SIZE;\r
- #else\r
- uint16 CYDATA startRow = 0u;\r
- #endif /* (1u == BL_NUM_OF_FLASH_ARRAYS) */\r
+ uint16 CYDATA startRow;\r
+ uint8 CYDATA ArrayIdBtlderEnds;\r
+\r
+\r
+ /*******************************************************************************\r
+ * - For the flash array where bootloader application ends, return the first\r
+ * full row after the bootloader application.\r
+ *\r
+ * - For the fully occupied flash array, the number of rows in array is returned.\r
+ * As there is no space for the bootloadable application in this array.\r
+ *\r
+ * - For the arrays next to the occupied array, zero is returned.\r
+ * The bootloadable application can written from the their beginning.\r
+ *\r
+ *******************************************************************************/\r
+ ArrayIdBtlderEnds = (uint8) (*BL_SizeBytesAccess / CY_FLASH_SIZEOF_ARRAY);\r
+\r
+ if (btldrData == ArrayIdBtlderEnds)\r
+ {\r
+ startRow = (uint16) (*BL_SizeBytesAccess / CY_FLASH_SIZEOF_ROW) %\r
+ BL_NUMBER_OF_ROWS_IN_ARRAY;\r
+ }\r
+ else if (btldrData > ArrayIdBtlderEnds)\r
+ {\r
+ startRow = BL_FIRST_ROW_IN_ARRAY;\r
+ }\r
+ else /* (btldrData < ArrayIdBtlderEnds) */\r
+ {\r
+ startRow = BL_NUMBER_OF_ROWS_IN_ARRAY;\r
+ }\r
\r
packetBuffer[BL_DATA_ADDR] = LO8(startRow);\r
packetBuffer[BL_DATA_ADDR + 1u] = HI8(startRow);\r
- packetBuffer[BL_DATA_ADDR + 2u] = LO8(CY_FLASH_NUMBER_ROWS - 1u);\r
- packetBuffer[BL_DATA_ADDR + 3u] = HI8(CY_FLASH_NUMBER_ROWS - 1u);\r
+\r
+ packetBuffer[BL_DATA_ADDR + 2u] =\r
+ LO8(BL_NUMBER_OF_ROWS_IN_ARRAY - 1u);\r
+\r
+ packetBuffer[BL_DATA_ADDR + 3u] =\r
+ HI8(BL_NUMBER_OF_ROWS_IN_ARRAY - 1u);\r
\r
rspSize = 4u;\r
ackCode = CYRET_SUCCESS;\r
(uint8)BL_ValidateBootloadable(btldrData);\r
\r
packetBuffer[BL_DATA_ADDR + 1u] =\r
- (uint8)BL_MD_BTLDB_ACTIVE_VALUE(btldrData);\r
+ (uint8) BL_GetMetadata(BL_GET_BTLDB_ACTIVE, btldrData);\r
\r
rspSize = 2u;\r
ackCode = CYRET_SUCCESS;\r
#if(CY_PSOC3)\r
(void) memset(dataBuffer, (char8) 0, (int16) dataOffset);\r
#else\r
- (void) memset(dataBuffer, 0, dataOffset);\r
+ (void) memset(dataBuffer, 0, (uint32) dataOffset);\r
#endif /* (CY_PSOC3) */\r
}\r
else\r
#if(CY_PSOC3)\r
(void) memcpy(&dataBuffer[dataOffset],\r
&packetBuffer[BL_DATA_ADDR + 3u],\r
- ( int16 )pktSize - 3);\r
+ (int16) pktSize - 3);\r
#else\r
(void) memcpy(&dataBuffer[dataOffset],\r
&packetBuffer[BL_DATA_ADDR + 3u],\r
- pktSize - 3u);\r
+ (uint32) pktSize - 3u);\r
#endif /* (CY_PSOC3) */\r
\r
dataOffset += (pktSize - 3u);\r
/* Check if we have all data to program */\r
if(dataOffset == pktSize)\r
{\r
- /* Get FLASH/EEPROM row number */\r
+ uint16 row;\r
+ uint16 firstRow;\r
+\r
+ /* Get FLASH/EEPROM row number inside of the array */\r
dataOffset = ((uint16)((uint16)packetBuffer[BL_DATA_ADDR + 2u] << 8u)) |\r
packetBuffer[BL_DATA_ADDR + 1u];\r
\r
+\r
+ /* Metadata section resides in Flash (cannot be in EEPROM). */\r
#if(!CY_PSOC4)\r
if(btldrData <= BL_LAST_FLASH_ARRAYID)\r
{\r
#endif /* (!CY_PSOC4) */\r
\r
- #if(0u == BL_DUAL_APP_BOOTLOADER)\r
\r
- if(0u == clearedMetaData)\r
- {\r
- /* Metadata section must be filled with zeroes */\r
+ /* btldrData - holds flash array Id sent by host */\r
+ /* dataOffset - holds flash row Id sent by host */\r
+ row = (uint16)(btldrData * BL_NUMBER_OF_ROWS_IN_ARRAY) + dataOffset;\r
\r
- uint8 erase[BL_FROW_SIZE];\r
\r
- #if(CY_PSOC3)\r
- (void) memset(erase, (char8) 0, (int16) BL_FROW_SIZE);\r
- #else\r
- (void) memset(erase, 0, BL_FROW_SIZE);\r
- #endif /* (CY_PSOC3) */\r
+ /*******************************************************************************\r
+ * Refuse to write to the row within range of the bootloader application\r
+ *******************************************************************************/\r
\r
- #if(CY_PSOC4)\r
- (void) CySysFlashWriteRow(BL_MD_ROW, erase);\r
- #else\r
- (void) CyWriteRowFull((uint8) BL_MD_FLASH_ARRAY_NUM,\r
- (uint16) BL_MD_ROW,\r
- erase,\r
- BL_FROW_SIZE);\r
- #endif /* (CY_PSOC4) */\r
+ /* First empty flash row after bootloader application */\r
+ firstRow = (uint16) (*BL_SizeBytesAccess / CYDEV_FLS_ROW_SIZE);\r
+ if ((*BL_SizeBytesAccess % CYDEV_FLS_ROW_SIZE) != 0u)\r
+ {\r
+ firstRow++;\r
+ }\r
\r
- /* Set up flag that metadata was cleared */\r
- clearedMetaData = 1u;\r
- }\r
+ /* Check to see if the row to program will not corrupt the bootloader application */\r
+ if(row < firstRow)\r
+ {\r
+ ackCode = BL_ERR_ROW;\r
+ dataOffset = 0u;\r
+ break;\r
+ }\r
\r
- #else\r
+\r
+ #if(0u != BL_DUAL_APP_BOOTLOADER)\r
\r
if(BL_activeApp < BL_MD_BTLDB_ACTIVE_NONE)\r
{\r
- /* First active bootloadable application row */\r
- uint16 firstRow = (uint16) 1u +\r
- (uint16) BL_GetMetadata(BL_GET_METADATA_BTLDR_LAST_ROW,\r
+ uint16 lastRow;\r
+\r
+\r
+ /*******************************************************************************\r
+ * For the first bootloadable application gets the last flash row occupied by\r
+ * the bootloader application image:\r
+ * ---------------------------------------------------------------------------\r
+ * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 |\r
+ * ---------------------------------------------------------------------------\r
+ * |<--firstRow---|>\r
+ *\r
+ * For the second bootloadable application gets the last flash row occupied by\r
+ * the first bootloadable application:\r
+ * ---------------------------------------------------------------------------\r
+ * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 |\r
+ * ---------------------------------------------------------------------------\r
+ * |<-------------firstRow-----------------|>\r
+ *\r
+ * Incremented by 1 to get the first available row.\r
+ *\r
+ * Note: M1 and M2 stands for the metadata # 1 and metadata # 2, metadata\r
+ * sections for the 1st and 2nd bootloadable applications.\r
+ *******************************************************************************/\r
+ firstRow = (uint16) 1u +\r
+ (uint16) BL_GetMetadata(BL_GET_BTLDR_LAST_ROW,\r
BL_activeApp);\r
\r
- #if(CY_PSOC4)\r
- uint16 row = dataOffset;\r
- #else\r
- uint16 row = (uint16)(btldrData * (CYDEV_FLS_SECTOR_SIZE / CYDEV_FLS_ROW_SIZE)) +\r
- dataOffset;\r
- #endif /* (CY_PSOC4) */\r
+\r
+ /*******************************************************************************\r
+ * The number of flash rows available for the both bootloadable applications:\r
+ *\r
+ * First bootloadable application is active:\r
+ * ---------------------------------------------------------------------------\r
+ * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 |\r
+ * ---------------------------------------------------------------------------\r
+ * |<-------------------lastRow -------------------->|\r
+ *\r
+ * Second bootloadable application is active:\r
+ * ---------------------------------------------------------------------------\r
+ * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 |\r
+ * ---------------------------------------------------------------------------\r
+ * |<-------lastRow-------->|\r
+ *******************************************************************************/\r
+ lastRow = (uint16)(CY_FLASH_NUMBER_ROWS -\r
+ BL_NUMBER_OF_METADATA_ROWS -\r
+ firstRow);\r
\r
\r
/*******************************************************************************\r
- * Last row is equal to the first row plus the number of rows available for each\r
- * app. To compute this, we first subtract the number of appliaction images from\r
- * the total flash rows: (CY_FLASH_NUMBER_ROWS - 2u).\r
+ * The number of flash rows available for the active bootloadable application:\r
*\r
- * Then subtract off the first row:\r
- * App Rows = (CY_FLASH_NUMBER_ROWS - 2u - firstRow)\r
- * Then divide that number by the number of application that must fit within the\r
- * space, if we are app1 then that number is 2, if app2 then 1. Our divisor is\r
- * then: (2u - BL_activeApp).\r
+ * First bootloadable application is active: the number of flash rows available\r
+ * for the both bootloadable applications should be divided by 2 - 2 bootloadable\r
+ * applications should fit there.\r
*\r
- * Adding this number to firstRow gives the address right beyond our valid range\r
- * so we subtract 1.\r
+ * Second bootloadable application is active: the number of flash rows available\r
+ * for the both bootloadable applications should be divided by 1 - 1 bootloadable\r
+ * application should fit there.\r
*******************************************************************************/\r
- uint16 lastRow = (firstRow - 1u) +\r
- ((uint16)((CYDEV_FLASH_SIZE / CYDEV_FLS_ROW_SIZE) - 2u - firstRow) /\r
- ((uint16)2u - (uint16)BL_activeApp));\r
+ lastRow = lastRow / (BL_NUMBER_OF_BTLDBLE_APPS -\r
+ BL_activeApp);\r
\r
\r
/*******************************************************************************\r
- * Check to see if the row to program is within the range of the active\r
- * application, or if it maches the active application's metadata row. If so,\r
- * refuse to program as it would corrupt the active app.\r
+ * The last row equals to the first row plus the number of rows available for\r
+ * the each bootloadable application. That gives the flash row number right\r
+ * beyond the valid range, so we subtract 1.\r
+ *\r
+ * First bootloadable application is active:\r
+ * ---------------------------------------------------------------------------\r
+ * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 |\r
+ * ---------------------------------------------------------------------------\r
+ * |<----------------lastRow ------------->|\r
+ *\r
+ * Second bootloadable application is active:\r
+ * ---------------------------------------------------------------------------\r
+ * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 |\r
+ * ---------------------------------------------------------------------------\r
+ * |<-----------------------------lastRow-------------------------->|\r
+ *******************************************************************************/\r
+ lastRow = (firstRow + lastRow) - 1u;\r
+\r
+\r
+ /*******************************************************************************\r
+ * 1. Refuse to write row within the range of the active application\r
+ *\r
+ * First bootloadable application is active:\r
+ * ---------------------------------------------------------------------------\r
+ * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 |\r
+ * ---------------------------------------------------------------------------\r
+ * |<----------------lastRow ------------->|\r
+ * |<--firstRow---|>\r
+ * |<-------protected------>|\r
+ *\r
+ * Second bootloadable application is active:\r
+ * ---------------------------------------------------------------------------\r
+ * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 |\r
+ * ---------------------------------------------------------------------------\r
+ * |<-------------firstRow-----------------|>\r
+ * |<-----------------------------lastRow-------------------------->|\r
+ * |<-------protected------>|\r
+ *\r
+ * 2. Refuse to write to the row that contains metadata of the active\r
+ * bootloadable application.\r
+ *\r
*******************************************************************************/\r
if(((row >= firstRow) && (row <= lastRow)) ||\r
((btldrData == BL_MD_FLASH_ARRAY_NUM) &&\r
}\r
}\r
\r
- #endif /* (0u == BL_DUAL_APP_BOOTLOADER) */\r
+ #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */\r
\r
- #if(!CY_PSOC4)\r
+\r
+\r
+ /*******************************************************************************\r
+ * Clear row that contains the metadata, when 'Fast bootloadable application\r
+ * validation' option is enabled.\r
+ *\r
+ * If 'Fast bootloadable application validation' option is enabled, the\r
+ * bootloader only computes the checksum the first time and assumes that it\r
+ * remains valid in each future startup. The metadata row is cleared because the\r
+ * bootloadable application might become corrupted during update, while\r
+ * 'Bootloadable Application Verification Status' field will still report that\r
+ * application is valid.\r
+ *******************************************************************************/\r
+ #if(0u != BL_FAST_APP_VALIDATION)\r
+\r
+ if(0u == clearedMetaData)\r
+ {\r
+ /* Metadata section must be filled with zeros */\r
+\r
+ uint8 erase[BL_FROW_SIZE];\r
+ uint8 BL_notActiveApp;\r
+\r
+\r
+ #if(CY_PSOC3)\r
+ (void) memset(erase, (char8) 0, (int16) BL_FROW_SIZE);\r
+ #else\r
+ (void) memset(erase, 0, BL_FROW_SIZE);\r
+ #endif /* (CY_PSOC3) */\r
+\r
+\r
+ #if(0u != BL_DUAL_APP_BOOTLOADER)\r
+ if (BL_MD_BTLDB_ACTIVE_0 == BL_activeApp)\r
+ {\r
+ BL_notActiveApp = BL_MD_BTLDB_ACTIVE_1;\r
+ }\r
+ else\r
+ {\r
+ BL_notActiveApp = BL_MD_BTLDB_ACTIVE_0;\r
+ }\r
+ #else\r
+ BL_notActiveApp = BL_MD_BTLDB_ACTIVE_0;\r
+ #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */\r
+\r
+\r
+ #if(CY_PSOC4)\r
+ (void) CySysFlashWriteRow(\r
+ BL_MD_ROW_NUM(BL_notActiveApp),\r
+ erase);\r
+ #else\r
+ (void) CyWriteRowFull(\r
+ (uint8) BL_MD_FLASH_ARRAY_NUM,\r
+ (uint16) BL_MD_ROW_NUM(BL_notActiveApp),\r
+ erase,\r
+ BL_FROW_SIZE);\r
+ #endif /* (CY_PSOC4) */\r
+\r
+ /* PSoC 5: Do not care about flushing the cache as flash row has been erased. */\r
+\r
+ /* Set up flag that metadata was cleared */\r
+ clearedMetaData = 1u;\r
}\r
+\r
+ #endif /* (0u != BL_FAST_APP_VALIDATION) */\r
+\r
+\r
+ #if(!CY_PSOC4)\r
+ } /* (btldrData <= BL_LAST_FLASH_ARRAYID) */\r
#endif /* (!CY_PSOC4) */\r
\r
- #if(CY_PSOC4)\r
\r
- ackCode = (CYRET_SUCCESS != CySysFlashWriteRow((uint32) dataOffset, dataBuffer)) \\r
+ #if(CY_PSOC4)\r
+ ackCode = (CYRET_SUCCESS != CySysFlashWriteRow((uint32) row, dataBuffer)) \\r
? BL_ERR_ROW \\r
: CYRET_SUCCESS;\r
-\r
#else\r
-\r
ackCode = (CYRET_SUCCESS != CyWriteRowFull(btldrData, dataOffset, dataBuffer, pktSize)) \\r
? BL_ERR_ROW \\r
: CYRET_SUCCESS;\r
-\r
#endif /* (CY_PSOC4) */\r
\r
+\r
+ #if(CY_PSOC5)\r
+ /***************************************************************************\r
+ * When writing Flash, data in the instruction cache can become stale.\r
+ * Therefore, the cache data does not correlate to the data just written to\r
+ * Flash. A call to CyFlushCache() is required to invalidate the data in the\r
+ * cache and force fresh information to be loaded from Flash.\r
+ ***************************************************************************/\r
+ CyFlushCache();\r
+ #endif /* (CY_PSOC5) */\r
+\r
}\r
else\r
{\r
/* If something failed the host would send this command to reset the bootloader. */\r
dataOffset = 0u;\r
\r
- /* Don't ack the packet, just get ready to accept the next one */\r
+ /* Don't acknowledge the packet, just get ready to accept the next one */\r
continue;\r
}\r
break;\r
\r
\r
/***************************************************************************\r
- * Set active application\r
+ * Set an active application\r
***************************************************************************/\r
#if(0u != BL_DUAL_APP_BOOTLOADER)\r
\r
#else\r
(void) memcpy(&dataBuffer[dataOffset],\r
&packetBuffer[BL_DATA_ADDR],\r
- pktSize);\r
+ (uint32) pktSize);\r
#endif /* (CY_PSOC3) */\r
\r
dataOffset += pktSize;\r
#else\r
(void) memcpy(&packetBuffer[BL_DATA_ADDR],\r
&BtldrVersion,\r
- rspSize);\r
+ (uint32) rspSize);\r
#endif /* (CY_PSOC3) */\r
\r
ackCode = CYRET_SUCCESS;\r
/***************************************************************************\r
* Verify row\r
***************************************************************************/\r
+ #if (0u != BL_CMD_VERIFY_ROW_AVAIL)\r
+\r
case BL_COMMAND_VERIFY:\r
\r
if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 3u))\r
/* Both PSoC 3 and PSoC 5LP architectures have one EEPROM array. */\r
rowAddr = (uint32)rowNum * CYDEV_EEPROM_ROW_SIZE;\r
\r
- checksum = BL_Calc8BitEepromSum(rowAddr, CYDEV_EEPROM_ROW_SIZE);\r
+ checksum = BL_Calc8BitSum(CY_EEPROM_BASE, rowAddr, CYDEV_EEPROM_ROW_SIZE);\r
}\r
else\r
{\r
rowAddr = ((uint32)btldrData * CYDEV_FLS_SECTOR_SIZE)\r
+ ((uint32)rowNum * CYDEV_FLS_ROW_SIZE);\r
\r
- checksum = BL_Calc8BitFlashSum(rowAddr, CYDEV_FLS_ROW_SIZE);\r
+ checksum = BL_Calc8BitSum(CY_FLASH_BASE, rowAddr, CYDEV_FLS_ROW_SIZE);\r
}\r
\r
#else\r
uint32 CYDATA rowAddr = ((uint32)btldrData * CYDEV_FLS_SECTOR_SIZE)\r
+ ((uint32)rowNum * CYDEV_FLS_ROW_SIZE);\r
\r
- uint8 CYDATA checksum = BL_Calc8BitFlashSum(rowAddr, CYDEV_FLS_ROW_SIZE);\r
+ uint8 CYDATA checksum = BL_Calc8BitSum(CY_FLASH_BASE,\r
+ rowAddr,\r
+ CYDEV_FLS_ROW_SIZE);\r
\r
#endif /* (!CY_PSOC4) */\r
\r
\r
\r
/*******************************************************************************\r
- * App Verified & App Active are information that is updated in flash at runtime\r
- * remove these items from the checksum to allow the host to verify everything is\r
+ * App Verified & App Active are information that is updated in Flash at runtime.\r
+ * Remove these items from the checksum to allow the host to verify everything is\r
* correct.\r
******************************************************************************/\r
if((BL_MD_FLASH_ARRAY_NUM == btldrData) &&\r
(BL_CONTAIN_METADATA(rowNum)))\r
{\r
- checksum -= BL_MD_BTLDB_ACTIVE_VALUE (BL_GET_APP_ID(rowNum));\r
- checksum -= BL_MD_BTLDB_VERIFIED_VALUE(BL_GET_APP_ID(rowNum));\r
+\r
+ checksum -= (uint8)BL_GetMetadata(BL_GET_BTLDB_ACTIVE,\r
+ BL_GET_APP_ID(rowNum));\r
+\r
+ checksum -= (uint8)BL_GetMetadata(BL_GET_BTLDB_STATUS,\r
+ BL_GET_APP_ID(rowNum));\r
}\r
\r
packetBuffer[BL_DATA_ADDR] = (uint8)1u + (uint8)(~checksum);\r
}\r
break;\r
\r
+ #endif /* (0u != BL_CMD_VERIFY_ROW_AVAIL) */\r
+\r
\r
/***************************************************************************\r
* Exit bootloader\r
\r
if(CYRET_SUCCESS == BL_ValidateBootloadable(BL_activeApp))\r
{\r
- BL_SET_RUN_TYPE(BL_START_APP);\r
+ BL_SET_RUN_TYPE(BL_SCHEDULE_BTLDB);\r
}\r
\r
CySoftwareReset();\r
}\r
}\r
\r
- /* ?CK the packet and function. */\r
+ /* Reply with acknowledge or not acknowledge packet */\r
(void) BL_WritePacket(ackCode, packetBuffer, rspSize);\r
\r
} while ((0u == timeOut) || (BL_COMMUNICATION_STATE_ACTIVE == communicationState));\r
********************************************************************************\r
*\r
* Summary:\r
-* Creates a bootloader responce packet and transmits it back to the bootloader\r
+* Creates a bootloader response packet and transmits it back to the bootloader\r
* host application over the already established communications protocol.\r
*\r
* Parameters:\r
* The number of bytes contained within the buffer to pass back\r
*\r
* Return:\r
-* CYRET_SUCCESS if successful.\r
-* CYRET_UNKNOWN if there was an error tranmitting the packet.\r
+* CYRET_SUCCESS if successful. Any other non-zero value if failure occurred.\r
*\r
*******************************************************************************/\r
static cystatus BL_WritePacket(uint8 status, uint8 buffer[], uint16 size) CYSMALL \\r
{\r
uint16 CYDATA checksum;\r
\r
- /* Start of the packet. */\r
+ /* Start of packet. */\r
buffer[BL_SOP_ADDR] = BL_SOP;\r
buffer[BL_CMD_ADDR] = status;\r
buffer[BL_SIZE_ADDR] = LO8(size);\r
buffer[BL_SIZE_ADDR + 1u] = HI8(size);\r
\r
- /* Compute the checksum. */\r
+ /* Compute checksum. */\r
checksum = BL_CalcPacketChecksum(buffer, size + BL_DATA_ADDR);\r
\r
buffer[BL_CHK_ADDR(size)] = LO8(checksum);\r
buffer[BL_CHK_ADDR(1u + size)] = HI8(checksum);\r
buffer[BL_EOP_ADDR(size)] = BL_EOP;\r
\r
- /* Start the packet transmit. */\r
+ /* Start packet transmit. */\r
return(CyBtldrCommWrite(buffer, size + BL_MIN_PKT_SIZE, &size, 150u));\r
}\r
\r
********************************************************************************\r
*\r
* Summary:\r
-* Writes byte a flash memory location\r
+* Writes a byte to the specified Flash memory location.\r
*\r
* Parameters:\r
* address:\r
-* Address in Flash memory where data will be written\r
+* The address in Flash memory where data will be written\r
*\r
* runType:\r
* Byte to be written\r
uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE);\r
#endif /* !(CY_PSOC4) */\r
\r
- uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);\r
+ #if (CY_PSOC4)\r
+ uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE);\r
+ #else\r
+ uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);\r
+ #endif /* (CY_PSOC4) */\r
+\r
uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE);\r
uint16 idx;\r
\r
#else\r
(void) CyWriteRowData(arrayId, rowNum, rowData);\r
#endif /* (CY_PSOC4) */\r
+\r
+ #if(CY_PSOC5)\r
+ /***************************************************************************\r
+ * When writing Flash, data in the instruction cache can become stale.\r
+ * Therefore, the cache data does not correlate to the data just written to\r
+ * Flash. A call to CyFlushCache() is required to invalidate the data in the\r
+ * cache and force fresh information to be loaded from Flash.\r
+ ***************************************************************************/\r
+ CyFlushCache();\r
+ #endif /* (CY_PSOC5) */\r
}\r
\r
\r
********************************************************************************\r
*\r
* Summary:\r
-* Returns value of the multi-byte field.\r
+* Returns the value of the specified field of the metadata section.\r
*\r
* Parameters:\r
-* fieldName:\r
+* field:\r
* The field to get data from:\r
-* BL_GET_METADATA_BTLDB_ADDR\r
-* BL_GET_METADATA_BTLDR_LAST_ROW\r
-* BL_GET_METADATA_BTLDB_LENGTH\r
-* BL_GET_METADATA_BTLDR_APP_VERSION\r
-* BL_GET_METADATA_BTLDB_APP_VERSION\r
-* BL_GET_METADATA_BTLDB_APP_ID\r
-* BL_GET_METADATA_BTLDB_APP_CUST_ID\r
+* BL_GET_BTLDB_CHECKSUM - Bootloadable Application Checksum\r
+* BL_GET_BTLDB_ADDR - Bootloadable Application Start\r
+* Routine Address\r
+* BL_GET_BTLDR_LAST_ROW - Bootloader Last Flash Row\r
+* BL_GET_BTLDB_LENGTH - Bootloadable Application Length\r
+* BL_GET_BTLDB_ACTIVE - Active Bootloadable Application\r
+* BL_GET_BTLDB_STATUS - Bootloadable Application\r
+* Verification Status\r
+* BL_GET_BTLDR_APP_VERSION - Bootloader Application Version\r
+* BL_GET_BTLDB_APP_VERSION - Bootloadable Application Version\r
+* BL_GET_BTLDB_APP_ID - Bootloadable Application ID\r
+* BL_GET_BTLDB_APP_CUST_ID - Bootloadable Application Custom ID\r
*\r
* appId:\r
-* Number of the bootlodable application.\r
+* Number of the bootlodable application. Should be 0 for the normal\r
+* bootloader and 0 or 1 for the Multi-Application bootloader.\r
*\r
* Return:\r
-* None\r
+* The value of the specified field of the specified application.\r
*\r
*******************************************************************************/\r
-static uint32 BL_GetMetadata(uint8 fieldName, uint8 appId)\r
+uint32 BL_GetMetadata(uint8 field, uint8 appId)\r
{\r
uint32 fieldPtr;\r
uint8 fieldSize = 2u;\r
- uint32 result;\r
+ uint32 result = 0u;\r
\r
- switch (fieldName)\r
+ switch (field)\r
{\r
- case BL_GET_METADATA_BTLDB_APP_CUST_ID:\r
- fieldPtr = BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId);\r
- fieldSize = 4u;\r
- break;\r
-\r
- case BL_GET_METADATA_BTLDR_APP_VERSION:\r
- fieldPtr = BL_MD_BTLDR_APP_VERSION_OFFSET(appId);\r
+ case BL_GET_BTLDB_CHECKSUM:\r
+ fieldPtr = BL_MD_BTLDB_CHECKSUM_OFFSET(appId);\r
+ fieldSize = 1u;\r
break;\r
\r
- case BL_GET_METADATA_BTLDB_ADDR:\r
+ case BL_GET_BTLDB_ADDR:\r
fieldPtr = BL_MD_BTLDB_ADDR_OFFSET(appId);\r
#if(!CY_PSOC3)\r
fieldSize = 4u;\r
#endif /* (!CY_PSOC3) */\r
break;\r
\r
- case BL_GET_METADATA_BTLDR_LAST_ROW:\r
+ case BL_GET_BTLDR_LAST_ROW:\r
fieldPtr = BL_MD_BTLDR_LAST_ROW_OFFSET(appId);\r
break;\r
\r
- case BL_GET_METADATA_BTLDB_LENGTH:\r
+ case BL_GET_BTLDB_LENGTH:\r
fieldPtr = BL_MD_BTLDB_LENGTH_OFFSET(appId);\r
#if(!CY_PSOC3)\r
fieldSize = 4u;\r
#endif /* (!CY_PSOC3) */\r
break;\r
\r
- case BL_GET_METADATA_BTLDB_APP_VERSION:\r
+ case BL_GET_BTLDB_ACTIVE:\r
+ fieldPtr = BL_MD_BTLDB_ACTIVE_OFFSET(appId);\r
+ fieldSize = 1u;\r
+ break;\r
+\r
+ case BL_GET_BTLDB_STATUS:\r
+ fieldPtr = BL_MD_BTLDB_VERIFIED_OFFSET(appId);\r
+ fieldSize = 1u;\r
+ break;\r
+\r
+ case BL_GET_BTLDB_APP_VERSION:\r
fieldPtr = BL_MD_BTLDB_APP_VERSION_OFFSET(appId);\r
break;\r
\r
- case BL_GET_METADATA_BTLDB_APP_ID:\r
+ case BL_GET_BTLDR_APP_VERSION:\r
+ fieldPtr = BL_MD_BTLDR_APP_VERSION_OFFSET(appId);\r
+ break;\r
+\r
+ case BL_GET_BTLDB_APP_ID:\r
fieldPtr = BL_MD_BTLDB_APP_ID_OFFSET(appId);\r
break;\r
\r
+ case BL_GET_BTLDB_APP_CUST_ID:\r
+ fieldPtr = BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId);\r
+ fieldSize = 4u;\r
+ break;\r
+\r
default:\r
/* Should never be here */\r
CYASSERT(0u != 0u);\r
}\r
\r
\r
- /* Read all fields as big-endian */\r
- if (2u == fieldSize)\r
- {\r
- result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u));\r
- result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *) fieldPtr ) << 8u;\r
- }\r
- else\r
+ if (1u == fieldSize)\r
{\r
- result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 3u));\r
- result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 2u)) << 8u;\r
- result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)) << 16u;\r
- result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr )) << 24u;\r
+ result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)fieldPtr);\r
}\r
\r
- /* Following fields should be little-endian */\r
-#if(!CY_PSOC3)\r
- switch (fieldName)\r
- {\r
- case BL_GET_METADATA_BTLDR_LAST_ROW:\r
- result = CYSWAP_ENDIAN16(result);\r
- break;\r
+ #if(CY_PSOC3) /* Big-endian */\r
\r
- case BL_GET_METADATA_BTLDB_ADDR:\r
- case BL_GET_METADATA_BTLDB_LENGTH:\r
- result = CYSWAP_ENDIAN32(result);\r
- break;\r
+ if (2u == fieldSize)\r
+ {\r
+ result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u));\r
+ result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr )) << 8u;\r
+ }\r
\r
- default:\r
- break;\r
- }\r
+ if (4u == fieldSize)\r
+ {\r
+ result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 3u));\r
+ result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 2u)) << 8u;\r
+ result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)) << 16u;\r
+ result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr )) << 24u;\r
+ }\r
\r
-#endif /* (!CY_PSOC3) */\r
+ #else /* PSoC 4 and PSoC 5: Little-endian */\r
+\r
+ if (2u == fieldSize)\r
+ {\r
+ result = (uint32) CY_GET_XTND_REG8((volatile uint8 *) (fieldPtr ));\r
+ result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *) (fieldPtr + 1u)) << 8u;\r
+ }\r
+\r
+ if (4u == fieldSize)\r
+ {\r
+ result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr ));\r
+ result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)) << 8u;\r
+ result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 2u)) << 16u;\r
+ result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 3u)) << 24u;\r
+ }\r
+\r
+ #endif /* (CY_PSOC3) */\r
\r
return (result);\r
}\r
/*******************************************************************************\r
* File Name: BL.h\r
-* Version 1.20\r
+* Version 1.30\r
*\r
* Description:\r
* Provides an API for the Bootloader. The API includes functions for starting\r
* application.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#define CY_BOOTLOADER_BL_H\r
\r
#include "cytypes.h"\r
-\r
-\r
-/* Check to see if required defines such as CY_PSOC5LP are available */\r
-/* They are defined starting with cy_boot v3.0 */\r
-#if !defined (CY_PSOC5LP)\r
- #error Component Bootloader_v1_20 requires cy_boot v3.0 or later\r
-#endif /* (CY_ PSOC5X) */\r
-\r
+#include "CyFlash.h"\r
\r
#define BL_DUAL_APP_BOOTLOADER (0u)\r
#define BL_BOOTLOADER_APP_VERSION (0u)\r
#define BL_SCHEDULE_BTLDR (0x40u)\r
#define BL_SCHEDULE_MASK (0xC0u)\r
\r
-\r
#if defined(__ARMCC_VERSION) || defined (__GNUC__)\r
__attribute__((section (".bootloader")))\r
#elif defined (__ICCARM__)\r
\r
/*******************************************************************************\r
* Get the reason of the device reset\r
-* Return cyBtldrRunType in case if software reset was reset reason and\r
+* Return cyBtldrRunType in the case if software reset was the reset reason and\r
* set cyBtldrRunType to zero (bootloader application is scheduled - that is\r
-* initial clean state) and return zero.\r
+* the initial clean state) and return zero.\r
*******************************************************************************/\r
#if(CY_PSOC4)\r
#define BL_GET_RUN_TYPE (cyBtldrRunType)\r
#endif /* (CY_PSOC4) */\r
\r
\r
-/* Returns the number of Flash arrays availalbe in the device */\r
-#define BL_NUM_OF_FLASH_ARRAYS (CYDEV_FLASH_SIZE / CYDEV_FLS_SECTOR_SIZE)\r
+/* Returns the number of Flash arrays available in the device */\r
+#ifndef CY_FLASH_NUMBER_ARRAYS\r
+ #define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLASH_SIZE / CYDEV_FLS_SECTOR_SIZE)\r
+#endif /* CY_FLASH_NUMBER_ARRAYS */\r
\r
\r
/*******************************************************************************\r
void BL_SetFlashByte(uint32 address, uint8 runType);\r
void CyBtldr_CheckLaunch(void) CYSMALL ;\r
void BL_Start(void) CYSMALL ;\r
+cystatus BL_ValidateBootloadable(uint8 appId) \\r
+ CYSMALL ;\r
+uint8 BL_Calc8BitSum(uint32 baseAddr, uint32 start, uint32 size) CYSMALL \\r
+ ;\r
+uint32 BL_GetMetadata(uint8 field, uint8 appId) \\r
+ ;\r
+void BL_Exit(uint8 appId) CYSMALL ;\r
\r
#if(CY_PSOC3)\r
/* Implementation for the PSoC 3 resides in a BL_psoc3.a51 file. */\r
- extern void BL_LaunchBootloadable(uint32 appAddr);\r
+ void BL_LaunchBootloadable(uint32 appAddr);\r
#endif /* (CY_PSOC3) */\r
\r
-/* If using custom interface as the IO Component, user must provide these functions */\r
+/* When using a custom interface as the IO Component, the user must provide these functions */\r
#if defined(CYDEV_BOOTLOADER_IO_COMP) && (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)\r
\r
extern void CyBtldrCommStart(void);\r
#endif /* defined(CYDEV_BOOTLOADER_IO_COMP) && (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface) */\r
\r
\r
+/*******************************************************************************\r
+* BL_GetMetadata()\r
+*******************************************************************************/\r
+#define BL_GET_BTLDB_CHECKSUM (1u)\r
+#define BL_GET_BTLDB_ADDR (2u)\r
+#define BL_GET_BTLDR_LAST_ROW (3u)\r
+#define BL_GET_BTLDB_LENGTH (4u)\r
+#define BL_GET_BTLDB_ACTIVE (5u)\r
+#define BL_GET_BTLDB_STATUS (6u)\r
+#define BL_GET_BTLDR_APP_VERSION (7u)\r
+#define BL_GET_BTLDB_APP_VERSION (8u)\r
+#define BL_GET_BTLDB_APP_ID (9u)\r
+#define BL_GET_BTLDB_APP_CUST_ID (10u)\r
+\r
+#define BL_GET_METADATA_RESPONSE_SIZE (56u)\r
+\r
+/*******************************************************************************\r
+* BL_Exit()\r
+*******************************************************************************/\r
+#define BL_EXIT_TO_BTLDR (2u)\r
+#define BL_EXIT_TO_BTLDB (0u)\r
+#if(0u != BL_DUAL_APP_BOOTLOADER)\r
+ #define BL_EXIT_TO_BTLDB_1 (0u)\r
+ #define BL_EXIT_TO_BTLDB_2 (1u)\r
+#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */\r
+\r
+\r
/*******************************************************************************\r
* Kept for backward compatibility.\r
*******************************************************************************/\r
#if(0u != BL_DUAL_APP_BOOTLOADER)\r
#define BL_ValidateApp(x) BL_ValidateBootloadable((x))\r
- #define BL_ValidateApplication \\r
+ #define BL_ValidateApplication() \\r
BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0)\r
#else\r
- #define BL_ValidateApplication \\r
+ #define BL_ValidateApplication() \\r
BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0)\r
#define BL_ValidateApp(x) BL_ValidateBootloadable((x))\r
#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */\r
+#define BL_Calc8BitFlashSum(start, size) BL_Calc8BitSum(CY_FLASH_BASE, (start), (size))\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from version 1.10\r
+* The following code is DEPRECATED and must not be used.\r
*******************************************************************************/\r
#define BL_BOOTLOADABLE_APP_VALID (BL_BOOTLOADER_APP_VALIDATION)\r
#define CyBtldr_Start BL_Start\r
\r
-\r
-/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from version 1.20\r
-*******************************************************************************/\r
+#define BL_NUM_OF_FLASH_ARRAYS (CYDEV_FLASH_SIZE / CYDEV_FLS_SECTOR_SIZE)\r
#define BL_META_BASE(x) (CYDEV_FLASH_BASE + \\r
(CYDEV_FLASH_SIZE - (( uint32 )(x) * CYDEV_FLS_ROW_SIZE) - \\r
BL_META_DATA_SIZE))\r
BL_META_APP_CHECKSUM_OFFSET)\r
#if(0u == BL_DUAL_APP_BOOTLOADER)\r
#define BL_MD_BASE BL_META_BASE(0u)\r
- #define BL_MD_ROW ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \\r
- - 1u)\r
+\r
+ #if(!CY_PSOC4)\r
+ #define BL_MD_ROW ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \\r
+ - 1u)\r
+ #else\r
+ #define BL_MD_ROW (CY_FLASH_NUMBER_ROWS - 1u)\r
+ #endif /* (CY_PSOC4) */\r
+\r
#define BL_MD_CHECKSUM_ADDR BL_META_CHECKSUM_ADDR(0u)\r
#define BL_MD_LAST_BLDR_ROW_ADDR BL_META_LAST_BLDR_ROW_ADDR(0u)\r
#define BL_MD_APP_BYTE_LEN BL_META_APP_BYTE_LEN(0u)\r
#define BL_MD_APP_ENTRY_POINT_ADDR BL_META_APP_ENTRY_POINT_ADDR(0u)\r
#define BL_MD_APP_RUN_ADDR BL_META_APP_RUN_ADDR(0u)\r
#else\r
- #define BL_MD_ROW(x) ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \\r
- - 1u - ( uint32 )(x))\r
+ #if(!CY_PSOC4)\r
+ #define BL_MD_ROW(x) ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \\r
+ - 1u - ( uint32 )(x))\r
+ #else\r
+ #define BL_MD_ROW(x) (CY_FLASH_NUMBER_ROWS - 1u - ( uint32 )(x))\r
+ #endif /* (CY_PSOC4) */\r
+\r
#define BL_MD_CHECKSUM_ADDR BL_META_CHECKSUM_ADDR(appId)\r
#define BL_MD_LAST_BLDR_ROW_ADDR BL_META_LAST_BLDR_ROW_ADDR(appId)\r
#define BL_MD_APP_BYTE_LEN BL_META_APP_BYTE_LEN(appId)\r
#define BL_START_APP (BL_SCHEDULE_BTLDB)\r
#define BL_START_BTLDR (BL_SCHEDULE_BTLDR)\r
\r
-/* Some PSoC Creator versions used to generate only one name types */\r
+/* Some PSoC Creator versions are used to generate only one name types */\r
#if !defined (CYDEV_FLASH_BASE)\r
#define CYDEV_FLASH_BASE (CYDEV_FLS_BASE)\r
#endif /* !defined (CYDEV_FLASH_BASE) */\r
/*******************************************************************************\r
* File Name: BL_PVT.h\r
-* Version 1.20\r
+* Version 1.30\r
*\r
* Description:\r
* Provides an API for the Bootloader.\r
*\r
********************************************************************************\r
-* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
\r
#define BL_VERSION {\\r
- (uint8)20, \\r
+ (uint8)30, \\r
(uint8)1, \\r
(uint8)0x01u \\r
}\r
#define BL_EOP (0x17u) /* End of Packet */\r
\r
\r
-/* Bootloader command responces */\r
+/* Bootloader command responses */\r
#define BL_ERR_KEY (0x01u) /* The provided key does not match the expected value */\r
#define BL_ERR_VERIFY (0x02u) /* The verification of flash failed */\r
#define BL_ERR_LENGTH (0x03u) /* The amount of data available is outside the expected range */\r
BL_ValidateBootloadable()\r
*******************************************************************************/\r
#define BL_FIRST_APP_BYTE(appId) ((uint32)CYDEV_FLS_ROW_SIZE * \\r
- ((uint32) BL_GetMetadata(BL_GET_METADATA_BTLDR_LAST_ROW, appId) + \\r
+ ((uint32) BL_GetMetadata(BL_GET_BTLDR_LAST_ROW, appId) + \\r
(uint32) 1u))\r
\r
#define BL_MD_BTLDB_IS_VERIFIED (0x01u)\r
#define BL_WAIT_FOR_COMMAND_FOREVER (0x00u)\r
\r
\r
- /* Maximum number of bytes accepted in a packet plus some */\r
+ /* The maximum number of bytes accepted in a packet plus some */\r
#define BL_SIZEOF_COMMAND_BUFFER (300u)\r
\r
\r
#endif /* (0u != BL_PACKET_CHECKSUM_CRC) */\r
\r
\r
-/*******************************************************************************\r
-* BL_GetMetadata()\r
-*******************************************************************************/\r
-#define BL_GET_METADATA_BTLDB_ADDR (1u)\r
-#define BL_GET_METADATA_BTLDR_LAST_ROW (2u)\r
-#define BL_GET_METADATA_BTLDB_LENGTH (3u)\r
-#define BL_GET_METADATA_BTLDR_APP_VERSION (4u)\r
-#define BL_GET_METADATA_BTLDB_APP_VERSION (5u)\r
-#define BL_GET_METADATA_BTLDB_APP_ID (6u)\r
-#define BL_GET_METADATA_BTLDB_APP_CUST_ID (7u)\r
-\r
-\r
/*******************************************************************************\r
* CyBtldr_CheckLaunch()\r
*******************************************************************************/\r
\r
\r
/*******************************************************************************\r
-* Metadata base address. In case of bootloader application, the metadata is\r
-* placed at row N-1; in case of multi-application bootloader, the bootloadable\r
-* application number 1 will use row N-1, and application number 2 will use row\r
-* N-2 to store its metadata, where N is the total number of rows for the\r
-* selected device.\r
+* The Metadata base address. In the case of the bootloader application, the\r
+* metadata is placed at row N-1; in the case of the multi-application\r
+* bootloader, the bootloadable application number 1 will use row N-1, and\r
+* application number 2 will use row N-2 to store its metadata, where N is the\r
+* total number of the rows for the selected device.\r
*******************************************************************************/\r
#define BL_MD_BASE_ADDR(appId) (CYDEV_FLASH_BASE + \\r
(CYDEV_FLASH_SIZE - ((uint32)(appId) * CYDEV_FLS_ROW_SIZE) - \\r
\r
#define BL_MD_FLASH_ARRAY_NUM (BL_NUM_OF_FLASH_ARRAYS - 1u)\r
\r
-#define BL_MD_ROW_NUM(appId) ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) - \\r
- 1u - (uint32)(appId))\r
+#if(!CY_PSOC4)\r
+ #define BL_MD_ROW_NUM(appId) ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) - \\r
+ 1u - (uint32)(appId))\r
+#else\r
+ #define BL_MD_ROW_NUM(appId) (CY_FLASH_NUMBER_ROWS - 1u - (uint32)(appId))\r
+#endif /* (!CY_PSOC4) */\r
+\r
\r
#define BL_MD_BTLDB_CHECKSUM_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 0u)\r
#if(CY_PSOC3)\r
#define BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 24u)\r
\r
\r
-/*******************************************************************************\r
-* Macro for 1 byte long metadata fields\r
-*******************************************************************************/\r
-#define BL_MD_BTLDB_CHECKSUM_PTR (appId) \\r
- ((reg8 *)(BL_MD_BTLDB_CHECKSUM_OFFSET(appId)))\r
-#define BL_MD_BTLDB_CHECKSUM_VALUE(appId) \\r
- (CY_GET_XTND_REG8(BL_MD_BTLDB_CHECKSUM_OFFSET(appId)))\r
-\r
-#define BL_MD_BTLDB_ACTIVE_PTR(appId) \\r
- ((reg8 *)(BL_MD_BTLDB_ACTIVE_OFFSET(appId)))\r
-#define BL_MD_BTLDB_ACTIVE_VALUE(appId) \\r
- (CY_GET_XTND_REG8(BL_MD_BTLDB_ACTIVE_OFFSET(appId)))\r
-\r
-#define BL_MD_BTLDB_VERIFIED_PTR(appId) \\r
- ((reg8 *)(BL_MD_BTLDB_VERIFIED_OFFSET(appId)))\r
-#define BL_MD_BTLDB_VERIFIED_VALUE(appId) \\r
- (CY_GET_XTND_REG8(BL_MD_BTLDB_VERIFIED_OFFSET(appId)))\r
-\r
-\r
-/*******************************************************************************\r
-* Macro for multiple bytes long metadata fields pointers \r
-*******************************************************************************/\r
-#define BL_MD_BTLDB_ADDR_PTR (appId) \\r
- ((reg8 *)(BL_MD_BTLDB_ADDR_OFFSET(appId)))\r
-\r
-#define BL_MD_BTLDR_LAST_ROW_PTR (appId) \\r
- ((reg8 *)(BL_MD_BTLDR_LAST_ROW_OFFSET(appId)))\r
-\r
-#define BL_MD_BTLDB_LENGTH_PTR(appId) \\r
- ((reg8 *)(BL_MD_BTLDB_LENGTH_OFFSET(appId)))\r
-\r
-#define BL_MD_BTLDR_APP_VERSION_PTR(appId) \\r
- ((reg8 *)(BL_MD_BTLDR_APP_VERSION_OFFSET(appId)))\r
-\r
-#define BL_MD_BTLDB_APP_ID_PTR(appId) \\r
- ((reg8 *)(BL_MD_BTLDB_APP_ID_OFFSET(appId)))\r
-\r
-#define BL_MD_BTLDB_APP_VERSION_PTR(appId) \\r
- ((reg8 *)(BL_MD_BTLDB_APP_VERSION_OFFSET(appId)))\r
-\r
-#define BL_MD_BTLDB_APP_CUST_ID_PTR(appId) \\r
- ((reg8 *)(BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId)))\r
-\r
-\r
/*******************************************************************************\r
* Get data byte from FLASH\r
*******************************************************************************/\r
\r
\r
/*******************************************************************************\r
-* Offset of the Bootloader application in flash\r
+* Number of addresses remapped from Flash to RAM, when interrupt vectors are\r
+* configured to be stored in RAM (default setting, configured by cy_boot).\r
*******************************************************************************/\r
#if(CY_PSOC4)\r
#define BL_MD_BTLDR_ADDR_PTR (0xC0u) /* Exclude the vector */\r
\r
\r
/*******************************************************************************\r
-* Maximum number of Bootloadable applications\r
+* The maximum number of Bootloadable applications\r
*******************************************************************************/\r
#if(1u == BL_DUAL_APP_BOOTLOADER)\r
#define BL_MAX_NUM_OF_BTLDB (0x02u)\r
\r
\r
/*******************************************************************************\r
-* Returns TRUE if row specified as parameter contains metadata section\r
+* Returns TRUE if the row specified as a parameter contains a metadata section\r
*******************************************************************************/\r
#if(0u != BL_DUAL_APP_BOOTLOADER)\r
#define BL_CONTAIN_METADATA(row) \\r
\r
\r
/*******************************************************************************\r
-* Metadata section is located at the last flash row for the Boootloader, for the\r
-* Multi-Application Bootloader, metadata section of the Bootloadable application\r
-* # 0 is located at the last flash row, and metadata section of the Bootloadable\r
-* application # 1 is located in the flash row before last.\r
+* The Metadata section is located in the last flash row for the Boootloader, for\r
+* the Multi-Application Bootloader, the metadata section of the Bootloadable\r
+* application # 0 is located in the last flash row, and the metadata section of\r
+* the Bootloadable application # 1 is located in the flash row before last.\r
*******************************************************************************/\r
#if(0u != BL_DUAL_APP_BOOTLOADER)\r
#define BL_GET_APP_ID(row) \\r
#define BL_GET_APP_ID(row) (BL_MD_BTLDB_ACTIVE_0)\r
#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */\r
\r
+\r
+/*******************************************************************************\r
+* Defines the number of flash rows reserved for the metadata section\r
+*******************************************************************************/\r
+#if(0u == BL_DUAL_APP_BOOTLOADER)\r
+ #define BL_NUMBER_OF_METADATA_ROWS (1u)\r
+#else\r
+ #define BL_NUMBER_OF_METADATA_ROWS (2u)\r
+#endif /* (0u == BL_DUAL_APP_BOOTLOADER) */\r
+\r
+\r
+/*******************************************************************************\r
+* Defines the number of possible bootloadable applications\r
+*******************************************************************************/\r
+#if(0u == BL_DUAL_APP_BOOTLOADER)\r
+ #define BL_NUMBER_OF_BTLDBLE_APPS (1u)\r
+#else\r
+ #define BL_NUMBER_OF_BTLDBLE_APPS (2u)\r
+#endif /* (0u == BL_DUAL_APP_BOOTLOADER) */\r
+\r
+#define BL_NUMBER_OF_ROWS_IN_ARRAY ((uint16)(CY_FLASH_SIZEOF_ARRAY/CY_FLASH_SIZEOF_ROW))\r
+#define BL_FIRST_ROW_IN_ARRAY (0u)\r
+\r
#endif /* CY_BOOTLOADER_BL_PVT_H */\r
\r
\r
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };\r
define block HSTACK {block HEAP, last block CSTACK};\r
\r
+if (CY_APPL_LOADABLE)\r
+{\r
define block LOADER { readonly section .cybootloader };\r
+}\r
define block APPL with fixed order {readonly section .romvectors, readonly};\r
\r
/* The address of Flash row next after Bootloader image */\r
do not initialize { readwrite section .ramvectors };\r
\r
/******** Placements *********/\r
+if (CY_APPL_LOADABLE)\r
+{\r
".cybootloader" : place at start of ROM_region {block LOADER};\r
+}\r
+\r
"APPL" : place at start of APPL_region {block APPL};\r
\r
"RAMVEC" : place at start of RAM_region { readwrite section .ramvectors };\r
section .cymeta };\r
\r
".cyloadermeta" : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };\r
+if (CY_APPL_LOADABLE)\r
+{\r
".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };\r
+}\r
".cyconfigecc" : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc };\r
".cycustnvl" : place at address mem : 0x90000000 { readonly section .cycustnvl };\r
".cywolatch" : place at address mem : 0x90100000 { readonly section .cywolatch };\r
\r
;********************************************************************************\r
;* File Name: Cm3RealView.scat\r
-;* Version 4.0\r
+;* Version 4.20\r
;*\r
;* Description:\r
;* This Linker Descriptor file describes the memory layout of the PSoC5\r
;*\r
;* Note:\r
;*\r
-;* romvectors: Cypress default Interrupt sevice routine vector table.\r
+;* romvectors: Cypress default Interrupt service routine vector table.\r
;*\r
;* This is the ISR vector table at bootup. Used only for the reset vector.\r
;*\r
;*\r
;*\r
;********************************************************************************\r
-;* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+;* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
;* You may use this file only in accordance with the license, terms, conditions,\r
;* disclaimers, and limitations in the end user license agreement accompanying\r
;* the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: Cm3Start.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Startup code for the ARM CM3.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
extern void __iar_data_init3 (void);\r
#endif /* (__ARMCC_VERSION) */\r
\r
+#if defined(__GNUC__)\r
+ #include <errno.h>\r
+ extern int errno;\r
+ extern int end;\r
+#endif /* defined(__GNUC__) */\r
+\r
/* Global variables */\r
#if !defined (__ICCARM__)\r
CY_NOINIT static uint32 cySysNoInitDataValid;\r
********************************************************************************\r
*\r
* Summary:\r
-* This function is called for all interrupts, other than reset, that get\r
+* This function is called for all interrupts, other than a reset that gets\r
* called before the system is setup.\r
*\r
* Parameters:\r
while(1)\r
{\r
/***********************************************************************\r
- * We should never get here. If we do, a serious problem occured, so go\r
+ * We must not get here. If we do, a serious problem occurs, so go\r
* into an infinite loop.\r
***********************************************************************/\r
}\r
\r
#if defined(__ARMCC_VERSION)\r
\r
-/* Local function for the device reset. */\r
+/* Local function for device reset. */\r
extern void Reset(void);\r
\r
/* Application entry point. */\r
********************************************************************************\r
*\r
* Summary:\r
-* This function is called imediatly before the users main\r
+* This function is called immediately before the users main\r
*\r
* Parameters:\r
* None\r
\r
while (1)\r
{\r
- /* If main returns it is undefined what we should do. */\r
+ /* If main returns, it is undefined what we should do. */\r
}\r
}\r
\r
/* Application entry point. */\r
extern int main(void);\r
\r
-/* The static objects constructors initializer */\r
+/* Static objects constructors initializer */\r
extern void __libc_init_array(void);\r
\r
typedef unsigned char __cy_byte_align8 __attribute ((aligned (8)));\r
#define __cy_region_num ((size_t)&__cy_region_num)\r
\r
\r
+/*******************************************************************************\r
+* System Calls of the Red Hat newlib C Library\r
+*******************************************************************************/\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: _exit\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Exit a program without cleaning up files. If your system doesn't provide\r
+* this, it is best to avoid linking with subroutines that require it (exit,\r
+* system).\r
+*\r
+* Parameters:\r
+* status: Status caused program exit.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+__attribute__((weak))\r
+void _exit(int status)\r
+{\r
+ /* Cause divide by 0 exception */\r
+ int x = status / (int) INT_MAX;\r
+ x = 4 / x;\r
+\r
+ while(1)\r
+ {\r
+\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: _sbrk\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Increase program data space. As malloc and related functions depend on this,\r
+* it is useful to have a working implementation. The following suffices for a\r
+* standalone system; it exploits the symbol end automatically defined by the\r
+* GNU linker.\r
+*\r
+* Parameters:\r
+* nbytes: The number of bytes requested (if the parameter value is positive)\r
+* from the heap or returned back to the heap (if the parameter value is\r
+* negative).\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+__attribute__((weak))\r
+void * _sbrk (int nbytes)\r
+{\r
+ extern int end; /* Symbol defined by linker map. Start of free memory (as symbol). */\r
+ void * returnValue;\r
+\r
+ /* The statically held previous end of the heap, with its initialization. */\r
+ static void *heapPointer = (void *) &end; /* Previous end */\r
+\r
+ if (((heapPointer + nbytes) - (void *) &end) <= CYDEV_HEAP_SIZE)\r
+ {\r
+ returnValue = heapPointer;\r
+ heapPointer += nbytes;\r
+ }\r
+ else\r
+ {\r
+ errno = ENOMEM;\r
+ returnValue = (void *) -1;\r
+ }\r
+\r
+ return (returnValue);\r
+}\r
+\r
+\r
/*******************************************************************************\r
* Function Name: Reset\r
********************************************************************************\r
Start_c();\r
}\r
\r
-__attribute__((weak))\r
-void _exit(int status)\r
-{\r
- /* Cause a divide by 0 exception */\r
- int x = status / INT_MAX;\r
- x = 4 / x;\r
-\r
- while(1)\r
- {\r
- }\r
-}\r
\r
/*******************************************************************************\r
* Function Name: Start_c\r
*\r
* Summary:\r
* This function handles initializing the .data and .bss sections in\r
-* preperation for running standard C code. Once initialization is complete\r
+* preparation for running the standard C code. Once initialization is complete\r
* it will call main(). This function will never return.\r
*\r
* Parameters:\r
const struct __cy_region *rptr = __cy_regions;\r
\r
/* Initialize memory */\r
- for (regions = __cy_region_num, rptr = __cy_regions; regions--; rptr++)\r
+ for (regions = __cy_region_num; regions != 0u; regions--)\r
{\r
uint32 *src = (uint32 *)rptr->init;\r
uint32 *dst = (uint32 *)rptr->data;\r
\r
for (count = 0u; count != limit; count += sizeof (uint32))\r
{\r
- *dst++ = *src++;\r
+ *dst = *src;\r
+ dst++;\r
+ src++;\r
}\r
limit = rptr->zero_size;\r
for (count = 0u; count != limit; count += sizeof (uint32))\r
{\r
- *dst++ = 0u;\r
+ *dst = 0u;\r
+ dst++;\r
}\r
+\r
+ rptr++;\r
}\r
\r
/* Invoke static objects constructors */\r
********************************************************************************\r
*\r
* Summary:\r
-* This function perform early initializations for the IAR Embedded\r
-* Workbench IDE. It is executed in the context of reset interrupt handler\r
+* This function performs early initializations for the IAR Embedded\r
+* Workbench IDE. It is executed in the context of a reset interrupt handler\r
* before the data sections are initialized.\r
*\r
* Parameters:\r
const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] =\r
#endif /* defined (__ICCARM__) */\r
{\r
- INITIAL_STACK_POINTER, /* The initial stack pointer 0 */\r
- #if defined (__ICCARM__) /* The reset handler 1 */\r
+ INITIAL_STACK_POINTER, /* Initial stack pointer 0 */\r
+ #if defined (__ICCARM__) /* Reset handler 1 */\r
__iar_program_start,\r
#else\r
(cyisraddress)&Reset,\r
#endif /* defined (__ICCARM__) */\r
- &IntDefaultHandler, /* The NMI handler 2 */\r
- &IntDefaultHandler, /* The hard fault handler 3 */\r
+ &IntDefaultHandler, /* NMI handler 2 */\r
+ &IntDefaultHandler, /* Hard fault handler 3 */\r
};\r
\r
#if defined(__ARMCC_VERSION)\r
/* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */\r
CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1);\r
\r
- /* Point NVIC at the RAM vector table. */\r
+ /* Point NVIC at RAM vector table. */\r
*CYINT_VECT_TABLE = CyRamVectors;\r
\r
/* Initialize the configuration registers. */\r
\r
#if(0u != DMA_CHANNELS_USED__MASK0)\r
\r
- /* Setup DMA - only necessary if the design contains a DMA component. */\r
+ /* Setup DMA - only necessary if design contains DMA component. */\r
CyDmacConfigure();\r
\r
#endif /* (0u != DMA_CHANNELS_USED__MASK0) */\r
/*******************************************************************************\r
* File Name: CyBootAsmGnu.s\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Assembly routines for GNU as.\r
*\r
********************************************************************************\r
-* Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2010-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
;-------------------------------------------------------------------------------\r
; FILENAME: CyBootAsmIar.s\r
-; Version 4.0\r
+; Version 4.20\r
;\r
; DESCRIPTION:\r
; Assembly routines for IAR Embedded Workbench IDE.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions,\r
; disclaimers, and limitations in the end user license agreement accompanying\r
; the software package with which this file was provided.\r
;\r
; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit\r
; with interrupts still enabled. The test and set of the interrupt bits is not\r
-; atomic. Therefore, to avoid corrupting processor state, it must be the policy \r
+; atomic. Therefore, to avoid a corrupting processor state, it must be the policy \r
; that all interrupt routines restore the interrupt enable bits as they were \r
; found on entry.\r
;\r
;-------------------------------------------------------------------------------\r
; FILENAME: CyBootAsmRv.s\r
-; Version 4.0\r
+; Version 4.20\r
;\r
; DESCRIPTION:\r
; Assembly routines for RealView.\r
;\r
;-------------------------------------------------------------------------------\r
-; Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright 2010-2014, Cypress Semiconductor Corporation. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions,\r
; disclaimers, and limitations in the end user license agreement accompanying\r
; the software package with which this file was provided.\r
;\r
; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit\r
; with interrupts still enabled. The test and set of the interrupt bits is not\r
-; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid\r
+; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a\r
; corrupting processor state, it must be the policy that all interrupt routines\r
; restore the interrupt enable bits as they were found on entry.\r
;\r
/*******************************************************************************\r
* File Name: CyDmac.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides an API for the DMAC component. The API includes functions for the\r
* not being used.\r
*\r
* This code uses the first byte of each TD to manage the free list of TD's.\r
-* The user can over write this once the TD is allocated.\r
+* The user can overwrite this once the TD is allocated.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
* are initialized. To avoid zeroing, these variables should be initialized\r
* properly during segments initialization as well.\r
*******************************************************************************/\r
-static uint8 CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; /* Current Number of free elements in the list */\r
-static uint8 CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of the first available TD */\r
+static uint8 CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; /* Current Number of free elements on list */\r
+static uint8 CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of first available TD */\r
static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0; /* Bit map of DMA channel ownership */\r
\r
\r
*\r
* Summary:\r
* Creates a linked list of all the TDs to be allocated. This function is called\r
-* by the startup code; you do not normally need to call it. You could call this\r
+* by the startup code; you do not normally need to call it. You can call this\r
* function if all of the DMA channels are inactive.\r
*\r
* Parameters:\r
CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u);\r
}\r
\r
- /* Make the last one point to zero. */\r
+ /* Make last one point to zero. */\r
CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = 0u;\r
}\r
\r
* are determined by the BUS_TIMEOUT field in the PHUBCFG register.\r
*\r
* Theory:\r
-* Once an error occurs the error bits are sticky and are only cleared by a\r
-* write 1 to the error register.\r
+* Once an error occurs the error bits are sticky and are only cleared by \r
+* writing 1 to the error register.\r
*\r
*******************************************************************************/\r
uint8 CyDmacError(void) \r
* Set to 1 when an access is attempted to an invalid address.\r
*\r
* DMAC_BUS_TIMEOUT:\r
-* Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values\r
+* Set to 1 when a bus timeout occurs. Cleared by writing 1. Timeout values\r
* are determined by the BUS_TIMEOUT field in the PHUBCFG register.\r
*\r
* Return:\r
* None\r
*\r
* Theory:\r
-* Once an error occurs the error bits are sticky and are only cleared by a\r
-* write 1 to the error register.\r
+* Once an error occurs the error bits are sticky and are only cleared by \r
+* writing 1 to the error register.\r
*\r
*******************************************************************************/\r
void CyDmacClearError(uint8 error) \r
********************************************************************************\r
*\r
* Summary:\r
-* When an DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC and DMAC_PERIPH_ERR occurs the\r
+* When DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC, and DMAC_PERIPH_ERR occur the\r
* address of the error is written to the error address register and can be read\r
* with this function.\r
*\r
/* Enter critical section! */\r
interruptState = CyEnterCriticalSection();\r
\r
- /* Look for a free channel. */\r
+ /* Look for free channel. */\r
for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++)\r
{\r
if(0uL == (CyDmaChannels & channel))\r
{\r
- /* Mark the channel as used. */\r
+ /* Mark channel as used. */\r
CyDmaChannels |= channel;\r
break;\r
}\r
/* Enter critical section */\r
interruptState = CyEnterCriticalSection();\r
\r
- /* Clear the bit mask that keeps track of ownership. */\r
+ /* Clear bit mask that keeps track of ownership. */\r
CyDmaChannels &= ~(((uint32) 1u) << chHandle);\r
\r
/* Exit critical section */\r
* Preserves the original TD state when the TD has completed. This parameter\r
* applies to all TDs in the channel.\r
*\r
-* 0 - When a TD is completed, the DMAC leaves the TD configuration values in\r
+* 0 - When TD is completed, the DMAC leaves the TD configuration values in\r
* their current state, and does not restore them to their original state.\r
*\r
-* 1 - When a TD is completed, the DMAC restores the original configuration\r
+* 1 - When TD is completed, the DMAC restores the original configuration\r
* values of the TD.\r
*\r
* When preserveTds is set, the TD slot that equals the channel number becomes\r
{\r
if (0u != preserveTds)\r
{\r
- /* Store the intermediate TD states separately in CHn_SEP_TD0/1 to\r
- * preserve the original TD chain\r
+ /* Store intermediate TD states separately in CHn_SEP_TD0/1 to\r
+ * preserve original TD chain\r
*/\r
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP;\r
}\r
else\r
{\r
- /* Store the intermediate and final TD states on top of the original TD chain */\r
+ /* Store intermediate and final TD states on top of original TD chain */\r
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP);\r
}\r
\r
/* Disable channel */\r
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN));\r
\r
- /* Store the intermediate and final TD states on top of the original TD chain */\r
+ /* Store intermediate and final TD states on top of original TD chain */\r
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP));\r
status = CYRET_SUCCESS;\r
}\r
********************************************************************************\r
*\r
* Summary:\r
-* Clears pending DMA data request.\r
+* Clears pending the DMA data request.\r
*\r
* Parameters:\r
* uint8 chHandle:\r
* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().\r
*\r
* uint8 startTd:\r
-* The index of TD to set as the first TD associated with the channel. Zero is\r
+* Set the TD index as the first TD associated with the channel. Zero is\r
* a valid TD index.\r
*\r
* Return:\r
\r
if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS)\r
{\r
- /* Get pointer to the Next available. */\r
+ /* Get pointer to Next available. */\r
element = CyDmaTdFreeIndex;\r
\r
/* Decrement the count. */\r
CyDmaTdCurrentNumber--;\r
\r
- /* Update the next available pointer. */\r
+ /* Update next available pointer. */\r
CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0];\r
}\r
\r
/* Enter critical section! */\r
uint8 interruptState = CyEnterCriticalSection();\r
\r
- /* Get pointer to the Next available. */\r
+ /* Get pointer to Next available. */\r
CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex;\r
\r
/* Set new Next Available. */\r
* CYRET_BAD_PARAM if tdHandle is invalid.\r
*\r
* Side Effects:\r
-* If a TD has a transfer count of N and is executed, the transfer count becomes\r
+* If TD has a transfer count of N and is executed, the transfer count becomes\r
* 0. If it is reexecuted, the Transfer count of zero will be interpreted as a\r
-* request for indefinite transfer. Be careful when requesting a TD with a\r
+* request for indefinite transfer. Be careful when requesting TD with a\r
* transfer count of zero.\r
*\r
*******************************************************************************/\r
\r
if(tdHandle < CY_DMA_NUMBEROF_TDS)\r
{\r
- /* If we have a pointer */\r
+ /* If we have pointer */\r
if(NULL != transferCount)\r
{\r
- /* Get the 12 bits of the transfer count */\r
+ /* Get 12 bits of transfer count */\r
reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0];\r
*transferCount = 0x0FFFu & CY_GET_REG16(convert);\r
}\r
\r
- /* If we have a pointer */\r
+ /* If we have pointer */\r
if(NULL != nextTd)\r
{\r
- /* Get the Next TD pointer */\r
+ /* Get Next TD pointer */\r
*nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u];\r
}\r
\r
- /* If we have a pointer */\r
+ /* If we have pointer */\r
if(NULL != configuration)\r
{\r
- /* Get the configuration the TD */\r
+ /* Get configuration TD */\r
*configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u];\r
}\r
\r
/*******************************************************************************\r
* File Name: CyDmac.h\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides the function definitions for the DMA Controller.\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
#define CY_DMA_TD_SIZE 0x08u\r
\r
-/* The "u" was removed as workaround for Keil compiler bug */\r
+/* "u" was removed as workaround for Keil compiler bug */\r
#define CY_DMA_TD_SWAP_EN 0x80\r
#define CY_DMA_TD_SWAP_SIZE4 0x40\r
#define CY_DMA_TD_AUTO_EXEC_NEXT 0x20\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0\r
+* The following code is OBSOLETE and must not be used.\r
+*\r
+* If the obsoleted macro definitions intended for use in the application use the\r
+* following scheme, redefine your own versions of these definitions:\r
+* #ifdef <OBSOLETED_DEFINE>\r
+* #undef <OBSOLETED_DEFINE>\r
+* #define <OBSOLETED_DEFINE> (<New Value>)\r
+* #endif\r
+*\r
+* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* used in the application and their modification might lead to unexpected\r
+* consequences.\r
*******************************************************************************/\r
#define DMA_INVALID_CHANNEL (CY_DMA_INVALID_CHANNEL)\r
#define DMA_INVALID_TD (CY_DMA_INVALID_TD)\r
/*******************************************************************************\r
* File Name: CyFlash.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides an API for the FLASH/EEPROM.\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
#include "CyFlash.h"\r
\r
+/* The number of EEPROM arrays */\r
+#define CY_FLASH_EEPROM_NUMBER_ARRAYS (1u)\r
+\r
\r
/*******************************************************************************\r
-* Holds die temperature, updated by CySetTemp(). Used for flash writting.\r
+* Holds the die temperature, updated by CySetTemp(). Used for flash writing.\r
* The first byte is the sign of the temperature (0 = negative, 1 = positive).\r
* The second byte is the magnitude.\r
*******************************************************************************/\r
\r
\r
static cystatus CySetTempInt(void);\r
+static cystatus CyFlashGetSpcAlgorithm(void);\r
\r
\r
/*******************************************************************************\r
*******************************************************************************/\r
void CyFlash_Start(void) \r
{\r
- /* Active Power Mode */\r
- *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;\r
+ uint8 interruptState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+\r
+ /***************************************************************************\r
+ * Enable SPC clock. This also internally enables the 36MHz IMO, since this\r
+ * is required for the SPC to function.\r
+ ***************************************************************************/\r
+ CY_FLASH_PM_ACT_CFG0_REG |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;\r
+ CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;\r
+\r
\r
- /* Standby Power Mode */\r
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;\r
+ /***************************************************************************\r
+ * The wake count defines the number of Bus Clock cycles it takes for the\r
+ * flash or eeprom to wake up from a low power mode independent of the chip\r
+ * power mode. Wake up time for these blocks is 5 us.\r
+ * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E\r
+ * (30d) defines the wake up time as 60 cycles of the Bus Clock.\r
+ * This register needs to be written with a value dependent on the Bus Clock\r
+ * frequency so that the duration of the cycles is equal to or greater than\r
+ * the 5 us delay required.\r
+ ***************************************************************************/\r
+ CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;\r
+\r
+\r
+ /***************************************************************************\r
+ * Enable flash. Active flash macros consume current, but re-enabling a\r
+ * disabled flash macro takes 5us. If the CPU attempts to fetch out of the\r
+ * macro during that time, it will be stalled. This bit allows the flash to\r
+ * be enabled even if the CPU is disabled, which allows a quicker return to\r
+ * code execution.\r
+ ***************************************************************************/\r
+ CY_FLASH_PM_ACT_CFG12_REG |= CY_FLASH_PM_ACT_CFG12_EN_FM;\r
+ CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_FM;\r
+\r
+ while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))\r
+ {\r
+ /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */\r
+ }\r
\r
- CyDelayUs(CY_FLASH_EE_STARTUP_DELAY);\r
+ CyExitCriticalSection(interruptState);\r
}\r
\r
\r
*******************************************************************************/\r
void CyFlash_Stop(void) \r
{\r
- /* Active Power Mode */\r
- *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));\r
+ uint8 interruptState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ CY_FLASH_PM_ACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_FM));\r
+ CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_FM));\r
\r
- /* Standby Power Mode */\r
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));\r
+ CyExitCriticalSection(interruptState);\r
}\r
\r
\r
*\r
* Summary:\r
* Sends a command to the SPC to read the die temperature. Sets a global value\r
-* used by the Write functions. This function must be called once before\r
+* used by the Write function. This function must be called once before\r
* executing a series of Flash writing functions.\r
*\r
* Parameters:\r
}\r
\r
\r
+/*******************************************************************************\r
+* Function Name: CyFlashGetSpcAlgorithm\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sends a command to the SPC to download code into RAM.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* status:\r
+* CYRET_SUCCESS - if successful\r
+* CYRET_LOCKED - if Flash writing already in use\r
+* CYRET_UNKNOWN - if there was an SPC error\r
+*\r
+*******************************************************************************/\r
+static cystatus CyFlashGetSpcAlgorithm(void) \r
+{\r
+ cystatus status;\r
+\r
+ /* Make sure SPC is powered */\r
+ CySpcStart();\r
+\r
+ if(CySpcLock() == CYRET_SUCCESS)\r
+ {\r
+ status = CySpcGetAlgorithm();\r
+\r
+ if(CYRET_STARTED == status)\r
+ {\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Spin until idle. */\r
+ CyDelayUs(1u);\r
+ }\r
+\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ }\r
+ }\r
+ CySpcUnlock();\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+\r
+ return (status);\r
+}\r
+\r
+\r
/*******************************************************************************\r
* Function Name: CySetTemp\r
********************************************************************************\r
*\r
* Summary:\r
-* This is a wraparound for CySetTempInt(). It is used to return second\r
-* successful read of temperature value.\r
+* This is a wraparound for CySetTempInt(). It is used to return the second\r
+* successful read of the temperature value.\r
*\r
* Parameters:\r
* None\r
* CYRET_UNKNOWN if there was an SPC error.\r
*\r
* uint8 dieTemperature[2]:\r
-* Holds die temperature for the flash writting algorithm. The first byte is\r
+* Holds the die temperature for the flash writing algorithm. The first byte is\r
* the sign of the temperature (0 = negative, 1 = positive). The second byte is\r
* the magnitude.\r
*\r
*******************************************************************************/\r
cystatus CySetTemp(void) \r
{\r
- cystatus status = CySetTempInt();\r
+ cystatus status = CyFlashGetSpcAlgorithm();\r
\r
if(status == CYRET_SUCCESS)\r
{\r
*\r
* Summary:\r
* Sets the user supplied temporary buffer to store SPC data while performing\r
-* flash and EEPROM commands. This buffer is only necessary when Flash ECC is\r
+* Flash and EEPROM commands. This buffer is only necessary when the Flash ECC is\r
* disabled.\r
*\r
* Parameters:\r
* buffer:\r
-* Address of block of memory to store temporary memory. The size of the block\r
+* The address of a block of memory to store temporary memory. The size of the block\r
* of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE.\r
*\r
* Return:\r
\r
if(NULL == buffer)\r
{\r
+ rowBuffer = rowBuffer;\r
status = CYRET_BAD_PARAM;\r
}\r
else if(CySpcLock() != CYRET_SUCCESS)\r
{\r
+ rowBuffer = rowBuffer;\r
status = CYRET_LOCKED;\r
}\r
else\r
\r
#else\r
\r
- /* To supress the warning */\r
+ /* To suppress warning */\r
buffer = buffer;\r
\r
#endif /* (CYDEV_ECC_ENABLE == 0u) */\r
}\r
\r
\r
-#if(CYDEV_ECC_ENABLE == 1)\r
-\r
- /*******************************************************************************\r
- * Function Name: CyWriteRowData\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Sends a command to the SPC to load and program a row of data in\r
- * Flash or EEPROM.\r
- *\r
- * Parameters:\r
- * arrayID: ID of the array to write.\r
- * The type of write, Flash or EEPROM, is determined from the array ID.\r
- * The arrays in the part are sequential starting at the first ID for the\r
- * specific memory type. The array ID for the Flash memory lasts from 0x00 to\r
- * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.\r
- * rowAddress: rowAddress of flash row to program.\r
- * rowData: Array of bytes to write.\r
- *\r
- * Return:\r
- * status:\r
- * CYRET_SUCCESS if successful.\r
- * CYRET_LOCKED if the SPC is already in use.\r
- * CYRET_CANCELED if command not accepted\r
- * CYRET_UNKNOWN if there was an SPC error.\r
- *\r
- *******************************************************************************/\r
- cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) \r
- {\r
- uint16 rowSize;\r
- cystatus status;\r
-\r
- rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;\r
- status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);\r
-\r
- return(status);\r
- }\r
-\r
-#else\r
-\r
- /*******************************************************************************\r
- * Function Name: CyWriteRowData\r
- ********************************************************************************\r
- *\r
- * Summary:\r
- * Sends a command to the SPC to load and program a row of data in\r
- * Flash or EEPROM.\r
- *\r
- * Parameters:\r
- * arrayID : ID of the array to write.\r
- * The type of write, Flash or EEPROM, is determined from the array ID.\r
- * The arrays in the part are sequential starting at the first ID for the\r
- * specific memory type. The array ID for the Flash memory lasts from 0x00 to\r
- * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.\r
- * rowAddress : rowAddress of flash row to program.\r
- * rowData : Array of bytes to write.\r
- *\r
- * Return:\r
- * status:\r
- * CYRET_SUCCESS if successful.\r
- * CYRET_LOCKED if the SPC is already in use.\r
- * CYRET_CANCELED if command not accepted\r
- * CYRET_UNKNOWN if there was an SPC error.\r
- *\r
- *******************************************************************************/\r
- cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) \r
- {\r
- uint8 i;\r
- uint32 offset;\r
- uint16 rowSize;\r
- cystatus status;\r
-\r
- /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */\r
- if(NULL != rowBuffer)\r
- {\r
- if(arrayId > CY_SPC_LAST_FLASH_ARRAYID)\r
- {\r
- rowSize = CYDEV_EEPROM_ROW_SIZE;\r
- }\r
- else\r
- {\r
- rowSize = CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE;\r
-\r
- /* Save the ECC area. */\r
- offset = CYDEV_ECC_BASE +\r
- ((uint32)arrayId * CYDEV_ECC_SECTOR_SIZE) +\r
- ((uint32)rowAddress * CYDEV_ECC_ROW_SIZE);\r
-\r
- for(i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)\r
- {\r
- *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i));\r
- }\r
- }\r
-\r
- /* Copy the rowdata to the temporary buffer. */\r
- #if(CY_PSOC3)\r
- (void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE);\r
- #else\r
- (void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE);\r
- #endif /* (CY_PSOC3) */\r
-\r
- status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize);\r
- }\r
- else\r
- {\r
- status = CYRET_UNKNOWN;\r
- }\r
+/*******************************************************************************\r
+* Function Name: CyWriteRowData\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sends a command to the SPC to load and program a row of data in\r
+* Flash or EEPROM.\r
+*\r
+* Parameters:\r
+* arrayID: ID of the array to write.\r
+* The type of write, Flash or EEPROM, is determined from the array ID.\r
+* The arrays in the part are sequential starting at the first ID for the\r
+* specific memory type. The array ID for the Flash memory lasts from 0x00 to\r
+* 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.\r
+* rowAddress: rowAddress of flash row to program.\r
+* rowData: Array of bytes to write.\r
+*\r
+* Return:\r
+* status:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_LOCKED if the SPC is already in use.\r
+* CYRET_CANCELED if command not accepted\r
+* CYRET_UNKNOWN if there was an SPC error.\r
+*\r
+*******************************************************************************/\r
+cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) \r
+{\r
+ uint16 rowSize;\r
+ cystatus status;\r
\r
- return(status);\r
- }\r
+ rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;\r
+ status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);\r
\r
-#endif /* (CYDEV_ECC_ENABLE == 0u) */\r
+ return(status);\r
+}\r
\r
\r
+/*******************************************************************\r
+* If "Enable Error Correcting Code (ECC)" and "Store Configuration\r
+* Data in ECC" DWR options are disabled, ECC section is available\r
+* for user data.\r
+*******************************************************************/\r
#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))\r
\r
/*******************************************************************************\r
********************************************************************************\r
*\r
* Summary:\r
- * Sends a command to the SPC to load and program a row of config data in flash.\r
+ * Sends a command to the SPC to load and program a row of config data in the Flash.\r
* This function is only valid for Flash array IDs (not for EEPROM).\r
*\r
* Parameters:\r
* The arrays in the part are sequential starting at the first ID for the\r
* specific memory type. The array ID for the Flash memory lasts\r
* from 0x00 to 0x3F.\r
- * rowAddress: Address of the sector to erase.\r
- * rowECC: Array of bytes to write.\r
+ * rowAddress: The address of the sector to erase.\r
+ * rowECC: The array of bytes to write.\r
*\r
* Return:\r
* status:\r
cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\\r
\r
{\r
- uint32 offset;\r
- uint16 i;\r
cystatus status;\r
\r
- /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */\r
- if(NULL != rowBuffer)\r
- {\r
- /* Read the existing flash data. */\r
- offset = ((uint32)arrayId * CYDEV_FLS_SECTOR_SIZE) +\r
- ((uint32)rowAddress * CYDEV_FLS_ROW_SIZE);\r
-\r
- #if (CYDEV_FLS_BASE != 0u)\r
- offset += CYDEV_FLS_BASE;\r
- #endif /* (CYDEV_FLS_BASE != 0u) */\r
-\r
- for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)\r
- {\r
- rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i));\r
- }\r
-\r
- #if(CY_PSOC3)\r
- (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],\r
- (void *)(uint32)rowECC,\r
- (int16)CYDEV_ECC_ROW_SIZE);\r
- #else\r
- (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],\r
- (const void *)rowECC,\r
- CYDEV_ECC_ROW_SIZE);\r
- #endif /* (CY_PSOC3) */\r
-\r
- status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);\r
- }\r
- else\r
- {\r
- status = CYRET_UNKNOWN;\r
- }\r
+ status = CyWriteRowFull(arrayId, rowAddress, rowECC, CYDEV_ECC_ROW_SIZE);\r
\r
return (status);\r
}\r
* Function Name: CyWriteRowFull\r
********************************************************************************\r
* Summary:\r
-* Sends a command to the SPC to load and program a row of data in flash.\r
+* Sends a command to the SPC to load and program a row of data in the Flash.\r
* rowData array is expected to contain Flash and ECC data if needed.\r
*\r
* Parameters:\r
cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \\r
\r
{\r
- cystatus status;\r
+ cystatus status = CYRET_SUCCESS;\r
\r
- if(CySpcLock() == CYRET_SUCCESS)\r
+ if((arrayId <= CY_SPC_LAST_FLASH_ARRAYID) && (arrayId > (CY_FLASH_NUMBER_ARRAYS + CY_SPC_FIRST_FLASH_ARRAYID)))\r
{\r
- /* Load row data into SPC internal latch */\r
- status = CySpcLoadRow(arrayId, rowData, rowSize);\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
\r
- if(CYRET_STARTED == status)\r
+ if(arrayId > CY_SPC_LAST_EE_ARRAYID)\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+\r
+ if((arrayId >= CY_SPC_FIRST_EE_ARRAYID) && (arrayId > (CY_FLASH_EEPROM_NUMBER_ARRAYS + CY_SPC_FIRST_EE_ARRAYID)))\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+\r
+ if(arrayId <= CY_SPC_LAST_FLASH_ARRAYID)\r
+ {\r
+ /* Flash */\r
+ if(rowNumber > (CY_FLASH_NUMBER_ROWS/CY_FLASH_NUMBER_ARRAYS))\r
{\r
- while(CY_SPC_BUSY)\r
- {\r
- /* Wait for SPC to finish and get SPC status */\r
- CyDelayUs(1u);\r
- }\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* EEPROM */\r
+ if(rowNumber > (CY_EEPROM_NUMBER_ROWS/CY_FLASH_EEPROM_NUMBER_ARRAYS))\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
\r
- /* Hide SPC status */\r
- if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
- {\r
- status = CYRET_SUCCESS;\r
- }\r
- else\r
- {\r
- status = CYRET_UNKNOWN;\r
- }\r
+ if(CY_EEPROM_SIZEOF_ROW != rowSize)\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+ }\r
\r
- if(CYRET_SUCCESS == status)\r
+ if(rowData == NULL)\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+\r
+\r
+ if(status == CYRET_SUCCESS)\r
+ {\r
+ if(CySpcLock() == CYRET_SUCCESS)\r
+ {\r
+ /* Load row data into SPC internal latch */\r
+ status = CySpcLoadRowFull(arrayId, rowNumber, rowData, rowSize);\r
+\r
+ if(CYRET_STARTED == status)\r
{\r
- /* Erase and program flash with the data from SPC interval latch */\r
- status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Wait for SPC to finish and get SPC status */\r
+ CyDelayUs(1u);\r
+ }\r
\r
- if(CYRET_STARTED == status)\r
+ /* Hide SPC status */\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
{\r
- while(CY_SPC_BUSY)\r
- {\r
- /* Wait for SPC to finish and get SPC status */\r
- CyDelayUs(1u);\r
- }\r
+ status = CYRET_SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
\r
- /* Hide SPC status */\r
- if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
- {\r
- status = CYRET_SUCCESS;\r
- }\r
- else\r
+ if(CYRET_SUCCESS == status)\r
+ {\r
+ /* Erase and program flash with data from SPC interval latch */\r
+ status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);\r
+\r
+ if(CYRET_STARTED == status)\r
{\r
- status = CYRET_UNKNOWN;\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Wait for SPC to finish and get SPC status */\r
+ CyDelayUs(1u);\r
+ }\r
+\r
+ /* Hide SPC status */\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
}\r
}\r
}\r
-\r
+ CySpcUnlock();\r
+ } /* if(CySpcLock() == CYRET_SUCCESS) */\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
}\r
-\r
- CySpcUnlock();\r
- }\r
- else\r
- {\r
- status = CYRET_LOCKED;\r
}\r
\r
return(status);\r
*\r
* Summary:\r
* Sets the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash. This function must be called before increasing CPU\r
-* clock frequency. It can optionally be called after lowering CPU clock\r
-* frequency in order to improve CPU performance.\r
+* coming back from the Flash. This function must be called before increasing the CPU\r
+* clock frequency. It can optionally be called after lowering the CPU clock\r
+* frequency in order to improve the CPU performance.\r
*\r
* Parameters:\r
* uint8 freq:\r
\r
/***************************************************************************\r
* The number of clock cycles the cache will wait before it samples data\r
- * coming back from Flash must be equal or greater to to the CPU frequency\r
+ * coming back from the Flash must be equal or greater to to the CPU frequency\r
* outlined in clock cycles.\r
***************************************************************************/\r
\r
- #if (CY_PSOC3)\r
-\r
- if (freq <= 22u)\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_22MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
- else if (freq <= 44u)\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
- else\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_GREATER_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
-\r
- #endif /* (CY_PSOC3) */\r
-\r
-\r
- #if (CY_PSOC5)\r
-\r
- if (freq <= 16u)\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
- else if (freq <= 33u)\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
- else if (freq <= 50u)\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
- else\r
- {\r
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
- ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
- }\r
-\r
- #endif /* (CY_PSOC5) */\r
+ if (freq < CY_FLASH_CACHE_WS_1_FREQ_MAX)\r
+ {\r
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |\r
+ CY_FLASH_CACHE_WS_1_VALUE_MASK;\r
+ }\r
+ else if (freq < CY_FLASH_CACHE_WS_2_FREQ_MAX)\r
+ {\r
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |\r
+ CY_FLASH_CACHE_WS_2_VALUE_MASK;\r
+ }\r
+ else if (freq < CY_FLASH_CACHE_WS_3_FREQ_MAX)\r
+ {\r
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |\r
+ CY_FLASH_CACHE_WS_3_VALUE_MASK;\r
+ }\r
+#if (CY_PSOC5)\r
+ else if (freq < CY_FLASH_CACHE_WS_4_FREQ_MAX)\r
+ {\r
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |\r
+ CY_FLASH_CACHE_WS_4_VALUE_MASK;\r
+ }\r
+ else if (freq <= CY_FLASH_CACHE_WS_5_FREQ_MAX)\r
+ {\r
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |\r
+ CY_FLASH_CACHE_WS_5_VALUE_MASK;\r
+ }\r
+#endif /* (CY_PSOC5) */\r
+ else\r
+ {\r
+ /* Halt CPU in debug mode if frequency is invalid */\r
+ CYASSERT(0u != 0u);\r
+ }\r
\r
/* Restore global interrupt enable state */\r
CyExitCriticalSection(interruptState);\r
*******************************************************************************/\r
void CyEEPROM_Start(void) \r
{\r
- /* Active Power Mode */\r
- *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;\r
+ uint8 interruptState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+\r
+ /***************************************************************************\r
+ * Enable SPC clock. This also internally enables the 36MHz IMO, since this\r
+ * is required for the SPC to function.\r
+ ***************************************************************************/\r
+ CY_FLASH_PM_ACT_CFG0_REG |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;\r
+ CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;\r
\r
- /* Standby Power Mode */\r
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;\r
+\r
+ /***************************************************************************\r
+ * The wake count defines the number of Bus Clock cycles it takes for the\r
+ * flash or EEPROM to wake up from a low power mode independent of the chip\r
+ * power mode. Wake up time for these blocks is 5 us.\r
+ * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E\r
+ * (30d) defines the wake up time as 60 cycles of the Bus Clock.\r
+ * This register needs to be written with a value dependent on the Bus Clock\r
+ * frequency so that the duration of the cycles is equal to or greater than\r
+ * the 5 us delay required.\r
+ ***************************************************************************/\r
+ CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;\r
+\r
+\r
+ /***************************************************************************\r
+ * Enable EEPROM. Re-enabling an EEPROM macro takes 5us. During this time,\r
+ * the EE will not acknowledge a PHUB request.\r
+ ***************************************************************************/\r
+ CY_FLASH_PM_ACT_CFG12_REG |= CY_FLASH_PM_ACT_CFG12_EN_EE;\r
+ CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_EE;\r
+\r
+ while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))\r
+ {\r
+ /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */\r
+ }\r
+\r
+ CyExitCriticalSection(interruptState);\r
}\r
\r
\r
*******************************************************************************/\r
void CyEEPROM_Stop (void) \r
{\r
- /* Active Power Mode */\r
- *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));\r
+ uint8 interruptState;\r
\r
- /* Standby Power Mode */\r
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ CY_FLASH_PM_ACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_EE));\r
+ CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_EE));\r
+\r
+ CyExitCriticalSection(interruptState);\r
}\r
\r
\r
*******************************************************************************/\r
void CyEEPROM_ReadReserve(void) \r
{\r
- /* Make a request for PHUB to have access */\r
- *CY_FLASH_EE_SCR_PTR |= CY_FLASH_EE_SCR_AHB_EE_REQ;\r
+ /* Make request for PHUB to have access */\r
+ CY_FLASH_EE_SCR_REG |= CY_FLASH_EE_SCR_AHB_EE_REQ;\r
\r
- while (0u == (*CY_FLASH_EE_SCR_PTR & CY_FLASH_EE_SCR_AHB_EE_ACK))\r
+ while (0u == (CY_FLASH_EE_SCR_REG & CY_FLASH_EE_SCR_AHB_EE_ACK))\r
{\r
- /* Wait for acknowledgement from PHUB */\r
+ /* Wait for acknowledgment from PHUB */\r
}\r
}\r
\r
*******************************************************************************/\r
void CyEEPROM_ReadRelease(void) \r
{\r
- *CY_FLASH_EE_SCR_PTR |= 0x00u;\r
+ CY_FLASH_EE_SCR_REG &= (uint8)(~CY_FLASH_EE_SCR_AHB_EE_REQ);\r
}\r
\r
\r
/*******************************************************************************\r
* File Name: CyFlash.h\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides the function definitions for the FLASH/EEPROM.\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#define CY_FLASH_NUMBER_ROWS (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE)\r
#define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE)\r
\r
+#if(CYDEV_ECC_ENABLE == 0)\r
+ #define CY_FLASH_SIZEOF_FULL_ROW (CY_FLASH_SIZEOF_ROW + CY_FLASH_SIZEOF_ECC_ROW)\r
+#else\r
+ #define CY_FLASH_SIZEOF_FULL_ROW (CY_FLASH_SIZEOF_ROW)\r
+#endif /* (CYDEV_ECC_ENABLE == 0) */\r
#define CY_EEPROM_BASE (CYDEV_EE_BASE)\r
#define CY_EEPROM_SIZE (CYDEV_EE_SIZE)\r
#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EEPROM_SECTOR_SIZE)\r
#define CY_EEPROM_SIZEOF_ROW (CYDEV_EEPROM_ROW_SIZE)\r
-#define CY_EEPROM_NUMBER_ROWS (EEPROM_SIZE / CYDEV_EEPROM_ROW_SIZE)\r
+#define CY_EEPROM_NUMBER_ROWS (CYDEV_EE_SIZE / CYDEV_EEPROM_ROW_SIZE)\r
#define CY_EEPROM_NUMBER_ARRAYS (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY)\r
-\r
+#define CY_EEPROM_NUMBER_SECTORS (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)\r
+#define CY_EEPROM_SIZEOF_SECTOR (CYDEV_EEPROM_SECTOR_SIZE)\r
\r
#if !defined(CYDEV_FLS_BASE)\r
#define CYDEV_FLS_BASE CYDEV_FLASH_BASE\r
/***************************************\r
* Registers\r
***************************************/\r
+/* Active Power Mode Configuration Register 0 */\r
+#define CY_FLASH_PM_ACT_CFG0_REG (* (reg8 *) CYREG_PM_ACT_CFG0)\r
+#define CY_FLASH_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)\r
+\r
+/* Alternate Active Power Mode Configuration Register 0 */\r
+#define CY_FLASH_PM_ALTACT_CFG0_REG (* (reg8 *) CYREG_PM_STBY_CFG0)\r
+#define CY_FLASH_PM_ALTACT_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0)\r
+\r
/* Active Power Mode Configuration Register 12 */\r
-#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12)\r
-#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)\r
+#define CY_FLASH_PM_ACT_CFG12_REG (* (reg8 *) CYREG_PM_ACT_CFG12)\r
+#define CY_FLASH_PM_ACT_CFG12_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)\r
\r
/* Alternate Active Power Mode Configuration Register 12 */\r
-#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12)\r
-#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)\r
+#define CY_FLASH_PM_ALTACT_CFG12_REG (* (reg8 *) CYREG_PM_STBY_CFG12)\r
+#define CY_FLASH_PM_ALTACT_CFG12_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)\r
+\r
+/* Wake count (BUS_CLK cycles) it takes for the Flash and EEPROM to wake up */\r
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_REG (* (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)\r
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_PTR ( (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)\r
+\r
+/* Flash macro control register */\r
+#define CY_FLASH_SPC_FM_EE_CR_REG (* (reg8 *) CYREG_SPC_FM_EE_CR)\r
+#define CY_FLASH_SPC_FM_EE_CR_PTR ( (reg8 *) CYREG_SPC_FM_EE_CR)\r
\r
\r
/* Cache Control Register */\r
***************************************/\r
\r
/* Power Mode Masks */\r
-#define CY_FLASH_PM_EE_MASK (0x10u)\r
-#define CY_FLASH_PM_FLASH_MASK (0x01u)\r
\r
-/* Frequency Constants */\r
+/* Enable EEPROM */\r
+#define CY_FLASH_PM_ACT_CFG12_EN_EE (0x10u)\r
+#define CY_FLASH_PM_ALTACT_CFG12_EN_EE (0x10u)\r
+\r
+/* Enable Flash */\r
#if (CY_PSOC3)\r
+ #define CY_FLASH_PM_ACT_CFG12_EN_FM (0x01u)\r
+ #define CY_FLASH_PM_ALTACT_CFG12_EN_FM (0x01u)\r
+#else\r
+ #define CY_FLASH_PM_ACT_CFG12_EN_FM (0x0Fu)\r
+ #define CY_FLASH_PM_ALTACT_CFG12_EN_FM (0x0Fu)\r
+#endif /* (CY_PSOC3) */\r
+\r
\r
- #define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u)\r
- #define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u)\r
- #define CY_FLASH_GREATER_44MHz (0x03u)\r
\r
+/* Frequency Constants */\r
+#if (CY_PSOC3)\r
+ #define CY_FLASH_CACHE_WS_VALUE_MASK (0xC0u)\r
+ #define CY_FLASH_CACHE_WS_1_VALUE_MASK (0x40u)\r
+ #define CY_FLASH_CACHE_WS_2_VALUE_MASK (0x80u)\r
+ #define CY_FLASH_CACHE_WS_3_VALUE_MASK (0xC0u)\r
+\r
+ #define CY_FLASH_CACHE_WS_1_FREQ_MAX (22u)\r
+ #define CY_FLASH_CACHE_WS_2_FREQ_MAX (44u)\r
+ #define CY_FLASH_CACHE_WS_3_FREQ_MAX (67u)\r
#endif /* (CY_PSOC3) */\r
\r
#if (CY_PSOC5)\r
-\r
- #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u)\r
- #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u)\r
- #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u)\r
- #define CY_FLASH_GREATER_51MHz (0x00u)\r
-\r
+ #define CY_FLASH_CACHE_WS_VALUE_MASK (0xE0u)\r
+ #define CY_FLASH_CACHE_WS_1_VALUE_MASK (0x40u)\r
+ #define CY_FLASH_CACHE_WS_2_VALUE_MASK (0x80u)\r
+ #define CY_FLASH_CACHE_WS_3_VALUE_MASK (0xC0u)\r
+ #define CY_FLASH_CACHE_WS_4_VALUE_MASK (0x00u)\r
+ #define CY_FLASH_CACHE_WS_5_VALUE_MASK (0x20u)\r
+\r
+ #define CY_FLASH_CACHE_WS_1_FREQ_MAX (16u)\r
+ #define CY_FLASH_CACHE_WS_2_FREQ_MAX (33u)\r
+ #define CY_FLASH_CACHE_WS_3_FREQ_MAX (50u)\r
+ #define CY_FLASH_CACHE_WS_4_FREQ_MAX (67u)\r
+ #define CY_FLASH_CACHE_WS_5_FREQ_MAX (83u)\r
#endif /* (CY_PSOC5) */\r
\r
#define CY_FLASH_CYCLES_MASK_SHIFT (0x06u)\r
#define CY_FLASH_CYCLES_MASK ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT)))\r
-#define CY_FLASH_EE_STARTUP_DELAY (5u)\r
\r
#define CY_FLASH_EE_SCR_AHB_EE_REQ (0x01u)\r
#define CY_FLASH_EE_SCR_AHB_EE_ACK (0x02u)\r
\r
\r
+#define CY_FLASH_EE_EE_AWAKE (0x20u)\r
+\r
+/* 5(us) * BUS_CLK(80 MHz) / granularity(2) */\r
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ (0xC8u)\r
+\r
+/* Enable clk_spc. This also internally enables the 36MHz IMO. */\r
+#define CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC (0x08u)\r
+#define CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC (0x08u)\r
\r
/* Default values for getting temperature. */\r
\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0\r
+* Thne following code is OBSOLETE and must not be used starting with cy_boot\r
+* 4.20.\r
+*\r
+* If the obsoleted macro definitions intended for use in the application use the\r
+* following scheme, redefine your own versions of these definitions:\r
+* #ifdef <OBSOLETED_DEFINE>\r
+* #undef <OBSOLETED_DEFINE>\r
+* #define <OBSOLETED_DEFINE> (<New Value>)\r
+* #endif\r
+*\r
+* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* used in the application and their modification might lead to unexpected\r
+* consequences.\r
+*******************************************************************************/\r
+#if (CY_PSOC5)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u)\r
+ #define CY_FLASH_GREATER_51MHz (0x00u)\r
+#endif /* (CY_PSOC5) */\r
+\r
+#if (CY_PSOC3)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u)\r
+ #define CY_FLASH_GREATER_44MHz (0x03u)\r
+#endif /* (CY_PSOC3) */\r
+\r
+#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12)\r
+#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)\r
+#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12)\r
+#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)\r
+#define CY_FLASH_PM_EE_MASK (0x10u)\r
+#define CY_FLASH_PM_FLASH_MASK (0x01u)\r
+\r
+/*******************************************************************************\r
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.0\r
*******************************************************************************/\r
#define FLASH_SIZE (CY_FLASH_SIZE)\r
#define FLASH_SIZEOF_SECTOR (CY_FLASH_SIZEOF_ARRAY)\r
#define EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY)\r
#define EEPROM_NUMBER_ROWS (CY_EEPROM_NUMBER_ROWS)\r
#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS)\r
-#define CY_EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS)\r
-#define CY_EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY)\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30\r
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.30\r
*******************************************************************************/\r
#define FLASH_CYCLES_PTR (CY_FLASH_CONTROL_PTR)\r
\r
/*******************************************************************************\r
* File Name: CyLib.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
-* Provides system API for the clocking, interrupts and watchdog timer.\r
+* Provides a system API for the clocking, interrupts and watchdog timer.\r
*\r
* Note:\r
* Documentation of the API's in this file is located in the\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
static void CyIMO_SetTrimValue(uint8 freq) ;\r
static void CyBusClk_Internal_SetDivider(uint16 divider);\r
\r
+#if(CY_PSOC5)\r
+ static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS];\r
+ static void CySysTickServiceCallbacks(void);\r
+ uint32 CySysTickInitVar = 0u;\r
+#endif /* (CY_PSOC5) */\r
+\r
\r
/*******************************************************************************\r
* Function Name: CyPLL_OUT_Start\r
* clock can still be used.\r
*\r
* Side Effects:\r
-* If wait is enabled: This function wses the Fast Time Wheel to time the wait.\r
+* If wait is enabled: This function uses the Fast Time Wheel to time the wait.\r
* Any other use of the Fast Time Wheel will be stopped during the period of\r
* this function and then restored. This function also uses the 100 KHz ILO.\r
* If not enabled, this function will enable the 100 KHz ILO for the period of\r
uint8 pmTwCfg2State;\r
\r
\r
- /* Enables the PLL circuit */\r
+ /* Enables PLL circuit */\r
CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE;\r
\r
if(wait != 0u)\r
\r
while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))\r
{\r
- /* Wait for the interrupt status */\r
+ /* Wait for interrupt status */\r
if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))\r
{\r
if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))\r
* None\r
*\r
* Side Effects:\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution results in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
* None\r
*\r
* Side Effects:\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution results in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the3 Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
* None\r
*\r
* Side Effects:\r
-* If wait is enabled: This function wses the Fast Time Wheel to time the wait.\r
+* If wait is enabled: This function uses the Fast Time Wheel to time the wait.\r
* Any other use of the Fast Time Wheel will be stopped during the period of\r
* this function and then restored. This function also uses the 100 KHz ILO.\r
* If not enabled, this function will enable the 100 KHz ILO for the period of\r
\r
if(0u != wait)\r
{\r
- /* Need to turn on the 100KHz ILO if it happens to not already be running.*/\r
+ /* Need to turn on 100KHz ILO if it happens to not already be running.*/\r
ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;\r
pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG;\r
pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG;\r
\r
while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))\r
{\r
- /* Wait for the interrupt status */\r
+ /* Wait for interrupt status */\r
}\r
\r
if(0u == ilo100KhzEnable)\r
/* If USB is powered */\r
if(usbPowerOn == 1u)\r
{\r
- /* Lock the USB Oscillator */\r
+ /* Lock USB Oscillator */\r
CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN;\r
}\r
break;\r
* None\r
*\r
* Side Effects:\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution results in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
* When the USB setting is chosen, the USB clock locking circuit is enabled.\r
uint8 nextFreq;\r
\r
/***************************************************************************\r
- * When changing the IMO frequency the Trim values must also be set\r
+ * If the IMO frequency is changed,the Trim values must also be set\r
* accordingly.This requires reading the current frequency. If the new\r
- * frequency is faster, then set the new trim and then change the frequency,\r
- * otherwise change the frequency and then set the new trim values.\r
+ * frequency is faster, then set a new trim and then change the frequency,\r
+ * otherwise change the frequency and then set new trim values.\r
***************************************************************************/\r
\r
currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK));\r
\r
- /* Check if the requested frequency is USB. */\r
+ /* Check if requested frequency is USB. */\r
nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq;\r
\r
switch (currentFreq)\r
\r
if (nextFreq >= currentFreq)\r
{\r
- /* Set the new trim first */\r
+ /* Set new trim first */\r
CyIMO_SetTrimValue(freq);\r
}\r
\r
- /* Set the usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */\r
+ /* Set usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */\r
switch(freq)\r
{\r
case CY_IMO_FREQ_3MHZ:\r
break;\r
}\r
\r
- /* Turn on the IMO Doubler, if switching to CY_IMO_FREQ_USB */\r
+ /* Tu rn onIMO Doubler, if switching to CY_IMO_FREQ_USB */\r
if (freq == CY_IMO_FREQ_USB)\r
{\r
CyIMO_EnableDoubler();\r
\r
if (nextFreq < currentFreq)\r
{\r
- /* Set the new trim after setting the frequency */\r
+ /* Set the trim after setting frequency */\r
CyIMO_SetTrimValue(freq);\r
}\r
}\r
* Sets the source of the clock output from the IMO block.\r
*\r
* The output from the IMO is by default the IMO itself. Optionally the MHz\r
-* Crystal or a DSI input can be the source of the IMO output instead.\r
+* Crystal or DSI input can be the source of the IMO output instead.\r
*\r
* Parameters:\r
* source: CY_IMO_SOURCE_DSI to set the DSI as source.\r
* None\r
*\r
* Side Effects:\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
*******************************************************************************/\r
void CyIMO_EnableDoubler(void) \r
{\r
- /* Set the FASTCLK_IMO_CR_PTR regigster's 4th bit */\r
+ /* Set FASTCLK_IMO_CR_PTR regigster's 4th bit */\r
CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER;\r
}\r
\r
* The current source and the new source must both be running and stable before\r
* calling this function.\r
*\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
*\r
* Parameters:\r
* uint8 divider:\r
-* Valid range [0-255]. The clock will be divided by this value + 1.\r
-* For example to divide by 2 this parameter should be set to 1.\r
+* The valid range is [0-255]. The clock will be divided by this value + 1.\r
+* For example to divide this parameter by two should be set to 1.\r
*\r
* Return:\r
* None\r
*\r
* Side Effects:\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
* When changing the Master or Bus clock divider value from div-by-n to div-by-1\r
********************************************************************************\r
*\r
* Summary:\r
-* Function used by CyBusClk_SetDivider(). For internal use only.\r
+* The function used by CyBusClk_SetDivider(). For internal use only.\r
*\r
* Parameters:\r
* divider: Valid range [0-65535].\r
* The clock will be divided by this value + 1.\r
-* For example to divide by 2 this parameter should be set to 1.\r
+* For example, to divide this parameter by two should be set to 1.\r
*\r
* Return:\r
* None\r
/* Enable mask bits to enable shadow loads */\r
CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK;\r
\r
- /* Update Shadow Divider Value Register with the new divider */\r
+ /* Update Shadow Divider Value Register with new divider */\r
CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider);\r
CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider);\r
\r
********************************************************************************\r
*\r
* Summary:\r
-* Sets the divider value used to generate Bus Clock.\r
+* Sets the divider value used to generate the Bus Clock.\r
*\r
* Parameters:\r
* divider: Valid range [0-65535]. The clock will be divided by this value + 1.\r
-* For example to divide by 2 this parameter should be set to 1.\r
+* For example, to divide this parameter by two should be set to 1.\r
*\r
* Return:\r
* None\r
*\r
* Side Effects:\r
-* If as result of this function execution the CPU clock frequency is increased\r
+* If this function execution resulted in the CPU clock frequency increasing,\r
* then the number of clock cycles the cache will wait before it samples data\r
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
-* with appropriate parameter. It can be optionally called if CPU clock\r
-* frequency is lowered in order to improve CPU performance.\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
\r
interruptState = CyEnterCriticalSection();\r
\r
- /* Work around to set the bus clock divider value */\r
+ /* Work around to set bus clock divider value */\r
busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u);\r
busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG;\r
\r
if ((divider == 0u) || (busClkDiv == 0u))\r
{\r
- /* Save away the master clock divider value */\r
+ /* Save away master clock divider value */\r
masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG;\r
\r
if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV)\r
\r
if (divider == 0u)\r
{\r
- /* Set the SSS bit and the divider register desired value */\r
+ /* Set SSS bit and divider register desired value */\r
CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS;\r
CyBusClk_Internal_SetDivider(divider);\r
}\r
CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS));\r
}\r
\r
- /* Restore the master clock */\r
+ /* Restore master clock */\r
CyMasterClk_SetDivider(masterClkDiv);\r
}\r
else\r
*\r
* Parameters:\r
* divider: Valid range [0-15]. The clock will be divided by this value + 1.\r
- * For example to divide by 2 this parameter should be set to 1.\r
+ * For example, to divide this parameter by two should be set to 1.\r
*\r
* Return:\r
* None\r
*\r
* Side Effects:\r
- * If as result of this function execution the CPU clock frequency is increased\r
- * then the number of clock cycles the cache will wait before it samples data\r
- * coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
- * with appropriate parameter. It can be optionally called if CPU clock\r
- * frequency is lowered in order to improve CPU performance.\r
+ * If this function execution resulted in the CPU clock frequency increasing,\r
+* then the number of clock cycles the cache will wait before it samples data\r
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with an appropriate parameter. It can be optionally called if the CPU clock\r
+* frequency is lowered in order to improve the CPU performance.\r
* See CyFlash_SetWaitCycles() description for more information.\r
*\r
*******************************************************************************/\r
*******************************************************************************/\r
void CyILO_Start1K(void) \r
{\r
- /* Set the bit 1 of ILO RS */\r
+ /* Set bit 1 of ILO RS */\r
CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ;\r
}\r
\r
* Summary:\r
* Disables the ILO 1 KHz oscillator.\r
*\r
-* Note The ILO 1 KHz oscillator must be enabled if Sleep or Hibernate low power\r
+* Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low power\r
* mode APIs are expected to be used. For more information, refer to the Power\r
* Management section of this document.\r
*\r
*******************************************************************************/\r
void CyILO_Stop1K(void) \r
{\r
- /* Clear the bit 1 of ILO RS */\r
+ /* Clear bit 1 of ILO RS */\r
CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ));\r
}\r
\r
*******************************************************************************/\r
void CyILO_Enable33K(void) \r
{\r
- /* Set the bit 5 of ILO RS */\r
+ /* Set bit 5 of ILO RS */\r
CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ;\r
}\r
\r
/* Get current state. */\r
state = CY_LIB_SLOWCLK_ILO_CR0_REG;\r
\r
- /* Set the the oscillator power mode. */\r
+ /* Set the oscillator power mode. */\r
if(mode != CY_ILO_FAST_START)\r
{\r
CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE);\r
CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE)));\r
}\r
\r
- /* Return the old mode. */\r
+ /* Return old mode. */\r
return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION);\r
}\r
\r
CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN;\r
#endif /* (CY_PSOC3) */\r
\r
- /* Enable operation of the 32K Crystal Oscillator */\r
+ /* Enable operation of 32K Crystal Oscillator */\r
CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN;\r
\r
for (i = 1000u; i > 0u; i--)\r
{\r
if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT))\r
{\r
- /* Ready - switch to the hign power mode */\r
+ /* Ready - switch to high power mode */\r
(void) CyXTAL_32KHZ_SetPowerMode(0u);\r
\r
break;\r
********************************************************************************\r
*\r
* Summary:\r
-* Sets the power mode for the 32 KHz oscillator used during sleep mode.\r
+* Sets the power mode for the 32 KHz oscillator used during the sleep mode.\r
* Allows for lower power during sleep when there are fewer sources of noise.\r
-* During active mode the oscillator is always run in high power mode.\r
+* During the active mode the oscillator is always run in the high power mode.\r
*\r
* Parameters:\r
* uint8 mode\r
uint8 pmTwCfg2Tmp;\r
\r
\r
- /* Enables the MHz crystal oscillator circuit */\r
+ /* Enables MHz crystal oscillator circuit */\r
CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE;\r
\r
\r
/* Read XERR bit to clear it */\r
(void) CY_CLK_XMHZ_CSR_REG;\r
\r
- /* Wait for a millisecond - 4 x 250 us */\r
+ /* Wait for 1 millisecond - 4 x 250 us */\r
for(count = 4u; count > 0u; count--)\r
{\r
while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))\r
{\r
- /* Wait for the FTW interrupt event */\r
+ /* Wait for FTW interrupt event */\r
}\r
}\r
\r
\r
/*******************************************************************\r
- * High output indicates oscillator failure.\r
- * Only can be used after start-up interval (1 ms) is completed.\r
+ * High output indicates an oscillator failure.\r
+ * Only can be used after a start-up interval (1 ms) is completed.\r
*******************************************************************/\r
if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR))\r
{\r
*******************************************************************************/\r
void CyXTAL_Stop(void) \r
{\r
- /* Disable the the oscillator. */\r
+ /* Disable oscillator. */\r
FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE));\r
}\r
\r
*\r
* Summary:\r
* Reads the XERR status bit for the megahertz crystal. This status bit is a\r
-* sticky clear on read value. This function is not available for PSoC5.\r
+* sticky, clear on read. This function is not available for PSoC5.\r
*\r
* Parameters:\r
* None\r
uint8 CyXTAL_ReadStatus(void) \r
{\r
/***************************************************************************\r
- * High output indicates oscillator failure. Only use this after start-up\r
- * interval is completed. This can be used for status and failure recovery.\r
+ * High output indicates an oscillator failure. Only use this after a start-up\r
+ * interval is completed. This can be used for the status and failure recovery.\r
***************************************************************************/\r
return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u);\r
}\r
* Enables the fault recovery circuit which will switch to the IMO in the case\r
* of a fault in the megahertz crystal circuit. The crystal must be up and\r
* running with the XERR bit at 0, before calling this function to prevent\r
-* immediate fault switchover. This function is not available for PSoC5.\r
+* an immediate fault switchover. This function is not available for PSoC5.\r
*\r
* Parameters:\r
* None\r
********************************************************************************\r
*\r
* Summary:\r
-* Sets the startup settings for the crystal. Logic model outputs a frequency\r
+* Sets the startup settings for the crystal. The logic model outputs a frequency\r
* (setting + 4) MHz when enabled.\r
*\r
* This is artificial as the actual frequency is determined by an attached\r
*\r
* Parameters:\r
* setting: Valid range [0-31].\r
-* Value is dependent on the frequency and quality of the crystal being used.\r
+* The value is dependent on the frequency and quality of the crystal being used.\r
* Refer to the device TRM and datasheet for more information.\r
*\r
* Return:\r
********************************************************************************\r
*\r
* Summary:\r
-* Forces a software reset of the device.\r
+* Forces a device software reset.\r
*\r
* Parameters:\r
* None\r
*\r
* Note:\r
* CyDelay has been implemented with the instruction cache assumed enabled. When\r
-* instruction cache is disabled on PSoC5, CyDelay will be two times larger. For\r
-* example, with instruction cache disabled CyDelay(100) would result in about\r
-* 200 ms delay instead of 100 ms.\r
+* the instruction cache is disabled on PSoC5, CyDelay will be two times larger.\r
+* For example, with instruction cache disabled CyDelay(100) would result in\r
+* about 200 ms delay instead of 100 ms.\r
*\r
* Parameters:\r
* milliseconds: number of milliseconds to delay.\r
*\r
* Side Effects:\r
* CyDelayUS has been implemented with the instruction cache assumed enabled.\r
- * When instruction cache is disabled on PSoC 5, CyDelayUs will be two times\r
- * larger. For example, with instruction cache disabled CyDelayUs(100) would\r
+ * When the instruction cache is disabled on PSoC 5, CyDelayUs will be two times\r
+ * larger. For example, with the instruction cache disabled CyDelayUs(100) would\r
* result in about 200 us delay instead of 100 us.\r
*\r
* If the bus clock frequency is a small non-integer number, the actual delay\r
********************************************************************************\r
*\r
* Summary:\r
-* Sets clock frequency for CyDelay.\r
+* Sets the clock frequency for CyDelay.\r
*\r
* Parameters:\r
-* freq: Frequency of bus clock in Hertz.\r
+* freq: The frequency of the bus clock in Hertz.\r
*\r
* Return:\r
* None\r
* Enables the watchdog timer.\r
*\r
* The timer is configured for the specified count interval, the central\r
-* timewheel is cleared, the setting for low power mode is configured and the\r
+* timewheel is cleared, the setting for the low power mode is configured and the\r
* watchdog timer is enabled.\r
*\r
* Once enabled the watchdog cannot be disabled. The watchdog counts each time\r
CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET;\r
CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET));\r
\r
- /* Setting the low power mode */\r
+ /* Setting low power mode */\r
CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) |\r
(CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK)));\r
\r
- /* Enables the watchdog reset */\r
+ /* Enables watchdog reset */\r
CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN;\r
}\r
\r
*\r
* Summary:\r
* Enables the digital low voltage monitors to generate interrupt on Vddd\r
-* archives specified threshold and optionally resets device.\r
+* archives specified threshold and optionally resets the device.\r
*\r
* Parameters:\r
-* reset: Option to reset device at a specified Vddd threshold:\r
+* reset: The option to reset the device at a specified Vddd threshold:\r
* 0 - Device is not reset.\r
* 1 - Device is reset.\r
*\r
* threshold: Sets the trip level for the voltage monitor.\r
-* Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV\r
-* interval.\r
+* Values from 1.70 V to 5.45 V are accepted with an interval of approximately\r
+* 250 mV.\r
*\r
* Return:\r
* None\r
(CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK)));\r
CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN;\r
\r
- /* Timeout to eliminate glitches on the LVI/HVI when enabling */\r
+ /* Timeout to eliminate glitches on LVI/HVI when enabling */\r
CyDelayUs(1u);\r
\r
(void)CY_VD_PERSISTENT_STATUS_REG;\r
*\r
* Summary:\r
* Enables the analog low voltage monitors to generate interrupt on Vdda\r
-* archives specified threshold and optionally resets device.\r
+* archives specified threshold and optionally resets the device.\r
*\r
* Parameters:\r
-* reset: Option to reset device at a specified Vdda threshold:\r
+* reset: The option to reset the device at a specified Vdda threshold:\r
* 0 - Device is not reset.\r
* 1 - Device is reset.\r
*\r
CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu);\r
CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN;\r
\r
- /* Timeout to eliminate glitches on the LVI/HVI when enabling */\r
+ /* Timeout to eliminate glitches on LVI/HVI when enabling */\r
CyDelayUs(1u);\r
\r
(void)CY_VD_PERSISTENT_STATUS_REG;\r
CY_NOP;\r
CY_NOP;\r
\r
- /* All entries in the cache are invalidated on the next clock cycle. */\r
+ /* All entries in cache are invalidated on next clock cycle. */\r
CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH;\r
\r
+ /* Once this is executed it's guaranteed the cache has been flushed */\r
+ (void) CY_CACHE_CONTROL_REG;\r
\r
- /***********************************************************************\r
- * The prefetch unit could/would be filled with the instructions that\r
- * succeed the flush. Since a flush is desired then theoretically those\r
- * instructions might be considered stale/invalid.\r
- ***********************************************************************/\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
- CY_NOP;\r
+ /* Flush the pipeline */\r
+ CY_SYS_ISB;\r
\r
/* Restore global interrupt enable state */\r
CyExitCriticalSection(interruptState);\r
* SysTick, PendSV and others.\r
*\r
* Parameters:\r
- * number: Interrupt number, valid range [0-15].\r
- address: Pointer to an interrupt service routine.\r
+ * number: System interrupt number:\r
+ * CY_INT_NMI_IRQN - Non Maskable Interrupt\r
+ * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt\r
+ * CY_INT_MEM_MANAGE_IRQN - Memory Management Interrupt\r
+ * CY_INT_BUS_FAULT_IRQN - Bus Fault Interrupt\r
+ * CY_INT_USAGE_FAULT_IRQN - Usage Fault Interrupt\r
+ * CY_INT_SVCALL_IRQN - SV Call Interrupt\r
+ * CY_INT_DEBUG_MONITOR_IRQN - Debug Monitor Interrupt\r
+ * CY_INT_PEND_SV_IRQN - Pend SV Interrupt\r
+ * CY_INT_SYSTICK_IRQN - System Tick Interrupt\r
+ *\r
+ * address: Pointer to an interrupt service routine.\r
*\r
* Return:\r
* The old ISR vector at this location.\r
* SysTick, PendSV and others.\r
*\r
* Parameters:\r
- * number: The interrupt number, valid range [0-15].\r
+ * number: System interrupt number:\r
+ * CY_INT_NMI_IRQN - Non Maskable Interrupt\r
+ * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt\r
+ * CY_INT_MEMORY_MANAGEMENT_IRQN - Memory Management Interrupt\r
+ * CY_INT_BUS_FAULT_IRQN - Bus Fault Interrupt\r
+ * CY_INT_USAGE_FAULT_IRQN - Usage Fault Interrupt\r
+ * CY_INT_SVCALL_IRQN - SV Call Interrupt\r
+ * CY_INT_DEBUG_MONITOR_IRQN - Debug Monitor Interrupt\r
+ * CY_INT_PEND_SV_IRQN - Pend SV Interrupt\r
+ * CY_INT_SYSTICK_IRQN - System Tick Interrupt\r
*\r
* Return:\r
* Address of the ISR in the interrupt vector table.\r
* number: Valid range [0-31]. Interrupt number\r
*\r
* Return:\r
- * Address of the ISR in the interrupt vector table.\r
+ * The address of the ISR in the interrupt vector table.\r
*\r
*******************************************************************************/\r
cyisraddress CyIntGetVector(uint8 number)\r
\r
CYASSERT(number <= CY_INT_NUMBER_MAX);\r
\r
- /* Get a pointer to the Interrupt enable register. */\r
+ /* Get pointer to Interrupt enable register. */\r
stateReg = CY_INT_ENABLE_PTR;\r
\r
- /* Get the state of the interrupt. */\r
+ /* Get state of interrupt. */\r
return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u));\r
}\r
\r
\r
CYASSERT(number <= CY_INT_NUMBER_MAX);\r
\r
- /* Get a pointer to the Interrupt enable register. */\r
+ /* Get pointer to Interrupt enable register. */\r
stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u);\r
\r
- /* Get the state of the interrupt. */\r
+ /* Get state of interrupt. */\r
return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u)));\r
}\r
\r
* If 1 is passed as a parameter:\r
* - if any of the SC blocks are used - enable pumps for the SC blocks and\r
* start boost clock.\r
- * - For the each enabled SC block set boost clock index and enable boost\r
+ * - For each enabled SC block set a boost clock index and enable the boost\r
* clock.\r
*\r
* If non-1 value is passed as a parameter:\r
* - If all SC blocks are not used - disable pumps for the SC blocks and\r
- * stop boost clock.\r
- * - For the each enabled SC block clear boost clock index and disable boost\r
+ * stop the boost clock.\r
+ * - For each enabled SC block clear the boost clock index and disable the boost\r
* clock.\r
*\r
- * The global variable CyScPumpEnabled is updated to be equal to passed\r
+ * The global variable CyScPumpEnabled is updated to be equal to passed the\r
* parameter.\r
*\r
* Parameters:\r
- * uint8 enable: Enable/disable SC pumps and boost clock for enabled SC block.\r
+ * uint8 enable: Enable/disable SC pumps and the boost clock for the enabled SC block.\r
* 1 - Enable\r
* 0 - Disable\r
*\r
#endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
\r
\r
+#if(CY_PSOC5)\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickStart\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Configures the SysTick timer to generate interrupt every 1 ms by call to the\r
+ * CySysTickInit() function and starts it by calling CySysTickEnable() function.\r
+ * Refer to the corresponding function description for the details.\r
+\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickStart(void)\r
+ {\r
+ if (0u == CySysTickInitVar)\r
+ {\r
+ CySysTickInit();\r
+ CySysTickInitVar = 1u;\r
+ }\r
+\r
+ CySysTickEnable();\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickInit\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Initializes the callback addresses with pointers to NULL, associates the\r
+ * SysTick system vector with the function that is responsible for calling\r
+ * registered callback functions, configures SysTick timer to generate interrupt\r
+ * every 1 ms.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set.\r
+ *\r
+ * The 1 ms interrupt interval is configured based on the frequency determined\r
+ * by PSoC Creator at build time. If System clock frequency is changed in\r
+ * runtime, the CyDelayFreq() with the appropriate parameter should be called.\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickInit(void)\r
+ {\r
+ uint32 i;\r
+\r
+ for (i = 0u; i<CY_SYS_SYST_NUM_OF_CALLBACKS; i++)\r
+ {\r
+ CySysTickCallbacks[i] = (void *) 0;\r
+ }\r
+\r
+ (void) CyIntSetSysVector(CY_INT_SYSTICK_IRQN, &CySysTickServiceCallbacks);\r
+ CySysTickSetClockSource(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK);\r
+ CySysTickSetReload(cydelay_freq_hz/1000u);\r
+ CySysTickClear();\r
+ CyIntEnable(CY_INT_SYSTICK_IRQN);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickEnable\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Enables the SysTick timer and its interrupt.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickEnable(void)\r
+ {\r
+ CySysTickEnableInterrupt();\r
+ CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE;\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickStop\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Stops the system timer (SysTick).\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickStop(void)\r
+ {\r
+ CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE));\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickEnableInterrupt\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Enables the SysTick interrupt.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickEnableInterrupt(void)\r
+ {\r
+ CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE_INT;\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickDisableInterrupt\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Disables the SysTick interrupt.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickDisableInterrupt(void)\r
+ {\r
+ CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE_INT));\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickSetReload\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Sets value the counter is set to on startup and after it reaches zero. This\r
+ * function do not change or reset current sysTick counter value, so it should\r
+ * be cleared using CySysTickClear() API.\r
+ *\r
+ * Parameters:\r
+ * value: Valid range [0x0-0x00FFFFFF]. Counter reset value.\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickSetReload(uint32 value)\r
+ {\r
+ CY_SYS_SYST_RVR_REG = (value & CY_SYS_SYST_RVR_CNT_MASK);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickGetReload\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Sets value the counter is set to on startup and after it reaches zero.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * Counter reset value\r
+ *\r
+ *******************************************************************************/\r
+ uint32 CySysTickGetReload(void)\r
+ {\r
+ return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_RVR_CNT_MASK);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickGetValue\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Gets current SysTick counter value.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * Current SysTick counter value\r
+ *\r
+ *******************************************************************************/\r
+ uint32 CySysTickGetValue(void)\r
+ {\r
+ return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_CVR_REG);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickSetClockSource\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Sets the clock source for the SysTick counter.\r
+ *\r
+ * Parameters:\r
+ * clockSource: Clock source for SysTick counter\r
+ * Define Clock Source\r
+ * CY_SYS_SYST_CSR_CLK_SRC_SYSCLK SysTick is clocked by CPU clock.\r
+ * CY_SYS_SYST_CSR_CLK_SRC_LFCLK SysTick is clocked by the low frequency\r
+ * clock (ILO 100 KHz for PSoC 5LP, LFCLK for PSoC 4).\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * Clears SysTick count flag if it was set. If clock source is not ready this\r
+ * function call will have no effect. After changing clock source to the low frequency\r
+ * clock the counter and reload register values will remain unchanged so time to\r
+ * the interrupt will be significantly bigger and vice versa.\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickSetClockSource(uint32 clockSource)\r
+ {\r
+ if (clockSource == CY_SYS_SYST_CSR_CLK_SRC_SYSCLK)\r
+ {\r
+ CY_SYS_SYST_CSR_REG |= (uint32)(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT);\r
+ }\r
+ else\r
+ {\r
+ CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT));\r
+ }\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickGetCountFlag\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * The count flag is set once SysTick counter reaches zero.\r
+ * The flag cleared on read.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * Returns non-zero value if counter is set, otherwise zero is returned.\r
+ *\r
+ *******************************************************************************/\r
+ uint32 CySysTickGetCountFlag(void)\r
+ {\r
+ return ((CY_SYS_SYST_CSR_REG>>CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickClear\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Clears the SysTick counter for well-defined startup.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CySysTickClear(void)\r
+ {\r
+ CY_SYS_SYST_CVR_REG = 0u;\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickSetCallback\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * The function set the pointers to the functions that will be called on\r
+ * SysTick interrupt.\r
+ *\r
+ * Parameters:\r
+ * number: The number of callback function address to be set.\r
+ * The valid range is from 0 to 4.\r
+ * CallbackFunction: Function address.\r
+ *\r
+ * Return:\r
+ * Returns the address of the previous callback function.\r
+ * The NULL is returned if the specified address in not set.\r
+ *\r
+ *******************************************************************************/\r
+ cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function)\r
+ {\r
+ cySysTickCallback retVal;\r
+\r
+ retVal = CySysTickCallbacks[number];\r
+ CySysTickCallbacks[number] = function;\r
+ return (retVal);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickGetCallback\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * The function get the specified callback pointer.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ cySysTickCallback CySysTickGetCallback(uint32 number)\r
+ {\r
+ return ((cySysTickCallback) CySysTickCallbacks[number]);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySysTickServiceCallbacks\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * System Tick timer interrupt routine\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ static void CySysTickServiceCallbacks(void)\r
+ {\r
+ uint32 i;\r
+\r
+ /* Verify that tick timer flag was set */\r
+ if (1u == CySysTickGetCountFlag())\r
+ {\r
+ for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++)\r
+ {\r
+ if (CySysTickCallbacks[i] != (void *) 0)\r
+ {\r
+ (void)(CySysTickCallbacks[i])();\r
+ }\r
+ }\r
+ }\r
+ }\r
+#endif /* (CY_PSOC5) */\r
+\r
+\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: CyLib.h\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides the function definitions for the system, clocking, interrupts and\r
* Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
void CySetScPumps(uint8 enable) ;\r
\r
+#if(CY_PSOC5)\r
+ /* Default interrupt handler */\r
+ CY_ISR_PROTO(IntDefaultHandler);\r
+#endif /* (CY_PSOC5) */\r
+\r
+#if(CY_PSOC5)\r
+ /* System tick timer APIs */\r
+ typedef void (*cySysTickCallback)(void);\r
+\r
+ void CySysTickStart(void);\r
+ void CySysTickInit(void);\r
+ void CySysTickEnable(void);\r
+ void CySysTickStop(void);\r
+ void CySysTickEnableInterrupt(void);\r
+ void CySysTickDisableInterrupt(void);\r
+ void CySysTickSetReload(uint32 value);\r
+ uint32 CySysTickGetReload(void);\r
+ uint32 CySysTickGetValue(void);\r
+ cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function);\r
+ cySysTickCallback CySysTickGetCallback(uint32 number);\r
+ void CySysTickSetClockSource(uint32 clockSource);\r
+ uint32 CySysTickGetCountFlag(void);\r
+ void CySysTickClear(void);\r
+#endif /* (CY_PSOC5) */\r
\r
/***************************************\r
* API Constants\r
#define CY_ALT_ACT_USB_ENABLED (0x01u)\r
\r
\r
+#if(CY_PSOC5)\r
+\r
+ /***************************************************************************\r
+ * Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ * so that all instructions following the ISB are fetched from cache or\r
+ * memory, after the instruction has been completed.\r
+ ***************************************************************************/\r
+\r
+ #if defined(__ARMCC_VERSION)\r
+ #define CY_SYS_ISB __isb(0x0f)\r
+ #else /* ASM for GCC & IAR */\r
+ #define CY_SYS_ISB asm volatile ("isb \n")\r
+ #endif /* (__ARMCC_VERSION) */\r
+\r
+#endif /* (CY_PSOC5) */\r
+\r
+\r
/***************************************\r
* Registers\r
***************************************/\r
#define CY_CACHE_CONTROL_REG (* (reg16 *) CYREG_CACHE_CC_CTL )\r
#define CY_CACHE_CONTROL_PTR ( (reg16 *) CYREG_CACHE_CC_CTL )\r
\r
+ /* System tick registers */\r
+ #define CY_SYS_SYST_CSR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CTL)\r
+ #define CY_SYS_SYST_CSR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CTL)\r
+\r
+ #define CY_SYS_SYST_RVR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_RELOAD)\r
+ #define CY_SYS_SYST_RVR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_RELOAD)\r
+\r
+ #define CY_SYS_SYST_CVR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CURRENT)\r
+ #define CY_SYS_SYST_CVR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CURRENT)\r
+\r
+ #define CY_SYS_SYST_CALIB_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CAL)\r
+ #define CY_SYS_SYST_CALIB_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CAL)\r
+\r
#elif (CY_PSOC3)\r
\r
/* Interrupt Address Vector registers */\r
#define CY_INT_VECT_TABLE ((cyisraddress CYXDATA *) CYREG_INTC_VECT_MBASE)\r
\r
- /* Interrrupt Controller Priority Registers */\r
+ /* Interrupt Controller Priority Registers */\r
#define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_INTC_PRIOR0)\r
#define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_INTC_PRIOR0)\r
\r
- /* Interrrupt Controller Set Enable Registers */\r
+ /* Interrupt Controller Set Enable Registers */\r
#define CY_INT_ENABLE_REG (* (reg8 *) CYREG_INTC_SET_EN0)\r
#define CY_INT_ENABLE_PTR ( (reg8 *) CYREG_INTC_SET_EN0)\r
\r
#define CY_INT_SET_EN3_REG (* (reg8 *) CYREG_INTC_SET_EN3)\r
#define CY_INT_SET_EN3_PTR ( (reg8 *) CYREG_INTC_SET_EN3)\r
\r
- /* Interrrupt Controller Clear Enable Registers */\r
+ /* Interrupt Controller Clear Enable Registers */\r
#define CY_INT_CLEAR_REG (* (reg8 *) CYREG_INTC_CLR_EN0)\r
#define CY_INT_CLEAR_PTR ( (reg8 *) CYREG_INTC_CLR_EN0)\r
\r
#define CY_INT_CLR_EN3_PTR ( (reg8 *) CYREG_INTC_CLR_EN3)\r
\r
\r
- /* Interrrupt Controller Set Pend Registers */\r
+ /* Interrupt Controller Set Pend Registers */\r
#define CY_INT_SET_PEND_REG (* (reg8 *) CYREG_INTC_SET_PD0)\r
#define CY_INT_SET_PEND_PTR ( (reg8 *) CYREG_INTC_SET_PD0)\r
\r
- /* Interrrupt Controller Clear Pend Registers */\r
+ /* Interrupt Controller Clear Pend Registers */\r
#define CY_INT_CLR_PEND_REG (* (reg8 *) CYREG_INTC_CLR_PD0)\r
#define CY_INT_CLR_PEND_PTR ( (reg8 *) CYREG_INTC_CLR_PD0)\r
\r
* Macro Name: CyAssert\r
********************************************************************************\r
* Summary:\r
-* Macro that evaluates the expression and if it is false (evaluates to 0) then\r
-* the processor is halted.\r
+* The macro that evaluates the expression and if it is false (evaluates to 0)\r
+* then the processor is halted.\r
*\r
* This macro is evaluated unless NDEBUG is defined.\r
*\r
#define CY_RESET_GPIO1 (0x80u)\r
\r
\r
-/* Interrrupt Controller Configuration and Status Register */\r
+/* Interrupt Controller Configuration and Status Register */\r
#if(CY_PSOC3)\r
#define INTERRUPT_CSR ((reg8 *) CYREG_INTC_CSR_EN)\r
#define DISABLE_IRQ_SET ((uint8)(0x01u << 1u)) /* INTC_CSR_EN */\r
#define CY_CACHE_CONTROL_FLUSH (0x0004u)\r
#define CY_LIB_RESET_CR2_RESET (0x01u)\r
\r
+#if(CY_PSOC5)\r
+ /* System tick API constants */\r
+ #define CY_SYS_SYST_CSR_ENABLE ((uint32) (0x01u))\r
+ #define CY_SYS_SYST_CSR_ENABLE_INT ((uint32) (0x02u))\r
+ #define CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT ((uint32) (0x02u))\r
+ #define CY_SYS_SYST_CSR_COUNTFLAG_SHIFT ((uint32) (16u))\r
+ #define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ((uint32) (1u))\r
+ #define CY_SYS_SYST_CSR_CLK_SRC_LFCLK ((uint32) (0u))\r
+ #define CY_SYS_SYST_RVR_CNT_MASK ((uint32) (0x00FFFFFFu))\r
+ #define CY_SYS_SYST_NUM_OF_CALLBACKS ((uint32) (5u))\r
+#endif /* (CY_PSOC5) */\r
+\r
+\r
\r
/*******************************************************************************\r
* Interrupt API constants\r
/* Mask to get valid range of system interrupt 0-15 */\r
#define CY_INT_SYS_NUMBER_MASK (0xFu)\r
\r
+#if(CY_PSOC5)\r
+\r
+ /* CyIntSetSysVector()/CyIntGetSysVector() - parameter definitions */\r
+ #define CY_INT_NMI_IRQN ( 2u) /* Non Maskable Interrupt */\r
+ #define CY_INT_HARD_FAULT_IRQN ( 3u) /* Hard Fault Interrupt */\r
+ #define CY_INT_MEM_MANAGE_IRQN ( 4u) /* Memory Management Interrupt */\r
+ #define CY_INT_BUS_FAULT_IRQN ( 5u) /* Bus Fault Interrupt */\r
+ #define CY_INT_USAGE_FAULT_IRQN ( 6u) /* Usage Fault Interrupt */\r
+ #define CY_INT_SVCALL_IRQN (11u) /* SV Call Interrupt */\r
+ #define CY_INT_DEBUG_MONITOR_IRQN (12u) /* Debug Monitor Interrupt */\r
+ #define CY_INT_PEND_SV_IRQN (14u) /* Pend SV Interrupt */\r
+ #define CY_INT_SYSTICK_IRQN (15u) /* System Tick Interrupt */\r
+\r
+#endif /* (CY_PSOC5) */\r
\r
/*******************************************************************************\r
* Interrupt Macros\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used.\r
+* The following code is OBSOLETE and must not be used.\r
+*\r
+* If the obsoleted macro definitions intended for use in the application use the\r
+* following scheme, redefine your own versions of these definitions:\r
+* #ifdef <OBSOLETED_DEFINE>\r
+* #undef <OBSOLETED_DEFINE>\r
+* #define <OBSOLETED_DEFINE> (<New Value>)\r
+* #endif\r
+*\r
+* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* used in the application and their modification might lead to unexpected\r
+* consequences.\r
*******************************************************************************/\r
+\r
#define CYGlobalIntEnable CyGlobalIntEnable\r
#define CYGlobalIntDisable CyGlobalIntDisable\r
\r
#define cymemset(s,c,n) memset((s),(c),(n))\r
#define cymemcpy(d,s,n) memcpy((d),(s),(n))\r
\r
-\r
-/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0\r
-*******************************************************************************/\r
#define MFGCFG_X32_TR_PTR (CY_CLK_XTAL32_TR_PTR)\r
#define MFGCFG_X32_TR (CY_CLK_XTAL32_TR_REG)\r
#define SLOWCLK_X32_TST_PTR (CY_CLK_XTAL32_TST_PTR)\r
#define CY_VD_PRESISTENT_STATUS_PTR (CY_VD_PERSISTENT_STATUS_PTR)\r
\r
\r
-/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.20\r
-*******************************************************************************/\r
-\r
#if(CY_PSOC5)\r
\r
#define CYINT_IRQ_BASE (CY_INT_IRQ_BASE)\r
#endif /* (CY_PSOC5) */\r
\r
\r
-/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30\r
-*******************************************************************************/\r
+\r
#define BUS_AMASK_CLEAR (0xF0u)\r
#define BUS_DMASK_CLEAR (0x00u)\r
#define CLKDIST_LD_LOAD_SET (0x01u)\r
#define CLKDIST_CR (*(reg8 *) CYREG_CLKDIST_CR)\r
\r
\r
-/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.50\r
-*******************************************************************************/\r
#define IMO_PM_ENABLE (0x10u)\r
#define PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)\r
#define PM_ACT_CFG0 (*(reg8 *) CYREG_PM_ACT_CFG0)\r
/*******************************************************************************\r
* File Name: CySpc.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides an API for the System Performance Component.\r
* application.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
* Summary:\r
* Loads a row of data into the row latch of a Flash/EEPROM array.\r
*\r
+* The buffer pointer should point to the data that should be written to the\r
+* flash row directly (no data in ECC/flash will be preserved). It is Flash API\r
+* responsibility to prepare data: the preserved data are copied from flash into\r
+* array with the modified data.\r
+*\r
* Parameters:\r
* uint8 array:\r
* Id of the array.\r
}\r
\r
\r
+/*******************************************************************************\r
+* Function Name: CySpcLoadRowFull\r
+********************************************************************************\r
+* Summary:\r
+* Loads a row of data into the row latch of a Flash/EEPROM array.\r
+*\r
+* The only data that are going to be changed should be passed. The function\r
+* will handle unmodified data preservation based on DWR settings and input\r
+* parameters.\r
+*\r
+* Parameters:\r
+* uint8 array:\r
+* Id of the array.\r
+*\r
+* uint16 row:\r
+* Flash row number to be loaded.\r
+*\r
+* uint8* buffer:\r
+* Data to be loaded to the row latch\r
+*\r
+* uint8 size:\r
+* The number of data bytes that the SPC expects to be written. Depends on the\r
+* type of the array and, if the array is Flash, whether ECC is being enabled\r
+* or not. There are following values: flash row latch size with ECC enabled,\r
+* flash row latch size with ECC disabled and EEPROM row latch size.\r
+*\r
+* Return:\r
+* CYRET_STARTED\r
+* CYRET_CANCELED\r
+* CYRET_LOCKED\r
+*\r
+*******************************************************************************/\r
+cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\\r
+\r
+{\r
+ cystatus status = CYRET_STARTED;\r
+ uint16 i;\r
+\r
+ #if (CYDEV_ECC_ENABLE == 0)\r
+ uint32 offset;\r
+ #endif /* (CYDEV_ECC_ENABLE == 0) */\r
+\r
+ /* Make sure the SPC is ready to accept command */\r
+ if(CY_SPC_IDLE)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW);\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW;\r
+\r
+ /* Make sure the command was accepted */\r
+ if(CY_SPC_BUSY)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = array;\r
+\r
+ /*******************************************************************\r
+ * If "Enable Error Correcting Code (ECC)" and "Store Configuration\r
+ * Data in ECC" DWR options are disabled, ECC section is available\r
+ * for user data.\r
+ *******************************************************************/\r
+ #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))\r
+\r
+ /*******************************************************************\r
+ * If size parameter equals size of the ECC row and selected array\r
+ * identification corresponds to the flash array (but not to EEPROM\r
+ * array) then data are going to be written to the ECC section.\r
+ * In this case flash data must be preserved. The flash data copied\r
+ * from flash data section to the SPC data register.\r
+ *******************************************************************/\r
+ if ((size == CYDEV_ECC_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))\r
+ {\r
+ offset = CYDEV_FLS_BASE +\r
+ ((uint32) array * CYDEV_FLS_SECTOR_SIZE) +\r
+ ((uint32) row * CYDEV_FLS_ROW_SIZE );\r
+\r
+ for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));\r
+ }\r
+ }\r
+\r
+ #endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */\r
+\r
+\r
+ for(i = 0u; i < size; i++)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = buffer[i];\r
+ }\r
+\r
+\r
+ /*******************************************************************\r
+ * If "Enable Error Correcting Code (ECC)" DWR option is disabled,\r
+ * ECC section can be used for storing device configuration data\r
+ * ("Store Configuration Data in ECC" DWR option is enabled) or for\r
+ * storing user data in the ECC section ("Store Configuration Data in\r
+ * ECC" DWR option is enabled). In both cases, the data in the ECC\r
+ * section must be preserved if flash data is written.\r
+ *******************************************************************/\r
+ #if (CYDEV_ECC_ENABLE == 0)\r
+\r
+\r
+ /*******************************************************************\r
+ * If size parameter equals size of the flash row and selected array\r
+ * identification corresponds to the flash array (but not to EEPROM\r
+ * array) then data are going to be written to the flash data\r
+ * section. In this case, ECC section data must be preserved.\r
+ * The ECC section data copied from ECC section to the SPC data\r
+ * register.\r
+ *******************************************************************/\r
+ if ((size == CYDEV_FLS_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))\r
+ {\r
+ offset = CYDEV_ECC_BASE +\r
+ ((uint32) array * CYDEV_ECC_SECTOR_SIZE) +\r
+ ((uint32) row * CYDEV_ECC_ROW_SIZE );\r
+\r
+ for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));\r
+ }\r
+ }\r
+\r
+ #else\r
+\r
+ if(0u != row)\r
+ {\r
+ /* To remove unreferenced local variable warning */\r
+ }\r
+\r
+ #endif /* (CYDEV_ECC_ENABLE == 0) */\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_CANCELED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
/*******************************************************************************\r
* Function Name: CySpcWriteRow\r
********************************************************************************\r
}\r
\r
\r
+/*******************************************************************************\r
+* Function Name: CySpcGetAlgorithm\r
+********************************************************************************\r
+* Summary:\r
+* Downloads SPC algorithm from SPC SROM into SRAM.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* CYRET_STARTED\r
+* CYRET_LOCKED\r
+*\r
+*******************************************************************************/\r
+cystatus CySpcGetAlgorithm(void)\r
+{\r
+ cystatus status = CYRET_STARTED;\r
+\r
+ /* Make sure the SPC is ready to accept command */\r
+ if(CY_SPC_IDLE)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_DWNLD_ALGORITHM);\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_CMD_DWNLD_ALGORITHM;\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
/* [] END OF FILE */\r
+\r
/*******************************************************************************\r
* File Name: CySpc.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides definitions for the System Performance Component API.\r
* application.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\\r
;\r
cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size);\r
+cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\\r
+;\r
cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\\r
;\r
cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber);\r
cystatus CySpcGetTemp(uint8 numSamples);\r
+cystatus CySpcGetAlgorithm(void);\r
cystatus CySpcLock(void);\r
void CySpcUnlock(void);\r
\r
#define CY_SPC_STATUS_CODE_MASK (0xFCu)\r
#define CY_SPC_STATUS_CODE_SHIFT (0x02u)\r
\r
-/* Status codes for the SPC. */\r
+/* Status codes for SPC. */\r
#define CY_SPC_STATUS_SUCCESS (0x00u) /* Operation Successful */\r
#define CY_SPC_STATUS_INVALID_ARRAY_ID (0x01u) /* Invalid Array ID for given command */\r
#define CY_SPC_STATUS_INVALID_2BYTEKEY (0x02u) /* Invalid 2-byte key */\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0\r
+* The following code is OBSOLETE and must not be used.\r
+*\r
+* If the obsoleted macro definitions intended for use in the application use the\r
+* following scheme, redefine your own versions of these definitions:\r
+* #ifdef <OBSOLETED_DEFINE>\r
+* #undef <OBSOLETED_DEFINE>\r
+* #define <OBSOLETED_DEFINE> (<New Value>)\r
+* #endif\r
+*\r
+* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* used in the application and their modification might lead to unexpected\r
+* consequences.\r
*******************************************************************************/\r
#define FIRST_FLASH_ARRAYID (CY_SPC_FIRST_FLASH_ARRAYID)\r
#define LAST_FLASH_ARRAYID (CY_SPC_LAST_FLASH_ARRAYID)\r
/*******************************************************************************\r
* File Name: SCSI_Out_DBx.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SCSI_Out_DBx_0 SCSI_Out_DBx__0__PC\r
-#define SCSI_Out_DBx_1 SCSI_Out_DBx__1__PC\r
-#define SCSI_Out_DBx_2 SCSI_Out_DBx__2__PC\r
-#define SCSI_Out_DBx_3 SCSI_Out_DBx__3__PC\r
-#define SCSI_Out_DBx_4 SCSI_Out_DBx__4__PC\r
-#define SCSI_Out_DBx_5 SCSI_Out_DBx__5__PC\r
-#define SCSI_Out_DBx_6 SCSI_Out_DBx__6__PC\r
-#define SCSI_Out_DBx_7 SCSI_Out_DBx__7__PC\r
-\r
-#define SCSI_Out_DBx_DB0 SCSI_Out_DBx__DB0__PC\r
-#define SCSI_Out_DBx_DB1 SCSI_Out_DBx__DB1__PC\r
-#define SCSI_Out_DBx_DB2 SCSI_Out_DBx__DB2__PC\r
-#define SCSI_Out_DBx_DB3 SCSI_Out_DBx__DB3__PC\r
-#define SCSI_Out_DBx_DB4 SCSI_Out_DBx__DB4__PC\r
-#define SCSI_Out_DBx_DB5 SCSI_Out_DBx__DB5__PC\r
-#define SCSI_Out_DBx_DB6 SCSI_Out_DBx__DB6__PC\r
-#define SCSI_Out_DBx_DB7 SCSI_Out_DBx__DB7__PC\r
+#define SCSI_Out_DBx_0 (SCSI_Out_DBx__0__PC)\r
+#define SCSI_Out_DBx_1 (SCSI_Out_DBx__1__PC)\r
+#define SCSI_Out_DBx_2 (SCSI_Out_DBx__2__PC)\r
+#define SCSI_Out_DBx_3 (SCSI_Out_DBx__3__PC)\r
+#define SCSI_Out_DBx_4 (SCSI_Out_DBx__4__PC)\r
+#define SCSI_Out_DBx_5 (SCSI_Out_DBx__5__PC)\r
+#define SCSI_Out_DBx_6 (SCSI_Out_DBx__6__PC)\r
+#define SCSI_Out_DBx_7 (SCSI_Out_DBx__7__PC)\r
+\r
+#define SCSI_Out_DBx_DB0 (SCSI_Out_DBx__DB0__PC)\r
+#define SCSI_Out_DBx_DB1 (SCSI_Out_DBx__DB1__PC)\r
+#define SCSI_Out_DBx_DB2 (SCSI_Out_DBx__DB2__PC)\r
+#define SCSI_Out_DBx_DB3 (SCSI_Out_DBx__DB3__PC)\r
+#define SCSI_Out_DBx_DB4 (SCSI_Out_DBx__DB4__PC)\r
+#define SCSI_Out_DBx_DB5 (SCSI_Out_DBx__DB5__PC)\r
+#define SCSI_Out_DBx_DB6 (SCSI_Out_DBx__DB6__PC)\r
+#define SCSI_Out_DBx_DB7 (SCSI_Out_DBx__DB7__PC)\r
\r
#endif /* End Pins SCSI_Out_DBx_ALIASES_H */\r
\r
/*******************************************************************************\r
* File Name: SCSI_Out.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/***************************************\r
* Constants \r
***************************************/\r
-#define SCSI_Out_0 SCSI_Out__0__PC\r
-#define SCSI_Out_1 SCSI_Out__1__PC\r
-#define SCSI_Out_2 SCSI_Out__2__PC\r
-#define SCSI_Out_3 SCSI_Out__3__PC\r
-#define SCSI_Out_4 SCSI_Out__4__PC\r
-#define SCSI_Out_5 SCSI_Out__5__PC\r
-#define SCSI_Out_6 SCSI_Out__6__PC\r
-#define SCSI_Out_7 SCSI_Out__7__PC\r
-#define SCSI_Out_8 SCSI_Out__8__PC\r
-#define SCSI_Out_9 SCSI_Out__9__PC\r
-\r
-#define SCSI_Out_DBP_raw SCSI_Out__DBP_raw__PC\r
-#define SCSI_Out_ATN SCSI_Out__ATN__PC\r
-#define SCSI_Out_BSY SCSI_Out__BSY__PC\r
-#define SCSI_Out_ACK SCSI_Out__ACK__PC\r
-#define SCSI_Out_RST SCSI_Out__RST__PC\r
-#define SCSI_Out_MSG SCSI_Out__MSG__PC\r
-#define SCSI_Out_SEL SCSI_Out__SEL__PC\r
-#define SCSI_Out_CD SCSI_Out__CD__PC\r
-#define SCSI_Out_REQ SCSI_Out__REQ__PC\r
-#define SCSI_Out_IO_raw SCSI_Out__IO_raw__PC\r
+#define SCSI_Out_0 (SCSI_Out__0__PC)\r
+#define SCSI_Out_1 (SCSI_Out__1__PC)\r
+#define SCSI_Out_2 (SCSI_Out__2__PC)\r
+#define SCSI_Out_3 (SCSI_Out__3__PC)\r
+#define SCSI_Out_4 (SCSI_Out__4__PC)\r
+#define SCSI_Out_5 (SCSI_Out__5__PC)\r
+#define SCSI_Out_6 (SCSI_Out__6__PC)\r
+#define SCSI_Out_7 (SCSI_Out__7__PC)\r
+#define SCSI_Out_8 (SCSI_Out__8__PC)\r
+#define SCSI_Out_9 (SCSI_Out__9__PC)\r
+\r
+#define SCSI_Out_DBP_raw (SCSI_Out__DBP_raw__PC)\r
+#define SCSI_Out_ATN (SCSI_Out__ATN__PC)\r
+#define SCSI_Out_BSY (SCSI_Out__BSY__PC)\r
+#define SCSI_Out_ACK (SCSI_Out__ACK__PC)\r
+#define SCSI_Out_RST (SCSI_Out__RST__PC)\r
+#define SCSI_Out_MSG (SCSI_Out__MSG__PC)\r
+#define SCSI_Out_SEL (SCSI_Out__SEL__PC)\r
+#define SCSI_Out_CD (SCSI_Out__CD__PC)\r
+#define SCSI_Out_REQ (SCSI_Out__REQ__PC)\r
+#define SCSI_Out_IO_raw (SCSI_Out__IO_raw__PC)\r
\r
#endif /* End Pins SCSI_Out_ALIASES_H */\r
\r
/*******************************************************************************
* File Name: SD_PULLUP.c
-* Version 1.90
+* Version 2.10
*
* Description:
* This file contains API to enable firmware control of a Pins component.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Change the drive mode on the pins of the port.
*
* Parameters:
-* mode: Change the pins to this drive mode.
+* mode: Change the pins to one of the following drive modes.
+*
+* SD_PULLUP_DM_STRONG Strong Drive
+* SD_PULLUP_DM_OD_HI Open Drain, Drives High
+* SD_PULLUP_DM_OD_LO Open Drain, Drives Low
+* SD_PULLUP_DM_RES_UP Resistive Pull Up
+* SD_PULLUP_DM_RES_DWN Resistive Pull Down
+* SD_PULLUP_DM_RES_UPDWN Resistive Pull Up/Down
+* SD_PULLUP_DM_DIG_HIZ High Impedance Digital
+* SD_PULLUP_DM_ALG_HIZ High Impedance Analog
*
* Return:
* None
/*******************************************************************************
* File Name: SD_PULLUP.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
/*******************************************************************************
* File Name: SD_PULLUP.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define SD_PULLUP_0 SD_PULLUP__0__PC
-#define SD_PULLUP_1 SD_PULLUP__1__PC
-#define SD_PULLUP_2 SD_PULLUP__2__PC
-#define SD_PULLUP_3 SD_PULLUP__3__PC
-#define SD_PULLUP_4 SD_PULLUP__4__PC
+#define SD_PULLUP_0 (SD_PULLUP__0__PC)
+#define SD_PULLUP_1 (SD_PULLUP__1__PC)
+#define SD_PULLUP_2 (SD_PULLUP__2__PC)
+#define SD_PULLUP_3 (SD_PULLUP__3__PC)
+#define SD_PULLUP_4 (SD_PULLUP__4__PC)
#endif /* End Pins SD_PULLUP_ALIASES_H */
/*******************************************************************************\r
* File Name: USBFS.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* API for USBFS Component.\r
* registers are indexed by variations of epNumber - 1.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#include "USBFS_hid.h"\r
#if(USBFS_DMA1_REMOVE == 0u)\r
#include "USBFS_ep1_dma.h"\r
-#endif /* End USBFS_DMA1_REMOVE */\r
+#endif /* USBFS_DMA1_REMOVE */\r
#if(USBFS_DMA2_REMOVE == 0u)\r
#include "USBFS_ep2_dma.h"\r
-#endif /* End USBFS_DMA2_REMOVE */\r
+#endif /* USBFS_DMA2_REMOVE */\r
#if(USBFS_DMA3_REMOVE == 0u)\r
#include "USBFS_ep3_dma.h"\r
-#endif /* End USBFS_DMA3_REMOVE */\r
+#endif /* USBFS_DMA3_REMOVE */\r
#if(USBFS_DMA4_REMOVE == 0u)\r
#include "USBFS_ep4_dma.h"\r
-#endif /* End USBFS_DMA4_REMOVE */\r
+#endif /* USBFS_DMA4_REMOVE */\r
#if(USBFS_DMA5_REMOVE == 0u)\r
#include "USBFS_ep5_dma.h"\r
-#endif /* End USBFS_DMA5_REMOVE */\r
+#endif /* USBFS_DMA5_REMOVE */\r
#if(USBFS_DMA6_REMOVE == 0u)\r
#include "USBFS_ep6_dma.h"\r
-#endif /* End USBFS_DMA6_REMOVE */\r
+#endif /* USBFS_DMA6_REMOVE */\r
#if(USBFS_DMA7_REMOVE == 0u)\r
#include "USBFS_ep7_dma.h"\r
-#endif /* End USBFS_DMA7_REMOVE */\r
+#endif /* USBFS_DMA7_REMOVE */\r
#if(USBFS_DMA8_REMOVE == 0u)\r
#include "USBFS_ep8_dma.h"\r
-#endif /* End USBFS_DMA8_REMOVE */\r
+#endif /* USBFS_DMA8_REMOVE */\r
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ #include "USBFS_EP_DMA_Done_isr.h"\r
+ #include "USBFS_EP8_DMA_Done_SR.h"\r
+ #include "USBFS_EP17_DMA_Done_SR.h"\r
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
\r
\r
/***************************************\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
uint8 USBFS_DmaChan[USBFS_MAX_EP];\r
uint8 USBFS_DmaTd[USBFS_MAX_EP];\r
-#endif /* End USBFS_EP_MM */\r
+#endif /* USBFS_EP_MM */\r
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ static uint8 clearInDataRdyStatus = USBFS_ARB_EPX_CFG_DEFAULT;\r
+ uint8 USBFS_DmaNextTd[USBFS_MAX_EP];\r
+ const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP] =\r
+ { 0u,\r
+ USBFS_ep1_TD_TERMOUT_EN,\r
+ USBFS_ep2_TD_TERMOUT_EN,\r
+ USBFS_ep3_TD_TERMOUT_EN,\r
+ USBFS_ep4_TD_TERMOUT_EN,\r
+ USBFS_ep5_TD_TERMOUT_EN,\r
+ USBFS_ep6_TD_TERMOUT_EN,\r
+ USBFS_ep7_TD_TERMOUT_EN,\r
+ USBFS_ep8_TD_TERMOUT_EN\r
+ };\r
+ volatile uint16 USBFS_inLength[USBFS_MAX_EP];\r
+ const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];\r
+ volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];\r
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
\r
\r
/*******************************************************************************\r
uint8 enableInterrupts;\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
uint16 i;\r
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
enableInterrupts = CyEnterCriticalSection();\r
\r
for (i = 0u; i < USBFS_MAX_EP; i++)\r
{\r
USBFS_DmaTd[i] = DMA_INVALID_TD;\r
+ #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ USBFS_DmaNextTd[i] = DMA_INVALID_TD;\r
+ #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
}\r
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
CyExitCriticalSection(enableInterrupts);\r
\r
#if(USBFS_SOF_ISR_REMOVE == 0u)\r
(void) CyIntSetVector(USBFS_SOF_VECT_NUM, &USBFS_SOF_ISR);\r
CyIntSetPriority(USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR);\r
- #endif /* End USBFS_SOF_ISR_REMOVE */\r
+ #endif /* USBFS_SOF_ISR_REMOVE */\r
\r
/* Set the Control Endpoint Interrupt. */\r
(void) CyIntSetVector(USBFS_EP_0_VECT_NUM, &USBFS_EP_0_ISR);\r
#if(USBFS_EP1_ISR_REMOVE == 0u)\r
(void) CyIntSetVector(USBFS_EP_1_VECT_NUM, &USBFS_EP_1_ISR);\r
CyIntSetPriority(USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR);\r
- #endif /* End USBFS_EP1_ISR_REMOVE */\r
+ #endif /* USBFS_EP1_ISR_REMOVE */\r
\r
/* Set the Data Endpoint 2 Interrupt. */\r
#if(USBFS_EP2_ISR_REMOVE == 0u)\r
(void) CyIntSetVector(USBFS_EP_2_VECT_NUM, &USBFS_EP_2_ISR);\r
CyIntSetPriority(USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR);\r
- #endif /* End USBFS_EP2_ISR_REMOVE */\r
+ #endif /* USBFS_EP2_ISR_REMOVE */\r
\r
/* Set the Data Endpoint 3 Interrupt. */\r
#if(USBFS_EP3_ISR_REMOVE == 0u)\r
(void) CyIntSetVector(USBFS_EP_3_VECT_NUM, &USBFS_EP_3_ISR);\r
CyIntSetPriority(USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR);\r
- #endif /* End USBFS_EP3_ISR_REMOVE */\r
+ #endif /* USBFS_EP3_ISR_REMOVE */\r
\r
/* Set the Data Endpoint 4 Interrupt. */\r
#if(USBFS_EP4_ISR_REMOVE == 0u)\r
(void) CyIntSetVector(USBFS_EP_4_VECT_NUM, &USBFS_EP_4_ISR);\r
CyIntSetPriority(USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR);\r
- #endif /* End USBFS_EP4_ISR_REMOVE */\r
+ #endif /* USBFS_EP4_ISR_REMOVE */\r
\r
/* Set the Data Endpoint 5 Interrupt. */\r
#if(USBFS_EP5_ISR_REMOVE == 0u)\r
(void) CyIntSetVector(USBFS_EP_5_VECT_NUM, &USBFS_EP_5_ISR);\r
CyIntSetPriority(USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR);\r
- #endif /* End USBFS_EP5_ISR_REMOVE */\r
+ #endif /* USBFS_EP5_ISR_REMOVE */\r
\r
/* Set the Data Endpoint 6 Interrupt. */\r
#if(USBFS_EP6_ISR_REMOVE == 0u)\r
(void) CyIntSetVector(USBFS_EP_6_VECT_NUM, &USBFS_EP_6_ISR);\r
CyIntSetPriority(USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR);\r
- #endif /* End USBFS_EP6_ISR_REMOVE */\r
+ #endif /* USBFS_EP6_ISR_REMOVE */\r
\r
/* Set the Data Endpoint 7 Interrupt. */\r
#if(USBFS_EP7_ISR_REMOVE == 0u)\r
(void) CyIntSetVector(USBFS_EP_7_VECT_NUM, &USBFS_EP_7_ISR);\r
CyIntSetPriority(USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR);\r
- #endif /* End USBFS_EP7_ISR_REMOVE */\r
+ #endif /* USBFS_EP7_ISR_REMOVE */\r
\r
/* Set the Data Endpoint 8 Interrupt. */\r
#if(USBFS_EP8_ISR_REMOVE == 0u)\r
(void) CyIntSetVector(USBFS_EP_8_VECT_NUM, &USBFS_EP_8_ISR);\r
CyIntSetPriority(USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR);\r
- #endif /* End USBFS_EP8_ISR_REMOVE */\r
+ #endif /* USBFS_EP8_ISR_REMOVE */\r
\r
#if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))\r
/* Set the ARB Interrupt. */\r
(void) CyIntSetVector(USBFS_ARB_VECT_NUM, &USBFS_ARB_ISR);\r
CyIntSetPriority(USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR);\r
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
}\r
\r
CyIntEnable(USBFS_EP_0_VECT_NUM);\r
#if(USBFS_EP1_ISR_REMOVE == 0u)\r
CyIntEnable(USBFS_EP_1_VECT_NUM);\r
- #endif /* End USBFS_EP1_ISR_REMOVE */\r
+ #endif /* USBFS_EP1_ISR_REMOVE */\r
#if(USBFS_EP2_ISR_REMOVE == 0u)\r
CyIntEnable(USBFS_EP_2_VECT_NUM);\r
- #endif /* End USBFS_EP2_ISR_REMOVE */\r
+ #endif /* USBFS_EP2_ISR_REMOVE */\r
#if(USBFS_EP3_ISR_REMOVE == 0u)\r
CyIntEnable(USBFS_EP_3_VECT_NUM);\r
- #endif /* End USBFS_EP3_ISR_REMOVE */\r
+ #endif /* USBFS_EP3_ISR_REMOVE */\r
#if(USBFS_EP4_ISR_REMOVE == 0u)\r
CyIntEnable(USBFS_EP_4_VECT_NUM);\r
- #endif /* End USBFS_EP4_ISR_REMOVE */\r
+ #endif /* USBFS_EP4_ISR_REMOVE */\r
#if(USBFS_EP5_ISR_REMOVE == 0u)\r
CyIntEnable(USBFS_EP_5_VECT_NUM);\r
- #endif /* End USBFS_EP5_ISR_REMOVE */\r
+ #endif /* USBFS_EP5_ISR_REMOVE */\r
#if(USBFS_EP6_ISR_REMOVE == 0u)\r
CyIntEnable(USBFS_EP_6_VECT_NUM);\r
- #endif /* End USBFS_EP6_ISR_REMOVE */\r
+ #endif /* USBFS_EP6_ISR_REMOVE */\r
#if(USBFS_EP7_ISR_REMOVE == 0u)\r
CyIntEnable(USBFS_EP_7_VECT_NUM);\r
- #endif /* End USBFS_EP7_ISR_REMOVE */\r
+ #endif /* USBFS_EP7_ISR_REMOVE */\r
#if(USBFS_EP8_ISR_REMOVE == 0u)\r
CyIntEnable(USBFS_EP_8_VECT_NUM);\r
- #endif /* End USBFS_EP8_ISR_REMOVE */\r
+ #endif /* USBFS_EP8_ISR_REMOVE */\r
#if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))\r
/* usb arb interrupt enable */\r
USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;\r
CyIntEnable(USBFS_ARB_VECT_NUM);\r
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
/* Arbiter configuration for DMA transfers */\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
-\r
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
/*Set cfg cmplt this rises DMA request when the full configuration is done */\r
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #if(USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ /* Init interrupt which handles verification of the successful DMA transaction */\r
+ USBFS_EP_DMA_Done_isr_StartEx(&USBFS_EP_DMA_DONE_ISR);\r
+ USBFS_EP17_DMA_Done_SR_InterruptEnable();\r
+ USBFS_EP8_DMA_Done_SR_InterruptEnable();\r
+ #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
USBFS_transferState = USBFS_TRANS_STATE_IDLE;\r
\r
USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;\r
#else\r
USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE;\r
- #endif /* End USBFS_VDDD_MV < USBFS_3500MV */\r
+ #endif /* USBFS_VDDD_MV < USBFS_3500MV */\r
break;\r
}\r
\r
\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */\r
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
/* Disable the SIE */\r
USBFS_CR0_REG &= (uint8)(~USBFS_CR0_ENABLE);\r
CyIntDisable(USBFS_EP_0_VECT_NUM);\r
#if(USBFS_EP1_ISR_REMOVE == 0u)\r
CyIntDisable(USBFS_EP_1_VECT_NUM);\r
- #endif /* End USBFS_EP1_ISR_REMOVE */\r
+ #endif /* USBFS_EP1_ISR_REMOVE */\r
#if(USBFS_EP2_ISR_REMOVE == 0u)\r
CyIntDisable(USBFS_EP_2_VECT_NUM);\r
- #endif /* End USBFS_EP2_ISR_REMOVE */\r
+ #endif /* USBFS_EP2_ISR_REMOVE */\r
#if(USBFS_EP3_ISR_REMOVE == 0u)\r
CyIntDisable(USBFS_EP_3_VECT_NUM);\r
- #endif /* End USBFS_EP3_ISR_REMOVE */\r
+ #endif /* USBFS_EP3_ISR_REMOVE */\r
#if(USBFS_EP4_ISR_REMOVE == 0u)\r
CyIntDisable(USBFS_EP_4_VECT_NUM);\r
- #endif /* End USBFS_EP4_ISR_REMOVE */\r
+ #endif /* USBFS_EP4_ISR_REMOVE */\r
#if(USBFS_EP5_ISR_REMOVE == 0u)\r
CyIntDisable(USBFS_EP_5_VECT_NUM);\r
- #endif /* End USBFS_EP5_ISR_REMOVE */\r
+ #endif /* USBFS_EP5_ISR_REMOVE */\r
#if(USBFS_EP6_ISR_REMOVE == 0u)\r
CyIntDisable(USBFS_EP_6_VECT_NUM);\r
- #endif /* End USBFS_EP6_ISR_REMOVE */\r
+ #endif /* USBFS_EP6_ISR_REMOVE */\r
#if(USBFS_EP7_ISR_REMOVE == 0u)\r
CyIntDisable(USBFS_EP_7_VECT_NUM);\r
- #endif /* End USBFS_EP7_ISR_REMOVE */\r
+ #endif /* USBFS_EP7_ISR_REMOVE */\r
#if(USBFS_EP8_ISR_REMOVE == 0u)\r
CyIntDisable(USBFS_EP_8_VECT_NUM);\r
- #endif /* End USBFS_EP8_ISR_REMOVE */\r
+ #endif /* USBFS_EP8_ISR_REMOVE */\r
\r
/* Clear all of the component data */\r
USBFS_configuration = 0u;\r
* No.\r
*\r
*******************************************************************************/\r
- void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData)\r
+ void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)\r
\r
{\r
uint16 src;\r
src = HI16(CYDEV_PERIPH_BASE);\r
dst = HI16(pData);\r
}\r
- #endif /* End C51 */\r
+ #endif /* C51 */\r
switch(epNumber)\r
{\r
case USBFS_EP1:\r
#if(USBFS_DMA1_REMOVE == 0u)\r
USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize(\r
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_DMA1_REMOVE */\r
+ #endif /* USBFS_DMA1_REMOVE */\r
break;\r
case USBFS_EP2:\r
#if(USBFS_DMA2_REMOVE == 0u)\r
USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize(\r
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_DMA2_REMOVE */\r
+ #endif /* USBFS_DMA2_REMOVE */\r
break;\r
case USBFS_EP3:\r
#if(USBFS_DMA3_REMOVE == 0u)\r
USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize(\r
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_DMA3_REMOVE */\r
+ #endif /* USBFS_DMA3_REMOVE */\r
break;\r
case USBFS_EP4:\r
#if(USBFS_DMA4_REMOVE == 0u)\r
USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize(\r
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_DMA4_REMOVE */\r
+ #endif /* USBFS_DMA4_REMOVE */\r
break;\r
case USBFS_EP5:\r
#if(USBFS_DMA5_REMOVE == 0u)\r
USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize(\r
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_DMA5_REMOVE */\r
+ #endif /* USBFS_DMA5_REMOVE */\r
break;\r
case USBFS_EP6:\r
#if(USBFS_DMA6_REMOVE == 0u)\r
USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize(\r
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_DMA6_REMOVE */\r
+ #endif /* USBFS_DMA6_REMOVE */\r
break;\r
case USBFS_EP7:\r
#if(USBFS_DMA7_REMOVE == 0u)\r
USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize(\r
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_DMA7_REMOVE */\r
+ #endif /* USBFS_DMA7_REMOVE */\r
break;\r
case USBFS_EP8:\r
#if(USBFS_DMA8_REMOVE == 0u)\r
USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize(\r
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);\r
- #endif /* End USBFS_DMA8_REMOVE */\r
+ #endif /* USBFS_DMA8_REMOVE */\r
break;\r
default:\r
/* Do not support EP0 DMA transfers */\r
if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
USBFS_DmaTd[epNumber] = CyDmaTdAllocate();\r
+ #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ USBFS_DmaNextTd[epNumber] = CyDmaTdAllocate();\r
+ #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
+\r
}\r
}\r
\r
CyDmaTdFree(USBFS_DmaTd[i]);\r
USBFS_DmaTd[i] = DMA_INVALID_TD;\r
}\r
+ #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ if(USBFS_DmaNextTd[i] != DMA_INVALID_TD)\r
+ {\r
+ CyDmaTdFree(USBFS_DmaNextTd[i]);\r
+ USBFS_DmaNextTd[i] = DMA_INVALID_TD;\r
+ }\r
+ #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
i++;\r
}while((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP));\r
}\r
\r
-#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+#endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
+\r
+\r
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: USBFS_LoadNextInEP\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * This internal function is used for IN endpoint DMA reconfiguration in\r
+ * Auto DMA mode.\r
+ *\r
+ * Parameters:\r
+ * epNumber: Contains the data endpoint number.\r
+ * mode: 0 - Configure DMA to send the the rest of data.\r
+ * 1 - Configure DMA to repeat 2 last bytes of the first burst.\r
+ *\r
+ * Return:\r
+ * None.\r
+ *\r
+ *******************************************************************************/\r
+ void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) \r
+ {\r
+ reg16 *convert;\r
+\r
+ if(mode == 0u)\r
+ {\r
+ /* Configure DMA to send the the rest of data */\r
+ /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */\r
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];\r
+ /* Set transfer length */\r
+ CY_SET_REG16(convert, USBFS_inLength[epNumber] - USBFS_DMA_BYTES_PER_BURST);\r
+ /* CyDmaTdSetAddress API is optimized to change only source address */\r
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];\r
+ CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] +\r
+ USBFS_DMA_BYTES_PER_BURST));\r
+ USBFS_inBufFull[epNumber] = 1u;\r
+ }\r
+ else\r
+ {\r
+ /* Configure DMA to repeat 2 last bytes of the first burst. */\r
+ /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */\r
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];\r
+ /* Set transfer length */\r
+ CY_SET_REG16(convert, USBFS_DMA_BYTES_REPEAT);\r
+ /* CyDmaTdSetAddress API is optimized to change only source address */\r
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];\r
+ CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] +\r
+ USBFS_DMA_BYTES_PER_BURST - USBFS_DMA_BYTES_REPEAT));\r
+ }\r
+\r
+ /* CyDmaChSetInitialTd API is optimised to init TD */\r
+ CY_DMA_CH_STRUCT_PTR[USBFS_DmaChan[epNumber]].basic_status[1u] = USBFS_DmaTd[epNumber];\r
+ }\r
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
\r
\r
/*******************************************************************************\r
********************************************************************************\r
*\r
* Summary:\r
-* Loads and enables the specified USB data endpoint for an IN interrupt or bulk\r
-* transfer.\r
+* Loads and enables the specified USB data endpoint for an IN transfer.\r
*\r
* Parameters:\r
* epNumber: Contains the data endpoint number.\r
reg8 *p;\r
#if(USBFS_EP_MM == USBFS__EP_MANUAL)\r
uint16 i;\r
- #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */\r
\r
if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))\r
{\r
{\r
length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset;\r
}\r
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
\r
/* Set the count and data toggle */\r
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri),\r
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);\r
#else\r
/* Init DMA if it was not initialized */\r
- if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD)\r
+ if (USBFS_DmaTd[epNumber] == DMA_INVALID_TD)\r
{\r
USBFS_InitEP_DMA(epNumber, pData);\r
}\r
- #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */\r
\r
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
- if((pData != NULL) && (length > 0u))\r
+ if ((pData != NULL) && (length > 0u))\r
{\r
/* Enable DMA in mode2 for transferring data */\r
(void) CyDmaChDisable(USBFS_DmaChan[epNumber]);\r
/* When zero-length packet - write the Mode register directly */\r
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);\r
}\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- if(pData != NULL)\r
+ if (pData != NULL)\r
{\r
/* Enable DMA in mode3 for transferring data */\r
(void) CyDmaChDisable(USBFS_DmaChan[epNumber]);\r
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ USBFS_inLength[epNumber] = length;\r
+ USBFS_inDataPointer[epNumber] = pData;\r
+ /* Configure DMA to send the data only for the first burst */\r
+ (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber],\r
+ (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length,\r
+ USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);\r
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));\r
+ /* The second TD will be executed only when the first one fails.\r
+ * The intention of this TD is to generate NRQ interrupt\r
+ * and repeat 2 last bytes of the first burst.\r
+ */\r
+ (void) CyDmaTdSetConfiguration(USBFS_DmaNextTd[epNumber], 1u,\r
+ USBFS_DmaNextTd[epNumber],\r
+ USBFS_epX_TD_TERMOUT_EN[epNumber]);\r
+ /* Configure DmaNextTd to clear Data ready status */\r
+ (void) CyDmaTdSetAddress(USBFS_DmaNextTd[epNumber], LO16((uint32)&clearInDataRdyStatus),\r
+ LO16((uint32)(USBFS_ARB_EP1_CFG_IND + ri)));\r
+ #else /* Configure DMA to send all data*/\r
(void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length,\r
USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);\r
(void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));\r
+ #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */\r
+\r
/* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */\r
(void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);\r
/* Enable the DMA */\r
USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;\r
if(length > 0u)\r
{\r
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)\r
+ USBFS_inLength[epNumber] = length;\r
+ USBFS_inBufFull[epNumber] = 0u;\r
+ (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);\r
+ /* Configure DMA to send the data only for the first burst */\r
+ (void) CyDmaTdSetConfiguration(\r
+ USBFS_DmaTd[epNumber], (length > USBFS_DMA_BYTES_PER_BURST) ?\r
+ USBFS_DMA_BYTES_PER_BURST : length,\r
+ USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR );\r
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],\r
+ LO16((uint32)USBFS_inDataPointer[epNumber]), LO16((uint32)p));\r
+ /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */\r
+ (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);\r
+ /* Enable the DMA */\r
+ (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);\r
+ (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);\r
+ #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+\r
/* Set Data ready status, This will generate DMA request */\r
- * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+ #ifndef USBFS_MANUAL_IN_EP_ARM\r
+ * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+ #endif /* USBFS_MANUAL_IN_EP_ARM */\r
/* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */\r
}\r
else\r
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);\r
}\r
}\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
-\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
}\r
}\r
\r
reg8 *p;\r
#if(USBFS_EP_MM == USBFS__EP_MANUAL)\r
uint16 i;\r
- #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */\r
#if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
uint16 xferCount;\r
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
\r
if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL))\r
{\r
{\r
length = xferCount;\r
}\r
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
\r
#if(USBFS_EP_MM == USBFS__EP_MANUAL)\r
/* Copy the data using the arbiter data register */\r
{\r
USBFS_InitEP_DMA(epNumber, pData);\r
}\r
- #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */\r
+\r
+ #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */\r
\r
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
/* Enable DMA in mode2 for transferring data */\r
* (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ;\r
* (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ));\r
/* Out EP will be (re)armed in arb ISR after transfer complete */\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
/* Enable DMA in mode3 for transferring data */\r
(void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);\r
(void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);\r
/* Out EP will be (re)armed in arb ISR after transfer complete */\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
\r
}\r
else\r
/*******************************************************************************\r
* File Name: USBFS.h\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
-* Header File for the USFS component. Contains prototypes and constant values.\r
+* Header File for the USBFS component. Contains prototypes and constant values.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#include "cyfitter.h"\r
#include "CyLib.h"\r
\r
+/* User supplied definitions. */\r
+/* `#START USER_DEFINITIONS` Place your declaration here */\r
+\r
+/* `#END` */\r
+\r
\r
/***************************************\r
* Conditional Compilation Parameters\r
/* Check to see if required defines such as CY_PSOC5LP are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5LP)\r
- #error Component USBFS_v2_60 requires cy_boot v3.0 or later\r
+ #error Component USBFS_v2_80 requires cy_boot v3.0 or later\r
#endif /* (CY_PSOC5LP) */\r
\r
\r
#else\r
#define USBFS_DATA\r
#define USBFS_XDATA\r
-#endif /* End __C51__ */\r
+#endif /* __C51__ */\r
#define USBFS_NULL NULL\r
\r
\r
#define USBFS_EP8_ISR_REMOVE (1u)\r
#define USBFS_EP_MM (0u)\r
#define USBFS_EP_MA (0u)\r
+#define USBFS_EP_DMA_AUTO_OPT (0u)\r
#define USBFS_DMA1_REMOVE (1u)\r
#define USBFS_DMA2_REMOVE (1u)\r
#define USBFS_DMA3_REMOVE (1u)\r
#endif /* USBFS_ENABLE_FWSN_STRING */\r
#if (USBFS_MON_VBUS == 1u)\r
uint8 USBFS_VBusPresent(void) ;\r
-#endif /* End USBFS_MON_VBUS */\r
+#endif /* USBFS_MON_VBUS */\r
\r
#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \\r
(CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))\r
void USBFS_CyBtldrCommStart(void) ;\r
void USBFS_CyBtldrCommStop(void) ;\r
void USBFS_CyBtldrCommReset(void) ;\r
- cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
+ cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
;\r
- cystatus USBFS_CyBtldrCommRead( uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
+ cystatus USBFS_CyBtldrCommRead (uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
;\r
\r
- #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* EP 1 OUT */\r
- #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* EP 2 IN */\r
- #define USBFS_BTLDR_MAX_PACKET_SIZE USBFS_BTLDR_SIZEOF_WRITE_BUFFER\r
+ #define USBFS_BTLDR_OUT_EP (0x01u)\r
+ #define USBFS_BTLDR_IN_EP (0x02u)\r
+\r
+ #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* EP 1 OUT */\r
+ #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* EP 2 IN */\r
+ #define USBFS_BTLDR_MAX_PACKET_SIZE USBFS_BTLDR_SIZEOF_WRITE_BUFFER\r
+\r
+ #define USBFS_BTLDR_WAIT_1_MS (1u) /* Time Out quantity equal 1mS */\r
\r
/* These defines active if used USBFS interface as an\r
* IO Component for bootloading. When Custom_Interface selected\r
* in Bootloder configuration as the IO Component, user must\r
- * provide these functions\r
+ * provide these functions.\r
*/\r
#if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS)\r
#define CyBtldrCommStart USBFS_CyBtldrCommStart\r
#define CyBtldrCommRead USBFS_CyBtldrCommRead\r
#endif /*End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */\r
\r
-#endif /* End CYDEV_BOOTLOADER_IO_COMP */\r
+#endif /* CYDEV_BOOTLOADER_IO_COMP */\r
\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData)\r
+ void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)\r
;\r
void USBFS_Stop_DMA(uint8 epNumber) ;\r
-#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL) */\r
+#endif /* USBFS_EP_MM != USBFS__EP_MANUAL) */\r
\r
#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)\r
void USBFS_MIDI_EP_Init(void) ;\r
void USBFS_MIDI_OUT_EP_Service(void) ;\r
#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */\r
\r
-#endif /* End USBFS_ENABLE_MIDI_API != 0u */\r
+#endif /* USBFS_ENABLE_MIDI_API != 0u */\r
\r
/* Renamed Functions for backward compatibility.\r
* Should not be used in new designs.\r
#define USBFS_EP_USAGE_TYPE_RESERVED (0x30u)\r
#define USBFS_EP_USAGE_TYPE_MASK (0x30u)\r
\r
-/* Endpoint Status defines */\r
+/* point Status defines */\r
#define USBFS_EP_STATUS_LENGTH (0x02u)\r
\r
-/* Endpoint Device defines */\r
+/* point Device defines */\r
#define USBFS_DEVICE_STATUS_LENGTH (0x02u)\r
\r
#define USBFS_STATUS_LENGTH_MAX \\r
/* DMA manual mode defines */\r
#define USBFS_DMA_BYTES_PER_BURST (0u)\r
#define USBFS_DMA_REQUEST_PER_BURST (0u)\r
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
+#endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
/* DMA automatic mode defines */\r
#define USBFS_DMA_BYTES_PER_BURST (32u)\r
+ #define USBFS_DMA_BYTES_REPEAT (2u)\r
/* BUF_SIZE-BYTES_PER_BURST examples: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */\r
#define USBFS_DMA_BUF_SIZE (0x55u)\r
#define USBFS_DMA_REQUEST_PER_BURST (1u)\r
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+\r
+ #if(USBFS_DMA1_REMOVE == 0u)\r
+ #define USBFS_ep1_TD_TERMOUT_EN USBFS_ep1__TD_TERMOUT_EN\r
+ #else\r
+ #define USBFS_ep1_TD_TERMOUT_EN (0u)\r
+ #endif /* USBFS_DMA1_REMOVE == 0u */\r
+ #if(USBFS_DMA2_REMOVE == 0u)\r
+ #define USBFS_ep2_TD_TERMOUT_EN USBFS_ep2__TD_TERMOUT_EN\r
+ #else\r
+ #define USBFS_ep2_TD_TERMOUT_EN (0u)\r
+ #endif /* USBFS_DMA2_REMOVE == 0u */\r
+ #if(USBFS_DMA3_REMOVE == 0u)\r
+ #define USBFS_ep3_TD_TERMOUT_EN USBFS_ep3__TD_TERMOUT_EN\r
+ #else\r
+ #define USBFS_ep3_TD_TERMOUT_EN (0u)\r
+ #endif /* USBFS_DMA3_REMOVE == 0u */\r
+ #if(USBFS_DMA4_REMOVE == 0u)\r
+ #define USBFS_ep4_TD_TERMOUT_EN USBFS_ep4__TD_TERMOUT_EN\r
+ #else\r
+ #define USBFS_ep4_TD_TERMOUT_EN (0u)\r
+ #endif /* USBFS_DMA4_REMOVE == 0u */\r
+ #if(USBFS_DMA5_REMOVE == 0u)\r
+ #define USBFS_ep5_TD_TERMOUT_EN USBFS_ep5__TD_TERMOUT_EN\r
+ #else\r
+ #define USBFS_ep5_TD_TERMOUT_EN (0u)\r
+ #endif /* USBFS_DMA5_REMOVE == 0u */\r
+ #if(USBFS_DMA6_REMOVE == 0u)\r
+ #define USBFS_ep6_TD_TERMOUT_EN USBFS_ep6__TD_TERMOUT_EN\r
+ #else\r
+ #define USBFS_ep6_TD_TERMOUT_EN (0u)\r
+ #endif /* USBFS_DMA6_REMOVE == 0u */\r
+ #if(USBFS_DMA7_REMOVE == 0u)\r
+ #define USBFS_ep7_TD_TERMOUT_EN USBFS_ep7__TD_TERMOUT_EN\r
+ #else\r
+ #define USBFS_ep7_TD_TERMOUT_EN (0u)\r
+ #endif /* USBFS_DMA7_REMOVE == 0u */\r
+ #if(USBFS_DMA8_REMOVE == 0u)\r
+ #define USBFS_ep8_TD_TERMOUT_EN USBFS_ep8__TD_TERMOUT_EN\r
+ #else\r
+ #define USBFS_ep8_TD_TERMOUT_EN (0u)\r
+ #endif /* USBFS_DMA8_REMOVE == 0u */\r
+\r
+ #define USBFS_EP17_SR_MASK (0x7fu)\r
+ #define USBFS_EP8_SR_MASK (0x03u)\r
+\r
+#endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
\r
/* DIE ID string descriptor defines */\r
#if defined(USBFS_ENABLE_IDSN_STRING)\r
#if(!CY_PSOC5LP)\r
#define USBFS_USBIO_CR2_PTR ( (reg8 *) USBFS_USB__USBIO_CR2)\r
#define USBFS_USBIO_CR2_REG (* (reg8 *) USBFS_USB__USBIO_CR2)\r
-#endif /* End CY_PSOC5LP */\r
+#endif /* CY_PSOC5LP */\r
\r
#define USBFS_DIE_ID CYDEV_FLSHID_CUST_TABLES_BASE\r
\r
#else\r
#define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG )\r
#define USBFS_VBUS_MASK (0x01u)\r
- #endif /* End USBFS_EXTERN_VBUS == 0u */\r
-#endif /* End USBFS_MON_VBUS */\r
+ #endif /* USBFS_EXTERN_VBUS == 0u */\r
+#endif /* USBFS_MON_VBUS */\r
\r
/* Renamed Registers for backward compatibility.\r
* Should not be used in new designs.\r
#define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0)\r
#define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0)\r
#define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET)\r
-#endif /* End CYDEV_CHIP_DIE_EXPECT */\r
+#endif /* CYDEV_CHIP_DIE_EXPECT */\r
\r
\r
/***************************************\r
#define USBFS_ARB_EPX_CFG_CRC_BYPASS (0x04u)\r
#define USBFS_ARB_EPX_CFG_DMA_REQ (0x02u)\r
#define USBFS_ARB_EPX_CFG_IN_DATA_RDY (0x01u)\r
+#define USBFS_ARB_EPX_CFG_DEFAULT (USBFS_ARB_EPX_CFG_RESET | \\r
+ USBFS_ARB_EPX_CFG_CRC_BYPASS)\r
\r
#define USBFS_ARB_EPX_SR_IN_BUF_FULL (0x01u)\r
#define USBFS_ARB_EPX_SR_DMA_GNT (0x02u)\r
#define USBFS_ARB_EPX_INT_MASK (0x1Du)\r
#else\r
#define USBFS_ARB_EPX_INT_MASK (0x1Fu)\r
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+#endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
#define USBFS_ARB_INT_MASK (uint8)((USBFS_DMA1_REMOVE ^ 1u) | \\r
(uint8)((USBFS_DMA2_REMOVE ^ 1u) << 1u) | \\r
(uint8)((USBFS_DMA3_REMOVE ^ 1u) << 2u) | \\r
#define USBFS_DYN_RECONFIG_RDY_STS (0x10u)\r
\r
\r
-#endif /* End CY_USBFS_USBFS_H */\r
+#endif /* CY_USBFS_USBFS_H */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_Dm.c \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
* Change the drive mode on the pins of the port.\r
* \r
* Parameters: \r
-* mode: Change the pins to this drive mode.\r
+* mode: Change the pins to one of the following drive modes.\r
+*\r
+* USBFS_Dm_DM_STRONG Strong Drive \r
+* USBFS_Dm_DM_OD_HI Open Drain, Drives High \r
+* USBFS_Dm_DM_OD_LO Open Drain, Drives Low \r
+* USBFS_Dm_DM_RES_UP Resistive Pull Up \r
+* USBFS_Dm_DM_RES_DWN Resistive Pull Down \r
+* USBFS_Dm_DM_RES_UPDWN Resistive Pull Up/Down \r
+* USBFS_Dm_DM_DIG_HIZ High Impedance Digital \r
+* USBFS_Dm_DM_ALG_HIZ High Impedance Analog \r
*\r
* Return: \r
* None\r
/*******************************************************************************\r
* File Name: USBFS_Dm.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/* Check to see if required defines such as CY_PSOC5A are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
#endif /* (CY_PSOC5A) */\r
\r
/* APIs are not generated for P15[7:6] */\r
/*******************************************************************************\r
* File Name: USBFS_Dm.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/***************************************\r
* Constants \r
***************************************/\r
-#define USBFS_Dm_0 USBFS_Dm__0__PC\r
+#define USBFS_Dm_0 (USBFS_Dm__0__PC)\r
\r
#endif /* End Pins USBFS_Dm_ALIASES_H */\r
\r
/*******************************************************************************\r
* File Name: USBFS_Dp.c \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file contains API to enable firmware control of a Pins component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
* Change the drive mode on the pins of the port.\r
* \r
* Parameters: \r
-* mode: Change the pins to this drive mode.\r
+* mode: Change the pins to one of the following drive modes.\r
+*\r
+* USBFS_Dp_DM_STRONG Strong Drive \r
+* USBFS_Dp_DM_OD_HI Open Drain, Drives High \r
+* USBFS_Dp_DM_OD_LO Open Drain, Drives Low \r
+* USBFS_Dp_DM_RES_UP Resistive Pull Up \r
+* USBFS_Dp_DM_RES_DWN Resistive Pull Down \r
+* USBFS_Dp_DM_RES_UPDWN Resistive Pull Up/Down \r
+* USBFS_Dp_DM_DIG_HIZ High Impedance Digital \r
+* USBFS_Dp_DM_ALG_HIZ High Impedance Analog \r
*\r
* Return: \r
* None\r
/*******************************************************************************\r
* File Name: USBFS_Dp.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/* Check to see if required defines such as CY_PSOC5A are available */\r
/* They are defined starting with cy_boot v3.0 */\r
#if !defined (CY_PSOC5A)\r
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later\r
#endif /* (CY_PSOC5A) */\r
\r
/* APIs are not generated for P15[7:6] */\r
/*******************************************************************************\r
* File Name: USBFS_Dp.h \r
-* Version 1.90\r
+* Version 2.10\r
*\r
* Description:\r
* This file containts Control Register function prototypes and register defines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions, \r
* disclaimers, and limitations in the end user license agreement accompanying \r
* the software package with which this file was provided.\r
/***************************************\r
* Constants \r
***************************************/\r
-#define USBFS_Dp_0 USBFS_Dp__0__PC\r
+#define USBFS_Dp_0 (USBFS_Dp__0__PC)\r
\r
#endif /* End Pins USBFS_Dp_ALIASES_H */\r
\r
/*******************************************************************************\r
* File Name: USBFS_audio.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* USB AUDIO Class request handler.\r
*\r
-* Note:\r
+* Related Document:\r
+* Universal Serial Bus Device Class Definition for Audio Devices Release 1.0\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
#include "USBFS_audio.h"\r
#include "USBFS_pvt.h"\r
-#if defined(USBFS_ENABLE_MIDI_STREAMING) \r
+#if defined(USBFS_ENABLE_MIDI_STREAMING)\r
#include "USBFS_midi.h"\r
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/\r
+#endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
\r
\r
/***************************************\r
USBFS_VOL_MAX_MSB};\r
volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_RES_LSB,\r
USBFS_VOL_RES_MSB};\r
-#endif /* End USBFS_ENABLE_AUDIO_STREAMING */\r
+#endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
\r
\r
/*******************************************************************************\r
uint8 USBFS_DispatchAUDIOClassRqst(void) \r
{\r
uint8 requestHandled = USBFS_FALSE;\r
+ uint8 bmRequestType = CY_GET_REG8(USBFS_bmRequestType);\r
\r
#if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
uint8 epNumber;\r
epNumber = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED;\r
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */\r
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
\r
- if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)\r
+\r
+ if ((bmRequestType & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)\r
{\r
/* Control Read */\r
- if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \\r
- USBFS_RQST_RCPT_EP)\r
+ if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)\r
{\r
/* Endpoint */\r
switch (CY_GET_REG8(USBFS_bRequest))\r
#if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)\r
{\r
- /* Endpoint Control Selector is Sampling Frequency */\r
+ /* point Control Selector is Sampling Frequency */\r
USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;\r
USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber];\r
requestHandled = USBFS_InitControlRead();\r
}\r
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */\r
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
\r
/* `#START AUDIO_READ_REQUESTS` Place other request handler here */\r
\r
break;\r
}\r
}\r
- else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \\r
- USBFS_RQST_RCPT_IFC)\r
+ else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)\r
{\r
/* Interface or Entity ID */\r
switch (CY_GET_REG8(USBFS_bRequest))\r
/* `#START MUTE_CONTROL_GET_REQUEST` Place multi-channel handler here */\r
\r
/* `#END` */\r
- \r
+\r
/* Entity ID Control Selector is MUTE */\r
USBFS_currentTD.wCount = 1u;\r
USBFS_currentTD.pData = &USBFS_currentMute;\r
USBFS_currentTD.wCount = 0u;\r
requestHandled = USBFS_InitControlWrite();\r
\r
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */\r
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
\r
/* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */\r
\r
{ /* USBFS_RQST_RCPT_OTHER */\r
}\r
}\r
- else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == \\r
- USBFS_RQST_DIR_H2D)\r
+ else\r
{\r
/* Control Write */\r
- if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \\r
- USBFS_RQST_RCPT_EP)\r
+ if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)\r
{\r
- /* Endpoint */\r
+ /* point */\r
switch (CY_GET_REG8(USBFS_bRequest))\r
{\r
case USBFS_SET_CUR:\r
#if defined(USBFS_ENABLE_AUDIO_STREAMING)\r
if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)\r
{\r
- /* Endpoint Control Selector is Sampling Frequency */\r
+ /* point Control Selector is Sampling Frequency */\r
USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;\r
USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber];\r
requestHandled = USBFS_InitControlWrite();\r
USBFS_frequencyChanged = epNumber;\r
}\r
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */\r
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
\r
/* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */\r
\r
break;\r
}\r
}\r
- else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \\r
- USBFS_RQST_RCPT_IFC)\r
+ else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)\r
{\r
/* Interface or Entity ID */\r
switch (CY_GET_REG8(USBFS_bRequest))\r
\r
/* `#END` */\r
}\r
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */\r
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */\r
\r
/* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */\r
\r
}\r
}\r
else\r
- { /* USBFS_RQST_RCPT_OTHER */\r
+ {\r
+ /* USBFS_RQST_RCPT_OTHER */\r
}\r
}\r
- else\r
- { /* requestHandled is initialized as FALSE by default */\r
- }\r
\r
return(requestHandled);\r
}\r
\r
-\r
#endif /* USER_SUPPLIED_AUDIO_HANDLER */\r
\r
\r
\r
/* `#END` */\r
\r
-#endif /* End USBFS_ENABLE_AUDIO_CLASS*/\r
+#endif /* USBFS_ENABLE_AUDIO_CLASS */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_audio.h\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
-* Header File for the USFS component. Contains prototypes and constant values.\r
+* Header File for the USBFS component. Contains prototypes and constant values.\r
+*\r
+* Related Document:\r
+* Universal Serial Bus Device Class Definition for Audio Devices Release 1.0\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#define USBFS_GET_MEM (0x85u)\r
#define USBFS_GET_STAT (0xFFu)\r
\r
-/* Endpoint Control Selectors (AUDIO Table A-19) */\r
+/* point Control Selectors (AUDIO Table A-19) */\r
#define USBFS_EP_CONTROL_UNDEFINED (0x00u)\r
#define USBFS_SAMPLING_FREQ_CONTROL (0x01u)\r
#define USBFS_PITCH_CONTROL (0x02u)\r
extern volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN];\r
extern volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN];\r
\r
-#endif /* End CY_USBFS_USBFS_audio_H */\r
+#endif /* CY_USBFS_USBFS_audio_H */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_boot.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* Boot loader API for USBFS Component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
(CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))\r
\r
\r
-/***************************************\r
-* Bootloader defines\r
-***************************************/\r
-\r
-#define USBFS_CyBtLdrStarttimer(X, T) {USBFS_universalTime = T * 10; X = 0u;}\r
-#define USBFS_CyBtLdrChecktimer(X) ((X++ < USBFS_universalTime) ? 1u : 0u)\r
-\r
-#define USBFS_BTLDR_OUT_EP (0x01u)\r
-#define USBFS_BTLDR_IN_EP (0x02u)\r
-\r
-\r
/***************************************\r
* Bootloader Variables\r
***************************************/\r
\r
-static uint16 USBFS_universalTime;\r
-static uint8 USBFS_started = 0u;\r
+static uint8 USBFS_started = 0u;\r
\r
\r
/*******************************************************************************\r
\r
/* USB component started, the correct enumeration will be checked in first Read operation */\r
USBFS_started = 1u;\r
-\r
}\r
\r
\r
* Resets the receive and transmit communication Buffers.\r
*\r
* Parameters:\r
-* None.\r
+* None\r
*\r
* Return:\r
-* None.\r
+* None\r
*\r
* Reentrant:\r
-* No.\r
+* No\r
*\r
*******************************************************************************/\r
void USBFS_CyBtldrCommReset(void) \r
* Returns the value that best describes the problem.\r
*\r
* Reentrant:\r
-* No.\r
+* No\r
*\r
*******************************************************************************/\r
-cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
+cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
\r
{\r
- uint16 time;\r
- cystatus status;\r
+ cystatus retCode;\r
+ uint16 timeoutMs;\r
+\r
+ timeoutMs = ((uint16) 10u * timeOut); /* Convert from 10mS check to number 1mS checks */\r
\r
/* Enable IN transfer */\r
USBFS_LoadInEP(USBFS_BTLDR_IN_EP, pData, USBFS_BTLDR_SIZEOF_READ_BUFFER);\r
\r
- /* Start a timer to wait on. */\r
- USBFS_CyBtLdrStarttimer(time, timeOut);\r
-\r
/* Wait for the master to read it. */\r
- while((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) && \\r
- USBFS_CyBtLdrChecktimer(time))\r
+ while ((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) &&\r
+ (0u != timeoutMs))\r
{\r
- CyDelay(1u); /* 1ms delay */\r
+ CyDelay(USBFS_BTLDR_WAIT_1_MS);\r
+ timeoutMs--;\r
}\r
\r
if (USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL)\r
{\r
- status = CYRET_TIMEOUT;\r
+ retCode = CYRET_TIMEOUT;\r
}\r
else\r
{\r
*count = size;\r
- status = CYRET_SUCCESS;\r
+ retCode = CYRET_SUCCESS;\r
}\r
\r
- return(status);\r
+ return(retCode);\r
}\r
\r
\r
* Returns the value that best describes the problem.\r
*\r
* Reentrant:\r
-* No.\r
+* No\r
*\r
*******************************************************************************/\r
-cystatus USBFS_CyBtldrCommRead(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
+cystatus USBFS_CyBtldrCommRead(uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL\r
\r
{\r
- cystatus status;\r
- uint16 time;\r
+ cystatus retCode;\r
+ uint16 timeoutMs;\r
+\r
+ timeoutMs = ((uint16) 10u * timeOut); /* Convert from 10mS check to number 1mS checks */\r
\r
- if(size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER)\r
+ if (size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER)\r
{\r
size = USBFS_BTLDR_SIZEOF_WRITE_BUFFER;\r
}\r
- /* Start a timer to wait on. */\r
- USBFS_CyBtLdrStarttimer(time, timeOut);\r
\r
/* Wait on enumeration in first time */\r
- if(USBFS_started)\r
+ if (0u != USBFS_started)\r
{\r
/* Wait for Device to enumerate */\r
- while(!USBFS_GetConfiguration() && USBFS_CyBtLdrChecktimer(time))\r
+ while ((0u ==USBFS_GetConfiguration()) && (0u != timeoutMs))\r
{\r
- CyDelay(1u); /* 1ms delay */\r
+ CyDelay(USBFS_BTLDR_WAIT_1_MS);\r
+ timeoutMs--;\r
}\r
+\r
/* Enable first OUT, if enumeration complete */\r
- if(USBFS_GetConfiguration())\r
+ if (0u != USBFS_GetConfiguration())\r
{\r
- USBFS_IsConfigurationChanged(); /* Clear configuration changes state status */\r
+ (void) USBFS_IsConfigurationChanged(); /* Clear configuration changes state status */\r
USBFS_CyBtldrCommReset();\r
USBFS_started = 0u;\r
}\r
}\r
else /* Check for configuration changes, has been done by Host */\r
{\r
- if(USBFS_IsConfigurationChanged() != 0u) /* Host could send double SET_INTERFACE request or RESET */\r
+ if (0u != USBFS_IsConfigurationChanged()) /* Host could send double SET_INTERFACE request or RESET */\r
{\r
- if(USBFS_GetConfiguration() != 0u) /* Init OUT endpoints when device reconfigured */\r
+ if (0u != USBFS_GetConfiguration()) /* Init OUT endpoints when device reconfigured */\r
{\r
USBFS_CyBtldrCommReset();\r
}\r
}\r
}\r
+\r
+ timeoutMs = ((uint16) 10u * timeOut); /* Re-arm timeout */\r
+\r
/* Wait on next packet */\r
while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \\r
- USBFS_CyBtLdrChecktimer(time))\r
+ (0u != timeoutMs))\r
{\r
- CyDelay(1u); /* 1ms delay */\r
+ CyDelay(USBFS_BTLDR_WAIT_1_MS);\r
+ timeoutMs--;\r
}\r
\r
/* OUT EP has completed */\r
if (USBFS_GetEPState(USBFS_BTLDR_OUT_EP) == USBFS_OUT_BUFFER_FULL)\r
{\r
*count = USBFS_ReadOutEP(USBFS_BTLDR_OUT_EP, pData, size);\r
- status = CYRET_SUCCESS;\r
+ retCode = CYRET_SUCCESS;\r
}\r
else\r
{\r
*count = 0u;\r
- status = CYRET_TIMEOUT;\r
+ retCode = CYRET_TIMEOUT;\r
}\r
- return(status);\r
+\r
+ return(retCode);\r
}\r
\r
-#endif /* End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */\r
+#endif /* CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_cdc.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
-* USB HID Class request handler.\r
+* USB CDC class request handler.\r
*\r
-* Note:\r
+* Related Document:\r
+* Universal Serial Bus Class Definitions for Communication Devices Version 1.1\r
*\r
********************************************************************************\r
-* Copyright 2012-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2012-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
* CDC Variables\r
***************************************/\r
\r
-volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE];\r
+volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE] =\r
+{\r
+ 0x00u, 0xC2u, 0x01u, 0x00u, /* Data terminal rate 115200 */\r
+ 0x00u, /* 1 Stop bit */\r
+ 0x00u, /* None parity */\r
+ 0x08u /* 8 data bits */\r
+};\r
volatile uint8 USBFS_lineChanged;\r
volatile uint16 USBFS_lineControlBitmap;\r
volatile uint8 USBFS_cdc_data_in_ep;\r
/***************************************\r
* Static Function Prototypes\r
***************************************/\r
-static uint16 USBFS_StrLen(const char8 string[]) ;\r
+#if (USBFS_ENABLE_CDC_CLASS_API != 0u)\r
+ static uint16 USBFS_StrLen(const char8 string[]) ;\r
+#endif /* (USBFS_ENABLE_CDC_CLASS_API != 0u) */\r
\r
\r
/***************************************\r
***************************************/\r
#if (USBFS_ENABLE_CDC_CLASS_API != 0u)\r
\r
-\r
/*******************************************************************************\r
* Function Name: USBFS_CDC_Init\r
********************************************************************************\r
********************************************************************************\r
*\r
* Summary:\r
- * Sends a specified number of bytes from the location specified by a\r
- * pointer to the PC.\r
+ * This function sends a specified number of bytes from the location specified\r
+ * by a pointer to the PC. The USBFS_CDCIsReady() function should be\r
+ * called before sending new data, to be sure that the previous data has\r
+ * finished sending.\r
+ * If the last sent packet is less than maximum packet size the USB transfer\r
+ * of this short packet will identify the end of the segment. If the last sent\r
+ * packet is exactly maximum packet size, it shall be followed by a zero-length\r
+ * packet (which is a short packet) to assure the end of segment is properly\r
+ * identified. To send zero-length packet, use USBFS_PutData() API\r
+ * with length parameter set to zero.\r
*\r
* Parameters:\r
* pData: pointer to the buffer containing data to be sent.\r
* length: Specifies the number of bytes to send from the pData\r
* buffer. Maximum length will be limited by the maximum packet\r
- * size for the endpoint.\r
+ * size for the endpoint. Data will be lost if length is greater than Max\r
+ * Packet Size.\r
*\r
* Return:\r
* None.\r
********************************************************************************\r
*\r
* Summary:\r
- * Sends a null terminated string to the PC.\r
+ * This function sends a null terminated string to the PC. This function will\r
+ * block if there is not enough memory to place the whole string. It will block\r
+ * until the entire string has been written to the transmit buffer.\r
+ * The USBUART_CDCIsReady() function should be called before sending data with\r
+ * a new call to USBFS_PutString(), to be sure that the previous data\r
+ * has finished sending.\r
*\r
* Parameters:\r
- * string: pointer to the string to be sent to the PC\r
+ * string: pointer to the string to be sent to the PC.\r
*\r
* Return:\r
* None.\r
* Reentrant:\r
* No.\r
*\r
- * Theory:\r
- * This function will block if there is not enough memory to place the whole\r
- * string, it will block until the entire string has been written to the\r
- * transmit buffer.\r
- *\r
*******************************************************************************/\r
void USBFS_PutString(const char8 string[]) \r
{\r
- uint16 str_length;\r
- uint16 send_length;\r
- uint16 buf_index = 0u;\r
+ uint16 strLength;\r
+ uint16 sendLength;\r
+ uint16 bufIndex = 0u;\r
\r
/* Get length of the null terminated string */\r
- str_length = USBFS_StrLen(string);\r
+ strLength = USBFS_StrLen(string);\r
do\r
{\r
/* Limits length to maximum packet size for the EP */\r
- send_length = (str_length > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ?\r
- USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : str_length;\r
+ sendLength = (strLength > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ?\r
+ USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : strLength;\r
/* Enable IN transfer */\r
- USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[buf_index], send_length);\r
- str_length -= send_length;\r
+ USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[bufIndex], sendLength);\r
+ strLength -= sendLength;\r
\r
- /* If more data are present to send */\r
- if(str_length > 0u)\r
+ /* If more data are present to send or full packet was sent */\r
+ if((strLength > 0u) || (sendLength == USBFS_EP[USBFS_cdc_data_in_ep].bufferSize))\r
{\r
- buf_index += send_length;\r
+ bufIndex += sendLength;\r
/* Wait for the Host to read it. */\r
while(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState ==\r
USBFS_IN_BUFFER_FULL)\r
{\r
;\r
}\r
+ /* If the last sent packet is exactly maximum packet size,\r
+ * it shall be followed by a zero-length packet to assure the\r
+ * end of segment is properly identified by the terminal.\r
+ */\r
+ if(strLength == 0u)\r
+ {\r
+ USBFS_LoadInEP(USBFS_cdc_data_in_ep, NULL, 0u);\r
+ }\r
}\r
- }while(str_length > 0u);\r
+ }while(strLength > 0u);\r
}\r
\r
\r
*\r
* Summary:\r
* This function returns the number of bytes that were received from the PC.\r
+ * The returned length value should be passed to USBFS_GetData() as\r
+ * a parameter to read all received data. If all of the received data is not\r
+ * read at one time by the USBFS_GetData() API, the unread data will\r
+ * be lost.\r
*\r
* Parameters:\r
* None.\r
*\r
* Return:\r
- * Returns the number of received bytes.\r
+ * Returns the number of received bytes. The maximum amount of received data at\r
+ * a time is limited by the maximum packet size for the endpoint.\r
*\r
* Global variables:\r
* USBFS_cdc_data_out_ep: CDC OUT endpoint number used.\r
*******************************************************************************/\r
uint16 USBFS_GetCount(void) \r
{\r
- uint16 bytesCount = 0u;\r
+ uint16 bytesCount;\r
\r
if (USBFS_EP[USBFS_cdc_data_out_ep].apiEpState == USBFS_OUT_BUFFER_FULL)\r
{\r
bytesCount = USBFS_GetEPCount(USBFS_cdc_data_out_ep);\r
}\r
+ else\r
+ {\r
+ bytesCount = 0u;\r
+ }\r
\r
return(bytesCount);\r
}\r
*\r
* Summary:\r
* Returns a nonzero value if the component received data or received\r
- * zero-length packet. The GetAll() or GetData() API should be called to read\r
- * data from the buffer and re-init OUT endpoint even when zero-length packet\r
- * received.\r
+ * zero-length packet. The USBFS_GetAll() or\r
+ * USBFS_GetData() API should be called to read data from the buffer\r
+ * and re-init OUT endpoint even when zero-length packet received.\r
*\r
* Parameters:\r
* None.\r
********************************************************************************\r
*\r
* Summary:\r
- * Returns a nonzero value if the component is ready to send more data to the\r
- * PC. Otherwise returns zero. Should be called before sending new data to\r
- * ensure the previous data has finished sending.This function returns the\r
- * number of bytes that were received from the PC.\r
+ * This function returns a nonzero value if the component is ready to send more\r
+ * data to the PC; otherwise, it returns zero. The function should be called\r
+ * before sending new data when using any of the following APIs:\r
+ * USBFS_PutData(),USBFS_PutString(),\r
+ * USBFS_PutChar or USBFS_PutCRLF(),\r
+ * to be sure that the previous data has finished sending.\r
*\r
* Parameters:\r
* None.\r
*\r
* Return:\r
- * If the buffer can accept new data then this function returns a nonzero value.\r
- * Otherwise zero is returned.\r
+ * If the buffer can accept new data, this function returns a nonzero value.\r
+ * Otherwise, it returns zero.\r
*\r
* Global variables:\r
* USBFS_cdc_data_in_ep: CDC IN endpoint number used.\r
********************************************************************************\r
*\r
* Summary:\r
- * Gets a specified number of bytes from the input buffer and places it in a\r
- * data array specified by the passed pointer.\r
- * USBFS_DataIsReady() API should be called before, to be sure\r
- * that data is received from the Host.\r
+ * This function gets a specified number of bytes from the input buffer and\r
+ * places them in a data array specified by the passed pointer.\r
+ * The USBFS_DataIsReady() API should be called first, to be sure\r
+ * that data is received from the host. If all received data will not be read at\r
+ * once, the unread data will be lost. The USBFS_GetData() API should\r
+ * be called to get the number of bytes that were received.\r
*\r
* Parameters:\r
* pData: Pointer to the data array where data will be placed.\r
********************************************************************************\r
*\r
* Summary:\r
- * Reads one byte of received data from the buffer.\r
+ * This function reads one byte of received data from the buffer. If more than\r
+ * one byte has been received from the host, the rest of the data will be lost.\r
*\r
* Parameters:\r
* None.\r
********************************************************************************\r
*\r
* Summary:\r
- * This function returns clear on read status of the line.\r
+ * This function returns clear on read status of the line. It returns not zero\r
+ * value when the host sends updated coding or control information to the\r
+ * device. The USBFS_GetDTERate(), USBFS_GetCharFormat()\r
+ * or USBFS_GetParityType() or USBFS_GetDataBits() API\r
+ * should be called to read data coding information.\r
+ * The USBFS_GetLineControl() API should be called to read line\r
+ * control information.\r
*\r
* Parameters:\r
* None.\r
*\r
* Return:\r
- * If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE request received then not\r
- * zero value returned. Otherwise zero is returned.\r
+ * If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE requests are received, it\r
+ * returns a nonzero value. Otherwise, it returns zero.\r
*\r
* Global variables:\r
- * USBFS_transferState - it is checked to be sure then OUT data\r
+ * USBFS_transferState: it is checked to be sure then OUT data\r
* phase has been complete, and data written to the lineCoding or Control\r
* Bitmap buffer.\r
* USBFS_lineChanged: used as a flag to be aware that Host has been\r
return(USBFS_lineControlBitmap);\r
}\r
\r
-#endif /* End USBFS_ENABLE_CDC_CLASS_API*/\r
+#endif /* USBFS_ENABLE_CDC_CLASS_API*/\r
\r
\r
/*******************************************************************************\r
\r
/* `#END` */\r
\r
-#endif /* End USBFS_ENABLE_CDC_CLASS*/\r
+#endif /* USBFS_ENABLE_CDC_CLASS*/\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_cdc.h\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
-* Header File for the USFS component.\r
+* Header File for the USBFS component.\r
* Contains CDC class prototypes and constant values.\r
*\r
+* Related Document:\r
+* Universal Serial Bus Class Definitions for Communication Devices Version 1.1\r
+*\r
********************************************************************************\r
-* Copyright 2012-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2012-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
uint8 USBFS_GetParityType(void) ;\r
uint8 USBFS_GetDataBits(void) ;\r
uint16 USBFS_GetLineControl(void) ;\r
-#endif /* End USBFS_ENABLE_CDC_CLASS_API*/\r
+#endif /* USBFS_ENABLE_CDC_CLASS_API */\r
\r
\r
/***************************************\r
extern volatile uint8 USBFS_cdc_data_in_ep;\r
extern volatile uint8 USBFS_cdc_data_out_ep;\r
\r
-#endif /* End CY_USBFS_USBFS_cdc_H */\r
+#endif /* CY_USBFS_USBFS_cdc_H */\r
\r
\r
/* [] END OF FILE */\r
;******************************************************************************\r
; File Name: USBFS_cdc.inf\r
-; Version 2.60\r
+; Version 2.80\r
;\r
; Description:\r
; Windows USB CDC setup file for USBUART Device.\r
;\r
;******************************************************************************\r
-; Copyright 2007-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; Copyright 2007-2014, Cypress Semiconductor Corporation. All rights reserved.\r
; You may use this file only in accordance with the license, terms, conditions,\r
; disclaimers, and limitations in the end user license agreement accompanying\r
; the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: USBFS_cls.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* USB Class request handler.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
break;\r
case USBFS_RQST_RCPT_EP: /* Class-specific request directed to the endpoint */\r
/* Find related interface to the endpoint, wIndexLo contain EP number */\r
- interfaceNumber =\r
- USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].interface;\r
+ interfaceNumber = USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) &\r
+ USBFS_DIR_UNUSED].interface;\r
break;\r
default: /* RequestHandled is initialized as FALSE by default */\r
break;\r
case USBFS_CLASS_AUDIO:\r
#if defined(USBFS_ENABLE_AUDIO_CLASS)\r
requestHandled = USBFS_DispatchAUDIOClassRqst();\r
- #endif /* USBFS_ENABLE_HID_CLASS */\r
+ #endif /* USBFS_CLASS_AUDIO */\r
break;\r
case USBFS_CLASS_CDC:\r
#if defined(USBFS_ENABLE_CDC_CLASS)\r
/*******************************************************************************\r
* File Name: USBFS_descr.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* USB descriptors and storage.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
/*****************************************************************************\r
* User supplied descriptors. If you want to specify your own descriptors,\r
-* remove the comments around the define USER_SUPPLIED_DESCRIPTORS below and\r
-* add your descriptors.\r
+* define USER_SUPPLIED_DESCRIPTORS below and add your descriptors.\r
*****************************************************************************/\r
/* `#START USER_DESCRIPTORS_DECLARATIONS` Place your declaration here */\r
\r
/*******************************************************************************\r
* File Name: USBFS_drv.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* Endpoint 0 Driver for the USBFS Component.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: USBFS_episr.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* Data endpoint Interrupt Service Routines\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
#include "USBFS.h"\r
#include "USBFS_pvt.h"\r
-#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)\r
+#if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u))\r
#include "USBFS_midi.h"\r
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/\r
+#endif /* (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)) */\r
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ #include "USBFS_EP8_DMA_Done_SR.h"\r
+ #include "USBFS_EP17_DMA_Done_SR.h"\r
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
\r
\r
/***************************************\r
******************************************************************************/\r
CY_ISR(USBFS_EP_1_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
uint8 int_en;\r
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
int_en = EA;\r
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) &\r
(uint8)~USBFS_SIE_EP_INT_EP1_MASK);\r
\r
- #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT )\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP1)\r
{\r
USBFS_MIDI_OUT_EP_Service();\r
}\r
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
/* `#START EP1_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 )\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
EA = int_en;\r
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
}\r
\r
-#endif /* End USBFS_EP1_ISR_REMOVE */\r
+#endif /* USBFS_EP1_ISR_REMOVE */\r
\r
\r
#if(USBFS_EP2_ISR_REMOVE == 0u)\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_2_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
uint8 int_en;\r
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 )\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
int_en = EA;\r
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
& (uint8)~USBFS_SIE_EP_INT_EP2_MASK);\r
\r
- #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT )\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP2)\r
{\r
USBFS_MIDI_OUT_EP_Service();\r
}\r
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
/* `#START EP2_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
EA = int_en;\r
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
}\r
\r
-#endif /* End USBFS_EP2_ISR_REMOVE */\r
+#endif /* USBFS_EP2_ISR_REMOVE */\r
\r
\r
#if(USBFS_EP3_ISR_REMOVE == 0u)\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_3_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
uint8 int_en;\r
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */\r
\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
int_en = EA;\r
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
& (uint8)~USBFS_SIE_EP_INT_EP3_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP3)\r
{\r
USBFS_MIDI_OUT_EP_Service();\r
}\r
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
/* `#START EP3_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
EA = int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
}\r
\r
-#endif /* End USBFS_EP3_ISR_REMOVE */\r
+#endif /* USBFS_EP3_ISR_REMOVE */\r
\r
\r
#if(USBFS_EP4_ISR_REMOVE == 0u)\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_4_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
uint8 int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
int_en = EA;\r
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
& (uint8)~USBFS_SIE_EP_INT_EP4_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP4)\r
{\r
USBFS_MIDI_OUT_EP_Service();\r
}\r
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
/* `#START EP4_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
EA = int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
}\r
\r
-#endif /* End USBFS_EP4_ISR_REMOVE */\r
+#endif /* USBFS_EP4_ISR_REMOVE */\r
\r
\r
#if(USBFS_EP5_ISR_REMOVE == 0u)\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_5_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
uint8 int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
int_en = EA;\r
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
& (uint8)~USBFS_SIE_EP_INT_EP5_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP5)\r
{\r
USBFS_MIDI_OUT_EP_Service();\r
}\r
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
/* `#START EP5_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
EA = int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
}\r
-#endif /* End USBFS_EP5_ISR_REMOVE */\r
+#endif /* USBFS_EP5_ISR_REMOVE */\r
\r
\r
#if(USBFS_EP6_ISR_REMOVE == 0u)\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_6_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
uint8 int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
int_en = EA;\r
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
& (uint8)~USBFS_SIE_EP_INT_EP6_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP6)\r
{\r
USBFS_MIDI_OUT_EP_Service();\r
}\r
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
/* `#START EP6_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
EA = int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
}\r
\r
-#endif /* End USBFS_EP6_ISR_REMOVE */\r
+#endif /* USBFS_EP6_ISR_REMOVE */\r
\r
\r
#if(USBFS_EP7_ISR_REMOVE == 0u)\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_7_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
uint8 int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
int_en = EA;\r
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
& (uint8)~USBFS_SIE_EP_INT_EP7_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP7)\r
{\r
USBFS_MIDI_OUT_EP_Service();\r
}\r
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
/* `#START EP7_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
EA = int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
}\r
\r
-#endif /* End USBFS_EP7_ISR_REMOVE */\r
+#endif /* USBFS_EP7_ISR_REMOVE */\r
\r
\r
#if(USBFS_EP8_ISR_REMOVE == 0u)\r
*******************************************************************************/\r
CY_ISR(USBFS_EP_8_ISR)\r
{\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
uint8 int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
int_en = EA;\r
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)\r
& (uint8)~USBFS_SIE_EP_INT_EP8_MASK);\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT)\r
if(USBFS_midi_out_ep == USBFS_EP8)\r
{\r
USBFS_MIDI_OUT_EP_Service();\r
}\r
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */\r
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */\r
\r
/* `#START EP8_END_USER_CODE` Place your code here */\r
\r
/* `#END` */\r
\r
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \\r
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)\r
EA = int_en;\r
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */\r
}\r
\r
-#endif /* End USBFS_EP8_ISR_REMOVE */\r
+#endif /* USBFS_EP8_ISR_REMOVE */\r
\r
\r
/*******************************************************************************\r
/* Clear Data ready status */\r
*(reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) &=\r
(uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+ #if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ /* Setup common area DMA with rest of the data */\r
+ if(USBFS_inLength[ep] > USBFS_DMA_BYTES_PER_BURST)\r
+ {\r
+ USBFS_LoadNextInEP(ep, 0u);\r
+ }\r
+ else\r
+ {\r
+ USBFS_inBufFull[ep] = 1u;\r
+ }\r
+ #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
/* Write the Mode register */\r
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), USBFS_EP[ep].epMode);\r
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN)\r
{ /* Clear MIDI input pointer */\r
USBFS_midiInPointer = 0u;\r
}\r
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/\r
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
}\r
}\r
/* (re)arm Out EP only for mode2 */\r
USBFS_EP[ep].epMode);\r
}\r
}\r
- #endif /* End USBFS_EP_MM */\r
+ #endif /* USBFS_EP_MM */\r
\r
/* `#START ARB_USER_CODE` Place your code here for handle Buffer Underflow/Overflow */\r
\r
/* `#END` */\r
}\r
\r
-#endif /* End USBFS_EP_MM */\r
+#endif /* USBFS_EP_MM */\r
+\r
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ /******************************************************************************\r
+ * Function Name: USBFS_EP_DMA_DONE_ISR\r
+ *******************************************************************************\r
+ *\r
+ * Summary:\r
+ * Endpoint 1 DMA Done Interrupt Service Routine\r
+ *\r
+ * Parameters:\r
+ * None.\r
+ *\r
+ * Return:\r
+ * None.\r
+ *\r
+ ******************************************************************************/\r
+ CY_ISR(USBFS_EP_DMA_DONE_ISR)\r
+ {\r
+ uint8 int8Status;\r
+ uint8 int17Status;\r
+ uint8 ep_status;\r
+ uint8 ep = USBFS_EP1;\r
+ uint8 ptr = 0u;\r
+\r
+ /* `#START EP_DMA_DONE_BEGIN_USER_CODE` Place your code here */\r
+\r
+ /* `#END` */\r
+\r
+ /* Read clear on read status register with the EP source of interrupt */\r
+ int17Status = USBFS_EP17_DMA_Done_SR_Read() & USBFS_EP17_SR_MASK;\r
+ int8Status = USBFS_EP8_DMA_Done_SR_Read() & USBFS_EP8_SR_MASK;\r
+\r
+ while(int8Status != 0u)\r
+ {\r
+ while(int17Status != 0u)\r
+ {\r
+ if((int17Status & 1u) != 0u) /* If EpX interrupt present */\r
+ {\r
+ /* Read Endpoint Status Register */\r
+ ep_status = CY_GET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr));\r
+ if( ((ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL) == 0u) &&\r
+ (USBFS_inBufFull[ep] == 0u))\r
+ {\r
+ /* `#START EP_DMA_DONE_USER_CODE` Place your code here */\r
+\r
+ /* `#END` */\r
+\r
+ CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ptr), 0x00u);\r
+ /* repeat 2 last bytes to prefetch endpoint area */\r
+ CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ptr),\r
+ USBFS_DMA_BYTES_PER_BURST * ep - USBFS_DMA_BYTES_REPEAT);\r
+ USBFS_LoadNextInEP(ep, 1);\r
+ /* Set Data ready status, This will generate DMA request */\r
+ * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;\r
+ }\r
+ }\r
+ ptr += USBFS_EPX_CNTX_ADDR_OFFSET; /* prepare pointer for next EP */\r
+ ep++;\r
+ int17Status >>= 1u;\r
+ }\r
+ int8Status >>= 1u;\r
+ if(int8Status != 0u)\r
+ {\r
+ /* Prepare pointer for EP8 */\r
+ ptr = ((USBFS_EP8 - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
+ ep = USBFS_EP8;\r
+ int17Status = int8Status & 0x01u;\r
+ }\r
+ }\r
+\r
+ /* `#START EP_DMA_DONE_END_USER_CODE` Place your code here */\r
+\r
+ /* `#END` */\r
+ }\r
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_hid.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* USB HID Class request handler.\r
*\r
+* Related Document:\r
+* Device Class Definition for Human Interface Devices (HID) Version 1.11\r
+*\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
/* `#END` */\r
\r
-#endif /* End USBFS_ENABLE_HID_CLASS */\r
+#endif /* USBFS_ENABLE_HID_CLASS */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_hid.h\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
-* Header File for the USFS component. Contains prototypes and constant values.\r
+* Header File for the USBFS component. Contains prototypes and constant values.\r
+*\r
+* Related Document:\r
+* Device Class Definition for Human Interface Devices (HID) Version 1.11\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#define USBFS_HID_GET_REPORT_OUTPUT (0x02u)\r
#define USBFS_HID_GET_REPORT_FEATURE (0x03u)\r
\r
-#endif /* End CY_USBFS_USBFS_hid_H */\r
+#endif /* CY_USBFS_USBFS_hid_H */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_midi.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* MIDI Streaming request handler.\r
* This file contains routines for sending and receiving MIDI\r
* messages, and handles running status in both directions.\r
*\r
+* Related Document:\r
+* Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0\r
+* MIDI 1.0 Detailed Specification Document Version 4.2\r
+*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */\r
#else\r
volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */\r
- #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */\r
+ #endif /* (USBFS_MIDI_IN_BUFF_SIZE >= 256) */\r
volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */\r
uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */\r
-#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */\r
+#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
\r
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */\r
uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */\r
-#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */\r
+#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
static USBFS_MIDI_RX_STATUS USBFS_MIDI1_Event; /* MIDI RX status structure */\r
static USBFS_MIDI_RX_STATUS USBFS_MIDI2_Event; /* MIDI RX status structure */\r
static volatile uint8 USBFS_MIDI2_TxRunStat; /* MIDI Output running status */\r
volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
\r
/***************************************\r
{\r
#if (USBFS_MIDI_IN_BUFF_SIZE > 0)\r
USBFS_midiInPointer = 0u;\r
- #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */\r
+ #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
#if (USBFS_MIDI_IN_BUFF_SIZE > 0)\r
/* Init DMA configurations for IN EP*/\r
USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer,\r
USBFS_MIDI_IN_BUFF_SIZE);\r
- \r
- #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */\r
+\r
+ #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */\r
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
/* Init DMA configurations for OUT EP*/\r
(void)USBFS_ReadOutEP(USBFS_midi_out_ep, USBFS_midiOutBuffer,\r
USBFS_MIDI_OUT_BUFF_SIZE);\r
- #endif /*USBFS_MIDI_OUT_BUFF_SIZE > 0 */\r
- #endif /* End USBFS__EP_DMAAUTO */\r
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
+ #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */\r
\r
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
USBFS_EnableOutEP(USBFS_midi_out_ep);\r
- #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */\r
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */\r
\r
/* Initialize the MIDI port(s) */\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
USBFS_MIDI_Init();\r
- #endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
}\r
\r
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)\r
#else\r
uint8 outLength;\r
uint8 outPointer;\r
- #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >=256 */\r
+ #endif /* USBFS_MIDI_OUT_BUFF_SIZE >=256 */\r
\r
uint8 dmaState = 0u;\r
\r
/* Service the USB MIDI output endpoint */\r
if (USBFS_GetEPState(USBFS_midi_out_ep) == USBFS_OUT_BUFFER_FULL)\r
{\r
- #if USBFS_MIDI_OUT_BUFF_SIZE >= 256\r
+ #if(USBFS_MIDI_OUT_BUFF_SIZE >= 256)\r
outLength = USBFS_GetEPCount(USBFS_midi_out_ep);\r
#else\r
outLength = (uint8)USBFS_GetEPCount(USBFS_midi_out_ep);\r
- #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */\r
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */\r
+\r
#if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
- #if USBFS_MIDI_OUT_BUFF_SIZE >= 256\r
+ #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256)\r
outLength = USBFS_ReadOutEP(USBFS_midi_out_ep,\r
USBFS_midiOutBuffer, outLength);\r
#else\r
outLength = (uint8)USBFS_ReadOutEP(USBFS_midi_out_ep,\r
USBFS_midiOutBuffer, (uint16)outLength);\r
- #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */\r
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */\r
+\r
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
do /* wait for DMA transfer complete */\r
{\r
- (void)CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState);\r
- }while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u);\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ (void) CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState);\r
+ }\r
+ while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u);\r
+ #endif /* (USBFS_EP_MM == USBFS__EP_DMAMANUAL) */\r
+\r
+ #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */\r
+\r
if(dmaState != 0u)\r
{\r
/* Suppress compiler warning */\r
}\r
+\r
if (outLength >= USBFS_EVENT_LENGTH)\r
{\r
outPointer = 0u;\r
{\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
USBFS_MIDI2_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]);\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
}\r
else\r
{\r
\r
/* `#END` */\r
}\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
/* Process any local MIDI output functions */\r
USBFS_callbackLocalMidiEvent(\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
/* Enable Out EP*/\r
USBFS_EnableOutEP(USBFS_midi_out_ep);\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */\r
}\r
}\r
\r
#else /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
/* rearm IN EP */\r
USBFS_LoadInEP(USBFS_midi_in_ep, NULL, (uint16)USBFS_midiInPointer);\r
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO*/\r
+ #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */\r
\r
/* Clear the midiInPointer. For DMA mode, clear this pointer in the ARB ISR when data are moved by DMA */\r
#if(USBFS_EP_MM == USBFS__EP_MANUAL)\r
USBFS_midiInPointer = 0u;\r
- #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */\r
+ #endif /* (USBFS_EP_MM == USBFS__EP_MANUAL) */\r
}\r
}\r
}\r
uint8 m2 = 0u;\r
do\r
{\r
- if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))\r
+ if (USBFS_midiInPointer <=\r
+ (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))\r
{\r
/* Check MIDI1 input port for a complete event */\r
m1 = USBFS_MIDI1_GetEvent();\r
}\r
\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
- if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))\r
+ if (USBFS_midiInPointer <=\r
+ (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))\r
{\r
/* Check MIDI2 input port for a complete event */\r
m2 = USBFS_MIDI2_GetEvent();\r
USBFS_MIDI2_Event.size, USBFS_MIDI_CABLE_01);\r
}\r
}\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
\r
- }while( (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))\r
- && ((m1 != 0u) || (m2 != 0u)) );\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ }while( (USBFS_midiInPointer <=\r
+ (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) &&\r
+ ((m1 != 0u) || (m2 != 0u)) );\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
/* Service the USB MIDI input endpoint */\r
USBFS_MIDI_IN_EP_Service();\r
MIDI1_UART_DisableRxInt();\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
MIDI2_UART_DisableRxInt();\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
if (USBFS_midiInPointer >\r
(USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))\r
(USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))\r
{\r
USBFS_MIDI_IN_EP_Service();\r
- if (USBFS_midiInPointer >\r
- (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))\r
+ if(USBFS_midiInPointer >\r
+ (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))\r
{\r
/* Error condition. HOST is not ready to receive this packet. */\r
retError = USBFS_TRUE;\r
break;\r
}\r
}\r
- }while(ic > USBFS_EVENT_BYTE3);\r
+ }\r
+ while(ic > USBFS_EVENT_BYTE3);\r
\r
if(retError == USBFS_FALSE)\r
{\r
MIDI1_UART_EnableRxInt();\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
MIDI2_UART_EnableRxInt();\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
return (retError);\r
}\r
/* Change the priority of the UART TX interrupt */\r
CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM);\r
CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM);\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/\r
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/\r
\r
/* `#START MIDI_INIT_CUSTOM` Init other extended UARTs here */\r
\r
uint8 rxData;\r
#if (MIDI1_UART_RXBUFFERSIZE >= 256u)\r
uint16 rxBufferRead;\r
- #if CY_PSOC3 /* This local variable is required only for PSOC3 and large buffer */\r
+ #if (CY_PSOC3) /* This local variable is required only for PSOC3 and large buffer */\r
uint16 rxBufferWrite;\r
- #endif /* end CY_PSOC3 */\r
+ #endif /* (CY_PSOC3) */\r
#else\r
uint8 rxBufferRead;\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* (MIDI1_UART_RXBUFFERSIZE >= 256u) */\r
+\r
uint8 rxBufferLoopDetect;\r
/* Read buffer loop condition to the local variable */\r
rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect;\r
/* Protect variables that could change on interrupt by disabling Rx interrupt.*/\r
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntDisable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
rxBufferRead = MIDI1_UART_rxBufferRead;\r
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
rxBufferWrite = MIDI1_UART_rxBufferWrite;\r
CyIntEnable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
\r
/* Stay here until either the buffer is empty or we have a complete message\r
* in the message buffer. Note that we must use a temporary buffer pointer\r
while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )\r
#else\r
while ( ((rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */\r
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
{\r
rxData = MIDI1_UART_rxBuffer[rxBufferRead];\r
/* Increment pointer with a wrap */\r
MIDI1_UART_rxBufferLoopDetect = 0u;\r
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntDisable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */\r
MIDI1_UART_rxBufferRead = rxBufferRead;\r
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntEnable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */\r
}\r
\r
msgRtn = USBFS_ProcessMidiIn(rxData,\r
*/\r
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntDisable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
MIDI1_UART_rxBufferRead = rxBufferRead;\r
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntEnable(MIDI1_UART_RX_VECT_NUM);\r
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
}\r
\r
return (msgRtn);\r
/* `#END` */\r
}\r
\r
+\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
\r
\r
uint8 rxData;\r
#if (MIDI2_UART_RXBUFFERSIZE >= 256u)\r
uint16 rxBufferRead;\r
- #if CY_PSOC3 /* This local variable required only for PSOC3 and large buffer */\r
+ #if (CY_PSOC3) /* This local variable required only for PSOC3 and large buffer */\r
uint16 rxBufferWrite;\r
- #endif /* end CY_PSOC3 */\r
+ #endif /* (CY_PSOC3) */\r
#else\r
uint8 rxBufferRead;\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* (MIDI2_UART_RXBUFFERSIZE >= 256) */\r
+\r
uint8 rxBufferLoopDetect;\r
/* Read buffer loop condition to the local variable */\r
rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect;\r
/* Protect variables that could change on interrupt by disabling Rx interrupt.*/\r
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntDisable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
rxBufferRead = MIDI2_UART_rxBufferRead;\r
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
rxBufferWrite = MIDI2_UART_rxBufferWrite;\r
CyIntEnable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
\r
/* Stay here until either the buffer is empty or we have a complete message\r
* in the message buffer. Note that we must use a temporary output pointer to\r
while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )\r
#else\r
while ( ((rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
{\r
rxData = MIDI2_UART_rxBuffer[rxBufferRead];\r
rxBufferRead++;\r
MIDI2_UART_rxBufferLoopDetect = 0u;\r
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntDisable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
MIDI2_UART_rxBufferRead = rxBufferRead;\r
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntEnable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
}\r
\r
msgRtn = USBFS_ProcessMidiIn(rxData,\r
*/\r
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntDisable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
MIDI2_UART_rxBufferRead = rxBufferRead;\r
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))\r
CyIntEnable(MIDI2_UART_RX_VECT_NUM);\r
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */\r
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */\r
}\r
\r
return (msgRtn);\r
\r
/* `#END` */\r
}\r
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */\r
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */\r
\r
-#endif /* End (USBFS_ENABLE_MIDI_API != 0u) */\r
+#endif /* (USBFS_ENABLE_MIDI_API != 0u) */\r
\r
\r
/* `#START MIDI_FUNCTIONS` Place any additional functions here */\r
\r
/* `#END` */\r
\r
-#endif /* End defined(USBFS_ENABLE_MIDI_STREAMING) */\r
+#endif /* defined(USBFS_ENABLE_MIDI_STREAMING) */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_midi.h\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* Header File for the USBFS MIDI module.\r
* Contains prototypes and constant values.\r
*\r
+* Related Document:\r
+* Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0\r
+* MIDI 1.0 Detailed Specification Document Version 4.2\r
+*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
\r
/***************************************\r
-* Data Struct Definition\r
+* Data Structure Definition\r
***************************************/\r
\r
/* The following structure is used to hold status information for\r
#define USBFS_CUSTOM_UART_TX_PRIOR_NUM (0x04u)\r
#define USBFS_CUSTOM_UART_RX_PRIOR_NUM (0x02u)\r
\r
-#define USBFS_ISR_SERVICE_MIDI_OUT \\r
+#define USBFS_ISR_SERVICE_MIDI_OUT \\r
( (USBFS_ENABLE_MIDI_API != 0u) && \\r
- (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO) )\r
+ (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO))\r
#define USBFS_ISR_SERVICE_MIDI_IN \\r
( (USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_IN_BUFF_SIZE > 0) )\r
\r
+\r
/***************************************\r
* External function references\r
***************************************/\r
\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)\r
#include "MIDI1_UART.h"\r
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
#include "MIDI2_UART.h"\r
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
+#endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
#include <CyDmac.h>\r
-#endif /* End USBFS_EP_MM */\r
+#endif /* USBFS_EP_MM */\r
\r
\r
/***************************************\r
uint8 USBFS_MIDI2_GetEvent(void) ;\r
void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[])\r
;\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
+#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
\r
\r
/***************************************\r
extern volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */\r
#else\r
extern volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */\r
- #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */\r
+ #endif /* USBFS_MIDI_IN_BUFF_SIZE >=256 */\r
extern volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */\r
extern uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */\r
#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */\r
extern volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */\r
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)\r
extern volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */\r
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */\r
+#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */\r
\r
#endif /* USBFS_ENABLE_MIDI_STREAMING */\r
\r
\r
-#endif /* End CY_USBFS_USBFS_midi_H */\r
+#endif /* CY_USBFS_USBFS_midi_H */\r
\r
\r
/* [] END OF FILE */\r
/*******************************************************************************\r
* File Name: USBFS_pm.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* This file provides Suspend/Resume APIs functionality.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
#if(USBFS_DP_ISR_REMOVE == 0u)\r
\r
-\r
/*******************************************************************************\r
* Function Name: USBFS_DP_Interrupt\r
********************************************************************************\r
********************************************************************************\r
*\r
* Summary:\r
-* This function disables the USBFS block and prepares for power donwn mode.\r
+* This function disables the USBFS block and prepares for power down mode.\r
*\r
* Parameters:\r
* None.\r
\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */\r
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
/* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */\r
USBFS_USBIO_CR0_REG &= (uint8)~USBFS_USBIO_CR0_TEN;\r
/* Disable the SIE */\r
USBFS_CR0_REG &= (uint8)~USBFS_CR0_ENABLE;\r
\r
- CyDelayUs(0u); /*~50ns delay */\r
+ CyDelayUs(0u); /* ~50ns delay */\r
/* Store mode and Disable VRegulator*/\r
USBFS_backup.mode = USBFS_CR1_REG & USBFS_CR1_REG_ENABLE;\r
USBFS_CR1_REG &= (uint8)~USBFS_CR1_REG_ENABLE;\r
{\r
USBFS_backup.enableState = 0u;\r
}\r
+\r
CyExitCriticalSection(enableInterrupts);\r
\r
/* Set the DP Interrupt for wake-up from sleep mode. */\r
#if(USBFS_DP_ISR_REMOVE == 0u)\r
- (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR);\r
+ (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR);\r
CyIntSetPriority(USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIOR);\r
CyIntClearPending(USBFS_DP_INTC_VECT_NUM);\r
CyIntEnable(USBFS_DP_INTC_VECT_NUM);\r
#endif /* (USBFS_DP_ISR_REMOVE == 0u) */\r
-\r
}\r
\r
\r
{\r
#if(USBFS_DP_ISR_REMOVE == 0u)\r
CyIntDisable(USBFS_DP_INTC_VECT_NUM);\r
- #endif /* End USBFS_DP_ISR_REMOVE */\r
+ #endif /* USBFS_DP_ISR_REMOVE */\r
\r
/* Enable USB block */\r
USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB;\r
/* Set the USBIO pull-up enable */\r
USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N;\r
\r
- /* Reinit Arbiter configuration for DMA transfers */\r
+ /* Re-init Arbiter configuration for DMA transfers */\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
- /* usb arb interrupt enable */\r
+ /* Usb arb interrupt enable */\r
USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;\r
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)\r
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
/*Set cfg cmplt this rises DMA request when the full configuration is done */\r
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
/* STALL_IN_OUT */\r
CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT);\r
\r
/* Restore USB register settings */\r
USBFS_RestoreConfig();\r
-\r
}\r
+\r
CyExitCriticalSection(enableInterrupts);\r
}\r
\r
/*******************************************************************************\r
* File Name: .h\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* This private file provides constants and parameter values for the\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
extern uint8 USBFS_DmaChan[USBFS_MAX_EP];\r
extern uint8 USBFS_DmaTd[USBFS_MAX_EP];\r
-#endif /* End USBFS_EP_MM */\r
+#endif /* USBFS_EP_MM */\r
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ extern uint8 USBFS_DmaNextTd[USBFS_MAX_EP];\r
+ extern const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP];\r
+ extern volatile uint16 USBFS_inLength[USBFS_MAX_EP];\r
+ extern const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];\r
+ extern volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];\r
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */\r
\r
extern volatile uint8 USBFS_ep0Toggle;\r
extern volatile uint8 USBFS_lastPacketSize;\r
void USBFS_ConfigAltChanged(void) ;\r
void USBFS_ConfigReg(void) ;\r
\r
-const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)\r
+const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)\r
;\r
const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void)\r
;\r
void USBFS_SaveConfig(void) ;\r
void USBFS_RestoreConfig(void) ;\r
\r
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) ;\r
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
+\r
#if defined(USBFS_ENABLE_IDSN_STRING)\r
void USBFS_ReadDieID(uint8 descr[]) ;\r
#endif /* USBFS_ENABLE_IDSN_STRING */\r
\r
#if defined(USBFS_ENABLE_HID_CLASS)\r
uint8 USBFS_DispatchHIDClassRqst(void);\r
-#endif /* End USBFS_ENABLE_HID_CLASS */\r
+#endif /* USBFS_ENABLE_HID_CLASS */\r
#if defined(USBFS_ENABLE_AUDIO_CLASS)\r
uint8 USBFS_DispatchAUDIOClassRqst(void);\r
-#endif /* End USBFS_ENABLE_HID_CLASS */\r
+#endif /* USBFS_ENABLE_HID_CLASS */\r
#if defined(USBFS_ENABLE_CDC_CLASS)\r
uint8 USBFS_DispatchCDCClassRqst(void);\r
-#endif /* End USBFS_ENABLE_CDC_CLASS */\r
+#endif /* USBFS_ENABLE_CDC_CLASS */\r
\r
CY_ISR_PROTO(USBFS_EP_0_ISR);\r
#if(USBFS_EP1_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_EP_1_ISR);\r
-#endif /* End USBFS_EP1_ISR_REMOVE */\r
+#endif /* USBFS_EP1_ISR_REMOVE */\r
#if(USBFS_EP2_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_EP_2_ISR);\r
-#endif /* End USBFS_EP2_ISR_REMOVE */\r
+#endif /* USBFS_EP2_ISR_REMOVE */\r
#if(USBFS_EP3_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_EP_3_ISR);\r
-#endif /* End USBFS_EP3_ISR_REMOVE */\r
+#endif /* USBFS_EP3_ISR_REMOVE */\r
#if(USBFS_EP4_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_EP_4_ISR);\r
-#endif /* End USBFS_EP4_ISR_REMOVE */\r
+#endif /* USBFS_EP4_ISR_REMOVE */\r
#if(USBFS_EP5_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_EP_5_ISR);\r
-#endif /* End USBFS_EP5_ISR_REMOVE */\r
+#endif /* USBFS_EP5_ISR_REMOVE */\r
#if(USBFS_EP6_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_EP_6_ISR);\r
-#endif /* End USBFS_EP6_ISR_REMOVE */\r
+#endif /* USBFS_EP6_ISR_REMOVE */\r
#if(USBFS_EP7_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_EP_7_ISR);\r
-#endif /* End USBFS_EP7_ISR_REMOVE */\r
+#endif /* USBFS_EP7_ISR_REMOVE */\r
#if(USBFS_EP8_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_EP_8_ISR);\r
-#endif /* End USBFS_EP8_ISR_REMOVE */\r
+#endif /* USBFS_EP8_ISR_REMOVE */\r
CY_ISR_PROTO(USBFS_BUS_RESET_ISR);\r
#if(USBFS_SOF_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_SOF_ISR);\r
-#endif /* End USBFS_SOF_ISR_REMOVE */\r
+#endif /* USBFS_SOF_ISR_REMOVE */\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
CY_ISR_PROTO(USBFS_ARB_ISR);\r
-#endif /* End USBFS_EP_MM */\r
+#endif /* USBFS_EP_MM */\r
#if(USBFS_DP_ISR_REMOVE == 0u)\r
CY_ISR_PROTO(USBFS_DP_ISR);\r
-#endif /* End USBFS_DP_ISR_REMOVE */\r
-\r
+#endif /* USBFS_DP_ISR_REMOVE */\r
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))\r
+ CY_ISR_PROTO(USBFS_EP_DMA_DONE_ISR);\r
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */\r
\r
/***************************************\r
* Request Handlers\r
/***************************************\r
* HID Internal references\r
***************************************/\r
+\r
#if defined(USBFS_ENABLE_HID_CLASS)\r
void USBFS_FindReport(void) ;\r
void USBFS_FindReportDescriptor(void) ;\r
/***************************************\r
* MIDI Internal references\r
***************************************/\r
+\r
#if defined(USBFS_ENABLE_MIDI_STREAMING)\r
void USBFS_MIDI_IN_EP_Service(void) ;\r
#endif /* USBFS_ENABLE_MIDI_STREAMING */\r
/*******************************************************************************\r
* File Name: USBFS_std.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* USB Standard request handler.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
#include "USBFS.h"\r
#include "USBFS_cdc.h"\r
#include "USBFS_pvt.h"\r
-#if defined(USBFS_ENABLE_MIDI_STREAMING) \r
+#if defined(USBFS_ENABLE_MIDI_STREAMING)\r
#include "USBFS_midi.h"\r
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/\r
+#endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
\r
\r
/***************************************\r
\r
#if defined(USBFS_ENABLE_FWSN_STRING)\r
\r
-\r
/*******************************************************************************\r
* Function Name: USBFS_SerialNumString\r
********************************************************************************\r
USBFS_snStringConfirm = USBFS_FALSE;\r
if(snString != NULL)\r
{\r
- USBFS_fwSerialNumberStringDescriptor = snString;\r
/* Check descriptor validation */\r
if( (snString[0u] > 1u ) && (snString[1u] == USBFS_DESCR_STRING) )\r
{\r
+ USBFS_fwSerialNumberStringDescriptor = snString;\r
USBFS_snStringConfirm = USBFS_TRUE;\r
}\r
}\r
{\r
uint8 requestHandled = USBFS_FALSE;\r
uint8 interfaceNumber;\r
+ uint8 configurationN;\r
#if defined(USBFS_ENABLE_STRINGS)\r
volatile uint8 *pStr = 0u;\r
#if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS)\r
else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_CONFIG)\r
{\r
pTmp = USBFS_GetConfigTablePtr(CY_GET_REG8(USBFS_wValueLo));\r
- USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;\r
- USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \\r
- USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \\r
- (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];\r
- requestHandled = USBFS_InitControlRead();\r
+ if( pTmp != NULL ) /* Verify that requested descriptor exists */\r
+ {\r
+ USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;\r
+ USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \\r
+ USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \\r
+ (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];\r
+ requestHandled = USBFS_InitControlRead();\r
+ }\r
}\r
#if defined(USBFS_ENABLE_STRINGS)\r
else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_STRING)\r
pStr = &pStr[descrLength];\r
nStr++;\r
}\r
- #endif /* End USBFS_ENABLE_DESCRIPTOR_STRINGS */\r
+ #endif /* USBFS_ENABLE_DESCRIPTOR_STRINGS */\r
/* Microsoft OS String*/\r
#if defined(USBFS_ENABLE_MSOS_STRING)\r
if( CY_GET_REG8(USBFS_wValueLo) == USBFS_STRING_MSOS )\r
{\r
pStr = (volatile uint8 *)&USBFS_MSOS_DESCRIPTOR[0u];\r
}\r
- #endif /* End USBFS_ENABLE_MSOS_STRING*/\r
+ #endif /* USBFS_ENABLE_MSOS_STRING*/\r
/* SN string */\r
#if defined(USBFS_ENABLE_SN_STRING)\r
if( (CY_GET_REG8(USBFS_wValueLo) != 0u) &&\r
(CY_GET_REG8(USBFS_wValueLo) ==\r
USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT]) )\r
{\r
- pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];\r
- #if defined(USBFS_ENABLE_FWSN_STRING)\r
- if(USBFS_snStringConfirm != USBFS_FALSE)\r
- {\r
- pStr = USBFS_fwSerialNumberStringDescriptor;\r
- }\r
- #endif /* USBFS_ENABLE_FWSN_STRING */\r
+\r
#if defined(USBFS_ENABLE_IDSN_STRING)\r
/* Read DIE ID and generate string descriptor in RAM */\r
USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor);\r
pStr = USBFS_idSerialNumberStringDescriptor;\r
- #endif /* End USBFS_ENABLE_IDSN_STRING */\r
+ #elif defined(USBFS_ENABLE_FWSN_STRING)\r
+ if(USBFS_snStringConfirm != USBFS_FALSE)\r
+ {\r
+ pStr = USBFS_fwSerialNumberStringDescriptor;\r
+ }\r
+ else\r
+ {\r
+ pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];\r
+ }\r
+ #else\r
+ pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];\r
+ #endif /* defined(USBFS_ENABLE_IDSN_STRING) */\r
}\r
- #endif /* End USBFS_ENABLE_SN_STRING */\r
+ #endif /* USBFS_ENABLE_SN_STRING */\r
if (*pStr != 0u)\r
{\r
USBFS_currentTD.count = *pStr;\r
requestHandled = USBFS_InitControlRead();\r
}\r
}\r
- #endif /* End USBFS_ENABLE_STRINGS */\r
+ #endif /* USBFS_ENABLE_STRINGS */\r
else\r
{\r
requestHandled = USBFS_DispatchClassRqst();\r
requestHandled = USBFS_InitNoDataControlTransfer();\r
break;\r
case USBFS_SET_CONFIGURATION:\r
- USBFS_configuration = CY_GET_REG8(USBFS_wValueLo);\r
- USBFS_configurationChanged = USBFS_TRUE;\r
- USBFS_Config(USBFS_TRUE);\r
- requestHandled = USBFS_InitNoDataControlTransfer();\r
+ configurationN = CY_GET_REG8(USBFS_wValueLo);\r
+ if(configurationN > 0u)\r
+ { /* Verify that configuration descriptor exists */\r
+ pTmp = USBFS_GetConfigTablePtr(configurationN - 1u);\r
+ }\r
+ /* Responds with a Request Error when configuration number is invalid */\r
+ if (((configurationN > 0u) && (pTmp != NULL)) || (configurationN == 0u))\r
+ {\r
+ /* Set new configuration if it has been changed */\r
+ if(configurationN != USBFS_configuration)\r
+ {\r
+ USBFS_configuration = configurationN;\r
+ USBFS_configurationChanged = USBFS_TRUE;\r
+ USBFS_Config(USBFS_TRUE);\r
+ }\r
+ requestHandled = USBFS_InitNoDataControlTransfer();\r
+ }\r
break;\r
case USBFS_SET_INTERFACE:\r
if (USBFS_ValidateAlternateSetting() != 0u)\r
USBFS_Config(USBFS_FALSE);\r
#else\r
USBFS_ConfigAltChanged();\r
- #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */\r
+ #endif /* (USBFS_EP_MA == USBFS__MA_DYNAMIC) */\r
/* Update handled Alt setting changes status */\r
USBFS_interfaceSetting_last[interfaceNumber] =\r
USBFS_interfaceSetting[interfaceNumber];\r
uint8 value;\r
const char8 CYCODE hex[16u] = "0123456789ABCDEF";\r
\r
-\r
/* Check descriptor validation */\r
if( descr != NULL)\r
{\r
}\r
}\r
\r
-#endif /* End USBFS_ENABLE_IDSN_STRING */\r
+#endif /* USBFS_ENABLE_IDSN_STRING */\r
\r
\r
/*******************************************************************************\r
uint8 ep;\r
uint8 i;\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- uint8 ep_type = 0u;\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ uint8 epType = 0u;\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
\r
/* Set the endpoint buffer addresses */\r
ep = USBFS_EP1;\r
for (i = 0u; i < 0x80u; i+= 0x10u)\r
{\r
- CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_CRC_BYPASS |\r
- USBFS_ARB_EPX_CFG_RESET);\r
-\r
+ CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_DEFAULT);\r
#if(USBFS_EP_MM != USBFS__EP_MANUAL)\r
/* Enable all Arbiter EP Interrupts : err, buf under, buf over, dma gnt(mode2 only), in buf full */\r
CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_INT_EN_IND + i), USBFS_ARB_EPX_INT_MASK);\r
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */\r
\r
if(USBFS_EP[ep].epMode != USBFS_MODE_DISABLE)\r
{\r
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_OUT);\r
/* Prepare EP type mask for automatic memory allocation */\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
- ep_type |= (uint8)(0x01u << (ep - USBFS_EP1));\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ epType |= (uint8)(0x01u << (ep - USBFS_EP1));\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
}\r
}\r
else\r
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);\r
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu);\r
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);\r
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
\r
ep++;\r
}\r
USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST; /* DMA burst threshold */\r
USBFS_DMA_THRES_MSB_REG = 0u;\r
USBFS_EP_ACTIVE_REG = USBFS_ARB_INT_MASK;\r
- USBFS_EP_TYPE_REG = ep_type;\r
+ USBFS_EP_TYPE_REG = epType;\r
/* Cfg_cmp bit set to 1 once configuration is complete. */\r
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM |\r
USBFS_ARB_CFG_CFG_CPM;\r
/* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */\r
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
\r
CY_SET_REG8(USBFS_SIE_EP_INT_EN_PTR, 0xFFu);\r
}\r
uint8 ep;\r
uint8 cur_ep;\r
uint8 i;\r
- uint8 ep_type;\r
+ uint8 epType;\r
const uint8 *pDescr;\r
#if(USBFS_EP_MM != USBFS__EP_DMAAUTO)\r
uint16 buffCount = 0u;\r
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
\r
const T_USBFS_LUT CYCODE *pTmp;\r
const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP;\r
pEP = (T_USBFS_EP_SETTINGS_BLOCK *) pTmp->p_list;\r
for (i = 0u; i < ep; i++)\r
{\r
- /* Compare current Alternate setting with EP Alt*/\r
+ /* Compare current Alternate setting with EP Alt */\r
if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)\r
{\r
cur_ep = pEP->addr & USBFS_DIR_UNUSED;\r
- ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;\r
+ epType = pEP->attributes & USBFS_EP_TYPE_MASK;\r
if (pEP->addr & USBFS_DIR_IN)\r
{\r
/* IN Endpoint */\r
USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;\r
- USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?\r
+ USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;\r
#if defined(USBFS_ENABLE_CDC_CLASS)\r
if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||\r
(pEP->bMisc == USBFS_CLASS_CDC)) &&\r
- (ep_type != USBFS_EP_TYPE_INT))\r
+ (epType != USBFS_EP_TYPE_INT))\r
{\r
USBFS_cdc_data_in_ep = cur_ep;\r
}\r
- #endif /* End USBFS_ENABLE_CDC_CLASS*/\r
+ #endif /* USBFS_ENABLE_CDC_CLASS*/\r
#if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
(USBFS_MIDI_IN_BUFF_SIZE > 0) )\r
if((pEP->bMisc == USBFS_CLASS_AUDIO) &&\r
- (ep_type == USBFS_EP_TYPE_BULK))\r
+ (epType == USBFS_EP_TYPE_BULK))\r
{\r
USBFS_midi_in_ep = cur_ep;\r
}\r
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/\r
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
}\r
else\r
{\r
/* OUT Endpoint */\r
USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;\r
- USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?\r
+ USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;\r
#if defined(USBFS_ENABLE_CDC_CLASS)\r
if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||\r
(pEP->bMisc == USBFS_CLASS_CDC)) &&\r
- (ep_type != USBFS_EP_TYPE_INT))\r
+ (epType != USBFS_EP_TYPE_INT))\r
{\r
USBFS_cdc_data_out_ep = cur_ep;\r
}\r
- #endif /* End USBFS_ENABLE_CDC_CLASS*/\r
+ #endif /* USBFS_ENABLE_CDC_CLASS*/\r
#if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
(USBFS_MIDI_OUT_BUFF_SIZE > 0) )\r
if((pEP->bMisc == USBFS_CLASS_AUDIO) &&\r
- (ep_type == USBFS_EP_TYPE_BULK))\r
+ (epType == USBFS_EP_TYPE_BULK))\r
{\r
USBFS_midi_out_ep = cur_ep;\r
}\r
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/\r
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
}\r
USBFS_EP[cur_ep].bufferSize = pEP->bufferSize;\r
USBFS_EP[cur_ep].addr = pEP->addr;\r
}\r
pEP = &pEP[1u];\r
}\r
- #else /* Config for static EP memory allocation */\r
+ #else /* Configure for static EP memory allocation */\r
for (i = USBFS_EP1; i < USBFS_MAX_EP; i++)\r
{\r
/* p_list points the endpoint setting table. */\r
/* Compare current Alternate setting with EP Alt*/\r
if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)\r
{\r
- ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;\r
+ epType = pEP->attributes & USBFS_EP_TYPE_MASK;\r
if ((pEP->addr & USBFS_DIR_IN) != 0u)\r
{\r
/* IN Endpoint */\r
USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING;\r
- USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?\r
+ USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;\r
- /* Find and init CDC IN endpoint number */\r
+ /* Find and initialize CDC IN endpoint number */\r
#if defined(USBFS_ENABLE_CDC_CLASS)\r
if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||\r
(pEP->bMisc == USBFS_CLASS_CDC)) &&\r
- (ep_type != USBFS_EP_TYPE_INT))\r
+ (epType != USBFS_EP_TYPE_INT))\r
{\r
USBFS_cdc_data_in_ep = i;\r
}\r
- #endif /* End USBFS_ENABLE_CDC_CLASS*/\r
+ #endif /* USBFS_ENABLE_CDC_CLASS*/\r
#if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
(USBFS_MIDI_IN_BUFF_SIZE > 0) )\r
if((pEP->bMisc == USBFS_CLASS_AUDIO) &&\r
- (ep_type == USBFS_EP_TYPE_BULK))\r
+ (epType == USBFS_EP_TYPE_BULK))\r
{\r
USBFS_midi_in_ep = i;\r
}\r
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/\r
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
}\r
else\r
{\r
/* OUT Endpoint */\r
USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING;\r
- USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?\r
+ USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;\r
- /* Find and init CDC IN endpoint number */\r
+ /* Find and initialize CDC IN endpoint number */\r
#if defined(USBFS_ENABLE_CDC_CLASS)\r
if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||\r
(pEP->bMisc == USBFS_CLASS_CDC)) &&\r
- (ep_type != USBFS_EP_TYPE_INT))\r
+ (epType != USBFS_EP_TYPE_INT))\r
{\r
USBFS_cdc_data_out_ep = i;\r
}\r
- #endif /* End USBFS_ENABLE_CDC_CLASS*/\r
+ #endif /* USBFS_ENABLE_CDC_CLASS*/\r
#if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \\r
(USBFS_MIDI_OUT_BUFF_SIZE > 0) )\r
if((pEP->bMisc == USBFS_CLASS_AUDIO) &&\r
- (ep_type == USBFS_EP_TYPE_BULK))\r
+ (epType == USBFS_EP_TYPE_BULK))\r
{\r
USBFS_midi_out_ep = i;\r
}\r
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/\r
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/\r
}\r
USBFS_EP[i].addr = pEP->addr;\r
USBFS_EP[i].attrib = pEP->attributes;\r
\r
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)\r
break; /* use first EP setting in Auto memory managment */\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
}\r
}\r
pEP = &pEP[1u];\r
}\r
}\r
- #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */\r
+ #endif /* (USBFS_EP_MA == USBFS__MA_DYNAMIC) */\r
\r
/* Init class array for each interface and interface number for each EP.\r
* It is used for handling Class specific requests directed to either an\r
USBFS_EP[ep].buffOffset = buffCount;\r
buffCount += USBFS_EP[ep].bufferSize;\r
}\r
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */\r
\r
/* Configure hardware registers */\r
USBFS_ConfigReg();\r
uint8 ep;\r
uint8 cur_ep;\r
uint8 i;\r
- uint8 ep_type;\r
+ uint8 epType;\r
uint8 ri;\r
\r
const T_USBFS_LUT CYCODE *pTmp;\r
{\r
cur_ep = pEP->addr & USBFS_DIR_UNUSED;\r
ri = ((cur_ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);\r
- ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;\r
+ epType = pEP->attributes & USBFS_EP_TYPE_MASK;\r
if ((pEP->addr & USBFS_DIR_IN) != 0u)\r
{\r
/* IN Endpoint */\r
USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;\r
- USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?\r
+ USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;\r
}\r
else\r
{\r
/* OUT Endpoint */\r
USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;\r
- USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?\r
+ USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?\r
USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;\r
}\r
/* Change the SIE mode for the selected EP to NAK ALL */\r
USBFS_EP[cur_ep].buffOffset & 0xFFu);\r
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ri),\r
USBFS_EP[cur_ep].buffOffset >> 8u);\r
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */\r
}\r
/* Get next EP element */\r
pEP = &pEP[1u];\r
* This routine returns a pointer a configuration table entry\r
*\r
* Parameters:\r
-* c: Configuration Index\r
+* confIndex: Configuration Index\r
*\r
* Return:\r
-* Device Descriptor pointer.\r
+* Device Descriptor pointer or NULL when descriptor isn't exists.\r
*\r
*******************************************************************************/\r
-const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)\r
+const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)\r
\r
{\r
/* Device Table */\r
\r
/* The first entry points to the Device Descriptor,\r
* the rest configuration entries.\r
- */\r
- return( (const T_USBFS_LUT CYCODE *) pTmp[c + 1u].p_list );\r
+ * Set pointer to the first Configuration Descriptor\r
+ */\r
+ pTmp = &pTmp[1u];\r
+ /* For this table, c is the number of configuration descriptors */\r
+ if(confIndex >= pTmp->c) /* Verify that required configuration descriptor exists */\r
+ {\r
+ pTmp = (const T_USBFS_LUT CYCODE *) NULL;\r
+ }\r
+ else\r
+ {\r
+ pTmp = (const T_USBFS_LUT CYCODE *) pTmp[confIndex].p_list;\r
+ }\r
+\r
+ return( pTmp );\r
}\r
\r
\r
\r
{\r
const T_USBFS_LUT CYCODE *pTmp;\r
+ const uint8 CYCODE *pInterfaceClass;\r
uint8 currentInterfacesNum;\r
\r
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);\r
- currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];\r
- /* Third entry in the LUT starts the Interface Table pointers */\r
- /* The INTERFACE_CLASS table is located after all interfaces */\r
- pTmp = &pTmp[currentInterfacesNum + 2u];\r
- return( (const uint8 CYCODE *) pTmp->p_list );\r
+ if( pTmp != NULL )\r
+ {\r
+ currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];\r
+ /* Third entry in the LUT starts the Interface Table pointers */\r
+ /* The INTERFACE_CLASS table is located after all interfaces */\r
+ pTmp = &pTmp[currentInterfacesNum + 2u];\r
+ pInterfaceClass = (const uint8 CYCODE *) pTmp->p_list;\r
+ }\r
+ else\r
+ {\r
+ pInterfaceClass = (const uint8 CYCODE *) NULL;\r
+ }\r
+\r
+ return( pInterfaceClass );\r
}\r
\r
\r
/*******************************************************************************\r
* File Name: USBFS_vnd.c\r
-* Version 2.60\r
+* Version 2.80\r
*\r
* Description:\r
* USB vendor request handler.\r
* Note:\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
********************************************************************************\r
*\r
* Summary:\r
-* This routine provide users with a method to implement vendor specifc\r
+* This routine provide users with a method to implement vendor specific\r
* requests.\r
*\r
* To implement vendor specific requests, add your code in this function to\r
USBFS_currentTD.pData = (volatile uint8 *)&USBFS_MSOS_CONFIGURATION_DESCR[0u];\r
USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u];\r
requestHandled = USBFS_InitControlRead();\r
- #endif /* End USBFS_ENABLE_MSOS_STRING */\r
+ #endif /* USBFS_ENABLE_MSOS_STRING */\r
break;\r
default:\r
break;\r
*/\r
EXTERN(Reset)\r
\r
-/* Bring in the interrupt routines & vector */\r
+/* Bring in interrupt routines & vector */\r
EXTERN(main)\r
\r
-/* Bring in the meta data */\r
+/* Bring in meta data */\r
EXTERN(cy_meta_loader cy_bootloader cy_meta_loadable cy_meta_bootloader)\r
EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata)\r
\r
/* Make sure we pulled in some reset code. */\r
ASSERT (. != __cy_reset, "No reset code");\r
\r
- /* Place the DMA initialization before text to ensure it gets placed in first 64K of flash */\r
+ /* Place DMA initialization before text to ensure it gets placed in first 64K of flash */\r
*(.dma_init)\r
ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash");\r
\r
/*******************************************************************************\r
* File Name: core_cm3_psoc5.h\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides important type information for the PSoC5. This includes types\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
/*******************************************************************************\r
* File Name: cyPm.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides an API for the power management.\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
\r
/*******************************************************************\r
-* Place your includes, defines and code here. Do not use merge\r
-* region below unless any component datasheet suggest to do so.\r
+* Place your includes, defines, and code here. Do not use the merge\r
+* region below unless any component datasheet suggests doing so.\r
*******************************************************************/\r
/* `#START CY_PM_HEADER_INCLUDE` */\r
\r
*\r
* Summary:\r
* This function is called in preparation for entering sleep or hibernate low\r
-* power modes. Saves all state of the clocking system that does not persist\r
-* during sleep/hibernate or that needs to be altered in preparation for\r
+* power modes. Saves all the states of the clocking system that do not persist\r
+* during sleep/hibernate or that need to be altered in preparation for\r
* sleep/hibernate. Shutdowns all the digital and analog clock dividers for the\r
* active power mode configuration.\r
*\r
cyPmClockBackup.imo2x = CY_PM_DISABLED;\r
}\r
\r
+ /* Master clock - save source */\r
+ cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK;\r
+\r
+ /* Switch Master clock's source from PLL's output to PLL's source */\r
+ if(CY_MASTER_SOURCE_PLL == cyPmClockBackup.masterClkSrc)\r
+ {\r
+ switch (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_PLL_SRC_MASK)\r
+ {\r
+ case CY_PM_CLKDIST_PLL_SRC_IMO:\r
+ CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO);\r
+ break;\r
+\r
+ case CY_PM_CLKDIST_PLL_SRC_XTAL:\r
+ CyMasterClk_SetSource(CY_MASTER_SOURCE_XTAL);\r
+ break;\r
+\r
+ case CY_PM_CLKDIST_PLL_SRC_DSI:\r
+ CyMasterClk_SetSource(CY_MASTER_SOURCE_DSI);\r
+ break;\r
+\r
+ default:\r
+ CYASSERT(0u != 0u);\r
+ break;\r
+ }\r
+ }\r
+\r
+ /* PLL - check enable state, disable if needed */\r
+ if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE))\r
+ {\r
+ /* PLL is enabled - save state and disable */\r
+ cyPmClockBackup.pllEnableState = CY_PM_ENABLED;\r
+ CyPLL_OUT_Stop();\r
+ }\r
+ else\r
+ {\r
+ /* PLL is disabled - save state */\r
+ cyPmClockBackup.pllEnableState = CY_PM_DISABLED;\r
+ }\r
+\r
/* IMO - set appropriate frequency for LPM */\r
CyIMO_SetFreq(CY_PM_IMO_FREQ_LPM);\r
\r
/* IMO - save disabled state */\r
cyPmClockBackup.imoEnable = CY_PM_DISABLED;\r
\r
- /* IMO - enable */\r
+ /* Enable the IMO. Use software delay instead of the FTW-based inside */\r
CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE);\r
+\r
+ /* Settling time of the IMO is of the order of less than 6us */\r
+ CyDelayUs(6u);\r
}\r
\r
/* IMO - save the current IMOCLK source and set to IMO if not yet */\r
cyPmClockBackup.imoClkSrc =\r
(0u == (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO2X_SRC)) ? CY_IMO_SOURCE_DSI : CY_IMO_SOURCE_XTAL;\r
\r
- /* IMO - set IMOCLK source to MHz OSC */\r
+ /* IMO - set IMOCLK source to IMO */\r
CyIMO_SetSource(CY_IMO_SOURCE_IMO);\r
}\r
else\r
if(CY_PM_DIV_BY_ONE != cyPmClockBackup.clkSyncDiv)\r
{\r
CyMasterClk_SetDivider(CY_PM_DIV_BY_ONE);\r
- } /* Need to change nothing if master clock divider is 1 */\r
-\r
- /* Master clock - save current source */\r
- cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK;\r
+ } /* No change if master clock divider is 1 */\r
\r
/* Master clock source - set it to IMO if not yet. */\r
if(CY_MASTER_SOURCE_IMO != cyPmClockBackup.masterClkSrc)\r
{\r
CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO);\r
- } /* Need to change nothing if master clock source is IMO */\r
+ } /* No change if master clock source is IMO */\r
\r
/* Bus clock - save divider and set it, if needed, to divide-by-one */\r
cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u);\r
CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE);\r
} /* Do nothing if saved and actual values are equal */\r
\r
- /* Set number of wait cycles for the flash according CPU frequency in MHz */\r
+ /* Set number of wait cycles for flash according to CPU frequency in MHz */\r
CyFlash_SetWaitCycles((uint8)CY_PM_GET_CPU_FREQ_MHZ);\r
\r
- /* PLL - check enable state, disable if needed */\r
- if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE))\r
- {\r
- /* PLL is enabled - save state and disable */\r
- cyPmClockBackup.pllEnableState = CY_PM_ENABLED;\r
- CyPLL_OUT_Stop();\r
- }\r
- else\r
- {\r
- /* PLL is disabled - save state */\r
- cyPmClockBackup.pllEnableState = CY_PM_DISABLED;\r
- }\r
-\r
/* MHz ECO - check enable state and disable if needed */\r
if(0u != (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_ENABLE))\r
{\r
\r
\r
/***************************************************************************\r
- * Save enable state of delay between the system bus clock and each of the\r
- * 4 individual analog clocks. This bit non-retention and it's value should\r
+ * Save the enable state of delay between the system bus clock and each of the\r
+ * 4 individual analog clocks. This bit non-retention and its value should\r
* be restored on wakeup.\r
***************************************************************************/\r
if(0u != (CY_PM_CLKDIST_DELAY_REG & CY_PM_CLKDIST_DELAY_EN))\r
*\r
* PSoC 3 and PSoC 5LP:\r
* The merge region could be used to process state when the megahertz crystal is\r
-* not ready after the hold-off timeout.\r
+* not ready after a hold-off timeout.\r
*\r
* PSoC 5:\r
-* The 130 ms is given for the megahertz crystal to stabilize. It's readiness is\r
-* not verified after the hold-off timeout.\r
+* The 130 ms is given for the megahertz crystal to stabilize. Its readiness is\r
+* not verified after a hold-off timeout.\r
*\r
* Parameters:\r
* None\r
CY_IMO_FREQ_12MHZ, CY_IMO_FREQ_6MHZ, CY_IMO_FREQ_24MHZ, CY_IMO_FREQ_3MHZ,\r
CY_IMO_FREQ_48MHZ, 5u, 6u};\r
\r
- /* Restore enable state of delay between the system bus clock and ACLKs. */\r
+ /* Restore enable state of delay between system bus clock and ACLKs. */\r
if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay)\r
{\r
- /* Delay for both the bandgap and the delay line to settle out */\r
+ /* Delay for both bandgap and delay line to settle out */\r
CyDelayCycles((uint32)(CY_PM_CLK_DELAY_BANDGAP_SETTLE_US + CY_PM_CLK_DELAY_BIAS_SETTLE_US) *\r
CY_PM_GET_CPU_FREQ_MHZ);\r
\r
if(CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState)\r
{\r
/***********************************************************************\r
- * Enabling XMHZ XTAL. The actual CyXTAL_Start() with non zero wait\r
+ * Enabling XMHZ XTAL. The actual CyXTAL_Start() with a non zero wait\r
* period uses FTW for period measurement. This could cause a problem\r
* if CTW/FTW is used as a wake up time in the low power modes APIs.\r
* So, the XTAL wait procedure is implemented with a software delay.\r
{\r
/*******************************************************************\r
* Process the situation when megahertz crystal is not ready.\r
- * Time to stabialize value is crystal specific.\r
+ * Time to stabilize the value is crystal specific.\r
*******************************************************************/\r
/* `#START_MHZ_ECO_TIMEOUT` */\r
\r
} /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */\r
\r
\r
- /* Temprorary set the maximum flash wait cycles */\r
+ /* Temprorary set maximum flash wait cycles */\r
CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES);\r
\r
- /* The XTAL and DSI clocks are ready to be source for Master clock. */\r
+ /* XTAL and DSI clocks are ready to be source for Master clock. */\r
if((CY_PM_MASTER_CLK_SRC_XTAL == cyPmClockBackup.masterClkSrc) ||\r
(CY_PM_MASTER_CLK_SRC_DSI == cyPmClockBackup.masterClkSrc))\r
{\r
CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE);\r
}\r
\r
- /* IMO - restore disable state if needed */\r
- if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) &&\r
- (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)))\r
- {\r
- CyIMO_Stop();\r
- }\r
-\r
/* IMO - restore IMOCLK source */\r
CyIMO_SetSource(cyPmClockBackup.imoClkSrc);\r
\r
cyPmClockBackup.clkImoSrc;\r
}\r
\r
+\r
/* PLL restore state */\r
if(CY_PM_ENABLED == cyPmClockBackup.pllEnableState)\r
{\r
* as a wakeup time in the low power modes APIs. To omit this issue PLL\r
* wait procedure is implemented with a software delay.\r
***********************************************************************/\r
+ status = CYRET_TIMEOUT;\r
\r
/* Enable PLL */\r
(void) CyPLL_OUT_Start(CY_PM_PLL_OUT_NO_WAIT);\r
\r
- /* Make a 250 us delay */\r
- CyDelayCycles((uint32)CY_PM_WAIT_250_US * CY_PM_GET_CPU_FREQ_MHZ);\r
+ /* Read to clear lock status after delay */\r
+ CyDelayUs((uint32)80u);\r
+ (void) CY_PM_FASTCLK_PLL_SR_REG;\r
+\r
+ /* It should take 250 us lock: 251-80 = 171 */\r
+ for(i = 171u; i > 0u; i--)\r
+ {\r
+ CyDelayUs((uint32)1u);\r
+\r
+ /* Accept PLL is OK after two consecutive polls indicate PLL lock */\r
+ if((0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED)) &&\r
+ (0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED)))\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ break;\r
+ }\r
+ }\r
+\r
+ if(CYRET_TIMEOUT == status)\r
+ {\r
+ /*******************************************************************\r
+ * Process the situation when PLL is not ready.\r
+ *******************************************************************/\r
+ /* `#START_PLL_TIMEOUT` */\r
+\r
+ /* `#END` */\r
+ }\r
} /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */\r
\r
\r
CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc);\r
}\r
\r
+ /* IMO - disable if it was originally disabled */\r
+ if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) &&\r
+ (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)))\r
+ {\r
+ CyIMO_Stop();\r
+ }\r
+\r
/* Bus clock - restore divider, if needed */\r
clkBusDivTmp = (uint16) ((uint16)CY_PM_CLK_BUS_MSB_DIV_REG << 8u);\r
clkBusDivTmp |= CY_PM_CLK_BUS_LSB_DIV_REG;\r
* Sleep Timer component and one second interval should be configured with the\r
* RTC component.\r
*\r
-* The wakeup behavior depends on wakeupSource parameter in the following\r
+* The wakeup behavior depends on the wakeupSource parameter in the following\r
* manner: upon function execution the device will be switched from Active to\r
* Alternate Active mode and then the CPU will be halted. When an enabled wakeup\r
* event occurs the device will return to Active mode. Similarly when an\r
For PSoC 3 silicon the valid range of values is 1 to 256.\r
*\r
* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if\r
-* a wakeupTime has been specified the associated timer will be\r
+* a wakeupTime has been specified, the associated timer will be\r
* included as a wakeup source.\r
*\r
* Define Source\r
* *Note : FTW and HVI/LVI wakeup signals are in the same mask bit.\r
* **Note: CTW and One PPS wakeup signals are in the same mask bit.\r
*\r
-* When specifying a Comparator as the wakeupSource an instance specific define\r
-* should be used that will track with the specific comparator that the instance\r
-* is placed into. As an example, for a Comparator instance named MyComp the\r
+* When specifying a Comparator as the wakeupSource, an instance specific define\r
+* that will track with the specific comparator that the instance\r
+* is placed into should be used. As an example, for a Comparator instance named MyComp the\r
* value to OR into the mask is: MyComp_ctComp__CMP_MASK.\r
*\r
* When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus()\r
-* function must be called upon wakeup with corresponding parameter. Please\r
+* function must be called upon wakeup with a corresponding parameter. Please\r
* refer to the CyPmReadStatus() API in the System Reference Guide for more\r
* information.\r
*\r
* If a wakeupTime other than NONE is specified, then upon exit the state of the\r
* specified timer will be left as specified by wakeupTime with the timer\r
* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is\r
-* used as wakeup time) or ILO 100 KHz (if FTW timer is used as wakeup time)\r
+* used as wakeup time) or ILO 100 KHz (if the FTW timer is used as wakeup time)\r
* will be left started.\r
*\r
*******************************************************************************/\r
{\r
CyPmFtwSetInterval(PM_ALT_ACT_FTW_INTERVAL(wakeupTime));\r
\r
- /* Include associated timer to the wakeupSource */\r
+ /* Include associated timer to wakeupSource */\r
wakeupSource |= PM_ALT_ACT_SRC_FTW;\r
}\r
\r
/* Save current CTW configuration and set new one */\r
CyPmCtwSetInterval((uint8)(wakeupTime - 1u));\r
\r
- /* Include associated timer to the wakeupSource */\r
+ /* Include associated timer to wakeupSource */\r
wakeupSource |= PM_ALT_ACT_SRC_CTW;\r
}\r
\r
/* Save current 1PPS configuration and set new one */\r
CyPmOppsSet();\r
\r
- /* Include associated timer to the wakeupSource */\r
+ /* Include associated timer to wakeupSource */\r
wakeupSource |= PM_ALT_ACT_SRC_ONE_PPS;\r
}\r
\r
* Puts the part into the Sleep state.\r
*\r
* Note Before calling this function, you must manually configure the power\r
-* mode of the source clocks for the timer that is used as wakeup timer.\r
+* mode of the source clocks for the timer that is used as the wakeup timer.\r
*\r
* Note Before calling this function, you must prepare clock tree configuration\r
* for the low power mode by calling CyPmSaveClocks(). And restore clock\r
* PSoC 3:\r
* Before switching to Sleep, if a wakeupTime other than NONE is specified,\r
* then the appropriate timer state is configured as specified with the\r
-* interrupt for that timer disabled. The wakeup source will be the combination\r
+* interrupt for that timer disabled. The wakeup source will be a combination\r
* of the values specified in the wakeupSource and any timer specified in the\r
* wakeupTime argument. Once the wakeup condition is satisfied, then all saved\r
* state is restored and the function returns in the Active state.\r
* The wakeupTime parameter is not used and the only NONE can be specified.\r
* The wakeup time must be configured with the component, SleepTimer for CTW\r
* intervals and RTC for 1PPS interval. The component must be configured to\r
-* generate an interrrupt.\r
+* generate interrupt.\r
*\r
* Parameters:\r
* wakeupTime: Specifies a timer wakeup source and the frequency of that\r
* detect (power supply supervising capabilities) are required in a design\r
* during sleep, use the Central Time Wheel (CTW) to periodically wake the\r
* device, perform software buzz, and refresh the supervisory services. If LVI,\r
-* HVI, or Brown Out is not required, then use of the CTW is not required.\r
+* HVI, or Brown Out is not required, then CTW is not required.\r
* Refer to the device errata for more information.\r
*\r
*******************************************************************************/\r
\r
/***********************************************************************\r
* PSoC3 < TO6:\r
- * - Hardware buzz must be disabled before sleep mode entry.\r
+ * - Hardware buzz must be disabled before the sleep mode entry.\r
* - Voltage supervision (HVI/LVI) requires hardware buzz, so they must\r
- * be aslo disabled.\r
+ * be also disabled.\r
*\r
* PSoC3 >= TO6:\r
- * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware buzz must be\r
- * enabled before sleep mode entry and restored on wakeup.\r
+ * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware\r
+ * buzz must be enabled before the sleep mode entry and restored on\r
+ * the wakeup.\r
***********************************************************************/\r
#if(CY_PSOC3)\r
\r
\r
\r
/*******************************************************************************\r
- * For ARM-based devices, an interrupt is required for the CPU to wake up. The\r
+ * For ARM-based devices,interrupt is required for the CPU to wake up. The\r
* Power Management implementation assumes that wakeup time is configured with a\r
- * separate component (component-based wakeup time configuration) for an\r
+ * separate component (component-based wakeup time configuration) for\r
* interrupt to be issued on terminal count. For more information, refer to the\r
* Wakeup Time Configuration section of System Reference Guide.\r
*******************************************************************************/\r
/* CTW - save current and set new configuration */\r
if((wakeupTime >= PM_SLEEP_TIME_CTW_2MS) && (wakeupTime <= PM_SLEEP_TIME_CTW_4096MS))\r
{\r
- /* Save current and set new configuration of the CTW */\r
+ /* Save current and set new configuration of CTW */\r
CyPmCtwSetInterval((uint8)(wakeupTime - 1u));\r
\r
- /* Include associated timer to the wakeupSource */\r
+ /* Include associated timer to wakeupSource */\r
wakeupSource |= PM_SLEEP_SRC_CTW;\r
}\r
\r
/* Save current and set new configuration of the 1PPS */\r
CyPmOppsSet();\r
\r
- /* Include associated timer to the wakeupSource */\r
+ /* Include associated timer to wakeupSource */\r
wakeupSource |= PM_SLEEP_SRC_ONE_PPS;\r
}\r
\r
\r
\r
/*******************************************************************\r
- * Do not use merge region below unless any component datasheet\r
- * suggest to do so.\r
+ * Do not use the merge region below unless any component datasheet\r
+ * suggests doing so.\r
*******************************************************************/\r
/* `#START CY_PM_JUST_BEFORE_SLEEP` */\r
\r
CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK));\r
}\r
\r
- /* Switch to the Sleep mode */\r
+ /* Switch to Sleep mode */\r
CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_SLEEP);\r
\r
/* Recommended readback. */\r
(void) CY_PM_MODE_CSR_REG;\r
\r
- /* Two recommended NOPs to get into the mode. */\r
+ /* Two recommended NOPs to get into mode. */\r
CY_NOP;\r
CY_NOP;\r
\r
* PSoC 3 and PSoC 5LP:\r
* Before switching to Hibernate, the current status of the PICU wakeup source\r
* bit is saved and then set. This configures the device to wake up from the\r
-* PICU. Make sure you have at least one pin configured to generate a PICU\r
+* PICU. Make sure you have at least one pin configured to generate PICU\r
* interrupt. For pin Px.y, the register "PICU_INTTYPE_PICUx_INTTYPEy" controls\r
* the PICU behavior. In the TRM, this register is "PICU[0..15]_INTTYPE[0..7]."\r
* In the Pins component datasheet, this register is referred to as the IRQ\r
* requirement begins when the device wakes up. There is no hardware check that\r
* this requirement is met. The specified delay should be done on ISR entry.\r
*\r
-* After wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is\r
+* After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is\r
* instance name of the Pins component) function must be called to clear the\r
-* latched pin events to allow proper Hibernate mode entry andd to enable\r
+* latched pin events to allow the proper Hibernate mode entry and to enable\r
* detection of future events.\r
*\r
* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to\r
* measure Hibernate/Sleep regulator settling time after a reset. The holdoff\r
-* delay is measured using rising edges of the 1 kHz ILO.\r
+* delay is measured using the rising edges of the 1 kHz ILO.\r
*\r
*******************************************************************************/\r
void CyPmHibernate(void) \r
\r
/***********************************************************************\r
* The Hibernate/Sleep regulator has a settling time after a reset.\r
- * During this time, the system ignores requests to enter Sleep and\r
- * Hibernate modes. The holdoff delay is measured using rising edges of\r
+ * During this time, the system ignores requests to enter the Sleep and\r
+ * Hibernate modes. The holdoff delay is measured using the rising edges of\r
* the 1 kHz ILO.\r
***********************************************************************/\r
if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q))\r
/* Recommended readback. */\r
(void) CY_PM_MODE_CSR_REG;\r
\r
- /* Two recommended NOPs to get into the mode. */\r
+ /* Two recommended NOPs to get into mode. */\r
CY_NOP;\r
CY_NOP;\r
\r
/* Enter critical section */\r
interruptState = CyEnterCriticalSection();\r
\r
- /* Save value of the register, copy it and clear desired bit */\r
+ /* Save value of register, copy it and clear desired bit */\r
interruptStatus |= CY_PM_INT_SR_REG;\r
tmpStatus = interruptStatus;\r
interruptStatus &= ((uint8)(~mask));\r
if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP))\r
{\r
/***********************************************************************\r
- * If I2C backup regulator is enabled, all the fixed-function registers\r
- * store their values while device is in low power mode, otherwise their\r
+ * If the I2C backup regulator is enabled, all the fixed-function registers\r
+ * store their values while the device is in the low power mode, otherwise their\r
* configuration is lost. The I2C API makes a decision to restore or not\r
* to restore I2C registers based on this. If this regulator will be\r
- * disabled and then enabled, I2C API will suppose that I2C block\r
+ * disabled and then enabled, I2C API will suppose that the I2C block\r
* registers preserved their values, while this is not true. So, the\r
* backup regulator is disabled. The I2C sleep APIs is responsible for\r
* restoration.\r
\r
\r
/***************************************************************************\r
- * Save and set power mode wakeup trim registers\r
+ * Save and set the power mode wakeup trim registers\r
***************************************************************************/\r
cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG;\r
cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG;\r
********************************************************************************\r
*\r
* Summary:\r
-* Restore device for proper Hibernate mode exit:\r
-* - Restore LVI/HVI configuration - call CyPmHviLviRestore()\r
+* Restores the device for the proper Hibernate mode exit:\r
+* - Restores LVI/HVI configuration - calsl CyPmHviLviRestore()\r
* - CyPmHibSlpSaveRestore() function is called\r
-* - Restores ILO power down mode state and enable it\r
-* - Restores state of 1 kHz and 100 kHz ILO and disable them\r
-* - Restores sleep regulator settings\r
+* - Restores ILO power down mode state and enables it\r
+* - Restores the state of 1 kHz and 100 kHz ILO and disables them\r
+* - Restores the sleep regulator settings\r
*\r
* Parameters:\r
* None\r
\r
\r
/***************************************************************************\r
- * Restore power mode wakeup trim registers\r
+ * Restore the power mode wakeup trim registers\r
***************************************************************************/\r
CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0;\r
CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1;\r
********************************************************************************\r
*\r
* Summary:\r
-* Performs CTW configuration:\r
-* - Disables CTW interrupt\r
+* Performs the CTW configuration:\r
+* - Disables the CTW interrupt\r
* - Enables 1 kHz ILO\r
-* - Sets new CTW interval\r
+* - Sets a new CTW interval\r
*\r
* Parameters:\r
* ctwInterval: the CTW interval to be set.\r
/* Set CTW interval if needed */\r
if(CY_PM_TW_CFG1_REG != ctwInterval)\r
{\r
- /* Set the new CTW interval. Could be changed if CTW is disabled */\r
+ /* Set new CTW interval. Could be changed if CTW is disabled */\r
CY_PM_TW_CFG1_REG = ctwInterval;\r
} /* Required interval is already set */\r
\r
- /* Enable the CTW */\r
+ /* Enable CTW */\r
CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN;\r
}\r
}\r
* Summary:\r
* Performs 1PPS configuration:\r
* - Starts 32 KHz XTAL\r
-* - Disables 1PPS interupts\r
+* - Disables 1PPS interrupts\r
* - Enables 1PPS\r
*\r
* Parameters:\r
********************************************************************************\r
*\r
* Summary:\r
-* Performs FTW configuration:\r
-* - Disables FTW interrupt\r
+* Performs the FTW configuration:\r
+* - Disables the FTW interrupt\r
* - Enables 100 kHz ILO\r
-* - Sets new FTW interval.\r
+* - Sets a new FTW interval.\r
*\r
* Parameters:\r
* ftwInterval - FTW counter interval.\r
* None\r
*\r
* Side Effects:\r
-* Enables ILO 100 KHz clock and leaves it enabled.\r
+* Enables the ILO 100 KHz clock and leaves it enabled.\r
*\r
*******************************************************************************/\r
void CyPmFtwSetInterval(uint8 ftwInterval) \r
/* Enable 100kHz ILO */\r
CyILO_Start100K();\r
\r
- /* Iterval could be set only while FTW is disabled */\r
+ /* Interval could be set only while FTW is disabled */\r
if(0u != (CY_PM_TW_CFG2_REG & CY_PM_FTW_EN))\r
{\r
/* Disable FTW, set new FTW interval if needed and enable it again */\r
if(CY_PM_TW_CFG0_REG != ftwInterval)\r
{\r
- /* Disable the CTW, set new CTW interval and enable it again */\r
+ /* Disable CTW, set new CTW interval and enable it again */\r
CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_EN));\r
CY_PM_TW_CFG0_REG = ftwInterval;\r
CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN;\r
/* Set new FTW counter interval if needed. FTW is disabled. */\r
if(CY_PM_TW_CFG0_REG != ftwInterval)\r
{\r
- /* Set the new CTW interval. Could be changed if CTW is disabled */\r
+ /* Set new CTW interval. Could be changed if CTW is disabled */\r
CY_PM_TW_CFG0_REG = ftwInterval;\r
} /* Required interval is already set */\r
\r
- /* Enable the FTW */\r
+ /* Enable FTW */\r
CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN;\r
}\r
}\r
********************************************************************************\r
*\r
* Summary:\r
-* This API is used for preparing device for Sleep and Hibernate low power\r
+* This API is used for preparing the device for the Sleep and Hibernate low power\r
* modes entry:\r
-* - Saves COMP, VIDAC, DSM and SAR routing connections (PSoC 5)\r
-* - Saves SC/CT routing connections (PSoC 3/5/5LP)\r
-* - Disables Serial Wire Viewer (SWV) (PSoC 3)\r
-* - Save boost reference selection and set it to internal\r
+* - Saves the COMP, VIDAC, DSM, and SAR routing connections (PSoC 5)\r
+* - Saves the SC/CT routing connections (PSoC 3/5/5LP)\r
+* - Disables the Serial Wire Viewer (SWV) (PSoC 3)\r
+* - Saves the boost reference selection and sets it to internal\r
*\r
* Parameters:\r
* None\r
********************************************************************************\r
*\r
* Summary:\r
-* This API is used for restoring device configurations after wakeup from Sleep\r
+* This API is used for restoring the device configurations after wakeup from the Sleep\r
* and Hibernate low power modes:\r
-* - Restores SC/CT routing connections\r
-* - Restores enable state of Serial Wire Viewer (SWV) (PSoC 3)\r
-* - Restore boost reference selection\r
+* - Restores the SC/CT routing connections\r
+* - Restores the enable state of the Serial Wire Viewer (SWV) (PSoC 3)\r
+* - Restores the boost reference selection\r
*\r
* Parameters:\r
* None\r
cyPmBackup.lvidEn = CY_PM_ENABLED;\r
cyPmBackup.lvidTrip = CY_VD_LVI_TRIP_REG & CY_VD_LVI_TRIP_LVID_MASK;\r
\r
- /* Save state of reset device at a specified Vddd threshold */\r
+ /* Save state of reset device at specified Vddd threshold */\r
cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \\r
CY_PM_DISABLED : CY_PM_ENABLED;\r
\r
cyPmBackup.lviaEn = CY_PM_ENABLED;\r
cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u;\r
\r
- /* Save state of reset device at a specified Vdda threshold */\r
+ /* Save state of reset device at specified Vdda threshold */\r
cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \\r
CY_PM_DISABLED : CY_PM_ENABLED;\r
\r
********************************************************************************\r
*\r
* Summary:\r
-* Restores analog and digital LVI and HVI configuration.\r
+* Restores the analog and digital LVI and HVI configuration.\r
*\r
* Parameters:\r
* None\r
/*******************************************************************************\r
* File Name: cyPm.h\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* Provides the function definitions for the power management API.\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
#if(CY_PSOC3)\r
\r
- /* Wake up time for the Sleep mode */\r
+ /* Wake up time for Sleep mode */\r
#define PM_SLEEP_TIME_ONE_PPS (0x01u)\r
#define PM_SLEEP_TIME_CTW_2MS (0x02u)\r
#define PM_SLEEP_TIME_CTW_4MS (0x03u)\r
/* Difference between parameter's value and register's one */\r
#define CY_PM_FTW_INTERVAL_SHIFT (0x000Eu)\r
\r
- /* Wake up time for the Alternate Active mode */\r
+ /* Wake up time for Alternate Active mode */\r
#define PM_ALT_ACT_TIME_ONE_PPS (0x0001u)\r
#define PM_ALT_ACT_TIME_CTW_2MS (0x0002u)\r
#define PM_ALT_ACT_TIME_CTW_4MS (0x0003u)\r
#endif /* (CY_PSOC3) */\r
\r
\r
-/* Wake up sources for the Sleep mode */\r
+/* Wake up sources for Sleep mode */\r
#define PM_SLEEP_SRC_COMPARATOR0 (0x0001u)\r
#define PM_SLEEP_SRC_COMPARATOR1 (0x0002u)\r
#define PM_SLEEP_SRC_COMPARATOR2 (0x0004u)\r
#define PM_SLEEP_SRC_ONE_PPS (0x0800u)\r
#define PM_SLEEP_SRC_LCD (0x1000u)\r
\r
-/* Wake up sources for the Alternate Active mode */\r
+/* Wake up sources for Alternate Active mode */\r
#define PM_ALT_ACT_SRC_COMPARATOR0 (0x0001u)\r
#define PM_ALT_ACT_SRC_COMPARATOR1 (0x0002u)\r
#define PM_ALT_ACT_SRC_COMPARATOR2 (0x0004u)\r
#define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (5u)\r
\r
\r
-/* Delay line bandgap current settling time starting from a wakeup event */\r
+/* Delay line bandgap current settling time starting from wakeup event */\r
#define CY_PM_CLK_DELAY_BANDGAP_SETTLE_US (50u)\r
\r
/* Delay line internal bias settling */\r
\r
#if(CY_PSOC5)\r
\r
- /* The CPU clock is directly derived from bus clock */\r
+ /* CPU clock is directly derived from bus clock */\r
#define CY_PM_GET_CPU_FREQ_MHZ (cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK])\r
\r
#endif /* (CY_PSOC5) */\r
/*******************************************************************************\r
* The low power mode entry is different for PSoC 3 and PSoC 5 devices. The low\r
* power modes in PSoC 5 devices are invoked by Wait-For-Interrupt (WFI)\r
-* instruction. The ARM compilers has __wfi() instristic that inserts a WFI\r
+* instruction. The ARM compilers has __wfi() intrinsic that inserts a WFI\r
* instruction into the instruction stream generated by the compiler. The GCC\r
* compiler has to execute assembly language instruction.\r
*******************************************************************************/\r
/*******************************************************************************\r
* This macro defines the IMO frequency that will be set by CyPmSaveClocks()\r
* function based on Enable Fast IMO during Startup option from the DWR file.\r
-* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering\r
+* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering the\r
* low power mode and restore IMO back to the value set by CyPmSaveClocks()\r
* immediately on wakeup.\r
*******************************************************************************/\r
/* CyPmSaveClocks()/CyPmRestoreClocks() */\r
uint8 enClkA; /* Analog clocks enable */\r
uint8 enClkD; /* Digital clocks enable */\r
- uint8 masterClkSrc; /* The Master clock source */\r
+ uint8 masterClkSrc; /* Master clock source */\r
uint8 imoFreq; /* IMO frequency (reg's value) */\r
uint8 imoUsbClk; /* IMO USB CLK (reg's value) */\r
uint8 flashWaitCycles; /* Flash wait cycles */\r
uint8 clkImoSrc;\r
uint8 imo2x; /* IMO doubler enable state */\r
uint8 clkSyncDiv; /* Master clk divider */\r
- uint16 clkBusDiv; /* The clk_bus divider */\r
+ uint16 clkBusDiv; /* clk_bus divider */\r
uint8 pllEnableState; /* PLL enable state */\r
uint8 xmhzEnableState; /* XM HZ enable state */\r
uint8 clkDistDelay; /* Delay for clk_bus and ACLKs */\r
#define CY_PM_BOOST_CR2_REG (* (reg8 *) CYREG_BOOST_CR2 )\r
#define CY_PM_BOOST_CR2_PTR ( (reg8 *) CYREG_BOOST_CR2 )\r
\r
+#if(CY_PSOC3)\r
+\r
+ /* Interrrupt Controller Configuration and Status Register */\r
+ #define CY_PM_INTC_CSR_EN_REG (* (reg8 *) CYREG_INTC_CSR_EN )\r
+ #define CY_PM_INTC_CSR_EN_PTR ( (reg8 *) CYREG_INTC_CSR_EN )\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
\r
/***************************************\r
* Register Constants\r
#define CY_PM_CLKDIST_IMO_OUT_IMO (0x00u)\r
#define CY_PM_CLKDIST_IMO2X_SRC (0x40u)\r
\r
-/* Waiting for the hibernate/sleep regulator to stabilize */\r
+#define CY_PM_CLKDIST_PLL_SRC_MASK (0x03u)\r
+#define CY_PM_CLKDIST_PLL_SRC_IMO (0x00u)\r
+#define CY_PM_CLKDIST_PLL_SRC_XTAL (0x01u)\r
+#define CY_PM_CLKDIST_PLL_SRC_DSI (0x02u)\r
+\r
+/* Waiting for hibernate/sleep regulator to stabilize */\r
#define CY_PM_MODE_CSR_PWRUP_PULSE_Q (0x08u)\r
\r
#define CY_PM_MODE_CSR_ACTIVE (0x00u) /* Active power mode */\r
/* I2C regulator backup enable */\r
#define CY_PM_PWRSYS_CR1_I2CREG_BACKUP (0x04u)\r
\r
-/* When set, prepares the system to disable the LDO-A */\r
+/* When set, prepares system to disable LDO-A */\r
#define CY_PM_PWRSYS_CR1_LDOA_ISO (0x01u)\r
\r
-/* When set, disables the analog LDO regulator */\r
+/* When set, disables analog LDO regulator */\r
#define CY_PM_PWRSYS_CR1_LDOA_DIS (0x02u)\r
\r
#define CY_PM_PWRSYS_WAKE_TR2_VCCD_CLK_DET (0x04u)\r
/* Bus Clock divider to divide-by-one */\r
#define CY_PM_BUS_CLK_DIV_BY_ONE (0x00u)\r
\r
-/* HVI/LVI feature on the external analog and digital supply mask */\r
+/* HVI/LVI feature on external analog and digital supply mask */\r
#define CY_PM_RESET_CR1_HVI_LVI_EN_MASK (0x07u)\r
\r
-/* The high-voltage-interrupt feature on the external analog supply */\r
+/* High-voltage-interrupt feature on external analog supply */\r
#define CY_PM_RESET_CR1_HVIA_EN (0x04u)\r
\r
-/* The low-voltage-interrupt feature on the external analog supply */\r
+/* Low-voltage-interrupt feature on external analog supply */\r
#define CY_PM_RESET_CR1_LVIA_EN (0x02u)\r
\r
-/* The low-voltage-interrupt feature on the external digital supply */\r
+/* Low-voltage-interrupt feature on external digital supply */\r
#define CY_PM_RESET_CR1_LVID_EN (0x01u)\r
\r
-/* Allows the system to program delays on clk_sync_d */\r
+/* Allows system to program delays on clk_sync_d */\r
#define CY_PM_CLKDIST_DELAY_EN (0x04u)\r
\r
\r
#endif /* (CY_PSOC3) */\r
\r
\r
-/* Disable the sleep regulator and shorts vccd to vpwrsleep */\r
+/* Disables sleep regulator and shorts vccd to vpwrsleep */\r
#define CY_PM_PWRSYS_SLP_TR_BYPASS (0x10u)\r
\r
/* Boost Control 2: Select external precision reference */\r
\r
#endif /* (CY_PSOC5) */\r
\r
+#if(CY_PSOC3)\r
+\r
+ /* Interrrupt Controller Configuration and Status Register */\r
+ #define CY_PM_INTC_CSR_EN_CLK (0x01u)\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
+/*******************************************************************************\r
+* Lock Status Flag. If lock is acquired this flag will stay set (regardless of\r
+* whether lock is subsequently lost) until it is read. Upon reading it will\r
+* clear. If lock is still true then the bit will simply set again. If lock\r
+* happens to be false when the clear on read occurs then the bit will stay\r
+* cleared until the next lock event.\r
+*******************************************************************************/\r
+#define CY_PM_FASTCLK_PLL_LOCKED (0x01u)\r
+\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30\r
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.30\r
+*\r
+* If the obsoleted macro definitions intended for use in the application use the\r
+* following scheme, redefine your own versions of these definitions:\r
+* #ifdef <OBSOLETED_DEFINE>\r
+* #undef <OBSOLETED_DEFINE>\r
+* #define <OBSOLETED_DEFINE> (<New Value>)\r
+* #endif\r
+*\r
+* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* used in the application and their modification might lead to unexpected\r
+* consequences.\r
*******************************************************************************/\r
#if(CY_PSOC3)\r
\r
/*******************************************************************************\r
* FILENAME: cydevice.h\r
* OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator 3.0 Component Pack 7\r
+* PSoC Creator 3.1\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
/*******************************************************************************\r
* FILENAME: cydevice_trm.h\r
* \r
-* PSoC Creator 3.0 Component Pack 7\r
+* PSoC Creator 3.1\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
/*******************************************************************************\r
* FILENAME: cydevicegnu.inc\r
* OBSOLETE: Do not use this file. Use the _trm version instead.\r
-* PSoC Creator 3.0 Component Pack 7\r
+* PSoC Creator 3.1\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
/*******************************************************************************\r
* FILENAME: cydevicegnu_trm.inc\r
* \r
-* PSoC Creator 3.0 Component Pack 7\r
+* PSoC Creator 3.1\r
*\r
* DESCRIPTION:\r
* This file provides all of the address values for the entire PSoC device.\r
;\r
; FILENAME: cydeviceiar.inc\r
; OBSOLETE: Do not use this file. Use the _trm version instead.\r
-; PSoC Creator 3.0 Component Pack 7\r
+; PSoC Creator 3.1\r
;\r
; DESCRIPTION:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
; FILENAME: cydeviceiar_trm.inc\r
; \r
-; PSoC Creator 3.0 Component Pack 7\r
+; PSoC Creator 3.1\r
;\r
; DESCRIPTION:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
; FILENAME: cydevicerv.inc\r
; OBSOLETE: Do not use this file. Use the _trm version instead.\r
-; PSoC Creator 3.0 Component Pack 7\r
+; PSoC Creator 3.1\r
;\r
; DESCRIPTION:\r
; This file provides all of the address values for the entire PSoC device.\r
;\r
; FILENAME: cydevicerv_trm.inc\r
; \r
-; PSoC Creator 3.0 Component Pack 7\r
+; PSoC Creator 3.1\r
;\r
; DESCRIPTION:\r
; This file provides all of the address values for the entire PSoC device.\r
#include <cydevice.h>\r
#include <cydevice_trm.h>\r
\r
+/* USBFS_arb_int */\r
+#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_arb_int__INTC_MASK 0x400000u\r
+#define USBFS_arb_int__INTC_NUMBER 22u\r
+#define USBFS_arb_int__INTC_PRIOR_NUM 7u\r
+#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22\r
+#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
/* USBFS_bus_reset */\r
#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
-/* USBFS_arb_int */\r
-#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_arb_int__INTC_MASK 0x400000u\r
-#define USBFS_arb_int__INTC_NUMBER 22u\r
-#define USBFS_arb_int__INTC_PRIOR_NUM 7u\r
-#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22\r
-#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+/* USBFS_Dm */\r
+#define USBFS_Dm__0__MASK 0x80u\r
+#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1\r
+#define USBFS_Dm__0__PORT 15u\r
+#define USBFS_Dm__0__SHIFT 7\r
+#define USBFS_Dm__AG CYREG_PRT15_AG\r
+#define USBFS_Dm__AMUX CYREG_PRT15_AMUX\r
+#define USBFS_Dm__BIE CYREG_PRT15_BIE\r
+#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK\r
+#define USBFS_Dm__BYP CYREG_PRT15_BYP\r
+#define USBFS_Dm__CTL CYREG_PRT15_CTL\r
+#define USBFS_Dm__DM0 CYREG_PRT15_DM0\r
+#define USBFS_Dm__DM1 CYREG_PRT15_DM1\r
+#define USBFS_Dm__DM2 CYREG_PRT15_DM2\r
+#define USBFS_Dm__DR CYREG_PRT15_DR\r
+#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS\r
+#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
+#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN\r
+#define USBFS_Dm__MASK 0x80u\r
+#define USBFS_Dm__PORT 15u\r
+#define USBFS_Dm__PRT CYREG_PRT15_PRT\r
+#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
+#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
+#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
+#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
+#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
+#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
+#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
+#define USBFS_Dm__PS CYREG_PRT15_PS\r
+#define USBFS_Dm__SHIFT 7\r
+#define USBFS_Dm__SLW CYREG_PRT15_SLW\r
+\r
+/* USBFS_Dp */\r
+#define USBFS_Dp__0__MASK 0x40u\r
+#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0\r
+#define USBFS_Dp__0__PORT 15u\r
+#define USBFS_Dp__0__SHIFT 6\r
+#define USBFS_Dp__AG CYREG_PRT15_AG\r
+#define USBFS_Dp__AMUX CYREG_PRT15_AMUX\r
+#define USBFS_Dp__BIE CYREG_PRT15_BIE\r
+#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK\r
+#define USBFS_Dp__BYP CYREG_PRT15_BYP\r
+#define USBFS_Dp__CTL CYREG_PRT15_CTL\r
+#define USBFS_Dp__DM0 CYREG_PRT15_DM0\r
+#define USBFS_Dp__DM1 CYREG_PRT15_DM1\r
+#define USBFS_Dp__DM2 CYREG_PRT15_DM2\r
+#define USBFS_Dp__DR CYREG_PRT15_DR\r
+#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS\r
+#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT\r
+#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
+#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN\r
+#define USBFS_Dp__MASK 0x40u\r
+#define USBFS_Dp__PORT 15u\r
+#define USBFS_Dp__PRT CYREG_PRT15_PRT\r
+#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
+#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
+#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
+#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
+#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
+#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
+#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
+#define USBFS_Dp__PS CYREG_PRT15_PS\r
+#define USBFS_Dp__SHIFT 6\r
+#define USBFS_Dp__SLW CYREG_PRT15_SLW\r
+#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15\r
+\r
+/* USBFS_dp_int */\r
+#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_dp_int__INTC_MASK 0x1000u\r
+#define USBFS_dp_int__INTC_NUMBER 12u\r
+#define USBFS_dp_int__INTC_PRIOR_NUM 7u\r
+#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12\r
+#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_0 */\r
+#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_0__INTC_MASK 0x1000000u\r
+#define USBFS_ep_0__INTC_NUMBER 24u\r
+#define USBFS_ep_0__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24\r
+#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_1 */\r
+#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_1__INTC_MASK 0x01u\r
+#define USBFS_ep_1__INTC_NUMBER 0u\r
+#define USBFS_ep_1__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
+#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_2 */\r
+#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define USBFS_ep_2__INTC_MASK 0x02u\r
+#define USBFS_ep_2__INTC_NUMBER 1u\r
+#define USBFS_ep_2__INTC_PRIOR_NUM 7u\r
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
+#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
/* USBFS_sof_int */\r
#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
-/* SCSI_Out_DBx */\r
-#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__0__MASK 0x08u\r
-#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC3\r
-#define SCSI_Out_DBx__0__PORT 6u\r
-#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__0__SHIFT 3\r
-#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__1__MASK 0x04u\r
-#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC2\r
-#define SCSI_Out_DBx__1__PORT 6u\r
-#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__1__SHIFT 2\r
-#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__2__MASK 0x02u\r
-#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC1\r
-#define SCSI_Out_DBx__2__PORT 6u\r
-#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__2__SHIFT 1\r
-#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__3__MASK 0x01u\r
-#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC0\r
-#define SCSI_Out_DBx__3__PORT 6u\r
-#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__3__SHIFT 0\r
-#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__4__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__4__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__4__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__4__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__4__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__4__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__4__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__4__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__4__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__4__MASK 0x80u\r
-#define SCSI_Out_DBx__4__PC CYREG_PRT4_PC7\r
-#define SCSI_Out_DBx__4__PORT 4u\r
-#define SCSI_Out_DBx__4__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__4__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__4__SHIFT 7\r
-#define SCSI_Out_DBx__4__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__5__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__5__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__5__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__5__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__5__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__5__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__5__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__5__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__5__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__5__MASK 0x40u\r
-#define SCSI_Out_DBx__5__PC CYREG_PRT4_PC6\r
-#define SCSI_Out_DBx__5__PORT 4u\r
-#define SCSI_Out_DBx__5__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__5__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__5__SHIFT 6\r
-#define SCSI_Out_DBx__5__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__6__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__6__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__6__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__6__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__6__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__6__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__6__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__6__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__6__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__6__MASK 0x20u\r
-#define SCSI_Out_DBx__6__PC CYREG_PRT4_PC5\r
-#define SCSI_Out_DBx__6__PORT 4u\r
-#define SCSI_Out_DBx__6__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__6__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__6__SHIFT 5\r
-#define SCSI_Out_DBx__6__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__7__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__7__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__7__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__7__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__7__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__7__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__7__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__7__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__7__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__7__MASK 0x10u\r
-#define SCSI_Out_DBx__7__PC CYREG_PRT4_PC4\r
-#define SCSI_Out_DBx__7__PORT 4u\r
-#define SCSI_Out_DBx__7__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__7__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__7__SHIFT 4\r
-#define SCSI_Out_DBx__7__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__DB0__MASK 0x08u\r
-#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC3\r
-#define SCSI_Out_DBx__DB0__PORT 6u\r
-#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB0__SHIFT 3\r
-#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__DB1__MASK 0x04u\r
-#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC2\r
-#define SCSI_Out_DBx__DB1__PORT 6u\r
-#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB1__SHIFT 2\r
-#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__DB2__MASK 0x02u\r
-#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC1\r
-#define SCSI_Out_DBx__DB2__PORT 6u\r
-#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB2__SHIFT 1\r
-#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG\r
-#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX\r
-#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE\r
-#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK\r
-#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP\r
-#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL\r
-#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0\r
-#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1\r
-#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2\r
-#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR\r
-#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS\r
-#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN\r
-#define SCSI_Out_DBx__DB3__MASK 0x01u\r
-#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC0\r
-#define SCSI_Out_DBx__DB3__PORT 6u\r
-#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT\r
-#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
-#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
-#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
-#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS\r
-#define SCSI_Out_DBx__DB3__SHIFT 0\r
-#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW\r
-#define SCSI_Out_DBx__DB4__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__DB4__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__DB4__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__DB4__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__DB4__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__DB4__MASK 0x80u\r
-#define SCSI_Out_DBx__DB4__PC CYREG_PRT4_PC7\r
-#define SCSI_Out_DBx__DB4__PORT 4u\r
-#define SCSI_Out_DBx__DB4__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__DB4__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB4__SHIFT 7\r
-#define SCSI_Out_DBx__DB4__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__DB5__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__DB5__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__DB5__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__DB5__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__DB5__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__DB5__MASK 0x40u\r
-#define SCSI_Out_DBx__DB5__PC CYREG_PRT4_PC6\r
-#define SCSI_Out_DBx__DB5__PORT 4u\r
-#define SCSI_Out_DBx__DB5__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__DB5__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB5__SHIFT 6\r
-#define SCSI_Out_DBx__DB5__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__DB6__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__DB6__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__DB6__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__DB6__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__DB6__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__DB6__MASK 0x20u\r
-#define SCSI_Out_DBx__DB6__PC CYREG_PRT4_PC5\r
-#define SCSI_Out_DBx__DB6__PORT 4u\r
-#define SCSI_Out_DBx__DB6__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__DB6__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB6__SHIFT 5\r
-#define SCSI_Out_DBx__DB6__SLW CYREG_PRT4_SLW\r
-#define SCSI_Out_DBx__DB7__AG CYREG_PRT4_AG\r
-#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT4_AMUX\r
-#define SCSI_Out_DBx__DB7__BIE CYREG_PRT4_BIE\r
-#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT4_BIT_MASK\r
-#define SCSI_Out_DBx__DB7__BYP CYREG_PRT4_BYP\r
-#define SCSI_Out_DBx__DB7__CTL CYREG_PRT4_CTL\r
-#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT4_DM0\r
-#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT4_DM1\r
-#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT4_DM2\r
-#define SCSI_Out_DBx__DB7__DR CYREG_PRT4_DR\r
-#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT4_INP_DIS\r
-#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
-#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT4_LCD_EN\r
-#define SCSI_Out_DBx__DB7__MASK 0x10u\r
-#define SCSI_Out_DBx__DB7__PC CYREG_PRT4_PC4\r
-#define SCSI_Out_DBx__DB7__PORT 4u\r
-#define SCSI_Out_DBx__DB7__PRT CYREG_PRT4_PRT\r
-#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
-#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
-#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
-#define SCSI_Out_DBx__DB7__PS CYREG_PRT4_PS\r
-#define SCSI_Out_DBx__DB7__SHIFT 4\r
-#define SCSI_Out_DBx__DB7__SLW CYREG_PRT4_SLW\r
-\r
-/* USBFS_dp_int */\r
-#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_dp_int__INTC_MASK 0x1000u\r
-#define USBFS_dp_int__INTC_NUMBER 12u\r
-#define USBFS_dp_int__INTC_PRIOR_NUM 7u\r
-#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12\r
-#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_0 */\r
-#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_0__INTC_MASK 0x1000000u\r
-#define USBFS_ep_0__INTC_NUMBER 24u\r
-#define USBFS_ep_0__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24\r
-#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_1 */\r
-#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_1__INTC_MASK 0x01u\r
-#define USBFS_ep_1__INTC_NUMBER 0u\r
-#define USBFS_ep_1__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
-#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_2 */\r
-#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
-#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
-#define USBFS_ep_2__INTC_MASK 0x02u\r
-#define USBFS_ep_2__INTC_NUMBER 1u\r
-#define USBFS_ep_2__INTC_PRIOR_NUM 7u\r
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
-#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
-#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
-\r
-/* SD_PULLUP */\r
-#define SD_PULLUP__0__MASK 0x02u\r
-#define SD_PULLUP__0__PC CYREG_PRT3_PC1\r
-#define SD_PULLUP__0__PORT 3u\r
-#define SD_PULLUP__0__SHIFT 1\r
-#define SD_PULLUP__1__MASK 0x04u\r
-#define SD_PULLUP__1__PC CYREG_PRT3_PC2\r
-#define SD_PULLUP__1__PORT 3u\r
-#define SD_PULLUP__1__SHIFT 2\r
-#define SD_PULLUP__2__MASK 0x08u\r
-#define SD_PULLUP__2__PC CYREG_PRT3_PC3\r
-#define SD_PULLUP__2__PORT 3u\r
-#define SD_PULLUP__2__SHIFT 3\r
-#define SD_PULLUP__3__MASK 0x10u\r
-#define SD_PULLUP__3__PC CYREG_PRT3_PC4\r
-#define SD_PULLUP__3__PORT 3u\r
-#define SD_PULLUP__3__SHIFT 4\r
-#define SD_PULLUP__4__MASK 0x20u\r
-#define SD_PULLUP__4__PC CYREG_PRT3_PC5\r
-#define SD_PULLUP__4__PORT 3u\r
-#define SD_PULLUP__4__SHIFT 5\r
-#define SD_PULLUP__AG CYREG_PRT3_AG\r
-#define SD_PULLUP__AMUX CYREG_PRT3_AMUX\r
-#define SD_PULLUP__BIE CYREG_PRT3_BIE\r
-#define SD_PULLUP__BIT_MASK CYREG_PRT3_BIT_MASK\r
-#define SD_PULLUP__BYP CYREG_PRT3_BYP\r
-#define SD_PULLUP__CTL CYREG_PRT3_CTL\r
-#define SD_PULLUP__DM0 CYREG_PRT3_DM0\r
-#define SD_PULLUP__DM1 CYREG_PRT3_DM1\r
-#define SD_PULLUP__DM2 CYREG_PRT3_DM2\r
-#define SD_PULLUP__DR CYREG_PRT3_DR\r
-#define SD_PULLUP__INP_DIS CYREG_PRT3_INP_DIS\r
-#define SD_PULLUP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
-#define SD_PULLUP__LCD_EN CYREG_PRT3_LCD_EN\r
-#define SD_PULLUP__MASK 0x3Eu\r
-#define SD_PULLUP__PORT 3u\r
-#define SD_PULLUP__PRT CYREG_PRT3_PRT\r
-#define SD_PULLUP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
-#define SD_PULLUP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
-#define SD_PULLUP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
-#define SD_PULLUP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
-#define SD_PULLUP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
-#define SD_PULLUP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
-#define SD_PULLUP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
-#define SD_PULLUP__PS CYREG_PRT3_PS\r
-#define SD_PULLUP__SHIFT 1\r
-#define SD_PULLUP__SLW CYREG_PRT3_SLW\r
-\r
/* USBFS_USB */\r
#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG\r
#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG\r
#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES\r
#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB\r
#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG\r
+#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE\r
+#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE\r
#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT\r
#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR\r
#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0\r
#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5\r
#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6\r
#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7\r
-#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE\r
-#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE\r
#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE\r
#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5\r
#define USBFS_USB__PM_ACT_MSK 0x01u\r
#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5\r
#define USBFS_USB__PM_STBY_MSK 0x01u\r
+#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN\r
+#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR\r
#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0\r
#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1\r
#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0\r
#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0\r
#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1\r
#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0\r
-#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN\r
-#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR\r
#define USBFS_USB__SOF0 CYREG_USB_SOF0\r
#define USBFS_USB__SOF1 CYREG_USB_SOF1\r
+#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN\r
#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0\r
#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1\r
-#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN\r
\r
/* SCSI_Out */\r
#define SCSI_Out__0__AG CYREG_PRT4_AG\r
#define SCSI_Out__SEL__SHIFT 3\r
#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW\r
\r
-/* USBFS_Dm */\r
-#define USBFS_Dm__0__MASK 0x80u\r
-#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1\r
-#define USBFS_Dm__0__PORT 15u\r
-#define USBFS_Dm__0__SHIFT 7\r
-#define USBFS_Dm__AG CYREG_PRT15_AG\r
-#define USBFS_Dm__AMUX CYREG_PRT15_AMUX\r
-#define USBFS_Dm__BIE CYREG_PRT15_BIE\r
-#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK\r
-#define USBFS_Dm__BYP CYREG_PRT15_BYP\r
-#define USBFS_Dm__CTL CYREG_PRT15_CTL\r
-#define USBFS_Dm__DM0 CYREG_PRT15_DM0\r
-#define USBFS_Dm__DM1 CYREG_PRT15_DM1\r
-#define USBFS_Dm__DM2 CYREG_PRT15_DM2\r
-#define USBFS_Dm__DR CYREG_PRT15_DR\r
-#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS\r
-#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
-#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN\r
-#define USBFS_Dm__MASK 0x80u\r
-#define USBFS_Dm__PORT 15u\r
-#define USBFS_Dm__PRT CYREG_PRT15_PRT\r
-#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
-#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
-#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
-#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
-#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
-#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
-#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
-#define USBFS_Dm__PS CYREG_PRT15_PS\r
-#define USBFS_Dm__SHIFT 7\r
-#define USBFS_Dm__SLW CYREG_PRT15_SLW\r
+/* SCSI_Out_DBx */\r
+#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__0__MASK 0x08u\r
+#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC3\r
+#define SCSI_Out_DBx__0__PORT 6u\r
+#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__0__SHIFT 3\r
+#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__1__MASK 0x04u\r
+#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC2\r
+#define SCSI_Out_DBx__1__PORT 6u\r
+#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__1__SHIFT 2\r
+#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__2__MASK 0x02u\r
+#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC1\r
+#define SCSI_Out_DBx__2__PORT 6u\r
+#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__2__SHIFT 1\r
+#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__3__MASK 0x01u\r
+#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC0\r
+#define SCSI_Out_DBx__3__PORT 6u\r
+#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__3__SHIFT 0\r
+#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__4__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__4__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__4__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__4__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__4__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__4__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__4__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__4__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__4__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__4__MASK 0x80u\r
+#define SCSI_Out_DBx__4__PC CYREG_PRT4_PC7\r
+#define SCSI_Out_DBx__4__PORT 4u\r
+#define SCSI_Out_DBx__4__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__4__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__4__SHIFT 7\r
+#define SCSI_Out_DBx__4__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__5__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__5__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__5__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__5__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__5__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__5__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__5__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__5__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__5__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__5__MASK 0x40u\r
+#define SCSI_Out_DBx__5__PC CYREG_PRT4_PC6\r
+#define SCSI_Out_DBx__5__PORT 4u\r
+#define SCSI_Out_DBx__5__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__5__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__5__SHIFT 6\r
+#define SCSI_Out_DBx__5__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__6__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__6__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__6__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__6__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__6__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__6__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__6__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__6__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__6__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__6__MASK 0x20u\r
+#define SCSI_Out_DBx__6__PC CYREG_PRT4_PC5\r
+#define SCSI_Out_DBx__6__PORT 4u\r
+#define SCSI_Out_DBx__6__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__6__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__6__SHIFT 5\r
+#define SCSI_Out_DBx__6__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__7__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__7__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__7__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__7__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__7__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__7__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__7__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__7__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__7__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__7__MASK 0x10u\r
+#define SCSI_Out_DBx__7__PC CYREG_PRT4_PC4\r
+#define SCSI_Out_DBx__7__PORT 4u\r
+#define SCSI_Out_DBx__7__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__7__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__7__SHIFT 4\r
+#define SCSI_Out_DBx__7__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__DB0__MASK 0x08u\r
+#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC3\r
+#define SCSI_Out_DBx__DB0__PORT 6u\r
+#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__DB0__SHIFT 3\r
+#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__DB1__MASK 0x04u\r
+#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC2\r
+#define SCSI_Out_DBx__DB1__PORT 6u\r
+#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__DB1__SHIFT 2\r
+#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__DB2__MASK 0x02u\r
+#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC1\r
+#define SCSI_Out_DBx__DB2__PORT 6u\r
+#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__DB2__SHIFT 1\r
+#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG\r
+#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR\r
+#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out_DBx__DB3__MASK 0x01u\r
+#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC0\r
+#define SCSI_Out_DBx__DB3__PORT 6u\r
+#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS\r
+#define SCSI_Out_DBx__DB3__SHIFT 0\r
+#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out_DBx__DB4__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__DB4__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__DB4__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__DB4__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__DB4__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__DB4__MASK 0x80u\r
+#define SCSI_Out_DBx__DB4__PC CYREG_PRT4_PC7\r
+#define SCSI_Out_DBx__DB4__PORT 4u\r
+#define SCSI_Out_DBx__DB4__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__DB4__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__DB4__SHIFT 7\r
+#define SCSI_Out_DBx__DB4__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__DB5__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__DB5__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__DB5__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__DB5__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__DB5__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__DB5__MASK 0x40u\r
+#define SCSI_Out_DBx__DB5__PC CYREG_PRT4_PC6\r
+#define SCSI_Out_DBx__DB5__PORT 4u\r
+#define SCSI_Out_DBx__DB5__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__DB5__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__DB5__SHIFT 6\r
+#define SCSI_Out_DBx__DB5__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__DB6__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__DB6__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__DB6__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__DB6__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__DB6__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__DB6__MASK 0x20u\r
+#define SCSI_Out_DBx__DB6__PC CYREG_PRT4_PC5\r
+#define SCSI_Out_DBx__DB6__PORT 4u\r
+#define SCSI_Out_DBx__DB6__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__DB6__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__DB6__SHIFT 5\r
+#define SCSI_Out_DBx__DB6__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out_DBx__DB7__AG CYREG_PRT4_AG\r
+#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out_DBx__DB7__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out_DBx__DB7__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out_DBx__DB7__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out_DBx__DB7__DR CYREG_PRT4_DR\r
+#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out_DBx__DB7__MASK 0x10u\r
+#define SCSI_Out_DBx__DB7__PC CYREG_PRT4_PC4\r
+#define SCSI_Out_DBx__DB7__PORT 4u\r
+#define SCSI_Out_DBx__DB7__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out_DBx__DB7__PS CYREG_PRT4_PS\r
+#define SCSI_Out_DBx__DB7__SHIFT 4\r
+#define SCSI_Out_DBx__DB7__SLW CYREG_PRT4_SLW\r
\r
-/* USBFS_Dp */\r
-#define USBFS_Dp__0__MASK 0x40u\r
-#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0\r
-#define USBFS_Dp__0__PORT 15u\r
-#define USBFS_Dp__0__SHIFT 6\r
-#define USBFS_Dp__AG CYREG_PRT15_AG\r
-#define USBFS_Dp__AMUX CYREG_PRT15_AMUX\r
-#define USBFS_Dp__BIE CYREG_PRT15_BIE\r
-#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK\r
-#define USBFS_Dp__BYP CYREG_PRT15_BYP\r
-#define USBFS_Dp__CTL CYREG_PRT15_CTL\r
-#define USBFS_Dp__DM0 CYREG_PRT15_DM0\r
-#define USBFS_Dp__DM1 CYREG_PRT15_DM1\r
-#define USBFS_Dp__DM2 CYREG_PRT15_DM2\r
-#define USBFS_Dp__DR CYREG_PRT15_DR\r
-#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS\r
-#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT\r
-#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG\r
-#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN\r
-#define USBFS_Dp__MASK 0x40u\r
-#define USBFS_Dp__PORT 15u\r
-#define USBFS_Dp__PRT CYREG_PRT15_PRT\r
-#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL\r
-#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN\r
-#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0\r
-#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1\r
-#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0\r
-#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1\r
-#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT\r
-#define USBFS_Dp__PS CYREG_PRT15_PS\r
-#define USBFS_Dp__SHIFT 6\r
-#define USBFS_Dp__SLW CYREG_PRT15_SLW\r
-#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15\r
+/* SD_PULLUP */\r
+#define SD_PULLUP__0__MASK 0x02u\r
+#define SD_PULLUP__0__PC CYREG_PRT3_PC1\r
+#define SD_PULLUP__0__PORT 3u\r
+#define SD_PULLUP__0__SHIFT 1\r
+#define SD_PULLUP__1__MASK 0x04u\r
+#define SD_PULLUP__1__PC CYREG_PRT3_PC2\r
+#define SD_PULLUP__1__PORT 3u\r
+#define SD_PULLUP__1__SHIFT 2\r
+#define SD_PULLUP__2__MASK 0x08u\r
+#define SD_PULLUP__2__PC CYREG_PRT3_PC3\r
+#define SD_PULLUP__2__PORT 3u\r
+#define SD_PULLUP__2__SHIFT 3\r
+#define SD_PULLUP__3__MASK 0x10u\r
+#define SD_PULLUP__3__PC CYREG_PRT3_PC4\r
+#define SD_PULLUP__3__PORT 3u\r
+#define SD_PULLUP__3__SHIFT 4\r
+#define SD_PULLUP__4__MASK 0x20u\r
+#define SD_PULLUP__4__PC CYREG_PRT3_PC5\r
+#define SD_PULLUP__4__PORT 3u\r
+#define SD_PULLUP__4__SHIFT 5\r
+#define SD_PULLUP__AG CYREG_PRT3_AG\r
+#define SD_PULLUP__AMUX CYREG_PRT3_AMUX\r
+#define SD_PULLUP__BIE CYREG_PRT3_BIE\r
+#define SD_PULLUP__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_PULLUP__BYP CYREG_PRT3_BYP\r
+#define SD_PULLUP__CTL CYREG_PRT3_CTL\r
+#define SD_PULLUP__DM0 CYREG_PRT3_DM0\r
+#define SD_PULLUP__DM1 CYREG_PRT3_DM1\r
+#define SD_PULLUP__DM2 CYREG_PRT3_DM2\r
+#define SD_PULLUP__DR CYREG_PRT3_DR\r
+#define SD_PULLUP__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_PULLUP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_PULLUP__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_PULLUP__MASK 0x3Eu\r
+#define SD_PULLUP__PORT 3u\r
+#define SD_PULLUP__PRT CYREG_PRT3_PRT\r
+#define SD_PULLUP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_PULLUP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_PULLUP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_PULLUP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_PULLUP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_PULLUP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_PULLUP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_PULLUP__PS CYREG_PRT3_PS\r
+#define SD_PULLUP__SHIFT 1\r
+#define SD_PULLUP__SLW CYREG_PRT3_SLW\r
\r
/* Miscellaneous */\r
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */\r
-#define CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO 0\r
-#define CYDEV_DEBUGGING_DPS_SWD_SWV 6\r
-#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0\r
-#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0\r
-#define CYDEV_CONFIG_FASTBOOT_ENABLED 1\r
-#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u\r
-#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u\r
-#define CYDEV_CHIP_MEMBER_5B 4u\r
-#define CYDEV_CHIP_FAMILY_PSOC5 3u\r
-#define CYDEV_CHIP_DIE_PSOC5LP 4u\r
-#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP\r
-#define CYDEV_BOOTLOADER_IO_COMP_USBFS 1\r
#define BCLK__BUS_CLK__HZ 64000000U\r
#define BCLK__BUS_CLK__KHZ 64000U\r
#define BCLK__BUS_CLK__MHZ 64U\r
+#define CY_VERSION "PSoC Creator 3.1"\r
#define CYDEV_BOOTLOADER_APPLICATIONS 1u\r
#define CYDEV_BOOTLOADER_CHECKSUM_BASIC 0\r
#define CYDEV_BOOTLOADER_CHECKSUM_CRC 1\r
+#define CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO 0\r
+#define CyBtldr_Custom_Interface CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO\r
+#define CYDEV_BOOTLOADER_IO_COMP_USBFS 1\r
+#define CyBtldr_USBFS CYDEV_BOOTLOADER_IO_COMP_USBFS\r
#define CYDEV_BOOTLOADER_IO_COMP CYDEV_BOOTLOADER_IO_COMP_USBFS\r
-#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT\r
#define CYDEV_CHIP_DIE_LEOPARD 1u\r
-#define CYDEV_CHIP_DIE_PANTHER 3u\r
-#define CYDEV_CHIP_DIE_PSOC4A 2u\r
+#define CYDEV_CHIP_DIE_PANTHER 6u\r
+#define CYDEV_CHIP_DIE_PSOC4A 3u\r
+#define CYDEV_CHIP_DIE_PSOC5LP 5u\r
#define CYDEV_CHIP_DIE_UNKNOWN 0u\r
#define CYDEV_CHIP_FAMILY_PSOC3 1u\r
#define CYDEV_CHIP_FAMILY_PSOC4 2u\r
+#define CYDEV_CHIP_FAMILY_PSOC5 3u\r
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u\r
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5\r
#define CYDEV_CHIP_JTAG_ID 0x2E133069u\r
#define CYDEV_CHIP_MEMBER_3A 1u\r
-#define CYDEV_CHIP_MEMBER_4A 2u\r
-#define CYDEV_CHIP_MEMBER_5A 3u\r
+#define CYDEV_CHIP_MEMBER_4A 3u\r
+#define CYDEV_CHIP_MEMBER_4D 2u\r
+#define CYDEV_CHIP_MEMBER_4F 4u\r
+#define CYDEV_CHIP_MEMBER_5A 6u\r
+#define CYDEV_CHIP_MEMBER_5B 5u\r
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u\r
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B\r
+#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED\r
+#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT\r
+#define CYDEV_CHIP_REV_LEOPARD_ES1 0u\r
+#define CYDEV_CHIP_REV_LEOPARD_ES2 1u\r
+#define CYDEV_CHIP_REV_LEOPARD_ES3 3u\r
+#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u\r
+#define CYDEV_CHIP_REV_PANTHER_ES0 0u\r
+#define CYDEV_CHIP_REV_PANTHER_ES1 1u\r
+#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u\r
+#define CYDEV_CHIP_REV_PSOC4A_ES0 17u\r
+#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u\r
+#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u\r
+#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_3A_ES1 0u\r
#define CYDEV_CHIP_REVISION_3A_ES2 1u\r
#define CYDEV_CHIP_REVISION_3A_ES3 3u\r
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u\r
#define CYDEV_CHIP_REVISION_4A_ES0 17u\r
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u\r
+#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_5A_ES0 0u\r
#define CYDEV_CHIP_REVISION_5A_ES1 1u\r
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u\r
#define CYDEV_CHIP_REVISION_5B_ES0 0u\r
+#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u\r
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION\r
-#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REV_PSOC5LP_PRODUCTION\r
-#define CYDEV_CHIP_REV_LEOPARD_ES1 0u\r
-#define CYDEV_CHIP_REV_LEOPARD_ES2 1u\r
-#define CYDEV_CHIP_REV_LEOPARD_ES3 3u\r
-#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u\r
-#define CYDEV_CHIP_REV_PANTHER_ES0 0u\r
-#define CYDEV_CHIP_REV_PANTHER_ES1 1u\r
-#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u\r
-#define CYDEV_CHIP_REV_PSOC4A_ES0 17u\r
-#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u\r
-#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u\r
+#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED\r
+#define CYDEV_CONFIG_FASTBOOT_ENABLED 1\r
+#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0\r
+#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
+#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1\r
+#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2\r
#define CYDEV_CONFIGURATION_COMPRESSED 1\r
#define CYDEV_CONFIGURATION_DMA 0\r
#define CYDEV_CONFIGURATION_ECC 0\r
#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED\r
+#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0\r
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED\r
#define CYDEV_CONFIGURATION_MODE_DMA 2\r
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1\r
-#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
-#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1\r
-#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2\r
-#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV\r
+#define CYDEV_DEBUG_ENABLE_MASK 0x20u\r
+#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG\r
#define CYDEV_DEBUGGING_DPS_Disable 3\r
#define CYDEV_DEBUGGING_DPS_JTAG_4 1\r
#define CYDEV_DEBUGGING_DPS_JTAG_5 0\r
#define CYDEV_DEBUGGING_DPS_SWD 2\r
+#define CYDEV_DEBUGGING_DPS_SWD_SWV 6\r
+#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV\r
#define CYDEV_DEBUGGING_ENABLE 1\r
#define CYDEV_DEBUGGING_XRES 0\r
-#define CYDEV_DEBUG_ENABLE_MASK 0x20u\r
-#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG\r
#define CYDEV_DMA_CHANNELS_AVAILABLE 24u\r
#define CYDEV_ECC_ENABLE 0\r
#define CYDEV_HEAP_SIZE 0x0800\r
#define CYDEV_VDDIO2_MV 5000\r
#define CYDEV_VDDIO3 5.0\r
#define CYDEV_VDDIO3_MV 5000\r
-#define CYDEV_VIO0 5\r
+#define CYDEV_VIO0 5.0\r
#define CYDEV_VIO0_MV 5000\r
-#define CYDEV_VIO1 5\r
+#define CYDEV_VIO1 5.0\r
#define CYDEV_VIO1_MV 5000\r
-#define CYDEV_VIO2 5\r
+#define CYDEV_VIO2 5.0\r
#define CYDEV_VIO2_MV 5000\r
-#define CYDEV_VIO3 5\r
+#define CYDEV_VIO3 5.0\r
#define CYDEV_VIO3_MV 5000\r
-#define CyBtldr_Custom_Interface CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO\r
-#define CyBtldr_USBFS CYDEV_BOOTLOADER_IO_COMP_USBFS\r
+#define CYIPBLOCK_ARM_CM3_VERSION 0\r
+#define CYIPBLOCK_P3_ANAIF_VERSION 0\r
+#define CYIPBLOCK_P3_CAPSENSE_VERSION 0\r
+#define CYIPBLOCK_P3_COMP_VERSION 0\r
+#define CYIPBLOCK_P3_DMA_VERSION 0\r
+#define CYIPBLOCK_P3_DRQ_VERSION 0\r
+#define CYIPBLOCK_P3_EMIF_VERSION 0\r
+#define CYIPBLOCK_P3_I2C_VERSION 0\r
+#define CYIPBLOCK_P3_LCD_VERSION 0\r
+#define CYIPBLOCK_P3_LPF_VERSION 0\r
+#define CYIPBLOCK_P3_PM_VERSION 0\r
+#define CYIPBLOCK_P3_TIMER_VERSION 0\r
+#define CYIPBLOCK_P3_USB_VERSION 0\r
+#define CYIPBLOCK_P3_VIDAC_VERSION 0\r
+#define CYIPBLOCK_P3_VREF_VERSION 0\r
+#define CYIPBLOCK_S8_GPIO_VERSION 0\r
+#define CYIPBLOCK_S8_IRQ_VERSION 0\r
+#define CYIPBLOCK_S8_SAR_VERSION 0\r
+#define CYIPBLOCK_S8_SIO_VERSION 0\r
+#define CYIPBLOCK_S8_UDB_VERSION 0\r
#define DMA_CHANNELS_USED__MASK0 0x00000000u\r
#define CYDEV_BOOTLOADER_ENABLE 1\r
\r
/*******************************************************************************\r
* FILENAME: cyfitter_cfg.c\r
-* PSoC Creator 3.0 Component Pack 7\r
+* PSoC Creator 3.1\r
*\r
* Description:\r
* This file is automatically generated by PSoC Creator with device \r
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)\r
{\r
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];\r
- CYMEMZERO(ms->address, (uint32)(ms->size));\r
+ CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));\r
}\r
\r
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);\r
/*******************************************************************************\r
* FILENAME: cyfitter_cfg.h\r
-* PSoC Creator 3.0 Component Pack 7\r
+* PSoC Creator 3.1\r
*\r
* Description:\r
* This file is automatically generated by PSoC Creator.\r
.include "cydevicegnu.inc"\r
.include "cydevicegnu_trm.inc"\r
\r
+/* USBFS_arb_int */\r
+.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_arb_int__INTC_MASK, 0x400000\r
+.set USBFS_arb_int__INTC_NUMBER, 22\r
+.set USBFS_arb_int__INTC_PRIOR_NUM, 7\r
+.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22\r
+.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
/* USBFS_bus_reset */\r
.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
-/* USBFS_arb_int */\r
-.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_arb_int__INTC_MASK, 0x400000\r
-.set USBFS_arb_int__INTC_NUMBER, 22\r
-.set USBFS_arb_int__INTC_PRIOR_NUM, 7\r
-.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22\r
-.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+/* USBFS_Dm */\r
+.set USBFS_Dm__0__MASK, 0x80\r
+.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1\r
+.set USBFS_Dm__0__PORT, 15\r
+.set USBFS_Dm__0__SHIFT, 7\r
+.set USBFS_Dm__AG, CYREG_PRT15_AG\r
+.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX\r
+.set USBFS_Dm__BIE, CYREG_PRT15_BIE\r
+.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK\r
+.set USBFS_Dm__BYP, CYREG_PRT15_BYP\r
+.set USBFS_Dm__CTL, CYREG_PRT15_CTL\r
+.set USBFS_Dm__DM0, CYREG_PRT15_DM0\r
+.set USBFS_Dm__DM1, CYREG_PRT15_DM1\r
+.set USBFS_Dm__DM2, CYREG_PRT15_DM2\r
+.set USBFS_Dm__DR, CYREG_PRT15_DR\r
+.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS\r
+.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
+.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN\r
+.set USBFS_Dm__MASK, 0x80\r
+.set USBFS_Dm__PORT, 15\r
+.set USBFS_Dm__PRT, CYREG_PRT15_PRT\r
+.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
+.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
+.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
+.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
+.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
+.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
+.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
+.set USBFS_Dm__PS, CYREG_PRT15_PS\r
+.set USBFS_Dm__SHIFT, 7\r
+.set USBFS_Dm__SLW, CYREG_PRT15_SLW\r
+\r
+/* USBFS_Dp */\r
+.set USBFS_Dp__0__MASK, 0x40\r
+.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0\r
+.set USBFS_Dp__0__PORT, 15\r
+.set USBFS_Dp__0__SHIFT, 6\r
+.set USBFS_Dp__AG, CYREG_PRT15_AG\r
+.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX\r
+.set USBFS_Dp__BIE, CYREG_PRT15_BIE\r
+.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK\r
+.set USBFS_Dp__BYP, CYREG_PRT15_BYP\r
+.set USBFS_Dp__CTL, CYREG_PRT15_CTL\r
+.set USBFS_Dp__DM0, CYREG_PRT15_DM0\r
+.set USBFS_Dp__DM1, CYREG_PRT15_DM1\r
+.set USBFS_Dp__DM2, CYREG_PRT15_DM2\r
+.set USBFS_Dp__DR, CYREG_PRT15_DR\r
+.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS\r
+.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT\r
+.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
+.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN\r
+.set USBFS_Dp__MASK, 0x40\r
+.set USBFS_Dp__PORT, 15\r
+.set USBFS_Dp__PRT, CYREG_PRT15_PRT\r
+.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
+.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
+.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
+.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
+.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
+.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
+.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
+.set USBFS_Dp__PS, CYREG_PRT15_PS\r
+.set USBFS_Dp__SHIFT, 6\r
+.set USBFS_Dp__SLW, CYREG_PRT15_SLW\r
+.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15\r
+\r
+/* USBFS_dp_int */\r
+.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_dp_int__INTC_MASK, 0x1000\r
+.set USBFS_dp_int__INTC_NUMBER, 12\r
+.set USBFS_dp_int__INTC_PRIOR_NUM, 7\r
+.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12\r
+.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_0 */\r
+.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_0__INTC_MASK, 0x1000000\r
+.set USBFS_ep_0__INTC_NUMBER, 24\r
+.set USBFS_ep_0__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24\r
+.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_1 */\r
+.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_1__INTC_MASK, 0x01\r
+.set USBFS_ep_1__INTC_NUMBER, 0\r
+.set USBFS_ep_1__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
+.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_2 */\r
+.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set USBFS_ep_2__INTC_MASK, 0x02\r
+.set USBFS_ep_2__INTC_NUMBER, 1\r
+.set USBFS_ep_2__INTC_PRIOR_NUM, 7\r
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
+.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
/* USBFS_sof_int */\r
.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
-/* SCSI_Out_DBx */\r
-.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__0__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__0__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__0__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__0__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__0__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__0__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__0__MASK, 0x08\r
-.set SCSI_Out_DBx__0__PC, CYREG_PRT6_PC3\r
-.set SCSI_Out_DBx__0__PORT, 6\r
-.set SCSI_Out_DBx__0__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__0__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__0__SHIFT, 3\r
-.set SCSI_Out_DBx__0__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__1__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__1__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__1__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__1__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__1__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__1__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__1__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__1__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__1__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__1__MASK, 0x04\r
-.set SCSI_Out_DBx__1__PC, CYREG_PRT6_PC2\r
-.set SCSI_Out_DBx__1__PORT, 6\r
-.set SCSI_Out_DBx__1__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__1__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__1__SHIFT, 2\r
-.set SCSI_Out_DBx__1__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__2__MASK, 0x02\r
-.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC1\r
-.set SCSI_Out_DBx__2__PORT, 6\r
-.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__2__SHIFT, 1\r
-.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__3__MASK, 0x01\r
-.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC0\r
-.set SCSI_Out_DBx__3__PORT, 6\r
-.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__3__SHIFT, 0\r
-.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__4__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__4__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__4__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__4__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__4__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__4__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__4__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__4__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__4__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__4__MASK, 0x80\r
-.set SCSI_Out_DBx__4__PC, CYREG_PRT4_PC7\r
-.set SCSI_Out_DBx__4__PORT, 4\r
-.set SCSI_Out_DBx__4__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__4__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__4__SHIFT, 7\r
-.set SCSI_Out_DBx__4__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__5__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__5__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__5__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__5__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__5__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__5__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__5__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__5__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__5__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__5__MASK, 0x40\r
-.set SCSI_Out_DBx__5__PC, CYREG_PRT4_PC6\r
-.set SCSI_Out_DBx__5__PORT, 4\r
-.set SCSI_Out_DBx__5__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__5__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__5__SHIFT, 6\r
-.set SCSI_Out_DBx__5__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__6__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__6__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__6__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__6__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__6__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__6__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__6__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__6__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__6__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__6__MASK, 0x20\r
-.set SCSI_Out_DBx__6__PC, CYREG_PRT4_PC5\r
-.set SCSI_Out_DBx__6__PORT, 4\r
-.set SCSI_Out_DBx__6__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__6__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__6__SHIFT, 5\r
-.set SCSI_Out_DBx__6__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__7__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__7__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__7__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__7__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__7__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__7__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__7__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__7__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__7__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__7__MASK, 0x10\r
-.set SCSI_Out_DBx__7__PC, CYREG_PRT4_PC4\r
-.set SCSI_Out_DBx__7__PORT, 4\r
-.set SCSI_Out_DBx__7__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__7__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__7__SHIFT, 4\r
-.set SCSI_Out_DBx__7__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__DB0__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__DB0__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__DB0__MASK, 0x08\r
-.set SCSI_Out_DBx__DB0__PC, CYREG_PRT6_PC3\r
-.set SCSI_Out_DBx__DB0__PORT, 6\r
-.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__DB0__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__DB0__SHIFT, 3\r
-.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__DB1__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__DB1__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__DB1__MASK, 0x04\r
-.set SCSI_Out_DBx__DB1__PC, CYREG_PRT6_PC2\r
-.set SCSI_Out_DBx__DB1__PORT, 6\r
-.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__DB1__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__DB1__SHIFT, 2\r
-.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__DB2__MASK, 0x02\r
-.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC1\r
-.set SCSI_Out_DBx__DB2__PORT, 6\r
-.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__DB2__SHIFT, 1\r
-.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG\r
-.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX\r
-.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE\r
-.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
-.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP\r
-.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL\r
-.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0\r
-.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1\r
-.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2\r
-.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR\r
-.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS\r
-.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN\r
-.set SCSI_Out_DBx__DB3__MASK, 0x01\r
-.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC0\r
-.set SCSI_Out_DBx__DB3__PORT, 6\r
-.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT\r
-.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
-.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
-.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
-.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS\r
-.set SCSI_Out_DBx__DB3__SHIFT, 0\r
-.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW\r
-.set SCSI_Out_DBx__DB4__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__DB4__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__DB4__MASK, 0x80\r
-.set SCSI_Out_DBx__DB4__PC, CYREG_PRT4_PC7\r
-.set SCSI_Out_DBx__DB4__PORT, 4\r
-.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__DB4__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__DB4__SHIFT, 7\r
-.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__DB5__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__DB5__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__DB5__MASK, 0x40\r
-.set SCSI_Out_DBx__DB5__PC, CYREG_PRT4_PC6\r
-.set SCSI_Out_DBx__DB5__PORT, 4\r
-.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__DB5__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__DB5__SHIFT, 6\r
-.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__DB6__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__DB6__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__DB6__MASK, 0x20\r
-.set SCSI_Out_DBx__DB6__PC, CYREG_PRT4_PC5\r
-.set SCSI_Out_DBx__DB6__PORT, 4\r
-.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__DB6__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__DB6__SHIFT, 5\r
-.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT4_SLW\r
-.set SCSI_Out_DBx__DB7__AG, CYREG_PRT4_AG\r
-.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT4_AMUX\r
-.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT4_BIE\r
-.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT4_BIT_MASK\r
-.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT4_BYP\r
-.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT4_CTL\r
-.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT4_DM0\r
-.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT4_DM1\r
-.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT4_DM2\r
-.set SCSI_Out_DBx__DB7__DR, CYREG_PRT4_DR\r
-.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT4_INP_DIS\r
-.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
-.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT4_LCD_EN\r
-.set SCSI_Out_DBx__DB7__MASK, 0x10\r
-.set SCSI_Out_DBx__DB7__PC, CYREG_PRT4_PC4\r
-.set SCSI_Out_DBx__DB7__PORT, 4\r
-.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT4_PRT\r
-.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
-.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
-.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
-.set SCSI_Out_DBx__DB7__PS, CYREG_PRT4_PS\r
-.set SCSI_Out_DBx__DB7__SHIFT, 4\r
-.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT4_SLW\r
-\r
-/* USBFS_dp_int */\r
-.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_dp_int__INTC_MASK, 0x1000\r
-.set USBFS_dp_int__INTC_NUMBER, 12\r
-.set USBFS_dp_int__INTC_PRIOR_NUM, 7\r
-.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12\r
-.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_0 */\r
-.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_0__INTC_MASK, 0x1000000\r
-.set USBFS_ep_0__INTC_NUMBER, 24\r
-.set USBFS_ep_0__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24\r
-.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_1 */\r
-.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_1__INTC_MASK, 0x01\r
-.set USBFS_ep_1__INTC_NUMBER, 0\r
-.set USBFS_ep_1__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
-.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_2 */\r
-.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
-.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
-.set USBFS_ep_2__INTC_MASK, 0x02\r
-.set USBFS_ep_2__INTC_NUMBER, 1\r
-.set USBFS_ep_2__INTC_PRIOR_NUM, 7\r
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
-.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
-.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
-\r
-/* SD_PULLUP */\r
-.set SD_PULLUP__0__MASK, 0x02\r
-.set SD_PULLUP__0__PC, CYREG_PRT3_PC1\r
-.set SD_PULLUP__0__PORT, 3\r
-.set SD_PULLUP__0__SHIFT, 1\r
-.set SD_PULLUP__1__MASK, 0x04\r
-.set SD_PULLUP__1__PC, CYREG_PRT3_PC2\r
-.set SD_PULLUP__1__PORT, 3\r
-.set SD_PULLUP__1__SHIFT, 2\r
-.set SD_PULLUP__2__MASK, 0x08\r
-.set SD_PULLUP__2__PC, CYREG_PRT3_PC3\r
-.set SD_PULLUP__2__PORT, 3\r
-.set SD_PULLUP__2__SHIFT, 3\r
-.set SD_PULLUP__3__MASK, 0x10\r
-.set SD_PULLUP__3__PC, CYREG_PRT3_PC4\r
-.set SD_PULLUP__3__PORT, 3\r
-.set SD_PULLUP__3__SHIFT, 4\r
-.set SD_PULLUP__4__MASK, 0x20\r
-.set SD_PULLUP__4__PC, CYREG_PRT3_PC5\r
-.set SD_PULLUP__4__PORT, 3\r
-.set SD_PULLUP__4__SHIFT, 5\r
-.set SD_PULLUP__AG, CYREG_PRT3_AG\r
-.set SD_PULLUP__AMUX, CYREG_PRT3_AMUX\r
-.set SD_PULLUP__BIE, CYREG_PRT3_BIE\r
-.set SD_PULLUP__BIT_MASK, CYREG_PRT3_BIT_MASK\r
-.set SD_PULLUP__BYP, CYREG_PRT3_BYP\r
-.set SD_PULLUP__CTL, CYREG_PRT3_CTL\r
-.set SD_PULLUP__DM0, CYREG_PRT3_DM0\r
-.set SD_PULLUP__DM1, CYREG_PRT3_DM1\r
-.set SD_PULLUP__DM2, CYREG_PRT3_DM2\r
-.set SD_PULLUP__DR, CYREG_PRT3_DR\r
-.set SD_PULLUP__INP_DIS, CYREG_PRT3_INP_DIS\r
-.set SD_PULLUP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
-.set SD_PULLUP__LCD_EN, CYREG_PRT3_LCD_EN\r
-.set SD_PULLUP__MASK, 0x3E\r
-.set SD_PULLUP__PORT, 3\r
-.set SD_PULLUP__PRT, CYREG_PRT3_PRT\r
-.set SD_PULLUP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
-.set SD_PULLUP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
-.set SD_PULLUP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
-.set SD_PULLUP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
-.set SD_PULLUP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
-.set SD_PULLUP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
-.set SD_PULLUP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
-.set SD_PULLUP__PS, CYREG_PRT3_PS\r
-.set SD_PULLUP__SHIFT, 1\r
-.set SD_PULLUP__SLW, CYREG_PRT3_SLW\r
-\r
/* USBFS_USB */\r
.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG\r
.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG\r
.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES\r
.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB\r
.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG\r
+.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE\r
+.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE\r
.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT\r
.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR\r
.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0\r
.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5\r
.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6\r
.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7\r
-.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE\r
-.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE\r
.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE\r
.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5\r
.set USBFS_USB__PM_ACT_MSK, 0x01\r
.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5\r
.set USBFS_USB__PM_STBY_MSK, 0x01\r
+.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN\r
+.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR\r
.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0\r
.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1\r
.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0\r
.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0\r
.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1\r
.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0\r
-.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN\r
-.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR\r
.set USBFS_USB__SOF0, CYREG_USB_SOF0\r
.set USBFS_USB__SOF1, CYREG_USB_SOF1\r
+.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN\r
.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0\r
.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1\r
-.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN\r
\r
/* SCSI_Out */\r
.set SCSI_Out__0__AG, CYREG_PRT4_AG\r
.set SCSI_Out__SEL__SHIFT, 3\r
.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW\r
\r
-/* USBFS_Dm */\r
-.set USBFS_Dm__0__MASK, 0x80\r
-.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1\r
-.set USBFS_Dm__0__PORT, 15\r
-.set USBFS_Dm__0__SHIFT, 7\r
-.set USBFS_Dm__AG, CYREG_PRT15_AG\r
-.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX\r
-.set USBFS_Dm__BIE, CYREG_PRT15_BIE\r
-.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK\r
-.set USBFS_Dm__BYP, CYREG_PRT15_BYP\r
-.set USBFS_Dm__CTL, CYREG_PRT15_CTL\r
-.set USBFS_Dm__DM0, CYREG_PRT15_DM0\r
-.set USBFS_Dm__DM1, CYREG_PRT15_DM1\r
-.set USBFS_Dm__DM2, CYREG_PRT15_DM2\r
-.set USBFS_Dm__DR, CYREG_PRT15_DR\r
-.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS\r
-.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
-.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN\r
-.set USBFS_Dm__MASK, 0x80\r
-.set USBFS_Dm__PORT, 15\r
-.set USBFS_Dm__PRT, CYREG_PRT15_PRT\r
-.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
-.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
-.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
-.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
-.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
-.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
-.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
-.set USBFS_Dm__PS, CYREG_PRT15_PS\r
-.set USBFS_Dm__SHIFT, 7\r
-.set USBFS_Dm__SLW, CYREG_PRT15_SLW\r
+/* SCSI_Out_DBx */\r
+.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__0__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__0__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__0__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__0__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__0__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__0__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__0__MASK, 0x08\r
+.set SCSI_Out_DBx__0__PC, CYREG_PRT6_PC3\r
+.set SCSI_Out_DBx__0__PORT, 6\r
+.set SCSI_Out_DBx__0__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__0__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__0__SHIFT, 3\r
+.set SCSI_Out_DBx__0__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__1__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__1__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__1__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__1__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__1__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__1__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__1__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__1__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__1__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__1__MASK, 0x04\r
+.set SCSI_Out_DBx__1__PC, CYREG_PRT6_PC2\r
+.set SCSI_Out_DBx__1__PORT, 6\r
+.set SCSI_Out_DBx__1__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__1__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__1__SHIFT, 2\r
+.set SCSI_Out_DBx__1__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__2__MASK, 0x02\r
+.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC1\r
+.set SCSI_Out_DBx__2__PORT, 6\r
+.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__2__SHIFT, 1\r
+.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__3__MASK, 0x01\r
+.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC0\r
+.set SCSI_Out_DBx__3__PORT, 6\r
+.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__3__SHIFT, 0\r
+.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__4__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__4__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__4__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__4__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__4__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__4__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__4__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__4__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__4__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__4__MASK, 0x80\r
+.set SCSI_Out_DBx__4__PC, CYREG_PRT4_PC7\r
+.set SCSI_Out_DBx__4__PORT, 4\r
+.set SCSI_Out_DBx__4__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__4__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__4__SHIFT, 7\r
+.set SCSI_Out_DBx__4__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__5__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__5__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__5__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__5__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__5__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__5__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__5__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__5__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__5__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__5__MASK, 0x40\r
+.set SCSI_Out_DBx__5__PC, CYREG_PRT4_PC6\r
+.set SCSI_Out_DBx__5__PORT, 4\r
+.set SCSI_Out_DBx__5__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__5__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__5__SHIFT, 6\r
+.set SCSI_Out_DBx__5__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__6__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__6__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__6__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__6__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__6__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__6__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__6__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__6__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__6__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__6__MASK, 0x20\r
+.set SCSI_Out_DBx__6__PC, CYREG_PRT4_PC5\r
+.set SCSI_Out_DBx__6__PORT, 4\r
+.set SCSI_Out_DBx__6__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__6__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__6__SHIFT, 5\r
+.set SCSI_Out_DBx__6__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__7__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__7__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__7__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__7__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__7__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__7__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__7__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__7__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__7__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__7__MASK, 0x10\r
+.set SCSI_Out_DBx__7__PC, CYREG_PRT4_PC4\r
+.set SCSI_Out_DBx__7__PORT, 4\r
+.set SCSI_Out_DBx__7__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__7__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__7__SHIFT, 4\r
+.set SCSI_Out_DBx__7__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__DB0__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__DB0__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__DB0__MASK, 0x08\r
+.set SCSI_Out_DBx__DB0__PC, CYREG_PRT6_PC3\r
+.set SCSI_Out_DBx__DB0__PORT, 6\r
+.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__DB0__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__DB0__SHIFT, 3\r
+.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__DB1__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__DB1__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__DB1__MASK, 0x04\r
+.set SCSI_Out_DBx__DB1__PC, CYREG_PRT6_PC2\r
+.set SCSI_Out_DBx__DB1__PORT, 6\r
+.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__DB1__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__DB1__SHIFT, 2\r
+.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__DB2__MASK, 0x02\r
+.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC1\r
+.set SCSI_Out_DBx__DB2__PORT, 6\r
+.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__DB2__SHIFT, 1\r
+.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG\r
+.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR\r
+.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out_DBx__DB3__MASK, 0x01\r
+.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC0\r
+.set SCSI_Out_DBx__DB3__PORT, 6\r
+.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS\r
+.set SCSI_Out_DBx__DB3__SHIFT, 0\r
+.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out_DBx__DB4__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__DB4__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__DB4__MASK, 0x80\r
+.set SCSI_Out_DBx__DB4__PC, CYREG_PRT4_PC7\r
+.set SCSI_Out_DBx__DB4__PORT, 4\r
+.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__DB4__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__DB4__SHIFT, 7\r
+.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__DB5__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__DB5__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__DB5__MASK, 0x40\r
+.set SCSI_Out_DBx__DB5__PC, CYREG_PRT4_PC6\r
+.set SCSI_Out_DBx__DB5__PORT, 4\r
+.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__DB5__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__DB5__SHIFT, 6\r
+.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__DB6__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__DB6__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__DB6__MASK, 0x20\r
+.set SCSI_Out_DBx__DB6__PC, CYREG_PRT4_PC5\r
+.set SCSI_Out_DBx__DB6__PORT, 4\r
+.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__DB6__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__DB6__SHIFT, 5\r
+.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out_DBx__DB7__AG, CYREG_PRT4_AG\r
+.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out_DBx__DB7__DR, CYREG_PRT4_DR\r
+.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out_DBx__DB7__MASK, 0x10\r
+.set SCSI_Out_DBx__DB7__PC, CYREG_PRT4_PC4\r
+.set SCSI_Out_DBx__DB7__PORT, 4\r
+.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out_DBx__DB7__PS, CYREG_PRT4_PS\r
+.set SCSI_Out_DBx__DB7__SHIFT, 4\r
+.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT4_SLW\r
\r
-/* USBFS_Dp */\r
-.set USBFS_Dp__0__MASK, 0x40\r
-.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0\r
-.set USBFS_Dp__0__PORT, 15\r
-.set USBFS_Dp__0__SHIFT, 6\r
-.set USBFS_Dp__AG, CYREG_PRT15_AG\r
-.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX\r
-.set USBFS_Dp__BIE, CYREG_PRT15_BIE\r
-.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK\r
-.set USBFS_Dp__BYP, CYREG_PRT15_BYP\r
-.set USBFS_Dp__CTL, CYREG_PRT15_CTL\r
-.set USBFS_Dp__DM0, CYREG_PRT15_DM0\r
-.set USBFS_Dp__DM1, CYREG_PRT15_DM1\r
-.set USBFS_Dp__DM2, CYREG_PRT15_DM2\r
-.set USBFS_Dp__DR, CYREG_PRT15_DR\r
-.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS\r
-.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT\r
-.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG\r
-.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN\r
-.set USBFS_Dp__MASK, 0x40\r
-.set USBFS_Dp__PORT, 15\r
-.set USBFS_Dp__PRT, CYREG_PRT15_PRT\r
-.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL\r
-.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN\r
-.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0\r
-.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1\r
-.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0\r
-.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1\r
-.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT\r
-.set USBFS_Dp__PS, CYREG_PRT15_PS\r
-.set USBFS_Dp__SHIFT, 6\r
-.set USBFS_Dp__SLW, CYREG_PRT15_SLW\r
-.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15\r
+/* SD_PULLUP */\r
+.set SD_PULLUP__0__MASK, 0x02\r
+.set SD_PULLUP__0__PC, CYREG_PRT3_PC1\r
+.set SD_PULLUP__0__PORT, 3\r
+.set SD_PULLUP__0__SHIFT, 1\r
+.set SD_PULLUP__1__MASK, 0x04\r
+.set SD_PULLUP__1__PC, CYREG_PRT3_PC2\r
+.set SD_PULLUP__1__PORT, 3\r
+.set SD_PULLUP__1__SHIFT, 2\r
+.set SD_PULLUP__2__MASK, 0x08\r
+.set SD_PULLUP__2__PC, CYREG_PRT3_PC3\r
+.set SD_PULLUP__2__PORT, 3\r
+.set SD_PULLUP__2__SHIFT, 3\r
+.set SD_PULLUP__3__MASK, 0x10\r
+.set SD_PULLUP__3__PC, CYREG_PRT3_PC4\r
+.set SD_PULLUP__3__PORT, 3\r
+.set SD_PULLUP__3__SHIFT, 4\r
+.set SD_PULLUP__4__MASK, 0x20\r
+.set SD_PULLUP__4__PC, CYREG_PRT3_PC5\r
+.set SD_PULLUP__4__PORT, 3\r
+.set SD_PULLUP__4__SHIFT, 5\r
+.set SD_PULLUP__AG, CYREG_PRT3_AG\r
+.set SD_PULLUP__AMUX, CYREG_PRT3_AMUX\r
+.set SD_PULLUP__BIE, CYREG_PRT3_BIE\r
+.set SD_PULLUP__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_PULLUP__BYP, CYREG_PRT3_BYP\r
+.set SD_PULLUP__CTL, CYREG_PRT3_CTL\r
+.set SD_PULLUP__DM0, CYREG_PRT3_DM0\r
+.set SD_PULLUP__DM1, CYREG_PRT3_DM1\r
+.set SD_PULLUP__DM2, CYREG_PRT3_DM2\r
+.set SD_PULLUP__DR, CYREG_PRT3_DR\r
+.set SD_PULLUP__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_PULLUP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_PULLUP__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_PULLUP__MASK, 0x3E\r
+.set SD_PULLUP__PORT, 3\r
+.set SD_PULLUP__PRT, CYREG_PRT3_PRT\r
+.set SD_PULLUP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_PULLUP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_PULLUP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_PULLUP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_PULLUP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_PULLUP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_PULLUP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_PULLUP__PS, CYREG_PRT3_PS\r
+.set SD_PULLUP__SHIFT, 1\r
+.set SD_PULLUP__SLW, CYREG_PRT3_SLW\r
\r
/* Miscellaneous */\r
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */\r
-.set CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO, 0\r
-.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6\r
-.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0\r
-.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0\r
-.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1\r
-.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0\r
-.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0\r
-.set CYDEV_CHIP_MEMBER_5B, 4\r
-.set CYDEV_CHIP_FAMILY_PSOC5, 3\r
-.set CYDEV_CHIP_DIE_PSOC5LP, 4\r
-.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP\r
-.set CYDEV_BOOTLOADER_IO_COMP_USBFS, 1\r
.set BCLK__BUS_CLK__HZ, 64000000\r
.set BCLK__BUS_CLK__KHZ, 64000\r
.set BCLK__BUS_CLK__MHZ, 64\r
.set CYDEV_BOOTLOADER_APPLICATIONS, 1\r
.set CYDEV_BOOTLOADER_CHECKSUM_BASIC, 0\r
.set CYDEV_BOOTLOADER_CHECKSUM_CRC, 1\r
+.set CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO, 0\r
+.set CyBtldr_Custom_Interface, CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO\r
+.set CYDEV_BOOTLOADER_IO_COMP_USBFS, 1\r
+.set CyBtldr_USBFS, CYDEV_BOOTLOADER_IO_COMP_USBFS\r
.set CYDEV_BOOTLOADER_IO_COMP, CYDEV_BOOTLOADER_IO_COMP_USBFS\r
-.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT\r
.set CYDEV_CHIP_DIE_LEOPARD, 1\r
-.set CYDEV_CHIP_DIE_PANTHER, 3\r
-.set CYDEV_CHIP_DIE_PSOC4A, 2\r
+.set CYDEV_CHIP_DIE_PANTHER, 6\r
+.set CYDEV_CHIP_DIE_PSOC4A, 3\r
+.set CYDEV_CHIP_DIE_PSOC5LP, 5\r
.set CYDEV_CHIP_DIE_UNKNOWN, 0\r
.set CYDEV_CHIP_FAMILY_PSOC3, 1\r
.set CYDEV_CHIP_FAMILY_PSOC4, 2\r
+.set CYDEV_CHIP_FAMILY_PSOC5, 3\r
.set CYDEV_CHIP_FAMILY_UNKNOWN, 0\r
.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5\r
.set CYDEV_CHIP_JTAG_ID, 0x2E133069\r
.set CYDEV_CHIP_MEMBER_3A, 1\r
-.set CYDEV_CHIP_MEMBER_4A, 2\r
-.set CYDEV_CHIP_MEMBER_5A, 3\r
+.set CYDEV_CHIP_MEMBER_4A, 3\r
+.set CYDEV_CHIP_MEMBER_4D, 2\r
+.set CYDEV_CHIP_MEMBER_4F, 4\r
+.set CYDEV_CHIP_MEMBER_5A, 6\r
+.set CYDEV_CHIP_MEMBER_5B, 5\r
.set CYDEV_CHIP_MEMBER_UNKNOWN, 0\r
.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B\r
+.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED\r
+.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT\r
+.set CYDEV_CHIP_REV_LEOPARD_ES1, 0\r
+.set CYDEV_CHIP_REV_LEOPARD_ES2, 1\r
+.set CYDEV_CHIP_REV_LEOPARD_ES3, 3\r
+.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3\r
+.set CYDEV_CHIP_REV_PANTHER_ES0, 0\r
+.set CYDEV_CHIP_REV_PANTHER_ES1, 1\r
+.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1\r
+.set CYDEV_CHIP_REV_PSOC4A_ES0, 17\r
+.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17\r
+.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0\r
+.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_3A_ES1, 0\r
.set CYDEV_CHIP_REVISION_3A_ES2, 1\r
.set CYDEV_CHIP_REVISION_3A_ES3, 3\r
.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3\r
.set CYDEV_CHIP_REVISION_4A_ES0, 17\r
.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17\r
+.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_5A_ES0, 0\r
.set CYDEV_CHIP_REVISION_5A_ES1, 1\r
.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1\r
.set CYDEV_CHIP_REVISION_5B_ES0, 0\r
+.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0\r
.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION\r
-.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REV_PSOC5LP_PRODUCTION\r
-.set CYDEV_CHIP_REV_LEOPARD_ES1, 0\r
-.set CYDEV_CHIP_REV_LEOPARD_ES2, 1\r
-.set CYDEV_CHIP_REV_LEOPARD_ES3, 3\r
-.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3\r
-.set CYDEV_CHIP_REV_PANTHER_ES0, 0\r
-.set CYDEV_CHIP_REV_PANTHER_ES1, 1\r
-.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1\r
-.set CYDEV_CHIP_REV_PSOC4A_ES0, 17\r
-.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17\r
-.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0\r
+.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED\r
+.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1\r
+.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0\r
+.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
+.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1\r
+.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2\r
.set CYDEV_CONFIGURATION_COMPRESSED, 1\r
.set CYDEV_CONFIGURATION_DMA, 0\r
.set CYDEV_CONFIGURATION_ECC, 0\r
.set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED\r
+.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0\r
.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED\r
.set CYDEV_CONFIGURATION_MODE_DMA, 2\r
.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1\r
-.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
-.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1\r
-.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2\r
-.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV\r
+.set CYDEV_DEBUG_ENABLE_MASK, 0x20\r
+.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG\r
.set CYDEV_DEBUGGING_DPS_Disable, 3\r
.set CYDEV_DEBUGGING_DPS_JTAG_4, 1\r
.set CYDEV_DEBUGGING_DPS_JTAG_5, 0\r
.set CYDEV_DEBUGGING_DPS_SWD, 2\r
+.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6\r
+.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV\r
.set CYDEV_DEBUGGING_ENABLE, 1\r
.set CYDEV_DEBUGGING_XRES, 0\r
-.set CYDEV_DEBUG_ENABLE_MASK, 0x20\r
-.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG\r
.set CYDEV_DMA_CHANNELS_AVAILABLE, 24\r
.set CYDEV_ECC_ENABLE, 0\r
.set CYDEV_HEAP_SIZE, 0x0800\r
.set CYDEV_VDDIO1_MV, 5000\r
.set CYDEV_VDDIO2_MV, 5000\r
.set CYDEV_VDDIO3_MV, 5000\r
-.set CYDEV_VIO0, 5\r
.set CYDEV_VIO0_MV, 5000\r
-.set CYDEV_VIO1, 5\r
.set CYDEV_VIO1_MV, 5000\r
-.set CYDEV_VIO2, 5\r
.set CYDEV_VIO2_MV, 5000\r
-.set CYDEV_VIO3, 5\r
.set CYDEV_VIO3_MV, 5000\r
-.set CyBtldr_Custom_Interface, CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO\r
-.set CyBtldr_USBFS, CYDEV_BOOTLOADER_IO_COMP_USBFS\r
+.set CYIPBLOCK_ARM_CM3_VERSION, 0\r
+.set CYIPBLOCK_P3_ANAIF_VERSION, 0\r
+.set CYIPBLOCK_P3_CAPSENSE_VERSION, 0\r
+.set CYIPBLOCK_P3_COMP_VERSION, 0\r
+.set CYIPBLOCK_P3_DMA_VERSION, 0\r
+.set CYIPBLOCK_P3_DRQ_VERSION, 0\r
+.set CYIPBLOCK_P3_EMIF_VERSION, 0\r
+.set CYIPBLOCK_P3_I2C_VERSION, 0\r
+.set CYIPBLOCK_P3_LCD_VERSION, 0\r
+.set CYIPBLOCK_P3_LPF_VERSION, 0\r
+.set CYIPBLOCK_P3_PM_VERSION, 0\r
+.set CYIPBLOCK_P3_TIMER_VERSION, 0\r
+.set CYIPBLOCK_P3_USB_VERSION, 0\r
+.set CYIPBLOCK_P3_VIDAC_VERSION, 0\r
+.set CYIPBLOCK_P3_VREF_VERSION, 0\r
+.set CYIPBLOCK_S8_GPIO_VERSION, 0\r
+.set CYIPBLOCK_S8_IRQ_VERSION, 0\r
+.set CYIPBLOCK_S8_SAR_VERSION, 0\r
+.set CYIPBLOCK_S8_SIO_VERSION, 0\r
+.set CYIPBLOCK_S8_UDB_VERSION, 0\r
.set DMA_CHANNELS_USED__MASK0, 0x00000000\r
.set CYDEV_BOOTLOADER_ENABLE, 1\r
.endif\r
INCLUDE cydeviceiar.inc\r
INCLUDE cydeviceiar_trm.inc\r
\r
+/* USBFS_arb_int */\r
+USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_arb_int__INTC_MASK EQU 0x400000\r
+USBFS_arb_int__INTC_NUMBER EQU 22\r
+USBFS_arb_int__INTC_PRIOR_NUM EQU 7\r
+USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22\r
+USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
/* USBFS_bus_reset */\r
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
-/* USBFS_arb_int */\r
-USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_arb_int__INTC_MASK EQU 0x400000\r
-USBFS_arb_int__INTC_NUMBER EQU 22\r
-USBFS_arb_int__INTC_PRIOR_NUM EQU 7\r
-USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22\r
-USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+/* USBFS_Dm */\r
+USBFS_Dm__0__MASK EQU 0x80\r
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1\r
+USBFS_Dm__0__PORT EQU 15\r
+USBFS_Dm__0__SHIFT EQU 7\r
+USBFS_Dm__AG EQU CYREG_PRT15_AG\r
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX\r
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE\r
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP\r
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL\r
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0\r
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1\r
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2\r
+USBFS_Dm__DR EQU CYREG_PRT15_DR\r
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+USBFS_Dm__MASK EQU 0x80\r
+USBFS_Dm__PORT EQU 15\r
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT\r
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+USBFS_Dm__PS EQU CYREG_PRT15_PS\r
+USBFS_Dm__SHIFT EQU 7\r
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW\r
+\r
+/* USBFS_Dp */\r
+USBFS_Dp__0__MASK EQU 0x40\r
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0\r
+USBFS_Dp__0__PORT EQU 15\r
+USBFS_Dp__0__SHIFT EQU 6\r
+USBFS_Dp__AG EQU CYREG_PRT15_AG\r
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX\r
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE\r
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP\r
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL\r
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0\r
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1\r
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2\r
+USBFS_Dp__DR EQU CYREG_PRT15_DR\r
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT\r
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+USBFS_Dp__MASK EQU 0x40\r
+USBFS_Dp__PORT EQU 15\r
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT\r
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+USBFS_Dp__PS EQU CYREG_PRT15_PS\r
+USBFS_Dp__SHIFT EQU 6\r
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW\r
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15\r
+\r
+/* USBFS_dp_int */\r
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_dp_int__INTC_MASK EQU 0x1000\r
+USBFS_dp_int__INTC_NUMBER EQU 12\r
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7\r
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12\r
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_0 */\r
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_0__INTC_MASK EQU 0x1000000\r
+USBFS_ep_0__INTC_NUMBER EQU 24\r
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24\r
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_1 */\r
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_1__INTC_MASK EQU 0x01\r
+USBFS_ep_1__INTC_NUMBER EQU 0\r
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+/* USBFS_ep_2 */\r
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_2__INTC_MASK EQU 0x02\r
+USBFS_ep_2__INTC_NUMBER EQU 1\r
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
/* USBFS_sof_int */\r
USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
-/* SCSI_Out_DBx */\r
-SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__0__MASK EQU 0x08\r
-SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out_DBx__0__PORT EQU 6\r
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__0__SHIFT EQU 3\r
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__1__MASK EQU 0x04\r
-SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2\r
-SCSI_Out_DBx__1__PORT EQU 6\r
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__1__SHIFT EQU 2\r
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__2__MASK EQU 0x02\r
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out_DBx__2__PORT EQU 6\r
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__2__SHIFT EQU 1\r
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__3__MASK EQU 0x01\r
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out_DBx__3__PORT EQU 6\r
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__3__SHIFT EQU 0\r
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__4__MASK EQU 0x80\r
-SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7\r
-SCSI_Out_DBx__4__PORT EQU 4\r
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__4__SHIFT EQU 7\r
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__5__MASK EQU 0x40\r
-SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6\r
-SCSI_Out_DBx__5__PORT EQU 4\r
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__5__SHIFT EQU 6\r
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__6__MASK EQU 0x20\r
-SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out_DBx__6__PORT EQU 4\r
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__6__SHIFT EQU 5\r
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__7__MASK EQU 0x10\r
-SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out_DBx__7__PORT EQU 4\r
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__7__SHIFT EQU 4\r
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB0__MASK EQU 0x08\r
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out_DBx__DB0__PORT EQU 6\r
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB0__SHIFT EQU 3\r
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB1__MASK EQU 0x04\r
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2\r
-SCSI_Out_DBx__DB1__PORT EQU 6\r
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB1__SHIFT EQU 2\r
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB2__MASK EQU 0x02\r
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out_DBx__DB2__PORT EQU 6\r
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB2__SHIFT EQU 1\r
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB3__MASK EQU 0x01\r
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out_DBx__DB3__PORT EQU 6\r
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB3__SHIFT EQU 0\r
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB4__MASK EQU 0x80\r
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7\r
-SCSI_Out_DBx__DB4__PORT EQU 4\r
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB4__SHIFT EQU 7\r
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB5__MASK EQU 0x40\r
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6\r
-SCSI_Out_DBx__DB5__PORT EQU 4\r
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB5__SHIFT EQU 6\r
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB6__MASK EQU 0x20\r
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out_DBx__DB6__PORT EQU 4\r
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB6__SHIFT EQU 5\r
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB7__MASK EQU 0x10\r
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out_DBx__DB7__PORT EQU 4\r
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB7__SHIFT EQU 4\r
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW\r
-\r
-/* USBFS_dp_int */\r
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_dp_int__INTC_MASK EQU 0x1000\r
-USBFS_dp_int__INTC_NUMBER EQU 12\r
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7\r
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12\r
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_0 */\r
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_0__INTC_MASK EQU 0x1000000\r
-USBFS_ep_0__INTC_NUMBER EQU 24\r
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24\r
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_1 */\r
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x01\r
-USBFS_ep_1__INTC_NUMBER EQU 0\r
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* USBFS_ep_2 */\r
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x02\r
-USBFS_ep_2__INTC_NUMBER EQU 1\r
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-/* SD_PULLUP */\r
-SD_PULLUP__0__MASK EQU 0x02\r
-SD_PULLUP__0__PC EQU CYREG_PRT3_PC1\r
-SD_PULLUP__0__PORT EQU 3\r
-SD_PULLUP__0__SHIFT EQU 1\r
-SD_PULLUP__1__MASK EQU 0x04\r
-SD_PULLUP__1__PC EQU CYREG_PRT3_PC2\r
-SD_PULLUP__1__PORT EQU 3\r
-SD_PULLUP__1__SHIFT EQU 2\r
-SD_PULLUP__2__MASK EQU 0x08\r
-SD_PULLUP__2__PC EQU CYREG_PRT3_PC3\r
-SD_PULLUP__2__PORT EQU 3\r
-SD_PULLUP__2__SHIFT EQU 3\r
-SD_PULLUP__3__MASK EQU 0x10\r
-SD_PULLUP__3__PC EQU CYREG_PRT3_PC4\r
-SD_PULLUP__3__PORT EQU 3\r
-SD_PULLUP__3__SHIFT EQU 4\r
-SD_PULLUP__4__MASK EQU 0x20\r
-SD_PULLUP__4__PC EQU CYREG_PRT3_PC5\r
-SD_PULLUP__4__PORT EQU 3\r
-SD_PULLUP__4__SHIFT EQU 5\r
-SD_PULLUP__AG EQU CYREG_PRT3_AG\r
-SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX\r
-SD_PULLUP__BIE EQU CYREG_PRT3_BIE\r
-SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_PULLUP__BYP EQU CYREG_PRT3_BYP\r
-SD_PULLUP__CTL EQU CYREG_PRT3_CTL\r
-SD_PULLUP__DM0 EQU CYREG_PRT3_DM0\r
-SD_PULLUP__DM1 EQU CYREG_PRT3_DM1\r
-SD_PULLUP__DM2 EQU CYREG_PRT3_DM2\r
-SD_PULLUP__DR EQU CYREG_PRT3_DR\r
-SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_PULLUP__MASK EQU 0x3E\r
-SD_PULLUP__PORT EQU 3\r
-SD_PULLUP__PRT EQU CYREG_PRT3_PRT\r
-SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_PULLUP__PS EQU CYREG_PRT3_PS\r
-SD_PULLUP__SHIFT EQU 1\r
-SD_PULLUP__SLW EQU CYREG_PRT3_SLW\r
-\r
/* USBFS_USB */\r
USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG\r
USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG\r
USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES\r
USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB\r
USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG\r
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE\r
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE\r
USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT\r
USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR\r
USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0\r
USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5\r
USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6\r
USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7\r
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE\r
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE\r
USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE\r
USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5\r
USBFS_USB__PM_ACT_MSK EQU 0x01\r
USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5\r
USBFS_USB__PM_STBY_MSK EQU 0x01\r
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN\r
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR\r
USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0\r
USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1\r
USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0\r
USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0\r
USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1\r
USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0\r
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN\r
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR\r
USBFS_USB__SOF0 EQU CYREG_USB_SOF0\r
USBFS_USB__SOF1 EQU CYREG_USB_SOF1\r
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN\r
USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0\r
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN\r
\r
/* SCSI_Out */\r
SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
SCSI_Out__SEL__SHIFT EQU 3\r
SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
\r
-/* USBFS_Dm */\r
-USBFS_Dm__0__MASK EQU 0x80\r
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1\r
-USBFS_Dm__0__PORT EQU 15\r
-USBFS_Dm__0__SHIFT EQU 7\r
-USBFS_Dm__AG EQU CYREG_PRT15_AG\r
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX\r
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE\r
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP\r
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL\r
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0\r
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1\r
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2\r
-USBFS_Dm__DR EQU CYREG_PRT15_DR\r
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-USBFS_Dm__MASK EQU 0x80\r
-USBFS_Dm__PORT EQU 15\r
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT\r
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-USBFS_Dm__PS EQU CYREG_PRT15_PS\r
-USBFS_Dm__SHIFT EQU 7\r
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW\r
+/* SCSI_Out_DBx */\r
+SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__0__MASK EQU 0x08\r
+SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out_DBx__0__PORT EQU 6\r
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__0__SHIFT EQU 3\r
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__1__MASK EQU 0x04\r
+SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out_DBx__1__PORT EQU 6\r
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__1__SHIFT EQU 2\r
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__2__MASK EQU 0x02\r
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out_DBx__2__PORT EQU 6\r
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__2__SHIFT EQU 1\r
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__3__MASK EQU 0x01\r
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out_DBx__3__PORT EQU 6\r
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__3__SHIFT EQU 0\r
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__4__MASK EQU 0x80\r
+SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out_DBx__4__PORT EQU 4\r
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__4__SHIFT EQU 7\r
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__5__MASK EQU 0x40\r
+SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out_DBx__5__PORT EQU 4\r
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__5__SHIFT EQU 6\r
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__6__MASK EQU 0x20\r
+SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out_DBx__6__PORT EQU 4\r
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__6__SHIFT EQU 5\r
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__7__MASK EQU 0x10\r
+SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out_DBx__7__PORT EQU 4\r
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__7__SHIFT EQU 4\r
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB0__MASK EQU 0x08\r
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out_DBx__DB0__PORT EQU 6\r
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB0__SHIFT EQU 3\r
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB1__MASK EQU 0x04\r
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out_DBx__DB1__PORT EQU 6\r
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB1__SHIFT EQU 2\r
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB2__MASK EQU 0x02\r
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out_DBx__DB2__PORT EQU 6\r
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB2__SHIFT EQU 1\r
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB3__MASK EQU 0x01\r
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out_DBx__DB3__PORT EQU 6\r
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB3__SHIFT EQU 0\r
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB4__MASK EQU 0x80\r
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out_DBx__DB4__PORT EQU 4\r
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB4__SHIFT EQU 7\r
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB5__MASK EQU 0x40\r
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out_DBx__DB5__PORT EQU 4\r
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB5__SHIFT EQU 6\r
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB6__MASK EQU 0x20\r
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out_DBx__DB6__PORT EQU 4\r
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB6__SHIFT EQU 5\r
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB7__MASK EQU 0x10\r
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out_DBx__DB7__PORT EQU 4\r
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB7__SHIFT EQU 4\r
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW\r
\r
-/* USBFS_Dp */\r
-USBFS_Dp__0__MASK EQU 0x40\r
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0\r
-USBFS_Dp__0__PORT EQU 15\r
-USBFS_Dp__0__SHIFT EQU 6\r
-USBFS_Dp__AG EQU CYREG_PRT15_AG\r
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX\r
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE\r
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP\r
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL\r
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0\r
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1\r
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2\r
-USBFS_Dp__DR EQU CYREG_PRT15_DR\r
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT\r
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-USBFS_Dp__MASK EQU 0x40\r
-USBFS_Dp__PORT EQU 15\r
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT\r
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-USBFS_Dp__PS EQU CYREG_PRT15_PS\r
-USBFS_Dp__SHIFT EQU 6\r
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW\r
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15\r
+/* SD_PULLUP */\r
+SD_PULLUP__0__MASK EQU 0x02\r
+SD_PULLUP__0__PC EQU CYREG_PRT3_PC1\r
+SD_PULLUP__0__PORT EQU 3\r
+SD_PULLUP__0__SHIFT EQU 1\r
+SD_PULLUP__1__MASK EQU 0x04\r
+SD_PULLUP__1__PC EQU CYREG_PRT3_PC2\r
+SD_PULLUP__1__PORT EQU 3\r
+SD_PULLUP__1__SHIFT EQU 2\r
+SD_PULLUP__2__MASK EQU 0x08\r
+SD_PULLUP__2__PC EQU CYREG_PRT3_PC3\r
+SD_PULLUP__2__PORT EQU 3\r
+SD_PULLUP__2__SHIFT EQU 3\r
+SD_PULLUP__3__MASK EQU 0x10\r
+SD_PULLUP__3__PC EQU CYREG_PRT3_PC4\r
+SD_PULLUP__3__PORT EQU 3\r
+SD_PULLUP__3__SHIFT EQU 4\r
+SD_PULLUP__4__MASK EQU 0x20\r
+SD_PULLUP__4__PC EQU CYREG_PRT3_PC5\r
+SD_PULLUP__4__PORT EQU 3\r
+SD_PULLUP__4__SHIFT EQU 5\r
+SD_PULLUP__AG EQU CYREG_PRT3_AG\r
+SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX\r
+SD_PULLUP__BIE EQU CYREG_PRT3_BIE\r
+SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_PULLUP__BYP EQU CYREG_PRT3_BYP\r
+SD_PULLUP__CTL EQU CYREG_PRT3_CTL\r
+SD_PULLUP__DM0 EQU CYREG_PRT3_DM0\r
+SD_PULLUP__DM1 EQU CYREG_PRT3_DM1\r
+SD_PULLUP__DM2 EQU CYREG_PRT3_DM2\r
+SD_PULLUP__DR EQU CYREG_PRT3_DR\r
+SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_PULLUP__MASK EQU 0x3E\r
+SD_PULLUP__PORT EQU 3\r
+SD_PULLUP__PRT EQU CYREG_PRT3_PRT\r
+SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_PULLUP__PS EQU CYREG_PRT3_PS\r
+SD_PULLUP__SHIFT EQU 1\r
+SD_PULLUP__SLW EQU CYREG_PRT3_SLW\r
\r
/* Miscellaneous */\r
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */\r
-CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0\r
-CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6\r
-CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0\r
-CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0\r
-CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1\r
-CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0\r
-CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
-CYDEV_CHIP_MEMBER_5B EQU 4\r
-CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
-CYDEV_CHIP_DIE_PSOC5LP EQU 4\r
-CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP\r
-CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1\r
BCLK__BUS_CLK__HZ EQU 64000000\r
BCLK__BUS_CLK__KHZ EQU 64000\r
BCLK__BUS_CLK__MHZ EQU 64\r
CYDEV_BOOTLOADER_APPLICATIONS EQU 1\r
CYDEV_BOOTLOADER_CHECKSUM_BASIC EQU 0\r
CYDEV_BOOTLOADER_CHECKSUM_CRC EQU 1\r
+CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0\r
+CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO\r
+CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1\r
+CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS\r
CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS\r
-CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT\r
CYDEV_CHIP_DIE_LEOPARD EQU 1\r
-CYDEV_CHIP_DIE_PANTHER EQU 3\r
-CYDEV_CHIP_DIE_PSOC4A EQU 2\r
+CYDEV_CHIP_DIE_PANTHER EQU 6\r
+CYDEV_CHIP_DIE_PSOC4A EQU 3\r
+CYDEV_CHIP_DIE_PSOC5LP EQU 5\r
CYDEV_CHIP_DIE_UNKNOWN EQU 0\r
CYDEV_CHIP_FAMILY_PSOC3 EQU 1\r
CYDEV_CHIP_FAMILY_PSOC4 EQU 2\r
+CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0\r
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5\r
CYDEV_CHIP_JTAG_ID EQU 0x2E133069\r
CYDEV_CHIP_MEMBER_3A EQU 1\r
-CYDEV_CHIP_MEMBER_4A EQU 2\r
-CYDEV_CHIP_MEMBER_5A EQU 3\r
+CYDEV_CHIP_MEMBER_4A EQU 3\r
+CYDEV_CHIP_MEMBER_4D EQU 2\r
+CYDEV_CHIP_MEMBER_4F EQU 4\r
+CYDEV_CHIP_MEMBER_5A EQU 6\r
+CYDEV_CHIP_MEMBER_5B EQU 5\r
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0\r
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B\r
+CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED\r
+CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT\r
+CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0\r
+CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1\r
+CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3\r
+CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3\r
+CYDEV_CHIP_REV_PANTHER_ES0 EQU 0\r
+CYDEV_CHIP_REV_PANTHER_ES1 EQU 1\r
+CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1\r
+CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17\r
+CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17\r
+CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0\r
+CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_3A_ES1 EQU 0\r
CYDEV_CHIP_REVISION_3A_ES2 EQU 1\r
CYDEV_CHIP_REVISION_3A_ES3 EQU 3\r
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3\r
CYDEV_CHIP_REVISION_4A_ES0 EQU 17\r
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17\r
+CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_5A_ES0 EQU 0\r
CYDEV_CHIP_REVISION_5A_ES1 EQU 1\r
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1\r
CYDEV_CHIP_REVISION_5B_ES0 EQU 0\r
+CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION\r
-CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION\r
-CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0\r
-CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1\r
-CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3\r
-CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3\r
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0\r
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1\r
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1\r
-CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17\r
-CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17\r
-CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0\r
+CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED\r
+CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1\r
+CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0\r
+CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
+CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1\r
+CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2\r
CYDEV_CONFIGURATION_COMPRESSED EQU 1\r
CYDEV_CONFIGURATION_DMA EQU 0\r
CYDEV_CONFIGURATION_ECC EQU 0\r
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED\r
+CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0\r
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED\r
CYDEV_CONFIGURATION_MODE_DMA EQU 2\r
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1\r
-CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
-CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1\r
-CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2\r
-CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV\r
+CYDEV_DEBUG_ENABLE_MASK EQU 0x20\r
+CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG\r
CYDEV_DEBUGGING_DPS_Disable EQU 3\r
CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1\r
CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0\r
CYDEV_DEBUGGING_DPS_SWD EQU 2\r
+CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6\r
+CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV\r
CYDEV_DEBUGGING_ENABLE EQU 1\r
CYDEV_DEBUGGING_XRES EQU 0\r
-CYDEV_DEBUG_ENABLE_MASK EQU 0x20\r
-CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG\r
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24\r
CYDEV_ECC_ENABLE EQU 0\r
CYDEV_HEAP_SIZE EQU 0x0800\r
CYDEV_VDDIO1_MV EQU 5000\r
CYDEV_VDDIO2_MV EQU 5000\r
CYDEV_VDDIO3_MV EQU 5000\r
-CYDEV_VIO0 EQU 5\r
CYDEV_VIO0_MV EQU 5000\r
-CYDEV_VIO1 EQU 5\r
CYDEV_VIO1_MV EQU 5000\r
-CYDEV_VIO2 EQU 5\r
CYDEV_VIO2_MV EQU 5000\r
-CYDEV_VIO3 EQU 5\r
CYDEV_VIO3_MV EQU 5000\r
-CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO\r
-CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS\r
+CYIPBLOCK_ARM_CM3_VERSION EQU 0\r
+CYIPBLOCK_P3_ANAIF_VERSION EQU 0\r
+CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0\r
+CYIPBLOCK_P3_COMP_VERSION EQU 0\r
+CYIPBLOCK_P3_DMA_VERSION EQU 0\r
+CYIPBLOCK_P3_DRQ_VERSION EQU 0\r
+CYIPBLOCK_P3_EMIF_VERSION EQU 0\r
+CYIPBLOCK_P3_I2C_VERSION EQU 0\r
+CYIPBLOCK_P3_LCD_VERSION EQU 0\r
+CYIPBLOCK_P3_LPF_VERSION EQU 0\r
+CYIPBLOCK_P3_PM_VERSION EQU 0\r
+CYIPBLOCK_P3_TIMER_VERSION EQU 0\r
+CYIPBLOCK_P3_USB_VERSION EQU 0\r
+CYIPBLOCK_P3_VIDAC_VERSION EQU 0\r
+CYIPBLOCK_P3_VREF_VERSION EQU 0\r
+CYIPBLOCK_S8_GPIO_VERSION EQU 0\r
+CYIPBLOCK_S8_IRQ_VERSION EQU 0\r
+CYIPBLOCK_S8_SAR_VERSION EQU 0\r
+CYIPBLOCK_S8_SIO_VERSION EQU 0\r
+CYIPBLOCK_S8_UDB_VERSION EQU 0\r
DMA_CHANNELS_USED__MASK0 EQU 0x00000000\r
CYDEV_BOOTLOADER_ENABLE EQU 1\r
\r
GET cydevicerv.inc\r
GET cydevicerv_trm.inc\r
\r
+; USBFS_arb_int\r
+USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_arb_int__INTC_MASK EQU 0x400000\r
+USBFS_arb_int__INTC_NUMBER EQU 22\r
+USBFS_arb_int__INTC_PRIOR_NUM EQU 7\r
+USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22\r
+USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
; USBFS_bus_reset\r
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
-; USBFS_arb_int\r
-USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_arb_int__INTC_MASK EQU 0x400000\r
-USBFS_arb_int__INTC_NUMBER EQU 22\r
-USBFS_arb_int__INTC_PRIOR_NUM EQU 7\r
-USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22\r
-USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+; USBFS_Dm\r
+USBFS_Dm__0__MASK EQU 0x80\r
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1\r
+USBFS_Dm__0__PORT EQU 15\r
+USBFS_Dm__0__SHIFT EQU 7\r
+USBFS_Dm__AG EQU CYREG_PRT15_AG\r
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX\r
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE\r
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP\r
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL\r
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0\r
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1\r
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2\r
+USBFS_Dm__DR EQU CYREG_PRT15_DR\r
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+USBFS_Dm__MASK EQU 0x80\r
+USBFS_Dm__PORT EQU 15\r
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT\r
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+USBFS_Dm__PS EQU CYREG_PRT15_PS\r
+USBFS_Dm__SHIFT EQU 7\r
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW\r
+\r
+; USBFS_Dp\r
+USBFS_Dp__0__MASK EQU 0x40\r
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0\r
+USBFS_Dp__0__PORT EQU 15\r
+USBFS_Dp__0__SHIFT EQU 6\r
+USBFS_Dp__AG EQU CYREG_PRT15_AG\r
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX\r
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE\r
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP\r
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL\r
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0\r
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1\r
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2\r
+USBFS_Dp__DR EQU CYREG_PRT15_DR\r
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS\r
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT\r
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN\r
+USBFS_Dp__MASK EQU 0x40\r
+USBFS_Dp__PORT EQU 15\r
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT\r
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
+USBFS_Dp__PS EQU CYREG_PRT15_PS\r
+USBFS_Dp__SHIFT EQU 6\r
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW\r
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15\r
+\r
+; USBFS_dp_int\r
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_dp_int__INTC_MASK EQU 0x1000\r
+USBFS_dp_int__INTC_NUMBER EQU 12\r
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7\r
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12\r
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; USBFS_ep_0\r
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_0__INTC_MASK EQU 0x1000000\r
+USBFS_ep_0__INTC_NUMBER EQU 24\r
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24\r
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; USBFS_ep_1\r
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_1__INTC_MASK EQU 0x01\r
+USBFS_ep_1__INTC_NUMBER EQU 0\r
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; USBFS_ep_2\r
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+USBFS_ep_2__INTC_MASK EQU 0x02\r
+USBFS_ep_2__INTC_NUMBER EQU 1\r
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
; USBFS_sof_int\r
USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
-; SCSI_Out_DBx\r
-SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__0__MASK EQU 0x08\r
-SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out_DBx__0__PORT EQU 6\r
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__0__SHIFT EQU 3\r
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__1__MASK EQU 0x04\r
-SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2\r
-SCSI_Out_DBx__1__PORT EQU 6\r
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__1__SHIFT EQU 2\r
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__2__MASK EQU 0x02\r
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out_DBx__2__PORT EQU 6\r
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__2__SHIFT EQU 1\r
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__3__MASK EQU 0x01\r
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out_DBx__3__PORT EQU 6\r
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__3__SHIFT EQU 0\r
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__4__MASK EQU 0x80\r
-SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7\r
-SCSI_Out_DBx__4__PORT EQU 4\r
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__4__SHIFT EQU 7\r
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__5__MASK EQU 0x40\r
-SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6\r
-SCSI_Out_DBx__5__PORT EQU 4\r
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__5__SHIFT EQU 6\r
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__6__MASK EQU 0x20\r
-SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out_DBx__6__PORT EQU 4\r
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__6__SHIFT EQU 5\r
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__7__MASK EQU 0x10\r
-SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out_DBx__7__PORT EQU 4\r
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__7__SHIFT EQU 4\r
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB0__MASK EQU 0x08\r
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3\r
-SCSI_Out_DBx__DB0__PORT EQU 6\r
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB0__SHIFT EQU 3\r
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB1__MASK EQU 0x04\r
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2\r
-SCSI_Out_DBx__DB1__PORT EQU 6\r
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB1__SHIFT EQU 2\r
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB2__MASK EQU 0x02\r
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1\r
-SCSI_Out_DBx__DB2__PORT EQU 6\r
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB2__SHIFT EQU 1\r
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
-SCSI_Out_DBx__DB3__MASK EQU 0x01\r
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0\r
-SCSI_Out_DBx__DB3__PORT EQU 6\r
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
-SCSI_Out_DBx__DB3__SHIFT EQU 0\r
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB4__MASK EQU 0x80\r
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7\r
-SCSI_Out_DBx__DB4__PORT EQU 4\r
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB4__SHIFT EQU 7\r
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB5__MASK EQU 0x40\r
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6\r
-SCSI_Out_DBx__DB5__PORT EQU 4\r
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB5__SHIFT EQU 6\r
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB6__MASK EQU 0x20\r
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5\r
-SCSI_Out_DBx__DB6__PORT EQU 4\r
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB6__SHIFT EQU 5\r
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW\r
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG\r
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX\r
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE\r
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP\r
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL\r
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0\r
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1\r
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2\r
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR\r
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
-SCSI_Out_DBx__DB7__MASK EQU 0x10\r
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4\r
-SCSI_Out_DBx__DB7__PORT EQU 4\r
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT\r
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS\r
-SCSI_Out_DBx__DB7__SHIFT EQU 4\r
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW\r
-\r
-; USBFS_dp_int\r
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_dp_int__INTC_MASK EQU 0x1000\r
-USBFS_dp_int__INTC_NUMBER EQU 12\r
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7\r
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12\r
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_ep_0\r
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_0__INTC_MASK EQU 0x1000000\r
-USBFS_ep_0__INTC_NUMBER EQU 24\r
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24\r
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_ep_1\r
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_1__INTC_MASK EQU 0x01\r
-USBFS_ep_1__INTC_NUMBER EQU 0\r
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; USBFS_ep_2\r
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
-USBFS_ep_2__INTC_MASK EQU 0x02\r
-USBFS_ep_2__INTC_NUMBER EQU 1\r
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7\r
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
-\r
-; SD_PULLUP\r
-SD_PULLUP__0__MASK EQU 0x02\r
-SD_PULLUP__0__PC EQU CYREG_PRT3_PC1\r
-SD_PULLUP__0__PORT EQU 3\r
-SD_PULLUP__0__SHIFT EQU 1\r
-SD_PULLUP__1__MASK EQU 0x04\r
-SD_PULLUP__1__PC EQU CYREG_PRT3_PC2\r
-SD_PULLUP__1__PORT EQU 3\r
-SD_PULLUP__1__SHIFT EQU 2\r
-SD_PULLUP__2__MASK EQU 0x08\r
-SD_PULLUP__2__PC EQU CYREG_PRT3_PC3\r
-SD_PULLUP__2__PORT EQU 3\r
-SD_PULLUP__2__SHIFT EQU 3\r
-SD_PULLUP__3__MASK EQU 0x10\r
-SD_PULLUP__3__PC EQU CYREG_PRT3_PC4\r
-SD_PULLUP__3__PORT EQU 3\r
-SD_PULLUP__3__SHIFT EQU 4\r
-SD_PULLUP__4__MASK EQU 0x20\r
-SD_PULLUP__4__PC EQU CYREG_PRT3_PC5\r
-SD_PULLUP__4__PORT EQU 3\r
-SD_PULLUP__4__SHIFT EQU 5\r
-SD_PULLUP__AG EQU CYREG_PRT3_AG\r
-SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX\r
-SD_PULLUP__BIE EQU CYREG_PRT3_BIE\r
-SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
-SD_PULLUP__BYP EQU CYREG_PRT3_BYP\r
-SD_PULLUP__CTL EQU CYREG_PRT3_CTL\r
-SD_PULLUP__DM0 EQU CYREG_PRT3_DM0\r
-SD_PULLUP__DM1 EQU CYREG_PRT3_DM1\r
-SD_PULLUP__DM2 EQU CYREG_PRT3_DM2\r
-SD_PULLUP__DR EQU CYREG_PRT3_DR\r
-SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS\r
-SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
-SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN\r
-SD_PULLUP__MASK EQU 0x3E\r
-SD_PULLUP__PORT EQU 3\r
-SD_PULLUP__PRT EQU CYREG_PRT3_PRT\r
-SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
-SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
-SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
-SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
-SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
-SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
-SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
-SD_PULLUP__PS EQU CYREG_PRT3_PS\r
-SD_PULLUP__SHIFT EQU 1\r
-SD_PULLUP__SLW EQU CYREG_PRT3_SLW\r
-\r
; USBFS_USB\r
USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG\r
USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG\r
USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES\r
USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB\r
USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG\r
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE\r
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE\r
USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT\r
USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR\r
USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0\r
USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5\r
USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6\r
USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7\r
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE\r
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE\r
USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE\r
USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5\r
USBFS_USB__PM_ACT_MSK EQU 0x01\r
USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5\r
USBFS_USB__PM_STBY_MSK EQU 0x01\r
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN\r
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR\r
USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0\r
USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1\r
USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0\r
USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0\r
USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1\r
USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0\r
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN\r
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR\r
USBFS_USB__SOF0 EQU CYREG_USB_SOF0\r
USBFS_USB__SOF1 EQU CYREG_USB_SOF1\r
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN\r
USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0\r
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1\r
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN\r
\r
; SCSI_Out\r
SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
SCSI_Out__SEL__SHIFT EQU 3\r
SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW\r
\r
-; USBFS_Dm\r
-USBFS_Dm__0__MASK EQU 0x80\r
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1\r
-USBFS_Dm__0__PORT EQU 15\r
-USBFS_Dm__0__SHIFT EQU 7\r
-USBFS_Dm__AG EQU CYREG_PRT15_AG\r
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX\r
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE\r
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP\r
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL\r
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0\r
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1\r
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2\r
-USBFS_Dm__DR EQU CYREG_PRT15_DR\r
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-USBFS_Dm__MASK EQU 0x80\r
-USBFS_Dm__PORT EQU 15\r
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT\r
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-USBFS_Dm__PS EQU CYREG_PRT15_PS\r
-USBFS_Dm__SHIFT EQU 7\r
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW\r
+; SCSI_Out_DBx\r
+SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__0__MASK EQU 0x08\r
+SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out_DBx__0__PORT EQU 6\r
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__0__SHIFT EQU 3\r
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__1__MASK EQU 0x04\r
+SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out_DBx__1__PORT EQU 6\r
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__1__SHIFT EQU 2\r
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__2__MASK EQU 0x02\r
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out_DBx__2__PORT EQU 6\r
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__2__SHIFT EQU 1\r
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__3__MASK EQU 0x01\r
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out_DBx__3__PORT EQU 6\r
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__3__SHIFT EQU 0\r
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__4__MASK EQU 0x80\r
+SCSI_Out_DBx__4__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out_DBx__4__PORT EQU 4\r
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__4__SHIFT EQU 7\r
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__5__MASK EQU 0x40\r
+SCSI_Out_DBx__5__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out_DBx__5__PORT EQU 4\r
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__5__SHIFT EQU 6\r
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__6__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__6__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__6__MASK EQU 0x20\r
+SCSI_Out_DBx__6__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out_DBx__6__PORT EQU 4\r
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__6__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__6__SHIFT EQU 5\r
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__7__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__7__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__7__MASK EQU 0x10\r
+SCSI_Out_DBx__7__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out_DBx__7__PORT EQU 4\r
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__7__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__7__SHIFT EQU 4\r
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB0__MASK EQU 0x08\r
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out_DBx__DB0__PORT EQU 6\r
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB0__SHIFT EQU 3\r
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB1__MASK EQU 0x04\r
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out_DBx__DB1__PORT EQU 6\r
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB1__SHIFT EQU 2\r
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB2__MASK EQU 0x02\r
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out_DBx__DB2__PORT EQU 6\r
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB2__SHIFT EQU 1\r
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG\r
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR\r
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out_DBx__DB3__MASK EQU 0x01\r
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out_DBx__DB3__PORT EQU 6\r
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS\r
+SCSI_Out_DBx__DB3__SHIFT EQU 0\r
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB4__MASK EQU 0x80\r
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out_DBx__DB4__PORT EQU 4\r
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB4__SHIFT EQU 7\r
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB5__MASK EQU 0x40\r
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out_DBx__DB5__PORT EQU 4\r
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB5__SHIFT EQU 6\r
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB6__MASK EQU 0x20\r
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out_DBx__DB6__PORT EQU 4\r
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB6__SHIFT EQU 5\r
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT4_AG\r
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT4_DR\r
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out_DBx__DB7__MASK EQU 0x10\r
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out_DBx__DB7__PORT EQU 4\r
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT4_PS\r
+SCSI_Out_DBx__DB7__SHIFT EQU 4\r
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT4_SLW\r
\r
-; USBFS_Dp\r
-USBFS_Dp__0__MASK EQU 0x40\r
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0\r
-USBFS_Dp__0__PORT EQU 15\r
-USBFS_Dp__0__SHIFT EQU 6\r
-USBFS_Dp__AG EQU CYREG_PRT15_AG\r
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX\r
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE\r
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK\r
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP\r
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL\r
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0\r
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1\r
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2\r
-USBFS_Dp__DR EQU CYREG_PRT15_DR\r
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS\r
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT\r
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG\r
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN\r
-USBFS_Dp__MASK EQU 0x40\r
-USBFS_Dp__PORT EQU 15\r
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT\r
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL\r
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN\r
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0\r
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1\r
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0\r
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1\r
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT\r
-USBFS_Dp__PS EQU CYREG_PRT15_PS\r
-USBFS_Dp__SHIFT EQU 6\r
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW\r
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15\r
+; SD_PULLUP\r
+SD_PULLUP__0__MASK EQU 0x02\r
+SD_PULLUP__0__PC EQU CYREG_PRT3_PC1\r
+SD_PULLUP__0__PORT EQU 3\r
+SD_PULLUP__0__SHIFT EQU 1\r
+SD_PULLUP__1__MASK EQU 0x04\r
+SD_PULLUP__1__PC EQU CYREG_PRT3_PC2\r
+SD_PULLUP__1__PORT EQU 3\r
+SD_PULLUP__1__SHIFT EQU 2\r
+SD_PULLUP__2__MASK EQU 0x08\r
+SD_PULLUP__2__PC EQU CYREG_PRT3_PC3\r
+SD_PULLUP__2__PORT EQU 3\r
+SD_PULLUP__2__SHIFT EQU 3\r
+SD_PULLUP__3__MASK EQU 0x10\r
+SD_PULLUP__3__PC EQU CYREG_PRT3_PC4\r
+SD_PULLUP__3__PORT EQU 3\r
+SD_PULLUP__3__SHIFT EQU 4\r
+SD_PULLUP__4__MASK EQU 0x20\r
+SD_PULLUP__4__PC EQU CYREG_PRT3_PC5\r
+SD_PULLUP__4__PORT EQU 3\r
+SD_PULLUP__4__SHIFT EQU 5\r
+SD_PULLUP__AG EQU CYREG_PRT3_AG\r
+SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX\r
+SD_PULLUP__BIE EQU CYREG_PRT3_BIE\r
+SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_PULLUP__BYP EQU CYREG_PRT3_BYP\r
+SD_PULLUP__CTL EQU CYREG_PRT3_CTL\r
+SD_PULLUP__DM0 EQU CYREG_PRT3_DM0\r
+SD_PULLUP__DM1 EQU CYREG_PRT3_DM1\r
+SD_PULLUP__DM2 EQU CYREG_PRT3_DM2\r
+SD_PULLUP__DR EQU CYREG_PRT3_DR\r
+SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_PULLUP__MASK EQU 0x3E\r
+SD_PULLUP__PORT EQU 3\r
+SD_PULLUP__PRT EQU CYREG_PRT3_PRT\r
+SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_PULLUP__PS EQU CYREG_PRT3_PS\r
+SD_PULLUP__SHIFT EQU 1\r
+SD_PULLUP__SLW EQU CYREG_PRT3_SLW\r
\r
; Miscellaneous\r
-; -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release\r
-CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0\r
-CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6\r
-CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0\r
-CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0\r
-CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1\r
-CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0\r
-CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
-CYDEV_CHIP_MEMBER_5B EQU 4\r
-CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
-CYDEV_CHIP_DIE_PSOC5LP EQU 4\r
-CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP\r
-CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1\r
BCLK__BUS_CLK__HZ EQU 64000000\r
BCLK__BUS_CLK__KHZ EQU 64000\r
BCLK__BUS_CLK__MHZ EQU 64\r
CYDEV_BOOTLOADER_APPLICATIONS EQU 1\r
CYDEV_BOOTLOADER_CHECKSUM_BASIC EQU 0\r
CYDEV_BOOTLOADER_CHECKSUM_CRC EQU 1\r
+CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0\r
+CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO\r
+CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1\r
+CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS\r
CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS\r
-CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT\r
CYDEV_CHIP_DIE_LEOPARD EQU 1\r
-CYDEV_CHIP_DIE_PANTHER EQU 3\r
-CYDEV_CHIP_DIE_PSOC4A EQU 2\r
+CYDEV_CHIP_DIE_PANTHER EQU 6\r
+CYDEV_CHIP_DIE_PSOC4A EQU 3\r
+CYDEV_CHIP_DIE_PSOC5LP EQU 5\r
CYDEV_CHIP_DIE_UNKNOWN EQU 0\r
CYDEV_CHIP_FAMILY_PSOC3 EQU 1\r
CYDEV_CHIP_FAMILY_PSOC4 EQU 2\r
+CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0\r
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5\r
CYDEV_CHIP_JTAG_ID EQU 0x2E133069\r
CYDEV_CHIP_MEMBER_3A EQU 1\r
-CYDEV_CHIP_MEMBER_4A EQU 2\r
-CYDEV_CHIP_MEMBER_5A EQU 3\r
+CYDEV_CHIP_MEMBER_4A EQU 3\r
+CYDEV_CHIP_MEMBER_4D EQU 2\r
+CYDEV_CHIP_MEMBER_4F EQU 4\r
+CYDEV_CHIP_MEMBER_5A EQU 6\r
+CYDEV_CHIP_MEMBER_5B EQU 5\r
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0\r
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B\r
+CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED\r
+CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT\r
+CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0\r
+CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1\r
+CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3\r
+CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3\r
+CYDEV_CHIP_REV_PANTHER_ES0 EQU 0\r
+CYDEV_CHIP_REV_PANTHER_ES1 EQU 1\r
+CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1\r
+CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17\r
+CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17\r
+CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0\r
+CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_3A_ES1 EQU 0\r
CYDEV_CHIP_REVISION_3A_ES2 EQU 1\r
CYDEV_CHIP_REVISION_3A_ES3 EQU 3\r
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3\r
CYDEV_CHIP_REVISION_4A_ES0 EQU 17\r
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17\r
+CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_5A_ES0 EQU 0\r
CYDEV_CHIP_REVISION_5A_ES1 EQU 1\r
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1\r
CYDEV_CHIP_REVISION_5B_ES0 EQU 0\r
+CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION\r
-CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION\r
-CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0\r
-CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1\r
-CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3\r
-CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3\r
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0\r
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1\r
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1\r
-CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17\r
-CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17\r
-CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0\r
+CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED\r
+CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1\r
+CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0\r
+CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
+CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1\r
+CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2\r
CYDEV_CONFIGURATION_COMPRESSED EQU 1\r
CYDEV_CONFIGURATION_DMA EQU 0\r
CYDEV_CONFIGURATION_ECC EQU 0\r
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED\r
+CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0\r
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED\r
CYDEV_CONFIGURATION_MODE_DMA EQU 2\r
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1\r
-CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
-CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1\r
-CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2\r
-CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV\r
+CYDEV_DEBUG_ENABLE_MASK EQU 0x20\r
+CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG\r
CYDEV_DEBUGGING_DPS_Disable EQU 3\r
CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1\r
CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0\r
CYDEV_DEBUGGING_DPS_SWD EQU 2\r
+CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6\r
+CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV\r
CYDEV_DEBUGGING_ENABLE EQU 1\r
CYDEV_DEBUGGING_XRES EQU 0\r
-CYDEV_DEBUG_ENABLE_MASK EQU 0x20\r
-CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG\r
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24\r
CYDEV_ECC_ENABLE EQU 0\r
CYDEV_HEAP_SIZE EQU 0x0800\r
CYDEV_VDDIO1_MV EQU 5000\r
CYDEV_VDDIO2_MV EQU 5000\r
CYDEV_VDDIO3_MV EQU 5000\r
-CYDEV_VIO0 EQU 5\r
CYDEV_VIO0_MV EQU 5000\r
-CYDEV_VIO1 EQU 5\r
CYDEV_VIO1_MV EQU 5000\r
-CYDEV_VIO2 EQU 5\r
CYDEV_VIO2_MV EQU 5000\r
-CYDEV_VIO3 EQU 5\r
CYDEV_VIO3_MV EQU 5000\r
-CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO\r
-CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS\r
+CYIPBLOCK_ARM_CM3_VERSION EQU 0\r
+CYIPBLOCK_P3_ANAIF_VERSION EQU 0\r
+CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0\r
+CYIPBLOCK_P3_COMP_VERSION EQU 0\r
+CYIPBLOCK_P3_DMA_VERSION EQU 0\r
+CYIPBLOCK_P3_DRQ_VERSION EQU 0\r
+CYIPBLOCK_P3_EMIF_VERSION EQU 0\r
+CYIPBLOCK_P3_I2C_VERSION EQU 0\r
+CYIPBLOCK_P3_LCD_VERSION EQU 0\r
+CYIPBLOCK_P3_LPF_VERSION EQU 0\r
+CYIPBLOCK_P3_PM_VERSION EQU 0\r
+CYIPBLOCK_P3_TIMER_VERSION EQU 0\r
+CYIPBLOCK_P3_USB_VERSION EQU 0\r
+CYIPBLOCK_P3_VIDAC_VERSION EQU 0\r
+CYIPBLOCK_P3_VREF_VERSION EQU 0\r
+CYIPBLOCK_S8_GPIO_VERSION EQU 0\r
+CYIPBLOCK_S8_IRQ_VERSION EQU 0\r
+CYIPBLOCK_S8_SAR_VERSION EQU 0\r
+CYIPBLOCK_S8_SIO_VERSION EQU 0\r
+CYIPBLOCK_S8_UDB_VERSION EQU 0\r
DMA_CHANNELS_USED__MASK0 EQU 0x00000000\r
CYDEV_BOOTLOADER_ENABLE EQU 1\r
ENDIF\r
/*******************************************************************************\r
* FILENAME: cymetadata.c\r
* \r
-* PSoC Creator 3.0 Component Pack 7\r
+* PSoC Creator 3.1\r
*\r
* DESCRIPTION:\r
* This file defines all extra memory spaces that need to be included.\r
/*******************************************************************************\r
* File Name: cypins.h\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
-* This file contains the function prototypes and constants used for port/pin\r
+* This file contains the function prototypes and constants used for a port/pin\r
* in access and control.\r
*\r
* Note:\r
* System Reference Guide provided with PSoC Creator.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
* Note that this only has an effect for pins configured as software pins that\r
* are not driven by hardware.\r
*\r
+* The macro operation is not atomic. It is not guaranteed that shared register\r
+* will remain uncorrupted during simultaneous read-modify-write operations\r
+* performed by two threads (main and interrupt threads). To guarantee data\r
+* integrity in such cases, the macro should be invoked while the specific\r
+* interrupt is disabled or within critical section (all interrupts are\r
+* disabled).\r
+*\r
* Parameters:\r
* pinPC: Port pin configuration register (uint16).\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
********************************************************************************\r
*\r
* Summary:\r
-* This macro sets the state of the specified pin to 0\r
+* This macro sets the state of the specified pin to 0.\r
+*\r
+* The macro operation is not atomic. It is not guaranteed that shared register\r
+* will remain uncorrupted during simultaneous read-modify-write operations\r
+* performed by two threads (main and interrupt threads). To guarantee data\r
+* integrity in such cases, the macro should be invoked while the specific\r
+* interrupt is disabled or within critical section (all interrupts are\r
+* disabled).\r
*\r
* Parameters:\r
* pinPC: address of a Pin Configuration register.\r
* Summary:\r
* Sets the drive mode for the pin (DM).\r
*\r
+* The macro operation is not atomic. It is not guaranteed that shared register\r
+* will remain uncorrupted during simultaneous read-modify-write operations\r
+* performed by two threads (main and interrupt threads). To guarantee data\r
+* integrity in such cases, the macro should be invoked while the specific\r
+* interrupt is disabled or within critical section (all interrupts are\r
+* disabled).\r
+*\r
* Parameters:\r
* pinPC: Port pin configuration register (uint16)\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
*\r
*\r
* Return:\r
-* mode: Current drive mode for the pin\r
+* mode: The current drive mode for the pin\r
*\r
* Define Source\r
* PIN_DM_ALG_HIZ Analog HiZ\r
********************************************************************************\r
*\r
* Summary:\r
-* Set the slew rate for the pin to fast edge rate.\r
+* Set the slew rate for the pin to fast the edge rate.\r
* Note that this only applies for pins in strong output drive modes,\r
* not to resistive drive modes.\r
*\r
+* The macro operation is not atomic. It is not guaranteed that shared register\r
+* will remain uncorrupted during simultaneous read-modify-write operations\r
+* performed by two threads (main and interrupt threads). To guarantee data\r
+* integrity in such cases, the macro should be invoked while the specific\r
+* interrupt is disabled or within critical section (all interrupts are\r
+* disabled).\r
+*\r
* Parameters:\r
* pinPC: address of a Pin Configuration register.\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
********************************************************************************\r
*\r
* Summary:\r
-* Set the slew rate for the pin to slow edge rate.\r
+* Set the slew rate for the pin to slow the edge rate.\r
* Note that this only applies for pins in strong output drive modes,\r
* not to resistive drive modes.\r
*\r
+* The macro operation is not atomic. It is not guaranteed that shared register\r
+* will remain uncorrupted during simultaneous read-modify-write operations\r
+* performed by two threads (main and interrupt threads). To guarantee data\r
+* integrity in such cases, the macro should be invoked while the specific\r
+* interrupt is disabled or within critical section (all interrupts are\r
+* disabled).\r
+*\r
* Parameters:\r
* pinPC: address of a Pin Configuration register.\r
* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30\r
+* The following code is OBSOLETE and must not be used.\r
+*\r
+* If the obsoleted macro definitions intended for use in the application use the\r
+* following scheme, redefine your own versions of these definitions:\r
+* #ifdef <OBSOLETED_DEFINE>\r
+* #undef <OBSOLETED_DEFINE>\r
+* #define <OBSOLETED_DEFINE> (<New Value>)\r
+* #endif\r
+*\r
+* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* used in the application and their modification might lead to unexpected\r
+* consequences.\r
*******************************************************************************/\r
#define PC_DRIVE_MODE_SHIFT (CY_PINS_PC_DRIVE_MODE_SHIFT)\r
#define PC_DRIVE_MODE_MASK (CY_PINS_PC_DRIVE_MODE_MASK)\r
/*******************************************************************************\r
* FILENAME: cytypes.h\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
* CyTypes provides register access macros and approved types for use in\r
* data the correct way.\r
*\r
* Register Access macros and functions perform their operations on an\r
-* input of type pointer to void. The arguments passed to it should be\r
+* input of the type pointer to void. The arguments passed to it should be\r
* pointers to the type associated with the register size.\r
* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value)\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
\r
#if defined( __ICCARM__ )\r
/* Suppress warning for multiple volatile variables in an expression. */\r
- /* This is common in component code and the usage is not order dependent. */\r
+ /* This is common in component code and usage is not order dependent. */\r
#pragma diag_suppress=Pa082\r
#endif /* defined( __ICCARM__ ) */\r
\r
/*******************************************************************************\r
* MEMBER encodes both the family and the detailed architecture\r
*******************************************************************************/\r
-#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)\r
#ifdef CYDEV_CHIP_MEMBER_4D\r
- #define CY_PSOC4D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)\r
- #define CY_PSOC4SF (CY_PSOC4D)\r
+ #define CY_PSOC4_4000 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)\r
#else\r
- #define CY_PSOC4D (0u != 0u)\r
- #define CY_PSOC4SF (CY_PSOC4D)\r
+ #define CY_PSOC4_4000 (0u != 0u)\r
#endif /* CYDEV_CHIP_MEMBER_4D */\r
\r
-#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)\r
-#ifdef CYDEV_CHIP_MEMBER_5B\r
- #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)\r
+#define CY_PSOC4_4100 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)\r
+#define CY_PSOC4_4200 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)\r
+\r
+#ifdef CYDEV_CHIP_MEMBER_4F\r
+ #define CY_PSOC4_4100BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F)\r
+ #define CY_PSOC4_4200BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F)\r
#else\r
- #define CY_PSOC5LP (0u != 0u)\r
-#endif /* CYDEV_CHIP_MEMBER_5B */\r
+ #define CY_PSOC4_4100BL (0u != 0u)\r
+ #define CY_PSOC4_4200BL (0u != 0u)\r
+#endif /* CYDEV_CHIP_MEMBER_4F */\r
\r
\r
/*******************************************************************************\r
-* UDB revisions\r
+* IP blocks\r
*******************************************************************************/\r
-#define CY_UDB_V0 (CY_PSOC5A)\r
-#define CY_UDB_V1 (!CY_UDB_V0)\r
+#if (CY_PSOC4)\r
+\r
+ /* Using SRSSv2 or SRS-Lite */\r
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
+ #define CY_IP_SRSSV2 (0u == 0u)\r
+ #define CY_IP_SRSSLT (!CY_IP_SRSSV2)\r
+ #else\r
+ #define CY_IP_SRSSV2 (0u != 0u)\r
+ #define CY_IP_SRSSLT (!CY_IP_SRSSV2)\r
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+\r
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
+ #define CY_IP_CPUSSV2 (0u != 0u)\r
+ #define CY_IP_CPUSS (0u == 0u)\r
+ #else\r
+ #define CY_IP_CPUSSV2 (0u != 0u)\r
+ #define CY_IP_CPUSS (!CY_IP_CPUSSV2)\r
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+\r
+ /* Product uses FLASH-Lite or regular FLASH */\r
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
+ #define CY_IP_FMLT (0u != 0u) /* FLASH-Lite */\r
+ #define CY_IP_FM (!CY_IP_FMLT) /* Regular FLASH */\r
+ #else\r
+ #define CY_IP_FMLT (-1u != 0u)\r
+ #define CY_IP_FM (!CY_IP_FMLT)\r
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+\r
+ /* Number of interrupt request inputs to CM0 */\r
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
+ #define CY_IP_INT_NR (32u)\r
+ #else\r
+ #define CY_IP_INT_NR (-1u)\r
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+\r
+ /* Number of Flash macros used in the device (0, 1 or 2) */\r
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
+ #define CY_IP_FLASH_MACROS (1u)\r
+ #else\r
+ #define CY_IP_FLASH_MACROS (-1u)\r
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+\r
+\r
+ /* Number of Flash macros used in the device (0, 1 or 2) */\r
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)\r
+ #define CY_IP_BLESS (0u != 0u)\r
+ #else\r
+ #define CY_IP_BLESS (0u != 0u)\r
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+\r
+ /* Watch Crystal Oscillator (WCO) is present (32kHz) */\r
+ #if (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200)\r
+ #define CY_IP_WCO (0u != 0u)\r
+ #elif CY_IP_BLESS || defined (CYIPBLOCK_s8swco_VERSION)\r
+ #define CY_IP_WCO (0u == 0u)\r
+ #elif (CY_IP_SRSSV2)\r
+ #define CY_IP_WCO (-1u)\r
+ #else\r
+ #define CY_IP_WCO (0u != 0u)\r
+ #endif /* (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200) */\r
+\r
+#endif /* (CY_PSOC4) */\r
+\r
+\r
+/*******************************************************************************\r
+* The components version defines. Available started from cy_boot 4.20\r
+* Use the following construction in order to identify cy_boot version:\r
+* (defined(CY_BOOT_VERSION) && CY_BOOT_VERSION >= CY_BOOT_4_20)\r
+*******************************************************************************/\r
+#define CY_BOOT_4_20 (420u)\r
+#define CY_BOOT_VERSION (CY_BOOT_4_20)\r
\r
\r
/*******************************************************************************\r
\r
#endif /* (!CY_PSOC3) */\r
\r
-/* Signed or unsigned depending on the compiler selection */\r
+/* Signed or unsigned depending on compiler selection */\r
typedef char char8;\r
\r
\r
\r
#else\r
\r
- /* Prototype for function to set a 24-bit register. Located at cyutils.c */\r
+ /* Prototype for function to set 24-bit register. Located at cyutils.c */\r
extern void CySetReg24(uint32 volatile * addr, uint32 value);\r
\r
#if(CY_PSOC4)\r
#define XDATA\r
\r
#if defined(__ARMCC_VERSION)\r
+\r
#define CY_NOINIT __attribute__ ((section(".noinit"), zero_init))\r
#define CY_NORETURN __attribute__ ((noreturn))\r
#define CY_SECTION(name) __attribute__ ((section(name)))\r
+\r
+ /* Specifies a minimum alignment (in bytes) for variables of the\r
+ * specified type.\r
+ */\r
#define CY_ALIGN(align) __align(align)\r
+\r
+\r
+ /* Attached to an enum, struct, or union type definition, specified that\r
+ * the minimum required memory be used to represent the type.\r
+ */\r
+ #define CY_PACKED\r
+ #define CY_PACKED_ATTR __attribute__ ((packed))\r
+ #define CY_INLINE __inline\r
#elif defined (__GNUC__)\r
+\r
#define CY_NOINIT __attribute__ ((section(".noinit")))\r
#define CY_NORETURN __attribute__ ((noreturn))\r
#define CY_SECTION(name) __attribute__ ((section(name)))\r
#define CY_ALIGN(align) __attribute__ ((aligned(align)))\r
+ #define CY_PACKED\r
+ #define CY_PACKED_ATTR __attribute__ ((packed))\r
+ #define CY_INLINE inline\r
#elif defined (__ICCARM__)\r
+\r
#define CY_NOINIT __no_init\r
#define CY_NORETURN __noreturn\r
+ #define CY_PACKED __packed\r
+ #define CY_PACKED_ATTR\r
+ #define CY_INLINE inline\r
#endif /* (__ARMCC_VERSION) */\r
\r
#endif /* (CY_PSOC3) */\r
\r
#if(CY_PSOC3)\r
\r
- /* 8051 naturally returns an 8 bit value. */\r
+ /* 8051 naturally returns 8 bit value. */\r
typedef unsigned char cystatus;\r
\r
#else\r
\r
- /* ARM naturally returns a 32 bit value. */\r
+ /* ARM naturally returns 32 bit value. */\r
typedef unsigned long cystatus;\r
\r
#endif /* (CY_PSOC3) */\r
* KEIL for the 8051 is a big endian compiler This causes problems as the on chip\r
* registers are little endian. Byte swapping for two and four byte registers is\r
* implemented in the functions below. This will require conditional compilation\r
- * of function prototypes in code.\r
+ * of function prototypes in the code.\r
*******************************************************************************/\r
\r
/* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */\r
* Data manipulation defines\r
*******************************************************************************/\r
\r
-/* Get 8 bits of a 16 bit value. */\r
+/* Get 8 bits of 16 bit value. */\r
#define LO8(x) ((uint8) ((x) & 0xFFu))\r
#define HI8(x) ((uint8) ((uint16)(x) >> 8))\r
\r
-/* Get 16 bits of a 32 bit value. */\r
+/* Get 16 bits of 32 bit value. */\r
#define LO16(x) ((uint16) ((x) & 0xFFFFu))\r
#define HI16(x) ((uint16) ((uint32)(x) >> 16))\r
\r
-/* Swap the byte ordering of a 32 bit value */\r
+/* Swap the byte ordering of 32 bit value */\r
#define CYSWAP_ENDIAN32(x) \\r
((uint32)(((x) >> 24) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24)))\r
\r
-/* Swap the byte ordering of a 16 bit value */\r
+/* Swap the byte ordering of 16 bit value */\r
#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | ((x) >> 8)))\r
\r
\r
/*******************************************************************************\r
-* Defines the standard return values used PSoC content. A function is\r
+* Defines the standard return values used in PSoC content. A function is\r
* not limited to these return values but can use them when returning standard\r
* error values. Return values can be overloaded if documented in the function\r
* header. On the 8051 a function can use a larger return type but still use the\r
\r
\r
/*******************************************************************************\r
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.10\r
+* The following code is OBSOLETE and must not be used starting from cy_boot 3.10\r
+*\r
+* If the obsoleted macro definitions intended for use in the application use the\r
+* following scheme, redefine your own versions of these definitions:\r
+* #ifdef <OBSOLETED_DEFINE>\r
+* #undef <OBSOLETED_DEFINE>\r
+* #define <OBSOLETED_DEFINE> (<New Value>)\r
+* #endif\r
+*\r
+* Note: Redefine obsoleted macro definitions with caution. They might still be\r
+* used in the application and their modification might lead to unexpected\r
+* consequences.\r
*******************************************************************************/\r
+#define CY_UDB_V0 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)\r
+#define CY_UDB_V1 (!CY_UDB_V0)\r
+#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)\r
+#ifdef CYDEV_CHIP_MEMBER_4D\r
+ #define CY_PSOC4D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)\r
+ #define CY_PSOC4SF (CY_PSOC4D)\r
+#else\r
+ #define CY_PSOC4D (0u != 0u)\r
+ #define CY_PSOC4SF (CY_PSOC4D)\r
+#endif /* CYDEV_CHIP_MEMBER_4D */\r
+#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)\r
+#ifdef CYDEV_CHIP_MEMBER_5B\r
+ #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)\r
+#else\r
+ #define CY_PSOC5LP (0u != 0u)\r
+#endif /* CYDEV_CHIP_MEMBER_5B */\r
+\r
+#if (!CY_PSOC4)\r
+\r
+ /* Device is PSoC 3 and the revision is ES2 or earlier */\r
+ #define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \\r
+ (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2))\r
\r
-/* Device is PSoC 3 and the revision is ES2 or earlier */\r
-#define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \\r
- (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2))\r
+ /* Device is PSoC 3 and the revision is ES3 or later */\r
+ #define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \\r
+ (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3))\r
\r
-/* Device is PSoC 3 and the revision is ES3 or later */\r
-#define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \\r
- (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3))\r
+ /* Device is PSoC 5 and the revision is ES1 or earlier */\r
+ #define CY_PSOC5_ES1 (CY_PSOC5A && \\r
+ (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1))\r
\r
-/* Device is PSoC 5 and the revision is ES1 or earlier */\r
-#define CY_PSOC5_ES1 (CY_PSOC5A && \\r
- (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1))\r
+ /* Device is PSoC 5 and the revision is ES2 or later */\r
+ #define CY_PSOC5_ES2 (CY_PSOC5A && \\r
+ (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1))\r
\r
-/* Device is PSoC 5 and the revision is ES2 or later */\r
-#define CY_PSOC5_ES2 (CY_PSOC5A && \\r
- (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1))\r
+#endif /* (!CY_PSOC4) */\r
\r
#endif /* CY_BOOT_CYTYPES_H */\r
\r
/*******************************************************************************\r
* FILENAME: cyutils.c\r
-* Version 4.0\r
+* Version 4.20\r
*\r
* Description:\r
-* CyUtils provides function to handle 24-bit value writes.\r
+* CyUtils provides a function to handle 24-bit value writes.\r
*\r
********************************************************************************\r
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.\r
* You may use this file only in accordance with the license, terms, conditions,\r
* disclaimers, and limitations in the end user license agreement accompanying\r
* the software package with which this file was provided.\r
****************************************************************************\r
*\r
* Summary:\r
- * Writes the 24-bit value to the specified register.\r
+ * Writes a 24-bit value to the specified register.\r
*\r
* Parameters:\r
- * addr : adress where data must be written\r
- * value: data that must be written\r
+ * addr : the address where data must be written.\r
+ * value: the data that must be written.\r
*\r
* Return:\r
* None\r
* Reads the 24-bit value from the specified register.\r
*\r
* Parameters:\r
- * addr : adress where data must be read\r
+ * addr : the address where data must be read.\r
*\r
* Return:\r
* None\r
/*******************************************************************************\r
* File Name: project.h\r
- * PSoC Creator 3.0 Component Pack 7\r
+ * PSoC Creator 3.1\r
*\r
* Description:\r
* This file is automatically generated by PSoC Creator and should not \r
<block name="SD_PULLUP" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">\r
- <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0">\r
<field name="fsusbio_ref_en" from="0" to="0" access="RW" resetVal="" desc="" />\r
<field name="fsusbio_pd_n" from="1" to="1" access="RW" resetVal="" desc="" />\r
<register name="USBFS_EP0_DR6" address="0x40006006" bitWidth="8" desc="lengthLo" />\r
<register name="USBFS_EP0_DR7" address="0x40006007" bitWidth="8" desc="lengthHi" />\r
<register name="USBFS_CR0" address="0x40006008" bitWidth="8" desc="USB Control Register 0">\r
- <field name="device_address" from="0" to="6" access="R" resetVal="" desc="" />\r
+ <field name="device_address" from="6" to="0" access="R" resetVal="" desc="" />\r
<field name="usb_enable" from="7" to="7" access="RW" resetVal="" desc="" />\r
</register>\r
<register name="USBFS_CR1" address="0x40006009" bitWidth="8" desc="USB Control Register 1">\r
<GlobalPages />\r
<GlobalTools name="Code Generation">\r
<GlobalPages>\r
+<name_val_pair name="General@Application Type" v="Bootloader" />\r
+<name_val_pair name="General@Custom Code Gen Options" v="" />\r
+<name_val_pair name="General@Skip Code Generation" v="False" />\r
+<name_val_pair name="General@Custom Synthesis Options" v="" />\r
+<name_val_pair name="General@Quiet Output" v="True" />\r
<name_val_pair name="General@Synthesis Goal" v="Speed" />\r
<name_val_pair name="General@Synthesis Optimization Effort" v="Exhaustive" />\r
-<name_val_pair name="General@Quiet Output" v="True" />\r
-<name_val_pair name="General@Custom Synthesis Options" v="" />\r
-<name_val_pair name="General@Skip Code Generation" v="False" />\r
-<name_val_pair name="General@Custom Code Gen Options" v="" />\r
<name_val_pair name="General@Virtual Node Substitution" v="3" />\r
-<name_val_pair name="General@Application Type" v="Bootloader" />\r
<name_val_pair name="General@Custom Fitter Options" v="" />\r
</GlobalPages>\r
</GlobalTools>\r
</GlobalTools>\r
<GlobalTools name="Customizer">\r
<GlobalPages>\r
-<name_val_pair name="General@Customizer Build Mode" v="Release" />\r
-<name_val_pair name="General@Command Line Options" v="" />\r
<name_val_pair name="General@Assembly References" v="" />\r
+<name_val_pair name="General@Command Line Options" v="" />\r
+<name_val_pair name="General@Customizer Build Mode" v="Release" />\r
</GlobalPages>\r
</GlobalTools>\r
</name>\r
<platform>\r
<name v="c9323d49-d323-40b8-9b59-cc008d68a989">\r
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />\r
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+<dep name=".\CortexM3\ARM_GCC_484\Release\cyutils.o" />\r
+<dep name=".\CortexM3\ARM_GCC_484\Release\SD_PULLUP.o" />\r
+<dep name=".\CortexM3\ARM_GCC_484\Release\USB_Bootloader.a" />\r
+<dep name="${CyRoot}\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\CortexM3\ARM_GCC_484\Release\CyComponentLibrary.a" />\r
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</CyGuid_1173175f-1b9b-4ad4-a065-754a48a27021>\r
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<v>Cypress Component Catalog\Digital\Registers</v>\r
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-<last_generation v="0" />\r
+<last_generation v="1" />\r
</CyGuid_925cc1e1-309e-4e08-b0a1-09a83c35b157>\r
</dataGuid>\r
<dataGuid v="769d31ea-68b1-4f0c-b90a-7c10a43ee563">\r
<CyGuid_769d31ea-68b1-4f0c-b90a-7c10a43ee563 type_name="CyDesigner.Common.ProjMgmt.Model.CyLinkCustomData" version="1">\r
-<deps_time v="130621704041554601" />\r
+<deps_time v="130664016042069689" />\r
</CyGuid_769d31ea-68b1-4f0c-b90a-7c10a43ee563>\r
</dataGuid>\r
<dataGuid v="bf610382-39c6-441f-80b8-b04622ea7845">\r
<peripheral>\r
<name>USBFS</name>\r
<description>USBFS</description>\r
- <baseAddress>0x40004394</baseAddress>\r
+ <baseAddress>0x0</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
- <size>0x1D0A</size>\r
+ <size>0x0</size>\r
<usage>registers</usage>\r
</addressBlock>\r
<registers>\r
<register>\r
<name>USBFS_PM_USB_CR0</name>\r
<description>USB Power Mode Control Register 0</description>\r
- <addressOffset>0x0</addressOffset>\r
+ <addressOffset>0x40004394</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_PM_ACT_CFG</name>\r
<description>Active Power Mode Configuration Register</description>\r
- <addressOffset>0x11</addressOffset>\r
+ <addressOffset>0x400043A5</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_PM_STBY_CFG</name>\r
<description>Standby Power Mode Configuration Register</description>\r
- <addressOffset>0x21</addressOffset>\r
+ <addressOffset>0x400043B5</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_PRT_PS</name>\r
<description>Port Pin State Register</description>\r
- <addressOffset>0xE5D</addressOffset>\r
+ <addressOffset>0x400051F1</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_PRT_DM0</name>\r
<description>Port Drive Mode Register</description>\r
- <addressOffset>0xE5E</addressOffset>\r
+ <addressOffset>0x400051F2</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_PRT_DM1</name>\r
<description>Port Drive Mode Register</description>\r
- <addressOffset>0xE5F</addressOffset>\r
+ <addressOffset>0x400051F3</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_PRT_INP_DIS</name>\r
<description>Input buffer disable override</description>\r
- <addressOffset>0xE64</addressOffset>\r
+ <addressOffset>0x400051F8</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP0_DR0</name>\r
<description>bmRequestType</description>\r
- <addressOffset>0x1C6C</addressOffset>\r
+ <addressOffset>0x40006000</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP0_DR1</name>\r
<description>bRequest</description>\r
- <addressOffset>0x1C6D</addressOffset>\r
+ <addressOffset>0x40006001</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP0_DR2</name>\r
<description>wValueLo</description>\r
- <addressOffset>0x1C6E</addressOffset>\r
+ <addressOffset>0x40006002</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP0_DR3</name>\r
<description>wValueHi</description>\r
- <addressOffset>0x1C6F</addressOffset>\r
+ <addressOffset>0x40006003</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP0_DR4</name>\r
<description>wIndexLo</description>\r
- <addressOffset>0x1C70</addressOffset>\r
+ <addressOffset>0x40006004</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP0_DR5</name>\r
<description>wIndexHi</description>\r
- <addressOffset>0x1C71</addressOffset>\r
+ <addressOffset>0x40006005</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP0_DR6</name>\r
<description>lengthLo</description>\r
- <addressOffset>0x1C72</addressOffset>\r
+ <addressOffset>0x40006006</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP0_DR7</name>\r
<description>lengthHi</description>\r
- <addressOffset>0x1C73</addressOffset>\r
+ <addressOffset>0x40006007</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_CR0</name>\r
<description>USB Control Register 0</description>\r
- <addressOffset>0x1C74</addressOffset>\r
+ <addressOffset>0x40006008</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<field>\r
<name>device_address</name>\r
<description>No description available</description>\r
- <lsb>6</lsb>\r
- <msb>0</msb>\r
+ <lsb>0</lsb>\r
+ <msb>6</msb>\r
<access>read-only</access>\r
</field>\r
<field>\r
<register>\r
<name>USBFS_CR1</name>\r
<description>USB Control Register 1</description>\r
- <addressOffset>0x1C75</addressOffset>\r
+ <addressOffset>0x40006009</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_SIE_EP1_CR0</name>\r
<description>The Endpoint1 Control Register</description>\r
- <addressOffset>0x1C7A</addressOffset>\r
+ <addressOffset>0x4000600E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_USBIO_CR0</name>\r
<description>USBIO Control Register 0</description>\r
- <addressOffset>0x1C7C</addressOffset>\r
+ <addressOffset>0x40006010</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_USBIO_CR1</name>\r
<description>USBIO Control Register 1</description>\r
- <addressOffset>0x1C7E</addressOffset>\r
+ <addressOffset>0x40006012</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_SIE_EP2_CR0</name>\r
<description>The Endpoint2 Control Register</description>\r
- <addressOffset>0x1C8A</addressOffset>\r
+ <addressOffset>0x4000601E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_SIE_EP3_CR0</name>\r
<description>The Endpoint3 Control Register</description>\r
- <addressOffset>0x1C9A</addressOffset>\r
+ <addressOffset>0x4000602E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_SIE_EP4_CR0</name>\r
<description>The Endpoint4 Control Register</description>\r
- <addressOffset>0x1CAA</addressOffset>\r
+ <addressOffset>0x4000603E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_SIE_EP5_CR0</name>\r
<description>The Endpoint5 Control Register</description>\r
- <addressOffset>0x1CBA</addressOffset>\r
+ <addressOffset>0x4000604E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_SIE_EP6_CR0</name>\r
<description>The Endpoint6 Control Register</description>\r
- <addressOffset>0x1CCA</addressOffset>\r
+ <addressOffset>0x4000605E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_SIE_EP7_CR0</name>\r
<description>The Endpoint7 Control Register</description>\r
- <addressOffset>0x1CDA</addressOffset>\r
+ <addressOffset>0x4000606E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_SIE_EP8_CR0</name>\r
<description>The Endpoint8 Control Register</description>\r
- <addressOffset>0x1CEA</addressOffset>\r
+ <addressOffset>0x4000607E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_BUF_SIZE</name>\r
<description>Dedicated Endpoint Buffer Size Register</description>\r
- <addressOffset>0x1CF8</addressOffset>\r
+ <addressOffset>0x4000608C</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP_ACTIVE</name>\r
<description>Endpoint Active Indication Register</description>\r
- <addressOffset>0x1CFA</addressOffset>\r
+ <addressOffset>0x4000608E</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_EP_TYPE</name>\r
<description>Endpoint Type (IN/OUT) Indication</description>\r
- <addressOffset>0x1CFB</addressOffset>\r
+ <addressOffset>0x4000608F</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
<register>\r
<name>USBFS_USB_CLK_EN</name>\r
<description>USB Block Clock Enable Register</description>\r
- <addressOffset>0x1D09</addressOffset>\r
+ <addressOffset>0x4000609D</addressOffset>\r
<size>8</size>\r
<access>read-write</access>\r
<resetValue>0</resetValue>\r
/*******************************************************************************
* File Name: Bootloadable_1.c
-* Version 1.20
+* Version 1.30
*
* Description:
* Provides an API for the Bootloadable application. The API includes a
-* single function for starting bootloader.
+* single function for starting the bootloader.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Function Name: Bootloadable_1_Load
********************************************************************************
* Summary:
-* Begins the bootloading algorithm, downloading a new ACD image from the host.
+* Begins the bootloading algorithm downloading a new ACD image from the host.
*
* Parameters:
* None
/*******************************************************************************
-* Function Name: Bootloadable_1_SetFlashByte
-********************************************************************************
-* Summary:
-* Sets byte at specified address in Flash.
-*
-* Parameters:
-* None
-*
-* Returns:
-* None
-*
+* The following code is OBSOLETE and must not be used.
*******************************************************************************/
void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType)
{
uint32 flsAddr = address - CYDEV_FLASH_BASE;
- uint8 rowData[CYDEV_FLS_ROW_SIZE];
+ uint8 rowData[CYDEV_FLS_ROW_SIZE];
#if !(CY_PSOC4)
- uint8 arrayId = (uint8)(flsAddr / CYDEV_FLS_SECTOR_SIZE);
+ uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE);
#endif /* !(CY_PSOC4) */
- uint16 rowNum = (uint16)((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);
+ #if (CY_PSOC4)
+ uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE);
+ #else
+ uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);
+ #endif /* (CY_PSOC4) */
+
uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE);
uint16 idx;
}
rowData[address % CYDEV_FLS_ROW_SIZE] = runType;
-
#if(CY_PSOC4)
- (void) CySysFlashWriteRow((uint32)rowNum, rowData);
+ (void) CySysFlashWriteRow((uint32) rowNum, rowData);
#else
(void) CyWriteRowData(arrayId, rowNum, rowData);
#endif /* (CY_PSOC4) */
+
+ #if(CY_PSOC5)
+ /***************************************************************************
+ * When writing Flash, data in the instruction cache can become stale.
+ * Therefore, the cache data does not correlate to the data just written to
+ * Flash. A call to CyFlushCache() is required to invalidate the data in the
+ * cache and force fresh information to be loaded from Flash.
+ ***************************************************************************/
+ CyFlushCache();
+ #endif /* (CY_PSOC5) */
}
/*******************************************************************************
* File Name: Bootloadable_1.h
-* Version 1.20
+* Version 1.30
*
* Description:
* Provides an API for the Bootloadable application. The API includes a
* single function for starting bootloader.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
- #error Component Bootloadable_v1_20 requires cy_boot v3.0 or later
+ #error Component Bootloadable_v1_30 requires cy_boot v3.0 or later
#endif /* !defined (CY_PSOC5LP) */
/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from version 1.10
+* The following code is OBSOLETE and must not be used starting from version 1.10
*******************************************************************************/
#define CYBTDLR_SET_RUN_TYPE(x) Bootloadable_1_SET_RUN_TYPE(x)
/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from version 1.20
+* The following code is OBSOLETE and must not be used starting from version 1.20
*******************************************************************************/
#define Bootloadable_1_START_APP (0x80u)
#define Bootloadable_1_START_BTLDR (0x40u)
#define Bootloadable_1_SetFlashRunType(runType) \
Bootloadable_1_SetFlashByte(Bootloadable_1_MD_APP_RUN_ADDR(0), (runType))
-void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) ;
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+* #ifdef <OBSOLETED_DEFINE>
+* #undef <OBSOLETED_DEFINE>
+* #define <OBSOLETED_DEFINE> (<New Value>)
+* #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+* used in the application and their modification might lead to unexpected
+* consequences.
+*******************************************************************************/
+void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) ;
#if(CY_PSOC4)
- #define Bootloadable_1_SOFTWARE_RESET CY_SET_REG32(CYREG_CM0_AIRCR, 0x05FA0004u)
+ #define Bootloadable_1_SOFTWARE_RESET CySoftwareReset()
#else
- #define Bootloadable_1_SOFTWARE_RESET CY_SET_REG8(CYREG_RESET_CR2, 0x01u)
+ #define Bootloadable_1_SOFTWARE_RESET CySoftwareReset()
#endif /* (CY_PSOC4) */
#if(CY_PSOC4)
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (32768 / 2);
define symbol __ICFEDIT_region_RAM_end__ = 0x20000000 + (32768 / 2) - 1;
/*-Sizes-*/
-define symbol __ICFEDIT_size_cstack__ = 0x4000;
-define symbol __ICFEDIT_size_heap__ = 0x1000;
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_heap__ = 0x0400;
/**** End of ICF editor section. ###ICF###*/
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, last block CSTACK};
+if (CY_APPL_LOADABLE)
+{
define block LOADER { readonly section .cybootloader };
+}
define block APPL with fixed order {readonly section .romvectors, readonly};
/* The address of Flash row next after Bootloader image */
do not initialize { readwrite section .ramvectors };
/******** Placements *********/
+if (CY_APPL_LOADABLE)
+{
".cybootloader" : place at start of ROM_region {block LOADER};
+}
+
"APPL" : place at start of APPL_region {block APPL};
"RAMVEC" : place at start of RAM_region { readwrite section .ramvectors };
section .cymeta };
".cyloadermeta" : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };
+if (CY_APPL_LOADABLE)
+{
".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };
+}
".cyconfigecc" : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc };
".cycustnvl" : place at address mem : 0x90000000 { readonly section .cycustnvl };
".cywolatch" : place at address mem : 0x90100000 { readonly section .cywolatch };
;********************************************************************************
;* File Name: Cm3RealView.scat
-;* Version 4.0
+;* Version 4.20
;*
;* Description:
;* This Linker Descriptor file describes the memory layout of the PSoC5
;*
;* Note:
;*
-;* romvectors: Cypress default Interrupt sevice routine vector table.
+;* romvectors: Cypress default Interrupt service routine vector table.
;*
;* This is the ISR vector table at bootup. Used only for the reset vector.
;*
;*
;*
;********************************************************************************
-;* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+;* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
;* You may use this file only in accordance with the license, terms, conditions,
;* disclaimers, and limitations in the end user license agreement accompanying
;* the software package with which this file was provided.
.ANY (+RW, +ZI)
}
- ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x1000 - 0x4000) EMPTY 0x1000
+ ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0400 - 0x1000) EMPTY 0x0400
{
}
- ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x4000
+ ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x1000
{
}
}
/*******************************************************************************
* File Name: Cm3Start.c
-* Version 4.0
+* Version 4.20
*
* Description:
* Startup code for the ARM CM3.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
extern void __iar_data_init3 (void);
#endif /* (__ARMCC_VERSION) */
+#if defined(__GNUC__)
+ #include <errno.h>
+ extern int errno;
+ extern int end;
+#endif /* defined(__GNUC__) */
+
/* Global variables */
#if !defined (__ICCARM__)
CY_NOINIT static uint32 cySysNoInitDataValid;
********************************************************************************
*
* Summary:
-* This function is called for all interrupts, other than reset, that get
+* This function is called for all interrupts, other than a reset that gets
* called before the system is setup.
*
* Parameters:
while(1)
{
/***********************************************************************
- * We should never get here. If we do, a serious problem occured, so go
+ * We must not get here. If we do, a serious problem occurs, so go
* into an infinite loop.
***********************************************************************/
}
#if defined(__ARMCC_VERSION)
-/* Local function for the device reset. */
+/* Local function for device reset. */
extern void Reset(void);
/* Application entry point. */
********************************************************************************
*
* Summary:
-* This function is called imediatly before the users main
+* This function is called immediately before the users main
*
* Parameters:
* None
while (1)
{
- /* If main returns it is undefined what we should do. */
+ /* If main returns, it is undefined what we should do. */
}
}
/* Application entry point. */
extern int main(void);
-/* The static objects constructors initializer */
+/* Static objects constructors initializer */
extern void __libc_init_array(void);
typedef unsigned char __cy_byte_align8 __attribute ((aligned (8)));
#define __cy_region_num ((size_t)&__cy_region_num)
+/*******************************************************************************
+* System Calls of the Red Hat newlib C Library
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: _exit
+********************************************************************************
+*
+* Summary:
+* Exit a program without cleaning up files. If your system doesn't provide
+* this, it is best to avoid linking with subroutines that require it (exit,
+* system).
+*
+* Parameters:
+* status: Status caused program exit.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+__attribute__((weak))
+void _exit(int status)
+{
+ /* Cause divide by 0 exception */
+ int x = status / (int) INT_MAX;
+ x = 4 / x;
+
+ while(1)
+ {
+
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: _sbrk
+********************************************************************************
+*
+* Summary:
+* Increase program data space. As malloc and related functions depend on this,
+* it is useful to have a working implementation. The following suffices for a
+* standalone system; it exploits the symbol end automatically defined by the
+* GNU linker.
+*
+* Parameters:
+* nbytes: The number of bytes requested (if the parameter value is positive)
+* from the heap or returned back to the heap (if the parameter value is
+* negative).
+*
+* Return:
+* None
+*
+*******************************************************************************/
+__attribute__((weak))
+void * _sbrk (int nbytes)
+{
+ extern int end; /* Symbol defined by linker map. Start of free memory (as symbol). */
+ void * returnValue;
+
+ /* The statically held previous end of the heap, with its initialization. */
+ static void *heapPointer = (void *) &end; /* Previous end */
+
+ if (((heapPointer + nbytes) - (void *) &end) <= CYDEV_HEAP_SIZE)
+ {
+ returnValue = heapPointer;
+ heapPointer += nbytes;
+ }
+ else
+ {
+ errno = ENOMEM;
+ returnValue = (void *) -1;
+ }
+
+ return (returnValue);
+}
+
+
/*******************************************************************************
* Function Name: Reset
********************************************************************************
Start_c();
}
-__attribute__((weak))
-void _exit(int status)
-{
- /* Cause a divide by 0 exception */
- int x = status / INT_MAX;
- x = 4 / x;
-
- while(1)
- {
- }
-}
/*******************************************************************************
* Function Name: Start_c
*
* Summary:
* This function handles initializing the .data and .bss sections in
-* preperation for running standard C code. Once initialization is complete
+* preparation for running the standard C code. Once initialization is complete
* it will call main(). This function will never return.
*
* Parameters:
const struct __cy_region *rptr = __cy_regions;
/* Initialize memory */
- for (regions = __cy_region_num, rptr = __cy_regions; regions--; rptr++)
+ for (regions = __cy_region_num; regions != 0u; regions--)
{
uint32 *src = (uint32 *)rptr->init;
uint32 *dst = (uint32 *)rptr->data;
for (count = 0u; count != limit; count += sizeof (uint32))
{
- *dst++ = *src++;
+ *dst = *src;
+ dst++;
+ src++;
}
limit = rptr->zero_size;
for (count = 0u; count != limit; count += sizeof (uint32))
{
- *dst++ = 0u;
+ *dst = 0u;
+ dst++;
}
+
+ rptr++;
}
/* Invoke static objects constructors */
********************************************************************************
*
* Summary:
-* This function perform early initializations for the IAR Embedded
-* Workbench IDE. It is executed in the context of reset interrupt handler
+* This function performs early initializations for the IAR Embedded
+* Workbench IDE. It is executed in the context of a reset interrupt handler
* before the data sections are initialized.
*
* Parameters:
const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] =
#endif /* defined (__ICCARM__) */
{
- INITIAL_STACK_POINTER, /* The initial stack pointer 0 */
- #if defined (__ICCARM__) /* The reset handler 1 */
+ INITIAL_STACK_POINTER, /* Initial stack pointer 0 */
+ #if defined (__ICCARM__) /* Reset handler 1 */
__iar_program_start,
#else
(cyisraddress)&Reset,
#endif /* defined (__ICCARM__) */
- &IntDefaultHandler, /* The NMI handler 2 */
- &IntDefaultHandler, /* The hard fault handler 3 */
+ &IntDefaultHandler, /* NMI handler 2 */
+ &IntDefaultHandler, /* Hard fault handler 3 */
};
#if defined(__ARMCC_VERSION)
/* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */
CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1);
- /* Point NVIC at the RAM vector table. */
+ /* Point NVIC at RAM vector table. */
*CYINT_VECT_TABLE = CyRamVectors;
/* Initialize the configuration registers. */
#if(0u != DMA_CHANNELS_USED__MASK0)
- /* Setup DMA - only necessary if the design contains a DMA component. */
+ /* Setup DMA - only necessary if design contains DMA component. */
CyDmacConfigure();
#endif /* (0u != DMA_CHANNELS_USED__MASK0) */
/*******************************************************************************
* File Name: CyBootAsmGnu.s
-* Version 4.0
+* Version 4.20
*
* Description:
* Assembly routines for GNU as.
*
********************************************************************************
-* Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2010-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
;-------------------------------------------------------------------------------
; FILENAME: CyBootAsmIar.s
-; Version 4.0
+; Version 4.20
;
; DESCRIPTION:
; Assembly routines for IAR Embedded Workbench IDE.
;
;-------------------------------------------------------------------------------
-; Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.
+; Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
;
; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
; with interrupts still enabled. The test and set of the interrupt bits is not
-; atomic. Therefore, to avoid corrupting processor state, it must be the policy
+; atomic. Therefore, to avoid a corrupting processor state, it must be the policy
; that all interrupt routines restore the interrupt enable bits as they were
; found on entry.
;
;-------------------------------------------------------------------------------
; FILENAME: CyBootAsmRv.s
-; Version 4.0
+; Version 4.20
;
; DESCRIPTION:
; Assembly routines for RealView.
;
;-------------------------------------------------------------------------------
-; Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved.
+; Copyright 2010-2014, Cypress Semiconductor Corporation. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
;
; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
; with interrupts still enabled. The test and set of the interrupt bits is not
-; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid
+; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a
; corrupting processor state, it must be the policy that all interrupt routines
; restore the interrupt enable bits as they were found on entry.
;
/*******************************************************************************
* File Name: CyDmac.c
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides an API for the DMAC component. The API includes functions for the
* not being used.
*
* This code uses the first byte of each TD to manage the free list of TD's.
-* The user can over write this once the TD is allocated.
+* The user can overwrite this once the TD is allocated.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* are initialized. To avoid zeroing, these variables should be initialized
* properly during segments initialization as well.
*******************************************************************************/
-static uint8 CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; /* Current Number of free elements in the list */
-static uint8 CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of the first available TD */
+static uint8 CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; /* Current Number of free elements on list */
+static uint8 CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of first available TD */
static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0; /* Bit map of DMA channel ownership */
*
* Summary:
* Creates a linked list of all the TDs to be allocated. This function is called
-* by the startup code; you do not normally need to call it. You could call this
+* by the startup code; you do not normally need to call it. You can call this
* function if all of the DMA channels are inactive.
*
* Parameters:
CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u);
}
- /* Make the last one point to zero. */
+ /* Make last one point to zero. */
CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = 0u;
}
* are determined by the BUS_TIMEOUT field in the PHUBCFG register.
*
* Theory:
-* Once an error occurs the error bits are sticky and are only cleared by a
-* write 1 to the error register.
+* Once an error occurs the error bits are sticky and are only cleared by
+* writing 1 to the error register.
*
*******************************************************************************/
uint8 CyDmacError(void)
* Set to 1 when an access is attempted to an invalid address.
*
* DMAC_BUS_TIMEOUT:
-* Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values
+* Set to 1 when a bus timeout occurs. Cleared by writing 1. Timeout values
* are determined by the BUS_TIMEOUT field in the PHUBCFG register.
*
* Return:
* None
*
* Theory:
-* Once an error occurs the error bits are sticky and are only cleared by a
-* write 1 to the error register.
+* Once an error occurs the error bits are sticky and are only cleared by
+* writing 1 to the error register.
*
*******************************************************************************/
void CyDmacClearError(uint8 error)
********************************************************************************
*
* Summary:
-* When an DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC and DMAC_PERIPH_ERR occurs the
+* When DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC, and DMAC_PERIPH_ERR occur the
* address of the error is written to the error address register and can be read
* with this function.
*
/* Enter critical section! */
interruptState = CyEnterCriticalSection();
- /* Look for a free channel. */
+ /* Look for free channel. */
for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++)
{
if(0uL == (CyDmaChannels & channel))
{
- /* Mark the channel as used. */
+ /* Mark channel as used. */
CyDmaChannels |= channel;
break;
}
/* Enter critical section */
interruptState = CyEnterCriticalSection();
- /* Clear the bit mask that keeps track of ownership. */
+ /* Clear bit mask that keeps track of ownership. */
CyDmaChannels &= ~(((uint32) 1u) << chHandle);
/* Exit critical section */
* Preserves the original TD state when the TD has completed. This parameter
* applies to all TDs in the channel.
*
-* 0 - When a TD is completed, the DMAC leaves the TD configuration values in
+* 0 - When TD is completed, the DMAC leaves the TD configuration values in
* their current state, and does not restore them to their original state.
*
-* 1 - When a TD is completed, the DMAC restores the original configuration
+* 1 - When TD is completed, the DMAC restores the original configuration
* values of the TD.
*
* When preserveTds is set, the TD slot that equals the channel number becomes
{
if (0u != preserveTds)
{
- /* Store the intermediate TD states separately in CHn_SEP_TD0/1 to
- * preserve the original TD chain
+ /* Store intermediate TD states separately in CHn_SEP_TD0/1 to
+ * preserve original TD chain
*/
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP;
}
else
{
- /* Store the intermediate and final TD states on top of the original TD chain */
+ /* Store intermediate and final TD states on top of original TD chain */
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP);
}
/* Disable channel */
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN));
- /* Store the intermediate and final TD states on top of the original TD chain */
+ /* Store intermediate and final TD states on top of original TD chain */
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP));
status = CYRET_SUCCESS;
}
********************************************************************************
*
* Summary:
-* Clears pending DMA data request.
+* Clears pending the DMA data request.
*
* Parameters:
* uint8 chHandle:
* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().
*
* uint8 startTd:
-* The index of TD to set as the first TD associated with the channel. Zero is
+* Set the TD index as the first TD associated with the channel. Zero is
* a valid TD index.
*
* Return:
if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS)
{
- /* Get pointer to the Next available. */
+ /* Get pointer to Next available. */
element = CyDmaTdFreeIndex;
/* Decrement the count. */
CyDmaTdCurrentNumber--;
- /* Update the next available pointer. */
+ /* Update next available pointer. */
CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0];
}
/* Enter critical section! */
uint8 interruptState = CyEnterCriticalSection();
- /* Get pointer to the Next available. */
+ /* Get pointer to Next available. */
CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex;
/* Set new Next Available. */
* CYRET_BAD_PARAM if tdHandle is invalid.
*
* Side Effects:
-* If a TD has a transfer count of N and is executed, the transfer count becomes
+* If TD has a transfer count of N and is executed, the transfer count becomes
* 0. If it is reexecuted, the Transfer count of zero will be interpreted as a
-* request for indefinite transfer. Be careful when requesting a TD with a
+* request for indefinite transfer. Be careful when requesting TD with a
* transfer count of zero.
*
*******************************************************************************/
if(tdHandle < CY_DMA_NUMBEROF_TDS)
{
- /* If we have a pointer */
+ /* If we have pointer */
if(NULL != transferCount)
{
- /* Get the 12 bits of the transfer count */
+ /* Get 12 bits of transfer count */
reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0];
*transferCount = 0x0FFFu & CY_GET_REG16(convert);
}
- /* If we have a pointer */
+ /* If we have pointer */
if(NULL != nextTd)
{
- /* Get the Next TD pointer */
+ /* Get Next TD pointer */
*nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u];
}
- /* If we have a pointer */
+ /* If we have pointer */
if(NULL != configuration)
{
- /* Get the configuration the TD */
+ /* Get configuration TD */
*configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u];
}
/*******************************************************************************
* File Name: CyDmac.h
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides the function definitions for the DMA Controller.
* System Reference Guide provided with PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#define CY_DMA_TD_SIZE 0x08u
-/* The "u" was removed as workaround for Keil compiler bug */
+/* "u" was removed as workaround for Keil compiler bug */
#define CY_DMA_TD_SWAP_EN 0x80
#define CY_DMA_TD_SWAP_SIZE4 0x40
#define CY_DMA_TD_AUTO_EXEC_NEXT 0x20
/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+* #ifdef <OBSOLETED_DEFINE>
+* #undef <OBSOLETED_DEFINE>
+* #define <OBSOLETED_DEFINE> (<New Value>)
+* #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+* used in the application and their modification might lead to unexpected
+* consequences.
*******************************************************************************/
#define DMA_INVALID_CHANNEL (CY_DMA_INVALID_CHANNEL)
#define DMA_INVALID_TD (CY_DMA_INVALID_TD)
/*******************************************************************************
* File Name: CyFlash.c
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides an API for the FLASH/EEPROM.
* System Reference Guide provided with PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "CyFlash.h"
+/* The number of EEPROM arrays */
+#define CY_FLASH_EEPROM_NUMBER_ARRAYS (1u)
+
/*******************************************************************************
-* Holds die temperature, updated by CySetTemp(). Used for flash writting.
+* Holds the die temperature, updated by CySetTemp(). Used for flash writing.
* The first byte is the sign of the temperature (0 = negative, 1 = positive).
* The second byte is the magnitude.
*******************************************************************************/
static cystatus CySetTempInt(void);
+static cystatus CyFlashGetSpcAlgorithm(void);
/*******************************************************************************
*******************************************************************************/
void CyFlash_Start(void)
{
- /* Active Power Mode */
- *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
+ uint8 interruptState;
+
+ interruptState = CyEnterCriticalSection();
+
+
+ /***************************************************************************
+ * Enable SPC clock. This also internally enables the 36MHz IMO, since this
+ * is required for the SPC to function.
+ ***************************************************************************/
+ CY_FLASH_PM_ACT_CFG0_REG |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
+ CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
+
- /* Standby Power Mode */
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
+ /***************************************************************************
+ * The wake count defines the number of Bus Clock cycles it takes for the
+ * flash or eeprom to wake up from a low power mode independent of the chip
+ * power mode. Wake up time for these blocks is 5 us.
+ * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
+ * (30d) defines the wake up time as 60 cycles of the Bus Clock.
+ * This register needs to be written with a value dependent on the Bus Clock
+ * frequency so that the duration of the cycles is equal to or greater than
+ * the 5 us delay required.
+ ***************************************************************************/
+ CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
+
+
+ /***************************************************************************
+ * Enable flash. Active flash macros consume current, but re-enabling a
+ * disabled flash macro takes 5us. If the CPU attempts to fetch out of the
+ * macro during that time, it will be stalled. This bit allows the flash to
+ * be enabled even if the CPU is disabled, which allows a quicker return to
+ * code execution.
+ ***************************************************************************/
+ CY_FLASH_PM_ACT_CFG12_REG |= CY_FLASH_PM_ACT_CFG12_EN_FM;
+ CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_FM;
+
+ while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
+ {
+ /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
+ }
- CyDelayUs(CY_FLASH_EE_STARTUP_DELAY);
+ CyExitCriticalSection(interruptState);
}
*******************************************************************************/
void CyFlash_Stop(void)
{
- /* Active Power Mode */
- *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
+ uint8 interruptState;
+
+ interruptState = CyEnterCriticalSection();
+
+ CY_FLASH_PM_ACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_FM));
+ CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_FM));
- /* Standby Power Mode */
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
+ CyExitCriticalSection(interruptState);
}
*
* Summary:
* Sends a command to the SPC to read the die temperature. Sets a global value
-* used by the Write functions. This function must be called once before
+* used by the Write function. This function must be called once before
* executing a series of Flash writing functions.
*
* Parameters:
}
+/*******************************************************************************
+* Function Name: CyFlashGetSpcAlgorithm
+********************************************************************************
+*
+* Summary:
+* Sends a command to the SPC to download code into RAM.
+*
+* Parameters:
+* None
+*
+* Return:
+* status:
+* CYRET_SUCCESS - if successful
+* CYRET_LOCKED - if Flash writing already in use
+* CYRET_UNKNOWN - if there was an SPC error
+*
+*******************************************************************************/
+static cystatus CyFlashGetSpcAlgorithm(void)
+{
+ cystatus status;
+
+ /* Make sure SPC is powered */
+ CySpcStart();
+
+ if(CySpcLock() == CYRET_SUCCESS)
+ {
+ status = CySpcGetAlgorithm();
+
+ if(CYRET_STARTED == status)
+ {
+ while(CY_SPC_BUSY)
+ {
+ /* Spin until idle. */
+ CyDelayUs(1u);
+ }
+
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+ {
+ status = CYRET_SUCCESS;
+ }
+ }
+ CySpcUnlock();
+ }
+ else
+ {
+ status = CYRET_LOCKED;
+ }
+
+ return (status);
+}
+
+
/*******************************************************************************
* Function Name: CySetTemp
********************************************************************************
*
* Summary:
-* This is a wraparound for CySetTempInt(). It is used to return second
-* successful read of temperature value.
+* This is a wraparound for CySetTempInt(). It is used to return the second
+* successful read of the temperature value.
*
* Parameters:
* None
* CYRET_UNKNOWN if there was an SPC error.
*
* uint8 dieTemperature[2]:
-* Holds die temperature for the flash writting algorithm. The first byte is
+* Holds the die temperature for the flash writing algorithm. The first byte is
* the sign of the temperature (0 = negative, 1 = positive). The second byte is
* the magnitude.
*
*******************************************************************************/
cystatus CySetTemp(void)
{
- cystatus status = CySetTempInt();
+ cystatus status = CyFlashGetSpcAlgorithm();
if(status == CYRET_SUCCESS)
{
*
* Summary:
* Sets the user supplied temporary buffer to store SPC data while performing
-* flash and EEPROM commands. This buffer is only necessary when Flash ECC is
+* Flash and EEPROM commands. This buffer is only necessary when the Flash ECC is
* disabled.
*
* Parameters:
* buffer:
-* Address of block of memory to store temporary memory. The size of the block
+* The address of a block of memory to store temporary memory. The size of the block
* of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE.
*
* Return:
if(NULL == buffer)
{
+ rowBuffer = rowBuffer;
status = CYRET_BAD_PARAM;
}
else if(CySpcLock() != CYRET_SUCCESS)
{
+ rowBuffer = rowBuffer;
status = CYRET_LOCKED;
}
else
#else
- /* To supress the warning */
+ /* To suppress warning */
buffer = buffer;
#endif /* (CYDEV_ECC_ENABLE == 0u) */
}
-#if(CYDEV_ECC_ENABLE == 1)
-
- /*******************************************************************************
- * Function Name: CyWriteRowData
- ********************************************************************************
- *
- * Summary:
- * Sends a command to the SPC to load and program a row of data in
- * Flash or EEPROM.
- *
- * Parameters:
- * arrayID: ID of the array to write.
- * The type of write, Flash or EEPROM, is determined from the array ID.
- * The arrays in the part are sequential starting at the first ID for the
- * specific memory type. The array ID for the Flash memory lasts from 0x00 to
- * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
- * rowAddress: rowAddress of flash row to program.
- * rowData: Array of bytes to write.
- *
- * Return:
- * status:
- * CYRET_SUCCESS if successful.
- * CYRET_LOCKED if the SPC is already in use.
- * CYRET_CANCELED if command not accepted
- * CYRET_UNKNOWN if there was an SPC error.
- *
- *******************************************************************************/
- cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData)
- {
- uint16 rowSize;
- cystatus status;
-
- rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;
- status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);
-
- return(status);
- }
-
-#else
-
- /*******************************************************************************
- * Function Name: CyWriteRowData
- ********************************************************************************
- *
- * Summary:
- * Sends a command to the SPC to load and program a row of data in
- * Flash or EEPROM.
- *
- * Parameters:
- * arrayID : ID of the array to write.
- * The type of write, Flash or EEPROM, is determined from the array ID.
- * The arrays in the part are sequential starting at the first ID for the
- * specific memory type. The array ID for the Flash memory lasts from 0x00 to
- * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
- * rowAddress : rowAddress of flash row to program.
- * rowData : Array of bytes to write.
- *
- * Return:
- * status:
- * CYRET_SUCCESS if successful.
- * CYRET_LOCKED if the SPC is already in use.
- * CYRET_CANCELED if command not accepted
- * CYRET_UNKNOWN if there was an SPC error.
- *
- *******************************************************************************/
- cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData)
- {
- uint8 i;
- uint32 offset;
- uint16 rowSize;
- cystatus status;
-
- /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */
- if(NULL != rowBuffer)
- {
- if(arrayId > CY_SPC_LAST_FLASH_ARRAYID)
- {
- rowSize = CYDEV_EEPROM_ROW_SIZE;
- }
- else
- {
- rowSize = CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE;
-
- /* Save the ECC area. */
- offset = CYDEV_ECC_BASE +
- ((uint32)arrayId * CYDEV_ECC_SECTOR_SIZE) +
- ((uint32)rowAddress * CYDEV_ECC_ROW_SIZE);
-
- for(i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
- {
- *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
- }
- }
-
- /* Copy the rowdata to the temporary buffer. */
- #if(CY_PSOC3)
- (void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE);
- #else
- (void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE);
- #endif /* (CY_PSOC3) */
-
- status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize);
- }
- else
- {
- status = CYRET_UNKNOWN;
- }
+/*******************************************************************************
+* Function Name: CyWriteRowData
+********************************************************************************
+*
+* Summary:
+* Sends a command to the SPC to load and program a row of data in
+* Flash or EEPROM.
+*
+* Parameters:
+* arrayID: ID of the array to write.
+* The type of write, Flash or EEPROM, is determined from the array ID.
+* The arrays in the part are sequential starting at the first ID for the
+* specific memory type. The array ID for the Flash memory lasts from 0x00 to
+* 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
+* rowAddress: rowAddress of flash row to program.
+* rowData: Array of bytes to write.
+*
+* Return:
+* status:
+* CYRET_SUCCESS if successful.
+* CYRET_LOCKED if the SPC is already in use.
+* CYRET_CANCELED if command not accepted
+* CYRET_UNKNOWN if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData)
+{
+ uint16 rowSize;
+ cystatus status;
- return(status);
- }
+ rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;
+ status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);
-#endif /* (CYDEV_ECC_ENABLE == 0u) */
+ return(status);
+}
+/*******************************************************************
+* If "Enable Error Correcting Code (ECC)" and "Store Configuration
+* Data in ECC" DWR options are disabled, ECC section is available
+* for user data.
+*******************************************************************/
#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
/*******************************************************************************
********************************************************************************
*
* Summary:
- * Sends a command to the SPC to load and program a row of config data in flash.
+ * Sends a command to the SPC to load and program a row of config data in the Flash.
* This function is only valid for Flash array IDs (not for EEPROM).
*
* Parameters:
* The arrays in the part are sequential starting at the first ID for the
* specific memory type. The array ID for the Flash memory lasts
* from 0x00 to 0x3F.
- * rowAddress: Address of the sector to erase.
- * rowECC: Array of bytes to write.
+ * rowAddress: The address of the sector to erase.
+ * rowECC: The array of bytes to write.
*
* Return:
* status:
cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\
{
- uint32 offset;
- uint16 i;
cystatus status;
- /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */
- if(NULL != rowBuffer)
- {
- /* Read the existing flash data. */
- offset = ((uint32)arrayId * CYDEV_FLS_SECTOR_SIZE) +
- ((uint32)rowAddress * CYDEV_FLS_ROW_SIZE);
-
- #if (CYDEV_FLS_BASE != 0u)
- offset += CYDEV_FLS_BASE;
- #endif /* (CYDEV_FLS_BASE != 0u) */
-
- for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
- {
- rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
- }
-
- #if(CY_PSOC3)
- (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],
- (void *)(uint32)rowECC,
- (int16)CYDEV_ECC_ROW_SIZE);
- #else
- (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],
- (const void *)rowECC,
- CYDEV_ECC_ROW_SIZE);
- #endif /* (CY_PSOC3) */
-
- status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);
- }
- else
- {
- status = CYRET_UNKNOWN;
- }
+ status = CyWriteRowFull(arrayId, rowAddress, rowECC, CYDEV_ECC_ROW_SIZE);
return (status);
}
* Function Name: CyWriteRowFull
********************************************************************************
* Summary:
-* Sends a command to the SPC to load and program a row of data in flash.
+* Sends a command to the SPC to load and program a row of data in the Flash.
* rowData array is expected to contain Flash and ECC data if needed.
*
* Parameters:
cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \
{
- cystatus status;
+ cystatus status = CYRET_SUCCESS;
- if(CySpcLock() == CYRET_SUCCESS)
+ if((arrayId <= CY_SPC_LAST_FLASH_ARRAYID) && (arrayId > (CY_FLASH_NUMBER_ARRAYS + CY_SPC_FIRST_FLASH_ARRAYID)))
{
- /* Load row data into SPC internal latch */
- status = CySpcLoadRow(arrayId, rowData, rowSize);
+ status = CYRET_BAD_PARAM;
+ }
- if(CYRET_STARTED == status)
+ if(arrayId > CY_SPC_LAST_EE_ARRAYID)
+ {
+ status = CYRET_BAD_PARAM;
+ }
+
+ if((arrayId >= CY_SPC_FIRST_EE_ARRAYID) && (arrayId > (CY_FLASH_EEPROM_NUMBER_ARRAYS + CY_SPC_FIRST_EE_ARRAYID)))
+ {
+ status = CYRET_BAD_PARAM;
+ }
+
+ if(arrayId <= CY_SPC_LAST_FLASH_ARRAYID)
+ {
+ /* Flash */
+ if(rowNumber > (CY_FLASH_NUMBER_ROWS/CY_FLASH_NUMBER_ARRAYS))
{
- while(CY_SPC_BUSY)
- {
- /* Wait for SPC to finish and get SPC status */
- CyDelayUs(1u);
- }
+ status = CYRET_BAD_PARAM;
+ }
+ }
+ else
+ {
+ /* EEPROM */
+ if(rowNumber > (CY_EEPROM_NUMBER_ROWS/CY_FLASH_EEPROM_NUMBER_ARRAYS))
+ {
+ status = CYRET_BAD_PARAM;
+ }
- /* Hide SPC status */
- if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
- {
- status = CYRET_SUCCESS;
- }
- else
- {
- status = CYRET_UNKNOWN;
- }
+ if(CY_EEPROM_SIZEOF_ROW != rowSize)
+ {
+ status = CYRET_BAD_PARAM;
+ }
+ }
- if(CYRET_SUCCESS == status)
+ if(rowData == NULL)
+ {
+ status = CYRET_BAD_PARAM;
+ }
+
+
+ if(status == CYRET_SUCCESS)
+ {
+ if(CySpcLock() == CYRET_SUCCESS)
+ {
+ /* Load row data into SPC internal latch */
+ status = CySpcLoadRowFull(arrayId, rowNumber, rowData, rowSize);
+
+ if(CYRET_STARTED == status)
{
- /* Erase and program flash with the data from SPC interval latch */
- status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);
+ while(CY_SPC_BUSY)
+ {
+ /* Wait for SPC to finish and get SPC status */
+ CyDelayUs(1u);
+ }
- if(CYRET_STARTED == status)
+ /* Hide SPC status */
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
{
- while(CY_SPC_BUSY)
- {
- /* Wait for SPC to finish and get SPC status */
- CyDelayUs(1u);
- }
+ status = CYRET_SUCCESS;
+ }
+ else
+ {
+ status = CYRET_UNKNOWN;
+ }
- /* Hide SPC status */
- if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
- {
- status = CYRET_SUCCESS;
- }
- else
+ if(CYRET_SUCCESS == status)
+ {
+ /* Erase and program flash with data from SPC interval latch */
+ status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);
+
+ if(CYRET_STARTED == status)
{
- status = CYRET_UNKNOWN;
+ while(CY_SPC_BUSY)
+ {
+ /* Wait for SPC to finish and get SPC status */
+ CyDelayUs(1u);
+ }
+
+ /* Hide SPC status */
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+ {
+ status = CYRET_SUCCESS;
+ }
+ else
+ {
+ status = CYRET_UNKNOWN;
+ }
}
}
}
-
+ CySpcUnlock();
+ } /* if(CySpcLock() == CYRET_SUCCESS) */
+ else
+ {
+ status = CYRET_LOCKED;
}
-
- CySpcUnlock();
- }
- else
- {
- status = CYRET_LOCKED;
}
return(status);
*
* Summary:
* Sets the number of clock cycles the cache will wait before it samples data
-* coming back from Flash. This function must be called before increasing CPU
-* clock frequency. It can optionally be called after lowering CPU clock
-* frequency in order to improve CPU performance.
+* coming back from the Flash. This function must be called before increasing the CPU
+* clock frequency. It can optionally be called after lowering the CPU clock
+* frequency in order to improve the CPU performance.
*
* Parameters:
* uint8 freq:
/***************************************************************************
* The number of clock cycles the cache will wait before it samples data
- * coming back from Flash must be equal or greater to to the CPU frequency
+ * coming back from the Flash must be equal or greater to to the CPU frequency
* outlined in clock cycles.
***************************************************************************/
- #if (CY_PSOC3)
-
- if (freq <= 22u)
- {
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_22MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
- }
- else if (freq <= 44u)
- {
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
- }
- else
- {
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
- ((uint8)(CY_FLASH_GREATER_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
- }
-
- #endif /* (CY_PSOC3) */
-
-
- #if (CY_PSOC5)
-
- if (freq <= 16u)
- {
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
- }
- else if (freq <= 33u)
- {
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
- }
- else if (freq <= 50u)
- {
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
- }
- else
- {
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
- ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
- }
-
- #endif /* (CY_PSOC5) */
+ if (freq < CY_FLASH_CACHE_WS_1_FREQ_MAX)
+ {
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+ CY_FLASH_CACHE_WS_1_VALUE_MASK;
+ }
+ else if (freq < CY_FLASH_CACHE_WS_2_FREQ_MAX)
+ {
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+ CY_FLASH_CACHE_WS_2_VALUE_MASK;
+ }
+ else if (freq < CY_FLASH_CACHE_WS_3_FREQ_MAX)
+ {
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+ CY_FLASH_CACHE_WS_3_VALUE_MASK;
+ }
+#if (CY_PSOC5)
+ else if (freq < CY_FLASH_CACHE_WS_4_FREQ_MAX)
+ {
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+ CY_FLASH_CACHE_WS_4_VALUE_MASK;
+ }
+ else if (freq <= CY_FLASH_CACHE_WS_5_FREQ_MAX)
+ {
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+ CY_FLASH_CACHE_WS_5_VALUE_MASK;
+ }
+#endif /* (CY_PSOC5) */
+ else
+ {
+ /* Halt CPU in debug mode if frequency is invalid */
+ CYASSERT(0u != 0u);
+ }
/* Restore global interrupt enable state */
CyExitCriticalSection(interruptState);
*******************************************************************************/
void CyEEPROM_Start(void)
{
- /* Active Power Mode */
- *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
+ uint8 interruptState;
+
+ interruptState = CyEnterCriticalSection();
+
+
+ /***************************************************************************
+ * Enable SPC clock. This also internally enables the 36MHz IMO, since this
+ * is required for the SPC to function.
+ ***************************************************************************/
+ CY_FLASH_PM_ACT_CFG0_REG |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
+ CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
- /* Standby Power Mode */
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
+
+ /***************************************************************************
+ * The wake count defines the number of Bus Clock cycles it takes for the
+ * flash or EEPROM to wake up from a low power mode independent of the chip
+ * power mode. Wake up time for these blocks is 5 us.
+ * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
+ * (30d) defines the wake up time as 60 cycles of the Bus Clock.
+ * This register needs to be written with a value dependent on the Bus Clock
+ * frequency so that the duration of the cycles is equal to or greater than
+ * the 5 us delay required.
+ ***************************************************************************/
+ CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
+
+
+ /***************************************************************************
+ * Enable EEPROM. Re-enabling an EEPROM macro takes 5us. During this time,
+ * the EE will not acknowledge a PHUB request.
+ ***************************************************************************/
+ CY_FLASH_PM_ACT_CFG12_REG |= CY_FLASH_PM_ACT_CFG12_EN_EE;
+ CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_EE;
+
+ while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
+ {
+ /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
+ }
+
+ CyExitCriticalSection(interruptState);
}
*******************************************************************************/
void CyEEPROM_Stop (void)
{
- /* Active Power Mode */
- *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
+ uint8 interruptState;
- /* Standby Power Mode */
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
+ interruptState = CyEnterCriticalSection();
+
+ CY_FLASH_PM_ACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_EE));
+ CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_EE));
+
+ CyExitCriticalSection(interruptState);
}
*******************************************************************************/
void CyEEPROM_ReadReserve(void)
{
- /* Make a request for PHUB to have access */
- *CY_FLASH_EE_SCR_PTR |= CY_FLASH_EE_SCR_AHB_EE_REQ;
+ /* Make request for PHUB to have access */
+ CY_FLASH_EE_SCR_REG |= CY_FLASH_EE_SCR_AHB_EE_REQ;
- while (0u == (*CY_FLASH_EE_SCR_PTR & CY_FLASH_EE_SCR_AHB_EE_ACK))
+ while (0u == (CY_FLASH_EE_SCR_REG & CY_FLASH_EE_SCR_AHB_EE_ACK))
{
- /* Wait for acknowledgement from PHUB */
+ /* Wait for acknowledgment from PHUB */
}
}
*******************************************************************************/
void CyEEPROM_ReadRelease(void)
{
- *CY_FLASH_EE_SCR_PTR |= 0x00u;
+ CY_FLASH_EE_SCR_REG &= (uint8)(~CY_FLASH_EE_SCR_AHB_EE_REQ);
}
/*******************************************************************************
* File Name: CyFlash.h
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides the function definitions for the FLASH/EEPROM.
* System Reference Guide provided with PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#define CY_FLASH_NUMBER_ROWS (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE)
#define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE)
+#if(CYDEV_ECC_ENABLE == 0)
+ #define CY_FLASH_SIZEOF_FULL_ROW (CY_FLASH_SIZEOF_ROW + CY_FLASH_SIZEOF_ECC_ROW)
+#else
+ #define CY_FLASH_SIZEOF_FULL_ROW (CY_FLASH_SIZEOF_ROW)
+#endif /* (CYDEV_ECC_ENABLE == 0) */
#define CY_EEPROM_BASE (CYDEV_EE_BASE)
#define CY_EEPROM_SIZE (CYDEV_EE_SIZE)
#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EEPROM_SECTOR_SIZE)
#define CY_EEPROM_SIZEOF_ROW (CYDEV_EEPROM_ROW_SIZE)
-#define CY_EEPROM_NUMBER_ROWS (EEPROM_SIZE / CYDEV_EEPROM_ROW_SIZE)
+#define CY_EEPROM_NUMBER_ROWS (CYDEV_EE_SIZE / CYDEV_EEPROM_ROW_SIZE)
#define CY_EEPROM_NUMBER_ARRAYS (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY)
-
+#define CY_EEPROM_NUMBER_SECTORS (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)
+#define CY_EEPROM_SIZEOF_SECTOR (CYDEV_EEPROM_SECTOR_SIZE)
#if !defined(CYDEV_FLS_BASE)
#define CYDEV_FLS_BASE CYDEV_FLASH_BASE
/***************************************
* Registers
***************************************/
+/* Active Power Mode Configuration Register 0 */
+#define CY_FLASH_PM_ACT_CFG0_REG (* (reg8 *) CYREG_PM_ACT_CFG0)
+#define CY_FLASH_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)
+
+/* Alternate Active Power Mode Configuration Register 0 */
+#define CY_FLASH_PM_ALTACT_CFG0_REG (* (reg8 *) CYREG_PM_STBY_CFG0)
+#define CY_FLASH_PM_ALTACT_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0)
+
/* Active Power Mode Configuration Register 12 */
-#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12)
-#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_CFG12_REG (* (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_CFG12_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)
/* Alternate Active Power Mode Configuration Register 12 */
-#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12)
-#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_CFG12_REG (* (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_CFG12_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)
+
+/* Wake count (BUS_CLK cycles) it takes for the Flash and EEPROM to wake up */
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_REG (* (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_PTR ( (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
+
+/* Flash macro control register */
+#define CY_FLASH_SPC_FM_EE_CR_REG (* (reg8 *) CYREG_SPC_FM_EE_CR)
+#define CY_FLASH_SPC_FM_EE_CR_PTR ( (reg8 *) CYREG_SPC_FM_EE_CR)
/* Cache Control Register */
***************************************/
/* Power Mode Masks */
-#define CY_FLASH_PM_EE_MASK (0x10u)
-#define CY_FLASH_PM_FLASH_MASK (0x01u)
-/* Frequency Constants */
+/* Enable EEPROM */
+#define CY_FLASH_PM_ACT_CFG12_EN_EE (0x10u)
+#define CY_FLASH_PM_ALTACT_CFG12_EN_EE (0x10u)
+
+/* Enable Flash */
#if (CY_PSOC3)
+ #define CY_FLASH_PM_ACT_CFG12_EN_FM (0x01u)
+ #define CY_FLASH_PM_ALTACT_CFG12_EN_FM (0x01u)
+#else
+ #define CY_FLASH_PM_ACT_CFG12_EN_FM (0x0Fu)
+ #define CY_FLASH_PM_ALTACT_CFG12_EN_FM (0x0Fu)
+#endif /* (CY_PSOC3) */
+
- #define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u)
- #define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u)
- #define CY_FLASH_GREATER_44MHz (0x03u)
+/* Frequency Constants */
+#if (CY_PSOC3)
+ #define CY_FLASH_CACHE_WS_VALUE_MASK (0xC0u)
+ #define CY_FLASH_CACHE_WS_1_VALUE_MASK (0x40u)
+ #define CY_FLASH_CACHE_WS_2_VALUE_MASK (0x80u)
+ #define CY_FLASH_CACHE_WS_3_VALUE_MASK (0xC0u)
+
+ #define CY_FLASH_CACHE_WS_1_FREQ_MAX (22u)
+ #define CY_FLASH_CACHE_WS_2_FREQ_MAX (44u)
+ #define CY_FLASH_CACHE_WS_3_FREQ_MAX (67u)
#endif /* (CY_PSOC3) */
#if (CY_PSOC5)
-
- #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u)
- #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u)
- #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u)
- #define CY_FLASH_GREATER_51MHz (0x00u)
-
+ #define CY_FLASH_CACHE_WS_VALUE_MASK (0xE0u)
+ #define CY_FLASH_CACHE_WS_1_VALUE_MASK (0x40u)
+ #define CY_FLASH_CACHE_WS_2_VALUE_MASK (0x80u)
+ #define CY_FLASH_CACHE_WS_3_VALUE_MASK (0xC0u)
+ #define CY_FLASH_CACHE_WS_4_VALUE_MASK (0x00u)
+ #define CY_FLASH_CACHE_WS_5_VALUE_MASK (0x20u)
+
+ #define CY_FLASH_CACHE_WS_1_FREQ_MAX (16u)
+ #define CY_FLASH_CACHE_WS_2_FREQ_MAX (33u)
+ #define CY_FLASH_CACHE_WS_3_FREQ_MAX (50u)
+ #define CY_FLASH_CACHE_WS_4_FREQ_MAX (67u)
+ #define CY_FLASH_CACHE_WS_5_FREQ_MAX (83u)
#endif /* (CY_PSOC5) */
#define CY_FLASH_CYCLES_MASK_SHIFT (0x06u)
#define CY_FLASH_CYCLES_MASK ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT)))
-#define CY_FLASH_EE_STARTUP_DELAY (5u)
#define CY_FLASH_EE_SCR_AHB_EE_REQ (0x01u)
#define CY_FLASH_EE_SCR_AHB_EE_ACK (0x02u)
+#define CY_FLASH_EE_EE_AWAKE (0x20u)
+
+/* 5(us) * BUS_CLK(80 MHz) / granularity(2) */
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ (0xC8u)
+
+/* Enable clk_spc. This also internally enables the 36MHz IMO. */
+#define CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC (0x08u)
+#define CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC (0x08u)
/* Default values for getting temperature. */
/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
+* Thne following code is OBSOLETE and must not be used starting with cy_boot
+* 4.20.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+* #ifdef <OBSOLETED_DEFINE>
+* #undef <OBSOLETED_DEFINE>
+* #define <OBSOLETED_DEFINE> (<New Value>)
+* #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+* used in the application and their modification might lead to unexpected
+* consequences.
+*******************************************************************************/
+#if (CY_PSOC5)
+ #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u)
+ #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u)
+ #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u)
+ #define CY_FLASH_GREATER_51MHz (0x00u)
+#endif /* (CY_PSOC5) */
+
+#if (CY_PSOC3)
+ #define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u)
+ #define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u)
+ #define CY_FLASH_GREATER_44MHz (0x03u)
+#endif /* (CY_PSOC3) */
+
+#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_EE_MASK (0x10u)
+#define CY_FLASH_PM_FLASH_MASK (0x01u)
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.0
*******************************************************************************/
#define FLASH_SIZE (CY_FLASH_SIZE)
#define FLASH_SIZEOF_SECTOR (CY_FLASH_SIZEOF_ARRAY)
#define EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY)
#define EEPROM_NUMBER_ROWS (CY_EEPROM_NUMBER_ROWS)
#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS)
-#define CY_EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS)
-#define CY_EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY)
/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.30
*******************************************************************************/
#define FLASH_CYCLES_PTR (CY_FLASH_CONTROL_PTR)
/*******************************************************************************
* File Name: CyLib.c
-* Version 4.0
+* Version 4.20
*
* Description:
-* Provides system API for the clocking, interrupts and watchdog timer.
+* Provides a system API for the clocking, interrupts and watchdog timer.
*
* Note:
* Documentation of the API's in this file is located in the
* System Reference Guide provided with PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
static void CyIMO_SetTrimValue(uint8 freq) ;
static void CyBusClk_Internal_SetDivider(uint16 divider);
+#if(CY_PSOC5)
+ static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS];
+ static void CySysTickServiceCallbacks(void);
+ uint32 CySysTickInitVar = 0u;
+#endif /* (CY_PSOC5) */
+
/*******************************************************************************
* Function Name: CyPLL_OUT_Start
* clock can still be used.
*
* Side Effects:
-* If wait is enabled: This function wses the Fast Time Wheel to time the wait.
+* If wait is enabled: This function uses the Fast Time Wheel to time the wait.
* Any other use of the Fast Time Wheel will be stopped during the period of
* this function and then restored. This function also uses the 100 KHz ILO.
* If not enabled, this function will enable the 100 KHz ILO for the period of
uint8 pmTwCfg2State;
- /* Enables the PLL circuit */
+ /* Enables PLL circuit */
CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE;
if(wait != 0u)
while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
{
- /* Wait for the interrupt status */
+ /* Wait for interrupt status */
if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))
{
if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))
* None
*
* Side Effects:
-* If as result of this function execution the CPU clock frequency is increased
+* If this function execution results in the CPU clock frequency increasing,
* then the number of clock cycles the cache will wait before it samples data
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-* with appropriate parameter. It can be optionally called if CPU clock
-* frequency is lowered in order to improve CPU performance.
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+* with an appropriate parameter. It can be optionally called if the CPU clock
+* frequency is lowered in order to improve the CPU performance.
* See CyFlash_SetWaitCycles() description for more information.
*
*******************************************************************************/
* None
*
* Side Effects:
-* If as result of this function execution the CPU clock frequency is increased
+* If this function execution results in the CPU clock frequency increasing,
* then the number of clock cycles the cache will wait before it samples data
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-* with appropriate parameter. It can be optionally called if CPU clock
-* frequency is lowered in order to improve CPU performance.
+* coming back from the3 Flash must be adjusted by calling CyFlash_SetWaitCycles()
+* with an appropriate parameter. It can be optionally called if the CPU clock
+* frequency is lowered in order to improve the CPU performance.
* See CyFlash_SetWaitCycles() description for more information.
*
*******************************************************************************/
* None
*
* Side Effects:
-* If wait is enabled: This function wses the Fast Time Wheel to time the wait.
+* If wait is enabled: This function uses the Fast Time Wheel to time the wait.
* Any other use of the Fast Time Wheel will be stopped during the period of
* this function and then restored. This function also uses the 100 KHz ILO.
* If not enabled, this function will enable the 100 KHz ILO for the period of
if(0u != wait)
{
- /* Need to turn on the 100KHz ILO if it happens to not already be running.*/
+ /* Need to turn on 100KHz ILO if it happens to not already be running.*/
ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;
pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG;
pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG;
while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
{
- /* Wait for the interrupt status */
+ /* Wait for interrupt status */
}
if(0u == ilo100KhzEnable)
/* If USB is powered */
if(usbPowerOn == 1u)
{
- /* Lock the USB Oscillator */
+ /* Lock USB Oscillator */
CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN;
}
break;
* None
*
* Side Effects:
-* If as result of this function execution the CPU clock frequency is increased
+* If this function execution results in the CPU clock frequency increasing,
* then the number of clock cycles the cache will wait before it samples data
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-* with appropriate parameter. It can be optionally called if CPU clock
-* frequency is lowered in order to improve CPU performance.
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+* with an appropriate parameter. It can be optionally called if the CPU clock
+* frequency is lowered in order to improve the CPU performance.
* See CyFlash_SetWaitCycles() description for more information.
*
* When the USB setting is chosen, the USB clock locking circuit is enabled.
uint8 nextFreq;
/***************************************************************************
- * When changing the IMO frequency the Trim values must also be set
+ * If the IMO frequency is changed,the Trim values must also be set
* accordingly.This requires reading the current frequency. If the new
- * frequency is faster, then set the new trim and then change the frequency,
- * otherwise change the frequency and then set the new trim values.
+ * frequency is faster, then set a new trim and then change the frequency,
+ * otherwise change the frequency and then set new trim values.
***************************************************************************/
currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK));
- /* Check if the requested frequency is USB. */
+ /* Check if requested frequency is USB. */
nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq;
switch (currentFreq)
if (nextFreq >= currentFreq)
{
- /* Set the new trim first */
+ /* Set new trim first */
CyIMO_SetTrimValue(freq);
}
- /* Set the usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */
+ /* Set usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */
switch(freq)
{
case CY_IMO_FREQ_3MHZ:
break;
}
- /* Turn on the IMO Doubler, if switching to CY_IMO_FREQ_USB */
+ /* Tu rn onIMO Doubler, if switching to CY_IMO_FREQ_USB */
if (freq == CY_IMO_FREQ_USB)
{
CyIMO_EnableDoubler();
if (nextFreq < currentFreq)
{
- /* Set the new trim after setting the frequency */
+ /* Set the trim after setting frequency */
CyIMO_SetTrimValue(freq);
}
}
* Sets the source of the clock output from the IMO block.
*
* The output from the IMO is by default the IMO itself. Optionally the MHz
-* Crystal or a DSI input can be the source of the IMO output instead.
+* Crystal or DSI input can be the source of the IMO output instead.
*
* Parameters:
* source: CY_IMO_SOURCE_DSI to set the DSI as source.
* None
*
* Side Effects:
-* If as result of this function execution the CPU clock frequency is increased
+* If this function execution resulted in the CPU clock frequency increasing,
* then the number of clock cycles the cache will wait before it samples data
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-* with appropriate parameter. It can be optionally called if CPU clock
-* frequency is lowered in order to improve CPU performance.
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+* with an appropriate parameter. It can be optionally called if the CPU clock
+* frequency is lowered in order to improve the CPU performance.
* See CyFlash_SetWaitCycles() description for more information.
*
*******************************************************************************/
*******************************************************************************/
void CyIMO_EnableDoubler(void)
{
- /* Set the FASTCLK_IMO_CR_PTR regigster's 4th bit */
+ /* Set FASTCLK_IMO_CR_PTR regigster's 4th bit */
CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER;
}
* The current source and the new source must both be running and stable before
* calling this function.
*
-* If as result of this function execution the CPU clock frequency is increased
+* If this function execution resulted in the CPU clock frequency increasing,
* then the number of clock cycles the cache will wait before it samples data
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-* with appropriate parameter. It can be optionally called if CPU clock
-* frequency is lowered in order to improve CPU performance.
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+* with an appropriate parameter. It can be optionally called if the CPU clock
+* frequency is lowered in order to improve the CPU performance.
* See CyFlash_SetWaitCycles() description for more information.
*
*******************************************************************************/
*
* Parameters:
* uint8 divider:
-* Valid range [0-255]. The clock will be divided by this value + 1.
-* For example to divide by 2 this parameter should be set to 1.
+* The valid range is [0-255]. The clock will be divided by this value + 1.
+* For example to divide this parameter by two should be set to 1.
*
* Return:
* None
*
* Side Effects:
-* If as result of this function execution the CPU clock frequency is increased
+* If this function execution resulted in the CPU clock frequency increasing,
* then the number of clock cycles the cache will wait before it samples data
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-* with appropriate parameter. It can be optionally called if CPU clock
-* frequency is lowered in order to improve CPU performance.
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+* with an appropriate parameter. It can be optionally called if the CPU clock
+* frequency is lowered in order to improve the CPU performance.
* See CyFlash_SetWaitCycles() description for more information.
*
* When changing the Master or Bus clock divider value from div-by-n to div-by-1
********************************************************************************
*
* Summary:
-* Function used by CyBusClk_SetDivider(). For internal use only.
+* The function used by CyBusClk_SetDivider(). For internal use only.
*
* Parameters:
* divider: Valid range [0-65535].
* The clock will be divided by this value + 1.
-* For example to divide by 2 this parameter should be set to 1.
+* For example, to divide this parameter by two should be set to 1.
*
* Return:
* None
/* Enable mask bits to enable shadow loads */
CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK;
- /* Update Shadow Divider Value Register with the new divider */
+ /* Update Shadow Divider Value Register with new divider */
CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider);
CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider);
********************************************************************************
*
* Summary:
-* Sets the divider value used to generate Bus Clock.
+* Sets the divider value used to generate the Bus Clock.
*
* Parameters:
* divider: Valid range [0-65535]. The clock will be divided by this value + 1.
-* For example to divide by 2 this parameter should be set to 1.
+* For example, to divide this parameter by two should be set to 1.
*
* Return:
* None
*
* Side Effects:
-* If as result of this function execution the CPU clock frequency is increased
+* If this function execution resulted in the CPU clock frequency increasing,
* then the number of clock cycles the cache will wait before it samples data
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-* with appropriate parameter. It can be optionally called if CPU clock
-* frequency is lowered in order to improve CPU performance.
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+* with an appropriate parameter. It can be optionally called if the CPU clock
+* frequency is lowered in order to improve the CPU performance.
* See CyFlash_SetWaitCycles() description for more information.
*
*******************************************************************************/
interruptState = CyEnterCriticalSection();
- /* Work around to set the bus clock divider value */
+ /* Work around to set bus clock divider value */
busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u);
busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG;
if ((divider == 0u) || (busClkDiv == 0u))
{
- /* Save away the master clock divider value */
+ /* Save away master clock divider value */
masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG;
if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV)
if (divider == 0u)
{
- /* Set the SSS bit and the divider register desired value */
+ /* Set SSS bit and divider register desired value */
CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS;
CyBusClk_Internal_SetDivider(divider);
}
CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS));
}
- /* Restore the master clock */
+ /* Restore master clock */
CyMasterClk_SetDivider(masterClkDiv);
}
else
*
* Parameters:
* divider: Valid range [0-15]. The clock will be divided by this value + 1.
- * For example to divide by 2 this parameter should be set to 1.
+ * For example, to divide this parameter by two should be set to 1.
*
* Return:
* None
*
* Side Effects:
- * If as result of this function execution the CPU clock frequency is increased
- * then the number of clock cycles the cache will wait before it samples data
- * coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
- * with appropriate parameter. It can be optionally called if CPU clock
- * frequency is lowered in order to improve CPU performance.
+ * If this function execution resulted in the CPU clock frequency increasing,
+* then the number of clock cycles the cache will wait before it samples data
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+* with an appropriate parameter. It can be optionally called if the CPU clock
+* frequency is lowered in order to improve the CPU performance.
* See CyFlash_SetWaitCycles() description for more information.
*
*******************************************************************************/
*******************************************************************************/
void CyILO_Start1K(void)
{
- /* Set the bit 1 of ILO RS */
+ /* Set bit 1 of ILO RS */
CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ;
}
* Summary:
* Disables the ILO 1 KHz oscillator.
*
-* Note The ILO 1 KHz oscillator must be enabled if Sleep or Hibernate low power
+* Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low power
* mode APIs are expected to be used. For more information, refer to the Power
* Management section of this document.
*
*******************************************************************************/
void CyILO_Stop1K(void)
{
- /* Clear the bit 1 of ILO RS */
+ /* Clear bit 1 of ILO RS */
CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ));
}
*******************************************************************************/
void CyILO_Enable33K(void)
{
- /* Set the bit 5 of ILO RS */
+ /* Set bit 5 of ILO RS */
CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ;
}
/* Get current state. */
state = CY_LIB_SLOWCLK_ILO_CR0_REG;
- /* Set the the oscillator power mode. */
+ /* Set the oscillator power mode. */
if(mode != CY_ILO_FAST_START)
{
CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE);
CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE)));
}
- /* Return the old mode. */
+ /* Return old mode. */
return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION);
}
CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN;
#endif /* (CY_PSOC3) */
- /* Enable operation of the 32K Crystal Oscillator */
+ /* Enable operation of 32K Crystal Oscillator */
CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN;
for (i = 1000u; i > 0u; i--)
{
if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT))
{
- /* Ready - switch to the hign power mode */
+ /* Ready - switch to high power mode */
(void) CyXTAL_32KHZ_SetPowerMode(0u);
break;
********************************************************************************
*
* Summary:
-* Sets the power mode for the 32 KHz oscillator used during sleep mode.
+* Sets the power mode for the 32 KHz oscillator used during the sleep mode.
* Allows for lower power during sleep when there are fewer sources of noise.
-* During active mode the oscillator is always run in high power mode.
+* During the active mode the oscillator is always run in the high power mode.
*
* Parameters:
* uint8 mode
uint8 pmTwCfg2Tmp;
- /* Enables the MHz crystal oscillator circuit */
+ /* Enables MHz crystal oscillator circuit */
CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE;
/* Read XERR bit to clear it */
(void) CY_CLK_XMHZ_CSR_REG;
- /* Wait for a millisecond - 4 x 250 us */
+ /* Wait for 1 millisecond - 4 x 250 us */
for(count = 4u; count > 0u; count--)
{
while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
{
- /* Wait for the FTW interrupt event */
+ /* Wait for FTW interrupt event */
}
}
/*******************************************************************
- * High output indicates oscillator failure.
- * Only can be used after start-up interval (1 ms) is completed.
+ * High output indicates an oscillator failure.
+ * Only can be used after a start-up interval (1 ms) is completed.
*******************************************************************/
if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR))
{
*******************************************************************************/
void CyXTAL_Stop(void)
{
- /* Disable the the oscillator. */
+ /* Disable oscillator. */
FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE));
}
*
* Summary:
* Reads the XERR status bit for the megahertz crystal. This status bit is a
-* sticky clear on read value. This function is not available for PSoC5.
+* sticky, clear on read. This function is not available for PSoC5.
*
* Parameters:
* None
uint8 CyXTAL_ReadStatus(void)
{
/***************************************************************************
- * High output indicates oscillator failure. Only use this after start-up
- * interval is completed. This can be used for status and failure recovery.
+ * High output indicates an oscillator failure. Only use this after a start-up
+ * interval is completed. This can be used for the status and failure recovery.
***************************************************************************/
return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u);
}
* Enables the fault recovery circuit which will switch to the IMO in the case
* of a fault in the megahertz crystal circuit. The crystal must be up and
* running with the XERR bit at 0, before calling this function to prevent
-* immediate fault switchover. This function is not available for PSoC5.
+* an immediate fault switchover. This function is not available for PSoC5.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Sets the startup settings for the crystal. Logic model outputs a frequency
+* Sets the startup settings for the crystal. The logic model outputs a frequency
* (setting + 4) MHz when enabled.
*
* This is artificial as the actual frequency is determined by an attached
*
* Parameters:
* setting: Valid range [0-31].
-* Value is dependent on the frequency and quality of the crystal being used.
+* The value is dependent on the frequency and quality of the crystal being used.
* Refer to the device TRM and datasheet for more information.
*
* Return:
********************************************************************************
*
* Summary:
-* Forces a software reset of the device.
+* Forces a device software reset.
*
* Parameters:
* None
*
* Note:
* CyDelay has been implemented with the instruction cache assumed enabled. When
-* instruction cache is disabled on PSoC5, CyDelay will be two times larger. For
-* example, with instruction cache disabled CyDelay(100) would result in about
-* 200 ms delay instead of 100 ms.
+* the instruction cache is disabled on PSoC5, CyDelay will be two times larger.
+* For example, with instruction cache disabled CyDelay(100) would result in
+* about 200 ms delay instead of 100 ms.
*
* Parameters:
* milliseconds: number of milliseconds to delay.
*
* Side Effects:
* CyDelayUS has been implemented with the instruction cache assumed enabled.
- * When instruction cache is disabled on PSoC 5, CyDelayUs will be two times
- * larger. For example, with instruction cache disabled CyDelayUs(100) would
+ * When the instruction cache is disabled on PSoC 5, CyDelayUs will be two times
+ * larger. For example, with the instruction cache disabled CyDelayUs(100) would
* result in about 200 us delay instead of 100 us.
*
* If the bus clock frequency is a small non-integer number, the actual delay
********************************************************************************
*
* Summary:
-* Sets clock frequency for CyDelay.
+* Sets the clock frequency for CyDelay.
*
* Parameters:
-* freq: Frequency of bus clock in Hertz.
+* freq: The frequency of the bus clock in Hertz.
*
* Return:
* None
* Enables the watchdog timer.
*
* The timer is configured for the specified count interval, the central
-* timewheel is cleared, the setting for low power mode is configured and the
+* timewheel is cleared, the setting for the low power mode is configured and the
* watchdog timer is enabled.
*
* Once enabled the watchdog cannot be disabled. The watchdog counts each time
CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET;
CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET));
- /* Setting the low power mode */
+ /* Setting low power mode */
CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) |
(CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK)));
- /* Enables the watchdog reset */
+ /* Enables watchdog reset */
CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN;
}
*
* Summary:
* Enables the digital low voltage monitors to generate interrupt on Vddd
-* archives specified threshold and optionally resets device.
+* archives specified threshold and optionally resets the device.
*
* Parameters:
-* reset: Option to reset device at a specified Vddd threshold:
+* reset: The option to reset the device at a specified Vddd threshold:
* 0 - Device is not reset.
* 1 - Device is reset.
*
* threshold: Sets the trip level for the voltage monitor.
-* Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV
-* interval.
+* Values from 1.70 V to 5.45 V are accepted with an interval of approximately
+* 250 mV.
*
* Return:
* None
(CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK)));
CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN;
- /* Timeout to eliminate glitches on the LVI/HVI when enabling */
+ /* Timeout to eliminate glitches on LVI/HVI when enabling */
CyDelayUs(1u);
(void)CY_VD_PERSISTENT_STATUS_REG;
*
* Summary:
* Enables the analog low voltage monitors to generate interrupt on Vdda
-* archives specified threshold and optionally resets device.
+* archives specified threshold and optionally resets the device.
*
* Parameters:
-* reset: Option to reset device at a specified Vdda threshold:
+* reset: The option to reset the device at a specified Vdda threshold:
* 0 - Device is not reset.
* 1 - Device is reset.
*
CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu);
CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN;
- /* Timeout to eliminate glitches on the LVI/HVI when enabling */
+ /* Timeout to eliminate glitches on LVI/HVI when enabling */
CyDelayUs(1u);
(void)CY_VD_PERSISTENT_STATUS_REG;
CY_NOP;
CY_NOP;
- /* All entries in the cache are invalidated on the next clock cycle. */
+ /* All entries in cache are invalidated on next clock cycle. */
CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH;
+ /* Once this is executed it's guaranteed the cache has been flushed */
+ (void) CY_CACHE_CONTROL_REG;
- /***********************************************************************
- * The prefetch unit could/would be filled with the instructions that
- * succeed the flush. Since a flush is desired then theoretically those
- * instructions might be considered stale/invalid.
- ***********************************************************************/
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
+ /* Flush the pipeline */
+ CY_SYS_ISB;
/* Restore global interrupt enable state */
CyExitCriticalSection(interruptState);
* SysTick, PendSV and others.
*
* Parameters:
- * number: Interrupt number, valid range [0-15].
- address: Pointer to an interrupt service routine.
+ * number: System interrupt number:
+ * CY_INT_NMI_IRQN - Non Maskable Interrupt
+ * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt
+ * CY_INT_MEM_MANAGE_IRQN - Memory Management Interrupt
+ * CY_INT_BUS_FAULT_IRQN - Bus Fault Interrupt
+ * CY_INT_USAGE_FAULT_IRQN - Usage Fault Interrupt
+ * CY_INT_SVCALL_IRQN - SV Call Interrupt
+ * CY_INT_DEBUG_MONITOR_IRQN - Debug Monitor Interrupt
+ * CY_INT_PEND_SV_IRQN - Pend SV Interrupt
+ * CY_INT_SYSTICK_IRQN - System Tick Interrupt
+ *
+ * address: Pointer to an interrupt service routine.
*
* Return:
* The old ISR vector at this location.
* SysTick, PendSV and others.
*
* Parameters:
- * number: The interrupt number, valid range [0-15].
+ * number: System interrupt number:
+ * CY_INT_NMI_IRQN - Non Maskable Interrupt
+ * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt
+ * CY_INT_MEMORY_MANAGEMENT_IRQN - Memory Management Interrupt
+ * CY_INT_BUS_FAULT_IRQN - Bus Fault Interrupt
+ * CY_INT_USAGE_FAULT_IRQN - Usage Fault Interrupt
+ * CY_INT_SVCALL_IRQN - SV Call Interrupt
+ * CY_INT_DEBUG_MONITOR_IRQN - Debug Monitor Interrupt
+ * CY_INT_PEND_SV_IRQN - Pend SV Interrupt
+ * CY_INT_SYSTICK_IRQN - System Tick Interrupt
*
* Return:
* Address of the ISR in the interrupt vector table.
* number: Valid range [0-31]. Interrupt number
*
* Return:
- * Address of the ISR in the interrupt vector table.
+ * The address of the ISR in the interrupt vector table.
*
*******************************************************************************/
cyisraddress CyIntGetVector(uint8 number)
CYASSERT(number <= CY_INT_NUMBER_MAX);
- /* Get a pointer to the Interrupt enable register. */
+ /* Get pointer to Interrupt enable register. */
stateReg = CY_INT_ENABLE_PTR;
- /* Get the state of the interrupt. */
+ /* Get state of interrupt. */
return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u));
}
CYASSERT(number <= CY_INT_NUMBER_MAX);
- /* Get a pointer to the Interrupt enable register. */
+ /* Get pointer to Interrupt enable register. */
stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u);
- /* Get the state of the interrupt. */
+ /* Get state of interrupt. */
return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u)));
}
* If 1 is passed as a parameter:
* - if any of the SC blocks are used - enable pumps for the SC blocks and
* start boost clock.
- * - For the each enabled SC block set boost clock index and enable boost
+ * - For each enabled SC block set a boost clock index and enable the boost
* clock.
*
* If non-1 value is passed as a parameter:
* - If all SC blocks are not used - disable pumps for the SC blocks and
- * stop boost clock.
- * - For the each enabled SC block clear boost clock index and disable boost
+ * stop the boost clock.
+ * - For each enabled SC block clear the boost clock index and disable the boost
* clock.
*
- * The global variable CyScPumpEnabled is updated to be equal to passed
+ * The global variable CyScPumpEnabled is updated to be equal to passed the
* parameter.
*
* Parameters:
- * uint8 enable: Enable/disable SC pumps and boost clock for enabled SC block.
+ * uint8 enable: Enable/disable SC pumps and the boost clock for the enabled SC block.
* 1 - Enable
* 0 - Disable
*
#endif /* (CYDEV_VARIABLE_VDDA == 1) */
+#if(CY_PSOC5)
+ /*******************************************************************************
+ * Function Name: CySysTickStart
+ ********************************************************************************
+ *
+ * Summary:
+ * Configures the SysTick timer to generate interrupt every 1 ms by call to the
+ * CySysTickInit() function and starts it by calling CySysTickEnable() function.
+ * Refer to the corresponding function description for the details.
+
+ * Parameters:
+ * None
+ *
+ * Return:
+ * None
+ *
+ * Side Effects:
+ * Clears SysTick count flag if it was set
+ *
+ *******************************************************************************/
+ void CySysTickStart(void)
+ {
+ if (0u == CySysTickInitVar)
+ {
+ CySysTickInit();
+ CySysTickInitVar = 1u;
+ }
+
+ CySysTickEnable();
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickInit
+ ********************************************************************************
+ *
+ * Summary:
+ * Initializes the callback addresses with pointers to NULL, associates the
+ * SysTick system vector with the function that is responsible for calling
+ * registered callback functions, configures SysTick timer to generate interrupt
+ * every 1 ms.
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * None
+ *
+ * Side Effects:
+ * Clears SysTick count flag if it was set.
+ *
+ * The 1 ms interrupt interval is configured based on the frequency determined
+ * by PSoC Creator at build time. If System clock frequency is changed in
+ * runtime, the CyDelayFreq() with the appropriate parameter should be called.
+ *
+ *******************************************************************************/
+ void CySysTickInit(void)
+ {
+ uint32 i;
+
+ for (i = 0u; i<CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+ {
+ CySysTickCallbacks[i] = (void *) 0;
+ }
+
+ (void) CyIntSetSysVector(CY_INT_SYSTICK_IRQN, &CySysTickServiceCallbacks);
+ CySysTickSetClockSource(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK);
+ CySysTickSetReload(cydelay_freq_hz/1000u);
+ CySysTickClear();
+ CyIntEnable(CY_INT_SYSTICK_IRQN);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickEnable
+ ********************************************************************************
+ *
+ * Summary:
+ * Enables the SysTick timer and its interrupt.
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * None
+ *
+ * Side Effects:
+ * Clears SysTick count flag if it was set
+ *
+ *******************************************************************************/
+ void CySysTickEnable(void)
+ {
+ CySysTickEnableInterrupt();
+ CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE;
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickStop
+ ********************************************************************************
+ *
+ * Summary:
+ * Stops the system timer (SysTick).
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * None
+ *
+ * Side Effects:
+ * Clears SysTick count flag if it was set
+ *
+ *******************************************************************************/
+ void CySysTickStop(void)
+ {
+ CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE));
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickEnableInterrupt
+ ********************************************************************************
+ *
+ * Summary:
+ * Enables the SysTick interrupt.
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * None
+ *
+ * Side Effects:
+ * Clears SysTick count flag if it was set
+ *
+ *******************************************************************************/
+ void CySysTickEnableInterrupt(void)
+ {
+ CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE_INT;
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickDisableInterrupt
+ ********************************************************************************
+ *
+ * Summary:
+ * Disables the SysTick interrupt.
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * None
+ *
+ * Side Effects:
+ * Clears SysTick count flag if it was set
+ *
+ *******************************************************************************/
+ void CySysTickDisableInterrupt(void)
+ {
+ CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE_INT));
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickSetReload
+ ********************************************************************************
+ *
+ * Summary:
+ * Sets value the counter is set to on startup and after it reaches zero. This
+ * function do not change or reset current sysTick counter value, so it should
+ * be cleared using CySysTickClear() API.
+ *
+ * Parameters:
+ * value: Valid range [0x0-0x00FFFFFF]. Counter reset value.
+ *
+ * Return:
+ * None
+ *
+ *******************************************************************************/
+ void CySysTickSetReload(uint32 value)
+ {
+ CY_SYS_SYST_RVR_REG = (value & CY_SYS_SYST_RVR_CNT_MASK);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickGetReload
+ ********************************************************************************
+ *
+ * Summary:
+ * Sets value the counter is set to on startup and after it reaches zero.
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * Counter reset value
+ *
+ *******************************************************************************/
+ uint32 CySysTickGetReload(void)
+ {
+ return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_RVR_CNT_MASK);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickGetValue
+ ********************************************************************************
+ *
+ * Summary:
+ * Gets current SysTick counter value.
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * Current SysTick counter value
+ *
+ *******************************************************************************/
+ uint32 CySysTickGetValue(void)
+ {
+ return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_CVR_REG);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickSetClockSource
+ ********************************************************************************
+ *
+ * Summary:
+ * Sets the clock source for the SysTick counter.
+ *
+ * Parameters:
+ * clockSource: Clock source for SysTick counter
+ * Define Clock Source
+ * CY_SYS_SYST_CSR_CLK_SRC_SYSCLK SysTick is clocked by CPU clock.
+ * CY_SYS_SYST_CSR_CLK_SRC_LFCLK SysTick is clocked by the low frequency
+ * clock (ILO 100 KHz for PSoC 5LP, LFCLK for PSoC 4).
+ *
+ * Return:
+ * None
+ *
+ * Side Effects:
+ * Clears SysTick count flag if it was set. If clock source is not ready this
+ * function call will have no effect. After changing clock source to the low frequency
+ * clock the counter and reload register values will remain unchanged so time to
+ * the interrupt will be significantly bigger and vice versa.
+ *
+ *******************************************************************************/
+ void CySysTickSetClockSource(uint32 clockSource)
+ {
+ if (clockSource == CY_SYS_SYST_CSR_CLK_SRC_SYSCLK)
+ {
+ CY_SYS_SYST_CSR_REG |= (uint32)(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT);
+ }
+ else
+ {
+ CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT));
+ }
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickGetCountFlag
+ ********************************************************************************
+ *
+ * Summary:
+ * The count flag is set once SysTick counter reaches zero.
+ * The flag cleared on read.
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * Returns non-zero value if counter is set, otherwise zero is returned.
+ *
+ *******************************************************************************/
+ uint32 CySysTickGetCountFlag(void)
+ {
+ return ((CY_SYS_SYST_CSR_REG>>CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickClear
+ ********************************************************************************
+ *
+ * Summary:
+ * Clears the SysTick counter for well-defined startup.
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * None
+ *
+ *******************************************************************************/
+ void CySysTickClear(void)
+ {
+ CY_SYS_SYST_CVR_REG = 0u;
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickSetCallback
+ ********************************************************************************
+ *
+ * Summary:
+ * The function set the pointers to the functions that will be called on
+ * SysTick interrupt.
+ *
+ * Parameters:
+ * number: The number of callback function address to be set.
+ * The valid range is from 0 to 4.
+ * CallbackFunction: Function address.
+ *
+ * Return:
+ * Returns the address of the previous callback function.
+ * The NULL is returned if the specified address in not set.
+ *
+ *******************************************************************************/
+ cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function)
+ {
+ cySysTickCallback retVal;
+
+ retVal = CySysTickCallbacks[number];
+ CySysTickCallbacks[number] = function;
+ return (retVal);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickGetCallback
+ ********************************************************************************
+ *
+ * Summary:
+ * The function get the specified callback pointer.
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * None
+ *
+ *******************************************************************************/
+ cySysTickCallback CySysTickGetCallback(uint32 number)
+ {
+ return ((cySysTickCallback) CySysTickCallbacks[number]);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickServiceCallbacks
+ ********************************************************************************
+ *
+ * Summary:
+ * System Tick timer interrupt routine
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * None
+ *
+ *******************************************************************************/
+ static void CySysTickServiceCallbacks(void)
+ {
+ uint32 i;
+
+ /* Verify that tick timer flag was set */
+ if (1u == CySysTickGetCountFlag())
+ {
+ for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+ {
+ if (CySysTickCallbacks[i] != (void *) 0)
+ {
+ (void)(CySysTickCallbacks[i])();
+ }
+ }
+ }
+ }
+#endif /* (CY_PSOC5) */
+
+
/* [] END OF FILE */
/*******************************************************************************
* File Name: CyLib.h
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides the function definitions for the system, clocking, interrupts and
* Guide provided with PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
void CySetScPumps(uint8 enable) ;
+#if(CY_PSOC5)
+ /* Default interrupt handler */
+ CY_ISR_PROTO(IntDefaultHandler);
+#endif /* (CY_PSOC5) */
+
+#if(CY_PSOC5)
+ /* System tick timer APIs */
+ typedef void (*cySysTickCallback)(void);
+
+ void CySysTickStart(void);
+ void CySysTickInit(void);
+ void CySysTickEnable(void);
+ void CySysTickStop(void);
+ void CySysTickEnableInterrupt(void);
+ void CySysTickDisableInterrupt(void);
+ void CySysTickSetReload(uint32 value);
+ uint32 CySysTickGetReload(void);
+ uint32 CySysTickGetValue(void);
+ cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function);
+ cySysTickCallback CySysTickGetCallback(uint32 number);
+ void CySysTickSetClockSource(uint32 clockSource);
+ uint32 CySysTickGetCountFlag(void);
+ void CySysTickClear(void);
+#endif /* (CY_PSOC5) */
/***************************************
* API Constants
#define CY_ALT_ACT_USB_ENABLED (0x01u)
+#if(CY_PSOC5)
+
+ /***************************************************************************
+ * Instruction Synchronization Barrier flushes the pipeline in the processor,
+ * so that all instructions following the ISB are fetched from cache or
+ * memory, after the instruction has been completed.
+ ***************************************************************************/
+
+ #if defined(__ARMCC_VERSION)
+ #define CY_SYS_ISB __isb(0x0f)
+ #else /* ASM for GCC & IAR */
+ #define CY_SYS_ISB asm volatile ("isb \n")
+ #endif /* (__ARMCC_VERSION) */
+
+#endif /* (CY_PSOC5) */
+
+
/***************************************
* Registers
***************************************/
#define CY_CACHE_CONTROL_REG (* (reg16 *) CYREG_CACHE_CC_CTL )
#define CY_CACHE_CONTROL_PTR ( (reg16 *) CYREG_CACHE_CC_CTL )
+ /* System tick registers */
+ #define CY_SYS_SYST_CSR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CTL)
+ #define CY_SYS_SYST_CSR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CTL)
+
+ #define CY_SYS_SYST_RVR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_RELOAD)
+ #define CY_SYS_SYST_RVR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_RELOAD)
+
+ #define CY_SYS_SYST_CVR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CURRENT)
+ #define CY_SYS_SYST_CVR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CURRENT)
+
+ #define CY_SYS_SYST_CALIB_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CAL)
+ #define CY_SYS_SYST_CALIB_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CAL)
+
#elif (CY_PSOC3)
/* Interrupt Address Vector registers */
#define CY_INT_VECT_TABLE ((cyisraddress CYXDATA *) CYREG_INTC_VECT_MBASE)
- /* Interrrupt Controller Priority Registers */
+ /* Interrupt Controller Priority Registers */
#define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_INTC_PRIOR0)
#define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_INTC_PRIOR0)
- /* Interrrupt Controller Set Enable Registers */
+ /* Interrupt Controller Set Enable Registers */
#define CY_INT_ENABLE_REG (* (reg8 *) CYREG_INTC_SET_EN0)
#define CY_INT_ENABLE_PTR ( (reg8 *) CYREG_INTC_SET_EN0)
#define CY_INT_SET_EN3_REG (* (reg8 *) CYREG_INTC_SET_EN3)
#define CY_INT_SET_EN3_PTR ( (reg8 *) CYREG_INTC_SET_EN3)
- /* Interrrupt Controller Clear Enable Registers */
+ /* Interrupt Controller Clear Enable Registers */
#define CY_INT_CLEAR_REG (* (reg8 *) CYREG_INTC_CLR_EN0)
#define CY_INT_CLEAR_PTR ( (reg8 *) CYREG_INTC_CLR_EN0)
#define CY_INT_CLR_EN3_PTR ( (reg8 *) CYREG_INTC_CLR_EN3)
- /* Interrrupt Controller Set Pend Registers */
+ /* Interrupt Controller Set Pend Registers */
#define CY_INT_SET_PEND_REG (* (reg8 *) CYREG_INTC_SET_PD0)
#define CY_INT_SET_PEND_PTR ( (reg8 *) CYREG_INTC_SET_PD0)
- /* Interrrupt Controller Clear Pend Registers */
+ /* Interrupt Controller Clear Pend Registers */
#define CY_INT_CLR_PEND_REG (* (reg8 *) CYREG_INTC_CLR_PD0)
#define CY_INT_CLR_PEND_PTR ( (reg8 *) CYREG_INTC_CLR_PD0)
* Macro Name: CyAssert
********************************************************************************
* Summary:
-* Macro that evaluates the expression and if it is false (evaluates to 0) then
-* the processor is halted.
+* The macro that evaluates the expression and if it is false (evaluates to 0)
+* then the processor is halted.
*
* This macro is evaluated unless NDEBUG is defined.
*
#define CY_RESET_GPIO1 (0x80u)
-/* Interrrupt Controller Configuration and Status Register */
+/* Interrupt Controller Configuration and Status Register */
#if(CY_PSOC3)
#define INTERRUPT_CSR ((reg8 *) CYREG_INTC_CSR_EN)
#define DISABLE_IRQ_SET ((uint8)(0x01u << 1u)) /* INTC_CSR_EN */
#define CY_CACHE_CONTROL_FLUSH (0x0004u)
#define CY_LIB_RESET_CR2_RESET (0x01u)
+#if(CY_PSOC5)
+ /* System tick API constants */
+ #define CY_SYS_SYST_CSR_ENABLE ((uint32) (0x01u))
+ #define CY_SYS_SYST_CSR_ENABLE_INT ((uint32) (0x02u))
+ #define CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT ((uint32) (0x02u))
+ #define CY_SYS_SYST_CSR_COUNTFLAG_SHIFT ((uint32) (16u))
+ #define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ((uint32) (1u))
+ #define CY_SYS_SYST_CSR_CLK_SRC_LFCLK ((uint32) (0u))
+ #define CY_SYS_SYST_RVR_CNT_MASK ((uint32) (0x00FFFFFFu))
+ #define CY_SYS_SYST_NUM_OF_CALLBACKS ((uint32) (5u))
+#endif /* (CY_PSOC5) */
+
+
/*******************************************************************************
* Interrupt API constants
/* Mask to get valid range of system interrupt 0-15 */
#define CY_INT_SYS_NUMBER_MASK (0xFu)
+#if(CY_PSOC5)
+
+ /* CyIntSetSysVector()/CyIntGetSysVector() - parameter definitions */
+ #define CY_INT_NMI_IRQN ( 2u) /* Non Maskable Interrupt */
+ #define CY_INT_HARD_FAULT_IRQN ( 3u) /* Hard Fault Interrupt */
+ #define CY_INT_MEM_MANAGE_IRQN ( 4u) /* Memory Management Interrupt */
+ #define CY_INT_BUS_FAULT_IRQN ( 5u) /* Bus Fault Interrupt */
+ #define CY_INT_USAGE_FAULT_IRQN ( 6u) /* Usage Fault Interrupt */
+ #define CY_INT_SVCALL_IRQN (11u) /* SV Call Interrupt */
+ #define CY_INT_DEBUG_MONITOR_IRQN (12u) /* Debug Monitor Interrupt */
+ #define CY_INT_PEND_SV_IRQN (14u) /* Pend SV Interrupt */
+ #define CY_INT_SYSTICK_IRQN (15u) /* System Tick Interrupt */
+
+#endif /* (CY_PSOC5) */
/*******************************************************************************
* Interrupt Macros
/*******************************************************************************
-* Following code are OBSOLETE and must not be used.
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+* #ifdef <OBSOLETED_DEFINE>
+* #undef <OBSOLETED_DEFINE>
+* #define <OBSOLETED_DEFINE> (<New Value>)
+* #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+* used in the application and their modification might lead to unexpected
+* consequences.
*******************************************************************************/
+
#define CYGlobalIntEnable CyGlobalIntEnable
#define CYGlobalIntDisable CyGlobalIntDisable
#define cymemset(s,c,n) memset((s),(c),(n))
#define cymemcpy(d,s,n) memcpy((d),(s),(n))
-
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
-*******************************************************************************/
#define MFGCFG_X32_TR_PTR (CY_CLK_XTAL32_TR_PTR)
#define MFGCFG_X32_TR (CY_CLK_XTAL32_TR_REG)
#define SLOWCLK_X32_TST_PTR (CY_CLK_XTAL32_TST_PTR)
#define CY_VD_PRESISTENT_STATUS_PTR (CY_VD_PERSISTENT_STATUS_PTR)
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.20
-*******************************************************************************/
-
#if(CY_PSOC5)
#define CYINT_IRQ_BASE (CY_INT_IRQ_BASE)
#endif /* (CY_PSOC5) */
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
-*******************************************************************************/
+
#define BUS_AMASK_CLEAR (0xF0u)
#define BUS_DMASK_CLEAR (0x00u)
#define CLKDIST_LD_LOAD_SET (0x01u)
#define CLKDIST_CR (*(reg8 *) CYREG_CLKDIST_CR)
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.50
-*******************************************************************************/
#define IMO_PM_ENABLE (0x10u)
#define PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)
#define PM_ACT_CFG0 (*(reg8 *) CYREG_PM_ACT_CFG0)
/*******************************************************************************
* File Name: CySpc.c
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides an API for the System Performance Component.
* application.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Summary:
* Loads a row of data into the row latch of a Flash/EEPROM array.
*
+* The buffer pointer should point to the data that should be written to the
+* flash row directly (no data in ECC/flash will be preserved). It is Flash API
+* responsibility to prepare data: the preserved data are copied from flash into
+* array with the modified data.
+*
* Parameters:
* uint8 array:
* Id of the array.
}
+/*******************************************************************************
+* Function Name: CySpcLoadRowFull
+********************************************************************************
+* Summary:
+* Loads a row of data into the row latch of a Flash/EEPROM array.
+*
+* The only data that are going to be changed should be passed. The function
+* will handle unmodified data preservation based on DWR settings and input
+* parameters.
+*
+* Parameters:
+* uint8 array:
+* Id of the array.
+*
+* uint16 row:
+* Flash row number to be loaded.
+*
+* uint8* buffer:
+* Data to be loaded to the row latch
+*
+* uint8 size:
+* The number of data bytes that the SPC expects to be written. Depends on the
+* type of the array and, if the array is Flash, whether ECC is being enabled
+* or not. There are following values: flash row latch size with ECC enabled,
+* flash row latch size with ECC disabled and EEPROM row latch size.
+*
+* Return:
+* CYRET_STARTED
+* CYRET_CANCELED
+* CYRET_LOCKED
+*
+*******************************************************************************/
+cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\
+
+{
+ cystatus status = CYRET_STARTED;
+ uint16 i;
+
+ #if (CYDEV_ECC_ENABLE == 0)
+ uint32 offset;
+ #endif /* (CYDEV_ECC_ENABLE == 0) */
+
+ /* Make sure the SPC is ready to accept command */
+ if(CY_SPC_IDLE)
+ {
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW);
+ CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW;
+
+ /* Make sure the command was accepted */
+ if(CY_SPC_BUSY)
+ {
+ CY_SPC_CPU_DATA_REG = array;
+
+ /*******************************************************************
+ * If "Enable Error Correcting Code (ECC)" and "Store Configuration
+ * Data in ECC" DWR options are disabled, ECC section is available
+ * for user data.
+ *******************************************************************/
+ #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
+
+ /*******************************************************************
+ * If size parameter equals size of the ECC row and selected array
+ * identification corresponds to the flash array (but not to EEPROM
+ * array) then data are going to be written to the ECC section.
+ * In this case flash data must be preserved. The flash data copied
+ * from flash data section to the SPC data register.
+ *******************************************************************/
+ if ((size == CYDEV_ECC_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))
+ {
+ offset = CYDEV_FLS_BASE +
+ ((uint32) array * CYDEV_FLS_SECTOR_SIZE) +
+ ((uint32) row * CYDEV_FLS_ROW_SIZE );
+
+ for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
+ {
+ CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
+ }
+ }
+
+ #endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */
+
+
+ for(i = 0u; i < size; i++)
+ {
+ CY_SPC_CPU_DATA_REG = buffer[i];
+ }
+
+
+ /*******************************************************************
+ * If "Enable Error Correcting Code (ECC)" DWR option is disabled,
+ * ECC section can be used for storing device configuration data
+ * ("Store Configuration Data in ECC" DWR option is enabled) or for
+ * storing user data in the ECC section ("Store Configuration Data in
+ * ECC" DWR option is enabled). In both cases, the data in the ECC
+ * section must be preserved if flash data is written.
+ *******************************************************************/
+ #if (CYDEV_ECC_ENABLE == 0)
+
+
+ /*******************************************************************
+ * If size parameter equals size of the flash row and selected array
+ * identification corresponds to the flash array (but not to EEPROM
+ * array) then data are going to be written to the flash data
+ * section. In this case, ECC section data must be preserved.
+ * The ECC section data copied from ECC section to the SPC data
+ * register.
+ *******************************************************************/
+ if ((size == CYDEV_FLS_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))
+ {
+ offset = CYDEV_ECC_BASE +
+ ((uint32) array * CYDEV_ECC_SECTOR_SIZE) +
+ ((uint32) row * CYDEV_ECC_ROW_SIZE );
+
+ for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
+ {
+ CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
+ }
+ }
+
+ #else
+
+ if(0u != row)
+ {
+ /* To remove unreferenced local variable warning */
+ }
+
+ #endif /* (CYDEV_ECC_ENABLE == 0) */
+ }
+ else
+ {
+ status = CYRET_CANCELED;
+ }
+ }
+ else
+ {
+ status = CYRET_LOCKED;
+ }
+
+ return(status);
+}
+
+
/*******************************************************************************
* Function Name: CySpcWriteRow
********************************************************************************
}
+/*******************************************************************************
+* Function Name: CySpcGetAlgorithm
+********************************************************************************
+* Summary:
+* Downloads SPC algorithm from SPC SROM into SRAM.
+*
+* Parameters:
+* None
+*
+* Return:
+* CYRET_STARTED
+* CYRET_LOCKED
+*
+*******************************************************************************/
+cystatus CySpcGetAlgorithm(void)
+{
+ cystatus status = CYRET_STARTED;
+
+ /* Make sure the SPC is ready to accept command */
+ if(CY_SPC_IDLE)
+ {
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_DWNLD_ALGORITHM);
+ CY_SPC_CPU_DATA_REG = CY_SPC_CMD_DWNLD_ALGORITHM;
+ }
+ else
+ {
+ status = CYRET_LOCKED;
+ }
+
+ return(status);
+}
+
/* [] END OF FILE */
+
/*******************************************************************************
* File Name: CySpc.c
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides definitions for the System Performance Component API.
* application.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\
;
cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size);
+cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\
+;
cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\
;
cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber);
cystatus CySpcGetTemp(uint8 numSamples);
+cystatus CySpcGetAlgorithm(void);
cystatus CySpcLock(void);
void CySpcUnlock(void);
#define CY_SPC_STATUS_CODE_MASK (0xFCu)
#define CY_SPC_STATUS_CODE_SHIFT (0x02u)
-/* Status codes for the SPC. */
+/* Status codes for SPC. */
#define CY_SPC_STATUS_SUCCESS (0x00u) /* Operation Successful */
#define CY_SPC_STATUS_INVALID_ARRAY_ID (0x01u) /* Invalid Array ID for given command */
#define CY_SPC_STATUS_INVALID_2BYTEKEY (0x02u) /* Invalid 2-byte key */
/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+* #ifdef <OBSOLETED_DEFINE>
+* #undef <OBSOLETED_DEFINE>
+* #define <OBSOLETED_DEFINE> (<New Value>)
+* #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+* used in the application and their modification might lead to unexpected
+* consequences.
*******************************************************************************/
#define FIRST_FLASH_ARRAYID (CY_SPC_FIRST_FLASH_ARRAYID)
#define LAST_FLASH_ARRAYID (CY_SPC_LAST_FLASH_ARRAYID)
/*******************************************************************************
* File Name: Debug_Timer.c
-* Version 2.50
+* Version 2.70
*
* Description:
* The Timer component consists of a 8, 16, 24 or 32-bit timer with
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#endif /* Set Capture Mode for UDB implementation if capture mode is software controlled */
#if (Debug_Timer_SoftwareTriggerMode)
- if (0u == (Debug_Timer_CONTROL & Debug_Timer__B_TIMER__TM_SOFTWARE))
- {
- Debug_Timer_SetTriggerMode(Debug_Timer_INIT_TRIGGER_MODE);
- }
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+ if (0u == (Debug_Timer_CONTROL & Debug_Timer__B_TIMER__TM_SOFTWARE))
+ {
+ Debug_Timer_SetTriggerMode(Debug_Timer_INIT_TRIGGER_MODE);
+ }
+ #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
#endif /* Set trigger mode for UDB Implementation if trigger mode is software controlled */
/* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
#if (Debug_Timer_EnableTriggerMode)
Debug_Timer_EnableTrigger();
#endif /* Set Trigger enable bit for UDB implementation in the control register*/
-
- #if (Debug_Timer_InterruptOnCaptureCount)
- #if (!Debug_Timer_ControlRegRemoved)
- Debug_Timer_SetInterruptCount(Debug_Timer_INIT_INT_CAPTURE_COUNT);
- #endif /* Set interrupt count in control register if control register is not removed */
- #endif /*Set interrupt count in UDB implementation if interrupt count feature is checked.*/
+
+
+ #if (Debug_Timer_InterruptOnCaptureCount && !Debug_Timer_UDB_CONTROL_REG_REMOVED)
+ Debug_Timer_SetInterruptCount(Debug_Timer_INIT_INT_CAPTURE_COUNT);
+ #endif /* Set interrupt count in UDB implementation if interrupt count feature is checked.*/
Debug_Timer_ClearFIFO();
#endif /* Configure additional features of UDB implementation */
#endif /* Set Enable bit for enabling Fixed function timer*/
/* Remove assignment if control register is removed */
- #if (!Debug_Timer_ControlRegRemoved || Debug_Timer_UsingFixedFunction)
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED || Debug_Timer_UsingFixedFunction)
Debug_Timer_CONTROL |= Debug_Timer_CTRL_ENABLE;
#endif /* Remove assignment if control register is removed */
}
void Debug_Timer_Stop(void)
{
/* Disable Timer */
- #if(!Debug_Timer_ControlRegRemoved || Debug_Timer_UsingFixedFunction)
+ #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED || Debug_Timer_UsingFixedFunction)
Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_ENABLE));
#endif /* Remove assignment if control register is removed */
void Debug_Timer_SoftwareCapture(void)
{
/* Generate a software capture by reading the counter register */
- (void)Debug_Timer_COUNTER_LSB;
+ #if(Debug_Timer_UsingFixedFunction)
+ (void)CY_GET_REG16(Debug_Timer_COUNTER_LSB_PTR);
+ #else
+ (void)CY_GET_REG8(Debug_Timer_COUNTER_LSB_PTR_8BIT);
+ #endif/* (Debug_Timer_UsingFixedFunction) */
/* Capture Data is now in the FIFO */
}
}
-#if (!Debug_Timer_ControlRegRemoved) /* Remove API if control register is removed */
+#if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) /* Remove API if control register is unused */
/*******************************************************************************
*******************************************************************************/
uint8 Debug_Timer_ReadControlRegister(void)
{
- return ((uint8)Debug_Timer_CONTROL);
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+ return ((uint8)Debug_Timer_CONTROL);
+ #else
+ return (0);
+ #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
}
*******************************************************************************/
void Debug_Timer_WriteControlRegister(uint8 control)
{
- Debug_Timer_CONTROL = control;
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+ Debug_Timer_CONTROL = control;
+ #else
+ control = 0u;
+ #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
}
-#endif /* Remove API if control register is removed */
+
+#endif /* Remove API if control register is unused */
/*******************************************************************************
* void
*
*******************************************************************************/
-void Debug_Timer_WriteCounter(uint16 counter) \
-
+void Debug_Timer_WriteCounter(uint16 counter)
{
#if(Debug_Timer_UsingFixedFunction)
/* This functionality is removed until a FixedFunction HW update to
*******************************************************************************/
uint16 Debug_Timer_ReadCounter(void)
{
-
/* Force capture by reading Accumulator */
/* Must first do a software capture to be able to read the counter */
/* It is up to the user code to make sure there isn't already captured data in the FIFO */
- (void)Debug_Timer_COUNTER_LSB;
+ #if(Debug_Timer_UsingFixedFunction)
+ (void)CY_GET_REG16(Debug_Timer_COUNTER_LSB_PTR);
+ #else
+ (void)CY_GET_REG8(Debug_Timer_COUNTER_LSB_PTR_8BIT);
+ #endif/* (Debug_Timer_UsingFixedFunction) */
/* Read the data from the FIFO (or capture register for Fixed Function)*/
#if(Debug_Timer_UsingFixedFunction)
#if(!Debug_Timer_UsingFixedFunction) /* UDB Specific Functions */
+
/*******************************************************************************
* The functions below this point are only available using the UDB
* implementation. If a feature is selected, then the API is enabled.
captureMode = ((uint8)((uint8)captureMode << Debug_Timer_CTRL_CAP_MODE_SHIFT));
captureMode &= (Debug_Timer_CTRL_CAP_MODE_MASK);
- /* Clear the Current Setting */
- Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_CAP_MODE_MASK));
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+ /* Clear the Current Setting */
+ Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_CAP_MODE_MASK));
- /* Write The New Setting */
- Debug_Timer_CONTROL |= captureMode;
+ /* Write The New Setting */
+ Debug_Timer_CONTROL |= captureMode;
+ #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
}
#endif /* Remove API if Capture Mode is not Software Controlled */
/* This must only set to two bits of the control register associated */
triggerMode &= Debug_Timer_CTRL_TRIG_MODE_MASK;
- /* Clear the Current Setting */
- Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_MODE_MASK));
-
- /* Write The New Setting */
- Debug_Timer_CONTROL |= (triggerMode | Debug_Timer__B_TIMER__TM_SOFTWARE);
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) /* Remove assignment if control register is removed */
+
+ /* Clear the Current Setting */
+ Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_MODE_MASK));
+ /* Write The New Setting */
+ Debug_Timer_CONTROL |= (triggerMode | Debug_Timer__B_TIMER__TM_SOFTWARE);
+ #endif /* Remove code section if control register is not used */
}
#endif /* Remove API if Trigger Mode is not Software Controlled */
*******************************************************************************/
void Debug_Timer_EnableTrigger(void)
{
- #if (!Debug_Timer_ControlRegRemoved) /* Remove assignment if control register is removed */
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) /* Remove assignment if control register is removed */
Debug_Timer_CONTROL |= Debug_Timer_CTRL_TRIG_EN;
#endif /* Remove code section if control register is not used */
}
*******************************************************************************/
void Debug_Timer_DisableTrigger(void)
{
- #if (!Debug_Timer_ControlRegRemoved) /* Remove assignment if control register is removed */
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED ) /* Remove assignment if control register is removed */
Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_EN));
#endif /* Remove code section if control register is not used */
}
#endif /* Remove API is Trigger Mode is set to None */
-
#if(Debug_Timer_InterruptOnCaptureCount)
-#if (!Debug_Timer_ControlRegRemoved) /* Remove API if control register is removed */
/*******************************************************************************
/* This must only set to two bits of the control register associated */
interruptCount &= Debug_Timer_CTRL_INTCNT_MASK;
- /* Clear the Current Setting */
- Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_INTCNT_MASK));
- /* Write The New Setting */
- Debug_Timer_CONTROL |= interruptCount;
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
+ /* Clear the Current Setting */
+ Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_INTCNT_MASK));
+ /* Write The New Setting */
+ Debug_Timer_CONTROL |= interruptCount;
+ #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
}
-#endif /* Remove API if control register is removed */
#endif /* Debug_Timer_InterruptOnCaptureCount */
/*******************************************************************************
* File Name: Debug_Timer.h
-* Version 2.50
+* Version 2.70
*
* Description:
* Contains the function prototypes and constants available to the timer
* None
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
-#if !defined(CY_Timer_v2_30_Debug_Timer_H)
-#define CY_Timer_v2_30_Debug_Timer_H
+#if !defined(CY_Timer_v2_60_Debug_Timer_H)
+#define CY_Timer_v2_60_Debug_Timer_H
#include "cytypes.h"
#include "cyfitter.h"
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
- #error Component Timer_v2_50 requires cy_boot v3.0 or later
+ #error Component Timer_v2_70 requires cy_boot v3.0 or later
#endif /* (CY_ PSOC5LP) */
#define Debug_Timer_RunModeUsed 0u
#define Debug_Timer_ControlRegRemoved 0u
+#if defined(Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG)
+ #define Debug_Timer_UDB_CONTROL_REG_REMOVED (0u)
+#elif (Debug_Timer_UsingFixedFunction)
+ #define Debug_Timer_UDB_CONTROL_REG_REMOVED (0u)
+#else
+ #define Debug_Timer_UDB_CONTROL_REG_REMOVED (1u)
+#endif /* End Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG */
+
/***************************************
* Type defines
{
uint8 TimerEnableState;
#if(!Debug_Timer_UsingFixedFunction)
- #if (CY_UDB_V0)
- uint16 TimerUdb; /* Timer internal counter value */
- uint16 TimerPeriod; /* Timer Period value */
- uint8 InterruptMaskValue; /* Timer Compare Value */
- #if (Debug_Timer_UsingHWCaptureCounter)
- uint8 TimerCaptureCounter; /* Timer Capture Counter Value */
- #endif /* variable declaration for backing up Capture Counter value*/
- #endif /* variables for non retention registers in CY_UDB_V0 */
-
- #if (CY_UDB_V1)
- uint16 TimerUdb;
- uint8 InterruptMaskValue;
- #if (Debug_Timer_UsingHWCaptureCounter)
- uint8 TimerCaptureCounter;
- #endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */
- #endif /* (CY_UDB_V1) */
-
- #if (!Debug_Timer_ControlRegRemoved)
+
+ uint16 TimerUdb;
+ uint8 InterruptMaskValue;
+ #if (Debug_Timer_UsingHWCaptureCounter)
+ uint8 TimerCaptureCounter;
+ #endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */
+
+ #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED)
uint8 TimerControlRegister;
#endif /* variable declaration for backing up enable state of the Timer */
#endif /* define backup variables only for UDB implementation. Fixed function registers are all retention */
+
}Debug_Timer_backupStruct;
/* Deprecated function. Do not use this in future. Retained for backward compatibility */
#define Debug_Timer_GetInterruptSource() Debug_Timer_ReadStatusRegister()
-#if(!Debug_Timer_ControlRegRemoved)
+#if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
uint8 Debug_Timer_ReadControlRegister(void) ;
- void Debug_Timer_WriteControlRegister(uint8 control) \
- ;
-#endif /* (!Debug_Timer_ControlRegRemoved) */
+ void Debug_Timer_WriteControlRegister(uint8 control) ;
+#endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */
uint16 Debug_Timer_ReadPeriod(void) ;
-void Debug_Timer_WritePeriod(uint16 period) \
- ;
+void Debug_Timer_WritePeriod(uint16 period) ;
uint16 Debug_Timer_ReadCounter(void) ;
-void Debug_Timer_WriteCounter(uint16 counter) \
- ;
+void Debug_Timer_WriteCounter(uint16 counter) ;
uint16 Debug_Timer_ReadCapture(void) ;
void Debug_Timer_SoftwareCapture(void) ;
-
#if(!Debug_Timer_UsingFixedFunction) /* UDB Prototypes */
#if (Debug_Timer_SoftwareCaptureMode)
void Debug_Timer_SetCaptureMode(uint8 captureMode) ;
#if (Debug_Timer_SoftwareTriggerMode)
void Debug_Timer_SetTriggerMode(uint8 triggerMode) ;
#endif /* (Debug_Timer_SoftwareTriggerMode) */
+
#if (Debug_Timer_EnableTriggerMode)
void Debug_Timer_EnableTrigger(void) ;
void Debug_Timer_DisableTrigger(void) ;
#endif /* (Debug_Timer_EnableTriggerMode) */
+
#if(Debug_Timer_InterruptOnCaptureCount)
- #if(!Debug_Timer_ControlRegRemoved)
- void Debug_Timer_SetInterruptCount(uint8 interruptCount) \
- ;
- #endif /* (!Debug_Timer_ControlRegRemoved) */
+ void Debug_Timer_SetInterruptCount(uint8 interruptCount) ;
#endif /* (Debug_Timer_InterruptOnCaptureCount) */
#if (Debug_Timer_UsingHWCaptureCounter)
- void Debug_Timer_SetCaptureCount(uint8 captureCount) \
- ;
+ void Debug_Timer_SetCaptureCount(uint8 captureCount) ;
uint8 Debug_Timer_ReadCaptureCount(void) ;
#endif /* (Debug_Timer_UsingHWCaptureCounter) */
#if (CY_PSOC5A)
/* Use CFG1 Mode bits to set run mode */
/* As defined by Verilog Implementation */
- #define Debug_Timer_CTRL_MODE_SHIFT 0x01u
- #define Debug_Timer_CTRL_MODE_MASK ((uint8)((uint8)0x07u << Debug_Timer_CTRL_MODE_SHIFT))
+ #define Debug_Timer_CTRL_MODE_SHIFT 0x01u
+ #define Debug_Timer_CTRL_MODE_MASK ((uint8)((uint8)0x07u << Debug_Timer_CTRL_MODE_SHIFT))
#endif /* (CY_PSOC5A) */
#if (CY_PSOC3 || CY_PSOC5LP)
/* Control3 Register Bit Locations */
#endif /* CY_PSOC3 || CY_PSOC5 */
#endif
+ #define Debug_Timer_COUNTER_LSB_PTR_8BIT ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG )
+
#if (Debug_Timer_UsingHWCaptureCounter)
#define Debug_Timer_CAP_COUNT (*(reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
#define Debug_Timer_CAP_COUNT_PTR ( (reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG )
/*******************************************************************************
* File Name: Debug_Timer_PM.c
-* Version 2.50
+* Version 2.70
*
* Description:
* This file provides the power management source code to API for the
* None
*
*******************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#include "Debug_Timer.h"
+
static Debug_Timer_backupStruct Debug_Timer_backup;
void Debug_Timer_SaveConfig(void)
{
#if (!Debug_Timer_UsingFixedFunction)
- /* Backup the UDB non-rentention registers for CY_UDB_V0 */
- #if (CY_UDB_V0)
- Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter();
- Debug_Timer_backup.TimerPeriod = Debug_Timer_ReadPeriod();
- Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK;
- #if (Debug_Timer_UsingHWCaptureCounter)
- Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount();
- #endif /* Backup the UDB non-rentention register capture counter for CY_UDB_V0 */
- #endif /* Backup the UDB non-rentention registers for CY_UDB_V0 */
-
- #if (CY_UDB_V1)
- Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter();
- Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK;
- #if (Debug_Timer_UsingHWCaptureCounter)
- Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount();
- #endif /* Back Up capture counter register */
- #endif /* Backup non retention registers, interrupt mask and capture counter for CY_UDB_V1 */
+ Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter();
+ Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK;
+ #if (Debug_Timer_UsingHWCaptureCounter)
+ Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount();
+ #endif /* Back Up capture counter register */
- #if(!Debug_Timer_ControlRegRemoved)
+ #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
Debug_Timer_backup.TimerControlRegister = Debug_Timer_ReadControlRegister();
#endif /* Backup the enable state of the Timer component */
#endif /* Backup non retention registers in UDB implementation. All fixed function registers are retention */
void Debug_Timer_RestoreConfig(void)
{
#if (!Debug_Timer_UsingFixedFunction)
- /* Restore the UDB non-rentention registers for CY_UDB_V0 */
- #if (CY_UDB_V0)
- /* Interrupt State Backup for Critical Region*/
- uint8 Debug_Timer_interruptState;
-
- Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb);
- Debug_Timer_WritePeriod(Debug_Timer_backup.TimerPeriod);
- /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/
- /* Enter Critical Region*/
- Debug_Timer_interruptState = CyEnterCriticalSection();
- /* Use the interrupt output of the status register for IRQ output */
- Debug_Timer_STATUS_AUX_CTRL |= Debug_Timer_STATUS_ACTL_INT_EN_MASK;
- /* Exit Critical Region*/
- CyExitCriticalSection(Debug_Timer_interruptState);
- Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue;
- #if (Debug_Timer_UsingHWCaptureCounter)
- Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter);
- #endif /* Restore the UDB non-rentention register capture counter for CY_UDB_V0 */
- #endif /* Restore the UDB non-rentention registers for CY_UDB_V0 */
- #if (CY_UDB_V1)
- Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb);
- Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue;
- #if (Debug_Timer_UsingHWCaptureCounter)
- Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter);
- #endif /* Restore Capture counter register*/
- #endif /* Restore up non retention registers, interrupt mask and capture counter for CY_UDB_V1 */
+ Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb);
+ Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue;
+ #if (Debug_Timer_UsingHWCaptureCounter)
+ Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter);
+ #endif /* Restore Capture counter register*/
- #if(!Debug_Timer_ControlRegRemoved)
+ #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
Debug_Timer_WriteControlRegister(Debug_Timer_backup.TimerControlRegister);
#endif /* Restore the enable state of the Timer component */
#endif /* Restore non retention registers in the UDB implementation only */
*******************************************************************************/
void Debug_Timer_Sleep(void)
{
- #if(!Debug_Timer_ControlRegRemoved)
+ #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
/* Save Counter's enable state */
if(Debug_Timer_CTRL_ENABLE == (Debug_Timer_CONTROL & Debug_Timer_CTRL_ENABLE))
{
void Debug_Timer_Wakeup(void)
{
Debug_Timer_RestoreConfig();
- #if(!Debug_Timer_ControlRegRemoved)
+ #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED)
if(Debug_Timer_backup.TimerEnableState == 1u)
{ /* Enable Timer's operation */
Debug_Timer_Enable();
/*******************************************************************************
* File Name: EXTLED.c
-* Version 1.90
+* Version 2.10
*
* Description:
* This file contains API to enable firmware control of a Pins component.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Change the drive mode on the pins of the port.
*
* Parameters:
-* mode: Change the pins to this drive mode.
+* mode: Change the pins to one of the following drive modes.
+*
+* EXTLED_DM_STRONG Strong Drive
+* EXTLED_DM_OD_HI Open Drain, Drives High
+* EXTLED_DM_OD_LO Open Drain, Drives Low
+* EXTLED_DM_RES_UP Resistive Pull Up
+* EXTLED_DM_RES_DWN Resistive Pull Down
+* EXTLED_DM_RES_UPDWN Resistive Pull Up/Down
+* EXTLED_DM_DIG_HIZ High Impedance Digital
+* EXTLED_DM_ALG_HIZ High Impedance Analog
*
* Return:
* None
/*******************************************************************************
* File Name: EXTLED.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
/*******************************************************************************
* File Name: EXTLED.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define EXTLED_0 EXTLED__0__PC
+#define EXTLED_0 (EXTLED__0__PC)
#endif /* End Pins EXTLED_ALIASES_H */
/*******************************************************************************
* File Name: LED1.c
-* Version 1.90
+* Version 2.10
*
* Description:
* This file contains API to enable firmware control of a Pins component.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Change the drive mode on the pins of the port.
*
* Parameters:
-* mode: Change the pins to this drive mode.
+* mode: Change the pins to one of the following drive modes.
+*
+* LED1_DM_STRONG Strong Drive
+* LED1_DM_OD_HI Open Drain, Drives High
+* LED1_DM_OD_LO Open Drain, Drives Low
+* LED1_DM_RES_UP Resistive Pull Up
+* LED1_DM_RES_DWN Resistive Pull Down
+* LED1_DM_RES_UPDWN Resistive Pull Up/Down
+* LED1_DM_DIG_HIZ High Impedance Digital
+* LED1_DM_ALG_HIZ High Impedance Analog
*
* Return:
* None
/*******************************************************************************
* File Name: LED1.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
/*******************************************************************************
* File Name: LED1.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define LED1_0 LED1__0__PC
+#define LED1_0 (LED1__0__PC)
#endif /* End Pins LED1_ALIASES_H */
/*******************************************************************************
* File Name: SCSI_CLK.c
-* Version 2.10
+* Version 2.20
*
* Description:
* This file provides the source code to the API for the clock component.
/*******************************************************************************
* File Name: SCSI_CLK.h
-* Version 2.10
+* Version 2.20
*
* Description:
* Provides the function and constant definitions for the clock component.
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
- #error Component cy_clock_v2_10 requires cy_boot v3.0 or later
+ #error Component cy_clock_v2_20 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5LP) */
/*******************************************************************************
* File Name: SCSI_In_DBx.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define SCSI_In_DBx_0 SCSI_In_DBx__0__PC
-#define SCSI_In_DBx_1 SCSI_In_DBx__1__PC
-#define SCSI_In_DBx_2 SCSI_In_DBx__2__PC
-#define SCSI_In_DBx_3 SCSI_In_DBx__3__PC
-#define SCSI_In_DBx_4 SCSI_In_DBx__4__PC
-#define SCSI_In_DBx_5 SCSI_In_DBx__5__PC
-#define SCSI_In_DBx_6 SCSI_In_DBx__6__PC
-#define SCSI_In_DBx_7 SCSI_In_DBx__7__PC
-
-#define SCSI_In_DBx_DB0 SCSI_In_DBx__DB0__PC
-#define SCSI_In_DBx_DB1 SCSI_In_DBx__DB1__PC
-#define SCSI_In_DBx_DB2 SCSI_In_DBx__DB2__PC
-#define SCSI_In_DBx_DB3 SCSI_In_DBx__DB3__PC
-#define SCSI_In_DBx_DB4 SCSI_In_DBx__DB4__PC
-#define SCSI_In_DBx_DB5 SCSI_In_DBx__DB5__PC
-#define SCSI_In_DBx_DB6 SCSI_In_DBx__DB6__PC
-#define SCSI_In_DBx_DB7 SCSI_In_DBx__DB7__PC
+#define SCSI_In_DBx_0 (SCSI_In_DBx__0__PC)
+#define SCSI_In_DBx_1 (SCSI_In_DBx__1__PC)
+#define SCSI_In_DBx_2 (SCSI_In_DBx__2__PC)
+#define SCSI_In_DBx_3 (SCSI_In_DBx__3__PC)
+#define SCSI_In_DBx_4 (SCSI_In_DBx__4__PC)
+#define SCSI_In_DBx_5 (SCSI_In_DBx__5__PC)
+#define SCSI_In_DBx_6 (SCSI_In_DBx__6__PC)
+#define SCSI_In_DBx_7 (SCSI_In_DBx__7__PC)
+
+#define SCSI_In_DBx_DB0 (SCSI_In_DBx__DB0__PC)
+#define SCSI_In_DBx_DB1 (SCSI_In_DBx__DB1__PC)
+#define SCSI_In_DBx_DB2 (SCSI_In_DBx__DB2__PC)
+#define SCSI_In_DBx_DB3 (SCSI_In_DBx__DB3__PC)
+#define SCSI_In_DBx_DB4 (SCSI_In_DBx__DB4__PC)
+#define SCSI_In_DBx_DB5 (SCSI_In_DBx__DB5__PC)
+#define SCSI_In_DBx_DB6 (SCSI_In_DBx__DB6__PC)
+#define SCSI_In_DBx_DB7 (SCSI_In_DBx__DB7__PC)
#endif /* End Pins SCSI_In_DBx_ALIASES_H */
/*******************************************************************************
* File Name: SCSI_In.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define SCSI_In_0 SCSI_In__0__PC
-#define SCSI_In_1 SCSI_In__1__PC
-#define SCSI_In_2 SCSI_In__2__PC
-#define SCSI_In_3 SCSI_In__3__PC
-#define SCSI_In_4 SCSI_In__4__PC
-
-#define SCSI_In_DBP SCSI_In__DBP__PC
-#define SCSI_In_MSG SCSI_In__MSG__PC
-#define SCSI_In_CD SCSI_In__CD__PC
-#define SCSI_In_REQ SCSI_In__REQ__PC
-#define SCSI_In_IO SCSI_In__IO__PC
+#define SCSI_In_0 (SCSI_In__0__PC)
+#define SCSI_In_1 (SCSI_In__1__PC)
+#define SCSI_In_2 (SCSI_In__2__PC)
+#define SCSI_In_3 (SCSI_In__3__PC)
+#define SCSI_In_4 (SCSI_In__4__PC)
+
+#define SCSI_In_DBP (SCSI_In__DBP__PC)
+#define SCSI_In_MSG (SCSI_In__MSG__PC)
+#define SCSI_In_CD (SCSI_In__CD__PC)
+#define SCSI_In_REQ (SCSI_In__REQ__PC)
+#define SCSI_In_IO (SCSI_In__IO__PC)
#endif /* End Pins SCSI_In_ALIASES_H */
/*******************************************************************************
* File Name: SCSI_Noise.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define SCSI_Noise_0 SCSI_Noise__0__PC
-#define SCSI_Noise_1 SCSI_Noise__1__PC
-#define SCSI_Noise_2 SCSI_Noise__2__PC
-#define SCSI_Noise_3 SCSI_Noise__3__PC
-#define SCSI_Noise_4 SCSI_Noise__4__PC
-
-#define SCSI_Noise_ATN SCSI_Noise__ATN__PC
-#define SCSI_Noise_BSY SCSI_Noise__BSY__PC
-#define SCSI_Noise_SEL SCSI_Noise__SEL__PC
-#define SCSI_Noise_RST SCSI_Noise__RST__PC
-#define SCSI_Noise_ACK SCSI_Noise__ACK__PC
+#define SCSI_Noise_0 (SCSI_Noise__0__PC)
+#define SCSI_Noise_1 (SCSI_Noise__1__PC)
+#define SCSI_Noise_2 (SCSI_Noise__2__PC)
+#define SCSI_Noise_3 (SCSI_Noise__3__PC)
+#define SCSI_Noise_4 (SCSI_Noise__4__PC)
+
+#define SCSI_Noise_ATN (SCSI_Noise__ATN__PC)
+#define SCSI_Noise_BSY (SCSI_Noise__BSY__PC)
+#define SCSI_Noise_SEL (SCSI_Noise__SEL__PC)
+#define SCSI_Noise_RST (SCSI_Noise__RST__PC)
+#define SCSI_Noise_ACK (SCSI_Noise__ACK__PC)
#endif /* End Pins SCSI_Noise_ALIASES_H */
/*******************************************************************************
* File Name: SCSI_Out_DBx.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define SCSI_Out_DBx_0 SCSI_Out_DBx__0__PC
-#define SCSI_Out_DBx_1 SCSI_Out_DBx__1__PC
-#define SCSI_Out_DBx_2 SCSI_Out_DBx__2__PC
-#define SCSI_Out_DBx_3 SCSI_Out_DBx__3__PC
-#define SCSI_Out_DBx_4 SCSI_Out_DBx__4__PC
-#define SCSI_Out_DBx_5 SCSI_Out_DBx__5__PC
-#define SCSI_Out_DBx_6 SCSI_Out_DBx__6__PC
-#define SCSI_Out_DBx_7 SCSI_Out_DBx__7__PC
-
-#define SCSI_Out_DBx_DB0 SCSI_Out_DBx__DB0__PC
-#define SCSI_Out_DBx_DB1 SCSI_Out_DBx__DB1__PC
-#define SCSI_Out_DBx_DB2 SCSI_Out_DBx__DB2__PC
-#define SCSI_Out_DBx_DB3 SCSI_Out_DBx__DB3__PC
-#define SCSI_Out_DBx_DB4 SCSI_Out_DBx__DB4__PC
-#define SCSI_Out_DBx_DB5 SCSI_Out_DBx__DB5__PC
-#define SCSI_Out_DBx_DB6 SCSI_Out_DBx__DB6__PC
-#define SCSI_Out_DBx_DB7 SCSI_Out_DBx__DB7__PC
+#define SCSI_Out_DBx_0 (SCSI_Out_DBx__0__PC)
+#define SCSI_Out_DBx_1 (SCSI_Out_DBx__1__PC)
+#define SCSI_Out_DBx_2 (SCSI_Out_DBx__2__PC)
+#define SCSI_Out_DBx_3 (SCSI_Out_DBx__3__PC)
+#define SCSI_Out_DBx_4 (SCSI_Out_DBx__4__PC)
+#define SCSI_Out_DBx_5 (SCSI_Out_DBx__5__PC)
+#define SCSI_Out_DBx_6 (SCSI_Out_DBx__6__PC)
+#define SCSI_Out_DBx_7 (SCSI_Out_DBx__7__PC)
+
+#define SCSI_Out_DBx_DB0 (SCSI_Out_DBx__DB0__PC)
+#define SCSI_Out_DBx_DB1 (SCSI_Out_DBx__DB1__PC)
+#define SCSI_Out_DBx_DB2 (SCSI_Out_DBx__DB2__PC)
+#define SCSI_Out_DBx_DB3 (SCSI_Out_DBx__DB3__PC)
+#define SCSI_Out_DBx_DB4 (SCSI_Out_DBx__DB4__PC)
+#define SCSI_Out_DBx_DB5 (SCSI_Out_DBx__DB5__PC)
+#define SCSI_Out_DBx_DB6 (SCSI_Out_DBx__DB6__PC)
+#define SCSI_Out_DBx_DB7 (SCSI_Out_DBx__DB7__PC)
#endif /* End Pins SCSI_Out_DBx_ALIASES_H */
/*******************************************************************************
* File Name: SCSI_Out.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define SCSI_Out_0 SCSI_Out__0__PC
-#define SCSI_Out_1 SCSI_Out__1__PC
-#define SCSI_Out_2 SCSI_Out__2__PC
-#define SCSI_Out_3 SCSI_Out__3__PC
-#define SCSI_Out_4 SCSI_Out__4__PC
-#define SCSI_Out_5 SCSI_Out__5__PC
-#define SCSI_Out_6 SCSI_Out__6__PC
-#define SCSI_Out_7 SCSI_Out__7__PC
-#define SCSI_Out_8 SCSI_Out__8__PC
-#define SCSI_Out_9 SCSI_Out__9__PC
-
-#define SCSI_Out_DBP_raw SCSI_Out__DBP_raw__PC
-#define SCSI_Out_ATN SCSI_Out__ATN__PC
-#define SCSI_Out_BSY SCSI_Out__BSY__PC
-#define SCSI_Out_ACK SCSI_Out__ACK__PC
-#define SCSI_Out_RST SCSI_Out__RST__PC
-#define SCSI_Out_MSG_raw SCSI_Out__MSG_raw__PC
-#define SCSI_Out_SEL SCSI_Out__SEL__PC
-#define SCSI_Out_CD_raw SCSI_Out__CD_raw__PC
-#define SCSI_Out_REQ SCSI_Out__REQ__PC
-#define SCSI_Out_IO_raw SCSI_Out__IO_raw__PC
+#define SCSI_Out_0 (SCSI_Out__0__PC)
+#define SCSI_Out_1 (SCSI_Out__1__PC)
+#define SCSI_Out_2 (SCSI_Out__2__PC)
+#define SCSI_Out_3 (SCSI_Out__3__PC)
+#define SCSI_Out_4 (SCSI_Out__4__PC)
+#define SCSI_Out_5 (SCSI_Out__5__PC)
+#define SCSI_Out_6 (SCSI_Out__6__PC)
+#define SCSI_Out_7 (SCSI_Out__7__PC)
+#define SCSI_Out_8 (SCSI_Out__8__PC)
+#define SCSI_Out_9 (SCSI_Out__9__PC)
+
+#define SCSI_Out_DBP_raw (SCSI_Out__DBP_raw__PC)
+#define SCSI_Out_ATN (SCSI_Out__ATN__PC)
+#define SCSI_Out_BSY (SCSI_Out__BSY__PC)
+#define SCSI_Out_ACK (SCSI_Out__ACK__PC)
+#define SCSI_Out_RST (SCSI_Out__RST__PC)
+#define SCSI_Out_MSG_raw (SCSI_Out__MSG_raw__PC)
+#define SCSI_Out_SEL (SCSI_Out__SEL__PC)
+#define SCSI_Out_CD_raw (SCSI_Out__CD_raw__PC)
+#define SCSI_Out_REQ (SCSI_Out__REQ__PC)
+#define SCSI_Out_IO_raw (SCSI_Out__IO_raw__PC)
#endif /* End Pins SCSI_Out_ALIASES_H */
/*******************************************************************************
* File Name: SD_CD.c
-* Version 1.90
+* Version 2.10
*
* Description:
* This file contains API to enable firmware control of a Pins component.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Change the drive mode on the pins of the port.
*
* Parameters:
-* mode: Change the pins to this drive mode.
+* mode: Change the pins to one of the following drive modes.
+*
+* SD_CD_DM_STRONG Strong Drive
+* SD_CD_DM_OD_HI Open Drain, Drives High
+* SD_CD_DM_OD_LO Open Drain, Drives Low
+* SD_CD_DM_RES_UP Resistive Pull Up
+* SD_CD_DM_RES_DWN Resistive Pull Down
+* SD_CD_DM_RES_UPDWN Resistive Pull Up/Down
+* SD_CD_DM_DIG_HIZ High Impedance Digital
+* SD_CD_DM_ALG_HIZ High Impedance Analog
*
* Return:
* None
/*******************************************************************************
* File Name: SD_CD.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
/*******************************************************************************
* File Name: SD_CD.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define SD_CD_0 SD_CD__0__PC
+#define SD_CD_0 (SD_CD__0__PC)
#endif /* End Pins SD_CD_ALIASES_H */
/*******************************************************************************
* File Name: SD_CS.c
-* Version 1.90
+* Version 2.10
*
* Description:
* This file contains API to enable firmware control of a Pins component.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Change the drive mode on the pins of the port.
*
* Parameters:
-* mode: Change the pins to this drive mode.
+* mode: Change the pins to one of the following drive modes.
+*
+* SD_CS_DM_STRONG Strong Drive
+* SD_CS_DM_OD_HI Open Drain, Drives High
+* SD_CS_DM_OD_LO Open Drain, Drives Low
+* SD_CS_DM_RES_UP Resistive Pull Up
+* SD_CS_DM_RES_DWN Resistive Pull Down
+* SD_CS_DM_RES_UPDWN Resistive Pull Up/Down
+* SD_CS_DM_DIG_HIZ High Impedance Digital
+* SD_CS_DM_ALG_HIZ High Impedance Analog
*
* Return:
* None
/*******************************************************************************
* File Name: SD_CS.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
/*******************************************************************************
* File Name: SD_CS.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define SD_CS_0 SD_CS__0__PC
+#define SD_CS_0 (SD_CS__0__PC)
#endif /* End Pins SD_CS_ALIASES_H */
/*******************************************************************************
* File Name: SD_Data_Clk.c
-* Version 2.10
+* Version 2.20
*
* Description:
* This file provides the source code to the API for the clock component.
/*******************************************************************************
* File Name: SD_Data_Clk.h
-* Version 2.10
+* Version 2.20
*
* Description:
* Provides the function and constant definitions for the clock component.
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
- #error Component cy_clock_v2_10 requires cy_boot v3.0 or later
+ #error Component cy_clock_v2_20 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5LP) */
/*******************************************************************************
* File Name: SD_MISO.c
-* Version 1.90
+* Version 2.10
*
* Description:
* This file contains API to enable firmware control of a Pins component.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Change the drive mode on the pins of the port.
*
* Parameters:
-* mode: Change the pins to this drive mode.
+* mode: Change the pins to one of the following drive modes.
+*
+* SD_MISO_DM_STRONG Strong Drive
+* SD_MISO_DM_OD_HI Open Drain, Drives High
+* SD_MISO_DM_OD_LO Open Drain, Drives Low
+* SD_MISO_DM_RES_UP Resistive Pull Up
+* SD_MISO_DM_RES_DWN Resistive Pull Down
+* SD_MISO_DM_RES_UPDWN Resistive Pull Up/Down
+* SD_MISO_DM_DIG_HIZ High Impedance Digital
+* SD_MISO_DM_ALG_HIZ High Impedance Analog
*
* Return:
* None
/*******************************************************************************
* File Name: SD_MISO.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
/*******************************************************************************
* File Name: SD_MISO.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define SD_MISO_0 SD_MISO__0__PC
+#define SD_MISO_0 (SD_MISO__0__PC)
#endif /* End Pins SD_MISO_ALIASES_H */
/*******************************************************************************
* File Name: SD_MOSI.c
-* Version 1.90
+* Version 2.10
*
* Description:
* This file contains API to enable firmware control of a Pins component.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Change the drive mode on the pins of the port.
*
* Parameters:
-* mode: Change the pins to this drive mode.
+* mode: Change the pins to one of the following drive modes.
+*
+* SD_MOSI_DM_STRONG Strong Drive
+* SD_MOSI_DM_OD_HI Open Drain, Drives High
+* SD_MOSI_DM_OD_LO Open Drain, Drives Low
+* SD_MOSI_DM_RES_UP Resistive Pull Up
+* SD_MOSI_DM_RES_DWN Resistive Pull Down
+* SD_MOSI_DM_RES_UPDWN Resistive Pull Up/Down
+* SD_MOSI_DM_DIG_HIZ High Impedance Digital
+* SD_MOSI_DM_ALG_HIZ High Impedance Analog
*
* Return:
* None
/*******************************************************************************
* File Name: SD_MOSI.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
/*******************************************************************************
* File Name: SD_MOSI.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define SD_MOSI_0 SD_MOSI__0__PC
+#define SD_MOSI_0 (SD_MOSI__0__PC)
#endif /* End Pins SD_MOSI_ALIASES_H */
/*******************************************************************************
* File Name: SD_SCK.c
-* Version 1.90
+* Version 2.10
*
* Description:
* This file contains API to enable firmware control of a Pins component.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Change the drive mode on the pins of the port.
*
* Parameters:
-* mode: Change the pins to this drive mode.
+* mode: Change the pins to one of the following drive modes.
+*
+* SD_SCK_DM_STRONG Strong Drive
+* SD_SCK_DM_OD_HI Open Drain, Drives High
+* SD_SCK_DM_OD_LO Open Drain, Drives Low
+* SD_SCK_DM_RES_UP Resistive Pull Up
+* SD_SCK_DM_RES_DWN Resistive Pull Down
+* SD_SCK_DM_RES_UPDWN Resistive Pull Up/Down
+* SD_SCK_DM_DIG_HIZ High Impedance Digital
+* SD_SCK_DM_ALG_HIZ High Impedance Analog
*
* Return:
* None
/*******************************************************************************
* File Name: SD_SCK.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
/*******************************************************************************
* File Name: SD_SCK.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define SD_SCK_0 SD_SCK__0__PC
+#define SD_SCK_0 (SD_SCK__0__PC)
#endif /* End Pins SD_SCK_ALIASES_H */
/*******************************************************************************
* File Name: USBFS.c
-* Version 2.60
+* Version 2.80
*
* Description:
* API for USBFS Component.
* registers are indexed by variations of epNumber - 1.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "USBFS_hid.h"
#if(USBFS_DMA1_REMOVE == 0u)
#include "USBFS_ep1_dma.h"
-#endif /* End USBFS_DMA1_REMOVE */
+#endif /* USBFS_DMA1_REMOVE */
#if(USBFS_DMA2_REMOVE == 0u)
#include "USBFS_ep2_dma.h"
-#endif /* End USBFS_DMA2_REMOVE */
+#endif /* USBFS_DMA2_REMOVE */
#if(USBFS_DMA3_REMOVE == 0u)
#include "USBFS_ep3_dma.h"
-#endif /* End USBFS_DMA3_REMOVE */
+#endif /* USBFS_DMA3_REMOVE */
#if(USBFS_DMA4_REMOVE == 0u)
#include "USBFS_ep4_dma.h"
-#endif /* End USBFS_DMA4_REMOVE */
+#endif /* USBFS_DMA4_REMOVE */
#if(USBFS_DMA5_REMOVE == 0u)
#include "USBFS_ep5_dma.h"
-#endif /* End USBFS_DMA5_REMOVE */
+#endif /* USBFS_DMA5_REMOVE */
#if(USBFS_DMA6_REMOVE == 0u)
#include "USBFS_ep6_dma.h"
-#endif /* End USBFS_DMA6_REMOVE */
+#endif /* USBFS_DMA6_REMOVE */
#if(USBFS_DMA7_REMOVE == 0u)
#include "USBFS_ep7_dma.h"
-#endif /* End USBFS_DMA7_REMOVE */
+#endif /* USBFS_DMA7_REMOVE */
#if(USBFS_DMA8_REMOVE == 0u)
#include "USBFS_ep8_dma.h"
-#endif /* End USBFS_DMA8_REMOVE */
+#endif /* USBFS_DMA8_REMOVE */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ #include "USBFS_EP_DMA_Done_isr.h"
+ #include "USBFS_EP8_DMA_Done_SR.h"
+ #include "USBFS_EP17_DMA_Done_SR.h"
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
/***************************************
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
uint8 USBFS_DmaChan[USBFS_MAX_EP];
uint8 USBFS_DmaTd[USBFS_MAX_EP];
-#endif /* End USBFS_EP_MM */
+#endif /* USBFS_EP_MM */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ static uint8 clearInDataRdyStatus = USBFS_ARB_EPX_CFG_DEFAULT;
+ uint8 USBFS_DmaNextTd[USBFS_MAX_EP];
+ const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP] =
+ { 0u,
+ USBFS_ep1_TD_TERMOUT_EN,
+ USBFS_ep2_TD_TERMOUT_EN,
+ USBFS_ep3_TD_TERMOUT_EN,
+ USBFS_ep4_TD_TERMOUT_EN,
+ USBFS_ep5_TD_TERMOUT_EN,
+ USBFS_ep6_TD_TERMOUT_EN,
+ USBFS_ep7_TD_TERMOUT_EN,
+ USBFS_ep8_TD_TERMOUT_EN
+ };
+ volatile uint16 USBFS_inLength[USBFS_MAX_EP];
+ const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];
+ volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
/*******************************************************************************
uint8 enableInterrupts;
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
uint16 i;
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
enableInterrupts = CyEnterCriticalSection();
for (i = 0u; i < USBFS_MAX_EP; i++)
{
USBFS_DmaTd[i] = DMA_INVALID_TD;
+ #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ USBFS_DmaNextTd[i] = DMA_INVALID_TD;
+ #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
}
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
CyExitCriticalSection(enableInterrupts);
#if(USBFS_SOF_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBFS_SOF_VECT_NUM, &USBFS_SOF_ISR);
CyIntSetPriority(USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR);
- #endif /* End USBFS_SOF_ISR_REMOVE */
+ #endif /* USBFS_SOF_ISR_REMOVE */
/* Set the Control Endpoint Interrupt. */
(void) CyIntSetVector(USBFS_EP_0_VECT_NUM, &USBFS_EP_0_ISR);
#if(USBFS_EP1_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBFS_EP_1_VECT_NUM, &USBFS_EP_1_ISR);
CyIntSetPriority(USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR);
- #endif /* End USBFS_EP1_ISR_REMOVE */
+ #endif /* USBFS_EP1_ISR_REMOVE */
/* Set the Data Endpoint 2 Interrupt. */
#if(USBFS_EP2_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBFS_EP_2_VECT_NUM, &USBFS_EP_2_ISR);
CyIntSetPriority(USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR);
- #endif /* End USBFS_EP2_ISR_REMOVE */
+ #endif /* USBFS_EP2_ISR_REMOVE */
/* Set the Data Endpoint 3 Interrupt. */
#if(USBFS_EP3_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBFS_EP_3_VECT_NUM, &USBFS_EP_3_ISR);
CyIntSetPriority(USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR);
- #endif /* End USBFS_EP3_ISR_REMOVE */
+ #endif /* USBFS_EP3_ISR_REMOVE */
/* Set the Data Endpoint 4 Interrupt. */
#if(USBFS_EP4_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBFS_EP_4_VECT_NUM, &USBFS_EP_4_ISR);
CyIntSetPriority(USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR);
- #endif /* End USBFS_EP4_ISR_REMOVE */
+ #endif /* USBFS_EP4_ISR_REMOVE */
/* Set the Data Endpoint 5 Interrupt. */
#if(USBFS_EP5_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBFS_EP_5_VECT_NUM, &USBFS_EP_5_ISR);
CyIntSetPriority(USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR);
- #endif /* End USBFS_EP5_ISR_REMOVE */
+ #endif /* USBFS_EP5_ISR_REMOVE */
/* Set the Data Endpoint 6 Interrupt. */
#if(USBFS_EP6_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBFS_EP_6_VECT_NUM, &USBFS_EP_6_ISR);
CyIntSetPriority(USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR);
- #endif /* End USBFS_EP6_ISR_REMOVE */
+ #endif /* USBFS_EP6_ISR_REMOVE */
/* Set the Data Endpoint 7 Interrupt. */
#if(USBFS_EP7_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBFS_EP_7_VECT_NUM, &USBFS_EP_7_ISR);
CyIntSetPriority(USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR);
- #endif /* End USBFS_EP7_ISR_REMOVE */
+ #endif /* USBFS_EP7_ISR_REMOVE */
/* Set the Data Endpoint 8 Interrupt. */
#if(USBFS_EP8_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBFS_EP_8_VECT_NUM, &USBFS_EP_8_ISR);
CyIntSetPriority(USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR);
- #endif /* End USBFS_EP8_ISR_REMOVE */
+ #endif /* USBFS_EP8_ISR_REMOVE */
#if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))
/* Set the ARB Interrupt. */
(void) CyIntSetVector(USBFS_ARB_VECT_NUM, &USBFS_ARB_ISR);
CyIntSetPriority(USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR);
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
}
CyIntEnable(USBFS_EP_0_VECT_NUM);
#if(USBFS_EP1_ISR_REMOVE == 0u)
CyIntEnable(USBFS_EP_1_VECT_NUM);
- #endif /* End USBFS_EP1_ISR_REMOVE */
+ #endif /* USBFS_EP1_ISR_REMOVE */
#if(USBFS_EP2_ISR_REMOVE == 0u)
CyIntEnable(USBFS_EP_2_VECT_NUM);
- #endif /* End USBFS_EP2_ISR_REMOVE */
+ #endif /* USBFS_EP2_ISR_REMOVE */
#if(USBFS_EP3_ISR_REMOVE == 0u)
CyIntEnable(USBFS_EP_3_VECT_NUM);
- #endif /* End USBFS_EP3_ISR_REMOVE */
+ #endif /* USBFS_EP3_ISR_REMOVE */
#if(USBFS_EP4_ISR_REMOVE == 0u)
CyIntEnable(USBFS_EP_4_VECT_NUM);
- #endif /* End USBFS_EP4_ISR_REMOVE */
+ #endif /* USBFS_EP4_ISR_REMOVE */
#if(USBFS_EP5_ISR_REMOVE == 0u)
CyIntEnable(USBFS_EP_5_VECT_NUM);
- #endif /* End USBFS_EP5_ISR_REMOVE */
+ #endif /* USBFS_EP5_ISR_REMOVE */
#if(USBFS_EP6_ISR_REMOVE == 0u)
CyIntEnable(USBFS_EP_6_VECT_NUM);
- #endif /* End USBFS_EP6_ISR_REMOVE */
+ #endif /* USBFS_EP6_ISR_REMOVE */
#if(USBFS_EP7_ISR_REMOVE == 0u)
CyIntEnable(USBFS_EP_7_VECT_NUM);
- #endif /* End USBFS_EP7_ISR_REMOVE */
+ #endif /* USBFS_EP7_ISR_REMOVE */
#if(USBFS_EP8_ISR_REMOVE == 0u)
CyIntEnable(USBFS_EP_8_VECT_NUM);
- #endif /* End USBFS_EP8_ISR_REMOVE */
+ #endif /* USBFS_EP8_ISR_REMOVE */
#if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))
/* usb arb interrupt enable */
USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;
CyIntEnable(USBFS_ARB_VECT_NUM);
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
/* Arbiter configuration for DMA transfers */
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
-
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
/*Set cfg cmplt this rises DMA request when the full configuration is done */
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+ #if(USBFS_EP_DMA_AUTO_OPT == 0u)
+ /* Init interrupt which handles verification of the successful DMA transaction */
+ USBFS_EP_DMA_Done_isr_StartEx(&USBFS_EP_DMA_DONE_ISR);
+ USBFS_EP17_DMA_Done_SR_InterruptEnable();
+ USBFS_EP8_DMA_Done_SR_InterruptEnable();
+ #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
USBFS_transferState = USBFS_TRANS_STATE_IDLE;
USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;
#else
USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE;
- #endif /* End USBFS_VDDD_MV < USBFS_3500MV */
+ #endif /* USBFS_VDDD_MV < USBFS_3500MV */
break;
}
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
/* Disable the SIE */
USBFS_CR0_REG &= (uint8)(~USBFS_CR0_ENABLE);
CyIntDisable(USBFS_EP_0_VECT_NUM);
#if(USBFS_EP1_ISR_REMOVE == 0u)
CyIntDisable(USBFS_EP_1_VECT_NUM);
- #endif /* End USBFS_EP1_ISR_REMOVE */
+ #endif /* USBFS_EP1_ISR_REMOVE */
#if(USBFS_EP2_ISR_REMOVE == 0u)
CyIntDisable(USBFS_EP_2_VECT_NUM);
- #endif /* End USBFS_EP2_ISR_REMOVE */
+ #endif /* USBFS_EP2_ISR_REMOVE */
#if(USBFS_EP3_ISR_REMOVE == 0u)
CyIntDisable(USBFS_EP_3_VECT_NUM);
- #endif /* End USBFS_EP3_ISR_REMOVE */
+ #endif /* USBFS_EP3_ISR_REMOVE */
#if(USBFS_EP4_ISR_REMOVE == 0u)
CyIntDisable(USBFS_EP_4_VECT_NUM);
- #endif /* End USBFS_EP4_ISR_REMOVE */
+ #endif /* USBFS_EP4_ISR_REMOVE */
#if(USBFS_EP5_ISR_REMOVE == 0u)
CyIntDisable(USBFS_EP_5_VECT_NUM);
- #endif /* End USBFS_EP5_ISR_REMOVE */
+ #endif /* USBFS_EP5_ISR_REMOVE */
#if(USBFS_EP6_ISR_REMOVE == 0u)
CyIntDisable(USBFS_EP_6_VECT_NUM);
- #endif /* End USBFS_EP6_ISR_REMOVE */
+ #endif /* USBFS_EP6_ISR_REMOVE */
#if(USBFS_EP7_ISR_REMOVE == 0u)
CyIntDisable(USBFS_EP_7_VECT_NUM);
- #endif /* End USBFS_EP7_ISR_REMOVE */
+ #endif /* USBFS_EP7_ISR_REMOVE */
#if(USBFS_EP8_ISR_REMOVE == 0u)
CyIntDisable(USBFS_EP_8_VECT_NUM);
- #endif /* End USBFS_EP8_ISR_REMOVE */
+ #endif /* USBFS_EP8_ISR_REMOVE */
/* Clear all of the component data */
USBFS_configuration = 0u;
* No.
*
*******************************************************************************/
- void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData)
+ void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)
{
uint16 src;
src = HI16(CYDEV_PERIPH_BASE);
dst = HI16(pData);
}
- #endif /* End C51 */
+ #endif /* C51 */
switch(epNumber)
{
case USBFS_EP1:
#if(USBFS_DMA1_REMOVE == 0u)
USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize(
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
- #endif /* End USBFS_DMA1_REMOVE */
+ #endif /* USBFS_DMA1_REMOVE */
break;
case USBFS_EP2:
#if(USBFS_DMA2_REMOVE == 0u)
USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize(
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
- #endif /* End USBFS_DMA2_REMOVE */
+ #endif /* USBFS_DMA2_REMOVE */
break;
case USBFS_EP3:
#if(USBFS_DMA3_REMOVE == 0u)
USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize(
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
- #endif /* End USBFS_DMA3_REMOVE */
+ #endif /* USBFS_DMA3_REMOVE */
break;
case USBFS_EP4:
#if(USBFS_DMA4_REMOVE == 0u)
USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize(
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
- #endif /* End USBFS_DMA4_REMOVE */
+ #endif /* USBFS_DMA4_REMOVE */
break;
case USBFS_EP5:
#if(USBFS_DMA5_REMOVE == 0u)
USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize(
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
- #endif /* End USBFS_DMA5_REMOVE */
+ #endif /* USBFS_DMA5_REMOVE */
break;
case USBFS_EP6:
#if(USBFS_DMA6_REMOVE == 0u)
USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize(
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
- #endif /* End USBFS_DMA6_REMOVE */
+ #endif /* USBFS_DMA6_REMOVE */
break;
case USBFS_EP7:
#if(USBFS_DMA7_REMOVE == 0u)
USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize(
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
- #endif /* End USBFS_DMA7_REMOVE */
+ #endif /* USBFS_DMA7_REMOVE */
break;
case USBFS_EP8:
#if(USBFS_DMA8_REMOVE == 0u)
USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize(
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
- #endif /* End USBFS_DMA8_REMOVE */
+ #endif /* USBFS_DMA8_REMOVE */
break;
default:
/* Do not support EP0 DMA transfers */
if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
{
USBFS_DmaTd[epNumber] = CyDmaTdAllocate();
+ #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ USBFS_DmaNextTd[epNumber] = CyDmaTdAllocate();
+ #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
+
}
}
CyDmaTdFree(USBFS_DmaTd[i]);
USBFS_DmaTd[i] = DMA_INVALID_TD;
}
+ #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ if(USBFS_DmaNextTd[i] != DMA_INVALID_TD)
+ {
+ CyDmaTdFree(USBFS_DmaNextTd[i]);
+ USBFS_DmaNextTd[i] = DMA_INVALID_TD;
+ }
+ #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
i++;
}while((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP));
}
-#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+#endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
+
+
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+
+
+ /*******************************************************************************
+ * Function Name: USBFS_LoadNextInEP
+ ********************************************************************************
+ *
+ * Summary:
+ * This internal function is used for IN endpoint DMA reconfiguration in
+ * Auto DMA mode.
+ *
+ * Parameters:
+ * epNumber: Contains the data endpoint number.
+ * mode: 0 - Configure DMA to send the the rest of data.
+ * 1 - Configure DMA to repeat 2 last bytes of the first burst.
+ *
+ * Return:
+ * None.
+ *
+ *******************************************************************************/
+ void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode)
+ {
+ reg16 *convert;
+
+ if(mode == 0u)
+ {
+ /* Configure DMA to send the the rest of data */
+ /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];
+ /* Set transfer length */
+ CY_SET_REG16(convert, USBFS_inLength[epNumber] - USBFS_DMA_BYTES_PER_BURST);
+ /* CyDmaTdSetAddress API is optimized to change only source address */
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];
+ CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] +
+ USBFS_DMA_BYTES_PER_BURST));
+ USBFS_inBufFull[epNumber] = 1u;
+ }
+ else
+ {
+ /* Configure DMA to repeat 2 last bytes of the first burst. */
+ /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];
+ /* Set transfer length */
+ CY_SET_REG16(convert, USBFS_DMA_BYTES_REPEAT);
+ /* CyDmaTdSetAddress API is optimized to change only source address */
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];
+ CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] +
+ USBFS_DMA_BYTES_PER_BURST - USBFS_DMA_BYTES_REPEAT));
+ }
+
+ /* CyDmaChSetInitialTd API is optimised to init TD */
+ CY_DMA_CH_STRUCT_PTR[USBFS_DmaChan[epNumber]].basic_status[1u] = USBFS_DmaTd[epNumber];
+ }
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
/*******************************************************************************
********************************************************************************
*
* Summary:
-* Loads and enables the specified USB data endpoint for an IN interrupt or bulk
-* transfer.
+* Loads and enables the specified USB data endpoint for an IN transfer.
*
* Parameters:
* epNumber: Contains the data endpoint number.
reg8 *p;
#if(USBFS_EP_MM == USBFS__EP_MANUAL)
uint16 i;
- #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */
if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
{
{
length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset;
}
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */
/* Set the count and data toggle */
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri),
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
#else
/* Init DMA if it was not initialized */
- if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD)
+ if (USBFS_DmaTd[epNumber] == DMA_INVALID_TD)
{
USBFS_InitEP_DMA(epNumber, pData);
}
- #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
- if((pData != NULL) && (length > 0u))
+ if ((pData != NULL) && (length > 0u))
{
/* Enable DMA in mode2 for transferring data */
(void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
/* When zero-length packet - write the Mode register directly */
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
}
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
- if(pData != NULL)
+ if (pData != NULL)
{
/* Enable DMA in mode3 for transferring data */
(void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)
+ USBFS_inLength[epNumber] = length;
+ USBFS_inDataPointer[epNumber] = pData;
+ /* Configure DMA to send the data only for the first burst */
+ (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber],
+ (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length,
+ USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));
+ /* The second TD will be executed only when the first one fails.
+ * The intention of this TD is to generate NRQ interrupt
+ * and repeat 2 last bytes of the first burst.
+ */
+ (void) CyDmaTdSetConfiguration(USBFS_DmaNextTd[epNumber], 1u,
+ USBFS_DmaNextTd[epNumber],
+ USBFS_epX_TD_TERMOUT_EN[epNumber]);
+ /* Configure DmaNextTd to clear Data ready status */
+ (void) CyDmaTdSetAddress(USBFS_DmaNextTd[epNumber], LO16((uint32)&clearInDataRdyStatus),
+ LO16((uint32)(USBFS_ARB_EP1_CFG_IND + ri)));
+ #else /* Configure DMA to send all data*/
(void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length,
USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);
(void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));
+ #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */
+
/* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
(void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);
/* Enable the DMA */
USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
if(length > 0u)
{
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)
+ USBFS_inLength[epNumber] = length;
+ USBFS_inBufFull[epNumber] = 0u;
+ (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
+ /* Configure DMA to send the data only for the first burst */
+ (void) CyDmaTdSetConfiguration(
+ USBFS_DmaTd[epNumber], (length > USBFS_DMA_BYTES_PER_BURST) ?
+ USBFS_DMA_BYTES_PER_BURST : length,
+ USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR );
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],
+ LO16((uint32)USBFS_inDataPointer[epNumber]), LO16((uint32)p));
+ /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
+ (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);
+ /* Enable the DMA */
+ (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
+ (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
+ #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */
+
/* Set Data ready status, This will generate DMA request */
- * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+ #ifndef USBFS_MANUAL_IN_EP_ARM
+ * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+ #endif /* USBFS_MANUAL_IN_EP_ARM */
/* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */
}
else
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
}
}
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
-
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
}
}
reg8 *p;
#if(USBFS_EP_MM == USBFS__EP_MANUAL)
uint16 i;
- #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */
#if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
uint16 xferCount;
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */
if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL))
{
{
length = xferCount;
}
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */
#if(USBFS_EP_MM == USBFS__EP_MANUAL)
/* Copy the data using the arbiter data register */
{
USBFS_InitEP_DMA(epNumber, pData);
}
- #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+
+ #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
/* Enable DMA in mode2 for transferring data */
* (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ;
* (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ));
/* Out EP will be (re)armed in arb ISR after transfer complete */
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
/* Enable DMA in mode3 for transferring data */
(void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
(void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
/* Out EP will be (re)armed in arb ISR after transfer complete */
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
}
else
/*******************************************************************************
* File Name: USBFS.h
-* Version 2.60
+* Version 2.80
*
* Description:
-* Header File for the USFS component. Contains prototypes and constant values.
+* Header File for the USBFS component. Contains prototypes and constant values.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "cyfitter.h"
#include "CyLib.h"
+/* User supplied definitions. */
+/* `#START USER_DEFINITIONS` Place your declaration here */
+
+/* `#END` */
+
/***************************************
* Conditional Compilation Parameters
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
- #error Component USBFS_v2_60 requires cy_boot v3.0 or later
+ #error Component USBFS_v2_80 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5LP) */
#else
#define USBFS_DATA
#define USBFS_XDATA
-#endif /* End __C51__ */
+#endif /* __C51__ */
#define USBFS_NULL NULL
#define USBFS_EP8_ISR_REMOVE (1u)
#define USBFS_EP_MM (0u)
#define USBFS_EP_MA (0u)
+#define USBFS_EP_DMA_AUTO_OPT (0u)
#define USBFS_DMA1_REMOVE (1u)
#define USBFS_DMA2_REMOVE (1u)
#define USBFS_DMA3_REMOVE (1u)
#endif /* USBFS_ENABLE_FWSN_STRING */
#if (USBFS_MON_VBUS == 1u)
uint8 USBFS_VBusPresent(void) ;
-#endif /* End USBFS_MON_VBUS */
+#endif /* USBFS_MON_VBUS */
#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \
(CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))
void USBFS_CyBtldrCommStart(void) ;
void USBFS_CyBtldrCommStop(void) ;
void USBFS_CyBtldrCommReset(void) ;
- cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+ cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
;
- cystatus USBFS_CyBtldrCommRead( uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+ cystatus USBFS_CyBtldrCommRead (uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
;
- #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* EP 1 OUT */
- #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* EP 2 IN */
- #define USBFS_BTLDR_MAX_PACKET_SIZE USBFS_BTLDR_SIZEOF_WRITE_BUFFER
+ #define USBFS_BTLDR_OUT_EP (0x01u)
+ #define USBFS_BTLDR_IN_EP (0x02u)
+
+ #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* EP 1 OUT */
+ #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* EP 2 IN */
+ #define USBFS_BTLDR_MAX_PACKET_SIZE USBFS_BTLDR_SIZEOF_WRITE_BUFFER
+
+ #define USBFS_BTLDR_WAIT_1_MS (1u) /* Time Out quantity equal 1mS */
/* These defines active if used USBFS interface as an
* IO Component for bootloading. When Custom_Interface selected
* in Bootloder configuration as the IO Component, user must
- * provide these functions
+ * provide these functions.
*/
#if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS)
#define CyBtldrCommStart USBFS_CyBtldrCommStart
#define CyBtldrCommRead USBFS_CyBtldrCommRead
#endif /*End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
-#endif /* End CYDEV_BOOTLOADER_IO_COMP */
+#endif /* CYDEV_BOOTLOADER_IO_COMP */
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
- void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData)
+ void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)
;
void USBFS_Stop_DMA(uint8 epNumber) ;
-#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL) */
+#endif /* USBFS_EP_MM != USBFS__EP_MANUAL) */
#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)
void USBFS_MIDI_EP_Init(void) ;
void USBFS_MIDI_OUT_EP_Service(void) ;
#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
-#endif /* End USBFS_ENABLE_MIDI_API != 0u */
+#endif /* USBFS_ENABLE_MIDI_API != 0u */
/* Renamed Functions for backward compatibility.
* Should not be used in new designs.
#define USBFS_EP_USAGE_TYPE_RESERVED (0x30u)
#define USBFS_EP_USAGE_TYPE_MASK (0x30u)
-/* Endpoint Status defines */
+/* point Status defines */
#define USBFS_EP_STATUS_LENGTH (0x02u)
-/* Endpoint Device defines */
+/* point Device defines */
#define USBFS_DEVICE_STATUS_LENGTH (0x02u)
#define USBFS_STATUS_LENGTH_MAX \
/* DMA manual mode defines */
#define USBFS_DMA_BYTES_PER_BURST (0u)
#define USBFS_DMA_REQUEST_PER_BURST (0u)
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+#endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
/* DMA automatic mode defines */
#define USBFS_DMA_BYTES_PER_BURST (32u)
+ #define USBFS_DMA_BYTES_REPEAT (2u)
/* BUF_SIZE-BYTES_PER_BURST examples: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */
#define USBFS_DMA_BUF_SIZE (0x55u)
#define USBFS_DMA_REQUEST_PER_BURST (1u)
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+
+ #if(USBFS_DMA1_REMOVE == 0u)
+ #define USBFS_ep1_TD_TERMOUT_EN USBFS_ep1__TD_TERMOUT_EN
+ #else
+ #define USBFS_ep1_TD_TERMOUT_EN (0u)
+ #endif /* USBFS_DMA1_REMOVE == 0u */
+ #if(USBFS_DMA2_REMOVE == 0u)
+ #define USBFS_ep2_TD_TERMOUT_EN USBFS_ep2__TD_TERMOUT_EN
+ #else
+ #define USBFS_ep2_TD_TERMOUT_EN (0u)
+ #endif /* USBFS_DMA2_REMOVE == 0u */
+ #if(USBFS_DMA3_REMOVE == 0u)
+ #define USBFS_ep3_TD_TERMOUT_EN USBFS_ep3__TD_TERMOUT_EN
+ #else
+ #define USBFS_ep3_TD_TERMOUT_EN (0u)
+ #endif /* USBFS_DMA3_REMOVE == 0u */
+ #if(USBFS_DMA4_REMOVE == 0u)
+ #define USBFS_ep4_TD_TERMOUT_EN USBFS_ep4__TD_TERMOUT_EN
+ #else
+ #define USBFS_ep4_TD_TERMOUT_EN (0u)
+ #endif /* USBFS_DMA4_REMOVE == 0u */
+ #if(USBFS_DMA5_REMOVE == 0u)
+ #define USBFS_ep5_TD_TERMOUT_EN USBFS_ep5__TD_TERMOUT_EN
+ #else
+ #define USBFS_ep5_TD_TERMOUT_EN (0u)
+ #endif /* USBFS_DMA5_REMOVE == 0u */
+ #if(USBFS_DMA6_REMOVE == 0u)
+ #define USBFS_ep6_TD_TERMOUT_EN USBFS_ep6__TD_TERMOUT_EN
+ #else
+ #define USBFS_ep6_TD_TERMOUT_EN (0u)
+ #endif /* USBFS_DMA6_REMOVE == 0u */
+ #if(USBFS_DMA7_REMOVE == 0u)
+ #define USBFS_ep7_TD_TERMOUT_EN USBFS_ep7__TD_TERMOUT_EN
+ #else
+ #define USBFS_ep7_TD_TERMOUT_EN (0u)
+ #endif /* USBFS_DMA7_REMOVE == 0u */
+ #if(USBFS_DMA8_REMOVE == 0u)
+ #define USBFS_ep8_TD_TERMOUT_EN USBFS_ep8__TD_TERMOUT_EN
+ #else
+ #define USBFS_ep8_TD_TERMOUT_EN (0u)
+ #endif /* USBFS_DMA8_REMOVE == 0u */
+
+ #define USBFS_EP17_SR_MASK (0x7fu)
+ #define USBFS_EP8_SR_MASK (0x03u)
+
+#endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
/* DIE ID string descriptor defines */
#if defined(USBFS_ENABLE_IDSN_STRING)
#if(!CY_PSOC5LP)
#define USBFS_USBIO_CR2_PTR ( (reg8 *) USBFS_USB__USBIO_CR2)
#define USBFS_USBIO_CR2_REG (* (reg8 *) USBFS_USB__USBIO_CR2)
-#endif /* End CY_PSOC5LP */
+#endif /* CY_PSOC5LP */
#define USBFS_DIE_ID CYDEV_FLSHID_CUST_TABLES_BASE
#else
#define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG )
#define USBFS_VBUS_MASK (0x01u)
- #endif /* End USBFS_EXTERN_VBUS == 0u */
-#endif /* End USBFS_MON_VBUS */
+ #endif /* USBFS_EXTERN_VBUS == 0u */
+#endif /* USBFS_MON_VBUS */
/* Renamed Registers for backward compatibility.
* Should not be used in new designs.
#define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0)
#define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0)
#define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET)
-#endif /* End CYDEV_CHIP_DIE_EXPECT */
+#endif /* CYDEV_CHIP_DIE_EXPECT */
/***************************************
#define USBFS_ARB_EPX_CFG_CRC_BYPASS (0x04u)
#define USBFS_ARB_EPX_CFG_DMA_REQ (0x02u)
#define USBFS_ARB_EPX_CFG_IN_DATA_RDY (0x01u)
+#define USBFS_ARB_EPX_CFG_DEFAULT (USBFS_ARB_EPX_CFG_RESET | \
+ USBFS_ARB_EPX_CFG_CRC_BYPASS)
#define USBFS_ARB_EPX_SR_IN_BUF_FULL (0x01u)
#define USBFS_ARB_EPX_SR_DMA_GNT (0x02u)
#define USBFS_ARB_EPX_INT_MASK (0x1Du)
#else
#define USBFS_ARB_EPX_INT_MASK (0x1Fu)
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+#endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
#define USBFS_ARB_INT_MASK (uint8)((USBFS_DMA1_REMOVE ^ 1u) | \
(uint8)((USBFS_DMA2_REMOVE ^ 1u) << 1u) | \
(uint8)((USBFS_DMA3_REMOVE ^ 1u) << 2u) | \
#define USBFS_DYN_RECONFIG_RDY_STS (0x10u)
-#endif /* End CY_USBFS_USBFS_H */
+#endif /* CY_USBFS_USBFS_H */
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_Dm.c
-* Version 1.90
+* Version 2.10
*
* Description:
* This file contains API to enable firmware control of a Pins component.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Change the drive mode on the pins of the port.
*
* Parameters:
-* mode: Change the pins to this drive mode.
+* mode: Change the pins to one of the following drive modes.
+*
+* USBFS_Dm_DM_STRONG Strong Drive
+* USBFS_Dm_DM_OD_HI Open Drain, Drives High
+* USBFS_Dm_DM_OD_LO Open Drain, Drives Low
+* USBFS_Dm_DM_RES_UP Resistive Pull Up
+* USBFS_Dm_DM_RES_DWN Resistive Pull Down
+* USBFS_Dm_DM_RES_UPDWN Resistive Pull Up/Down
+* USBFS_Dm_DM_DIG_HIZ High Impedance Digital
+* USBFS_Dm_DM_ALG_HIZ High Impedance Analog
*
* Return:
* None
/*******************************************************************************
* File Name: USBFS_Dm.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
/*******************************************************************************
* File Name: USBFS_Dm.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define USBFS_Dm_0 USBFS_Dm__0__PC
+#define USBFS_Dm_0 (USBFS_Dm__0__PC)
#endif /* End Pins USBFS_Dm_ALIASES_H */
/*******************************************************************************
* File Name: USBFS_Dp.c
-* Version 1.90
+* Version 2.10
*
* Description:
* This file contains API to enable firmware control of a Pins component.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Change the drive mode on the pins of the port.
*
* Parameters:
-* mode: Change the pins to this drive mode.
+* mode: Change the pins to one of the following drive modes.
+*
+* USBFS_Dp_DM_STRONG Strong Drive
+* USBFS_Dp_DM_OD_HI Open Drain, Drives High
+* USBFS_Dp_DM_OD_LO Open Drain, Drives Low
+* USBFS_Dp_DM_RES_UP Resistive Pull Up
+* USBFS_Dp_DM_RES_DWN Resistive Pull Down
+* USBFS_Dp_DM_RES_UPDWN Resistive Pull Up/Down
+* USBFS_Dp_DM_DIG_HIZ High Impedance Digital
+* USBFS_Dp_DM_ALG_HIZ High Impedance Analog
*
* Return:
* None
/*******************************************************************************
* File Name: USBFS_Dp.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
/*******************************************************************************
* File Name: USBFS_Dp.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define USBFS_Dp_0 USBFS_Dp__0__PC
+#define USBFS_Dp_0 (USBFS_Dp__0__PC)
#endif /* End Pins USBFS_Dp_ALIASES_H */
/*******************************************************************************
* File Name: USBFS_audio.c
-* Version 2.60
+* Version 2.80
*
* Description:
* USB AUDIO Class request handler.
*
-* Note:
+* Related Document:
+* Universal Serial Bus Device Class Definition for Audio Devices Release 1.0
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "USBFS_audio.h"
#include "USBFS_pvt.h"
-#if defined(USBFS_ENABLE_MIDI_STREAMING)
+#if defined(USBFS_ENABLE_MIDI_STREAMING)
#include "USBFS_midi.h"
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+#endif /* USBFS_ENABLE_MIDI_STREAMING*/
/***************************************
USBFS_VOL_MAX_MSB};
volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_RES_LSB,
USBFS_VOL_RES_MSB};
-#endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+#endif /* USBFS_ENABLE_AUDIO_STREAMING */
/*******************************************************************************
uint8 USBFS_DispatchAUDIOClassRqst(void)
{
uint8 requestHandled = USBFS_FALSE;
+ uint8 bmRequestType = CY_GET_REG8(USBFS_bmRequestType);
#if defined(USBFS_ENABLE_AUDIO_STREAMING)
uint8 epNumber;
epNumber = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED;
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */
- if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)
+
+ if ((bmRequestType & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)
{
/* Control Read */
- if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
- USBFS_RQST_RCPT_EP)
+ if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)
{
/* Endpoint */
switch (CY_GET_REG8(USBFS_bRequest))
#if defined(USBFS_ENABLE_AUDIO_STREAMING)
if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)
{
- /* Endpoint Control Selector is Sampling Frequency */
+ /* point Control Selector is Sampling Frequency */
USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;
USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber];
requestHandled = USBFS_InitControlRead();
}
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */
/* `#START AUDIO_READ_REQUESTS` Place other request handler here */
break;
}
}
- else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
- USBFS_RQST_RCPT_IFC)
+ else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)
{
/* Interface or Entity ID */
switch (CY_GET_REG8(USBFS_bRequest))
/* `#START MUTE_CONTROL_GET_REQUEST` Place multi-channel handler here */
/* `#END` */
-
+
/* Entity ID Control Selector is MUTE */
USBFS_currentTD.wCount = 1u;
USBFS_currentTD.pData = &USBFS_currentMute;
USBFS_currentTD.wCount = 0u;
requestHandled = USBFS_InitControlWrite();
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */
/* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */
{ /* USBFS_RQST_RCPT_OTHER */
}
}
- else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == \
- USBFS_RQST_DIR_H2D)
+ else
{
/* Control Write */
- if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
- USBFS_RQST_RCPT_EP)
+ if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)
{
- /* Endpoint */
+ /* point */
switch (CY_GET_REG8(USBFS_bRequest))
{
case USBFS_SET_CUR:
#if defined(USBFS_ENABLE_AUDIO_STREAMING)
if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)
{
- /* Endpoint Control Selector is Sampling Frequency */
+ /* point Control Selector is Sampling Frequency */
USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;
USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber];
requestHandled = USBFS_InitControlWrite();
USBFS_frequencyChanged = epNumber;
}
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */
/* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */
break;
}
}
- else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
- USBFS_RQST_RCPT_IFC)
+ else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)
{
/* Interface or Entity ID */
switch (CY_GET_REG8(USBFS_bRequest))
/* `#END` */
}
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */
/* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */
}
}
else
- { /* USBFS_RQST_RCPT_OTHER */
+ {
+ /* USBFS_RQST_RCPT_OTHER */
}
}
- else
- { /* requestHandled is initialized as FALSE by default */
- }
return(requestHandled);
}
-
#endif /* USER_SUPPLIED_AUDIO_HANDLER */
/* `#END` */
-#endif /* End USBFS_ENABLE_AUDIO_CLASS*/
+#endif /* USBFS_ENABLE_AUDIO_CLASS */
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_audio.h
-* Version 2.60
+* Version 2.80
*
* Description:
-* Header File for the USFS component. Contains prototypes and constant values.
+* Header File for the USBFS component. Contains prototypes and constant values.
+*
+* Related Document:
+* Universal Serial Bus Device Class Definition for Audio Devices Release 1.0
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#define USBFS_GET_MEM (0x85u)
#define USBFS_GET_STAT (0xFFu)
-/* Endpoint Control Selectors (AUDIO Table A-19) */
+/* point Control Selectors (AUDIO Table A-19) */
#define USBFS_EP_CONTROL_UNDEFINED (0x00u)
#define USBFS_SAMPLING_FREQ_CONTROL (0x01u)
#define USBFS_PITCH_CONTROL (0x02u)
extern volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN];
extern volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN];
-#endif /* End CY_USBFS_USBFS_audio_H */
+#endif /* CY_USBFS_USBFS_audio_H */
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_boot.c
-* Version 2.60
+* Version 2.80
*
* Description:
* Boot loader API for USBFS Component.
* Note:
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
(CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))
-/***************************************
-* Bootloader defines
-***************************************/
-
-#define USBFS_CyBtLdrStarttimer(X, T) {USBFS_universalTime = T * 10; X = 0u;}
-#define USBFS_CyBtLdrChecktimer(X) ((X++ < USBFS_universalTime) ? 1u : 0u)
-
-#define USBFS_BTLDR_OUT_EP (0x01u)
-#define USBFS_BTLDR_IN_EP (0x02u)
-
-
/***************************************
* Bootloader Variables
***************************************/
-static uint16 USBFS_universalTime;
-static uint8 USBFS_started = 0u;
+static uint8 USBFS_started = 0u;
/*******************************************************************************
/* USB component started, the correct enumeration will be checked in first Read operation */
USBFS_started = 1u;
-
}
* Resets the receive and transmit communication Buffers.
*
* Parameters:
-* None.
+* None
*
* Return:
-* None.
+* None
*
* Reentrant:
-* No.
+* No
*
*******************************************************************************/
void USBFS_CyBtldrCommReset(void)
* Returns the value that best describes the problem.
*
* Reentrant:
-* No.
+* No
*
*******************************************************************************/
-cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
{
- uint16 time;
- cystatus status;
+ cystatus retCode;
+ uint16 timeoutMs;
+
+ timeoutMs = ((uint16) 10u * timeOut); /* Convert from 10mS check to number 1mS checks */
/* Enable IN transfer */
USBFS_LoadInEP(USBFS_BTLDR_IN_EP, pData, USBFS_BTLDR_SIZEOF_READ_BUFFER);
- /* Start a timer to wait on. */
- USBFS_CyBtLdrStarttimer(time, timeOut);
-
/* Wait for the master to read it. */
- while((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) && \
- USBFS_CyBtLdrChecktimer(time))
+ while ((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) &&
+ (0u != timeoutMs))
{
- CyDelay(1u); /* 1ms delay */
+ CyDelay(USBFS_BTLDR_WAIT_1_MS);
+ timeoutMs--;
}
if (USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL)
{
- status = CYRET_TIMEOUT;
+ retCode = CYRET_TIMEOUT;
}
else
{
*count = size;
- status = CYRET_SUCCESS;
+ retCode = CYRET_SUCCESS;
}
- return(status);
+ return(retCode);
}
* Returns the value that best describes the problem.
*
* Reentrant:
-* No.
+* No
*
*******************************************************************************/
-cystatus USBFS_CyBtldrCommRead(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+cystatus USBFS_CyBtldrCommRead(uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
{
- cystatus status;
- uint16 time;
+ cystatus retCode;
+ uint16 timeoutMs;
+
+ timeoutMs = ((uint16) 10u * timeOut); /* Convert from 10mS check to number 1mS checks */
- if(size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER)
+ if (size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER)
{
size = USBFS_BTLDR_SIZEOF_WRITE_BUFFER;
}
- /* Start a timer to wait on. */
- USBFS_CyBtLdrStarttimer(time, timeOut);
/* Wait on enumeration in first time */
- if(USBFS_started)
+ if (0u != USBFS_started)
{
/* Wait for Device to enumerate */
- while(!USBFS_GetConfiguration() && USBFS_CyBtLdrChecktimer(time))
+ while ((0u ==USBFS_GetConfiguration()) && (0u != timeoutMs))
{
- CyDelay(1u); /* 1ms delay */
+ CyDelay(USBFS_BTLDR_WAIT_1_MS);
+ timeoutMs--;
}
+
/* Enable first OUT, if enumeration complete */
- if(USBFS_GetConfiguration())
+ if (0u != USBFS_GetConfiguration())
{
- USBFS_IsConfigurationChanged(); /* Clear configuration changes state status */
+ (void) USBFS_IsConfigurationChanged(); /* Clear configuration changes state status */
USBFS_CyBtldrCommReset();
USBFS_started = 0u;
}
}
else /* Check for configuration changes, has been done by Host */
{
- if(USBFS_IsConfigurationChanged() != 0u) /* Host could send double SET_INTERFACE request or RESET */
+ if (0u != USBFS_IsConfigurationChanged()) /* Host could send double SET_INTERFACE request or RESET */
{
- if(USBFS_GetConfiguration() != 0u) /* Init OUT endpoints when device reconfigured */
+ if (0u != USBFS_GetConfiguration()) /* Init OUT endpoints when device reconfigured */
{
USBFS_CyBtldrCommReset();
}
}
}
+
+ timeoutMs = ((uint16) 10u * timeOut); /* Re-arm timeout */
+
/* Wait on next packet */
while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \
- USBFS_CyBtLdrChecktimer(time))
+ (0u != timeoutMs))
{
- CyDelay(1u); /* 1ms delay */
+ CyDelay(USBFS_BTLDR_WAIT_1_MS);
+ timeoutMs--;
}
/* OUT EP has completed */
if (USBFS_GetEPState(USBFS_BTLDR_OUT_EP) == USBFS_OUT_BUFFER_FULL)
{
*count = USBFS_ReadOutEP(USBFS_BTLDR_OUT_EP, pData, size);
- status = CYRET_SUCCESS;
+ retCode = CYRET_SUCCESS;
}
else
{
*count = 0u;
- status = CYRET_TIMEOUT;
+ retCode = CYRET_TIMEOUT;
}
- return(status);
+
+ return(retCode);
}
-#endif /* End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
+#endif /* CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_cdc.c
-* Version 2.60
+* Version 2.80
*
* Description:
-* USB HID Class request handler.
+* USB CDC class request handler.
*
-* Note:
+* Related Document:
+* Universal Serial Bus Class Definitions for Communication Devices Version 1.1
*
********************************************************************************
-* Copyright 2012-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2012-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* CDC Variables
***************************************/
-volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE];
+volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE] =
+{
+ 0x00u, 0xC2u, 0x01u, 0x00u, /* Data terminal rate 115200 */
+ 0x00u, /* 1 Stop bit */
+ 0x00u, /* None parity */
+ 0x08u /* 8 data bits */
+};
volatile uint8 USBFS_lineChanged;
volatile uint16 USBFS_lineControlBitmap;
volatile uint8 USBFS_cdc_data_in_ep;
/***************************************
* Static Function Prototypes
***************************************/
-static uint16 USBFS_StrLen(const char8 string[]) ;
+#if (USBFS_ENABLE_CDC_CLASS_API != 0u)
+ static uint16 USBFS_StrLen(const char8 string[]) ;
+#endif /* (USBFS_ENABLE_CDC_CLASS_API != 0u) */
/***************************************
***************************************/
#if (USBFS_ENABLE_CDC_CLASS_API != 0u)
-
/*******************************************************************************
* Function Name: USBFS_CDC_Init
********************************************************************************
********************************************************************************
*
* Summary:
- * Sends a specified number of bytes from the location specified by a
- * pointer to the PC.
+ * This function sends a specified number of bytes from the location specified
+ * by a pointer to the PC. The USBFS_CDCIsReady() function should be
+ * called before sending new data, to be sure that the previous data has
+ * finished sending.
+ * If the last sent packet is less than maximum packet size the USB transfer
+ * of this short packet will identify the end of the segment. If the last sent
+ * packet is exactly maximum packet size, it shall be followed by a zero-length
+ * packet (which is a short packet) to assure the end of segment is properly
+ * identified. To send zero-length packet, use USBFS_PutData() API
+ * with length parameter set to zero.
*
* Parameters:
* pData: pointer to the buffer containing data to be sent.
* length: Specifies the number of bytes to send from the pData
* buffer. Maximum length will be limited by the maximum packet
- * size for the endpoint.
+ * size for the endpoint. Data will be lost if length is greater than Max
+ * Packet Size.
*
* Return:
* None.
********************************************************************************
*
* Summary:
- * Sends a null terminated string to the PC.
+ * This function sends a null terminated string to the PC. This function will
+ * block if there is not enough memory to place the whole string. It will block
+ * until the entire string has been written to the transmit buffer.
+ * The USBUART_CDCIsReady() function should be called before sending data with
+ * a new call to USBFS_PutString(), to be sure that the previous data
+ * has finished sending.
*
* Parameters:
- * string: pointer to the string to be sent to the PC
+ * string: pointer to the string to be sent to the PC.
*
* Return:
* None.
* Reentrant:
* No.
*
- * Theory:
- * This function will block if there is not enough memory to place the whole
- * string, it will block until the entire string has been written to the
- * transmit buffer.
- *
*******************************************************************************/
void USBFS_PutString(const char8 string[])
{
- uint16 str_length;
- uint16 send_length;
- uint16 buf_index = 0u;
+ uint16 strLength;
+ uint16 sendLength;
+ uint16 bufIndex = 0u;
/* Get length of the null terminated string */
- str_length = USBFS_StrLen(string);
+ strLength = USBFS_StrLen(string);
do
{
/* Limits length to maximum packet size for the EP */
- send_length = (str_length > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ?
- USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : str_length;
+ sendLength = (strLength > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ?
+ USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : strLength;
/* Enable IN transfer */
- USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[buf_index], send_length);
- str_length -= send_length;
+ USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[bufIndex], sendLength);
+ strLength -= sendLength;
- /* If more data are present to send */
- if(str_length > 0u)
+ /* If more data are present to send or full packet was sent */
+ if((strLength > 0u) || (sendLength == USBFS_EP[USBFS_cdc_data_in_ep].bufferSize))
{
- buf_index += send_length;
+ bufIndex += sendLength;
/* Wait for the Host to read it. */
while(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState ==
USBFS_IN_BUFFER_FULL)
{
;
}
+ /* If the last sent packet is exactly maximum packet size,
+ * it shall be followed by a zero-length packet to assure the
+ * end of segment is properly identified by the terminal.
+ */
+ if(strLength == 0u)
+ {
+ USBFS_LoadInEP(USBFS_cdc_data_in_ep, NULL, 0u);
+ }
}
- }while(str_length > 0u);
+ }while(strLength > 0u);
}
*
* Summary:
* This function returns the number of bytes that were received from the PC.
+ * The returned length value should be passed to USBFS_GetData() as
+ * a parameter to read all received data. If all of the received data is not
+ * read at one time by the USBFS_GetData() API, the unread data will
+ * be lost.
*
* Parameters:
* None.
*
* Return:
- * Returns the number of received bytes.
+ * Returns the number of received bytes. The maximum amount of received data at
+ * a time is limited by the maximum packet size for the endpoint.
*
* Global variables:
* USBFS_cdc_data_out_ep: CDC OUT endpoint number used.
*******************************************************************************/
uint16 USBFS_GetCount(void)
{
- uint16 bytesCount = 0u;
+ uint16 bytesCount;
if (USBFS_EP[USBFS_cdc_data_out_ep].apiEpState == USBFS_OUT_BUFFER_FULL)
{
bytesCount = USBFS_GetEPCount(USBFS_cdc_data_out_ep);
}
+ else
+ {
+ bytesCount = 0u;
+ }
return(bytesCount);
}
*
* Summary:
* Returns a nonzero value if the component received data or received
- * zero-length packet. The GetAll() or GetData() API should be called to read
- * data from the buffer and re-init OUT endpoint even when zero-length packet
- * received.
+ * zero-length packet. The USBFS_GetAll() or
+ * USBFS_GetData() API should be called to read data from the buffer
+ * and re-init OUT endpoint even when zero-length packet received.
*
* Parameters:
* None.
********************************************************************************
*
* Summary:
- * Returns a nonzero value if the component is ready to send more data to the
- * PC. Otherwise returns zero. Should be called before sending new data to
- * ensure the previous data has finished sending.This function returns the
- * number of bytes that were received from the PC.
+ * This function returns a nonzero value if the component is ready to send more
+ * data to the PC; otherwise, it returns zero. The function should be called
+ * before sending new data when using any of the following APIs:
+ * USBFS_PutData(),USBFS_PutString(),
+ * USBFS_PutChar or USBFS_PutCRLF(),
+ * to be sure that the previous data has finished sending.
*
* Parameters:
* None.
*
* Return:
- * If the buffer can accept new data then this function returns a nonzero value.
- * Otherwise zero is returned.
+ * If the buffer can accept new data, this function returns a nonzero value.
+ * Otherwise, it returns zero.
*
* Global variables:
* USBFS_cdc_data_in_ep: CDC IN endpoint number used.
********************************************************************************
*
* Summary:
- * Gets a specified number of bytes from the input buffer and places it in a
- * data array specified by the passed pointer.
- * USBFS_DataIsReady() API should be called before, to be sure
- * that data is received from the Host.
+ * This function gets a specified number of bytes from the input buffer and
+ * places them in a data array specified by the passed pointer.
+ * The USBFS_DataIsReady() API should be called first, to be sure
+ * that data is received from the host. If all received data will not be read at
+ * once, the unread data will be lost. The USBFS_GetData() API should
+ * be called to get the number of bytes that were received.
*
* Parameters:
* pData: Pointer to the data array where data will be placed.
********************************************************************************
*
* Summary:
- * Reads one byte of received data from the buffer.
+ * This function reads one byte of received data from the buffer. If more than
+ * one byte has been received from the host, the rest of the data will be lost.
*
* Parameters:
* None.
********************************************************************************
*
* Summary:
- * This function returns clear on read status of the line.
+ * This function returns clear on read status of the line. It returns not zero
+ * value when the host sends updated coding or control information to the
+ * device. The USBFS_GetDTERate(), USBFS_GetCharFormat()
+ * or USBFS_GetParityType() or USBFS_GetDataBits() API
+ * should be called to read data coding information.
+ * The USBFS_GetLineControl() API should be called to read line
+ * control information.
*
* Parameters:
* None.
*
* Return:
- * If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE request received then not
- * zero value returned. Otherwise zero is returned.
+ * If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE requests are received, it
+ * returns a nonzero value. Otherwise, it returns zero.
*
* Global variables:
- * USBFS_transferState - it is checked to be sure then OUT data
+ * USBFS_transferState: it is checked to be sure then OUT data
* phase has been complete, and data written to the lineCoding or Control
* Bitmap buffer.
* USBFS_lineChanged: used as a flag to be aware that Host has been
return(USBFS_lineControlBitmap);
}
-#endif /* End USBFS_ENABLE_CDC_CLASS_API*/
+#endif /* USBFS_ENABLE_CDC_CLASS_API*/
/*******************************************************************************
/* `#END` */
-#endif /* End USBFS_ENABLE_CDC_CLASS*/
+#endif /* USBFS_ENABLE_CDC_CLASS*/
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_cdc.h
-* Version 2.60
+* Version 2.80
*
* Description:
-* Header File for the USFS component.
+* Header File for the USBFS component.
* Contains CDC class prototypes and constant values.
*
+* Related Document:
+* Universal Serial Bus Class Definitions for Communication Devices Version 1.1
+*
********************************************************************************
-* Copyright 2012-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2012-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
uint8 USBFS_GetParityType(void) ;
uint8 USBFS_GetDataBits(void) ;
uint16 USBFS_GetLineControl(void) ;
-#endif /* End USBFS_ENABLE_CDC_CLASS_API*/
+#endif /* USBFS_ENABLE_CDC_CLASS_API */
/***************************************
extern volatile uint8 USBFS_cdc_data_in_ep;
extern volatile uint8 USBFS_cdc_data_out_ep;
-#endif /* End CY_USBFS_USBFS_cdc_H */
+#endif /* CY_USBFS_USBFS_cdc_H */
/* [] END OF FILE */
;******************************************************************************
; File Name: USBFS_cdc.inf
-; Version 2.60
+; Version 2.80
;
; Description:
; Windows USB CDC setup file for USBUART Device.
;
;******************************************************************************
-; Copyright 2007-2013, Cypress Semiconductor Corporation. All rights reserved.
+; Copyright 2007-2014, Cypress Semiconductor Corporation. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
/*******************************************************************************
* File Name: USBFS_cls.c
-* Version 2.60
+* Version 2.80
*
* Description:
* USB Class request handler.
* Note:
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
break;
case USBFS_RQST_RCPT_EP: /* Class-specific request directed to the endpoint */
/* Find related interface to the endpoint, wIndexLo contain EP number */
- interfaceNumber =
- USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].interface;
+ interfaceNumber = USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) &
+ USBFS_DIR_UNUSED].interface;
break;
default: /* RequestHandled is initialized as FALSE by default */
break;
case USBFS_CLASS_AUDIO:
#if defined(USBFS_ENABLE_AUDIO_CLASS)
requestHandled = USBFS_DispatchAUDIOClassRqst();
- #endif /* USBFS_ENABLE_HID_CLASS */
+ #endif /* USBFS_CLASS_AUDIO */
break;
case USBFS_CLASS_CDC:
#if defined(USBFS_ENABLE_CDC_CLASS)
/*******************************************************************************
* File Name: USBFS_descr.c
-* Version 2.60
+* Version 2.80
*
* Description:
* USB descriptors and storage.
* Note:
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*****************************************************************************
* User supplied descriptors. If you want to specify your own descriptors,
-* remove the comments around the define USER_SUPPLIED_DESCRIPTORS below and
-* add your descriptors.
+* define USER_SUPPLIED_DESCRIPTORS below and add your descriptors.
*****************************************************************************/
/* `#START USER_DESCRIPTORS_DECLARATIONS` Place your declaration here */
/* bEndpointAddress */ 0x01u,
/* bmAttributes */ 0x03u,
/* wMaxPacketSize */ 0x40u, 0x00u,
-/* bInterval */ 0x80u,
+/* bInterval */ 0x20u,
/*********************************************************************
* Endpoint Descriptor
*********************************************************************/
/* bEndpointAddress */ 0x82u,
/* bmAttributes */ 0x03u,
/* wMaxPacketSize */ 0x40u, 0x00u,
-/* bInterval */ 0x40u,
+/* bInterval */ 0x20u,
/*********************************************************************
* Interface Descriptor
*********************************************************************/
/* bEndpointAddress */ 0x03u,
/* bmAttributes */ 0x03u,
/* wMaxPacketSize */ 0x40u, 0x00u,
-/* bInterval */ 0x80u,
+/* bInterval */ 0x20u,
/*********************************************************************
* Endpoint Descriptor
*********************************************************************/
/* bEndpointAddress */ 0x84u,
/* bmAttributes */ 0x03u,
/* wMaxPacketSize */ 0x40u, 0x00u,
-/* bInterval */ 0x40u
+/* bInterval */ 0x20u
};
/*********************************************************************
/*******************************************************************************
* File Name: USBFS_drv.c
-* Version 2.60
+* Version 2.80
*
* Description:
* Endpoint 0 Driver for the USBFS Component.
* Note:
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************************
* File Name: USBFS_episr.c
-* Version 2.60
+* Version 2.80
*
* Description:
* Data endpoint Interrupt Service Routines
* Note:
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "USBFS.h"
#include "USBFS_pvt.h"
-#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)
+#if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u))
#include "USBFS_midi.h"
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+#endif /* (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)) */
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ #include "USBFS_EP8_DMA_Done_SR.h"
+ #include "USBFS_EP17_DMA_Done_SR.h"
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */
/***************************************
******************************************************************************/
CY_ISR(USBFS_EP_1_ISR)
{
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
uint8 int_en;
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
int_en = EA;
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) &
(uint8)~USBFS_SIE_EP_INT_EP1_MASK);
- #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT )
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT)
if(USBFS_midi_out_ep == USBFS_EP1)
{
USBFS_MIDI_OUT_EP_Service();
}
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */
/* `#START EP1_END_USER_CODE` Place your code here */
/* `#END` */
- #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 )
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
}
-#endif /* End USBFS_EP1_ISR_REMOVE */
+#endif /* USBFS_EP1_ISR_REMOVE */
#if(USBFS_EP2_ISR_REMOVE == 0u)
*******************************************************************************/
CY_ISR(USBFS_EP_2_ISR)
{
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
uint8 int_en;
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 )
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
int_en = EA;
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
& (uint8)~USBFS_SIE_EP_INT_EP2_MASK);
- #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT )
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT)
if(USBFS_midi_out_ep == USBFS_EP2)
{
USBFS_MIDI_OUT_EP_Service();
}
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */
/* `#START EP2_END_USER_CODE` Place your code here */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
}
-#endif /* End USBFS_EP2_ISR_REMOVE */
+#endif /* USBFS_EP2_ISR_REMOVE */
#if(USBFS_EP3_ISR_REMOVE == 0u)
*******************************************************************************/
CY_ISR(USBFS_EP_3_ISR)
{
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
uint8 int_en;
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
int_en = EA;
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
& (uint8)~USBFS_SIE_EP_INT_EP3_MASK);
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT)
if(USBFS_midi_out_ep == USBFS_EP3)
{
USBFS_MIDI_OUT_EP_Service();
}
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */
/* `#START EP3_END_USER_CODE` Place your code here */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
}
-#endif /* End USBFS_EP3_ISR_REMOVE */
+#endif /* USBFS_EP3_ISR_REMOVE */
#if(USBFS_EP4_ISR_REMOVE == 0u)
*******************************************************************************/
CY_ISR(USBFS_EP_4_ISR)
{
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
int_en = EA;
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
& (uint8)~USBFS_SIE_EP_INT_EP4_MASK);
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT)
if(USBFS_midi_out_ep == USBFS_EP4)
{
USBFS_MIDI_OUT_EP_Service();
}
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */
/* `#START EP4_END_USER_CODE` Place your code here */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
}
-#endif /* End USBFS_EP4_ISR_REMOVE */
+#endif /* USBFS_EP4_ISR_REMOVE */
#if(USBFS_EP5_ISR_REMOVE == 0u)
*******************************************************************************/
CY_ISR(USBFS_EP_5_ISR)
{
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
int_en = EA;
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
& (uint8)~USBFS_SIE_EP_INT_EP5_MASK);
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT)
if(USBFS_midi_out_ep == USBFS_EP5)
{
USBFS_MIDI_OUT_EP_Service();
}
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */
/* `#START EP5_END_USER_CODE` Place your code here */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
}
-#endif /* End USBFS_EP5_ISR_REMOVE */
+#endif /* USBFS_EP5_ISR_REMOVE */
#if(USBFS_EP6_ISR_REMOVE == 0u)
*******************************************************************************/
CY_ISR(USBFS_EP_6_ISR)
{
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
int_en = EA;
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
& (uint8)~USBFS_SIE_EP_INT_EP6_MASK);
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT)
if(USBFS_midi_out_ep == USBFS_EP6)
{
USBFS_MIDI_OUT_EP_Service();
}
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */
/* `#START EP6_END_USER_CODE` Place your code here */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
}
-#endif /* End USBFS_EP6_ISR_REMOVE */
+#endif /* USBFS_EP6_ISR_REMOVE */
#if(USBFS_EP7_ISR_REMOVE == 0u)
*******************************************************************************/
CY_ISR(USBFS_EP_7_ISR)
{
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
int_en = EA;
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
& (uint8)~USBFS_SIE_EP_INT_EP7_MASK);
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT)
if(USBFS_midi_out_ep == USBFS_EP7)
{
USBFS_MIDI_OUT_EP_Service();
}
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */
/* `#START EP7_END_USER_CODE` Place your code here */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
}
-#endif /* End USBFS_EP7_ISR_REMOVE */
+#endif /* USBFS_EP7_ISR_REMOVE */
#if(USBFS_EP8_ISR_REMOVE == 0u)
*******************************************************************************/
CY_ISR(USBFS_EP_8_ISR)
{
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
int_en = EA;
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
& (uint8)~USBFS_SIE_EP_INT_EP8_MASK);
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT)
if(USBFS_midi_out_ep == USBFS_EP8)
{
USBFS_MIDI_OUT_EP_Service();
}
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */
/* `#START EP8_END_USER_CODE` Place your code here */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
}
-#endif /* End USBFS_EP8_ISR_REMOVE */
+#endif /* USBFS_EP8_ISR_REMOVE */
/*******************************************************************************
/* Clear Data ready status */
*(reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) &=
(uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+ #if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ /* Setup common area DMA with rest of the data */
+ if(USBFS_inLength[ep] > USBFS_DMA_BYTES_PER_BURST)
+ {
+ USBFS_LoadNextInEP(ep, 0u);
+ }
+ else
+ {
+ USBFS_inBufFull[ep] = 1u;
+ }
+ #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
/* Write the Mode register */
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), USBFS_EP[ep].epMode);
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN)
{ /* Clear MIDI input pointer */
USBFS_midiInPointer = 0u;
}
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/
}
}
/* (re)arm Out EP only for mode2 */
USBFS_EP[ep].epMode);
}
}
- #endif /* End USBFS_EP_MM */
+ #endif /* USBFS_EP_MM */
/* `#START ARB_USER_CODE` Place your code here for handle Buffer Underflow/Overflow */
/* `#END` */
}
-#endif /* End USBFS_EP_MM */
+#endif /* USBFS_EP_MM */
+
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ /******************************************************************************
+ * Function Name: USBFS_EP_DMA_DONE_ISR
+ *******************************************************************************
+ *
+ * Summary:
+ * Endpoint 1 DMA Done Interrupt Service Routine
+ *
+ * Parameters:
+ * None.
+ *
+ * Return:
+ * None.
+ *
+ ******************************************************************************/
+ CY_ISR(USBFS_EP_DMA_DONE_ISR)
+ {
+ uint8 int8Status;
+ uint8 int17Status;
+ uint8 ep_status;
+ uint8 ep = USBFS_EP1;
+ uint8 ptr = 0u;
+
+ /* `#START EP_DMA_DONE_BEGIN_USER_CODE` Place your code here */
+
+ /* `#END` */
+
+ /* Read clear on read status register with the EP source of interrupt */
+ int17Status = USBFS_EP17_DMA_Done_SR_Read() & USBFS_EP17_SR_MASK;
+ int8Status = USBFS_EP8_DMA_Done_SR_Read() & USBFS_EP8_SR_MASK;
+
+ while(int8Status != 0u)
+ {
+ while(int17Status != 0u)
+ {
+ if((int17Status & 1u) != 0u) /* If EpX interrupt present */
+ {
+ /* Read Endpoint Status Register */
+ ep_status = CY_GET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr));
+ if( ((ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL) == 0u) &&
+ (USBFS_inBufFull[ep] == 0u))
+ {
+ /* `#START EP_DMA_DONE_USER_CODE` Place your code here */
+
+ /* `#END` */
+
+ CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ptr), 0x00u);
+ /* repeat 2 last bytes to prefetch endpoint area */
+ CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ptr),
+ USBFS_DMA_BYTES_PER_BURST * ep - USBFS_DMA_BYTES_REPEAT);
+ USBFS_LoadNextInEP(ep, 1);
+ /* Set Data ready status, This will generate DMA request */
+ * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+ }
+ }
+ ptr += USBFS_EPX_CNTX_ADDR_OFFSET; /* prepare pointer for next EP */
+ ep++;
+ int17Status >>= 1u;
+ }
+ int8Status >>= 1u;
+ if(int8Status != 0u)
+ {
+ /* Prepare pointer for EP8 */
+ ptr = ((USBFS_EP8 - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
+ ep = USBFS_EP8;
+ int17Status = int8Status & 0x01u;
+ }
+ }
+
+ /* `#START EP_DMA_DONE_END_USER_CODE` Place your code here */
+
+ /* `#END` */
+ }
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_hid.c
-* Version 2.60
+* Version 2.80
*
* Description:
* USB HID Class request handler.
*
+* Related Document:
+* Device Class Definition for Human Interface Devices (HID) Version 1.11
+*
* Note:
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/* `#END` */
-#endif /* End USBFS_ENABLE_HID_CLASS */
+#endif /* USBFS_ENABLE_HID_CLASS */
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_hid.h
-* Version 2.60
+* Version 2.80
*
* Description:
-* Header File for the USFS component. Contains prototypes and constant values.
+* Header File for the USBFS component. Contains prototypes and constant values.
+*
+* Related Document:
+* Device Class Definition for Human Interface Devices (HID) Version 1.11
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#define USBFS_HID_GET_REPORT_OUTPUT (0x02u)
#define USBFS_HID_GET_REPORT_FEATURE (0x03u)
-#endif /* End CY_USBFS_USBFS_hid_H */
+#endif /* CY_USBFS_USBFS_hid_H */
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_midi.c
-* Version 2.60
+* Version 2.80
*
* Description:
* MIDI Streaming request handler.
* This file contains routines for sending and receiving MIDI
* messages, and handles running status in both directions.
*
+* Related Document:
+* Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0
+* MIDI 1.0 Detailed Specification Document Version 4.2
+*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */
#else
volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */
- #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */
+ #endif /* (USBFS_MIDI_IN_BUFF_SIZE >= 256) */
volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */
uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */
-#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
+#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */
uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */
-#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
+#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)
static USBFS_MIDI_RX_STATUS USBFS_MIDI1_Event; /* MIDI RX status structure */
static USBFS_MIDI_RX_STATUS USBFS_MIDI2_Event; /* MIDI RX status structure */
static volatile uint8 USBFS_MIDI2_TxRunStat; /* MIDI Output running status */
volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
/***************************************
{
#if (USBFS_MIDI_IN_BUFF_SIZE > 0)
USBFS_midiInPointer = 0u;
- #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
+ #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
#if (USBFS_MIDI_IN_BUFF_SIZE > 0)
/* Init DMA configurations for IN EP*/
USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer,
USBFS_MIDI_IN_BUFF_SIZE);
-
- #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
+
+ #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
/* Init DMA configurations for OUT EP*/
(void)USBFS_ReadOutEP(USBFS_midi_out_ep, USBFS_midiOutBuffer,
USBFS_MIDI_OUT_BUFF_SIZE);
- #endif /*USBFS_MIDI_OUT_BUFF_SIZE > 0 */
- #endif /* End USBFS__EP_DMAAUTO */
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */
+ #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
USBFS_EnableOutEP(USBFS_midi_out_ep);
- #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */
/* Initialize the MIDI port(s) */
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)
USBFS_MIDI_Init();
- #endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
}
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
#else
uint8 outLength;
uint8 outPointer;
- #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >=256 */
+ #endif /* USBFS_MIDI_OUT_BUFF_SIZE >=256 */
uint8 dmaState = 0u;
/* Service the USB MIDI output endpoint */
if (USBFS_GetEPState(USBFS_midi_out_ep) == USBFS_OUT_BUFFER_FULL)
{
- #if USBFS_MIDI_OUT_BUFF_SIZE >= 256
+ #if(USBFS_MIDI_OUT_BUFF_SIZE >= 256)
outLength = USBFS_GetEPCount(USBFS_midi_out_ep);
#else
outLength = (uint8)USBFS_GetEPCount(USBFS_midi_out_ep);
- #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */
+
#if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
- #if USBFS_MIDI_OUT_BUFF_SIZE >= 256
+ #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256)
outLength = USBFS_ReadOutEP(USBFS_midi_out_ep,
USBFS_midiOutBuffer, outLength);
#else
outLength = (uint8)USBFS_ReadOutEP(USBFS_midi_out_ep,
USBFS_midiOutBuffer, (uint16)outLength);
- #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */
+
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
do /* wait for DMA transfer complete */
{
- (void)CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState);
- }while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u);
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+ (void) CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState);
+ }
+ while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u);
+ #endif /* (USBFS_EP_MM == USBFS__EP_DMAMANUAL) */
+
+ #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */
+
if(dmaState != 0u)
{
/* Suppress compiler warning */
}
+
if (outLength >= USBFS_EVENT_LENGTH)
{
outPointer = 0u;
{
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
USBFS_MIDI2_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]);
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
}
else
{
/* `#END` */
}
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
/* Process any local MIDI output functions */
USBFS_callbackLocalMidiEvent(
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
/* Enable Out EP*/
USBFS_EnableOutEP(USBFS_midi_out_ep);
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+ #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */
}
}
#else /* USBFS_EP_MM != USBFS__EP_DMAAUTO */
/* rearm IN EP */
USBFS_LoadInEP(USBFS_midi_in_ep, NULL, (uint16)USBFS_midiInPointer);
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO*/
+ #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */
/* Clear the midiInPointer. For DMA mode, clear this pointer in the ARB ISR when data are moved by DMA */
#if(USBFS_EP_MM == USBFS__EP_MANUAL)
USBFS_midiInPointer = 0u;
- #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */
+ #endif /* (USBFS_EP_MM == USBFS__EP_MANUAL) */
}
}
}
uint8 m2 = 0u;
do
{
- if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
+ if (USBFS_midiInPointer <=
+ (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
{
/* Check MIDI1 input port for a complete event */
m1 = USBFS_MIDI1_GetEvent();
}
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
- if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
+ if (USBFS_midiInPointer <=
+ (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
{
/* Check MIDI2 input port for a complete event */
m2 = USBFS_MIDI2_GetEvent();
USBFS_MIDI2_Event.size, USBFS_MIDI_CABLE_01);
}
}
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
- }while( (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
- && ((m1 != 0u) || (m2 != 0u)) );
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+ }while( (USBFS_midiInPointer <=
+ (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) &&
+ ((m1 != 0u) || (m2 != 0u)) );
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
/* Service the USB MIDI input endpoint */
USBFS_MIDI_IN_EP_Service();
MIDI1_UART_DisableRxInt();
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
MIDI2_UART_DisableRxInt();
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
if (USBFS_midiInPointer >
(USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
(USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
{
USBFS_MIDI_IN_EP_Service();
- if (USBFS_midiInPointer >
- (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
+ if(USBFS_midiInPointer >
+ (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
{
/* Error condition. HOST is not ready to receive this packet. */
retError = USBFS_TRUE;
break;
}
}
- }while(ic > USBFS_EVENT_BYTE3);
+ }
+ while(ic > USBFS_EVENT_BYTE3);
if(retError == USBFS_FALSE)
{
MIDI1_UART_EnableRxInt();
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
MIDI2_UART_EnableRxInt();
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
return (retError);
}
/* Change the priority of the UART TX interrupt */
CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM);
CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM);
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/
/* `#START MIDI_INIT_CUSTOM` Init other extended UARTs here */
uint8 rxData;
#if (MIDI1_UART_RXBUFFERSIZE >= 256u)
uint16 rxBufferRead;
- #if CY_PSOC3 /* This local variable is required only for PSOC3 and large buffer */
+ #if (CY_PSOC3) /* This local variable is required only for PSOC3 and large buffer */
uint16 rxBufferWrite;
- #endif /* end CY_PSOC3 */
+ #endif /* (CY_PSOC3) */
#else
uint8 rxBufferRead;
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+ #endif /* (MIDI1_UART_RXBUFFERSIZE >= 256u) */
+
uint8 rxBufferLoopDetect;
/* Read buffer loop condition to the local variable */
rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect;
/* Protect variables that could change on interrupt by disabling Rx interrupt.*/
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntDisable(MIDI1_UART_RX_VECT_NUM);
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
rxBufferRead = MIDI1_UART_rxBufferRead;
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
rxBufferWrite = MIDI1_UART_rxBufferWrite;
CyIntEnable(MIDI1_UART_RX_VECT_NUM);
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
/* Stay here until either the buffer is empty or we have a complete message
* in the message buffer. Note that we must use a temporary buffer pointer
while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
#else
while ( ((rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
{
rxData = MIDI1_UART_rxBuffer[rxBufferRead];
/* Increment pointer with a wrap */
MIDI1_UART_rxBufferLoopDetect = 0u;
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntDisable(MIDI1_UART_RX_VECT_NUM);
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+ #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */
MIDI1_UART_rxBufferRead = rxBufferRead;
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntEnable(MIDI1_UART_RX_VECT_NUM);
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+ #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */
}
msgRtn = USBFS_ProcessMidiIn(rxData,
*/
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntDisable(MIDI1_UART_RX_VECT_NUM);
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
MIDI1_UART_rxBufferRead = rxBufferRead;
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntEnable(MIDI1_UART_RX_VECT_NUM);
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
}
return (msgRtn);
/* `#END` */
}
+
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
uint8 rxData;
#if (MIDI2_UART_RXBUFFERSIZE >= 256u)
uint16 rxBufferRead;
- #if CY_PSOC3 /* This local variable required only for PSOC3 and large buffer */
+ #if (CY_PSOC3) /* This local variable required only for PSOC3 and large buffer */
uint16 rxBufferWrite;
- #endif /* end CY_PSOC3 */
+ #endif /* (CY_PSOC3) */
#else
uint8 rxBufferRead;
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+ #endif /* (MIDI2_UART_RXBUFFERSIZE >= 256) */
+
uint8 rxBufferLoopDetect;
/* Read buffer loop condition to the local variable */
rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect;
/* Protect variables that could change on interrupt by disabling Rx interrupt.*/
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntDisable(MIDI2_UART_RX_VECT_NUM);
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
rxBufferRead = MIDI2_UART_rxBufferRead;
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
rxBufferWrite = MIDI2_UART_rxBufferWrite;
CyIntEnable(MIDI2_UART_RX_VECT_NUM);
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
/* Stay here until either the buffer is empty or we have a complete message
* in the message buffer. Note that we must use a temporary output pointer to
while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
#else
while ( ((rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
{
rxData = MIDI2_UART_rxBuffer[rxBufferRead];
rxBufferRead++;
MIDI2_UART_rxBufferLoopDetect = 0u;
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntDisable(MIDI2_UART_RX_VECT_NUM);
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
MIDI2_UART_rxBufferRead = rxBufferRead;
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntEnable(MIDI2_UART_RX_VECT_NUM);
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
}
msgRtn = USBFS_ProcessMidiIn(rxData,
*/
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntDisable(MIDI2_UART_RX_VECT_NUM);
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
MIDI2_UART_rxBufferRead = rxBufferRead;
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntEnable(MIDI2_UART_RX_VECT_NUM);
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
}
return (msgRtn);
/* `#END` */
}
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
-#endif /* End (USBFS_ENABLE_MIDI_API != 0u) */
+#endif /* (USBFS_ENABLE_MIDI_API != 0u) */
/* `#START MIDI_FUNCTIONS` Place any additional functions here */
/* `#END` */
-#endif /* End defined(USBFS_ENABLE_MIDI_STREAMING) */
+#endif /* defined(USBFS_ENABLE_MIDI_STREAMING) */
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_midi.h
-* Version 2.60
+* Version 2.80
*
* Description:
* Header File for the USBFS MIDI module.
* Contains prototypes and constant values.
*
+* Related Document:
+* Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0
+* MIDI 1.0 Detailed Specification Document Version 4.2
+*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
-* Data Struct Definition
+* Data Structure Definition
***************************************/
/* The following structure is used to hold status information for
#define USBFS_CUSTOM_UART_TX_PRIOR_NUM (0x04u)
#define USBFS_CUSTOM_UART_RX_PRIOR_NUM (0x02u)
-#define USBFS_ISR_SERVICE_MIDI_OUT \
+#define USBFS_ISR_SERVICE_MIDI_OUT \
( (USBFS_ENABLE_MIDI_API != 0u) && \
- (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO) )
+ (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO))
#define USBFS_ISR_SERVICE_MIDI_IN \
( (USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_IN_BUFF_SIZE > 0) )
+
/***************************************
* External function references
***************************************/
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)
#include "MIDI1_UART.h"
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
#include "MIDI2_UART.h"
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+#endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
#include <CyDmac.h>
-#endif /* End USBFS_EP_MM */
+#endif /* USBFS_EP_MM */
/***************************************
uint8 USBFS_MIDI2_GetEvent(void) ;
void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[])
;
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
/***************************************
extern volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */
#else
extern volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */
- #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */
+ #endif /* USBFS_MIDI_IN_BUFF_SIZE >=256 */
extern volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */
extern uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */
#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
extern volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
extern volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
#endif /* USBFS_ENABLE_MIDI_STREAMING */
-#endif /* End CY_USBFS_USBFS_midi_H */
+#endif /* CY_USBFS_USBFS_midi_H */
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_pm.c
-* Version 2.60
+* Version 2.80
*
* Description:
* This file provides Suspend/Resume APIs functionality.
* Note:
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#if(USBFS_DP_ISR_REMOVE == 0u)
-
/*******************************************************************************
* Function Name: USBFS_DP_Interrupt
********************************************************************************
********************************************************************************
*
* Summary:
-* This function disables the USBFS block and prepares for power donwn mode.
+* This function disables the USBFS block and prepares for power down mode.
*
* Parameters:
* None.
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
/* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */
USBFS_USBIO_CR0_REG &= (uint8)~USBFS_USBIO_CR0_TEN;
/* Disable the SIE */
USBFS_CR0_REG &= (uint8)~USBFS_CR0_ENABLE;
- CyDelayUs(0u); /*~50ns delay */
+ CyDelayUs(0u); /* ~50ns delay */
/* Store mode and Disable VRegulator*/
USBFS_backup.mode = USBFS_CR1_REG & USBFS_CR1_REG_ENABLE;
USBFS_CR1_REG &= (uint8)~USBFS_CR1_REG_ENABLE;
{
USBFS_backup.enableState = 0u;
}
+
CyExitCriticalSection(enableInterrupts);
/* Set the DP Interrupt for wake-up from sleep mode. */
#if(USBFS_DP_ISR_REMOVE == 0u)
- (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR);
+ (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR);
CyIntSetPriority(USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIOR);
CyIntClearPending(USBFS_DP_INTC_VECT_NUM);
CyIntEnable(USBFS_DP_INTC_VECT_NUM);
#endif /* (USBFS_DP_ISR_REMOVE == 0u) */
-
}
{
#if(USBFS_DP_ISR_REMOVE == 0u)
CyIntDisable(USBFS_DP_INTC_VECT_NUM);
- #endif /* End USBFS_DP_ISR_REMOVE */
+ #endif /* USBFS_DP_ISR_REMOVE */
/* Enable USB block */
USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB;
/* Set the USBIO pull-up enable */
USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N;
- /* Reinit Arbiter configuration for DMA transfers */
+ /* Re-init Arbiter configuration for DMA transfers */
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
- /* usb arb interrupt enable */
+ /* Usb arb interrupt enable */
USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
/*Set cfg cmplt this rises DMA request when the full configuration is done */
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
/* STALL_IN_OUT */
CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT);
/* Restore USB register settings */
USBFS_RestoreConfig();
-
}
+
CyExitCriticalSection(enableInterrupts);
}
/*******************************************************************************
* File Name: .h
-* Version 2.60
+* Version 2.80
*
* Description:
* This private file provides constants and parameter values for the
* Note:
*
********************************************************************************
-* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
extern uint8 USBFS_DmaChan[USBFS_MAX_EP];
extern uint8 USBFS_DmaTd[USBFS_MAX_EP];
-#endif /* End USBFS_EP_MM */
+#endif /* USBFS_EP_MM */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ extern uint8 USBFS_DmaNextTd[USBFS_MAX_EP];
+ extern const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP];
+ extern volatile uint16 USBFS_inLength[USBFS_MAX_EP];
+ extern const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];
+ extern volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
extern volatile uint8 USBFS_ep0Toggle;
extern volatile uint8 USBFS_lastPacketSize;
void USBFS_ConfigAltChanged(void) ;
void USBFS_ConfigReg(void) ;
-const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)
+const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)
;
const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void)
;
void USBFS_SaveConfig(void) ;
void USBFS_RestoreConfig(void) ;
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) ;
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */
+
#if defined(USBFS_ENABLE_IDSN_STRING)
void USBFS_ReadDieID(uint8 descr[]) ;
#endif /* USBFS_ENABLE_IDSN_STRING */
#if defined(USBFS_ENABLE_HID_CLASS)
uint8 USBFS_DispatchHIDClassRqst(void);
-#endif /* End USBFS_ENABLE_HID_CLASS */
+#endif /* USBFS_ENABLE_HID_CLASS */
#if defined(USBFS_ENABLE_AUDIO_CLASS)
uint8 USBFS_DispatchAUDIOClassRqst(void);
-#endif /* End USBFS_ENABLE_HID_CLASS */
+#endif /* USBFS_ENABLE_HID_CLASS */
#if defined(USBFS_ENABLE_CDC_CLASS)
uint8 USBFS_DispatchCDCClassRqst(void);
-#endif /* End USBFS_ENABLE_CDC_CLASS */
+#endif /* USBFS_ENABLE_CDC_CLASS */
CY_ISR_PROTO(USBFS_EP_0_ISR);
#if(USBFS_EP1_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_EP_1_ISR);
-#endif /* End USBFS_EP1_ISR_REMOVE */
+#endif /* USBFS_EP1_ISR_REMOVE */
#if(USBFS_EP2_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_EP_2_ISR);
-#endif /* End USBFS_EP2_ISR_REMOVE */
+#endif /* USBFS_EP2_ISR_REMOVE */
#if(USBFS_EP3_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_EP_3_ISR);
-#endif /* End USBFS_EP3_ISR_REMOVE */
+#endif /* USBFS_EP3_ISR_REMOVE */
#if(USBFS_EP4_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_EP_4_ISR);
-#endif /* End USBFS_EP4_ISR_REMOVE */
+#endif /* USBFS_EP4_ISR_REMOVE */
#if(USBFS_EP5_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_EP_5_ISR);
-#endif /* End USBFS_EP5_ISR_REMOVE */
+#endif /* USBFS_EP5_ISR_REMOVE */
#if(USBFS_EP6_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_EP_6_ISR);
-#endif /* End USBFS_EP6_ISR_REMOVE */
+#endif /* USBFS_EP6_ISR_REMOVE */
#if(USBFS_EP7_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_EP_7_ISR);
-#endif /* End USBFS_EP7_ISR_REMOVE */
+#endif /* USBFS_EP7_ISR_REMOVE */
#if(USBFS_EP8_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_EP_8_ISR);
-#endif /* End USBFS_EP8_ISR_REMOVE */
+#endif /* USBFS_EP8_ISR_REMOVE */
CY_ISR_PROTO(USBFS_BUS_RESET_ISR);
#if(USBFS_SOF_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_SOF_ISR);
-#endif /* End USBFS_SOF_ISR_REMOVE */
+#endif /* USBFS_SOF_ISR_REMOVE */
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
CY_ISR_PROTO(USBFS_ARB_ISR);
-#endif /* End USBFS_EP_MM */
+#endif /* USBFS_EP_MM */
#if(USBFS_DP_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_DP_ISR);
-#endif /* End USBFS_DP_ISR_REMOVE */
-
+#endif /* USBFS_DP_ISR_REMOVE */
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ CY_ISR_PROTO(USBFS_EP_DMA_DONE_ISR);
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */
/***************************************
* Request Handlers
/***************************************
* HID Internal references
***************************************/
+
#if defined(USBFS_ENABLE_HID_CLASS)
void USBFS_FindReport(void) ;
void USBFS_FindReportDescriptor(void) ;
/***************************************
* MIDI Internal references
***************************************/
+
#if defined(USBFS_ENABLE_MIDI_STREAMING)
void USBFS_MIDI_IN_EP_Service(void) ;
#endif /* USBFS_ENABLE_MIDI_STREAMING */
/*******************************************************************************
* File Name: USBFS_std.c
-* Version 2.60
+* Version 2.80
*
* Description:
* USB Standard request handler.
* Note:
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "USBFS.h"
#include "USBFS_cdc.h"
#include "USBFS_pvt.h"
-#if defined(USBFS_ENABLE_MIDI_STREAMING)
+#if defined(USBFS_ENABLE_MIDI_STREAMING)
#include "USBFS_midi.h"
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+#endif /* USBFS_ENABLE_MIDI_STREAMING*/
/***************************************
#if defined(USBFS_ENABLE_FWSN_STRING)
-
/*******************************************************************************
* Function Name: USBFS_SerialNumString
********************************************************************************
USBFS_snStringConfirm = USBFS_FALSE;
if(snString != NULL)
{
- USBFS_fwSerialNumberStringDescriptor = snString;
/* Check descriptor validation */
if( (snString[0u] > 1u ) && (snString[1u] == USBFS_DESCR_STRING) )
{
+ USBFS_fwSerialNumberStringDescriptor = snString;
USBFS_snStringConfirm = USBFS_TRUE;
}
}
{
uint8 requestHandled = USBFS_FALSE;
uint8 interfaceNumber;
+ uint8 configurationN;
#if defined(USBFS_ENABLE_STRINGS)
volatile uint8 *pStr = 0u;
#if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS)
else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_CONFIG)
{
pTmp = USBFS_GetConfigTablePtr(CY_GET_REG8(USBFS_wValueLo));
- USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;
- USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \
- USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \
- (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];
- requestHandled = USBFS_InitControlRead();
+ if( pTmp != NULL ) /* Verify that requested descriptor exists */
+ {
+ USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;
+ USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \
+ USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \
+ (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];
+ requestHandled = USBFS_InitControlRead();
+ }
}
#if defined(USBFS_ENABLE_STRINGS)
else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_STRING)
pStr = &pStr[descrLength];
nStr++;
}
- #endif /* End USBFS_ENABLE_DESCRIPTOR_STRINGS */
+ #endif /* USBFS_ENABLE_DESCRIPTOR_STRINGS */
/* Microsoft OS String*/
#if defined(USBFS_ENABLE_MSOS_STRING)
if( CY_GET_REG8(USBFS_wValueLo) == USBFS_STRING_MSOS )
{
pStr = (volatile uint8 *)&USBFS_MSOS_DESCRIPTOR[0u];
}
- #endif /* End USBFS_ENABLE_MSOS_STRING*/
+ #endif /* USBFS_ENABLE_MSOS_STRING*/
/* SN string */
#if defined(USBFS_ENABLE_SN_STRING)
if( (CY_GET_REG8(USBFS_wValueLo) != 0u) &&
(CY_GET_REG8(USBFS_wValueLo) ==
USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT]) )
{
- pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];
- #if defined(USBFS_ENABLE_FWSN_STRING)
- if(USBFS_snStringConfirm != USBFS_FALSE)
- {
- pStr = USBFS_fwSerialNumberStringDescriptor;
- }
- #endif /* USBFS_ENABLE_FWSN_STRING */
+
#if defined(USBFS_ENABLE_IDSN_STRING)
/* Read DIE ID and generate string descriptor in RAM */
USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor);
pStr = USBFS_idSerialNumberStringDescriptor;
- #endif /* End USBFS_ENABLE_IDSN_STRING */
+ #elif defined(USBFS_ENABLE_FWSN_STRING)
+ if(USBFS_snStringConfirm != USBFS_FALSE)
+ {
+ pStr = USBFS_fwSerialNumberStringDescriptor;
+ }
+ else
+ {
+ pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];
+ }
+ #else
+ pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];
+ #endif /* defined(USBFS_ENABLE_IDSN_STRING) */
}
- #endif /* End USBFS_ENABLE_SN_STRING */
+ #endif /* USBFS_ENABLE_SN_STRING */
if (*pStr != 0u)
{
USBFS_currentTD.count = *pStr;
requestHandled = USBFS_InitControlRead();
}
}
- #endif /* End USBFS_ENABLE_STRINGS */
+ #endif /* USBFS_ENABLE_STRINGS */
else
{
requestHandled = USBFS_DispatchClassRqst();
requestHandled = USBFS_InitNoDataControlTransfer();
break;
case USBFS_SET_CONFIGURATION:
- USBFS_configuration = CY_GET_REG8(USBFS_wValueLo);
- USBFS_configurationChanged = USBFS_TRUE;
- USBFS_Config(USBFS_TRUE);
- requestHandled = USBFS_InitNoDataControlTransfer();
+ configurationN = CY_GET_REG8(USBFS_wValueLo);
+ if(configurationN > 0u)
+ { /* Verify that configuration descriptor exists */
+ pTmp = USBFS_GetConfigTablePtr(configurationN - 1u);
+ }
+ /* Responds with a Request Error when configuration number is invalid */
+ if (((configurationN > 0u) && (pTmp != NULL)) || (configurationN == 0u))
+ {
+ /* Set new configuration if it has been changed */
+ if(configurationN != USBFS_configuration)
+ {
+ USBFS_configuration = configurationN;
+ USBFS_configurationChanged = USBFS_TRUE;
+ USBFS_Config(USBFS_TRUE);
+ }
+ requestHandled = USBFS_InitNoDataControlTransfer();
+ }
break;
case USBFS_SET_INTERFACE:
if (USBFS_ValidateAlternateSetting() != 0u)
USBFS_Config(USBFS_FALSE);
#else
USBFS_ConfigAltChanged();
- #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
+ #endif /* (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
/* Update handled Alt setting changes status */
USBFS_interfaceSetting_last[interfaceNumber] =
USBFS_interfaceSetting[interfaceNumber];
uint8 value;
const char8 CYCODE hex[16u] = "0123456789ABCDEF";
-
/* Check descriptor validation */
if( descr != NULL)
{
}
}
-#endif /* End USBFS_ENABLE_IDSN_STRING */
+#endif /* USBFS_ENABLE_IDSN_STRING */
/*******************************************************************************
uint8 ep;
uint8 i;
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
- uint8 ep_type = 0u;
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+ uint8 epType = 0u;
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
/* Set the endpoint buffer addresses */
ep = USBFS_EP1;
for (i = 0u; i < 0x80u; i+= 0x10u)
{
- CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_CRC_BYPASS |
- USBFS_ARB_EPX_CFG_RESET);
-
+ CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_DEFAULT);
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
/* Enable all Arbiter EP Interrupts : err, buf under, buf over, dma gnt(mode2 only), in buf full */
CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_INT_EN_IND + i), USBFS_ARB_EPX_INT_MASK);
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
if(USBFS_EP[ep].epMode != USBFS_MODE_DISABLE)
{
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_OUT);
/* Prepare EP type mask for automatic memory allocation */
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
- ep_type |= (uint8)(0x01u << (ep - USBFS_EP1));
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+ epType |= (uint8)(0x01u << (ep - USBFS_EP1));
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
}
}
else
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu);
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */
ep++;
}
USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST; /* DMA burst threshold */
USBFS_DMA_THRES_MSB_REG = 0u;
USBFS_EP_ACTIVE_REG = USBFS_ARB_INT_MASK;
- USBFS_EP_TYPE_REG = ep_type;
+ USBFS_EP_TYPE_REG = epType;
/* Cfg_cmp bit set to 1 once configuration is complete. */
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM |
USBFS_ARB_CFG_CFG_CPM;
/* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
CY_SET_REG8(USBFS_SIE_EP_INT_EN_PTR, 0xFFu);
}
uint8 ep;
uint8 cur_ep;
uint8 i;
- uint8 ep_type;
+ uint8 epType;
const uint8 *pDescr;
#if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
uint16 buffCount = 0u;
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */
const T_USBFS_LUT CYCODE *pTmp;
const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP;
pEP = (T_USBFS_EP_SETTINGS_BLOCK *) pTmp->p_list;
for (i = 0u; i < ep; i++)
{
- /* Compare current Alternate setting with EP Alt*/
+ /* Compare current Alternate setting with EP Alt */
if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)
{
cur_ep = pEP->addr & USBFS_DIR_UNUSED;
- ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;
+ epType = pEP->attributes & USBFS_EP_TYPE_MASK;
if (pEP->addr & USBFS_DIR_IN)
{
/* IN Endpoint */
USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;
- USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+ USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;
#if defined(USBFS_ENABLE_CDC_CLASS)
if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
(pEP->bMisc == USBFS_CLASS_CDC)) &&
- (ep_type != USBFS_EP_TYPE_INT))
+ (epType != USBFS_EP_TYPE_INT))
{
USBFS_cdc_data_in_ep = cur_ep;
}
- #endif /* End USBFS_ENABLE_CDC_CLASS*/
+ #endif /* USBFS_ENABLE_CDC_CLASS*/
#if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
(USBFS_MIDI_IN_BUFF_SIZE > 0) )
if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
- (ep_type == USBFS_EP_TYPE_BULK))
+ (epType == USBFS_EP_TYPE_BULK))
{
USBFS_midi_in_ep = cur_ep;
}
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/
}
else
{
/* OUT Endpoint */
USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;
- USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+ USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;
#if defined(USBFS_ENABLE_CDC_CLASS)
if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
(pEP->bMisc == USBFS_CLASS_CDC)) &&
- (ep_type != USBFS_EP_TYPE_INT))
+ (epType != USBFS_EP_TYPE_INT))
{
USBFS_cdc_data_out_ep = cur_ep;
}
- #endif /* End USBFS_ENABLE_CDC_CLASS*/
+ #endif /* USBFS_ENABLE_CDC_CLASS*/
#if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
(USBFS_MIDI_OUT_BUFF_SIZE > 0) )
if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
- (ep_type == USBFS_EP_TYPE_BULK))
+ (epType == USBFS_EP_TYPE_BULK))
{
USBFS_midi_out_ep = cur_ep;
}
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/
}
USBFS_EP[cur_ep].bufferSize = pEP->bufferSize;
USBFS_EP[cur_ep].addr = pEP->addr;
}
pEP = &pEP[1u];
}
- #else /* Config for static EP memory allocation */
+ #else /* Configure for static EP memory allocation */
for (i = USBFS_EP1; i < USBFS_MAX_EP; i++)
{
/* p_list points the endpoint setting table. */
/* Compare current Alternate setting with EP Alt*/
if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)
{
- ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;
+ epType = pEP->attributes & USBFS_EP_TYPE_MASK;
if ((pEP->addr & USBFS_DIR_IN) != 0u)
{
/* IN Endpoint */
USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING;
- USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+ USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;
- /* Find and init CDC IN endpoint number */
+ /* Find and initialize CDC IN endpoint number */
#if defined(USBFS_ENABLE_CDC_CLASS)
if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
(pEP->bMisc == USBFS_CLASS_CDC)) &&
- (ep_type != USBFS_EP_TYPE_INT))
+ (epType != USBFS_EP_TYPE_INT))
{
USBFS_cdc_data_in_ep = i;
}
- #endif /* End USBFS_ENABLE_CDC_CLASS*/
+ #endif /* USBFS_ENABLE_CDC_CLASS*/
#if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
(USBFS_MIDI_IN_BUFF_SIZE > 0) )
if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
- (ep_type == USBFS_EP_TYPE_BULK))
+ (epType == USBFS_EP_TYPE_BULK))
{
USBFS_midi_in_ep = i;
}
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/
}
else
{
/* OUT Endpoint */
USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING;
- USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+ USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;
- /* Find and init CDC IN endpoint number */
+ /* Find and initialize CDC IN endpoint number */
#if defined(USBFS_ENABLE_CDC_CLASS)
if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
(pEP->bMisc == USBFS_CLASS_CDC)) &&
- (ep_type != USBFS_EP_TYPE_INT))
+ (epType != USBFS_EP_TYPE_INT))
{
USBFS_cdc_data_out_ep = i;
}
- #endif /* End USBFS_ENABLE_CDC_CLASS*/
+ #endif /* USBFS_ENABLE_CDC_CLASS*/
#if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
(USBFS_MIDI_OUT_BUFF_SIZE > 0) )
if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
- (ep_type == USBFS_EP_TYPE_BULK))
+ (epType == USBFS_EP_TYPE_BULK))
{
USBFS_midi_out_ep = i;
}
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/
}
USBFS_EP[i].addr = pEP->addr;
USBFS_EP[i].attrib = pEP->attributes;
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
break; /* use first EP setting in Auto memory managment */
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
}
}
pEP = &pEP[1u];
}
}
- #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
+ #endif /* (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
/* Init class array for each interface and interface number for each EP.
* It is used for handling Class specific requests directed to either an
USBFS_EP[ep].buffOffset = buffCount;
buffCount += USBFS_EP[ep].bufferSize;
}
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */
/* Configure hardware registers */
USBFS_ConfigReg();
uint8 ep;
uint8 cur_ep;
uint8 i;
- uint8 ep_type;
+ uint8 epType;
uint8 ri;
const T_USBFS_LUT CYCODE *pTmp;
{
cur_ep = pEP->addr & USBFS_DIR_UNUSED;
ri = ((cur_ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
- ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;
+ epType = pEP->attributes & USBFS_EP_TYPE_MASK;
if ((pEP->addr & USBFS_DIR_IN) != 0u)
{
/* IN Endpoint */
USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;
- USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+ USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;
}
else
{
/* OUT Endpoint */
USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;
- USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+ USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;
}
/* Change the SIE mode for the selected EP to NAK ALL */
USBFS_EP[cur_ep].buffOffset & 0xFFu);
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ri),
USBFS_EP[cur_ep].buffOffset >> 8u);
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
}
/* Get next EP element */
pEP = &pEP[1u];
* This routine returns a pointer a configuration table entry
*
* Parameters:
-* c: Configuration Index
+* confIndex: Configuration Index
*
* Return:
-* Device Descriptor pointer.
+* Device Descriptor pointer or NULL when descriptor isn't exists.
*
*******************************************************************************/
-const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)
+const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)
{
/* Device Table */
/* The first entry points to the Device Descriptor,
* the rest configuration entries.
- */
- return( (const T_USBFS_LUT CYCODE *) pTmp[c + 1u].p_list );
+ * Set pointer to the first Configuration Descriptor
+ */
+ pTmp = &pTmp[1u];
+ /* For this table, c is the number of configuration descriptors */
+ if(confIndex >= pTmp->c) /* Verify that required configuration descriptor exists */
+ {
+ pTmp = (const T_USBFS_LUT CYCODE *) NULL;
+ }
+ else
+ {
+ pTmp = (const T_USBFS_LUT CYCODE *) pTmp[confIndex].p_list;
+ }
+
+ return( pTmp );
}
{
const T_USBFS_LUT CYCODE *pTmp;
+ const uint8 CYCODE *pInterfaceClass;
uint8 currentInterfacesNum;
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);
- currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];
- /* Third entry in the LUT starts the Interface Table pointers */
- /* The INTERFACE_CLASS table is located after all interfaces */
- pTmp = &pTmp[currentInterfacesNum + 2u];
- return( (const uint8 CYCODE *) pTmp->p_list );
+ if( pTmp != NULL )
+ {
+ currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];
+ /* Third entry in the LUT starts the Interface Table pointers */
+ /* The INTERFACE_CLASS table is located after all interfaces */
+ pTmp = &pTmp[currentInterfacesNum + 2u];
+ pInterfaceClass = (const uint8 CYCODE *) pTmp->p_list;
+ }
+ else
+ {
+ pInterfaceClass = (const uint8 CYCODE *) NULL;
+ }
+
+ return( pInterfaceClass );
}
/*******************************************************************************
* File Name: USBFS_vnd.c
-* Version 2.60
+* Version 2.80
*
* Description:
* USB vendor request handler.
* Note:
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* This routine provide users with a method to implement vendor specifc
+* This routine provide users with a method to implement vendor specific
* requests.
*
* To implement vendor specific requests, add your code in this function to
USBFS_currentTD.pData = (volatile uint8 *)&USBFS_MSOS_CONFIGURATION_DESCR[0u];
USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u];
requestHandled = USBFS_InitControlRead();
- #endif /* End USBFS_ENABLE_MSOS_STRING */
+ #endif /* USBFS_ENABLE_MSOS_STRING */
break;
default:
break;
*/
EXTERN(Reset)
-/* Bring in the interrupt routines & vector */
+/* Bring in interrupt routines & vector */
EXTERN(main)
-/* Bring in the meta data */
+/* Bring in meta data */
EXTERN(cy_meta_loader cy_bootloader cy_meta_loadable cy_meta_bootloader)
EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata)
PROVIDE(__cy_heap_start = _end);
PROVIDE(__cy_region_num = (__cy_regions_end - __cy_regions) / 16);
PROVIDE(__cy_stack = ORIGIN(ram) + LENGTH(ram));
-PROVIDE(__cy_heap_end = __cy_stack - 0x4000);
+PROVIDE(__cy_heap_end = __cy_stack - 0x1000);
SECTIONS
/* Make sure we pulled in some reset code. */
ASSERT (. != __cy_reset, "No reset code");
- /* Place the DMA initialization before text to ensure it gets placed in first 64K of flash */
+ /* Place DMA initialization before text to ensure it gets placed in first 64K of flash */
*(.dma_init)
ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash");
.heap (NOLOAD) :
{
. = _end;
- . += 0x1000;
+ . += 0x0400;
__cy_heap_limit = .;
} >ram
- .stack (__cy_stack - 0x4000) (NOLOAD) :
+ .stack (__cy_stack - 0x1000) (NOLOAD) :
{
__cy_stack_limit = .;
- . += 0x4000;
+ . += 0x1000;
} >ram
/* Check if data + heap + stack exceeds RAM limit */
/*******************************************************************************
* File Name: core_cm3_psoc5.h
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides important type information for the PSoC5. This includes types
* System Reference Guide provided with PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************************
* File Name: cyPm.c
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides an API for the power management.
* System Reference Guide provided with PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************
-* Place your includes, defines and code here. Do not use merge
-* region below unless any component datasheet suggest to do so.
+* Place your includes, defines, and code here. Do not use the merge
+* region below unless any component datasheet suggests doing so.
*******************************************************************/
/* `#START CY_PM_HEADER_INCLUDE` */
*
* Summary:
* This function is called in preparation for entering sleep or hibernate low
-* power modes. Saves all state of the clocking system that does not persist
-* during sleep/hibernate or that needs to be altered in preparation for
+* power modes. Saves all the states of the clocking system that do not persist
+* during sleep/hibernate or that need to be altered in preparation for
* sleep/hibernate. Shutdowns all the digital and analog clock dividers for the
* active power mode configuration.
*
cyPmClockBackup.imo2x = CY_PM_DISABLED;
}
+ /* Master clock - save source */
+ cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK;
+
+ /* Switch Master clock's source from PLL's output to PLL's source */
+ if(CY_MASTER_SOURCE_PLL == cyPmClockBackup.masterClkSrc)
+ {
+ switch (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_PLL_SRC_MASK)
+ {
+ case CY_PM_CLKDIST_PLL_SRC_IMO:
+ CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO);
+ break;
+
+ case CY_PM_CLKDIST_PLL_SRC_XTAL:
+ CyMasterClk_SetSource(CY_MASTER_SOURCE_XTAL);
+ break;
+
+ case CY_PM_CLKDIST_PLL_SRC_DSI:
+ CyMasterClk_SetSource(CY_MASTER_SOURCE_DSI);
+ break;
+
+ default:
+ CYASSERT(0u != 0u);
+ break;
+ }
+ }
+
+ /* PLL - check enable state, disable if needed */
+ if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE))
+ {
+ /* PLL is enabled - save state and disable */
+ cyPmClockBackup.pllEnableState = CY_PM_ENABLED;
+ CyPLL_OUT_Stop();
+ }
+ else
+ {
+ /* PLL is disabled - save state */
+ cyPmClockBackup.pllEnableState = CY_PM_DISABLED;
+ }
+
/* IMO - set appropriate frequency for LPM */
CyIMO_SetFreq(CY_PM_IMO_FREQ_LPM);
/* IMO - save disabled state */
cyPmClockBackup.imoEnable = CY_PM_DISABLED;
- /* IMO - enable */
+ /* Enable the IMO. Use software delay instead of the FTW-based inside */
CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE);
+
+ /* Settling time of the IMO is of the order of less than 6us */
+ CyDelayUs(6u);
}
/* IMO - save the current IMOCLK source and set to IMO if not yet */
cyPmClockBackup.imoClkSrc =
(0u == (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO2X_SRC)) ? CY_IMO_SOURCE_DSI : CY_IMO_SOURCE_XTAL;
- /* IMO - set IMOCLK source to MHz OSC */
+ /* IMO - set IMOCLK source to IMO */
CyIMO_SetSource(CY_IMO_SOURCE_IMO);
}
else
if(CY_PM_DIV_BY_ONE != cyPmClockBackup.clkSyncDiv)
{
CyMasterClk_SetDivider(CY_PM_DIV_BY_ONE);
- } /* Need to change nothing if master clock divider is 1 */
-
- /* Master clock - save current source */
- cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK;
+ } /* No change if master clock divider is 1 */
/* Master clock source - set it to IMO if not yet. */
if(CY_MASTER_SOURCE_IMO != cyPmClockBackup.masterClkSrc)
{
CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO);
- } /* Need to change nothing if master clock source is IMO */
+ } /* No change if master clock source is IMO */
/* Bus clock - save divider and set it, if needed, to divide-by-one */
cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u);
CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE);
} /* Do nothing if saved and actual values are equal */
- /* Set number of wait cycles for the flash according CPU frequency in MHz */
+ /* Set number of wait cycles for flash according to CPU frequency in MHz */
CyFlash_SetWaitCycles((uint8)CY_PM_GET_CPU_FREQ_MHZ);
- /* PLL - check enable state, disable if needed */
- if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE))
- {
- /* PLL is enabled - save state and disable */
- cyPmClockBackup.pllEnableState = CY_PM_ENABLED;
- CyPLL_OUT_Stop();
- }
- else
- {
- /* PLL is disabled - save state */
- cyPmClockBackup.pllEnableState = CY_PM_DISABLED;
- }
-
/* MHz ECO - check enable state and disable if needed */
if(0u != (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_ENABLE))
{
/***************************************************************************
- * Save enable state of delay between the system bus clock and each of the
- * 4 individual analog clocks. This bit non-retention and it's value should
+ * Save the enable state of delay between the system bus clock and each of the
+ * 4 individual analog clocks. This bit non-retention and its value should
* be restored on wakeup.
***************************************************************************/
if(0u != (CY_PM_CLKDIST_DELAY_REG & CY_PM_CLKDIST_DELAY_EN))
*
* PSoC 3 and PSoC 5LP:
* The merge region could be used to process state when the megahertz crystal is
-* not ready after the hold-off timeout.
+* not ready after a hold-off timeout.
*
* PSoC 5:
-* The 130 ms is given for the megahertz crystal to stabilize. It's readiness is
-* not verified after the hold-off timeout.
+* The 130 ms is given for the megahertz crystal to stabilize. Its readiness is
+* not verified after a hold-off timeout.
*
* Parameters:
* None
CY_IMO_FREQ_12MHZ, CY_IMO_FREQ_6MHZ, CY_IMO_FREQ_24MHZ, CY_IMO_FREQ_3MHZ,
CY_IMO_FREQ_48MHZ, 5u, 6u};
- /* Restore enable state of delay between the system bus clock and ACLKs. */
+ /* Restore enable state of delay between system bus clock and ACLKs. */
if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay)
{
- /* Delay for both the bandgap and the delay line to settle out */
+ /* Delay for both bandgap and delay line to settle out */
CyDelayCycles((uint32)(CY_PM_CLK_DELAY_BANDGAP_SETTLE_US + CY_PM_CLK_DELAY_BIAS_SETTLE_US) *
CY_PM_GET_CPU_FREQ_MHZ);
if(CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState)
{
/***********************************************************************
- * Enabling XMHZ XTAL. The actual CyXTAL_Start() with non zero wait
+ * Enabling XMHZ XTAL. The actual CyXTAL_Start() with a non zero wait
* period uses FTW for period measurement. This could cause a problem
* if CTW/FTW is used as a wake up time in the low power modes APIs.
* So, the XTAL wait procedure is implemented with a software delay.
{
/*******************************************************************
* Process the situation when megahertz crystal is not ready.
- * Time to stabialize value is crystal specific.
+ * Time to stabilize the value is crystal specific.
*******************************************************************/
/* `#START_MHZ_ECO_TIMEOUT` */
} /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */
- /* Temprorary set the maximum flash wait cycles */
+ /* Temprorary set maximum flash wait cycles */
CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES);
- /* The XTAL and DSI clocks are ready to be source for Master clock. */
+ /* XTAL and DSI clocks are ready to be source for Master clock. */
if((CY_PM_MASTER_CLK_SRC_XTAL == cyPmClockBackup.masterClkSrc) ||
(CY_PM_MASTER_CLK_SRC_DSI == cyPmClockBackup.masterClkSrc))
{
CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE);
}
- /* IMO - restore disable state if needed */
- if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) &&
- (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)))
- {
- CyIMO_Stop();
- }
-
/* IMO - restore IMOCLK source */
CyIMO_SetSource(cyPmClockBackup.imoClkSrc);
cyPmClockBackup.clkImoSrc;
}
+
/* PLL restore state */
if(CY_PM_ENABLED == cyPmClockBackup.pllEnableState)
{
* as a wakeup time in the low power modes APIs. To omit this issue PLL
* wait procedure is implemented with a software delay.
***********************************************************************/
+ status = CYRET_TIMEOUT;
/* Enable PLL */
(void) CyPLL_OUT_Start(CY_PM_PLL_OUT_NO_WAIT);
- /* Make a 250 us delay */
- CyDelayCycles((uint32)CY_PM_WAIT_250_US * CY_PM_GET_CPU_FREQ_MHZ);
+ /* Read to clear lock status after delay */
+ CyDelayUs((uint32)80u);
+ (void) CY_PM_FASTCLK_PLL_SR_REG;
+
+ /* It should take 250 us lock: 251-80 = 171 */
+ for(i = 171u; i > 0u; i--)
+ {
+ CyDelayUs((uint32)1u);
+
+ /* Accept PLL is OK after two consecutive polls indicate PLL lock */
+ if((0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED)) &&
+ (0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED)))
+ {
+ status = CYRET_SUCCESS;
+ break;
+ }
+ }
+
+ if(CYRET_TIMEOUT == status)
+ {
+ /*******************************************************************
+ * Process the situation when PLL is not ready.
+ *******************************************************************/
+ /* `#START_PLL_TIMEOUT` */
+
+ /* `#END` */
+ }
} /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */
CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc);
}
+ /* IMO - disable if it was originally disabled */
+ if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) &&
+ (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)))
+ {
+ CyIMO_Stop();
+ }
+
/* Bus clock - restore divider, if needed */
clkBusDivTmp = (uint16) ((uint16)CY_PM_CLK_BUS_MSB_DIV_REG << 8u);
clkBusDivTmp |= CY_PM_CLK_BUS_LSB_DIV_REG;
* Sleep Timer component and one second interval should be configured with the
* RTC component.
*
-* The wakeup behavior depends on wakeupSource parameter in the following
+* The wakeup behavior depends on the wakeupSource parameter in the following
* manner: upon function execution the device will be switched from Active to
* Alternate Active mode and then the CPU will be halted. When an enabled wakeup
* event occurs the device will return to Active mode. Similarly when an
For PSoC 3 silicon the valid range of values is 1 to 256.
*
* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if
-* a wakeupTime has been specified the associated timer will be
+* a wakeupTime has been specified, the associated timer will be
* included as a wakeup source.
*
* Define Source
* *Note : FTW and HVI/LVI wakeup signals are in the same mask bit.
* **Note: CTW and One PPS wakeup signals are in the same mask bit.
*
-* When specifying a Comparator as the wakeupSource an instance specific define
-* should be used that will track with the specific comparator that the instance
-* is placed into. As an example, for a Comparator instance named MyComp the
+* When specifying a Comparator as the wakeupSource, an instance specific define
+* that will track with the specific comparator that the instance
+* is placed into should be used. As an example, for a Comparator instance named MyComp the
* value to OR into the mask is: MyComp_ctComp__CMP_MASK.
*
* When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus()
-* function must be called upon wakeup with corresponding parameter. Please
+* function must be called upon wakeup with a corresponding parameter. Please
* refer to the CyPmReadStatus() API in the System Reference Guide for more
* information.
*
* If a wakeupTime other than NONE is specified, then upon exit the state of the
* specified timer will be left as specified by wakeupTime with the timer
* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is
-* used as wakeup time) or ILO 100 KHz (if FTW timer is used as wakeup time)
+* used as wakeup time) or ILO 100 KHz (if the FTW timer is used as wakeup time)
* will be left started.
*
*******************************************************************************/
{
CyPmFtwSetInterval(PM_ALT_ACT_FTW_INTERVAL(wakeupTime));
- /* Include associated timer to the wakeupSource */
+ /* Include associated timer to wakeupSource */
wakeupSource |= PM_ALT_ACT_SRC_FTW;
}
/* Save current CTW configuration and set new one */
CyPmCtwSetInterval((uint8)(wakeupTime - 1u));
- /* Include associated timer to the wakeupSource */
+ /* Include associated timer to wakeupSource */
wakeupSource |= PM_ALT_ACT_SRC_CTW;
}
/* Save current 1PPS configuration and set new one */
CyPmOppsSet();
- /* Include associated timer to the wakeupSource */
+ /* Include associated timer to wakeupSource */
wakeupSource |= PM_ALT_ACT_SRC_ONE_PPS;
}
* Puts the part into the Sleep state.
*
* Note Before calling this function, you must manually configure the power
-* mode of the source clocks for the timer that is used as wakeup timer.
+* mode of the source clocks for the timer that is used as the wakeup timer.
*
* Note Before calling this function, you must prepare clock tree configuration
* for the low power mode by calling CyPmSaveClocks(). And restore clock
* PSoC 3:
* Before switching to Sleep, if a wakeupTime other than NONE is specified,
* then the appropriate timer state is configured as specified with the
-* interrupt for that timer disabled. The wakeup source will be the combination
+* interrupt for that timer disabled. The wakeup source will be a combination
* of the values specified in the wakeupSource and any timer specified in the
* wakeupTime argument. Once the wakeup condition is satisfied, then all saved
* state is restored and the function returns in the Active state.
* The wakeupTime parameter is not used and the only NONE can be specified.
* The wakeup time must be configured with the component, SleepTimer for CTW
* intervals and RTC for 1PPS interval. The component must be configured to
-* generate an interrrupt.
+* generate interrupt.
*
* Parameters:
* wakeupTime: Specifies a timer wakeup source and the frequency of that
* detect (power supply supervising capabilities) are required in a design
* during sleep, use the Central Time Wheel (CTW) to periodically wake the
* device, perform software buzz, and refresh the supervisory services. If LVI,
-* HVI, or Brown Out is not required, then use of the CTW is not required.
+* HVI, or Brown Out is not required, then CTW is not required.
* Refer to the device errata for more information.
*
*******************************************************************************/
/***********************************************************************
* PSoC3 < TO6:
- * - Hardware buzz must be disabled before sleep mode entry.
+ * - Hardware buzz must be disabled before the sleep mode entry.
* - Voltage supervision (HVI/LVI) requires hardware buzz, so they must
- * be aslo disabled.
+ * be also disabled.
*
* PSoC3 >= TO6:
- * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware buzz must be
- * enabled before sleep mode entry and restored on wakeup.
+ * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware
+ * buzz must be enabled before the sleep mode entry and restored on
+ * the wakeup.
***********************************************************************/
#if(CY_PSOC3)
/*******************************************************************************
- * For ARM-based devices, an interrupt is required for the CPU to wake up. The
+ * For ARM-based devices,interrupt is required for the CPU to wake up. The
* Power Management implementation assumes that wakeup time is configured with a
- * separate component (component-based wakeup time configuration) for an
+ * separate component (component-based wakeup time configuration) for
* interrupt to be issued on terminal count. For more information, refer to the
* Wakeup Time Configuration section of System Reference Guide.
*******************************************************************************/
/* CTW - save current and set new configuration */
if((wakeupTime >= PM_SLEEP_TIME_CTW_2MS) && (wakeupTime <= PM_SLEEP_TIME_CTW_4096MS))
{
- /* Save current and set new configuration of the CTW */
+ /* Save current and set new configuration of CTW */
CyPmCtwSetInterval((uint8)(wakeupTime - 1u));
- /* Include associated timer to the wakeupSource */
+ /* Include associated timer to wakeupSource */
wakeupSource |= PM_SLEEP_SRC_CTW;
}
/* Save current and set new configuration of the 1PPS */
CyPmOppsSet();
- /* Include associated timer to the wakeupSource */
+ /* Include associated timer to wakeupSource */
wakeupSource |= PM_SLEEP_SRC_ONE_PPS;
}
/*******************************************************************
- * Do not use merge region below unless any component datasheet
- * suggest to do so.
+ * Do not use the merge region below unless any component datasheet
+ * suggests doing so.
*******************************************************************/
/* `#START CY_PM_JUST_BEFORE_SLEEP` */
CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK));
}
- /* Switch to the Sleep mode */
+ /* Switch to Sleep mode */
CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_SLEEP);
/* Recommended readback. */
(void) CY_PM_MODE_CSR_REG;
- /* Two recommended NOPs to get into the mode. */
+ /* Two recommended NOPs to get into mode. */
CY_NOP;
CY_NOP;
* PSoC 3 and PSoC 5LP:
* Before switching to Hibernate, the current status of the PICU wakeup source
* bit is saved and then set. This configures the device to wake up from the
-* PICU. Make sure you have at least one pin configured to generate a PICU
+* PICU. Make sure you have at least one pin configured to generate PICU
* interrupt. For pin Px.y, the register "PICU_INTTYPE_PICUx_INTTYPEy" controls
* the PICU behavior. In the TRM, this register is "PICU[0..15]_INTTYPE[0..7]."
* In the Pins component datasheet, this register is referred to as the IRQ
* requirement begins when the device wakes up. There is no hardware check that
* this requirement is met. The specified delay should be done on ISR entry.
*
-* After wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is
+* After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is
* instance name of the Pins component) function must be called to clear the
-* latched pin events to allow proper Hibernate mode entry andd to enable
+* latched pin events to allow the proper Hibernate mode entry and to enable
* detection of future events.
*
* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to
* measure Hibernate/Sleep regulator settling time after a reset. The holdoff
-* delay is measured using rising edges of the 1 kHz ILO.
+* delay is measured using the rising edges of the 1 kHz ILO.
*
*******************************************************************************/
void CyPmHibernate(void)
/***********************************************************************
* The Hibernate/Sleep regulator has a settling time after a reset.
- * During this time, the system ignores requests to enter Sleep and
- * Hibernate modes. The holdoff delay is measured using rising edges of
+ * During this time, the system ignores requests to enter the Sleep and
+ * Hibernate modes. The holdoff delay is measured using the rising edges of
* the 1 kHz ILO.
***********************************************************************/
if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q))
/* Recommended readback. */
(void) CY_PM_MODE_CSR_REG;
- /* Two recommended NOPs to get into the mode. */
+ /* Two recommended NOPs to get into mode. */
CY_NOP;
CY_NOP;
/* Enter critical section */
interruptState = CyEnterCriticalSection();
- /* Save value of the register, copy it and clear desired bit */
+ /* Save value of register, copy it and clear desired bit */
interruptStatus |= CY_PM_INT_SR_REG;
tmpStatus = interruptStatus;
interruptStatus &= ((uint8)(~mask));
if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP))
{
/***********************************************************************
- * If I2C backup regulator is enabled, all the fixed-function registers
- * store their values while device is in low power mode, otherwise their
+ * If the I2C backup regulator is enabled, all the fixed-function registers
+ * store their values while the device is in the low power mode, otherwise their
* configuration is lost. The I2C API makes a decision to restore or not
* to restore I2C registers based on this. If this regulator will be
- * disabled and then enabled, I2C API will suppose that I2C block
+ * disabled and then enabled, I2C API will suppose that the I2C block
* registers preserved their values, while this is not true. So, the
* backup regulator is disabled. The I2C sleep APIs is responsible for
* restoration.
/***************************************************************************
- * Save and set power mode wakeup trim registers
+ * Save and set the power mode wakeup trim registers
***************************************************************************/
cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG;
cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG;
********************************************************************************
*
* Summary:
-* Restore device for proper Hibernate mode exit:
-* - Restore LVI/HVI configuration - call CyPmHviLviRestore()
+* Restores the device for the proper Hibernate mode exit:
+* - Restores LVI/HVI configuration - calsl CyPmHviLviRestore()
* - CyPmHibSlpSaveRestore() function is called
-* - Restores ILO power down mode state and enable it
-* - Restores state of 1 kHz and 100 kHz ILO and disable them
-* - Restores sleep regulator settings
+* - Restores ILO power down mode state and enables it
+* - Restores the state of 1 kHz and 100 kHz ILO and disables them
+* - Restores the sleep regulator settings
*
* Parameters:
* None
/***************************************************************************
- * Restore power mode wakeup trim registers
+ * Restore the power mode wakeup trim registers
***************************************************************************/
CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0;
CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1;
********************************************************************************
*
* Summary:
-* Performs CTW configuration:
-* - Disables CTW interrupt
+* Performs the CTW configuration:
+* - Disables the CTW interrupt
* - Enables 1 kHz ILO
-* - Sets new CTW interval
+* - Sets a new CTW interval
*
* Parameters:
* ctwInterval: the CTW interval to be set.
/* Set CTW interval if needed */
if(CY_PM_TW_CFG1_REG != ctwInterval)
{
- /* Set the new CTW interval. Could be changed if CTW is disabled */
+ /* Set new CTW interval. Could be changed if CTW is disabled */
CY_PM_TW_CFG1_REG = ctwInterval;
} /* Required interval is already set */
- /* Enable the CTW */
+ /* Enable CTW */
CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN;
}
}
* Summary:
* Performs 1PPS configuration:
* - Starts 32 KHz XTAL
-* - Disables 1PPS interupts
+* - Disables 1PPS interrupts
* - Enables 1PPS
*
* Parameters:
********************************************************************************
*
* Summary:
-* Performs FTW configuration:
-* - Disables FTW interrupt
+* Performs the FTW configuration:
+* - Disables the FTW interrupt
* - Enables 100 kHz ILO
-* - Sets new FTW interval.
+* - Sets a new FTW interval.
*
* Parameters:
* ftwInterval - FTW counter interval.
* None
*
* Side Effects:
-* Enables ILO 100 KHz clock and leaves it enabled.
+* Enables the ILO 100 KHz clock and leaves it enabled.
*
*******************************************************************************/
void CyPmFtwSetInterval(uint8 ftwInterval)
/* Enable 100kHz ILO */
CyILO_Start100K();
- /* Iterval could be set only while FTW is disabled */
+ /* Interval could be set only while FTW is disabled */
if(0u != (CY_PM_TW_CFG2_REG & CY_PM_FTW_EN))
{
/* Disable FTW, set new FTW interval if needed and enable it again */
if(CY_PM_TW_CFG0_REG != ftwInterval)
{
- /* Disable the CTW, set new CTW interval and enable it again */
+ /* Disable CTW, set new CTW interval and enable it again */
CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_EN));
CY_PM_TW_CFG0_REG = ftwInterval;
CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN;
/* Set new FTW counter interval if needed. FTW is disabled. */
if(CY_PM_TW_CFG0_REG != ftwInterval)
{
- /* Set the new CTW interval. Could be changed if CTW is disabled */
+ /* Set new CTW interval. Could be changed if CTW is disabled */
CY_PM_TW_CFG0_REG = ftwInterval;
} /* Required interval is already set */
- /* Enable the FTW */
+ /* Enable FTW */
CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN;
}
}
********************************************************************************
*
* Summary:
-* This API is used for preparing device for Sleep and Hibernate low power
+* This API is used for preparing the device for the Sleep and Hibernate low power
* modes entry:
-* - Saves COMP, VIDAC, DSM and SAR routing connections (PSoC 5)
-* - Saves SC/CT routing connections (PSoC 3/5/5LP)
-* - Disables Serial Wire Viewer (SWV) (PSoC 3)
-* - Save boost reference selection and set it to internal
+* - Saves the COMP, VIDAC, DSM, and SAR routing connections (PSoC 5)
+* - Saves the SC/CT routing connections (PSoC 3/5/5LP)
+* - Disables the Serial Wire Viewer (SWV) (PSoC 3)
+* - Saves the boost reference selection and sets it to internal
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* This API is used for restoring device configurations after wakeup from Sleep
+* This API is used for restoring the device configurations after wakeup from the Sleep
* and Hibernate low power modes:
-* - Restores SC/CT routing connections
-* - Restores enable state of Serial Wire Viewer (SWV) (PSoC 3)
-* - Restore boost reference selection
+* - Restores the SC/CT routing connections
+* - Restores the enable state of the Serial Wire Viewer (SWV) (PSoC 3)
+* - Restores the boost reference selection
*
* Parameters:
* None
cyPmBackup.lvidEn = CY_PM_ENABLED;
cyPmBackup.lvidTrip = CY_VD_LVI_TRIP_REG & CY_VD_LVI_TRIP_LVID_MASK;
- /* Save state of reset device at a specified Vddd threshold */
+ /* Save state of reset device at specified Vddd threshold */
cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \
CY_PM_DISABLED : CY_PM_ENABLED;
cyPmBackup.lviaEn = CY_PM_ENABLED;
cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u;
- /* Save state of reset device at a specified Vdda threshold */
+ /* Save state of reset device at specified Vdda threshold */
cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \
CY_PM_DISABLED : CY_PM_ENABLED;
********************************************************************************
*
* Summary:
-* Restores analog and digital LVI and HVI configuration.
+* Restores the analog and digital LVI and HVI configuration.
*
* Parameters:
* None
/*******************************************************************************
* File Name: cyPm.h
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides the function definitions for the power management API.
* System Reference Guide provided with PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#if(CY_PSOC3)
- /* Wake up time for the Sleep mode */
+ /* Wake up time for Sleep mode */
#define PM_SLEEP_TIME_ONE_PPS (0x01u)
#define PM_SLEEP_TIME_CTW_2MS (0x02u)
#define PM_SLEEP_TIME_CTW_4MS (0x03u)
/* Difference between parameter's value and register's one */
#define CY_PM_FTW_INTERVAL_SHIFT (0x000Eu)
- /* Wake up time for the Alternate Active mode */
+ /* Wake up time for Alternate Active mode */
#define PM_ALT_ACT_TIME_ONE_PPS (0x0001u)
#define PM_ALT_ACT_TIME_CTW_2MS (0x0002u)
#define PM_ALT_ACT_TIME_CTW_4MS (0x0003u)
#endif /* (CY_PSOC3) */
-/* Wake up sources for the Sleep mode */
+/* Wake up sources for Sleep mode */
#define PM_SLEEP_SRC_COMPARATOR0 (0x0001u)
#define PM_SLEEP_SRC_COMPARATOR1 (0x0002u)
#define PM_SLEEP_SRC_COMPARATOR2 (0x0004u)
#define PM_SLEEP_SRC_ONE_PPS (0x0800u)
#define PM_SLEEP_SRC_LCD (0x1000u)
-/* Wake up sources for the Alternate Active mode */
+/* Wake up sources for Alternate Active mode */
#define PM_ALT_ACT_SRC_COMPARATOR0 (0x0001u)
#define PM_ALT_ACT_SRC_COMPARATOR1 (0x0002u)
#define PM_ALT_ACT_SRC_COMPARATOR2 (0x0004u)
#define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (5u)
-/* Delay line bandgap current settling time starting from a wakeup event */
+/* Delay line bandgap current settling time starting from wakeup event */
#define CY_PM_CLK_DELAY_BANDGAP_SETTLE_US (50u)
/* Delay line internal bias settling */
#if(CY_PSOC5)
- /* The CPU clock is directly derived from bus clock */
+ /* CPU clock is directly derived from bus clock */
#define CY_PM_GET_CPU_FREQ_MHZ (cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK])
#endif /* (CY_PSOC5) */
/*******************************************************************************
* The low power mode entry is different for PSoC 3 and PSoC 5 devices. The low
* power modes in PSoC 5 devices are invoked by Wait-For-Interrupt (WFI)
-* instruction. The ARM compilers has __wfi() instristic that inserts a WFI
+* instruction. The ARM compilers has __wfi() intrinsic that inserts a WFI
* instruction into the instruction stream generated by the compiler. The GCC
* compiler has to execute assembly language instruction.
*******************************************************************************/
/*******************************************************************************
* This macro defines the IMO frequency that will be set by CyPmSaveClocks()
* function based on Enable Fast IMO during Startup option from the DWR file.
-* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering
+* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering the
* low power mode and restore IMO back to the value set by CyPmSaveClocks()
* immediately on wakeup.
*******************************************************************************/
/* CyPmSaveClocks()/CyPmRestoreClocks() */
uint8 enClkA; /* Analog clocks enable */
uint8 enClkD; /* Digital clocks enable */
- uint8 masterClkSrc; /* The Master clock source */
+ uint8 masterClkSrc; /* Master clock source */
uint8 imoFreq; /* IMO frequency (reg's value) */
uint8 imoUsbClk; /* IMO USB CLK (reg's value) */
uint8 flashWaitCycles; /* Flash wait cycles */
uint8 clkImoSrc;
uint8 imo2x; /* IMO doubler enable state */
uint8 clkSyncDiv; /* Master clk divider */
- uint16 clkBusDiv; /* The clk_bus divider */
+ uint16 clkBusDiv; /* clk_bus divider */
uint8 pllEnableState; /* PLL enable state */
uint8 xmhzEnableState; /* XM HZ enable state */
uint8 clkDistDelay; /* Delay for clk_bus and ACLKs */
#define CY_PM_BOOST_CR2_REG (* (reg8 *) CYREG_BOOST_CR2 )
#define CY_PM_BOOST_CR2_PTR ( (reg8 *) CYREG_BOOST_CR2 )
+#if(CY_PSOC3)
+
+ /* Interrrupt Controller Configuration and Status Register */
+ #define CY_PM_INTC_CSR_EN_REG (* (reg8 *) CYREG_INTC_CSR_EN )
+ #define CY_PM_INTC_CSR_EN_PTR ( (reg8 *) CYREG_INTC_CSR_EN )
+
+#endif /* (CY_PSOC3) */
+
/***************************************
* Register Constants
#define CY_PM_CLKDIST_IMO_OUT_IMO (0x00u)
#define CY_PM_CLKDIST_IMO2X_SRC (0x40u)
-/* Waiting for the hibernate/sleep regulator to stabilize */
+#define CY_PM_CLKDIST_PLL_SRC_MASK (0x03u)
+#define CY_PM_CLKDIST_PLL_SRC_IMO (0x00u)
+#define CY_PM_CLKDIST_PLL_SRC_XTAL (0x01u)
+#define CY_PM_CLKDIST_PLL_SRC_DSI (0x02u)
+
+/* Waiting for hibernate/sleep regulator to stabilize */
#define CY_PM_MODE_CSR_PWRUP_PULSE_Q (0x08u)
#define CY_PM_MODE_CSR_ACTIVE (0x00u) /* Active power mode */
/* I2C regulator backup enable */
#define CY_PM_PWRSYS_CR1_I2CREG_BACKUP (0x04u)
-/* When set, prepares the system to disable the LDO-A */
+/* When set, prepares system to disable LDO-A */
#define CY_PM_PWRSYS_CR1_LDOA_ISO (0x01u)
-/* When set, disables the analog LDO regulator */
+/* When set, disables analog LDO regulator */
#define CY_PM_PWRSYS_CR1_LDOA_DIS (0x02u)
#define CY_PM_PWRSYS_WAKE_TR2_VCCD_CLK_DET (0x04u)
/* Bus Clock divider to divide-by-one */
#define CY_PM_BUS_CLK_DIV_BY_ONE (0x00u)
-/* HVI/LVI feature on the external analog and digital supply mask */
+/* HVI/LVI feature on external analog and digital supply mask */
#define CY_PM_RESET_CR1_HVI_LVI_EN_MASK (0x07u)
-/* The high-voltage-interrupt feature on the external analog supply */
+/* High-voltage-interrupt feature on external analog supply */
#define CY_PM_RESET_CR1_HVIA_EN (0x04u)
-/* The low-voltage-interrupt feature on the external analog supply */
+/* Low-voltage-interrupt feature on external analog supply */
#define CY_PM_RESET_CR1_LVIA_EN (0x02u)
-/* The low-voltage-interrupt feature on the external digital supply */
+/* Low-voltage-interrupt feature on external digital supply */
#define CY_PM_RESET_CR1_LVID_EN (0x01u)
-/* Allows the system to program delays on clk_sync_d */
+/* Allows system to program delays on clk_sync_d */
#define CY_PM_CLKDIST_DELAY_EN (0x04u)
#endif /* (CY_PSOC3) */
-/* Disable the sleep regulator and shorts vccd to vpwrsleep */
+/* Disables sleep regulator and shorts vccd to vpwrsleep */
#define CY_PM_PWRSYS_SLP_TR_BYPASS (0x10u)
/* Boost Control 2: Select external precision reference */
#endif /* (CY_PSOC5) */
+#if(CY_PSOC3)
+
+ /* Interrrupt Controller Configuration and Status Register */
+ #define CY_PM_INTC_CSR_EN_CLK (0x01u)
+
+#endif /* (CY_PSOC3) */
+
+
+/*******************************************************************************
+* Lock Status Flag. If lock is acquired this flag will stay set (regardless of
+* whether lock is subsequently lost) until it is read. Upon reading it will
+* clear. If lock is still true then the bit will simply set again. If lock
+* happens to be false when the clear on read occurs then the bit will stay
+* cleared until the next lock event.
+*******************************************************************************/
+#define CY_PM_FASTCLK_PLL_LOCKED (0x01u)
+
/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.30
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+* #ifdef <OBSOLETED_DEFINE>
+* #undef <OBSOLETED_DEFINE>
+* #define <OBSOLETED_DEFINE> (<New Value>)
+* #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+* used in the application and their modification might lead to unexpected
+* consequences.
*******************************************************************************/
#if(CY_PSOC3)
const uint8 cy_bootloader[] = {
0x00u, 0x40u, 0x00u, 0x20u, 0x11u, 0x00u, 0x00u, 0x00u,
0x59u, 0x01u, 0x00u, 0x00u, 0x59u, 0x01u, 0x00u, 0x00u,
- 0x08u, 0xB5u, 0x04u, 0x4Bu, 0x04u, 0x48u, 0x1Au, 0x68u,
- 0x02u, 0x60u, 0x00u, 0xF0u, 0x87u, 0xFCu, 0x00u, 0xF0u,
- 0x9Du, 0xF8u, 0x00u, 0xBFu, 0xFAu, 0x46u, 0x00u, 0x40u,
- 0xBCu, 0x76u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x05u, 0x4Cu,
- 0x23u, 0x78u, 0x33u, 0xB9u, 0x04u, 0x48u, 0x10u, 0xB1u,
- 0x04u, 0x48u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x01u, 0x21u,
- 0x21u, 0x70u, 0x10u, 0xBDu, 0x28u, 0xC1u, 0xFFu, 0x1Fu,
- 0x00u, 0x00u, 0x00u, 0x00u, 0x24u, 0x20u, 0x00u, 0x00u,
+ 0x08u, 0xB5u, 0x05u, 0x4Bu, 0x1Au, 0x68u, 0x03u, 0xF5u,
+ 0x3Fu, 0x53u, 0x02u, 0x33u, 0x1Au, 0x60u, 0x00u, 0xF0u,
+ 0x51u, 0xFAu, 0x00u, 0xF0u, 0x9Bu, 0xF8u, 0x00u, 0xBFu,
+ 0xFAu, 0x46u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x05u, 0x4Cu,
+ 0x23u, 0x78u, 0x33u, 0xB9u, 0x04u, 0x4Bu, 0x13u, 0xB1u,
+ 0x04u, 0x48u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x01u, 0x23u,
+ 0x23u, 0x70u, 0x10u, 0xBDu, 0x28u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0xE4u, 0x20u, 0x00u, 0x00u,
0x08u, 0xB5u, 0x06u, 0x4Bu, 0x1Bu, 0xB1u, 0x06u, 0x48u,
0x06u, 0x49u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x06u, 0x48u,
- 0x01u, 0x68u, 0x11u, 0xB1u, 0x05u, 0x4Au, 0x02u, 0xB1u,
- 0x90u, 0x47u, 0x08u, 0xBDu, 0x00u, 0x00u, 0x00u, 0x00u,
- 0x24u, 0x20u, 0x00u, 0x00u, 0x2Cu, 0xC1u, 0xFFu, 0x1Fu,
+ 0x03u, 0x68u, 0x13u, 0xB1u, 0x05u, 0x4Bu, 0x03u, 0xB1u,
+ 0x98u, 0x47u, 0x08u, 0xBDu, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0xE4u, 0x20u, 0x00u, 0x00u, 0x2Cu, 0xC1u, 0xFFu, 0x1Fu,
0x08u, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u,
- 0x08u, 0xB5u, 0x34u, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u,
- 0xFEu, 0x00u, 0x18u, 0x70u, 0x93u, 0xF8u, 0x7Au, 0x10u,
- 0x01u, 0xF0u, 0xFEu, 0x02u, 0x83u, 0xF8u, 0x7Au, 0x20u,
- 0x2Fu, 0x33u, 0x18u, 0x78u, 0x00u, 0xF0u, 0xFEu, 0x01u,
- 0x19u, 0x70u, 0x13u, 0xF8u, 0x01u, 0x2Cu, 0x02u, 0xF0u,
- 0xFEu, 0x00u, 0x03u, 0xF8u, 0x01u, 0x0Cu, 0x13u, 0xF8u,
- 0x0Cu, 0x1Cu, 0x01u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u,
- 0x0Cu, 0x2Cu, 0x13u, 0xF8u, 0x2Au, 0x0Cu, 0x00u, 0xF0u,
- 0xFEu, 0x01u, 0x03u, 0xF8u, 0x2Au, 0x1Cu, 0x13u, 0xF8u,
- 0x2Eu, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x00u, 0x03u, 0xF8u,
- 0x2Eu, 0x0Cu, 0x13u, 0xF8u, 0x0Du, 0x1Cu, 0x01u, 0xF0u,
- 0xFEu, 0x02u, 0x03u, 0xF8u, 0x0Du, 0x2Cu, 0x13u, 0xF8u,
- 0x2Bu, 0x0Cu, 0x00u, 0xF0u, 0xFEu, 0x01u, 0x03u, 0xF8u,
- 0x2Bu, 0x1Cu, 0x13u, 0xF8u, 0x08u, 0x2Cu, 0x02u, 0xF0u,
- 0xFEu, 0x00u, 0x03u, 0xF8u, 0x08u, 0x0Cu, 0x0Cu, 0x3Bu,
- 0x03u, 0x33u, 0x19u, 0x78u, 0x01u, 0xF0u, 0xFEu, 0x02u,
- 0x1Au, 0x70u, 0x58u, 0x7Bu, 0x00u, 0xF0u, 0xFEu, 0x01u,
- 0x59u, 0x73u, 0x1Au, 0x7Bu, 0x02u, 0xF0u, 0xFEu, 0x00u,
- 0x18u, 0x73u, 0x13u, 0xF8u, 0x11u, 0x1Cu, 0x01u, 0xF0u,
+ 0x08u, 0xB5u, 0x34u, 0x4Bu, 0x1Au, 0x78u, 0x2Fu, 0x33u,
+ 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x2Fu, 0x2Cu,
+ 0x93u, 0xF8u, 0x4Bu, 0x20u, 0x02u, 0xF0u, 0xFEu, 0x02u,
+ 0x83u, 0xF8u, 0x4Bu, 0x20u, 0x1Au, 0x78u, 0x02u, 0xF0u,
+ 0xFEu, 0x02u, 0x1Au, 0x70u, 0x13u, 0xF8u, 0x01u, 0x2Cu,
+ 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x01u, 0x2Cu,
+ 0x13u, 0xF8u, 0x0Cu, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u,
+ 0x03u, 0xF8u, 0x0Cu, 0x2Cu, 0x13u, 0xF8u, 0x2Au, 0x2Cu,
+ 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x2Au, 0x2Cu,
+ 0x13u, 0xF8u, 0x2Eu, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u,
+ 0x03u, 0xF8u, 0x2Eu, 0x2Cu, 0x13u, 0xF8u, 0x0Du, 0x2Cu,
+ 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x0Du, 0x2Cu,
+ 0x13u, 0xF8u, 0x2Bu, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u,
+ 0x03u, 0xF8u, 0x2Bu, 0x2Cu, 0x13u, 0xF8u, 0x08u, 0x2Cu,
+ 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u, 0x08u, 0x2Cu,
+ 0x09u, 0x3Bu, 0x1Au, 0x78u, 0x02u, 0xF0u, 0xFEu, 0x02u,
+ 0x1Au, 0x70u, 0x5Au, 0x7Bu, 0x02u, 0xF0u, 0xFEu, 0x02u,
+ 0x5Au, 0x73u, 0x1Au, 0x7Bu, 0x02u, 0xF0u, 0xFEu, 0x02u,
+ 0x1Au, 0x73u, 0x13u, 0xF8u, 0x11u, 0x2Cu, 0x02u, 0xF0u,
0xFEu, 0x02u, 0x03u, 0xF8u, 0x11u, 0x2Cu, 0x13u, 0xF8u,
- 0x12u, 0x0Cu, 0x00u, 0xF0u, 0xFEu, 0x01u, 0x03u, 0xF8u,
- 0x12u, 0x1Cu, 0x13u, 0xF8u, 0x15u, 0x2Cu, 0x02u, 0xF0u,
- 0xFEu, 0x00u, 0x03u, 0xF8u, 0x15u, 0x0Cu, 0x13u, 0xF8u,
- 0x16u, 0x1Cu, 0x01u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u,
- 0x16u, 0x2Cu, 0x93u, 0xF8u, 0x55u, 0x00u, 0x00u, 0xF0u,
- 0xFEu, 0x01u, 0x83u, 0xF8u, 0x55u, 0x10u, 0x00u, 0xF0u,
- 0xADu, 0xFBu, 0xFEu, 0xE7u, 0x02u, 0x50u, 0x00u, 0x40u,
+ 0x12u, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u,
+ 0x12u, 0x2Cu, 0x13u, 0xF8u, 0x15u, 0x2Cu, 0x02u, 0xF0u,
+ 0xFEu, 0x02u, 0x03u, 0xF8u, 0x15u, 0x2Cu, 0x13u, 0xF8u,
+ 0x16u, 0x2Cu, 0x02u, 0xF0u, 0xFEu, 0x02u, 0x03u, 0xF8u,
+ 0x16u, 0x2Cu, 0x93u, 0xF8u, 0x55u, 0x20u, 0x02u, 0xF0u,
+ 0xFEu, 0x02u, 0x83u, 0xF8u, 0x55u, 0x20u, 0x00u, 0xF0u,
+ 0xF1u, 0xFBu, 0xFEu, 0xE7u, 0x02u, 0x50u, 0x00u, 0x40u,
0xFEu, 0xE7u, 0x00u, 0x00u, 0x08u, 0xB5u, 0x12u, 0x49u,
0x12u, 0x4Bu, 0x4Au, 0x1Cu, 0x1Au, 0xD0u, 0x53u, 0xF8u,
0x10u, 0x6Cu, 0x53u, 0xF8u, 0x0Cu, 0x0Cu, 0x53u, 0xF8u,
0x02u, 0x04u, 0x03u, 0xD0u, 0xB4u, 0x58u, 0x84u, 0x50u,
0x04u, 0x32u, 0xF7u, 0xE7u, 0x53u, 0xF8u, 0x04u, 0x0Cu,
0x00u, 0x22u, 0x82u, 0x42u, 0x03u, 0xD0u, 0x00u, 0x25u,
- 0xA5u, 0x50u, 0x04u, 0x32u, 0xF9u, 0xE7u, 0x01u, 0x39u,
- 0x10u, 0x33u, 0xE2u, 0xE7u, 0x01u, 0xF0u, 0x06u, 0xFFu,
+ 0xA5u, 0x50u, 0x04u, 0x32u, 0xF9u, 0xE7u, 0x10u, 0x33u,
+ 0x01u, 0x39u, 0xE2u, 0xE7u, 0x01u, 0xF0u, 0x66u, 0xFFu,
0xFFu, 0xF7u, 0x6Eu, 0xFFu, 0xFEu, 0xE7u, 0x00u, 0xBFu,
- 0x00u, 0x00u, 0x00u, 0x00u, 0x80u, 0x22u, 0x00u, 0x00u,
- 0x08u, 0xB5u, 0x10u, 0x4Au, 0x10u, 0x4Bu, 0x1Au, 0x60u,
- 0x98u, 0x68u, 0x40u, 0xF4u, 0x00u, 0x72u, 0x9Au, 0x60u,
- 0x00u, 0x23u, 0x03u, 0x2Bu, 0x96u, 0xBFu, 0x0Du, 0x4Au,
- 0x0Du, 0x49u, 0x52u, 0xF8u, 0x23u, 0x10u, 0x0Du, 0x4Au,
- 0x42u, 0xF8u, 0x23u, 0x10u, 0x01u, 0x33u, 0x30u, 0x2Bu,
- 0xF3u, 0xD1u, 0x0Bu, 0x49u, 0x0Bu, 0x4Bu, 0x08u, 0x78u,
- 0x0Bu, 0x49u, 0x18u, 0x70u, 0x0Au, 0x60u, 0x00u, 0xF0u,
- 0x17u, 0xF8u, 0x0Au, 0x48u, 0x00u, 0x22u, 0x02u, 0x60u,
- 0x08u, 0xBDu, 0x00u, 0xBFu, 0x00u, 0x04u, 0xFAu, 0x05u,
- 0x0Cu, 0xEDu, 0x00u, 0xE0u, 0x00u, 0x00u, 0x00u, 0x00u,
- 0x59u, 0x01u, 0x00u, 0x00u, 0x00u, 0xC0u, 0xFFu, 0x1Fu,
- 0xBCu, 0x76u, 0x00u, 0x40u, 0x04u, 0xC1u, 0xFFu, 0x1Fu,
- 0x08u, 0xEDu, 0x00u, 0xE0u, 0x00u, 0xC1u, 0xFFu, 0x1Fu,
- 0xF8u, 0xB5u, 0x72u, 0xB6u, 0x67u, 0x4Bu, 0x01u, 0x22u,
- 0xA3u, 0xF5u, 0xA0u, 0x61u, 0xA1u, 0xF5u, 0x80u, 0x75u,
- 0x06u, 0x20u, 0x52u, 0x24u, 0x64u, 0x4Eu, 0x1Au, 0x70u,
- 0x08u, 0x70u, 0x2Cu, 0x70u, 0x37u, 0x78u, 0x63u, 0x4Bu,
- 0x63u, 0x4Au, 0x40u, 0xF6u, 0x18u, 0x00u, 0x41u, 0xF2u,
- 0x51u, 0x21u, 0x17u, 0x70u, 0x19u, 0x25u, 0x18u, 0x80u,
- 0x00u, 0x24u, 0x23u, 0xF8u, 0x02u, 0x1Cu, 0x5Fu, 0x4Eu,
- 0x4Fu, 0xF4u, 0xF0u, 0x70u, 0x37u, 0x78u, 0x07u, 0xF0u,
- 0x01u, 0x02u, 0x42u, 0xEAu, 0x44u, 0x04u, 0x00u, 0xF0u,
- 0x7Fu, 0xFBu, 0x01u, 0x3Du, 0x04u, 0xF0u, 0x03u, 0x04u,
- 0x17u, 0xD0u, 0x03u, 0x2Cu, 0xEFu, 0xD1u, 0x58u, 0x48u,
- 0x58u, 0x4Fu, 0x00u, 0x26u, 0x4Fu, 0xF4u, 0x80u, 0x73u,
- 0x57u, 0x4Du, 0x07u, 0x21u, 0x48u, 0x22u, 0x02u, 0x24u,
- 0x03u, 0x80u, 0x01u, 0x70u, 0x3Eu, 0x70u, 0xBAu, 0x70u,
- 0x06u, 0x70u, 0x46u, 0x71u, 0x00u, 0xF8u, 0x03u, 0x4Cu,
- 0x28u, 0x78u, 0x40u, 0xF0u, 0x04u, 0x03u, 0x2Bu, 0x70u,
- 0x00u, 0xE0u, 0xFEu, 0xE7u, 0x4Fu, 0x4Fu, 0x06u, 0x21u,
- 0x01u, 0xFBu, 0x06u, 0x72u, 0x00u, 0x21u, 0x10u, 0x68u,
- 0x01u, 0x36u, 0x92u, 0x88u, 0x01u, 0xF0u, 0xADu, 0xFEu,
- 0x07u, 0x2Eu, 0xF3u, 0xD1u, 0x00u, 0x23u, 0x19u, 0x46u,
- 0x49u, 0x4Cu, 0x00u, 0x22u, 0x18u, 0x59u, 0x30u, 0x34u,
- 0xC6u, 0xB2u, 0x20u, 0xF0u, 0xFFu, 0x07u, 0x04u, 0xEBu,
- 0x41u, 0x04u, 0xD5u, 0xB2u, 0xAEu, 0x42u, 0x09u, 0xD0u,
- 0x04u, 0xEBu, 0x42u, 0x0Cu, 0x14u, 0xF8u, 0x12u, 0x50u,
- 0x9Cu, 0xF8u, 0x01u, 0xE0u, 0x01u, 0x32u, 0x05u, 0xF8u,
- 0x07u, 0xE0u, 0xF2u, 0xE7u, 0x04u, 0x33u, 0xC0u, 0xB2u,
- 0x30u, 0x2Bu, 0x01u, 0x44u, 0xE4u, 0xD1u, 0x3Du, 0x4Cu,
- 0x22u, 0x78u, 0x42u, 0xF0u, 0x02u, 0x00u, 0x20u, 0x70u,
- 0x21u, 0x7Cu, 0x3Bu, 0x48u, 0x41u, 0xF0u, 0x02u, 0x03u,
- 0x3Au, 0x49u, 0x23u, 0x74u, 0x0Cu, 0x78u, 0x44u, 0xF0u,
- 0x40u, 0x02u, 0x0Au, 0x70u, 0x03u, 0x78u, 0x38u, 0x4Au,
- 0x43u, 0xF0u, 0x10u, 0x04u, 0x37u, 0x4Bu, 0x04u, 0x70u,
- 0x18u, 0x68u, 0x5Cu, 0x68u, 0x10u, 0x60u, 0x18u, 0x89u,
- 0x54u, 0x60u, 0x10u, 0x81u, 0x1Au, 0x46u, 0x34u, 0x48u,
- 0x52u, 0xF8u, 0x0Au, 0x4Fu, 0x04u, 0x60u, 0x54u, 0x68u,
- 0x12u, 0x89u, 0x44u, 0x60u, 0x02u, 0x81u, 0x1Au, 0x46u,
- 0x52u, 0xF8u, 0x14u, 0x4Fu, 0x52u, 0x68u, 0x40u, 0xF8u,
- 0xCEu, 0x4Cu, 0x40u, 0xF8u, 0xCAu, 0x2Cu, 0x1Au, 0x46u,
- 0x52u, 0xF8u, 0x1Cu, 0x4Fu, 0x52u, 0x68u, 0x40u, 0xF8u,
- 0xBEu, 0x4Cu, 0x40u, 0xF8u, 0xBAu, 0x2Cu, 0x1Au, 0x46u,
- 0x52u, 0xF8u, 0x24u, 0x4Fu, 0x52u, 0x68u, 0x40u, 0xF8u,
- 0xAEu, 0x4Cu, 0x40u, 0xF8u, 0xAAu, 0x2Cu, 0x1Au, 0x46u,
- 0x52u, 0xF8u, 0x2Cu, 0x4Fu, 0x40u, 0xF8u, 0x9Eu, 0x4Cu,
- 0x52u, 0x68u, 0x40u, 0xF8u, 0x9Au, 0x2Cu, 0x53u, 0xF8u,
- 0x34u, 0x0Fu, 0x20u, 0x4Au, 0x5Bu, 0x68u, 0x10u, 0x60u,
- 0x1Fu, 0x48u, 0x53u, 0x60u, 0x02u, 0x78u, 0x42u, 0xF0u,
- 0x08u, 0x03u, 0x03u, 0x70u, 0x1Du, 0x48u, 0x1Eu, 0x4Au,
- 0x03u, 0x78u, 0x03u, 0xF0u, 0x07u, 0x00u, 0x1Bu, 0x09u,
- 0x10u, 0x70u, 0x53u, 0x70u, 0x1Bu, 0x4Au, 0x44u, 0x20u,
- 0x10u, 0x70u, 0x1Bu, 0x4Au, 0x0Bu, 0x46u, 0x0Cu, 0x31u,
- 0x53u, 0xF8u, 0x04u, 0x0Bu, 0x8Bu, 0x42u, 0x42u, 0xF8u,
- 0x04u, 0x0Bu, 0xF9u, 0xD1u, 0x19u, 0x88u, 0x11u, 0x80u,
- 0xF8u, 0xBDu, 0x00u, 0xBFu, 0x00u, 0x48u, 0x00u, 0x40u,
- 0x0Fu, 0x01u, 0x00u, 0x49u, 0x22u, 0x42u, 0x00u, 0x40u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x23u, 0x00u, 0x00u,
+ 0x08u, 0xB5u, 0x11u, 0x4Au, 0x11u, 0x4Bu, 0x1Au, 0x60u,
+ 0x9Au, 0x68u, 0x42u, 0xF4u, 0x00u, 0x72u, 0x9Au, 0x60u,
+ 0x00u, 0x23u, 0x03u, 0x2Bu, 0x98u, 0xBFu, 0x0Eu, 0x4Au,
+ 0x4Fu, 0xEAu, 0x83u, 0x00u, 0x94u, 0xBFu, 0x52u, 0xF8u,
+ 0x23u, 0x10u, 0x0Cu, 0x49u, 0x0Cu, 0x4Au, 0x01u, 0x33u,
+ 0x30u, 0x2Bu, 0x11u, 0x50u, 0xF1u, 0xD1u, 0x0Bu, 0x4Bu,
+ 0x19u, 0x78u, 0x0Bu, 0x4Bu, 0x19u, 0x70u, 0x0Bu, 0x4Bu,
+ 0x1Au, 0x60u, 0x00u, 0xF0u, 0x17u, 0xF8u, 0x0Au, 0x4Bu,
+ 0x00u, 0x22u, 0x1Au, 0x60u, 0x08u, 0xBDu, 0x00u, 0xBFu,
+ 0x00u, 0x04u, 0xFAu, 0x05u, 0x0Cu, 0xEDu, 0x00u, 0xE0u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x59u, 0x01u, 0x00u, 0x00u,
+ 0x00u, 0xC0u, 0xFFu, 0x1Fu, 0xBCu, 0x76u, 0x00u, 0x40u,
+ 0x04u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xEDu, 0x00u, 0xE0u,
+ 0x00u, 0xC1u, 0xFFu, 0x1Fu, 0xF8u, 0xB5u, 0x72u, 0xB6u,
+ 0x63u, 0x4Bu, 0x01u, 0x22u, 0x1Au, 0x70u, 0x06u, 0x22u,
+ 0xA3u, 0xF5u, 0xA0u, 0x63u, 0x1Au, 0x70u, 0x52u, 0x22u,
+ 0xA3u, 0xF5u, 0x80u, 0x73u, 0x1Au, 0x70u, 0x5Fu, 0x4Bu,
+ 0x19u, 0x25u, 0x1Au, 0x78u, 0x5Eu, 0x4Bu, 0xD2u, 0xB2u,
+ 0x1Au, 0x70u, 0x40u, 0xF6u, 0x18u, 0x02u, 0xA3u, 0xF2u,
+ 0x7Fu, 0x43u, 0x1Au, 0x80u, 0x41u, 0xF2u, 0x51u, 0x22u,
+ 0x23u, 0xF8u, 0x02u, 0x2Cu, 0x00u, 0x24u, 0x59u, 0x4Bu,
+ 0x4Fu, 0xF4u, 0xF0u, 0x70u, 0x1Bu, 0x78u, 0x03u, 0xF0u,
+ 0x01u, 0x03u, 0x43u, 0xEAu, 0x44u, 0x04u, 0x00u, 0xF0u,
+ 0x9Bu, 0xFBu, 0x01u, 0x3Du, 0x04u, 0xF0u, 0x03u, 0x04u,
+ 0x18u, 0xD0u, 0x03u, 0x2Cu, 0xEFu, 0xD1u, 0x52u, 0x4Bu,
+ 0x4Fu, 0xF4u, 0x80u, 0x72u, 0x1Au, 0x80u, 0x07u, 0x22u,
+ 0x1Au, 0x70u, 0x50u, 0x4Au, 0x00u, 0x24u, 0x48u, 0x21u,
+ 0x14u, 0x70u, 0x91u, 0x70u, 0x02u, 0x22u, 0x1Cu, 0x70u,
+ 0x5Cu, 0x71u, 0x03u, 0xF8u, 0x03u, 0x2Cu, 0x93u, 0xF8u,
+ 0xE4u, 0x26u, 0x42u, 0xF0u, 0x04u, 0x02u, 0x83u, 0xF8u,
+ 0xE4u, 0x26u, 0x00u, 0xE0u, 0xFEu, 0xE7u, 0x48u, 0x4Bu,
+ 0x00u, 0x21u, 0x23u, 0x44u, 0x18u, 0x68u, 0x9Au, 0x88u,
+ 0x06u, 0x34u, 0x01u, 0xF0u, 0x0Au, 0xFFu, 0x2Au, 0x2Cu,
+ 0xF5u, 0xD1u, 0x00u, 0x23u, 0x19u, 0x46u, 0x43u, 0x4Cu,
+ 0x00u, 0x22u, 0x18u, 0x59u, 0x30u, 0x34u, 0x20u, 0xF0u,
+ 0xFFu, 0x06u, 0xC0u, 0xB2u, 0x45u, 0x00u, 0x04u, 0xEBu,
+ 0x41u, 0x04u, 0xAAu, 0x42u, 0x08u, 0xD0u, 0x04u, 0xEBu,
+ 0x02u, 0x0Cu, 0xA7u, 0x5Cu, 0x9Cu, 0xF8u, 0x01u, 0xC0u,
+ 0x02u, 0x32u, 0x07u, 0xF8u, 0x06u, 0xC0u, 0xF4u, 0xE7u,
+ 0x04u, 0x33u, 0x30u, 0x2Bu, 0x01u, 0x44u, 0xE6u, 0xD1u,
+ 0x37u, 0x4Bu, 0x38u, 0x4Cu, 0x1Au, 0x78u, 0x42u, 0xF0u,
+ 0x02u, 0x02u, 0x1Au, 0x70u, 0x1Au, 0x7Cu, 0x42u, 0xF0u,
+ 0x02u, 0x02u, 0x1Au, 0x74u, 0x34u, 0x4Au, 0x13u, 0x78u,
+ 0x43u, 0xF0u, 0x40u, 0x03u, 0x13u, 0x70u, 0x33u, 0x4Bu,
+ 0x19u, 0x78u, 0x41u, 0xF0u, 0x10u, 0x01u, 0x19u, 0x70u,
+ 0x31u, 0x4Bu, 0x18u, 0x68u, 0x59u, 0x68u, 0x1Du, 0x46u,
+ 0x03u, 0xC4u, 0x19u, 0x89u, 0x55u, 0xF8u, 0x0Au, 0x0Fu,
+ 0x21u, 0x80u, 0x69u, 0x68u, 0xE8u, 0x34u, 0x03u, 0xC4u,
+ 0x29u, 0x89u, 0x18u, 0x46u, 0x21u, 0x80u, 0x50u, 0xF8u,
+ 0x14u, 0x1Fu, 0xA4u, 0xF6u, 0x48u, 0x64u, 0xC4u, 0xF8u,
+ 0x72u, 0x1Du, 0x41u, 0x68u, 0x18u, 0x46u, 0xC4u, 0xF8u,
+ 0x76u, 0x1Du, 0x50u, 0xF8u, 0x1Cu, 0x1Fu, 0xC4u, 0xF8u,
+ 0x82u, 0x1Du, 0x41u, 0x68u, 0x18u, 0x46u, 0xC4u, 0xF8u,
+ 0x86u, 0x1Du, 0x50u, 0xF8u, 0x24u, 0x1Fu, 0xC4u, 0xF8u,
+ 0x92u, 0x1Du, 0x41u, 0x68u, 0x18u, 0x46u, 0xC4u, 0xF8u,
+ 0x96u, 0x1Du, 0x50u, 0xF8u, 0x2Cu, 0x1Fu, 0xC4u, 0xF8u,
+ 0xA2u, 0x1Du, 0x41u, 0x68u, 0x1Bu, 0x48u, 0xC4u, 0xF8u,
+ 0xA6u, 0x1Du, 0x53u, 0xF8u, 0x34u, 0x1Fu, 0x01u, 0x60u,
+ 0x59u, 0x68u, 0x19u, 0x4Bu, 0x41u, 0x60u, 0x19u, 0x78u,
+ 0x41u, 0xF0u, 0x08u, 0x01u, 0x19u, 0x70u, 0x17u, 0x4Bu,
+ 0x17u, 0x49u, 0x1Bu, 0x78u, 0xDBu, 0xB2u, 0x03u, 0xF0u,
+ 0x07u, 0x00u, 0x1Bu, 0x09u, 0x08u, 0x70u, 0x4Bu, 0x70u,
+ 0x14u, 0x4Bu, 0x44u, 0x21u, 0x19u, 0x70u, 0x0Fu, 0xCAu,
+ 0x07u, 0xC4u, 0x23u, 0x80u, 0xF8u, 0xBDu, 0x00u, 0xBFu,
+ 0x00u, 0x48u, 0x00u, 0x40u, 0x0Fu, 0x01u, 0x00u, 0x49u,
0xA1u, 0x46u, 0x00u, 0x40u, 0x25u, 0x42u, 0x00u, 0x40u,
0x04u, 0x40u, 0x00u, 0x40u, 0x06u, 0x40u, 0x00u, 0x40u,
- 0xE8u, 0x46u, 0x00u, 0x40u, 0x28u, 0x20u, 0x00u, 0x00u,
- 0x54u, 0x20u, 0x00u, 0x00u, 0x03u, 0x50u, 0x01u, 0x40u,
- 0xC2u, 0x43u, 0x00u, 0x40u, 0xA0u, 0x43u, 0x00u, 0x40u,
- 0x00u, 0x51u, 0x00u, 0x40u, 0xB2u, 0x20u, 0x00u, 0x00u,
- 0xF0u, 0x51u, 0x00u, 0x40u, 0x62u, 0x51u, 0x00u, 0x40u,
+ 0xE8u, 0x20u, 0x00u, 0x00u, 0x14u, 0x21u, 0x00u, 0x00u,
+ 0x03u, 0x50u, 0x01u, 0x40u, 0x00u, 0x51u, 0x00u, 0x40u,
+ 0xA0u, 0x43u, 0x00u, 0x40u, 0xC2u, 0x43u, 0x00u, 0x40u,
+ 0x72u, 0x21u, 0x00u, 0x00u, 0x62u, 0x51u, 0x00u, 0x40u,
0x22u, 0x43u, 0x00u, 0x40u, 0xCFu, 0x01u, 0x00u, 0x49u,
0x6Eu, 0x58u, 0x00u, 0x40u, 0x76u, 0x58u, 0x00u, 0x40u,
- 0xB0u, 0x43u, 0x00u, 0x40u, 0x00u, 0x47u, 0x00u, 0x00u,
- 0x43u, 0x1Eu, 0x10u, 0xB5u, 0x02u, 0x46u, 0x06u, 0x2Bu,
- 0x0Du, 0xD8u, 0xDFu, 0xE8u, 0x03u, 0xF0u, 0x06u, 0x0Eu,
- 0x23u, 0x04u, 0x08u, 0x0Au, 0x21u, 0x00u, 0x16u, 0x48u,
- 0x08u, 0xE0u, 0x16u, 0x4Bu, 0x1Bu, 0xE0u, 0x16u, 0x48u,
- 0x04u, 0xE0u, 0x16u, 0x48u, 0x02u, 0xE0u, 0x00u, 0x20u,
- 0x00u, 0xE0u, 0x15u, 0x48u, 0x41u, 0x78u, 0x00u, 0x78u,
- 0x41u, 0xEAu, 0x00u, 0x20u, 0x02u, 0x2Au, 0x04u, 0xD0u,
- 0x03u, 0x2Au, 0x07u, 0xD0u, 0x01u, 0x2Au, 0x15u, 0xD1u,
- 0x04u, 0xE0u, 0x02u, 0x02u, 0x42u, 0xEAu, 0x10u, 0x23u,
- 0x98u, 0xB2u, 0x10u, 0xBDu, 0x00u, 0xBAu, 0x10u, 0xBDu,
- 0x0Cu, 0x4Bu, 0x00u, 0xE0u, 0x0Cu, 0x4Bu, 0xD8u, 0x78u,
- 0x9Cu, 0x78u, 0x59u, 0x78u, 0x1Bu, 0x78u, 0x40u, 0xEAu,
- 0x03u, 0x60u, 0x40u, 0xEAu, 0x04u, 0x23u, 0x43u, 0xEAu,
- 0x01u, 0x40u, 0xE3u, 0xE7u, 0x10u, 0xBDu, 0x00u, 0xBFu,
- 0xD2u, 0xFFu, 0x01u, 0x00u, 0xC1u, 0xFFu, 0x01u, 0x00u,
- 0xD6u, 0xFFu, 0x01u, 0x00u, 0xD4u, 0xFFu, 0x01u, 0x00u,
- 0xC5u, 0xFFu, 0x01u, 0x00u, 0xD8u, 0xFFu, 0x01u, 0x00u,
- 0xC9u, 0xFFu, 0x01u, 0x00u, 0x70u, 0xB5u, 0x02u, 0x20u,
- 0xFFu, 0xF7u, 0xB6u, 0xFFu, 0x06u, 0x46u, 0x03u, 0x20u,
- 0xFFu, 0xF7u, 0xB2u, 0xFFu, 0x71u, 0x1Cu, 0x00u, 0xEBu,
- 0x01u, 0x26u, 0x02u, 0x20u, 0xFFu, 0xF7u, 0xACu, 0xFFu,
- 0x00u, 0x24u, 0x01u, 0x30u, 0x01u, 0x02u, 0x25u, 0x46u,
- 0xB1u, 0x42u, 0x09u, 0xD2u, 0x11u, 0xF8u, 0x01u, 0x0Bu,
- 0x42u, 0x1Eu, 0xD3u, 0xB2u, 0x04u, 0x19u, 0xFDu, 0x2Bu,
- 0x98u, 0xBFu, 0x01u, 0x25u, 0xE4u, 0xB2u, 0xF3u, 0xE7u,
- 0x02u, 0x20u, 0xFFu, 0xF7u, 0x99u, 0xFFu, 0x0Fu, 0x49u,
- 0x42u, 0x1Cu, 0x13u, 0x02u, 0xDBu, 0x08u, 0x8Eu, 0x42u,
- 0x01u, 0xD0u, 0xF6u, 0x08u, 0x01u, 0xE0u, 0x4Fu, 0xF4u,
- 0x80u, 0x46u, 0xB3u, 0x42u, 0x06u, 0xD2u, 0x03u, 0xF1u,
- 0x90u, 0x41u, 0x08u, 0x78u, 0x01u, 0x33u, 0x02u, 0x19u,
- 0xD4u, 0xB2u, 0xF6u, 0xE7u, 0x05u, 0x48u, 0x64u, 0x42u,
- 0x02u, 0x78u, 0xE4u, 0xB2u, 0x94u, 0x42u, 0x01u, 0xD0u,
- 0x06u, 0x20u, 0x70u, 0xBDu, 0x00u, 0x2Du, 0xFBu, 0xD0u,
- 0x00u, 0x20u, 0x70u, 0xBDu, 0xC0u, 0xFFu, 0x01u, 0x00u,
- 0x2Du, 0xE9u, 0xF0u, 0x4Fu, 0xADu, 0xF5u, 0x61u, 0x7Du,
- 0x80u, 0x46u, 0x00u, 0xF0u, 0xE5u, 0xFBu, 0x62u, 0xB6u,
- 0x00u, 0x26u, 0xB2u, 0x46u, 0x4Fu, 0xF0u, 0x0Au, 0x09u,
- 0x37u, 0x46u, 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x01u, 0xD1u,
- 0xFFu, 0x23u, 0x00u, 0xE0u, 0x43u, 0x46u, 0x4Au, 0xA8u,
+ 0x00u, 0x47u, 0x10u, 0xB5u, 0x00u, 0x23u, 0x2Au, 0xB1u,
+ 0x01u, 0x3Au, 0x44u, 0x18u, 0xA4u, 0x5Cu, 0x23u, 0x44u,
+ 0xDBu, 0xB2u, 0xF8u, 0xE7u, 0x18u, 0x46u, 0x10u, 0xBDu,
+ 0x01u, 0x38u, 0x09u, 0x28u, 0x42u, 0xD8u, 0xDFu, 0xE8u,
+ 0x00u, 0xF0u, 0x05u, 0x0Bu, 0x11u, 0x17u, 0x1Du, 0x23u,
+ 0x2Fu, 0x29u, 0x35u, 0x3Bu, 0x09u, 0x02u, 0xC1u, 0xF5u,
+ 0xFFu, 0x31u, 0x01u, 0xF5u, 0xE0u, 0x71u, 0x3Bu, 0xE0u,
+ 0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF2u,
+ 0xC1u, 0x11u, 0x38u, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u,
+ 0xFFu, 0x31u, 0x01u, 0xF2u, 0xC5u, 0x11u, 0x2Au, 0xE0u,
+ 0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF2u,
+ 0xC9u, 0x11u, 0x2Cu, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u,
+ 0xFFu, 0x31u, 0x01u, 0xF5u, 0xE8u, 0x71u, 0x23u, 0xE0u,
+ 0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF2u,
+ 0xD1u, 0x11u, 0x1Du, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u,
+ 0xFFu, 0x31u, 0x01u, 0xF5u, 0xEBu, 0x71u, 0x12u, 0xE0u,
+ 0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF5u,
+ 0xE9u, 0x71u, 0x0Cu, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u,
+ 0xFFu, 0x31u, 0x01u, 0xF5u, 0xEAu, 0x71u, 0x06u, 0xE0u,
+ 0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF5u,
+ 0xECu, 0x71u, 0x08u, 0xE0u, 0x00u, 0x21u, 0x0Bu, 0x78u,
+ 0x48u, 0x78u, 0x43u, 0xEAu, 0x00u, 0x20u, 0x70u, 0x47u,
+ 0x08u, 0x78u, 0xC0u, 0xB2u, 0x70u, 0x47u, 0x0Bu, 0x78u,
+ 0x4Au, 0x78u, 0x88u, 0x78u, 0x00u, 0x04u, 0x40u, 0xEAu,
+ 0x02u, 0x20u, 0x18u, 0x43u, 0xCBu, 0x78u, 0x40u, 0xEAu,
+ 0x03u, 0x60u, 0x70u, 0x47u, 0x10u, 0xB5u, 0x0Bu, 0x4Bu,
+ 0x1Au, 0x78u, 0x02u, 0xF0u, 0xC0u, 0x02u, 0x80u, 0x2Au,
+ 0x0Eu, 0xD1u, 0x00u, 0x24u, 0x1Cu, 0x70u, 0x02u, 0x20u,
+ 0x21u, 0x46u, 0xFFu, 0xF7u, 0x99u, 0xFFu, 0x38u, 0xB1u,
+ 0x21u, 0x46u, 0x02u, 0x20u, 0xFFu, 0xF7u, 0x94u, 0xFFu,
+ 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x84u, 0xBFu,
+ 0x10u, 0xBDu, 0x00u, 0xBFu, 0xFAu, 0x46u, 0x00u, 0x40u,
+ 0xF8u, 0xB5u, 0x05u, 0x46u, 0x29u, 0x46u, 0x03u, 0x20u,
+ 0xFFu, 0xF7u, 0x86u, 0xFFu, 0x29u, 0x46u, 0x07u, 0x46u,
+ 0x04u, 0x20u, 0xFFu, 0xF7u, 0x81u, 0xFFu, 0x01u, 0x37u,
+ 0x00u, 0xEBu, 0x07u, 0x27u, 0x29u, 0x46u, 0x03u, 0x20u,
+ 0xFFu, 0xF7u, 0x7Au, 0xFFu, 0x00u, 0x24u, 0x01u, 0x30u,
+ 0x00u, 0x02u, 0x26u, 0x46u, 0xB8u, 0x42u, 0x09u, 0xD2u,
+ 0x10u, 0xF8u, 0x01u, 0x3Bu, 0x5Au, 0x1Eu, 0xD2u, 0xB2u,
+ 0xFDu, 0x2Au, 0x1Cu, 0x44u, 0x98u, 0xBFu, 0x01u, 0x26u,
+ 0xE4u, 0xB2u, 0xF3u, 0xE7u, 0x03u, 0x20u, 0x29u, 0x46u,
+ 0xFFu, 0xF7u, 0x66u, 0xFFu, 0x11u, 0x4Au, 0x01u, 0x30u,
+ 0x97u, 0x42u, 0x4Fu, 0xEAu, 0x00u, 0x23u, 0x4Fu, 0xEAu,
+ 0xD3u, 0x03u, 0x14u, 0xBFu, 0xFFu, 0x08u, 0x4Fu, 0xF4u,
+ 0x80u, 0x47u, 0xBBu, 0x42u, 0x06u, 0xD2u, 0x03u, 0xF1u,
+ 0x90u, 0x42u, 0x12u, 0x78u, 0x01u, 0x33u, 0x14u, 0x44u,
+ 0xE4u, 0xB2u, 0xF6u, 0xE7u, 0x01u, 0x20u, 0x29u, 0x46u,
+ 0xFFu, 0xF7u, 0x4Eu, 0xFFu, 0x64u, 0x42u, 0xE4u, 0xB2u,
+ 0x84u, 0x42u, 0x04u, 0xD1u, 0x00u, 0x2Eu, 0x14u, 0xBFu,
+ 0x00u, 0x20u, 0x06u, 0x20u, 0xF8u, 0xBDu, 0x06u, 0x20u,
+ 0xF8u, 0xBDu, 0x00u, 0xBFu, 0xC0u, 0xFFu, 0x01u, 0x00u,
+ 0x2Du, 0xE9u, 0xF0u, 0x4Fu, 0xADu, 0xF5u, 0x1Bu, 0x7Du,
+ 0x80u, 0x46u, 0x00u, 0xF0u, 0x15u, 0xFAu, 0x10u, 0xB1u,
+ 0x00u, 0x20u, 0x00u, 0xF0u, 0xE1u, 0xFAu, 0x00u, 0xF0u,
+ 0x3Bu, 0xFCu, 0x62u, 0xB6u, 0x00u, 0x26u, 0x4Fu, 0xF0u,
+ 0x0Au, 0x09u, 0x35u, 0x46u, 0xB8u, 0xF1u, 0x00u, 0x0Fu,
+ 0x14u, 0xBFu, 0x43u, 0x46u, 0xFFu, 0x23u, 0x04u, 0xA8u,
0x4Fu, 0xF4u, 0x96u, 0x71u, 0x01u, 0xAAu, 0x00u, 0xF0u,
- 0x0Du, 0xFCu, 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x03u, 0xD0u,
+ 0x5Bu, 0xFCu, 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x03u, 0xD0u,
0x09u, 0xF1u, 0xFFu, 0x39u, 0x5Fu, 0xFAu, 0x89u, 0xF9u,
0xB9u, 0xF1u, 0x00u, 0x0Fu, 0x02u, 0xD0u, 0x00u, 0x28u,
- 0xE7u, 0xD1u, 0x01u, 0xE0u, 0x00u, 0x28u, 0x71u, 0xD1u,
+ 0xE8u, 0xD1u, 0x01u, 0xE0u, 0x00u, 0x28u, 0x78u, 0xD1u,
0xBDu, 0xF8u, 0x04u, 0x20u, 0x06u, 0x2Au, 0x40u, 0xF2u,
- 0x7Bu, 0x81u, 0x9Du, 0xF8u, 0x28u, 0x31u, 0x01u, 0x2Bu,
- 0x40u, 0xF0u, 0x76u, 0x81u, 0x9Du, 0xF8u, 0x2Au, 0x01u,
- 0x9Du, 0xF8u, 0x2Bu, 0x51u, 0x4Au, 0xA9u, 0x40u, 0xEAu,
- 0x05u, 0x25u, 0xECu, 0x1Du, 0x4Bu, 0x19u, 0x94u, 0x42u,
- 0x58u, 0x79u, 0x19u, 0x79u, 0x00u, 0xF2u, 0x66u, 0x81u,
- 0x9Au, 0x79u, 0x17u, 0x2Au, 0x40u, 0xF0u, 0x64u, 0x81u,
- 0x2Bu, 0x1Du, 0x9Bu, 0xB2u, 0x00u, 0x22u, 0x3Bu, 0xB1u,
- 0x0Du, 0xF2u, 0x27u, 0x14u, 0xE4u, 0x5Cu, 0x01u, 0x3Bu,
- 0x12u, 0x19u, 0x92u, 0xB2u, 0x9Bu, 0xB2u, 0xF6u, 0xE7u,
- 0x52u, 0x42u, 0x41u, 0xEAu, 0x00u, 0x20u, 0x91u, 0xB2u,
- 0x88u, 0x42u, 0x40u, 0xF0u, 0x53u, 0x81u, 0x4Au, 0xE0u,
- 0x00u, 0x2Eu, 0x00u, 0xF0u, 0x4Du, 0x81u, 0x01u, 0x2Du,
- 0x4Fu, 0xF0u, 0x00u, 0x04u, 0x40u, 0xF0u, 0x3Cu, 0x81u,
- 0xBBu, 0xF1u, 0x01u, 0x0Fu, 0x00u, 0xF2u, 0x38u, 0x81u,
- 0xFFu, 0x23u, 0x8Du, 0xF8u, 0x2Cu, 0x41u, 0x8Du, 0xF8u,
- 0x2Du, 0x41u, 0x25u, 0x46u, 0x8Du, 0xF8u, 0x2Eu, 0x31u,
- 0x8Du, 0xF8u, 0x2Fu, 0x61u, 0x04u, 0x24u, 0x01u, 0x20u,
- 0x00u, 0x22u, 0x21u, 0x1Du, 0xADu, 0xF8u, 0x06u, 0x40u,
- 0x8Du, 0xF8u, 0x28u, 0x01u, 0x8Du, 0xF8u, 0x29u, 0x51u,
- 0x8Du, 0xF8u, 0x2Au, 0x41u, 0x8Du, 0xF8u, 0x2Bu, 0x21u,
- 0x8Bu, 0xB2u, 0x0Du, 0xF2u, 0x27u, 0x10u, 0xC1u, 0x5Cu,
- 0x01u, 0x3Bu, 0x52u, 0x18u, 0x9Bu, 0xB2u, 0x92u, 0xB2u,
- 0x00u, 0x2Bu, 0xF6u, 0xD1u, 0x50u, 0x42u, 0x81u, 0xB2u,
- 0x08u, 0x0Au, 0x4Bu, 0xAAu, 0x0Du, 0xF2u, 0x2Du, 0x13u,
- 0x11u, 0x55u, 0x18u, 0x55u, 0x17u, 0x21u, 0x0Du, 0xF5u,
- 0x97u, 0x72u, 0xE3u, 0x1Du, 0x11u, 0x55u, 0x4Au, 0xA8u,
- 0x99u, 0xB2u, 0x0Du, 0xF1u, 0x06u, 0x02u, 0x96u, 0x23u,
- 0x00u, 0xF0u, 0x62u, 0xFBu, 0xB8u, 0xF1u, 0x00u, 0x0Fu,
- 0x3Fu, 0xF4u, 0x72u, 0xAFu, 0x00u, 0x2Eu, 0x00u, 0xF0u,
- 0x12u, 0x81u, 0x01u, 0x26u, 0x69u, 0xE7u, 0x9Du, 0xF8u,
- 0x29u, 0x21u, 0x9Du, 0xF8u, 0x2Cu, 0xB1u, 0xA2u, 0xF1u,
- 0x31u, 0x03u, 0x0Au, 0x2Bu, 0x00u, 0xF2u, 0xF7u, 0x80u,
- 0x01u, 0xA1u, 0x51u, 0xF8u, 0x23u, 0xF0u, 0x00u, 0xBFu,
- 0xB5u, 0x06u, 0x00u, 0x00u, 0xD9u, 0x05u, 0x00u, 0x00u,
- 0x6Fu, 0x08u, 0x00u, 0x00u, 0xD3u, 0x06u, 0x00u, 0x00u,
- 0x85u, 0x07u, 0x00u, 0x00u, 0x6Fu, 0x08u, 0x00u, 0x00u,
- 0x8Bu, 0x07u, 0x00u, 0x00u, 0xA9u, 0x07u, 0x00u, 0x00u,
- 0xD3u, 0x06u, 0x00u, 0x00u, 0xC3u, 0x07u, 0x00u, 0x00u,
- 0x4Fu, 0x08u, 0x00u, 0x00u, 0x00u, 0x2Eu, 0x00u, 0xF0u,
- 0xDFu, 0x80u, 0x00u, 0x2Du, 0x40u, 0xF0u, 0xDCu, 0x80u,
- 0xFFu, 0xF7u, 0xF0u, 0xFEu, 0xD0u, 0xF1u, 0x01u, 0x02u,
- 0x38u, 0xBFu, 0x00u, 0x22u, 0x8Du, 0xF8u, 0x2Cu, 0x21u,
- 0xBBu, 0xE0u, 0x34u, 0x2Au, 0x12u, 0xD1u, 0x00u, 0x2Eu,
- 0x00u, 0xF0u, 0xCEu, 0x80u, 0x03u, 0x2Du, 0x40u, 0xF0u,
- 0xCBu, 0x80u, 0xABu, 0xF1u, 0x40u, 0x07u, 0x3Fu, 0x2Fu,
- 0x8Cu, 0xBFu, 0x4Fu, 0xF4u, 0x90u, 0x77u, 0x10u, 0x27u,
- 0x95u, 0xA8u, 0x00u, 0x21u, 0x3Au, 0x46u, 0x01u, 0xF0u,
- 0x88u, 0xFCu, 0x05u, 0xE0u, 0x00u, 0x2Eu, 0x00u, 0xF0u,
- 0xBBu, 0x80u, 0x02u, 0x2Du, 0x40u, 0xF2u, 0xB8u, 0x80u,
- 0x03u, 0x3Du, 0x95u, 0xABu, 0x2Au, 0x46u, 0xD8u, 0x19u,
- 0x0Du, 0xF2u, 0x2Fu, 0x11u, 0x01u, 0xF0u, 0x70u, 0xFCu,
- 0xABu, 0xF1u, 0x40u, 0x00u, 0x7Au, 0x19u, 0x3Fu, 0x28u,
- 0x96u, 0xB2u, 0x03u, 0xD8u, 0x00u, 0xF0u, 0xD4u, 0xF9u,
- 0x10u, 0x24u, 0x01u, 0xE0u, 0x4Fu, 0xF4u, 0x90u, 0x74u,
- 0xA6u, 0x42u, 0x40u, 0xF0u, 0x97u, 0x80u, 0x9Du, 0xF8u,
- 0x2Eu, 0x11u, 0x9Du, 0xF8u, 0x2Du, 0x71u, 0xBBu, 0xF1u,
- 0x3Fu, 0x0Fu, 0x47u, 0xEAu, 0x01u, 0x25u, 0x11u, 0xD8u,
- 0xBAu, 0xF1u, 0x00u, 0x0Fu, 0x0Eu, 0xD1u, 0x51u, 0x46u,
- 0x4Fu, 0xF4u, 0x90u, 0x72u, 0x02u, 0xA8u, 0x01u, 0xF0u,
- 0x58u, 0xFCu, 0x01u, 0x20u, 0xFFu, 0x21u, 0x02u, 0xAAu,
- 0x4Fu, 0xF4u, 0x90u, 0x73u, 0x00u, 0xF0u, 0x64u, 0xF9u,
- 0x4Fu, 0xF0u, 0x01u, 0x0Au, 0x33u, 0x46u, 0x58u, 0x46u,
- 0x29u, 0x46u, 0x95u, 0xAAu, 0x00u, 0xF0u, 0x5Cu, 0xF9u,
- 0x01u, 0x26u, 0x00u, 0x28u, 0x75u, 0xD0u, 0x00u, 0x27u,
- 0x0Au, 0x25u, 0x75u, 0xE0u, 0x00u, 0x2Eu, 0x77u, 0xD0u,
- 0x7Au, 0xE0u, 0x00u, 0x2Eu, 0x74u, 0xD0u, 0x7Cu, 0x19u,
- 0xB4u, 0xF5u, 0x96u, 0x7Fu, 0x6Eu, 0xD8u, 0x95u, 0xA9u,
- 0xC8u, 0x19u, 0x2Au, 0x46u, 0x4Bu, 0xA9u, 0x01u, 0xF0u,
- 0x2Bu, 0xFCu, 0xA7u, 0xB2u, 0x00u, 0x25u, 0x63u, 0xE0u,
- 0x00u, 0x2Du, 0x65u, 0xD1u, 0x3Au, 0x48u, 0x02u, 0xAEu,
- 0x4Bu, 0xACu, 0x03u, 0xC8u, 0x86u, 0xE8u, 0x03u, 0x00u,
- 0x84u, 0xE8u, 0x03u, 0x00u, 0x01u, 0x26u, 0x08u, 0x24u,
- 0x21u, 0xE7u, 0x00u, 0x2Eu, 0x58u, 0xD0u, 0x03u, 0x2Du,
- 0x56u, 0xD1u, 0x9Du, 0xF8u, 0x2Eu, 0x01u, 0x9Du, 0xF8u,
- 0x2Du, 0x11u, 0xABu, 0xF1u, 0x40u, 0x02u, 0x3Fu, 0x2Au,
- 0x41u, 0xEAu, 0x00u, 0x25u, 0x0Au, 0xD8u, 0x2Du, 0x01u,
- 0x00u, 0x23u, 0x10u, 0x22u, 0x2Du, 0x48u, 0x11u, 0x18u,
- 0x4Cu, 0x5Du, 0x01u, 0x3Au, 0x23u, 0x44u, 0xDBu, 0xB2u,
- 0xF8u, 0xD1u, 0x26u, 0xE0u, 0x05u, 0xEBu, 0x0Bu, 0x23u,
- 0x1Cu, 0x02u, 0x4Fu, 0xF4u, 0x80u, 0x72u, 0x00u, 0x23u,
- 0x01u, 0x3Au, 0x10u, 0x5Du, 0x19u, 0x18u, 0xCBu, 0xB2u,
- 0x00u, 0x2Au, 0xF9u, 0xD1u, 0xBBu, 0xF1u, 0x3Fu, 0x0Fu,
- 0x17u, 0xD8u, 0x0Bu, 0xF5u, 0x10u, 0x34u, 0x05u, 0xEBu,
- 0x04u, 0x20u, 0x41u, 0x01u, 0x54u, 0x5Cu, 0x01u, 0x32u,
- 0x1Bu, 0x19u, 0x20u, 0x2Au, 0xDBu, 0xB2u, 0xF9u, 0xD1u,
- 0xBBu, 0xF1u, 0x01u, 0x0Fu, 0x09u, 0xD1u, 0xFFu, 0x2Du,
- 0x07u, 0xD1u, 0x1Bu, 0x4Du, 0x1Bu, 0x4Cu, 0x28u, 0x78u,
- 0x19u, 0x1Au, 0x23u, 0x78u, 0xCAu, 0x1Au, 0x02u, 0xF0u,
- 0xFFu, 0x03u, 0x5Du, 0x42u, 0x8Du, 0xF8u, 0x2Cu, 0x51u,
- 0x00u, 0x25u, 0x01u, 0x24u, 0xDBu, 0xE6u, 0xFFu, 0xF7u,
- 0x29u, 0xFEu, 0x10u, 0xB9u, 0x14u, 0x4Du, 0x80u, 0x24u,
- 0x2Cu, 0x70u, 0x00u, 0xF0u, 0x47u, 0xF9u, 0x0Bu, 0xE0u,
- 0x04u, 0x25u, 0xD0u, 0xE6u, 0x01u, 0x26u, 0x00u, 0x27u,
- 0x04u, 0xE0u, 0x07u, 0x46u, 0x9Au, 0xE7u, 0x05u, 0x25u,
- 0x00u, 0x24u, 0xC8u, 0xE6u, 0x03u, 0x25u, 0xFBu, 0xE7u,
- 0x04u, 0x25u, 0xF9u, 0xE7u, 0x08u, 0x25u, 0xF7u, 0xE7u,
- 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x01u, 0xD1u, 0x47u, 0x46u,
- 0x5Eu, 0xE6u, 0x00u, 0x27u, 0xEDu, 0xE6u, 0x0Du, 0xF5u,
- 0x61u, 0x7Du, 0xBDu, 0xE8u, 0xF0u, 0x8Fu, 0x00u, 0xBFu,
- 0xF0u, 0x20u, 0x00u, 0x00u, 0xFFu, 0x7Fu, 0x00u, 0x40u,
- 0xD0u, 0xFFu, 0x01u, 0x00u, 0xD1u, 0xFFu, 0x01u, 0x00u,
- 0xFAu, 0x46u, 0x00u, 0x40u, 0x10u, 0xB5u, 0xC8u, 0xB0u,
- 0x00u, 0xF0u, 0x94u, 0xF8u, 0x10u, 0xB1u, 0x00u, 0x20u,
- 0x00u, 0xF0u, 0x16u, 0xF9u, 0x68u, 0x46u, 0x00u, 0xF0u,
- 0xA1u, 0xF8u, 0x10u, 0xB1u, 0x00u, 0x20u, 0x00u, 0xF0u,
- 0x0Fu, 0xF9u, 0x16u, 0x48u, 0x03u, 0x68u, 0x19u, 0x68u,
- 0x00u, 0x23u, 0x0Au, 0x46u, 0x22u, 0xB1u, 0x12u, 0xF8u,
- 0x01u, 0x4Du, 0xE3u, 0x18u, 0xDBu, 0xB2u, 0xF9u, 0xE7u,
- 0x42u, 0x68u, 0x10u, 0x78u, 0xC4u, 0x1Au, 0x04u, 0xF0u,
- 0xFFu, 0x03u, 0x83u, 0x42u, 0x00u, 0xD1u, 0x11u, 0xB9u,
- 0x00u, 0x20u, 0x00u, 0xF0u, 0xF9u, 0xF8u, 0x0Cu, 0x4Cu,
- 0xFFu, 0xF7u, 0xD4u, 0xFDu, 0x21u, 0x78u, 0x01u, 0xF0u,
- 0xC0u, 0x02u, 0x40u, 0x2Au, 0x00u, 0xD0u, 0x18u, 0xB1u,
- 0x00u, 0x20u, 0x20u, 0x70u, 0xFFu, 0xF7u, 0x0Cu, 0xFEu,
- 0x14u, 0x20u, 0xFFu, 0xF7u, 0x09u, 0xFEu, 0x80u, 0x20u,
- 0x20u, 0x70u, 0x00u, 0xF0u, 0xE7u, 0xF8u, 0x48u, 0xB0u,
- 0x10u, 0xBDu, 0x00u, 0xBFu, 0x0Cu, 0xC1u, 0xFFu, 0x1Fu,
- 0xFAu, 0x46u, 0x00u, 0x40u, 0x08u, 0xB5u, 0x0Au, 0x4Bu,
- 0x1Au, 0x78u, 0x02u, 0xF0u, 0xC0u, 0x00u, 0x80u, 0x28u,
- 0x0Cu, 0xD1u, 0x00u, 0x21u, 0x19u, 0x70u, 0x01u, 0x20u,
- 0xFFu, 0xF7u, 0x6Au, 0xFDu, 0x30u, 0xB1u, 0x01u, 0x20u,
- 0xFFu, 0xF7u, 0x66u, 0xFDu, 0xBDu, 0xE8u, 0x08u, 0x40u,
- 0xFFu, 0xF7u, 0x60u, 0xBDu, 0x08u, 0xBDu, 0x00u, 0xBFu,
+ 0x89u, 0x81u, 0x9Du, 0xF8u, 0x10u, 0x30u, 0x01u, 0x2Bu,
+ 0x40u, 0xF0u, 0x84u, 0x81u, 0x9Du, 0xF8u, 0x12u, 0x30u,
+ 0x9Du, 0xF8u, 0x13u, 0x40u, 0x43u, 0xEAu, 0x04u, 0x24u,
+ 0xE7u, 0x1Du, 0x04u, 0xABu, 0x23u, 0x44u, 0x97u, 0x42u,
+ 0x58u, 0x79u, 0x19u, 0x79u, 0x00u, 0xF2u, 0x74u, 0x81u,
+ 0x9Bu, 0x79u, 0x17u, 0x2Bu, 0x40u, 0xF0u, 0x72u, 0x81u,
+ 0x23u, 0x1Du, 0x9Bu, 0xB2u, 0x00u, 0x22u, 0x3Bu, 0xB1u,
+ 0x0Du, 0xF1u, 0x0Fu, 0x07u, 0xFFu, 0x5Cu, 0x01u, 0x3Bu,
+ 0x3Au, 0x44u, 0x92u, 0xB2u, 0x9Bu, 0xB2u, 0xF6u, 0xE7u,
+ 0x52u, 0x42u, 0x41u, 0xEAu, 0x00u, 0x23u, 0x92u, 0xB2u,
+ 0x93u, 0x42u, 0x40u, 0xF0u, 0x61u, 0x81u, 0x51u, 0xE0u,
+ 0x00u, 0x2Eu, 0x00u, 0xF0u, 0x5Bu, 0x81u, 0x01u, 0x2Cu,
+ 0x40u, 0xF0u, 0x58u, 0x81u, 0x01u, 0x2Fu, 0x00u, 0xF2u,
+ 0x55u, 0x81u, 0xB2u, 0x4Bu, 0x1Bu, 0x68u, 0x1Bu, 0x68u,
+ 0xC3u, 0xF3u, 0x07u, 0x42u, 0x97u, 0x42u, 0x73u, 0xD1u,
+ 0xC3u, 0xF3u, 0x07u, 0x23u, 0x8Du, 0xF8u, 0x14u, 0x30u,
+ 0x1Bu, 0x0Au, 0x8Du, 0xF8u, 0x15u, 0x30u, 0x00u, 0x24u,
+ 0xFFu, 0x23u, 0x8Du, 0xF8u, 0x16u, 0x30u, 0x8Du, 0xF8u,
+ 0x17u, 0x40u, 0x04u, 0x21u, 0x01u, 0x23u, 0x8Du, 0xF8u,
+ 0x10u, 0x30u, 0x00u, 0x22u, 0x0Bu, 0x1Du, 0xADu, 0xF8u,
+ 0x06u, 0x10u, 0x8Du, 0xF8u, 0x11u, 0x40u, 0x8Du, 0xF8u,
+ 0x12u, 0x10u, 0x8Du, 0xF8u, 0x13u, 0x20u, 0x9Bu, 0xB2u,
+ 0x0Du, 0xF1u, 0x0Fu, 0x00u, 0xC0u, 0x5Cu, 0x01u, 0x3Bu,
+ 0x02u, 0x44u, 0x9Bu, 0xB2u, 0x92u, 0xB2u, 0x00u, 0x2Bu,
+ 0xF6u, 0xD1u, 0x52u, 0x42u, 0x92u, 0xB2u, 0x05u, 0xABu,
+ 0x5Au, 0x54u, 0x12u, 0x0Au, 0x0Du, 0xF1u, 0x15u, 0x03u,
+ 0x5Au, 0x54u, 0x17u, 0x22u, 0x0Du, 0xF1u, 0x16u, 0x03u,
+ 0x5Au, 0x54u, 0x07u, 0x31u, 0x04u, 0xA8u, 0x89u, 0xB2u,
+ 0x0Du, 0xF1u, 0x06u, 0x02u, 0x96u, 0x23u, 0x00u, 0xF0u,
+ 0xB2u, 0xFBu, 0xB8u, 0xF1u, 0x00u, 0x0Fu, 0x3Fu, 0xF4u,
+ 0x69u, 0xAFu, 0x00u, 0x2Eu, 0x00u, 0xF0u, 0x19u, 0x81u,
+ 0x01u, 0x26u, 0x63u, 0xE7u, 0x9Du, 0xF8u, 0x11u, 0x20u,
+ 0x9Du, 0xF8u, 0x14u, 0x70u, 0xA2u, 0xF1u, 0x31u, 0x03u,
+ 0x0Au, 0x2Bu, 0x00u, 0xF2u, 0xFEu, 0x80u, 0x01u, 0xA1u,
+ 0x51u, 0xF8u, 0x23u, 0xF0u, 0x31u, 0x07u, 0x00u, 0x00u,
+ 0x49u, 0x06u, 0x00u, 0x00u, 0xFBu, 0x08u, 0x00u, 0x00u,
+ 0x5Bu, 0x07u, 0x00u, 0x00u, 0x0Bu, 0x08u, 0x00u, 0x00u,
+ 0xFBu, 0x08u, 0x00u, 0x00u, 0x11u, 0x08u, 0x00u, 0x00u,
+ 0x2Fu, 0x08u, 0x00u, 0x00u, 0x5Bu, 0x07u, 0x00u, 0x00u,
+ 0x4Bu, 0x08u, 0x00u, 0x00u, 0xD9u, 0x08u, 0x00u, 0x00u,
+ 0x00u, 0x2Eu, 0x00u, 0xF0u, 0xE7u, 0x80u, 0x00u, 0x2Cu,
+ 0x40u, 0xF0u, 0xE4u, 0x80u, 0x20u, 0x46u, 0xFFu, 0xF7u,
+ 0xDBu, 0xFEu, 0xD0u, 0xF1u, 0x01u, 0x00u, 0x38u, 0xBFu,
+ 0x00u, 0x20u, 0x8Du, 0xF8u, 0x14u, 0x00u, 0xC1u, 0xE0u,
+ 0x8Cu, 0xBFu, 0x00u, 0x23u, 0x4Fu, 0xF4u, 0x80u, 0x73u,
+ 0x88u, 0xE7u, 0x34u, 0x2Au, 0x12u, 0xD1u, 0x00u, 0x2Eu,
+ 0x00u, 0xF0u, 0xD0u, 0x80u, 0x03u, 0x2Cu, 0x40u, 0xF0u,
+ 0xCDu, 0x80u, 0xA7u, 0xF1u, 0x40u, 0x03u, 0x3Fu, 0x2Bu,
+ 0x8Cu, 0xBFu, 0x4Fu, 0xF4u, 0x90u, 0x75u, 0x10u, 0x25u,
+ 0x4Fu, 0xA8u, 0x00u, 0x21u, 0x2Au, 0x46u, 0x01u, 0xF0u,
+ 0xA4u, 0xFCu, 0x05u, 0xE0u, 0x00u, 0x2Eu, 0x00u, 0xF0u,
+ 0xBDu, 0x80u, 0x02u, 0x2Cu, 0x40u, 0xF2u, 0xBAu, 0x80u,
+ 0x03u, 0x3Cu, 0x4Fu, 0xA8u, 0x28u, 0x44u, 0x0Du, 0xF1u,
+ 0x17u, 0x01u, 0x22u, 0x46u, 0x01u, 0xF0u, 0x8Cu, 0xFCu,
+ 0xA7u, 0xF1u, 0x40u, 0x03u, 0x25u, 0x44u, 0x3Fu, 0x2Bu,
+ 0xADu, 0xB2u, 0x03u, 0xD8u, 0x00u, 0xF0u, 0xB6u, 0xF9u,
+ 0x10u, 0x23u, 0x01u, 0xE0u, 0x4Fu, 0xF4u, 0x90u, 0x73u,
+ 0x9Du, 0x42u, 0x40u, 0xF0u, 0x97u, 0x80u, 0x9Du, 0xF8u,
+ 0x16u, 0x10u, 0x9Du, 0xF8u, 0x15u, 0x30u, 0x3Fu, 0x2Fu,
+ 0x43u, 0xEAu, 0x01u, 0x21u, 0x0Fu, 0xD8u, 0x55u, 0x4Bu,
+ 0x01u, 0xEBu, 0x07u, 0x22u, 0x1Bu, 0x68u, 0x92u, 0xB2u,
+ 0x1Bu, 0x68u, 0xC3u, 0xF3u, 0x0Fu, 0x20u, 0x13u, 0xF0u,
+ 0xFFu, 0x0Fu, 0x1Cu, 0xBFu, 0x01u, 0x30u, 0x80u, 0xB2u,
+ 0x82u, 0x42u, 0xC0u, 0xF0u, 0x82u, 0x80u, 0x2Bu, 0x46u,
+ 0x4Fu, 0xAAu, 0x38u, 0x46u, 0x00u, 0xF0u, 0x30u, 0xF9u,
+ 0x00u, 0x28u, 0x0Cu, 0xBFu, 0x00u, 0x24u, 0x0Au, 0x24u,
+ 0x01u, 0x26u, 0x00u, 0xF0u, 0xD7u, 0xF9u, 0x00u, 0x25u,
+ 0x78u, 0xE0u, 0x00u, 0x2Eu, 0x7Au, 0xD0u, 0x7Du, 0xE0u,
+ 0x00u, 0x2Eu, 0x77u, 0xD0u, 0x2Fu, 0x19u, 0xB7u, 0xF5u,
+ 0x96u, 0x7Fu, 0x71u, 0xD8u, 0x4Fu, 0xA8u, 0x28u, 0x44u,
+ 0x22u, 0x46u, 0x05u, 0xA9u, 0x01u, 0xF0u, 0x48u, 0xFCu,
+ 0xBDu, 0xB2u, 0x00u, 0x24u, 0x66u, 0xE0u, 0x00u, 0x2Cu,
+ 0x68u, 0xD1u, 0x3Du, 0x4Au, 0x02u, 0xABu, 0x92u, 0xE8u,
+ 0x03u, 0x00u, 0x05u, 0xAAu, 0x83u, 0xE8u, 0x03u, 0x00u,
+ 0x82u, 0xE8u, 0x03u, 0x00u, 0x01u, 0x26u, 0x08u, 0x21u,
+ 0x1Cu, 0xE7u, 0x00u, 0x2Eu, 0x5Au, 0xD0u, 0x03u, 0x2Cu,
+ 0x58u, 0xD1u, 0x9Du, 0xF8u, 0x15u, 0x30u, 0x9Du, 0xF8u,
+ 0x16u, 0xA0u, 0x43u, 0xEAu, 0x0Au, 0x2Au, 0xA7u, 0xF1u,
+ 0x40u, 0x03u, 0x3Fu, 0x2Bu, 0x07u, 0xD8u, 0x31u, 0x48u,
+ 0x4Fu, 0xEAu, 0x0Au, 0x11u, 0x10u, 0x22u, 0xFFu, 0xF7u,
+ 0xC4u, 0xFDu, 0x04u, 0x46u, 0x2Au, 0xE0u, 0x4Fu, 0xEAu,
+ 0x07u, 0x2Bu, 0x0Au, 0xEBu, 0x0Bu, 0x01u, 0x00u, 0x20u,
+ 0x09u, 0x02u, 0x4Fu, 0xF4u, 0x80u, 0x72u, 0xFFu, 0xF7u,
+ 0xB8u, 0xFDu, 0x3Fu, 0x2Fu, 0x04u, 0x46u, 0x1Du, 0xD8u,
+ 0x0Bu, 0xF1u, 0x10u, 0x7Bu, 0xD3u, 0x44u, 0x4Fu, 0xEAu,
+ 0x4Bu, 0x1Bu, 0x00u, 0x23u, 0x13u, 0xF8u, 0x0Bu, 0x20u,
+ 0x01u, 0x33u, 0x14u, 0x44u, 0x20u, 0x2Bu, 0xE4u, 0xB2u,
+ 0xF8u, 0xD1u, 0x01u, 0x2Fu, 0x0Eu, 0xD1u, 0xBAu, 0xF1u,
+ 0xFFu, 0x0Fu, 0x0Bu, 0xD1u, 0x00u, 0x21u, 0x05u, 0x20u,
+ 0xFFu, 0xF7u, 0xAAu, 0xFDu, 0x20u, 0x1Au, 0xC4u, 0xB2u,
+ 0x00u, 0x21u, 0x06u, 0x20u, 0xFFu, 0xF7u, 0xA4u, 0xFDu,
+ 0x20u, 0x1Au, 0xC4u, 0xB2u, 0x64u, 0x42u, 0x8Du, 0xF8u,
+ 0x14u, 0x40u, 0x00u, 0x24u, 0x01u, 0x21u, 0xD5u, 0xE6u,
+ 0x00u, 0x20u, 0xFFu, 0xF7u, 0x0Du, 0xFEu, 0x10u, 0xB9u,
+ 0x13u, 0x4Bu, 0x80u, 0x22u, 0x1Au, 0x70u, 0x00u, 0xF0u,
+ 0x41u, 0xF9u, 0x0Bu, 0xE0u, 0x01u, 0x26u, 0x00u, 0x25u,
+ 0x06u, 0xE0u, 0x01u, 0x26u, 0x00u, 0x25u, 0x0Au, 0x24u,
+ 0x00u, 0xE0u, 0x05u, 0x24u, 0x00u, 0x21u, 0xC1u, 0xE6u,
+ 0x03u, 0x24u, 0xFBu, 0xE7u, 0x04u, 0x24u, 0xF9u, 0xE7u,
+ 0x08u, 0x24u, 0xF7u, 0xE7u, 0xB8u, 0xF1u, 0x00u, 0x0Fu,
+ 0x01u, 0xD1u, 0x45u, 0x46u, 0x4Eu, 0xE6u, 0x00u, 0x25u,
+ 0xE6u, 0xE6u, 0x0Du, 0xF5u, 0x1Bu, 0x7Du, 0xBDu, 0xE8u,
+ 0xF0u, 0x8Fu, 0x00u, 0xBFu, 0x0Cu, 0xC1u, 0xFFu, 0x1Fu,
+ 0xB0u, 0x21u, 0x00u, 0x00u, 0x00u, 0x80u, 0x00u, 0x40u,
+ 0xFAu, 0x46u, 0x00u, 0x40u, 0x70u, 0xB5u, 0x00u, 0x20u,
+ 0xFFu, 0xF7u, 0xDEu, 0xFDu, 0x15u, 0x4Du, 0x00u, 0x28u,
+ 0x2Bu, 0x68u, 0x4Fu, 0xF0u, 0x00u, 0x00u, 0x1Cu, 0x68u,
+ 0x01u, 0x46u, 0x22u, 0x46u, 0x0Cu, 0xBFu, 0x00u, 0x26u,
+ 0x06u, 0x26u, 0xFFu, 0xF7u, 0x52u, 0xFDu, 0x6Bu, 0x68u,
+ 0x1Bu, 0x78u, 0x18u, 0x1Au, 0x00u, 0xF0u, 0xFFu, 0x00u,
+ 0x98u, 0x42u, 0x00u, 0xD1u, 0x14u, 0xB9u, 0x00u, 0x20u,
+ 0x00u, 0xF0u, 0xFEu, 0xF8u, 0x0Au, 0x4Cu, 0x23u, 0x78u,
+ 0x03u, 0xF0u, 0xC0u, 0x03u, 0x40u, 0x2Bu, 0x00u, 0xD0u,
+ 0x1Eu, 0xB1u, 0x00u, 0x20u, 0x20u, 0x70u, 0xFFu, 0xF7u,
+ 0x07u, 0xFEu, 0x14u, 0x20u, 0xFFu, 0xF7u, 0x04u, 0xFEu,
+ 0x80u, 0x23u, 0x23u, 0x70u, 0xBDu, 0xE8u, 0x70u, 0x40u,
+ 0x00u, 0xF0u, 0xECu, 0xB8u, 0x0Cu, 0xC1u, 0xFFu, 0x1Fu,
0xFAu, 0x46u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x00u,
0x02u, 0x30u, 0x80u, 0x08u, 0x00u, 0xF0u, 0x05u, 0x80u,
0x00u, 0xBFu, 0x01u, 0x38u, 0x00u, 0x46u, 0x7Fu, 0xF4u,
0xFCu, 0xAFu, 0x70u, 0x47u, 0xEFu, 0xF3u, 0x10u, 0x80u,
0x72u, 0xB6u, 0x70u, 0x47u, 0x80u, 0xF3u, 0x10u, 0x88u,
0x70u, 0x47u, 0x00u, 0xBFu, 0xAFu, 0xF3u, 0x00u, 0x80u,
- 0x01u, 0x20u, 0x10u, 0xB5u, 0x00u, 0xF0u, 0x60u, 0xF9u,
- 0x07u, 0x28u, 0x09u, 0xD0u, 0x4Fu, 0xF0u, 0xFFu, 0x34u,
- 0x17u, 0xE0u, 0x0Eu, 0x4Bu, 0x18u, 0x78u, 0x00u, 0xF0u,
- 0x02u, 0x01u, 0xCAu, 0xB2u, 0x00u, 0x2Au, 0xF5u, 0xD1u,
- 0x02u, 0x21u, 0x0Bu, 0x48u, 0x00u, 0xF0u, 0xECu, 0xF8u,
- 0x02u, 0x28u, 0xF2u, 0xD1u, 0x07u, 0x4Cu, 0x23u, 0x78u,
- 0x03u, 0xF0u, 0x02u, 0x00u, 0xC1u, 0xB2u, 0x19u, 0xB9u,
- 0x01u, 0x20u, 0x00u, 0xF0u, 0xAFu, 0xF8u, 0xF5u, 0xE7u,
- 0x00u, 0x24u, 0x00u, 0xF0u, 0x7Fu, 0xF9u, 0x20u, 0x46u,
- 0x10u, 0xBDu, 0x00u, 0xBFu, 0x22u, 0x47u, 0x00u, 0x40u,
- 0x57u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x00u, 0xF0u,
- 0xC1u, 0xF8u, 0x00u, 0xF0u, 0x53u, 0xF9u, 0x58u, 0xB9u,
- 0xFFu, 0xF7u, 0xCEu, 0xFFu, 0x48u, 0xB9u, 0x00u, 0xF0u,
- 0xB9u, 0xF8u, 0x00u, 0xF0u, 0x4Bu, 0xF9u, 0x18u, 0xB9u,
- 0xBDu, 0xE8u, 0x08u, 0x40u, 0xFFu, 0xF7u, 0xC4u, 0xBFu,
- 0x04u, 0x20u, 0x08u, 0xBDu, 0x38u, 0xB5u, 0x04u, 0x46u,
- 0x00u, 0xF0u, 0xACu, 0xF8u, 0x4Cu, 0xB1u, 0x00u, 0xF0u,
- 0x3Du, 0xF9u, 0x05u, 0x46u, 0x38u, 0xB9u, 0x05u, 0x4Bu,
- 0x1Cu, 0x60u, 0x00u, 0xF0u, 0x57u, 0xF9u, 0x28u, 0x46u,
- 0x38u, 0xBDu, 0x01u, 0x20u, 0x38u, 0xBDu, 0x04u, 0x20u,
- 0x38u, 0xBDu, 0x00u, 0xBFu, 0x44u, 0xC1u, 0xFFu, 0x1Fu,
- 0xF8u, 0xB5u, 0x05u, 0x46u, 0x0Eu, 0x46u, 0x17u, 0x46u,
- 0x1Cu, 0x46u, 0x00u, 0xF0u, 0x27u, 0xF9u, 0xF0u, 0xB9u,
- 0x22u, 0x46u, 0x28u, 0x46u, 0x39u, 0x46u, 0x00u, 0xF0u,
- 0xB9u, 0xF8u, 0x07u, 0x28u, 0x04u, 0x46u, 0x13u, 0xD1u,
- 0x1Du, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u, 0x02u, 0x00u,
- 0xC1u, 0xB2u, 0x19u, 0xB9u, 0x01u, 0x20u, 0x00u, 0xF0u,
- 0x61u, 0xF8u, 0xF5u, 0xE7u, 0x1Cu, 0x78u, 0x04u, 0xF0u,
- 0x02u, 0x02u, 0xD0u, 0xB2u, 0x10u, 0xB1u, 0x1Bu, 0x78u,
- 0x9Bu, 0x08u, 0x06u, 0xD0u, 0x4Fu, 0xF0u, 0xFFu, 0x34u,
- 0x00u, 0xF0u, 0x28u, 0xF9u, 0x22u, 0xE0u, 0x04u, 0x24u,
- 0x20u, 0xE0u, 0x12u, 0x4Cu, 0x28u, 0x46u, 0x22u, 0x78u,
- 0x63u, 0x78u, 0x31u, 0x46u, 0x00u, 0xF0u, 0xBCu, 0xF8u,
- 0x07u, 0x28u, 0x04u, 0x46u, 0xF0u, 0xD1u, 0x0Cu, 0x49u,
- 0x0Au, 0x78u, 0x02u, 0xF0u, 0x02u, 0x00u, 0xC3u, 0xB2u,
- 0x1Bu, 0xB9u, 0x01u, 0x20u, 0x00u, 0xF0u, 0x3Eu, 0xF8u,
- 0xF5u, 0xE7u, 0x0Cu, 0x78u, 0x04u, 0xF0u, 0x02u, 0x02u,
- 0xD0u, 0xB2u, 0x00u, 0x28u, 0xDEu, 0xD0u, 0x09u, 0x78u,
- 0x8Bu, 0x08u, 0x14u, 0xBFu, 0x4Fu, 0xF0u, 0xFFu, 0x34u,
- 0x00u, 0x24u, 0xD9u, 0xE7u, 0x20u, 0x46u, 0xF8u, 0xBDu,
- 0x22u, 0x47u, 0x00u, 0x40u, 0x57u, 0xC1u, 0xFFu, 0x1Fu,
- 0x04u, 0x4Bu, 0x1Au, 0x78u, 0x42u, 0xF0u, 0x10u, 0x00u,
- 0x18u, 0x70u, 0x19u, 0x7Cu, 0x41u, 0xF0u, 0x10u, 0x02u,
- 0x1Au, 0x74u, 0x70u, 0x47u, 0xACu, 0x43u, 0x00u, 0x40u,
+ 0x38u, 0xB5u, 0x00u, 0xF0u, 0x2Du, 0xF9u, 0x00u, 0xF0u,
+ 0xD9u, 0xF9u, 0x00u, 0x28u, 0x38u, 0xD1u, 0x00u, 0xF0u,
+ 0x0Fu, 0xFAu, 0x07u, 0x28u, 0x04u, 0x46u, 0x0Fu, 0xD1u,
+ 0x1Bu, 0x4Bu, 0x1Au, 0x78u, 0x90u, 0x07u, 0x03u, 0xD4u,
+ 0x01u, 0x20u, 0x00u, 0xF0u, 0xDBu, 0xF8u, 0xF7u, 0xE7u,
+ 0x1Au, 0x78u, 0x91u, 0x07u, 0x04u, 0xD5u, 0x1Bu, 0x78u,
+ 0x9Bu, 0x08u, 0x14u, 0xBFu, 0x07u, 0x24u, 0x00u, 0x24u,
+ 0x00u, 0xF0u, 0xE0u, 0xF9u, 0x0Cu, 0xBBu, 0x00u, 0xF0u,
+ 0x0Fu, 0xF9u, 0x00u, 0xF0u, 0xBBu, 0xF9u, 0xD8u, 0xB9u,
+ 0x01u, 0x20u, 0x00u, 0xF0u, 0x9Du, 0xF9u, 0x07u, 0x28u,
+ 0x05u, 0xD0u, 0x4Fu, 0xF0u, 0xFFu, 0x34u, 0x10u, 0xE0u,
+ 0x2Bu, 0x78u, 0x9Bu, 0x07u, 0xF9u, 0xD4u, 0x0Bu, 0x48u,
+ 0x02u, 0x21u, 0x00u, 0xF0u, 0x0Fu, 0xF9u, 0x02u, 0x28u,
+ 0x07u, 0x4Du, 0xF5u, 0xD1u, 0x2Bu, 0x78u, 0x9Au, 0x07u,
+ 0x03u, 0xD4u, 0x01u, 0x20u, 0x00u, 0xF0u, 0xB2u, 0xF8u,
+ 0xF8u, 0xE7u, 0x00u, 0xF0u, 0xBFu, 0xF9u, 0x00u, 0xE0u,
+ 0x04u, 0x24u, 0x20u, 0x46u, 0x38u, 0xBDu, 0x00u, 0xBFu,
+ 0x22u, 0x47u, 0x00u, 0x40u, 0x50u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x41u, 0x28u, 0xF8u, 0xB5u, 0x05u, 0x46u, 0x0Eu, 0x46u,
+ 0x17u, 0x46u, 0x1Cu, 0x46u, 0x0Au, 0xD8u, 0xC1u, 0x1Eu,
+ 0x3Cu, 0x29u, 0x8Cu, 0xBFu, 0x00u, 0x21u, 0x01u, 0x21u,
+ 0x3Fu, 0x28u, 0x04u, 0xD8u, 0xB6u, 0xF5u, 0x80u, 0x7Fu,
+ 0x29u, 0xD8u, 0x05u, 0xE0u, 0x01u, 0x21u, 0x81u, 0x2Eu,
+ 0x28u, 0xBFu, 0x01u, 0x21u, 0x10u, 0x2Cu, 0x22u, 0xD1u,
+ 0x0Fu, 0xB3u, 0x01u, 0xBBu, 0x00u, 0xF0u, 0x7Au, 0xF9u,
+ 0xF8u, 0xB9u, 0x23u, 0x46u, 0x28u, 0x46u, 0x31u, 0x46u,
+ 0x3Au, 0x46u, 0x00u, 0xF0u, 0xF1u, 0xF8u, 0x07u, 0x28u,
+ 0x04u, 0x46u, 0x11u, 0xD1u, 0x1Bu, 0x4Bu, 0x1Au, 0x78u,
+ 0x1Fu, 0x46u, 0x12u, 0xF0u, 0x02u, 0x0Fu, 0x03u, 0xD1u,
+ 0x01u, 0x20u, 0x00u, 0xF0u, 0x77u, 0xF8u, 0xF5u, 0xE7u,
+ 0x1Au, 0x78u, 0x90u, 0x07u, 0x02u, 0xD5u, 0x1Bu, 0x78u,
+ 0x9Bu, 0x08u, 0x08u, 0xD0u, 0x4Fu, 0xF0u, 0xFFu, 0x34u,
+ 0x00u, 0xF0u, 0x7Cu, 0xF9u, 0x1Fu, 0xE0u, 0x01u, 0x24u,
+ 0x1Du, 0xE0u, 0x04u, 0x24u, 0x1Bu, 0xE0u, 0x10u, 0x4Bu,
+ 0x28u, 0x46u, 0x1Au, 0x78u, 0x31u, 0x46u, 0x5Bu, 0x78u,
+ 0x00u, 0xF0u, 0x16u, 0xF9u, 0x07u, 0x28u, 0x04u, 0x46u,
+ 0xEEu, 0xD1u, 0x3Au, 0x78u, 0x09u, 0x4Bu, 0x91u, 0x07u,
+ 0x03u, 0xD4u, 0x01u, 0x20u, 0x00u, 0xF0u, 0x56u, 0xF8u,
+ 0xF7u, 0xE7u, 0x1Au, 0x78u, 0x92u, 0x07u, 0xE1u, 0xD5u,
+ 0x1Bu, 0x78u, 0x9Bu, 0x08u, 0x0Cu, 0xBFu, 0x00u, 0x24u,
+ 0x6Fu, 0xF0u, 0x00u, 0x04u, 0xDCu, 0xE7u, 0x20u, 0x46u,
+ 0xF8u, 0xBDu, 0x00u, 0xBFu, 0x22u, 0x47u, 0x00u, 0x40u,
+ 0x50u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0xFFu, 0xF7u,
+ 0x49u, 0xFFu, 0x0Fu, 0x4Bu, 0x1Au, 0x78u, 0x0Cu, 0x33u,
+ 0x42u, 0xF0u, 0x08u, 0x02u, 0x03u, 0xF8u, 0x0Cu, 0x2Cu,
+ 0x1Au, 0x79u, 0x42u, 0xF0u, 0x08u, 0x02u, 0x1Au, 0x71u,
+ 0xC8u, 0x22u, 0x83u, 0xF8u, 0x55u, 0x23u, 0x1Au, 0x78u,
+ 0x42u, 0xF0u, 0x10u, 0x02u, 0x1Au, 0x70u, 0x1Au, 0x7Cu,
+ 0x42u, 0xF0u, 0x10u, 0x02u, 0x1Au, 0x74u, 0x05u, 0x4Bu,
+ 0x1Bu, 0x78u, 0x9Bu, 0x06u, 0xFBu, 0xD5u, 0xBDu, 0xE8u,
+ 0x08u, 0x40u, 0xFFu, 0xF7u, 0x2Fu, 0xBFu, 0x00u, 0xBFu,
+ 0xA0u, 0x43u, 0x00u, 0x40u, 0x00u, 0x47u, 0x00u, 0x40u,
0x01u, 0xBEu, 0x70u, 0x47u, 0x02u, 0x4Bu, 0x1Au, 0x78u,
- 0x42u, 0xF0u, 0x01u, 0x00u, 0x18u, 0x70u, 0x70u, 0x47u,
+ 0x42u, 0xF0u, 0x01u, 0x02u, 0x1Au, 0x70u, 0x70u, 0x47u,
0xF6u, 0x46u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x04u, 0x46u,
0xB4u, 0xF5u, 0x00u, 0x4Fu, 0x06u, 0x4Bu, 0x05u, 0xD9u,
- 0x18u, 0x68u, 0xFFu, 0xF7u, 0x29u, 0xFFu, 0xA4u, 0xF5u,
+ 0x18u, 0x68u, 0xFFu, 0xF7u, 0x09u, 0xFFu, 0xA4u, 0xF5u,
0x00u, 0x44u, 0xF5u, 0xE7u, 0x58u, 0x68u, 0x60u, 0x43u,
- 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x20u, 0xBFu,
- 0x14u, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x4Bu, 0x19u, 0x7Au,
- 0x48u, 0x43u, 0xFFu, 0xF7u, 0x19u, 0xBFu, 0x00u, 0xBFu,
- 0x14u, 0xC1u, 0xFFu, 0x1Fu, 0x05u, 0x4Bu, 0x00u, 0xF0u,
- 0x1Fu, 0x00u, 0x1Bu, 0x68u, 0x00u, 0xF1u, 0x10u, 0x02u,
- 0x53u, 0xF8u, 0x22u, 0x00u, 0x43u, 0xF8u, 0x22u, 0x10u,
- 0x70u, 0x47u, 0x00u, 0xBFu, 0x08u, 0xEDu, 0x00u, 0xE0u,
- 0x00u, 0xF0u, 0x1Fu, 0x00u, 0x00u, 0xF1u, 0x60u, 0x43u,
- 0x49u, 0x01u, 0x03u, 0xF5u, 0x64u, 0x42u, 0xC8u, 0xB2u,
- 0x10u, 0x70u, 0x70u, 0x47u, 0x08u, 0xB5u, 0xFFu, 0xF7u,
- 0x05u, 0xFFu, 0x06u, 0x4Bu, 0x1Au, 0x78u, 0x42u, 0xF0u,
- 0x08u, 0x01u, 0x19u, 0x70u, 0x1Au, 0x7Cu, 0x42u, 0xF0u,
- 0x08u, 0x01u, 0x19u, 0x74u, 0xBDu, 0xE8u, 0x08u, 0x40u,
- 0xFFu, 0xF7u, 0xFCu, 0xBEu, 0xA0u, 0x43u, 0x00u, 0x40u,
- 0x70u, 0xB5u, 0x06u, 0x46u, 0x0Du, 0x46u, 0x00u, 0x24u,
- 0xE3u, 0xB2u, 0xABu, 0x42u, 0x0Cu, 0xD2u, 0x07u, 0x48u,
- 0x01u, 0x78u, 0xCBu, 0x07u, 0x03u, 0xD4u, 0x01u, 0x20u,
- 0xFFu, 0xF7u, 0xC0u, 0xFFu, 0xF7u, 0xE7u, 0x04u, 0x4Au,
- 0x13u, 0x78u, 0x33u, 0x55u, 0x01u, 0x34u, 0xEFu, 0xE7u,
- 0x28u, 0x46u, 0x70u, 0xBDu, 0x22u, 0x47u, 0x00u, 0x40u,
- 0x20u, 0x47u, 0x00u, 0x40u, 0x30u, 0xB5u, 0x10u, 0x4Bu,
- 0x1Cu, 0x78u, 0x04u, 0xF0u, 0x02u, 0x04u, 0xE4u, 0xB2u,
- 0xACu, 0xB1u, 0x0Eu, 0x4Cu, 0xB6u, 0x25u, 0x25u, 0x70u,
- 0xD5u, 0x25u, 0x25u, 0x70u, 0x02u, 0x25u, 0x25u, 0x70u,
- 0x1Bu, 0x78u, 0x2Bu, 0x40u, 0xDBu, 0xB2u, 0x63u, 0xB9u,
- 0x20u, 0x70u, 0x98u, 0xB2u, 0x90u, 0x42u, 0x04u, 0xD2u,
- 0xCCu, 0x5Cu, 0x06u, 0x48u, 0x01u, 0x33u, 0x04u, 0x70u,
- 0xF7u, 0xE7u, 0x07u, 0x20u, 0x30u, 0xBDu, 0x04u, 0x20u,
- 0x30u, 0xBDu, 0x09u, 0x20u, 0x30u, 0xBDu, 0x00u, 0xBFu,
+ 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x00u, 0xBFu,
+ 0x14u, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x4Bu, 0x1Bu, 0x7Au,
+ 0x58u, 0x43u, 0xFFu, 0xF7u, 0xF9u, 0xBEu, 0x00u, 0xBFu,
+ 0x14u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0xFFu, 0xF7u,
+ 0xFDu, 0xFEu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu,
+ 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu,
+ 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu,
+ 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu,
+ 0x00u, 0xBFu, 0x06u, 0x4Bu, 0x1Au, 0x88u, 0x92u, 0xB2u,
+ 0x42u, 0xF0u, 0x04u, 0x02u, 0x1Au, 0x80u, 0x1Bu, 0x88u,
+ 0xBFu, 0xF3u, 0x6Fu, 0x8Fu, 0xBDu, 0xE8u, 0x08u, 0x40u,
+ 0xFFu, 0xF7u, 0xE4u, 0xBEu, 0x00u, 0x48u, 0x00u, 0x40u,
+ 0x05u, 0x4Bu, 0x00u, 0xF0u, 0x1Fu, 0x00u, 0x1Bu, 0x68u,
+ 0x00u, 0xF1u, 0x10u, 0x02u, 0x53u, 0xF8u, 0x22u, 0x00u,
+ 0x43u, 0xF8u, 0x22u, 0x10u, 0x70u, 0x47u, 0x00u, 0xBFu,
+ 0x08u, 0xEDu, 0x00u, 0xE0u, 0x00u, 0xF0u, 0x1Fu, 0x00u,
+ 0x00u, 0xF1u, 0x60u, 0x40u, 0x49u, 0x01u, 0x00u, 0xF5u,
+ 0x64u, 0x40u, 0xC9u, 0xB2u, 0x01u, 0x70u, 0x70u, 0x47u,
+ 0x08u, 0xB5u, 0xFFu, 0xF7u, 0xC3u, 0xFEu, 0x06u, 0x4Bu,
+ 0x1Au, 0x78u, 0x42u, 0xF0u, 0x08u, 0x02u, 0x1Au, 0x70u,
+ 0x1Au, 0x7Cu, 0x42u, 0xF0u, 0x08u, 0x02u, 0x1Au, 0x74u,
+ 0xBDu, 0xE8u, 0x08u, 0x40u, 0xFFu, 0xF7u, 0xBAu, 0xBEu,
+ 0xA0u, 0x43u, 0x00u, 0x40u, 0x70u, 0xB5u, 0x06u, 0x46u,
+ 0x0Du, 0x46u, 0x00u, 0x24u, 0xE3u, 0xB2u, 0xABu, 0x42u,
+ 0x0Cu, 0xD2u, 0x07u, 0x4Bu, 0x1Bu, 0x78u, 0xDBu, 0x07u,
+ 0x03u, 0xD4u, 0x01u, 0x20u, 0xFFu, 0xF7u, 0x9Eu, 0xFFu,
+ 0xF7u, 0xE7u, 0x04u, 0x4Bu, 0x1Bu, 0x78u, 0x33u, 0x55u,
+ 0x01u, 0x34u, 0xEFu, 0xE7u, 0x28u, 0x46u, 0x70u, 0xBDu,
+ 0x22u, 0x47u, 0x00u, 0x40u, 0x20u, 0x47u, 0x00u, 0x40u,
+ 0xF0u, 0xB5u, 0x21u, 0x4Du, 0x2Cu, 0x78u, 0xA4u, 0x07u,
+ 0x39u, 0xD5u, 0x20u, 0x4Cu, 0xB6u, 0x26u, 0x26u, 0x70u,
+ 0xD5u, 0x26u, 0x26u, 0x70u, 0x02u, 0x26u, 0x26u, 0x70u,
+ 0x2Eu, 0x78u, 0x06u, 0xF0u, 0x02u, 0x06u, 0x06u, 0xF0u,
+ 0xFFu, 0x05u, 0x76u, 0xBBu, 0x20u, 0x2Bu, 0x20u, 0x70u,
+ 0x01u, 0xD0u, 0x00u, 0x25u, 0x0Cu, 0xE0u, 0x3Fu, 0x28u,
+ 0xFBu, 0xD8u, 0x01u, 0xEBu, 0x00u, 0x27u, 0x3Fu, 0x02u,
+ 0xEEu, 0x5Du, 0x01u, 0x35u, 0xF6u, 0xB2u, 0xB5u, 0xF5u,
+ 0x80u, 0x7Fu, 0x26u, 0x70u, 0xF8u, 0xD1u, 0xF0u, 0xE7u,
+ 0xAEu, 0xB2u, 0x9Eu, 0x42u, 0x03u, 0xD2u, 0x56u, 0x5Du,
+ 0x01u, 0x35u, 0x26u, 0x70u, 0xF8u, 0xE7u, 0xB3u, 0xF5u,
+ 0x80u, 0x7Fu, 0x01u, 0xD0u, 0x07u, 0x20u, 0xF0u, 0xBDu,
+ 0x3Fu, 0x28u, 0xFBu, 0xD8u, 0x00u, 0xF5u, 0x10u, 0x30u,
+ 0x01u, 0xEBu, 0x00u, 0x21u, 0x49u, 0x01u, 0x00u, 0x23u,
+ 0x5Au, 0x5Cu, 0x01u, 0x33u, 0xD2u, 0xB2u, 0x20u, 0x2Bu,
+ 0x22u, 0x70u, 0xF9u, 0xD1u, 0xEEu, 0xE7u, 0x04u, 0x20u,
+ 0xF0u, 0xBDu, 0x09u, 0x20u, 0xF0u, 0xBDu, 0x00u, 0xBFu,
0x22u, 0x47u, 0x00u, 0x40u, 0x20u, 0x47u, 0x00u, 0x40u,
- 0x70u, 0xB5u, 0x0Fu, 0x4Du, 0x2Cu, 0x78u, 0x04u, 0xF0u,
- 0x02u, 0x04u, 0xE4u, 0xB2u, 0xA4u, 0xB1u, 0x0Du, 0x4Cu,
- 0xB6u, 0x26u, 0x26u, 0x70u, 0xD8u, 0x26u, 0x26u, 0x70u,
- 0x05u, 0x26u, 0x26u, 0x70u, 0x2Du, 0x78u, 0x05u, 0xF0u,
- 0x02u, 0x05u, 0xEDu, 0xB2u, 0x55u, 0xB9u, 0x20u, 0x70u,
+ 0x70u, 0xB5u, 0x0Du, 0x4Du, 0x2Cu, 0x78u, 0xA6u, 0x07u,
+ 0x12u, 0xD5u, 0x0Cu, 0x4Cu, 0xB6u, 0x26u, 0x26u, 0x70u,
+ 0xD8u, 0x26u, 0x26u, 0x70u, 0x05u, 0x26u, 0x26u, 0x70u,
+ 0x2Du, 0x78u, 0xADu, 0x07u, 0x0Au, 0xD4u, 0x20u, 0x70u,
0x08u, 0x0Au, 0xC9u, 0xB2u, 0x20u, 0x70u, 0x21u, 0x70u,
- 0x07u, 0x20u, 0x22u, 0x70u, 0x23u, 0x70u, 0x70u, 0xBDu,
+ 0x22u, 0x70u, 0x23u, 0x70u, 0x07u, 0x20u, 0x70u, 0xBDu,
0x04u, 0x20u, 0x70u, 0xBDu, 0x09u, 0x20u, 0x70u, 0xBDu,
0x22u, 0x47u, 0x00u, 0x40u, 0x20u, 0x47u, 0x00u, 0x40u,
- 0x0Cu, 0x4Au, 0x13u, 0x78u, 0x03u, 0xF0u, 0x02u, 0x01u,
- 0xCBu, 0xB2u, 0x73u, 0xB1u, 0x0Au, 0x4Bu, 0xB6u, 0x21u,
- 0x19u, 0x70u, 0xE1u, 0x21u, 0x19u, 0x70u, 0x0Eu, 0x21u,
- 0x19u, 0x70u, 0x12u, 0x78u, 0x02u, 0xF0u, 0x02u, 0x01u,
- 0xCAu, 0xB2u, 0x22u, 0xB9u, 0x18u, 0x70u, 0x07u, 0x20u,
+ 0x0Au, 0x4Au, 0x13u, 0x78u, 0x99u, 0x07u, 0x0Cu, 0xD5u,
+ 0x09u, 0x4Bu, 0xB6u, 0x21u, 0x19u, 0x70u, 0xE1u, 0x21u,
+ 0x19u, 0x70u, 0x0Eu, 0x21u, 0x19u, 0x70u, 0x12u, 0x78u,
+ 0x92u, 0x07u, 0x04u, 0xD4u, 0x18u, 0x70u, 0x07u, 0x20u,
0x70u, 0x47u, 0x04u, 0x20u, 0x70u, 0x47u, 0x09u, 0x20u,
0x70u, 0x47u, 0x00u, 0xBFu, 0x22u, 0x47u, 0x00u, 0x40u,
0x20u, 0x47u, 0x00u, 0x40u, 0x38u, 0xB5u, 0xFFu, 0xF7u,
- 0x71u, 0xFEu, 0x0Cu, 0x4Bu, 0x19u, 0x78u, 0x79u, 0xB9u,
+ 0x15u, 0xFEu, 0x0Cu, 0x4Bu, 0x19u, 0x78u, 0x79u, 0xB9u,
0x01u, 0x25u, 0x0Bu, 0x4Au, 0x1Du, 0x70u, 0x14u, 0x68u,
0x2Cu, 0x40u, 0x0Au, 0xD0u, 0x14u, 0x68u, 0x24u, 0xF0u,
0x01u, 0x04u, 0x14u, 0x60u, 0x00u, 0xBFu, 0x00u, 0xBFu,
0x00u, 0xBFu, 0x5Du, 0x60u, 0x0Cu, 0x46u, 0x00u, 0xE0u,
- 0x04u, 0x24u, 0xFFu, 0xF7u, 0x5Fu, 0xFEu, 0x20u, 0x46u,
- 0x38u, 0xBDu, 0x00u, 0xBFu, 0x48u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x04u, 0x24u, 0xFFu, 0xF7u, 0x03u, 0xFEu, 0x20u, 0x46u,
+ 0x38u, 0xBDu, 0x00u, 0xBFu, 0x44u, 0xC1u, 0xFFu, 0x1Fu,
0x04u, 0x00u, 0x08u, 0x40u, 0x10u, 0xB5u, 0xFFu, 0xF7u,
- 0x51u, 0xFEu, 0x09u, 0x4Bu, 0x00u, 0x22u, 0x59u, 0x68u,
+ 0xF5u, 0xFDu, 0x09u, 0x4Bu, 0x00u, 0x22u, 0x59u, 0x68u,
0x1Au, 0x70u, 0x01u, 0x29u, 0x08u, 0xD1u, 0x07u, 0x49u,
0x0Cu, 0x68u, 0x44u, 0xF0u, 0x01u, 0x04u, 0x0Cu, 0x60u,
0x00u, 0xBFu, 0x00u, 0xBFu, 0x00u, 0xBFu, 0x5Au, 0x60u,
- 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x42u, 0xBEu,
- 0x48u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x00u, 0x08u, 0x40u,
+ 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0xE6u, 0xBDu,
+ 0x44u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x00u, 0x08u, 0x40u,
+ 0x07u, 0x4Bu, 0x1Bu, 0x78u, 0x9Bu, 0x07u, 0x08u, 0xD5u,
+ 0x06u, 0x4Bu, 0xB6u, 0x22u, 0x1Au, 0x70u, 0xE0u, 0x22u,
+ 0x1Au, 0x70u, 0x0Du, 0x22u, 0x1Au, 0x70u, 0x07u, 0x20u,
+ 0x70u, 0x47u, 0x04u, 0x20u, 0x70u, 0x47u, 0x00u, 0xBFu,
+ 0x22u, 0x47u, 0x00u, 0x40u, 0x20u, 0x47u, 0x00u, 0x40u,
0x08u, 0xB5u, 0x62u, 0xB6u, 0x00u, 0x20u, 0x02u, 0x21u,
- 0x00u, 0xF0u, 0x62u, 0xF9u, 0x01u, 0x4Bu, 0x01u, 0x22u,
- 0x1Au, 0x70u, 0x08u, 0xBDu, 0x50u, 0xC1u, 0xFFu, 0x1Fu,
- 0x01u, 0x20u, 0x00u, 0xF0u, 0x03u, 0xBAu, 0x00u, 0x00u,
- 0xF8u, 0xB5u, 0x07u, 0x46u, 0x0Eu, 0x46u, 0x02u, 0x20u,
- 0x15u, 0x46u, 0x39u, 0x46u, 0x40u, 0x22u, 0x1Cu, 0x46u,
- 0x00u, 0xF0u, 0xBAu, 0xF9u, 0x0Au, 0x23u, 0x5Cu, 0x43u,
- 0x0Du, 0x48u, 0x44u, 0x80u, 0x00u, 0x24u, 0x02u, 0x20u,
- 0x00u, 0xF0u, 0x94u, 0xF9u, 0x50u, 0xB9u, 0x0Au, 0x49u,
- 0x67u, 0x1Cu, 0x4Au, 0x88u, 0xBFu, 0xB2u, 0xA2u, 0x42u,
- 0x04u, 0xD9u, 0x01u, 0x20u, 0xFFu, 0xF7u, 0xD2u, 0xFEu,
- 0x3Cu, 0x46u, 0xF0u, 0xE7u, 0x02u, 0x20u, 0x00u, 0xF0u,
- 0x85u, 0xF9u, 0x10u, 0xB1u, 0x2Eu, 0x80u, 0x00u, 0x20u,
- 0xF8u, 0xBDu, 0x10u, 0x20u, 0xF8u, 0xBDu, 0x00u, 0xBFu,
- 0x50u, 0xC1u, 0xFFu, 0x1Fu, 0x2Du, 0xE9u, 0xF0u, 0x41u,
- 0x15u, 0x46u, 0x0Au, 0x22u, 0x53u, 0x43u, 0x28u, 0x4Cu,
- 0x80u, 0x46u, 0x63u, 0x80u, 0x24u, 0x78u, 0x0Fu, 0x46u,
- 0xD4u, 0xB1u, 0x00u, 0x24u, 0x00u, 0xF0u, 0x5Eu, 0xF9u,
- 0x58u, 0xB9u, 0x23u, 0x4Bu, 0x66u, 0x1Cu, 0x58u, 0x88u,
- 0xB6u, 0xB2u, 0xA0u, 0x42u, 0x04u, 0xD9u, 0x01u, 0x20u,
- 0xFFu, 0xF7u, 0xACu, 0xFEu, 0x34u, 0x46u, 0xF1u, 0xE7u,
- 0x34u, 0x46u, 0x00u, 0xF0u, 0x4Fu, 0xF9u, 0xE0u, 0xB1u,
- 0x00u, 0xF0u, 0x52u, 0xF9u, 0xFFu, 0xF7u, 0xB0u, 0xFFu,
- 0x19u, 0x4Au, 0x00u, 0x21u, 0x11u, 0x70u, 0x14u, 0xE0u,
- 0x00u, 0xF0u, 0x4Au, 0xF9u, 0x08u, 0xB9u, 0x00u, 0x24u,
- 0x0Fu, 0xE0u, 0x00u, 0xF0u, 0x3Fu, 0xF9u, 0x00u, 0x28u,
- 0xF9u, 0xD0u, 0xFFu, 0xF7u, 0xA1u, 0xFFu, 0x08u, 0xE0u,
- 0x11u, 0x4Bu, 0x66u, 0x1Cu, 0x59u, 0x88u, 0xB6u, 0xB2u,
- 0xA1u, 0x42u, 0x09u, 0xD9u, 0xFFu, 0xF7u, 0x8Au, 0xFEu,
- 0x34u, 0x46u, 0x01u, 0x20u, 0x00u, 0xF0u, 0x3Eu, 0xF9u,
- 0x01u, 0x28u, 0x4Fu, 0xF0u, 0x01u, 0x00u, 0xEFu, 0xD1u,
- 0x00u, 0xF0u, 0x38u, 0xF9u, 0x01u, 0x28u, 0x0Au, 0xD1u,
- 0x41u, 0x46u, 0x40u, 0x2Fu, 0x34u, 0xBFu, 0x3Au, 0x46u,
- 0x40u, 0x22u, 0x00u, 0xF0u, 0x9Fu, 0xF9u, 0x28u, 0x80u,
- 0x00u, 0x20u, 0xBDu, 0xE8u, 0xF0u, 0x81u, 0x00u, 0x20u,
- 0x28u, 0x80u, 0x10u, 0x20u, 0xBDu, 0xE8u, 0xF0u, 0x81u,
- 0x50u, 0xC1u, 0xFFu, 0x1Fu, 0xF8u, 0xB5u, 0xFFu, 0xF7u,
- 0xA5u, 0xFDu, 0x38u, 0x4Bu, 0x07u, 0x46u, 0x1Au, 0x78u,
- 0x01u, 0x25u, 0x42u, 0xF0u, 0x01u, 0x00u, 0x18u, 0x70u,
- 0x19u, 0x7Cu, 0x02u, 0x26u, 0x41u, 0xF0u, 0x01u, 0x04u,
- 0x1Cu, 0x74u, 0x33u, 0x4Bu, 0x33u, 0x4Cu, 0x1Du, 0x70u,
- 0x03u, 0xF8u, 0x94u, 0x6Cu, 0x13u, 0xF8u, 0x8Du, 0x2Cu,
- 0x02u, 0xF0u, 0x7Fu, 0x00u, 0x03u, 0xF8u, 0x8Du, 0x0Cu,
- 0x00u, 0x20u, 0xFFu, 0xF7u, 0x63u, 0xFEu, 0x21u, 0x78u,
- 0x2Du, 0x48u, 0x01u, 0xF0u, 0xF9u, 0x03u, 0x23u, 0x70u,
- 0x02u, 0x78u, 0x02u, 0xF0u, 0xDFu, 0x01u, 0x01u, 0x70u,
- 0x23u, 0x78u, 0x28u, 0x46u, 0x2Bu, 0x43u, 0x23u, 0x70u,
- 0xFFu, 0xF7u, 0x54u, 0xFEu, 0x28u, 0x20u, 0xFFu, 0xF7u,
- 0x51u, 0xFEu, 0x26u, 0x48u, 0x02u, 0x78u, 0x02u, 0xF0u,
- 0x7Fu, 0x01u, 0x01u, 0x70u, 0x03u, 0x78u, 0x03u, 0xF0u,
- 0xBFu, 0x02u, 0x02u, 0x70u, 0x20u, 0x78u, 0x30u, 0x43u,
- 0x20u, 0x70u, 0x30u, 0x46u, 0xFFu, 0xF7u, 0x42u, 0xFEu,
- 0x21u, 0x78u, 0x1Fu, 0x4Au, 0x41u, 0xF0u, 0x04u, 0x03u,
- 0x23u, 0x70u, 0x00u, 0x24u, 0x14u, 0x70u, 0x38u, 0x46u,
- 0x54u, 0x70u, 0xFFu, 0xF7u, 0x63u, 0xFDu, 0x17u, 0x20u,
- 0x1Au, 0x49u, 0xFFu, 0xF7u, 0x3Bu, 0xFEu, 0x17u, 0x20u,
- 0x07u, 0x21u, 0xFFu, 0xF7u, 0x45u, 0xFEu, 0x15u, 0x20u,
- 0x17u, 0x49u, 0xFFu, 0xF7u, 0x33u, 0xFEu, 0x15u, 0x20u,
- 0x07u, 0x21u, 0xFFu, 0xF7u, 0x3Du, 0xFEu, 0x18u, 0x20u,
- 0x14u, 0x49u, 0xFFu, 0xF7u, 0x2Bu, 0xFEu, 0x18u, 0x20u,
- 0x07u, 0x21u, 0xFFu, 0xF7u, 0x35u, 0xFEu, 0x20u, 0x46u,
- 0x11u, 0x49u, 0xFFu, 0xF7u, 0x23u, 0xFEu, 0x20u, 0x46u,
- 0x07u, 0x21u, 0xFFu, 0xF7u, 0x2Du, 0xFEu, 0x28u, 0x46u,
- 0x0Eu, 0x49u, 0xFFu, 0xF7u, 0x1Bu, 0xFEu, 0x28u, 0x46u,
- 0x07u, 0x21u, 0xBDu, 0xE8u, 0xF8u, 0x40u, 0xFFu, 0xF7u,
- 0x23u, 0xBEu, 0x00u, 0xBFu, 0xA5u, 0x43u, 0x00u, 0x40u,
- 0x9Du, 0x60u, 0x00u, 0x40u, 0x94u, 0x43u, 0x00u, 0x40u,
+ 0x00u, 0xF0u, 0x4Eu, 0xF9u, 0x01u, 0x4Bu, 0x01u, 0x22u,
+ 0x1Au, 0x70u, 0x08u, 0xBDu, 0x4Cu, 0xC1u, 0xFFu, 0x1Fu,
+ 0x01u, 0x20u, 0x00u, 0xF0u, 0xF1u, 0xB9u, 0xF8u, 0xB5u,
+ 0x07u, 0x46u, 0x0Eu, 0x46u, 0x15u, 0x46u, 0x03u, 0xEBu,
+ 0x83u, 0x03u, 0x02u, 0x20u, 0x39u, 0x46u, 0x40u, 0x22u,
+ 0x5Cu, 0x00u, 0x00u, 0xF0u, 0xA7u, 0xF9u, 0x02u, 0x20u,
+ 0x00u, 0xF0u, 0x86u, 0xF9u, 0x30u, 0xB9u, 0x2Cu, 0xB1u,
+ 0x01u, 0x20u, 0x01u, 0x3Cu, 0xFFu, 0xF7u, 0x8Au, 0xFEu,
+ 0xA4u, 0xB2u, 0xF4u, 0xE7u, 0x02u, 0x20u, 0x00u, 0xF0u,
+ 0x7Bu, 0xF9u, 0x10u, 0xB1u, 0x2Eu, 0x80u, 0x00u, 0x20u,
+ 0xF8u, 0xBDu, 0x10u, 0x20u, 0xF8u, 0xBDu, 0x00u, 0x00u,
+ 0x2Du, 0xE9u, 0xF8u, 0x43u, 0x03u, 0xEBu, 0x83u, 0x03u,
+ 0x5Cu, 0x00u, 0x23u, 0x4Bu, 0x16u, 0x46u, 0x1Au, 0x78u,
+ 0x80u, 0x46u, 0x0Fu, 0x46u, 0x99u, 0x46u, 0xAAu, 0xB1u,
+ 0x25u, 0x46u, 0x00u, 0xF0u, 0x53u, 0xF9u, 0x30u, 0xB9u,
+ 0x2Du, 0xB1u, 0x01u, 0x20u, 0x01u, 0x3Du, 0xFFu, 0xF7u,
+ 0x69u, 0xFEu, 0xADu, 0xB2u, 0xF5u, 0xE7u, 0x00u, 0xF0u,
+ 0x49u, 0xF9u, 0xA8u, 0xB1u, 0x00u, 0xF0u, 0x4Cu, 0xF9u,
+ 0xFFu, 0xF7u, 0xBEu, 0xFFu, 0x00u, 0x23u, 0x89u, 0xF8u,
+ 0x00u, 0x30u, 0x0Du, 0xE0u, 0x00u, 0xF0u, 0x44u, 0xF9u,
+ 0x50u, 0xB1u, 0x00u, 0xF0u, 0x3Bu, 0xF9u, 0x38u, 0xB1u,
+ 0xFFu, 0xF7u, 0xB2u, 0xFFu, 0x04u, 0xE0u, 0x54u, 0xB1u,
+ 0xFFu, 0xF7u, 0x50u, 0xFEu, 0x01u, 0x3Cu, 0xA4u, 0xB2u,
+ 0x01u, 0x20u, 0x00u, 0xF0u, 0x41u, 0xF9u, 0x01u, 0x28u,
+ 0x4Fu, 0xF0u, 0x01u, 0x00u, 0xF3u, 0xD1u, 0x00u, 0xF0u,
+ 0x3Bu, 0xF9u, 0x01u, 0x28u, 0x0Au, 0xD1u, 0x41u, 0x46u,
+ 0x40u, 0x2Fu, 0x34u, 0xBFu, 0x3Au, 0x46u, 0x40u, 0x22u,
+ 0x00u, 0xF0u, 0xA4u, 0xF9u, 0x30u, 0x80u, 0x00u, 0x20u,
+ 0xBDu, 0xE8u, 0xF8u, 0x83u, 0x00u, 0x23u, 0x33u, 0x80u,
+ 0x10u, 0x20u, 0xBDu, 0xE8u, 0xF8u, 0x83u, 0x00u, 0xBFu,
+ 0x4Cu, 0xC1u, 0xFFu, 0x1Fu, 0xF8u, 0xB5u, 0xFFu, 0xF7u,
+ 0x49u, 0xFDu, 0x39u, 0x4Bu, 0x01u, 0x25u, 0x1Au, 0x78u,
+ 0x02u, 0x26u, 0x42u, 0xF0u, 0x01u, 0x02u, 0x1Au, 0x70u,
+ 0x1Au, 0x7Cu, 0x36u, 0x4Cu, 0x42u, 0xF0u, 0x01u, 0x02u,
+ 0x1Au, 0x74u, 0x03u, 0xF5u, 0xE7u, 0x53u, 0x18u, 0x33u,
+ 0x1Du, 0x70u, 0x03u, 0xF8u, 0x94u, 0x6Cu, 0x13u, 0xF8u,
+ 0x8Du, 0x2Cu, 0x07u, 0x46u, 0x02u, 0xF0u, 0x7Fu, 0x02u,
+ 0x03u, 0xF8u, 0x8Du, 0x2Cu, 0x00u, 0x20u, 0xFFu, 0xF7u,
+ 0x25u, 0xFEu, 0x23u, 0x78u, 0x28u, 0x46u, 0x03u, 0xF0u,
+ 0xF9u, 0x03u, 0x23u, 0x70u, 0x2Au, 0x4Bu, 0x1Au, 0x78u,
+ 0x02u, 0xF0u, 0xDFu, 0x02u, 0x1Au, 0x70u, 0x23u, 0x78u,
+ 0x2Bu, 0x43u, 0x23u, 0x70u, 0xFFu, 0xF7u, 0x16u, 0xFEu,
+ 0x28u, 0x20u, 0xFFu, 0xF7u, 0x13u, 0xFEu, 0x25u, 0x4Bu,
+ 0x30u, 0x46u, 0x1Au, 0x78u, 0x02u, 0xF0u, 0x7Fu, 0x02u,
+ 0x1Au, 0x70u, 0x1Au, 0x78u, 0x02u, 0xF0u, 0xBFu, 0x02u,
+ 0x1Au, 0x70u, 0x23u, 0x78u, 0x33u, 0x43u, 0x23u, 0x70u,
+ 0xFFu, 0xF7u, 0x04u, 0xFEu, 0x23u, 0x78u, 0x38u, 0x46u,
+ 0x43u, 0xF0u, 0x04u, 0x03u, 0x23u, 0x70u, 0x1Cu, 0x4Bu,
+ 0x00u, 0x24u, 0x1Cu, 0x70u, 0x5Cu, 0x70u, 0xFFu, 0xF7u,
+ 0x05u, 0xFDu, 0x1Au, 0x49u, 0x17u, 0x20u, 0xFFu, 0xF7u,
+ 0x1Fu, 0xFEu, 0x17u, 0x20u, 0x07u, 0x21u, 0xFFu, 0xF7u,
+ 0x29u, 0xFEu, 0x17u, 0x49u, 0x15u, 0x20u, 0xFFu, 0xF7u,
+ 0x17u, 0xFEu, 0x15u, 0x20u, 0x07u, 0x21u, 0xFFu, 0xF7u,
+ 0x21u, 0xFEu, 0x14u, 0x49u, 0x18u, 0x20u, 0xFFu, 0xF7u,
+ 0x0Fu, 0xFEu, 0x18u, 0x20u, 0x07u, 0x21u, 0xFFu, 0xF7u,
+ 0x19u, 0xFEu, 0x20u, 0x46u, 0x10u, 0x49u, 0xFFu, 0xF7u,
+ 0x07u, 0xFEu, 0x20u, 0x46u, 0x07u, 0x21u, 0xFFu, 0xF7u,
+ 0x11u, 0xFEu, 0x28u, 0x46u, 0x0Du, 0x49u, 0xFFu, 0xF7u,
+ 0xFFu, 0xFDu, 0x28u, 0x46u, 0x07u, 0x21u, 0xBDu, 0xE8u,
+ 0xF8u, 0x40u, 0xFFu, 0xF7u, 0x07u, 0xBEu, 0x00u, 0xBFu,
+ 0xA5u, 0x43u, 0x00u, 0x40u, 0x94u, 0x43u, 0x00u, 0x40u,
0x12u, 0x60u, 0x00u, 0x40u, 0xF8u, 0x51u, 0x00u, 0x40u,
- 0x84u, 0x60u, 0x00u, 0x40u, 0x23u, 0x16u, 0x00u, 0x00u,
- 0x21u, 0x16u, 0x00u, 0x00u, 0x61u, 0x14u, 0x00u, 0x00u,
- 0xB9u, 0x15u, 0x00u, 0x00u, 0xEDu, 0x15u, 0x00u, 0x00u,
+ 0x84u, 0x60u, 0x00u, 0x40u, 0x13u, 0x17u, 0x00u, 0x00u,
+ 0x11u, 0x17u, 0x00u, 0x00u, 0x65u, 0x15u, 0x00u, 0x00u,
+ 0xA9u, 0x16u, 0x00u, 0x00u, 0xDDu, 0x16u, 0x00u, 0x00u,
0x18u, 0x4Bu, 0x01u, 0x22u, 0x10u, 0xB5u, 0x1Au, 0x70u,
0x17u, 0x4Bu, 0x4Fu, 0xF4u, 0x00u, 0x04u, 0x1Cu, 0x60u,
0x4Fu, 0xF0u, 0x80u, 0x74u, 0x1Cu, 0x60u, 0x1Au, 0x60u,
0x02u, 0x22u, 0x1Au, 0x60u, 0x13u, 0x4Bu, 0x00u, 0x24u,
0x1Cu, 0x70u, 0x13u, 0x4Bu, 0x01u, 0xB1u, 0x03u, 0x22u,
- 0x12u, 0x49u, 0x1Au, 0x70u, 0x12u, 0x4Bu, 0x08u, 0x70u,
- 0x12u, 0x4Au, 0x00u, 0x20u, 0x12u, 0x49u, 0x18u, 0x70u,
- 0x12u, 0x4Bu, 0x10u, 0x70u, 0x08u, 0x70u, 0x12u, 0x4Au,
- 0x12u, 0x49u, 0x18u, 0x70u, 0x12u, 0x4Bu, 0x10u, 0x70u,
- 0x08u, 0x70u, 0x80u, 0x22u, 0x03u, 0x20u, 0x18u, 0x70u,
- 0x01u, 0x20u, 0x03u, 0xF8u, 0x20u, 0x2Cu, 0xFFu, 0xF7u,
- 0xE7u, 0xFCu, 0x0Eu, 0x48u, 0x04u, 0x21u, 0x01u, 0x70u,
- 0x10u, 0xBDu, 0x00u, 0xBFu, 0xECu, 0xC1u, 0xFFu, 0x1Fu,
- 0x00u, 0xE1u, 0x00u, 0xE0u, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
- 0x09u, 0x60u, 0x00u, 0x40u, 0x6Cu, 0xC1u, 0xFFu, 0x1Fu,
- 0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x6Du, 0xC1u, 0xFFu, 0x1Fu,
- 0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu,
- 0x6Fu, 0xC1u, 0xFFu, 0x1Fu, 0xE5u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x1Au, 0x70u, 0x12u, 0x4Bu, 0x12u, 0x4Au, 0x18u, 0x70u,
+ 0x00u, 0x23u, 0x13u, 0x70u, 0x11u, 0x4Au, 0x01u, 0x20u,
+ 0x13u, 0x70u, 0x11u, 0x4Au, 0x13u, 0x70u, 0x11u, 0x4Au,
+ 0x13u, 0x70u, 0x11u, 0x4Au, 0x13u, 0x70u, 0x11u, 0x4Au,
+ 0x13u, 0x70u, 0x11u, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u,
+ 0x80u, 0x22u, 0x03u, 0xF8u, 0x20u, 0x2Cu, 0xFFu, 0xF7u,
+ 0x8Bu, 0xFCu, 0x0Eu, 0x4Bu, 0x04u, 0x22u, 0x1Au, 0x70u,
+ 0x10u, 0xBDu, 0x00u, 0xBFu, 0xE4u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x00u, 0xE1u, 0x00u, 0xE0u, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+ 0x09u, 0x60u, 0x00u, 0x40u, 0x64u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x65u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x68u, 0xC1u, 0xFFu, 0x1Fu, 0x54u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x67u, 0xC1u, 0xFFu, 0x1Fu, 0xDDu, 0xC1u, 0xFFu, 0x1Fu,
0x28u, 0x60u, 0x00u, 0x40u, 0x12u, 0x60u, 0x00u, 0x40u,
0x70u, 0xB5u, 0x07u, 0x4Cu, 0x06u, 0x46u, 0x23u, 0x78u,
0x0Du, 0x46u, 0x1Bu, 0xB9u, 0xFFu, 0xF7u, 0x22u, 0xFFu,
- 0x01u, 0x20u, 0x20u, 0x70u, 0x30u, 0x46u, 0x29u, 0x46u,
+ 0x01u, 0x23u, 0x23u, 0x70u, 0x30u, 0x46u, 0x29u, 0x46u,
0xBDu, 0xE8u, 0x70u, 0x40u, 0xFFu, 0xF7u, 0xA4u, 0xBFu,
- 0x54u, 0xC1u, 0xFFu, 0x1Fu, 0x0Cu, 0x4Bu, 0x01u, 0x22u,
- 0x0Cu, 0x49u, 0x1Au, 0x70u, 0x00u, 0x20u, 0x0Cu, 0x4Au,
- 0x0Cu, 0x4Bu, 0x08u, 0x70u, 0x0Cu, 0x49u, 0x10u, 0x70u,
- 0x18u, 0x70u, 0x0Cu, 0x4Au, 0x0Cu, 0x4Bu, 0x08u, 0x70u,
- 0x0Cu, 0x49u, 0x10u, 0x70u, 0x18u, 0x70u, 0x0Cu, 0x4Bu,
- 0x08u, 0x70u, 0x80u, 0x22u, 0x03u, 0x20u, 0x18u, 0x70u,
+ 0x4Du, 0xC1u, 0xFFu, 0x1Fu, 0x0Cu, 0x4Bu, 0x01u, 0x22u,
+ 0x1Au, 0x70u, 0x0Cu, 0x4Au, 0x00u, 0x23u, 0x13u, 0x70u,
+ 0x0Bu, 0x4Au, 0x13u, 0x70u, 0x0Bu, 0x4Au, 0x13u, 0x70u,
+ 0x0Bu, 0x4Au, 0x13u, 0x70u, 0x0Bu, 0x4Au, 0x13u, 0x70u,
+ 0x0Bu, 0x4Au, 0x13u, 0x70u, 0x0Bu, 0x4Au, 0x13u, 0x70u,
+ 0x0Bu, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u, 0x80u, 0x22u,
0x03u, 0xF8u, 0x20u, 0x2Cu, 0x70u, 0x47u, 0x00u, 0xBFu,
- 0xECu, 0xC1u, 0xFFu, 0x1Fu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
- 0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x6Du, 0xC1u, 0xFFu, 0x1Fu,
- 0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu,
- 0x6Fu, 0xC1u, 0xFFu, 0x1Fu, 0xE5u, 0xC1u, 0xFFu, 0x1Fu,
+ 0xE4u, 0xC1u, 0xFFu, 0x1Fu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+ 0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x65u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x68u, 0xC1u, 0xFFu, 0x1Fu, 0x54u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x67u, 0xC1u, 0xFFu, 0x1Fu, 0xDDu, 0xC1u, 0xFFu, 0x1Fu,
0x28u, 0x60u, 0x00u, 0x40u, 0x01u, 0x4Bu, 0x18u, 0x78u,
- 0x70u, 0x47u, 0x00u, 0xBFu, 0x71u, 0xC1u, 0xFFu, 0x1Fu,
- 0x03u, 0x4Bu, 0x18u, 0x78u, 0x10u, 0xB1u, 0x00u, 0x22u,
- 0x18u, 0x78u, 0x1Au, 0x70u, 0x70u, 0x47u, 0x00u, 0xBFu,
- 0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x4Bu, 0x0Cu, 0x22u,
- 0x02u, 0xFBu, 0x00u, 0x30u, 0x40u, 0x78u, 0x70u, 0x47u,
- 0x78u, 0xC1u, 0xFFu, 0x1Fu, 0x01u, 0x38u, 0xC3u, 0xB2u,
- 0x07u, 0x2Bu, 0x0Cu, 0xD8u, 0x19u, 0x01u, 0x07u, 0x4Au,
- 0xCBu, 0xB2u, 0x98u, 0x5Cu, 0x51u, 0x1Cu, 0x5Bu, 0x5Cu,
- 0x00u, 0xF0u, 0x0Fu, 0x02u, 0x43u, 0xEAu, 0x02u, 0x20u,
- 0x81u, 0x1Eu, 0x88u, 0xB2u, 0x70u, 0x47u, 0x00u, 0x20u,
- 0x70u, 0x47u, 0x00u, 0xBFu, 0x0Cu, 0x60u, 0x00u, 0x40u,
- 0x43u, 0x1Eu, 0xDBu, 0xB2u, 0x07u, 0x2Bu, 0xF0u, 0xB5u,
- 0x2Fu, 0xD8u, 0x18u, 0x4Eu, 0x1Cu, 0x01u, 0x0Cu, 0x27u,
- 0xE3u, 0xB2u, 0x07u, 0xFBu, 0x00u, 0x64u, 0xE7u, 0x88u,
- 0x15u, 0x4Du, 0xBFu, 0xB2u, 0xC7u, 0xF5u, 0x00u, 0x77u,
- 0xBAu, 0x42u, 0x1Du, 0x44u, 0x03u, 0xD9u, 0xE2u, 0x88u,
- 0xC2u, 0xF5u, 0x00u, 0x74u, 0xA2u, 0xB2u, 0x0Cu, 0x24u,
- 0x04u, 0xFBu, 0x00u, 0x66u, 0xF4u, 0x78u, 0x44u, 0xEAu,
- 0x12u, 0x26u, 0x0Eu, 0x4Cu, 0x1Eu, 0x55u, 0xD6u, 0xB2u,
- 0x01u, 0x34u, 0x1Eu, 0x55u, 0x49u, 0xB9u, 0x09u, 0x4Au,
- 0x0Cu, 0x21u, 0x01u, 0xFBu, 0x00u, 0x20u, 0x00u, 0x21u,
- 0x41u, 0x70u, 0x40u, 0x79u, 0x08u, 0x4Au, 0x98u, 0x54u,
- 0xF0u, 0xBDu, 0x00u, 0x24u, 0xA6u, 0xB2u, 0x96u, 0x42u,
- 0xF1u, 0xD2u, 0x0Eu, 0x5Du, 0x01u, 0x34u, 0x2Eu, 0x70u,
- 0xF8u, 0xE7u, 0xF0u, 0xBDu, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
- 0x88u, 0x60u, 0x00u, 0x40u, 0x0Cu, 0x60u, 0x00u, 0x40u,
- 0x0Eu, 0x60u, 0x00u, 0x40u, 0x43u, 0x1Eu, 0xDBu, 0xB2u,
- 0x07u, 0x2Bu, 0x0Au, 0xD8u, 0x05u, 0x4Au, 0x0Cu, 0x21u,
- 0x01u, 0xFBu, 0x00u, 0x20u, 0x00u, 0x21u, 0x41u, 0x70u,
- 0x1Bu, 0x01u, 0x40u, 0x79u, 0x02u, 0x4Au, 0xDBu, 0xB2u,
- 0x98u, 0x54u, 0x70u, 0x47u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x70u, 0x47u, 0x00u, 0xBFu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x04u, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u, 0xFFu, 0x00u,
+ 0x1Au, 0xB1u, 0x18u, 0x78u, 0x00u, 0x22u, 0xC0u, 0xB2u,
+ 0x1Au, 0x70u, 0x70u, 0x47u, 0x68u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x02u, 0x4Bu, 0x0Cu, 0x22u, 0x02u, 0xFBu, 0x00u, 0x30u,
+ 0x40u, 0x78u, 0x70u, 0x47u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x01u, 0x38u, 0xC3u, 0xB2u, 0x07u, 0x2Bu, 0x0Cu, 0xD8u,
+ 0x07u, 0x4Au, 0x1Bu, 0x01u, 0xDBu, 0xB2u, 0x98u, 0x5Cu,
+ 0x01u, 0x32u, 0x9Bu, 0x5Cu, 0x00u, 0xF0u, 0x0Fu, 0x00u,
+ 0x43u, 0xEAu, 0x00u, 0x20u, 0x02u, 0x38u, 0x80u, 0xB2u,
+ 0x70u, 0x47u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0xBFu,
+ 0x0Cu, 0x60u, 0x00u, 0x40u, 0x43u, 0x1Eu, 0xDBu, 0xB2u,
+ 0x07u, 0x2Bu, 0xF0u, 0xB5u, 0x2Fu, 0xD8u, 0x18u, 0x4Eu,
+ 0x0Cu, 0x24u, 0x04u, 0xFBu, 0x00u, 0x64u, 0xE7u, 0x88u,
+ 0x1Bu, 0x01u, 0xBFu, 0xB2u, 0x15u, 0x4Du, 0xC7u, 0xF5u,
+ 0x00u, 0x77u, 0xDBu, 0xB2u, 0xBAu, 0x42u, 0x1Du, 0x44u,
+ 0x03u, 0xD9u, 0xE2u, 0x88u, 0xC2u, 0xF5u, 0x00u, 0x72u,
+ 0x92u, 0xB2u, 0x0Cu, 0x24u, 0x04u, 0xFBu, 0x00u, 0x64u,
+ 0xE7u, 0x78u, 0x0Fu, 0x4Cu, 0x47u, 0xEAu, 0x12u, 0x27u,
+ 0x1Fu, 0x55u, 0xD7u, 0xB2u, 0x01u, 0x34u, 0x1Fu, 0x55u,
+ 0x49u, 0xB9u, 0x0Cu, 0x22u, 0x02u, 0xFBu, 0x00u, 0x60u,
+ 0x00u, 0x22u, 0x42u, 0x70u, 0x41u, 0x79u, 0x09u, 0x4Au,
+ 0xC9u, 0xB2u, 0x99u, 0x54u, 0xF0u, 0xBDu, 0x00u, 0x24u,
+ 0xA7u, 0xB2u, 0x97u, 0x42u, 0xF1u, 0xD2u, 0x0Fu, 0x5Du,
+ 0x01u, 0x34u, 0x2Fu, 0x70u, 0xF8u, 0xE7u, 0xF0u, 0xBDu,
+ 0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x88u, 0x60u, 0x00u, 0x40u,
+ 0x0Cu, 0x60u, 0x00u, 0x40u, 0x0Eu, 0x60u, 0x00u, 0x40u,
+ 0x43u, 0x1Eu, 0xDBu, 0xB2u, 0x07u, 0x2Bu, 0x0Bu, 0xD8u,
+ 0x06u, 0x4Au, 0x0Cu, 0x21u, 0x01u, 0xFBu, 0x00u, 0x20u,
+ 0x00u, 0x22u, 0x42u, 0x70u, 0x41u, 0x79u, 0x1Bu, 0x01u,
+ 0x03u, 0x4Au, 0xDBu, 0xB2u, 0xC9u, 0xB2u, 0x99u, 0x54u,
+ 0x70u, 0x47u, 0x00u, 0xBFu, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
0x0Eu, 0x60u, 0x00u, 0x40u, 0xF8u, 0xB5u, 0x43u, 0x1Eu,
- 0x0Du, 0x46u, 0xD9u, 0xB2u, 0x07u, 0x29u, 0x07u, 0x46u,
- 0x14u, 0x46u, 0x16u, 0xD8u, 0xBDu, 0xB1u, 0x0Au, 0x01u,
- 0x0Cu, 0x4Eu, 0xD3u, 0xB2u, 0x9Eu, 0x19u, 0xFFu, 0xF7u,
- 0x89u, 0xFFu, 0xA0u, 0x42u, 0x28u, 0xBFu, 0x20u, 0x46u,
- 0x84u, 0xB2u, 0x00u, 0x22u, 0x90u, 0xB2u, 0xA0u, 0x42u,
- 0x03u, 0xD2u, 0x31u, 0x78u, 0xA9u, 0x54u, 0x01u, 0x32u,
- 0xF8u, 0xE7u, 0x38u, 0x46u, 0xFFu, 0xF7u, 0xCEu, 0xFFu,
- 0x02u, 0xE0u, 0x00u, 0x24u, 0x00u, 0xE0u, 0x2Cu, 0x46u,
+ 0xDBu, 0xB2u, 0x07u, 0x2Bu, 0x07u, 0x46u, 0x0Du, 0x46u,
+ 0x14u, 0x46u, 0x16u, 0xD8u, 0xB9u, 0xB1u, 0x1Bu, 0x01u,
+ 0x0Cu, 0x4Eu, 0xDBu, 0xB2u, 0x1Eu, 0x44u, 0xFFu, 0xF7u,
+ 0x87u, 0xFFu, 0xA0u, 0x42u, 0x28u, 0xBFu, 0x20u, 0x46u,
+ 0x84u, 0xB2u, 0x00u, 0x23u, 0x9Au, 0xB2u, 0xA2u, 0x42u,
+ 0x03u, 0xD2u, 0x32u, 0x78u, 0xEAu, 0x54u, 0x01u, 0x33u,
+ 0xF8u, 0xE7u, 0x38u, 0x46u, 0xFFu, 0xF7u, 0xCCu, 0xFFu,
+ 0x02u, 0xE0u, 0x00u, 0x24u, 0x00u, 0xE0u, 0x0Cu, 0x46u,
0x20u, 0x46u, 0xF8u, 0xBDu, 0x88u, 0x60u, 0x00u, 0x40u,
- 0x1Bu, 0x4Bu, 0x1Cu, 0x49u, 0x1Au, 0x88u, 0x08u, 0x78u,
- 0x82u, 0x18u, 0x91u, 0xB2u, 0x19u, 0x80u, 0x1Au, 0x49u,
- 0x1Au, 0x4Bu, 0xCAu, 0xB2u, 0x18u, 0x88u, 0x80u, 0xB2u,
- 0x78u, 0xB1u, 0x19u, 0x4Au, 0x91u, 0x42u, 0x0Bu, 0xD0u,
- 0x5Au, 0x68u, 0x10u, 0x78u, 0x01u, 0xF8u, 0x01u, 0x0Bu,
- 0x5Au, 0x68u, 0x50u, 0x1Cu, 0x58u, 0x60u, 0x1Au, 0x88u,
- 0x50u, 0x1Eu, 0x82u, 0xB2u, 0x1Au, 0x80u, 0xEBu, 0xE7u,
- 0x08u, 0x22u, 0x0Eu, 0x49u, 0x0Bu, 0x78u, 0x08u, 0x2Bu,
- 0x00u, 0xD0u, 0x5Au, 0xB1u, 0x0Fu, 0x48u, 0x01u, 0x78u,
- 0x81u, 0xF0u, 0x80u, 0x03u, 0x0Eu, 0x49u, 0x03u, 0x70u,
- 0x0Fu, 0x20u, 0x0Eu, 0x4Bu, 0x08u, 0x70u, 0x02u, 0x20u,
- 0x18u, 0x70u, 0x04u, 0xE0u, 0x0Au, 0x49u, 0x0Bu, 0x4Bu,
- 0x02u, 0x20u, 0x08u, 0x70u, 0x18u, 0x70u, 0x03u, 0x49u,
- 0x09u, 0x48u, 0x0Au, 0x70u, 0x02u, 0x70u, 0x70u, 0x47u,
- 0xE8u, 0xC1u, 0xFFu, 0x1Fu, 0xE5u, 0xC1u, 0xFFu, 0x1Fu,
- 0x00u, 0x60u, 0x00u, 0x40u, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
- 0x08u, 0x60u, 0x00u, 0x40u, 0x6Eu, 0xC1u, 0xFFu, 0x1Fu,
- 0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
- 0xE6u, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x4Bu, 0x02u, 0x22u,
- 0x1Au, 0x70u, 0x07u, 0x49u, 0x07u, 0x4Bu, 0x80u, 0x20u,
- 0x0Fu, 0x22u, 0x08u, 0x70u, 0x1Au, 0x70u, 0x06u, 0x49u,
- 0x06u, 0x4Au, 0x00u, 0x20u, 0x08u, 0x70u, 0x10u, 0x70u,
- 0x01u, 0x20u, 0x70u, 0x47u, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
- 0x6Eu, 0xC1u, 0xFFu, 0x1Fu, 0x5Du, 0xC1u, 0xFFu, 0x1Fu,
- 0xE5u, 0xC1u, 0xFFu, 0x1Fu, 0xE6u, 0xC1u, 0xFFu, 0x1Fu,
- 0x10u, 0xB5u, 0x15u, 0x4Bu, 0x1Au, 0x78u, 0x15u, 0x4Bu,
- 0x02u, 0xF0u, 0x0Fu, 0x00u, 0x81u, 0x1Eu, 0x18u, 0x88u,
- 0xCAu, 0xB2u, 0x11u, 0x18u, 0x88u, 0xB2u, 0x12u, 0x49u,
- 0x18u, 0x80u, 0x12u, 0x4Bu, 0x18u, 0x88u, 0x80u, 0xB2u,
- 0x70u, 0xB1u, 0x6Au, 0xB1u, 0x58u, 0x68u, 0x11u, 0xF8u,
- 0x01u, 0x4Bu, 0x01u, 0x3Au, 0x04u, 0x70u, 0x58u, 0x68u,
- 0xD2u, 0xB2u, 0x01u, 0x30u, 0x58u, 0x60u, 0x18u, 0x88u,
- 0x01u, 0x38u, 0x80u, 0xB2u, 0x18u, 0x80u, 0xECu, 0xE7u,
- 0x09u, 0x49u, 0x0Au, 0x4Bu, 0x0Au, 0x70u, 0x1Au, 0x78u,
- 0x0Bu, 0x21u, 0x82u, 0xF0u, 0x80u, 0x00u, 0x18u, 0x70u,
- 0x07u, 0x4Bu, 0x19u, 0x70u, 0x10u, 0xBDu, 0x00u, 0xBFu,
- 0x29u, 0x60u, 0x00u, 0x40u, 0xE8u, 0xC1u, 0xFFu, 0x1Fu,
- 0x00u, 0x60u, 0x00u, 0x40u, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
- 0xE6u, 0xC1u, 0xFFu, 0x1Fu, 0x6Eu, 0xC1u, 0xFFu, 0x1Fu,
- 0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x06u, 0x4Au, 0x07u, 0x48u,
- 0x06u, 0x23u, 0x13u, 0x70u, 0x03u, 0x70u, 0x06u, 0x4Bu,
- 0x06u, 0x48u, 0x80u, 0x21u, 0x00u, 0x22u, 0x19u, 0x70u,
- 0x02u, 0x70u, 0x01u, 0x20u, 0x70u, 0x47u, 0x00u, 0xBFu,
- 0x72u, 0xC1u, 0xFFu, 0x1Fu, 0x5Du, 0xC1u, 0xFFu, 0x1Fu,
- 0x6Eu, 0xC1u, 0xFFu, 0x1Fu, 0xE6u, 0xC1u, 0xFFu, 0x1Fu,
- 0x05u, 0x4Bu, 0x9Au, 0x68u, 0x3Au, 0xB1u, 0x99u, 0x68u,
- 0x04u, 0x4Au, 0x08u, 0x70u, 0x98u, 0x68u, 0x11u, 0x88u,
- 0x41u, 0x80u, 0x00u, 0x20u, 0x98u, 0x60u, 0x70u, 0x47u,
- 0x60u, 0xC1u, 0xFFu, 0x1Fu, 0xE8u, 0xC1u, 0xFFu, 0x1Fu,
- 0x08u, 0xB5u, 0x0Au, 0x4Bu, 0x1Au, 0x78u, 0x32u, 0xB1u,
- 0x19u, 0x78u, 0x09u, 0x4Au, 0x41u, 0xF0u, 0x80u, 0x00u,
- 0x00u, 0x21u, 0x10u, 0x70u, 0x19u, 0x70u, 0x07u, 0x4Bu,
- 0x00u, 0x20u, 0x18u, 0x70u, 0x01u, 0x20u, 0xFFu, 0xF7u,
- 0xDFu, 0xFFu, 0x05u, 0x49u, 0x03u, 0x22u, 0x0Au, 0x70u,
- 0x08u, 0xBDu, 0x00u, 0xBFu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu,
- 0x08u, 0x60u, 0x00u, 0x40u, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
- 0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x05u, 0x4Bu,
+ 0x30u, 0xB5u, 0x1Au, 0x4Bu, 0x1Au, 0x48u, 0x1Au, 0x88u,
+ 0x01u, 0x78u, 0x0Au, 0x44u, 0x92u, 0xB2u, 0x19u, 0x49u,
+ 0x1Au, 0x80u, 0x19u, 0x4Bu, 0xCAu, 0xB2u, 0x1Cu, 0x88u,
+ 0xA4u, 0xB2u, 0x84u, 0xB1u, 0x17u, 0x4Au, 0x91u, 0x42u,
+ 0x0Cu, 0xD0u, 0x5Au, 0x68u, 0x12u, 0x78u, 0xD2u, 0xB2u,
+ 0x01u, 0xF8u, 0x01u, 0x2Bu, 0x5Au, 0x68u, 0x01u, 0x32u,
+ 0x5Au, 0x60u, 0x1Au, 0x88u, 0x01u, 0x3Au, 0x92u, 0xB2u,
+ 0x1Au, 0x80u, 0xEAu, 0xE7u, 0x08u, 0x22u, 0x03u, 0x78u,
+ 0x0Fu, 0x4Cu, 0x08u, 0x2Bu, 0x0Fu, 0x4Bu, 0x00u, 0xD0u,
+ 0x42u, 0xB1u, 0x0Fu, 0x49u, 0x0Du, 0x78u, 0x85u, 0xF0u,
+ 0x80u, 0x05u, 0x0Du, 0x70u, 0x0Fu, 0x21u, 0x21u, 0x70u,
+ 0x02u, 0x21u, 0x01u, 0xE0u, 0x02u, 0x21u, 0x21u, 0x70u,
+ 0x19u, 0x70u, 0x0Au, 0x4Bu, 0x02u, 0x70u, 0x1Au, 0x70u,
+ 0x30u, 0xBDu, 0x00u, 0xBFu, 0xE0u, 0xC1u, 0xFFu, 0x1Fu,
+ 0xDDu, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x60u, 0x00u, 0x40u,
+ 0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0x60u, 0x00u, 0x40u,
+ 0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+ 0x66u, 0xC1u, 0xFFu, 0x1Fu, 0xDEu, 0xC1u, 0xFFu, 0x1Fu,
+ 0x07u, 0x4Bu, 0x02u, 0x22u, 0x1Au, 0x70u, 0x07u, 0x4Bu,
+ 0x80u, 0x22u, 0x1Au, 0x70u, 0x06u, 0x4Bu, 0x0Fu, 0x22u,
+ 0x1Au, 0x70u, 0x06u, 0x4Au, 0x00u, 0x23u, 0x13u, 0x70u,
+ 0x05u, 0x4Au, 0x01u, 0x20u, 0x13u, 0x70u, 0x70u, 0x47u,
+ 0x6Au, 0xC1u, 0xFFu, 0x1Fu, 0x66u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x55u, 0xC1u, 0xFFu, 0x1Fu, 0xDDu, 0xC1u, 0xFFu, 0x1Fu,
+ 0xDEu, 0xC1u, 0xFFu, 0x1Fu, 0x10u, 0xB5u, 0x15u, 0x4Bu,
+ 0x1Au, 0x78u, 0x15u, 0x4Bu, 0x02u, 0xF0u, 0x0Fu, 0x02u,
+ 0x19u, 0x88u, 0x02u, 0x3Au, 0xD2u, 0xB2u, 0x11u, 0x44u,
+ 0x89u, 0xB2u, 0x19u, 0x80u, 0x11u, 0x49u, 0x12u, 0x4Bu,
+ 0x18u, 0x88u, 0x80u, 0xB2u, 0x78u, 0xB1u, 0x72u, 0xB1u,
+ 0x58u, 0x68u, 0x11u, 0xF8u, 0x01u, 0x4Bu, 0x01u, 0x3Au,
+ 0xE4u, 0xB2u, 0x04u, 0x70u, 0x58u, 0x68u, 0xD2u, 0xB2u,
+ 0x01u, 0x30u, 0x58u, 0x60u, 0x18u, 0x88u, 0x01u, 0x38u,
+ 0x80u, 0xB2u, 0x18u, 0x80u, 0xEBu, 0xE7u, 0x09u, 0x4Bu,
+ 0x1Au, 0x70u, 0x09u, 0x4Bu, 0x1Au, 0x78u, 0x82u, 0xF0u,
+ 0x80u, 0x02u, 0x1Au, 0x70u, 0x07u, 0x4Bu, 0x0Bu, 0x22u,
+ 0x1Au, 0x70u, 0x10u, 0xBDu, 0x29u, 0x60u, 0x00u, 0x40u,
+ 0xE0u, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x60u, 0x00u, 0x40u,
+ 0x58u, 0xC1u, 0xFFu, 0x1Fu, 0xDEu, 0xC1u, 0xFFu, 0x1Fu,
+ 0x66u, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x06u, 0x4Au, 0x06u, 0x23u, 0x13u, 0x70u, 0x06u, 0x4Au,
+ 0x01u, 0x20u, 0x13u, 0x70u, 0x05u, 0x4Bu, 0x80u, 0x22u,
+ 0x1Au, 0x70u, 0x05u, 0x4Bu, 0x00u, 0x22u, 0x1Au, 0x70u,
+ 0x70u, 0x47u, 0x00u, 0xBFu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+ 0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x66u, 0xC1u, 0xFFu, 0x1Fu,
+ 0xDEu, 0xC1u, 0xFFu, 0x1Fu, 0x05u, 0x4Bu, 0x9Au, 0x68u,
+ 0x3Au, 0xB1u, 0x9Au, 0x68u, 0x04u, 0x49u, 0x10u, 0x70u,
+ 0x9Au, 0x68u, 0x09u, 0x88u, 0x51u, 0x80u, 0x00u, 0x22u,
+ 0x9Au, 0x60u, 0x70u, 0x47u, 0x58u, 0xC1u, 0xFFu, 0x1Fu,
+ 0xE0u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x12u, 0x4Bu,
+ 0x1Au, 0x78u, 0xD2u, 0xB2u, 0x1Au, 0x70u, 0x1Bu, 0x78u,
+ 0xDBu, 0xB2u, 0x1Au, 0x06u, 0x02u, 0xD5u, 0x0Fu, 0x4Au,
+ 0x13u, 0x70u, 0x08u, 0xBDu, 0x02u, 0x20u, 0xFFu, 0xF7u,
+ 0xE1u, 0xFFu, 0x0Du, 0x4Bu, 0x1Bu, 0x78u, 0x03u, 0xF0u,
+ 0x60u, 0x03u, 0x20u, 0x2Bu, 0x05u, 0xD0u, 0x40u, 0x2Bu,
+ 0x06u, 0xD0u, 0x43u, 0xB9u, 0x00u, 0xF0u, 0x94u, 0xFCu,
+ 0x04u, 0xE0u, 0x00u, 0xF0u, 0xE1u, 0xFDu, 0x01u, 0xE0u,
+ 0x00u, 0xF0u, 0xD2u, 0xFDu, 0x10u, 0xB9u, 0x03u, 0x4Bu,
+ 0x03u, 0x22u, 0x1Au, 0x70u, 0x08u, 0xBDu, 0x00u, 0xBFu,
+ 0x28u, 0x60u, 0x00u, 0x40u, 0x55u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x00u, 0x60u, 0x00u, 0x40u, 0x08u, 0xB5u, 0x08u, 0x49u,
+ 0x08u, 0x4Bu, 0x01u, 0x20u, 0x1Au, 0x88u, 0x09u, 0x78u,
+ 0x0Au, 0x44u, 0x92u, 0xB2u, 0x1Au, 0x80u, 0x06u, 0x4Bu,
+ 0x00u, 0x22u, 0x1Au, 0x70u, 0xFFu, 0xF7u, 0xB6u, 0xFFu,
+ 0x04u, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u, 0x08u, 0xBDu,
+ 0xDDu, 0xC1u, 0xFFu, 0x1Fu, 0xE0u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x6Au, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x08u, 0xB5u, 0x0Cu, 0x4Bu, 0x1Bu, 0x78u, 0xDBu, 0xB2u,
+ 0x04u, 0x2Bu, 0x07u, 0xD0u, 0x06u, 0x2Bu, 0x09u, 0xD0u,
+ 0x02u, 0x2Bu, 0x0Du, 0xD1u, 0xBDu, 0xE8u, 0x08u, 0x40u,
+ 0xFFu, 0xF7u, 0xD8u, 0xBFu, 0xBDu, 0xE8u, 0x08u, 0x40u,
+ 0xFFu, 0xF7u, 0x48u, 0xBFu, 0x03u, 0x20u, 0xFFu, 0xF7u,
+ 0x95u, 0xFFu, 0x03u, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u,
+ 0x08u, 0xBDu, 0x00u, 0xBFu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+ 0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x05u, 0x4Bu,
0x00u, 0x22u, 0x01u, 0x20u, 0x1Au, 0x70u, 0xFFu, 0xF7u,
- 0xCBu, 0xFFu, 0x03u, 0x49u, 0x03u, 0x20u, 0x08u, 0x70u,
- 0x08u, 0xBDu, 0x00u, 0xBFu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
- 0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x4Bu, 0x18u, 0x78u,
- 0x04u, 0x28u, 0x05u, 0xD0u, 0x06u, 0x28u, 0x05u, 0xD0u,
- 0x02u, 0x28u, 0x05u, 0xD1u, 0xFFu, 0xF7u, 0x04u, 0xBFu,
- 0xFFu, 0xF7u, 0xE4u, 0xBFu, 0xFFu, 0xF7u, 0xC4u, 0xBFu,
- 0x70u, 0x47u, 0x00u, 0xBFu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
- 0x08u, 0xB5u, 0x08u, 0x49u, 0x08u, 0x4Bu, 0x1Au, 0x88u,
- 0x08u, 0x78u, 0x82u, 0x18u, 0x91u, 0xB2u, 0x19u, 0x80u,
- 0x06u, 0x4Bu, 0x00u, 0x20u, 0x18u, 0x70u, 0x01u, 0x20u,
- 0xFFu, 0xF7u, 0xA2u, 0xFFu, 0x04u, 0x49u, 0x03u, 0x22u,
- 0x0Au, 0x70u, 0x08u, 0xBDu, 0xE5u, 0xC1u, 0xFFu, 0x1Fu,
- 0xE8u, 0xC1u, 0xFFu, 0x1Fu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
- 0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x0Bu, 0x4Bu,
- 0x18u, 0x78u, 0x04u, 0x28u, 0x07u, 0xD0u, 0x06u, 0x28u,
- 0x09u, 0xD0u, 0x02u, 0x28u, 0x0Du, 0xD1u, 0xBDu, 0xE8u,
- 0x08u, 0x40u, 0xFFu, 0xF7u, 0xD9u, 0xBFu, 0xBDu, 0xE8u,
- 0x08u, 0x40u, 0xFFu, 0xF7u, 0x35u, 0xBFu, 0x03u, 0x20u,
- 0xFFu, 0xF7u, 0x82u, 0xFFu, 0x02u, 0x49u, 0x03u, 0x22u,
- 0x0Au, 0x70u, 0x08u, 0xBDu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
- 0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x11u, 0x4Bu,
- 0x1Au, 0x78u, 0x1Au, 0x70u, 0x18u, 0x78u, 0x02u, 0x06u,
- 0x02u, 0xD5u, 0x0Fu, 0x4Bu, 0x18u, 0x70u, 0x08u, 0xBDu,
- 0x02u, 0x20u, 0xFFu, 0xF7u, 0x6Du, 0xFFu, 0x0Du, 0x49u,
- 0x0Bu, 0x78u, 0x03u, 0xF0u, 0x60u, 0x02u, 0x20u, 0x2Au,
- 0x05u, 0xD0u, 0x40u, 0x2Au, 0x06u, 0xD0u, 0x42u, 0xB9u,
- 0x00u, 0xF0u, 0x4Au, 0xFCu, 0x04u, 0xE0u, 0x00u, 0xF0u,
- 0x8Du, 0xFDu, 0x01u, 0xE0u, 0x00u, 0xF0u, 0x7Eu, 0xFDu,
- 0x10u, 0xB9u, 0x03u, 0x49u, 0x03u, 0x20u, 0x08u, 0x70u,
- 0x08u, 0xBDu, 0x00u, 0xBFu, 0x28u, 0x60u, 0x00u, 0x40u,
- 0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x60u, 0x00u, 0x40u,
- 0x08u, 0xB5u, 0x22u, 0x4Bu, 0x1Au, 0x78u, 0xD0u, 0xB2u,
- 0x00u, 0xF0u, 0x10u, 0x01u, 0xCBu, 0xB2u, 0x00u, 0x2Bu,
- 0x3Bu, 0xD0u, 0x52u, 0xB2u, 0x00u, 0x2Au, 0x0Au, 0xDAu,
- 0x00u, 0xF0u, 0x0Fu, 0x01u, 0x01u, 0x29u, 0x34u, 0xD1u,
- 0xFFu, 0xF7u, 0xC4u, 0xFFu, 0x1Au, 0x4Bu, 0x18u, 0x78u,
- 0x00u, 0x06u, 0x0Du, 0xD5u, 0x08u, 0xBDu, 0x00u, 0xF0u,
- 0x40u, 0x01u, 0xCBu, 0xB2u, 0x13u, 0xB1u, 0xFFu, 0xF7u,
- 0x71u, 0xFFu, 0x05u, 0xE0u, 0x00u, 0xF0u, 0x20u, 0x00u,
- 0xC2u, 0xB2u, 0x12u, 0xB3u, 0xFFu, 0xF7u, 0x96u, 0xFFu,
- 0x10u, 0x4Au, 0x11u, 0x78u, 0x09u, 0x06u, 0x1Cu, 0xD4u,
- 0x10u, 0x4Bu, 0x11u, 0x4Au, 0x18u, 0x78u, 0x11u, 0x78u,
- 0x41u, 0xEAu, 0x00u, 0x03u, 0x0Fu, 0x48u, 0x03u, 0x70u,
- 0x02u, 0x78u, 0x93u, 0x42u, 0x11u, 0xD1u, 0x0Au, 0x49u,
- 0x08u, 0x4Bu, 0x0Au, 0x78u, 0x18u, 0x78u, 0x00u, 0xF0u,
- 0x80u, 0x00u, 0xC0u, 0xB2u, 0x20u, 0xB9u, 0x0Au, 0x78u,
- 0x1Au, 0x70u, 0x19u, 0x78u, 0x01u, 0xF0u, 0x0Fu, 0x02u,
- 0x03u, 0x4Bu, 0x18u, 0x78u, 0x82u, 0x42u, 0xEEu, 0xD1u,
- 0x08u, 0xBDu, 0x08u, 0xBDu, 0x28u, 0x60u, 0x00u, 0x40u,
- 0x5Du, 0xC1u, 0xFFu, 0x1Fu, 0x6Eu, 0xC1u, 0xFFu, 0x1Fu,
- 0xE6u, 0xC1u, 0xFFu, 0x1Fu, 0x29u, 0x60u, 0x00u, 0x40u,
+ 0x85u, 0xFFu, 0x03u, 0x4Bu, 0x03u, 0x22u, 0x1Au, 0x70u,
+ 0x08u, 0xBDu, 0x00u, 0xBFu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+ 0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x0Au, 0x4Bu,
+ 0x1Au, 0x78u, 0x32u, 0xB1u, 0x19u, 0x78u, 0x09u, 0x4Au,
+ 0x41u, 0xF0u, 0x80u, 0x01u, 0x11u, 0x70u, 0x00u, 0x22u,
+ 0x1Au, 0x70u, 0x07u, 0x4Bu, 0x00u, 0x22u, 0x01u, 0x20u,
+ 0x1Au, 0x70u, 0xFFu, 0xF7u, 0x6Bu, 0xFFu, 0x05u, 0x4Bu,
+ 0x03u, 0x22u, 0x1Au, 0x70u, 0x08u, 0xBDu, 0x00u, 0xBFu,
+ 0x54u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0x60u, 0x00u, 0x40u,
+ 0x6Au, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x07u, 0x4Bu, 0x1Bu, 0x78u, 0xDBu, 0xB2u, 0x04u, 0x2Bu,
+ 0x05u, 0xD0u, 0x06u, 0x2Bu, 0x05u, 0xD0u, 0x02u, 0x2Bu,
+ 0x05u, 0xD1u, 0xFFu, 0xF7u, 0xA1u, 0xBEu, 0xFFu, 0xF7u,
+ 0xC5u, 0xBFu, 0xFFu, 0xF7u, 0xD3u, 0xBFu, 0x70u, 0x47u,
+ 0x6Au, 0xC1u, 0xFFu, 0x1Fu, 0x10u, 0xB5u, 0x1Du, 0x4Cu,
+ 0x23u, 0x78u, 0xDBu, 0xB2u, 0xDAu, 0x06u, 0x33u, 0xD5u,
+ 0x18u, 0x06u, 0x0Au, 0xD5u, 0x03u, 0xF0u, 0x0Fu, 0x03u,
+ 0x01u, 0x2Bu, 0x2Du, 0xD1u, 0xFFu, 0xF7u, 0x4Eu, 0xFFu,
+ 0x17u, 0x4Bu, 0x1Bu, 0x78u, 0x19u, 0x06u, 0x09u, 0xD5u,
+ 0x10u, 0xBDu, 0x5Au, 0x06u, 0x02u, 0xD5u, 0xFFu, 0xF7u,
+ 0xD7u, 0xFFu, 0x03u, 0xE0u, 0x9Bu, 0x06u, 0x1Fu, 0xD5u,
+ 0xFFu, 0xF7u, 0x86u, 0xFFu, 0x23u, 0x78u, 0x1Bu, 0x06u,
+ 0x1Au, 0xD4u, 0x10u, 0x4Bu, 0x10u, 0x4Au, 0x1Bu, 0x78u,
+ 0x12u, 0x78u, 0x13u, 0x43u, 0x0Fu, 0x4Au, 0x13u, 0x70u,
+ 0x12u, 0x78u, 0x93u, 0x42u, 0x10u, 0xD1u, 0x0Au, 0x4Bu,
+ 0x08u, 0x49u, 0x1Au, 0x78u, 0x20u, 0x78u, 0xD2u, 0xB2u,
+ 0x00u, 0x06u, 0x05u, 0xD4u, 0x1Au, 0x78u, 0xD2u, 0xB2u,
+ 0x0Au, 0x70u, 0x0Au, 0x78u, 0x02u, 0xF0u, 0x0Fu, 0x02u,
+ 0x1Bu, 0x78u, 0x9Au, 0x42u, 0xEFu, 0xD1u, 0x10u, 0xBDu,
+ 0x10u, 0xBDu, 0x00u, 0xBFu, 0x28u, 0x60u, 0x00u, 0x40u,
+ 0x55u, 0xC1u, 0xFFu, 0x1Fu, 0x66u, 0xC1u, 0xFFu, 0x1Fu,
+ 0xDEu, 0xC1u, 0xFFu, 0x1Fu, 0x29u, 0x60u, 0x00u, 0x40u,
0x05u, 0x4Au, 0x00u, 0x23u, 0x13u, 0x80u, 0x05u, 0x4Au,
0x91u, 0x68u, 0x19u, 0xB1u, 0x91u, 0x68u, 0x0Bu, 0x70u,
- 0x90u, 0x68u, 0x43u, 0x80u, 0x70u, 0x47u, 0x00u, 0xBFu,
- 0xE8u, 0xC1u, 0xFFu, 0x1Fu, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
- 0x08u, 0xB5u, 0x0Cu, 0x49u, 0x0Cu, 0x4Bu, 0x04u, 0x22u,
- 0x80u, 0x20u, 0x1Au, 0x70u, 0x08u, 0x70u, 0xFFu, 0xF7u,
- 0xE7u, 0xFFu, 0x0Au, 0x4Bu, 0x1Au, 0x78u, 0x58u, 0x1Eu,
- 0x09u, 0x4Bu, 0x01u, 0x78u, 0x18u, 0x88u, 0x41u, 0xEAu,
- 0x02u, 0x22u, 0x81u, 0xB2u, 0x91u, 0x42u, 0x88u, 0xBFu,
- 0x1Au, 0x80u, 0x06u, 0x4Bu, 0x0Bu, 0x22u, 0x1Au, 0x70u,
- 0x01u, 0x20u, 0x08u, 0xBDu, 0x6Eu, 0xC1u, 0xFFu, 0x1Fu,
- 0x72u, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x60u, 0x00u, 0x40u,
- 0x60u, 0xC1u, 0xFFu, 0x1Fu, 0x5Du, 0xC1u, 0xFFu, 0x1Fu,
- 0x10u, 0xB5u, 0x0Fu, 0x4Cu, 0x23u, 0x88u, 0x98u, 0xB2u,
- 0x10u, 0xB9u, 0xFFu, 0xF7u, 0x5Bu, 0xFEu, 0x14u, 0xE0u,
- 0x0Cu, 0x49u, 0x0Du, 0x4Bu, 0x02u, 0x22u, 0x00u, 0x20u,
- 0x0Au, 0x70u, 0x18u, 0x70u, 0xFFu, 0xF7u, 0xBCu, 0xFFu,
- 0x0Au, 0x49u, 0x48u, 0x1Eu, 0x0Au, 0x78u, 0x03u, 0x78u,
- 0x43u, 0xEAu, 0x02u, 0x21u, 0x22u, 0x88u, 0x90u, 0xB2u,
- 0x88u, 0x42u, 0x88u, 0xBFu, 0x21u, 0x80u, 0xFFu, 0xF7u,
- 0xFBu, 0xFDu, 0x01u, 0x20u, 0x10u, 0xBDu, 0x00u, 0xBFu,
- 0x60u, 0xC1u, 0xFFu, 0x1Fu, 0x72u, 0xC1u, 0xFFu, 0x1Fu,
- 0x6Eu, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x60u, 0x00u, 0x40u,
- 0x09u, 0x4Bu, 0x0Au, 0x48u, 0x1Bu, 0x78u, 0x02u, 0x7Bu,
- 0x02u, 0xF0u, 0x03u, 0x01u, 0x01u, 0x29u, 0x03u, 0xD0u,
- 0xC3u, 0x7Bu, 0x83u, 0xF0u, 0x80u, 0x02u, 0xC2u, 0x73u,
- 0x01u, 0x21u, 0x41u, 0x73u, 0x04u, 0x48u, 0x03u, 0x78u,
- 0x03u, 0xF0u, 0xFEu, 0x02u, 0x02u, 0x70u, 0x70u, 0x47u,
- 0x0Eu, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
- 0x0Bu, 0x60u, 0x00u, 0x40u, 0x09u, 0x4Bu, 0x0Au, 0x48u,
- 0x1Bu, 0x78u, 0x02u, 0x7Eu, 0x02u, 0xF0u, 0x03u, 0x01u,
- 0x01u, 0x29u, 0x03u, 0xD0u, 0xC3u, 0x7Eu, 0x83u, 0xF0u,
- 0x80u, 0x02u, 0xC2u, 0x76u, 0x01u, 0x21u, 0x41u, 0x76u,
- 0x04u, 0x48u, 0x03u, 0x78u, 0x03u, 0xF0u, 0xFDu, 0x02u,
- 0x02u, 0x70u, 0x70u, 0x47u, 0x1Eu, 0x60u, 0x00u, 0x40u,
- 0x78u, 0xC1u, 0xFFu, 0x1Fu, 0x0Bu, 0x60u, 0x00u, 0x40u,
- 0x70u, 0x47u, 0xFFu, 0xF7u, 0xE7u, 0xBCu, 0x00u, 0x00u,
- 0x08u, 0xB5u, 0x0Bu, 0x4Bu, 0x18u, 0x78u, 0x41u, 0x1Eu,
- 0xC8u, 0xB2u, 0x00u, 0xF0u, 0x59u, 0xF9u, 0x09u, 0x4Au,
- 0x09u, 0x49u, 0x13u, 0x78u, 0x00u, 0xEBu, 0xC3u, 0x00u,
- 0x42u, 0x69u, 0xCBu, 0x5Cu, 0x02u, 0xEBu, 0xC3u, 0x00u,
- 0x42u, 0x68u, 0x06u, 0x4Bu, 0x50u, 0x6Au, 0x01u, 0x78u,
- 0x19u, 0x80u, 0x58u, 0x60u, 0x08u, 0xBDu, 0x00u, 0xBFu,
- 0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x60u, 0x00u, 0x40u,
- 0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
- 0x08u, 0xB5u, 0x0Du, 0x4Bu, 0x18u, 0x78u, 0x41u, 0x1Eu,
- 0xC8u, 0xB2u, 0x00u, 0xF0u, 0x39u, 0xF9u, 0x0Bu, 0x4Au,
- 0x0Bu, 0x49u, 0x13u, 0x78u, 0x00u, 0xEBu, 0xC3u, 0x00u,
- 0x42u, 0x69u, 0xCBu, 0x5Cu, 0x02u, 0xEBu, 0xC3u, 0x00u,
- 0x42u, 0x68u, 0xD3u, 0x69u, 0x07u, 0x4Au, 0x59u, 0x78u,
- 0x13u, 0xF8u, 0x02u, 0x0Bu, 0x40u, 0xEAu, 0x01u, 0x21u,
- 0x11u, 0x80u, 0x53u, 0x60u, 0x08u, 0xBDu, 0x00u, 0xBFu,
- 0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x60u, 0x00u, 0x40u,
- 0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
- 0x10u, 0xB5u, 0x16u, 0x4Cu, 0x00u, 0x23u, 0x16u, 0x48u,
- 0x23u, 0x80u, 0x01u, 0x78u, 0x4Au, 0x1Eu, 0xD0u, 0xB2u,
- 0x00u, 0xF0u, 0x12u, 0xF9u, 0x13u, 0x49u, 0x14u, 0x4Bu,
- 0x1Bu, 0x78u, 0x0Au, 0x78u, 0x00u, 0xEBu, 0xC2u, 0x00u,
- 0x41u, 0x69u, 0xD2u, 0xB9u, 0x11u, 0x4Au, 0x01u, 0x3Bu,
- 0x10u, 0x78u, 0xDAu, 0xB2u, 0x01u, 0xEBu, 0xC0u, 0x01u,
- 0x02u, 0x2Au, 0x49u, 0x68u, 0x11u, 0xD8u, 0x0Eu, 0x4Au,
- 0x01u, 0xEBu, 0xC3u, 0x00u, 0x12u, 0x78u, 0x11u, 0xF8u,
- 0x33u, 0x10u, 0x91u, 0x42u, 0x09u, 0xD3u, 0x0Cu, 0x23u,
- 0x5Au, 0x43u, 0x41u, 0x68u, 0x8Bu, 0x18u, 0x58u, 0x68u,
- 0x8Au, 0x5Au, 0x99u, 0x68u, 0x60u, 0x60u, 0x22u, 0x80u,
- 0xA1u, 0x60u, 0x10u, 0xBDu, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
- 0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x04u, 0x60u, 0x00u, 0x40u,
- 0x03u, 0x60u, 0x00u, 0x40u, 0x5Eu, 0xC1u, 0xFFu, 0x1Fu,
- 0x02u, 0x60u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x3Au, 0x4Bu,
- 0x3Au, 0x4Au, 0x18u, 0x78u, 0x11u, 0x78u, 0x09u, 0x06u,
- 0x34u, 0xD5u, 0x51u, 0x1Cu, 0x0Bu, 0x78u, 0x5Au, 0x1Eu,
- 0x05u, 0x2Au, 0x67u, 0xD8u, 0xDFu, 0xE8u, 0x02u, 0xF0u,
- 0x10u, 0x18u, 0x27u, 0x66u, 0x66u, 0x03u, 0x34u, 0x48u,
- 0x01u, 0x78u, 0x21u, 0x29u, 0x02u, 0xD1u, 0xFFu, 0xF7u,
- 0x6Bu, 0xFFu, 0x07u, 0xE0u, 0x03u, 0x78u, 0x22u, 0x2Bu,
- 0x58u, 0xD1u, 0xFFu, 0xF7u, 0x85u, 0xFFu, 0x01u, 0xE0u,
- 0xFFu, 0xF7u, 0xA6u, 0xFFu, 0x2Du, 0x49u, 0x0Bu, 0x88u,
- 0x98u, 0xB2u, 0x00u, 0x28u, 0x4Eu, 0xD0u, 0x0Au, 0xE0u,
- 0x00u, 0x28u, 0x4Bu, 0xD1u, 0x2Au, 0x4Bu, 0x18u, 0x78u,
- 0x00u, 0x28u, 0x47u, 0xD1u, 0x27u, 0x48u, 0x01u, 0x22u,
- 0x28u, 0x49u, 0x02u, 0x80u, 0x41u, 0x60u, 0xBDu, 0xE8u,
- 0x10u, 0x40u, 0xFFu, 0xF7u, 0xEDu, 0xBEu, 0x00u, 0x28u,
- 0x3Cu, 0xD1u, 0x22u, 0x48u, 0x01u, 0x22u, 0x02u, 0x80u,
- 0x23u, 0x49u, 0xF3u, 0xE7u, 0x13u, 0x78u, 0x1Au, 0x06u,
- 0x34u, 0xD4u, 0x22u, 0x4Au, 0x11u, 0x78u, 0x09u, 0x29u,
- 0x05u, 0xD0u, 0x2Fu, 0xD3u, 0x0Au, 0x29u, 0x0Du, 0xD0u,
- 0x0Bu, 0x29u, 0x2Bu, 0xD1u, 0x22u, 0xE0u, 0xFFu, 0xF7u,
- 0x7Bu, 0xFFu, 0x18u, 0x4Bu, 0x1Au, 0x88u, 0x90u, 0xB2u,
- 0x00u, 0x28u, 0x23u, 0xD0u, 0xBDu, 0xE8u, 0x10u, 0x40u,
- 0xFFu, 0xF7u, 0xAAu, 0xBEu, 0xF0u, 0xB9u, 0x14u, 0x48u,
- 0x01u, 0x78u, 0xD9u, 0xB9u, 0x44u, 0x1Cu, 0x23u, 0x78u,
- 0x12u, 0x4Au, 0x13u, 0x70u, 0x14u, 0x4Bu, 0x14u, 0x78u,
- 0x18u, 0x78u, 0x84u, 0x42u, 0x01u, 0xD2u, 0x19u, 0x70u,
- 0x04u, 0xE0u, 0x19u, 0x78u, 0x01u, 0x29u, 0x01u, 0xD9u,
- 0x12u, 0x78u, 0x1Au, 0x70u, 0xBDu, 0xE8u, 0x10u, 0x40u,
- 0xFFu, 0xF7u, 0x6Cu, 0xBDu, 0x30u, 0xB9u, 0x08u, 0x48u,
- 0x03u, 0x78u, 0x01u, 0x2Bu, 0x02u, 0xD8u, 0x02u, 0x78u,
- 0x07u, 0x4Bu, 0xF2u, 0xE7u, 0x00u, 0x20u, 0x10u, 0xBDu,
+ 0x92u, 0x68u, 0x53u, 0x80u, 0x70u, 0x47u, 0x00u, 0xBFu,
+ 0xE0u, 0xC1u, 0xFFu, 0x1Fu, 0x58u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x10u, 0xB5u, 0x0Fu, 0x4Cu, 0x23u, 0x88u, 0x9Bu, 0xB2u,
+ 0x13u, 0xB9u, 0xFFu, 0xF7u, 0x85u, 0xFEu, 0x14u, 0xE0u,
+ 0x0Cu, 0x4Bu, 0x02u, 0x22u, 0x1Au, 0x70u, 0x0Cu, 0x4Bu,
+ 0x00u, 0x22u, 0x1Au, 0x70u, 0xFFu, 0xF7u, 0xE0u, 0xFFu,
+ 0x0Au, 0x4Bu, 0x1Au, 0x78u, 0x01u, 0x3Bu, 0x1Bu, 0x78u,
+ 0x43u, 0xEAu, 0x02u, 0x23u, 0x22u, 0x88u, 0x92u, 0xB2u,
+ 0x9Au, 0x42u, 0x88u, 0xBFu, 0x23u, 0x80u, 0xFFu, 0xF7u,
+ 0x27u, 0xFEu, 0x01u, 0x20u, 0x10u, 0xBDu, 0x00u, 0xBFu,
+ 0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+ 0x66u, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x60u, 0x00u, 0x40u,
+ 0x08u, 0xB5u, 0x0Cu, 0x4Bu, 0x04u, 0x22u, 0x1Au, 0x70u,
+ 0x0Bu, 0x4Bu, 0x80u, 0x22u, 0x1Au, 0x70u, 0xFFu, 0xF7u,
+ 0xBFu, 0xFFu, 0x0Au, 0x4Bu, 0x01u, 0x20u, 0x1Au, 0x78u,
+ 0x01u, 0x3Bu, 0x1Bu, 0x78u, 0x43u, 0xEAu, 0x02u, 0x22u,
+ 0x07u, 0x4Bu, 0x19u, 0x88u, 0x89u, 0xB2u, 0x91u, 0x42u,
+ 0x88u, 0xBFu, 0x1Au, 0x80u, 0x05u, 0x4Bu, 0x0Bu, 0x22u,
+ 0x1Au, 0x70u, 0x08u, 0xBDu, 0x6Au, 0xC1u, 0xFFu, 0x1Fu,
+ 0x66u, 0xC1u, 0xFFu, 0x1Fu, 0x07u, 0x60u, 0x00u, 0x40u,
+ 0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x09u, 0x4Bu, 0x1Bu, 0x78u, 0x09u, 0x4Bu, 0x1Au, 0x7Bu,
+ 0x02u, 0xF0u, 0x03u, 0x02u, 0x01u, 0x2Au, 0x03u, 0xD0u,
+ 0xDAu, 0x7Bu, 0x82u, 0xF0u, 0x80u, 0x02u, 0xDAu, 0x73u,
+ 0x01u, 0x22u, 0x5Au, 0x73u, 0x04u, 0x4Bu, 0x1Au, 0x78u,
+ 0x02u, 0xF0u, 0xFEu, 0x02u, 0x1Au, 0x70u, 0x70u, 0x47u,
+ 0x0Eu, 0x60u, 0x00u, 0x40u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x0Bu, 0x60u, 0x00u, 0x40u, 0x09u, 0x4Bu, 0x1Bu, 0x78u,
+ 0x09u, 0x4Bu, 0x1Au, 0x7Eu, 0x02u, 0xF0u, 0x03u, 0x02u,
+ 0x01u, 0x2Au, 0x03u, 0xD0u, 0xDAu, 0x7Eu, 0x82u, 0xF0u,
+ 0x80u, 0x02u, 0xDAu, 0x76u, 0x01u, 0x22u, 0x5Au, 0x76u,
+ 0x04u, 0x4Bu, 0x1Au, 0x78u, 0x02u, 0xF0u, 0xFDu, 0x02u,
+ 0x1Au, 0x70u, 0x70u, 0x47u, 0x1Eu, 0x60u, 0x00u, 0x40u,
+ 0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x0Bu, 0x60u, 0x00u, 0x40u,
+ 0x70u, 0x47u, 0xFFu, 0xF7u, 0xEBu, 0xBCu, 0x00u, 0x00u,
+ 0x08u, 0xB5u, 0x0Cu, 0x4Bu, 0x18u, 0x78u, 0x01u, 0x38u,
+ 0xC0u, 0xB2u, 0x00u, 0xF0u, 0x4Bu, 0xF9u, 0x0Au, 0x4Bu,
+ 0x0Au, 0x49u, 0x1Bu, 0x78u, 0xDBu, 0xB2u, 0x00u, 0xEBu,
+ 0xC3u, 0x00u, 0x42u, 0x69u, 0xCBu, 0x5Cu, 0x02u, 0xEBu,
+ 0xC3u, 0x03u, 0x5Bu, 0x68u, 0x5Au, 0x6Au, 0x06u, 0x4Bu,
+ 0x11u, 0x78u, 0xC9u, 0xB2u, 0x19u, 0x80u, 0x5Au, 0x60u,
+ 0x08u, 0xBDu, 0x00u, 0xBFu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x04u, 0x60u, 0x00u, 0x40u, 0x56u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0xB5u, 0x0Du, 0x4Bu,
+ 0x18u, 0x78u, 0x01u, 0x38u, 0xC0u, 0xB2u, 0x00u, 0xF0u,
+ 0x29u, 0xF9u, 0x0Bu, 0x4Bu, 0x0Bu, 0x49u, 0x1Bu, 0x78u,
+ 0xDBu, 0xB2u, 0x00u, 0xEBu, 0xC3u, 0x00u, 0x42u, 0x69u,
+ 0xCBu, 0x5Cu, 0x02u, 0xEBu, 0xC3u, 0x03u, 0x5Bu, 0x68u,
+ 0xDBu, 0x69u, 0x59u, 0x78u, 0x13u, 0xF8u, 0x02u, 0x2Bu,
+ 0x42u, 0xEAu, 0x01u, 0x21u, 0x04u, 0x4Au, 0x11u, 0x80u,
+ 0x53u, 0x60u, 0x08u, 0xBDu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x04u, 0x60u, 0x00u, 0x40u, 0x56u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x58u, 0xC1u, 0xFFu, 0x1Fu, 0x10u, 0xB5u, 0x19u, 0x4Cu,
+ 0x00u, 0x23u, 0x23u, 0x80u, 0x18u, 0x4Bu, 0x18u, 0x78u,
+ 0x01u, 0x38u, 0xC0u, 0xB2u, 0x00u, 0xF0u, 0x02u, 0xF9u,
+ 0x16u, 0x4Bu, 0x17u, 0x4Au, 0x1Bu, 0x78u, 0x12u, 0x78u,
+ 0xDBu, 0xB2u, 0xD2u, 0xB2u, 0x00u, 0xEBu, 0xC2u, 0x00u,
+ 0x41u, 0x69u, 0xEAu, 0xB9u, 0x13u, 0x4Au, 0x12u, 0x78u,
+ 0x01u, 0xEBu, 0xC2u, 0x02u, 0x51u, 0x68u, 0x5Au, 0x1Eu,
+ 0x02u, 0x2Au, 0x15u, 0xD8u, 0x10u, 0x4Au, 0x03u, 0xF1u,
+ 0x00u, 0x53u, 0x01u, 0x3Bu, 0x12u, 0x78u, 0x01u, 0xEBu,
+ 0xC3u, 0x00u, 0x11u, 0xF8u, 0x33u, 0x30u, 0xD2u, 0xB2u,
+ 0x93u, 0x42u, 0x09u, 0xD3u, 0x0Cu, 0x23u, 0x5Au, 0x43u,
+ 0x41u, 0x68u, 0x8Bu, 0x18u, 0x58u, 0x68u, 0x8Au, 0x5Au,
+ 0x9Bu, 0x68u, 0x60u, 0x60u, 0x22u, 0x80u, 0xA3u, 0x60u,
+ 0x10u, 0xBDu, 0x00u, 0xBFu, 0x58u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x03u, 0x60u, 0x00u, 0x40u,
+ 0x04u, 0x60u, 0x00u, 0x40u, 0x56u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x02u, 0x60u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x3Cu, 0x4Bu,
+ 0x3Cu, 0x4Au, 0x1Bu, 0x78u, 0x11u, 0x78u, 0xDBu, 0xB2u,
+ 0x09u, 0x06u, 0x34u, 0xD5u, 0x01u, 0x32u, 0x12u, 0x78u,
+ 0x01u, 0x3Au, 0x05u, 0x2Au, 0x6Au, 0xD8u, 0xDFu, 0xE8u,
+ 0x02u, 0xF0u, 0x10u, 0x18u, 0x27u, 0x69u, 0x69u, 0x03u,
+ 0x35u, 0x4Bu, 0x1Au, 0x78u, 0x21u, 0x2Au, 0x02u, 0xD1u,
+ 0xFFu, 0xF7u, 0x62u, 0xFFu, 0x07u, 0xE0u, 0x1Bu, 0x78u,
+ 0x22u, 0x2Bu, 0x5Bu, 0xD1u, 0xFFu, 0xF7u, 0x7Eu, 0xFFu,
+ 0x01u, 0xE0u, 0xFFu, 0xF7u, 0x9Fu, 0xFFu, 0x2Fu, 0x4Bu,
+ 0x1Bu, 0x88u, 0x9Bu, 0xB2u, 0x00u, 0x2Bu, 0x51u, 0xD0u,
+ 0x0Au, 0xE0u, 0x00u, 0x2Bu, 0x4Eu, 0xD1u, 0x2Cu, 0x4Bu,
+ 0x1Bu, 0x78u, 0x00u, 0x2Bu, 0x4Au, 0xD1u, 0x29u, 0x4Bu,
+ 0x01u, 0x22u, 0x1Au, 0x80u, 0x29u, 0x4Au, 0x5Au, 0x60u,
+ 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0xC0u, 0xBEu,
+ 0x00u, 0x2Bu, 0x3Fu, 0xD1u, 0x23u, 0x4Bu, 0x01u, 0x22u,
+ 0x1Au, 0x80u, 0x25u, 0x4Au, 0xF3u, 0xE7u, 0x12u, 0x78u,
+ 0x12u, 0x06u, 0x37u, 0xD4u, 0x23u, 0x4Au, 0x12u, 0x78u,
+ 0xD2u, 0xB2u, 0x0Au, 0x2Au, 0x0Du, 0xD0u, 0x0Bu, 0x2Au,
+ 0x27u, 0xD0u, 0x09u, 0x2Au, 0x2Eu, 0xD1u, 0xFFu, 0xF7u,
+ 0x75u, 0xFFu, 0x1Au, 0x4Bu, 0x1Bu, 0x88u, 0x9Bu, 0xB2u,
+ 0x43u, 0xB3u, 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u,
+ 0xCBu, 0xBEu, 0x1Bu, 0xBBu, 0x16u, 0x4Bu, 0x1Bu, 0x78u,
+ 0x03u, 0xF0u, 0xFFu, 0x01u, 0xF3u, 0xB9u, 0x12u, 0x4Bu,
+ 0x14u, 0x4Au, 0x1Bu, 0x78u, 0xDBu, 0xB2u, 0x13u, 0x70u,
+ 0x15u, 0x4Bu, 0x14u, 0x78u, 0x18u, 0x78u, 0x84u, 0x42u,
+ 0x01u, 0xD2u, 0x19u, 0x70u, 0x05u, 0xE0u, 0x19u, 0x78u,
+ 0x01u, 0x29u, 0x02u, 0xD9u, 0x12u, 0x78u, 0xD2u, 0xB2u,
+ 0x1Au, 0x70u, 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u,
+ 0x67u, 0xBDu, 0x3Bu, 0xB9u, 0x08u, 0x4Bu, 0x1Au, 0x78u,
+ 0x01u, 0x2Au, 0x03u, 0xD8u, 0x1Au, 0x78u, 0x08u, 0x4Bu,
+ 0xD2u, 0xB2u, 0xF1u, 0xE7u, 0x00u, 0x20u, 0x10u, 0xBDu,
0x04u, 0x60u, 0x00u, 0x40u, 0x00u, 0x60u, 0x00u, 0x40u,
- 0x03u, 0x60u, 0x00u, 0x40u, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
- 0x02u, 0x60u, 0x00u, 0x40u, 0xEAu, 0xC1u, 0xFFu, 0x1Fu,
- 0xECu, 0xC1u, 0xFFu, 0x1Fu, 0x01u, 0x60u, 0x00u, 0x40u,
- 0xEBu, 0xC1u, 0xFFu, 0x1Fu, 0x30u, 0xB5u, 0x01u, 0x22u,
- 0x02u, 0xF1u, 0x0Fu, 0x03u, 0x18u, 0x01u, 0x09u, 0x2Au,
- 0xC3u, 0xB2u, 0x3Bu, 0xD0u, 0x1Fu, 0x49u, 0x03u, 0xF1u,
- 0x80u, 0x44u, 0x0Cu, 0x20u, 0x04u, 0xF5u, 0xC1u, 0x45u,
- 0x00u, 0xFBu, 0x02u, 0x14u, 0x28u, 0x70u, 0x1Cu, 0x49u,
- 0x65u, 0x79u, 0x59u, 0x18u, 0x25u, 0xB1u, 0x24u, 0x79u,
- 0x24u, 0x06u, 0x58u, 0xBFu, 0x08u, 0x20u, 0x00u, 0xE0u,
- 0x80u, 0x20u, 0x08u, 0x70u, 0x17u, 0x49u, 0x0Cu, 0x24u,
- 0x58u, 0x18u, 0x14u, 0x49u, 0x04u, 0xFBu, 0x02u, 0x11u,
- 0x0Cu, 0x89u, 0x01u, 0x32u, 0xC4u, 0xF3u, 0x07u, 0x24u,
- 0x04u, 0x70u, 0x0Cu, 0x89u, 0x12u, 0x48u, 0xE4u, 0xB2u,
- 0x18u, 0x18u, 0x04u, 0x70u, 0xCCu, 0x88u, 0x11u, 0x48u,
- 0xE4u, 0xB2u, 0x18u, 0x18u, 0x04u, 0x70u, 0xCCu, 0x88u,
- 0x0Fu, 0x48u, 0xC4u, 0xF3u, 0x07u, 0x24u, 0x18u, 0x18u,
- 0x04u, 0x70u, 0xCCu, 0x88u, 0x0Du, 0x48u, 0xE4u, 0xB2u,
- 0x18u, 0x18u, 0x04u, 0x70u, 0x0Cu, 0x48u, 0xD2u, 0xB2u,
- 0x18u, 0x18u, 0xCBu, 0x88u, 0xC3u, 0xF3u, 0x07u, 0x21u,
- 0x01u, 0x70u, 0xBDu, 0xE7u, 0x09u, 0x49u, 0xFFu, 0x22u,
- 0x0Au, 0x70u, 0x30u, 0xBDu, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
- 0x0Eu, 0x60u, 0x00u, 0x40u, 0x0Cu, 0x60u, 0x00u, 0x40u,
- 0x0Du, 0x60u, 0x00u, 0x40u, 0x86u, 0x60u, 0x00u, 0x40u,
- 0x87u, 0x60u, 0x00u, 0x40u, 0x84u, 0x60u, 0x00u, 0x40u,
- 0x85u, 0x60u, 0x00u, 0x40u, 0x0Au, 0x60u, 0x00u, 0x40u,
- 0x04u, 0x4Bu, 0x05u, 0x49u, 0x1Au, 0x78u, 0x01u, 0xEBu,
- 0xC2u, 0x03u, 0x5Au, 0x68u, 0x02u, 0xEBu, 0xC0u, 0x00u,
- 0xC0u, 0x68u, 0x70u, 0x47u, 0x6Cu, 0xC1u, 0xFFu, 0x1Fu,
- 0xF8u, 0x20u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x3Du, 0x4Bu,
- 0x1Au, 0x78u, 0x00u, 0x2Au, 0x74u, 0xD0u, 0x18u, 0x78u,
- 0x41u, 0x1Eu, 0xC8u, 0xB2u, 0xFFu, 0xF7u, 0xE8u, 0xFFu,
- 0xC3u, 0x68u, 0x05u, 0x7Au, 0x08u, 0x33u, 0x00u, 0x20u,
- 0xA8u, 0x42u, 0x69u, 0xD0u, 0x13u, 0xF8u, 0x08u, 0x2Cu,
- 0x35u, 0x49u, 0x36u, 0x4Cu, 0x8Eu, 0x5Cu, 0xA4u, 0x5Cu,
- 0xA6u, 0x42u, 0x5Du, 0xD0u, 0x89u, 0x5Cu, 0x13u, 0xF8u,
- 0x07u, 0x4Cu, 0x8Cu, 0x42u, 0x58u, 0xD1u, 0x32u, 0x49u,
- 0x09u, 0x78u, 0x8Au, 0x42u, 0x54u, 0xD1u, 0x13u, 0xF8u,
- 0x06u, 0x7Cu, 0x07u, 0xF0u, 0x7Fu, 0x02u, 0x56u, 0x1Eu,
- 0x34u, 0x01u, 0xE1u, 0xB2u, 0x13u, 0xF8u, 0x05u, 0x6Cu,
- 0x2Cu, 0x4Cu, 0x17u, 0xF0u, 0x80u, 0x0Fu, 0x4Fu, 0xF0u,
- 0x0Cu, 0x07u, 0x06u, 0xF0u, 0x03u, 0x06u, 0x07u, 0xFBu,
- 0x02u, 0x44u, 0x06u, 0xD0u, 0x01u, 0x27u, 0x67u, 0x70u,
- 0xBEu, 0x42u, 0x14u, 0xBFu, 0x0Du, 0x26u, 0x07u, 0x26u,
- 0x05u, 0xE0u, 0x00u, 0x27u, 0x67u, 0x70u, 0x01u, 0x2Eu,
- 0x14u, 0xBFu, 0x09u, 0x26u, 0x05u, 0x26u, 0x66u, 0x71u,
- 0x21u, 0x4Cu, 0x01u, 0x26u, 0x0Fu, 0x19u, 0x0Cu, 0x24u,
- 0x54u, 0x43u, 0x3Eu, 0x70u, 0x1Du, 0x4Eu, 0x33u, 0xF8u,
- 0x04u, 0x7Cu, 0x32u, 0x19u, 0x17u, 0x81u, 0x13u, 0xF8u,
- 0x06u, 0x7Cu, 0x17u, 0x71u, 0x13u, 0xF8u, 0x05u, 0x7Cu,
- 0x37u, 0x55u, 0x00u, 0x26u, 0xD6u, 0x70u, 0x16u, 0x89u,
- 0x18u, 0x4Cu, 0xC6u, 0xF3u, 0x07u, 0x26u, 0x0Cu, 0x19u,
- 0x26u, 0x70u, 0x16u, 0x89u, 0x16u, 0x4Cu, 0xF6u, 0xB2u,
- 0x0Cu, 0x19u, 0x26u, 0x70u, 0xD6u, 0x88u, 0x15u, 0x4Cu,
- 0xF6u, 0xB2u, 0x0Cu, 0x19u, 0x26u, 0x70u, 0xD6u, 0x88u,
- 0x13u, 0x4Cu, 0xC6u, 0xF3u, 0x07u, 0x26u, 0x0Cu, 0x19u,
- 0x26u, 0x70u, 0xD6u, 0x88u, 0x11u, 0x4Cu, 0xF6u, 0xB2u,
- 0x0Cu, 0x19u, 0x26u, 0x70u, 0x10u, 0x4Cu, 0x0Cu, 0x19u,
- 0xD1u, 0x88u, 0xC1u, 0xF3u, 0x07u, 0x22u, 0x22u, 0x70u,
- 0x01u, 0x30u, 0xC0u, 0xB2u, 0x08u, 0x33u, 0x93u, 0xE7u,
- 0xF8u, 0xBDu, 0x00u, 0xBFu, 0x71u, 0xC1u, 0xFFu, 0x1Fu,
- 0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0xE4u, 0xC1u, 0xFFu, 0x1Fu,
- 0x04u, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x03u, 0x60u, 0x00u, 0x40u, 0x58u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x02u, 0x60u, 0x00u, 0x40u, 0xE2u, 0xC1u, 0xFFu, 0x1Fu,
+ 0xE4u, 0xC1u, 0xFFu, 0x1Fu, 0x01u, 0x60u, 0x00u, 0x40u,
+ 0xE3u, 0xC1u, 0xFFu, 0x1Fu, 0x30u, 0xB5u, 0x1Cu, 0x4Bu,
+ 0x01u, 0x21u, 0x1Cu, 0x4Au, 0x0Cu, 0x20u, 0x00u, 0xFBu,
+ 0x01u, 0x24u, 0x83u, 0xF8u, 0x72u, 0x00u, 0x65u, 0x79u,
+ 0x25u, 0xB1u, 0x24u, 0x79u, 0x24u, 0x06u, 0x58u, 0xBFu,
+ 0x08u, 0x20u, 0x00u, 0xE0u, 0x80u, 0x20u, 0x18u, 0x70u,
+ 0x0Cu, 0x20u, 0x00u, 0xFBu, 0x01u, 0x22u, 0x10u, 0x89u,
+ 0x01u, 0x31u, 0xC0u, 0xF3u, 0x07u, 0x20u, 0x03u, 0xF8u,
+ 0x02u, 0x0Cu, 0x10u, 0x89u, 0x09u, 0x29u, 0xC0u, 0xB2u,
+ 0x03u, 0xF8u, 0x01u, 0x0Cu, 0xD0u, 0x88u, 0x03u, 0xF1u,
+ 0x10u, 0x03u, 0xC0u, 0xB2u, 0x83u, 0xF8u, 0x68u, 0x00u,
+ 0xD0u, 0x88u, 0xC0u, 0xF3u, 0x07u, 0x20u, 0x83u, 0xF8u,
+ 0x69u, 0x00u, 0xD0u, 0x88u, 0xC0u, 0xB2u, 0x83u, 0xF8u,
+ 0x66u, 0x00u, 0xD2u, 0x88u, 0xC2u, 0xF3u, 0x07u, 0x22u,
+ 0x83u, 0xF8u, 0x67u, 0x20u, 0xCDu, 0xD1u, 0x04u, 0x4Bu,
+ 0xFFu, 0x22u, 0x1Au, 0x70u, 0x30u, 0xBDu, 0x00u, 0xBFu,
+ 0x0Eu, 0x60u, 0x00u, 0x40u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x0Au, 0x60u, 0x00u, 0x40u, 0x07u, 0x4Bu, 0x1Au, 0x78u,
+ 0x07u, 0x4Bu, 0x03u, 0xEBu, 0xC2u, 0x03u, 0x5Bu, 0x68u,
+ 0x03u, 0xF1u, 0x08u, 0x02u, 0x1Bu, 0x7Au, 0x83u, 0x42u,
+ 0x86u, 0xBFu, 0x02u, 0xEBu, 0xC0u, 0x00u, 0x40u, 0x68u,
+ 0x00u, 0x20u, 0x70u, 0x47u, 0x64u, 0xC1u, 0xFFu, 0x1Fu,
+ 0xB8u, 0x21u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x39u, 0x4Bu,
+ 0x1Au, 0x78u, 0x00u, 0x2Au, 0x6Cu, 0xD0u, 0x18u, 0x78u,
+ 0x01u, 0x38u, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0xE2u, 0xFFu,
+ 0xC3u, 0x68u, 0x04u, 0x7Au, 0x08u, 0x33u, 0x03u, 0xEBu,
+ 0xC4u, 0x04u, 0xA3u, 0x42u, 0x60u, 0xD0u, 0x13u, 0xF8u,
+ 0x08u, 0x2Cu, 0x31u, 0x49u, 0x31u, 0x48u, 0x8Du, 0x5Cu,
+ 0x80u, 0x5Cu, 0x85u, 0x42u, 0x56u, 0xD0u, 0x89u, 0x5Cu,
+ 0x13u, 0xF8u, 0x07u, 0x0Cu, 0x88u, 0x42u, 0x51u, 0xD1u,
+ 0x2Du, 0x49u, 0x09u, 0x78u, 0x8Au, 0x42u, 0x4Du, 0xD1u,
+ 0x13u, 0xF8u, 0x06u, 0x0Cu, 0x13u, 0xF8u, 0x05u, 0x6Cu,
+ 0x00u, 0xF0u, 0x7Fu, 0x02u, 0x51u, 0x1Eu, 0x10u, 0xF0u,
+ 0x80u, 0x0Fu, 0x28u, 0x48u, 0x4Fu, 0xEAu, 0x01u, 0x11u,
+ 0x4Fu, 0xF0u, 0x0Cu, 0x05u, 0xC9u, 0xB2u, 0x06u, 0xF0u,
+ 0x03u, 0x06u, 0x05u, 0xFBu, 0x02u, 0x05u, 0x06u, 0xD0u,
+ 0x01u, 0x27u, 0xBEu, 0x42u, 0x6Fu, 0x70u, 0x14u, 0xBFu,
+ 0x0Du, 0x26u, 0x07u, 0x26u, 0x05u, 0xE0u, 0x00u, 0x27u,
+ 0x01u, 0x2Eu, 0x6Fu, 0x70u, 0x14u, 0xBFu, 0x09u, 0x26u,
+ 0x05u, 0x26u, 0x6Eu, 0x71u, 0x1Cu, 0x4Du, 0x01u, 0x26u,
+ 0x6Eu, 0x54u, 0x0Cu, 0x25u, 0x55u, 0x43u, 0x33u, 0xF8u,
+ 0x04u, 0x6Cu, 0x42u, 0x19u, 0x16u, 0x81u, 0x13u, 0xF8u,
+ 0x06u, 0x6Cu, 0x16u, 0x71u, 0x13u, 0xF8u, 0x05u, 0x6Cu,
+ 0x46u, 0x55u, 0x00u, 0x20u, 0xD0u, 0x70u, 0x15u, 0x89u,
+ 0x14u, 0x48u, 0xC5u, 0xF3u, 0x07u, 0x25u, 0x45u, 0x54u,
+ 0x15u, 0x89u, 0x01u, 0x30u, 0xEDu, 0xB2u, 0x45u, 0x54u,
+ 0xD5u, 0x88u, 0x79u, 0x30u, 0xEDu, 0xB2u, 0x45u, 0x54u,
+ 0xD5u, 0x88u, 0x01u, 0x30u, 0xC5u, 0xF3u, 0x07u, 0x25u,
+ 0x45u, 0x54u, 0xD5u, 0x88u, 0x03u, 0x38u, 0xEDu, 0xB2u,
+ 0x45u, 0x54u, 0xD2u, 0x88u, 0x01u, 0x30u, 0xC2u, 0xF3u,
+ 0x07u, 0x22u, 0x42u, 0x54u, 0x08u, 0x33u, 0x9Cu, 0xE7u,
+ 0xF8u, 0xBDu, 0x00u, 0xBFu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x56u, 0xC1u, 0xFFu, 0x1Fu, 0xDCu, 0xC1u, 0xFFu, 0x1Fu,
+ 0x04u, 0x60u, 0x00u, 0x40u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
0x0Eu, 0x60u, 0x00u, 0x40u, 0x0Cu, 0x60u, 0x00u, 0x40u,
- 0x0Du, 0x60u, 0x00u, 0x40u, 0x86u, 0x60u, 0x00u, 0x40u,
- 0x87u, 0x60u, 0x00u, 0x40u, 0x84u, 0x60u, 0x00u, 0x40u,
- 0x85u, 0x60u, 0x00u, 0x40u, 0x08u, 0xB5u, 0x06u, 0x4Bu,
- 0x18u, 0x78u, 0x41u, 0x1Eu, 0xC8u, 0xB2u, 0xFFu, 0xF7u,
- 0x57u, 0xFFu, 0x42u, 0x68u, 0x13u, 0x79u, 0x00u, 0xEBu,
- 0xC3u, 0x00u, 0x40u, 0x69u, 0x08u, 0xBDu, 0x00u, 0xBFu,
- 0x71u, 0xC1u, 0xFFu, 0x1Fu, 0xF8u, 0xB5u, 0x00u, 0x21u,
- 0x0Cu, 0x24u, 0x4Cu, 0x43u, 0x51u, 0x4Du, 0x01u, 0x31u,
- 0x00u, 0x23u, 0x2Au, 0x19u, 0x09u, 0x29u, 0x2Bu, 0x55u,
- 0x93u, 0x70u, 0x02u, 0xF1u, 0x08u, 0x04u, 0x53u, 0x70u,
+ 0x08u, 0xB5u, 0x06u, 0x4Bu, 0x18u, 0x78u, 0x01u, 0x38u,
+ 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x63u, 0xFFu, 0x20u, 0xB1u,
+ 0x43u, 0x68u, 0x1Bu, 0x79u, 0x00u, 0xEBu, 0xC3u, 0x00u,
+ 0x40u, 0x69u, 0x08u, 0xBDu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,
+ 0xF8u, 0xB5u, 0x00u, 0x21u, 0x0Cu, 0x25u, 0x4Du, 0x43u,
+ 0x4Cu, 0x4Cu, 0x01u, 0x31u, 0x00u, 0x23u, 0x62u, 0x19u,
+ 0x09u, 0x29u, 0x63u, 0x55u, 0x93u, 0x70u, 0x53u, 0x70u,
0xD3u, 0x70u, 0x53u, 0x71u, 0x13u, 0x81u, 0x93u, 0x72u,
- 0xEEu, 0xD1u, 0x18u, 0xB1u, 0x4Au, 0x48u, 0x4Bu, 0x4Au,
- 0x03u, 0x70u, 0x13u, 0x70u, 0x4Au, 0x4Bu, 0x19u, 0x78u,
- 0x00u, 0x29u, 0x00u, 0xF0u, 0x8Au, 0x80u, 0x1Cu, 0x78u,
- 0x60u, 0x1Eu, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x2Cu, 0xFFu,
- 0x42u, 0x68u, 0xD3u, 0x79u, 0x03u, 0xF0u, 0x40u, 0x01u,
- 0xCCu, 0xB2u, 0x44u, 0x4Bu, 0x1Cu, 0xB1u, 0x1Cu, 0x78u,
- 0x44u, 0xF0u, 0x01u, 0x01u, 0x02u, 0xE0u, 0x1Au, 0x78u,
- 0x02u, 0xF0u, 0xFEu, 0x01u, 0x04u, 0x7Au, 0x19u, 0x70u,
- 0x01u, 0x22u, 0xC3u, 0x68u, 0x00u, 0x21u, 0x08u, 0x33u,
- 0xA1u, 0x42u, 0x43u, 0xD0u, 0x13u, 0xF8u, 0x06u, 0x5Cu,
- 0x05u, 0xF0u, 0x7Fu, 0x06u, 0xB2u, 0x42u, 0x39u, 0xD1u,
- 0x34u, 0x4Eu, 0x0Cu, 0x27u, 0x07u, 0xFBu, 0x02u, 0x66u,
- 0xB6u, 0xF8u, 0x08u, 0xE0u, 0x33u, 0xF8u, 0x04u, 0x7Cu,
- 0x1Fu, 0xFAu, 0x8Eu, 0xFCu, 0xBCu, 0x45u, 0x38u, 0xBFu,
- 0x37u, 0x81u, 0x13u, 0xF8u, 0x08u, 0x6Cu, 0x2Eu, 0x4Fu,
- 0xBEu, 0x5Du, 0x13u, 0xF8u, 0x07u, 0x7Cu, 0xB7u, 0x42u,
- 0x24u, 0xD1u, 0x13u, 0xF8u, 0x05u, 0x6Cu, 0x15u, 0xF0u,
- 0x80u, 0x0Fu, 0x28u, 0x4Du, 0x4Fu, 0xF0u, 0x0Cu, 0x07u,
- 0x06u, 0xF0u, 0x03u, 0x06u, 0x07u, 0xFBu, 0x02u, 0x55u,
- 0x06u, 0xD0u, 0x01u, 0x27u, 0x6Fu, 0x70u, 0xBEu, 0x42u,
- 0x14u, 0xBFu, 0x0Du, 0x26u, 0x07u, 0x26u, 0x05u, 0xE0u,
- 0x00u, 0x27u, 0x6Fu, 0x70u, 0x01u, 0x2Eu, 0x14u, 0xBFu,
- 0x09u, 0x26u, 0x05u, 0x26u, 0x6Eu, 0x71u, 0x0Cu, 0x25u,
- 0x55u, 0x43u, 0x1Cu, 0x4Eu, 0x13u, 0xF8u, 0x06u, 0xECu,
- 0x77u, 0x19u, 0x87u, 0xF8u, 0x04u, 0xE0u, 0x13u, 0xF8u,
- 0x05u, 0x7Cu, 0x77u, 0x55u, 0x01u, 0x31u, 0xC9u, 0xB2u,
- 0x08u, 0x33u, 0xB9u, 0xE7u, 0x01u, 0x32u, 0x09u, 0x2Au,
- 0xB3u, 0xD1u, 0xC3u, 0x68u, 0x00u, 0x22u, 0x08u, 0x33u,
- 0xA2u, 0x42u, 0x0Du, 0xD0u, 0x13u, 0xF8u, 0x06u, 0x5Cu,
- 0x0Cu, 0x26u, 0x05u, 0xF0u, 0x7Fu, 0x01u, 0x0Fu, 0x4Du,
- 0x13u, 0xF8u, 0x08u, 0x0Cu, 0x06u, 0xFBu, 0x01u, 0x51u,
- 0x01u, 0x32u, 0x88u, 0x72u, 0xD2u, 0xB2u, 0xEEu, 0xE7u,
- 0xFFu, 0xF7u, 0x5Cu, 0xFFu, 0x0Eu, 0x4Bu, 0x00u, 0x22u,
- 0x18u, 0x60u, 0x01u, 0x23u, 0x07u, 0x49u, 0x0Cu, 0x20u,
- 0x00u, 0xFBu, 0x03u, 0x10u, 0xC2u, 0x80u, 0x01u, 0x89u,
- 0x01u, 0x33u, 0x52u, 0x18u, 0x09u, 0x2Bu, 0x92u, 0xB2u,
- 0xF4u, 0xD1u, 0xBDu, 0xE8u, 0xF8u, 0x40u, 0xFFu, 0xF7u,
- 0x4Du, 0xBEu, 0xF8u, 0xBDu, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
- 0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0xE4u, 0xC1u, 0xFFu, 0x1Fu,
- 0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x6Fu, 0xC1u, 0xFFu, 0x1Fu,
- 0x74u, 0xC1u, 0xFFu, 0x1Fu, 0x12u, 0x4Bu, 0x19u, 0x78u,
- 0x01u, 0xF0u, 0x7Fu, 0x01u, 0x4Au, 0x1Eu, 0xD0u, 0xB2u,
- 0x07u, 0x28u, 0x1Au, 0xD8u, 0x03u, 0x01u, 0xDAu, 0xB2u,
- 0x0Eu, 0x4Bu, 0x0Cu, 0x20u, 0x00u, 0xFBu, 0x01u, 0x30u,
- 0x81u, 0x78u, 0x41u, 0xF0u, 0x01u, 0x03u, 0x00u, 0x21u,
- 0x83u, 0x70u, 0xC1u, 0x70u, 0x43u, 0x78u, 0x43u, 0xF0u,
- 0x02u, 0x01u, 0x41u, 0x70u, 0x00u, 0x79u, 0x08u, 0x4Bu,
- 0x10u, 0xF0u, 0x80u, 0x0Fu, 0x01u, 0xD0u, 0x8Du, 0x21u,
- 0x00u, 0xE0u, 0x89u, 0x21u, 0xD1u, 0x54u, 0xFFu, 0xF7u,
- 0x6Du, 0xBBu, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0xBFu,
- 0x04u, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
- 0x0Eu, 0x60u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x1Au, 0x4Bu,
- 0x18u, 0x78u, 0x00u, 0xF0u, 0x7Fu, 0x03u, 0x5Au, 0x1Eu,
- 0xD2u, 0xB2u, 0x07u, 0x2Au, 0x2Au, 0xD8u, 0x17u, 0x49u,
- 0x0Cu, 0x20u, 0x00u, 0xFBu, 0x03u, 0x13u, 0x9Cu, 0x78u,
- 0x12u, 0x01u, 0x04u, 0xF0u, 0xFEu, 0x01u, 0x99u, 0x70u,
- 0x00u, 0x24u, 0x13u, 0x49u, 0xDCu, 0x70u, 0xD2u, 0xB2u,
- 0x54u, 0x5Cu, 0x04u, 0xF0u, 0x7Fu, 0x04u, 0x54u, 0x54u,
- 0x59u, 0x78u, 0x01u, 0xF0u, 0xFDu, 0x01u, 0x59u, 0x70u,
- 0x19u, 0x79u, 0x5Bu, 0x78u, 0x11u, 0xF0u, 0x80u, 0x0Fu,
- 0x0Cu, 0x49u, 0x05u, 0xD0u, 0x01u, 0x2Bu, 0x01u, 0xD1u,
- 0x50u, 0x54u, 0x07u, 0xE0u, 0x0Du, 0x20u, 0x04u, 0xE0u,
- 0x01u, 0x2Bu, 0x01u, 0xD1u, 0x08u, 0x20u, 0x00u, 0xE0u,
- 0x09u, 0x20u, 0x50u, 0x54u, 0xBDu, 0xE8u, 0x10u, 0x40u,
- 0xFFu, 0xF7u, 0x30u, 0xBBu, 0x00u, 0x20u, 0x10u, 0xBDu,
- 0x04u, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
- 0x0Cu, 0x60u, 0x00u, 0x40u, 0x0Eu, 0x60u, 0x00u, 0x40u,
- 0x10u, 0xB5u, 0x0Cu, 0x4Bu, 0x0Cu, 0x48u, 0x1Cu, 0x78u,
- 0x01u, 0x78u, 0x4Au, 0x1Eu, 0xD0u, 0xB2u, 0xFFu, 0xF7u,
- 0x27u, 0xFEu, 0x43u, 0x68u, 0x18u, 0x79u, 0xA0u, 0x42u,
- 0x09u, 0xD9u, 0x44u, 0xB9u, 0x07u, 0x4Bu, 0x08u, 0x4Au,
- 0x19u, 0x78u, 0x08u, 0x48u, 0x11u, 0x70u, 0x01u, 0x78u,
- 0x01u, 0x20u, 0x19u, 0x70u, 0x10u, 0xBDu, 0x00u, 0x20u,
+ 0xF0u, 0xD1u, 0x18u, 0xB1u, 0x46u, 0x4Au, 0x13u, 0x70u,
+ 0x46u, 0x4Au, 0x13u, 0x70u, 0x46u, 0x4Bu, 0x1Au, 0x78u,
+ 0x00u, 0x2Au, 0x00u, 0xF0u, 0x81u, 0x80u, 0x18u, 0x78u,
+ 0x01u, 0x38u, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x3Au, 0xFFu,
+ 0x43u, 0x68u, 0x01u, 0x7Au, 0xDBu, 0x79u, 0xC9u, 0x00u,
+ 0x13u, 0xF0u, 0x40u, 0x0Fu, 0x3Fu, 0x4Bu, 0x1Au, 0x78u,
+ 0x14u, 0xBFu, 0x42u, 0xF0u, 0x01u, 0x02u, 0x02u, 0xF0u,
+ 0xFEu, 0x02u, 0x1Au, 0x70u, 0x01u, 0x22u, 0xC3u, 0x68u,
+ 0x08u, 0x33u, 0x03u, 0xEBu, 0x01u, 0x0Eu, 0x73u, 0x45u,
+ 0x3Du, 0xD0u, 0x13u, 0xF8u, 0x06u, 0x5Cu, 0x05u, 0xF0u,
+ 0x7Fu, 0x06u, 0xB2u, 0x42u, 0x35u, 0xD1u, 0x0Cu, 0x26u,
+ 0x06u, 0xFBu, 0x02u, 0x46u, 0xB6u, 0xF8u, 0x08u, 0xC0u,
+ 0x33u, 0xF8u, 0x04u, 0x7Cu, 0x1Fu, 0xFAu, 0x8Cu, 0xFCu,
+ 0xBCu, 0x45u, 0x38u, 0xBFu, 0x37u, 0x81u, 0x13u, 0xF8u,
+ 0x08u, 0x6Cu, 0x2Bu, 0x4Fu, 0xBEu, 0x5Du, 0x13u, 0xF8u,
+ 0x07u, 0x7Cu, 0xB7u, 0x42u, 0x21u, 0xD1u, 0x13u, 0xF8u,
+ 0x05u, 0x6Cu, 0x15u, 0xF0u, 0x80u, 0x0Fu, 0x4Fu, 0xF0u,
+ 0x0Cu, 0x05u, 0x06u, 0xF0u, 0x03u, 0x06u, 0x05u, 0xFBu,
+ 0x02u, 0x45u, 0x06u, 0xD0u, 0x01u, 0x27u, 0xBEu, 0x42u,
+ 0x6Fu, 0x70u, 0x14u, 0xBFu, 0x0Du, 0x26u, 0x07u, 0x26u,
+ 0x05u, 0xE0u, 0x00u, 0x27u, 0x01u, 0x2Eu, 0x6Fu, 0x70u,
+ 0x14u, 0xBFu, 0x09u, 0x26u, 0x05u, 0x26u, 0x6Eu, 0x71u,
+ 0x0Cu, 0x25u, 0x55u, 0x43u, 0x13u, 0xF8u, 0x06u, 0x7Cu,
+ 0x66u, 0x19u, 0x37u, 0x71u, 0x13u, 0xF8u, 0x05u, 0x6Cu,
+ 0x66u, 0x55u, 0x08u, 0x33u, 0xBFu, 0xE7u, 0x01u, 0x32u,
+ 0x09u, 0x2Au, 0xB8u, 0xD1u, 0xC3u, 0x68u, 0x03u, 0xF1u,
+ 0x08u, 0x02u, 0x11u, 0x44u, 0x08u, 0x33u, 0x8Bu, 0x42u,
+ 0x0Au, 0xD0u, 0x13u, 0xF8u, 0x06u, 0x2Cu, 0x0Cu, 0x25u,
+ 0x02u, 0xF0u, 0x7Fu, 0x02u, 0x05u, 0xFBu, 0x02u, 0x42u,
+ 0x13u, 0xF8u, 0x08u, 0x0Cu, 0x90u, 0x72u, 0xF1u, 0xE7u,
+ 0xFFu, 0xF7u, 0x66u, 0xFFu, 0x0Eu, 0x4Bu, 0x00u, 0x22u,
+ 0x18u, 0x60u, 0x01u, 0x23u, 0x0Cu, 0x21u, 0x01u, 0xFBu,
+ 0x03u, 0x41u, 0xCAu, 0x80u, 0x09u, 0x89u, 0x01u, 0x33u,
+ 0x0Au, 0x44u, 0x09u, 0x2Bu, 0x92u, 0xB2u, 0xF5u, 0xD1u,
+ 0xBDu, 0xE8u, 0xF8u, 0x40u, 0xFFu, 0xF7u, 0x7Eu, 0xBEu,
+ 0xF8u, 0xBDu, 0x00u, 0xBFu, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x56u, 0xC1u, 0xFFu, 0x1Fu, 0xDCu, 0xC1u, 0xFFu, 0x1Fu,
+ 0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x67u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x6Cu, 0xC1u, 0xFFu, 0x1Fu, 0x11u, 0x4Bu, 0x19u, 0x78u,
+ 0x01u, 0xF0u, 0x7Fu, 0x01u, 0x4Au, 0x1Eu, 0xD2u, 0xB2u,
+ 0x07u, 0x2Au, 0x19u, 0xD8u, 0x0Eu, 0x4Bu, 0x0Cu, 0x20u,
+ 0x00u, 0xFBu, 0x01u, 0x33u, 0x99u, 0x78u, 0x12u, 0x01u,
+ 0x41u, 0xF0u, 0x01u, 0x01u, 0x99u, 0x70u, 0x00u, 0x21u,
+ 0xD9u, 0x70u, 0x59u, 0x78u, 0xD2u, 0xB2u, 0x41u, 0xF0u,
+ 0x02u, 0x01u, 0x59u, 0x70u, 0x1Bu, 0x79u, 0x13u, 0xF0u,
+ 0x80u, 0x0Fu, 0x06u, 0x4Bu, 0x14u, 0xBFu, 0x8Du, 0x21u,
+ 0x89u, 0x21u, 0xD1u, 0x54u, 0xFFu, 0xF7u, 0x98u, 0xBBu,
+ 0x00u, 0x20u, 0x70u, 0x47u, 0x04u, 0x60u, 0x00u, 0x40u,
+ 0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x0Eu, 0x60u, 0x00u, 0x40u,
+ 0x10u, 0xB5u, 0x1Au, 0x4Bu, 0x1Bu, 0x78u, 0x03u, 0xF0u,
+ 0x7Fu, 0x03u, 0x5Au, 0x1Eu, 0xD2u, 0xB2u, 0x07u, 0x2Au,
+ 0x29u, 0xD8u, 0x17u, 0x49u, 0x0Cu, 0x20u, 0x00u, 0xFBu,
+ 0x03u, 0x13u, 0x99u, 0x78u, 0x12u, 0x01u, 0x01u, 0xF0u,
+ 0xFEu, 0x01u, 0x99u, 0x70u, 0x00u, 0x21u, 0xD9u, 0x70u,
+ 0x12u, 0x49u, 0xD2u, 0xB2u, 0x54u, 0x5Cu, 0x04u, 0xF0u,
+ 0x7Fu, 0x04u, 0x54u, 0x54u, 0x59u, 0x78u, 0x01u, 0xF0u,
+ 0xFDu, 0x01u, 0x59u, 0x70u, 0x19u, 0x79u, 0x5Bu, 0x78u,
+ 0x11u, 0xF0u, 0x80u, 0x0Fu, 0x0Cu, 0x49u, 0x05u, 0xD0u,
+ 0x01u, 0x2Bu, 0x01u, 0xD1u, 0x50u, 0x54u, 0x06u, 0xE0u,
+ 0x0Du, 0x23u, 0x03u, 0xE0u, 0x01u, 0x2Bu, 0x0Cu, 0xBFu,
+ 0x08u, 0x23u, 0x09u, 0x23u, 0x53u, 0x54u, 0xBDu, 0xE8u,
+ 0x10u, 0x40u, 0xFFu, 0xF7u, 0x5Du, 0xBBu, 0x00u, 0x20u,
0x10u, 0xBDu, 0x00u, 0xBFu, 0x04u, 0x60u, 0x00u, 0x40u,
- 0x71u, 0xC1u, 0xFFu, 0x1Fu, 0x5Eu, 0xC1u, 0xFFu, 0x1Fu,
- 0xE4u, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x60u, 0x00u, 0x40u,
- 0x10u, 0xB5u, 0x7Cu, 0x4Bu, 0x00u, 0x22u, 0x1Au, 0x80u,
- 0x7Bu, 0x4Au, 0x7Cu, 0x48u, 0x11u, 0x78u, 0x11u, 0xF0u,
- 0x80u, 0x0Fu, 0x00u, 0xF0u, 0x8Au, 0x80u, 0x01u, 0x78u,
- 0x0Au, 0x29u, 0x00u, 0xF2u, 0x22u, 0x81u, 0xDFu, 0xE8u,
- 0x11u, 0xF0u, 0x58u, 0x00u, 0x20u, 0x01u, 0x20u, 0x01u,
- 0x20u, 0x01u, 0x20u, 0x01u, 0x20u, 0x01u, 0x0Bu, 0x00u,
- 0x20u, 0x01u, 0x78u, 0x00u, 0x20u, 0x01u, 0x7Cu, 0x00u,
- 0x71u, 0x4Bu, 0x19u, 0x78u, 0x01u, 0x29u, 0x0Au, 0xD1u,
- 0x70u, 0x48u, 0x71u, 0x49u, 0x02u, 0x78u, 0x01u, 0xEBu,
- 0xC2u, 0x03u, 0x58u, 0x68u, 0x12u, 0x23u, 0x42u, 0x68u,
- 0x68u, 0x48u, 0x42u, 0x60u, 0x0Fu, 0xE0u, 0x18u, 0x78u,
- 0x02u, 0x28u, 0x11u, 0xD1u, 0x6Bu, 0x4Bu, 0x18u, 0x78u,
- 0xFFu, 0xF7u, 0xDAu, 0xFDu, 0x42u, 0x68u, 0x63u, 0x48u,
- 0x42u, 0x60u, 0x41u, 0x68u, 0xCBu, 0x78u, 0x42u, 0x68u,
- 0x91u, 0x78u, 0x41u, 0xEAu, 0x03u, 0x23u, 0x03u, 0x80u,
- 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x0Cu, 0xBCu,
- 0x1Au, 0x78u, 0x03u, 0x2Au, 0x21u, 0xD1u, 0x62u, 0x4Bu,
- 0x00u, 0x22u, 0x60u, 0x49u, 0x08u, 0x78u, 0x90u, 0x42u,
- 0x0Au, 0xD8u, 0x0Au, 0x78u, 0x82u, 0xB1u, 0x5Du, 0x49u,
- 0x5Eu, 0x48u, 0x09u, 0x78u, 0x5Eu, 0x4Au, 0x00u, 0x7Cu,
- 0x88u, 0x42u, 0x08u, 0xBFu, 0x13u, 0x46u, 0x07u, 0xE0u,
- 0x18u, 0x78u, 0x00u, 0x28u, 0xF1u, 0xD0u, 0x19u, 0x78u,
- 0x50u, 0x1Cu, 0x5Bu, 0x18u, 0xC2u, 0xB2u, 0xE8u, 0xE7u,
- 0x19u, 0x78u, 0x00u, 0x29u, 0x00u, 0xF0u, 0xD1u, 0x80u,
- 0x18u, 0x78u, 0x4Cu, 0x4Au, 0x10u, 0x80u, 0x53u, 0x60u,
- 0xD6u, 0xE7u, 0xBDu, 0xE8u, 0x10u, 0x40u, 0x00u, 0xF0u,
- 0xDDu, 0xB8u, 0x11u, 0x78u, 0x11u, 0xF0u, 0x03u, 0x02u,
- 0x11u, 0xD0u, 0x02u, 0x2Au, 0x40u, 0xF0u, 0xC1u, 0x80u,
- 0x44u, 0x49u, 0x4Eu, 0x4Bu, 0x0Au, 0x80u, 0x18u, 0x78u,
- 0x4Du, 0x4Au, 0x00u, 0xF0u, 0x7Fu, 0x03u, 0x0Cu, 0x20u,
- 0x00u, 0xFBu, 0x03u, 0x23u, 0x98u, 0x78u, 0x4Bu, 0x4Bu,
- 0x00u, 0x22u, 0x18u, 0x70u, 0x06u, 0xE0u, 0x3Du, 0x49u,
- 0x02u, 0x23u, 0x49u, 0x48u, 0x0Bu, 0x80u, 0x00u, 0x78u,
- 0x46u, 0x4Bu, 0x18u, 0x70u, 0x5Au, 0x70u, 0x4Bu, 0x60u,
- 0xB2u, 0xE7u, 0x01u, 0x22u, 0x1Au, 0x80u, 0x45u, 0x48u,
- 0x05u, 0xE0u, 0x01u, 0x22u, 0x3Fu, 0x48u, 0x1Au, 0x80u,
- 0x02u, 0x78u, 0x43u, 0x49u, 0x88u, 0x18u, 0x58u, 0x60u,
- 0xA6u, 0xE7u, 0x03u, 0x78u, 0x58u, 0x1Eu, 0x0Au, 0x28u,
- 0x00u, 0xF2u, 0x97u, 0x80u, 0xDFu, 0xE8u, 0x10u, 0xF0u,
- 0x2Bu, 0x00u, 0x95u, 0x00u, 0x44u, 0x00u, 0x95u, 0x00u,
- 0x0Bu, 0x00u, 0x95u, 0x00u, 0x95u, 0x00u, 0x95u, 0x00u,
- 0x0Fu, 0x00u, 0x95u, 0x00u, 0x19u, 0x00u, 0x2Fu, 0x4Bu,
- 0x38u, 0x49u, 0x18u, 0x78u, 0x4Cu, 0xE0u, 0x2Du, 0x4Bu,
- 0x34u, 0x4Au, 0x18u, 0x78u, 0x36u, 0x49u, 0x10u, 0x70u,
- 0x01u, 0x20u, 0x08u, 0x70u, 0xFFu, 0xF7u, 0x0Au, 0xFEu,
- 0x77u, 0xE0u, 0xFFu, 0xF7u, 0x25u, 0xFFu, 0x00u, 0x28u,
- 0x77u, 0xD0u, 0x2Au, 0x4Cu, 0x31u, 0x4Au, 0x24u, 0x78u,
- 0x2Fu, 0x4Bu, 0x01u, 0x21u, 0x14u, 0x70u, 0x19u, 0x70u,
- 0xFFu, 0xF7u, 0x58u, 0xFDu, 0x2Au, 0x48u, 0x2Eu, 0x49u,
- 0x02u, 0x5Du, 0x0Au, 0x55u, 0x65u, 0xE0u, 0x12u, 0x78u,
- 0x02u, 0xF0u, 0x03u, 0x01u, 0x01u, 0x29u, 0x55u, 0xD0u,
- 0x09u, 0xD3u, 0x02u, 0x29u, 0x61u, 0xD1u, 0x1Bu, 0x4Bu,
- 0x18u, 0x78u, 0x00u, 0x28u, 0x5Du, 0xD1u, 0xBDu, 0xE8u,
- 0x10u, 0x40u, 0xFFu, 0xF7u, 0xC7u, 0xBEu, 0x17u, 0x4Au,
- 0x11u, 0x78u, 0x01u, 0x29u, 0x55u, 0xD1u, 0x1Cu, 0x49u,
- 0x0Bu, 0x78u, 0x03u, 0xF0u, 0xFDu, 0x00u, 0x17u, 0xE0u,
- 0x10u, 0x78u, 0x00u, 0xF0u, 0x03u, 0x02u, 0x01u, 0x2Au,
- 0x3Cu, 0xD0u, 0x09u, 0xD3u, 0x02u, 0x2Au, 0x48u, 0xD1u,
- 0x0Eu, 0x49u, 0x0Bu, 0x78u, 0x00u, 0x2Bu, 0x44u, 0xD1u,
- 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x82u, 0xBEu,
- 0x0Au, 0x48u, 0x02u, 0x78u, 0x01u, 0x2Au, 0x3Cu, 0xD1u,
- 0x0Fu, 0x49u, 0x0Bu, 0x78u, 0x43u, 0xF0u, 0x02u, 0x00u,
- 0x08u, 0x70u, 0x32u, 0xE0u, 0x60u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x0Cu, 0x60u, 0x00u, 0x40u,
+ 0x0Eu, 0x60u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x0Du, 0x4Bu,
+ 0x1Cu, 0x78u, 0x0Du, 0x4Bu, 0xE4u, 0xB2u, 0x18u, 0x78u,
+ 0x01u, 0x38u, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x3Eu, 0xFEu,
+ 0x43u, 0x68u, 0x1Bu, 0x79u, 0xA3u, 0x42u, 0x0Bu, 0xD9u,
+ 0x54u, 0xB9u, 0x08u, 0x4Bu, 0x08u, 0x4Au, 0x19u, 0x78u,
+ 0x01u, 0x20u, 0xC9u, 0xB2u, 0x11u, 0x70u, 0x07u, 0x4Au,
+ 0x12u, 0x78u, 0xD2u, 0xB2u, 0x1Au, 0x70u, 0x10u, 0xBDu,
+ 0x00u, 0x20u, 0x10u, 0xBDu, 0x04u, 0x60u, 0x00u, 0x40u,
+ 0x69u, 0xC1u, 0xFFu, 0x1Fu, 0x56u, 0xC1u, 0xFFu, 0x1Fu,
+ 0xDCu, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x60u, 0x00u, 0x40u,
+ 0x38u, 0xB5u, 0x8Cu, 0x4Cu, 0x00u, 0x23u, 0x23u, 0x80u,
+ 0x8Bu, 0x4Bu, 0x1Au, 0x78u, 0x12u, 0xF0u, 0x80u, 0x0Fu,
+ 0x8Au, 0x4Au, 0x12u, 0x78u, 0x00u, 0xF0u, 0x88u, 0x80u,
+ 0x0Au, 0x2Au, 0x00u, 0xF2u, 0x08u, 0x81u, 0xDFu, 0xE8u,
+ 0x12u, 0xF0u, 0x58u, 0x00u, 0x06u, 0x01u, 0x06u, 0x01u,
+ 0x06u, 0x01u, 0x06u, 0x01u, 0x06u, 0x01u, 0x0Bu, 0x00u,
+ 0x06u, 0x01u, 0x78u, 0x00u, 0x06u, 0x01u, 0x7Cu, 0x00u,
+ 0x81u, 0x4Bu, 0x1Au, 0x78u, 0x01u, 0x2Au, 0x09u, 0xD1u,
+ 0x80u, 0x4Bu, 0x1Au, 0x78u, 0x80u, 0x4Bu, 0x03u, 0xEBu,
+ 0xC2u, 0x03u, 0x5Bu, 0x68u, 0x5Bu, 0x68u, 0x63u, 0x60u,
+ 0x12u, 0x23u, 0x11u, 0xE0u, 0x1Au, 0x78u, 0x02u, 0x2Au,
+ 0x13u, 0xD1u, 0x7Cu, 0x4Bu, 0x18u, 0x78u, 0xFFu, 0xF7u,
+ 0xF1u, 0xFDu, 0x00u, 0x28u, 0x00u, 0xF0u, 0xE3u, 0x80u,
+ 0x43u, 0x68u, 0x63u, 0x60u, 0x63u, 0x68u, 0xDAu, 0x78u,
+ 0x63u, 0x68u, 0x9Bu, 0x78u, 0x43u, 0xEAu, 0x02u, 0x23u,
+ 0x23u, 0x80u, 0xBDu, 0xE8u, 0x38u, 0x40u, 0xFFu, 0xF7u,
+ 0x0Bu, 0xBCu, 0x1Bu, 0x78u, 0x03u, 0x2Bu, 0x20u, 0xD1u,
+ 0x71u, 0x4Bu, 0x00u, 0x22u, 0x6Fu, 0x49u, 0xD0u, 0xB2u,
+ 0x0Du, 0x78u, 0x85u, 0x42u, 0x0Au, 0xD8u, 0x0Au, 0x78u,
+ 0x7Au, 0xB1u, 0x6Cu, 0x4Au, 0x6Du, 0x48u, 0x11u, 0x78u,
+ 0x00u, 0x7Cu, 0x6Du, 0x4Au, 0x88u, 0x42u, 0x08u, 0xBFu,
+ 0x13u, 0x46u, 0x06u, 0xE0u, 0x18u, 0x78u, 0x01u, 0x32u,
+ 0x00u, 0x28u, 0xF0u, 0xD0u, 0x19u, 0x78u, 0x0Bu, 0x44u,
+ 0xE8u, 0xE7u, 0x1Au, 0x78u, 0x00u, 0x2Au, 0x00u, 0xF0u,
+ 0xB6u, 0x80u, 0x1Au, 0x78u, 0xD2u, 0xB2u, 0x22u, 0x80u,
+ 0x19u, 0xE0u, 0xBDu, 0xE8u, 0x38u, 0x40u, 0x00u, 0xF0u,
+ 0xE7u, 0xB8u, 0x1Au, 0x78u, 0x12u, 0xF0u, 0x03u, 0x02u,
+ 0x13u, 0xD0u, 0x02u, 0x2Au, 0x40u, 0xF0u, 0xA7u, 0x80u,
+ 0x5Eu, 0x4Bu, 0x22u, 0x80u, 0x1Bu, 0x78u, 0x5Eu, 0x4Au,
+ 0x03u, 0xF0u, 0x7Fu, 0x03u, 0x0Cu, 0x21u, 0x01u, 0xFBu,
+ 0x03u, 0x23u, 0x9Au, 0x78u, 0x5Bu, 0x4Bu, 0xD2u, 0xB2u,
+ 0x1Au, 0x70u, 0x00u, 0x22u, 0x5Au, 0x70u, 0x63u, 0x60u,
+ 0xBBu, 0xE7u, 0x02u, 0x23u, 0x23u, 0x80u, 0x58u, 0x4Bu,
+ 0x19u, 0x78u, 0x56u, 0x4Bu, 0xC9u, 0xB2u, 0x19u, 0x70u,
+ 0xF4u, 0xE7u, 0x01u, 0x23u, 0x23u, 0x80u, 0x55u, 0x4Bu,
+ 0xF1u, 0xE7u, 0x01u, 0x23u, 0x23u, 0x80u, 0x4Fu, 0x4Bu,
+ 0x53u, 0x4Au, 0x1Bu, 0x78u, 0x13u, 0x44u, 0xEAu, 0xE7u,
+ 0x01u, 0x3Au, 0x0Au, 0x2Au, 0x7Fu, 0xD8u, 0xDFu, 0xE8u,
+ 0x02u, 0xF0u, 0x36u, 0x7Eu, 0x52u, 0x7Eu, 0x06u, 0x7Eu,
+ 0x7Eu, 0x7Eu, 0x0Bu, 0x7Eu, 0x22u, 0x00u, 0x43u, 0x4Bu,
+ 0x1Au, 0x78u, 0x4Cu, 0x4Bu, 0xD2u, 0xB2u, 0x60u, 0xE0u,
+ 0x40u, 0x4Bu, 0x1Bu, 0x78u, 0x03u, 0xF0u, 0xFFu, 0x04u,
+ 0x53u, 0xB9u, 0x46u, 0x4Bu, 0x1Au, 0x78u, 0x94u, 0x42u,
+ 0x65u, 0xD0u, 0x1Cu, 0x70u, 0x46u, 0x4Bu, 0x01u, 0x20u,
+ 0x18u, 0x70u, 0xFFu, 0xF7u, 0x15u, 0xFEu, 0x5Eu, 0xE0u,
+ 0x60u, 0x1Eu, 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0x6Au, 0xFDu,
+ 0x00u, 0x28u, 0xEEu, 0xD1u, 0x5Bu, 0xE0u, 0xFFu, 0xF7u,
+ 0x1Du, 0xFFu, 0x00u, 0x28u, 0x57u, 0xD0u, 0x37u, 0x4Bu,
+ 0x01u, 0x22u, 0x1Cu, 0x78u, 0x3Du, 0x4Bu, 0xE4u, 0xB2u,
+ 0x1Cu, 0x70u, 0x3Bu, 0x4Bu, 0x1Au, 0x70u, 0xFFu, 0xF7u,
+ 0x6Du, 0xFDu, 0x37u, 0x4Bu, 0x1Au, 0x5Du, 0x3Au, 0x4Bu,
+ 0xD2u, 0xB2u, 0x1Au, 0x55u, 0x43u, 0xE0u, 0x1Bu, 0x78u,
+ 0x03u, 0xF0u, 0x03u, 0x03u, 0x01u, 0x2Bu, 0x32u, 0xD0u,
+ 0x0Cu, 0xD3u, 0x02u, 0x2Bu, 0x3Fu, 0xD1u, 0x03u, 0xF1u,
+ 0x80u, 0x43u, 0x03u, 0xF5u, 0xC0u, 0x43u, 0x1Bu, 0x78u,
+ 0x00u, 0x2Bu, 0x38u, 0xD1u, 0xBDu, 0xE8u, 0x38u, 0x40u,
+ 0xFFu, 0xF7u, 0xBAu, 0xBEu, 0x21u, 0x4Bu, 0x1Bu, 0x78u,
+ 0x01u, 0x2Bu, 0x30u, 0xD1u, 0x26u, 0x4Bu, 0x1Au, 0x78u,
+ 0x02u, 0xF0u, 0xFDu, 0x02u, 0x19u, 0xE0u, 0x1Bu, 0x78u,
+ 0x03u, 0xF0u, 0x03u, 0x03u, 0x01u, 0x2Bu, 0x16u, 0xD0u,
+ 0x0Bu, 0xD3u, 0x02u, 0x2Bu, 0x23u, 0xD1u, 0x03u, 0xF1u,
+ 0x80u, 0x43u, 0x03u, 0xF5u, 0xC0u, 0x43u, 0x1Bu, 0x78u,
+ 0xEBu, 0xB9u, 0xBDu, 0xE8u, 0x38u, 0x40u, 0xFFu, 0xF7u,
+ 0x75u, 0xBEu, 0x14u, 0x4Bu, 0x1Bu, 0x78u, 0x01u, 0x2Bu,
+ 0x15u, 0xD1u, 0x19u, 0x4Bu, 0x1Au, 0x78u, 0x42u, 0xF0u,
+ 0x02u, 0x02u, 0x1Au, 0x70u, 0x0Bu, 0xE0u, 0x13u, 0x4Bu,
+ 0x1Au, 0x78u, 0x62u, 0xB9u, 0x1Bu, 0x78u, 0x1Bu, 0x4Au,
+ 0x0Cu, 0x48u, 0xDBu, 0xB2u, 0xD1u, 0x5Cu, 0x00u, 0x78u,
+ 0x21u, 0xEAu, 0x00u, 0x01u, 0xD1u, 0x54u, 0xBDu, 0xE8u,
+ 0x38u, 0x40u, 0xFFu, 0xF7u, 0x15u, 0xBAu, 0x00u, 0x20u,
+ 0x38u, 0xBDu, 0x00u, 0xBFu, 0x58u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x00u, 0x60u, 0x00u, 0x40u, 0x01u, 0x60u, 0x00u, 0x40u,
+ 0x03u, 0x60u, 0x00u, 0x40u, 0x64u, 0xC1u, 0xFFu, 0x1Fu,
+ 0xB8u, 0x21u, 0x00u, 0x00u, 0x02u, 0x60u, 0x00u, 0x40u,
+ 0x7Eu, 0x22u, 0x00u, 0x00u, 0xFAu, 0x22u, 0x00u, 0x00u,
+ 0x74u, 0x22u, 0x00u, 0x00u, 0x04u, 0x60u, 0x00u, 0x40u,
+ 0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x4Eu, 0xC1u, 0xFFu, 0x1Fu,
+ 0x67u, 0xC1u, 0xFFu, 0x1Fu, 0x69u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x56u, 0xC1u, 0xFFu, 0x1Fu, 0x54u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x68u, 0xC1u, 0xFFu, 0x1Fu, 0x65u, 0xC1u, 0xFFu, 0x1Fu,
+ 0xDCu, 0xC1u, 0xFFu, 0x1Fu, 0x6Bu, 0xC1u, 0xFFu, 0x1Fu,
+ 0x03u, 0x4Bu, 0x00u, 0x20u, 0x1Bu, 0x78u, 0x1Bu, 0x06u,
+ 0x44u, 0xBFu, 0x02u, 0x4Bu, 0x1Bu, 0x78u, 0x70u, 0x47u,
0x00u, 0x60u, 0x00u, 0x40u, 0x01u, 0x60u, 0x00u, 0x40u,
- 0x03u, 0x60u, 0x00u, 0x40u, 0x6Cu, 0xC1u, 0xFFu, 0x1Fu,
- 0xF8u, 0x20u, 0x00u, 0x00u, 0x02u, 0x60u, 0x00u, 0x40u,
- 0xBEu, 0x21u, 0x00u, 0x00u, 0x3Au, 0x22u, 0x00u, 0x00u,
- 0xB4u, 0x21u, 0x00u, 0x00u, 0x04u, 0x60u, 0x00u, 0x40u,
- 0x78u, 0xC1u, 0xFFu, 0x1Fu, 0x55u, 0xC1u, 0xFFu, 0x1Fu,
- 0x6Fu, 0xC1u, 0xFFu, 0x1Fu, 0x71u, 0xC1u, 0xFFu, 0x1Fu,
- 0x5Eu, 0xC1u, 0xFFu, 0x1Fu, 0x5Cu, 0xC1u, 0xFFu, 0x1Fu,
- 0x70u, 0xC1u, 0xFFu, 0x1Fu, 0x6Du, 0xC1u, 0xFFu, 0x1Fu,
- 0xE4u, 0xC1u, 0xFFu, 0x1Fu, 0x08u, 0x48u, 0x02u, 0x78u,
- 0x5Au, 0xB9u, 0x03u, 0x78u, 0x07u, 0x4Au, 0x08u, 0x48u,
- 0xD1u, 0x5Cu, 0x00u, 0x78u, 0x21u, 0xEAu, 0x00u, 0x01u,
- 0xD1u, 0x54u, 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u,
- 0xD1u, 0xB9u, 0x00u, 0x20u, 0x10u, 0xBDu, 0x00u, 0xBFu,
- 0x04u, 0x60u, 0x00u, 0x40u, 0x73u, 0xC1u, 0xFFu, 0x1Fu,
- 0x02u, 0x60u, 0x00u, 0x40u, 0x03u, 0x4Bu, 0x18u, 0x78u,
- 0x01u, 0x06u, 0x44u, 0xBFu, 0x02u, 0x49u, 0x09u, 0x78u,
- 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x60u, 0x00u, 0x40u,
- 0x01u, 0x60u, 0x00u, 0x40u, 0x0Fu, 0x4Bu, 0x18u, 0x78u,
- 0x00u, 0xF0u, 0x03u, 0x01u, 0x01u, 0x29u, 0x0Cu, 0xD0u,
- 0x02u, 0x29u, 0x0Du, 0xD1u, 0x0Cu, 0x4Au, 0x0Cu, 0x21u,
- 0x10u, 0x78u, 0x0Cu, 0x4Au, 0x00u, 0xF0u, 0x7Fu, 0x03u,
- 0x01u, 0xFBu, 0x03u, 0x20u, 0x08u, 0x30u, 0x83u, 0x78u,
- 0x03u, 0xE0u, 0x07u, 0x4Bu, 0x1Bu, 0x78u, 0x00u, 0xE0u,
- 0x00u, 0x23u, 0x07u, 0x49u, 0x0Au, 0x68u, 0xD0u, 0x5Cu,
- 0x03u, 0x28u, 0x01u, 0xD1u, 0xFFu, 0xF7u, 0xC6u, 0xBBu,
- 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x60u, 0x00u, 0x40u,
- 0x04u, 0x60u, 0x00u, 0x40u, 0x78u, 0xC1u, 0xFFu, 0x1Fu,
- 0x74u, 0xC1u, 0xFFu, 0x1Fu, 0x38u, 0xB5u, 0x0Eu, 0x4Du,
- 0x0Eu, 0x4Bu, 0x00u, 0x24u, 0xE8u, 0x1Au, 0x85u, 0x10u,
- 0xACu, 0x42u, 0x05u, 0xD0u, 0x0Bu, 0x49u, 0x51u, 0xF8u,
- 0x24u, 0x20u, 0x90u, 0x47u, 0x01u, 0x34u, 0xF7u, 0xE7u,
- 0x00u, 0xF0u, 0x40u, 0xF9u, 0x08u, 0x49u, 0x09u, 0x4Au,
- 0x54u, 0x1Au, 0xA5u, 0x10u, 0x00u, 0x24u, 0xACu, 0x42u,
- 0x05u, 0xD0u, 0x05u, 0x4Bu, 0x53u, 0xF8u, 0x24u, 0x00u,
- 0x80u, 0x47u, 0x01u, 0x34u, 0xF7u, 0xE7u, 0x38u, 0xBDu,
- 0x58u, 0x22u, 0x00u, 0x00u, 0x58u, 0x22u, 0x00u, 0x00u,
- 0x58u, 0x22u, 0x00u, 0x00u, 0x60u, 0x22u, 0x00u, 0x00u,
+ 0x10u, 0x4Bu, 0x1Bu, 0x78u, 0x03u, 0xF0u, 0x03u, 0x03u,
+ 0x01u, 0x2Bu, 0x0Cu, 0xD0u, 0x02u, 0x2Bu, 0x0Eu, 0xD1u,
+ 0x0Du, 0x4Bu, 0x0Eu, 0x4Au, 0x1Bu, 0x78u, 0x0Cu, 0x21u,
+ 0x03u, 0xF0u, 0x7Fu, 0x03u, 0x01u, 0xFBu, 0x03u, 0x23u,
+ 0x08u, 0x33u, 0x9Bu, 0x78u, 0x01u, 0xE0u, 0x08u, 0x4Bu,
+ 0x1Bu, 0x78u, 0xDBu, 0xB2u, 0x00u, 0xE0u, 0x00u, 0x23u,
+ 0x07u, 0x4Au, 0x12u, 0x68u, 0xD3u, 0x5Cu, 0x03u, 0x2Bu,
+ 0x01u, 0xD1u, 0xFFu, 0xF7u, 0xE7u, 0xBBu, 0x00u, 0x20u,
+ 0x70u, 0x47u, 0x00u, 0xBFu, 0x00u, 0x60u, 0x00u, 0x40u,
+ 0x04u, 0x60u, 0x00u, 0x40u, 0x70u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x6Cu, 0xC1u, 0xFFu, 0x1Fu, 0x70u, 0xB5u, 0x0Eu, 0x4Bu,
+ 0x0Eu, 0x4Du, 0x00u, 0x24u, 0xEDu, 0x1Au, 0xADu, 0x10u,
+ 0x1Eu, 0x46u, 0xACu, 0x42u, 0x04u, 0xD0u, 0x56u, 0xF8u,
+ 0x24u, 0x20u, 0x90u, 0x47u, 0x01u, 0x34u, 0xF8u, 0xE7u,
+ 0x00u, 0xF0u, 0x40u, 0xF9u, 0x08u, 0x4Du, 0x09u, 0x4Bu,
+ 0x00u, 0x24u, 0xEDu, 0x1Au, 0xADu, 0x10u, 0x1Eu, 0x46u,
+ 0xACu, 0x42u, 0x04u, 0xD0u, 0x56u, 0xF8u, 0x24u, 0x20u,
+ 0x90u, 0x47u, 0x01u, 0x34u, 0xF8u, 0xE7u, 0x70u, 0xBDu,
+ 0x18u, 0x23u, 0x00u, 0x00u, 0x18u, 0x23u, 0x00u, 0x00u,
+ 0x20u, 0x23u, 0x00u, 0x00u, 0x18u, 0x23u, 0x00u, 0x00u,
0x10u, 0xB5u, 0x00u, 0x23u, 0x93u, 0x42u, 0x03u, 0xD0u,
0xCCu, 0x5Cu, 0xC4u, 0x54u, 0x01u, 0x33u, 0xF9u, 0xE7u,
- 0x10u, 0xBDu, 0x82u, 0x18u, 0x03u, 0x46u, 0x93u, 0x42u,
+ 0x10u, 0xBDu, 0x02u, 0x44u, 0x03u, 0x46u, 0x93u, 0x42u,
0x02u, 0xD0u, 0x03u, 0xF8u, 0x01u, 0x1Bu, 0xFAu, 0xE7u,
- 0x70u, 0x47u, 0x00u, 0x00u, 0xA0u, 0x22u, 0x00u, 0x00u,
- 0x32u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x70u, 0x47u, 0x00u, 0x00u, 0x60u, 0x23u, 0x00u, 0x00u,
+ 0x05u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x10u, 0x51u, 0x00u, 0x40u, 0x10u, 0x00u, 0xC0u, 0x51u,
0x00u, 0x40u, 0x10u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u,
0x00u, 0x10u, 0x00u, 0x14u, 0x01u, 0x40u, 0x00u, 0x08u,
0x30u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u,
0x03u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x33u,
0x33u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
- 0x69u, 0x30u, 0x13u, 0x2Eu, 0x00u, 0x14u, 0x01u, 0x01u,
- 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x21u, 0x00u, 0x00u,
- 0x01u, 0x00u, 0x00u, 0x00u, 0x3Au, 0x22u, 0x00u, 0x00u,
- 0x01u, 0x00u, 0x00u, 0x00u, 0x10u, 0x21u, 0x00u, 0x00u,
- 0x01u, 0x00u, 0x00u, 0x00u, 0x11u, 0x22u, 0x00u, 0x00u,
- 0x02u, 0x00u, 0x00u, 0x00u, 0x32u, 0x21u, 0x00u, 0x00u,
- 0x01u, 0x00u, 0x00u, 0x00u, 0x44u, 0x21u, 0x00u, 0x00u,
- 0x00u, 0x00u, 0x00u, 0x00u, 0x30u, 0x21u, 0x00u, 0x00u,
+ 0x69u, 0x30u, 0x13u, 0x2Eu, 0x00u, 0x1Eu, 0x01u, 0x01u,
+ 0x01u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x21u, 0x00u, 0x00u,
+ 0x01u, 0x00u, 0x00u, 0x00u, 0xFAu, 0x22u, 0x00u, 0x00u,
+ 0x01u, 0x00u, 0x00u, 0x00u, 0xD0u, 0x21u, 0x00u, 0x00u,
+ 0x01u, 0x00u, 0x00u, 0x00u, 0xD1u, 0x22u, 0x00u, 0x00u,
+ 0x02u, 0x00u, 0x00u, 0x00u, 0xF2u, 0x21u, 0x00u, 0x00u,
+ 0x01u, 0x00u, 0x00u, 0x00u, 0x04u, 0x22u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0xF0u, 0x21u, 0x00u, 0x00u,
0x03u, 0x00u, 0x00u, 0x00u, 0x01u, 0x03u, 0x40u, 0x00u,
0x03u, 0x00u, 0x00u, 0x00u, 0x82u, 0x03u, 0x40u, 0x00u,
0x03u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
- 0x4Cu, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
- 0x80u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
- 0x74u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x0Cu, 0x22u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x40u, 0x22u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x34u, 0x22u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
- 0x8Cu, 0x21u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
- 0x23u, 0x22u, 0x00u, 0x00u, 0x41u, 0x00u, 0x00u, 0x00u,
- 0x33u, 0xC2u, 0xFFu, 0x1Fu, 0x74u, 0xC2u, 0xFFu, 0x1Fu,
- 0x41u, 0x00u, 0x00u, 0x00u, 0xF2u, 0xC1u, 0xFFu, 0x1Fu,
- 0xEEu, 0xC1u, 0xFFu, 0x1Fu, 0x24u, 0x00u, 0x05u, 0x01u,
+ 0x4Cu, 0x22u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u,
+ 0xE3u, 0x22u, 0x00u, 0x00u, 0x41u, 0x00u, 0x00u, 0x00u,
+ 0x2Bu, 0xC2u, 0xFFu, 0x1Fu, 0x6Cu, 0xC2u, 0xFFu, 0x1Fu,
+ 0x41u, 0x00u, 0x00u, 0x00u, 0xEAu, 0xC1u, 0xFFu, 0x1Fu,
+ 0xE6u, 0xC1u, 0xFFu, 0x1Fu, 0x24u, 0x00u, 0x05u, 0x01u,
0x09u, 0x00u, 0xA1u, 0x00u, 0x09u, 0x00u, 0xA1u, 0x00u,
0x09u, 0x00u, 0x15u, 0x00u, 0x25u, 0xFFu, 0x75u, 0x08u,
0x95u, 0x40u, 0x91u, 0x02u, 0x09u, 0x00u, 0x15u, 0x00u,
0x51u, 0x00u, 0x00u, 0x00u, 0xB1u, 0x01u, 0x00u, 0x00u,
0xF8u, 0xB5u, 0x00u, 0xBFu, 0xF8u, 0xBCu, 0x08u, 0xBCu,
0x9Eu, 0x46u, 0x70u, 0x47u, 0x2Du, 0x00u, 0x00u, 0x00u,
- 0x80u, 0x22u, 0x00u, 0x00u, 0x08u, 0xC1u, 0xFFu, 0x1Fu,
- 0x20u, 0x00u, 0x00u, 0x00u, 0x50u, 0x01u, 0x00u, 0x00u,
- 0x00u, 0x00u, 0x00u, 0x00u, 0x1Cu, 0x20u, 0x00u, 0x00u,
- 0x20u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x7Du,
+ 0x40u, 0x23u, 0x00u, 0x00u, 0x08u, 0xC1u, 0xFFu, 0x1Fu,
+ 0x20u, 0x00u, 0x00u, 0x00u, 0x48u, 0x01u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0xDCu, 0x20u, 0x00u, 0x00u,
+ 0xE0u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x7Du,
0x00u, 0xFAu, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u,
0x00u, 0x90u, 0xD0u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
#endif
const uint8 cy_metadata[] = {
0x00u, 0x01u, 0x2Eu, 0x13u, 0x30u, 0x69u, 0x00u, 0x01u,
- 0x2Eu, 0x1Fu, 0x9Au, 0x6Bu};
+ 0x2Eu, 0x20u, 0x36u, 0x6Bu};
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
__attribute__ ((__section__(".cycustnvl"), used))
/* GENERATED CODE -- CHANGES WILL BE OVERWRITTEN */
-define symbol CYDEV_BTLDR_SIZE = 0x00002300;
+define symbol CYDEV_BTLDR_SIZE = 0x00002400;
/*******************************************************************************
* FILENAME: cydevice.h
* OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator 3.1
*
* DESCRIPTION:
* This file provides all of the address values for the entire PSoC device.
/*******************************************************************************
* FILENAME: cydevice_trm.h
*
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator 3.1
*
* DESCRIPTION:
* This file provides all of the address values for the entire PSoC device.
/*******************************************************************************
* FILENAME: cydevicegnu.inc
* OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator 3.1
*
* DESCRIPTION:
* This file provides all of the address values for the entire PSoC device.
/*******************************************************************************
* FILENAME: cydevicegnu_trm.inc
*
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator 3.1
*
* DESCRIPTION:
* This file provides all of the address values for the entire PSoC device.
;
; FILENAME: cydeviceiar.inc
; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator 3.1
;
; DESCRIPTION:
; This file provides all of the address values for the entire PSoC device.
;
; FILENAME: cydeviceiar_trm.inc
;
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator 3.1
;
; DESCRIPTION:
; This file provides all of the address values for the entire PSoC device.
;
; FILENAME: cydevicerv.inc
; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator 3.1
;
; DESCRIPTION:
; This file provides all of the address values for the entire PSoC device.
;
; FILENAME: cydevicerv_trm.inc
;
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator 3.1
;
; DESCRIPTION:
; This file provides all of the address values for the entire PSoC device.
#include <cydevice.h>
#include <cydevice_trm.h>
-/* Debug_Timer_Interrupt */
-#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define Debug_Timer_Interrupt__INTC_MASK 0x02u
-#define Debug_Timer_Interrupt__INTC_NUMBER 1u
-#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u
-#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1
-#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SCSI_RX_DMA_COMPLETE */
-#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u
-#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u
-#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0
-#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SCSI_TX_DMA_COMPLETE */
-#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x08u
-#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 3u
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3
-#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* Debug_Timer_TimerHW */
-#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0
-#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1
-#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0
-#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1
-#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2
-#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0
-#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1
-#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0
-#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1
-#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3
-#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u
-#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3
-#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u
-#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0
-#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1
-#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0
+/* LED1 */
+#define LED1__0__MASK 0x02u
+#define LED1__0__PC CYREG_PRT0_PC1
+#define LED1__0__PORT 0u
+#define LED1__0__SHIFT 1
+#define LED1__AG CYREG_PRT0_AG
+#define LED1__AMUX CYREG_PRT0_AMUX
+#define LED1__BIE CYREG_PRT0_BIE
+#define LED1__BIT_MASK CYREG_PRT0_BIT_MASK
+#define LED1__BYP CYREG_PRT0_BYP
+#define LED1__CTL CYREG_PRT0_CTL
+#define LED1__DM0 CYREG_PRT0_DM0
+#define LED1__DM1 CYREG_PRT0_DM1
+#define LED1__DM2 CYREG_PRT0_DM2
+#define LED1__DR CYREG_PRT0_DR
+#define LED1__INP_DIS CYREG_PRT0_INP_DIS
+#define LED1__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define LED1__LCD_EN CYREG_PRT0_LCD_EN
+#define LED1__MASK 0x02u
+#define LED1__PORT 0u
+#define LED1__PRT CYREG_PRT0_PRT
+#define LED1__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define LED1__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define LED1__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define LED1__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define LED1__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define LED1__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define LED1__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define LED1__PS CYREG_PRT0_PS
+#define LED1__SHIFT 1
+#define LED1__SLW CYREG_PRT0_SLW
-/* SD_RX_DMA_COMPLETE */
-#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SD_RX_DMA_COMPLETE__INTC_MASK 0x10u
-#define SD_RX_DMA_COMPLETE__INTC_NUMBER 4u
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
-#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* SD_CD */
+#define SD_CD__0__MASK 0x20u
+#define SD_CD__0__PC CYREG_PRT3_PC5
+#define SD_CD__0__PORT 3u
+#define SD_CD__0__SHIFT 5
+#define SD_CD__AG CYREG_PRT3_AG
+#define SD_CD__AMUX CYREG_PRT3_AMUX
+#define SD_CD__BIE CYREG_PRT3_BIE
+#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_CD__BYP CYREG_PRT3_BYP
+#define SD_CD__CTL CYREG_PRT3_CTL
+#define SD_CD__DM0 CYREG_PRT3_DM0
+#define SD_CD__DM1 CYREG_PRT3_DM1
+#define SD_CD__DM2 CYREG_PRT3_DM2
+#define SD_CD__DR CYREG_PRT3_DR
+#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_CD__MASK 0x20u
+#define SD_CD__PORT 3u
+#define SD_CD__PRT CYREG_PRT3_PRT
+#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_CD__PS CYREG_PRT3_PS
+#define SD_CD__SHIFT 5
+#define SD_CD__SLW CYREG_PRT3_SLW
-/* SD_TX_DMA_COMPLETE */
-#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SD_TX_DMA_COMPLETE__INTC_MASK 0x20u
-#define SD_TX_DMA_COMPLETE__INTC_NUMBER 5u
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
-#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5
-#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* SD_CS */
+#define SD_CS__0__MASK 0x10u
+#define SD_CS__0__PC CYREG_PRT3_PC4
+#define SD_CS__0__PORT 3u
+#define SD_CS__0__SHIFT 4
+#define SD_CS__AG CYREG_PRT3_AG
+#define SD_CS__AMUX CYREG_PRT3_AMUX
+#define SD_CS__BIE CYREG_PRT3_BIE
+#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_CS__BYP CYREG_PRT3_BYP
+#define SD_CS__CTL CYREG_PRT3_CTL
+#define SD_CS__DM0 CYREG_PRT3_DM0
+#define SD_CS__DM1 CYREG_PRT3_DM1
+#define SD_CS__DM2 CYREG_PRT3_DM2
+#define SD_CS__DR CYREG_PRT3_DR
+#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_CS__MASK 0x10u
+#define SD_CS__PORT 3u
+#define SD_CS__PRT CYREG_PRT3_PRT
+#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_CS__PS CYREG_PRT3_PS
+#define SD_CS__SHIFT 4
+#define SD_CS__SLW CYREG_PRT3_SLW
-/* SCSI_Parity_Error */
-#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
-#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST
+/* USBFS_arb_int */
+#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_arb_int__INTC_MASK 0x400000u
+#define USBFS_arb_int__INTC_NUMBER 22u
+#define USBFS_arb_int__INTC_PRIOR_NUM 7u
+#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22
+#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* USBFS_bus_reset */
#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-/* SCSI_CTL_PHASE */
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
+/* USBFS_Dm */
+#define USBFS_Dm__0__MASK 0x80u
+#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
+#define USBFS_Dm__0__PORT 15u
+#define USBFS_Dm__0__SHIFT 7
+#define USBFS_Dm__AG CYREG_PRT15_AG
+#define USBFS_Dm__AMUX CYREG_PRT15_AMUX
+#define USBFS_Dm__BIE CYREG_PRT15_BIE
+#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK
+#define USBFS_Dm__BYP CYREG_PRT15_BYP
+#define USBFS_Dm__CTL CYREG_PRT15_CTL
+#define USBFS_Dm__DM0 CYREG_PRT15_DM0
+#define USBFS_Dm__DM1 CYREG_PRT15_DM1
+#define USBFS_Dm__DM2 CYREG_PRT15_DM2
+#define USBFS_Dm__DR CYREG_PRT15_DR
+#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS
+#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN
+#define USBFS_Dm__MASK 0x80u
+#define USBFS_Dm__PORT 15u
+#define USBFS_Dm__PRT CYREG_PRT15_PRT
+#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define USBFS_Dm__PS CYREG_PRT15_PS
+#define USBFS_Dm__SHIFT 7
+#define USBFS_Dm__SLW CYREG_PRT15_SLW
-/* SCSI_Filtered */
-#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u
-#define SCSI_Filtered_sts_sts_reg__0__POS 0
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST
-#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
-#define SCSI_Filtered_sts_sts_reg__1__POS 1
-#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
-#define SCSI_Filtered_sts_sts_reg__2__POS 2
-#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
-#define SCSI_Filtered_sts_sts_reg__3__POS 3
-#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
-#define SCSI_Filtered_sts_sts_reg__4__POS 4
-#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB00_MSK
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB00_ST
+/* USBFS_Dp */
+#define USBFS_Dp__0__MASK 0x40u
+#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
+#define USBFS_Dp__0__PORT 15u
+#define USBFS_Dp__0__SHIFT 6
+#define USBFS_Dp__AG CYREG_PRT15_AG
+#define USBFS_Dp__AMUX CYREG_PRT15_AMUX
+#define USBFS_Dp__BIE CYREG_PRT15_BIE
+#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK
+#define USBFS_Dp__BYP CYREG_PRT15_BYP
+#define USBFS_Dp__CTL CYREG_PRT15_CTL
+#define USBFS_Dp__DM0 CYREG_PRT15_DM0
+#define USBFS_Dp__DM1 CYREG_PRT15_DM1
+#define USBFS_Dp__DM2 CYREG_PRT15_DM2
+#define USBFS_Dp__DR CYREG_PRT15_DR
+#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS
+#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT
+#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN
+#define USBFS_Dp__MASK 0x40u
+#define USBFS_Dp__PORT 15u
+#define USBFS_Dp__PRT CYREG_PRT15_PRT
+#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define USBFS_Dp__PS CYREG_PRT15_PS
+#define USBFS_Dp__SHIFT 6
+#define USBFS_Dp__SLW CYREG_PRT15_SLW
+#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15
-/* SCSI_Out_Bits */
-#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u
-#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
-#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
-#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
-#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
-#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
-#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3
-#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u
-#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4
-#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u
-#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5
-#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u
-#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
-#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
-#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+/* USBFS_dp_int */
+#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_dp_int__INTC_MASK 0x1000u
+#define USBFS_dp_int__INTC_NUMBER 12u
+#define USBFS_dp_int__INTC_PRIOR_NUM 7u
+#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12
+#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-/* USBFS_arb_int */
-#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_arb_int__INTC_MASK 0x400000u
-#define USBFS_arb_int__INTC_NUMBER 22u
-#define USBFS_arb_int__INTC_PRIOR_NUM 7u
-#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22
-#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* USBFS_ep_0 */
+#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_0__INTC_MASK 0x1000000u
+#define USBFS_ep_0__INTC_NUMBER 24u
+#define USBFS_ep_0__INTC_PRIOR_NUM 7u
+#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24
+#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_1 */
+#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_1__INTC_MASK 0x40u
+#define USBFS_ep_1__INTC_NUMBER 6u
+#define USBFS_ep_1__INTC_PRIOR_NUM 7u
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_6
+#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_2 */
+#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_2__INTC_MASK 0x80u
+#define USBFS_ep_2__INTC_NUMBER 7u
+#define USBFS_ep_2__INTC_PRIOR_NUM 7u
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_7
+#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_3 */
+#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_3__INTC_MASK 0x100u
+#define USBFS_ep_3__INTC_NUMBER 8u
+#define USBFS_ep_3__INTC_PRIOR_NUM 7u
+#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_8
+#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_4 */
+#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_4__INTC_MASK 0x200u
+#define USBFS_ep_4__INTC_NUMBER 9u
+#define USBFS_ep_4__INTC_PRIOR_NUM 7u
+#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_9
+#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* USBFS_sof_int */
#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-/* SCSI_Out_Ctl */
-#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
+/* USBFS_USB */
+#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG
+#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG
+#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN
+#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR
+#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG
+#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN
+#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR
+#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG
+#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN
+#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR
+#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG
+#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN
+#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR
+#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG
+#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN
+#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR
+#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG
+#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN
+#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR
+#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG
+#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN
+#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR
+#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG
+#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN
+#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR
+#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN
+#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR
+#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR
+#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA
+#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB
+#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA
+#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB
+#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR
+#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA
+#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB
+#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA
+#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB
+#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR
+#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA
+#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB
+#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA
+#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB
+#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR
+#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA
+#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB
+#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA
+#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB
+#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR
+#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA
+#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB
+#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA
+#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB
+#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR
+#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA
+#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB
+#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA
+#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB
+#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR
+#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA
+#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB
+#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA
+#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB
+#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR
+#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA
+#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB
+#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA
+#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB
+#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE
+#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT
+#define USBFS_USB__CR0 CYREG_USB_CR0
+#define USBFS_USB__CR1 CYREG_USB_CR1
+#define USBFS_USB__CWA CYREG_USB_CWA
+#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB
+#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES
+#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB
+#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG
+#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
+#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE
+#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT
+#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR
+#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0
+#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1
+#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2
+#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3
+#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4
+#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5
+#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6
+#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7
+#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE
+#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5
+#define USBFS_USB__PM_ACT_MSK 0x01u
+#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5
+#define USBFS_USB__PM_STBY_MSK 0x01u
+#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
+#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
+#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0
+#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1
+#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0
+#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0
+#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1
+#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0
+#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0
+#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1
+#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0
+#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0
+#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1
+#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0
+#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0
+#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1
+#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0
+#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0
+#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1
+#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0
+#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0
+#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1
+#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0
+#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0
+#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1
+#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0
+#define USBFS_USB__SOF0 CYREG_USB_SOF0
+#define USBFS_USB__SOF1 CYREG_USB_SOF1
+#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
+#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0
+#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
-/* SCSI_Out_DBx */
-#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
-#define SCSI_Out_DBx__0__AMUX CYREG_PRT5_AMUX
-#define SCSI_Out_DBx__0__BIE CYREG_PRT5_BIE
-#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_Out_DBx__0__BYP CYREG_PRT5_BYP
-#define SCSI_Out_DBx__0__CTL CYREG_PRT5_CTL
-#define SCSI_Out_DBx__0__DM0 CYREG_PRT5_DM0
-#define SCSI_Out_DBx__0__DM1 CYREG_PRT5_DM1
-#define SCSI_Out_DBx__0__DM2 CYREG_PRT5_DM2
-#define SCSI_Out_DBx__0__DR CYREG_PRT5_DR
-#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_Out_DBx__0__MASK 0x02u
-#define SCSI_Out_DBx__0__PC CYREG_PRT5_PC1
-#define SCSI_Out_DBx__0__PORT 5u
-#define SCSI_Out_DBx__0__PRT CYREG_PRT5_PRT
-#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_Out_DBx__0__PS CYREG_PRT5_PS
-#define SCSI_Out_DBx__0__SHIFT 1
-#define SCSI_Out_DBx__0__SLW CYREG_PRT5_SLW
-#define SCSI_Out_DBx__1__AG CYREG_PRT5_AG
-#define SCSI_Out_DBx__1__AMUX CYREG_PRT5_AMUX
-#define SCSI_Out_DBx__1__BIE CYREG_PRT5_BIE
-#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_Out_DBx__1__BYP CYREG_PRT5_BYP
-#define SCSI_Out_DBx__1__CTL CYREG_PRT5_CTL
-#define SCSI_Out_DBx__1__DM0 CYREG_PRT5_DM0
-#define SCSI_Out_DBx__1__DM1 CYREG_PRT5_DM1
-#define SCSI_Out_DBx__1__DM2 CYREG_PRT5_DM2
-#define SCSI_Out_DBx__1__DR CYREG_PRT5_DR
-#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_Out_DBx__1__MASK 0x01u
-#define SCSI_Out_DBx__1__PC CYREG_PRT5_PC0
-#define SCSI_Out_DBx__1__PORT 5u
-#define SCSI_Out_DBx__1__PRT CYREG_PRT5_PRT
-#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_Out_DBx__1__PS CYREG_PRT5_PS
-#define SCSI_Out_DBx__1__SHIFT 0
-#define SCSI_Out_DBx__1__SLW CYREG_PRT5_SLW
-#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__2__MASK 0x20u
-#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC5
-#define SCSI_Out_DBx__2__PORT 6u
-#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__2__SHIFT 5
-#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__3__MASK 0x10u
-#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC4
-#define SCSI_Out_DBx__3__PORT 6u
-#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__3__SHIFT 4
-#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__4__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__4__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__4__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__4__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__4__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__4__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__4__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__4__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__4__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__4__MASK 0x80u
-#define SCSI_Out_DBx__4__PC CYREG_PRT2_PC7
-#define SCSI_Out_DBx__4__PORT 2u
-#define SCSI_Out_DBx__4__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__4__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__4__SHIFT 7
-#define SCSI_Out_DBx__4__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__5__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__5__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__5__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__5__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__5__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__5__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__5__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__5__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__5__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__5__MASK 0x40u
-#define SCSI_Out_DBx__5__PC CYREG_PRT2_PC6
-#define SCSI_Out_DBx__5__PORT 2u
-#define SCSI_Out_DBx__5__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__5__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__5__SHIFT 6
-#define SCSI_Out_DBx__5__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__6__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__6__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__6__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__6__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__6__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__6__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__6__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__6__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__6__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__6__MASK 0x08u
-#define SCSI_Out_DBx__6__PC CYREG_PRT2_PC3
-#define SCSI_Out_DBx__6__PORT 2u
-#define SCSI_Out_DBx__6__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__6__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__6__SHIFT 3
-#define SCSI_Out_DBx__6__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__7__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__7__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__7__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__7__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__7__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__7__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__7__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__7__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__7__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__7__MASK 0x04u
-#define SCSI_Out_DBx__7__PC CYREG_PRT2_PC2
-#define SCSI_Out_DBx__7__PORT 2u
-#define SCSI_Out_DBx__7__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__7__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__7__SHIFT 2
-#define SCSI_Out_DBx__7__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB0__AG CYREG_PRT5_AG
-#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT5_AMUX
-#define SCSI_Out_DBx__DB0__BIE CYREG_PRT5_BIE
-#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_Out_DBx__DB0__BYP CYREG_PRT5_BYP
-#define SCSI_Out_DBx__DB0__CTL CYREG_PRT5_CTL
-#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT5_DM0
-#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT5_DM1
-#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT5_DM2
-#define SCSI_Out_DBx__DB0__DR CYREG_PRT5_DR
-#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_Out_DBx__DB0__MASK 0x02u
-#define SCSI_Out_DBx__DB0__PC CYREG_PRT5_PC1
-#define SCSI_Out_DBx__DB0__PORT 5u
-#define SCSI_Out_DBx__DB0__PRT CYREG_PRT5_PRT
-#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_Out_DBx__DB0__PS CYREG_PRT5_PS
-#define SCSI_Out_DBx__DB0__SHIFT 1
-#define SCSI_Out_DBx__DB0__SLW CYREG_PRT5_SLW
-#define SCSI_Out_DBx__DB1__AG CYREG_PRT5_AG
-#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT5_AMUX
-#define SCSI_Out_DBx__DB1__BIE CYREG_PRT5_BIE
-#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_Out_DBx__DB1__BYP CYREG_PRT5_BYP
-#define SCSI_Out_DBx__DB1__CTL CYREG_PRT5_CTL
-#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT5_DM0
-#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT5_DM1
-#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT5_DM2
-#define SCSI_Out_DBx__DB1__DR CYREG_PRT5_DR
-#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_Out_DBx__DB1__MASK 0x01u
-#define SCSI_Out_DBx__DB1__PC CYREG_PRT5_PC0
-#define SCSI_Out_DBx__DB1__PORT 5u
-#define SCSI_Out_DBx__DB1__PRT CYREG_PRT5_PRT
-#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_Out_DBx__DB1__PS CYREG_PRT5_PS
-#define SCSI_Out_DBx__DB1__SHIFT 0
-#define SCSI_Out_DBx__DB1__SLW CYREG_PRT5_SLW
-#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__DB2__MASK 0x20u
-#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC5
-#define SCSI_Out_DBx__DB2__PORT 6u
-#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__DB2__SHIFT 5
-#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__DB3__MASK 0x10u
-#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC4
-#define SCSI_Out_DBx__DB3__PORT 6u
-#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__DB3__SHIFT 4
-#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__DB4__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB4__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB4__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB4__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB4__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB4__MASK 0x80u
-#define SCSI_Out_DBx__DB4__PC CYREG_PRT2_PC7
-#define SCSI_Out_DBx__DB4__PORT 2u
-#define SCSI_Out_DBx__DB4__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB4__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB4__SHIFT 7
-#define SCSI_Out_DBx__DB4__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB5__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB5__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB5__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB5__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB5__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB5__MASK 0x40u
-#define SCSI_Out_DBx__DB5__PC CYREG_PRT2_PC6
-#define SCSI_Out_DBx__DB5__PORT 2u
-#define SCSI_Out_DBx__DB5__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB5__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB5__SHIFT 6
-#define SCSI_Out_DBx__DB5__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB6__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB6__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB6__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB6__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB6__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB6__MASK 0x08u
-#define SCSI_Out_DBx__DB6__PC CYREG_PRT2_PC3
-#define SCSI_Out_DBx__DB6__PORT 2u
-#define SCSI_Out_DBx__DB6__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB6__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB6__SHIFT 3
-#define SCSI_Out_DBx__DB6__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB7__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB7__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB7__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB7__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB7__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB7__MASK 0x04u
-#define SCSI_Out_DBx__DB7__PC CYREG_PRT2_PC2
-#define SCSI_Out_DBx__DB7__PORT 2u
-#define SCSI_Out_DBx__DB7__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB7__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB7__SHIFT 2
-#define SCSI_Out_DBx__DB7__SLW CYREG_PRT2_SLW
-
-/* SCSI_RST_ISR */
-#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define SCSI_RST_ISR__INTC_MASK 0x04u
-#define SCSI_RST_ISR__INTC_NUMBER 2u
-#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u
-#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2
-#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SDCard_BSPIM */
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB09_10_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB09_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB09_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB09_ST
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB09_10_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB09_10_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB09_10_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB09_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB09_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB09_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB09_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB09_MSK
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB09_MSK_ACTL
-#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
-#define SDCard_BSPIM_RxStsReg__4__POS 4
-#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
-#define SDCard_BSPIM_RxStsReg__5__POS 5
-#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
-#define SDCard_BSPIM_RxStsReg__6__POS 6
-#define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB11_MSK
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB11_ST
-#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
-#define SDCard_BSPIM_TxStsReg__0__POS 0
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB10_11_ST
-#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
-#define SDCard_BSPIM_TxStsReg__1__POS 1
-#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
-#define SDCard_BSPIM_TxStsReg__2__POS 2
-#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
-#define SDCard_BSPIM_TxStsReg__3__POS 3
-#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
-#define SDCard_BSPIM_TxStsReg__4__POS 4
-#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB10_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB10_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB10_ST
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB09_10_A0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB09_10_A1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB09_10_D0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB09_10_D1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB09_10_F0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB09_10_F1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB09_A0_A1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB09_A0
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB09_A1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB09_D0_D1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB09_D0
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB09_D1
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB09_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB09_F0_F1
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB09_F0
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB09_F1
-
-/* USBFS_dp_int */
-#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_dp_int__INTC_MASK 0x1000u
-#define USBFS_dp_int__INTC_NUMBER 12u
-#define USBFS_dp_int__INTC_PRIOR_NUM 7u
-#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12
-#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SCSI_In_DBx */
-#define SCSI_In_DBx__0__AG CYREG_PRT5_AG
-#define SCSI_In_DBx__0__AMUX CYREG_PRT5_AMUX
-#define SCSI_In_DBx__0__BIE CYREG_PRT5_BIE
-#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_In_DBx__0__BYP CYREG_PRT5_BYP
-#define SCSI_In_DBx__0__CTL CYREG_PRT5_CTL
-#define SCSI_In_DBx__0__DM0 CYREG_PRT5_DM0
-#define SCSI_In_DBx__0__DM1 CYREG_PRT5_DM1
-#define SCSI_In_DBx__0__DM2 CYREG_PRT5_DM2
-#define SCSI_In_DBx__0__DR CYREG_PRT5_DR
-#define SCSI_In_DBx__0__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_In_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_In_DBx__0__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_In_DBx__0__MASK 0x08u
-#define SCSI_In_DBx__0__PC CYREG_PRT5_PC3
-#define SCSI_In_DBx__0__PORT 5u
-#define SCSI_In_DBx__0__PRT CYREG_PRT5_PRT
-#define SCSI_In_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_In_DBx__0__PS CYREG_PRT5_PS
-#define SCSI_In_DBx__0__SHIFT 3
-#define SCSI_In_DBx__0__SLW CYREG_PRT5_SLW
-#define SCSI_In_DBx__1__AG CYREG_PRT5_AG
-#define SCSI_In_DBx__1__AMUX CYREG_PRT5_AMUX
-#define SCSI_In_DBx__1__BIE CYREG_PRT5_BIE
-#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_In_DBx__1__BYP CYREG_PRT5_BYP
-#define SCSI_In_DBx__1__CTL CYREG_PRT5_CTL
-#define SCSI_In_DBx__1__DM0 CYREG_PRT5_DM0
-#define SCSI_In_DBx__1__DM1 CYREG_PRT5_DM1
-#define SCSI_In_DBx__1__DM2 CYREG_PRT5_DM2
-#define SCSI_In_DBx__1__DR CYREG_PRT5_DR
-#define SCSI_In_DBx__1__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_In_DBx__1__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_In_DBx__1__MASK 0x04u
-#define SCSI_In_DBx__1__PC CYREG_PRT5_PC2
-#define SCSI_In_DBx__1__PORT 5u
-#define SCSI_In_DBx__1__PRT CYREG_PRT5_PRT
-#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_In_DBx__1__PS CYREG_PRT5_PS
-#define SCSI_In_DBx__1__SHIFT 2
-#define SCSI_In_DBx__1__SLW CYREG_PRT5_SLW
-#define SCSI_In_DBx__2__AG CYREG_PRT6_AG
-#define SCSI_In_DBx__2__AMUX CYREG_PRT6_AMUX
-#define SCSI_In_DBx__2__BIE CYREG_PRT6_BIE
-#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In_DBx__2__BYP CYREG_PRT6_BYP
-#define SCSI_In_DBx__2__CTL CYREG_PRT6_CTL
-#define SCSI_In_DBx__2__DM0 CYREG_PRT6_DM0
-#define SCSI_In_DBx__2__DM1 CYREG_PRT6_DM1
-#define SCSI_In_DBx__2__DM2 CYREG_PRT6_DM2
-#define SCSI_In_DBx__2__DR CYREG_PRT6_DR
-#define SCSI_In_DBx__2__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In_DBx__2__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In_DBx__2__MASK 0x80u
-#define SCSI_In_DBx__2__PC CYREG_PRT6_PC7
-#define SCSI_In_DBx__2__PORT 6u
-#define SCSI_In_DBx__2__PRT CYREG_PRT6_PRT
-#define SCSI_In_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In_DBx__2__PS CYREG_PRT6_PS
-#define SCSI_In_DBx__2__SHIFT 7
-#define SCSI_In_DBx__2__SLW CYREG_PRT6_SLW
-#define SCSI_In_DBx__3__AG CYREG_PRT6_AG
-#define SCSI_In_DBx__3__AMUX CYREG_PRT6_AMUX
-#define SCSI_In_DBx__3__BIE CYREG_PRT6_BIE
-#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In_DBx__3__BYP CYREG_PRT6_BYP
-#define SCSI_In_DBx__3__CTL CYREG_PRT6_CTL
-#define SCSI_In_DBx__3__DM0 CYREG_PRT6_DM0
-#define SCSI_In_DBx__3__DM1 CYREG_PRT6_DM1
-#define SCSI_In_DBx__3__DM2 CYREG_PRT6_DM2
-#define SCSI_In_DBx__3__DR CYREG_PRT6_DR
-#define SCSI_In_DBx__3__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In_DBx__3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In_DBx__3__MASK 0x40u
-#define SCSI_In_DBx__3__PC CYREG_PRT6_PC6
-#define SCSI_In_DBx__3__PORT 6u
-#define SCSI_In_DBx__3__PRT CYREG_PRT6_PRT
-#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In_DBx__3__PS CYREG_PRT6_PS
-#define SCSI_In_DBx__3__SHIFT 6
-#define SCSI_In_DBx__3__SLW CYREG_PRT6_SLW
-#define SCSI_In_DBx__4__AG CYREG_PRT12_AG
-#define SCSI_In_DBx__4__BIE CYREG_PRT12_BIE
-#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_In_DBx__4__BYP CYREG_PRT12_BYP
-#define SCSI_In_DBx__4__DM0 CYREG_PRT12_DM0
-#define SCSI_In_DBx__4__DM1 CYREG_PRT12_DM1
-#define SCSI_In_DBx__4__DM2 CYREG_PRT12_DM2
-#define SCSI_In_DBx__4__DR CYREG_PRT12_DR
-#define SCSI_In_DBx__4__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_In_DBx__4__MASK 0x20u
-#define SCSI_In_DBx__4__PC CYREG_PRT12_PC5
-#define SCSI_In_DBx__4__PORT 12u
-#define SCSI_In_DBx__4__PRT CYREG_PRT12_PRT
-#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_In_DBx__4__PS CYREG_PRT12_PS
-#define SCSI_In_DBx__4__SHIFT 5
-#define SCSI_In_DBx__4__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_In_DBx__4__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_In_DBx__4__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_In_DBx__4__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_In_DBx__4__SLW CYREG_PRT12_SLW
-#define SCSI_In_DBx__5__AG CYREG_PRT12_AG
-#define SCSI_In_DBx__5__BIE CYREG_PRT12_BIE
-#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_In_DBx__5__BYP CYREG_PRT12_BYP
-#define SCSI_In_DBx__5__DM0 CYREG_PRT12_DM0
-#define SCSI_In_DBx__5__DM1 CYREG_PRT12_DM1
-#define SCSI_In_DBx__5__DM2 CYREG_PRT12_DM2
-#define SCSI_In_DBx__5__DR CYREG_PRT12_DR
-#define SCSI_In_DBx__5__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_In_DBx__5__MASK 0x10u
-#define SCSI_In_DBx__5__PC CYREG_PRT12_PC4
-#define SCSI_In_DBx__5__PORT 12u
-#define SCSI_In_DBx__5__PRT CYREG_PRT12_PRT
-#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_In_DBx__5__PS CYREG_PRT12_PS
-#define SCSI_In_DBx__5__SHIFT 4
-#define SCSI_In_DBx__5__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_In_DBx__5__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_In_DBx__5__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_In_DBx__5__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_In_DBx__5__SLW CYREG_PRT12_SLW
-#define SCSI_In_DBx__6__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__6__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__6__MASK 0x20u
-#define SCSI_In_DBx__6__PC CYREG_PRT2_PC5
-#define SCSI_In_DBx__6__PORT 2u
-#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__6__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__6__SHIFT 5
-#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__7__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__7__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__7__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__7__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__7__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__7__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__7__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__7__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__7__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__7__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__7__MASK 0x10u
-#define SCSI_In_DBx__7__PC CYREG_PRT2_PC4
-#define SCSI_In_DBx__7__PORT 2u
-#define SCSI_In_DBx__7__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__7__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__7__SHIFT 4
-#define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__DB0__AG CYREG_PRT5_AG
-#define SCSI_In_DBx__DB0__AMUX CYREG_PRT5_AMUX
-#define SCSI_In_DBx__DB0__BIE CYREG_PRT5_BIE
-#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_In_DBx__DB0__BYP CYREG_PRT5_BYP
-#define SCSI_In_DBx__DB0__CTL CYREG_PRT5_CTL
-#define SCSI_In_DBx__DB0__DM0 CYREG_PRT5_DM0
-#define SCSI_In_DBx__DB0__DM1 CYREG_PRT5_DM1
-#define SCSI_In_DBx__DB0__DM2 CYREG_PRT5_DM2
-#define SCSI_In_DBx__DB0__DR CYREG_PRT5_DR
-#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_In_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_In_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_In_DBx__DB0__MASK 0x08u
-#define SCSI_In_DBx__DB0__PC CYREG_PRT5_PC3
-#define SCSI_In_DBx__DB0__PORT 5u
-#define SCSI_In_DBx__DB0__PRT CYREG_PRT5_PRT
-#define SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_In_DBx__DB0__PS CYREG_PRT5_PS
-#define SCSI_In_DBx__DB0__SHIFT 3
-#define SCSI_In_DBx__DB0__SLW CYREG_PRT5_SLW
-#define SCSI_In_DBx__DB1__AG CYREG_PRT5_AG
-#define SCSI_In_DBx__DB1__AMUX CYREG_PRT5_AMUX
-#define SCSI_In_DBx__DB1__BIE CYREG_PRT5_BIE
-#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_In_DBx__DB1__BYP CYREG_PRT5_BYP
-#define SCSI_In_DBx__DB1__CTL CYREG_PRT5_CTL
-#define SCSI_In_DBx__DB1__DM0 CYREG_PRT5_DM0
-#define SCSI_In_DBx__DB1__DM1 CYREG_PRT5_DM1
-#define SCSI_In_DBx__DB1__DM2 CYREG_PRT5_DM2
-#define SCSI_In_DBx__DB1__DR CYREG_PRT5_DR
-#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_In_DBx__DB1__MASK 0x04u
-#define SCSI_In_DBx__DB1__PC CYREG_PRT5_PC2
-#define SCSI_In_DBx__DB1__PORT 5u
-#define SCSI_In_DBx__DB1__PRT CYREG_PRT5_PRT
-#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_In_DBx__DB1__PS CYREG_PRT5_PS
-#define SCSI_In_DBx__DB1__SHIFT 2
-#define SCSI_In_DBx__DB1__SLW CYREG_PRT5_SLW
-#define SCSI_In_DBx__DB2__AG CYREG_PRT6_AG
-#define SCSI_In_DBx__DB2__AMUX CYREG_PRT6_AMUX
-#define SCSI_In_DBx__DB2__BIE CYREG_PRT6_BIE
-#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In_DBx__DB2__BYP CYREG_PRT6_BYP
-#define SCSI_In_DBx__DB2__CTL CYREG_PRT6_CTL
-#define SCSI_In_DBx__DB2__DM0 CYREG_PRT6_DM0
-#define SCSI_In_DBx__DB2__DM1 CYREG_PRT6_DM1
-#define SCSI_In_DBx__DB2__DM2 CYREG_PRT6_DM2
-#define SCSI_In_DBx__DB2__DR CYREG_PRT6_DR
-#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In_DBx__DB2__MASK 0x80u
-#define SCSI_In_DBx__DB2__PC CYREG_PRT6_PC7
-#define SCSI_In_DBx__DB2__PORT 6u
-#define SCSI_In_DBx__DB2__PRT CYREG_PRT6_PRT
-#define SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In_DBx__DB2__PS CYREG_PRT6_PS
-#define SCSI_In_DBx__DB2__SHIFT 7
-#define SCSI_In_DBx__DB2__SLW CYREG_PRT6_SLW
-#define SCSI_In_DBx__DB3__AG CYREG_PRT6_AG
-#define SCSI_In_DBx__DB3__AMUX CYREG_PRT6_AMUX
-#define SCSI_In_DBx__DB3__BIE CYREG_PRT6_BIE
-#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_In_DBx__DB3__BYP CYREG_PRT6_BYP
-#define SCSI_In_DBx__DB3__CTL CYREG_PRT6_CTL
-#define SCSI_In_DBx__DB3__DM0 CYREG_PRT6_DM0
-#define SCSI_In_DBx__DB3__DM1 CYREG_PRT6_DM1
-#define SCSI_In_DBx__DB3__DM2 CYREG_PRT6_DM2
-#define SCSI_In_DBx__DB3__DR CYREG_PRT6_DR
-#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_In_DBx__DB3__MASK 0x40u
-#define SCSI_In_DBx__DB3__PC CYREG_PRT6_PC6
-#define SCSI_In_DBx__DB3__PORT 6u
-#define SCSI_In_DBx__DB3__PRT CYREG_PRT6_PRT
-#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_In_DBx__DB3__PS CYREG_PRT6_PS
-#define SCSI_In_DBx__DB3__SHIFT 6
-#define SCSI_In_DBx__DB3__SLW CYREG_PRT6_SLW
-#define SCSI_In_DBx__DB4__AG CYREG_PRT12_AG
-#define SCSI_In_DBx__DB4__BIE CYREG_PRT12_BIE
-#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_In_DBx__DB4__BYP CYREG_PRT12_BYP
-#define SCSI_In_DBx__DB4__DM0 CYREG_PRT12_DM0
-#define SCSI_In_DBx__DB4__DM1 CYREG_PRT12_DM1
-#define SCSI_In_DBx__DB4__DM2 CYREG_PRT12_DM2
-#define SCSI_In_DBx__DB4__DR CYREG_PRT12_DR
-#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_In_DBx__DB4__MASK 0x20u
-#define SCSI_In_DBx__DB4__PC CYREG_PRT12_PC5
-#define SCSI_In_DBx__DB4__PORT 12u
-#define SCSI_In_DBx__DB4__PRT CYREG_PRT12_PRT
-#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_In_DBx__DB4__PS CYREG_PRT12_PS
-#define SCSI_In_DBx__DB4__SHIFT 5
-#define SCSI_In_DBx__DB4__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_In_DBx__DB4__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_In_DBx__DB4__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_In_DBx__DB4__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_In_DBx__DB4__SLW CYREG_PRT12_SLW
-#define SCSI_In_DBx__DB5__AG CYREG_PRT12_AG
-#define SCSI_In_DBx__DB5__BIE CYREG_PRT12_BIE
-#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT12_BIT_MASK
-#define SCSI_In_DBx__DB5__BYP CYREG_PRT12_BYP
-#define SCSI_In_DBx__DB5__DM0 CYREG_PRT12_DM0
-#define SCSI_In_DBx__DB5__DM1 CYREG_PRT12_DM1
-#define SCSI_In_DBx__DB5__DM2 CYREG_PRT12_DM2
-#define SCSI_In_DBx__DB5__DR CYREG_PRT12_DR
-#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT12_INP_DIS
-#define SCSI_In_DBx__DB5__MASK 0x10u
-#define SCSI_In_DBx__DB5__PC CYREG_PRT12_PC4
-#define SCSI_In_DBx__DB5__PORT 12u
-#define SCSI_In_DBx__DB5__PRT CYREG_PRT12_PRT
-#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
-#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
-#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
-#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
-#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
-#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
-#define SCSI_In_DBx__DB5__PS CYREG_PRT12_PS
-#define SCSI_In_DBx__DB5__SHIFT 4
-#define SCSI_In_DBx__DB5__SIO_CFG CYREG_PRT12_SIO_CFG
-#define SCSI_In_DBx__DB5__SIO_DIFF CYREG_PRT12_SIO_DIFF
-#define SCSI_In_DBx__DB5__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
-#define SCSI_In_DBx__DB5__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
-#define SCSI_In_DBx__DB5__SLW CYREG_PRT12_SLW
-#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__DB6__MASK 0x20u
-#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC5
-#define SCSI_In_DBx__DB6__PORT 2u
-#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__DB6__SHIFT 5
-#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW
-#define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG
-#define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX
-#define SCSI_In_DBx__DB7__BIE CYREG_PRT2_BIE
-#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_In_DBx__DB7__BYP CYREG_PRT2_BYP
-#define SCSI_In_DBx__DB7__CTL CYREG_PRT2_CTL
-#define SCSI_In_DBx__DB7__DM0 CYREG_PRT2_DM0
-#define SCSI_In_DBx__DB7__DM1 CYREG_PRT2_DM1
-#define SCSI_In_DBx__DB7__DM2 CYREG_PRT2_DM2
-#define SCSI_In_DBx__DB7__DR CYREG_PRT2_DR
-#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_In_DBx__DB7__MASK 0x10u
-#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC4
-#define SCSI_In_DBx__DB7__PORT 2u
-#define SCSI_In_DBx__DB7__PRT CYREG_PRT2_PRT
-#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS
-#define SCSI_In_DBx__DB7__SHIFT 4
-#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW
-
-/* SCSI_RX_DMA */
-#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SCSI_RX_DMA__DRQ_NUMBER 0u
-#define SCSI_RX_DMA__NUMBEROF_TDS 0u
-#define SCSI_RX_DMA__PRIORITY 2u
-#define SCSI_RX_DMA__TERMIN_EN 0u
-#define SCSI_RX_DMA__TERMIN_SEL 0u
-#define SCSI_RX_DMA__TERMOUT0_EN 1u
-#define SCSI_RX_DMA__TERMOUT0_SEL 0u
-#define SCSI_RX_DMA__TERMOUT1_EN 0u
-#define SCSI_RX_DMA__TERMOUT1_SEL 0u
-
-/* SCSI_TX_DMA */
-#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SCSI_TX_DMA__DRQ_NUMBER 1u
-#define SCSI_TX_DMA__NUMBEROF_TDS 0u
-#define SCSI_TX_DMA__PRIORITY 2u
-#define SCSI_TX_DMA__TERMIN_EN 0u
-#define SCSI_TX_DMA__TERMIN_SEL 0u
-#define SCSI_TX_DMA__TERMOUT0_EN 1u
-#define SCSI_TX_DMA__TERMOUT0_SEL 1u
-#define SCSI_TX_DMA__TERMOUT1_EN 0u
-#define SCSI_TX_DMA__TERMOUT1_SEL 0u
-
-/* SD_Data_Clk */
-#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0
-#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1
-#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2
-#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u
-#define SD_Data_Clk__INDEX 0x00u
-#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2
-#define SD_Data_Clk__PM_ACT_MSK 0x01u
-#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2
-#define SD_Data_Clk__PM_STBY_MSK 0x01u
-
-/* timer_clock */
-#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0
-#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1
-#define timer_clock__CFG2 CYREG_CLKDIST_DCFG2_CFG2
-#define timer_clock__CFG2_SRC_SEL_MASK 0x07u
-#define timer_clock__INDEX 0x02u
-#define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2
-#define timer_clock__PM_ACT_MSK 0x04u
-#define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2
-#define timer_clock__PM_STBY_MSK 0x04u
-
-/* SCSI_Noise */
-#define SCSI_Noise__0__AG CYREG_PRT2_AG
-#define SCSI_Noise__0__AMUX CYREG_PRT2_AMUX
-#define SCSI_Noise__0__BIE CYREG_PRT2_BIE
-#define SCSI_Noise__0__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Noise__0__BYP CYREG_PRT2_BYP
-#define SCSI_Noise__0__CTL CYREG_PRT2_CTL
-#define SCSI_Noise__0__DM0 CYREG_PRT2_DM0
-#define SCSI_Noise__0__DM1 CYREG_PRT2_DM1
-#define SCSI_Noise__0__DM2 CYREG_PRT2_DM2
-#define SCSI_Noise__0__DR CYREG_PRT2_DR
-#define SCSI_Noise__0__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Noise__0__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Noise__0__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Noise__0__MASK 0x01u
-#define SCSI_Noise__0__PC CYREG_PRT2_PC0
-#define SCSI_Noise__0__PORT 2u
-#define SCSI_Noise__0__PRT CYREG_PRT2_PRT
-#define SCSI_Noise__0__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Noise__0__PS CYREG_PRT2_PS
-#define SCSI_Noise__0__SHIFT 0
-#define SCSI_Noise__0__SLW CYREG_PRT2_SLW
-#define SCSI_Noise__1__AG CYREG_PRT6_AG
-#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX
-#define SCSI_Noise__1__BIE CYREG_PRT6_BIE
-#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Noise__1__BYP CYREG_PRT6_BYP
-#define SCSI_Noise__1__CTL CYREG_PRT6_CTL
-#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0
-#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1
-#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2
-#define SCSI_Noise__1__DR CYREG_PRT6_DR
-#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Noise__1__MASK 0x08u
-#define SCSI_Noise__1__PC CYREG_PRT6_PC3
-#define SCSI_Noise__1__PORT 6u
-#define SCSI_Noise__1__PRT CYREG_PRT6_PRT
-#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Noise__1__PS CYREG_PRT6_PS
-#define SCSI_Noise__1__SHIFT 3
-#define SCSI_Noise__1__SLW CYREG_PRT6_SLW
-#define SCSI_Noise__2__AG CYREG_PRT4_AG
-#define SCSI_Noise__2__AMUX CYREG_PRT4_AMUX
-#define SCSI_Noise__2__BIE CYREG_PRT4_BIE
-#define SCSI_Noise__2__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Noise__2__BYP CYREG_PRT4_BYP
-#define SCSI_Noise__2__CTL CYREG_PRT4_CTL
-#define SCSI_Noise__2__DM0 CYREG_PRT4_DM0
-#define SCSI_Noise__2__DM1 CYREG_PRT4_DM1
-#define SCSI_Noise__2__DM2 CYREG_PRT4_DM2
-#define SCSI_Noise__2__DR CYREG_PRT4_DR
-#define SCSI_Noise__2__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Noise__2__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Noise__2__MASK 0x08u
-#define SCSI_Noise__2__PC CYREG_PRT4_PC3
-#define SCSI_Noise__2__PORT 4u
-#define SCSI_Noise__2__PRT CYREG_PRT4_PRT
-#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Noise__2__PS CYREG_PRT4_PS
-#define SCSI_Noise__2__SHIFT 3
-#define SCSI_Noise__2__SLW CYREG_PRT4_SLW
-#define SCSI_Noise__3__AG CYREG_PRT4_AG
-#define SCSI_Noise__3__AMUX CYREG_PRT4_AMUX
-#define SCSI_Noise__3__BIE CYREG_PRT4_BIE
-#define SCSI_Noise__3__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Noise__3__BYP CYREG_PRT4_BYP
-#define SCSI_Noise__3__CTL CYREG_PRT4_CTL
-#define SCSI_Noise__3__DM0 CYREG_PRT4_DM0
-#define SCSI_Noise__3__DM1 CYREG_PRT4_DM1
-#define SCSI_Noise__3__DM2 CYREG_PRT4_DM2
-#define SCSI_Noise__3__DR CYREG_PRT4_DR
-#define SCSI_Noise__3__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Noise__3__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Noise__3__MASK 0x80u
-#define SCSI_Noise__3__PC CYREG_PRT4_PC7
-#define SCSI_Noise__3__PORT 4u
-#define SCSI_Noise__3__PRT CYREG_PRT4_PRT
-#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Noise__3__PS CYREG_PRT4_PS
-#define SCSI_Noise__3__SHIFT 7
-#define SCSI_Noise__3__SLW CYREG_PRT4_SLW
-#define SCSI_Noise__4__AG CYREG_PRT6_AG
-#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX
-#define SCSI_Noise__4__BIE CYREG_PRT6_BIE
-#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Noise__4__BYP CYREG_PRT6_BYP
-#define SCSI_Noise__4__CTL CYREG_PRT6_CTL
-#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0
-#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1
-#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2
-#define SCSI_Noise__4__DR CYREG_PRT6_DR
-#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Noise__4__MASK 0x04u
-#define SCSI_Noise__4__PC CYREG_PRT6_PC2
-#define SCSI_Noise__4__PORT 6u
-#define SCSI_Noise__4__PRT CYREG_PRT6_PRT
-#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Noise__4__PS CYREG_PRT6_PS
-#define SCSI_Noise__4__SHIFT 2
-#define SCSI_Noise__4__SLW CYREG_PRT6_SLW
-#define SCSI_Noise__ACK__AG CYREG_PRT6_AG
-#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX
-#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE
-#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP
-#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL
-#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0
-#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1
-#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2
-#define SCSI_Noise__ACK__DR CYREG_PRT6_DR
-#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Noise__ACK__MASK 0x04u
-#define SCSI_Noise__ACK__PC CYREG_PRT6_PC2
-#define SCSI_Noise__ACK__PORT 6u
-#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT
-#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Noise__ACK__PS CYREG_PRT6_PS
-#define SCSI_Noise__ACK__SHIFT 2
-#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW
-#define SCSI_Noise__ATN__AG CYREG_PRT2_AG
-#define SCSI_Noise__ATN__AMUX CYREG_PRT2_AMUX
-#define SCSI_Noise__ATN__BIE CYREG_PRT2_BIE
-#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Noise__ATN__BYP CYREG_PRT2_BYP
-#define SCSI_Noise__ATN__CTL CYREG_PRT2_CTL
-#define SCSI_Noise__ATN__DM0 CYREG_PRT2_DM0
-#define SCSI_Noise__ATN__DM1 CYREG_PRT2_DM1
-#define SCSI_Noise__ATN__DM2 CYREG_PRT2_DM2
-#define SCSI_Noise__ATN__DR CYREG_PRT2_DR
-#define SCSI_Noise__ATN__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Noise__ATN__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Noise__ATN__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Noise__ATN__MASK 0x01u
-#define SCSI_Noise__ATN__PC CYREG_PRT2_PC0
-#define SCSI_Noise__ATN__PORT 2u
-#define SCSI_Noise__ATN__PRT CYREG_PRT2_PRT
-#define SCSI_Noise__ATN__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Noise__ATN__PS CYREG_PRT2_PS
-#define SCSI_Noise__ATN__SHIFT 0
-#define SCSI_Noise__ATN__SLW CYREG_PRT2_SLW
-#define SCSI_Noise__BSY__AG CYREG_PRT6_AG
-#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX
-#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE
-#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP
-#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL
-#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0
-#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1
-#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2
-#define SCSI_Noise__BSY__DR CYREG_PRT6_DR
-#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Noise__BSY__MASK 0x08u
-#define SCSI_Noise__BSY__PC CYREG_PRT6_PC3
-#define SCSI_Noise__BSY__PORT 6u
-#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT
-#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Noise__BSY__PS CYREG_PRT6_PS
-#define SCSI_Noise__BSY__SHIFT 3
-#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW
-#define SCSI_Noise__RST__AG CYREG_PRT4_AG
-#define SCSI_Noise__RST__AMUX CYREG_PRT4_AMUX
-#define SCSI_Noise__RST__BIE CYREG_PRT4_BIE
-#define SCSI_Noise__RST__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Noise__RST__BYP CYREG_PRT4_BYP
-#define SCSI_Noise__RST__CTL CYREG_PRT4_CTL
-#define SCSI_Noise__RST__DM0 CYREG_PRT4_DM0
-#define SCSI_Noise__RST__DM1 CYREG_PRT4_DM1
-#define SCSI_Noise__RST__DM2 CYREG_PRT4_DM2
-#define SCSI_Noise__RST__DR CYREG_PRT4_DR
-#define SCSI_Noise__RST__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Noise__RST__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Noise__RST__MASK 0x80u
-#define SCSI_Noise__RST__PC CYREG_PRT4_PC7
-#define SCSI_Noise__RST__PORT 4u
-#define SCSI_Noise__RST__PRT CYREG_PRT4_PRT
-#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Noise__RST__PS CYREG_PRT4_PS
-#define SCSI_Noise__RST__SHIFT 7
-#define SCSI_Noise__RST__SLW CYREG_PRT4_SLW
-#define SCSI_Noise__SEL__AG CYREG_PRT4_AG
-#define SCSI_Noise__SEL__AMUX CYREG_PRT4_AMUX
-#define SCSI_Noise__SEL__BIE CYREG_PRT4_BIE
-#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Noise__SEL__BYP CYREG_PRT4_BYP
-#define SCSI_Noise__SEL__CTL CYREG_PRT4_CTL
-#define SCSI_Noise__SEL__DM0 CYREG_PRT4_DM0
-#define SCSI_Noise__SEL__DM1 CYREG_PRT4_DM1
-#define SCSI_Noise__SEL__DM2 CYREG_PRT4_DM2
-#define SCSI_Noise__SEL__DR CYREG_PRT4_DR
-#define SCSI_Noise__SEL__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Noise__SEL__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Noise__SEL__MASK 0x08u
-#define SCSI_Noise__SEL__PC CYREG_PRT4_PC3
-#define SCSI_Noise__SEL__PORT 4u
-#define SCSI_Noise__SEL__PRT CYREG_PRT4_PRT
-#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Noise__SEL__PS CYREG_PRT4_PS
-#define SCSI_Noise__SEL__SHIFT 3
-#define SCSI_Noise__SEL__SLW CYREG_PRT4_SLW
-
-/* scsiTarget */
-#define scsiTarget_StatusReg__0__MASK 0x01u
-#define scsiTarget_StatusReg__0__POS 0
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
-#define scsiTarget_StatusReg__1__MASK 0x02u
-#define scsiTarget_StatusReg__1__POS 1
-#define scsiTarget_StatusReg__2__MASK 0x04u
-#define scsiTarget_StatusReg__2__POS 2
-#define scsiTarget_StatusReg__3__MASK 0x08u
-#define scsiTarget_StatusReg__3__POS 3
-#define scsiTarget_StatusReg__4__MASK 0x10u
-#define scsiTarget_StatusReg__4__POS 4
-#define scsiTarget_StatusReg__MASK 0x1Fu
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB03_MSK
-#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
-#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
-#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL
-#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB03_ST
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB12_MSK
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB12_ST_CTL
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB12_ST_CTL
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB12_ST
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB12_CTL
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB12_CTL
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB12_MSK
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB12_13_A0
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB12_13_A1
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB12_13_D0
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB12_13_D1
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB12_13_F0
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB12_13_F1
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB12_A0_A1
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB12_A0
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB12_A1
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB12_D0_D1
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB12_D0
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB12_D1
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB12_ACTL
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB12_F0_F1
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB12_F0
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB12_F1
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-
-/* USBFS_ep_0 */
-#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_0__INTC_MASK 0x1000000u
-#define USBFS_ep_0__INTC_NUMBER 24u
-#define USBFS_ep_0__INTC_PRIOR_NUM 7u
-#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24
-#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_1 */
-#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_1__INTC_MASK 0x40u
-#define USBFS_ep_1__INTC_NUMBER 6u
-#define USBFS_ep_1__INTC_PRIOR_NUM 7u
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_6
-#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_2 */
-#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_2__INTC_MASK 0x80u
-#define USBFS_ep_2__INTC_NUMBER 7u
-#define USBFS_ep_2__INTC_PRIOR_NUM 7u
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_7
-#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_3 */
-#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_3__INTC_MASK 0x100u
-#define USBFS_ep_3__INTC_NUMBER 8u
-#define USBFS_ep_3__INTC_PRIOR_NUM 7u
-#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_8
-#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_4 */
-#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_4__INTC_MASK 0x200u
-#define USBFS_ep_4__INTC_NUMBER 9u
-#define USBFS_ep_4__INTC_PRIOR_NUM 7u
-#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_9
-#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SD_RX_DMA */
-#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SD_RX_DMA__DRQ_NUMBER 2u
-#define SD_RX_DMA__NUMBEROF_TDS 0u
-#define SD_RX_DMA__PRIORITY 2u
-#define SD_RX_DMA__TERMIN_EN 0u
-#define SD_RX_DMA__TERMIN_SEL 0u
-#define SD_RX_DMA__TERMOUT0_EN 1u
-#define SD_RX_DMA__TERMOUT0_SEL 2u
-#define SD_RX_DMA__TERMOUT1_EN 0u
-#define SD_RX_DMA__TERMOUT1_SEL 0u
-
-/* SD_TX_DMA */
-#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
-#define SD_TX_DMA__DRQ_NUMBER 3u
-#define SD_TX_DMA__NUMBEROF_TDS 0u
-#define SD_TX_DMA__PRIORITY 2u
-#define SD_TX_DMA__TERMIN_EN 0u
-#define SD_TX_DMA__TERMIN_SEL 0u
-#define SD_TX_DMA__TERMOUT0_EN 1u
-#define SD_TX_DMA__TERMOUT0_SEL 3u
-#define SD_TX_DMA__TERMOUT1_EN 0u
-#define SD_TX_DMA__TERMOUT1_SEL 0u
-
-/* USBFS_USB */
-#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG
-#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG
-#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN
-#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR
-#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG
-#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN
-#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR
-#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG
-#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN
-#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR
-#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG
-#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN
-#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR
-#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG
-#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN
-#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR
-#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG
-#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN
-#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR
-#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG
-#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN
-#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR
-#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG
-#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN
-#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR
-#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN
-#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR
-#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR
-#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA
-#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB
-#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA
-#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB
-#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR
-#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA
-#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB
-#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA
-#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB
-#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR
-#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA
-#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB
-#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA
-#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB
-#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR
-#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA
-#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB
-#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA
-#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB
-#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR
-#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA
-#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB
-#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA
-#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB
-#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR
-#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA
-#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB
-#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA
-#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB
-#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR
-#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA
-#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB
-#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA
-#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB
-#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR
-#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA
-#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB
-#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA
-#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB
-#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE
-#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT
-#define USBFS_USB__CR0 CYREG_USB_CR0
-#define USBFS_USB__CR1 CYREG_USB_CR1
-#define USBFS_USB__CWA CYREG_USB_CWA
-#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB
-#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES
-#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB
-#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG
-#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT
-#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR
-#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0
-#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1
-#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2
-#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3
-#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4
-#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5
-#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6
-#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7
-#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
-#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE
-#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE
-#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5
-#define USBFS_USB__PM_ACT_MSK 0x01u
-#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5
-#define USBFS_USB__PM_STBY_MSK 0x01u
-#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0
-#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1
-#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0
-#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0
-#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1
-#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0
-#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0
-#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1
-#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0
-#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0
-#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1
-#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0
-#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0
-#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1
-#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0
-#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0
-#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1
-#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0
-#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0
-#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1
-#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0
-#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0
-#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1
-#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0
-#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
-#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
-#define USBFS_USB__SOF0 CYREG_USB_SOF0
-#define USBFS_USB__SOF1 CYREG_USB_SOF1
-#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0
-#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
-#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
-
-/* SCSI_CLK */
-#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0
-#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1
-#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2
-#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u
-#define SCSI_CLK__INDEX 0x01u
-#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2
-#define SCSI_CLK__PM_ACT_MSK 0x02u
-#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2
-#define SCSI_CLK__PM_STBY_MSK 0x02u
-
-/* SCSI_Out */
-#define SCSI_Out__0__AG CYREG_PRT15_AG
-#define SCSI_Out__0__AMUX CYREG_PRT15_AMUX
-#define SCSI_Out__0__BIE CYREG_PRT15_BIE
-#define SCSI_Out__0__BIT_MASK CYREG_PRT15_BIT_MASK
-#define SCSI_Out__0__BYP CYREG_PRT15_BYP
-#define SCSI_Out__0__CTL CYREG_PRT15_CTL
-#define SCSI_Out__0__DM0 CYREG_PRT15_DM0
-#define SCSI_Out__0__DM1 CYREG_PRT15_DM1
-#define SCSI_Out__0__DM2 CYREG_PRT15_DM2
-#define SCSI_Out__0__DR CYREG_PRT15_DR
-#define SCSI_Out__0__INP_DIS CYREG_PRT15_INP_DIS
-#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define SCSI_Out__0__LCD_EN CYREG_PRT15_LCD_EN
-#define SCSI_Out__0__MASK 0x20u
-#define SCSI_Out__0__PC CYREG_IO_PC_PRT15_PC5
-#define SCSI_Out__0__PORT 15u
-#define SCSI_Out__0__PRT CYREG_PRT15_PRT
-#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define SCSI_Out__0__PS CYREG_PRT15_PS
-#define SCSI_Out__0__SHIFT 5
-#define SCSI_Out__0__SLW CYREG_PRT15_SLW
-#define SCSI_Out__1__AG CYREG_PRT15_AG
-#define SCSI_Out__1__AMUX CYREG_PRT15_AMUX
-#define SCSI_Out__1__BIE CYREG_PRT15_BIE
-#define SCSI_Out__1__BIT_MASK CYREG_PRT15_BIT_MASK
-#define SCSI_Out__1__BYP CYREG_PRT15_BYP
-#define SCSI_Out__1__CTL CYREG_PRT15_CTL
-#define SCSI_Out__1__DM0 CYREG_PRT15_DM0
-#define SCSI_Out__1__DM1 CYREG_PRT15_DM1
-#define SCSI_Out__1__DM2 CYREG_PRT15_DM2
-#define SCSI_Out__1__DR CYREG_PRT15_DR
-#define SCSI_Out__1__INP_DIS CYREG_PRT15_INP_DIS
-#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define SCSI_Out__1__LCD_EN CYREG_PRT15_LCD_EN
-#define SCSI_Out__1__MASK 0x10u
-#define SCSI_Out__1__PC CYREG_IO_PC_PRT15_PC4
-#define SCSI_Out__1__PORT 15u
-#define SCSI_Out__1__PRT CYREG_PRT15_PRT
-#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define SCSI_Out__1__PS CYREG_PRT15_PS
-#define SCSI_Out__1__SHIFT 4
-#define SCSI_Out__1__SLW CYREG_PRT15_SLW
-#define SCSI_Out__2__AG CYREG_PRT6_AG
-#define SCSI_Out__2__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out__2__BIE CYREG_PRT6_BIE
-#define SCSI_Out__2__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out__2__BYP CYREG_PRT6_BYP
-#define SCSI_Out__2__CTL CYREG_PRT6_CTL
-#define SCSI_Out__2__DM0 CYREG_PRT6_DM0
-#define SCSI_Out__2__DM1 CYREG_PRT6_DM1
-#define SCSI_Out__2__DM2 CYREG_PRT6_DM2
-#define SCSI_Out__2__DR CYREG_PRT6_DR
-#define SCSI_Out__2__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out__2__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out__2__MASK 0x02u
-#define SCSI_Out__2__PC CYREG_PRT6_PC1
-#define SCSI_Out__2__PORT 6u
-#define SCSI_Out__2__PRT CYREG_PRT6_PRT
-#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out__2__PS CYREG_PRT6_PS
-#define SCSI_Out__2__SHIFT 1
-#define SCSI_Out__2__SLW CYREG_PRT6_SLW
-#define SCSI_Out__3__AG CYREG_PRT6_AG
-#define SCSI_Out__3__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out__3__BIE CYREG_PRT6_BIE
-#define SCSI_Out__3__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out__3__BYP CYREG_PRT6_BYP
-#define SCSI_Out__3__CTL CYREG_PRT6_CTL
-#define SCSI_Out__3__DM0 CYREG_PRT6_DM0
-#define SCSI_Out__3__DM1 CYREG_PRT6_DM1
-#define SCSI_Out__3__DM2 CYREG_PRT6_DM2
-#define SCSI_Out__3__DR CYREG_PRT6_DR
-#define SCSI_Out__3__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out__3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out__3__MASK 0x01u
-#define SCSI_Out__3__PC CYREG_PRT6_PC0
-#define SCSI_Out__3__PORT 6u
-#define SCSI_Out__3__PRT CYREG_PRT6_PRT
-#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out__3__PS CYREG_PRT6_PS
-#define SCSI_Out__3__SHIFT 0
-#define SCSI_Out__3__SLW CYREG_PRT6_SLW
-#define SCSI_Out__4__AG CYREG_PRT4_AG
-#define SCSI_Out__4__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out__4__BIE CYREG_PRT4_BIE
-#define SCSI_Out__4__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out__4__BYP CYREG_PRT4_BYP
-#define SCSI_Out__4__CTL CYREG_PRT4_CTL
-#define SCSI_Out__4__DM0 CYREG_PRT4_DM0
-#define SCSI_Out__4__DM1 CYREG_PRT4_DM1
-#define SCSI_Out__4__DM2 CYREG_PRT4_DM2
-#define SCSI_Out__4__DR CYREG_PRT4_DR
-#define SCSI_Out__4__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out__4__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out__4__MASK 0x20u
-#define SCSI_Out__4__PC CYREG_PRT4_PC5
-#define SCSI_Out__4__PORT 4u
-#define SCSI_Out__4__PRT CYREG_PRT4_PRT
-#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out__4__PS CYREG_PRT4_PS
-#define SCSI_Out__4__SHIFT 5
-#define SCSI_Out__4__SLW CYREG_PRT4_SLW
-#define SCSI_Out__5__AG CYREG_PRT4_AG
-#define SCSI_Out__5__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out__5__BIE CYREG_PRT4_BIE
-#define SCSI_Out__5__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out__5__BYP CYREG_PRT4_BYP
-#define SCSI_Out__5__CTL CYREG_PRT4_CTL
-#define SCSI_Out__5__DM0 CYREG_PRT4_DM0
-#define SCSI_Out__5__DM1 CYREG_PRT4_DM1
-#define SCSI_Out__5__DM2 CYREG_PRT4_DM2
-#define SCSI_Out__5__DR CYREG_PRT4_DR
-#define SCSI_Out__5__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out__5__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out__5__MASK 0x10u
-#define SCSI_Out__5__PC CYREG_PRT4_PC4
-#define SCSI_Out__5__PORT 4u
-#define SCSI_Out__5__PRT CYREG_PRT4_PRT
-#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out__5__PS CYREG_PRT4_PS
-#define SCSI_Out__5__SHIFT 4
-#define SCSI_Out__5__SLW CYREG_PRT4_SLW
-#define SCSI_Out__6__AG CYREG_PRT0_AG
-#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__6__BIE CYREG_PRT0_BIE
-#define SCSI_Out__6__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__6__BYP CYREG_PRT0_BYP
-#define SCSI_Out__6__CTL CYREG_PRT0_CTL
-#define SCSI_Out__6__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__6__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__6__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__6__DR CYREG_PRT0_DR
-#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__6__MASK 0x80u
-#define SCSI_Out__6__PC CYREG_PRT0_PC7
-#define SCSI_Out__6__PORT 0u
-#define SCSI_Out__6__PRT CYREG_PRT0_PRT
-#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__6__PS CYREG_PRT0_PS
-#define SCSI_Out__6__SHIFT 7
-#define SCSI_Out__6__SLW CYREG_PRT0_SLW
-#define SCSI_Out__7__AG CYREG_PRT0_AG
-#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__7__BIE CYREG_PRT0_BIE
-#define SCSI_Out__7__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__7__BYP CYREG_PRT0_BYP
-#define SCSI_Out__7__CTL CYREG_PRT0_CTL
-#define SCSI_Out__7__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__7__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__7__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__7__DR CYREG_PRT0_DR
-#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__7__MASK 0x40u
-#define SCSI_Out__7__PC CYREG_PRT0_PC6
-#define SCSI_Out__7__PORT 0u
-#define SCSI_Out__7__PRT CYREG_PRT0_PRT
-#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__7__PS CYREG_PRT0_PS
-#define SCSI_Out__7__SHIFT 6
-#define SCSI_Out__7__SLW CYREG_PRT0_SLW
-#define SCSI_Out__8__AG CYREG_PRT0_AG
-#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__8__BIE CYREG_PRT0_BIE
-#define SCSI_Out__8__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__8__BYP CYREG_PRT0_BYP
-#define SCSI_Out__8__CTL CYREG_PRT0_CTL
-#define SCSI_Out__8__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__8__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__8__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__8__DR CYREG_PRT0_DR
-#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__8__MASK 0x08u
-#define SCSI_Out__8__PC CYREG_PRT0_PC3
-#define SCSI_Out__8__PORT 0u
-#define SCSI_Out__8__PRT CYREG_PRT0_PRT
-#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__8__PS CYREG_PRT0_PS
-#define SCSI_Out__8__SHIFT 3
-#define SCSI_Out__8__SLW CYREG_PRT0_SLW
-#define SCSI_Out__9__AG CYREG_PRT0_AG
-#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__9__BIE CYREG_PRT0_BIE
-#define SCSI_Out__9__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__9__BYP CYREG_PRT0_BYP
-#define SCSI_Out__9__CTL CYREG_PRT0_CTL
-#define SCSI_Out__9__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__9__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__9__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__9__DR CYREG_PRT0_DR
-#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__9__MASK 0x04u
-#define SCSI_Out__9__PC CYREG_PRT0_PC2
-#define SCSI_Out__9__PORT 0u
-#define SCSI_Out__9__PRT CYREG_PRT0_PRT
-#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__9__PS CYREG_PRT0_PS
-#define SCSI_Out__9__SHIFT 2
-#define SCSI_Out__9__SLW CYREG_PRT0_SLW
-#define SCSI_Out__ACK__AG CYREG_PRT6_AG
-#define SCSI_Out__ACK__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out__ACK__BIE CYREG_PRT6_BIE
-#define SCSI_Out__ACK__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out__ACK__BYP CYREG_PRT6_BYP
-#define SCSI_Out__ACK__CTL CYREG_PRT6_CTL
-#define SCSI_Out__ACK__DM0 CYREG_PRT6_DM0
-#define SCSI_Out__ACK__DM1 CYREG_PRT6_DM1
-#define SCSI_Out__ACK__DM2 CYREG_PRT6_DM2
-#define SCSI_Out__ACK__DR CYREG_PRT6_DR
-#define SCSI_Out__ACK__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out__ACK__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out__ACK__MASK 0x01u
-#define SCSI_Out__ACK__PC CYREG_PRT6_PC0
-#define SCSI_Out__ACK__PORT 6u
-#define SCSI_Out__ACK__PRT CYREG_PRT6_PRT
-#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out__ACK__PS CYREG_PRT6_PS
-#define SCSI_Out__ACK__SHIFT 0
-#define SCSI_Out__ACK__SLW CYREG_PRT6_SLW
-#define SCSI_Out__ATN__AG CYREG_PRT15_AG
-#define SCSI_Out__ATN__AMUX CYREG_PRT15_AMUX
-#define SCSI_Out__ATN__BIE CYREG_PRT15_BIE
-#define SCSI_Out__ATN__BIT_MASK CYREG_PRT15_BIT_MASK
-#define SCSI_Out__ATN__BYP CYREG_PRT15_BYP
-#define SCSI_Out__ATN__CTL CYREG_PRT15_CTL
-#define SCSI_Out__ATN__DM0 CYREG_PRT15_DM0
-#define SCSI_Out__ATN__DM1 CYREG_PRT15_DM1
-#define SCSI_Out__ATN__DM2 CYREG_PRT15_DM2
-#define SCSI_Out__ATN__DR CYREG_PRT15_DR
-#define SCSI_Out__ATN__INP_DIS CYREG_PRT15_INP_DIS
-#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define SCSI_Out__ATN__LCD_EN CYREG_PRT15_LCD_EN
-#define SCSI_Out__ATN__MASK 0x10u
-#define SCSI_Out__ATN__PC CYREG_IO_PC_PRT15_PC4
-#define SCSI_Out__ATN__PORT 15u
-#define SCSI_Out__ATN__PRT CYREG_PRT15_PRT
-#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define SCSI_Out__ATN__PS CYREG_PRT15_PS
-#define SCSI_Out__ATN__SHIFT 4
-#define SCSI_Out__ATN__SLW CYREG_PRT15_SLW
-#define SCSI_Out__BSY__AG CYREG_PRT6_AG
-#define SCSI_Out__BSY__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out__BSY__BIE CYREG_PRT6_BIE
-#define SCSI_Out__BSY__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out__BSY__BYP CYREG_PRT6_BYP
-#define SCSI_Out__BSY__CTL CYREG_PRT6_CTL
-#define SCSI_Out__BSY__DM0 CYREG_PRT6_DM0
-#define SCSI_Out__BSY__DM1 CYREG_PRT6_DM1
-#define SCSI_Out__BSY__DM2 CYREG_PRT6_DM2
-#define SCSI_Out__BSY__DR CYREG_PRT6_DR
-#define SCSI_Out__BSY__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out__BSY__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out__BSY__MASK 0x02u
-#define SCSI_Out__BSY__PC CYREG_PRT6_PC1
-#define SCSI_Out__BSY__PORT 6u
-#define SCSI_Out__BSY__PRT CYREG_PRT6_PRT
-#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out__BSY__PS CYREG_PRT6_PS
-#define SCSI_Out__BSY__SHIFT 1
-#define SCSI_Out__BSY__SLW CYREG_PRT6_SLW
-#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG
-#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE
-#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP
-#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL
-#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR
-#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__CD_raw__MASK 0x40u
-#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC6
-#define SCSI_Out__CD_raw__PORT 0u
-#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT
-#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS
-#define SCSI_Out__CD_raw__SHIFT 6
-#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW
-#define SCSI_Out__DBP_raw__AG CYREG_PRT15_AG
-#define SCSI_Out__DBP_raw__AMUX CYREG_PRT15_AMUX
-#define SCSI_Out__DBP_raw__BIE CYREG_PRT15_BIE
-#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT15_BIT_MASK
-#define SCSI_Out__DBP_raw__BYP CYREG_PRT15_BYP
-#define SCSI_Out__DBP_raw__CTL CYREG_PRT15_CTL
-#define SCSI_Out__DBP_raw__DM0 CYREG_PRT15_DM0
-#define SCSI_Out__DBP_raw__DM1 CYREG_PRT15_DM1
-#define SCSI_Out__DBP_raw__DM2 CYREG_PRT15_DM2
-#define SCSI_Out__DBP_raw__DR CYREG_PRT15_DR
-#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT15_INP_DIS
-#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT15_LCD_EN
-#define SCSI_Out__DBP_raw__MASK 0x20u
-#define SCSI_Out__DBP_raw__PC CYREG_IO_PC_PRT15_PC5
-#define SCSI_Out__DBP_raw__PORT 15u
-#define SCSI_Out__DBP_raw__PRT CYREG_PRT15_PRT
-#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define SCSI_Out__DBP_raw__PS CYREG_PRT15_PS
-#define SCSI_Out__DBP_raw__SHIFT 5
-#define SCSI_Out__DBP_raw__SLW CYREG_PRT15_SLW
-#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG
-#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__IO_raw__BIE CYREG_PRT0_BIE
-#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__IO_raw__BYP CYREG_PRT0_BYP
-#define SCSI_Out__IO_raw__CTL CYREG_PRT0_CTL
-#define SCSI_Out__IO_raw__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__IO_raw__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR
-#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__IO_raw__MASK 0x04u
-#define SCSI_Out__IO_raw__PC CYREG_PRT0_PC2
-#define SCSI_Out__IO_raw__PORT 0u
-#define SCSI_Out__IO_raw__PRT CYREG_PRT0_PRT
-#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS
-#define SCSI_Out__IO_raw__SHIFT 2
-#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW
-#define SCSI_Out__MSG_raw__AG CYREG_PRT4_AG
-#define SCSI_Out__MSG_raw__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out__MSG_raw__BIE CYREG_PRT4_BIE
-#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out__MSG_raw__BYP CYREG_PRT4_BYP
-#define SCSI_Out__MSG_raw__CTL CYREG_PRT4_CTL
-#define SCSI_Out__MSG_raw__DM0 CYREG_PRT4_DM0
-#define SCSI_Out__MSG_raw__DM1 CYREG_PRT4_DM1
-#define SCSI_Out__MSG_raw__DM2 CYREG_PRT4_DM2
-#define SCSI_Out__MSG_raw__DR CYREG_PRT4_DR
-#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out__MSG_raw__MASK 0x10u
-#define SCSI_Out__MSG_raw__PC CYREG_PRT4_PC4
-#define SCSI_Out__MSG_raw__PORT 4u
-#define SCSI_Out__MSG_raw__PRT CYREG_PRT4_PRT
-#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out__MSG_raw__PS CYREG_PRT4_PS
-#define SCSI_Out__MSG_raw__SHIFT 4
-#define SCSI_Out__MSG_raw__SLW CYREG_PRT4_SLW
-#define SCSI_Out__REQ__AG CYREG_PRT0_AG
-#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE
-#define SCSI_Out__REQ__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__REQ__BYP CYREG_PRT0_BYP
-#define SCSI_Out__REQ__CTL CYREG_PRT0_CTL
-#define SCSI_Out__REQ__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__REQ__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__REQ__DR CYREG_PRT0_DR
-#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__REQ__MASK 0x08u
-#define SCSI_Out__REQ__PC CYREG_PRT0_PC3
-#define SCSI_Out__REQ__PORT 0u
-#define SCSI_Out__REQ__PRT CYREG_PRT0_PRT
-#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__REQ__PS CYREG_PRT0_PS
-#define SCSI_Out__REQ__SHIFT 3
-#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW
-#define SCSI_Out__RST__AG CYREG_PRT4_AG
-#define SCSI_Out__RST__AMUX CYREG_PRT4_AMUX
-#define SCSI_Out__RST__BIE CYREG_PRT4_BIE
-#define SCSI_Out__RST__BIT_MASK CYREG_PRT4_BIT_MASK
-#define SCSI_Out__RST__BYP CYREG_PRT4_BYP
-#define SCSI_Out__RST__CTL CYREG_PRT4_CTL
-#define SCSI_Out__RST__DM0 CYREG_PRT4_DM0
-#define SCSI_Out__RST__DM1 CYREG_PRT4_DM1
-#define SCSI_Out__RST__DM2 CYREG_PRT4_DM2
-#define SCSI_Out__RST__DR CYREG_PRT4_DR
-#define SCSI_Out__RST__INP_DIS CYREG_PRT4_INP_DIS
-#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
-#define SCSI_Out__RST__LCD_EN CYREG_PRT4_LCD_EN
-#define SCSI_Out__RST__MASK 0x20u
-#define SCSI_Out__RST__PC CYREG_PRT4_PC5
-#define SCSI_Out__RST__PORT 4u
-#define SCSI_Out__RST__PRT CYREG_PRT4_PRT
-#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
-#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
-#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
-#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
-#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
-#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
-#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
-#define SCSI_Out__RST__PS CYREG_PRT4_PS
-#define SCSI_Out__RST__SHIFT 5
-#define SCSI_Out__RST__SLW CYREG_PRT4_SLW
-#define SCSI_Out__SEL__AG CYREG_PRT0_AG
-#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX
-#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE
-#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK
-#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP
-#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL
-#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0
-#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1
-#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2
-#define SCSI_Out__SEL__DR CYREG_PRT0_DR
-#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS
-#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN
-#define SCSI_Out__SEL__MASK 0x80u
-#define SCSI_Out__SEL__PC CYREG_PRT0_PC7
-#define SCSI_Out__SEL__PORT 0u
-#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT
-#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define SCSI_Out__SEL__PS CYREG_PRT0_PS
-#define SCSI_Out__SEL__SHIFT 7
-#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW
+/* EXTLED */
+#define EXTLED__0__MASK 0x01u
+#define EXTLED__0__PC CYREG_PRT0_PC0
+#define EXTLED__0__PORT 0u
+#define EXTLED__0__SHIFT 0
+#define EXTLED__AG CYREG_PRT0_AG
+#define EXTLED__AMUX CYREG_PRT0_AMUX
+#define EXTLED__BIE CYREG_PRT0_BIE
+#define EXTLED__BIT_MASK CYREG_PRT0_BIT_MASK
+#define EXTLED__BYP CYREG_PRT0_BYP
+#define EXTLED__CTL CYREG_PRT0_CTL
+#define EXTLED__DM0 CYREG_PRT0_DM0
+#define EXTLED__DM1 CYREG_PRT0_DM1
+#define EXTLED__DM2 CYREG_PRT0_DM2
+#define EXTLED__DR CYREG_PRT0_DR
+#define EXTLED__INP_DIS CYREG_PRT0_INP_DIS
+#define EXTLED__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define EXTLED__LCD_EN CYREG_PRT0_LCD_EN
+#define EXTLED__MASK 0x01u
+#define EXTLED__PORT 0u
+#define EXTLED__PRT CYREG_PRT0_PRT
+#define EXTLED__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define EXTLED__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define EXTLED__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define EXTLED__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define EXTLED__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define EXTLED__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define EXTLED__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define EXTLED__PS CYREG_PRT0_PS
+#define EXTLED__SHIFT 0
+#define EXTLED__SLW CYREG_PRT0_SLW
-/* USBFS_Dm */
-#define USBFS_Dm__0__MASK 0x80u
-#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
-#define USBFS_Dm__0__PORT 15u
-#define USBFS_Dm__0__SHIFT 7
-#define USBFS_Dm__AG CYREG_PRT15_AG
-#define USBFS_Dm__AMUX CYREG_PRT15_AMUX
-#define USBFS_Dm__BIE CYREG_PRT15_BIE
-#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK
-#define USBFS_Dm__BYP CYREG_PRT15_BYP
-#define USBFS_Dm__CTL CYREG_PRT15_CTL
-#define USBFS_Dm__DM0 CYREG_PRT15_DM0
-#define USBFS_Dm__DM1 CYREG_PRT15_DM1
-#define USBFS_Dm__DM2 CYREG_PRT15_DM2
-#define USBFS_Dm__DR CYREG_PRT15_DR
-#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS
-#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN
-#define USBFS_Dm__MASK 0x80u
-#define USBFS_Dm__PORT 15u
-#define USBFS_Dm__PRT CYREG_PRT15_PRT
-#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define USBFS_Dm__PS CYREG_PRT15_PS
-#define USBFS_Dm__SHIFT 7
-#define USBFS_Dm__SLW CYREG_PRT15_SLW
+/* SDCard_BSPIM */
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB10_11_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB10_11_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB10_11_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB10_11_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB10_11_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB10_11_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB10_11_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB10_11_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB10_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB10_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB10_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB10_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB10_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB10_MSK
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB10_11_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB10_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB10_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB10_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB10_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB10_ST
+#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
+#define SDCard_BSPIM_RxStsReg__4__POS 4
+#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
+#define SDCard_BSPIM_RxStsReg__5__POS 5
+#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
+#define SDCard_BSPIM_RxStsReg__6__POS 6
+#define SDCard_BSPIM_RxStsReg__MASK 0x70u
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB11_MSK
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB11_ST
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB08_09_A0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB08_09_A1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB08_09_D0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB08_09_D1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB08_09_F0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB08_09_F1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB08_A0_A1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB08_A0
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB08_A1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB08_D0_D1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB08_D0
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB08_D1
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB08_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB08_F0_F1
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB08_F0
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB08_F1
+#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
+#define SDCard_BSPIM_TxStsReg__0__POS 0
+#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
+#define SDCard_BSPIM_TxStsReg__1__POS 1
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
+#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
+#define SDCard_BSPIM_TxStsReg__2__POS 2
+#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
+#define SDCard_BSPIM_TxStsReg__3__POS 3
+#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
+#define SDCard_BSPIM_TxStsReg__4__POS 4
+#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB08_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB08_ST
-/* USBFS_Dp */
-#define USBFS_Dp__0__MASK 0x40u
-#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
-#define USBFS_Dp__0__PORT 15u
-#define USBFS_Dp__0__SHIFT 6
-#define USBFS_Dp__AG CYREG_PRT15_AG
-#define USBFS_Dp__AMUX CYREG_PRT15_AMUX
-#define USBFS_Dp__BIE CYREG_PRT15_BIE
-#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK
-#define USBFS_Dp__BYP CYREG_PRT15_BYP
-#define USBFS_Dp__CTL CYREG_PRT15_CTL
-#define USBFS_Dp__DM0 CYREG_PRT15_DM0
-#define USBFS_Dp__DM1 CYREG_PRT15_DM1
-#define USBFS_Dp__DM2 CYREG_PRT15_DM2
-#define USBFS_Dp__DR CYREG_PRT15_DR
-#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS
-#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT
-#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN
-#define USBFS_Dp__MASK 0x40u
-#define USBFS_Dp__PORT 15u
-#define USBFS_Dp__PRT CYREG_PRT15_PRT
-#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define USBFS_Dp__PS CYREG_PRT15_PS
-#define USBFS_Dp__SHIFT 6
-#define USBFS_Dp__SLW CYREG_PRT15_SLW
-#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15
+/* SD_SCK */
+#define SD_SCK__0__MASK 0x04u
+#define SD_SCK__0__PC CYREG_PRT3_PC2
+#define SD_SCK__0__PORT 3u
+#define SD_SCK__0__SHIFT 2
+#define SD_SCK__AG CYREG_PRT3_AG
+#define SD_SCK__AMUX CYREG_PRT3_AMUX
+#define SD_SCK__BIE CYREG_PRT3_BIE
+#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_SCK__BYP CYREG_PRT3_BYP
+#define SD_SCK__CTL CYREG_PRT3_CTL
+#define SD_SCK__DM0 CYREG_PRT3_DM0
+#define SD_SCK__DM1 CYREG_PRT3_DM1
+#define SD_SCK__DM2 CYREG_PRT3_DM2
+#define SD_SCK__DR CYREG_PRT3_DR
+#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_SCK__MASK 0x04u
+#define SD_SCK__PORT 3u
+#define SD_SCK__PRT CYREG_PRT3_PRT
+#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_SCK__PS CYREG_PRT3_PS
+#define SD_SCK__SHIFT 2
+#define SD_SCK__SLW CYREG_PRT3_SLW
/* SCSI_In */
#define SCSI_In__0__AG CYREG_PRT2_AG
#define SCSI_In__REQ__SHIFT 5
#define SCSI_In__REQ__SLW CYREG_PRT0_SLW
-/* SD_MISO */
-#define SD_MISO__0__MASK 0x02u
-#define SD_MISO__0__PC CYREG_PRT3_PC1
-#define SD_MISO__0__PORT 3u
-#define SD_MISO__0__SHIFT 1
-#define SD_MISO__AG CYREG_PRT3_AG
-#define SD_MISO__AMUX CYREG_PRT3_AMUX
-#define SD_MISO__BIE CYREG_PRT3_BIE
-#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_MISO__BYP CYREG_PRT3_BYP
-#define SD_MISO__CTL CYREG_PRT3_CTL
-#define SD_MISO__DM0 CYREG_PRT3_DM0
-#define SD_MISO__DM1 CYREG_PRT3_DM1
-#define SD_MISO__DM2 CYREG_PRT3_DM2
-#define SD_MISO__DR CYREG_PRT3_DR
-#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_MISO__MASK 0x02u
-#define SD_MISO__PORT 3u
-#define SD_MISO__PRT CYREG_PRT3_PRT
-#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_MISO__PS CYREG_PRT3_PS
-#define SD_MISO__SHIFT 1
-#define SD_MISO__SLW CYREG_PRT3_SLW
+/* SCSI_In_DBx */
+#define SCSI_In_DBx__0__AG CYREG_PRT5_AG
+#define SCSI_In_DBx__0__AMUX CYREG_PRT5_AMUX
+#define SCSI_In_DBx__0__BIE CYREG_PRT5_BIE
+#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_In_DBx__0__BYP CYREG_PRT5_BYP
+#define SCSI_In_DBx__0__CTL CYREG_PRT5_CTL
+#define SCSI_In_DBx__0__DM0 CYREG_PRT5_DM0
+#define SCSI_In_DBx__0__DM1 CYREG_PRT5_DM1
+#define SCSI_In_DBx__0__DM2 CYREG_PRT5_DM2
+#define SCSI_In_DBx__0__DR CYREG_PRT5_DR
+#define SCSI_In_DBx__0__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_In_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_In_DBx__0__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_In_DBx__0__MASK 0x08u
+#define SCSI_In_DBx__0__PC CYREG_PRT5_PC3
+#define SCSI_In_DBx__0__PORT 5u
+#define SCSI_In_DBx__0__PRT CYREG_PRT5_PRT
+#define SCSI_In_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_In_DBx__0__PS CYREG_PRT5_PS
+#define SCSI_In_DBx__0__SHIFT 3
+#define SCSI_In_DBx__0__SLW CYREG_PRT5_SLW
+#define SCSI_In_DBx__1__AG CYREG_PRT5_AG
+#define SCSI_In_DBx__1__AMUX CYREG_PRT5_AMUX
+#define SCSI_In_DBx__1__BIE CYREG_PRT5_BIE
+#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_In_DBx__1__BYP CYREG_PRT5_BYP
+#define SCSI_In_DBx__1__CTL CYREG_PRT5_CTL
+#define SCSI_In_DBx__1__DM0 CYREG_PRT5_DM0
+#define SCSI_In_DBx__1__DM1 CYREG_PRT5_DM1
+#define SCSI_In_DBx__1__DM2 CYREG_PRT5_DM2
+#define SCSI_In_DBx__1__DR CYREG_PRT5_DR
+#define SCSI_In_DBx__1__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_In_DBx__1__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_In_DBx__1__MASK 0x04u
+#define SCSI_In_DBx__1__PC CYREG_PRT5_PC2
+#define SCSI_In_DBx__1__PORT 5u
+#define SCSI_In_DBx__1__PRT CYREG_PRT5_PRT
+#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_In_DBx__1__PS CYREG_PRT5_PS
+#define SCSI_In_DBx__1__SHIFT 2
+#define SCSI_In_DBx__1__SLW CYREG_PRT5_SLW
+#define SCSI_In_DBx__2__AG CYREG_PRT6_AG
+#define SCSI_In_DBx__2__AMUX CYREG_PRT6_AMUX
+#define SCSI_In_DBx__2__BIE CYREG_PRT6_BIE
+#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_In_DBx__2__BYP CYREG_PRT6_BYP
+#define SCSI_In_DBx__2__CTL CYREG_PRT6_CTL
+#define SCSI_In_DBx__2__DM0 CYREG_PRT6_DM0
+#define SCSI_In_DBx__2__DM1 CYREG_PRT6_DM1
+#define SCSI_In_DBx__2__DM2 CYREG_PRT6_DM2
+#define SCSI_In_DBx__2__DR CYREG_PRT6_DR
+#define SCSI_In_DBx__2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_In_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_In_DBx__2__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_In_DBx__2__MASK 0x80u
+#define SCSI_In_DBx__2__PC CYREG_PRT6_PC7
+#define SCSI_In_DBx__2__PORT 6u
+#define SCSI_In_DBx__2__PRT CYREG_PRT6_PRT
+#define SCSI_In_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_In_DBx__2__PS CYREG_PRT6_PS
+#define SCSI_In_DBx__2__SHIFT 7
+#define SCSI_In_DBx__2__SLW CYREG_PRT6_SLW
+#define SCSI_In_DBx__3__AG CYREG_PRT6_AG
+#define SCSI_In_DBx__3__AMUX CYREG_PRT6_AMUX
+#define SCSI_In_DBx__3__BIE CYREG_PRT6_BIE
+#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_In_DBx__3__BYP CYREG_PRT6_BYP
+#define SCSI_In_DBx__3__CTL CYREG_PRT6_CTL
+#define SCSI_In_DBx__3__DM0 CYREG_PRT6_DM0
+#define SCSI_In_DBx__3__DM1 CYREG_PRT6_DM1
+#define SCSI_In_DBx__3__DM2 CYREG_PRT6_DM2
+#define SCSI_In_DBx__3__DR CYREG_PRT6_DR
+#define SCSI_In_DBx__3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_In_DBx__3__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_In_DBx__3__MASK 0x40u
+#define SCSI_In_DBx__3__PC CYREG_PRT6_PC6
+#define SCSI_In_DBx__3__PORT 6u
+#define SCSI_In_DBx__3__PRT CYREG_PRT6_PRT
+#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_In_DBx__3__PS CYREG_PRT6_PS
+#define SCSI_In_DBx__3__SHIFT 6
+#define SCSI_In_DBx__3__SLW CYREG_PRT6_SLW
+#define SCSI_In_DBx__4__AG CYREG_PRT12_AG
+#define SCSI_In_DBx__4__BIE CYREG_PRT12_BIE
+#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT12_BIT_MASK
+#define SCSI_In_DBx__4__BYP CYREG_PRT12_BYP
+#define SCSI_In_DBx__4__DM0 CYREG_PRT12_DM0
+#define SCSI_In_DBx__4__DM1 CYREG_PRT12_DM1
+#define SCSI_In_DBx__4__DM2 CYREG_PRT12_DM2
+#define SCSI_In_DBx__4__DR CYREG_PRT12_DR
+#define SCSI_In_DBx__4__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_In_DBx__4__MASK 0x20u
+#define SCSI_In_DBx__4__PC CYREG_PRT12_PC5
+#define SCSI_In_DBx__4__PORT 12u
+#define SCSI_In_DBx__4__PRT CYREG_PRT12_PRT
+#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define SCSI_In_DBx__4__PS CYREG_PRT12_PS
+#define SCSI_In_DBx__4__SHIFT 5
+#define SCSI_In_DBx__4__SIO_CFG CYREG_PRT12_SIO_CFG
+#define SCSI_In_DBx__4__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define SCSI_In_DBx__4__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define SCSI_In_DBx__4__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define SCSI_In_DBx__4__SLW CYREG_PRT12_SLW
+#define SCSI_In_DBx__5__AG CYREG_PRT12_AG
+#define SCSI_In_DBx__5__BIE CYREG_PRT12_BIE
+#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT12_BIT_MASK
+#define SCSI_In_DBx__5__BYP CYREG_PRT12_BYP
+#define SCSI_In_DBx__5__DM0 CYREG_PRT12_DM0
+#define SCSI_In_DBx__5__DM1 CYREG_PRT12_DM1
+#define SCSI_In_DBx__5__DM2 CYREG_PRT12_DM2
+#define SCSI_In_DBx__5__DR CYREG_PRT12_DR
+#define SCSI_In_DBx__5__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_In_DBx__5__MASK 0x10u
+#define SCSI_In_DBx__5__PC CYREG_PRT12_PC4
+#define SCSI_In_DBx__5__PORT 12u
+#define SCSI_In_DBx__5__PRT CYREG_PRT12_PRT
+#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define SCSI_In_DBx__5__PS CYREG_PRT12_PS
+#define SCSI_In_DBx__5__SHIFT 4
+#define SCSI_In_DBx__5__SIO_CFG CYREG_PRT12_SIO_CFG
+#define SCSI_In_DBx__5__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define SCSI_In_DBx__5__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define SCSI_In_DBx__5__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define SCSI_In_DBx__5__SLW CYREG_PRT12_SLW
+#define SCSI_In_DBx__6__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__6__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__6__MASK 0x20u
+#define SCSI_In_DBx__6__PC CYREG_PRT2_PC5
+#define SCSI_In_DBx__6__PORT 2u
+#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__6__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__6__SHIFT 5
+#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__7__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__7__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__7__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__7__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__7__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__7__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__7__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__7__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__7__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__7__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__7__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__7__MASK 0x10u
+#define SCSI_In_DBx__7__PC CYREG_PRT2_PC4
+#define SCSI_In_DBx__7__PORT 2u
+#define SCSI_In_DBx__7__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__7__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__7__SHIFT 4
+#define SCSI_In_DBx__7__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__DB0__AG CYREG_PRT5_AG
+#define SCSI_In_DBx__DB0__AMUX CYREG_PRT5_AMUX
+#define SCSI_In_DBx__DB0__BIE CYREG_PRT5_BIE
+#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_In_DBx__DB0__BYP CYREG_PRT5_BYP
+#define SCSI_In_DBx__DB0__CTL CYREG_PRT5_CTL
+#define SCSI_In_DBx__DB0__DM0 CYREG_PRT5_DM0
+#define SCSI_In_DBx__DB0__DM1 CYREG_PRT5_DM1
+#define SCSI_In_DBx__DB0__DM2 CYREG_PRT5_DM2
+#define SCSI_In_DBx__DB0__DR CYREG_PRT5_DR
+#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_In_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_In_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_In_DBx__DB0__MASK 0x08u
+#define SCSI_In_DBx__DB0__PC CYREG_PRT5_PC3
+#define SCSI_In_DBx__DB0__PORT 5u
+#define SCSI_In_DBx__DB0__PRT CYREG_PRT5_PRT
+#define SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_In_DBx__DB0__PS CYREG_PRT5_PS
+#define SCSI_In_DBx__DB0__SHIFT 3
+#define SCSI_In_DBx__DB0__SLW CYREG_PRT5_SLW
+#define SCSI_In_DBx__DB1__AG CYREG_PRT5_AG
+#define SCSI_In_DBx__DB1__AMUX CYREG_PRT5_AMUX
+#define SCSI_In_DBx__DB1__BIE CYREG_PRT5_BIE
+#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_In_DBx__DB1__BYP CYREG_PRT5_BYP
+#define SCSI_In_DBx__DB1__CTL CYREG_PRT5_CTL
+#define SCSI_In_DBx__DB1__DM0 CYREG_PRT5_DM0
+#define SCSI_In_DBx__DB1__DM1 CYREG_PRT5_DM1
+#define SCSI_In_DBx__DB1__DM2 CYREG_PRT5_DM2
+#define SCSI_In_DBx__DB1__DR CYREG_PRT5_DR
+#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_In_DBx__DB1__MASK 0x04u
+#define SCSI_In_DBx__DB1__PC CYREG_PRT5_PC2
+#define SCSI_In_DBx__DB1__PORT 5u
+#define SCSI_In_DBx__DB1__PRT CYREG_PRT5_PRT
+#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_In_DBx__DB1__PS CYREG_PRT5_PS
+#define SCSI_In_DBx__DB1__SHIFT 2
+#define SCSI_In_DBx__DB1__SLW CYREG_PRT5_SLW
+#define SCSI_In_DBx__DB2__AG CYREG_PRT6_AG
+#define SCSI_In_DBx__DB2__AMUX CYREG_PRT6_AMUX
+#define SCSI_In_DBx__DB2__BIE CYREG_PRT6_BIE
+#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_In_DBx__DB2__BYP CYREG_PRT6_BYP
+#define SCSI_In_DBx__DB2__CTL CYREG_PRT6_CTL
+#define SCSI_In_DBx__DB2__DM0 CYREG_PRT6_DM0
+#define SCSI_In_DBx__DB2__DM1 CYREG_PRT6_DM1
+#define SCSI_In_DBx__DB2__DM2 CYREG_PRT6_DM2
+#define SCSI_In_DBx__DB2__DR CYREG_PRT6_DR
+#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_In_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_In_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_In_DBx__DB2__MASK 0x80u
+#define SCSI_In_DBx__DB2__PC CYREG_PRT6_PC7
+#define SCSI_In_DBx__DB2__PORT 6u
+#define SCSI_In_DBx__DB2__PRT CYREG_PRT6_PRT
+#define SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_In_DBx__DB2__PS CYREG_PRT6_PS
+#define SCSI_In_DBx__DB2__SHIFT 7
+#define SCSI_In_DBx__DB2__SLW CYREG_PRT6_SLW
+#define SCSI_In_DBx__DB3__AG CYREG_PRT6_AG
+#define SCSI_In_DBx__DB3__AMUX CYREG_PRT6_AMUX
+#define SCSI_In_DBx__DB3__BIE CYREG_PRT6_BIE
+#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_In_DBx__DB3__BYP CYREG_PRT6_BYP
+#define SCSI_In_DBx__DB3__CTL CYREG_PRT6_CTL
+#define SCSI_In_DBx__DB3__DM0 CYREG_PRT6_DM0
+#define SCSI_In_DBx__DB3__DM1 CYREG_PRT6_DM1
+#define SCSI_In_DBx__DB3__DM2 CYREG_PRT6_DM2
+#define SCSI_In_DBx__DB3__DR CYREG_PRT6_DR
+#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_In_DBx__DB3__MASK 0x40u
+#define SCSI_In_DBx__DB3__PC CYREG_PRT6_PC6
+#define SCSI_In_DBx__DB3__PORT 6u
+#define SCSI_In_DBx__DB3__PRT CYREG_PRT6_PRT
+#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_In_DBx__DB3__PS CYREG_PRT6_PS
+#define SCSI_In_DBx__DB3__SHIFT 6
+#define SCSI_In_DBx__DB3__SLW CYREG_PRT6_SLW
+#define SCSI_In_DBx__DB4__AG CYREG_PRT12_AG
+#define SCSI_In_DBx__DB4__BIE CYREG_PRT12_BIE
+#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT12_BIT_MASK
+#define SCSI_In_DBx__DB4__BYP CYREG_PRT12_BYP
+#define SCSI_In_DBx__DB4__DM0 CYREG_PRT12_DM0
+#define SCSI_In_DBx__DB4__DM1 CYREG_PRT12_DM1
+#define SCSI_In_DBx__DB4__DM2 CYREG_PRT12_DM2
+#define SCSI_In_DBx__DB4__DR CYREG_PRT12_DR
+#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_In_DBx__DB4__MASK 0x20u
+#define SCSI_In_DBx__DB4__PC CYREG_PRT12_PC5
+#define SCSI_In_DBx__DB4__PORT 12u
+#define SCSI_In_DBx__DB4__PRT CYREG_PRT12_PRT
+#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define SCSI_In_DBx__DB4__PS CYREG_PRT12_PS
+#define SCSI_In_DBx__DB4__SHIFT 5
+#define SCSI_In_DBx__DB4__SIO_CFG CYREG_PRT12_SIO_CFG
+#define SCSI_In_DBx__DB4__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define SCSI_In_DBx__DB4__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define SCSI_In_DBx__DB4__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define SCSI_In_DBx__DB4__SLW CYREG_PRT12_SLW
+#define SCSI_In_DBx__DB5__AG CYREG_PRT12_AG
+#define SCSI_In_DBx__DB5__BIE CYREG_PRT12_BIE
+#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT12_BIT_MASK
+#define SCSI_In_DBx__DB5__BYP CYREG_PRT12_BYP
+#define SCSI_In_DBx__DB5__DM0 CYREG_PRT12_DM0
+#define SCSI_In_DBx__DB5__DM1 CYREG_PRT12_DM1
+#define SCSI_In_DBx__DB5__DM2 CYREG_PRT12_DM2
+#define SCSI_In_DBx__DB5__DR CYREG_PRT12_DR
+#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT12_INP_DIS
+#define SCSI_In_DBx__DB5__MASK 0x10u
+#define SCSI_In_DBx__DB5__PC CYREG_PRT12_PC4
+#define SCSI_In_DBx__DB5__PORT 12u
+#define SCSI_In_DBx__DB5__PRT CYREG_PRT12_PRT
+#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
+#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
+#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
+#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
+#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
+#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
+#define SCSI_In_DBx__DB5__PS CYREG_PRT12_PS
+#define SCSI_In_DBx__DB5__SHIFT 4
+#define SCSI_In_DBx__DB5__SIO_CFG CYREG_PRT12_SIO_CFG
+#define SCSI_In_DBx__DB5__SIO_DIFF CYREG_PRT12_SIO_DIFF
+#define SCSI_In_DBx__DB5__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
+#define SCSI_In_DBx__DB5__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
+#define SCSI_In_DBx__DB5__SLW CYREG_PRT12_SLW
+#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__DB6__MASK 0x20u
+#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC5
+#define SCSI_In_DBx__DB6__PORT 2u
+#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__DB6__SHIFT 5
+#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW
+#define SCSI_In_DBx__DB7__AG CYREG_PRT2_AG
+#define SCSI_In_DBx__DB7__AMUX CYREG_PRT2_AMUX
+#define SCSI_In_DBx__DB7__BIE CYREG_PRT2_BIE
+#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_In_DBx__DB7__BYP CYREG_PRT2_BYP
+#define SCSI_In_DBx__DB7__CTL CYREG_PRT2_CTL
+#define SCSI_In_DBx__DB7__DM0 CYREG_PRT2_DM0
+#define SCSI_In_DBx__DB7__DM1 CYREG_PRT2_DM1
+#define SCSI_In_DBx__DB7__DM2 CYREG_PRT2_DM2
+#define SCSI_In_DBx__DB7__DR CYREG_PRT2_DR
+#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_In_DBx__DB7__MASK 0x10u
+#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC4
+#define SCSI_In_DBx__DB7__PORT 2u
+#define SCSI_In_DBx__DB7__PRT CYREG_PRT2_PRT
+#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_In_DBx__DB7__PS CYREG_PRT2_PS
+#define SCSI_In_DBx__DB7__SHIFT 4
+#define SCSI_In_DBx__DB7__SLW CYREG_PRT2_SLW
+
+/* SD_MISO */
+#define SD_MISO__0__MASK 0x02u
+#define SD_MISO__0__PC CYREG_PRT3_PC1
+#define SD_MISO__0__PORT 3u
+#define SD_MISO__0__SHIFT 1
+#define SD_MISO__AG CYREG_PRT3_AG
+#define SD_MISO__AMUX CYREG_PRT3_AMUX
+#define SD_MISO__BIE CYREG_PRT3_BIE
+#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_MISO__BYP CYREG_PRT3_BYP
+#define SD_MISO__CTL CYREG_PRT3_CTL
+#define SD_MISO__DM0 CYREG_PRT3_DM0
+#define SD_MISO__DM1 CYREG_PRT3_DM1
+#define SD_MISO__DM2 CYREG_PRT3_DM2
+#define SD_MISO__DR CYREG_PRT3_DR
+#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_MISO__MASK 0x02u
+#define SD_MISO__PORT 3u
+#define SD_MISO__PRT CYREG_PRT3_PRT
+#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_MISO__PS CYREG_PRT3_PS
+#define SD_MISO__SHIFT 1
+#define SD_MISO__SLW CYREG_PRT3_SLW
+
+/* SD_MOSI */
+#define SD_MOSI__0__MASK 0x08u
+#define SD_MOSI__0__PC CYREG_PRT3_PC3
+#define SD_MOSI__0__PORT 3u
+#define SD_MOSI__0__SHIFT 3
+#define SD_MOSI__AG CYREG_PRT3_AG
+#define SD_MOSI__AMUX CYREG_PRT3_AMUX
+#define SD_MOSI__BIE CYREG_PRT3_BIE
+#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_MOSI__BYP CYREG_PRT3_BYP
+#define SD_MOSI__CTL CYREG_PRT3_CTL
+#define SD_MOSI__DM0 CYREG_PRT3_DM0
+#define SD_MOSI__DM1 CYREG_PRT3_DM1
+#define SD_MOSI__DM2 CYREG_PRT3_DM2
+#define SD_MOSI__DR CYREG_PRT3_DR
+#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_MOSI__MASK 0x08u
+#define SD_MOSI__PORT 3u
+#define SD_MOSI__PRT CYREG_PRT3_PRT
+#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_MOSI__PS CYREG_PRT3_PS
+#define SD_MOSI__SHIFT 3
+#define SD_MOSI__SLW CYREG_PRT3_SLW
+
+/* SCSI_CLK */
+#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0
+#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1
+#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2
+#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u
+#define SCSI_CLK__INDEX 0x01u
+#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2
+#define SCSI_CLK__PM_ACT_MSK 0x02u
+#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2
+#define SCSI_CLK__PM_STBY_MSK 0x02u
+
+/* SCSI_Out */
+#define SCSI_Out__0__AG CYREG_PRT15_AG
+#define SCSI_Out__0__AMUX CYREG_PRT15_AMUX
+#define SCSI_Out__0__BIE CYREG_PRT15_BIE
+#define SCSI_Out__0__BIT_MASK CYREG_PRT15_BIT_MASK
+#define SCSI_Out__0__BYP CYREG_PRT15_BYP
+#define SCSI_Out__0__CTL CYREG_PRT15_CTL
+#define SCSI_Out__0__DM0 CYREG_PRT15_DM0
+#define SCSI_Out__0__DM1 CYREG_PRT15_DM1
+#define SCSI_Out__0__DM2 CYREG_PRT15_DM2
+#define SCSI_Out__0__DR CYREG_PRT15_DR
+#define SCSI_Out__0__INP_DIS CYREG_PRT15_INP_DIS
+#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define SCSI_Out__0__LCD_EN CYREG_PRT15_LCD_EN
+#define SCSI_Out__0__MASK 0x20u
+#define SCSI_Out__0__PC CYREG_IO_PC_PRT15_PC5
+#define SCSI_Out__0__PORT 15u
+#define SCSI_Out__0__PRT CYREG_PRT15_PRT
+#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define SCSI_Out__0__PS CYREG_PRT15_PS
+#define SCSI_Out__0__SHIFT 5
+#define SCSI_Out__0__SLW CYREG_PRT15_SLW
+#define SCSI_Out__1__AG CYREG_PRT15_AG
+#define SCSI_Out__1__AMUX CYREG_PRT15_AMUX
+#define SCSI_Out__1__BIE CYREG_PRT15_BIE
+#define SCSI_Out__1__BIT_MASK CYREG_PRT15_BIT_MASK
+#define SCSI_Out__1__BYP CYREG_PRT15_BYP
+#define SCSI_Out__1__CTL CYREG_PRT15_CTL
+#define SCSI_Out__1__DM0 CYREG_PRT15_DM0
+#define SCSI_Out__1__DM1 CYREG_PRT15_DM1
+#define SCSI_Out__1__DM2 CYREG_PRT15_DM2
+#define SCSI_Out__1__DR CYREG_PRT15_DR
+#define SCSI_Out__1__INP_DIS CYREG_PRT15_INP_DIS
+#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define SCSI_Out__1__LCD_EN CYREG_PRT15_LCD_EN
+#define SCSI_Out__1__MASK 0x10u
+#define SCSI_Out__1__PC CYREG_IO_PC_PRT15_PC4
+#define SCSI_Out__1__PORT 15u
+#define SCSI_Out__1__PRT CYREG_PRT15_PRT
+#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define SCSI_Out__1__PS CYREG_PRT15_PS
+#define SCSI_Out__1__SHIFT 4
+#define SCSI_Out__1__SLW CYREG_PRT15_SLW
+#define SCSI_Out__2__AG CYREG_PRT6_AG
+#define SCSI_Out__2__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out__2__BIE CYREG_PRT6_BIE
+#define SCSI_Out__2__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out__2__BYP CYREG_PRT6_BYP
+#define SCSI_Out__2__CTL CYREG_PRT6_CTL
+#define SCSI_Out__2__DM0 CYREG_PRT6_DM0
+#define SCSI_Out__2__DM1 CYREG_PRT6_DM1
+#define SCSI_Out__2__DM2 CYREG_PRT6_DM2
+#define SCSI_Out__2__DR CYREG_PRT6_DR
+#define SCSI_Out__2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out__2__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out__2__MASK 0x02u
+#define SCSI_Out__2__PC CYREG_PRT6_PC1
+#define SCSI_Out__2__PORT 6u
+#define SCSI_Out__2__PRT CYREG_PRT6_PRT
+#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out__2__PS CYREG_PRT6_PS
+#define SCSI_Out__2__SHIFT 1
+#define SCSI_Out__2__SLW CYREG_PRT6_SLW
+#define SCSI_Out__3__AG CYREG_PRT6_AG
+#define SCSI_Out__3__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out__3__BIE CYREG_PRT6_BIE
+#define SCSI_Out__3__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out__3__BYP CYREG_PRT6_BYP
+#define SCSI_Out__3__CTL CYREG_PRT6_CTL
+#define SCSI_Out__3__DM0 CYREG_PRT6_DM0
+#define SCSI_Out__3__DM1 CYREG_PRT6_DM1
+#define SCSI_Out__3__DM2 CYREG_PRT6_DM2
+#define SCSI_Out__3__DR CYREG_PRT6_DR
+#define SCSI_Out__3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out__3__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out__3__MASK 0x01u
+#define SCSI_Out__3__PC CYREG_PRT6_PC0
+#define SCSI_Out__3__PORT 6u
+#define SCSI_Out__3__PRT CYREG_PRT6_PRT
+#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out__3__PS CYREG_PRT6_PS
+#define SCSI_Out__3__SHIFT 0
+#define SCSI_Out__3__SLW CYREG_PRT6_SLW
+#define SCSI_Out__4__AG CYREG_PRT4_AG
+#define SCSI_Out__4__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out__4__BIE CYREG_PRT4_BIE
+#define SCSI_Out__4__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out__4__BYP CYREG_PRT4_BYP
+#define SCSI_Out__4__CTL CYREG_PRT4_CTL
+#define SCSI_Out__4__DM0 CYREG_PRT4_DM0
+#define SCSI_Out__4__DM1 CYREG_PRT4_DM1
+#define SCSI_Out__4__DM2 CYREG_PRT4_DM2
+#define SCSI_Out__4__DR CYREG_PRT4_DR
+#define SCSI_Out__4__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out__4__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out__4__MASK 0x20u
+#define SCSI_Out__4__PC CYREG_PRT4_PC5
+#define SCSI_Out__4__PORT 4u
+#define SCSI_Out__4__PRT CYREG_PRT4_PRT
+#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out__4__PS CYREG_PRT4_PS
+#define SCSI_Out__4__SHIFT 5
+#define SCSI_Out__4__SLW CYREG_PRT4_SLW
+#define SCSI_Out__5__AG CYREG_PRT4_AG
+#define SCSI_Out__5__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out__5__BIE CYREG_PRT4_BIE
+#define SCSI_Out__5__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out__5__BYP CYREG_PRT4_BYP
+#define SCSI_Out__5__CTL CYREG_PRT4_CTL
+#define SCSI_Out__5__DM0 CYREG_PRT4_DM0
+#define SCSI_Out__5__DM1 CYREG_PRT4_DM1
+#define SCSI_Out__5__DM2 CYREG_PRT4_DM2
+#define SCSI_Out__5__DR CYREG_PRT4_DR
+#define SCSI_Out__5__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out__5__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out__5__MASK 0x10u
+#define SCSI_Out__5__PC CYREG_PRT4_PC4
+#define SCSI_Out__5__PORT 4u
+#define SCSI_Out__5__PRT CYREG_PRT4_PRT
+#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out__5__PS CYREG_PRT4_PS
+#define SCSI_Out__5__SHIFT 4
+#define SCSI_Out__5__SLW CYREG_PRT4_SLW
+#define SCSI_Out__6__AG CYREG_PRT0_AG
+#define SCSI_Out__6__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__6__BIE CYREG_PRT0_BIE
+#define SCSI_Out__6__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__6__BYP CYREG_PRT0_BYP
+#define SCSI_Out__6__CTL CYREG_PRT0_CTL
+#define SCSI_Out__6__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__6__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__6__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__6__DR CYREG_PRT0_DR
+#define SCSI_Out__6__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__6__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__6__MASK 0x80u
+#define SCSI_Out__6__PC CYREG_PRT0_PC7
+#define SCSI_Out__6__PORT 0u
+#define SCSI_Out__6__PRT CYREG_PRT0_PRT
+#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__6__PS CYREG_PRT0_PS
+#define SCSI_Out__6__SHIFT 7
+#define SCSI_Out__6__SLW CYREG_PRT0_SLW
+#define SCSI_Out__7__AG CYREG_PRT0_AG
+#define SCSI_Out__7__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__7__BIE CYREG_PRT0_BIE
+#define SCSI_Out__7__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__7__BYP CYREG_PRT0_BYP
+#define SCSI_Out__7__CTL CYREG_PRT0_CTL
+#define SCSI_Out__7__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__7__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__7__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__7__DR CYREG_PRT0_DR
+#define SCSI_Out__7__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__7__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__7__MASK 0x40u
+#define SCSI_Out__7__PC CYREG_PRT0_PC6
+#define SCSI_Out__7__PORT 0u
+#define SCSI_Out__7__PRT CYREG_PRT0_PRT
+#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__7__PS CYREG_PRT0_PS
+#define SCSI_Out__7__SHIFT 6
+#define SCSI_Out__7__SLW CYREG_PRT0_SLW
+#define SCSI_Out__8__AG CYREG_PRT0_AG
+#define SCSI_Out__8__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__8__BIE CYREG_PRT0_BIE
+#define SCSI_Out__8__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__8__BYP CYREG_PRT0_BYP
+#define SCSI_Out__8__CTL CYREG_PRT0_CTL
+#define SCSI_Out__8__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__8__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__8__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__8__DR CYREG_PRT0_DR
+#define SCSI_Out__8__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__8__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__8__MASK 0x08u
+#define SCSI_Out__8__PC CYREG_PRT0_PC3
+#define SCSI_Out__8__PORT 0u
+#define SCSI_Out__8__PRT CYREG_PRT0_PRT
+#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__8__PS CYREG_PRT0_PS
+#define SCSI_Out__8__SHIFT 3
+#define SCSI_Out__8__SLW CYREG_PRT0_SLW
+#define SCSI_Out__9__AG CYREG_PRT0_AG
+#define SCSI_Out__9__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__9__BIE CYREG_PRT0_BIE
+#define SCSI_Out__9__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__9__BYP CYREG_PRT0_BYP
+#define SCSI_Out__9__CTL CYREG_PRT0_CTL
+#define SCSI_Out__9__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__9__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__9__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__9__DR CYREG_PRT0_DR
+#define SCSI_Out__9__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__9__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__9__MASK 0x04u
+#define SCSI_Out__9__PC CYREG_PRT0_PC2
+#define SCSI_Out__9__PORT 0u
+#define SCSI_Out__9__PRT CYREG_PRT0_PRT
+#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__9__PS CYREG_PRT0_PS
+#define SCSI_Out__9__SHIFT 2
+#define SCSI_Out__9__SLW CYREG_PRT0_SLW
+#define SCSI_Out__ACK__AG CYREG_PRT6_AG
+#define SCSI_Out__ACK__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out__ACK__BIE CYREG_PRT6_BIE
+#define SCSI_Out__ACK__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out__ACK__BYP CYREG_PRT6_BYP
+#define SCSI_Out__ACK__CTL CYREG_PRT6_CTL
+#define SCSI_Out__ACK__DM0 CYREG_PRT6_DM0
+#define SCSI_Out__ACK__DM1 CYREG_PRT6_DM1
+#define SCSI_Out__ACK__DM2 CYREG_PRT6_DM2
+#define SCSI_Out__ACK__DR CYREG_PRT6_DR
+#define SCSI_Out__ACK__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out__ACK__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out__ACK__MASK 0x01u
+#define SCSI_Out__ACK__PC CYREG_PRT6_PC0
+#define SCSI_Out__ACK__PORT 6u
+#define SCSI_Out__ACK__PRT CYREG_PRT6_PRT
+#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out__ACK__PS CYREG_PRT6_PS
+#define SCSI_Out__ACK__SHIFT 0
+#define SCSI_Out__ACK__SLW CYREG_PRT6_SLW
+#define SCSI_Out__ATN__AG CYREG_PRT15_AG
+#define SCSI_Out__ATN__AMUX CYREG_PRT15_AMUX
+#define SCSI_Out__ATN__BIE CYREG_PRT15_BIE
+#define SCSI_Out__ATN__BIT_MASK CYREG_PRT15_BIT_MASK
+#define SCSI_Out__ATN__BYP CYREG_PRT15_BYP
+#define SCSI_Out__ATN__CTL CYREG_PRT15_CTL
+#define SCSI_Out__ATN__DM0 CYREG_PRT15_DM0
+#define SCSI_Out__ATN__DM1 CYREG_PRT15_DM1
+#define SCSI_Out__ATN__DM2 CYREG_PRT15_DM2
+#define SCSI_Out__ATN__DR CYREG_PRT15_DR
+#define SCSI_Out__ATN__INP_DIS CYREG_PRT15_INP_DIS
+#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define SCSI_Out__ATN__LCD_EN CYREG_PRT15_LCD_EN
+#define SCSI_Out__ATN__MASK 0x10u
+#define SCSI_Out__ATN__PC CYREG_IO_PC_PRT15_PC4
+#define SCSI_Out__ATN__PORT 15u
+#define SCSI_Out__ATN__PRT CYREG_PRT15_PRT
+#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define SCSI_Out__ATN__PS CYREG_PRT15_PS
+#define SCSI_Out__ATN__SHIFT 4
+#define SCSI_Out__ATN__SLW CYREG_PRT15_SLW
+#define SCSI_Out__BSY__AG CYREG_PRT6_AG
+#define SCSI_Out__BSY__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out__BSY__BIE CYREG_PRT6_BIE
+#define SCSI_Out__BSY__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out__BSY__BYP CYREG_PRT6_BYP
+#define SCSI_Out__BSY__CTL CYREG_PRT6_CTL
+#define SCSI_Out__BSY__DM0 CYREG_PRT6_DM0
+#define SCSI_Out__BSY__DM1 CYREG_PRT6_DM1
+#define SCSI_Out__BSY__DM2 CYREG_PRT6_DM2
+#define SCSI_Out__BSY__DR CYREG_PRT6_DR
+#define SCSI_Out__BSY__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out__BSY__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out__BSY__MASK 0x02u
+#define SCSI_Out__BSY__PC CYREG_PRT6_PC1
+#define SCSI_Out__BSY__PORT 6u
+#define SCSI_Out__BSY__PRT CYREG_PRT6_PRT
+#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out__BSY__PS CYREG_PRT6_PS
+#define SCSI_Out__BSY__SHIFT 1
+#define SCSI_Out__BSY__SLW CYREG_PRT6_SLW
+#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG
+#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE
+#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP
+#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL
+#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR
+#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__CD_raw__MASK 0x40u
+#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC6
+#define SCSI_Out__CD_raw__PORT 0u
+#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT
+#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS
+#define SCSI_Out__CD_raw__SHIFT 6
+#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW
+#define SCSI_Out__DBP_raw__AG CYREG_PRT15_AG
+#define SCSI_Out__DBP_raw__AMUX CYREG_PRT15_AMUX
+#define SCSI_Out__DBP_raw__BIE CYREG_PRT15_BIE
+#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT15_BIT_MASK
+#define SCSI_Out__DBP_raw__BYP CYREG_PRT15_BYP
+#define SCSI_Out__DBP_raw__CTL CYREG_PRT15_CTL
+#define SCSI_Out__DBP_raw__DM0 CYREG_PRT15_DM0
+#define SCSI_Out__DBP_raw__DM1 CYREG_PRT15_DM1
+#define SCSI_Out__DBP_raw__DM2 CYREG_PRT15_DM2
+#define SCSI_Out__DBP_raw__DR CYREG_PRT15_DR
+#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT15_INP_DIS
+#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT15_LCD_EN
+#define SCSI_Out__DBP_raw__MASK 0x20u
+#define SCSI_Out__DBP_raw__PC CYREG_IO_PC_PRT15_PC5
+#define SCSI_Out__DBP_raw__PORT 15u
+#define SCSI_Out__DBP_raw__PRT CYREG_PRT15_PRT
+#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define SCSI_Out__DBP_raw__PS CYREG_PRT15_PS
+#define SCSI_Out__DBP_raw__SHIFT 5
+#define SCSI_Out__DBP_raw__SLW CYREG_PRT15_SLW
+#define SCSI_Out__IO_raw__AG CYREG_PRT0_AG
+#define SCSI_Out__IO_raw__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__IO_raw__BIE CYREG_PRT0_BIE
+#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__IO_raw__BYP CYREG_PRT0_BYP
+#define SCSI_Out__IO_raw__CTL CYREG_PRT0_CTL
+#define SCSI_Out__IO_raw__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__IO_raw__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__IO_raw__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__IO_raw__DR CYREG_PRT0_DR
+#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__IO_raw__MASK 0x04u
+#define SCSI_Out__IO_raw__PC CYREG_PRT0_PC2
+#define SCSI_Out__IO_raw__PORT 0u
+#define SCSI_Out__IO_raw__PRT CYREG_PRT0_PRT
+#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__IO_raw__PS CYREG_PRT0_PS
+#define SCSI_Out__IO_raw__SHIFT 2
+#define SCSI_Out__IO_raw__SLW CYREG_PRT0_SLW
+#define SCSI_Out__MSG_raw__AG CYREG_PRT4_AG
+#define SCSI_Out__MSG_raw__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out__MSG_raw__BIE CYREG_PRT4_BIE
+#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out__MSG_raw__BYP CYREG_PRT4_BYP
+#define SCSI_Out__MSG_raw__CTL CYREG_PRT4_CTL
+#define SCSI_Out__MSG_raw__DM0 CYREG_PRT4_DM0
+#define SCSI_Out__MSG_raw__DM1 CYREG_PRT4_DM1
+#define SCSI_Out__MSG_raw__DM2 CYREG_PRT4_DM2
+#define SCSI_Out__MSG_raw__DR CYREG_PRT4_DR
+#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out__MSG_raw__MASK 0x10u
+#define SCSI_Out__MSG_raw__PC CYREG_PRT4_PC4
+#define SCSI_Out__MSG_raw__PORT 4u
+#define SCSI_Out__MSG_raw__PRT CYREG_PRT4_PRT
+#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out__MSG_raw__PS CYREG_PRT4_PS
+#define SCSI_Out__MSG_raw__SHIFT 4
+#define SCSI_Out__MSG_raw__SLW CYREG_PRT4_SLW
+#define SCSI_Out__REQ__AG CYREG_PRT0_AG
+#define SCSI_Out__REQ__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__REQ__BIE CYREG_PRT0_BIE
+#define SCSI_Out__REQ__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__REQ__BYP CYREG_PRT0_BYP
+#define SCSI_Out__REQ__CTL CYREG_PRT0_CTL
+#define SCSI_Out__REQ__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__REQ__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__REQ__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__REQ__DR CYREG_PRT0_DR
+#define SCSI_Out__REQ__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__REQ__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__REQ__MASK 0x08u
+#define SCSI_Out__REQ__PC CYREG_PRT0_PC3
+#define SCSI_Out__REQ__PORT 0u
+#define SCSI_Out__REQ__PRT CYREG_PRT0_PRT
+#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__REQ__PS CYREG_PRT0_PS
+#define SCSI_Out__REQ__SHIFT 3
+#define SCSI_Out__REQ__SLW CYREG_PRT0_SLW
+#define SCSI_Out__RST__AG CYREG_PRT4_AG
+#define SCSI_Out__RST__AMUX CYREG_PRT4_AMUX
+#define SCSI_Out__RST__BIE CYREG_PRT4_BIE
+#define SCSI_Out__RST__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Out__RST__BYP CYREG_PRT4_BYP
+#define SCSI_Out__RST__CTL CYREG_PRT4_CTL
+#define SCSI_Out__RST__DM0 CYREG_PRT4_DM0
+#define SCSI_Out__RST__DM1 CYREG_PRT4_DM1
+#define SCSI_Out__RST__DM2 CYREG_PRT4_DM2
+#define SCSI_Out__RST__DR CYREG_PRT4_DR
+#define SCSI_Out__RST__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Out__RST__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Out__RST__MASK 0x20u
+#define SCSI_Out__RST__PC CYREG_PRT4_PC5
+#define SCSI_Out__RST__PORT 4u
+#define SCSI_Out__RST__PRT CYREG_PRT4_PRT
+#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Out__RST__PS CYREG_PRT4_PS
+#define SCSI_Out__RST__SHIFT 5
+#define SCSI_Out__RST__SLW CYREG_PRT4_SLW
+#define SCSI_Out__SEL__AG CYREG_PRT0_AG
+#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX
+#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE
+#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK
+#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP
+#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL
+#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0
+#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1
+#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2
+#define SCSI_Out__SEL__DR CYREG_PRT0_DR
+#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS
+#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN
+#define SCSI_Out__SEL__MASK 0x80u
+#define SCSI_Out__SEL__PC CYREG_PRT0_PC7
+#define SCSI_Out__SEL__PORT 0u
+#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT
+#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define SCSI_Out__SEL__PS CYREG_PRT0_PS
+#define SCSI_Out__SEL__SHIFT 7
+#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW
+
+/* SCSI_Out_Bits */
+#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u
+#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
+#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
+#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
+#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
+#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
+#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
+#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3
+#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u
+#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4
+#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u
+#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5
+#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u
+#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
+#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
+#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB15_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB15_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB15_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB15_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB15_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB15_MSK
+
+/* SCSI_Out_Ctl */
+#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
+#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK
+
+/* SCSI_Out_DBx */
+#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
+#define SCSI_Out_DBx__0__AMUX CYREG_PRT5_AMUX
+#define SCSI_Out_DBx__0__BIE CYREG_PRT5_BIE
+#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_Out_DBx__0__BYP CYREG_PRT5_BYP
+#define SCSI_Out_DBx__0__CTL CYREG_PRT5_CTL
+#define SCSI_Out_DBx__0__DM0 CYREG_PRT5_DM0
+#define SCSI_Out_DBx__0__DM1 CYREG_PRT5_DM1
+#define SCSI_Out_DBx__0__DM2 CYREG_PRT5_DM2
+#define SCSI_Out_DBx__0__DR CYREG_PRT5_DR
+#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_Out_DBx__0__MASK 0x02u
+#define SCSI_Out_DBx__0__PC CYREG_PRT5_PC1
+#define SCSI_Out_DBx__0__PORT 5u
+#define SCSI_Out_DBx__0__PRT CYREG_PRT5_PRT
+#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_Out_DBx__0__PS CYREG_PRT5_PS
+#define SCSI_Out_DBx__0__SHIFT 1
+#define SCSI_Out_DBx__0__SLW CYREG_PRT5_SLW
+#define SCSI_Out_DBx__1__AG CYREG_PRT5_AG
+#define SCSI_Out_DBx__1__AMUX CYREG_PRT5_AMUX
+#define SCSI_Out_DBx__1__BIE CYREG_PRT5_BIE
+#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_Out_DBx__1__BYP CYREG_PRT5_BYP
+#define SCSI_Out_DBx__1__CTL CYREG_PRT5_CTL
+#define SCSI_Out_DBx__1__DM0 CYREG_PRT5_DM0
+#define SCSI_Out_DBx__1__DM1 CYREG_PRT5_DM1
+#define SCSI_Out_DBx__1__DM2 CYREG_PRT5_DM2
+#define SCSI_Out_DBx__1__DR CYREG_PRT5_DR
+#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_Out_DBx__1__MASK 0x01u
+#define SCSI_Out_DBx__1__PC CYREG_PRT5_PC0
+#define SCSI_Out_DBx__1__PORT 5u
+#define SCSI_Out_DBx__1__PRT CYREG_PRT5_PRT
+#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_Out_DBx__1__PS CYREG_PRT5_PS
+#define SCSI_Out_DBx__1__SHIFT 0
+#define SCSI_Out_DBx__1__SLW CYREG_PRT5_SLW
+#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__2__MASK 0x20u
+#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC5
+#define SCSI_Out_DBx__2__PORT 6u
+#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__2__SHIFT 5
+#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__3__MASK 0x10u
+#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC4
+#define SCSI_Out_DBx__3__PORT 6u
+#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__3__SHIFT 4
+#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__4__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__4__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__4__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__4__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__4__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__4__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__4__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__4__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__4__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__4__MASK 0x80u
+#define SCSI_Out_DBx__4__PC CYREG_PRT2_PC7
+#define SCSI_Out_DBx__4__PORT 2u
+#define SCSI_Out_DBx__4__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__4__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__4__SHIFT 7
+#define SCSI_Out_DBx__4__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__5__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__5__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__5__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__5__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__5__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__5__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__5__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__5__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__5__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__5__MASK 0x40u
+#define SCSI_Out_DBx__5__PC CYREG_PRT2_PC6
+#define SCSI_Out_DBx__5__PORT 2u
+#define SCSI_Out_DBx__5__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__5__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__5__SHIFT 6
+#define SCSI_Out_DBx__5__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__6__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__6__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__6__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__6__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__6__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__6__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__6__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__6__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__6__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__6__MASK 0x08u
+#define SCSI_Out_DBx__6__PC CYREG_PRT2_PC3
+#define SCSI_Out_DBx__6__PORT 2u
+#define SCSI_Out_DBx__6__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__6__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__6__SHIFT 3
+#define SCSI_Out_DBx__6__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__7__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__7__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__7__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__7__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__7__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__7__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__7__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__7__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__7__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__7__MASK 0x04u
+#define SCSI_Out_DBx__7__PC CYREG_PRT2_PC2
+#define SCSI_Out_DBx__7__PORT 2u
+#define SCSI_Out_DBx__7__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__7__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__7__SHIFT 2
+#define SCSI_Out_DBx__7__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB0__AG CYREG_PRT5_AG
+#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT5_AMUX
+#define SCSI_Out_DBx__DB0__BIE CYREG_PRT5_BIE
+#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_Out_DBx__DB0__BYP CYREG_PRT5_BYP
+#define SCSI_Out_DBx__DB0__CTL CYREG_PRT5_CTL
+#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT5_DM0
+#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT5_DM1
+#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT5_DM2
+#define SCSI_Out_DBx__DB0__DR CYREG_PRT5_DR
+#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_Out_DBx__DB0__MASK 0x02u
+#define SCSI_Out_DBx__DB0__PC CYREG_PRT5_PC1
+#define SCSI_Out_DBx__DB0__PORT 5u
+#define SCSI_Out_DBx__DB0__PRT CYREG_PRT5_PRT
+#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_Out_DBx__DB0__PS CYREG_PRT5_PS
+#define SCSI_Out_DBx__DB0__SHIFT 1
+#define SCSI_Out_DBx__DB0__SLW CYREG_PRT5_SLW
+#define SCSI_Out_DBx__DB1__AG CYREG_PRT5_AG
+#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT5_AMUX
+#define SCSI_Out_DBx__DB1__BIE CYREG_PRT5_BIE
+#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_Out_DBx__DB1__BYP CYREG_PRT5_BYP
+#define SCSI_Out_DBx__DB1__CTL CYREG_PRT5_CTL
+#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT5_DM0
+#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT5_DM1
+#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT5_DM2
+#define SCSI_Out_DBx__DB1__DR CYREG_PRT5_DR
+#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_Out_DBx__DB1__MASK 0x01u
+#define SCSI_Out_DBx__DB1__PC CYREG_PRT5_PC0
+#define SCSI_Out_DBx__DB1__PORT 5u
+#define SCSI_Out_DBx__DB1__PRT CYREG_PRT5_PRT
+#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_Out_DBx__DB1__PS CYREG_PRT5_PS
+#define SCSI_Out_DBx__DB1__SHIFT 0
+#define SCSI_Out_DBx__DB1__SLW CYREG_PRT5_SLW
+#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__DB2__MASK 0x20u
+#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC5
+#define SCSI_Out_DBx__DB2__PORT 6u
+#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__DB2__SHIFT 5
+#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__DB3__MASK 0x10u
+#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC4
+#define SCSI_Out_DBx__DB3__PORT 6u
+#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__DB3__SHIFT 4
+#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__DB4__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB4__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB4__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB4__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB4__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB4__MASK 0x80u
+#define SCSI_Out_DBx__DB4__PC CYREG_PRT2_PC7
+#define SCSI_Out_DBx__DB4__PORT 2u
+#define SCSI_Out_DBx__DB4__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB4__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB4__SHIFT 7
+#define SCSI_Out_DBx__DB4__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB5__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB5__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB5__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB5__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB5__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB5__MASK 0x40u
+#define SCSI_Out_DBx__DB5__PC CYREG_PRT2_PC6
+#define SCSI_Out_DBx__DB5__PORT 2u
+#define SCSI_Out_DBx__DB5__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB5__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB5__SHIFT 6
+#define SCSI_Out_DBx__DB5__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB6__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB6__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB6__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB6__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB6__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB6__MASK 0x08u
+#define SCSI_Out_DBx__DB6__PC CYREG_PRT2_PC3
+#define SCSI_Out_DBx__DB6__PORT 2u
+#define SCSI_Out_DBx__DB6__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB6__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB6__SHIFT 3
+#define SCSI_Out_DBx__DB6__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB7__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB7__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB7__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB7__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB7__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB7__MASK 0x04u
+#define SCSI_Out_DBx__DB7__PC CYREG_PRT2_PC2
+#define SCSI_Out_DBx__DB7__PORT 2u
+#define SCSI_Out_DBx__DB7__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB7__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB7__SHIFT 2
+#define SCSI_Out_DBx__DB7__SLW CYREG_PRT2_SLW
+
+/* SD_RX_DMA */
+#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define SD_RX_DMA__DRQ_NUMBER 2u
+#define SD_RX_DMA__NUMBEROF_TDS 0u
+#define SD_RX_DMA__PRIORITY 2u
+#define SD_RX_DMA__TERMIN_EN 0u
+#define SD_RX_DMA__TERMIN_SEL 0u
+#define SD_RX_DMA__TERMOUT0_EN 1u
+#define SD_RX_DMA__TERMOUT0_SEL 2u
+#define SD_RX_DMA__TERMOUT1_EN 0u
+#define SD_RX_DMA__TERMOUT1_SEL 0u
+
+/* SD_RX_DMA_COMPLETE */
+#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SD_RX_DMA_COMPLETE__INTC_MASK 0x10u
+#define SD_RX_DMA_COMPLETE__INTC_NUMBER 4u
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4
+#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* SD_TX_DMA */
+#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define SD_TX_DMA__DRQ_NUMBER 3u
+#define SD_TX_DMA__NUMBEROF_TDS 0u
+#define SD_TX_DMA__PRIORITY 2u
+#define SD_TX_DMA__TERMIN_EN 0u
+#define SD_TX_DMA__TERMIN_SEL 0u
+#define SD_TX_DMA__TERMOUT0_EN 1u
+#define SD_TX_DMA__TERMOUT0_SEL 3u
+#define SD_TX_DMA__TERMOUT1_EN 0u
+#define SD_TX_DMA__TERMOUT1_SEL 0u
+
+/* SD_TX_DMA_COMPLETE */
+#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SD_TX_DMA_COMPLETE__INTC_MASK 0x20u
+#define SD_TX_DMA_COMPLETE__INTC_NUMBER 5u
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5
+#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* SCSI_Noise */
+#define SCSI_Noise__0__AG CYREG_PRT2_AG
+#define SCSI_Noise__0__AMUX CYREG_PRT2_AMUX
+#define SCSI_Noise__0__BIE CYREG_PRT2_BIE
+#define SCSI_Noise__0__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Noise__0__BYP CYREG_PRT2_BYP
+#define SCSI_Noise__0__CTL CYREG_PRT2_CTL
+#define SCSI_Noise__0__DM0 CYREG_PRT2_DM0
+#define SCSI_Noise__0__DM1 CYREG_PRT2_DM1
+#define SCSI_Noise__0__DM2 CYREG_PRT2_DM2
+#define SCSI_Noise__0__DR CYREG_PRT2_DR
+#define SCSI_Noise__0__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Noise__0__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Noise__0__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Noise__0__MASK 0x01u
+#define SCSI_Noise__0__PC CYREG_PRT2_PC0
+#define SCSI_Noise__0__PORT 2u
+#define SCSI_Noise__0__PRT CYREG_PRT2_PRT
+#define SCSI_Noise__0__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Noise__0__PS CYREG_PRT2_PS
+#define SCSI_Noise__0__SHIFT 0
+#define SCSI_Noise__0__SLW CYREG_PRT2_SLW
+#define SCSI_Noise__1__AG CYREG_PRT6_AG
+#define SCSI_Noise__1__AMUX CYREG_PRT6_AMUX
+#define SCSI_Noise__1__BIE CYREG_PRT6_BIE
+#define SCSI_Noise__1__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Noise__1__BYP CYREG_PRT6_BYP
+#define SCSI_Noise__1__CTL CYREG_PRT6_CTL
+#define SCSI_Noise__1__DM0 CYREG_PRT6_DM0
+#define SCSI_Noise__1__DM1 CYREG_PRT6_DM1
+#define SCSI_Noise__1__DM2 CYREG_PRT6_DM2
+#define SCSI_Noise__1__DR CYREG_PRT6_DR
+#define SCSI_Noise__1__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Noise__1__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Noise__1__MASK 0x08u
+#define SCSI_Noise__1__PC CYREG_PRT6_PC3
+#define SCSI_Noise__1__PORT 6u
+#define SCSI_Noise__1__PRT CYREG_PRT6_PRT
+#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Noise__1__PS CYREG_PRT6_PS
+#define SCSI_Noise__1__SHIFT 3
+#define SCSI_Noise__1__SLW CYREG_PRT6_SLW
+#define SCSI_Noise__2__AG CYREG_PRT4_AG
+#define SCSI_Noise__2__AMUX CYREG_PRT4_AMUX
+#define SCSI_Noise__2__BIE CYREG_PRT4_BIE
+#define SCSI_Noise__2__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Noise__2__BYP CYREG_PRT4_BYP
+#define SCSI_Noise__2__CTL CYREG_PRT4_CTL
+#define SCSI_Noise__2__DM0 CYREG_PRT4_DM0
+#define SCSI_Noise__2__DM1 CYREG_PRT4_DM1
+#define SCSI_Noise__2__DM2 CYREG_PRT4_DM2
+#define SCSI_Noise__2__DR CYREG_PRT4_DR
+#define SCSI_Noise__2__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Noise__2__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Noise__2__MASK 0x08u
+#define SCSI_Noise__2__PC CYREG_PRT4_PC3
+#define SCSI_Noise__2__PORT 4u
+#define SCSI_Noise__2__PRT CYREG_PRT4_PRT
+#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Noise__2__PS CYREG_PRT4_PS
+#define SCSI_Noise__2__SHIFT 3
+#define SCSI_Noise__2__SLW CYREG_PRT4_SLW
+#define SCSI_Noise__3__AG CYREG_PRT4_AG
+#define SCSI_Noise__3__AMUX CYREG_PRT4_AMUX
+#define SCSI_Noise__3__BIE CYREG_PRT4_BIE
+#define SCSI_Noise__3__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Noise__3__BYP CYREG_PRT4_BYP
+#define SCSI_Noise__3__CTL CYREG_PRT4_CTL
+#define SCSI_Noise__3__DM0 CYREG_PRT4_DM0
+#define SCSI_Noise__3__DM1 CYREG_PRT4_DM1
+#define SCSI_Noise__3__DM2 CYREG_PRT4_DM2
+#define SCSI_Noise__3__DR CYREG_PRT4_DR
+#define SCSI_Noise__3__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Noise__3__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Noise__3__MASK 0x80u
+#define SCSI_Noise__3__PC CYREG_PRT4_PC7
+#define SCSI_Noise__3__PORT 4u
+#define SCSI_Noise__3__PRT CYREG_PRT4_PRT
+#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Noise__3__PS CYREG_PRT4_PS
+#define SCSI_Noise__3__SHIFT 7
+#define SCSI_Noise__3__SLW CYREG_PRT4_SLW
+#define SCSI_Noise__4__AG CYREG_PRT6_AG
+#define SCSI_Noise__4__AMUX CYREG_PRT6_AMUX
+#define SCSI_Noise__4__BIE CYREG_PRT6_BIE
+#define SCSI_Noise__4__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Noise__4__BYP CYREG_PRT6_BYP
+#define SCSI_Noise__4__CTL CYREG_PRT6_CTL
+#define SCSI_Noise__4__DM0 CYREG_PRT6_DM0
+#define SCSI_Noise__4__DM1 CYREG_PRT6_DM1
+#define SCSI_Noise__4__DM2 CYREG_PRT6_DM2
+#define SCSI_Noise__4__DR CYREG_PRT6_DR
+#define SCSI_Noise__4__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Noise__4__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Noise__4__MASK 0x04u
+#define SCSI_Noise__4__PC CYREG_PRT6_PC2
+#define SCSI_Noise__4__PORT 6u
+#define SCSI_Noise__4__PRT CYREG_PRT6_PRT
+#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Noise__4__PS CYREG_PRT6_PS
+#define SCSI_Noise__4__SHIFT 2
+#define SCSI_Noise__4__SLW CYREG_PRT6_SLW
+#define SCSI_Noise__ACK__AG CYREG_PRT6_AG
+#define SCSI_Noise__ACK__AMUX CYREG_PRT6_AMUX
+#define SCSI_Noise__ACK__BIE CYREG_PRT6_BIE
+#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Noise__ACK__BYP CYREG_PRT6_BYP
+#define SCSI_Noise__ACK__CTL CYREG_PRT6_CTL
+#define SCSI_Noise__ACK__DM0 CYREG_PRT6_DM0
+#define SCSI_Noise__ACK__DM1 CYREG_PRT6_DM1
+#define SCSI_Noise__ACK__DM2 CYREG_PRT6_DM2
+#define SCSI_Noise__ACK__DR CYREG_PRT6_DR
+#define SCSI_Noise__ACK__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Noise__ACK__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Noise__ACK__MASK 0x04u
+#define SCSI_Noise__ACK__PC CYREG_PRT6_PC2
+#define SCSI_Noise__ACK__PORT 6u
+#define SCSI_Noise__ACK__PRT CYREG_PRT6_PRT
+#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Noise__ACK__PS CYREG_PRT6_PS
+#define SCSI_Noise__ACK__SHIFT 2
+#define SCSI_Noise__ACK__SLW CYREG_PRT6_SLW
+#define SCSI_Noise__ATN__AG CYREG_PRT2_AG
+#define SCSI_Noise__ATN__AMUX CYREG_PRT2_AMUX
+#define SCSI_Noise__ATN__BIE CYREG_PRT2_BIE
+#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Noise__ATN__BYP CYREG_PRT2_BYP
+#define SCSI_Noise__ATN__CTL CYREG_PRT2_CTL
+#define SCSI_Noise__ATN__DM0 CYREG_PRT2_DM0
+#define SCSI_Noise__ATN__DM1 CYREG_PRT2_DM1
+#define SCSI_Noise__ATN__DM2 CYREG_PRT2_DM2
+#define SCSI_Noise__ATN__DR CYREG_PRT2_DR
+#define SCSI_Noise__ATN__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Noise__ATN__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Noise__ATN__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Noise__ATN__MASK 0x01u
+#define SCSI_Noise__ATN__PC CYREG_PRT2_PC0
+#define SCSI_Noise__ATN__PORT 2u
+#define SCSI_Noise__ATN__PRT CYREG_PRT2_PRT
+#define SCSI_Noise__ATN__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Noise__ATN__PS CYREG_PRT2_PS
+#define SCSI_Noise__ATN__SHIFT 0
+#define SCSI_Noise__ATN__SLW CYREG_PRT2_SLW
+#define SCSI_Noise__BSY__AG CYREG_PRT6_AG
+#define SCSI_Noise__BSY__AMUX CYREG_PRT6_AMUX
+#define SCSI_Noise__BSY__BIE CYREG_PRT6_BIE
+#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Noise__BSY__BYP CYREG_PRT6_BYP
+#define SCSI_Noise__BSY__CTL CYREG_PRT6_CTL
+#define SCSI_Noise__BSY__DM0 CYREG_PRT6_DM0
+#define SCSI_Noise__BSY__DM1 CYREG_PRT6_DM1
+#define SCSI_Noise__BSY__DM2 CYREG_PRT6_DM2
+#define SCSI_Noise__BSY__DR CYREG_PRT6_DR
+#define SCSI_Noise__BSY__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Noise__BSY__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Noise__BSY__MASK 0x08u
+#define SCSI_Noise__BSY__PC CYREG_PRT6_PC3
+#define SCSI_Noise__BSY__PORT 6u
+#define SCSI_Noise__BSY__PRT CYREG_PRT6_PRT
+#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Noise__BSY__PS CYREG_PRT6_PS
+#define SCSI_Noise__BSY__SHIFT 3
+#define SCSI_Noise__BSY__SLW CYREG_PRT6_SLW
+#define SCSI_Noise__RST__AG CYREG_PRT4_AG
+#define SCSI_Noise__RST__AMUX CYREG_PRT4_AMUX
+#define SCSI_Noise__RST__BIE CYREG_PRT4_BIE
+#define SCSI_Noise__RST__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Noise__RST__BYP CYREG_PRT4_BYP
+#define SCSI_Noise__RST__CTL CYREG_PRT4_CTL
+#define SCSI_Noise__RST__DM0 CYREG_PRT4_DM0
+#define SCSI_Noise__RST__DM1 CYREG_PRT4_DM1
+#define SCSI_Noise__RST__DM2 CYREG_PRT4_DM2
+#define SCSI_Noise__RST__DR CYREG_PRT4_DR
+#define SCSI_Noise__RST__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Noise__RST__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Noise__RST__MASK 0x80u
+#define SCSI_Noise__RST__PC CYREG_PRT4_PC7
+#define SCSI_Noise__RST__PORT 4u
+#define SCSI_Noise__RST__PRT CYREG_PRT4_PRT
+#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Noise__RST__PS CYREG_PRT4_PS
+#define SCSI_Noise__RST__SHIFT 7
+#define SCSI_Noise__RST__SLW CYREG_PRT4_SLW
+#define SCSI_Noise__SEL__AG CYREG_PRT4_AG
+#define SCSI_Noise__SEL__AMUX CYREG_PRT4_AMUX
+#define SCSI_Noise__SEL__BIE CYREG_PRT4_BIE
+#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT4_BIT_MASK
+#define SCSI_Noise__SEL__BYP CYREG_PRT4_BYP
+#define SCSI_Noise__SEL__CTL CYREG_PRT4_CTL
+#define SCSI_Noise__SEL__DM0 CYREG_PRT4_DM0
+#define SCSI_Noise__SEL__DM1 CYREG_PRT4_DM1
+#define SCSI_Noise__SEL__DM2 CYREG_PRT4_DM2
+#define SCSI_Noise__SEL__DR CYREG_PRT4_DR
+#define SCSI_Noise__SEL__INP_DIS CYREG_PRT4_INP_DIS
+#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG
+#define SCSI_Noise__SEL__LCD_EN CYREG_PRT4_LCD_EN
+#define SCSI_Noise__SEL__MASK 0x08u
+#define SCSI_Noise__SEL__PC CYREG_PRT4_PC3
+#define SCSI_Noise__SEL__PORT 4u
+#define SCSI_Noise__SEL__PRT CYREG_PRT4_PRT
+#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL
+#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN
+#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0
+#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1
+#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0
+#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1
+#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT
+#define SCSI_Noise__SEL__PS CYREG_PRT4_PS
+#define SCSI_Noise__SEL__SHIFT 3
+#define SCSI_Noise__SEL__SLW CYREG_PRT4_SLW
+
+/* scsiTarget */
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB11_12_A0
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB11_12_A1
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB11_12_D0
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB11_12_D1
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB11_12_F0
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB11_12_F1
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB11_A0_A1
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB11_A0
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB11_A1
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB11_D0_D1
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB11_D0
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB11_D1
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB11_F0_F1
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB11_F0
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB11_F1
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB11_MSK
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB11_ST
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB11_CTL
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB11_CTL
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB11_MSK
+#define scsiTarget_StatusReg__0__MASK 0x01u
+#define scsiTarget_StatusReg__0__POS 0
+#define scsiTarget_StatusReg__1__MASK 0x02u
+#define scsiTarget_StatusReg__1__POS 1
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST
+#define scsiTarget_StatusReg__2__MASK 0x04u
+#define scsiTarget_StatusReg__2__POS 2
+#define scsiTarget_StatusReg__3__MASK 0x08u
+#define scsiTarget_StatusReg__3__POS 3
+#define scsiTarget_StatusReg__4__MASK 0x10u
+#define scsiTarget_StatusReg__4__POS 4
+#define scsiTarget_StatusReg__MASK 0x1Fu
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB00_MSK
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB00_ST
-/* SD_MOSI */
-#define SD_MOSI__0__MASK 0x08u
-#define SD_MOSI__0__PC CYREG_PRT3_PC3
-#define SD_MOSI__0__PORT 3u
-#define SD_MOSI__0__SHIFT 3
-#define SD_MOSI__AG CYREG_PRT3_AG
-#define SD_MOSI__AMUX CYREG_PRT3_AMUX
-#define SD_MOSI__BIE CYREG_PRT3_BIE
-#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_MOSI__BYP CYREG_PRT3_BYP
-#define SD_MOSI__CTL CYREG_PRT3_CTL
-#define SD_MOSI__DM0 CYREG_PRT3_DM0
-#define SD_MOSI__DM1 CYREG_PRT3_DM1
-#define SD_MOSI__DM2 CYREG_PRT3_DM2
-#define SD_MOSI__DR CYREG_PRT3_DR
-#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_MOSI__MASK 0x08u
-#define SD_MOSI__PORT 3u
-#define SD_MOSI__PRT CYREG_PRT3_PRT
-#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_MOSI__PS CYREG_PRT3_PS
-#define SD_MOSI__SHIFT 3
-#define SD_MOSI__SLW CYREG_PRT3_SLW
+/* Debug_Timer_Interrupt */
+#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define Debug_Timer_Interrupt__INTC_MASK 0x02u
+#define Debug_Timer_Interrupt__INTC_NUMBER 1u
+#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u
+#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1
+#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* Debug_Timer_TimerHW */
+#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0
+#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1
+#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0
+#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1
+#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2
+#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0
+#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1
+#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0
+#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1
+#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3
+#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u
+#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3
+#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u
+#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0
+#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1
+#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0
+
+/* SCSI_RX_DMA */
+#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define SCSI_RX_DMA__DRQ_NUMBER 0u
+#define SCSI_RX_DMA__NUMBEROF_TDS 0u
+#define SCSI_RX_DMA__PRIORITY 2u
+#define SCSI_RX_DMA__TERMIN_EN 0u
+#define SCSI_RX_DMA__TERMIN_SEL 0u
+#define SCSI_RX_DMA__TERMOUT0_EN 1u
+#define SCSI_RX_DMA__TERMOUT0_SEL 0u
+#define SCSI_RX_DMA__TERMOUT1_EN 0u
+#define SCSI_RX_DMA__TERMOUT1_SEL 0u
+
+/* SCSI_RX_DMA_COMPLETE */
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x01u
+#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 0u
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_0
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* SCSI_TX_DMA */
+#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0
+#define SCSI_TX_DMA__DRQ_NUMBER 1u
+#define SCSI_TX_DMA__NUMBEROF_TDS 0u
+#define SCSI_TX_DMA__PRIORITY 2u
+#define SCSI_TX_DMA__TERMIN_EN 0u
+#define SCSI_TX_DMA__TERMIN_SEL 0u
+#define SCSI_TX_DMA__TERMOUT0_EN 1u
+#define SCSI_TX_DMA__TERMOUT0_SEL 1u
+#define SCSI_TX_DMA__TERMOUT1_EN 0u
+#define SCSI_TX_DMA__TERMOUT1_SEL 0u
+
+/* SCSI_TX_DMA_COMPLETE */
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x08u
+#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 3u
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u
+#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_3
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* SD_Data_Clk */
+#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0
+#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1
+#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2
+#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u
+#define SD_Data_Clk__INDEX 0x00u
+#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2
+#define SD_Data_Clk__PM_ACT_MSK 0x01u
+#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2
+#define SD_Data_Clk__PM_STBY_MSK 0x01u
-/* EXTLED */
-#define EXTLED__0__MASK 0x01u
-#define EXTLED__0__PC CYREG_PRT0_PC0
-#define EXTLED__0__PORT 0u
-#define EXTLED__0__SHIFT 0
-#define EXTLED__AG CYREG_PRT0_AG
-#define EXTLED__AMUX CYREG_PRT0_AMUX
-#define EXTLED__BIE CYREG_PRT0_BIE
-#define EXTLED__BIT_MASK CYREG_PRT0_BIT_MASK
-#define EXTLED__BYP CYREG_PRT0_BYP
-#define EXTLED__CTL CYREG_PRT0_CTL
-#define EXTLED__DM0 CYREG_PRT0_DM0
-#define EXTLED__DM1 CYREG_PRT0_DM1
-#define EXTLED__DM2 CYREG_PRT0_DM2
-#define EXTLED__DR CYREG_PRT0_DR
-#define EXTLED__INP_DIS CYREG_PRT0_INP_DIS
-#define EXTLED__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define EXTLED__LCD_EN CYREG_PRT0_LCD_EN
-#define EXTLED__MASK 0x01u
-#define EXTLED__PORT 0u
-#define EXTLED__PRT CYREG_PRT0_PRT
-#define EXTLED__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define EXTLED__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define EXTLED__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define EXTLED__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define EXTLED__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define EXTLED__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define EXTLED__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define EXTLED__PS CYREG_PRT0_PS
-#define EXTLED__SHIFT 0
-#define EXTLED__SLW CYREG_PRT0_SLW
+/* timer_clock */
+#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0
+#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1
+#define timer_clock__CFG2 CYREG_CLKDIST_DCFG2_CFG2
+#define timer_clock__CFG2_SRC_SEL_MASK 0x07u
+#define timer_clock__INDEX 0x02u
+#define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2
+#define timer_clock__PM_ACT_MSK 0x04u
+#define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2
+#define timer_clock__PM_STBY_MSK 0x04u
-/* SD_SCK */
-#define SD_SCK__0__MASK 0x04u
-#define SD_SCK__0__PC CYREG_PRT3_PC2
-#define SD_SCK__0__PORT 3u
-#define SD_SCK__0__SHIFT 2
-#define SD_SCK__AG CYREG_PRT3_AG
-#define SD_SCK__AMUX CYREG_PRT3_AMUX
-#define SD_SCK__BIE CYREG_PRT3_BIE
-#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_SCK__BYP CYREG_PRT3_BYP
-#define SD_SCK__CTL CYREG_PRT3_CTL
-#define SD_SCK__DM0 CYREG_PRT3_DM0
-#define SD_SCK__DM1 CYREG_PRT3_DM1
-#define SD_SCK__DM2 CYREG_PRT3_DM2
-#define SD_SCK__DR CYREG_PRT3_DR
-#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_SCK__MASK 0x04u
-#define SD_SCK__PORT 3u
-#define SD_SCK__PRT CYREG_PRT3_PRT
-#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_SCK__PS CYREG_PRT3_PS
-#define SD_SCK__SHIFT 2
-#define SD_SCK__SLW CYREG_PRT3_SLW
+/* SCSI_RST_ISR */
+#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define SCSI_RST_ISR__INTC_MASK 0x04u
+#define SCSI_RST_ISR__INTC_NUMBER 2u
+#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u
+#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_2
+#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-/* SD_CD */
-#define SD_CD__0__MASK 0x20u
-#define SD_CD__0__PC CYREG_PRT3_PC5
-#define SD_CD__0__PORT 3u
-#define SD_CD__0__SHIFT 5
-#define SD_CD__AG CYREG_PRT3_AG
-#define SD_CD__AMUX CYREG_PRT3_AMUX
-#define SD_CD__BIE CYREG_PRT3_BIE
-#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_CD__BYP CYREG_PRT3_BYP
-#define SD_CD__CTL CYREG_PRT3_CTL
-#define SD_CD__DM0 CYREG_PRT3_DM0
-#define SD_CD__DM1 CYREG_PRT3_DM1
-#define SD_CD__DM2 CYREG_PRT3_DM2
-#define SD_CD__DR CYREG_PRT3_DR
-#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_CD__MASK 0x20u
-#define SD_CD__PORT 3u
-#define SD_CD__PRT CYREG_PRT3_PRT
-#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_CD__PS CYREG_PRT3_PS
-#define SD_CD__SHIFT 5
-#define SD_CD__SLW CYREG_PRT3_SLW
+/* SCSI_Filtered */
+#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u
+#define SCSI_Filtered_sts_sts_reg__0__POS 0
+#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
+#define SCSI_Filtered_sts_sts_reg__1__POS 1
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
+#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
+#define SCSI_Filtered_sts_sts_reg__2__POS 2
+#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
+#define SCSI_Filtered_sts_sts_reg__3__POS 3
+#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
+#define SCSI_Filtered_sts_sts_reg__4__POS 4
+#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB04_MSK
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB04_ST
-/* SD_CS */
-#define SD_CS__0__MASK 0x10u
-#define SD_CS__0__PC CYREG_PRT3_PC4
-#define SD_CS__0__PORT 3u
-#define SD_CS__0__SHIFT 4
-#define SD_CS__AG CYREG_PRT3_AG
-#define SD_CS__AMUX CYREG_PRT3_AMUX
-#define SD_CS__BIE CYREG_PRT3_BIE
-#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_CS__BYP CYREG_PRT3_BYP
-#define SD_CS__CTL CYREG_PRT3_CTL
-#define SD_CS__DM0 CYREG_PRT3_DM0
-#define SD_CS__DM1 CYREG_PRT3_DM1
-#define SD_CS__DM2 CYREG_PRT3_DM2
-#define SD_CS__DR CYREG_PRT3_DR
-#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_CS__MASK 0x10u
-#define SD_CS__PORT 3u
-#define SD_CS__PRT CYREG_PRT3_PRT
-#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_CS__PS CYREG_PRT3_PS
-#define SD_CS__SHIFT 4
-#define SD_CS__SLW CYREG_PRT3_SLW
+/* SCSI_CTL_PHASE */
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
-/* LED1 */
-#define LED1__0__MASK 0x02u
-#define LED1__0__PC CYREG_PRT0_PC1
-#define LED1__0__PORT 0u
-#define LED1__0__SHIFT 1
-#define LED1__AG CYREG_PRT0_AG
-#define LED1__AMUX CYREG_PRT0_AMUX
-#define LED1__BIE CYREG_PRT0_BIE
-#define LED1__BIT_MASK CYREG_PRT0_BIT_MASK
-#define LED1__BYP CYREG_PRT0_BYP
-#define LED1__CTL CYREG_PRT0_CTL
-#define LED1__DM0 CYREG_PRT0_DM0
-#define LED1__DM1 CYREG_PRT0_DM1
-#define LED1__DM2 CYREG_PRT0_DM2
-#define LED1__DR CYREG_PRT0_DR
-#define LED1__INP_DIS CYREG_PRT0_INP_DIS
-#define LED1__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define LED1__LCD_EN CYREG_PRT0_LCD_EN
-#define LED1__MASK 0x02u
-#define LED1__PORT 0u
-#define LED1__PRT CYREG_PRT0_PRT
-#define LED1__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define LED1__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define LED1__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define LED1__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define LED1__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define LED1__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define LED1__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define LED1__PS CYREG_PRT0_PS
-#define LED1__SHIFT 1
-#define LED1__SLW CYREG_PRT0_SLW
+/* SCSI_Parity_Error */
+#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
+#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
+#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB03_MSK
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB03_ST
/* Miscellaneous */
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
-#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
-#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
-#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
-#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
-#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
-#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
-#define CYDEV_CHIP_MEMBER_5B 4u
-#define CYDEV_CHIP_FAMILY_PSOC5 3u
-#define CYDEV_CHIP_DIE_PSOC5LP 4u
-#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP
#define BCLK__BUS_CLK__HZ 50000000U
#define BCLK__BUS_CLK__KHZ 50000U
#define BCLK__BUS_CLK__MHZ 50U
-#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
+#define CY_VERSION "PSoC Creator 3.1"
#define CYDEV_CHIP_DIE_LEOPARD 1u
-#define CYDEV_CHIP_DIE_PANTHER 3u
-#define CYDEV_CHIP_DIE_PSOC4A 2u
+#define CYDEV_CHIP_DIE_PANTHER 6u
+#define CYDEV_CHIP_DIE_PSOC4A 3u
+#define CYDEV_CHIP_DIE_PSOC5LP 5u
#define CYDEV_CHIP_DIE_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_PSOC3 1u
#define CYDEV_CHIP_FAMILY_PSOC4 2u
+#define CYDEV_CHIP_FAMILY_PSOC5 3u
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
#define CYDEV_CHIP_JTAG_ID 0x2E133069u
#define CYDEV_CHIP_MEMBER_3A 1u
-#define CYDEV_CHIP_MEMBER_4A 2u
-#define CYDEV_CHIP_MEMBER_5A 3u
+#define CYDEV_CHIP_MEMBER_4A 3u
+#define CYDEV_CHIP_MEMBER_4D 2u
+#define CYDEV_CHIP_MEMBER_4F 4u
+#define CYDEV_CHIP_MEMBER_5A 6u
+#define CYDEV_CHIP_MEMBER_5B 5u
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
+#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
+#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
+#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
+#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
+#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
+#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
+#define CYDEV_CHIP_REV_PANTHER_ES0 0u
+#define CYDEV_CHIP_REV_PANTHER_ES1 1u
+#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
+#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
+#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
+#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
+#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_3A_ES1 0u
#define CYDEV_CHIP_REVISION_3A_ES2 1u
#define CYDEV_CHIP_REVISION_3A_ES3 3u
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
#define CYDEV_CHIP_REVISION_4A_ES0 17u
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
+#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_5A_ES0 0u
#define CYDEV_CHIP_REVISION_5A_ES1 1u
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
#define CYDEV_CHIP_REVISION_5B_ES0 0u
+#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION
-#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
-#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
-#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
-#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
-#define CYDEV_CHIP_REV_PANTHER_ES0 0u
-#define CYDEV_CHIP_REV_PANTHER_ES1 1u
-#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
-#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
-#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
-#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
+#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
+#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
+#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
+#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
+#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
#define CYDEV_CONFIGURATION_COMPRESSED 1
#define CYDEV_CONFIGURATION_DMA 0
#define CYDEV_CONFIGURATION_ECC 0
#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED
+#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
#define CYDEV_CONFIGURATION_MODE_DMA 2
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
-#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
-#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
-#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
+#define CYDEV_DEBUG_ENABLE_MASK 0x20u
+#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
#define CYDEV_DEBUGGING_DPS_Disable 3
#define CYDEV_DEBUGGING_DPS_JTAG_4 1
#define CYDEV_DEBUGGING_DPS_JTAG_5 0
#define CYDEV_DEBUGGING_DPS_SWD 2
+#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
+#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
#define CYDEV_DEBUGGING_ENABLE 1
#define CYDEV_DEBUGGING_XRES 0
-#define CYDEV_DEBUG_ENABLE_MASK 0x20u
-#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
#define CYDEV_DMA_CHANNELS_AVAILABLE 24u
#define CYDEV_ECC_ENABLE 0
-#define CYDEV_HEAP_SIZE 0x1000
+#define CYDEV_HEAP_SIZE 0x0400
#define CYDEV_INSTRUCT_CACHE_ENABLED 1
#define CYDEV_INTR_RISING 0x0000003Eu
#define CYDEV_PROJ_TYPE 2
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
#define CYDEV_PROJ_TYPE_STANDARD 0
#define CYDEV_PROTECTION_ENABLE 0
-#define CYDEV_STACK_SIZE 0x4000
+#define CYDEV_STACK_SIZE 0x1000
#define CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP
#define CYDEV_USE_BUNDLED_CMSIS 1
#define CYDEV_VARIABLE_VDDA 0
#define CYDEV_VDDIO2_MV 5000
#define CYDEV_VDDIO3 3.3
#define CYDEV_VDDIO3_MV 3300
-#define CYDEV_VIO0 5
+#define CYDEV_VIO0 5.0
#define CYDEV_VIO0_MV 5000
-#define CYDEV_VIO1 5
+#define CYDEV_VIO1 5.0
#define CYDEV_VIO1_MV 5000
-#define CYDEV_VIO2 5
+#define CYDEV_VIO2 5.0
#define CYDEV_VIO2_MV 5000
#define CYDEV_VIO3 3.3
#define CYDEV_VIO3_MV 3300
+#define CYIPBLOCK_ARM_CM3_VERSION 0
+#define CYIPBLOCK_P3_ANAIF_VERSION 0
+#define CYIPBLOCK_P3_CAPSENSE_VERSION 0
+#define CYIPBLOCK_P3_COMP_VERSION 0
+#define CYIPBLOCK_P3_DMA_VERSION 0
+#define CYIPBLOCK_P3_DRQ_VERSION 0
+#define CYIPBLOCK_P3_EMIF_VERSION 0
+#define CYIPBLOCK_P3_I2C_VERSION 0
+#define CYIPBLOCK_P3_LCD_VERSION 0
+#define CYIPBLOCK_P3_LPF_VERSION 0
+#define CYIPBLOCK_P3_PM_VERSION 0
+#define CYIPBLOCK_P3_TIMER_VERSION 0
+#define CYIPBLOCK_P3_USB_VERSION 0
+#define CYIPBLOCK_P3_VIDAC_VERSION 0
+#define CYIPBLOCK_P3_VREF_VERSION 0
+#define CYIPBLOCK_S8_GPIO_VERSION 0
+#define CYIPBLOCK_S8_IRQ_VERSION 0
+#define CYIPBLOCK_S8_SAR_VERSION 0
+#define CYIPBLOCK_S8_SIO_VERSION 0
+#define CYIPBLOCK_S8_UDB_VERSION 0
#define DMA_CHANNELS_USED__MASK0 0x0000000Fu
#define CYDEV_BOOTLOADER_ENABLE 0
/*******************************************************************************
* FILENAME: cyfitter_cfg.c
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator 3.1
*
* Description:
* This file is automatically generated by PSoC Creator with device
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x40004501u, /* Base address: 0x40004500 Count: 1 */
0x40004F02u, /* Base address: 0x40004F00 Count: 2 */
- 0x40005210u, /* Base address: 0x40005200 Count: 16 */
+ 0x4000520Fu, /* Base address: 0x40005200 Count: 15 */
0x40006401u, /* Base address: 0x40006400 Count: 1 */
0x40006501u, /* Base address: 0x40006500 Count: 1 */
- 0x40010046u, /* Base address: 0x40010000 Count: 70 */
- 0x4001013Bu, /* Base address: 0x40010100 Count: 59 */
- 0x40010249u, /* Base address: 0x40010200 Count: 73 */
- 0x4001035Bu, /* Base address: 0x40010300 Count: 91 */
- 0x4001044Fu, /* Base address: 0x40010400 Count: 79 */
- 0x40010551u, /* Base address: 0x40010500 Count: 81 */
- 0x40010715u, /* Base address: 0x40010700 Count: 21 */
- 0x4001081Bu, /* Base address: 0x40010800 Count: 27 */
- 0x40010955u, /* Base address: 0x40010900 Count: 85 */
- 0x40010A48u, /* Base address: 0x40010A00 Count: 72 */
- 0x40010B56u, /* Base address: 0x40010B00 Count: 86 */
- 0x40010C42u, /* Base address: 0x40010C00 Count: 66 */
- 0x40010D59u, /* Base address: 0x40010D00 Count: 89 */
- 0x40010E4Au, /* Base address: 0x40010E00 Count: 74 */
- 0x40010F33u, /* Base address: 0x40010F00 Count: 51 */
- 0x4001150Du, /* Base address: 0x40011500 Count: 13 */
- 0x4001170Au, /* Base address: 0x40011700 Count: 10 */
- 0x40011858u, /* Base address: 0x40011800 Count: 88 */
- 0x40011949u, /* Base address: 0x40011900 Count: 73 */
- 0x40011A53u, /* Base address: 0x40011A00 Count: 83 */
- 0x40011B4Bu, /* Base address: 0x40011B00 Count: 75 */
- 0x40014019u, /* Base address: 0x40014000 Count: 25 */
+ 0x40010050u, /* Base address: 0x40010000 Count: 80 */
+ 0x4001013Eu, /* Base address: 0x40010100 Count: 62 */
+ 0x4001024Eu, /* Base address: 0x40010200 Count: 78 */
+ 0x40010358u, /* Base address: 0x40010300 Count: 88 */
+ 0x40010450u, /* Base address: 0x40010400 Count: 80 */
+ 0x4001054Eu, /* Base address: 0x40010500 Count: 78 */
+ 0x4001070Fu, /* Base address: 0x40010700 Count: 15 */
+ 0x4001084Bu, /* Base address: 0x40010800 Count: 75 */
+ 0x40010942u, /* Base address: 0x40010900 Count: 66 */
+ 0x40010A39u, /* Base address: 0x40010A00 Count: 57 */
+ 0x40010B50u, /* Base address: 0x40010B00 Count: 80 */
+ 0x40010C52u, /* Base address: 0x40010C00 Count: 82 */
+ 0x40010D54u, /* Base address: 0x40010D00 Count: 84 */
+ 0x40010E46u, /* Base address: 0x40010E00 Count: 70 */
+ 0x40010F3Du, /* Base address: 0x40010F00 Count: 61 */
+ 0x40011505u, /* Base address: 0x40011500 Count: 5 */
+ 0x40011703u, /* Base address: 0x40011700 Count: 3 */
+ 0x40011857u, /* Base address: 0x40011800 Count: 87 */
+ 0x40011941u, /* Base address: 0x40011900 Count: 65 */
+ 0x40011A4Bu, /* Base address: 0x40011A00 Count: 75 */
+ 0x40011B48u, /* Base address: 0x40011B00 Count: 72 */
+ 0x40014014u, /* Base address: 0x40014000 Count: 20 */
0x4001411Bu, /* Base address: 0x40014100 Count: 27 */
- 0x4001420Fu, /* Base address: 0x40014200 Count: 15 */
- 0x40014308u, /* Base address: 0x40014300 Count: 8 */
+ 0x40014217u, /* Base address: 0x40014200 Count: 23 */
+ 0x4001430Au, /* Base address: 0x40014300 Count: 10 */
0x40014414u, /* Base address: 0x40014400 Count: 20 */
- 0x4001451Cu, /* Base address: 0x40014500 Count: 28 */
+ 0x40014519u, /* Base address: 0x40014500 Count: 25 */
0x4001460Fu, /* Base address: 0x40014600 Count: 15 */
- 0x40014715u, /* Base address: 0x40014700 Count: 21 */
- 0x40014805u, /* Base address: 0x40014800 Count: 5 */
- 0x4001490Cu, /* Base address: 0x40014900 Count: 12 */
- 0x40014C03u, /* Base address: 0x40014C00 Count: 3 */
- 0x40014D0Bu, /* Base address: 0x40014D00 Count: 11 */
- 0x40015002u, /* Base address: 0x40015000 Count: 2 */
+ 0x4001470Eu, /* Base address: 0x40014700 Count: 14 */
+ 0x40014809u, /* Base address: 0x40014800 Count: 9 */
+ 0x4001490Eu, /* Base address: 0x40014900 Count: 14 */
+ 0x40014C07u, /* Base address: 0x40014C00 Count: 7 */
+ 0x40014D0Au, /* Base address: 0x40014D00 Count: 10 */
+ 0x40015004u, /* Base address: 0x40015000 Count: 4 */
0x40015104u, /* Base address: 0x40015100 Count: 4 */
};
{0x7Eu, 0x02u},
{0x01u, 0x20u},
{0x0Au, 0x4Bu},
- {0x00u, 0x08u},
- {0x01u, 0x44u},
+ {0x00u, 0x01u},
+ {0x01u, 0x48u},
{0x04u, 0x31u},
- {0x10u, 0xC0u},
- {0x11u, 0x88u},
- {0x18u, 0x08u},
- {0x19u, 0x04u},
+ {0x10u, 0xC8u},
+ {0x11u, 0x48u},
+ {0x18u, 0x04u},
+ {0x19u, 0x08u},
{0x1Cu, 0x30u},
{0x20u, 0x10u},
- {0x21u, 0x10u},
{0x24u, 0x44u},
- {0x28u, 0x01u},
- {0x30u, 0x10u},
- {0x31u, 0x30u},
+ {0x28u, 0x03u},
+ {0x29u, 0x02u},
+ {0x31u, 0x20u},
{0x78u, 0x20u},
{0x7Cu, 0x40u},
- {0x2Cu, 0x02u},
- {0x89u, 0x0Fu},
- {0x01u, 0x02u},
- {0x03u, 0x01u},
- {0x05u, 0x02u},
- {0x07u, 0x01u},
+ {0x2Bu, 0x02u},
+ {0x8Au, 0x0Fu},
+ {0x01u, 0x50u},
+ {0x03u, 0xA0u},
+ {0x05u, 0x06u},
+ {0x06u, 0x02u},
+ {0x07u, 0x09u},
+ {0x09u, 0x05u},
{0x0Au, 0x04u},
- {0x0Du, 0x04u},
- {0x0Fu, 0x08u},
- {0x12u, 0x08u},
- {0x16u, 0x01u},
- {0x17u, 0x08u},
- {0x19u, 0x01u},
- {0x1Bu, 0x02u},
- {0x1Fu, 0x04u},
- {0x21u, 0x02u},
+ {0x0Bu, 0x0Au},
+ {0x12u, 0x01u},
+ {0x15u, 0x60u},
+ {0x17u, 0x90u},
+ {0x1Bu, 0xFFu},
+ {0x1Cu, 0x04u},
+ {0x1Du, 0x30u},
+ {0x1Fu, 0xC0u},
+ {0x20u, 0x01u},
+ {0x21u, 0x03u},
{0x22u, 0x02u},
- {0x23u, 0x21u},
- {0x2Cu, 0x02u},
- {0x2Du, 0x02u},
- {0x2Eu, 0x04u},
- {0x2Fu, 0x11u},
- {0x30u, 0x01u},
- {0x31u, 0x20u},
- {0x33u, 0x10u},
- {0x34u, 0x08u},
- {0x35u, 0x03u},
- {0x36u, 0x06u},
- {0x37u, 0x0Cu},
- {0x3Bu, 0x20u},
- {0x3Eu, 0x40u},
- {0x3Fu, 0x40u},
+ {0x23u, 0x0Cu},
+ {0x24u, 0x04u},
+ {0x27u, 0xFFu},
+ {0x29u, 0xFFu},
+ {0x2Au, 0x04u},
+ {0x2Cu, 0x04u},
+ {0x2Du, 0x0Fu},
+ {0x2Fu, 0xF0u},
+ {0x30u, 0x03u},
+ {0x33u, 0xFFu},
+ {0x36u, 0x04u},
+ {0x39u, 0x20u},
+ {0x3Eu, 0x41u},
+ {0x3Fu, 0x14u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x99u},
{0x5Fu, 0x01u},
- {0x80u, 0x33u},
- {0x82u, 0xCCu},
- {0x83u, 0x10u},
- {0x87u, 0x10u},
- {0x88u, 0x0Fu},
- {0x89u, 0x19u},
- {0x8Au, 0xF0u},
- {0x8Bu, 0x02u},
- {0x8Du, 0x14u},
- {0x8Fu, 0x08u},
- {0x90u, 0x96u},
- {0x92u, 0x69u},
- {0x93u, 0x08u},
- {0x94u, 0x55u},
- {0x96u, 0xAAu},
- {0x98u, 0xFFu},
- {0x9Eu, 0xFFu},
- {0x9Fu, 0x07u},
- {0xA2u, 0xFFu},
- {0xA4u, 0xFFu},
- {0xA9u, 0x1Au},
+ {0x81u, 0x0Fu},
+ {0x83u, 0xF0u},
+ {0x87u, 0xFFu},
+ {0x88u, 0x09u},
+ {0x89u, 0xFFu},
+ {0x8Au, 0x06u},
+ {0x8Cu, 0x03u},
+ {0x8Du, 0x90u},
+ {0x8Eu, 0x0Cu},
+ {0x8Fu, 0x60u},
+ {0x90u, 0x50u},
+ {0x91u, 0x03u},
+ {0x92u, 0xA0u},
+ {0x93u, 0x0Cu},
+ {0x94u, 0x90u},
+ {0x96u, 0x60u},
+ {0x98u, 0x05u},
+ {0x99u, 0x05u},
+ {0x9Au, 0x0Au},
+ {0x9Bu, 0x0Au},
+ {0x9Cu, 0x30u},
+ {0x9Du, 0x50u},
+ {0x9Eu, 0xC0u},
+ {0x9Fu, 0xA0u},
+ {0xA0u, 0x0Fu},
+ {0xA1u, 0x30u},
+ {0xA2u, 0xF0u},
+ {0xA3u, 0xC0u},
+ {0xA5u, 0xFFu},
+ {0xA6u, 0xFFu},
+ {0xA9u, 0x09u},
{0xAAu, 0xFFu},
- {0xABu, 0x05u},
- {0xB1u, 0x0Fu},
- {0xB2u, 0xFFu},
- {0xB7u, 0x10u},
- {0xBAu, 0x08u},
- {0xBFu, 0x40u},
+ {0xABu, 0x06u},
+ {0xAEu, 0xFFu},
+ {0xB1u, 0xFFu},
+ {0xB4u, 0xFFu},
+ {0xBEu, 0x10u},
+ {0xBFu, 0x01u},
{0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x11u},
{0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x20u},
- {0x04u, 0x10u},
- {0x06u, 0x40u},
- {0x09u, 0x08u},
+ {0x03u, 0x18u},
+ {0x05u, 0x20u},
+ {0x06u, 0x06u},
+ {0x07u, 0x02u},
+ {0x09u, 0x80u},
{0x0Au, 0x80u},
- {0x0Cu, 0x01u},
- {0x0Du, 0x20u},
- {0x0Eu, 0x21u},
- {0x10u, 0x80u},
- {0x11u, 0x40u},
- {0x16u, 0xA4u},
- {0x19u, 0x01u},
- {0x1Au, 0x0Au},
- {0x1Cu, 0x10u},
- {0x1Fu, 0x04u},
- {0x21u, 0x0Du},
+ {0x0Cu, 0x90u},
+ {0x0Du, 0x19u},
+ {0x0Eu, 0x02u},
+ {0x0Fu, 0x08u},
+ {0x10u, 0x24u},
+ {0x12u, 0x41u},
+ {0x15u, 0x04u},
+ {0x16u, 0x68u},
+ {0x17u, 0x40u},
+ {0x18u, 0x80u},
+ {0x19u, 0x40u},
+ {0x1Fu, 0x20u},
{0x22u, 0x10u},
- {0x23u, 0x02u},
- {0x26u, 0x80u},
- {0x27u, 0x40u},
- {0x29u, 0x41u},
- {0x2Eu, 0x20u},
- {0x30u, 0x08u},
- {0x32u, 0x10u},
- {0x33u, 0x40u},
- {0x36u, 0x02u},
- {0x37u, 0x40u},
- {0x39u, 0x4Au},
- {0x3Du, 0x21u},
- {0x3Eu, 0x84u},
- {0x3Fu, 0x02u},
- {0x5Au, 0x61u},
- {0x5Bu, 0x08u},
- {0x5Fu, 0x80u},
- {0x63u, 0x02u},
+ {0x23u, 0x10u},
+ {0x26u, 0x02u},
+ {0x2Au, 0x6Au},
+ {0x2Cu, 0x80u},
+ {0x2Du, 0x24u},
+ {0x30u, 0x80u},
+ {0x31u, 0x08u},
+ {0x32u, 0x20u},
+ {0x34u, 0x90u},
+ {0x37u, 0x02u},
+ {0x39u, 0x22u},
+ {0x3Au, 0x04u},
+ {0x3Cu, 0x10u},
+ {0x3Du, 0x81u},
+ {0x3Eu, 0x08u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Au, 0x41u},
+ {0x5Bu, 0x20u},
+ {0x5Cu, 0x40u},
+ {0x61u, 0x40u},
{0x67u, 0x02u},
- {0x6Cu, 0x04u},
- {0x6Du, 0x04u},
- {0x6Fu, 0x22u},
- {0x80u, 0x02u},
- {0x82u, 0x40u},
- {0x83u, 0x01u},
- {0x86u, 0x01u},
- {0x87u, 0xA2u},
- {0x89u, 0x80u},
- {0x8Au, 0x40u},
- {0x8Bu, 0x08u},
- {0x8Cu, 0x44u},
- {0xC0u, 0x52u},
- {0xC2u, 0xFCu},
- {0xC4u, 0x79u},
- {0xCAu, 0x29u},
- {0xCCu, 0x9Eu},
- {0xCEu, 0xFBu},
+ {0x80u, 0x90u},
+ {0x82u, 0x20u},
+ {0x83u, 0x51u},
+ {0x85u, 0x01u},
+ {0x86u, 0x40u},
+ {0x8Au, 0x01u},
+ {0x8Bu, 0x04u},
+ {0x8Cu, 0x42u},
+ {0x8Eu, 0x70u},
+ {0x8Fu, 0x02u},
+ {0xC0u, 0xC6u},
+ {0xC2u, 0xF9u},
+ {0xC4u, 0xFFu},
+ {0xCAu, 0xEFu},
+ {0xCCu, 0xBEu},
+ {0xCEu, 0xF7u},
{0xD6u, 0x1Fu},
{0xD8u, 0x18u},
- {0xE2u, 0x16u},
- {0xE4u, 0x0Eu},
- {0xE6u, 0x11u},
- {0x01u, 0x04u},
- {0x04u, 0x36u},
- {0x06u, 0x49u},
+ {0xE2u, 0x4Cu},
+ {0xE4u, 0x04u},
+ {0xE6u, 0x01u},
+ {0x01u, 0x03u},
+ {0x02u, 0x01u},
+ {0x03u, 0x0Cu},
+ {0x09u, 0xFFu},
{0x0Au, 0x02u},
- {0x0Bu, 0x01u},
- {0x0Cu, 0x03u},
- {0x0Eu, 0x0Cu},
- {0x10u, 0x25u},
- {0x12u, 0x5Au},
- {0x14u, 0x10u},
- {0x16u, 0x60u},
- {0x17u, 0x02u},
- {0x18u, 0x10u},
- {0x1Bu, 0x08u},
- {0x1Eu, 0x13u},
- {0x20u, 0x27u},
- {0x22u, 0x58u},
- {0x24u, 0x01u},
- {0x30u, 0x0Fu},
- {0x31u, 0x04u},
- {0x32u, 0x70u},
- {0x33u, 0x01u},
- {0x35u, 0x02u},
- {0x37u, 0x08u},
- {0x3Au, 0x0Au},
- {0x56u, 0x08u},
- {0x58u, 0x04u},
- {0x59u, 0x04u},
- {0x5Bu, 0x04u},
- {0x5Cu, 0x91u},
- {0x5Du, 0x90u},
- {0x5Fu, 0x01u},
- {0x81u, 0x03u},
- {0x82u, 0x08u},
- {0x83u, 0x0Cu},
- {0x84u, 0x04u},
- {0x86u, 0x03u},
- {0x8Cu, 0x02u},
- {0x8Du, 0x0Fu},
- {0x8Eu, 0x04u},
- {0x8Fu, 0xF0u},
- {0x90u, 0x04u},
- {0x91u, 0x30u},
- {0x92u, 0x02u},
- {0x93u, 0xC0u},
- {0x95u, 0x50u},
- {0x97u, 0xA0u},
- {0x98u, 0x04u},
- {0x99u, 0x60u},
- {0x9Au, 0x02u},
- {0x9Bu, 0x90u},
- {0x9Du, 0x05u},
- {0x9Eu, 0x10u},
- {0x9Fu, 0x0Au},
- {0xA1u, 0x06u},
- {0xA3u, 0x09u},
- {0xA8u, 0x04u},
- {0xAAu, 0x02u},
- {0xACu, 0x08u},
- {0xAEu, 0x10u},
- {0xB0u, 0x01u},
- {0xB4u, 0x18u},
- {0xB5u, 0xFFu},
- {0xB6u, 0x06u},
- {0xB9u, 0x08u},
- {0xBAu, 0x80u},
- {0xBEu, 0x10u},
- {0xBFu, 0x14u},
- {0xD8u, 0x04u},
- {0xD9u, 0x04u},
- {0xDBu, 0x04u},
- {0xDCu, 0x09u},
- {0xDFu, 0x01u},
- {0x00u, 0x04u},
- {0x01u, 0x80u},
- {0x03u, 0x80u},
- {0x04u, 0x40u},
- {0x06u, 0x24u},
- {0x0Au, 0x88u},
- {0x0Bu, 0x01u},
- {0x0Du, 0x20u},
- {0x0Eu, 0x51u},
- {0x10u, 0x04u},
- {0x11u, 0x40u},
- {0x15u, 0x04u},
- {0x16u, 0x80u},
- {0x19u, 0xA0u},
- {0x1Au, 0x80u},
- {0x1Cu, 0x40u},
- {0x1Eu, 0x10u},
- {0x1Fu, 0x08u},
- {0x21u, 0x08u},
- {0x23u, 0x04u},
- {0x24u, 0x84u},
- {0x27u, 0x22u},
- {0x29u, 0x02u},
- {0x30u, 0x08u},
- {0x31u, 0x11u},
- {0x33u, 0x40u},
- {0x34u, 0x04u},
- {0x37u, 0x20u},
- {0x38u, 0x02u},
- {0x39u, 0x40u},
- {0x3Eu, 0x01u},
- {0x3Fu, 0x10u},
- {0x44u, 0x10u},
- {0x45u, 0x04u},
- {0x58u, 0x12u},
- {0x5Au, 0x04u},
- {0x5Bu, 0x80u},
- {0x5Cu, 0x20u},
- {0x5Eu, 0x80u},
- {0x5Fu, 0x08u},
- {0x62u, 0x80u},
- {0x64u, 0x04u},
- {0x65u, 0x40u},
- {0x67u, 0x10u},
- {0x69u, 0x40u},
- {0x81u, 0x24u},
- {0x82u, 0x80u},
- {0x86u, 0x04u},
- {0x89u, 0x10u},
- {0x8Au, 0x02u},
- {0x8Bu, 0x08u},
- {0x8Cu, 0x40u},
- {0x8Fu, 0x80u},
- {0x91u, 0x04u},
- {0x92u, 0x08u},
- {0x93u, 0x08u},
- {0x94u, 0x80u},
- {0x95u, 0x40u},
- {0x96u, 0x85u},
- {0x98u, 0x22u},
- {0x9Au, 0x20u},
- {0x9Bu, 0x40u},
- {0x9Du, 0xC0u},
- {0x9Eu, 0xC0u},
- {0xA1u, 0x20u},
- {0xA2u, 0xC0u},
- {0xA3u, 0x20u},
- {0xA4u, 0xD8u},
- {0xA6u, 0x12u},
- {0xA8u, 0x20u},
- {0xA9u, 0x10u},
- {0xAAu, 0x04u},
- {0xACu, 0x40u},
- {0xAEu, 0x20u},
- {0xAFu, 0x02u},
- {0xB0u, 0x01u},
- {0xB1u, 0x21u},
- {0xC0u, 0xEDu},
- {0xC2u, 0xFBu},
- {0xC4u, 0x33u},
- {0xCAu, 0x01u},
- {0xCCu, 0x6Fu},
- {0xCEu, 0xA9u},
- {0xD6u, 0x7Fu},
- {0xD8u, 0x78u},
- {0xE2u, 0x47u},
- {0xE4u, 0x01u},
- {0xE6u, 0x90u},
- {0xE8u, 0x02u},
- {0xEAu, 0x09u},
- {0xECu, 0x02u},
- {0x01u, 0x06u},
- {0x03u, 0x09u},
- {0x05u, 0x30u},
- {0x06u, 0xFFu},
- {0x07u, 0xC0u},
- {0x08u, 0x30u},
- {0x09u, 0x50u},
- {0x0Au, 0xC0u},
- {0x0Bu, 0xA0u},
- {0x0Cu, 0x09u},
- {0x0Du, 0x0Fu},
- {0x0Eu, 0x06u},
- {0x0Fu, 0xF0u},
- {0x10u, 0x0Fu},
- {0x11u, 0x60u},
- {0x12u, 0xF0u},
- {0x13u, 0x90u},
- {0x14u, 0xFFu},
- {0x15u, 0xFFu},
- {0x18u, 0xFFu},
- {0x1Bu, 0xFFu},
- {0x1Cu, 0x03u},
- {0x1Du, 0x03u},
- {0x1Eu, 0x0Cu},
- {0x1Fu, 0x0Cu},
- {0x20u, 0x05u},
- {0x21u, 0x05u},
- {0x22u, 0x0Au},
- {0x23u, 0x0Au},
+ {0x0Du, 0x60u},
+ {0x0Fu, 0x90u},
+ {0x11u, 0x30u},
+ {0x12u, 0x04u},
+ {0x13u, 0xC0u},
+ {0x19u, 0x06u},
+ {0x1Au, 0x10u},
+ {0x1Bu, 0x09u},
+ {0x1Du, 0x50u},
+ {0x1Fu, 0xA0u},
+ {0x20u, 0x02u},
+ {0x21u, 0x0Fu},
+ {0x22u, 0x04u},
+ {0x23u, 0xF0u},
{0x27u, 0xFFu},
- {0x28u, 0x50u},
- {0x2Au, 0xA0u},
- {0x2Cu, 0x90u},
- {0x2Eu, 0x60u},
- {0x32u, 0xFFu},
+ {0x29u, 0x05u},
+ {0x2Au, 0x08u},
+ {0x2Bu, 0x0Au},
+ {0x2Fu, 0xFFu},
+ {0x30u, 0x10u},
+ {0x32u, 0x06u},
{0x33u, 0xFFu},
+ {0x34u, 0x01u},
+ {0x36u, 0x08u},
{0x3Eu, 0x04u},
{0x3Fu, 0x04u},
{0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
+ {0x5Cu, 0x09u},
{0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x89u, 0x20u},
- {0x8Bu, 0x4Fu},
- {0x8Cu, 0x02u},
- {0x8Du, 0x40u},
+ {0x80u, 0x50u},
+ {0x82u, 0xA0u},
+ {0x86u, 0x08u},
+ {0x89u, 0x0Fu},
+ {0x8Au, 0x07u},
+ {0x8Bu, 0xF0u},
+ {0x8Cu, 0x0Au},
+ {0x8Du, 0x69u},
{0x8Eu, 0x05u},
- {0x8Fu, 0x1Fu},
- {0x94u, 0x02u},
- {0x95u, 0x03u},
- {0x96u, 0x01u},
- {0x97u, 0x0Cu},
- {0x98u, 0x02u},
- {0x99u, 0x05u},
- {0x9Au, 0x01u},
- {0x9Bu, 0x0Au},
- {0x9Cu, 0x01u},
+ {0x8Fu, 0x96u},
+ {0x91u, 0xFFu},
+ {0x92u, 0x40u},
+ {0x95u, 0x33u},
+ {0x97u, 0xCCu},
+ {0x9Au, 0x80u},
+ {0x9Bu, 0xFFu},
+ {0x9Cu, 0x09u},
{0x9Eu, 0x02u},
- {0x9Fu, 0x70u},
- {0xA5u, 0x0Fu},
- {0xA8u, 0x02u},
- {0xA9u, 0x06u},
- {0xAAu, 0x01u},
- {0xABu, 0x09u},
- {0xADu, 0x10u},
- {0xAFu, 0x2Fu},
- {0xB1u, 0x7Fu},
- {0xB4u, 0x04u},
- {0xB6u, 0x03u},
- {0xBAu, 0x80u},
+ {0x9Fu, 0xFFu},
+ {0xA1u, 0xFFu},
+ {0xA2u, 0x10u},
+ {0xA4u, 0x04u},
+ {0xA6u, 0x08u},
+ {0xA9u, 0x55u},
+ {0xAAu, 0x20u},
+ {0xABu, 0xAAu},
+ {0xAFu, 0xFFu},
+ {0xB0u, 0x30u},
+ {0xB2u, 0x0Fu},
+ {0xB4u, 0xC0u},
+ {0xB5u, 0xFFu},
+ {0xBBu, 0x20u},
+ {0xBEu, 0x11u},
{0xD4u, 0x01u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x19u},
+ {0xDCu, 0x11u},
{0xDDu, 0x10u},
{0xDFu, 0x01u},
- {0x00u, 0x20u},
+ {0x01u, 0x09u},
{0x02u, 0x01u},
- {0x03u, 0x20u},
- {0x07u, 0x02u},
- {0x08u, 0x50u},
- {0x09u, 0x08u},
- {0x0Bu, 0x84u},
- {0x0Eu, 0x09u},
- {0x0Fu, 0x10u},
- {0x11u, 0x10u},
- {0x12u, 0x82u},
+ {0x03u, 0x08u},
+ {0x04u, 0x20u},
+ {0x06u, 0x80u},
+ {0x09u, 0x82u},
+ {0x0Bu, 0x08u},
+ {0x0Du, 0x01u},
+ {0x0Eu, 0x04u},
+ {0x10u, 0x28u},
+ {0x11u, 0x02u},
+ {0x15u, 0x01u},
{0x17u, 0x20u},
- {0x18u, 0x20u},
- {0x1Eu, 0x09u},
- {0x22u, 0x08u},
- {0x24u, 0x40u},
- {0x27u, 0x40u},
- {0x28u, 0x10u},
- {0x29u, 0x02u},
- {0x2Fu, 0x26u},
- {0x30u, 0xC0u},
- {0x32u, 0x02u},
- {0x33u, 0x25u},
- {0x34u, 0x08u},
- {0x35u, 0x20u},
- {0x37u, 0x40u},
- {0x39u, 0x5Au},
- {0x3Au, 0x01u},
- {0x3Bu, 0x80u},
- {0x3Eu, 0xA0u},
- {0x58u, 0x80u},
+ {0x18u, 0xA0u},
+ {0x1Bu, 0x1Cu},
+ {0x1Cu, 0x22u},
+ {0x1Du, 0x01u},
+ {0x1Eu, 0x04u},
+ {0x1Fu, 0x02u},
+ {0x21u, 0x10u},
+ {0x26u, 0x08u},
+ {0x28u, 0x02u},
+ {0x29u, 0x50u},
+ {0x2Au, 0x01u},
+ {0x2Cu, 0x02u},
+ {0x2Du, 0x01u},
+ {0x2Eu, 0x08u},
+ {0x2Fu, 0x08u},
+ {0x30u, 0x24u},
+ {0x32u, 0x01u},
+ {0x33u, 0x41u},
+ {0x34u, 0x80u},
+ {0x36u, 0x01u},
+ {0x37u, 0x10u},
+ {0x39u, 0xA0u},
+ {0x3Cu, 0x10u},
+ {0x3Du, 0x80u},
+ {0x3Eu, 0x02u},
+ {0x46u, 0x44u},
+ {0x47u, 0x11u},
+ {0x5Bu, 0x80u},
{0x5Cu, 0x40u},
- {0x62u, 0x40u},
- {0x68u, 0x50u},
- {0x69u, 0x18u},
- {0x6Au, 0x80u},
- {0x6Bu, 0x01u},
- {0x70u, 0x08u},
- {0x71u, 0x11u},
- {0x72u, 0x40u},
- {0x73u, 0x01u},
- {0x81u, 0x18u},
- {0x82u, 0x40u},
- {0x83u, 0x04u},
- {0x86u, 0x0Au},
- {0x8Cu, 0x90u},
- {0x8Du, 0x40u},
- {0x91u, 0x40u},
- {0x93u, 0x1Cu},
- {0x95u, 0x10u},
- {0x96u, 0x01u},
- {0x97u, 0x01u},
- {0x9Au, 0xA0u},
- {0x9Bu, 0x22u},
- {0x9Du, 0x11u},
- {0x9Eu, 0x40u},
- {0xA3u, 0x22u},
- {0xA4u, 0xD8u},
- {0xA6u, 0x10u},
- {0xA7u, 0x80u},
- {0xA9u, 0x02u},
- {0xAAu, 0x40u},
- {0xABu, 0x02u},
- {0xADu, 0x08u},
+ {0x5Du, 0x10u},
+ {0x66u, 0xA0u},
+ {0x80u, 0x40u},
+ {0x84u, 0x01u},
+ {0x87u, 0x20u},
+ {0x8Du, 0x54u},
+ {0x90u, 0x10u},
+ {0x91u, 0x03u},
+ {0x92u, 0x02u},
+ {0x93u, 0x18u},
+ {0x98u, 0x80u},
+ {0x9Au, 0x02u},
+ {0x9Du, 0x04u},
+ {0x9Eu, 0x0Du},
+ {0xA0u, 0x02u},
+ {0xA1u, 0x41u},
+ {0xA2u, 0x03u},
+ {0xA3u, 0x20u},
+ {0xA4u, 0x20u},
+ {0xA5u, 0x80u},
+ {0xA7u, 0x04u},
+ {0xA9u, 0x01u},
+ {0xACu, 0x80u},
+ {0xADu, 0x01u},
+ {0xAFu, 0x20u},
+ {0xB1u, 0x48u},
+ {0xB2u, 0x01u},
{0xB3u, 0x08u},
- {0xB4u, 0x01u},
- {0xB6u, 0x04u},
- {0xC0u, 0x87u},
- {0xC2u, 0xEFu},
- {0xC4u, 0x4Bu},
- {0xCAu, 0x73u},
- {0xCCu, 0x7Fu},
- {0xCEu, 0x3Fu},
- {0xD6u, 0x18u},
- {0xD8u, 0x08u},
- {0xE0u, 0x0Eu},
- {0xE2u, 0x01u},
- {0xE4u, 0x04u},
- {0xEAu, 0x0Cu},
- {0xECu, 0x80u},
- {0xEEu, 0x24u},
- {0x86u, 0x10u},
- {0x88u, 0x08u},
- {0x91u, 0x50u},
- {0x92u, 0x80u},
- {0x93u, 0x04u},
- {0x95u, 0x02u},
- {0x9Cu, 0x08u},
- {0xA0u, 0x10u},
- {0xA4u, 0x80u},
- {0xA6u, 0x10u},
- {0xA7u, 0x80u},
- {0xABu, 0x81u},
- {0xACu, 0x40u},
- {0xADu, 0x20u},
- {0xAEu, 0x01u},
- {0xB1u, 0x02u},
- {0xB2u, 0x80u},
- {0xE6u, 0x8Cu},
- {0xE8u, 0x0Bu},
- {0xECu, 0x04u},
+ {0xB4u, 0x40u},
+ {0xB6u, 0x40u},
+ {0xC0u, 0x5Fu},
+ {0xC2u, 0x5Bu},
+ {0xC4u, 0x5Eu},
+ {0xCAu, 0xFDu},
+ {0xCCu, 0xBFu},
+ {0xCEu, 0xBCu},
+ {0xD6u, 0x38u},
+ {0xD8u, 0x30u},
+ {0xE0u, 0x01u},
+ {0xE2u, 0x02u},
+ {0xE4u, 0x08u},
+ {0xE6u, 0x02u},
+ {0xE8u, 0x40u},
+ {0xEAu, 0x08u},
+ {0xECu, 0x40u},
{0xEEu, 0x03u},
- {0x07u, 0x70u},
- {0x08u, 0x32u},
- {0x0Au, 0x01u},
- {0x0Bu, 0x08u},
- {0x0Fu, 0x07u},
- {0x10u, 0x01u},
- {0x12u, 0x1Au},
- {0x14u, 0x06u},
- {0x15u, 0x99u},
- {0x17u, 0x22u},
- {0x19u, 0xAAu},
- {0x1Au, 0x08u},
- {0x1Bu, 0x55u},
- {0x27u, 0x80u},
- {0x28u, 0x01u},
- {0x2Au, 0x2Cu},
- {0x2Du, 0x44u},
- {0x2Fu, 0x88u},
- {0x32u, 0x07u},
- {0x33u, 0xF0u},
- {0x34u, 0x38u},
- {0x37u, 0x0Fu},
- {0x38u, 0x08u},
+ {0x00u, 0x02u},
+ {0x02u, 0x04u},
+ {0x05u, 0x06u},
+ {0x07u, 0x09u},
+ {0x09u, 0x05u},
+ {0x0Bu, 0x0Au},
+ {0x13u, 0x70u},
+ {0x18u, 0x04u},
+ {0x19u, 0x40u},
+ {0x1Au, 0x02u},
+ {0x1Bu, 0x1Fu},
+ {0x1Cu, 0x04u},
+ {0x1Du, 0x10u},
+ {0x1Eu, 0x0Au},
+ {0x1Fu, 0x2Fu},
+ {0x21u, 0x20u},
+ {0x23u, 0x4Fu},
+ {0x24u, 0x04u},
+ {0x25u, 0x0Fu},
+ {0x26u, 0x03u},
+ {0x29u, 0x03u},
+ {0x2Bu, 0x0Cu},
+ {0x2Cu, 0x04u},
+ {0x2Eu, 0x02u},
+ {0x30u, 0x06u},
+ {0x31u, 0x7Fu},
+ {0x34u, 0x08u},
+ {0x36u, 0x01u},
+ {0x3Au, 0x02u},
{0x58u, 0x04u},
{0x59u, 0x04u},
- {0x5Cu, 0x10u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x19u},
{0x5Fu, 0x01u},
- {0x01u, 0x10u},
- {0x03u, 0x21u},
- {0x05u, 0x20u},
- {0x0Au, 0x45u},
- {0x0Eu, 0x58u},
- {0x10u, 0x20u},
- {0x11u, 0x01u},
- {0x13u, 0x50u},
- {0x16u, 0x08u},
- {0x1Au, 0x05u},
- {0x1Bu, 0x40u},
- {0x1Eu, 0x18u},
- {0x20u, 0x02u},
- {0x22u, 0x40u},
- {0x25u, 0x44u},
- {0x28u, 0x02u},
- {0x2Bu, 0x94u},
- {0x2Du, 0x04u},
- {0x2Eu, 0x80u},
- {0x30u, 0x04u},
- {0x32u, 0x60u},
- {0x36u, 0x28u},
- {0x37u, 0x20u},
- {0x38u, 0x60u},
- {0x3Au, 0x80u},
- {0x3Cu, 0x20u},
- {0x3Du, 0xC8u},
- {0x3Fu, 0x04u},
- {0x42u, 0x48u},
- {0x43u, 0x08u},
- {0x48u, 0x80u},
- {0x49u, 0xA5u},
- {0x4Bu, 0x12u},
- {0x50u, 0x08u},
- {0x51u, 0x08u},
- {0x52u, 0x10u},
- {0x53u, 0x40u},
- {0x58u, 0x50u},
- {0x5Au, 0x10u},
- {0x62u, 0x80u},
- {0x82u, 0x04u},
- {0x86u, 0x80u},
- {0x88u, 0x01u},
- {0x90u, 0x62u},
- {0x91u, 0x04u},
- {0x95u, 0x40u},
- {0x96u, 0x40u},
- {0x98u, 0x46u},
- {0x9Au, 0x21u},
- {0x9Bu, 0x04u},
- {0x9Cu, 0x90u},
- {0x9Du, 0x20u},
- {0x9Eu, 0x08u},
- {0xA0u, 0x10u},
- {0xA1u, 0x02u},
- {0xA2u, 0x28u},
- {0xA3u, 0x94u},
- {0xA4u, 0xC0u},
- {0xA5u, 0x80u},
- {0xA6u, 0x91u},
- {0xA8u, 0x01u},
- {0xABu, 0x01u},
- {0xACu, 0x04u},
- {0xADu, 0x01u},
- {0xAEu, 0x05u},
- {0xAFu, 0x04u},
- {0xB0u, 0x44u},
- {0xB2u, 0x11u},
- {0xB3u, 0x20u},
- {0xB5u, 0x08u},
- {0xC0u, 0x47u},
- {0xC2u, 0x7Bu},
- {0xC4u, 0x4Fu},
- {0xCAu, 0x5Fu},
- {0xCCu, 0x6Eu},
- {0xCEu, 0x7Cu},
- {0xD0u, 0x07u},
- {0xD2u, 0x0Cu},
- {0xD6u, 0x08u},
- {0xD8u, 0x08u},
- {0xE2u, 0x80u},
- {0xE6u, 0x80u},
- {0xEAu, 0x80u},
- {0xECu, 0x08u},
- {0xEEu, 0x01u},
- {0x00u, 0xFFu},
- {0x03u, 0x04u},
- {0x04u, 0x33u},
- {0x06u, 0xCCu},
- {0x0Au, 0xFFu},
- {0x0Bu, 0x10u},
- {0x0Eu, 0xFFu},
- {0x0Fu, 0x02u},
- {0x10u, 0x69u},
- {0x12u, 0x96u},
- {0x14u, 0x55u},
- {0x16u, 0xAAu},
- {0x18u, 0xFFu},
- {0x19u, 0x0Au},
- {0x1Bu, 0x14u},
- {0x1Cu, 0x0Fu},
- {0x1Eu, 0xF0u},
- {0x1Fu, 0x08u},
- {0x22u, 0xFFu},
- {0x29u, 0x01u},
- {0x33u, 0x18u},
- {0x35u, 0x06u},
- {0x36u, 0xFFu},
- {0x37u, 0x01u},
- {0x3Au, 0x80u},
- {0x3Fu, 0x54u},
- {0x56u, 0x08u},
- {0x58u, 0x04u},
- {0x59u, 0x04u},
- {0x5Bu, 0x04u},
- {0x5Cu, 0x01u},
- {0x5Du, 0x90u},
- {0x5Fu, 0x01u},
- {0x80u, 0x10u},
- {0x81u, 0x10u},
- {0x83u, 0x20u},
- {0x85u, 0x20u},
- {0x87u, 0x10u},
- {0x88u, 0x09u},
+ {0x82u, 0x10u},
+ {0x85u, 0x04u},
+ {0x87u, 0x02u},
{0x89u, 0x08u},
- {0x8Au, 0x02u},
- {0x8Bu, 0x04u},
{0x8Cu, 0x04u},
- {0x8Eu, 0x08u},
- {0x8Fu, 0x80u},
- {0x96u, 0x07u},
- {0x97u, 0x40u},
- {0x98u, 0x0Au},
- {0x9Au, 0x05u},
- {0x9Cu, 0x10u},
- {0x9Du, 0x02u},
- {0xA3u, 0x01u},
- {0xA4u, 0x10u},
- {0xA5u, 0x4Cu},
- {0xA7u, 0xB0u},
- {0xA8u, 0x10u},
+ {0x8Du, 0x04u},
+ {0x8Eu, 0x02u},
+ {0x8Fu, 0x02u},
+ {0x91u, 0x08u},
+ {0x94u, 0x02u},
+ {0x95u, 0x08u},
+ {0x96u, 0x04u},
+ {0x98u, 0x04u},
+ {0x99u, 0x02u},
+ {0x9Au, 0x02u},
+ {0x9Bu, 0x04u},
+ {0x9Fu, 0x10u},
+ {0xA0u, 0x04u},
+ {0xA1u, 0x04u},
+ {0xA2u, 0x0Au},
+ {0xA3u, 0x02u},
+ {0xA4u, 0x04u},
+ {0xA5u, 0x08u},
+ {0xA6u, 0x03u},
+ {0xABu, 0x01u},
{0xADu, 0x04u},
- {0xAEu, 0x08u},
- {0xAFu, 0x08u},
- {0xB1u, 0x3Cu},
- {0xB2u, 0x0Fu},
- {0xB3u, 0x02u},
- {0xB5u, 0x01u},
+ {0xAFu, 0x02u},
+ {0xB0u, 0x08u},
+ {0xB1u, 0x08u},
+ {0xB2u, 0x06u},
+ {0xB3u, 0x06u},
+ {0xB4u, 0x01u},
+ {0xB5u, 0x10u},
{0xB6u, 0x10u},
- {0xB7u, 0xC0u},
- {0xB8u, 0x80u},
- {0xBEu, 0x40u},
- {0xBFu, 0x45u},
+ {0xB7u, 0x01u},
+ {0xB9u, 0x02u},
+ {0xBAu, 0x08u},
+ {0xBBu, 0x08u},
+ {0xBFu, 0x01u},
+ {0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
- {0xDCu, 0x01u},
+ {0xDBu, 0x04u},
+ {0xDCu, 0x99u},
+ {0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x44u},
- {0x02u, 0x08u},
- {0x03u, 0x80u},
- {0x04u, 0x60u},
+ {0x01u, 0x02u},
+ {0x04u, 0x40u},
{0x05u, 0x01u},
- {0x09u, 0x20u},
- {0x0Au, 0x02u},
- {0x0Bu, 0x90u},
- {0x0Du, 0x20u},
- {0x0Eu, 0x12u},
- {0x11u, 0x01u},
- {0x17u, 0x68u},
- {0x1Au, 0x02u},
- {0x1Eu, 0x11u},
- {0x20u, 0x08u},
- {0x22u, 0x04u},
- {0x23u, 0x01u},
- {0x24u, 0x08u},
- {0x25u, 0x0Au},
- {0x26u, 0x40u},
- {0x28u, 0x08u},
- {0x2Cu, 0x80u},
- {0x2Fu, 0x21u},
- {0x31u, 0x8Cu},
- {0x33u, 0x20u},
- {0x36u, 0x84u},
- {0x39u, 0x60u},
- {0x3Au, 0x02u},
- {0x3Cu, 0x01u},
- {0x3Eu, 0x10u},
- {0x3Fu, 0x84u},
- {0x58u, 0x80u},
- {0x59u, 0x08u},
- {0x5Au, 0x20u},
- {0x60u, 0x0Eu},
- {0x63u, 0x20u},
- {0x79u, 0x08u},
- {0x7Au, 0x10u},
- {0x81u, 0x02u},
+ {0x0Au, 0x09u},
+ {0x0Eu, 0x28u},
+ {0x10u, 0x01u},
+ {0x12u, 0x20u},
+ {0x16u, 0x20u},
+ {0x17u, 0x02u},
+ {0x19u, 0x02u},
+ {0x1Au, 0x09u},
+ {0x1Cu, 0x40u},
+ {0x1Eu, 0x28u},
+ {0x1Fu, 0x40u},
+ {0x21u, 0x02u},
+ {0x23u, 0x80u},
+ {0x26u, 0x21u},
+ {0x27u, 0x22u},
+ {0x2Au, 0x09u},
+ {0x2Bu, 0x08u},
+ {0x2Du, 0x10u},
+ {0x2Fu, 0x62u},
+ {0x30u, 0x20u},
+ {0x31u, 0x82u},
+ {0x35u, 0x80u},
+ {0x36u, 0x0Au},
+ {0x37u, 0x20u},
+ {0x38u, 0x04u},
+ {0x39u, 0x20u},
+ {0x3Eu, 0x84u},
+ {0x3Fu, 0x10u},
+ {0x58u, 0x0Au},
+ {0x59u, 0x40u},
+ {0x5Bu, 0x20u},
+ {0x5Fu, 0x40u},
+ {0x62u, 0x40u},
+ {0x64u, 0x01u},
+ {0x65u, 0x80u},
+ {0x79u, 0x10u},
+ {0x7Au, 0x04u},
+ {0x82u, 0x01u},
+ {0x87u, 0x40u},
+ {0x89u, 0x08u},
+ {0x90u, 0x04u},
+ {0x91u, 0x20u},
+ {0x92u, 0x04u},
+ {0x93u, 0x10u},
+ {0x98u, 0x02u},
+ {0x99u, 0x01u},
+ {0x9Au, 0xE8u},
+ {0x9Du, 0x08u},
+ {0x9Eu, 0x05u},
+ {0x9Fu, 0xC0u},
+ {0xA0u, 0x30u},
+ {0xA2u, 0x0Au},
+ {0xA3u, 0x22u},
+ {0xA5u, 0x80u},
+ {0xA8u, 0x44u},
+ {0xACu, 0x24u},
+ {0xADu, 0x10u},
+ {0xB0u, 0x08u},
+ {0xB1u, 0x40u},
+ {0xB2u, 0x08u},
+ {0xB5u, 0x02u},
+ {0xB7u, 0x10u},
+ {0xC0u, 0x98u},
+ {0xC2u, 0x63u},
+ {0xC4u, 0x35u},
+ {0xCAu, 0xF7u},
+ {0xCCu, 0xFDu},
+ {0xCEu, 0x76u},
+ {0xD6u, 0x1Fu},
+ {0xD8u, 0x18u},
+ {0xE2u, 0x48u},
+ {0xE4u, 0x01u},
+ {0xE6u, 0x20u},
+ {0xEAu, 0x2Fu},
+ {0xEEu, 0x0Cu},
+ {0x8Fu, 0x08u},
+ {0x9Eu, 0x04u},
+ {0xA7u, 0x08u},
+ {0xAAu, 0x01u},
+ {0xACu, 0x10u},
+ {0xADu, 0x40u},
+ {0xAEu, 0x10u},
+ {0xB4u, 0x08u},
+ {0xB5u, 0x82u},
+ {0xB7u, 0x40u},
+ {0xE2u, 0x04u},
+ {0xE6u, 0x04u},
+ {0xE8u, 0x08u},
+ {0xEAu, 0x84u},
+ {0xEEu, 0x40u},
+ {0x04u, 0x02u},
+ {0x05u, 0xFFu},
+ {0x06u, 0x0Du},
+ {0x0Au, 0x10u},
+ {0x0Bu, 0xFFu},
+ {0x0Cu, 0x0Du},
+ {0x10u, 0x0Du},
+ {0x13u, 0xFFu},
+ {0x14u, 0x0Du},
+ {0x17u, 0xFFu},
+ {0x18u, 0x0Du},
+ {0x19u, 0xFFu},
+ {0x1Du, 0x0Fu},
+ {0x1Fu, 0xF0u},
+ {0x20u, 0x0Du},
+ {0x21u, 0x33u},
+ {0x23u, 0xCCu},
+ {0x24u, 0xE2u},
+ {0x25u, 0x55u},
+ {0x26u, 0x08u},
+ {0x27u, 0xAAu},
+ {0x28u, 0x82u},
+ {0x29u, 0x69u},
+ {0x2Au, 0x54u},
+ {0x2Bu, 0x96u},
+ {0x2Cu, 0x81u},
+ {0x2Eu, 0x32u},
+ {0x31u, 0xFFu},
+ {0x32u, 0x0Fu},
+ {0x34u, 0x70u},
+ {0x36u, 0x80u},
+ {0x3Au, 0x08u},
+ {0x3Bu, 0x02u},
+ {0x3Eu, 0x40u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Cu, 0x10u},
+ {0x5Fu, 0x01u},
+ {0x80u, 0x09u},
{0x82u, 0x02u},
- {0x83u, 0x40u},
- {0x85u, 0x10u},
- {0x87u, 0x08u},
+ {0x83u, 0x12u},
+ {0x85u, 0x20u},
+ {0x88u, 0x3Eu},
+ {0x89u, 0x04u},
+ {0x8Bu, 0x03u},
+ {0x8Fu, 0x0Cu},
+ {0x94u, 0x22u},
+ {0x95u, 0x08u},
+ {0x96u, 0x01u},
+ {0x97u, 0x03u},
+ {0x9Bu, 0x01u},
+ {0x9Du, 0x01u},
+ {0x9Fu, 0x02u},
+ {0xA1u, 0x40u},
+ {0xA2u, 0x38u},
+ {0xA3u, 0x80u},
+ {0xA4u, 0x01u},
+ {0xA6u, 0x14u},
+ {0xABu, 0x40u},
+ {0xAFu, 0x80u},
+ {0xB0u, 0x38u},
+ {0xB1u, 0xC0u},
+ {0xB3u, 0x20u},
+ {0xB4u, 0x07u},
+ {0xB5u, 0x10u},
+ {0xB7u, 0x0Fu},
+ {0xB8u, 0x20u},
+ {0xBEu, 0x01u},
+ {0xBFu, 0x05u},
+ {0xD6u, 0x08u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDBu, 0x04u},
+ {0xDDu, 0x90u},
+ {0xDFu, 0x01u},
+ {0x01u, 0x20u},
+ {0x03u, 0x40u},
+ {0x04u, 0x80u},
+ {0x05u, 0x14u},
+ {0x09u, 0x08u},
+ {0x0Cu, 0x2Au},
+ {0x11u, 0x08u},
+ {0x12u, 0x80u},
+ {0x15u, 0x29u},
+ {0x17u, 0x40u},
+ {0x19u, 0x20u},
+ {0x1Au, 0x80u},
+ {0x1Du, 0x54u},
+ {0x21u, 0x60u},
+ {0x22u, 0x81u},
+ {0x23u, 0x20u},
+ {0x25u, 0x01u},
+ {0x27u, 0x80u},
+ {0x29u, 0x01u},
+ {0x2Au, 0x80u},
+ {0x2Bu, 0x08u},
+ {0x2Cu, 0x84u},
+ {0x2Du, 0x04u},
+ {0x31u, 0x28u},
+ {0x33u, 0x40u},
+ {0x36u, 0x08u},
+ {0x37u, 0x91u},
+ {0x39u, 0xA4u},
+ {0x3Au, 0x01u},
+ {0x3Bu, 0x04u},
+ {0x3Cu, 0x08u},
+ {0x3Du, 0x20u},
+ {0x5Au, 0x60u},
+ {0x5Bu, 0x08u},
+ {0x60u, 0x22u},
+ {0x63u, 0x04u},
+ {0x81u, 0x10u},
{0x8Du, 0x01u},
- {0x8Fu, 0x20u},
- {0x90u, 0x62u},
+ {0x90u, 0x02u},
+ {0x92u, 0x49u},
+ {0x95u, 0x40u},
+ {0x97u, 0x20u},
+ {0x98u, 0x04u},
+ {0x99u, 0x01u},
+ {0x9Au, 0x8Au},
+ {0x9Bu, 0x15u},
+ {0x9Cu, 0x22u},
+ {0x9Fu, 0x20u},
+ {0xA0u, 0x84u},
+ {0xA1u, 0x10u},
+ {0xA2u, 0x08u},
+ {0xA7u, 0x10u},
+ {0xABu, 0x10u},
+ {0xB4u, 0x14u},
+ {0xC0u, 0xEAu},
+ {0xC2u, 0x74u},
+ {0xC4u, 0xFCu},
+ {0xCAu, 0xEDu},
+ {0xCCu, 0xFEu},
+ {0xCEu, 0x6Fu},
+ {0xD6u, 0x0Eu},
+ {0xD8u, 0x0Eu},
+ {0xE2u, 0x14u},
+ {0xE8u, 0x08u},
+ {0xEAu, 0x90u},
+ {0xEEu, 0x40u},
+ {0x25u, 0x01u},
+ {0x2Du, 0x02u},
+ {0x31u, 0x02u},
+ {0x33u, 0x01u},
+ {0x3Fu, 0x05u},
+ {0x59u, 0x04u},
+ {0x5Fu, 0x01u},
+ {0x85u, 0x08u},
+ {0x87u, 0x03u},
+ {0x89u, 0x37u},
+ {0x8Bu, 0x40u},
+ {0x93u, 0x2Cu},
+ {0x94u, 0x08u},
+ {0x97u, 0x7Fu},
+ {0x98u, 0x02u},
+ {0x99u, 0x4Fu},
+ {0x9Bu, 0x30u},
+ {0x9Cu, 0x04u},
+ {0xA1u, 0x02u},
+ {0xA5u, 0x10u},
+ {0xA7u, 0x01u},
+ {0xA8u, 0x01u},
+ {0xA9u, 0x03u},
+ {0xADu, 0x80u},
+ {0xB0u, 0x04u},
+ {0xB1u, 0x80u},
+ {0xB2u, 0x01u},
+ {0xB3u, 0x0Fu},
+ {0xB4u, 0x08u},
+ {0xB5u, 0x70u},
+ {0xB6u, 0x02u},
+ {0xBEu, 0x55u},
+ {0xBFu, 0x01u},
+ {0xC0u, 0x42u},
+ {0xC1u, 0x06u},
+ {0xC2u, 0x50u},
+ {0xC5u, 0xDEu},
+ {0xC6u, 0xF0u},
+ {0xC7u, 0x2Cu},
+ {0xC8u, 0x3Bu},
+ {0xC9u, 0xFFu},
+ {0xCAu, 0xFFu},
+ {0xCBu, 0xFFu},
+ {0xCFu, 0x2Cu},
+ {0xD6u, 0x01u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDAu, 0x04u},
+ {0xDBu, 0x04u},
+ {0xDCu, 0x10u},
+ {0xDDu, 0x01u},
+ {0xDFu, 0x01u},
+ {0xE2u, 0xC0u},
+ {0xE6u, 0x80u},
+ {0xE8u, 0x40u},
+ {0xE9u, 0x40u},
+ {0xEEu, 0x08u},
+ {0x0Cu, 0x84u},
+ {0x0Fu, 0x0Au},
+ {0x16u, 0x04u},
+ {0x1Du, 0x40u},
+ {0x1Eu, 0x88u},
+ {0x1Fu, 0x04u},
+ {0x23u, 0x50u},
+ {0x24u, 0x08u},
+ {0x25u, 0x14u},
+ {0x26u, 0x01u},
+ {0x27u, 0x14u},
+ {0x28u, 0x32u},
+ {0x2Du, 0xA6u},
+ {0x2Fu, 0x08u},
+ {0x30u, 0x02u},
+ {0x31u, 0x01u},
+ {0x36u, 0x08u},
+ {0x37u, 0x11u},
+ {0x3Cu, 0x08u},
+ {0x3Du, 0x20u},
+ {0x47u, 0x11u},
+ {0x4Cu, 0x14u},
+ {0x4Du, 0x03u},
+ {0x4Eu, 0x02u},
+ {0x55u, 0x01u},
+ {0x56u, 0x10u},
+ {0x57u, 0x08u},
+ {0x5Eu, 0x8Au},
+ {0x5Fu, 0x20u},
+ {0x65u, 0x40u},
+ {0x67u, 0x58u},
+ {0x6Cu, 0x21u},
+ {0x6Du, 0x10u},
+ {0x6Eu, 0x01u},
+ {0x74u, 0x08u},
+ {0x76u, 0x4Au},
+ {0x89u, 0x10u},
+ {0x8Au, 0x10u},
{0x91u, 0x04u},
- {0x92u, 0x20u},
- {0x93u, 0x90u},
+ {0x92u, 0x48u},
{0x94u, 0x08u},
- {0x95u, 0x49u},
- {0x96u, 0x50u},
- {0x97u, 0x01u},
- {0x98u, 0x40u},
- {0x9Au, 0x21u},
- {0x9Bu, 0x44u},
+ {0x95u, 0x41u},
+ {0x97u, 0x20u},
+ {0x98u, 0x04u},
+ {0x99u, 0x80u},
+ {0x9Au, 0x84u},
+ {0x9Bu, 0x01u},
{0x9Cu, 0x12u},
- {0x9Du, 0x24u},
- {0x9Eu, 0x08u},
- {0xA0u, 0x10u},
- {0xA1u, 0x20u},
- {0xA2u, 0x2Cu},
- {0xA3u, 0x84u},
- {0xA4u, 0x80u},
- {0xA6u, 0x40u},
- {0xA7u, 0x30u},
- {0xA9u, 0x44u},
- {0xACu, 0x40u},
- {0xAEu, 0x40u},
- {0xB4u, 0x20u},
- {0xB6u, 0x04u},
- {0xC0u, 0xDFu},
- {0xC2u, 0xEFu},
- {0xC4u, 0xE8u},
- {0xCAu, 0xD4u},
- {0xCCu, 0x5Cu},
- {0xCEu, 0xFDu},
- {0xD6u, 0x0Eu},
- {0xD8u, 0x0Eu},
- {0xE0u, 0x40u},
- {0xE2u, 0x10u},
- {0xE4u, 0x40u},
- {0xE8u, 0x02u},
- {0xEAu, 0x48u},
- {0xECu, 0x02u},
- {0xEEu, 0x30u},
- {0x03u, 0x7Eu},
- {0x05u, 0x80u},
- {0x06u, 0x01u},
- {0x08u, 0x88u},
- {0x0Au, 0x03u},
- {0x10u, 0x21u},
- {0x11u, 0x02u},
- {0x12u, 0x02u},
- {0x13u, 0x28u},
- {0x14u, 0x10u},
- {0x15u, 0x32u},
- {0x17u, 0x44u},
- {0x19u, 0x4Cu},
- {0x1Au, 0xECu},
- {0x1Bu, 0x32u},
- {0x1Eu, 0x02u},
- {0x24u, 0xE0u},
- {0x27u, 0x04u},
- {0x28u, 0x04u},
- {0x29u, 0x10u},
- {0x2Au, 0x43u},
- {0x2Du, 0x01u},
- {0x30u, 0x10u},
- {0x31u, 0x0Eu},
- {0x33u, 0x70u},
- {0x34u, 0x0Fu},
- {0x35u, 0x80u},
- {0x36u, 0xE0u},
- {0x37u, 0x01u},
- {0x3Eu, 0x41u},
- {0x3Fu, 0x50u},
- {0x40u, 0x52u},
- {0x41u, 0x03u},
- {0x42u, 0x40u},
- {0x45u, 0xE2u},
- {0x46u, 0xDCu},
- {0x47u, 0xF0u},
- {0x48u, 0x2Fu},
- {0x49u, 0xFFu},
- {0x4Au, 0xFFu},
- {0x4Bu, 0xFFu},
- {0x4Fu, 0x2Cu},
- {0x56u, 0x01u},
+ {0x9Du, 0x20u},
+ {0x9Eu, 0x40u},
+ {0x9Fu, 0x10u},
+ {0xA0u, 0x06u},
+ {0xA2u, 0x0Au},
+ {0xA3u, 0x05u},
+ {0xA4u, 0x28u},
+ {0xA5u, 0x15u},
+ {0xA7u, 0x10u},
+ {0xA8u, 0x10u},
+ {0xAAu, 0x40u},
+ {0xABu, 0x20u},
+ {0xADu, 0x80u},
+ {0xAFu, 0x01u},
+ {0xB1u, 0x04u},
+ {0xB2u, 0x14u},
+ {0xB6u, 0x50u},
+ {0xC2u, 0xE0u},
+ {0xC4u, 0x40u},
+ {0xCAu, 0xFAu},
+ {0xCCu, 0xE0u},
+ {0xCEu, 0x60u},
+ {0xD0u, 0xA0u},
+ {0xD2u, 0x30u},
+ {0xD6u, 0xF0u},
+ {0xD8u, 0xF0u},
+ {0xE2u, 0xC8u},
+ {0xE4u, 0x01u},
+ {0xE6u, 0x20u},
+ {0xE8u, 0x10u},
+ {0xEAu, 0xA0u},
+ {0xEEu, 0x3Du},
+ {0x03u, 0x22u},
+ {0x05u, 0x66u},
+ {0x07u, 0x19u},
+ {0x08u, 0x60u},
+ {0x09u, 0x15u},
+ {0x0Au, 0x90u},
+ {0x0Bu, 0x2Au},
+ {0x10u, 0x0Fu},
+ {0x11u, 0x17u},
+ {0x12u, 0xF0u},
+ {0x13u, 0x48u},
+ {0x14u, 0x03u},
+ {0x16u, 0x0Cu},
+ {0x17u, 0x73u},
+ {0x19u, 0x03u},
+ {0x1Bu, 0x0Cu},
+ {0x1Cu, 0x05u},
+ {0x1Eu, 0x0Au},
+ {0x24u, 0x50u},
+ {0x25u, 0x01u},
+ {0x26u, 0xA0u},
+ {0x28u, 0x30u},
+ {0x2Au, 0xC0u},
+ {0x2Cu, 0x06u},
+ {0x2Eu, 0x09u},
+ {0x30u, 0xFFu},
+ {0x33u, 0x0Fu},
+ {0x35u, 0x70u},
+ {0x37u, 0x70u},
+ {0x3Bu, 0x08u},
+ {0x3Eu, 0x01u},
+ {0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
- {0x5Au, 0x04u},
{0x5Bu, 0x04u},
{0x5Cu, 0x10u},
- {0x5Du, 0x01u},
+ {0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x62u, 0xC0u},
- {0x66u, 0x80u},
- {0x68u, 0x40u},
- {0x69u, 0x40u},
- {0x6Eu, 0x08u},
- {0x80u, 0x02u},
- {0x90u, 0x01u},
- {0xA5u, 0x01u},
- {0xB4u, 0x02u},
+ {0x80u, 0x33u},
+ {0x82u, 0xCCu},
+ {0x83u, 0x40u},
+ {0x84u, 0xFFu},
+ {0x87u, 0x04u},
+ {0x88u, 0x0Fu},
+ {0x89u, 0x10u},
+ {0x8Au, 0xF0u},
+ {0x8Bu, 0x08u},
+ {0x8Fu, 0x02u},
+ {0x90u, 0x96u},
+ {0x91u, 0x22u},
+ {0x92u, 0x69u},
+ {0x93u, 0x44u},
+ {0x94u, 0xFFu},
+ {0x95u, 0x08u},
+ {0x97u, 0x10u},
+ {0x99u, 0x10u},
+ {0x9Au, 0xFFu},
+ {0x9Bu, 0x08u},
+ {0xA1u, 0x10u},
+ {0xA3u, 0x08u},
+ {0xA4u, 0x55u},
+ {0xA6u, 0xAAu},
+ {0xA7u, 0x20u},
+ {0xAAu, 0xFFu},
+ {0xADu, 0x10u},
+ {0xAEu, 0xFFu},
+ {0xAFu, 0x09u},
+ {0xB1u, 0x60u},
+ {0xB2u, 0xFFu},
+ {0xB3u, 0x18u},
{0xB5u, 0x01u},
- {0xB6u, 0x01u},
- {0xBEu, 0x50u},
- {0xBFu, 0x10u},
+ {0xB7u, 0x06u},
+ {0xBAu, 0x08u},
+ {0xBBu, 0x08u},
+ {0xBFu, 0x41u},
+ {0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
+ {0xDBu, 0x04u},
+ {0xDCu, 0x91u},
+ {0xDDu, 0x90u},
{0xDFu, 0x01u},
+ {0x00u, 0x18u},
{0x02u, 0x80u},
- {0x04u, 0x08u},
- {0x05u, 0x20u},
+ {0x06u, 0x08u},
{0x08u, 0x02u},
- {0x0Cu, 0x80u},
- {0x0Eu, 0x44u},
- {0x0Fu, 0x10u},
- {0x14u, 0x10u},
- {0x16u, 0x08u},
- {0x19u, 0x90u},
- {0x1Eu, 0x05u},
- {0x1Fu, 0x01u},
+ {0x09u, 0x04u},
+ {0x0Au, 0x08u},
+ {0x0Cu, 0x02u},
+ {0x0Eu, 0x12u},
+ {0x10u, 0x10u},
+ {0x11u, 0xA0u},
+ {0x14u, 0x08u},
+ {0x15u, 0x40u},
+ {0x16u, 0x10u},
+ {0x18u, 0x30u},
+ {0x1Du, 0x01u},
+ {0x20u, 0x82u},
+ {0x22u, 0x1Cu},
{0x23u, 0x04u},
- {0x24u, 0x60u},
- {0x25u, 0x8Cu},
- {0x26u, 0x1Au},
+ {0x25u, 0x60u},
+ {0x27u, 0x21u},
+ {0x29u, 0x48u},
+ {0x2Au, 0x02u},
{0x2Bu, 0x10u},
- {0x2Cu, 0x20u},
- {0x2Eu, 0xA0u},
- {0x2Fu, 0x04u},
- {0x36u, 0x2Au},
- {0x3Du, 0x01u},
- {0x3Fu, 0x08u},
- {0x41u, 0x80u},
- {0x42u, 0x02u},
- {0x44u, 0x80u},
- {0x45u, 0x28u},
- {0x4Cu, 0x60u},
- {0x4Eu, 0x02u},
- {0x55u, 0x50u},
- {0x57u, 0x02u},
- {0x5Du, 0x80u},
+ {0x2Du, 0x04u},
+ {0x30u, 0x02u},
+ {0x32u, 0x14u},
+ {0x36u, 0x08u},
+ {0x37u, 0x21u},
+ {0x39u, 0x50u},
+ {0x3Au, 0x09u},
+ {0x3Du, 0x2Au},
+ {0x59u, 0x10u},
+ {0x5Au, 0x80u},
{0x5Eu, 0x20u},
- {0x5Fu, 0x05u},
- {0x65u, 0x14u},
- {0x66u, 0x02u},
- {0x67u, 0x02u},
- {0x6Cu, 0x01u},
+ {0x5Fu, 0x48u},
+ {0x63u, 0x0Au},
+ {0x64u, 0x04u},
+ {0x65u, 0x80u},
+ {0x66u, 0x04u},
{0x6Du, 0x04u},
- {0x6Fu, 0x44u},
- {0x74u, 0x1Au},
- {0x76u, 0x01u},
- {0x7Eu, 0x80u},
- {0x7Fu, 0x40u},
- {0x82u, 0x02u},
- {0x83u, 0x02u},
- {0x84u, 0x40u},
- {0x85u, 0x40u},
- {0x86u, 0x01u},
- {0x88u, 0x88u},
- {0x89u, 0x40u},
- {0x8Au, 0x01u},
- {0x8Cu, 0x40u},
- {0x8Eu, 0x10u},
- {0x93u, 0x18u},
- {0x95u, 0x09u},
- {0x96u, 0x12u},
- {0x9Au, 0x80u},
- {0x9Du, 0x40u},
- {0xA0u, 0x40u},
- {0xA1u, 0x20u},
- {0xA2u, 0xA4u},
- {0xA3u, 0x84u},
- {0xA4u, 0x02u},
- {0xA5u, 0x5Cu},
- {0xA6u, 0x02u},
- {0xA7u, 0x20u},
- {0xA9u, 0x08u},
- {0xACu, 0x01u},
- {0xADu, 0x20u},
- {0xB0u, 0x80u},
+ {0x6Fu, 0x0Au},
+ {0x81u, 0x10u},
+ {0x85u, 0x10u},
+ {0x87u, 0x0Cu},
+ {0x88u, 0x41u},
+ {0x8Du, 0x20u},
+ {0x8Eu, 0x04u},
+ {0x8Fu, 0x0Cu},
+ {0x92u, 0x10u},
+ {0x93u, 0x40u},
+ {0x94u, 0x08u},
+ {0x95u, 0x01u},
+ {0x97u, 0x20u},
+ {0x98u, 0x08u},
+ {0x99u, 0x40u},
+ {0x9Au, 0x9Bu},
+ {0x9Du, 0x09u},
+ {0x9Eu, 0x40u},
+ {0x9Fu, 0x10u},
+ {0xA0u, 0x06u},
+ {0xA2u, 0x93u},
+ {0xA4u, 0x28u},
+ {0xA5u, 0x60u},
+ {0xA6u, 0x08u},
+ {0xA7u, 0x02u},
+ {0xAAu, 0x01u},
+ {0xAFu, 0x0Au},
+ {0xB0u, 0x04u},
{0xB2u, 0x80u},
- {0xB3u, 0x40u},
+ {0xB3u, 0x01u},
{0xB5u, 0x80u},
- {0xC0u, 0x68u},
- {0xC2u, 0xF8u},
- {0xC4u, 0x60u},
- {0xCAu, 0x72u},
- {0xCCu, 0xE0u},
- {0xCEu, 0xC0u},
- {0xD0u, 0xE0u},
- {0xD2u, 0x10u},
- {0xD6u, 0xF0u},
- {0xD8u, 0xF0u},
- {0xE0u, 0xA0u},
- {0xE4u, 0x01u},
- {0xE6u, 0xBAu},
- {0xECu, 0x02u},
- {0xEEu, 0xA0u},
- {0x01u, 0x10u},
- {0x03u, 0x09u},
- {0x04u, 0x02u},
- {0x06u, 0x04u},
- {0x07u, 0x02u},
- {0x0Au, 0x08u},
- {0x15u, 0x10u},
- {0x16u, 0x02u},
- {0x17u, 0x08u},
- {0x19u, 0x08u},
- {0x1Au, 0x01u},
- {0x1Bu, 0x10u},
- {0x1Fu, 0x04u},
- {0x21u, 0x10u},
- {0x23u, 0x08u},
+ {0xC0u, 0x4Eu},
+ {0xC2u, 0xBEu},
+ {0xC4u, 0xE7u},
+ {0xCAu, 0x4Bu},
+ {0xCCu, 0xE7u},
+ {0xCEu, 0xEFu},
+ {0xD6u, 0x7Cu},
+ {0xD8u, 0x7Cu},
+ {0xE0u, 0x01u},
+ {0xE2u, 0x50u},
+ {0xE6u, 0x14u},
+ {0xEAu, 0x20u},
+ {0xEEu, 0x20u},
+ {0x02u, 0x01u},
+ {0x04u, 0x10u},
+ {0x05u, 0x02u},
+ {0x06u, 0x20u},
+ {0x07u, 0x09u},
+ {0x09u, 0x02u},
+ {0x0Bu, 0x01u},
+ {0x0Cu, 0x40u},
+ {0x0Eu, 0x80u},
+ {0x14u, 0x20u},
+ {0x16u, 0x12u},
+ {0x19u, 0x01u},
+ {0x1Bu, 0x02u},
+ {0x1Du, 0x02u},
+ {0x1Fu, 0x01u},
+ {0x20u, 0x80u},
+ {0x22u, 0x44u},
{0x25u, 0x02u},
- {0x27u, 0x04u},
- {0x29u, 0x10u},
- {0x2Bu, 0x08u},
- {0x2Eu, 0x04u},
+ {0x27u, 0x05u},
+ {0x2Au, 0x08u},
+ {0x2Cu, 0x32u},
+ {0x2Eu, 0xC4u},
{0x30u, 0x06u},
- {0x31u, 0x06u},
- {0x33u, 0x01u},
- {0x34u, 0x01u},
- {0x35u, 0x18u},
- {0x36u, 0x08u},
+ {0x32u, 0x08u},
+ {0x33u, 0x08u},
+ {0x34u, 0xF0u},
+ {0x35u, 0x03u},
+ {0x36u, 0x01u},
+ {0x37u, 0x04u},
{0x3Bu, 0x20u},
- {0x3Eu, 0x01u},
- {0x3Fu, 0x01u},
+ {0x3Eu, 0x11u},
{0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Cu, 0x99u},
{0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x80u, 0x08u},
- {0x82u, 0x04u},
- {0x83u, 0x0Fu},
- {0x85u, 0x97u},
- {0x87u, 0x20u},
- {0x89u, 0x02u},
- {0x8Du, 0x03u},
- {0x91u, 0x40u},
- {0x93u, 0x8Cu},
- {0x94u, 0x08u},
- {0x96u, 0x05u},
- {0x97u, 0x70u},
- {0x98u, 0x08u},
- {0x99u, 0xAFu},
- {0x9Au, 0x14u},
- {0x9Bu, 0x50u},
- {0x9Cu, 0x04u},
- {0x9Eu, 0x08u},
- {0xA1u, 0x08u},
- {0xA3u, 0x03u},
- {0xABu, 0x01u},
- {0xACu, 0x08u},
- {0xAEu, 0x06u},
- {0xAFu, 0x80u},
- {0xB0u, 0x10u},
- {0xB2u, 0x02u},
- {0xB3u, 0xF0u},
- {0xB4u, 0x01u},
- {0xB5u, 0x0Fu},
- {0xB6u, 0x0Cu},
- {0xBAu, 0x80u},
- {0xD6u, 0x08u},
+ {0x82u, 0x80u},
+ {0x83u, 0x38u},
+ {0x84u, 0x99u},
+ {0x85u, 0x01u},
+ {0x86u, 0x22u},
+ {0x89u, 0x4Au},
+ {0x8Au, 0x70u},
+ {0x8Bu, 0x15u},
+ {0x8Du, 0x22u},
+ {0x8Fu, 0x45u},
+ {0x91u, 0x01u},
+ {0x93u, 0x06u},
+ {0x96u, 0x08u},
+ {0x97u, 0x01u},
+ {0x98u, 0x44u},
+ {0x99u, 0x53u},
+ {0x9Au, 0x88u},
+ {0x9Bu, 0x2Cu},
+ {0x9Eu, 0x07u},
+ {0xA7u, 0x40u},
+ {0xA8u, 0xAAu},
+ {0xAAu, 0x55u},
+ {0xB1u, 0x07u},
+ {0xB2u, 0xF0u},
+ {0xB6u, 0x0Fu},
+ {0xB7u, 0x78u},
+ {0xBBu, 0x02u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x19u},
- {0xDDu, 0x90u},
+ {0xDCu, 0x11u},
{0xDFu, 0x01u},
- {0x01u, 0x20u},
- {0x03u, 0x20u},
- {0x05u, 0x01u},
- {0x0Au, 0x18u},
- {0x0Eu, 0x26u},
- {0x10u, 0x01u},
- {0x16u, 0x02u},
- {0x19u, 0x22u},
- {0x1Bu, 0x40u},
- {0x1Du, 0x01u},
- {0x1Eu, 0x26u},
- {0x1Fu, 0xC0u},
- {0x20u, 0x80u},
- {0x22u, 0x14u},
- {0x23u, 0x08u},
- {0x25u, 0x20u},
- {0x26u, 0x2Cu},
- {0x29u, 0x20u},
- {0x2Bu, 0x60u},
- {0x2Cu, 0x02u},
- {0x2Fu, 0x84u},
- {0x31u, 0x40u},
- {0x32u, 0x14u},
- {0x36u, 0x2Au},
- {0x39u, 0x08u},
- {0x3Au, 0x01u},
- {0x3Du, 0xA9u},
- {0x3Fu, 0x20u},
- {0x58u, 0x84u},
- {0x59u, 0x10u},
- {0x5Au, 0x02u},
- {0x5Du, 0x80u},
- {0x62u, 0x81u},
- {0x63u, 0x18u},
- {0x66u, 0x80u},
+ {0x01u, 0x08u},
+ {0x02u, 0x01u},
+ {0x03u, 0x80u},
+ {0x04u, 0x18u},
+ {0x06u, 0x60u},
+ {0x0Bu, 0x20u},
+ {0x0Cu, 0x08u},
+ {0x0Du, 0x20u},
+ {0x0Eu, 0x02u},
+ {0x10u, 0x82u},
+ {0x13u, 0x10u},
+ {0x17u, 0x10u},
+ {0x18u, 0x80u},
+ {0x19u, 0x64u},
+ {0x1Cu, 0x10u},
+ {0x1Eu, 0x12u},
+ {0x20u, 0x08u},
+ {0x22u, 0x50u},
+ {0x23u, 0x10u},
+ {0x24u, 0x01u},
+ {0x25u, 0x80u},
+ {0x26u, 0x02u},
+ {0x29u, 0x04u},
+ {0x2Cu, 0x20u},
+ {0x32u, 0x50u},
+ {0x36u, 0x0Au},
+ {0x37u, 0x10u},
+ {0x3Bu, 0x14u},
+ {0x3Cu, 0x09u},
+ {0x3Du, 0x80u},
+ {0x3Eu, 0x20u},
+ {0x59u, 0x90u},
+ {0x62u, 0x80u},
+ {0x63u, 0x04u},
+ {0x68u, 0x02u},
+ {0x6Cu, 0x90u},
+ {0x6Fu, 0x09u},
+ {0x75u, 0x02u},
+ {0x76u, 0x19u},
+ {0x80u, 0x50u},
+ {0x81u, 0x20u},
{0x82u, 0x02u},
- {0x83u, 0x18u},
- {0x87u, 0x04u},
- {0x88u, 0x04u},
- {0x89u, 0x02u},
- {0x8Du, 0x10u},
- {0xC0u, 0x16u},
- {0xC2u, 0xE6u},
- {0xC4u, 0x81u},
- {0xCAu, 0xB7u},
- {0xCCu, 0xEEu},
- {0xCEu, 0xF3u},
- {0xD6u, 0x1Fu},
- {0xD8u, 0x1Fu},
- {0xE2u, 0x22u},
- {0xE4u, 0x02u},
- {0x81u, 0x40u},
- {0x82u, 0x40u},
- {0x89u, 0x10u},
- {0x8Bu, 0x04u},
- {0x91u, 0x50u},
- {0x92u, 0x80u},
- {0x93u, 0x04u},
- {0xABu, 0x80u},
- {0xADu, 0x01u},
- {0xE2u, 0x04u},
- {0xE4u, 0x05u},
- {0xE6u, 0x40u},
- {0xEEu, 0x06u},
- {0x88u, 0x10u},
- {0x91u, 0x50u},
- {0x92u, 0x80u},
- {0x93u, 0x04u},
- {0x95u, 0x02u},
- {0xA0u, 0x10u},
- {0xA7u, 0x80u},
- {0xA8u, 0x80u},
- {0xE8u, 0x10u},
- {0xEAu, 0x04u},
- {0x01u, 0x41u},
- {0x05u, 0x41u},
- {0x08u, 0x99u},
- {0x09u, 0x40u},
- {0x0Au, 0x22u},
+ {0x83u, 0x80u},
+ {0x84u, 0x02u},
+ {0x86u, 0x10u},
+ {0x88u, 0x08u},
+ {0x89u, 0x03u},
+ {0x8Bu, 0x40u},
+ {0x8Du, 0x91u},
+ {0xC0u, 0x7Du},
+ {0xC2u, 0xE4u},
+ {0xC4u, 0x4Bu},
+ {0xCAu, 0x42u},
+ {0xCCu, 0xECu},
+ {0xCEu, 0xF6u},
+ {0xD6u, 0x0Cu},
+ {0xD8u, 0x0Cu},
+ {0xE0u, 0x01u},
+ {0xE2u, 0x90u},
+ {0xE4u, 0x10u},
+ {0xE6u, 0xC8u},
+ {0xAAu, 0x04u},
+ {0xE0u, 0x08u},
+ {0xE6u, 0x02u},
+ {0xEAu, 0x01u},
+ {0xEEu, 0x02u},
+ {0x9Eu, 0x04u},
+ {0xE2u, 0x08u},
+ {0xEEu, 0x01u},
+ {0x02u, 0x08u},
+ {0x03u, 0x08u},
+ {0x07u, 0x80u},
+ {0x0Bu, 0x07u},
{0x0Cu, 0x44u},
- {0x0Du, 0x47u},
{0x0Eu, 0x88u},
- {0x0Fu, 0x98u},
- {0x11u, 0x01u},
- {0x13u, 0x40u},
- {0x16u, 0x70u},
- {0x19u, 0xE2u},
- {0x1Au, 0x07u},
- {0x1Bu, 0x08u},
- {0x1Du, 0x81u},
- {0x1Fu, 0x40u},
- {0x21u, 0x41u},
- {0x25u, 0x88u},
- {0x26u, 0x80u},
- {0x27u, 0x61u},
+ {0x0Fu, 0x70u},
+ {0x11u, 0x44u},
+ {0x13u, 0x88u},
+ {0x15u, 0x99u},
+ {0x16u, 0x07u},
+ {0x17u, 0x22u},
+ {0x19u, 0xAAu},
+ {0x1Au, 0x70u},
+ {0x1Bu, 0x55u},
+ {0x1Eu, 0x80u},
+ {0x24u, 0x99u},
+ {0x26u, 0x22u},
{0x28u, 0xAAu},
- {0x29u, 0x04u},
{0x2Au, 0x55u},
- {0x2Du, 0x10u},
- {0x2Eu, 0x08u},
- {0x31u, 0xC0u},
- {0x32u, 0xF0u},
- {0x34u, 0x0Fu},
- {0x37u, 0x3Fu},
- {0x39u, 0x80u},
- {0x3Bu, 0x02u},
- {0x3Fu, 0x40u},
+ {0x32u, 0x0Fu},
+ {0x34u, 0xF0u},
+ {0x35u, 0x0Fu},
+ {0x37u, 0xF0u},
+ {0x40u, 0x36u},
+ {0x41u, 0x01u},
+ {0x42u, 0x50u},
+ {0x44u, 0x04u},
+ {0x45u, 0x0Eu},
+ {0x46u, 0xFCu},
+ {0x47u, 0xBDu},
+ {0x48u, 0x3Du},
+ {0x49u, 0xFFu},
+ {0x4Au, 0xFFu},
+ {0x4Bu, 0xFFu},
+ {0x4Cu, 0x22u},
+ {0x4Eu, 0xF0u},
+ {0x4Fu, 0x08u},
+ {0x50u, 0x04u},
+ {0x54u, 0x09u},
+ {0x56u, 0x04u},
{0x58u, 0x04u},
{0x59u, 0x04u},
- {0x5Cu, 0x01u},
+ {0x5Au, 0x04u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x11u},
{0x5Fu, 0x01u},
- {0x80u, 0x07u},
- {0x81u, 0xC0u},
- {0x82u, 0x10u},
- {0x83u, 0x02u},
- {0x84u, 0x03u},
- {0x85u, 0xC0u},
- {0x86u, 0x70u},
- {0x87u, 0x04u},
- {0x88u, 0x80u},
- {0x89u, 0xC0u},
- {0x8Au, 0x64u},
- {0x8Bu, 0x08u},
- {0x8Cu, 0x64u},
- {0x8Du, 0xC0u},
- {0x8Eu, 0x80u},
- {0x8Fu, 0x01u},
- {0x90u, 0x24u},
- {0x91u, 0x90u},
- {0x93u, 0x40u},
- {0x96u, 0x75u},
- {0x98u, 0xA4u},
- {0x9Au, 0x40u},
- {0x9Bu, 0x60u},
- {0x9Cu, 0xE4u},
+ {0x62u, 0xC0u},
+ {0x64u, 0x40u},
+ {0x65u, 0x01u},
+ {0x66u, 0x10u},
+ {0x67u, 0x11u},
+ {0x68u, 0xC0u},
+ {0x69u, 0x01u},
+ {0x6Bu, 0x11u},
+ {0x6Cu, 0x40u},
+ {0x6Du, 0x01u},
+ {0x6Eu, 0x40u},
+ {0x6Fu, 0x01u},
+ {0x81u, 0x0Cu},
+ {0x85u, 0xB8u},
+ {0x87u, 0x45u},
+ {0x89u, 0x73u},
+ {0x8Bu, 0x88u},
+ {0x8Du, 0x0Cu},
+ {0x91u, 0x04u},
+ {0x93u, 0x08u},
+ {0x95u, 0x08u},
+ {0x97u, 0x04u},
+ {0x98u, 0x01u},
+ {0x99u, 0x14u},
+ {0x9Bu, 0x08u},
{0x9Du, 0x80u},
- {0xA0u, 0xE4u},
- {0xA3u, 0x9Fu},
- {0xA4u, 0x08u},
- {0xA7u, 0xFFu},
- {0xA8u, 0x40u},
- {0xA9u, 0x7Fu},
- {0xAAu, 0x02u},
- {0xABu, 0x80u},
- {0xACu, 0x08u},
- {0xADu, 0x1Fu},
- {0xAFu, 0x20u},
- {0xB0u, 0x71u},
- {0xB2u, 0x08u},
- {0xB4u, 0x07u},
- {0xB5u, 0xFFu},
- {0xB6u, 0x80u},
- {0xB8u, 0x08u},
- {0xBAu, 0x30u},
- {0xBEu, 0x40u},
- {0xBFu, 0x10u},
- {0xD6u, 0x02u},
- {0xD7u, 0x2Cu},
+ {0x9Fu, 0x60u},
+ {0xA3u, 0x02u},
+ {0xA9u, 0x0Cu},
+ {0xADu, 0x2Fu},
+ {0xAFu, 0xD0u},
+ {0xB3u, 0x07u},
+ {0xB5u, 0x18u},
+ {0xB6u, 0x01u},
+ {0xB7u, 0xE0u},
+ {0xBBu, 0xACu},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
- {0xDBu, 0x04u},
+ {0xDCu, 0x09u},
{0xDFu, 0x01u},
- {0x01u, 0x12u},
- {0x03u, 0x21u},
- {0x04u, 0x60u},
- {0x08u, 0x04u},
- {0x09u, 0x01u},
- {0x0Au, 0x05u},
- {0x0Eu, 0x28u},
- {0x10u, 0x08u},
- {0x11u, 0x81u},
- {0x13u, 0x08u},
- {0x16u, 0x01u},
- {0x17u, 0x24u},
- {0x18u, 0x04u},
- {0x19u, 0xA2u},
- {0x1Au, 0x62u},
- {0x1Bu, 0x0Au},
- {0x1Eu, 0x28u},
- {0x23u, 0x08u},
- {0x25u, 0x41u},
- {0x27u, 0x40u},
- {0x28u, 0x04u},
- {0x29u, 0x21u},
- {0x2Bu, 0x22u},
- {0x2Eu, 0x09u},
- {0x2Fu, 0x29u},
- {0x32u, 0x10u},
- {0x33u, 0x41u},
- {0x35u, 0x20u},
- {0x37u, 0x41u},
- {0x38u, 0x80u},
- {0x39u, 0x15u},
- {0x3Bu, 0x40u},
- {0x3Du, 0x15u},
- {0x3Eu, 0x40u},
- {0x63u, 0x80u},
- {0x68u, 0x20u},
- {0x69u, 0x55u},
- {0x6Au, 0x04u},
- {0x6Bu, 0x01u},
- {0x70u, 0x40u},
- {0x72u, 0x01u},
- {0x8Au, 0x40u},
- {0x90u, 0x62u},
- {0x93u, 0x86u},
- {0x95u, 0x11u},
- {0x96u, 0x40u},
- {0x97u, 0x40u},
- {0x99u, 0x05u},
- {0x9Au, 0x31u},
- {0x9Bu, 0x24u},
- {0x9Cu, 0x80u},
- {0x9Du, 0xA0u},
- {0x9Eu, 0x08u},
- {0x9Fu, 0x01u},
- {0xA0u, 0x08u},
- {0xA1u, 0x0Au},
- {0xA2u, 0x20u},
- {0xA3u, 0x40u},
- {0xA4u, 0x60u},
- {0xA5u, 0x80u},
- {0xA6u, 0x11u},
- {0xA7u, 0x20u},
- {0xA9u, 0x04u},
- {0xB7u, 0x08u},
- {0xC0u, 0xCFu},
- {0xC2u, 0x6Fu},
- {0xC4u, 0xEFu},
- {0xCAu, 0xFFu},
- {0xCCu, 0xBDu},
+ {0x04u, 0x02u},
+ {0x07u, 0x01u},
+ {0x0Au, 0x08u},
+ {0x0Eu, 0x19u},
+ {0x17u, 0x14u},
+ {0x1Au, 0x02u},
+ {0x1Eu, 0x18u},
+ {0x1Fu, 0x18u},
+ {0x20u, 0x04u},
+ {0x21u, 0x0Cu},
+ {0x22u, 0x90u},
+ {0x23u, 0x10u},
+ {0x25u, 0x50u},
+ {0x28u, 0x01u},
+ {0x29u, 0x10u},
+ {0x2Bu, 0x40u},
+ {0x30u, 0x0Au},
+ {0x32u, 0x90u},
+ {0x37u, 0x15u},
+ {0x38u, 0x80u},
+ {0x39u, 0x29u},
+ {0x3Du, 0xE0u},
+ {0x3Eu, 0x0Au},
+ {0x3Fu, 0x20u},
+ {0x44u, 0x01u},
+ {0x45u, 0x04u},
+ {0x46u, 0x40u},
+ {0x47u, 0x40u},
+ {0x4Du, 0x84u},
+ {0x4Fu, 0x10u},
+ {0x56u, 0x25u},
+ {0x57u, 0xC0u},
+ {0x5Du, 0x04u},
+ {0x5Eu, 0x62u},
+ {0x65u, 0x40u},
+ {0x67u, 0x80u},
+ {0x87u, 0x40u},
+ {0x90u, 0x02u},
+ {0x92u, 0x09u},
+ {0x94u, 0x80u},
+ {0x95u, 0x69u},
+ {0x97u, 0x20u},
+ {0x99u, 0x40u},
+ {0x9Au, 0x0Au},
+ {0x9Bu, 0x15u},
+ {0x9Eu, 0x01u},
+ {0x9Fu, 0x40u},
+ {0xA4u, 0x2Au},
+ {0xA5u, 0x0Cu},
+ {0xA7u, 0x18u},
+ {0xAAu, 0x50u},
+ {0xABu, 0x08u},
+ {0xB2u, 0x01u},
+ {0xC0u, 0x90u},
+ {0xC2u, 0xE2u},
+ {0xC4u, 0x60u},
+ {0xCAu, 0x0Du},
+ {0xCCu, 0xEFu},
{0xCEu, 0xFFu},
- {0xD8u, 0x01u},
- {0xE4u, 0x80u},
- {0xE8u, 0x10u},
- {0x00u, 0x16u},
- {0x03u, 0x08u},
- {0x04u, 0x01u},
- {0x06u, 0x0Eu},
- {0x08u, 0x10u},
- {0x09u, 0x09u},
- {0x0Au, 0x06u},
- {0x0Bu, 0x02u},
- {0x0Cu, 0x07u},
- {0x0Du, 0x04u},
- {0x0Eu, 0x08u},
- {0x0Fu, 0x08u},
- {0x12u, 0x10u},
- {0x14u, 0x04u},
- {0x18u, 0x09u},
- {0x19u, 0x0Au},
- {0x1Au, 0x06u},
- {0x1Bu, 0x05u},
- {0x1Cu, 0x16u},
- {0x1Fu, 0x07u},
- {0x20u, 0x02u},
- {0x24u, 0x12u},
- {0x26u, 0x04u},
- {0x2Cu, 0x06u},
- {0x2Eu, 0x10u},
- {0x30u, 0x08u},
- {0x32u, 0x10u},
- {0x34u, 0x0Fu},
- {0x36u, 0x01u},
- {0x37u, 0x0Fu},
- {0x38u, 0x20u},
- {0x3Eu, 0x45u},
- {0x54u, 0x09u},
- {0x56u, 0x04u},
+ {0xD0u, 0xD0u},
+ {0xD2u, 0x30u},
+ {0xD6u, 0xF0u},
+ {0xD8u, 0x90u},
+ {0xEAu, 0x04u},
+ {0xEEu, 0x04u},
+ {0x00u, 0x01u},
+ {0x01u, 0xC0u},
+ {0x03u, 0x02u},
+ {0x05u, 0x80u},
+ {0x0Bu, 0xFFu},
+ {0x0Du, 0xC0u},
+ {0x0Fu, 0x01u},
+ {0x11u, 0x90u},
+ {0x13u, 0x40u},
+ {0x15u, 0xC0u},
+ {0x17u, 0x08u},
+ {0x18u, 0x01u},
+ {0x19u, 0xC0u},
+ {0x1Bu, 0x04u},
+ {0x1Du, 0x1Fu},
+ {0x1Fu, 0x20u},
+ {0x23u, 0x9Fu},
+ {0x25u, 0x7Fu},
+ {0x27u, 0x80u},
+ {0x2Fu, 0x60u},
+ {0x30u, 0x01u},
+ {0x37u, 0xFFu},
+ {0x38u, 0x02u},
+ {0x3Fu, 0x40u},
+ {0x56u, 0x02u},
+ {0x57u, 0x20u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x10u},
{0x5Fu, 0x01u},
- {0x80u, 0x90u},
- {0x82u, 0x60u},
- {0x85u, 0xFFu},
- {0x86u, 0xFFu},
- {0x88u, 0x0Fu},
- {0x8Au, 0xF0u},
- {0x8Cu, 0x50u},
- {0x8Eu, 0xA0u},
- {0x8Fu, 0xFFu},
- {0x91u, 0x06u},
- {0x92u, 0xFFu},
- {0x93u, 0x09u},
- {0x94u, 0x05u},
- {0x95u, 0x0Fu},
- {0x96u, 0x0Au},
- {0x97u, 0xF0u},
- {0x98u, 0x03u},
- {0x99u, 0x05u},
- {0x9Au, 0x0Cu},
- {0x9Bu, 0x0Au},
- {0x9Du, 0x30u},
- {0x9Fu, 0xC0u},
- {0xA0u, 0x30u},
- {0xA1u, 0x50u},
- {0xA2u, 0xC0u},
- {0xA3u, 0xA0u},
- {0xA5u, 0x03u},
- {0xA6u, 0xFFu},
- {0xA7u, 0x0Cu},
- {0xABu, 0xFFu},
- {0xACu, 0x09u},
- {0xADu, 0x60u},
- {0xAEu, 0x06u},
- {0xAFu, 0x90u},
- {0xB0u, 0xFFu},
- {0xB1u, 0xFFu},
- {0xBEu, 0x01u},
- {0xBFu, 0x01u},
+ {0x80u, 0x07u},
+ {0x81u, 0x6Cu},
+ {0x82u, 0x18u},
+ {0x84u, 0x01u},
+ {0x85u, 0x24u},
+ {0x89u, 0x91u},
+ {0x8Au, 0x80u},
+ {0x8Bu, 0x6Eu},
+ {0x8Cu, 0xC1u},
+ {0x8Du, 0x48u},
+ {0x90u, 0x01u},
+ {0x92u, 0xC0u},
+ {0x94u, 0xC0u},
+ {0x98u, 0x08u},
+ {0x99u, 0x24u},
+ {0x9Au, 0x21u},
+ {0x9Bu, 0x48u},
+ {0x9Cu, 0x04u},
+ {0x9Du, 0x71u},
+ {0x9Fu, 0x82u},
+ {0xA0u, 0xC1u},
+ {0xA1u, 0x6Cu},
+ {0xA4u, 0x22u},
+ {0xA5u, 0x10u},
+ {0xA6u, 0x08u},
+ {0xA7u, 0xEFu},
+ {0xA8u, 0xC1u},
+ {0xABu, 0x6Cu},
+ {0xACu, 0x10u},
+ {0xADu, 0x6Cu},
+ {0xB0u, 0x08u},
+ {0xB1u, 0x0Fu},
+ {0xB2u, 0x80u},
+ {0xB3u, 0xF0u},
+ {0xB4u, 0x3Fu},
+ {0xB6u, 0x40u},
+ {0xB8u, 0x20u},
+ {0xB9u, 0x08u},
+ {0xBEu, 0x55u},
{0xD4u, 0x40u},
{0xD6u, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
{0xDFu, 0x01u},
- {0x00u, 0x04u},
- {0x01u, 0x11u},
- {0x03u, 0x02u},
- {0x05u, 0x10u},
- {0x06u, 0x82u},
- {0x07u, 0x60u},
- {0x08u, 0x02u},
- {0x09u, 0x08u},
- {0x0Au, 0x19u},
- {0x0Bu, 0x80u},
- {0x0Du, 0x02u},
- {0x0Eu, 0x24u},
- {0x0Fu, 0x84u},
- {0x11u, 0x46u},
- {0x14u, 0x41u},
- {0x15u, 0x80u},
- {0x16u, 0x60u},
- {0x18u, 0x01u},
- {0x19u, 0x08u},
- {0x1Au, 0x48u},
- {0x1Bu, 0x20u},
- {0x1Cu, 0x80u},
- {0x21u, 0xC0u},
- {0x26u, 0x01u},
- {0x2Eu, 0xA6u},
- {0x31u, 0x80u},
- {0x32u, 0x20u},
- {0x34u, 0x49u},
- {0x36u, 0x10u},
- {0x38u, 0x62u},
- {0x3Eu, 0x08u},
+ {0x00u, 0x02u},
+ {0x04u, 0x04u},
+ {0x06u, 0x06u},
+ {0x07u, 0x40u},
+ {0x0Au, 0x04u},
+ {0x0Cu, 0x0Au},
+ {0x0Eu, 0x08u},
+ {0x0Fu, 0x02u},
+ {0x14u, 0x10u},
+ {0x15u, 0x09u},
+ {0x16u, 0x01u},
+ {0x17u, 0x20u},
+ {0x1Bu, 0x01u},
+ {0x1Du, 0x44u},
+ {0x1Eu, 0x46u},
+ {0x20u, 0x02u},
+ {0x24u, 0x10u},
+ {0x25u, 0x04u},
+ {0x26u, 0x04u},
+ {0x27u, 0x40u},
+ {0x28u, 0x10u},
+ {0x2Au, 0x01u},
+ {0x2Bu, 0x01u},
+ {0x2Cu, 0x1Au},
+ {0x2Eu, 0x02u},
+ {0x30u, 0x2Au},
+ {0x31u, 0x10u},
+ {0x33u, 0x40u},
+ {0x37u, 0x60u},
+ {0x38u, 0x94u},
+ {0x39u, 0x21u},
+ {0x3Cu, 0x14u},
+ {0x3Du, 0x01u},
{0x3Fu, 0x80u},
- {0x46u, 0x08u},
- {0x47u, 0x20u},
- {0x59u, 0x04u},
- {0x5Au, 0x52u},
- {0x60u, 0x01u},
- {0x61u, 0x01u},
- {0x64u, 0x02u},
- {0x65u, 0x08u},
- {0x66u, 0x11u},
- {0x80u, 0x08u},
- {0x81u, 0x11u},
- {0x83u, 0x40u},
- {0x8Au, 0x02u},
- {0x8Bu, 0x20u},
- {0x8Cu, 0x80u},
- {0x8Eu, 0x01u},
- {0x90u, 0x66u},
- {0x91u, 0x55u},
- {0x92u, 0x03u},
- {0x93u, 0x84u},
- {0x99u, 0x04u},
- {0x9Au, 0x70u},
- {0x9Cu, 0x80u},
- {0xA1u, 0x0Bu},
- {0xA2u, 0x30u},
- {0xA3u, 0x02u},
- {0xA4u, 0x40u},
- {0xA5u, 0x80u},
+ {0x59u, 0xC0u},
+ {0x62u, 0x80u},
+ {0x65u, 0x04u},
+ {0x66u, 0xA0u},
+ {0x67u, 0x40u},
+ {0x68u, 0x2Au},
+ {0x69u, 0x01u},
+ {0x6Bu, 0x20u},
+ {0x70u, 0x40u},
+ {0x72u, 0x02u},
+ {0x86u, 0x40u},
+ {0x87u, 0x40u},
+ {0x8Eu, 0x84u},
+ {0x90u, 0x04u},
+ {0x91u, 0x08u},
+ {0x94u, 0x80u},
+ {0x95u, 0x21u},
+ {0x96u, 0x40u},
+ {0x9Au, 0x25u},
+ {0x9Du, 0x90u},
+ {0x9Eu, 0x40u},
+ {0x9Fu, 0x40u},
+ {0xA2u, 0x80u},
+ {0xA3u, 0x40u},
+ {0xA4u, 0x2Au},
+ {0xA5u, 0x04u},
{0xA6u, 0x01u},
- {0xA7u, 0x20u},
- {0xAAu, 0x04u},
- {0xADu, 0x80u},
- {0xC0u, 0xFFu},
- {0xC2u, 0x7Fu},
- {0xC4u, 0xBDu},
- {0xCAu, 0xF0u},
- {0xCCu, 0xFCu},
- {0xCEu, 0x5Du},
- {0xD6u, 0x0Fu},
- {0xD8u, 0xF9u},
- {0xE0u, 0x80u},
- {0xE4u, 0x20u},
- {0xE6u, 0x40u},
- {0x04u, 0x40u},
- {0x0Cu, 0x80u},
- {0x13u, 0x10u},
+ {0xAAu, 0x10u},
+ {0xAEu, 0x01u},
+ {0xB2u, 0x10u},
+ {0xB3u, 0x80u},
+ {0xC0u, 0xF8u},
+ {0xC2u, 0xF2u},
+ {0xC4u, 0xF0u},
+ {0xCAu, 0xFBu},
+ {0xCCu, 0x3Fu},
+ {0xCEu, 0xFFu},
+ {0xD8u, 0xF8u},
+ {0x06u, 0x08u},
+ {0x0Fu, 0x08u},
+ {0x13u, 0x40u},
{0x17u, 0x48u},
- {0x32u, 0x02u},
+ {0x33u, 0x08u},
{0x36u, 0x80u},
{0x37u, 0x08u},
- {0x3Bu, 0x11u},
- {0x3Du, 0x08u},
- {0x3Eu, 0x40u},
- {0x43u, 0x10u},
- {0x67u, 0x80u},
- {0x85u, 0x40u},
- {0x87u, 0x40u},
- {0x8Cu, 0x10u},
- {0x8Eu, 0x02u},
+ {0x3Au, 0x01u},
+ {0x3Bu, 0x40u},
+ {0x3Du, 0x84u},
+ {0x42u, 0x01u},
+ {0x5Du, 0x01u},
+ {0x8Cu, 0x08u},
{0xC0u, 0x80u},
{0xC2u, 0x80u},
{0xC4u, 0xE0u},
{0xCCu, 0xE0u},
{0xCEu, 0xF0u},
{0xD0u, 0x10u},
- {0xD8u, 0x80u},
- {0xE2u, 0x10u},
- {0xE6u, 0x10u},
- {0x31u, 0x04u},
+ {0xD6u, 0x80u},
+ {0x32u, 0x08u},
{0x33u, 0x40u},
- {0x35u, 0x80u},
- {0x37u, 0x08u},
- {0x3Au, 0x10u},
- {0x57u, 0x04u},
- {0x59u, 0x40u},
- {0x60u, 0x10u},
- {0x82u, 0x40u},
- {0x88u, 0x10u},
- {0x8Fu, 0x05u},
- {0x90u, 0x10u},
- {0x96u, 0x40u},
- {0x97u, 0x01u},
- {0x99u, 0x40u},
+ {0x35u, 0x88u},
+ {0x38u, 0x40u},
+ {0x52u, 0x20u},
+ {0x5Bu, 0x20u},
+ {0x63u, 0x40u},
+ {0x87u, 0x40u},
+ {0x95u, 0x04u},
+ {0x96u, 0x01u},
+ {0x98u, 0x08u},
+ {0x9Au, 0x08u},
{0x9Bu, 0x40u},
- {0x9Fu, 0x10u},
- {0xA0u, 0x80u},
- {0xA5u, 0x04u},
+ {0x9Eu, 0x01u},
+ {0xA5u, 0x40u},
{0xA6u, 0x80u},
- {0xA8u, 0x40u},
+ {0xA7u, 0x08u},
+ {0xADu, 0x41u},
+ {0xB6u, 0x01u},
+ {0xB7u, 0x04u},
{0xCCu, 0xF0u},
{0xCEu, 0x10u},
- {0xD4u, 0xC0u},
+ {0xD4u, 0xA0u},
{0xD8u, 0x40u},
- {0xE2u, 0x20u},
- {0xECu, 0x20u},
+ {0xE6u, 0x40u},
+ {0xE8u, 0x40u},
+ {0xEAu, 0x10u},
{0x12u, 0x80u},
- {0x5Au, 0x04u},
- {0x92u, 0x04u},
- {0x9Du, 0x04u},
- {0x9Fu, 0x18u},
- {0xA0u, 0x10u},
- {0xA5u, 0x04u},
- {0xA6u, 0x80u},
- {0xADu, 0x80u},
- {0xAEu, 0x04u},
- {0xB0u, 0x80u},
- {0xB2u, 0x10u},
+ {0x58u, 0x08u},
+ {0x85u, 0x80u},
+ {0x86u, 0x08u},
+ {0x89u, 0x40u},
+ {0x8Cu, 0x40u},
+ {0x94u, 0x40u},
+ {0x95u, 0x04u},
+ {0x96u, 0x01u},
+ {0x98u, 0x08u},
+ {0x9Au, 0x08u},
+ {0x9Du, 0x88u},
+ {0x9Eu, 0x01u},
+ {0xA5u, 0x40u},
+ {0xA6u, 0x88u},
+ {0xA7u, 0x08u},
+ {0xABu, 0x20u},
+ {0xB2u, 0x20u},
{0xC4u, 0x10u},
{0xD6u, 0x40u},
- {0xEAu, 0x50u},
- {0x83u, 0x01u},
- {0x8Bu, 0x08u},
- {0x9Fu, 0x18u},
- {0xA0u, 0x10u},
- {0xA5u, 0x04u},
- {0xA9u, 0x04u},
+ {0xE2u, 0x10u},
+ {0xE4u, 0x40u},
+ {0xEAu, 0x80u},
+ {0x82u, 0x08u},
+ {0x83u, 0x20u},
+ {0x95u, 0x04u},
+ {0x96u, 0x01u},
+ {0xA6u, 0x08u},
+ {0xA7u, 0x08u},
+ {0xB1u, 0x08u},
+ {0xB6u, 0x01u},
+ {0xE2u, 0x20u},
{0xE6u, 0x20u},
- {0xEEu, 0x80u},
- {0x02u, 0x02u},
- {0x05u, 0x20u},
- {0x0Bu, 0x02u},
- {0x0Eu, 0x08u},
- {0x10u, 0x10u},
- {0x15u, 0x08u},
- {0x63u, 0x40u},
- {0x67u, 0x08u},
- {0x86u, 0x02u},
- {0x87u, 0x40u},
- {0x89u, 0x24u},
- {0x8Bu, 0x04u},
+ {0x01u, 0x40u},
+ {0x05u, 0x10u},
+ {0x08u, 0x80u},
+ {0x0Fu, 0x02u},
+ {0x10u, 0x80u},
+ {0x14u, 0x20u},
+ {0x5Bu, 0x04u},
+ {0x62u, 0x04u},
+ {0x83u, 0x04u},
+ {0x87u, 0x01u},
+ {0x88u, 0x80u},
{0x8Du, 0x40u},
+ {0x8Eu, 0x04u},
{0xC0u, 0x03u},
{0xC2u, 0x03u},
{0xC4u, 0x0Cu},
- {0xD8u, 0x03u},
- {0xE0u, 0x01u},
+ {0xD6u, 0x02u},
+ {0xD8u, 0x02u},
{0xE2u, 0x06u},
- {0xE6u, 0x01u},
- {0x00u, 0x08u},
- {0x04u, 0x08u},
- {0x0Au, 0x40u},
- {0x0Eu, 0x20u},
- {0x51u, 0x01u},
- {0x52u, 0x20u},
- {0x5Cu, 0x02u},
- {0x65u, 0x20u},
- {0x81u, 0x20u},
- {0x84u, 0x04u},
- {0x86u, 0x10u},
- {0x8Fu, 0x01u},
- {0x91u, 0x02u},
- {0x93u, 0x02u},
- {0x95u, 0x40u},
- {0x96u, 0x40u},
- {0xA2u, 0x04u},
- {0xADu, 0x01u},
- {0xB0u, 0x10u},
- {0xB6u, 0x40u},
+ {0xE4u, 0x08u},
+ {0x01u, 0x02u},
+ {0x05u, 0x01u},
+ {0x09u, 0x04u},
+ {0x0Eu, 0x40u},
+ {0x50u, 0x04u},
+ {0x5Fu, 0x20u},
+ {0x64u, 0x09u},
+ {0x80u, 0x20u},
+ {0x83u, 0x20u},
+ {0x88u, 0x09u},
+ {0x8Cu, 0x80u},
+ {0x98u, 0x20u},
+ {0x99u, 0x10u},
+ {0x9Du, 0x01u},
+ {0xA0u, 0x80u},
+ {0xB5u, 0x01u},
{0xC0u, 0x0Cu},
{0xC2u, 0x0Cu},
- {0xD4u, 0x05u},
- {0xD6u, 0x01u},
+ {0xD4u, 0x04u},
+ {0xD6u, 0x05u},
{0xD8u, 0x01u},
- {0xE2u, 0x02u},
- {0xEAu, 0x04u},
+ {0xE0u, 0x01u},
+ {0xE4u, 0x04u},
+ {0xE6u, 0x02u},
{0xEEu, 0x02u},
- {0x55u, 0x20u},
- {0x8Cu, 0x04u},
- {0x90u, 0x08u},
- {0x95u, 0x40u},
- {0x96u, 0x04u},
- {0x97u, 0x10u},
- {0x9Au, 0x10u},
- {0x9Cu, 0x02u},
- {0xA2u, 0x04u},
- {0xAEu, 0x30u},
- {0xAFu, 0x10u},
- {0xB2u, 0x04u},
+ {0x57u, 0x08u},
+ {0x83u, 0x08u},
+ {0x87u, 0x10u},
+ {0x8Fu, 0x04u},
+ {0x92u, 0x40u},
+ {0x94u, 0x10u},
+ {0xA8u, 0x10u},
+ {0xA9u, 0x10u},
+ {0xADu, 0x02u},
+ {0xB4u, 0x04u},
+ {0xB5u, 0x04u},
{0xD4u, 0x02u},
- {0xE2u, 0x08u},
- {0xEEu, 0x04u},
- {0x09u, 0x20u},
+ {0xE2u, 0x02u},
+ {0xE8u, 0x08u},
+ {0xEEu, 0x02u},
+ {0x0Au, 0x08u},
{0x0Bu, 0x10u},
- {0x0Eu, 0x04u},
- {0x0Fu, 0x20u},
- {0x89u, 0x20u},
- {0x93u, 0x08u},
- {0x95u, 0x40u},
- {0x96u, 0x04u},
+ {0x0Fu, 0x88u},
+ {0x83u, 0x40u},
+ {0x92u, 0x40u},
+ {0x94u, 0x10u},
+ {0x96u, 0x08u},
{0x97u, 0x10u},
- {0x9Au, 0x10u},
- {0xA7u, 0x10u},
- {0xABu, 0x10u},
- {0xAFu, 0x04u},
- {0xB0u, 0x02u},
- {0xB1u, 0x20u},
- {0xB6u, 0x04u},
- {0xC2u, 0x0Fu},
- {0xE6u, 0x01u},
- {0xE8u, 0x04u},
- {0xEAu, 0x02u},
- {0xECu, 0x01u},
- {0x93u, 0x02u},
- {0x9Fu, 0x50u},
- {0xA0u, 0x10u},
- {0xA5u, 0x04u},
- {0xB7u, 0x40u},
- {0x07u, 0x40u},
- {0x53u, 0x01u},
- {0x54u, 0x10u},
- {0x83u, 0x10u},
- {0x8Du, 0x04u},
- {0x93u, 0x02u},
- {0x9Fu, 0x50u},
{0xA0u, 0x10u},
- {0xA5u, 0x04u},
+ {0xA7u, 0x04u},
+ {0xACu, 0x10u},
+ {0xB2u, 0x04u},
+ {0xC2u, 0x0Fu},
+ {0xEAu, 0x01u},
+ {0x86u, 0x01u},
+ {0x92u, 0x80u},
+ {0x95u, 0x04u},
+ {0x96u, 0x01u},
+ {0xA3u, 0x20u},
+ {0xA7u, 0x08u},
+ {0xAAu, 0x40u},
+ {0xE2u, 0x10u},
+ {0xEEu, 0x80u},
+ {0x06u, 0x40u},
+ {0x57u, 0x20u},
+ {0x5Au, 0x80u},
+ {0x85u, 0x04u},
+ {0x86u, 0x40u},
+ {0x92u, 0x80u},
+ {0x95u, 0x04u},
+ {0xA3u, 0x20u},
+ {0xAFu, 0x08u},
{0xC0u, 0x20u},
{0xD4u, 0xC0u},
- {0xE2u, 0x20u},
- {0x93u, 0x08u},
- {0x95u, 0x40u},
- {0x9Au, 0x10u},
- {0x01u, 0x40u},
+ {0xE0u, 0x10u},
+ {0xE6u, 0x40u},
+ {0xEEu, 0x40u},
+ {0x94u, 0x50u},
+ {0x99u, 0x20u},
+ {0xA0u, 0x10u},
+ {0xA8u, 0x40u},
+ {0xAAu, 0x40u},
+ {0xB1u, 0x20u},
+ {0xE8u, 0x04u},
+ {0x00u, 0x40u},
{0x04u, 0x10u},
- {0x53u, 0x04u},
- {0x56u, 0x10u},
- {0x8Cu, 0x10u},
- {0x93u, 0x08u},
- {0x95u, 0x40u},
- {0x9Au, 0x10u},
+ {0x54u, 0x10u},
+ {0x5Du, 0x20u},
+ {0x94u, 0x50u},
+ {0x99u, 0x20u},
+ {0xA0u, 0x10u},
{0xC0u, 0x03u},
- {0xD4u, 0x06u},
- {0xE2u, 0x08u},
+ {0xD4u, 0x02u},
+ {0xD6u, 0x04u},
{0x10u, 0x03u},
+ {0x11u, 0x01u},
{0x1Cu, 0x03u},
+ {0x1Du, 0x01u},
{0x00u, 0xFDu},
{0x01u, 0xAFu},
{0x02u, 0x0Au},
/* address, size */
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},
{(void CYFAR *)(CYREG_PRT1_DR), 16u},
- {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 2176u},
- {(void CYFAR *)(CYDEV_UCFG_B0_P4_ROUTE_BASE), 1792u},
+ {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
{(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},
};
- /* UDB_0_2_0_CONFIG Address: CYDEV_UCFG_B0_P4_U1_BASE Size (bytes): 128 */
- static const uint8 CYCODE BS_UDB_0_2_0_CONFIG_VAL[] = {
- 0x00u, 0x00u, 0x00u, 0x00u, 0x13u, 0x00u, 0x24u, 0x00u, 0x68u, 0x00u, 0x00u, 0xFFu, 0x68u, 0x00u, 0x00u, 0xFFu,
- 0x09u, 0x00u, 0x16u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x10u, 0xFFu, 0x68u, 0x00u, 0x04u, 0x0Fu, 0x03u, 0xF0u,
- 0x68u, 0xFFu, 0x00u, 0x00u, 0x68u, 0x69u, 0x00u, 0x96u, 0x15u, 0x55u, 0x42u, 0xAAu, 0x68u, 0x33u, 0x00u, 0xCCu,
- 0x00u, 0x00u, 0x00u, 0x00u, 0x78u, 0x00u, 0x07u, 0xFFu, 0x00u, 0x00u, 0xA0u, 0x80u, 0x00u, 0x00u, 0x00u, 0x00u,
- 0x26u, 0x04u, 0x50u, 0x00u, 0x03u, 0xBEu, 0xFDu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x04u, 0x04u, 0x04u, 0x04u, 0x10u, 0x90u, 0x00u, 0x01u,
- 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
- 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
-
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {
- 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x02u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u};
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u};
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
/* dest, src, size */
- {(void CYFAR *)(CYDEV_UCFG_B0_P4_U1_BASE), BS_UDB_0_2_0_CONFIG_VAL, 128u},
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},
};
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
- CYMEMZERO(ms->address, (uint32)(ms->size));
+ CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
/* Copy device configuration data into registers */
/*******************************************************************************
* FILENAME: cyfitter_cfg.h
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator 3.1
*
* Description:
* This file is automatically generated by PSoC Creator.
.include "cydevicegnu.inc"
.include "cydevicegnu_trm.inc"
-/* Debug_Timer_Interrupt */
-.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set Debug_Timer_Interrupt__INTC_MASK, 0x02
-.set Debug_Timer_Interrupt__INTC_NUMBER, 1
-.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7
-.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
-.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SCSI_RX_DMA_COMPLETE */
-.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x01
-.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 0
-.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
-.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SCSI_TX_DMA_COMPLETE */
-.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x08
-.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 3
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3
-.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* Debug_Timer_TimerHW */
-.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0
-.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1
-.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0
-.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1
-.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2
-.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0
-.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1
-.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0
-.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1
-.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3
-.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01
-.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3
-.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01
-.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0
-.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1
-.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0
+/* LED1 */
+.set LED1__0__MASK, 0x02
+.set LED1__0__PC, CYREG_PRT0_PC1
+.set LED1__0__PORT, 0
+.set LED1__0__SHIFT, 1
+.set LED1__AG, CYREG_PRT0_AG
+.set LED1__AMUX, CYREG_PRT0_AMUX
+.set LED1__BIE, CYREG_PRT0_BIE
+.set LED1__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set LED1__BYP, CYREG_PRT0_BYP
+.set LED1__CTL, CYREG_PRT0_CTL
+.set LED1__DM0, CYREG_PRT0_DM0
+.set LED1__DM1, CYREG_PRT0_DM1
+.set LED1__DM2, CYREG_PRT0_DM2
+.set LED1__DR, CYREG_PRT0_DR
+.set LED1__INP_DIS, CYREG_PRT0_INP_DIS
+.set LED1__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set LED1__LCD_EN, CYREG_PRT0_LCD_EN
+.set LED1__MASK, 0x02
+.set LED1__PORT, 0
+.set LED1__PRT, CYREG_PRT0_PRT
+.set LED1__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set LED1__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set LED1__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set LED1__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set LED1__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set LED1__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set LED1__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set LED1__PS, CYREG_PRT0_PS
+.set LED1__SHIFT, 1
+.set LED1__SLW, CYREG_PRT0_SLW
-/* SD_RX_DMA_COMPLETE */
-.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x10
-.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 4
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4
-.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* SD_CD */
+.set SD_CD__0__MASK, 0x20
+.set SD_CD__0__PC, CYREG_PRT3_PC5
+.set SD_CD__0__PORT, 3
+.set SD_CD__0__SHIFT, 5
+.set SD_CD__AG, CYREG_PRT3_AG
+.set SD_CD__AMUX, CYREG_PRT3_AMUX
+.set SD_CD__BIE, CYREG_PRT3_BIE
+.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_CD__BYP, CYREG_PRT3_BYP
+.set SD_CD__CTL, CYREG_PRT3_CTL
+.set SD_CD__DM0, CYREG_PRT3_DM0
+.set SD_CD__DM1, CYREG_PRT3_DM1
+.set SD_CD__DM2, CYREG_PRT3_DM2
+.set SD_CD__DR, CYREG_PRT3_DR
+.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_CD__MASK, 0x20
+.set SD_CD__PORT, 3
+.set SD_CD__PRT, CYREG_PRT3_PRT
+.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_CD__PS, CYREG_PRT3_PS
+.set SD_CD__SHIFT, 5
+.set SD_CD__SLW, CYREG_PRT3_SLW
-/* SD_TX_DMA_COMPLETE */
-.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x20
-.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 5
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
-.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5
-.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* SD_CS */
+.set SD_CS__0__MASK, 0x10
+.set SD_CS__0__PC, CYREG_PRT3_PC4
+.set SD_CS__0__PORT, 3
+.set SD_CS__0__SHIFT, 4
+.set SD_CS__AG, CYREG_PRT3_AG
+.set SD_CS__AMUX, CYREG_PRT3_AMUX
+.set SD_CS__BIE, CYREG_PRT3_BIE
+.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_CS__BYP, CYREG_PRT3_BYP
+.set SD_CS__CTL, CYREG_PRT3_CTL
+.set SD_CS__DM0, CYREG_PRT3_DM0
+.set SD_CS__DM1, CYREG_PRT3_DM1
+.set SD_CS__DM2, CYREG_PRT3_DM2
+.set SD_CS__DR, CYREG_PRT3_DR
+.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_CS__MASK, 0x10
+.set SD_CS__PORT, 3
+.set SD_CS__PRT, CYREG_PRT3_PRT
+.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_CS__PS, CYREG_PRT3_PS
+.set SD_CS__SHIFT, 4
+.set SD_CS__SLW, CYREG_PRT3_SLW
-/* SCSI_Parity_Error */
-.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
-.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST
+/* USBFS_arb_int */
+.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_arb_int__INTC_MASK, 0x400000
+.set USBFS_arb_int__INTC_NUMBER, 22
+.set USBFS_arb_int__INTC_PRIOR_NUM, 7
+.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22
+.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* USBFS_bus_reset */
.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-/* SCSI_CTL_PHASE */
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
+/* USBFS_Dm */
+.set USBFS_Dm__0__MASK, 0x80
+.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1
+.set USBFS_Dm__0__PORT, 15
+.set USBFS_Dm__0__SHIFT, 7
+.set USBFS_Dm__AG, CYREG_PRT15_AG
+.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX
+.set USBFS_Dm__BIE, CYREG_PRT15_BIE
+.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set USBFS_Dm__BYP, CYREG_PRT15_BYP
+.set USBFS_Dm__CTL, CYREG_PRT15_CTL
+.set USBFS_Dm__DM0, CYREG_PRT15_DM0
+.set USBFS_Dm__DM1, CYREG_PRT15_DM1
+.set USBFS_Dm__DM2, CYREG_PRT15_DM2
+.set USBFS_Dm__DR, CYREG_PRT15_DR
+.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS
+.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN
+.set USBFS_Dm__MASK, 0x80
+.set USBFS_Dm__PORT, 15
+.set USBFS_Dm__PRT, CYREG_PRT15_PRT
+.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set USBFS_Dm__PS, CYREG_PRT15_PS
+.set USBFS_Dm__SHIFT, 7
+.set USBFS_Dm__SLW, CYREG_PRT15_SLW
-/* SCSI_Filtered */
-.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01
-.set SCSI_Filtered_sts_sts_reg__0__POS, 0
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST
-.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
-.set SCSI_Filtered_sts_sts_reg__1__POS, 1
-.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
-.set SCSI_Filtered_sts_sts_reg__2__POS, 2
-.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
-.set SCSI_Filtered_sts_sts_reg__3__POS, 3
-.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
-.set SCSI_Filtered_sts_sts_reg__4__POS, 4
-.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB00_MSK
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB00_ST
+/* USBFS_Dp */
+.set USBFS_Dp__0__MASK, 0x40
+.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0
+.set USBFS_Dp__0__PORT, 15
+.set USBFS_Dp__0__SHIFT, 6
+.set USBFS_Dp__AG, CYREG_PRT15_AG
+.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX
+.set USBFS_Dp__BIE, CYREG_PRT15_BIE
+.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set USBFS_Dp__BYP, CYREG_PRT15_BYP
+.set USBFS_Dp__CTL, CYREG_PRT15_CTL
+.set USBFS_Dp__DM0, CYREG_PRT15_DM0
+.set USBFS_Dp__DM1, CYREG_PRT15_DM1
+.set USBFS_Dp__DM2, CYREG_PRT15_DM2
+.set USBFS_Dp__DR, CYREG_PRT15_DR
+.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS
+.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT
+.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN
+.set USBFS_Dp__MASK, 0x40
+.set USBFS_Dp__PORT, 15
+.set USBFS_Dp__PRT, CYREG_PRT15_PRT
+.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set USBFS_Dp__PS, CYREG_PRT15_PS
+.set USBFS_Dp__SHIFT, 6
+.set USBFS_Dp__SLW, CYREG_PRT15_SLW
+.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15
-/* SCSI_Out_Bits */
-.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01
-.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
-.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
-.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
-.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
-.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
-.set SCSI_Out_Bits_Sync_ctrl_reg__3__POS, 3
-.set SCSI_Out_Bits_Sync_ctrl_reg__4__MASK, 0x10
-.set SCSI_Out_Bits_Sync_ctrl_reg__4__POS, 4
-.set SCSI_Out_Bits_Sync_ctrl_reg__5__MASK, 0x20
-.set SCSI_Out_Bits_Sync_ctrl_reg__5__POS, 5
-.set SCSI_Out_Bits_Sync_ctrl_reg__6__MASK, 0x40
-.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
-.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
-.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+/* USBFS_dp_int */
+.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_dp_int__INTC_MASK, 0x1000
+.set USBFS_dp_int__INTC_NUMBER, 12
+.set USBFS_dp_int__INTC_PRIOR_NUM, 7
+.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12
+.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-/* USBFS_arb_int */
-.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_arb_int__INTC_MASK, 0x400000
-.set USBFS_arb_int__INTC_NUMBER, 22
-.set USBFS_arb_int__INTC_PRIOR_NUM, 7
-.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22
-.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* USBFS_ep_0 */
+.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_0__INTC_MASK, 0x1000000
+.set USBFS_ep_0__INTC_NUMBER, 24
+.set USBFS_ep_0__INTC_PRIOR_NUM, 7
+.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24
+.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_1 */
+.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_1__INTC_MASK, 0x40
+.set USBFS_ep_1__INTC_NUMBER, 6
+.set USBFS_ep_1__INTC_PRIOR_NUM, 7
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_6
+.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_2 */
+.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_2__INTC_MASK, 0x80
+.set USBFS_ep_2__INTC_NUMBER, 7
+.set USBFS_ep_2__INTC_PRIOR_NUM, 7
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_7
+.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_3 */
+.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_3__INTC_MASK, 0x100
+.set USBFS_ep_3__INTC_NUMBER, 8
+.set USBFS_ep_3__INTC_PRIOR_NUM, 7
+.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_8
+.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_4 */
+.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_4__INTC_MASK, 0x200
+.set USBFS_ep_4__INTC_NUMBER, 9
+.set USBFS_ep_4__INTC_PRIOR_NUM, 7
+.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_9
+.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* USBFS_sof_int */
.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-/* SCSI_Out_Ctl */
-.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
+/* USBFS_USB */
+.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG
+.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG
+.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN
+.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR
+.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG
+.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN
+.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR
+.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG
+.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN
+.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR
+.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG
+.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN
+.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR
+.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG
+.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN
+.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR
+.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG
+.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN
+.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR
+.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG
+.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN
+.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR
+.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG
+.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN
+.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR
+.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN
+.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR
+.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR
+.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA
+.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB
+.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA
+.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB
+.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR
+.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA
+.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB
+.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA
+.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB
+.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR
+.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA
+.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB
+.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA
+.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB
+.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR
+.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA
+.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB
+.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA
+.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB
+.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR
+.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA
+.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB
+.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA
+.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB
+.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR
+.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA
+.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB
+.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA
+.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB
+.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR
+.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA
+.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB
+.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA
+.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB
+.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR
+.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA
+.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB
+.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA
+.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB
+.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE
+.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT
+.set USBFS_USB__CR0, CYREG_USB_CR0
+.set USBFS_USB__CR1, CYREG_USB_CR1
+.set USBFS_USB__CWA, CYREG_USB_CWA
+.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB
+.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES
+.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB
+.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG
+.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE
+.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE
+.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT
+.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR
+.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0
+.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1
+.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2
+.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3
+.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4
+.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5
+.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6
+.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7
+.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE
+.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5
+.set USBFS_USB__PM_ACT_MSK, 0x01
+.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5
+.set USBFS_USB__PM_STBY_MSK, 0x01
+.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN
+.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR
+.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0
+.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1
+.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0
+.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0
+.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1
+.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0
+.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0
+.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1
+.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0
+.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0
+.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1
+.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0
+.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0
+.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1
+.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0
+.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0
+.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1
+.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0
+.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0
+.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1
+.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0
+.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0
+.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1
+.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0
+.set USBFS_USB__SOF0, CYREG_USB_SOF0
+.set USBFS_USB__SOF1, CYREG_USB_SOF1
+.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN
+.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0
+.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
-/* SCSI_Out_DBx */
-.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
-.set SCSI_Out_DBx__0__AMUX, CYREG_PRT5_AMUX
-.set SCSI_Out_DBx__0__BIE, CYREG_PRT5_BIE
-.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_Out_DBx__0__BYP, CYREG_PRT5_BYP
-.set SCSI_Out_DBx__0__CTL, CYREG_PRT5_CTL
-.set SCSI_Out_DBx__0__DM0, CYREG_PRT5_DM0
-.set SCSI_Out_DBx__0__DM1, CYREG_PRT5_DM1
-.set SCSI_Out_DBx__0__DM2, CYREG_PRT5_DM2
-.set SCSI_Out_DBx__0__DR, CYREG_PRT5_DR
-.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_Out_DBx__0__MASK, 0x02
-.set SCSI_Out_DBx__0__PC, CYREG_PRT5_PC1
-.set SCSI_Out_DBx__0__PORT, 5
-.set SCSI_Out_DBx__0__PRT, CYREG_PRT5_PRT
-.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_Out_DBx__0__PS, CYREG_PRT5_PS
-.set SCSI_Out_DBx__0__SHIFT, 1
-.set SCSI_Out_DBx__0__SLW, CYREG_PRT5_SLW
-.set SCSI_Out_DBx__1__AG, CYREG_PRT5_AG
-.set SCSI_Out_DBx__1__AMUX, CYREG_PRT5_AMUX
-.set SCSI_Out_DBx__1__BIE, CYREG_PRT5_BIE
-.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_Out_DBx__1__BYP, CYREG_PRT5_BYP
-.set SCSI_Out_DBx__1__CTL, CYREG_PRT5_CTL
-.set SCSI_Out_DBx__1__DM0, CYREG_PRT5_DM0
-.set SCSI_Out_DBx__1__DM1, CYREG_PRT5_DM1
-.set SCSI_Out_DBx__1__DM2, CYREG_PRT5_DM2
-.set SCSI_Out_DBx__1__DR, CYREG_PRT5_DR
-.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_Out_DBx__1__MASK, 0x01
-.set SCSI_Out_DBx__1__PC, CYREG_PRT5_PC0
-.set SCSI_Out_DBx__1__PORT, 5
-.set SCSI_Out_DBx__1__PRT, CYREG_PRT5_PRT
-.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_Out_DBx__1__PS, CYREG_PRT5_PS
-.set SCSI_Out_DBx__1__SHIFT, 0
-.set SCSI_Out_DBx__1__SLW, CYREG_PRT5_SLW
-.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__2__MASK, 0x20
-.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC5
-.set SCSI_Out_DBx__2__PORT, 6
-.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__2__SHIFT, 5
-.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__3__MASK, 0x10
-.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC4
-.set SCSI_Out_DBx__3__PORT, 6
-.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__3__SHIFT, 4
-.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__4__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__4__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__4__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__4__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__4__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__4__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__4__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__4__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__4__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__4__MASK, 0x80
-.set SCSI_Out_DBx__4__PC, CYREG_PRT2_PC7
-.set SCSI_Out_DBx__4__PORT, 2
-.set SCSI_Out_DBx__4__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__4__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__4__SHIFT, 7
-.set SCSI_Out_DBx__4__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__5__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__5__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__5__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__5__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__5__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__5__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__5__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__5__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__5__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__5__MASK, 0x40
-.set SCSI_Out_DBx__5__PC, CYREG_PRT2_PC6
-.set SCSI_Out_DBx__5__PORT, 2
-.set SCSI_Out_DBx__5__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__5__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__5__SHIFT, 6
-.set SCSI_Out_DBx__5__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__6__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__6__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__6__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__6__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__6__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__6__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__6__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__6__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__6__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__6__MASK, 0x08
-.set SCSI_Out_DBx__6__PC, CYREG_PRT2_PC3
-.set SCSI_Out_DBx__6__PORT, 2
-.set SCSI_Out_DBx__6__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__6__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__6__SHIFT, 3
-.set SCSI_Out_DBx__6__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__7__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__7__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__7__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__7__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__7__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__7__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__7__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__7__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__7__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__7__MASK, 0x04
-.set SCSI_Out_DBx__7__PC, CYREG_PRT2_PC2
-.set SCSI_Out_DBx__7__PORT, 2
-.set SCSI_Out_DBx__7__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__7__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__7__SHIFT, 2
-.set SCSI_Out_DBx__7__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB0__AG, CYREG_PRT5_AG
-.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT5_AMUX
-.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT5_BIE
-.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT5_BYP
-.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT5_CTL
-.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT5_DM0
-.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT5_DM1
-.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT5_DM2
-.set SCSI_Out_DBx__DB0__DR, CYREG_PRT5_DR
-.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_Out_DBx__DB0__MASK, 0x02
-.set SCSI_Out_DBx__DB0__PC, CYREG_PRT5_PC1
-.set SCSI_Out_DBx__DB0__PORT, 5
-.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT5_PRT
-.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_Out_DBx__DB0__PS, CYREG_PRT5_PS
-.set SCSI_Out_DBx__DB0__SHIFT, 1
-.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT5_SLW
-.set SCSI_Out_DBx__DB1__AG, CYREG_PRT5_AG
-.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT5_AMUX
-.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT5_BIE
-.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT5_BYP
-.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT5_CTL
-.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT5_DM0
-.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT5_DM1
-.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT5_DM2
-.set SCSI_Out_DBx__DB1__DR, CYREG_PRT5_DR
-.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_Out_DBx__DB1__MASK, 0x01
-.set SCSI_Out_DBx__DB1__PC, CYREG_PRT5_PC0
-.set SCSI_Out_DBx__DB1__PORT, 5
-.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT5_PRT
-.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_Out_DBx__DB1__PS, CYREG_PRT5_PS
-.set SCSI_Out_DBx__DB1__SHIFT, 0
-.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT5_SLW
-.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__DB2__MASK, 0x20
-.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC5
-.set SCSI_Out_DBx__DB2__PORT, 6
-.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__DB2__SHIFT, 5
-.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__DB3__MASK, 0x10
-.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC4
-.set SCSI_Out_DBx__DB3__PORT, 6
-.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__DB3__SHIFT, 4
-.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__DB4__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB4__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB4__MASK, 0x80
-.set SCSI_Out_DBx__DB4__PC, CYREG_PRT2_PC7
-.set SCSI_Out_DBx__DB4__PORT, 2
-.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB4__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB4__SHIFT, 7
-.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB5__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB5__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB5__MASK, 0x40
-.set SCSI_Out_DBx__DB5__PC, CYREG_PRT2_PC6
-.set SCSI_Out_DBx__DB5__PORT, 2
-.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB5__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB5__SHIFT, 6
-.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB6__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB6__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB6__MASK, 0x08
-.set SCSI_Out_DBx__DB6__PC, CYREG_PRT2_PC3
-.set SCSI_Out_DBx__DB6__PORT, 2
-.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB6__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB6__SHIFT, 3
-.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB7__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB7__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB7__MASK, 0x04
-.set SCSI_Out_DBx__DB7__PC, CYREG_PRT2_PC2
-.set SCSI_Out_DBx__DB7__PORT, 2
-.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB7__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB7__SHIFT, 2
-.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT2_SLW
-
-/* SCSI_RST_ISR */
-.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set SCSI_RST_ISR__INTC_MASK, 0x04
-.set SCSI_RST_ISR__INTC_NUMBER, 2
-.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7
-.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_2
-.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SDCard_BSPIM */
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB09_10_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB09_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB09_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB09_ST
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_10_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB09_10_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB09_10_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB09_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB09_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB09_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB09_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB09_MSK
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB09_MSK_ACTL
-.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
-.set SDCard_BSPIM_RxStsReg__4__POS, 4
-.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
-.set SDCard_BSPIM_RxStsReg__5__POS, 5
-.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
-.set SDCard_BSPIM_RxStsReg__6__POS, 6
-.set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB11_MSK
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB11_ST
-.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
-.set SDCard_BSPIM_TxStsReg__0__POS, 0
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB10_11_ST
-.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
-.set SDCard_BSPIM_TxStsReg__1__POS, 1
-.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
-.set SDCard_BSPIM_TxStsReg__2__POS, 2
-.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
-.set SDCard_BSPIM_TxStsReg__3__POS, 3
-.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
-.set SDCard_BSPIM_TxStsReg__4__POS, 4
-.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB10_MSK
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB10_ST
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB09_10_A0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB09_10_A1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB09_10_D0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB09_10_D1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB09_10_F0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB09_10_F1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB09_A0_A1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB09_A0
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB09_A1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB09_D0_D1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB09_D0
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB09_D1
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB09_F0_F1
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB09_F0
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB09_F1
-
-/* USBFS_dp_int */
-.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_dp_int__INTC_MASK, 0x1000
-.set USBFS_dp_int__INTC_NUMBER, 12
-.set USBFS_dp_int__INTC_PRIOR_NUM, 7
-.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12
-.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SCSI_In_DBx */
-.set SCSI_In_DBx__0__AG, CYREG_PRT5_AG
-.set SCSI_In_DBx__0__AMUX, CYREG_PRT5_AMUX
-.set SCSI_In_DBx__0__BIE, CYREG_PRT5_BIE
-.set SCSI_In_DBx__0__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_In_DBx__0__BYP, CYREG_PRT5_BYP
-.set SCSI_In_DBx__0__CTL, CYREG_PRT5_CTL
-.set SCSI_In_DBx__0__DM0, CYREG_PRT5_DM0
-.set SCSI_In_DBx__0__DM1, CYREG_PRT5_DM1
-.set SCSI_In_DBx__0__DM2, CYREG_PRT5_DM2
-.set SCSI_In_DBx__0__DR, CYREG_PRT5_DR
-.set SCSI_In_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_In_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_In_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_In_DBx__0__MASK, 0x08
-.set SCSI_In_DBx__0__PC, CYREG_PRT5_PC3
-.set SCSI_In_DBx__0__PORT, 5
-.set SCSI_In_DBx__0__PRT, CYREG_PRT5_PRT
-.set SCSI_In_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_In_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_In_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_In_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_In_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_In_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_In_DBx__0__PS, CYREG_PRT5_PS
-.set SCSI_In_DBx__0__SHIFT, 3
-.set SCSI_In_DBx__0__SLW, CYREG_PRT5_SLW
-.set SCSI_In_DBx__1__AG, CYREG_PRT5_AG
-.set SCSI_In_DBx__1__AMUX, CYREG_PRT5_AMUX
-.set SCSI_In_DBx__1__BIE, CYREG_PRT5_BIE
-.set SCSI_In_DBx__1__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_In_DBx__1__BYP, CYREG_PRT5_BYP
-.set SCSI_In_DBx__1__CTL, CYREG_PRT5_CTL
-.set SCSI_In_DBx__1__DM0, CYREG_PRT5_DM0
-.set SCSI_In_DBx__1__DM1, CYREG_PRT5_DM1
-.set SCSI_In_DBx__1__DM2, CYREG_PRT5_DM2
-.set SCSI_In_DBx__1__DR, CYREG_PRT5_DR
-.set SCSI_In_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_In_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_In_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_In_DBx__1__MASK, 0x04
-.set SCSI_In_DBx__1__PC, CYREG_PRT5_PC2
-.set SCSI_In_DBx__1__PORT, 5
-.set SCSI_In_DBx__1__PRT, CYREG_PRT5_PRT
-.set SCSI_In_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_In_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_In_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_In_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_In_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_In_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_In_DBx__1__PS, CYREG_PRT5_PS
-.set SCSI_In_DBx__1__SHIFT, 2
-.set SCSI_In_DBx__1__SLW, CYREG_PRT5_SLW
-.set SCSI_In_DBx__2__AG, CYREG_PRT6_AG
-.set SCSI_In_DBx__2__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In_DBx__2__BIE, CYREG_PRT6_BIE
-.set SCSI_In_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In_DBx__2__BYP, CYREG_PRT6_BYP
-.set SCSI_In_DBx__2__CTL, CYREG_PRT6_CTL
-.set SCSI_In_DBx__2__DM0, CYREG_PRT6_DM0
-.set SCSI_In_DBx__2__DM1, CYREG_PRT6_DM1
-.set SCSI_In_DBx__2__DM2, CYREG_PRT6_DM2
-.set SCSI_In_DBx__2__DR, CYREG_PRT6_DR
-.set SCSI_In_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In_DBx__2__MASK, 0x80
-.set SCSI_In_DBx__2__PC, CYREG_PRT6_PC7
-.set SCSI_In_DBx__2__PORT, 6
-.set SCSI_In_DBx__2__PRT, CYREG_PRT6_PRT
-.set SCSI_In_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In_DBx__2__PS, CYREG_PRT6_PS
-.set SCSI_In_DBx__2__SHIFT, 7
-.set SCSI_In_DBx__2__SLW, CYREG_PRT6_SLW
-.set SCSI_In_DBx__3__AG, CYREG_PRT6_AG
-.set SCSI_In_DBx__3__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In_DBx__3__BIE, CYREG_PRT6_BIE
-.set SCSI_In_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In_DBx__3__BYP, CYREG_PRT6_BYP
-.set SCSI_In_DBx__3__CTL, CYREG_PRT6_CTL
-.set SCSI_In_DBx__3__DM0, CYREG_PRT6_DM0
-.set SCSI_In_DBx__3__DM1, CYREG_PRT6_DM1
-.set SCSI_In_DBx__3__DM2, CYREG_PRT6_DM2
-.set SCSI_In_DBx__3__DR, CYREG_PRT6_DR
-.set SCSI_In_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In_DBx__3__MASK, 0x40
-.set SCSI_In_DBx__3__PC, CYREG_PRT6_PC6
-.set SCSI_In_DBx__3__PORT, 6
-.set SCSI_In_DBx__3__PRT, CYREG_PRT6_PRT
-.set SCSI_In_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In_DBx__3__PS, CYREG_PRT6_PS
-.set SCSI_In_DBx__3__SHIFT, 6
-.set SCSI_In_DBx__3__SLW, CYREG_PRT6_SLW
-.set SCSI_In_DBx__4__AG, CYREG_PRT12_AG
-.set SCSI_In_DBx__4__BIE, CYREG_PRT12_BIE
-.set SCSI_In_DBx__4__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_In_DBx__4__BYP, CYREG_PRT12_BYP
-.set SCSI_In_DBx__4__DM0, CYREG_PRT12_DM0
-.set SCSI_In_DBx__4__DM1, CYREG_PRT12_DM1
-.set SCSI_In_DBx__4__DM2, CYREG_PRT12_DM2
-.set SCSI_In_DBx__4__DR, CYREG_PRT12_DR
-.set SCSI_In_DBx__4__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_In_DBx__4__MASK, 0x20
-.set SCSI_In_DBx__4__PC, CYREG_PRT12_PC5
-.set SCSI_In_DBx__4__PORT, 12
-.set SCSI_In_DBx__4__PRT, CYREG_PRT12_PRT
-.set SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_In_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_In_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_In_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_In_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_In_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_In_DBx__4__PS, CYREG_PRT12_PS
-.set SCSI_In_DBx__4__SHIFT, 5
-.set SCSI_In_DBx__4__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_In_DBx__4__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_In_DBx__4__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_In_DBx__4__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_In_DBx__4__SLW, CYREG_PRT12_SLW
-.set SCSI_In_DBx__5__AG, CYREG_PRT12_AG
-.set SCSI_In_DBx__5__BIE, CYREG_PRT12_BIE
-.set SCSI_In_DBx__5__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_In_DBx__5__BYP, CYREG_PRT12_BYP
-.set SCSI_In_DBx__5__DM0, CYREG_PRT12_DM0
-.set SCSI_In_DBx__5__DM1, CYREG_PRT12_DM1
-.set SCSI_In_DBx__5__DM2, CYREG_PRT12_DM2
-.set SCSI_In_DBx__5__DR, CYREG_PRT12_DR
-.set SCSI_In_DBx__5__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_In_DBx__5__MASK, 0x10
-.set SCSI_In_DBx__5__PC, CYREG_PRT12_PC4
-.set SCSI_In_DBx__5__PORT, 12
-.set SCSI_In_DBx__5__PRT, CYREG_PRT12_PRT
-.set SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_In_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_In_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_In_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_In_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_In_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_In_DBx__5__PS, CYREG_PRT12_PS
-.set SCSI_In_DBx__5__SHIFT, 4
-.set SCSI_In_DBx__5__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_In_DBx__5__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_In_DBx__5__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_In_DBx__5__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_In_DBx__5__SLW, CYREG_PRT12_SLW
-.set SCSI_In_DBx__6__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__6__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__6__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__6__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__6__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__6__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__6__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__6__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__6__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__6__MASK, 0x20
-.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC5
-.set SCSI_In_DBx__6__PORT, 2
-.set SCSI_In_DBx__6__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__6__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__6__SHIFT, 5
-.set SCSI_In_DBx__6__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__7__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__7__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__7__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__7__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__7__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__7__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__7__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__7__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__7__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__7__MASK, 0x10
-.set SCSI_In_DBx__7__PC, CYREG_PRT2_PC4
-.set SCSI_In_DBx__7__PORT, 2
-.set SCSI_In_DBx__7__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__7__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__7__SHIFT, 4
-.set SCSI_In_DBx__7__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__DB0__AG, CYREG_PRT5_AG
-.set SCSI_In_DBx__DB0__AMUX, CYREG_PRT5_AMUX
-.set SCSI_In_DBx__DB0__BIE, CYREG_PRT5_BIE
-.set SCSI_In_DBx__DB0__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_In_DBx__DB0__BYP, CYREG_PRT5_BYP
-.set SCSI_In_DBx__DB0__CTL, CYREG_PRT5_CTL
-.set SCSI_In_DBx__DB0__DM0, CYREG_PRT5_DM0
-.set SCSI_In_DBx__DB0__DM1, CYREG_PRT5_DM1
-.set SCSI_In_DBx__DB0__DM2, CYREG_PRT5_DM2
-.set SCSI_In_DBx__DB0__DR, CYREG_PRT5_DR
-.set SCSI_In_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_In_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_In_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_In_DBx__DB0__MASK, 0x08
-.set SCSI_In_DBx__DB0__PC, CYREG_PRT5_PC3
-.set SCSI_In_DBx__DB0__PORT, 5
-.set SCSI_In_DBx__DB0__PRT, CYREG_PRT5_PRT
-.set SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_In_DBx__DB0__PS, CYREG_PRT5_PS
-.set SCSI_In_DBx__DB0__SHIFT, 3
-.set SCSI_In_DBx__DB0__SLW, CYREG_PRT5_SLW
-.set SCSI_In_DBx__DB1__AG, CYREG_PRT5_AG
-.set SCSI_In_DBx__DB1__AMUX, CYREG_PRT5_AMUX
-.set SCSI_In_DBx__DB1__BIE, CYREG_PRT5_BIE
-.set SCSI_In_DBx__DB1__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_In_DBx__DB1__BYP, CYREG_PRT5_BYP
-.set SCSI_In_DBx__DB1__CTL, CYREG_PRT5_CTL
-.set SCSI_In_DBx__DB1__DM0, CYREG_PRT5_DM0
-.set SCSI_In_DBx__DB1__DM1, CYREG_PRT5_DM1
-.set SCSI_In_DBx__DB1__DM2, CYREG_PRT5_DM2
-.set SCSI_In_DBx__DB1__DR, CYREG_PRT5_DR
-.set SCSI_In_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_In_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_In_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_In_DBx__DB1__MASK, 0x04
-.set SCSI_In_DBx__DB1__PC, CYREG_PRT5_PC2
-.set SCSI_In_DBx__DB1__PORT, 5
-.set SCSI_In_DBx__DB1__PRT, CYREG_PRT5_PRT
-.set SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_In_DBx__DB1__PS, CYREG_PRT5_PS
-.set SCSI_In_DBx__DB1__SHIFT, 2
-.set SCSI_In_DBx__DB1__SLW, CYREG_PRT5_SLW
-.set SCSI_In_DBx__DB2__AG, CYREG_PRT6_AG
-.set SCSI_In_DBx__DB2__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In_DBx__DB2__BIE, CYREG_PRT6_BIE
-.set SCSI_In_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In_DBx__DB2__BYP, CYREG_PRT6_BYP
-.set SCSI_In_DBx__DB2__CTL, CYREG_PRT6_CTL
-.set SCSI_In_DBx__DB2__DM0, CYREG_PRT6_DM0
-.set SCSI_In_DBx__DB2__DM1, CYREG_PRT6_DM1
-.set SCSI_In_DBx__DB2__DM2, CYREG_PRT6_DM2
-.set SCSI_In_DBx__DB2__DR, CYREG_PRT6_DR
-.set SCSI_In_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In_DBx__DB2__MASK, 0x80
-.set SCSI_In_DBx__DB2__PC, CYREG_PRT6_PC7
-.set SCSI_In_DBx__DB2__PORT, 6
-.set SCSI_In_DBx__DB2__PRT, CYREG_PRT6_PRT
-.set SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In_DBx__DB2__PS, CYREG_PRT6_PS
-.set SCSI_In_DBx__DB2__SHIFT, 7
-.set SCSI_In_DBx__DB2__SLW, CYREG_PRT6_SLW
-.set SCSI_In_DBx__DB3__AG, CYREG_PRT6_AG
-.set SCSI_In_DBx__DB3__AMUX, CYREG_PRT6_AMUX
-.set SCSI_In_DBx__DB3__BIE, CYREG_PRT6_BIE
-.set SCSI_In_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_In_DBx__DB3__BYP, CYREG_PRT6_BYP
-.set SCSI_In_DBx__DB3__CTL, CYREG_PRT6_CTL
-.set SCSI_In_DBx__DB3__DM0, CYREG_PRT6_DM0
-.set SCSI_In_DBx__DB3__DM1, CYREG_PRT6_DM1
-.set SCSI_In_DBx__DB3__DM2, CYREG_PRT6_DM2
-.set SCSI_In_DBx__DB3__DR, CYREG_PRT6_DR
-.set SCSI_In_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_In_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_In_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_In_DBx__DB3__MASK, 0x40
-.set SCSI_In_DBx__DB3__PC, CYREG_PRT6_PC6
-.set SCSI_In_DBx__DB3__PORT, 6
-.set SCSI_In_DBx__DB3__PRT, CYREG_PRT6_PRT
-.set SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_In_DBx__DB3__PS, CYREG_PRT6_PS
-.set SCSI_In_DBx__DB3__SHIFT, 6
-.set SCSI_In_DBx__DB3__SLW, CYREG_PRT6_SLW
-.set SCSI_In_DBx__DB4__AG, CYREG_PRT12_AG
-.set SCSI_In_DBx__DB4__BIE, CYREG_PRT12_BIE
-.set SCSI_In_DBx__DB4__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_In_DBx__DB4__BYP, CYREG_PRT12_BYP
-.set SCSI_In_DBx__DB4__DM0, CYREG_PRT12_DM0
-.set SCSI_In_DBx__DB4__DM1, CYREG_PRT12_DM1
-.set SCSI_In_DBx__DB4__DM2, CYREG_PRT12_DM2
-.set SCSI_In_DBx__DB4__DR, CYREG_PRT12_DR
-.set SCSI_In_DBx__DB4__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_In_DBx__DB4__MASK, 0x20
-.set SCSI_In_DBx__DB4__PC, CYREG_PRT12_PC5
-.set SCSI_In_DBx__DB4__PORT, 12
-.set SCSI_In_DBx__DB4__PRT, CYREG_PRT12_PRT
-.set SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_In_DBx__DB4__PS, CYREG_PRT12_PS
-.set SCSI_In_DBx__DB4__SHIFT, 5
-.set SCSI_In_DBx__DB4__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_In_DBx__DB4__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_In_DBx__DB4__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_In_DBx__DB4__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_In_DBx__DB4__SLW, CYREG_PRT12_SLW
-.set SCSI_In_DBx__DB5__AG, CYREG_PRT12_AG
-.set SCSI_In_DBx__DB5__BIE, CYREG_PRT12_BIE
-.set SCSI_In_DBx__DB5__BIT_MASK, CYREG_PRT12_BIT_MASK
-.set SCSI_In_DBx__DB5__BYP, CYREG_PRT12_BYP
-.set SCSI_In_DBx__DB5__DM0, CYREG_PRT12_DM0
-.set SCSI_In_DBx__DB5__DM1, CYREG_PRT12_DM1
-.set SCSI_In_DBx__DB5__DM2, CYREG_PRT12_DM2
-.set SCSI_In_DBx__DB5__DR, CYREG_PRT12_DR
-.set SCSI_In_DBx__DB5__INP_DIS, CYREG_PRT12_INP_DIS
-.set SCSI_In_DBx__DB5__MASK, 0x10
-.set SCSI_In_DBx__DB5__PC, CYREG_PRT12_PC4
-.set SCSI_In_DBx__DB5__PORT, 12
-.set SCSI_In_DBx__DB5__PRT, CYREG_PRT12_PRT
-.set SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
-.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
-.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
-.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
-.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
-.set SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
-.set SCSI_In_DBx__DB5__PS, CYREG_PRT12_PS
-.set SCSI_In_DBx__DB5__SHIFT, 4
-.set SCSI_In_DBx__DB5__SIO_CFG, CYREG_PRT12_SIO_CFG
-.set SCSI_In_DBx__DB5__SIO_DIFF, CYREG_PRT12_SIO_DIFF
-.set SCSI_In_DBx__DB5__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
-.set SCSI_In_DBx__DB5__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
-.set SCSI_In_DBx__DB5__SLW, CYREG_PRT12_SLW
-.set SCSI_In_DBx__DB6__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__DB6__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__DB6__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__DB6__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__DB6__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__DB6__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__DB6__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__DB6__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__DB6__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__DB6__MASK, 0x20
-.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC5
-.set SCSI_In_DBx__DB6__PORT, 2
-.set SCSI_In_DBx__DB6__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__DB6__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__DB6__SHIFT, 5
-.set SCSI_In_DBx__DB6__SLW, CYREG_PRT2_SLW
-.set SCSI_In_DBx__DB7__AG, CYREG_PRT2_AG
-.set SCSI_In_DBx__DB7__AMUX, CYREG_PRT2_AMUX
-.set SCSI_In_DBx__DB7__BIE, CYREG_PRT2_BIE
-.set SCSI_In_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_In_DBx__DB7__BYP, CYREG_PRT2_BYP
-.set SCSI_In_DBx__DB7__CTL, CYREG_PRT2_CTL
-.set SCSI_In_DBx__DB7__DM0, CYREG_PRT2_DM0
-.set SCSI_In_DBx__DB7__DM1, CYREG_PRT2_DM1
-.set SCSI_In_DBx__DB7__DM2, CYREG_PRT2_DM2
-.set SCSI_In_DBx__DB7__DR, CYREG_PRT2_DR
-.set SCSI_In_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_In_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_In_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_In_DBx__DB7__MASK, 0x10
-.set SCSI_In_DBx__DB7__PC, CYREG_PRT2_PC4
-.set SCSI_In_DBx__DB7__PORT, 2
-.set SCSI_In_DBx__DB7__PRT, CYREG_PRT2_PRT
-.set SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_In_DBx__DB7__PS, CYREG_PRT2_PS
-.set SCSI_In_DBx__DB7__SHIFT, 4
-.set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW
-
-/* SCSI_RX_DMA */
-.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SCSI_RX_DMA__DRQ_NUMBER, 0
-.set SCSI_RX_DMA__NUMBEROF_TDS, 0
-.set SCSI_RX_DMA__PRIORITY, 2
-.set SCSI_RX_DMA__TERMIN_EN, 0
-.set SCSI_RX_DMA__TERMIN_SEL, 0
-.set SCSI_RX_DMA__TERMOUT0_EN, 1
-.set SCSI_RX_DMA__TERMOUT0_SEL, 0
-.set SCSI_RX_DMA__TERMOUT1_EN, 0
-.set SCSI_RX_DMA__TERMOUT1_SEL, 0
-
-/* SCSI_TX_DMA */
-.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SCSI_TX_DMA__DRQ_NUMBER, 1
-.set SCSI_TX_DMA__NUMBEROF_TDS, 0
-.set SCSI_TX_DMA__PRIORITY, 2
-.set SCSI_TX_DMA__TERMIN_EN, 0
-.set SCSI_TX_DMA__TERMIN_SEL, 0
-.set SCSI_TX_DMA__TERMOUT0_EN, 1
-.set SCSI_TX_DMA__TERMOUT0_SEL, 1
-.set SCSI_TX_DMA__TERMOUT1_EN, 0
-.set SCSI_TX_DMA__TERMOUT1_SEL, 0
-
-/* SD_Data_Clk */
-.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0
-.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1
-.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2
-.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07
-.set SD_Data_Clk__INDEX, 0x00
-.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2
-.set SD_Data_Clk__PM_ACT_MSK, 0x01
-.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2
-.set SD_Data_Clk__PM_STBY_MSK, 0x01
-
-/* timer_clock */
-.set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0
-.set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1
-.set timer_clock__CFG2, CYREG_CLKDIST_DCFG2_CFG2
-.set timer_clock__CFG2_SRC_SEL_MASK, 0x07
-.set timer_clock__INDEX, 0x02
-.set timer_clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2
-.set timer_clock__PM_ACT_MSK, 0x04
-.set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2
-.set timer_clock__PM_STBY_MSK, 0x04
-
-/* SCSI_Noise */
-.set SCSI_Noise__0__AG, CYREG_PRT2_AG
-.set SCSI_Noise__0__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Noise__0__BIE, CYREG_PRT2_BIE
-.set SCSI_Noise__0__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Noise__0__BYP, CYREG_PRT2_BYP
-.set SCSI_Noise__0__CTL, CYREG_PRT2_CTL
-.set SCSI_Noise__0__DM0, CYREG_PRT2_DM0
-.set SCSI_Noise__0__DM1, CYREG_PRT2_DM1
-.set SCSI_Noise__0__DM2, CYREG_PRT2_DM2
-.set SCSI_Noise__0__DR, CYREG_PRT2_DR
-.set SCSI_Noise__0__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Noise__0__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Noise__0__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Noise__0__MASK, 0x01
-.set SCSI_Noise__0__PC, CYREG_PRT2_PC0
-.set SCSI_Noise__0__PORT, 2
-.set SCSI_Noise__0__PRT, CYREG_PRT2_PRT
-.set SCSI_Noise__0__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Noise__0__PS, CYREG_PRT2_PS
-.set SCSI_Noise__0__SHIFT, 0
-.set SCSI_Noise__0__SLW, CYREG_PRT2_SLW
-.set SCSI_Noise__1__AG, CYREG_PRT6_AG
-.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE
-.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP
-.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL
-.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0
-.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1
-.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2
-.set SCSI_Noise__1__DR, CYREG_PRT6_DR
-.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Noise__1__MASK, 0x08
-.set SCSI_Noise__1__PC, CYREG_PRT6_PC3
-.set SCSI_Noise__1__PORT, 6
-.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT
-.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Noise__1__PS, CYREG_PRT6_PS
-.set SCSI_Noise__1__SHIFT, 3
-.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW
-.set SCSI_Noise__2__AG, CYREG_PRT4_AG
-.set SCSI_Noise__2__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Noise__2__BIE, CYREG_PRT4_BIE
-.set SCSI_Noise__2__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Noise__2__BYP, CYREG_PRT4_BYP
-.set SCSI_Noise__2__CTL, CYREG_PRT4_CTL
-.set SCSI_Noise__2__DM0, CYREG_PRT4_DM0
-.set SCSI_Noise__2__DM1, CYREG_PRT4_DM1
-.set SCSI_Noise__2__DM2, CYREG_PRT4_DM2
-.set SCSI_Noise__2__DR, CYREG_PRT4_DR
-.set SCSI_Noise__2__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Noise__2__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Noise__2__MASK, 0x08
-.set SCSI_Noise__2__PC, CYREG_PRT4_PC3
-.set SCSI_Noise__2__PORT, 4
-.set SCSI_Noise__2__PRT, CYREG_PRT4_PRT
-.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Noise__2__PS, CYREG_PRT4_PS
-.set SCSI_Noise__2__SHIFT, 3
-.set SCSI_Noise__2__SLW, CYREG_PRT4_SLW
-.set SCSI_Noise__3__AG, CYREG_PRT4_AG
-.set SCSI_Noise__3__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Noise__3__BIE, CYREG_PRT4_BIE
-.set SCSI_Noise__3__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Noise__3__BYP, CYREG_PRT4_BYP
-.set SCSI_Noise__3__CTL, CYREG_PRT4_CTL
-.set SCSI_Noise__3__DM0, CYREG_PRT4_DM0
-.set SCSI_Noise__3__DM1, CYREG_PRT4_DM1
-.set SCSI_Noise__3__DM2, CYREG_PRT4_DM2
-.set SCSI_Noise__3__DR, CYREG_PRT4_DR
-.set SCSI_Noise__3__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Noise__3__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Noise__3__MASK, 0x80
-.set SCSI_Noise__3__PC, CYREG_PRT4_PC7
-.set SCSI_Noise__3__PORT, 4
-.set SCSI_Noise__3__PRT, CYREG_PRT4_PRT
-.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Noise__3__PS, CYREG_PRT4_PS
-.set SCSI_Noise__3__SHIFT, 7
-.set SCSI_Noise__3__SLW, CYREG_PRT4_SLW
-.set SCSI_Noise__4__AG, CYREG_PRT6_AG
-.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE
-.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP
-.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL
-.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0
-.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1
-.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2
-.set SCSI_Noise__4__DR, CYREG_PRT6_DR
-.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Noise__4__MASK, 0x04
-.set SCSI_Noise__4__PC, CYREG_PRT6_PC2
-.set SCSI_Noise__4__PORT, 6
-.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT
-.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Noise__4__PS, CYREG_PRT6_PS
-.set SCSI_Noise__4__SHIFT, 2
-.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW
-.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG
-.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE
-.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP
-.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL
-.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0
-.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1
-.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2
-.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR
-.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Noise__ACK__MASK, 0x04
-.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC2
-.set SCSI_Noise__ACK__PORT, 6
-.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT
-.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS
-.set SCSI_Noise__ACK__SHIFT, 2
-.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW
-.set SCSI_Noise__ATN__AG, CYREG_PRT2_AG
-.set SCSI_Noise__ATN__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Noise__ATN__BIE, CYREG_PRT2_BIE
-.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Noise__ATN__BYP, CYREG_PRT2_BYP
-.set SCSI_Noise__ATN__CTL, CYREG_PRT2_CTL
-.set SCSI_Noise__ATN__DM0, CYREG_PRT2_DM0
-.set SCSI_Noise__ATN__DM1, CYREG_PRT2_DM1
-.set SCSI_Noise__ATN__DM2, CYREG_PRT2_DM2
-.set SCSI_Noise__ATN__DR, CYREG_PRT2_DR
-.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Noise__ATN__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Noise__ATN__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Noise__ATN__MASK, 0x01
-.set SCSI_Noise__ATN__PC, CYREG_PRT2_PC0
-.set SCSI_Noise__ATN__PORT, 2
-.set SCSI_Noise__ATN__PRT, CYREG_PRT2_PRT
-.set SCSI_Noise__ATN__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Noise__ATN__PS, CYREG_PRT2_PS
-.set SCSI_Noise__ATN__SHIFT, 0
-.set SCSI_Noise__ATN__SLW, CYREG_PRT2_SLW
-.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG
-.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE
-.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP
-.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL
-.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0
-.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1
-.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2
-.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR
-.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Noise__BSY__MASK, 0x08
-.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC3
-.set SCSI_Noise__BSY__PORT, 6
-.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT
-.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS
-.set SCSI_Noise__BSY__SHIFT, 3
-.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW
-.set SCSI_Noise__RST__AG, CYREG_PRT4_AG
-.set SCSI_Noise__RST__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Noise__RST__BIE, CYREG_PRT4_BIE
-.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Noise__RST__BYP, CYREG_PRT4_BYP
-.set SCSI_Noise__RST__CTL, CYREG_PRT4_CTL
-.set SCSI_Noise__RST__DM0, CYREG_PRT4_DM0
-.set SCSI_Noise__RST__DM1, CYREG_PRT4_DM1
-.set SCSI_Noise__RST__DM2, CYREG_PRT4_DM2
-.set SCSI_Noise__RST__DR, CYREG_PRT4_DR
-.set SCSI_Noise__RST__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Noise__RST__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Noise__RST__MASK, 0x80
-.set SCSI_Noise__RST__PC, CYREG_PRT4_PC7
-.set SCSI_Noise__RST__PORT, 4
-.set SCSI_Noise__RST__PRT, CYREG_PRT4_PRT
-.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Noise__RST__PS, CYREG_PRT4_PS
-.set SCSI_Noise__RST__SHIFT, 7
-.set SCSI_Noise__RST__SLW, CYREG_PRT4_SLW
-.set SCSI_Noise__SEL__AG, CYREG_PRT4_AG
-.set SCSI_Noise__SEL__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Noise__SEL__BIE, CYREG_PRT4_BIE
-.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Noise__SEL__BYP, CYREG_PRT4_BYP
-.set SCSI_Noise__SEL__CTL, CYREG_PRT4_CTL
-.set SCSI_Noise__SEL__DM0, CYREG_PRT4_DM0
-.set SCSI_Noise__SEL__DM1, CYREG_PRT4_DM1
-.set SCSI_Noise__SEL__DM2, CYREG_PRT4_DM2
-.set SCSI_Noise__SEL__DR, CYREG_PRT4_DR
-.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Noise__SEL__MASK, 0x08
-.set SCSI_Noise__SEL__PC, CYREG_PRT4_PC3
-.set SCSI_Noise__SEL__PORT, 4
-.set SCSI_Noise__SEL__PRT, CYREG_PRT4_PRT
-.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Noise__SEL__PS, CYREG_PRT4_PS
-.set SCSI_Noise__SEL__SHIFT, 3
-.set SCSI_Noise__SEL__SLW, CYREG_PRT4_SLW
-
-/* scsiTarget */
-.set scsiTarget_StatusReg__0__MASK, 0x01
-.set scsiTarget_StatusReg__0__POS, 0
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
-.set scsiTarget_StatusReg__1__MASK, 0x02
-.set scsiTarget_StatusReg__1__POS, 1
-.set scsiTarget_StatusReg__2__MASK, 0x04
-.set scsiTarget_StatusReg__2__POS, 2
-.set scsiTarget_StatusReg__3__MASK, 0x08
-.set scsiTarget_StatusReg__3__POS, 3
-.set scsiTarget_StatusReg__4__MASK, 0x10
-.set scsiTarget_StatusReg__4__POS, 4
-.set scsiTarget_StatusReg__MASK, 0x1F
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB03_MSK
-.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
-.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
-.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL
-.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB03_ST
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB12_MSK
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB12_ST_CTL
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB12_ST_CTL
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB12_ST
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB12_CTL
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB12_CTL
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB12_MSK
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB12_13_A0
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB12_13_A1
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB12_13_D0
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB12_13_D1
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB12_13_F0
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB12_13_F1
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB12_A0_A1
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB12_A0
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB12_A1
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB12_D0_D1
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB12_D0
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB12_D1
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB12_F0_F1
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB12_F0
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB12_F1
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-
-/* USBFS_ep_0 */
-.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_0__INTC_MASK, 0x1000000
-.set USBFS_ep_0__INTC_NUMBER, 24
-.set USBFS_ep_0__INTC_PRIOR_NUM, 7
-.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24
-.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_1 */
-.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_1__INTC_MASK, 0x40
-.set USBFS_ep_1__INTC_NUMBER, 6
-.set USBFS_ep_1__INTC_PRIOR_NUM, 7
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_6
-.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_2 */
-.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_2__INTC_MASK, 0x80
-.set USBFS_ep_2__INTC_NUMBER, 7
-.set USBFS_ep_2__INTC_PRIOR_NUM, 7
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_7
-.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_3 */
-.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_3__INTC_MASK, 0x100
-.set USBFS_ep_3__INTC_NUMBER, 8
-.set USBFS_ep_3__INTC_PRIOR_NUM, 7
-.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_8
-.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_4 */
-.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_4__INTC_MASK, 0x200
-.set USBFS_ep_4__INTC_NUMBER, 9
-.set USBFS_ep_4__INTC_PRIOR_NUM, 7
-.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_9
-.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SD_RX_DMA */
-.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SD_RX_DMA__DRQ_NUMBER, 2
-.set SD_RX_DMA__NUMBEROF_TDS, 0
-.set SD_RX_DMA__PRIORITY, 2
-.set SD_RX_DMA__TERMIN_EN, 0
-.set SD_RX_DMA__TERMIN_SEL, 0
-.set SD_RX_DMA__TERMOUT0_EN, 1
-.set SD_RX_DMA__TERMOUT0_SEL, 2
-.set SD_RX_DMA__TERMOUT1_EN, 0
-.set SD_RX_DMA__TERMOUT1_SEL, 0
-
-/* SD_TX_DMA */
-.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
-.set SD_TX_DMA__DRQ_NUMBER, 3
-.set SD_TX_DMA__NUMBEROF_TDS, 0
-.set SD_TX_DMA__PRIORITY, 2
-.set SD_TX_DMA__TERMIN_EN, 0
-.set SD_TX_DMA__TERMIN_SEL, 0
-.set SD_TX_DMA__TERMOUT0_EN, 1
-.set SD_TX_DMA__TERMOUT0_SEL, 3
-.set SD_TX_DMA__TERMOUT1_EN, 0
-.set SD_TX_DMA__TERMOUT1_SEL, 0
-
-/* USBFS_USB */
-.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG
-.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG
-.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN
-.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR
-.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG
-.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN
-.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR
-.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG
-.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN
-.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR
-.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG
-.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN
-.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR
-.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG
-.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN
-.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR
-.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG
-.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN
-.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR
-.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG
-.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN
-.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR
-.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG
-.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN
-.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR
-.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN
-.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR
-.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR
-.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA
-.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB
-.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA
-.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB
-.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR
-.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA
-.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB
-.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA
-.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB
-.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR
-.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA
-.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB
-.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA
-.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB
-.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR
-.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA
-.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB
-.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA
-.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB
-.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR
-.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA
-.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB
-.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA
-.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB
-.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR
-.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA
-.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB
-.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA
-.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB
-.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR
-.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA
-.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB
-.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA
-.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB
-.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR
-.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA
-.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB
-.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA
-.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB
-.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE
-.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT
-.set USBFS_USB__CR0, CYREG_USB_CR0
-.set USBFS_USB__CR1, CYREG_USB_CR1
-.set USBFS_USB__CWA, CYREG_USB_CWA
-.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB
-.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES
-.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB
-.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG
-.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT
-.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR
-.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0
-.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1
-.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2
-.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3
-.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4
-.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5
-.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6
-.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7
-.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE
-.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE
-.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE
-.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5
-.set USBFS_USB__PM_ACT_MSK, 0x01
-.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5
-.set USBFS_USB__PM_STBY_MSK, 0x01
-.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0
-.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1
-.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0
-.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0
-.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1
-.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0
-.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0
-.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1
-.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0
-.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0
-.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1
-.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0
-.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0
-.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1
-.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0
-.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0
-.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1
-.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0
-.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0
-.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1
-.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0
-.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0
-.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1
-.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0
-.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN
-.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR
-.set USBFS_USB__SOF0, CYREG_USB_SOF0
-.set USBFS_USB__SOF1, CYREG_USB_SOF1
-.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0
-.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
-.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN
-
-/* SCSI_CLK */
-.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0
-.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1
-.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2
-.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07
-.set SCSI_CLK__INDEX, 0x01
-.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2
-.set SCSI_CLK__PM_ACT_MSK, 0x02
-.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2
-.set SCSI_CLK__PM_STBY_MSK, 0x02
-
-/* SCSI_Out */
-.set SCSI_Out__0__AG, CYREG_PRT15_AG
-.set SCSI_Out__0__AMUX, CYREG_PRT15_AMUX
-.set SCSI_Out__0__BIE, CYREG_PRT15_BIE
-.set SCSI_Out__0__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set SCSI_Out__0__BYP, CYREG_PRT15_BYP
-.set SCSI_Out__0__CTL, CYREG_PRT15_CTL
-.set SCSI_Out__0__DM0, CYREG_PRT15_DM0
-.set SCSI_Out__0__DM1, CYREG_PRT15_DM1
-.set SCSI_Out__0__DM2, CYREG_PRT15_DM2
-.set SCSI_Out__0__DR, CYREG_PRT15_DR
-.set SCSI_Out__0__INP_DIS, CYREG_PRT15_INP_DIS
-.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set SCSI_Out__0__LCD_EN, CYREG_PRT15_LCD_EN
-.set SCSI_Out__0__MASK, 0x20
-.set SCSI_Out__0__PC, CYREG_IO_PC_PRT15_PC5
-.set SCSI_Out__0__PORT, 15
-.set SCSI_Out__0__PRT, CYREG_PRT15_PRT
-.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set SCSI_Out__0__PS, CYREG_PRT15_PS
-.set SCSI_Out__0__SHIFT, 5
-.set SCSI_Out__0__SLW, CYREG_PRT15_SLW
-.set SCSI_Out__1__AG, CYREG_PRT15_AG
-.set SCSI_Out__1__AMUX, CYREG_PRT15_AMUX
-.set SCSI_Out__1__BIE, CYREG_PRT15_BIE
-.set SCSI_Out__1__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set SCSI_Out__1__BYP, CYREG_PRT15_BYP
-.set SCSI_Out__1__CTL, CYREG_PRT15_CTL
-.set SCSI_Out__1__DM0, CYREG_PRT15_DM0
-.set SCSI_Out__1__DM1, CYREG_PRT15_DM1
-.set SCSI_Out__1__DM2, CYREG_PRT15_DM2
-.set SCSI_Out__1__DR, CYREG_PRT15_DR
-.set SCSI_Out__1__INP_DIS, CYREG_PRT15_INP_DIS
-.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set SCSI_Out__1__LCD_EN, CYREG_PRT15_LCD_EN
-.set SCSI_Out__1__MASK, 0x10
-.set SCSI_Out__1__PC, CYREG_IO_PC_PRT15_PC4
-.set SCSI_Out__1__PORT, 15
-.set SCSI_Out__1__PRT, CYREG_PRT15_PRT
-.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set SCSI_Out__1__PS, CYREG_PRT15_PS
-.set SCSI_Out__1__SHIFT, 4
-.set SCSI_Out__1__SLW, CYREG_PRT15_SLW
-.set SCSI_Out__2__AG, CYREG_PRT6_AG
-.set SCSI_Out__2__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out__2__BIE, CYREG_PRT6_BIE
-.set SCSI_Out__2__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out__2__BYP, CYREG_PRT6_BYP
-.set SCSI_Out__2__CTL, CYREG_PRT6_CTL
-.set SCSI_Out__2__DM0, CYREG_PRT6_DM0
-.set SCSI_Out__2__DM1, CYREG_PRT6_DM1
-.set SCSI_Out__2__DM2, CYREG_PRT6_DM2
-.set SCSI_Out__2__DR, CYREG_PRT6_DR
-.set SCSI_Out__2__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out__2__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out__2__MASK, 0x02
-.set SCSI_Out__2__PC, CYREG_PRT6_PC1
-.set SCSI_Out__2__PORT, 6
-.set SCSI_Out__2__PRT, CYREG_PRT6_PRT
-.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out__2__PS, CYREG_PRT6_PS
-.set SCSI_Out__2__SHIFT, 1
-.set SCSI_Out__2__SLW, CYREG_PRT6_SLW
-.set SCSI_Out__3__AG, CYREG_PRT6_AG
-.set SCSI_Out__3__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out__3__BIE, CYREG_PRT6_BIE
-.set SCSI_Out__3__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out__3__BYP, CYREG_PRT6_BYP
-.set SCSI_Out__3__CTL, CYREG_PRT6_CTL
-.set SCSI_Out__3__DM0, CYREG_PRT6_DM0
-.set SCSI_Out__3__DM1, CYREG_PRT6_DM1
-.set SCSI_Out__3__DM2, CYREG_PRT6_DM2
-.set SCSI_Out__3__DR, CYREG_PRT6_DR
-.set SCSI_Out__3__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out__3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out__3__MASK, 0x01
-.set SCSI_Out__3__PC, CYREG_PRT6_PC0
-.set SCSI_Out__3__PORT, 6
-.set SCSI_Out__3__PRT, CYREG_PRT6_PRT
-.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out__3__PS, CYREG_PRT6_PS
-.set SCSI_Out__3__SHIFT, 0
-.set SCSI_Out__3__SLW, CYREG_PRT6_SLW
-.set SCSI_Out__4__AG, CYREG_PRT4_AG
-.set SCSI_Out__4__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out__4__BIE, CYREG_PRT4_BIE
-.set SCSI_Out__4__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out__4__BYP, CYREG_PRT4_BYP
-.set SCSI_Out__4__CTL, CYREG_PRT4_CTL
-.set SCSI_Out__4__DM0, CYREG_PRT4_DM0
-.set SCSI_Out__4__DM1, CYREG_PRT4_DM1
-.set SCSI_Out__4__DM2, CYREG_PRT4_DM2
-.set SCSI_Out__4__DR, CYREG_PRT4_DR
-.set SCSI_Out__4__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out__4__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out__4__MASK, 0x20
-.set SCSI_Out__4__PC, CYREG_PRT4_PC5
-.set SCSI_Out__4__PORT, 4
-.set SCSI_Out__4__PRT, CYREG_PRT4_PRT
-.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out__4__PS, CYREG_PRT4_PS
-.set SCSI_Out__4__SHIFT, 5
-.set SCSI_Out__4__SLW, CYREG_PRT4_SLW
-.set SCSI_Out__5__AG, CYREG_PRT4_AG
-.set SCSI_Out__5__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out__5__BIE, CYREG_PRT4_BIE
-.set SCSI_Out__5__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out__5__BYP, CYREG_PRT4_BYP
-.set SCSI_Out__5__CTL, CYREG_PRT4_CTL
-.set SCSI_Out__5__DM0, CYREG_PRT4_DM0
-.set SCSI_Out__5__DM1, CYREG_PRT4_DM1
-.set SCSI_Out__5__DM2, CYREG_PRT4_DM2
-.set SCSI_Out__5__DR, CYREG_PRT4_DR
-.set SCSI_Out__5__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out__5__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out__5__MASK, 0x10
-.set SCSI_Out__5__PC, CYREG_PRT4_PC4
-.set SCSI_Out__5__PORT, 4
-.set SCSI_Out__5__PRT, CYREG_PRT4_PRT
-.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out__5__PS, CYREG_PRT4_PS
-.set SCSI_Out__5__SHIFT, 4
-.set SCSI_Out__5__SLW, CYREG_PRT4_SLW
-.set SCSI_Out__6__AG, CYREG_PRT0_AG
-.set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__6__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__6__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__6__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__6__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__6__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__6__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__6__DR, CYREG_PRT0_DR
-.set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__6__MASK, 0x80
-.set SCSI_Out__6__PC, CYREG_PRT0_PC7
-.set SCSI_Out__6__PORT, 0
-.set SCSI_Out__6__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__6__PS, CYREG_PRT0_PS
-.set SCSI_Out__6__SHIFT, 7
-.set SCSI_Out__6__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__7__AG, CYREG_PRT0_AG
-.set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__7__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__7__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__7__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__7__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__7__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__7__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__7__DR, CYREG_PRT0_DR
-.set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__7__MASK, 0x40
-.set SCSI_Out__7__PC, CYREG_PRT0_PC6
-.set SCSI_Out__7__PORT, 0
-.set SCSI_Out__7__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__7__PS, CYREG_PRT0_PS
-.set SCSI_Out__7__SHIFT, 6
-.set SCSI_Out__7__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__8__AG, CYREG_PRT0_AG
-.set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__8__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__8__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__8__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__8__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__8__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__8__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__8__DR, CYREG_PRT0_DR
-.set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__8__MASK, 0x08
-.set SCSI_Out__8__PC, CYREG_PRT0_PC3
-.set SCSI_Out__8__PORT, 0
-.set SCSI_Out__8__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__8__PS, CYREG_PRT0_PS
-.set SCSI_Out__8__SHIFT, 3
-.set SCSI_Out__8__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__9__AG, CYREG_PRT0_AG
-.set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__9__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__9__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__9__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__9__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__9__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__9__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__9__DR, CYREG_PRT0_DR
-.set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__9__MASK, 0x04
-.set SCSI_Out__9__PC, CYREG_PRT0_PC2
-.set SCSI_Out__9__PORT, 0
-.set SCSI_Out__9__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__9__PS, CYREG_PRT0_PS
-.set SCSI_Out__9__SHIFT, 2
-.set SCSI_Out__9__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__ACK__AG, CYREG_PRT6_AG
-.set SCSI_Out__ACK__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out__ACK__BIE, CYREG_PRT6_BIE
-.set SCSI_Out__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out__ACK__BYP, CYREG_PRT6_BYP
-.set SCSI_Out__ACK__CTL, CYREG_PRT6_CTL
-.set SCSI_Out__ACK__DM0, CYREG_PRT6_DM0
-.set SCSI_Out__ACK__DM1, CYREG_PRT6_DM1
-.set SCSI_Out__ACK__DM2, CYREG_PRT6_DM2
-.set SCSI_Out__ACK__DR, CYREG_PRT6_DR
-.set SCSI_Out__ACK__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out__ACK__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out__ACK__MASK, 0x01
-.set SCSI_Out__ACK__PC, CYREG_PRT6_PC0
-.set SCSI_Out__ACK__PORT, 6
-.set SCSI_Out__ACK__PRT, CYREG_PRT6_PRT
-.set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out__ACK__PS, CYREG_PRT6_PS
-.set SCSI_Out__ACK__SHIFT, 0
-.set SCSI_Out__ACK__SLW, CYREG_PRT6_SLW
-.set SCSI_Out__ATN__AG, CYREG_PRT15_AG
-.set SCSI_Out__ATN__AMUX, CYREG_PRT15_AMUX
-.set SCSI_Out__ATN__BIE, CYREG_PRT15_BIE
-.set SCSI_Out__ATN__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set SCSI_Out__ATN__BYP, CYREG_PRT15_BYP
-.set SCSI_Out__ATN__CTL, CYREG_PRT15_CTL
-.set SCSI_Out__ATN__DM0, CYREG_PRT15_DM0
-.set SCSI_Out__ATN__DM1, CYREG_PRT15_DM1
-.set SCSI_Out__ATN__DM2, CYREG_PRT15_DM2
-.set SCSI_Out__ATN__DR, CYREG_PRT15_DR
-.set SCSI_Out__ATN__INP_DIS, CYREG_PRT15_INP_DIS
-.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set SCSI_Out__ATN__LCD_EN, CYREG_PRT15_LCD_EN
-.set SCSI_Out__ATN__MASK, 0x10
-.set SCSI_Out__ATN__PC, CYREG_IO_PC_PRT15_PC4
-.set SCSI_Out__ATN__PORT, 15
-.set SCSI_Out__ATN__PRT, CYREG_PRT15_PRT
-.set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set SCSI_Out__ATN__PS, CYREG_PRT15_PS
-.set SCSI_Out__ATN__SHIFT, 4
-.set SCSI_Out__ATN__SLW, CYREG_PRT15_SLW
-.set SCSI_Out__BSY__AG, CYREG_PRT6_AG
-.set SCSI_Out__BSY__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out__BSY__BIE, CYREG_PRT6_BIE
-.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out__BSY__BYP, CYREG_PRT6_BYP
-.set SCSI_Out__BSY__CTL, CYREG_PRT6_CTL
-.set SCSI_Out__BSY__DM0, CYREG_PRT6_DM0
-.set SCSI_Out__BSY__DM1, CYREG_PRT6_DM1
-.set SCSI_Out__BSY__DM2, CYREG_PRT6_DM2
-.set SCSI_Out__BSY__DR, CYREG_PRT6_DR
-.set SCSI_Out__BSY__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out__BSY__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out__BSY__MASK, 0x02
-.set SCSI_Out__BSY__PC, CYREG_PRT6_PC1
-.set SCSI_Out__BSY__PORT, 6
-.set SCSI_Out__BSY__PRT, CYREG_PRT6_PRT
-.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out__BSY__PS, CYREG_PRT6_PS
-.set SCSI_Out__BSY__SHIFT, 1
-.set SCSI_Out__BSY__SLW, CYREG_PRT6_SLW
-.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG
-.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR
-.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__CD_raw__MASK, 0x40
-.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC6
-.set SCSI_Out__CD_raw__PORT, 0
-.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS
-.set SCSI_Out__CD_raw__SHIFT, 6
-.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__DBP_raw__AG, CYREG_PRT15_AG
-.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT15_AMUX
-.set SCSI_Out__DBP_raw__BIE, CYREG_PRT15_BIE
-.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set SCSI_Out__DBP_raw__BYP, CYREG_PRT15_BYP
-.set SCSI_Out__DBP_raw__CTL, CYREG_PRT15_CTL
-.set SCSI_Out__DBP_raw__DM0, CYREG_PRT15_DM0
-.set SCSI_Out__DBP_raw__DM1, CYREG_PRT15_DM1
-.set SCSI_Out__DBP_raw__DM2, CYREG_PRT15_DM2
-.set SCSI_Out__DBP_raw__DR, CYREG_PRT15_DR
-.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT15_INP_DIS
-.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT15_LCD_EN
-.set SCSI_Out__DBP_raw__MASK, 0x20
-.set SCSI_Out__DBP_raw__PC, CYREG_IO_PC_PRT15_PC5
-.set SCSI_Out__DBP_raw__PORT, 15
-.set SCSI_Out__DBP_raw__PRT, CYREG_PRT15_PRT
-.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set SCSI_Out__DBP_raw__PS, CYREG_PRT15_PS
-.set SCSI_Out__DBP_raw__SHIFT, 5
-.set SCSI_Out__DBP_raw__SLW, CYREG_PRT15_SLW
-.set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG
-.set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR
-.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__IO_raw__MASK, 0x04
-.set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC2
-.set SCSI_Out__IO_raw__PORT, 0
-.set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS
-.set SCSI_Out__IO_raw__SHIFT, 2
-.set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__MSG_raw__AG, CYREG_PRT4_AG
-.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out__MSG_raw__BIE, CYREG_PRT4_BIE
-.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out__MSG_raw__BYP, CYREG_PRT4_BYP
-.set SCSI_Out__MSG_raw__CTL, CYREG_PRT4_CTL
-.set SCSI_Out__MSG_raw__DM0, CYREG_PRT4_DM0
-.set SCSI_Out__MSG_raw__DM1, CYREG_PRT4_DM1
-.set SCSI_Out__MSG_raw__DM2, CYREG_PRT4_DM2
-.set SCSI_Out__MSG_raw__DR, CYREG_PRT4_DR
-.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out__MSG_raw__MASK, 0x10
-.set SCSI_Out__MSG_raw__PC, CYREG_PRT4_PC4
-.set SCSI_Out__MSG_raw__PORT, 4
-.set SCSI_Out__MSG_raw__PRT, CYREG_PRT4_PRT
-.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out__MSG_raw__PS, CYREG_PRT4_PS
-.set SCSI_Out__MSG_raw__SHIFT, 4
-.set SCSI_Out__MSG_raw__SLW, CYREG_PRT4_SLW
-.set SCSI_Out__REQ__AG, CYREG_PRT0_AG
-.set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__REQ__DR, CYREG_PRT0_DR
-.set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__REQ__MASK, 0x08
-.set SCSI_Out__REQ__PC, CYREG_PRT0_PC3
-.set SCSI_Out__REQ__PORT, 0
-.set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__REQ__PS, CYREG_PRT0_PS
-.set SCSI_Out__REQ__SHIFT, 3
-.set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW
-.set SCSI_Out__RST__AG, CYREG_PRT4_AG
-.set SCSI_Out__RST__AMUX, CYREG_PRT4_AMUX
-.set SCSI_Out__RST__BIE, CYREG_PRT4_BIE
-.set SCSI_Out__RST__BIT_MASK, CYREG_PRT4_BIT_MASK
-.set SCSI_Out__RST__BYP, CYREG_PRT4_BYP
-.set SCSI_Out__RST__CTL, CYREG_PRT4_CTL
-.set SCSI_Out__RST__DM0, CYREG_PRT4_DM0
-.set SCSI_Out__RST__DM1, CYREG_PRT4_DM1
-.set SCSI_Out__RST__DM2, CYREG_PRT4_DM2
-.set SCSI_Out__RST__DR, CYREG_PRT4_DR
-.set SCSI_Out__RST__INP_DIS, CYREG_PRT4_INP_DIS
-.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
-.set SCSI_Out__RST__LCD_EN, CYREG_PRT4_LCD_EN
-.set SCSI_Out__RST__MASK, 0x20
-.set SCSI_Out__RST__PC, CYREG_PRT4_PC5
-.set SCSI_Out__RST__PORT, 4
-.set SCSI_Out__RST__PRT, CYREG_PRT4_PRT
-.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
-.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
-.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
-.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
-.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
-.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
-.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
-.set SCSI_Out__RST__PS, CYREG_PRT4_PS
-.set SCSI_Out__RST__SHIFT, 5
-.set SCSI_Out__RST__SLW, CYREG_PRT4_SLW
-.set SCSI_Out__SEL__AG, CYREG_PRT0_AG
-.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX
-.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE
-.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP
-.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL
-.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0
-.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1
-.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2
-.set SCSI_Out__SEL__DR, CYREG_PRT0_DR
-.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS
-.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN
-.set SCSI_Out__SEL__MASK, 0x80
-.set SCSI_Out__SEL__PC, CYREG_PRT0_PC7
-.set SCSI_Out__SEL__PORT, 0
-.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT
-.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set SCSI_Out__SEL__PS, CYREG_PRT0_PS
-.set SCSI_Out__SEL__SHIFT, 7
-.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW
+/* EXTLED */
+.set EXTLED__0__MASK, 0x01
+.set EXTLED__0__PC, CYREG_PRT0_PC0
+.set EXTLED__0__PORT, 0
+.set EXTLED__0__SHIFT, 0
+.set EXTLED__AG, CYREG_PRT0_AG
+.set EXTLED__AMUX, CYREG_PRT0_AMUX
+.set EXTLED__BIE, CYREG_PRT0_BIE
+.set EXTLED__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set EXTLED__BYP, CYREG_PRT0_BYP
+.set EXTLED__CTL, CYREG_PRT0_CTL
+.set EXTLED__DM0, CYREG_PRT0_DM0
+.set EXTLED__DM1, CYREG_PRT0_DM1
+.set EXTLED__DM2, CYREG_PRT0_DM2
+.set EXTLED__DR, CYREG_PRT0_DR
+.set EXTLED__INP_DIS, CYREG_PRT0_INP_DIS
+.set EXTLED__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set EXTLED__LCD_EN, CYREG_PRT0_LCD_EN
+.set EXTLED__MASK, 0x01
+.set EXTLED__PORT, 0
+.set EXTLED__PRT, CYREG_PRT0_PRT
+.set EXTLED__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set EXTLED__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set EXTLED__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set EXTLED__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set EXTLED__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set EXTLED__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set EXTLED__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set EXTLED__PS, CYREG_PRT0_PS
+.set EXTLED__SHIFT, 0
+.set EXTLED__SLW, CYREG_PRT0_SLW
-/* USBFS_Dm */
-.set USBFS_Dm__0__MASK, 0x80
-.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1
-.set USBFS_Dm__0__PORT, 15
-.set USBFS_Dm__0__SHIFT, 7
-.set USBFS_Dm__AG, CYREG_PRT15_AG
-.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX
-.set USBFS_Dm__BIE, CYREG_PRT15_BIE
-.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set USBFS_Dm__BYP, CYREG_PRT15_BYP
-.set USBFS_Dm__CTL, CYREG_PRT15_CTL
-.set USBFS_Dm__DM0, CYREG_PRT15_DM0
-.set USBFS_Dm__DM1, CYREG_PRT15_DM1
-.set USBFS_Dm__DM2, CYREG_PRT15_DM2
-.set USBFS_Dm__DR, CYREG_PRT15_DR
-.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS
-.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN
-.set USBFS_Dm__MASK, 0x80
-.set USBFS_Dm__PORT, 15
-.set USBFS_Dm__PRT, CYREG_PRT15_PRT
-.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set USBFS_Dm__PS, CYREG_PRT15_PS
-.set USBFS_Dm__SHIFT, 7
-.set USBFS_Dm__SLW, CYREG_PRT15_SLW
+/* SDCard_BSPIM */
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB10_11_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB10_11_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB10_11_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB10_11_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB10_11_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB10_11_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB10_11_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB10_11_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB10_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB10_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB10_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB10_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB10_MSK
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB10_11_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB10_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB10_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB10_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB10_ST
+.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
+.set SDCard_BSPIM_RxStsReg__4__POS, 4
+.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
+.set SDCard_BSPIM_RxStsReg__5__POS, 5
+.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
+.set SDCard_BSPIM_RxStsReg__6__POS, 6
+.set SDCard_BSPIM_RxStsReg__MASK, 0x70
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB11_MSK
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB11_ST
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB08_09_A0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB08_09_A1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB08_09_D0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB08_09_D1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB08_09_F0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB08_09_F1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB08_A0_A1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB08_A0
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB08_A1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB08_D0_D1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB08_D0
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB08_D1
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB08_F0_F1
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB08_F0
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB08_F1
+.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
+.set SDCard_BSPIM_TxStsReg__0__POS, 0
+.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
+.set SDCard_BSPIM_TxStsReg__1__POS, 1
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST
+.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
+.set SDCard_BSPIM_TxStsReg__2__POS, 2
+.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
+.set SDCard_BSPIM_TxStsReg__3__POS, 3
+.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
+.set SDCard_BSPIM_TxStsReg__4__POS, 4
+.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB08_MSK
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB08_ST
-/* USBFS_Dp */
-.set USBFS_Dp__0__MASK, 0x40
-.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0
-.set USBFS_Dp__0__PORT, 15
-.set USBFS_Dp__0__SHIFT, 6
-.set USBFS_Dp__AG, CYREG_PRT15_AG
-.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX
-.set USBFS_Dp__BIE, CYREG_PRT15_BIE
-.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set USBFS_Dp__BYP, CYREG_PRT15_BYP
-.set USBFS_Dp__CTL, CYREG_PRT15_CTL
-.set USBFS_Dp__DM0, CYREG_PRT15_DM0
-.set USBFS_Dp__DM1, CYREG_PRT15_DM1
-.set USBFS_Dp__DM2, CYREG_PRT15_DM2
-.set USBFS_Dp__DR, CYREG_PRT15_DR
-.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS
-.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT
-.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN
-.set USBFS_Dp__MASK, 0x40
-.set USBFS_Dp__PORT, 15
-.set USBFS_Dp__PRT, CYREG_PRT15_PRT
-.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set USBFS_Dp__PS, CYREG_PRT15_PS
-.set USBFS_Dp__SHIFT, 6
-.set USBFS_Dp__SLW, CYREG_PRT15_SLW
-.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15
+/* SD_SCK */
+.set SD_SCK__0__MASK, 0x04
+.set SD_SCK__0__PC, CYREG_PRT3_PC2
+.set SD_SCK__0__PORT, 3
+.set SD_SCK__0__SHIFT, 2
+.set SD_SCK__AG, CYREG_PRT3_AG
+.set SD_SCK__AMUX, CYREG_PRT3_AMUX
+.set SD_SCK__BIE, CYREG_PRT3_BIE
+.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_SCK__BYP, CYREG_PRT3_BYP
+.set SD_SCK__CTL, CYREG_PRT3_CTL
+.set SD_SCK__DM0, CYREG_PRT3_DM0
+.set SD_SCK__DM1, CYREG_PRT3_DM1
+.set SD_SCK__DM2, CYREG_PRT3_DM2
+.set SD_SCK__DR, CYREG_PRT3_DR
+.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_SCK__MASK, 0x04
+.set SD_SCK__PORT, 3
+.set SD_SCK__PRT, CYREG_PRT3_PRT
+.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_SCK__PS, CYREG_PRT3_PS
+.set SD_SCK__SHIFT, 2
+.set SD_SCK__SLW, CYREG_PRT3_SLW
/* SCSI_In */
.set SCSI_In__0__AG, CYREG_PRT2_AG
.set SCSI_In__REQ__SHIFT, 5
.set SCSI_In__REQ__SLW, CYREG_PRT0_SLW
-/* SD_MISO */
-.set SD_MISO__0__MASK, 0x02
-.set SD_MISO__0__PC, CYREG_PRT3_PC1
-.set SD_MISO__0__PORT, 3
-.set SD_MISO__0__SHIFT, 1
-.set SD_MISO__AG, CYREG_PRT3_AG
-.set SD_MISO__AMUX, CYREG_PRT3_AMUX
-.set SD_MISO__BIE, CYREG_PRT3_BIE
-.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_MISO__BYP, CYREG_PRT3_BYP
-.set SD_MISO__CTL, CYREG_PRT3_CTL
-.set SD_MISO__DM0, CYREG_PRT3_DM0
-.set SD_MISO__DM1, CYREG_PRT3_DM1
-.set SD_MISO__DM2, CYREG_PRT3_DM2
-.set SD_MISO__DR, CYREG_PRT3_DR
-.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_MISO__MASK, 0x02
-.set SD_MISO__PORT, 3
-.set SD_MISO__PRT, CYREG_PRT3_PRT
-.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_MISO__PS, CYREG_PRT3_PS
-.set SD_MISO__SHIFT, 1
-.set SD_MISO__SLW, CYREG_PRT3_SLW
+/* SCSI_In_DBx */
+.set SCSI_In_DBx__0__AG, CYREG_PRT5_AG
+.set SCSI_In_DBx__0__AMUX, CYREG_PRT5_AMUX
+.set SCSI_In_DBx__0__BIE, CYREG_PRT5_BIE
+.set SCSI_In_DBx__0__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_In_DBx__0__BYP, CYREG_PRT5_BYP
+.set SCSI_In_DBx__0__CTL, CYREG_PRT5_CTL
+.set SCSI_In_DBx__0__DM0, CYREG_PRT5_DM0
+.set SCSI_In_DBx__0__DM1, CYREG_PRT5_DM1
+.set SCSI_In_DBx__0__DM2, CYREG_PRT5_DM2
+.set SCSI_In_DBx__0__DR, CYREG_PRT5_DR
+.set SCSI_In_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_In_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_In_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_In_DBx__0__MASK, 0x08
+.set SCSI_In_DBx__0__PC, CYREG_PRT5_PC3
+.set SCSI_In_DBx__0__PORT, 5
+.set SCSI_In_DBx__0__PRT, CYREG_PRT5_PRT
+.set SCSI_In_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_In_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_In_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_In_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_In_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_In_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_In_DBx__0__PS, CYREG_PRT5_PS
+.set SCSI_In_DBx__0__SHIFT, 3
+.set SCSI_In_DBx__0__SLW, CYREG_PRT5_SLW
+.set SCSI_In_DBx__1__AG, CYREG_PRT5_AG
+.set SCSI_In_DBx__1__AMUX, CYREG_PRT5_AMUX
+.set SCSI_In_DBx__1__BIE, CYREG_PRT5_BIE
+.set SCSI_In_DBx__1__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_In_DBx__1__BYP, CYREG_PRT5_BYP
+.set SCSI_In_DBx__1__CTL, CYREG_PRT5_CTL
+.set SCSI_In_DBx__1__DM0, CYREG_PRT5_DM0
+.set SCSI_In_DBx__1__DM1, CYREG_PRT5_DM1
+.set SCSI_In_DBx__1__DM2, CYREG_PRT5_DM2
+.set SCSI_In_DBx__1__DR, CYREG_PRT5_DR
+.set SCSI_In_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_In_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_In_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_In_DBx__1__MASK, 0x04
+.set SCSI_In_DBx__1__PC, CYREG_PRT5_PC2
+.set SCSI_In_DBx__1__PORT, 5
+.set SCSI_In_DBx__1__PRT, CYREG_PRT5_PRT
+.set SCSI_In_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_In_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_In_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_In_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_In_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_In_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_In_DBx__1__PS, CYREG_PRT5_PS
+.set SCSI_In_DBx__1__SHIFT, 2
+.set SCSI_In_DBx__1__SLW, CYREG_PRT5_SLW
+.set SCSI_In_DBx__2__AG, CYREG_PRT6_AG
+.set SCSI_In_DBx__2__AMUX, CYREG_PRT6_AMUX
+.set SCSI_In_DBx__2__BIE, CYREG_PRT6_BIE
+.set SCSI_In_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_In_DBx__2__BYP, CYREG_PRT6_BYP
+.set SCSI_In_DBx__2__CTL, CYREG_PRT6_CTL
+.set SCSI_In_DBx__2__DM0, CYREG_PRT6_DM0
+.set SCSI_In_DBx__2__DM1, CYREG_PRT6_DM1
+.set SCSI_In_DBx__2__DM2, CYREG_PRT6_DM2
+.set SCSI_In_DBx__2__DR, CYREG_PRT6_DR
+.set SCSI_In_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_In_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_In_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_In_DBx__2__MASK, 0x80
+.set SCSI_In_DBx__2__PC, CYREG_PRT6_PC7
+.set SCSI_In_DBx__2__PORT, 6
+.set SCSI_In_DBx__2__PRT, CYREG_PRT6_PRT
+.set SCSI_In_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_In_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_In_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_In_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_In_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_In_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_In_DBx__2__PS, CYREG_PRT6_PS
+.set SCSI_In_DBx__2__SHIFT, 7
+.set SCSI_In_DBx__2__SLW, CYREG_PRT6_SLW
+.set SCSI_In_DBx__3__AG, CYREG_PRT6_AG
+.set SCSI_In_DBx__3__AMUX, CYREG_PRT6_AMUX
+.set SCSI_In_DBx__3__BIE, CYREG_PRT6_BIE
+.set SCSI_In_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_In_DBx__3__BYP, CYREG_PRT6_BYP
+.set SCSI_In_DBx__3__CTL, CYREG_PRT6_CTL
+.set SCSI_In_DBx__3__DM0, CYREG_PRT6_DM0
+.set SCSI_In_DBx__3__DM1, CYREG_PRT6_DM1
+.set SCSI_In_DBx__3__DM2, CYREG_PRT6_DM2
+.set SCSI_In_DBx__3__DR, CYREG_PRT6_DR
+.set SCSI_In_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_In_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_In_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_In_DBx__3__MASK, 0x40
+.set SCSI_In_DBx__3__PC, CYREG_PRT6_PC6
+.set SCSI_In_DBx__3__PORT, 6
+.set SCSI_In_DBx__3__PRT, CYREG_PRT6_PRT
+.set SCSI_In_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_In_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_In_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_In_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_In_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_In_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_In_DBx__3__PS, CYREG_PRT6_PS
+.set SCSI_In_DBx__3__SHIFT, 6
+.set SCSI_In_DBx__3__SLW, CYREG_PRT6_SLW
+.set SCSI_In_DBx__4__AG, CYREG_PRT12_AG
+.set SCSI_In_DBx__4__BIE, CYREG_PRT12_BIE
+.set SCSI_In_DBx__4__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set SCSI_In_DBx__4__BYP, CYREG_PRT12_BYP
+.set SCSI_In_DBx__4__DM0, CYREG_PRT12_DM0
+.set SCSI_In_DBx__4__DM1, CYREG_PRT12_DM1
+.set SCSI_In_DBx__4__DM2, CYREG_PRT12_DM2
+.set SCSI_In_DBx__4__DR, CYREG_PRT12_DR
+.set SCSI_In_DBx__4__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_In_DBx__4__MASK, 0x20
+.set SCSI_In_DBx__4__PC, CYREG_PRT12_PC5
+.set SCSI_In_DBx__4__PORT, 12
+.set SCSI_In_DBx__4__PRT, CYREG_PRT12_PRT
+.set SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set SCSI_In_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set SCSI_In_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set SCSI_In_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set SCSI_In_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set SCSI_In_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set SCSI_In_DBx__4__PS, CYREG_PRT12_PS
+.set SCSI_In_DBx__4__SHIFT, 5
+.set SCSI_In_DBx__4__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set SCSI_In_DBx__4__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set SCSI_In_DBx__4__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set SCSI_In_DBx__4__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set SCSI_In_DBx__4__SLW, CYREG_PRT12_SLW
+.set SCSI_In_DBx__5__AG, CYREG_PRT12_AG
+.set SCSI_In_DBx__5__BIE, CYREG_PRT12_BIE
+.set SCSI_In_DBx__5__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set SCSI_In_DBx__5__BYP, CYREG_PRT12_BYP
+.set SCSI_In_DBx__5__DM0, CYREG_PRT12_DM0
+.set SCSI_In_DBx__5__DM1, CYREG_PRT12_DM1
+.set SCSI_In_DBx__5__DM2, CYREG_PRT12_DM2
+.set SCSI_In_DBx__5__DR, CYREG_PRT12_DR
+.set SCSI_In_DBx__5__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_In_DBx__5__MASK, 0x10
+.set SCSI_In_DBx__5__PC, CYREG_PRT12_PC4
+.set SCSI_In_DBx__5__PORT, 12
+.set SCSI_In_DBx__5__PRT, CYREG_PRT12_PRT
+.set SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set SCSI_In_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set SCSI_In_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set SCSI_In_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set SCSI_In_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set SCSI_In_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set SCSI_In_DBx__5__PS, CYREG_PRT12_PS
+.set SCSI_In_DBx__5__SHIFT, 4
+.set SCSI_In_DBx__5__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set SCSI_In_DBx__5__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set SCSI_In_DBx__5__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set SCSI_In_DBx__5__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set SCSI_In_DBx__5__SLW, CYREG_PRT12_SLW
+.set SCSI_In_DBx__6__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__6__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__6__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__6__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__6__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__6__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__6__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__6__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__6__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__6__MASK, 0x20
+.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC5
+.set SCSI_In_DBx__6__PORT, 2
+.set SCSI_In_DBx__6__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__6__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__6__SHIFT, 5
+.set SCSI_In_DBx__6__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__7__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__7__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__7__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__7__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__7__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__7__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__7__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__7__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__7__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__7__MASK, 0x10
+.set SCSI_In_DBx__7__PC, CYREG_PRT2_PC4
+.set SCSI_In_DBx__7__PORT, 2
+.set SCSI_In_DBx__7__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__7__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__7__SHIFT, 4
+.set SCSI_In_DBx__7__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__DB0__AG, CYREG_PRT5_AG
+.set SCSI_In_DBx__DB0__AMUX, CYREG_PRT5_AMUX
+.set SCSI_In_DBx__DB0__BIE, CYREG_PRT5_BIE
+.set SCSI_In_DBx__DB0__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_In_DBx__DB0__BYP, CYREG_PRT5_BYP
+.set SCSI_In_DBx__DB0__CTL, CYREG_PRT5_CTL
+.set SCSI_In_DBx__DB0__DM0, CYREG_PRT5_DM0
+.set SCSI_In_DBx__DB0__DM1, CYREG_PRT5_DM1
+.set SCSI_In_DBx__DB0__DM2, CYREG_PRT5_DM2
+.set SCSI_In_DBx__DB0__DR, CYREG_PRT5_DR
+.set SCSI_In_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_In_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_In_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_In_DBx__DB0__MASK, 0x08
+.set SCSI_In_DBx__DB0__PC, CYREG_PRT5_PC3
+.set SCSI_In_DBx__DB0__PORT, 5
+.set SCSI_In_DBx__DB0__PRT, CYREG_PRT5_PRT
+.set SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_In_DBx__DB0__PS, CYREG_PRT5_PS
+.set SCSI_In_DBx__DB0__SHIFT, 3
+.set SCSI_In_DBx__DB0__SLW, CYREG_PRT5_SLW
+.set SCSI_In_DBx__DB1__AG, CYREG_PRT5_AG
+.set SCSI_In_DBx__DB1__AMUX, CYREG_PRT5_AMUX
+.set SCSI_In_DBx__DB1__BIE, CYREG_PRT5_BIE
+.set SCSI_In_DBx__DB1__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_In_DBx__DB1__BYP, CYREG_PRT5_BYP
+.set SCSI_In_DBx__DB1__CTL, CYREG_PRT5_CTL
+.set SCSI_In_DBx__DB1__DM0, CYREG_PRT5_DM0
+.set SCSI_In_DBx__DB1__DM1, CYREG_PRT5_DM1
+.set SCSI_In_DBx__DB1__DM2, CYREG_PRT5_DM2
+.set SCSI_In_DBx__DB1__DR, CYREG_PRT5_DR
+.set SCSI_In_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_In_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_In_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_In_DBx__DB1__MASK, 0x04
+.set SCSI_In_DBx__DB1__PC, CYREG_PRT5_PC2
+.set SCSI_In_DBx__DB1__PORT, 5
+.set SCSI_In_DBx__DB1__PRT, CYREG_PRT5_PRT
+.set SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_In_DBx__DB1__PS, CYREG_PRT5_PS
+.set SCSI_In_DBx__DB1__SHIFT, 2
+.set SCSI_In_DBx__DB1__SLW, CYREG_PRT5_SLW
+.set SCSI_In_DBx__DB2__AG, CYREG_PRT6_AG
+.set SCSI_In_DBx__DB2__AMUX, CYREG_PRT6_AMUX
+.set SCSI_In_DBx__DB2__BIE, CYREG_PRT6_BIE
+.set SCSI_In_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_In_DBx__DB2__BYP, CYREG_PRT6_BYP
+.set SCSI_In_DBx__DB2__CTL, CYREG_PRT6_CTL
+.set SCSI_In_DBx__DB2__DM0, CYREG_PRT6_DM0
+.set SCSI_In_DBx__DB2__DM1, CYREG_PRT6_DM1
+.set SCSI_In_DBx__DB2__DM2, CYREG_PRT6_DM2
+.set SCSI_In_DBx__DB2__DR, CYREG_PRT6_DR
+.set SCSI_In_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_In_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_In_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_In_DBx__DB2__MASK, 0x80
+.set SCSI_In_DBx__DB2__PC, CYREG_PRT6_PC7
+.set SCSI_In_DBx__DB2__PORT, 6
+.set SCSI_In_DBx__DB2__PRT, CYREG_PRT6_PRT
+.set SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_In_DBx__DB2__PS, CYREG_PRT6_PS
+.set SCSI_In_DBx__DB2__SHIFT, 7
+.set SCSI_In_DBx__DB2__SLW, CYREG_PRT6_SLW
+.set SCSI_In_DBx__DB3__AG, CYREG_PRT6_AG
+.set SCSI_In_DBx__DB3__AMUX, CYREG_PRT6_AMUX
+.set SCSI_In_DBx__DB3__BIE, CYREG_PRT6_BIE
+.set SCSI_In_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_In_DBx__DB3__BYP, CYREG_PRT6_BYP
+.set SCSI_In_DBx__DB3__CTL, CYREG_PRT6_CTL
+.set SCSI_In_DBx__DB3__DM0, CYREG_PRT6_DM0
+.set SCSI_In_DBx__DB3__DM1, CYREG_PRT6_DM1
+.set SCSI_In_DBx__DB3__DM2, CYREG_PRT6_DM2
+.set SCSI_In_DBx__DB3__DR, CYREG_PRT6_DR
+.set SCSI_In_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_In_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_In_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_In_DBx__DB3__MASK, 0x40
+.set SCSI_In_DBx__DB3__PC, CYREG_PRT6_PC6
+.set SCSI_In_DBx__DB3__PORT, 6
+.set SCSI_In_DBx__DB3__PRT, CYREG_PRT6_PRT
+.set SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_In_DBx__DB3__PS, CYREG_PRT6_PS
+.set SCSI_In_DBx__DB3__SHIFT, 6
+.set SCSI_In_DBx__DB3__SLW, CYREG_PRT6_SLW
+.set SCSI_In_DBx__DB4__AG, CYREG_PRT12_AG
+.set SCSI_In_DBx__DB4__BIE, CYREG_PRT12_BIE
+.set SCSI_In_DBx__DB4__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set SCSI_In_DBx__DB4__BYP, CYREG_PRT12_BYP
+.set SCSI_In_DBx__DB4__DM0, CYREG_PRT12_DM0
+.set SCSI_In_DBx__DB4__DM1, CYREG_PRT12_DM1
+.set SCSI_In_DBx__DB4__DM2, CYREG_PRT12_DM2
+.set SCSI_In_DBx__DB4__DR, CYREG_PRT12_DR
+.set SCSI_In_DBx__DB4__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_In_DBx__DB4__MASK, 0x20
+.set SCSI_In_DBx__DB4__PC, CYREG_PRT12_PC5
+.set SCSI_In_DBx__DB4__PORT, 12
+.set SCSI_In_DBx__DB4__PRT, CYREG_PRT12_PRT
+.set SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set SCSI_In_DBx__DB4__PS, CYREG_PRT12_PS
+.set SCSI_In_DBx__DB4__SHIFT, 5
+.set SCSI_In_DBx__DB4__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set SCSI_In_DBx__DB4__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set SCSI_In_DBx__DB4__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set SCSI_In_DBx__DB4__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set SCSI_In_DBx__DB4__SLW, CYREG_PRT12_SLW
+.set SCSI_In_DBx__DB5__AG, CYREG_PRT12_AG
+.set SCSI_In_DBx__DB5__BIE, CYREG_PRT12_BIE
+.set SCSI_In_DBx__DB5__BIT_MASK, CYREG_PRT12_BIT_MASK
+.set SCSI_In_DBx__DB5__BYP, CYREG_PRT12_BYP
+.set SCSI_In_DBx__DB5__DM0, CYREG_PRT12_DM0
+.set SCSI_In_DBx__DB5__DM1, CYREG_PRT12_DM1
+.set SCSI_In_DBx__DB5__DM2, CYREG_PRT12_DM2
+.set SCSI_In_DBx__DB5__DR, CYREG_PRT12_DR
+.set SCSI_In_DBx__DB5__INP_DIS, CYREG_PRT12_INP_DIS
+.set SCSI_In_DBx__DB5__MASK, 0x10
+.set SCSI_In_DBx__DB5__PC, CYREG_PRT12_PC4
+.set SCSI_In_DBx__DB5__PORT, 12
+.set SCSI_In_DBx__DB5__PRT, CYREG_PRT12_PRT
+.set SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
+.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
+.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
+.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
+.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
+.set SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
+.set SCSI_In_DBx__DB5__PS, CYREG_PRT12_PS
+.set SCSI_In_DBx__DB5__SHIFT, 4
+.set SCSI_In_DBx__DB5__SIO_CFG, CYREG_PRT12_SIO_CFG
+.set SCSI_In_DBx__DB5__SIO_DIFF, CYREG_PRT12_SIO_DIFF
+.set SCSI_In_DBx__DB5__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
+.set SCSI_In_DBx__DB5__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
+.set SCSI_In_DBx__DB5__SLW, CYREG_PRT12_SLW
+.set SCSI_In_DBx__DB6__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__DB6__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__DB6__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__DB6__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__DB6__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__DB6__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__DB6__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__DB6__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__DB6__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__DB6__MASK, 0x20
+.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC5
+.set SCSI_In_DBx__DB6__PORT, 2
+.set SCSI_In_DBx__DB6__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__DB6__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__DB6__SHIFT, 5
+.set SCSI_In_DBx__DB6__SLW, CYREG_PRT2_SLW
+.set SCSI_In_DBx__DB7__AG, CYREG_PRT2_AG
+.set SCSI_In_DBx__DB7__AMUX, CYREG_PRT2_AMUX
+.set SCSI_In_DBx__DB7__BIE, CYREG_PRT2_BIE
+.set SCSI_In_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_In_DBx__DB7__BYP, CYREG_PRT2_BYP
+.set SCSI_In_DBx__DB7__CTL, CYREG_PRT2_CTL
+.set SCSI_In_DBx__DB7__DM0, CYREG_PRT2_DM0
+.set SCSI_In_DBx__DB7__DM1, CYREG_PRT2_DM1
+.set SCSI_In_DBx__DB7__DM2, CYREG_PRT2_DM2
+.set SCSI_In_DBx__DB7__DR, CYREG_PRT2_DR
+.set SCSI_In_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_In_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_In_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_In_DBx__DB7__MASK, 0x10
+.set SCSI_In_DBx__DB7__PC, CYREG_PRT2_PC4
+.set SCSI_In_DBx__DB7__PORT, 2
+.set SCSI_In_DBx__DB7__PRT, CYREG_PRT2_PRT
+.set SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_In_DBx__DB7__PS, CYREG_PRT2_PS
+.set SCSI_In_DBx__DB7__SHIFT, 4
+.set SCSI_In_DBx__DB7__SLW, CYREG_PRT2_SLW
+
+/* SD_MISO */
+.set SD_MISO__0__MASK, 0x02
+.set SD_MISO__0__PC, CYREG_PRT3_PC1
+.set SD_MISO__0__PORT, 3
+.set SD_MISO__0__SHIFT, 1
+.set SD_MISO__AG, CYREG_PRT3_AG
+.set SD_MISO__AMUX, CYREG_PRT3_AMUX
+.set SD_MISO__BIE, CYREG_PRT3_BIE
+.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_MISO__BYP, CYREG_PRT3_BYP
+.set SD_MISO__CTL, CYREG_PRT3_CTL
+.set SD_MISO__DM0, CYREG_PRT3_DM0
+.set SD_MISO__DM1, CYREG_PRT3_DM1
+.set SD_MISO__DM2, CYREG_PRT3_DM2
+.set SD_MISO__DR, CYREG_PRT3_DR
+.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_MISO__MASK, 0x02
+.set SD_MISO__PORT, 3
+.set SD_MISO__PRT, CYREG_PRT3_PRT
+.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_MISO__PS, CYREG_PRT3_PS
+.set SD_MISO__SHIFT, 1
+.set SD_MISO__SLW, CYREG_PRT3_SLW
+
+/* SD_MOSI */
+.set SD_MOSI__0__MASK, 0x08
+.set SD_MOSI__0__PC, CYREG_PRT3_PC3
+.set SD_MOSI__0__PORT, 3
+.set SD_MOSI__0__SHIFT, 3
+.set SD_MOSI__AG, CYREG_PRT3_AG
+.set SD_MOSI__AMUX, CYREG_PRT3_AMUX
+.set SD_MOSI__BIE, CYREG_PRT3_BIE
+.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_MOSI__BYP, CYREG_PRT3_BYP
+.set SD_MOSI__CTL, CYREG_PRT3_CTL
+.set SD_MOSI__DM0, CYREG_PRT3_DM0
+.set SD_MOSI__DM1, CYREG_PRT3_DM1
+.set SD_MOSI__DM2, CYREG_PRT3_DM2
+.set SD_MOSI__DR, CYREG_PRT3_DR
+.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_MOSI__MASK, 0x08
+.set SD_MOSI__PORT, 3
+.set SD_MOSI__PRT, CYREG_PRT3_PRT
+.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_MOSI__PS, CYREG_PRT3_PS
+.set SD_MOSI__SHIFT, 3
+.set SD_MOSI__SLW, CYREG_PRT3_SLW
+
+/* SCSI_CLK */
+.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0
+.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1
+.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2
+.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07
+.set SCSI_CLK__INDEX, 0x01
+.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2
+.set SCSI_CLK__PM_ACT_MSK, 0x02
+.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2
+.set SCSI_CLK__PM_STBY_MSK, 0x02
+
+/* SCSI_Out */
+.set SCSI_Out__0__AG, CYREG_PRT15_AG
+.set SCSI_Out__0__AMUX, CYREG_PRT15_AMUX
+.set SCSI_Out__0__BIE, CYREG_PRT15_BIE
+.set SCSI_Out__0__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set SCSI_Out__0__BYP, CYREG_PRT15_BYP
+.set SCSI_Out__0__CTL, CYREG_PRT15_CTL
+.set SCSI_Out__0__DM0, CYREG_PRT15_DM0
+.set SCSI_Out__0__DM1, CYREG_PRT15_DM1
+.set SCSI_Out__0__DM2, CYREG_PRT15_DM2
+.set SCSI_Out__0__DR, CYREG_PRT15_DR
+.set SCSI_Out__0__INP_DIS, CYREG_PRT15_INP_DIS
+.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set SCSI_Out__0__LCD_EN, CYREG_PRT15_LCD_EN
+.set SCSI_Out__0__MASK, 0x20
+.set SCSI_Out__0__PC, CYREG_IO_PC_PRT15_PC5
+.set SCSI_Out__0__PORT, 15
+.set SCSI_Out__0__PRT, CYREG_PRT15_PRT
+.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set SCSI_Out__0__PS, CYREG_PRT15_PS
+.set SCSI_Out__0__SHIFT, 5
+.set SCSI_Out__0__SLW, CYREG_PRT15_SLW
+.set SCSI_Out__1__AG, CYREG_PRT15_AG
+.set SCSI_Out__1__AMUX, CYREG_PRT15_AMUX
+.set SCSI_Out__1__BIE, CYREG_PRT15_BIE
+.set SCSI_Out__1__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set SCSI_Out__1__BYP, CYREG_PRT15_BYP
+.set SCSI_Out__1__CTL, CYREG_PRT15_CTL
+.set SCSI_Out__1__DM0, CYREG_PRT15_DM0
+.set SCSI_Out__1__DM1, CYREG_PRT15_DM1
+.set SCSI_Out__1__DM2, CYREG_PRT15_DM2
+.set SCSI_Out__1__DR, CYREG_PRT15_DR
+.set SCSI_Out__1__INP_DIS, CYREG_PRT15_INP_DIS
+.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set SCSI_Out__1__LCD_EN, CYREG_PRT15_LCD_EN
+.set SCSI_Out__1__MASK, 0x10
+.set SCSI_Out__1__PC, CYREG_IO_PC_PRT15_PC4
+.set SCSI_Out__1__PORT, 15
+.set SCSI_Out__1__PRT, CYREG_PRT15_PRT
+.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set SCSI_Out__1__PS, CYREG_PRT15_PS
+.set SCSI_Out__1__SHIFT, 4
+.set SCSI_Out__1__SLW, CYREG_PRT15_SLW
+.set SCSI_Out__2__AG, CYREG_PRT6_AG
+.set SCSI_Out__2__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out__2__BIE, CYREG_PRT6_BIE
+.set SCSI_Out__2__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out__2__BYP, CYREG_PRT6_BYP
+.set SCSI_Out__2__CTL, CYREG_PRT6_CTL
+.set SCSI_Out__2__DM0, CYREG_PRT6_DM0
+.set SCSI_Out__2__DM1, CYREG_PRT6_DM1
+.set SCSI_Out__2__DM2, CYREG_PRT6_DM2
+.set SCSI_Out__2__DR, CYREG_PRT6_DR
+.set SCSI_Out__2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out__2__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out__2__MASK, 0x02
+.set SCSI_Out__2__PC, CYREG_PRT6_PC1
+.set SCSI_Out__2__PORT, 6
+.set SCSI_Out__2__PRT, CYREG_PRT6_PRT
+.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out__2__PS, CYREG_PRT6_PS
+.set SCSI_Out__2__SHIFT, 1
+.set SCSI_Out__2__SLW, CYREG_PRT6_SLW
+.set SCSI_Out__3__AG, CYREG_PRT6_AG
+.set SCSI_Out__3__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out__3__BIE, CYREG_PRT6_BIE
+.set SCSI_Out__3__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out__3__BYP, CYREG_PRT6_BYP
+.set SCSI_Out__3__CTL, CYREG_PRT6_CTL
+.set SCSI_Out__3__DM0, CYREG_PRT6_DM0
+.set SCSI_Out__3__DM1, CYREG_PRT6_DM1
+.set SCSI_Out__3__DM2, CYREG_PRT6_DM2
+.set SCSI_Out__3__DR, CYREG_PRT6_DR
+.set SCSI_Out__3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out__3__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out__3__MASK, 0x01
+.set SCSI_Out__3__PC, CYREG_PRT6_PC0
+.set SCSI_Out__3__PORT, 6
+.set SCSI_Out__3__PRT, CYREG_PRT6_PRT
+.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out__3__PS, CYREG_PRT6_PS
+.set SCSI_Out__3__SHIFT, 0
+.set SCSI_Out__3__SLW, CYREG_PRT6_SLW
+.set SCSI_Out__4__AG, CYREG_PRT4_AG
+.set SCSI_Out__4__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out__4__BIE, CYREG_PRT4_BIE
+.set SCSI_Out__4__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out__4__BYP, CYREG_PRT4_BYP
+.set SCSI_Out__4__CTL, CYREG_PRT4_CTL
+.set SCSI_Out__4__DM0, CYREG_PRT4_DM0
+.set SCSI_Out__4__DM1, CYREG_PRT4_DM1
+.set SCSI_Out__4__DM2, CYREG_PRT4_DM2
+.set SCSI_Out__4__DR, CYREG_PRT4_DR
+.set SCSI_Out__4__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out__4__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out__4__MASK, 0x20
+.set SCSI_Out__4__PC, CYREG_PRT4_PC5
+.set SCSI_Out__4__PORT, 4
+.set SCSI_Out__4__PRT, CYREG_PRT4_PRT
+.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out__4__PS, CYREG_PRT4_PS
+.set SCSI_Out__4__SHIFT, 5
+.set SCSI_Out__4__SLW, CYREG_PRT4_SLW
+.set SCSI_Out__5__AG, CYREG_PRT4_AG
+.set SCSI_Out__5__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out__5__BIE, CYREG_PRT4_BIE
+.set SCSI_Out__5__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out__5__BYP, CYREG_PRT4_BYP
+.set SCSI_Out__5__CTL, CYREG_PRT4_CTL
+.set SCSI_Out__5__DM0, CYREG_PRT4_DM0
+.set SCSI_Out__5__DM1, CYREG_PRT4_DM1
+.set SCSI_Out__5__DM2, CYREG_PRT4_DM2
+.set SCSI_Out__5__DR, CYREG_PRT4_DR
+.set SCSI_Out__5__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out__5__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out__5__MASK, 0x10
+.set SCSI_Out__5__PC, CYREG_PRT4_PC4
+.set SCSI_Out__5__PORT, 4
+.set SCSI_Out__5__PRT, CYREG_PRT4_PRT
+.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out__5__PS, CYREG_PRT4_PS
+.set SCSI_Out__5__SHIFT, 4
+.set SCSI_Out__5__SLW, CYREG_PRT4_SLW
+.set SCSI_Out__6__AG, CYREG_PRT0_AG
+.set SCSI_Out__6__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__6__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__6__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__6__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__6__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__6__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__6__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__6__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__6__DR, CYREG_PRT0_DR
+.set SCSI_Out__6__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__6__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__6__MASK, 0x80
+.set SCSI_Out__6__PC, CYREG_PRT0_PC7
+.set SCSI_Out__6__PORT, 0
+.set SCSI_Out__6__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__6__PS, CYREG_PRT0_PS
+.set SCSI_Out__6__SHIFT, 7
+.set SCSI_Out__6__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__7__AG, CYREG_PRT0_AG
+.set SCSI_Out__7__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__7__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__7__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__7__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__7__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__7__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__7__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__7__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__7__DR, CYREG_PRT0_DR
+.set SCSI_Out__7__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__7__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__7__MASK, 0x40
+.set SCSI_Out__7__PC, CYREG_PRT0_PC6
+.set SCSI_Out__7__PORT, 0
+.set SCSI_Out__7__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__7__PS, CYREG_PRT0_PS
+.set SCSI_Out__7__SHIFT, 6
+.set SCSI_Out__7__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__8__AG, CYREG_PRT0_AG
+.set SCSI_Out__8__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__8__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__8__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__8__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__8__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__8__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__8__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__8__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__8__DR, CYREG_PRT0_DR
+.set SCSI_Out__8__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__8__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__8__MASK, 0x08
+.set SCSI_Out__8__PC, CYREG_PRT0_PC3
+.set SCSI_Out__8__PORT, 0
+.set SCSI_Out__8__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__8__PS, CYREG_PRT0_PS
+.set SCSI_Out__8__SHIFT, 3
+.set SCSI_Out__8__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__9__AG, CYREG_PRT0_AG
+.set SCSI_Out__9__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__9__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__9__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__9__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__9__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__9__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__9__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__9__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__9__DR, CYREG_PRT0_DR
+.set SCSI_Out__9__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__9__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__9__MASK, 0x04
+.set SCSI_Out__9__PC, CYREG_PRT0_PC2
+.set SCSI_Out__9__PORT, 0
+.set SCSI_Out__9__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__9__PS, CYREG_PRT0_PS
+.set SCSI_Out__9__SHIFT, 2
+.set SCSI_Out__9__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__ACK__AG, CYREG_PRT6_AG
+.set SCSI_Out__ACK__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out__ACK__BIE, CYREG_PRT6_BIE
+.set SCSI_Out__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out__ACK__BYP, CYREG_PRT6_BYP
+.set SCSI_Out__ACK__CTL, CYREG_PRT6_CTL
+.set SCSI_Out__ACK__DM0, CYREG_PRT6_DM0
+.set SCSI_Out__ACK__DM1, CYREG_PRT6_DM1
+.set SCSI_Out__ACK__DM2, CYREG_PRT6_DM2
+.set SCSI_Out__ACK__DR, CYREG_PRT6_DR
+.set SCSI_Out__ACK__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out__ACK__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out__ACK__MASK, 0x01
+.set SCSI_Out__ACK__PC, CYREG_PRT6_PC0
+.set SCSI_Out__ACK__PORT, 6
+.set SCSI_Out__ACK__PRT, CYREG_PRT6_PRT
+.set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out__ACK__PS, CYREG_PRT6_PS
+.set SCSI_Out__ACK__SHIFT, 0
+.set SCSI_Out__ACK__SLW, CYREG_PRT6_SLW
+.set SCSI_Out__ATN__AG, CYREG_PRT15_AG
+.set SCSI_Out__ATN__AMUX, CYREG_PRT15_AMUX
+.set SCSI_Out__ATN__BIE, CYREG_PRT15_BIE
+.set SCSI_Out__ATN__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set SCSI_Out__ATN__BYP, CYREG_PRT15_BYP
+.set SCSI_Out__ATN__CTL, CYREG_PRT15_CTL
+.set SCSI_Out__ATN__DM0, CYREG_PRT15_DM0
+.set SCSI_Out__ATN__DM1, CYREG_PRT15_DM1
+.set SCSI_Out__ATN__DM2, CYREG_PRT15_DM2
+.set SCSI_Out__ATN__DR, CYREG_PRT15_DR
+.set SCSI_Out__ATN__INP_DIS, CYREG_PRT15_INP_DIS
+.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set SCSI_Out__ATN__LCD_EN, CYREG_PRT15_LCD_EN
+.set SCSI_Out__ATN__MASK, 0x10
+.set SCSI_Out__ATN__PC, CYREG_IO_PC_PRT15_PC4
+.set SCSI_Out__ATN__PORT, 15
+.set SCSI_Out__ATN__PRT, CYREG_PRT15_PRT
+.set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set SCSI_Out__ATN__PS, CYREG_PRT15_PS
+.set SCSI_Out__ATN__SHIFT, 4
+.set SCSI_Out__ATN__SLW, CYREG_PRT15_SLW
+.set SCSI_Out__BSY__AG, CYREG_PRT6_AG
+.set SCSI_Out__BSY__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out__BSY__BIE, CYREG_PRT6_BIE
+.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out__BSY__BYP, CYREG_PRT6_BYP
+.set SCSI_Out__BSY__CTL, CYREG_PRT6_CTL
+.set SCSI_Out__BSY__DM0, CYREG_PRT6_DM0
+.set SCSI_Out__BSY__DM1, CYREG_PRT6_DM1
+.set SCSI_Out__BSY__DM2, CYREG_PRT6_DM2
+.set SCSI_Out__BSY__DR, CYREG_PRT6_DR
+.set SCSI_Out__BSY__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out__BSY__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out__BSY__MASK, 0x02
+.set SCSI_Out__BSY__PC, CYREG_PRT6_PC1
+.set SCSI_Out__BSY__PORT, 6
+.set SCSI_Out__BSY__PRT, CYREG_PRT6_PRT
+.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out__BSY__PS, CYREG_PRT6_PS
+.set SCSI_Out__BSY__SHIFT, 1
+.set SCSI_Out__BSY__SLW, CYREG_PRT6_SLW
+.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG
+.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR
+.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__CD_raw__MASK, 0x40
+.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC6
+.set SCSI_Out__CD_raw__PORT, 0
+.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS
+.set SCSI_Out__CD_raw__SHIFT, 6
+.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__DBP_raw__AG, CYREG_PRT15_AG
+.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT15_AMUX
+.set SCSI_Out__DBP_raw__BIE, CYREG_PRT15_BIE
+.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set SCSI_Out__DBP_raw__BYP, CYREG_PRT15_BYP
+.set SCSI_Out__DBP_raw__CTL, CYREG_PRT15_CTL
+.set SCSI_Out__DBP_raw__DM0, CYREG_PRT15_DM0
+.set SCSI_Out__DBP_raw__DM1, CYREG_PRT15_DM1
+.set SCSI_Out__DBP_raw__DM2, CYREG_PRT15_DM2
+.set SCSI_Out__DBP_raw__DR, CYREG_PRT15_DR
+.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT15_INP_DIS
+.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT15_LCD_EN
+.set SCSI_Out__DBP_raw__MASK, 0x20
+.set SCSI_Out__DBP_raw__PC, CYREG_IO_PC_PRT15_PC5
+.set SCSI_Out__DBP_raw__PORT, 15
+.set SCSI_Out__DBP_raw__PRT, CYREG_PRT15_PRT
+.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set SCSI_Out__DBP_raw__PS, CYREG_PRT15_PS
+.set SCSI_Out__DBP_raw__SHIFT, 5
+.set SCSI_Out__DBP_raw__SLW, CYREG_PRT15_SLW
+.set SCSI_Out__IO_raw__AG, CYREG_PRT0_AG
+.set SCSI_Out__IO_raw__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__IO_raw__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__IO_raw__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__IO_raw__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__IO_raw__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__IO_raw__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__IO_raw__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__IO_raw__DR, CYREG_PRT0_DR
+.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__IO_raw__MASK, 0x04
+.set SCSI_Out__IO_raw__PC, CYREG_PRT0_PC2
+.set SCSI_Out__IO_raw__PORT, 0
+.set SCSI_Out__IO_raw__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__IO_raw__PS, CYREG_PRT0_PS
+.set SCSI_Out__IO_raw__SHIFT, 2
+.set SCSI_Out__IO_raw__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__MSG_raw__AG, CYREG_PRT4_AG
+.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out__MSG_raw__BIE, CYREG_PRT4_BIE
+.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out__MSG_raw__BYP, CYREG_PRT4_BYP
+.set SCSI_Out__MSG_raw__CTL, CYREG_PRT4_CTL
+.set SCSI_Out__MSG_raw__DM0, CYREG_PRT4_DM0
+.set SCSI_Out__MSG_raw__DM1, CYREG_PRT4_DM1
+.set SCSI_Out__MSG_raw__DM2, CYREG_PRT4_DM2
+.set SCSI_Out__MSG_raw__DR, CYREG_PRT4_DR
+.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out__MSG_raw__MASK, 0x10
+.set SCSI_Out__MSG_raw__PC, CYREG_PRT4_PC4
+.set SCSI_Out__MSG_raw__PORT, 4
+.set SCSI_Out__MSG_raw__PRT, CYREG_PRT4_PRT
+.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out__MSG_raw__PS, CYREG_PRT4_PS
+.set SCSI_Out__MSG_raw__SHIFT, 4
+.set SCSI_Out__MSG_raw__SLW, CYREG_PRT4_SLW
+.set SCSI_Out__REQ__AG, CYREG_PRT0_AG
+.set SCSI_Out__REQ__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__REQ__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__REQ__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__REQ__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__REQ__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__REQ__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__REQ__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__REQ__DR, CYREG_PRT0_DR
+.set SCSI_Out__REQ__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__REQ__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__REQ__MASK, 0x08
+.set SCSI_Out__REQ__PC, CYREG_PRT0_PC3
+.set SCSI_Out__REQ__PORT, 0
+.set SCSI_Out__REQ__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__REQ__PS, CYREG_PRT0_PS
+.set SCSI_Out__REQ__SHIFT, 3
+.set SCSI_Out__REQ__SLW, CYREG_PRT0_SLW
+.set SCSI_Out__RST__AG, CYREG_PRT4_AG
+.set SCSI_Out__RST__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Out__RST__BIE, CYREG_PRT4_BIE
+.set SCSI_Out__RST__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Out__RST__BYP, CYREG_PRT4_BYP
+.set SCSI_Out__RST__CTL, CYREG_PRT4_CTL
+.set SCSI_Out__RST__DM0, CYREG_PRT4_DM0
+.set SCSI_Out__RST__DM1, CYREG_PRT4_DM1
+.set SCSI_Out__RST__DM2, CYREG_PRT4_DM2
+.set SCSI_Out__RST__DR, CYREG_PRT4_DR
+.set SCSI_Out__RST__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Out__RST__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Out__RST__MASK, 0x20
+.set SCSI_Out__RST__PC, CYREG_PRT4_PC5
+.set SCSI_Out__RST__PORT, 4
+.set SCSI_Out__RST__PRT, CYREG_PRT4_PRT
+.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Out__RST__PS, CYREG_PRT4_PS
+.set SCSI_Out__RST__SHIFT, 5
+.set SCSI_Out__RST__SLW, CYREG_PRT4_SLW
+.set SCSI_Out__SEL__AG, CYREG_PRT0_AG
+.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX
+.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE
+.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP
+.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL
+.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0
+.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1
+.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2
+.set SCSI_Out__SEL__DR, CYREG_PRT0_DR
+.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS
+.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN
+.set SCSI_Out__SEL__MASK, 0x80
+.set SCSI_Out__SEL__PC, CYREG_PRT0_PC7
+.set SCSI_Out__SEL__PORT, 0
+.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT
+.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set SCSI_Out__SEL__PS, CYREG_PRT0_PS
+.set SCSI_Out__SEL__SHIFT, 7
+.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW
+
+/* SCSI_Out_Bits */
+.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01
+.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
+.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
+.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
+.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
+.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
+.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
+.set SCSI_Out_Bits_Sync_ctrl_reg__3__POS, 3
+.set SCSI_Out_Bits_Sync_ctrl_reg__4__MASK, 0x10
+.set SCSI_Out_Bits_Sync_ctrl_reg__4__POS, 4
+.set SCSI_Out_Bits_Sync_ctrl_reg__5__MASK, 0x20
+.set SCSI_Out_Bits_Sync_ctrl_reg__5__POS, 5
+.set SCSI_Out_Bits_Sync_ctrl_reg__6__MASK, 0x40
+.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
+.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
+.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB15_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB15_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB15_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB15_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB15_MSK
+
+/* SCSI_Out_Ctl */
+.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
+.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK
+
+/* SCSI_Out_DBx */
+.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
+.set SCSI_Out_DBx__0__AMUX, CYREG_PRT5_AMUX
+.set SCSI_Out_DBx__0__BIE, CYREG_PRT5_BIE
+.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_Out_DBx__0__BYP, CYREG_PRT5_BYP
+.set SCSI_Out_DBx__0__CTL, CYREG_PRT5_CTL
+.set SCSI_Out_DBx__0__DM0, CYREG_PRT5_DM0
+.set SCSI_Out_DBx__0__DM1, CYREG_PRT5_DM1
+.set SCSI_Out_DBx__0__DM2, CYREG_PRT5_DM2
+.set SCSI_Out_DBx__0__DR, CYREG_PRT5_DR
+.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_Out_DBx__0__MASK, 0x02
+.set SCSI_Out_DBx__0__PC, CYREG_PRT5_PC1
+.set SCSI_Out_DBx__0__PORT, 5
+.set SCSI_Out_DBx__0__PRT, CYREG_PRT5_PRT
+.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_Out_DBx__0__PS, CYREG_PRT5_PS
+.set SCSI_Out_DBx__0__SHIFT, 1
+.set SCSI_Out_DBx__0__SLW, CYREG_PRT5_SLW
+.set SCSI_Out_DBx__1__AG, CYREG_PRT5_AG
+.set SCSI_Out_DBx__1__AMUX, CYREG_PRT5_AMUX
+.set SCSI_Out_DBx__1__BIE, CYREG_PRT5_BIE
+.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_Out_DBx__1__BYP, CYREG_PRT5_BYP
+.set SCSI_Out_DBx__1__CTL, CYREG_PRT5_CTL
+.set SCSI_Out_DBx__1__DM0, CYREG_PRT5_DM0
+.set SCSI_Out_DBx__1__DM1, CYREG_PRT5_DM1
+.set SCSI_Out_DBx__1__DM2, CYREG_PRT5_DM2
+.set SCSI_Out_DBx__1__DR, CYREG_PRT5_DR
+.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_Out_DBx__1__MASK, 0x01
+.set SCSI_Out_DBx__1__PC, CYREG_PRT5_PC0
+.set SCSI_Out_DBx__1__PORT, 5
+.set SCSI_Out_DBx__1__PRT, CYREG_PRT5_PRT
+.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_Out_DBx__1__PS, CYREG_PRT5_PS
+.set SCSI_Out_DBx__1__SHIFT, 0
+.set SCSI_Out_DBx__1__SLW, CYREG_PRT5_SLW
+.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__2__MASK, 0x20
+.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC5
+.set SCSI_Out_DBx__2__PORT, 6
+.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__2__SHIFT, 5
+.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__3__MASK, 0x10
+.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC4
+.set SCSI_Out_DBx__3__PORT, 6
+.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__3__SHIFT, 4
+.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__4__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__4__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__4__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__4__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__4__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__4__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__4__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__4__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__4__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__4__MASK, 0x80
+.set SCSI_Out_DBx__4__PC, CYREG_PRT2_PC7
+.set SCSI_Out_DBx__4__PORT, 2
+.set SCSI_Out_DBx__4__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__4__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__4__SHIFT, 7
+.set SCSI_Out_DBx__4__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__5__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__5__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__5__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__5__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__5__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__5__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__5__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__5__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__5__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__5__MASK, 0x40
+.set SCSI_Out_DBx__5__PC, CYREG_PRT2_PC6
+.set SCSI_Out_DBx__5__PORT, 2
+.set SCSI_Out_DBx__5__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__5__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__5__SHIFT, 6
+.set SCSI_Out_DBx__5__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__6__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__6__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__6__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__6__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__6__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__6__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__6__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__6__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__6__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__6__MASK, 0x08
+.set SCSI_Out_DBx__6__PC, CYREG_PRT2_PC3
+.set SCSI_Out_DBx__6__PORT, 2
+.set SCSI_Out_DBx__6__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__6__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__6__SHIFT, 3
+.set SCSI_Out_DBx__6__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__7__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__7__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__7__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__7__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__7__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__7__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__7__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__7__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__7__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__7__MASK, 0x04
+.set SCSI_Out_DBx__7__PC, CYREG_PRT2_PC2
+.set SCSI_Out_DBx__7__PORT, 2
+.set SCSI_Out_DBx__7__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__7__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__7__SHIFT, 2
+.set SCSI_Out_DBx__7__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB0__AG, CYREG_PRT5_AG
+.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT5_AMUX
+.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT5_BIE
+.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT5_BYP
+.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT5_CTL
+.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT5_DM0
+.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT5_DM1
+.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT5_DM2
+.set SCSI_Out_DBx__DB0__DR, CYREG_PRT5_DR
+.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_Out_DBx__DB0__MASK, 0x02
+.set SCSI_Out_DBx__DB0__PC, CYREG_PRT5_PC1
+.set SCSI_Out_DBx__DB0__PORT, 5
+.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT5_PRT
+.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_Out_DBx__DB0__PS, CYREG_PRT5_PS
+.set SCSI_Out_DBx__DB0__SHIFT, 1
+.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT5_SLW
+.set SCSI_Out_DBx__DB1__AG, CYREG_PRT5_AG
+.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT5_AMUX
+.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT5_BIE
+.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT5_BYP
+.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT5_CTL
+.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT5_DM0
+.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT5_DM1
+.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT5_DM2
+.set SCSI_Out_DBx__DB1__DR, CYREG_PRT5_DR
+.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_Out_DBx__DB1__MASK, 0x01
+.set SCSI_Out_DBx__DB1__PC, CYREG_PRT5_PC0
+.set SCSI_Out_DBx__DB1__PORT, 5
+.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT5_PRT
+.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_Out_DBx__DB1__PS, CYREG_PRT5_PS
+.set SCSI_Out_DBx__DB1__SHIFT, 0
+.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT5_SLW
+.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__DB2__MASK, 0x20
+.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC5
+.set SCSI_Out_DBx__DB2__PORT, 6
+.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__DB2__SHIFT, 5
+.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__DB3__MASK, 0x10
+.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC4
+.set SCSI_Out_DBx__DB3__PORT, 6
+.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__DB3__SHIFT, 4
+.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__DB4__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB4__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB4__MASK, 0x80
+.set SCSI_Out_DBx__DB4__PC, CYREG_PRT2_PC7
+.set SCSI_Out_DBx__DB4__PORT, 2
+.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB4__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB4__SHIFT, 7
+.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB5__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB5__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB5__MASK, 0x40
+.set SCSI_Out_DBx__DB5__PC, CYREG_PRT2_PC6
+.set SCSI_Out_DBx__DB5__PORT, 2
+.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB5__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB5__SHIFT, 6
+.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB6__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB6__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB6__MASK, 0x08
+.set SCSI_Out_DBx__DB6__PC, CYREG_PRT2_PC3
+.set SCSI_Out_DBx__DB6__PORT, 2
+.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB6__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB6__SHIFT, 3
+.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB7__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB7__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB7__MASK, 0x04
+.set SCSI_Out_DBx__DB7__PC, CYREG_PRT2_PC2
+.set SCSI_Out_DBx__DB7__PORT, 2
+.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB7__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB7__SHIFT, 2
+.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT2_SLW
+
+/* SD_RX_DMA */
+.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
+.set SD_RX_DMA__DRQ_NUMBER, 2
+.set SD_RX_DMA__NUMBEROF_TDS, 0
+.set SD_RX_DMA__PRIORITY, 2
+.set SD_RX_DMA__TERMIN_EN, 0
+.set SD_RX_DMA__TERMIN_SEL, 0
+.set SD_RX_DMA__TERMOUT0_EN, 1
+.set SD_RX_DMA__TERMOUT0_SEL, 2
+.set SD_RX_DMA__TERMOUT1_EN, 0
+.set SD_RX_DMA__TERMOUT1_SEL, 0
+
+/* SD_RX_DMA_COMPLETE */
+.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x10
+.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 4
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
+.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4
+.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* SD_TX_DMA */
+.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
+.set SD_TX_DMA__DRQ_NUMBER, 3
+.set SD_TX_DMA__NUMBEROF_TDS, 0
+.set SD_TX_DMA__PRIORITY, 2
+.set SD_TX_DMA__TERMIN_EN, 0
+.set SD_TX_DMA__TERMIN_SEL, 0
+.set SD_TX_DMA__TERMOUT0_EN, 1
+.set SD_TX_DMA__TERMOUT0_SEL, 3
+.set SD_TX_DMA__TERMOUT1_EN, 0
+.set SD_TX_DMA__TERMOUT1_SEL, 0
+
+/* SD_TX_DMA_COMPLETE */
+.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x20
+.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 5
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
+.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5
+.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* SCSI_Noise */
+.set SCSI_Noise__0__AG, CYREG_PRT2_AG
+.set SCSI_Noise__0__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Noise__0__BIE, CYREG_PRT2_BIE
+.set SCSI_Noise__0__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Noise__0__BYP, CYREG_PRT2_BYP
+.set SCSI_Noise__0__CTL, CYREG_PRT2_CTL
+.set SCSI_Noise__0__DM0, CYREG_PRT2_DM0
+.set SCSI_Noise__0__DM1, CYREG_PRT2_DM1
+.set SCSI_Noise__0__DM2, CYREG_PRT2_DM2
+.set SCSI_Noise__0__DR, CYREG_PRT2_DR
+.set SCSI_Noise__0__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Noise__0__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Noise__0__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Noise__0__MASK, 0x01
+.set SCSI_Noise__0__PC, CYREG_PRT2_PC0
+.set SCSI_Noise__0__PORT, 2
+.set SCSI_Noise__0__PRT, CYREG_PRT2_PRT
+.set SCSI_Noise__0__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Noise__0__PS, CYREG_PRT2_PS
+.set SCSI_Noise__0__SHIFT, 0
+.set SCSI_Noise__0__SLW, CYREG_PRT2_SLW
+.set SCSI_Noise__1__AG, CYREG_PRT6_AG
+.set SCSI_Noise__1__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Noise__1__BIE, CYREG_PRT6_BIE
+.set SCSI_Noise__1__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Noise__1__BYP, CYREG_PRT6_BYP
+.set SCSI_Noise__1__CTL, CYREG_PRT6_CTL
+.set SCSI_Noise__1__DM0, CYREG_PRT6_DM0
+.set SCSI_Noise__1__DM1, CYREG_PRT6_DM1
+.set SCSI_Noise__1__DM2, CYREG_PRT6_DM2
+.set SCSI_Noise__1__DR, CYREG_PRT6_DR
+.set SCSI_Noise__1__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Noise__1__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Noise__1__MASK, 0x08
+.set SCSI_Noise__1__PC, CYREG_PRT6_PC3
+.set SCSI_Noise__1__PORT, 6
+.set SCSI_Noise__1__PRT, CYREG_PRT6_PRT
+.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Noise__1__PS, CYREG_PRT6_PS
+.set SCSI_Noise__1__SHIFT, 3
+.set SCSI_Noise__1__SLW, CYREG_PRT6_SLW
+.set SCSI_Noise__2__AG, CYREG_PRT4_AG
+.set SCSI_Noise__2__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Noise__2__BIE, CYREG_PRT4_BIE
+.set SCSI_Noise__2__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Noise__2__BYP, CYREG_PRT4_BYP
+.set SCSI_Noise__2__CTL, CYREG_PRT4_CTL
+.set SCSI_Noise__2__DM0, CYREG_PRT4_DM0
+.set SCSI_Noise__2__DM1, CYREG_PRT4_DM1
+.set SCSI_Noise__2__DM2, CYREG_PRT4_DM2
+.set SCSI_Noise__2__DR, CYREG_PRT4_DR
+.set SCSI_Noise__2__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Noise__2__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Noise__2__MASK, 0x08
+.set SCSI_Noise__2__PC, CYREG_PRT4_PC3
+.set SCSI_Noise__2__PORT, 4
+.set SCSI_Noise__2__PRT, CYREG_PRT4_PRT
+.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Noise__2__PS, CYREG_PRT4_PS
+.set SCSI_Noise__2__SHIFT, 3
+.set SCSI_Noise__2__SLW, CYREG_PRT4_SLW
+.set SCSI_Noise__3__AG, CYREG_PRT4_AG
+.set SCSI_Noise__3__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Noise__3__BIE, CYREG_PRT4_BIE
+.set SCSI_Noise__3__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Noise__3__BYP, CYREG_PRT4_BYP
+.set SCSI_Noise__3__CTL, CYREG_PRT4_CTL
+.set SCSI_Noise__3__DM0, CYREG_PRT4_DM0
+.set SCSI_Noise__3__DM1, CYREG_PRT4_DM1
+.set SCSI_Noise__3__DM2, CYREG_PRT4_DM2
+.set SCSI_Noise__3__DR, CYREG_PRT4_DR
+.set SCSI_Noise__3__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Noise__3__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Noise__3__MASK, 0x80
+.set SCSI_Noise__3__PC, CYREG_PRT4_PC7
+.set SCSI_Noise__3__PORT, 4
+.set SCSI_Noise__3__PRT, CYREG_PRT4_PRT
+.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Noise__3__PS, CYREG_PRT4_PS
+.set SCSI_Noise__3__SHIFT, 7
+.set SCSI_Noise__3__SLW, CYREG_PRT4_SLW
+.set SCSI_Noise__4__AG, CYREG_PRT6_AG
+.set SCSI_Noise__4__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Noise__4__BIE, CYREG_PRT6_BIE
+.set SCSI_Noise__4__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Noise__4__BYP, CYREG_PRT6_BYP
+.set SCSI_Noise__4__CTL, CYREG_PRT6_CTL
+.set SCSI_Noise__4__DM0, CYREG_PRT6_DM0
+.set SCSI_Noise__4__DM1, CYREG_PRT6_DM1
+.set SCSI_Noise__4__DM2, CYREG_PRT6_DM2
+.set SCSI_Noise__4__DR, CYREG_PRT6_DR
+.set SCSI_Noise__4__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Noise__4__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Noise__4__MASK, 0x04
+.set SCSI_Noise__4__PC, CYREG_PRT6_PC2
+.set SCSI_Noise__4__PORT, 6
+.set SCSI_Noise__4__PRT, CYREG_PRT6_PRT
+.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Noise__4__PS, CYREG_PRT6_PS
+.set SCSI_Noise__4__SHIFT, 2
+.set SCSI_Noise__4__SLW, CYREG_PRT6_SLW
+.set SCSI_Noise__ACK__AG, CYREG_PRT6_AG
+.set SCSI_Noise__ACK__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Noise__ACK__BIE, CYREG_PRT6_BIE
+.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Noise__ACK__BYP, CYREG_PRT6_BYP
+.set SCSI_Noise__ACK__CTL, CYREG_PRT6_CTL
+.set SCSI_Noise__ACK__DM0, CYREG_PRT6_DM0
+.set SCSI_Noise__ACK__DM1, CYREG_PRT6_DM1
+.set SCSI_Noise__ACK__DM2, CYREG_PRT6_DM2
+.set SCSI_Noise__ACK__DR, CYREG_PRT6_DR
+.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Noise__ACK__MASK, 0x04
+.set SCSI_Noise__ACK__PC, CYREG_PRT6_PC2
+.set SCSI_Noise__ACK__PORT, 6
+.set SCSI_Noise__ACK__PRT, CYREG_PRT6_PRT
+.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Noise__ACK__PS, CYREG_PRT6_PS
+.set SCSI_Noise__ACK__SHIFT, 2
+.set SCSI_Noise__ACK__SLW, CYREG_PRT6_SLW
+.set SCSI_Noise__ATN__AG, CYREG_PRT2_AG
+.set SCSI_Noise__ATN__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Noise__ATN__BIE, CYREG_PRT2_BIE
+.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Noise__ATN__BYP, CYREG_PRT2_BYP
+.set SCSI_Noise__ATN__CTL, CYREG_PRT2_CTL
+.set SCSI_Noise__ATN__DM0, CYREG_PRT2_DM0
+.set SCSI_Noise__ATN__DM1, CYREG_PRT2_DM1
+.set SCSI_Noise__ATN__DM2, CYREG_PRT2_DM2
+.set SCSI_Noise__ATN__DR, CYREG_PRT2_DR
+.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Noise__ATN__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Noise__ATN__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Noise__ATN__MASK, 0x01
+.set SCSI_Noise__ATN__PC, CYREG_PRT2_PC0
+.set SCSI_Noise__ATN__PORT, 2
+.set SCSI_Noise__ATN__PRT, CYREG_PRT2_PRT
+.set SCSI_Noise__ATN__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Noise__ATN__PS, CYREG_PRT2_PS
+.set SCSI_Noise__ATN__SHIFT, 0
+.set SCSI_Noise__ATN__SLW, CYREG_PRT2_SLW
+.set SCSI_Noise__BSY__AG, CYREG_PRT6_AG
+.set SCSI_Noise__BSY__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Noise__BSY__BIE, CYREG_PRT6_BIE
+.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Noise__BSY__BYP, CYREG_PRT6_BYP
+.set SCSI_Noise__BSY__CTL, CYREG_PRT6_CTL
+.set SCSI_Noise__BSY__DM0, CYREG_PRT6_DM0
+.set SCSI_Noise__BSY__DM1, CYREG_PRT6_DM1
+.set SCSI_Noise__BSY__DM2, CYREG_PRT6_DM2
+.set SCSI_Noise__BSY__DR, CYREG_PRT6_DR
+.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Noise__BSY__MASK, 0x08
+.set SCSI_Noise__BSY__PC, CYREG_PRT6_PC3
+.set SCSI_Noise__BSY__PORT, 6
+.set SCSI_Noise__BSY__PRT, CYREG_PRT6_PRT
+.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Noise__BSY__PS, CYREG_PRT6_PS
+.set SCSI_Noise__BSY__SHIFT, 3
+.set SCSI_Noise__BSY__SLW, CYREG_PRT6_SLW
+.set SCSI_Noise__RST__AG, CYREG_PRT4_AG
+.set SCSI_Noise__RST__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Noise__RST__BIE, CYREG_PRT4_BIE
+.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Noise__RST__BYP, CYREG_PRT4_BYP
+.set SCSI_Noise__RST__CTL, CYREG_PRT4_CTL
+.set SCSI_Noise__RST__DM0, CYREG_PRT4_DM0
+.set SCSI_Noise__RST__DM1, CYREG_PRT4_DM1
+.set SCSI_Noise__RST__DM2, CYREG_PRT4_DM2
+.set SCSI_Noise__RST__DR, CYREG_PRT4_DR
+.set SCSI_Noise__RST__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Noise__RST__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Noise__RST__MASK, 0x80
+.set SCSI_Noise__RST__PC, CYREG_PRT4_PC7
+.set SCSI_Noise__RST__PORT, 4
+.set SCSI_Noise__RST__PRT, CYREG_PRT4_PRT
+.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Noise__RST__PS, CYREG_PRT4_PS
+.set SCSI_Noise__RST__SHIFT, 7
+.set SCSI_Noise__RST__SLW, CYREG_PRT4_SLW
+.set SCSI_Noise__SEL__AG, CYREG_PRT4_AG
+.set SCSI_Noise__SEL__AMUX, CYREG_PRT4_AMUX
+.set SCSI_Noise__SEL__BIE, CYREG_PRT4_BIE
+.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT4_BIT_MASK
+.set SCSI_Noise__SEL__BYP, CYREG_PRT4_BYP
+.set SCSI_Noise__SEL__CTL, CYREG_PRT4_CTL
+.set SCSI_Noise__SEL__DM0, CYREG_PRT4_DM0
+.set SCSI_Noise__SEL__DM1, CYREG_PRT4_DM1
+.set SCSI_Noise__SEL__DM2, CYREG_PRT4_DM2
+.set SCSI_Noise__SEL__DR, CYREG_PRT4_DR
+.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT4_INP_DIS
+.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG
+.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT4_LCD_EN
+.set SCSI_Noise__SEL__MASK, 0x08
+.set SCSI_Noise__SEL__PC, CYREG_PRT4_PC3
+.set SCSI_Noise__SEL__PORT, 4
+.set SCSI_Noise__SEL__PRT, CYREG_PRT4_PRT
+.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL
+.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN
+.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0
+.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1
+.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0
+.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1
+.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT
+.set SCSI_Noise__SEL__PS, CYREG_PRT4_PS
+.set SCSI_Noise__SEL__SHIFT, 3
+.set SCSI_Noise__SEL__SLW, CYREG_PRT4_SLW
+
+/* scsiTarget */
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB11_12_A0
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB11_12_A1
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB11_12_D0
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB11_12_D1
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB11_12_F0
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB11_12_F1
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB11_A0_A1
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB11_A0
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB11_A1
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB11_D0_D1
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB11_D0
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB11_D1
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB11_F0_F1
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB11_F0
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB11_F1
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB11_MSK
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB11_ST
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB11_CTL
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB11_CTL
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB11_MSK
+.set scsiTarget_StatusReg__0__MASK, 0x01
+.set scsiTarget_StatusReg__0__POS, 0
+.set scsiTarget_StatusReg__1__MASK, 0x02
+.set scsiTarget_StatusReg__1__POS, 1
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST
+.set scsiTarget_StatusReg__2__MASK, 0x04
+.set scsiTarget_StatusReg__2__POS, 2
+.set scsiTarget_StatusReg__3__MASK, 0x08
+.set scsiTarget_StatusReg__3__POS, 3
+.set scsiTarget_StatusReg__4__MASK, 0x10
+.set scsiTarget_StatusReg__4__POS, 4
+.set scsiTarget_StatusReg__MASK, 0x1F
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB00_MSK
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB00_ST
-/* SD_MOSI */
-.set SD_MOSI__0__MASK, 0x08
-.set SD_MOSI__0__PC, CYREG_PRT3_PC3
-.set SD_MOSI__0__PORT, 3
-.set SD_MOSI__0__SHIFT, 3
-.set SD_MOSI__AG, CYREG_PRT3_AG
-.set SD_MOSI__AMUX, CYREG_PRT3_AMUX
-.set SD_MOSI__BIE, CYREG_PRT3_BIE
-.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_MOSI__BYP, CYREG_PRT3_BYP
-.set SD_MOSI__CTL, CYREG_PRT3_CTL
-.set SD_MOSI__DM0, CYREG_PRT3_DM0
-.set SD_MOSI__DM1, CYREG_PRT3_DM1
-.set SD_MOSI__DM2, CYREG_PRT3_DM2
-.set SD_MOSI__DR, CYREG_PRT3_DR
-.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_MOSI__MASK, 0x08
-.set SD_MOSI__PORT, 3
-.set SD_MOSI__PRT, CYREG_PRT3_PRT
-.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_MOSI__PS, CYREG_PRT3_PS
-.set SD_MOSI__SHIFT, 3
-.set SD_MOSI__SLW, CYREG_PRT3_SLW
+/* Debug_Timer_Interrupt */
+.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set Debug_Timer_Interrupt__INTC_MASK, 0x02
+.set Debug_Timer_Interrupt__INTC_NUMBER, 1
+.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7
+.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
+.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* Debug_Timer_TimerHW */
+.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0
+.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1
+.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0
+.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1
+.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2
+.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0
+.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1
+.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0
+.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1
+.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3
+.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01
+.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3
+.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01
+.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0
+.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1
+.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0
+
+/* SCSI_RX_DMA */
+.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
+.set SCSI_RX_DMA__DRQ_NUMBER, 0
+.set SCSI_RX_DMA__NUMBEROF_TDS, 0
+.set SCSI_RX_DMA__PRIORITY, 2
+.set SCSI_RX_DMA__TERMIN_EN, 0
+.set SCSI_RX_DMA__TERMIN_SEL, 0
+.set SCSI_RX_DMA__TERMOUT0_EN, 1
+.set SCSI_RX_DMA__TERMOUT0_SEL, 0
+.set SCSI_RX_DMA__TERMOUT1_EN, 0
+.set SCSI_RX_DMA__TERMOUT1_SEL, 0
+
+/* SCSI_RX_DMA_COMPLETE */
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x01
+.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 0
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
+.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* SCSI_TX_DMA */
+.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0
+.set SCSI_TX_DMA__DRQ_NUMBER, 1
+.set SCSI_TX_DMA__NUMBEROF_TDS, 0
+.set SCSI_TX_DMA__PRIORITY, 2
+.set SCSI_TX_DMA__TERMIN_EN, 0
+.set SCSI_TX_DMA__TERMIN_SEL, 0
+.set SCSI_TX_DMA__TERMOUT0_EN, 1
+.set SCSI_TX_DMA__TERMOUT0_SEL, 1
+.set SCSI_TX_DMA__TERMOUT1_EN, 0
+.set SCSI_TX_DMA__TERMOUT1_SEL, 0
+
+/* SCSI_TX_DMA_COMPLETE */
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x08
+.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 3
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7
+.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_3
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* SD_Data_Clk */
+.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0
+.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1
+.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2
+.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07
+.set SD_Data_Clk__INDEX, 0x00
+.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2
+.set SD_Data_Clk__PM_ACT_MSK, 0x01
+.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2
+.set SD_Data_Clk__PM_STBY_MSK, 0x01
-/* EXTLED */
-.set EXTLED__0__MASK, 0x01
-.set EXTLED__0__PC, CYREG_PRT0_PC0
-.set EXTLED__0__PORT, 0
-.set EXTLED__0__SHIFT, 0
-.set EXTLED__AG, CYREG_PRT0_AG
-.set EXTLED__AMUX, CYREG_PRT0_AMUX
-.set EXTLED__BIE, CYREG_PRT0_BIE
-.set EXTLED__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set EXTLED__BYP, CYREG_PRT0_BYP
-.set EXTLED__CTL, CYREG_PRT0_CTL
-.set EXTLED__DM0, CYREG_PRT0_DM0
-.set EXTLED__DM1, CYREG_PRT0_DM1
-.set EXTLED__DM2, CYREG_PRT0_DM2
-.set EXTLED__DR, CYREG_PRT0_DR
-.set EXTLED__INP_DIS, CYREG_PRT0_INP_DIS
-.set EXTLED__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set EXTLED__LCD_EN, CYREG_PRT0_LCD_EN
-.set EXTLED__MASK, 0x01
-.set EXTLED__PORT, 0
-.set EXTLED__PRT, CYREG_PRT0_PRT
-.set EXTLED__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set EXTLED__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set EXTLED__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set EXTLED__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set EXTLED__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set EXTLED__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set EXTLED__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set EXTLED__PS, CYREG_PRT0_PS
-.set EXTLED__SHIFT, 0
-.set EXTLED__SLW, CYREG_PRT0_SLW
+/* timer_clock */
+.set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0
+.set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1
+.set timer_clock__CFG2, CYREG_CLKDIST_DCFG2_CFG2
+.set timer_clock__CFG2_SRC_SEL_MASK, 0x07
+.set timer_clock__INDEX, 0x02
+.set timer_clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2
+.set timer_clock__PM_ACT_MSK, 0x04
+.set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2
+.set timer_clock__PM_STBY_MSK, 0x04
-/* SD_SCK */
-.set SD_SCK__0__MASK, 0x04
-.set SD_SCK__0__PC, CYREG_PRT3_PC2
-.set SD_SCK__0__PORT, 3
-.set SD_SCK__0__SHIFT, 2
-.set SD_SCK__AG, CYREG_PRT3_AG
-.set SD_SCK__AMUX, CYREG_PRT3_AMUX
-.set SD_SCK__BIE, CYREG_PRT3_BIE
-.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_SCK__BYP, CYREG_PRT3_BYP
-.set SD_SCK__CTL, CYREG_PRT3_CTL
-.set SD_SCK__DM0, CYREG_PRT3_DM0
-.set SD_SCK__DM1, CYREG_PRT3_DM1
-.set SD_SCK__DM2, CYREG_PRT3_DM2
-.set SD_SCK__DR, CYREG_PRT3_DR
-.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_SCK__MASK, 0x04
-.set SD_SCK__PORT, 3
-.set SD_SCK__PRT, CYREG_PRT3_PRT
-.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_SCK__PS, CYREG_PRT3_PS
-.set SD_SCK__SHIFT, 2
-.set SD_SCK__SLW, CYREG_PRT3_SLW
+/* SCSI_RST_ISR */
+.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set SCSI_RST_ISR__INTC_MASK, 0x04
+.set SCSI_RST_ISR__INTC_NUMBER, 2
+.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7
+.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_2
+.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-/* SD_CD */
-.set SD_CD__0__MASK, 0x20
-.set SD_CD__0__PC, CYREG_PRT3_PC5
-.set SD_CD__0__PORT, 3
-.set SD_CD__0__SHIFT, 5
-.set SD_CD__AG, CYREG_PRT3_AG
-.set SD_CD__AMUX, CYREG_PRT3_AMUX
-.set SD_CD__BIE, CYREG_PRT3_BIE
-.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_CD__BYP, CYREG_PRT3_BYP
-.set SD_CD__CTL, CYREG_PRT3_CTL
-.set SD_CD__DM0, CYREG_PRT3_DM0
-.set SD_CD__DM1, CYREG_PRT3_DM1
-.set SD_CD__DM2, CYREG_PRT3_DM2
-.set SD_CD__DR, CYREG_PRT3_DR
-.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_CD__MASK, 0x20
-.set SD_CD__PORT, 3
-.set SD_CD__PRT, CYREG_PRT3_PRT
-.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_CD__PS, CYREG_PRT3_PS
-.set SD_CD__SHIFT, 5
-.set SD_CD__SLW, CYREG_PRT3_SLW
+/* SCSI_Filtered */
+.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01
+.set SCSI_Filtered_sts_sts_reg__0__POS, 0
+.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
+.set SCSI_Filtered_sts_sts_reg__1__POS, 1
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
+.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
+.set SCSI_Filtered_sts_sts_reg__2__POS, 2
+.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
+.set SCSI_Filtered_sts_sts_reg__3__POS, 3
+.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
+.set SCSI_Filtered_sts_sts_reg__4__POS, 4
+.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB04_MSK
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB04_ST
-/* SD_CS */
-.set SD_CS__0__MASK, 0x10
-.set SD_CS__0__PC, CYREG_PRT3_PC4
-.set SD_CS__0__PORT, 3
-.set SD_CS__0__SHIFT, 4
-.set SD_CS__AG, CYREG_PRT3_AG
-.set SD_CS__AMUX, CYREG_PRT3_AMUX
-.set SD_CS__BIE, CYREG_PRT3_BIE
-.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_CS__BYP, CYREG_PRT3_BYP
-.set SD_CS__CTL, CYREG_PRT3_CTL
-.set SD_CS__DM0, CYREG_PRT3_DM0
-.set SD_CS__DM1, CYREG_PRT3_DM1
-.set SD_CS__DM2, CYREG_PRT3_DM2
-.set SD_CS__DR, CYREG_PRT3_DR
-.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_CS__MASK, 0x10
-.set SD_CS__PORT, 3
-.set SD_CS__PRT, CYREG_PRT3_PRT
-.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_CS__PS, CYREG_PRT3_PS
-.set SD_CS__SHIFT, 4
-.set SD_CS__SLW, CYREG_PRT3_SLW
+/* SCSI_CTL_PHASE */
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
-/* LED1 */
-.set LED1__0__MASK, 0x02
-.set LED1__0__PC, CYREG_PRT0_PC1
-.set LED1__0__PORT, 0
-.set LED1__0__SHIFT, 1
-.set LED1__AG, CYREG_PRT0_AG
-.set LED1__AMUX, CYREG_PRT0_AMUX
-.set LED1__BIE, CYREG_PRT0_BIE
-.set LED1__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set LED1__BYP, CYREG_PRT0_BYP
-.set LED1__CTL, CYREG_PRT0_CTL
-.set LED1__DM0, CYREG_PRT0_DM0
-.set LED1__DM1, CYREG_PRT0_DM1
-.set LED1__DM2, CYREG_PRT0_DM2
-.set LED1__DR, CYREG_PRT0_DR
-.set LED1__INP_DIS, CYREG_PRT0_INP_DIS
-.set LED1__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set LED1__LCD_EN, CYREG_PRT0_LCD_EN
-.set LED1__MASK, 0x02
-.set LED1__PORT, 0
-.set LED1__PRT, CYREG_PRT0_PRT
-.set LED1__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set LED1__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set LED1__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set LED1__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set LED1__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set LED1__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set LED1__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set LED1__PS, CYREG_PRT0_PS
-.set LED1__SHIFT, 1
-.set LED1__SLW, CYREG_PRT0_SLW
+/* SCSI_Parity_Error */
+.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
+.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
+.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB03_MSK
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB03_ST
/* Miscellaneous */
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
-.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6
-.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0
-.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
-.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1
-.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
-.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0
-.set CYDEV_CHIP_MEMBER_5B, 4
-.set CYDEV_CHIP_FAMILY_PSOC5, 3
-.set CYDEV_CHIP_DIE_PSOC5LP, 4
-.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP
.set BCLK__BUS_CLK__HZ, 50000000
.set BCLK__BUS_CLK__KHZ, 50000
.set BCLK__BUS_CLK__MHZ, 50
-.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
.set CYDEV_CHIP_DIE_LEOPARD, 1
-.set CYDEV_CHIP_DIE_PANTHER, 3
-.set CYDEV_CHIP_DIE_PSOC4A, 2
+.set CYDEV_CHIP_DIE_PANTHER, 6
+.set CYDEV_CHIP_DIE_PSOC4A, 3
+.set CYDEV_CHIP_DIE_PSOC5LP, 5
.set CYDEV_CHIP_DIE_UNKNOWN, 0
.set CYDEV_CHIP_FAMILY_PSOC3, 1
.set CYDEV_CHIP_FAMILY_PSOC4, 2
+.set CYDEV_CHIP_FAMILY_PSOC5, 3
.set CYDEV_CHIP_FAMILY_UNKNOWN, 0
.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5
.set CYDEV_CHIP_JTAG_ID, 0x2E133069
.set CYDEV_CHIP_MEMBER_3A, 1
-.set CYDEV_CHIP_MEMBER_4A, 2
-.set CYDEV_CHIP_MEMBER_5A, 3
+.set CYDEV_CHIP_MEMBER_4A, 3
+.set CYDEV_CHIP_MEMBER_4D, 2
+.set CYDEV_CHIP_MEMBER_4F, 4
+.set CYDEV_CHIP_MEMBER_5A, 6
+.set CYDEV_CHIP_MEMBER_5B, 5
.set CYDEV_CHIP_MEMBER_UNKNOWN, 0
.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B
+.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED
+.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
+.set CYDEV_CHIP_REV_LEOPARD_ES1, 0
+.set CYDEV_CHIP_REV_LEOPARD_ES2, 1
+.set CYDEV_CHIP_REV_LEOPARD_ES3, 3
+.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3
+.set CYDEV_CHIP_REV_PANTHER_ES0, 0
+.set CYDEV_CHIP_REV_PANTHER_ES1, 1
+.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1
+.set CYDEV_CHIP_REV_PSOC4A_ES0, 17
+.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
+.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
+.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_3A_ES1, 0
.set CYDEV_CHIP_REVISION_3A_ES2, 1
.set CYDEV_CHIP_REVISION_3A_ES3, 3
.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3
.set CYDEV_CHIP_REVISION_4A_ES0, 17
.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17
+.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_5A_ES0, 0
.set CYDEV_CHIP_REVISION_5A_ES1, 1
.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1
.set CYDEV_CHIP_REVISION_5B_ES0, 0
+.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION
-.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-.set CYDEV_CHIP_REV_LEOPARD_ES1, 0
-.set CYDEV_CHIP_REV_LEOPARD_ES2, 1
-.set CYDEV_CHIP_REV_LEOPARD_ES3, 3
-.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3
-.set CYDEV_CHIP_REV_PANTHER_ES0, 0
-.set CYDEV_CHIP_REV_PANTHER_ES1, 1
-.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1
-.set CYDEV_CHIP_REV_PSOC4A_ES0, 17
-.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
-.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
+.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED
+.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1
+.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0
+.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1
+.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
.set CYDEV_CONFIGURATION_COMPRESSED, 1
.set CYDEV_CONFIGURATION_DMA, 0
.set CYDEV_CONFIGURATION_ECC, 0
.set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED
+.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED
.set CYDEV_CONFIGURATION_MODE_DMA, 2
.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1
-.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1
-.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
-.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV
+.set CYDEV_DEBUG_ENABLE_MASK, 0x20
+.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
.set CYDEV_DEBUGGING_DPS_Disable, 3
.set CYDEV_DEBUGGING_DPS_JTAG_4, 1
.set CYDEV_DEBUGGING_DPS_JTAG_5, 0
.set CYDEV_DEBUGGING_DPS_SWD, 2
+.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6
+.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV
.set CYDEV_DEBUGGING_ENABLE, 1
.set CYDEV_DEBUGGING_XRES, 0
-.set CYDEV_DEBUG_ENABLE_MASK, 0x20
-.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
.set CYDEV_DMA_CHANNELS_AVAILABLE, 24
.set CYDEV_ECC_ENABLE, 0
-.set CYDEV_HEAP_SIZE, 0x1000
+.set CYDEV_HEAP_SIZE, 0x0400
.set CYDEV_INSTRUCT_CACHE_ENABLED, 1
.set CYDEV_INTR_RISING, 0x0000003E
.set CYDEV_PROJ_TYPE, 2
.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3
.set CYDEV_PROJ_TYPE_STANDARD, 0
.set CYDEV_PROTECTION_ENABLE, 0
-.set CYDEV_STACK_SIZE, 0x4000
+.set CYDEV_STACK_SIZE, 0x1000
.set CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP, 1
.set CYDEV_USE_BUNDLED_CMSIS, 1
.set CYDEV_VARIABLE_VDDA, 0
.set CYDEV_VDDIO1_MV, 5000
.set CYDEV_VDDIO2_MV, 5000
.set CYDEV_VDDIO3_MV, 3300
-.set CYDEV_VIO0, 5
.set CYDEV_VIO0_MV, 5000
-.set CYDEV_VIO1, 5
.set CYDEV_VIO1_MV, 5000
-.set CYDEV_VIO2, 5
.set CYDEV_VIO2_MV, 5000
.set CYDEV_VIO3_MV, 3300
+.set CYIPBLOCK_ARM_CM3_VERSION, 0
+.set CYIPBLOCK_P3_ANAIF_VERSION, 0
+.set CYIPBLOCK_P3_CAPSENSE_VERSION, 0
+.set CYIPBLOCK_P3_COMP_VERSION, 0
+.set CYIPBLOCK_P3_DMA_VERSION, 0
+.set CYIPBLOCK_P3_DRQ_VERSION, 0
+.set CYIPBLOCK_P3_EMIF_VERSION, 0
+.set CYIPBLOCK_P3_I2C_VERSION, 0
+.set CYIPBLOCK_P3_LCD_VERSION, 0
+.set CYIPBLOCK_P3_LPF_VERSION, 0
+.set CYIPBLOCK_P3_PM_VERSION, 0
+.set CYIPBLOCK_P3_TIMER_VERSION, 0
+.set CYIPBLOCK_P3_USB_VERSION, 0
+.set CYIPBLOCK_P3_VIDAC_VERSION, 0
+.set CYIPBLOCK_P3_VREF_VERSION, 0
+.set CYIPBLOCK_S8_GPIO_VERSION, 0
+.set CYIPBLOCK_S8_IRQ_VERSION, 0
+.set CYIPBLOCK_S8_SAR_VERSION, 0
+.set CYIPBLOCK_S8_SIO_VERSION, 0
+.set CYIPBLOCK_S8_UDB_VERSION, 0
.set DMA_CHANNELS_USED__MASK0, 0x0000000F
.set CYDEV_BOOTLOADER_ENABLE, 0
.endif
INCLUDE cydeviceiar.inc
INCLUDE cydeviceiar_trm.inc
-/* Debug_Timer_Interrupt */
-Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-Debug_Timer_Interrupt__INTC_MASK EQU 0x02
-Debug_Timer_Interrupt__INTC_NUMBER EQU 1
-Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7
-Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
-Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SCSI_RX_DMA_COMPLETE */
-SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01
-SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
-SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SCSI_TX_DMA_COMPLETE */
-SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
-SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* Debug_Timer_TimerHW */
-Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
-Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
-Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
-Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
-Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
-Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
-Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
-Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0
-Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1
-Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
-Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01
-Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
-Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01
-Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0
-Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1
-Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0
+/* LED1 */
+LED1__0__MASK EQU 0x02
+LED1__0__PC EQU CYREG_PRT0_PC1
+LED1__0__PORT EQU 0
+LED1__0__SHIFT EQU 1
+LED1__AG EQU CYREG_PRT0_AG
+LED1__AMUX EQU CYREG_PRT0_AMUX
+LED1__BIE EQU CYREG_PRT0_BIE
+LED1__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+LED1__BYP EQU CYREG_PRT0_BYP
+LED1__CTL EQU CYREG_PRT0_CTL
+LED1__DM0 EQU CYREG_PRT0_DM0
+LED1__DM1 EQU CYREG_PRT0_DM1
+LED1__DM2 EQU CYREG_PRT0_DM2
+LED1__DR EQU CYREG_PRT0_DR
+LED1__INP_DIS EQU CYREG_PRT0_INP_DIS
+LED1__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+LED1__LCD_EN EQU CYREG_PRT0_LCD_EN
+LED1__MASK EQU 0x02
+LED1__PORT EQU 0
+LED1__PRT EQU CYREG_PRT0_PRT
+LED1__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+LED1__PS EQU CYREG_PRT0_PS
+LED1__SHIFT EQU 1
+LED1__SLW EQU CYREG_PRT0_SLW
-/* SD_RX_DMA_COMPLETE */
-SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
-SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
-SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* SD_CD */
+SD_CD__0__MASK EQU 0x20
+SD_CD__0__PC EQU CYREG_PRT3_PC5
+SD_CD__0__PORT EQU 3
+SD_CD__0__SHIFT EQU 5
+SD_CD__AG EQU CYREG_PRT3_AG
+SD_CD__AMUX EQU CYREG_PRT3_AMUX
+SD_CD__BIE EQU CYREG_PRT3_BIE
+SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_CD__BYP EQU CYREG_PRT3_BYP
+SD_CD__CTL EQU CYREG_PRT3_CTL
+SD_CD__DM0 EQU CYREG_PRT3_DM0
+SD_CD__DM1 EQU CYREG_PRT3_DM1
+SD_CD__DM2 EQU CYREG_PRT3_DM2
+SD_CD__DR EQU CYREG_PRT3_DR
+SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_CD__MASK EQU 0x20
+SD_CD__PORT EQU 3
+SD_CD__PRT EQU CYREG_PRT3_PRT
+SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_CD__PS EQU CYREG_PRT3_PS
+SD_CD__SHIFT EQU 5
+SD_CD__SLW EQU CYREG_PRT3_SLW
-/* SD_TX_DMA_COMPLETE */
-SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5
-SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
-SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* SD_CS */
+SD_CS__0__MASK EQU 0x10
+SD_CS__0__PC EQU CYREG_PRT3_PC4
+SD_CS__0__PORT EQU 3
+SD_CS__0__SHIFT EQU 4
+SD_CS__AG EQU CYREG_PRT3_AG
+SD_CS__AMUX EQU CYREG_PRT3_AMUX
+SD_CS__BIE EQU CYREG_PRT3_BIE
+SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_CS__BYP EQU CYREG_PRT3_BYP
+SD_CS__CTL EQU CYREG_PRT3_CTL
+SD_CS__DM0 EQU CYREG_PRT3_DM0
+SD_CS__DM1 EQU CYREG_PRT3_DM1
+SD_CS__DM2 EQU CYREG_PRT3_DM2
+SD_CS__DR EQU CYREG_PRT3_DR
+SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_CS__MASK EQU 0x10
+SD_CS__PORT EQU 3
+SD_CS__PRT EQU CYREG_PRT3_PRT
+SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_CS__PS EQU CYREG_PRT3_PS
+SD_CS__SHIFT EQU 4
+SD_CS__SLW EQU CYREG_PRT3_SLW
-/* SCSI_Parity_Error */
-SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
-SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
+/* USBFS_arb_int */
+USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_arb_int__INTC_MASK EQU 0x400000
+USBFS_arb_int__INTC_NUMBER EQU 22
+USBFS_arb_int__INTC_PRIOR_NUM EQU 7
+USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
+USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* USBFS_bus_reset */
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-/* SCSI_CTL_PHASE */
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
+/* USBFS_Dm */
+USBFS_Dm__0__MASK EQU 0x80
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
+USBFS_Dm__0__PORT EQU 15
+USBFS_Dm__0__SHIFT EQU 7
+USBFS_Dm__AG EQU CYREG_PRT15_AG
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dm__DR EQU CYREG_PRT15_DR
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dm__MASK EQU 0x80
+USBFS_Dm__PORT EQU 15
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dm__PS EQU CYREG_PRT15_PS
+USBFS_Dm__SHIFT EQU 7
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW
-/* SCSI_Filtered */
-SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
-SCSI_Filtered_sts_sts_reg__0__POS EQU 0
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST
-SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
-SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
-SCSI_Filtered_sts_sts_reg__2__POS EQU 2
-SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
-SCSI_Filtered_sts_sts_reg__3__POS EQU 3
-SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
-SCSI_Filtered_sts_sts_reg__4__POS EQU 4
-SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB00_MSK
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB00_ST
+/* USBFS_Dp */
+USBFS_Dp__0__MASK EQU 0x40
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
+USBFS_Dp__0__PORT EQU 15
+USBFS_Dp__0__SHIFT EQU 6
+USBFS_Dp__AG EQU CYREG_PRT15_AG
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dp__DR EQU CYREG_PRT15_DR
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dp__MASK EQU 0x40
+USBFS_Dp__PORT EQU 15
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dp__PS EQU CYREG_PRT15_PS
+USBFS_Dp__SHIFT EQU 6
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
-/* SCSI_Out_Bits */
-SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
-SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
-SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
-SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
-SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3
-SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10
-SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4
-SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20
-SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5
-SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
-SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
-SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
-SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+/* USBFS_dp_int */
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_dp_int__INTC_MASK EQU 0x1000
+USBFS_dp_int__INTC_NUMBER EQU 12
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-/* USBFS_arb_int */
-USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_arb_int__INTC_MASK EQU 0x400000
-USBFS_arb_int__INTC_NUMBER EQU 22
-USBFS_arb_int__INTC_PRIOR_NUM EQU 7
-USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
-USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* USBFS_ep_0 */
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_0__INTC_MASK EQU 0x1000000
+USBFS_ep_0__INTC_NUMBER EQU 24
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_1 */
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_1__INTC_MASK EQU 0x40
+USBFS_ep_1__INTC_NUMBER EQU 6
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_2 */
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_2__INTC_MASK EQU 0x80
+USBFS_ep_2__INTC_NUMBER EQU 7
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_3 */
+USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_3__INTC_MASK EQU 0x100
+USBFS_ep_3__INTC_NUMBER EQU 8
+USBFS_ep_3__INTC_PRIOR_NUM EQU 7
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
+USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_4 */
+USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_4__INTC_MASK EQU 0x200
+USBFS_ep_4__INTC_NUMBER EQU 9
+USBFS_ep_4__INTC_PRIOR_NUM EQU 7
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
+USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* USBFS_sof_int */
USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-/* SCSI_Out_Ctl */
-SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+/* USBFS_USB */
+USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
+USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
+USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN
+USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR
+USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG
+USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN
+USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR
+USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG
+USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN
+USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR
+USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG
+USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN
+USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR
+USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG
+USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN
+USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR
+USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG
+USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN
+USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR
+USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG
+USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN
+USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR
+USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG
+USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN
+USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR
+USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN
+USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR
+USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR
+USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA
+USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB
+USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA
+USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB
+USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR
+USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA
+USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB
+USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA
+USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB
+USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR
+USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA
+USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB
+USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA
+USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB
+USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR
+USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA
+USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB
+USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA
+USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB
+USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR
+USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA
+USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB
+USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA
+USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB
+USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR
+USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA
+USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB
+USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA
+USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB
+USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR
+USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA
+USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB
+USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA
+USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB
+USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR
+USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA
+USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB
+USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA
+USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB
+USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE
+USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT
+USBFS_USB__CR0 EQU CYREG_USB_CR0
+USBFS_USB__CR1 EQU CYREG_USB_CR1
+USBFS_USB__CWA EQU CYREG_USB_CWA
+USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
+USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
+USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
+USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
+USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
+USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
+USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
+USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1
+USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2
+USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3
+USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
+USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
+USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
+USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
+USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
+USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
+USBFS_USB__PM_ACT_MSK EQU 0x01
+USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
+USBFS_USB__PM_STBY_MSK EQU 0x01
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
+USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
+USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
+USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
+USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0
+USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1
+USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0
+USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0
+USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1
+USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0
+USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0
+USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1
+USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0
+USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0
+USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1
+USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0
+USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0
+USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1
+USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0
+USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0
+USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1
+USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
+USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
+USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
+USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
+USBFS_USB__SOF0 EQU CYREG_USB_SOF0
+USBFS_USB__SOF1 EQU CYREG_USB_SOF1
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
+USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
+USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
-/* SCSI_Out_DBx */
-SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__0__MASK EQU 0x02
-SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1
-SCSI_Out_DBx__0__PORT EQU 5
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__0__SHIFT EQU 1
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__1__MASK EQU 0x01
-SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0
-SCSI_Out_DBx__1__PORT EQU 5
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__1__SHIFT EQU 0
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__2__MASK EQU 0x20
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__2__PORT EQU 6
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__2__SHIFT EQU 5
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__3__MASK EQU 0x10
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4
-SCSI_Out_DBx__3__PORT EQU 6
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__3__SHIFT EQU 4
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__4__MASK EQU 0x80
-SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__4__PORT EQU 2
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__4__SHIFT EQU 7
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__5__MASK EQU 0x40
-SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6
-SCSI_Out_DBx__5__PORT EQU 2
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__5__SHIFT EQU 6
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__6__MASK EQU 0x08
-SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__6__PORT EQU 2
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__6__SHIFT EQU 3
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__7__MASK EQU 0x04
-SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2
-SCSI_Out_DBx__7__PORT EQU 2
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__7__SHIFT EQU 2
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__DB0__MASK EQU 0x02
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1
-SCSI_Out_DBx__DB0__PORT EQU 5
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__DB0__SHIFT EQU 1
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__DB1__MASK EQU 0x01
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0
-SCSI_Out_DBx__DB1__PORT EQU 5
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__DB1__SHIFT EQU 0
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB2__MASK EQU 0x20
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__DB2__PORT EQU 6
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB2__SHIFT EQU 5
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB3__MASK EQU 0x10
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4
-SCSI_Out_DBx__DB3__PORT EQU 6
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB3__SHIFT EQU 4
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB4__MASK EQU 0x80
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__DB4__PORT EQU 2
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB4__SHIFT EQU 7
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB5__MASK EQU 0x40
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6
-SCSI_Out_DBx__DB5__PORT EQU 2
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB5__SHIFT EQU 6
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB6__MASK EQU 0x08
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__DB6__PORT EQU 2
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB6__SHIFT EQU 3
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB7__MASK EQU 0x04
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2
-SCSI_Out_DBx__DB7__PORT EQU 2
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB7__SHIFT EQU 2
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
-
-/* SCSI_RST_ISR */
-SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RST_ISR__INTC_MASK EQU 0x04
-SCSI_RST_ISR__INTC_NUMBER EQU 2
-SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
-SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SDCard_BSPIM */
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB09_10_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB09_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB09_ST
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB09_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB09_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB09_MSK
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
-SDCard_BSPIM_RxStsReg__4__POS EQU 4
-SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
-SDCard_BSPIM_RxStsReg__5__POS EQU 5
-SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
-SDCard_BSPIM_RxStsReg__6__POS EQU 6
-SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
-SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
-SDCard_BSPIM_TxStsReg__0__POS EQU 0
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
-SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
-SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
-SDCard_BSPIM_TxStsReg__2__POS EQU 2
-SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
-SDCard_BSPIM_TxStsReg__3__POS EQU 3
-SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
-SDCard_BSPIM_TxStsReg__4__POS EQU 4
-SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB09_10_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB09_10_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB09_10_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB09_10_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB09_10_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB09_10_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB09_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB09_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB09_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB09_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB09_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB09_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB09_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB09_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB09_F1
-
-/* USBFS_dp_int */
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_dp_int__INTC_MASK EQU 0x1000
-USBFS_dp_int__INTC_NUMBER EQU 12
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SCSI_In_DBx */
-SCSI_In_DBx__0__AG EQU CYREG_PRT5_AG
-SCSI_In_DBx__0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_In_DBx__0__BIE EQU CYREG_PRT5_BIE
-SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_In_DBx__0__BYP EQU CYREG_PRT5_BYP
-SCSI_In_DBx__0__CTL EQU CYREG_PRT5_CTL
-SCSI_In_DBx__0__DM0 EQU CYREG_PRT5_DM0
-SCSI_In_DBx__0__DM1 EQU CYREG_PRT5_DM1
-SCSI_In_DBx__0__DM2 EQU CYREG_PRT5_DM2
-SCSI_In_DBx__0__DR EQU CYREG_PRT5_DR
-SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In_DBx__0__MASK EQU 0x08
-SCSI_In_DBx__0__PC EQU CYREG_PRT5_PC3
-SCSI_In_DBx__0__PORT EQU 5
-SCSI_In_DBx__0__PRT EQU CYREG_PRT5_PRT
-SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_In_DBx__0__PS EQU CYREG_PRT5_PS
-SCSI_In_DBx__0__SHIFT EQU 3
-SCSI_In_DBx__0__SLW EQU CYREG_PRT5_SLW
-SCSI_In_DBx__1__AG EQU CYREG_PRT5_AG
-SCSI_In_DBx__1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_In_DBx__1__BIE EQU CYREG_PRT5_BIE
-SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_In_DBx__1__BYP EQU CYREG_PRT5_BYP
-SCSI_In_DBx__1__CTL EQU CYREG_PRT5_CTL
-SCSI_In_DBx__1__DM0 EQU CYREG_PRT5_DM0
-SCSI_In_DBx__1__DM1 EQU CYREG_PRT5_DM1
-SCSI_In_DBx__1__DM2 EQU CYREG_PRT5_DM2
-SCSI_In_DBx__1__DR EQU CYREG_PRT5_DR
-SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In_DBx__1__MASK EQU 0x04
-SCSI_In_DBx__1__PC EQU CYREG_PRT5_PC2
-SCSI_In_DBx__1__PORT EQU 5
-SCSI_In_DBx__1__PRT EQU CYREG_PRT5_PRT
-SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_In_DBx__1__PS EQU CYREG_PRT5_PS
-SCSI_In_DBx__1__SHIFT EQU 2
-SCSI_In_DBx__1__SLW EQU CYREG_PRT5_SLW
-SCSI_In_DBx__2__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__2__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__2__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__2__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__2__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__2__MASK EQU 0x80
-SCSI_In_DBx__2__PC EQU CYREG_PRT6_PC7
-SCSI_In_DBx__2__PORT EQU 6
-SCSI_In_DBx__2__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__2__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__2__SHIFT EQU 7
-SCSI_In_DBx__2__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__3__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__3__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__3__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__3__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__3__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__3__MASK EQU 0x40
-SCSI_In_DBx__3__PC EQU CYREG_PRT6_PC6
-SCSI_In_DBx__3__PORT EQU 6
-SCSI_In_DBx__3__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__3__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__3__SHIFT EQU 6
-SCSI_In_DBx__3__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__4__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__4__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__4__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__4__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__4__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__4__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__4__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__4__MASK EQU 0x20
-SCSI_In_DBx__4__PC EQU CYREG_PRT12_PC5
-SCSI_In_DBx__4__PORT EQU 12
-SCSI_In_DBx__4__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__4__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__4__SHIFT EQU 5
-SCSI_In_DBx__4__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__4__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__5__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__5__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__5__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__5__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__5__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__5__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__5__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__5__MASK EQU 0x10
-SCSI_In_DBx__5__PC EQU CYREG_PRT12_PC4
-SCSI_In_DBx__5__PORT EQU 12
-SCSI_In_DBx__5__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__5__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__5__SHIFT EQU 4
-SCSI_In_DBx__5__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__5__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__6__MASK EQU 0x20
-SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC5
-SCSI_In_DBx__6__PORT EQU 2
-SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__6__SHIFT EQU 5
-SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__7__MASK EQU 0x10
-SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC4
-SCSI_In_DBx__7__PORT EQU 2
-SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__7__SHIFT EQU 4
-SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB0__AG EQU CYREG_PRT5_AG
-SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_In_DBx__DB0__BIE EQU CYREG_PRT5_BIE
-SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_In_DBx__DB0__BYP EQU CYREG_PRT5_BYP
-SCSI_In_DBx__DB0__CTL EQU CYREG_PRT5_CTL
-SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
-SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
-SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
-SCSI_In_DBx__DB0__DR EQU CYREG_PRT5_DR
-SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In_DBx__DB0__MASK EQU 0x08
-SCSI_In_DBx__DB0__PC EQU CYREG_PRT5_PC3
-SCSI_In_DBx__DB0__PORT EQU 5
-SCSI_In_DBx__DB0__PRT EQU CYREG_PRT5_PRT
-SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_In_DBx__DB0__PS EQU CYREG_PRT5_PS
-SCSI_In_DBx__DB0__SHIFT EQU 3
-SCSI_In_DBx__DB0__SLW EQU CYREG_PRT5_SLW
-SCSI_In_DBx__DB1__AG EQU CYREG_PRT5_AG
-SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_In_DBx__DB1__BIE EQU CYREG_PRT5_BIE
-SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_In_DBx__DB1__BYP EQU CYREG_PRT5_BYP
-SCSI_In_DBx__DB1__CTL EQU CYREG_PRT5_CTL
-SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
-SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
-SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
-SCSI_In_DBx__DB1__DR EQU CYREG_PRT5_DR
-SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In_DBx__DB1__MASK EQU 0x04
-SCSI_In_DBx__DB1__PC EQU CYREG_PRT5_PC2
-SCSI_In_DBx__DB1__PORT EQU 5
-SCSI_In_DBx__DB1__PRT EQU CYREG_PRT5_PRT
-SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_In_DBx__DB1__PS EQU CYREG_PRT5_PS
-SCSI_In_DBx__DB1__SHIFT EQU 2
-SCSI_In_DBx__DB1__SLW EQU CYREG_PRT5_SLW
-SCSI_In_DBx__DB2__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__DB2__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__DB2__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__DB2__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__DB2__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__DB2__MASK EQU 0x80
-SCSI_In_DBx__DB2__PC EQU CYREG_PRT6_PC7
-SCSI_In_DBx__DB2__PORT EQU 6
-SCSI_In_DBx__DB2__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__DB2__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__DB2__SHIFT EQU 7
-SCSI_In_DBx__DB2__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__DB3__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__DB3__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__DB3__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__DB3__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__DB3__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__DB3__MASK EQU 0x40
-SCSI_In_DBx__DB3__PC EQU CYREG_PRT6_PC6
-SCSI_In_DBx__DB3__PORT EQU 6
-SCSI_In_DBx__DB3__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__DB3__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__DB3__SHIFT EQU 6
-SCSI_In_DBx__DB3__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__DB4__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__DB4__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__DB4__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__DB4__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__DB4__MASK EQU 0x20
-SCSI_In_DBx__DB4__PC EQU CYREG_PRT12_PC5
-SCSI_In_DBx__DB4__PORT EQU 12
-SCSI_In_DBx__DB4__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__DB4__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__DB4__SHIFT EQU 5
-SCSI_In_DBx__DB4__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__DB4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__DB4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__DB4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__DB4__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__DB5__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__DB5__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__DB5__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__DB5__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__DB5__MASK EQU 0x10
-SCSI_In_DBx__DB5__PC EQU CYREG_PRT12_PC4
-SCSI_In_DBx__DB5__PORT EQU 12
-SCSI_In_DBx__DB5__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__DB5__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__DB5__SHIFT EQU 4
-SCSI_In_DBx__DB5__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__DB5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__DB5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__DB5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__DB5__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB6__MASK EQU 0x20
-SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC5
-SCSI_In_DBx__DB6__PORT EQU 2
-SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB6__SHIFT EQU 5
-SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB7__MASK EQU 0x10
-SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC4
-SCSI_In_DBx__DB7__PORT EQU 2
-SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB7__SHIFT EQU 4
-SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW
-
-/* SCSI_RX_DMA */
-SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_RX_DMA__DRQ_NUMBER EQU 0
-SCSI_RX_DMA__NUMBEROF_TDS EQU 0
-SCSI_RX_DMA__PRIORITY EQU 2
-SCSI_RX_DMA__TERMIN_EN EQU 0
-SCSI_RX_DMA__TERMIN_SEL EQU 0
-SCSI_RX_DMA__TERMOUT0_EN EQU 1
-SCSI_RX_DMA__TERMOUT0_SEL EQU 0
-SCSI_RX_DMA__TERMOUT1_EN EQU 0
-SCSI_RX_DMA__TERMOUT1_SEL EQU 0
-
-/* SCSI_TX_DMA */
-SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_TX_DMA__DRQ_NUMBER EQU 1
-SCSI_TX_DMA__NUMBEROF_TDS EQU 0
-SCSI_TX_DMA__PRIORITY EQU 2
-SCSI_TX_DMA__TERMIN_EN EQU 0
-SCSI_TX_DMA__TERMIN_SEL EQU 0
-SCSI_TX_DMA__TERMOUT0_EN EQU 1
-SCSI_TX_DMA__TERMOUT0_SEL EQU 1
-SCSI_TX_DMA__TERMOUT1_EN EQU 0
-SCSI_TX_DMA__TERMOUT1_SEL EQU 0
-
-/* SD_Data_Clk */
-SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
-SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
-SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
-SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
-SD_Data_Clk__INDEX EQU 0x00
-SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SD_Data_Clk__PM_ACT_MSK EQU 0x01
-SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SD_Data_Clk__PM_STBY_MSK EQU 0x01
-
-/* timer_clock */
-timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
-timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
-timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
-timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
-timer_clock__INDEX EQU 0x02
-timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-timer_clock__PM_ACT_MSK EQU 0x04
-timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-timer_clock__PM_STBY_MSK EQU 0x04
-
-/* SCSI_Noise */
-SCSI_Noise__0__AG EQU CYREG_PRT2_AG
-SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE
-SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP
-SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL
-SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0
-SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1
-SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2
-SCSI_Noise__0__DR EQU CYREG_PRT2_DR
-SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Noise__0__MASK EQU 0x01
-SCSI_Noise__0__PC EQU CYREG_PRT2_PC0
-SCSI_Noise__0__PORT EQU 2
-SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT
-SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Noise__0__PS EQU CYREG_PRT2_PS
-SCSI_Noise__0__SHIFT EQU 0
-SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW
-SCSI_Noise__1__AG EQU CYREG_PRT6_AG
-SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__1__DR EQU CYREG_PRT6_DR
-SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__1__MASK EQU 0x08
-SCSI_Noise__1__PC EQU CYREG_PRT6_PC3
-SCSI_Noise__1__PORT EQU 6
-SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__1__PS EQU CYREG_PRT6_PS
-SCSI_Noise__1__SHIFT EQU 3
-SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__2__AG EQU CYREG_PRT4_AG
-SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE
-SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP
-SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL
-SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0
-SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1
-SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2
-SCSI_Noise__2__DR EQU CYREG_PRT4_DR
-SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Noise__2__MASK EQU 0x08
-SCSI_Noise__2__PC EQU CYREG_PRT4_PC3
-SCSI_Noise__2__PORT EQU 4
-SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT
-SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Noise__2__PS EQU CYREG_PRT4_PS
-SCSI_Noise__2__SHIFT EQU 3
-SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW
-SCSI_Noise__3__AG EQU CYREG_PRT4_AG
-SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE
-SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP
-SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL
-SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0
-SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1
-SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2
-SCSI_Noise__3__DR EQU CYREG_PRT4_DR
-SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Noise__3__MASK EQU 0x80
-SCSI_Noise__3__PC EQU CYREG_PRT4_PC7
-SCSI_Noise__3__PORT EQU 4
-SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT
-SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Noise__3__PS EQU CYREG_PRT4_PS
-SCSI_Noise__3__SHIFT EQU 7
-SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW
-SCSI_Noise__4__AG EQU CYREG_PRT6_AG
-SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__4__DR EQU CYREG_PRT6_DR
-SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__4__MASK EQU 0x04
-SCSI_Noise__4__PC EQU CYREG_PRT6_PC2
-SCSI_Noise__4__PORT EQU 6
-SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__4__PS EQU CYREG_PRT6_PS
-SCSI_Noise__4__SHIFT EQU 2
-SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG
-SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR
-SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__ACK__MASK EQU 0x04
-SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2
-SCSI_Noise__ACK__PORT EQU 6
-SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS
-SCSI_Noise__ACK__SHIFT EQU 2
-SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG
-SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE
-SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP
-SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL
-SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0
-SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1
-SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2
-SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR
-SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Noise__ATN__MASK EQU 0x01
-SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0
-SCSI_Noise__ATN__PORT EQU 2
-SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT
-SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS
-SCSI_Noise__ATN__SHIFT EQU 0
-SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW
-SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG
-SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR
-SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__BSY__MASK EQU 0x08
-SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3
-SCSI_Noise__BSY__PORT EQU 6
-SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS
-SCSI_Noise__BSY__SHIFT EQU 3
-SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__RST__AG EQU CYREG_PRT4_AG
-SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE
-SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP
-SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL
-SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0
-SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1
-SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2
-SCSI_Noise__RST__DR EQU CYREG_PRT4_DR
-SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Noise__RST__MASK EQU 0x80
-SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7
-SCSI_Noise__RST__PORT EQU 4
-SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT
-SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Noise__RST__PS EQU CYREG_PRT4_PS
-SCSI_Noise__RST__SHIFT EQU 7
-SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW
-SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG
-SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE
-SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP
-SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL
-SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0
-SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1
-SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2
-SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR
-SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Noise__SEL__MASK EQU 0x08
-SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3
-SCSI_Noise__SEL__PORT EQU 4
-SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT
-SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS
-SCSI_Noise__SEL__SHIFT EQU 3
-SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW
-
-/* scsiTarget */
-scsiTarget_StatusReg__0__MASK EQU 0x01
-scsiTarget_StatusReg__0__POS EQU 0
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
-scsiTarget_StatusReg__1__MASK EQU 0x02
-scsiTarget_StatusReg__1__POS EQU 1
-scsiTarget_StatusReg__2__MASK EQU 0x04
-scsiTarget_StatusReg__2__POS EQU 2
-scsiTarget_StatusReg__3__MASK EQU 0x08
-scsiTarget_StatusReg__3__POS EQU 3
-scsiTarget_StatusReg__4__MASK EQU 0x10
-scsiTarget_StatusReg__4__POS EQU 4
-scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK
-scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
-scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL
-scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB12_MSK
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB12_ST
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB12_CTL
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB12_CTL
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB12_MSK
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB12_13_A0
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB12_13_A1
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB12_13_D0
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB12_13_D1
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB12_13_F0
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB12_13_F1
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB12_A0_A1
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB12_A0
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB12_A1
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB12_D0_D1
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB12_D0
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB12_D1
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB12_F0_F1
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB12_F0
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB12_F1
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-
-/* USBFS_ep_0 */
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_0__INTC_MASK EQU 0x1000000
-USBFS_ep_0__INTC_NUMBER EQU 24
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_1 */
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x40
-USBFS_ep_1__INTC_NUMBER EQU 6
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_2 */
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x80
-USBFS_ep_2__INTC_NUMBER EQU 7
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_3 */
-USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_3__INTC_MASK EQU 0x100
-USBFS_ep_3__INTC_NUMBER EQU 8
-USBFS_ep_3__INTC_PRIOR_NUM EQU 7
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
-USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_4 */
-USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_4__INTC_MASK EQU 0x200
-USBFS_ep_4__INTC_NUMBER EQU 9
-USBFS_ep_4__INTC_PRIOR_NUM EQU 7
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
-USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SD_RX_DMA */
-SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_RX_DMA__DRQ_NUMBER EQU 2
-SD_RX_DMA__NUMBEROF_TDS EQU 0
-SD_RX_DMA__PRIORITY EQU 2
-SD_RX_DMA__TERMIN_EN EQU 0
-SD_RX_DMA__TERMIN_SEL EQU 0
-SD_RX_DMA__TERMOUT0_EN EQU 1
-SD_RX_DMA__TERMOUT0_SEL EQU 2
-SD_RX_DMA__TERMOUT1_EN EQU 0
-SD_RX_DMA__TERMOUT1_SEL EQU 0
-
-/* SD_TX_DMA */
-SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_TX_DMA__DRQ_NUMBER EQU 3
-SD_TX_DMA__NUMBEROF_TDS EQU 0
-SD_TX_DMA__PRIORITY EQU 2
-SD_TX_DMA__TERMIN_EN EQU 0
-SD_TX_DMA__TERMIN_SEL EQU 0
-SD_TX_DMA__TERMOUT0_EN EQU 1
-SD_TX_DMA__TERMOUT0_SEL EQU 3
-SD_TX_DMA__TERMOUT1_EN EQU 0
-SD_TX_DMA__TERMOUT1_SEL EQU 0
-
-/* USBFS_USB */
-USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
-USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
-USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN
-USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR
-USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG
-USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN
-USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR
-USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG
-USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN
-USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR
-USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG
-USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN
-USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR
-USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG
-USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN
-USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR
-USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG
-USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN
-USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR
-USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG
-USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN
-USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR
-USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG
-USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN
-USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR
-USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN
-USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR
-USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR
-USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA
-USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB
-USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA
-USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB
-USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR
-USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA
-USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB
-USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA
-USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB
-USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR
-USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA
-USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB
-USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA
-USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB
-USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR
-USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA
-USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB
-USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA
-USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB
-USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR
-USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA
-USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB
-USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA
-USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB
-USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR
-USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA
-USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB
-USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA
-USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB
-USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR
-USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA
-USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB
-USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA
-USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB
-USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR
-USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA
-USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB
-USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA
-USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB
-USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE
-USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT
-USBFS_USB__CR0 EQU CYREG_USB_CR0
-USBFS_USB__CR1 EQU CYREG_USB_CR1
-USBFS_USB__CWA EQU CYREG_USB_CWA
-USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
-USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
-USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
-USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
-USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
-USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
-USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
-USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1
-USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2
-USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3
-USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
-USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
-USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
-USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
-USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
-USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
-USBFS_USB__PM_ACT_MSK EQU 0x01
-USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
-USBFS_USB__PM_STBY_MSK EQU 0x01
-USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
-USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
-USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
-USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0
-USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1
-USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0
-USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0
-USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1
-USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0
-USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0
-USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1
-USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0
-USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0
-USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1
-USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0
-USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0
-USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1
-USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0
-USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0
-USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1
-USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
-USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
-USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
-USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
-USBFS_USB__SOF0 EQU CYREG_USB_SOF0
-USBFS_USB__SOF1 EQU CYREG_USB_SOF1
-USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
-USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
-
-/* SCSI_CLK */
-SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
-SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
-SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
-SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
-SCSI_CLK__INDEX EQU 0x01
-SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SCSI_CLK__PM_ACT_MSK EQU 0x02
-SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SCSI_CLK__PM_STBY_MSK EQU 0x02
-
-/* SCSI_Out */
-SCSI_Out__0__AG EQU CYREG_PRT15_AG
-SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out__0__BIE EQU CYREG_PRT15_BIE
-SCSI_Out__0__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out__0__BYP EQU CYREG_PRT15_BYP
-SCSI_Out__0__CTL EQU CYREG_PRT15_CTL
-SCSI_Out__0__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out__0__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out__0__DR EQU CYREG_PRT15_DR
-SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out__0__MASK EQU 0x20
-SCSI_Out__0__PC EQU CYREG_IO_PC_PRT15_PC5
-SCSI_Out__0__PORT EQU 15
-SCSI_Out__0__PRT EQU CYREG_PRT15_PRT
-SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out__0__PS EQU CYREG_PRT15_PS
-SCSI_Out__0__SHIFT EQU 5
-SCSI_Out__0__SLW EQU CYREG_PRT15_SLW
-SCSI_Out__1__AG EQU CYREG_PRT15_AG
-SCSI_Out__1__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out__1__BIE EQU CYREG_PRT15_BIE
-SCSI_Out__1__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out__1__BYP EQU CYREG_PRT15_BYP
-SCSI_Out__1__CTL EQU CYREG_PRT15_CTL
-SCSI_Out__1__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out__1__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out__1__DR EQU CYREG_PRT15_DR
-SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out__1__MASK EQU 0x10
-SCSI_Out__1__PC EQU CYREG_IO_PC_PRT15_PC4
-SCSI_Out__1__PORT EQU 15
-SCSI_Out__1__PRT EQU CYREG_PRT15_PRT
-SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out__1__PS EQU CYREG_PRT15_PS
-SCSI_Out__1__SHIFT EQU 4
-SCSI_Out__1__SLW EQU CYREG_PRT15_SLW
-SCSI_Out__2__AG EQU CYREG_PRT6_AG
-SCSI_Out__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__2__DR EQU CYREG_PRT6_DR
-SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__2__MASK EQU 0x02
-SCSI_Out__2__PC EQU CYREG_PRT6_PC1
-SCSI_Out__2__PORT EQU 6
-SCSI_Out__2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__2__PS EQU CYREG_PRT6_PS
-SCSI_Out__2__SHIFT EQU 1
-SCSI_Out__2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__3__AG EQU CYREG_PRT6_AG
-SCSI_Out__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__3__DR EQU CYREG_PRT6_DR
-SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__3__MASK EQU 0x01
-SCSI_Out__3__PC EQU CYREG_PRT6_PC0
-SCSI_Out__3__PORT EQU 6
-SCSI_Out__3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__3__PS EQU CYREG_PRT6_PS
-SCSI_Out__3__SHIFT EQU 0
-SCSI_Out__3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__4__AG EQU CYREG_PRT4_AG
-SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__4__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__4__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__4__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__4__DR EQU CYREG_PRT4_DR
-SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__4__MASK EQU 0x20
-SCSI_Out__4__PC EQU CYREG_PRT4_PC5
-SCSI_Out__4__PORT EQU 4
-SCSI_Out__4__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__4__PS EQU CYREG_PRT4_PS
-SCSI_Out__4__SHIFT EQU 5
-SCSI_Out__4__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__5__AG EQU CYREG_PRT4_AG
-SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__5__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__5__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__5__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__5__DR EQU CYREG_PRT4_DR
-SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__5__MASK EQU 0x10
-SCSI_Out__5__PC EQU CYREG_PRT4_PC4
-SCSI_Out__5__PORT EQU 4
-SCSI_Out__5__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__5__PS EQU CYREG_PRT4_PS
-SCSI_Out__5__SHIFT EQU 4
-SCSI_Out__5__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__6__AG EQU CYREG_PRT0_AG
-SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__6__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__6__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__6__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__6__DR EQU CYREG_PRT0_DR
-SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__6__MASK EQU 0x80
-SCSI_Out__6__PC EQU CYREG_PRT0_PC7
-SCSI_Out__6__PORT EQU 0
-SCSI_Out__6__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__6__PS EQU CYREG_PRT0_PS
-SCSI_Out__6__SHIFT EQU 7
-SCSI_Out__6__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__7__AG EQU CYREG_PRT0_AG
-SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__7__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__7__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__7__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__7__DR EQU CYREG_PRT0_DR
-SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__7__MASK EQU 0x40
-SCSI_Out__7__PC EQU CYREG_PRT0_PC6
-SCSI_Out__7__PORT EQU 0
-SCSI_Out__7__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__7__PS EQU CYREG_PRT0_PS
-SCSI_Out__7__SHIFT EQU 6
-SCSI_Out__7__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__8__AG EQU CYREG_PRT0_AG
-SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__8__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__8__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__8__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__8__DR EQU CYREG_PRT0_DR
-SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__8__MASK EQU 0x08
-SCSI_Out__8__PC EQU CYREG_PRT0_PC3
-SCSI_Out__8__PORT EQU 0
-SCSI_Out__8__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__8__PS EQU CYREG_PRT0_PS
-SCSI_Out__8__SHIFT EQU 3
-SCSI_Out__8__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__9__AG EQU CYREG_PRT0_AG
-SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__9__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__9__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__9__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__9__DR EQU CYREG_PRT0_DR
-SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__9__MASK EQU 0x04
-SCSI_Out__9__PC EQU CYREG_PRT0_PC2
-SCSI_Out__9__PORT EQU 0
-SCSI_Out__9__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__9__PS EQU CYREG_PRT0_PS
-SCSI_Out__9__SHIFT EQU 2
-SCSI_Out__9__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__ACK__AG EQU CYREG_PRT6_AG
-SCSI_Out__ACK__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__ACK__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__ACK__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__ACK__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__ACK__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__ACK__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__ACK__DR EQU CYREG_PRT6_DR
-SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__ACK__MASK EQU 0x01
-SCSI_Out__ACK__PC EQU CYREG_PRT6_PC0
-SCSI_Out__ACK__PORT EQU 6
-SCSI_Out__ACK__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__ACK__PS EQU CYREG_PRT6_PS
-SCSI_Out__ACK__SHIFT EQU 0
-SCSI_Out__ACK__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__ATN__AG EQU CYREG_PRT15_AG
-SCSI_Out__ATN__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out__ATN__BIE EQU CYREG_PRT15_BIE
-SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out__ATN__BYP EQU CYREG_PRT15_BYP
-SCSI_Out__ATN__CTL EQU CYREG_PRT15_CTL
-SCSI_Out__ATN__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out__ATN__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out__ATN__DR EQU CYREG_PRT15_DR
-SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out__ATN__MASK EQU 0x10
-SCSI_Out__ATN__PC EQU CYREG_IO_PC_PRT15_PC4
-SCSI_Out__ATN__PORT EQU 15
-SCSI_Out__ATN__PRT EQU CYREG_PRT15_PRT
-SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out__ATN__PS EQU CYREG_PRT15_PS
-SCSI_Out__ATN__SHIFT EQU 4
-SCSI_Out__ATN__SLW EQU CYREG_PRT15_SLW
-SCSI_Out__BSY__AG EQU CYREG_PRT6_AG
-SCSI_Out__BSY__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__BSY__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__BSY__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__BSY__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__BSY__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__BSY__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__BSY__DR EQU CYREG_PRT6_DR
-SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__BSY__MASK EQU 0x02
-SCSI_Out__BSY__PC EQU CYREG_PRT6_PC1
-SCSI_Out__BSY__PORT EQU 6
-SCSI_Out__BSY__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__BSY__PS EQU CYREG_PRT6_PS
-SCSI_Out__BSY__SHIFT EQU 1
-SCSI_Out__BSY__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
-SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
-SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__CD_raw__MASK EQU 0x40
-SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC6
-SCSI_Out__CD_raw__PORT EQU 0
-SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
-SCSI_Out__CD_raw__SHIFT EQU 6
-SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__DBP_raw__AG EQU CYREG_PRT15_AG
-SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out__DBP_raw__BIE EQU CYREG_PRT15_BIE
-SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out__DBP_raw__BYP EQU CYREG_PRT15_BYP
-SCSI_Out__DBP_raw__CTL EQU CYREG_PRT15_CTL
-SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR
-SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out__DBP_raw__MASK EQU 0x20
-SCSI_Out__DBP_raw__PC EQU CYREG_IO_PC_PRT15_PC5
-SCSI_Out__DBP_raw__PORT EQU 15
-SCSI_Out__DBP_raw__PRT EQU CYREG_PRT15_PRT
-SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out__DBP_raw__PS EQU CYREG_PRT15_PS
-SCSI_Out__DBP_raw__SHIFT EQU 5
-SCSI_Out__DBP_raw__SLW EQU CYREG_PRT15_SLW
-SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG
-SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR
-SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__IO_raw__MASK EQU 0x04
-SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC2
-SCSI_Out__IO_raw__PORT EQU 0
-SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS
-SCSI_Out__IO_raw__SHIFT EQU 2
-SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__MSG_raw__AG EQU CYREG_PRT4_AG
-SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__MSG_raw__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__MSG_raw__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__MSG_raw__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__MSG_raw__DR EQU CYREG_PRT4_DR
-SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__MSG_raw__MASK EQU 0x10
-SCSI_Out__MSG_raw__PC EQU CYREG_PRT4_PC4
-SCSI_Out__MSG_raw__PORT EQU 4
-SCSI_Out__MSG_raw__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__MSG_raw__PS EQU CYREG_PRT4_PS
-SCSI_Out__MSG_raw__SHIFT EQU 4
-SCSI_Out__MSG_raw__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__REQ__AG EQU CYREG_PRT0_AG
-SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__REQ__DR EQU CYREG_PRT0_DR
-SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__REQ__MASK EQU 0x08
-SCSI_Out__REQ__PC EQU CYREG_PRT0_PC3
-SCSI_Out__REQ__PORT EQU 0
-SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__REQ__PS EQU CYREG_PRT0_PS
-SCSI_Out__REQ__SHIFT EQU 3
-SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__RST__AG EQU CYREG_PRT4_AG
-SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__RST__DR EQU CYREG_PRT4_DR
-SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__RST__MASK EQU 0x20
-SCSI_Out__RST__PC EQU CYREG_PRT4_PC5
-SCSI_Out__RST__PORT EQU 4
-SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__RST__PS EQU CYREG_PRT4_PS
-SCSI_Out__RST__SHIFT EQU 5
-SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__SEL__AG EQU CYREG_PRT0_AG
-SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
-SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__SEL__MASK EQU 0x80
-SCSI_Out__SEL__PC EQU CYREG_PRT0_PC7
-SCSI_Out__SEL__PORT EQU 0
-SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
-SCSI_Out__SEL__SHIFT EQU 7
-SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
+/* EXTLED */
+EXTLED__0__MASK EQU 0x01
+EXTLED__0__PC EQU CYREG_PRT0_PC0
+EXTLED__0__PORT EQU 0
+EXTLED__0__SHIFT EQU 0
+EXTLED__AG EQU CYREG_PRT0_AG
+EXTLED__AMUX EQU CYREG_PRT0_AMUX
+EXTLED__BIE EQU CYREG_PRT0_BIE
+EXTLED__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+EXTLED__BYP EQU CYREG_PRT0_BYP
+EXTLED__CTL EQU CYREG_PRT0_CTL
+EXTLED__DM0 EQU CYREG_PRT0_DM0
+EXTLED__DM1 EQU CYREG_PRT0_DM1
+EXTLED__DM2 EQU CYREG_PRT0_DM2
+EXTLED__DR EQU CYREG_PRT0_DR
+EXTLED__INP_DIS EQU CYREG_PRT0_INP_DIS
+EXTLED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+EXTLED__LCD_EN EQU CYREG_PRT0_LCD_EN
+EXTLED__MASK EQU 0x01
+EXTLED__PORT EQU 0
+EXTLED__PRT EQU CYREG_PRT0_PRT
+EXTLED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+EXTLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+EXTLED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+EXTLED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+EXTLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+EXTLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+EXTLED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+EXTLED__PS EQU CYREG_PRT0_PS
+EXTLED__SHIFT EQU 0
+EXTLED__SLW EQU CYREG_PRT0_SLW
-/* USBFS_Dm */
-USBFS_Dm__0__MASK EQU 0x80
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
-USBFS_Dm__0__PORT EQU 15
-USBFS_Dm__0__SHIFT EQU 7
-USBFS_Dm__AG EQU CYREG_PRT15_AG
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dm__DR EQU CYREG_PRT15_DR
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dm__MASK EQU 0x80
-USBFS_Dm__PORT EQU 15
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dm__PS EQU CYREG_PRT15_PS
-USBFS_Dm__SHIFT EQU 7
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW
+/* SDCard_BSPIM */
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB10_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB10_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB10_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB10_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB10_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB10_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB10_ST
+SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
+SDCard_BSPIM_RxStsReg__4__POS EQU 4
+SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
+SDCard_BSPIM_RxStsReg__5__POS EQU 5
+SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
+SDCard_BSPIM_RxStsReg__6__POS EQU 6
+SDCard_BSPIM_RxStsReg__MASK EQU 0x70
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB08_09_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB08_09_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB08_09_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB08_09_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB08_09_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB08_09_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB08_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB08_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB08_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB08_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB08_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB08_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB08_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB08_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB08_F1
+SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
+SDCard_BSPIM_TxStsReg__0__POS EQU 0
+SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
+SDCard_BSPIM_TxStsReg__1__POS EQU 1
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
+SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
+SDCard_BSPIM_TxStsReg__2__POS EQU 2
+SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
+SDCard_BSPIM_TxStsReg__3__POS EQU 3
+SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
+SDCard_BSPIM_TxStsReg__4__POS EQU 4
+SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
-/* USBFS_Dp */
-USBFS_Dp__0__MASK EQU 0x40
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
-USBFS_Dp__0__PORT EQU 15
-USBFS_Dp__0__SHIFT EQU 6
-USBFS_Dp__AG EQU CYREG_PRT15_AG
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dp__DR EQU CYREG_PRT15_DR
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dp__MASK EQU 0x40
-USBFS_Dp__PORT EQU 15
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dp__PS EQU CYREG_PRT15_PS
-USBFS_Dp__SHIFT EQU 6
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+/* SD_SCK */
+SD_SCK__0__MASK EQU 0x04
+SD_SCK__0__PC EQU CYREG_PRT3_PC2
+SD_SCK__0__PORT EQU 3
+SD_SCK__0__SHIFT EQU 2
+SD_SCK__AG EQU CYREG_PRT3_AG
+SD_SCK__AMUX EQU CYREG_PRT3_AMUX
+SD_SCK__BIE EQU CYREG_PRT3_BIE
+SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_SCK__BYP EQU CYREG_PRT3_BYP
+SD_SCK__CTL EQU CYREG_PRT3_CTL
+SD_SCK__DM0 EQU CYREG_PRT3_DM0
+SD_SCK__DM1 EQU CYREG_PRT3_DM1
+SD_SCK__DM2 EQU CYREG_PRT3_DM2
+SD_SCK__DR EQU CYREG_PRT3_DR
+SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_SCK__MASK EQU 0x04
+SD_SCK__PORT EQU 3
+SD_SCK__PRT EQU CYREG_PRT3_PRT
+SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_SCK__PS EQU CYREG_PRT3_PS
+SD_SCK__SHIFT EQU 2
+SD_SCK__SLW EQU CYREG_PRT3_SLW
/* SCSI_In */
SCSI_In__0__AG EQU CYREG_PRT2_AG
SCSI_In__REQ__SHIFT EQU 5
SCSI_In__REQ__SLW EQU CYREG_PRT0_SLW
-/* SD_MISO */
-SD_MISO__0__MASK EQU 0x02
-SD_MISO__0__PC EQU CYREG_PRT3_PC1
-SD_MISO__0__PORT EQU 3
-SD_MISO__0__SHIFT EQU 1
-SD_MISO__AG EQU CYREG_PRT3_AG
-SD_MISO__AMUX EQU CYREG_PRT3_AMUX
-SD_MISO__BIE EQU CYREG_PRT3_BIE
-SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_MISO__BYP EQU CYREG_PRT3_BYP
-SD_MISO__CTL EQU CYREG_PRT3_CTL
-SD_MISO__DM0 EQU CYREG_PRT3_DM0
-SD_MISO__DM1 EQU CYREG_PRT3_DM1
-SD_MISO__DM2 EQU CYREG_PRT3_DM2
-SD_MISO__DR EQU CYREG_PRT3_DR
-SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_MISO__MASK EQU 0x02
-SD_MISO__PORT EQU 3
-SD_MISO__PRT EQU CYREG_PRT3_PRT
-SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_MISO__PS EQU CYREG_PRT3_PS
-SD_MISO__SHIFT EQU 1
-SD_MISO__SLW EQU CYREG_PRT3_SLW
+/* SCSI_In_DBx */
+SCSI_In_DBx__0__AG EQU CYREG_PRT5_AG
+SCSI_In_DBx__0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In_DBx__0__BIE EQU CYREG_PRT5_BIE
+SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In_DBx__0__BYP EQU CYREG_PRT5_BYP
+SCSI_In_DBx__0__CTL EQU CYREG_PRT5_CTL
+SCSI_In_DBx__0__DM0 EQU CYREG_PRT5_DM0
+SCSI_In_DBx__0__DM1 EQU CYREG_PRT5_DM1
+SCSI_In_DBx__0__DM2 EQU CYREG_PRT5_DM2
+SCSI_In_DBx__0__DR EQU CYREG_PRT5_DR
+SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In_DBx__0__MASK EQU 0x08
+SCSI_In_DBx__0__PC EQU CYREG_PRT5_PC3
+SCSI_In_DBx__0__PORT EQU 5
+SCSI_In_DBx__0__PRT EQU CYREG_PRT5_PRT
+SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In_DBx__0__PS EQU CYREG_PRT5_PS
+SCSI_In_DBx__0__SHIFT EQU 3
+SCSI_In_DBx__0__SLW EQU CYREG_PRT5_SLW
+SCSI_In_DBx__1__AG EQU CYREG_PRT5_AG
+SCSI_In_DBx__1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In_DBx__1__BIE EQU CYREG_PRT5_BIE
+SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In_DBx__1__BYP EQU CYREG_PRT5_BYP
+SCSI_In_DBx__1__CTL EQU CYREG_PRT5_CTL
+SCSI_In_DBx__1__DM0 EQU CYREG_PRT5_DM0
+SCSI_In_DBx__1__DM1 EQU CYREG_PRT5_DM1
+SCSI_In_DBx__1__DM2 EQU CYREG_PRT5_DM2
+SCSI_In_DBx__1__DR EQU CYREG_PRT5_DR
+SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In_DBx__1__MASK EQU 0x04
+SCSI_In_DBx__1__PC EQU CYREG_PRT5_PC2
+SCSI_In_DBx__1__PORT EQU 5
+SCSI_In_DBx__1__PRT EQU CYREG_PRT5_PRT
+SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In_DBx__1__PS EQU CYREG_PRT5_PS
+SCSI_In_DBx__1__SHIFT EQU 2
+SCSI_In_DBx__1__SLW EQU CYREG_PRT5_SLW
+SCSI_In_DBx__2__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__2__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__2__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__2__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__2__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__2__MASK EQU 0x80
+SCSI_In_DBx__2__PC EQU CYREG_PRT6_PC7
+SCSI_In_DBx__2__PORT EQU 6
+SCSI_In_DBx__2__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__2__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__2__SHIFT EQU 7
+SCSI_In_DBx__2__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__3__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__3__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__3__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__3__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__3__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__3__MASK EQU 0x40
+SCSI_In_DBx__3__PC EQU CYREG_PRT6_PC6
+SCSI_In_DBx__3__PORT EQU 6
+SCSI_In_DBx__3__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__3__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__3__SHIFT EQU 6
+SCSI_In_DBx__3__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__4__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__4__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__4__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__4__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__4__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__4__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__4__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__4__MASK EQU 0x20
+SCSI_In_DBx__4__PC EQU CYREG_PRT12_PC5
+SCSI_In_DBx__4__PORT EQU 12
+SCSI_In_DBx__4__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__4__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__4__SHIFT EQU 5
+SCSI_In_DBx__4__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__4__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__5__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__5__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__5__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__5__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__5__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__5__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__5__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__5__MASK EQU 0x10
+SCSI_In_DBx__5__PC EQU CYREG_PRT12_PC4
+SCSI_In_DBx__5__PORT EQU 12
+SCSI_In_DBx__5__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__5__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__5__SHIFT EQU 4
+SCSI_In_DBx__5__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__5__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__6__MASK EQU 0x20
+SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC5
+SCSI_In_DBx__6__PORT EQU 2
+SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__6__SHIFT EQU 5
+SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__7__MASK EQU 0x10
+SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC4
+SCSI_In_DBx__7__PORT EQU 2
+SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__7__SHIFT EQU 4
+SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB0__AG EQU CYREG_PRT5_AG
+SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In_DBx__DB0__BIE EQU CYREG_PRT5_BIE
+SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In_DBx__DB0__BYP EQU CYREG_PRT5_BYP
+SCSI_In_DBx__DB0__CTL EQU CYREG_PRT5_CTL
+SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
+SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
+SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
+SCSI_In_DBx__DB0__DR EQU CYREG_PRT5_DR
+SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In_DBx__DB0__MASK EQU 0x08
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT5_PC3
+SCSI_In_DBx__DB0__PORT EQU 5
+SCSI_In_DBx__DB0__PRT EQU CYREG_PRT5_PRT
+SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In_DBx__DB0__PS EQU CYREG_PRT5_PS
+SCSI_In_DBx__DB0__SHIFT EQU 3
+SCSI_In_DBx__DB0__SLW EQU CYREG_PRT5_SLW
+SCSI_In_DBx__DB1__AG EQU CYREG_PRT5_AG
+SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In_DBx__DB1__BIE EQU CYREG_PRT5_BIE
+SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In_DBx__DB1__BYP EQU CYREG_PRT5_BYP
+SCSI_In_DBx__DB1__CTL EQU CYREG_PRT5_CTL
+SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
+SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
+SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
+SCSI_In_DBx__DB1__DR EQU CYREG_PRT5_DR
+SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In_DBx__DB1__MASK EQU 0x04
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT5_PC2
+SCSI_In_DBx__DB1__PORT EQU 5
+SCSI_In_DBx__DB1__PRT EQU CYREG_PRT5_PRT
+SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In_DBx__DB1__PS EQU CYREG_PRT5_PS
+SCSI_In_DBx__DB1__SHIFT EQU 2
+SCSI_In_DBx__DB1__SLW EQU CYREG_PRT5_SLW
+SCSI_In_DBx__DB2__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__DB2__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__DB2__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__DB2__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__DB2__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__DB2__MASK EQU 0x80
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT6_PC7
+SCSI_In_DBx__DB2__PORT EQU 6
+SCSI_In_DBx__DB2__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__DB2__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__DB2__SHIFT EQU 7
+SCSI_In_DBx__DB2__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__DB3__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__DB3__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__DB3__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__DB3__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__DB3__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__DB3__MASK EQU 0x40
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT6_PC6
+SCSI_In_DBx__DB3__PORT EQU 6
+SCSI_In_DBx__DB3__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__DB3__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__DB3__SHIFT EQU 6
+SCSI_In_DBx__DB3__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__DB4__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__DB4__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__DB4__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__DB4__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__DB4__MASK EQU 0x20
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT12_PC5
+SCSI_In_DBx__DB4__PORT EQU 12
+SCSI_In_DBx__DB4__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__DB4__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__DB4__SHIFT EQU 5
+SCSI_In_DBx__DB4__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__DB4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__DB4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__DB4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__DB4__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__DB5__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__DB5__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__DB5__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__DB5__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__DB5__MASK EQU 0x10
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT12_PC4
+SCSI_In_DBx__DB5__PORT EQU 12
+SCSI_In_DBx__DB5__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__DB5__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__DB5__SHIFT EQU 4
+SCSI_In_DBx__DB5__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__DB5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__DB5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__DB5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__DB5__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB6__MASK EQU 0x20
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC5
+SCSI_In_DBx__DB6__PORT EQU 2
+SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB6__SHIFT EQU 5
+SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB7__MASK EQU 0x10
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC4
+SCSI_In_DBx__DB7__PORT EQU 2
+SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB7__SHIFT EQU 4
+SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW
+
+/* SD_MISO */
+SD_MISO__0__MASK EQU 0x02
+SD_MISO__0__PC EQU CYREG_PRT3_PC1
+SD_MISO__0__PORT EQU 3
+SD_MISO__0__SHIFT EQU 1
+SD_MISO__AG EQU CYREG_PRT3_AG
+SD_MISO__AMUX EQU CYREG_PRT3_AMUX
+SD_MISO__BIE EQU CYREG_PRT3_BIE
+SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_MISO__BYP EQU CYREG_PRT3_BYP
+SD_MISO__CTL EQU CYREG_PRT3_CTL
+SD_MISO__DM0 EQU CYREG_PRT3_DM0
+SD_MISO__DM1 EQU CYREG_PRT3_DM1
+SD_MISO__DM2 EQU CYREG_PRT3_DM2
+SD_MISO__DR EQU CYREG_PRT3_DR
+SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_MISO__MASK EQU 0x02
+SD_MISO__PORT EQU 3
+SD_MISO__PRT EQU CYREG_PRT3_PRT
+SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_MISO__PS EQU CYREG_PRT3_PS
+SD_MISO__SHIFT EQU 1
+SD_MISO__SLW EQU CYREG_PRT3_SLW
+
+/* SD_MOSI */
+SD_MOSI__0__MASK EQU 0x08
+SD_MOSI__0__PC EQU CYREG_PRT3_PC3
+SD_MOSI__0__PORT EQU 3
+SD_MOSI__0__SHIFT EQU 3
+SD_MOSI__AG EQU CYREG_PRT3_AG
+SD_MOSI__AMUX EQU CYREG_PRT3_AMUX
+SD_MOSI__BIE EQU CYREG_PRT3_BIE
+SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_MOSI__BYP EQU CYREG_PRT3_BYP
+SD_MOSI__CTL EQU CYREG_PRT3_CTL
+SD_MOSI__DM0 EQU CYREG_PRT3_DM0
+SD_MOSI__DM1 EQU CYREG_PRT3_DM1
+SD_MOSI__DM2 EQU CYREG_PRT3_DM2
+SD_MOSI__DR EQU CYREG_PRT3_DR
+SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_MOSI__MASK EQU 0x08
+SD_MOSI__PORT EQU 3
+SD_MOSI__PRT EQU CYREG_PRT3_PRT
+SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_MOSI__PS EQU CYREG_PRT3_PS
+SD_MOSI__SHIFT EQU 3
+SD_MOSI__SLW EQU CYREG_PRT3_SLW
+
+/* SCSI_CLK */
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
+SCSI_CLK__INDEX EQU 0x01
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SCSI_CLK__PM_ACT_MSK EQU 0x02
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SCSI_CLK__PM_STBY_MSK EQU 0x02
+
+/* SCSI_Out */
+SCSI_Out__0__AG EQU CYREG_PRT15_AG
+SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out__0__BIE EQU CYREG_PRT15_BIE
+SCSI_Out__0__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out__0__BYP EQU CYREG_PRT15_BYP
+SCSI_Out__0__CTL EQU CYREG_PRT15_CTL
+SCSI_Out__0__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out__0__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out__0__DR EQU CYREG_PRT15_DR
+SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out__0__MASK EQU 0x20
+SCSI_Out__0__PC EQU CYREG_IO_PC_PRT15_PC5
+SCSI_Out__0__PORT EQU 15
+SCSI_Out__0__PRT EQU CYREG_PRT15_PRT
+SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out__0__PS EQU CYREG_PRT15_PS
+SCSI_Out__0__SHIFT EQU 5
+SCSI_Out__0__SLW EQU CYREG_PRT15_SLW
+SCSI_Out__1__AG EQU CYREG_PRT15_AG
+SCSI_Out__1__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out__1__BIE EQU CYREG_PRT15_BIE
+SCSI_Out__1__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out__1__BYP EQU CYREG_PRT15_BYP
+SCSI_Out__1__CTL EQU CYREG_PRT15_CTL
+SCSI_Out__1__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out__1__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out__1__DR EQU CYREG_PRT15_DR
+SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out__1__MASK EQU 0x10
+SCSI_Out__1__PC EQU CYREG_IO_PC_PRT15_PC4
+SCSI_Out__1__PORT EQU 15
+SCSI_Out__1__PRT EQU CYREG_PRT15_PRT
+SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out__1__PS EQU CYREG_PRT15_PS
+SCSI_Out__1__SHIFT EQU 4
+SCSI_Out__1__SLW EQU CYREG_PRT15_SLW
+SCSI_Out__2__AG EQU CYREG_PRT6_AG
+SCSI_Out__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__2__DR EQU CYREG_PRT6_DR
+SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__2__MASK EQU 0x02
+SCSI_Out__2__PC EQU CYREG_PRT6_PC1
+SCSI_Out__2__PORT EQU 6
+SCSI_Out__2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__2__PS EQU CYREG_PRT6_PS
+SCSI_Out__2__SHIFT EQU 1
+SCSI_Out__2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__3__AG EQU CYREG_PRT6_AG
+SCSI_Out__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__3__DR EQU CYREG_PRT6_DR
+SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__3__MASK EQU 0x01
+SCSI_Out__3__PC EQU CYREG_PRT6_PC0
+SCSI_Out__3__PORT EQU 6
+SCSI_Out__3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__3__PS EQU CYREG_PRT6_PS
+SCSI_Out__3__SHIFT EQU 0
+SCSI_Out__3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__4__AG EQU CYREG_PRT4_AG
+SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__4__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__4__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__4__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__4__DR EQU CYREG_PRT4_DR
+SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__4__MASK EQU 0x20
+SCSI_Out__4__PC EQU CYREG_PRT4_PC5
+SCSI_Out__4__PORT EQU 4
+SCSI_Out__4__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__4__PS EQU CYREG_PRT4_PS
+SCSI_Out__4__SHIFT EQU 5
+SCSI_Out__4__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__5__AG EQU CYREG_PRT4_AG
+SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__5__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__5__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__5__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__5__DR EQU CYREG_PRT4_DR
+SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__5__MASK EQU 0x10
+SCSI_Out__5__PC EQU CYREG_PRT4_PC4
+SCSI_Out__5__PORT EQU 4
+SCSI_Out__5__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__5__PS EQU CYREG_PRT4_PS
+SCSI_Out__5__SHIFT EQU 4
+SCSI_Out__5__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__6__AG EQU CYREG_PRT0_AG
+SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__6__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__6__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__6__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__6__DR EQU CYREG_PRT0_DR
+SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__6__MASK EQU 0x80
+SCSI_Out__6__PC EQU CYREG_PRT0_PC7
+SCSI_Out__6__PORT EQU 0
+SCSI_Out__6__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__6__PS EQU CYREG_PRT0_PS
+SCSI_Out__6__SHIFT EQU 7
+SCSI_Out__6__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__7__AG EQU CYREG_PRT0_AG
+SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__7__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__7__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__7__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__7__DR EQU CYREG_PRT0_DR
+SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__7__MASK EQU 0x40
+SCSI_Out__7__PC EQU CYREG_PRT0_PC6
+SCSI_Out__7__PORT EQU 0
+SCSI_Out__7__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__7__PS EQU CYREG_PRT0_PS
+SCSI_Out__7__SHIFT EQU 6
+SCSI_Out__7__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__8__AG EQU CYREG_PRT0_AG
+SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__8__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__8__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__8__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__8__DR EQU CYREG_PRT0_DR
+SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__8__MASK EQU 0x08
+SCSI_Out__8__PC EQU CYREG_PRT0_PC3
+SCSI_Out__8__PORT EQU 0
+SCSI_Out__8__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__8__PS EQU CYREG_PRT0_PS
+SCSI_Out__8__SHIFT EQU 3
+SCSI_Out__8__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__9__AG EQU CYREG_PRT0_AG
+SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__9__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__9__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__9__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__9__DR EQU CYREG_PRT0_DR
+SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__9__MASK EQU 0x04
+SCSI_Out__9__PC EQU CYREG_PRT0_PC2
+SCSI_Out__9__PORT EQU 0
+SCSI_Out__9__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__9__PS EQU CYREG_PRT0_PS
+SCSI_Out__9__SHIFT EQU 2
+SCSI_Out__9__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__ACK__AG EQU CYREG_PRT6_AG
+SCSI_Out__ACK__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__ACK__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__ACK__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__ACK__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__ACK__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__ACK__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__ACK__DR EQU CYREG_PRT6_DR
+SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__ACK__MASK EQU 0x01
+SCSI_Out__ACK__PC EQU CYREG_PRT6_PC0
+SCSI_Out__ACK__PORT EQU 6
+SCSI_Out__ACK__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__ACK__PS EQU CYREG_PRT6_PS
+SCSI_Out__ACK__SHIFT EQU 0
+SCSI_Out__ACK__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__ATN__AG EQU CYREG_PRT15_AG
+SCSI_Out__ATN__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out__ATN__BIE EQU CYREG_PRT15_BIE
+SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out__ATN__BYP EQU CYREG_PRT15_BYP
+SCSI_Out__ATN__CTL EQU CYREG_PRT15_CTL
+SCSI_Out__ATN__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out__ATN__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out__ATN__DR EQU CYREG_PRT15_DR
+SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out__ATN__MASK EQU 0x10
+SCSI_Out__ATN__PC EQU CYREG_IO_PC_PRT15_PC4
+SCSI_Out__ATN__PORT EQU 15
+SCSI_Out__ATN__PRT EQU CYREG_PRT15_PRT
+SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out__ATN__PS EQU CYREG_PRT15_PS
+SCSI_Out__ATN__SHIFT EQU 4
+SCSI_Out__ATN__SLW EQU CYREG_PRT15_SLW
+SCSI_Out__BSY__AG EQU CYREG_PRT6_AG
+SCSI_Out__BSY__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__BSY__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__BSY__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__BSY__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__BSY__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__BSY__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__BSY__DR EQU CYREG_PRT6_DR
+SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__BSY__MASK EQU 0x02
+SCSI_Out__BSY__PC EQU CYREG_PRT6_PC1
+SCSI_Out__BSY__PORT EQU 6
+SCSI_Out__BSY__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__BSY__PS EQU CYREG_PRT6_PS
+SCSI_Out__BSY__SHIFT EQU 1
+SCSI_Out__BSY__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__CD_raw__MASK EQU 0x40
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC6
+SCSI_Out__CD_raw__PORT EQU 0
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__CD_raw__SHIFT EQU 6
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT15_AG
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT15_BIE
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT15_BYP
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT15_CTL
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out__DBP_raw__MASK EQU 0x20
+SCSI_Out__DBP_raw__PC EQU CYREG_IO_PC_PRT15_PC5
+SCSI_Out__DBP_raw__PORT EQU 15
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT15_PRT
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT15_PS
+SCSI_Out__DBP_raw__SHIFT EQU 5
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT15_SLW
+SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__IO_raw__MASK EQU 0x04
+SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC2
+SCSI_Out__IO_raw__PORT EQU 0
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__IO_raw__SHIFT EQU 2
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT4_AG
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT4_DR
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__MSG_raw__MASK EQU 0x10
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT4_PC4
+SCSI_Out__MSG_raw__PORT EQU 4
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT4_PS
+SCSI_Out__MSG_raw__SHIFT EQU 4
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__REQ__AG EQU CYREG_PRT0_AG
+SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__REQ__DR EQU CYREG_PRT0_DR
+SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__REQ__MASK EQU 0x08
+SCSI_Out__REQ__PC EQU CYREG_PRT0_PC3
+SCSI_Out__REQ__PORT EQU 0
+SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__REQ__PS EQU CYREG_PRT0_PS
+SCSI_Out__REQ__SHIFT EQU 3
+SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__RST__AG EQU CYREG_PRT4_AG
+SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__RST__DR EQU CYREG_PRT4_DR
+SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__RST__MASK EQU 0x20
+SCSI_Out__RST__PC EQU CYREG_PRT4_PC5
+SCSI_Out__RST__PORT EQU 4
+SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__RST__PS EQU CYREG_PRT4_PS
+SCSI_Out__RST__SHIFT EQU 5
+SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__SEL__AG EQU CYREG_PRT0_AG
+SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
+SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__SEL__MASK EQU 0x80
+SCSI_Out__SEL__PC EQU CYREG_PRT0_PC7
+SCSI_Out__SEL__PORT EQU 0
+SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
+SCSI_Out__SEL__SHIFT EQU 7
+SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
+
+/* SCSI_Out_Bits */
+SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
+SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
+SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
+SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
+SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
+SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3
+SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10
+SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4
+SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20
+SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5
+SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
+SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
+SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
+SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
+
+/* SCSI_Out_Ctl */
+SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
+
+/* SCSI_Out_DBx */
+SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__0__MASK EQU 0x02
+SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1
+SCSI_Out_DBx__0__PORT EQU 5
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__0__SHIFT EQU 1
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__1__MASK EQU 0x01
+SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0
+SCSI_Out_DBx__1__PORT EQU 5
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__1__SHIFT EQU 0
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__2__MASK EQU 0x20
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__2__PORT EQU 6
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__2__SHIFT EQU 5
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__3__MASK EQU 0x10
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4
+SCSI_Out_DBx__3__PORT EQU 6
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__3__SHIFT EQU 4
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__4__MASK EQU 0x80
+SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__4__PORT EQU 2
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__4__SHIFT EQU 7
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__5__MASK EQU 0x40
+SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6
+SCSI_Out_DBx__5__PORT EQU 2
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__5__SHIFT EQU 6
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__6__MASK EQU 0x08
+SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__6__PORT EQU 2
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__6__SHIFT EQU 3
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__7__MASK EQU 0x04
+SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2
+SCSI_Out_DBx__7__PORT EQU 2
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__7__SHIFT EQU 2
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__DB0__MASK EQU 0x02
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1
+SCSI_Out_DBx__DB0__PORT EQU 5
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__DB0__SHIFT EQU 1
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__DB1__MASK EQU 0x01
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0
+SCSI_Out_DBx__DB1__PORT EQU 5
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__DB1__SHIFT EQU 0
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB2__MASK EQU 0x20
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__DB2__PORT EQU 6
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB2__SHIFT EQU 5
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB3__MASK EQU 0x10
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4
+SCSI_Out_DBx__DB3__PORT EQU 6
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB3__SHIFT EQU 4
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB4__MASK EQU 0x80
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__DB4__PORT EQU 2
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB4__SHIFT EQU 7
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB5__MASK EQU 0x40
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6
+SCSI_Out_DBx__DB5__PORT EQU 2
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB5__SHIFT EQU 6
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB6__MASK EQU 0x08
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__DB6__PORT EQU 2
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB6__SHIFT EQU 3
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB7__MASK EQU 0x04
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2
+SCSI_Out_DBx__DB7__PORT EQU 2
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB7__SHIFT EQU 2
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
+
+/* SD_RX_DMA */
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SD_RX_DMA__DRQ_NUMBER EQU 2
+SD_RX_DMA__NUMBEROF_TDS EQU 0
+SD_RX_DMA__PRIORITY EQU 2
+SD_RX_DMA__TERMIN_EN EQU 0
+SD_RX_DMA__TERMIN_SEL EQU 0
+SD_RX_DMA__TERMOUT0_EN EQU 1
+SD_RX_DMA__TERMOUT0_SEL EQU 2
+SD_RX_DMA__TERMOUT1_EN EQU 0
+SD_RX_DMA__TERMOUT1_SEL EQU 0
+
+/* SD_RX_DMA_COMPLETE */
+SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
+SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
+SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* SD_TX_DMA */
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SD_TX_DMA__DRQ_NUMBER EQU 3
+SD_TX_DMA__NUMBEROF_TDS EQU 0
+SD_TX_DMA__PRIORITY EQU 2
+SD_TX_DMA__TERMIN_EN EQU 0
+SD_TX_DMA__TERMIN_SEL EQU 0
+SD_TX_DMA__TERMOUT0_EN EQU 1
+SD_TX_DMA__TERMOUT0_SEL EQU 3
+SD_TX_DMA__TERMOUT1_EN EQU 0
+SD_TX_DMA__TERMOUT1_SEL EQU 0
+
+/* SD_TX_DMA_COMPLETE */
+SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5
+SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
+SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* SCSI_Noise */
+SCSI_Noise__0__AG EQU CYREG_PRT2_AG
+SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE
+SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP
+SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL
+SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0
+SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1
+SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2
+SCSI_Noise__0__DR EQU CYREG_PRT2_DR
+SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Noise__0__MASK EQU 0x01
+SCSI_Noise__0__PC EQU CYREG_PRT2_PC0
+SCSI_Noise__0__PORT EQU 2
+SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT
+SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Noise__0__PS EQU CYREG_PRT2_PS
+SCSI_Noise__0__SHIFT EQU 0
+SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW
+SCSI_Noise__1__AG EQU CYREG_PRT6_AG
+SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__1__DR EQU CYREG_PRT6_DR
+SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__1__MASK EQU 0x08
+SCSI_Noise__1__PC EQU CYREG_PRT6_PC3
+SCSI_Noise__1__PORT EQU 6
+SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__1__PS EQU CYREG_PRT6_PS
+SCSI_Noise__1__SHIFT EQU 3
+SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__2__AG EQU CYREG_PRT4_AG
+SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__2__DR EQU CYREG_PRT4_DR
+SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__2__MASK EQU 0x08
+SCSI_Noise__2__PC EQU CYREG_PRT4_PC3
+SCSI_Noise__2__PORT EQU 4
+SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__2__PS EQU CYREG_PRT4_PS
+SCSI_Noise__2__SHIFT EQU 3
+SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW
+SCSI_Noise__3__AG EQU CYREG_PRT4_AG
+SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__3__DR EQU CYREG_PRT4_DR
+SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__3__MASK EQU 0x80
+SCSI_Noise__3__PC EQU CYREG_PRT4_PC7
+SCSI_Noise__3__PORT EQU 4
+SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__3__PS EQU CYREG_PRT4_PS
+SCSI_Noise__3__SHIFT EQU 7
+SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW
+SCSI_Noise__4__AG EQU CYREG_PRT6_AG
+SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__4__DR EQU CYREG_PRT6_DR
+SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__4__MASK EQU 0x04
+SCSI_Noise__4__PC EQU CYREG_PRT6_PC2
+SCSI_Noise__4__PORT EQU 6
+SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__4__PS EQU CYREG_PRT6_PS
+SCSI_Noise__4__SHIFT EQU 2
+SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG
+SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR
+SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__ACK__MASK EQU 0x04
+SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2
+SCSI_Noise__ACK__PORT EQU 6
+SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS
+SCSI_Noise__ACK__SHIFT EQU 2
+SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG
+SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE
+SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP
+SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL
+SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0
+SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1
+SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2
+SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR
+SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Noise__ATN__MASK EQU 0x01
+SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0
+SCSI_Noise__ATN__PORT EQU 2
+SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT
+SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS
+SCSI_Noise__ATN__SHIFT EQU 0
+SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW
+SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG
+SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR
+SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__BSY__MASK EQU 0x08
+SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3
+SCSI_Noise__BSY__PORT EQU 6
+SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS
+SCSI_Noise__BSY__SHIFT EQU 3
+SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__RST__AG EQU CYREG_PRT4_AG
+SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__RST__DR EQU CYREG_PRT4_DR
+SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__RST__MASK EQU 0x80
+SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7
+SCSI_Noise__RST__PORT EQU 4
+SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__RST__PS EQU CYREG_PRT4_PS
+SCSI_Noise__RST__SHIFT EQU 7
+SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW
+SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG
+SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR
+SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__SEL__MASK EQU 0x08
+SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3
+SCSI_Noise__SEL__PORT EQU 4
+SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS
+SCSI_Noise__SEL__SHIFT EQU 3
+SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW
+
+/* scsiTarget */
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_StatusReg__0__MASK EQU 0x01
+scsiTarget_StatusReg__0__POS EQU 0
+scsiTarget_StatusReg__1__MASK EQU 0x02
+scsiTarget_StatusReg__1__POS EQU 1
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST
+scsiTarget_StatusReg__2__MASK EQU 0x04
+scsiTarget_StatusReg__2__POS EQU 2
+scsiTarget_StatusReg__3__MASK EQU 0x08
+scsiTarget_StatusReg__3__POS EQU 3
+scsiTarget_StatusReg__4__MASK EQU 0x10
+scsiTarget_StatusReg__4__POS EQU 4
+scsiTarget_StatusReg__MASK EQU 0x1F
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST
-/* SD_MOSI */
-SD_MOSI__0__MASK EQU 0x08
-SD_MOSI__0__PC EQU CYREG_PRT3_PC3
-SD_MOSI__0__PORT EQU 3
-SD_MOSI__0__SHIFT EQU 3
-SD_MOSI__AG EQU CYREG_PRT3_AG
-SD_MOSI__AMUX EQU CYREG_PRT3_AMUX
-SD_MOSI__BIE EQU CYREG_PRT3_BIE
-SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_MOSI__BYP EQU CYREG_PRT3_BYP
-SD_MOSI__CTL EQU CYREG_PRT3_CTL
-SD_MOSI__DM0 EQU CYREG_PRT3_DM0
-SD_MOSI__DM1 EQU CYREG_PRT3_DM1
-SD_MOSI__DM2 EQU CYREG_PRT3_DM2
-SD_MOSI__DR EQU CYREG_PRT3_DR
-SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_MOSI__MASK EQU 0x08
-SD_MOSI__PORT EQU 3
-SD_MOSI__PRT EQU CYREG_PRT3_PRT
-SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_MOSI__PS EQU CYREG_PRT3_PS
-SD_MOSI__SHIFT EQU 3
-SD_MOSI__SLW EQU CYREG_PRT3_SLW
+/* Debug_Timer_Interrupt */
+Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+Debug_Timer_Interrupt__INTC_MASK EQU 0x02
+Debug_Timer_Interrupt__INTC_NUMBER EQU 1
+Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
+Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* Debug_Timer_TimerHW */
+Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
+Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
+Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
+Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
+Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
+Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
+Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
+Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0
+Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1
+Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
+Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01
+Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
+Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01
+Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0
+Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1
+Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0
+
+/* SCSI_RX_DMA */
+SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SCSI_RX_DMA__DRQ_NUMBER EQU 0
+SCSI_RX_DMA__NUMBEROF_TDS EQU 0
+SCSI_RX_DMA__PRIORITY EQU 2
+SCSI_RX_DMA__TERMIN_EN EQU 0
+SCSI_RX_DMA__TERMIN_SEL EQU 0
+SCSI_RX_DMA__TERMOUT0_EN EQU 1
+SCSI_RX_DMA__TERMOUT0_SEL EQU 0
+SCSI_RX_DMA__TERMOUT1_EN EQU 0
+SCSI_RX_DMA__TERMOUT1_SEL EQU 0
+
+/* SCSI_RX_DMA_COMPLETE */
+SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
+SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* SCSI_TX_DMA */
+SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SCSI_TX_DMA__DRQ_NUMBER EQU 1
+SCSI_TX_DMA__NUMBEROF_TDS EQU 0
+SCSI_TX_DMA__PRIORITY EQU 2
+SCSI_TX_DMA__TERMIN_EN EQU 0
+SCSI_TX_DMA__TERMIN_SEL EQU 0
+SCSI_TX_DMA__TERMOUT0_EN EQU 1
+SCSI_TX_DMA__TERMOUT0_SEL EQU 1
+SCSI_TX_DMA__TERMOUT1_EN EQU 0
+SCSI_TX_DMA__TERMOUT1_SEL EQU 0
+
+/* SCSI_TX_DMA_COMPLETE */
+SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
+SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* SD_Data_Clk */
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
+SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
+SD_Data_Clk__INDEX EQU 0x00
+SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SD_Data_Clk__PM_ACT_MSK EQU 0x01
+SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SD_Data_Clk__PM_STBY_MSK EQU 0x01
-/* EXTLED */
-EXTLED__0__MASK EQU 0x01
-EXTLED__0__PC EQU CYREG_PRT0_PC0
-EXTLED__0__PORT EQU 0
-EXTLED__0__SHIFT EQU 0
-EXTLED__AG EQU CYREG_PRT0_AG
-EXTLED__AMUX EQU CYREG_PRT0_AMUX
-EXTLED__BIE EQU CYREG_PRT0_BIE
-EXTLED__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-EXTLED__BYP EQU CYREG_PRT0_BYP
-EXTLED__CTL EQU CYREG_PRT0_CTL
-EXTLED__DM0 EQU CYREG_PRT0_DM0
-EXTLED__DM1 EQU CYREG_PRT0_DM1
-EXTLED__DM2 EQU CYREG_PRT0_DM2
-EXTLED__DR EQU CYREG_PRT0_DR
-EXTLED__INP_DIS EQU CYREG_PRT0_INP_DIS
-EXTLED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-EXTLED__LCD_EN EQU CYREG_PRT0_LCD_EN
-EXTLED__MASK EQU 0x01
-EXTLED__PORT EQU 0
-EXTLED__PRT EQU CYREG_PRT0_PRT
-EXTLED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-EXTLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-EXTLED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-EXTLED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-EXTLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-EXTLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-EXTLED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-EXTLED__PS EQU CYREG_PRT0_PS
-EXTLED__SHIFT EQU 0
-EXTLED__SLW EQU CYREG_PRT0_SLW
+/* timer_clock */
+timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
+timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
+timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
+timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
+timer_clock__INDEX EQU 0x02
+timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+timer_clock__PM_ACT_MSK EQU 0x04
+timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+timer_clock__PM_STBY_MSK EQU 0x04
-/* SD_SCK */
-SD_SCK__0__MASK EQU 0x04
-SD_SCK__0__PC EQU CYREG_PRT3_PC2
-SD_SCK__0__PORT EQU 3
-SD_SCK__0__SHIFT EQU 2
-SD_SCK__AG EQU CYREG_PRT3_AG
-SD_SCK__AMUX EQU CYREG_PRT3_AMUX
-SD_SCK__BIE EQU CYREG_PRT3_BIE
-SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_SCK__BYP EQU CYREG_PRT3_BYP
-SD_SCK__CTL EQU CYREG_PRT3_CTL
-SD_SCK__DM0 EQU CYREG_PRT3_DM0
-SD_SCK__DM1 EQU CYREG_PRT3_DM1
-SD_SCK__DM2 EQU CYREG_PRT3_DM2
-SD_SCK__DR EQU CYREG_PRT3_DR
-SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_SCK__MASK EQU 0x04
-SD_SCK__PORT EQU 3
-SD_SCK__PRT EQU CYREG_PRT3_PRT
-SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_SCK__PS EQU CYREG_PRT3_PS
-SD_SCK__SHIFT EQU 2
-SD_SCK__SLW EQU CYREG_PRT3_SLW
+/* SCSI_RST_ISR */
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_RST_ISR__INTC_MASK EQU 0x04
+SCSI_RST_ISR__INTC_NUMBER EQU 2
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-/* SD_CD */
-SD_CD__0__MASK EQU 0x20
-SD_CD__0__PC EQU CYREG_PRT3_PC5
-SD_CD__0__PORT EQU 3
-SD_CD__0__SHIFT EQU 5
-SD_CD__AG EQU CYREG_PRT3_AG
-SD_CD__AMUX EQU CYREG_PRT3_AMUX
-SD_CD__BIE EQU CYREG_PRT3_BIE
-SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_CD__BYP EQU CYREG_PRT3_BYP
-SD_CD__CTL EQU CYREG_PRT3_CTL
-SD_CD__DM0 EQU CYREG_PRT3_DM0
-SD_CD__DM1 EQU CYREG_PRT3_DM1
-SD_CD__DM2 EQU CYREG_PRT3_DM2
-SD_CD__DR EQU CYREG_PRT3_DR
-SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_CD__MASK EQU 0x20
-SD_CD__PORT EQU 3
-SD_CD__PRT EQU CYREG_PRT3_PRT
-SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_CD__PS EQU CYREG_PRT3_PS
-SD_CD__SHIFT EQU 5
-SD_CD__SLW EQU CYREG_PRT3_SLW
+/* SCSI_Filtered */
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST
-/* SD_CS */
-SD_CS__0__MASK EQU 0x10
-SD_CS__0__PC EQU CYREG_PRT3_PC4
-SD_CS__0__PORT EQU 3
-SD_CS__0__SHIFT EQU 4
-SD_CS__AG EQU CYREG_PRT3_AG
-SD_CS__AMUX EQU CYREG_PRT3_AMUX
-SD_CS__BIE EQU CYREG_PRT3_BIE
-SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_CS__BYP EQU CYREG_PRT3_BYP
-SD_CS__CTL EQU CYREG_PRT3_CTL
-SD_CS__DM0 EQU CYREG_PRT3_DM0
-SD_CS__DM1 EQU CYREG_PRT3_DM1
-SD_CS__DM2 EQU CYREG_PRT3_DM2
-SD_CS__DR EQU CYREG_PRT3_DR
-SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_CS__MASK EQU 0x10
-SD_CS__PORT EQU 3
-SD_CS__PRT EQU CYREG_PRT3_PRT
-SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_CS__PS EQU CYREG_PRT3_PS
-SD_CS__SHIFT EQU 4
-SD_CS__SLW EQU CYREG_PRT3_SLW
+/* SCSI_CTL_PHASE */
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
-/* LED1 */
-LED1__0__MASK EQU 0x02
-LED1__0__PC EQU CYREG_PRT0_PC1
-LED1__0__PORT EQU 0
-LED1__0__SHIFT EQU 1
-LED1__AG EQU CYREG_PRT0_AG
-LED1__AMUX EQU CYREG_PRT0_AMUX
-LED1__BIE EQU CYREG_PRT0_BIE
-LED1__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-LED1__BYP EQU CYREG_PRT0_BYP
-LED1__CTL EQU CYREG_PRT0_CTL
-LED1__DM0 EQU CYREG_PRT0_DM0
-LED1__DM1 EQU CYREG_PRT0_DM1
-LED1__DM2 EQU CYREG_PRT0_DM2
-LED1__DR EQU CYREG_PRT0_DR
-LED1__INP_DIS EQU CYREG_PRT0_INP_DIS
-LED1__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-LED1__LCD_EN EQU CYREG_PRT0_LCD_EN
-LED1__MASK EQU 0x02
-LED1__PORT EQU 0
-LED1__PRT EQU CYREG_PRT0_PRT
-LED1__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-LED1__PS EQU CYREG_PRT0_PS
-LED1__SHIFT EQU 1
-LED1__SLW EQU CYREG_PRT0_SLW
+/* SCSI_Parity_Error */
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB03_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB03_ST
/* Miscellaneous */
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
-CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
-CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
-CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
-CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
-CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
-CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
-CYDEV_CHIP_MEMBER_5B EQU 4
-CYDEV_CHIP_FAMILY_PSOC5 EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 4
-CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP
BCLK__BUS_CLK__HZ EQU 50000000
BCLK__BUS_CLK__KHZ EQU 50000
BCLK__BUS_CLK__MHZ EQU 50
-CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 3
-CYDEV_CHIP_DIE_PSOC4A EQU 2
+CYDEV_CHIP_DIE_PANTHER EQU 6
+CYDEV_CHIP_DIE_PSOC4A EQU 3
+CYDEV_CHIP_DIE_PSOC5LP EQU 5
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
+CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
CYDEV_CHIP_JTAG_ID EQU 0x2E133069
CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 2
-CYDEV_CHIP_MEMBER_5A EQU 3
+CYDEV_CHIP_MEMBER_4A EQU 3
+CYDEV_CHIP_MEMBER_4D EQU 2
+CYDEV_CHIP_MEMBER_4F EQU 4
+CYDEV_CHIP_MEMBER_5A EQU 6
+CYDEV_CHIP_MEMBER_5B EQU 5
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
+CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
+CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
+CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
+CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
+CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
+CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
+CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
+CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
+CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
+CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
+CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
+CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5B_ES0 EQU 0
+CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION
-CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
-CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
-CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
-CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
-CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
-CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
-CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
+CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
+CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
+CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
+CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_DMA EQU 0
CYDEV_CONFIGURATION_ECC EQU 0
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
+CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
-CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
-CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
-CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
+CYDEV_DEBUG_ENABLE_MASK EQU 0x20
+CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
CYDEV_DEBUGGING_DPS_SWD EQU 2
+CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
+CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DEBUGGING_XRES EQU 0
-CYDEV_DEBUG_ENABLE_MASK EQU 0x20
-CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
CYDEV_ECC_ENABLE EQU 0
-CYDEV_HEAP_SIZE EQU 0x1000
+CYDEV_HEAP_SIZE EQU 0x0400
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
CYDEV_INTR_RISING EQU 0x0000003E
CYDEV_PROJ_TYPE EQU 2
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_PROTECTION_ENABLE EQU 0
-CYDEV_STACK_SIZE EQU 0x4000
+CYDEV_STACK_SIZE EQU 0x1000
CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1
CYDEV_USE_BUNDLED_CMSIS EQU 1
CYDEV_VARIABLE_VDDA EQU 0
CYDEV_VDDIO1_MV EQU 5000
CYDEV_VDDIO2_MV EQU 5000
CYDEV_VDDIO3_MV EQU 3300
-CYDEV_VIO0 EQU 5
CYDEV_VIO0_MV EQU 5000
-CYDEV_VIO1 EQU 5
CYDEV_VIO1_MV EQU 5000
-CYDEV_VIO2 EQU 5
CYDEV_VIO2_MV EQU 5000
CYDEV_VIO3_MV EQU 3300
+CYIPBLOCK_ARM_CM3_VERSION EQU 0
+CYIPBLOCK_P3_ANAIF_VERSION EQU 0
+CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0
+CYIPBLOCK_P3_COMP_VERSION EQU 0
+CYIPBLOCK_P3_DMA_VERSION EQU 0
+CYIPBLOCK_P3_DRQ_VERSION EQU 0
+CYIPBLOCK_P3_EMIF_VERSION EQU 0
+CYIPBLOCK_P3_I2C_VERSION EQU 0
+CYIPBLOCK_P3_LCD_VERSION EQU 0
+CYIPBLOCK_P3_LPF_VERSION EQU 0
+CYIPBLOCK_P3_PM_VERSION EQU 0
+CYIPBLOCK_P3_TIMER_VERSION EQU 0
+CYIPBLOCK_P3_USB_VERSION EQU 0
+CYIPBLOCK_P3_VIDAC_VERSION EQU 0
+CYIPBLOCK_P3_VREF_VERSION EQU 0
+CYIPBLOCK_S8_GPIO_VERSION EQU 0
+CYIPBLOCK_S8_IRQ_VERSION EQU 0
+CYIPBLOCK_S8_SAR_VERSION EQU 0
+CYIPBLOCK_S8_SIO_VERSION EQU 0
+CYIPBLOCK_S8_UDB_VERSION EQU 0
DMA_CHANNELS_USED__MASK0 EQU 0x0000000F
CYDEV_BOOTLOADER_ENABLE EQU 0
GET cydevicerv.inc
GET cydevicerv_trm.inc
-; Debug_Timer_Interrupt
-Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-Debug_Timer_Interrupt__INTC_MASK EQU 0x02
-Debug_Timer_Interrupt__INTC_NUMBER EQU 1
-Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7
-Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
-Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SCSI_RX_DMA_COMPLETE
-SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01
-SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
-SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SCSI_TX_DMA_COMPLETE
-SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08
-SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
-SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; Debug_Timer_TimerHW
-Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
-Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
-Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
-Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
-Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
-Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
-Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
-Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0
-Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1
-Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
-Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01
-Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
-Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01
-Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0
-Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1
-Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0
+; LED1
+LED1__0__MASK EQU 0x02
+LED1__0__PC EQU CYREG_PRT0_PC1
+LED1__0__PORT EQU 0
+LED1__0__SHIFT EQU 1
+LED1__AG EQU CYREG_PRT0_AG
+LED1__AMUX EQU CYREG_PRT0_AMUX
+LED1__BIE EQU CYREG_PRT0_BIE
+LED1__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+LED1__BYP EQU CYREG_PRT0_BYP
+LED1__CTL EQU CYREG_PRT0_CTL
+LED1__DM0 EQU CYREG_PRT0_DM0
+LED1__DM1 EQU CYREG_PRT0_DM1
+LED1__DM2 EQU CYREG_PRT0_DM2
+LED1__DR EQU CYREG_PRT0_DR
+LED1__INP_DIS EQU CYREG_PRT0_INP_DIS
+LED1__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+LED1__LCD_EN EQU CYREG_PRT0_LCD_EN
+LED1__MASK EQU 0x02
+LED1__PORT EQU 0
+LED1__PRT EQU CYREG_PRT0_PRT
+LED1__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+LED1__PS EQU CYREG_PRT0_PS
+LED1__SHIFT EQU 1
+LED1__SLW EQU CYREG_PRT0_SLW
-; SD_RX_DMA_COMPLETE
-SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
-SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
-SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
-SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; SD_CD
+SD_CD__0__MASK EQU 0x20
+SD_CD__0__PC EQU CYREG_PRT3_PC5
+SD_CD__0__PORT EQU 3
+SD_CD__0__SHIFT EQU 5
+SD_CD__AG EQU CYREG_PRT3_AG
+SD_CD__AMUX EQU CYREG_PRT3_AMUX
+SD_CD__BIE EQU CYREG_PRT3_BIE
+SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_CD__BYP EQU CYREG_PRT3_BYP
+SD_CD__CTL EQU CYREG_PRT3_CTL
+SD_CD__DM0 EQU CYREG_PRT3_DM0
+SD_CD__DM1 EQU CYREG_PRT3_DM1
+SD_CD__DM2 EQU CYREG_PRT3_DM2
+SD_CD__DR EQU CYREG_PRT3_DR
+SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_CD__MASK EQU 0x20
+SD_CD__PORT EQU 3
+SD_CD__PRT EQU CYREG_PRT3_PRT
+SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_CD__PS EQU CYREG_PRT3_PS
+SD_CD__SHIFT EQU 5
+SD_CD__SLW EQU CYREG_PRT3_SLW
-; SD_TX_DMA_COMPLETE
-SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20
-SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5
-SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
-SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
-SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; SD_CS
+SD_CS__0__MASK EQU 0x10
+SD_CS__0__PC EQU CYREG_PRT3_PC4
+SD_CS__0__PORT EQU 3
+SD_CS__0__SHIFT EQU 4
+SD_CS__AG EQU CYREG_PRT3_AG
+SD_CS__AMUX EQU CYREG_PRT3_AMUX
+SD_CS__BIE EQU CYREG_PRT3_BIE
+SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_CS__BYP EQU CYREG_PRT3_BYP
+SD_CS__CTL EQU CYREG_PRT3_CTL
+SD_CS__DM0 EQU CYREG_PRT3_DM0
+SD_CS__DM1 EQU CYREG_PRT3_DM1
+SD_CS__DM2 EQU CYREG_PRT3_DM2
+SD_CS__DR EQU CYREG_PRT3_DR
+SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_CS__MASK EQU 0x10
+SD_CS__PORT EQU 3
+SD_CS__PRT EQU CYREG_PRT3_PRT
+SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_CS__PS EQU CYREG_PRT3_PS
+SD_CS__SHIFT EQU 4
+SD_CS__SLW EQU CYREG_PRT3_SLW
-; SCSI_Parity_Error
-SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
-SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
+; USBFS_arb_int
+USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_arb_int__INTC_MASK EQU 0x400000
+USBFS_arb_int__INTC_NUMBER EQU 22
+USBFS_arb_int__INTC_PRIOR_NUM EQU 7
+USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
+USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; USBFS_bus_reset
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-; SCSI_CTL_PHASE
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
-SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
-SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
+; USBFS_Dm
+USBFS_Dm__0__MASK EQU 0x80
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
+USBFS_Dm__0__PORT EQU 15
+USBFS_Dm__0__SHIFT EQU 7
+USBFS_Dm__AG EQU CYREG_PRT15_AG
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dm__DR EQU CYREG_PRT15_DR
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dm__MASK EQU 0x80
+USBFS_Dm__PORT EQU 15
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dm__PS EQU CYREG_PRT15_PS
+USBFS_Dm__SHIFT EQU 7
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW
-; SCSI_Filtered
-SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
-SCSI_Filtered_sts_sts_reg__0__POS EQU 0
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST
-SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
-SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
-SCSI_Filtered_sts_sts_reg__2__POS EQU 2
-SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
-SCSI_Filtered_sts_sts_reg__3__POS EQU 3
-SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
-SCSI_Filtered_sts_sts_reg__4__POS EQU 4
-SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB00_MSK
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB00_ST
+; USBFS_Dp
+USBFS_Dp__0__MASK EQU 0x40
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
+USBFS_Dp__0__PORT EQU 15
+USBFS_Dp__0__SHIFT EQU 6
+USBFS_Dp__AG EQU CYREG_PRT15_AG
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dp__DR EQU CYREG_PRT15_DR
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dp__MASK EQU 0x40
+USBFS_Dp__PORT EQU 15
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dp__PS EQU CYREG_PRT15_PS
+USBFS_Dp__SHIFT EQU 6
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
-; SCSI_Out_Bits
-SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
-SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
-SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
-SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
-SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3
-SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10
-SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4
-SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20
-SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5
-SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
-SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
-SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
-SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+; USBFS_dp_int
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_dp_int__INTC_MASK EQU 0x1000
+USBFS_dp_int__INTC_NUMBER EQU 12
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-; USBFS_arb_int
-USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_arb_int__INTC_MASK EQU 0x400000
-USBFS_arb_int__INTC_NUMBER EQU 22
-USBFS_arb_int__INTC_PRIOR_NUM EQU 7
-USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22
-USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; USBFS_ep_0
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_0__INTC_MASK EQU 0x1000000
+USBFS_ep_0__INTC_NUMBER EQU 24
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_1
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_1__INTC_MASK EQU 0x40
+USBFS_ep_1__INTC_NUMBER EQU 6
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_2
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_2__INTC_MASK EQU 0x80
+USBFS_ep_2__INTC_NUMBER EQU 7
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_3
+USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_3__INTC_MASK EQU 0x100
+USBFS_ep_3__INTC_NUMBER EQU 8
+USBFS_ep_3__INTC_PRIOR_NUM EQU 7
+USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
+USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_4
+USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_4__INTC_MASK EQU 0x200
+USBFS_ep_4__INTC_NUMBER EQU 9
+USBFS_ep_4__INTC_PRIOR_NUM EQU 7
+USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
+USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; USBFS_sof_int
USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-; SCSI_Out_Ctl
-SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+; USBFS_USB
+USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
+USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
+USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN
+USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR
+USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG
+USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN
+USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR
+USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG
+USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN
+USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR
+USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG
+USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN
+USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR
+USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG
+USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN
+USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR
+USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG
+USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN
+USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR
+USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG
+USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN
+USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR
+USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG
+USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN
+USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR
+USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN
+USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR
+USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR
+USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA
+USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB
+USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA
+USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB
+USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR
+USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA
+USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB
+USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA
+USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB
+USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR
+USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA
+USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB
+USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA
+USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB
+USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR
+USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA
+USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB
+USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA
+USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB
+USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR
+USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA
+USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB
+USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA
+USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB
+USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR
+USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA
+USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB
+USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA
+USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB
+USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR
+USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA
+USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB
+USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA
+USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB
+USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR
+USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA
+USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB
+USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA
+USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB
+USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE
+USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT
+USBFS_USB__CR0 EQU CYREG_USB_CR0
+USBFS_USB__CR1 EQU CYREG_USB_CR1
+USBFS_USB__CWA EQU CYREG_USB_CWA
+USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
+USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
+USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
+USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
+USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
+USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
+USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
+USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1
+USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2
+USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3
+USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
+USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
+USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
+USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
+USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
+USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
+USBFS_USB__PM_ACT_MSK EQU 0x01
+USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
+USBFS_USB__PM_STBY_MSK EQU 0x01
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
+USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
+USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
+USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
+USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0
+USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1
+USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0
+USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0
+USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1
+USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0
+USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0
+USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1
+USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0
+USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0
+USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1
+USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0
+USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0
+USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1
+USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0
+USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0
+USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1
+USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
+USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
+USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
+USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
+USBFS_USB__SOF0 EQU CYREG_USB_SOF0
+USBFS_USB__SOF1 EQU CYREG_USB_SOF1
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
+USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
+USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
-; SCSI_Out_DBx
-SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__0__MASK EQU 0x02
-SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1
-SCSI_Out_DBx__0__PORT EQU 5
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__0__SHIFT EQU 1
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__1__MASK EQU 0x01
-SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0
-SCSI_Out_DBx__1__PORT EQU 5
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__1__SHIFT EQU 0
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__2__MASK EQU 0x20
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__2__PORT EQU 6
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__2__SHIFT EQU 5
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__3__MASK EQU 0x10
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4
-SCSI_Out_DBx__3__PORT EQU 6
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__3__SHIFT EQU 4
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__4__MASK EQU 0x80
-SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__4__PORT EQU 2
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__4__SHIFT EQU 7
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__5__MASK EQU 0x40
-SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6
-SCSI_Out_DBx__5__PORT EQU 2
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__5__SHIFT EQU 6
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__6__MASK EQU 0x08
-SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__6__PORT EQU 2
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__6__SHIFT EQU 3
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__7__MASK EQU 0x04
-SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2
-SCSI_Out_DBx__7__PORT EQU 2
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__7__SHIFT EQU 2
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__DB0__MASK EQU 0x02
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1
-SCSI_Out_DBx__DB0__PORT EQU 5
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__DB0__SHIFT EQU 1
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__DB1__MASK EQU 0x01
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0
-SCSI_Out_DBx__DB1__PORT EQU 5
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__DB1__SHIFT EQU 0
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB2__MASK EQU 0x20
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__DB2__PORT EQU 6
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB2__SHIFT EQU 5
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB3__MASK EQU 0x10
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4
-SCSI_Out_DBx__DB3__PORT EQU 6
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB3__SHIFT EQU 4
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB4__MASK EQU 0x80
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__DB4__PORT EQU 2
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB4__SHIFT EQU 7
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB5__MASK EQU 0x40
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6
-SCSI_Out_DBx__DB5__PORT EQU 2
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB5__SHIFT EQU 6
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB6__MASK EQU 0x08
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__DB6__PORT EQU 2
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB6__SHIFT EQU 3
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB7__MASK EQU 0x04
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2
-SCSI_Out_DBx__DB7__PORT EQU 2
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB7__SHIFT EQU 2
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
-
-; SCSI_RST_ISR
-SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-SCSI_RST_ISR__INTC_MASK EQU 0x04
-SCSI_RST_ISR__INTC_NUMBER EQU 2
-SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
-SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
-SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SDCard_BSPIM
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB09_10_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB09_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB09_ST
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_10_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB09_10_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB09_10_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB09_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB09_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB09_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB09_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB09_MSK
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB09_MSK_ACTL
-SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
-SDCard_BSPIM_RxStsReg__4__POS EQU 4
-SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
-SDCard_BSPIM_RxStsReg__5__POS EQU 5
-SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
-SDCard_BSPIM_RxStsReg__6__POS EQU 6
-SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
-SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
-SDCard_BSPIM_TxStsReg__0__POS EQU 0
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
-SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
-SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
-SDCard_BSPIM_TxStsReg__2__POS EQU 2
-SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
-SDCard_BSPIM_TxStsReg__3__POS EQU 3
-SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
-SDCard_BSPIM_TxStsReg__4__POS EQU 4
-SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB09_10_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB09_10_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB09_10_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB09_10_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB09_10_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB09_10_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB09_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB09_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB09_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB09_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB09_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB09_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB09_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB09_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB09_F1
-
-; USBFS_dp_int
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_dp_int__INTC_MASK EQU 0x1000
-USBFS_dp_int__INTC_NUMBER EQU 12
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SCSI_In_DBx
-SCSI_In_DBx__0__AG EQU CYREG_PRT5_AG
-SCSI_In_DBx__0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_In_DBx__0__BIE EQU CYREG_PRT5_BIE
-SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_In_DBx__0__BYP EQU CYREG_PRT5_BYP
-SCSI_In_DBx__0__CTL EQU CYREG_PRT5_CTL
-SCSI_In_DBx__0__DM0 EQU CYREG_PRT5_DM0
-SCSI_In_DBx__0__DM1 EQU CYREG_PRT5_DM1
-SCSI_In_DBx__0__DM2 EQU CYREG_PRT5_DM2
-SCSI_In_DBx__0__DR EQU CYREG_PRT5_DR
-SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In_DBx__0__MASK EQU 0x08
-SCSI_In_DBx__0__PC EQU CYREG_PRT5_PC3
-SCSI_In_DBx__0__PORT EQU 5
-SCSI_In_DBx__0__PRT EQU CYREG_PRT5_PRT
-SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_In_DBx__0__PS EQU CYREG_PRT5_PS
-SCSI_In_DBx__0__SHIFT EQU 3
-SCSI_In_DBx__0__SLW EQU CYREG_PRT5_SLW
-SCSI_In_DBx__1__AG EQU CYREG_PRT5_AG
-SCSI_In_DBx__1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_In_DBx__1__BIE EQU CYREG_PRT5_BIE
-SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_In_DBx__1__BYP EQU CYREG_PRT5_BYP
-SCSI_In_DBx__1__CTL EQU CYREG_PRT5_CTL
-SCSI_In_DBx__1__DM0 EQU CYREG_PRT5_DM0
-SCSI_In_DBx__1__DM1 EQU CYREG_PRT5_DM1
-SCSI_In_DBx__1__DM2 EQU CYREG_PRT5_DM2
-SCSI_In_DBx__1__DR EQU CYREG_PRT5_DR
-SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In_DBx__1__MASK EQU 0x04
-SCSI_In_DBx__1__PC EQU CYREG_PRT5_PC2
-SCSI_In_DBx__1__PORT EQU 5
-SCSI_In_DBx__1__PRT EQU CYREG_PRT5_PRT
-SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_In_DBx__1__PS EQU CYREG_PRT5_PS
-SCSI_In_DBx__1__SHIFT EQU 2
-SCSI_In_DBx__1__SLW EQU CYREG_PRT5_SLW
-SCSI_In_DBx__2__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__2__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__2__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__2__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__2__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__2__MASK EQU 0x80
-SCSI_In_DBx__2__PC EQU CYREG_PRT6_PC7
-SCSI_In_DBx__2__PORT EQU 6
-SCSI_In_DBx__2__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__2__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__2__SHIFT EQU 7
-SCSI_In_DBx__2__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__3__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__3__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__3__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__3__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__3__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__3__MASK EQU 0x40
-SCSI_In_DBx__3__PC EQU CYREG_PRT6_PC6
-SCSI_In_DBx__3__PORT EQU 6
-SCSI_In_DBx__3__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__3__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__3__SHIFT EQU 6
-SCSI_In_DBx__3__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__4__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__4__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__4__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__4__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__4__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__4__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__4__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__4__MASK EQU 0x20
-SCSI_In_DBx__4__PC EQU CYREG_PRT12_PC5
-SCSI_In_DBx__4__PORT EQU 12
-SCSI_In_DBx__4__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__4__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__4__SHIFT EQU 5
-SCSI_In_DBx__4__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__4__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__5__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__5__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__5__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__5__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__5__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__5__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__5__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__5__MASK EQU 0x10
-SCSI_In_DBx__5__PC EQU CYREG_PRT12_PC4
-SCSI_In_DBx__5__PORT EQU 12
-SCSI_In_DBx__5__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__5__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__5__SHIFT EQU 4
-SCSI_In_DBx__5__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__5__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__6__MASK EQU 0x20
-SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC5
-SCSI_In_DBx__6__PORT EQU 2
-SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__6__SHIFT EQU 5
-SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__7__MASK EQU 0x10
-SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC4
-SCSI_In_DBx__7__PORT EQU 2
-SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__7__SHIFT EQU 4
-SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB0__AG EQU CYREG_PRT5_AG
-SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_In_DBx__DB0__BIE EQU CYREG_PRT5_BIE
-SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_In_DBx__DB0__BYP EQU CYREG_PRT5_BYP
-SCSI_In_DBx__DB0__CTL EQU CYREG_PRT5_CTL
-SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
-SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
-SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
-SCSI_In_DBx__DB0__DR EQU CYREG_PRT5_DR
-SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In_DBx__DB0__MASK EQU 0x08
-SCSI_In_DBx__DB0__PC EQU CYREG_PRT5_PC3
-SCSI_In_DBx__DB0__PORT EQU 5
-SCSI_In_DBx__DB0__PRT EQU CYREG_PRT5_PRT
-SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_In_DBx__DB0__PS EQU CYREG_PRT5_PS
-SCSI_In_DBx__DB0__SHIFT EQU 3
-SCSI_In_DBx__DB0__SLW EQU CYREG_PRT5_SLW
-SCSI_In_DBx__DB1__AG EQU CYREG_PRT5_AG
-SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_In_DBx__DB1__BIE EQU CYREG_PRT5_BIE
-SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_In_DBx__DB1__BYP EQU CYREG_PRT5_BYP
-SCSI_In_DBx__DB1__CTL EQU CYREG_PRT5_CTL
-SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
-SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
-SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
-SCSI_In_DBx__DB1__DR EQU CYREG_PRT5_DR
-SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_In_DBx__DB1__MASK EQU 0x04
-SCSI_In_DBx__DB1__PC EQU CYREG_PRT5_PC2
-SCSI_In_DBx__DB1__PORT EQU 5
-SCSI_In_DBx__DB1__PRT EQU CYREG_PRT5_PRT
-SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_In_DBx__DB1__PS EQU CYREG_PRT5_PS
-SCSI_In_DBx__DB1__SHIFT EQU 2
-SCSI_In_DBx__DB1__SLW EQU CYREG_PRT5_SLW
-SCSI_In_DBx__DB2__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__DB2__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__DB2__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__DB2__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__DB2__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__DB2__MASK EQU 0x80
-SCSI_In_DBx__DB2__PC EQU CYREG_PRT6_PC7
-SCSI_In_DBx__DB2__PORT EQU 6
-SCSI_In_DBx__DB2__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__DB2__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__DB2__SHIFT EQU 7
-SCSI_In_DBx__DB2__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__DB3__AG EQU CYREG_PRT6_AG
-SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_In_DBx__DB3__BIE EQU CYREG_PRT6_BIE
-SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_In_DBx__DB3__BYP EQU CYREG_PRT6_BYP
-SCSI_In_DBx__DB3__CTL EQU CYREG_PRT6_CTL
-SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
-SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
-SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
-SCSI_In_DBx__DB3__DR EQU CYREG_PRT6_DR
-SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_In_DBx__DB3__MASK EQU 0x40
-SCSI_In_DBx__DB3__PC EQU CYREG_PRT6_PC6
-SCSI_In_DBx__DB3__PORT EQU 6
-SCSI_In_DBx__DB3__PRT EQU CYREG_PRT6_PRT
-SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_In_DBx__DB3__PS EQU CYREG_PRT6_PS
-SCSI_In_DBx__DB3__SHIFT EQU 6
-SCSI_In_DBx__DB3__SLW EQU CYREG_PRT6_SLW
-SCSI_In_DBx__DB4__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__DB4__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__DB4__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__DB4__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__DB4__MASK EQU 0x20
-SCSI_In_DBx__DB4__PC EQU CYREG_PRT12_PC5
-SCSI_In_DBx__DB4__PORT EQU 12
-SCSI_In_DBx__DB4__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__DB4__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__DB4__SHIFT EQU 5
-SCSI_In_DBx__DB4__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__DB4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__DB4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__DB4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__DB4__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__DB5__AG EQU CYREG_PRT12_AG
-SCSI_In_DBx__DB5__BIE EQU CYREG_PRT12_BIE
-SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT12_BIT_MASK
-SCSI_In_DBx__DB5__BYP EQU CYREG_PRT12_BYP
-SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT12_DM0
-SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT12_DM1
-SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT12_DM2
-SCSI_In_DBx__DB5__DR EQU CYREG_PRT12_DR
-SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT12_INP_DIS
-SCSI_In_DBx__DB5__MASK EQU 0x10
-SCSI_In_DBx__DB5__PC EQU CYREG_PRT12_PC4
-SCSI_In_DBx__DB5__PORT EQU 12
-SCSI_In_DBx__DB5__PRT EQU CYREG_PRT12_PRT
-SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
-SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
-SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
-SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
-SCSI_In_DBx__DB5__PS EQU CYREG_PRT12_PS
-SCSI_In_DBx__DB5__SHIFT EQU 4
-SCSI_In_DBx__DB5__SIO_CFG EQU CYREG_PRT12_SIO_CFG
-SCSI_In_DBx__DB5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
-SCSI_In_DBx__DB5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
-SCSI_In_DBx__DB5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
-SCSI_In_DBx__DB5__SLW EQU CYREG_PRT12_SLW
-SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB6__MASK EQU 0x20
-SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC5
-SCSI_In_DBx__DB6__PORT EQU 2
-SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB6__SHIFT EQU 5
-SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW
-SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG
-SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE
-SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP
-SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL
-SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
-SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
-SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
-SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR
-SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_In_DBx__DB7__MASK EQU 0x10
-SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC4
-SCSI_In_DBx__DB7__PORT EQU 2
-SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT
-SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS
-SCSI_In_DBx__DB7__SHIFT EQU 4
-SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW
-
-; SCSI_RX_DMA
-SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_RX_DMA__DRQ_NUMBER EQU 0
-SCSI_RX_DMA__NUMBEROF_TDS EQU 0
-SCSI_RX_DMA__PRIORITY EQU 2
-SCSI_RX_DMA__TERMIN_EN EQU 0
-SCSI_RX_DMA__TERMIN_SEL EQU 0
-SCSI_RX_DMA__TERMOUT0_EN EQU 1
-SCSI_RX_DMA__TERMOUT0_SEL EQU 0
-SCSI_RX_DMA__TERMOUT1_EN EQU 0
-SCSI_RX_DMA__TERMOUT1_SEL EQU 0
-
-; SCSI_TX_DMA
-SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SCSI_TX_DMA__DRQ_NUMBER EQU 1
-SCSI_TX_DMA__NUMBEROF_TDS EQU 0
-SCSI_TX_DMA__PRIORITY EQU 2
-SCSI_TX_DMA__TERMIN_EN EQU 0
-SCSI_TX_DMA__TERMIN_SEL EQU 0
-SCSI_TX_DMA__TERMOUT0_EN EQU 1
-SCSI_TX_DMA__TERMOUT0_SEL EQU 1
-SCSI_TX_DMA__TERMOUT1_EN EQU 0
-SCSI_TX_DMA__TERMOUT1_SEL EQU 0
-
-; SD_Data_Clk
-SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
-SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
-SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
-SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
-SD_Data_Clk__INDEX EQU 0x00
-SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SD_Data_Clk__PM_ACT_MSK EQU 0x01
-SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SD_Data_Clk__PM_STBY_MSK EQU 0x01
-
-; timer_clock
-timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
-timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
-timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
-timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
-timer_clock__INDEX EQU 0x02
-timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-timer_clock__PM_ACT_MSK EQU 0x04
-timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-timer_clock__PM_STBY_MSK EQU 0x04
-
-; SCSI_Noise
-SCSI_Noise__0__AG EQU CYREG_PRT2_AG
-SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE
-SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP
-SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL
-SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0
-SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1
-SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2
-SCSI_Noise__0__DR EQU CYREG_PRT2_DR
-SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Noise__0__MASK EQU 0x01
-SCSI_Noise__0__PC EQU CYREG_PRT2_PC0
-SCSI_Noise__0__PORT EQU 2
-SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT
-SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Noise__0__PS EQU CYREG_PRT2_PS
-SCSI_Noise__0__SHIFT EQU 0
-SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW
-SCSI_Noise__1__AG EQU CYREG_PRT6_AG
-SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__1__DR EQU CYREG_PRT6_DR
-SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__1__MASK EQU 0x08
-SCSI_Noise__1__PC EQU CYREG_PRT6_PC3
-SCSI_Noise__1__PORT EQU 6
-SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__1__PS EQU CYREG_PRT6_PS
-SCSI_Noise__1__SHIFT EQU 3
-SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__2__AG EQU CYREG_PRT4_AG
-SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE
-SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP
-SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL
-SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0
-SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1
-SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2
-SCSI_Noise__2__DR EQU CYREG_PRT4_DR
-SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Noise__2__MASK EQU 0x08
-SCSI_Noise__2__PC EQU CYREG_PRT4_PC3
-SCSI_Noise__2__PORT EQU 4
-SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT
-SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Noise__2__PS EQU CYREG_PRT4_PS
-SCSI_Noise__2__SHIFT EQU 3
-SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW
-SCSI_Noise__3__AG EQU CYREG_PRT4_AG
-SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE
-SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP
-SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL
-SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0
-SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1
-SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2
-SCSI_Noise__3__DR EQU CYREG_PRT4_DR
-SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Noise__3__MASK EQU 0x80
-SCSI_Noise__3__PC EQU CYREG_PRT4_PC7
-SCSI_Noise__3__PORT EQU 4
-SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT
-SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Noise__3__PS EQU CYREG_PRT4_PS
-SCSI_Noise__3__SHIFT EQU 7
-SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW
-SCSI_Noise__4__AG EQU CYREG_PRT6_AG
-SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__4__DR EQU CYREG_PRT6_DR
-SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__4__MASK EQU 0x04
-SCSI_Noise__4__PC EQU CYREG_PRT6_PC2
-SCSI_Noise__4__PORT EQU 6
-SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__4__PS EQU CYREG_PRT6_PS
-SCSI_Noise__4__SHIFT EQU 2
-SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG
-SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR
-SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__ACK__MASK EQU 0x04
-SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2
-SCSI_Noise__ACK__PORT EQU 6
-SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS
-SCSI_Noise__ACK__SHIFT EQU 2
-SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG
-SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE
-SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP
-SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL
-SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0
-SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1
-SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2
-SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR
-SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Noise__ATN__MASK EQU 0x01
-SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0
-SCSI_Noise__ATN__PORT EQU 2
-SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT
-SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS
-SCSI_Noise__ATN__SHIFT EQU 0
-SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW
-SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG
-SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE
-SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP
-SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL
-SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0
-SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1
-SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2
-SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR
-SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Noise__BSY__MASK EQU 0x08
-SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3
-SCSI_Noise__BSY__PORT EQU 6
-SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT
-SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS
-SCSI_Noise__BSY__SHIFT EQU 3
-SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW
-SCSI_Noise__RST__AG EQU CYREG_PRT4_AG
-SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE
-SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP
-SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL
-SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0
-SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1
-SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2
-SCSI_Noise__RST__DR EQU CYREG_PRT4_DR
-SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Noise__RST__MASK EQU 0x80
-SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7
-SCSI_Noise__RST__PORT EQU 4
-SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT
-SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Noise__RST__PS EQU CYREG_PRT4_PS
-SCSI_Noise__RST__SHIFT EQU 7
-SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW
-SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG
-SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE
-SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP
-SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL
-SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0
-SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1
-SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2
-SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR
-SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Noise__SEL__MASK EQU 0x08
-SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3
-SCSI_Noise__SEL__PORT EQU 4
-SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT
-SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS
-SCSI_Noise__SEL__SHIFT EQU 3
-SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW
-
-; scsiTarget
-scsiTarget_StatusReg__0__MASK EQU 0x01
-scsiTarget_StatusReg__0__POS EQU 0
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
-scsiTarget_StatusReg__1__MASK EQU 0x02
-scsiTarget_StatusReg__1__POS EQU 1
-scsiTarget_StatusReg__2__MASK EQU 0x04
-scsiTarget_StatusReg__2__POS EQU 2
-scsiTarget_StatusReg__3__MASK EQU 0x08
-scsiTarget_StatusReg__3__POS EQU 3
-scsiTarget_StatusReg__4__MASK EQU 0x10
-scsiTarget_StatusReg__4__POS EQU 4
-scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK
-scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
-scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL
-scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB12_MSK
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB12_ST_CTL
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB12_ST_CTL
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB12_ST
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB12_CTL
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB12_CTL
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB12_MSK
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB12_13_A0
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB12_13_A1
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB12_13_D0
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB12_13_D1
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB12_13_F0
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB12_13_F1
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB12_A0_A1
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB12_A0
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB12_A1
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB12_D0_D1
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB12_D0
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB12_D1
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB12_F0_F1
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB12_F0
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB12_F1
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-
-; USBFS_ep_0
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_0__INTC_MASK EQU 0x1000000
-USBFS_ep_0__INTC_NUMBER EQU 24
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_1
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x40
-USBFS_ep_1__INTC_NUMBER EQU 6
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_2
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x80
-USBFS_ep_2__INTC_NUMBER EQU 7
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_3
-USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_3__INTC_MASK EQU 0x100
-USBFS_ep_3__INTC_NUMBER EQU 8
-USBFS_ep_3__INTC_PRIOR_NUM EQU 7
-USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8
-USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_4
-USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_4__INTC_MASK EQU 0x200
-USBFS_ep_4__INTC_NUMBER EQU 9
-USBFS_ep_4__INTC_PRIOR_NUM EQU 7
-USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9
-USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SD_RX_DMA
-SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_RX_DMA__DRQ_NUMBER EQU 2
-SD_RX_DMA__NUMBEROF_TDS EQU 0
-SD_RX_DMA__PRIORITY EQU 2
-SD_RX_DMA__TERMIN_EN EQU 0
-SD_RX_DMA__TERMIN_SEL EQU 0
-SD_RX_DMA__TERMOUT0_EN EQU 1
-SD_RX_DMA__TERMOUT0_SEL EQU 2
-SD_RX_DMA__TERMOUT1_EN EQU 0
-SD_RX_DMA__TERMOUT1_SEL EQU 0
-
-; SD_TX_DMA
-SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
-SD_TX_DMA__DRQ_NUMBER EQU 3
-SD_TX_DMA__NUMBEROF_TDS EQU 0
-SD_TX_DMA__PRIORITY EQU 2
-SD_TX_DMA__TERMIN_EN EQU 0
-SD_TX_DMA__TERMIN_SEL EQU 0
-SD_TX_DMA__TERMOUT0_EN EQU 1
-SD_TX_DMA__TERMOUT0_SEL EQU 3
-SD_TX_DMA__TERMOUT1_EN EQU 0
-SD_TX_DMA__TERMOUT1_SEL EQU 0
-
-; USBFS_USB
-USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
-USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
-USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN
-USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR
-USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG
-USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN
-USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR
-USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG
-USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN
-USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR
-USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG
-USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN
-USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR
-USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG
-USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN
-USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR
-USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG
-USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN
-USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR
-USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG
-USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN
-USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR
-USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG
-USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN
-USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR
-USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN
-USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR
-USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR
-USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA
-USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB
-USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA
-USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB
-USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR
-USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA
-USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB
-USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA
-USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB
-USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR
-USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA
-USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB
-USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA
-USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB
-USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR
-USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA
-USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB
-USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA
-USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB
-USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR
-USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA
-USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB
-USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA
-USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB
-USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR
-USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA
-USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB
-USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA
-USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB
-USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR
-USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA
-USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB
-USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA
-USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB
-USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR
-USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA
-USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB
-USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA
-USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB
-USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE
-USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT
-USBFS_USB__CR0 EQU CYREG_USB_CR0
-USBFS_USB__CR1 EQU CYREG_USB_CR1
-USBFS_USB__CWA EQU CYREG_USB_CWA
-USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB
-USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
-USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
-USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
-USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
-USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
-USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
-USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1
-USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2
-USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3
-USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4
-USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
-USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
-USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
-USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
-USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
-USBFS_USB__PM_ACT_MSK EQU 0x01
-USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
-USBFS_USB__PM_STBY_MSK EQU 0x01
-USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
-USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
-USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
-USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0
-USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1
-USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0
-USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0
-USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1
-USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0
-USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0
-USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1
-USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0
-USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0
-USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1
-USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0
-USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0
-USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1
-USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0
-USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0
-USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1
-USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0
-USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
-USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
-USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
-USBFS_USB__SOF0 EQU CYREG_USB_SOF0
-USBFS_USB__SOF1 EQU CYREG_USB_SOF1
-USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
-USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
-
-; SCSI_CLK
-SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
-SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
-SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
-SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
-SCSI_CLK__INDEX EQU 0x01
-SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-SCSI_CLK__PM_ACT_MSK EQU 0x02
-SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-SCSI_CLK__PM_STBY_MSK EQU 0x02
-
-; SCSI_Out
-SCSI_Out__0__AG EQU CYREG_PRT15_AG
-SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out__0__BIE EQU CYREG_PRT15_BIE
-SCSI_Out__0__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out__0__BYP EQU CYREG_PRT15_BYP
-SCSI_Out__0__CTL EQU CYREG_PRT15_CTL
-SCSI_Out__0__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out__0__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out__0__DR EQU CYREG_PRT15_DR
-SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out__0__MASK EQU 0x20
-SCSI_Out__0__PC EQU CYREG_IO_PC_PRT15_PC5
-SCSI_Out__0__PORT EQU 15
-SCSI_Out__0__PRT EQU CYREG_PRT15_PRT
-SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out__0__PS EQU CYREG_PRT15_PS
-SCSI_Out__0__SHIFT EQU 5
-SCSI_Out__0__SLW EQU CYREG_PRT15_SLW
-SCSI_Out__1__AG EQU CYREG_PRT15_AG
-SCSI_Out__1__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out__1__BIE EQU CYREG_PRT15_BIE
-SCSI_Out__1__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out__1__BYP EQU CYREG_PRT15_BYP
-SCSI_Out__1__CTL EQU CYREG_PRT15_CTL
-SCSI_Out__1__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out__1__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out__1__DR EQU CYREG_PRT15_DR
-SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out__1__MASK EQU 0x10
-SCSI_Out__1__PC EQU CYREG_IO_PC_PRT15_PC4
-SCSI_Out__1__PORT EQU 15
-SCSI_Out__1__PRT EQU CYREG_PRT15_PRT
-SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out__1__PS EQU CYREG_PRT15_PS
-SCSI_Out__1__SHIFT EQU 4
-SCSI_Out__1__SLW EQU CYREG_PRT15_SLW
-SCSI_Out__2__AG EQU CYREG_PRT6_AG
-SCSI_Out__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__2__DR EQU CYREG_PRT6_DR
-SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__2__MASK EQU 0x02
-SCSI_Out__2__PC EQU CYREG_PRT6_PC1
-SCSI_Out__2__PORT EQU 6
-SCSI_Out__2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__2__PS EQU CYREG_PRT6_PS
-SCSI_Out__2__SHIFT EQU 1
-SCSI_Out__2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__3__AG EQU CYREG_PRT6_AG
-SCSI_Out__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__3__DR EQU CYREG_PRT6_DR
-SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__3__MASK EQU 0x01
-SCSI_Out__3__PC EQU CYREG_PRT6_PC0
-SCSI_Out__3__PORT EQU 6
-SCSI_Out__3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__3__PS EQU CYREG_PRT6_PS
-SCSI_Out__3__SHIFT EQU 0
-SCSI_Out__3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__4__AG EQU CYREG_PRT4_AG
-SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__4__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__4__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__4__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__4__DR EQU CYREG_PRT4_DR
-SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__4__MASK EQU 0x20
-SCSI_Out__4__PC EQU CYREG_PRT4_PC5
-SCSI_Out__4__PORT EQU 4
-SCSI_Out__4__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__4__PS EQU CYREG_PRT4_PS
-SCSI_Out__4__SHIFT EQU 5
-SCSI_Out__4__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__5__AG EQU CYREG_PRT4_AG
-SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__5__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__5__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__5__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__5__DR EQU CYREG_PRT4_DR
-SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__5__MASK EQU 0x10
-SCSI_Out__5__PC EQU CYREG_PRT4_PC4
-SCSI_Out__5__PORT EQU 4
-SCSI_Out__5__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__5__PS EQU CYREG_PRT4_PS
-SCSI_Out__5__SHIFT EQU 4
-SCSI_Out__5__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__6__AG EQU CYREG_PRT0_AG
-SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__6__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__6__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__6__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__6__DR EQU CYREG_PRT0_DR
-SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__6__MASK EQU 0x80
-SCSI_Out__6__PC EQU CYREG_PRT0_PC7
-SCSI_Out__6__PORT EQU 0
-SCSI_Out__6__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__6__PS EQU CYREG_PRT0_PS
-SCSI_Out__6__SHIFT EQU 7
-SCSI_Out__6__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__7__AG EQU CYREG_PRT0_AG
-SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__7__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__7__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__7__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__7__DR EQU CYREG_PRT0_DR
-SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__7__MASK EQU 0x40
-SCSI_Out__7__PC EQU CYREG_PRT0_PC6
-SCSI_Out__7__PORT EQU 0
-SCSI_Out__7__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__7__PS EQU CYREG_PRT0_PS
-SCSI_Out__7__SHIFT EQU 6
-SCSI_Out__7__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__8__AG EQU CYREG_PRT0_AG
-SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__8__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__8__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__8__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__8__DR EQU CYREG_PRT0_DR
-SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__8__MASK EQU 0x08
-SCSI_Out__8__PC EQU CYREG_PRT0_PC3
-SCSI_Out__8__PORT EQU 0
-SCSI_Out__8__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__8__PS EQU CYREG_PRT0_PS
-SCSI_Out__8__SHIFT EQU 3
-SCSI_Out__8__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__9__AG EQU CYREG_PRT0_AG
-SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__9__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__9__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__9__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__9__DR EQU CYREG_PRT0_DR
-SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__9__MASK EQU 0x04
-SCSI_Out__9__PC EQU CYREG_PRT0_PC2
-SCSI_Out__9__PORT EQU 0
-SCSI_Out__9__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__9__PS EQU CYREG_PRT0_PS
-SCSI_Out__9__SHIFT EQU 2
-SCSI_Out__9__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__ACK__AG EQU CYREG_PRT6_AG
-SCSI_Out__ACK__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__ACK__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__ACK__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__ACK__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__ACK__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__ACK__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__ACK__DR EQU CYREG_PRT6_DR
-SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__ACK__MASK EQU 0x01
-SCSI_Out__ACK__PC EQU CYREG_PRT6_PC0
-SCSI_Out__ACK__PORT EQU 6
-SCSI_Out__ACK__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__ACK__PS EQU CYREG_PRT6_PS
-SCSI_Out__ACK__SHIFT EQU 0
-SCSI_Out__ACK__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__ATN__AG EQU CYREG_PRT15_AG
-SCSI_Out__ATN__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out__ATN__BIE EQU CYREG_PRT15_BIE
-SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out__ATN__BYP EQU CYREG_PRT15_BYP
-SCSI_Out__ATN__CTL EQU CYREG_PRT15_CTL
-SCSI_Out__ATN__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out__ATN__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out__ATN__DR EQU CYREG_PRT15_DR
-SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out__ATN__MASK EQU 0x10
-SCSI_Out__ATN__PC EQU CYREG_IO_PC_PRT15_PC4
-SCSI_Out__ATN__PORT EQU 15
-SCSI_Out__ATN__PRT EQU CYREG_PRT15_PRT
-SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out__ATN__PS EQU CYREG_PRT15_PS
-SCSI_Out__ATN__SHIFT EQU 4
-SCSI_Out__ATN__SLW EQU CYREG_PRT15_SLW
-SCSI_Out__BSY__AG EQU CYREG_PRT6_AG
-SCSI_Out__BSY__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out__BSY__BIE EQU CYREG_PRT6_BIE
-SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out__BSY__BYP EQU CYREG_PRT6_BYP
-SCSI_Out__BSY__CTL EQU CYREG_PRT6_CTL
-SCSI_Out__BSY__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out__BSY__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out__BSY__DR EQU CYREG_PRT6_DR
-SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out__BSY__MASK EQU 0x02
-SCSI_Out__BSY__PC EQU CYREG_PRT6_PC1
-SCSI_Out__BSY__PORT EQU 6
-SCSI_Out__BSY__PRT EQU CYREG_PRT6_PRT
-SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out__BSY__PS EQU CYREG_PRT6_PS
-SCSI_Out__BSY__SHIFT EQU 1
-SCSI_Out__BSY__SLW EQU CYREG_PRT6_SLW
-SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
-SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
-SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__CD_raw__MASK EQU 0x40
-SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC6
-SCSI_Out__CD_raw__PORT EQU 0
-SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
-SCSI_Out__CD_raw__SHIFT EQU 6
-SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__DBP_raw__AG EQU CYREG_PRT15_AG
-SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT15_AMUX
-SCSI_Out__DBP_raw__BIE EQU CYREG_PRT15_BIE
-SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-SCSI_Out__DBP_raw__BYP EQU CYREG_PRT15_BYP
-SCSI_Out__DBP_raw__CTL EQU CYREG_PRT15_CTL
-SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT15_DM0
-SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT15_DM1
-SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2
-SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR
-SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS
-SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN
-SCSI_Out__DBP_raw__MASK EQU 0x20
-SCSI_Out__DBP_raw__PC EQU CYREG_IO_PC_PRT15_PC5
-SCSI_Out__DBP_raw__PORT EQU 15
-SCSI_Out__DBP_raw__PRT EQU CYREG_PRT15_PRT
-SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-SCSI_Out__DBP_raw__PS EQU CYREG_PRT15_PS
-SCSI_Out__DBP_raw__SHIFT EQU 5
-SCSI_Out__DBP_raw__SLW EQU CYREG_PRT15_SLW
-SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG
-SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR
-SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__IO_raw__MASK EQU 0x04
-SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC2
-SCSI_Out__IO_raw__PORT EQU 0
-SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS
-SCSI_Out__IO_raw__SHIFT EQU 2
-SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__MSG_raw__AG EQU CYREG_PRT4_AG
-SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__MSG_raw__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__MSG_raw__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__MSG_raw__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__MSG_raw__DR EQU CYREG_PRT4_DR
-SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__MSG_raw__MASK EQU 0x10
-SCSI_Out__MSG_raw__PC EQU CYREG_PRT4_PC4
-SCSI_Out__MSG_raw__PORT EQU 4
-SCSI_Out__MSG_raw__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__MSG_raw__PS EQU CYREG_PRT4_PS
-SCSI_Out__MSG_raw__SHIFT EQU 4
-SCSI_Out__MSG_raw__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__REQ__AG EQU CYREG_PRT0_AG
-SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__REQ__DR EQU CYREG_PRT0_DR
-SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__REQ__MASK EQU 0x08
-SCSI_Out__REQ__PC EQU CYREG_PRT0_PC3
-SCSI_Out__REQ__PORT EQU 0
-SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__REQ__PS EQU CYREG_PRT0_PS
-SCSI_Out__REQ__SHIFT EQU 3
-SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW
-SCSI_Out__RST__AG EQU CYREG_PRT4_AG
-SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX
-SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE
-SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
-SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP
-SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL
-SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0
-SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1
-SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2
-SCSI_Out__RST__DR EQU CYREG_PRT4_DR
-SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
-SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
-SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
-SCSI_Out__RST__MASK EQU 0x20
-SCSI_Out__RST__PC EQU CYREG_PRT4_PC5
-SCSI_Out__RST__PORT EQU 4
-SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT
-SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
-SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
-SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
-SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
-SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
-SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
-SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
-SCSI_Out__RST__PS EQU CYREG_PRT4_PS
-SCSI_Out__RST__SHIFT EQU 5
-SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW
-SCSI_Out__SEL__AG EQU CYREG_PRT0_AG
-SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX
-SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE
-SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP
-SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL
-SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0
-SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1
-SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
-SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
-SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
-SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
-SCSI_Out__SEL__MASK EQU 0x80
-SCSI_Out__SEL__PC EQU CYREG_PRT0_PC7
-SCSI_Out__SEL__PORT EQU 0
-SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT
-SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
-SCSI_Out__SEL__SHIFT EQU 7
-SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
+; EXTLED
+EXTLED__0__MASK EQU 0x01
+EXTLED__0__PC EQU CYREG_PRT0_PC0
+EXTLED__0__PORT EQU 0
+EXTLED__0__SHIFT EQU 0
+EXTLED__AG EQU CYREG_PRT0_AG
+EXTLED__AMUX EQU CYREG_PRT0_AMUX
+EXTLED__BIE EQU CYREG_PRT0_BIE
+EXTLED__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+EXTLED__BYP EQU CYREG_PRT0_BYP
+EXTLED__CTL EQU CYREG_PRT0_CTL
+EXTLED__DM0 EQU CYREG_PRT0_DM0
+EXTLED__DM1 EQU CYREG_PRT0_DM1
+EXTLED__DM2 EQU CYREG_PRT0_DM2
+EXTLED__DR EQU CYREG_PRT0_DR
+EXTLED__INP_DIS EQU CYREG_PRT0_INP_DIS
+EXTLED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+EXTLED__LCD_EN EQU CYREG_PRT0_LCD_EN
+EXTLED__MASK EQU 0x01
+EXTLED__PORT EQU 0
+EXTLED__PRT EQU CYREG_PRT0_PRT
+EXTLED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+EXTLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+EXTLED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+EXTLED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+EXTLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+EXTLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+EXTLED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+EXTLED__PS EQU CYREG_PRT0_PS
+EXTLED__SHIFT EQU 0
+EXTLED__SLW EQU CYREG_PRT0_SLW
-; USBFS_Dm
-USBFS_Dm__0__MASK EQU 0x80
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
-USBFS_Dm__0__PORT EQU 15
-USBFS_Dm__0__SHIFT EQU 7
-USBFS_Dm__AG EQU CYREG_PRT15_AG
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dm__DR EQU CYREG_PRT15_DR
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dm__MASK EQU 0x80
-USBFS_Dm__PORT EQU 15
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dm__PS EQU CYREG_PRT15_PS
-USBFS_Dm__SHIFT EQU 7
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW
+; SDCard_BSPIM
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB10_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB10_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB10_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB10_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB10_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB10_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB10_ST
+SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
+SDCard_BSPIM_RxStsReg__4__POS EQU 4
+SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
+SDCard_BSPIM_RxStsReg__5__POS EQU 5
+SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
+SDCard_BSPIM_RxStsReg__6__POS EQU 6
+SDCard_BSPIM_RxStsReg__MASK EQU 0x70
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB08_09_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB08_09_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB08_09_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB08_09_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB08_09_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB08_09_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB08_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB08_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB08_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB08_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB08_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB08_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB08_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB08_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB08_F1
+SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
+SDCard_BSPIM_TxStsReg__0__POS EQU 0
+SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
+SDCard_BSPIM_TxStsReg__1__POS EQU 1
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
+SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
+SDCard_BSPIM_TxStsReg__2__POS EQU 2
+SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
+SDCard_BSPIM_TxStsReg__3__POS EQU 3
+SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
+SDCard_BSPIM_TxStsReg__4__POS EQU 4
+SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
-; USBFS_Dp
-USBFS_Dp__0__MASK EQU 0x40
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
-USBFS_Dp__0__PORT EQU 15
-USBFS_Dp__0__SHIFT EQU 6
-USBFS_Dp__AG EQU CYREG_PRT15_AG
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dp__DR EQU CYREG_PRT15_DR
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dp__MASK EQU 0x40
-USBFS_Dp__PORT EQU 15
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dp__PS EQU CYREG_PRT15_PS
-USBFS_Dp__SHIFT EQU 6
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+; SD_SCK
+SD_SCK__0__MASK EQU 0x04
+SD_SCK__0__PC EQU CYREG_PRT3_PC2
+SD_SCK__0__PORT EQU 3
+SD_SCK__0__SHIFT EQU 2
+SD_SCK__AG EQU CYREG_PRT3_AG
+SD_SCK__AMUX EQU CYREG_PRT3_AMUX
+SD_SCK__BIE EQU CYREG_PRT3_BIE
+SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_SCK__BYP EQU CYREG_PRT3_BYP
+SD_SCK__CTL EQU CYREG_PRT3_CTL
+SD_SCK__DM0 EQU CYREG_PRT3_DM0
+SD_SCK__DM1 EQU CYREG_PRT3_DM1
+SD_SCK__DM2 EQU CYREG_PRT3_DM2
+SD_SCK__DR EQU CYREG_PRT3_DR
+SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_SCK__MASK EQU 0x04
+SD_SCK__PORT EQU 3
+SD_SCK__PRT EQU CYREG_PRT3_PRT
+SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_SCK__PS EQU CYREG_PRT3_PS
+SD_SCK__SHIFT EQU 2
+SD_SCK__SLW EQU CYREG_PRT3_SLW
; SCSI_In
SCSI_In__0__AG EQU CYREG_PRT2_AG
SCSI_In__REQ__SHIFT EQU 5
SCSI_In__REQ__SLW EQU CYREG_PRT0_SLW
-; SD_MISO
-SD_MISO__0__MASK EQU 0x02
-SD_MISO__0__PC EQU CYREG_PRT3_PC1
-SD_MISO__0__PORT EQU 3
-SD_MISO__0__SHIFT EQU 1
-SD_MISO__AG EQU CYREG_PRT3_AG
-SD_MISO__AMUX EQU CYREG_PRT3_AMUX
-SD_MISO__BIE EQU CYREG_PRT3_BIE
-SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_MISO__BYP EQU CYREG_PRT3_BYP
-SD_MISO__CTL EQU CYREG_PRT3_CTL
-SD_MISO__DM0 EQU CYREG_PRT3_DM0
-SD_MISO__DM1 EQU CYREG_PRT3_DM1
-SD_MISO__DM2 EQU CYREG_PRT3_DM2
-SD_MISO__DR EQU CYREG_PRT3_DR
-SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_MISO__MASK EQU 0x02
-SD_MISO__PORT EQU 3
-SD_MISO__PRT EQU CYREG_PRT3_PRT
-SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_MISO__PS EQU CYREG_PRT3_PS
-SD_MISO__SHIFT EQU 1
-SD_MISO__SLW EQU CYREG_PRT3_SLW
+; SCSI_In_DBx
+SCSI_In_DBx__0__AG EQU CYREG_PRT5_AG
+SCSI_In_DBx__0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In_DBx__0__BIE EQU CYREG_PRT5_BIE
+SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In_DBx__0__BYP EQU CYREG_PRT5_BYP
+SCSI_In_DBx__0__CTL EQU CYREG_PRT5_CTL
+SCSI_In_DBx__0__DM0 EQU CYREG_PRT5_DM0
+SCSI_In_DBx__0__DM1 EQU CYREG_PRT5_DM1
+SCSI_In_DBx__0__DM2 EQU CYREG_PRT5_DM2
+SCSI_In_DBx__0__DR EQU CYREG_PRT5_DR
+SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In_DBx__0__MASK EQU 0x08
+SCSI_In_DBx__0__PC EQU CYREG_PRT5_PC3
+SCSI_In_DBx__0__PORT EQU 5
+SCSI_In_DBx__0__PRT EQU CYREG_PRT5_PRT
+SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In_DBx__0__PS EQU CYREG_PRT5_PS
+SCSI_In_DBx__0__SHIFT EQU 3
+SCSI_In_DBx__0__SLW EQU CYREG_PRT5_SLW
+SCSI_In_DBx__1__AG EQU CYREG_PRT5_AG
+SCSI_In_DBx__1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In_DBx__1__BIE EQU CYREG_PRT5_BIE
+SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In_DBx__1__BYP EQU CYREG_PRT5_BYP
+SCSI_In_DBx__1__CTL EQU CYREG_PRT5_CTL
+SCSI_In_DBx__1__DM0 EQU CYREG_PRT5_DM0
+SCSI_In_DBx__1__DM1 EQU CYREG_PRT5_DM1
+SCSI_In_DBx__1__DM2 EQU CYREG_PRT5_DM2
+SCSI_In_DBx__1__DR EQU CYREG_PRT5_DR
+SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In_DBx__1__MASK EQU 0x04
+SCSI_In_DBx__1__PC EQU CYREG_PRT5_PC2
+SCSI_In_DBx__1__PORT EQU 5
+SCSI_In_DBx__1__PRT EQU CYREG_PRT5_PRT
+SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In_DBx__1__PS EQU CYREG_PRT5_PS
+SCSI_In_DBx__1__SHIFT EQU 2
+SCSI_In_DBx__1__SLW EQU CYREG_PRT5_SLW
+SCSI_In_DBx__2__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__2__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__2__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__2__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__2__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__2__MASK EQU 0x80
+SCSI_In_DBx__2__PC EQU CYREG_PRT6_PC7
+SCSI_In_DBx__2__PORT EQU 6
+SCSI_In_DBx__2__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__2__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__2__SHIFT EQU 7
+SCSI_In_DBx__2__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__3__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__3__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__3__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__3__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__3__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__3__MASK EQU 0x40
+SCSI_In_DBx__3__PC EQU CYREG_PRT6_PC6
+SCSI_In_DBx__3__PORT EQU 6
+SCSI_In_DBx__3__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__3__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__3__SHIFT EQU 6
+SCSI_In_DBx__3__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__4__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__4__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__4__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__4__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__4__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__4__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__4__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__4__MASK EQU 0x20
+SCSI_In_DBx__4__PC EQU CYREG_PRT12_PC5
+SCSI_In_DBx__4__PORT EQU 12
+SCSI_In_DBx__4__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__4__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__4__SHIFT EQU 5
+SCSI_In_DBx__4__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__4__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__5__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__5__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__5__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__5__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__5__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__5__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__5__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__5__MASK EQU 0x10
+SCSI_In_DBx__5__PC EQU CYREG_PRT12_PC4
+SCSI_In_DBx__5__PORT EQU 12
+SCSI_In_DBx__5__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__5__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__5__SHIFT EQU 4
+SCSI_In_DBx__5__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__5__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__6__MASK EQU 0x20
+SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC5
+SCSI_In_DBx__6__PORT EQU 2
+SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__6__SHIFT EQU 5
+SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__7__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__7__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__7__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__7__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__7__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__7__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__7__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__7__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__7__MASK EQU 0x10
+SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC4
+SCSI_In_DBx__7__PORT EQU 2
+SCSI_In_DBx__7__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__7__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__7__SHIFT EQU 4
+SCSI_In_DBx__7__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB0__AG EQU CYREG_PRT5_AG
+SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In_DBx__DB0__BIE EQU CYREG_PRT5_BIE
+SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In_DBx__DB0__BYP EQU CYREG_PRT5_BYP
+SCSI_In_DBx__DB0__CTL EQU CYREG_PRT5_CTL
+SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
+SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
+SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
+SCSI_In_DBx__DB0__DR EQU CYREG_PRT5_DR
+SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In_DBx__DB0__MASK EQU 0x08
+SCSI_In_DBx__DB0__PC EQU CYREG_PRT5_PC3
+SCSI_In_DBx__DB0__PORT EQU 5
+SCSI_In_DBx__DB0__PRT EQU CYREG_PRT5_PRT
+SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In_DBx__DB0__PS EQU CYREG_PRT5_PS
+SCSI_In_DBx__DB0__SHIFT EQU 3
+SCSI_In_DBx__DB0__SLW EQU CYREG_PRT5_SLW
+SCSI_In_DBx__DB1__AG EQU CYREG_PRT5_AG
+SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_In_DBx__DB1__BIE EQU CYREG_PRT5_BIE
+SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_In_DBx__DB1__BYP EQU CYREG_PRT5_BYP
+SCSI_In_DBx__DB1__CTL EQU CYREG_PRT5_CTL
+SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
+SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
+SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
+SCSI_In_DBx__DB1__DR EQU CYREG_PRT5_DR
+SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_In_DBx__DB1__MASK EQU 0x04
+SCSI_In_DBx__DB1__PC EQU CYREG_PRT5_PC2
+SCSI_In_DBx__DB1__PORT EQU 5
+SCSI_In_DBx__DB1__PRT EQU CYREG_PRT5_PRT
+SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_In_DBx__DB1__PS EQU CYREG_PRT5_PS
+SCSI_In_DBx__DB1__SHIFT EQU 2
+SCSI_In_DBx__DB1__SLW EQU CYREG_PRT5_SLW
+SCSI_In_DBx__DB2__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__DB2__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__DB2__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__DB2__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__DB2__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__DB2__MASK EQU 0x80
+SCSI_In_DBx__DB2__PC EQU CYREG_PRT6_PC7
+SCSI_In_DBx__DB2__PORT EQU 6
+SCSI_In_DBx__DB2__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__DB2__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__DB2__SHIFT EQU 7
+SCSI_In_DBx__DB2__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__DB3__AG EQU CYREG_PRT6_AG
+SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_In_DBx__DB3__BIE EQU CYREG_PRT6_BIE
+SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_In_DBx__DB3__BYP EQU CYREG_PRT6_BYP
+SCSI_In_DBx__DB3__CTL EQU CYREG_PRT6_CTL
+SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
+SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
+SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
+SCSI_In_DBx__DB3__DR EQU CYREG_PRT6_DR
+SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_In_DBx__DB3__MASK EQU 0x40
+SCSI_In_DBx__DB3__PC EQU CYREG_PRT6_PC6
+SCSI_In_DBx__DB3__PORT EQU 6
+SCSI_In_DBx__DB3__PRT EQU CYREG_PRT6_PRT
+SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_In_DBx__DB3__PS EQU CYREG_PRT6_PS
+SCSI_In_DBx__DB3__SHIFT EQU 6
+SCSI_In_DBx__DB3__SLW EQU CYREG_PRT6_SLW
+SCSI_In_DBx__DB4__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__DB4__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__DB4__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__DB4__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__DB4__MASK EQU 0x20
+SCSI_In_DBx__DB4__PC EQU CYREG_PRT12_PC5
+SCSI_In_DBx__DB4__PORT EQU 12
+SCSI_In_DBx__DB4__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__DB4__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__DB4__SHIFT EQU 5
+SCSI_In_DBx__DB4__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__DB4__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__DB4__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__DB4__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__DB4__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__DB5__AG EQU CYREG_PRT12_AG
+SCSI_In_DBx__DB5__BIE EQU CYREG_PRT12_BIE
+SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT12_BIT_MASK
+SCSI_In_DBx__DB5__BYP EQU CYREG_PRT12_BYP
+SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT12_DM0
+SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT12_DM1
+SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT12_DM2
+SCSI_In_DBx__DB5__DR EQU CYREG_PRT12_DR
+SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT12_INP_DIS
+SCSI_In_DBx__DB5__MASK EQU 0x10
+SCSI_In_DBx__DB5__PC EQU CYREG_PRT12_PC4
+SCSI_In_DBx__DB5__PORT EQU 12
+SCSI_In_DBx__DB5__PRT EQU CYREG_PRT12_PRT
+SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
+SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
+SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
+SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
+SCSI_In_DBx__DB5__PS EQU CYREG_PRT12_PS
+SCSI_In_DBx__DB5__SHIFT EQU 4
+SCSI_In_DBx__DB5__SIO_CFG EQU CYREG_PRT12_SIO_CFG
+SCSI_In_DBx__DB5__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
+SCSI_In_DBx__DB5__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
+SCSI_In_DBx__DB5__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
+SCSI_In_DBx__DB5__SLW EQU CYREG_PRT12_SLW
+SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB6__MASK EQU 0x20
+SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC5
+SCSI_In_DBx__DB6__PORT EQU 2
+SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB6__SHIFT EQU 5
+SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW
+SCSI_In_DBx__DB7__AG EQU CYREG_PRT2_AG
+SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_In_DBx__DB7__BIE EQU CYREG_PRT2_BIE
+SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_In_DBx__DB7__BYP EQU CYREG_PRT2_BYP
+SCSI_In_DBx__DB7__CTL EQU CYREG_PRT2_CTL
+SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
+SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
+SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
+SCSI_In_DBx__DB7__DR EQU CYREG_PRT2_DR
+SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_In_DBx__DB7__MASK EQU 0x10
+SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC4
+SCSI_In_DBx__DB7__PORT EQU 2
+SCSI_In_DBx__DB7__PRT EQU CYREG_PRT2_PRT
+SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_In_DBx__DB7__PS EQU CYREG_PRT2_PS
+SCSI_In_DBx__DB7__SHIFT EQU 4
+SCSI_In_DBx__DB7__SLW EQU CYREG_PRT2_SLW
+
+; SD_MISO
+SD_MISO__0__MASK EQU 0x02
+SD_MISO__0__PC EQU CYREG_PRT3_PC1
+SD_MISO__0__PORT EQU 3
+SD_MISO__0__SHIFT EQU 1
+SD_MISO__AG EQU CYREG_PRT3_AG
+SD_MISO__AMUX EQU CYREG_PRT3_AMUX
+SD_MISO__BIE EQU CYREG_PRT3_BIE
+SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_MISO__BYP EQU CYREG_PRT3_BYP
+SD_MISO__CTL EQU CYREG_PRT3_CTL
+SD_MISO__DM0 EQU CYREG_PRT3_DM0
+SD_MISO__DM1 EQU CYREG_PRT3_DM1
+SD_MISO__DM2 EQU CYREG_PRT3_DM2
+SD_MISO__DR EQU CYREG_PRT3_DR
+SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_MISO__MASK EQU 0x02
+SD_MISO__PORT EQU 3
+SD_MISO__PRT EQU CYREG_PRT3_PRT
+SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_MISO__PS EQU CYREG_PRT3_PS
+SD_MISO__SHIFT EQU 1
+SD_MISO__SLW EQU CYREG_PRT3_SLW
+
+; SD_MOSI
+SD_MOSI__0__MASK EQU 0x08
+SD_MOSI__0__PC EQU CYREG_PRT3_PC3
+SD_MOSI__0__PORT EQU 3
+SD_MOSI__0__SHIFT EQU 3
+SD_MOSI__AG EQU CYREG_PRT3_AG
+SD_MOSI__AMUX EQU CYREG_PRT3_AMUX
+SD_MOSI__BIE EQU CYREG_PRT3_BIE
+SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_MOSI__BYP EQU CYREG_PRT3_BYP
+SD_MOSI__CTL EQU CYREG_PRT3_CTL
+SD_MOSI__DM0 EQU CYREG_PRT3_DM0
+SD_MOSI__DM1 EQU CYREG_PRT3_DM1
+SD_MOSI__DM2 EQU CYREG_PRT3_DM2
+SD_MOSI__DR EQU CYREG_PRT3_DR
+SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_MOSI__MASK EQU 0x08
+SD_MOSI__PORT EQU 3
+SD_MOSI__PRT EQU CYREG_PRT3_PRT
+SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_MOSI__PS EQU CYREG_PRT3_PS
+SD_MOSI__SHIFT EQU 3
+SD_MOSI__SLW EQU CYREG_PRT3_SLW
+
+; SCSI_CLK
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
+SCSI_CLK__INDEX EQU 0x01
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SCSI_CLK__PM_ACT_MSK EQU 0x02
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SCSI_CLK__PM_STBY_MSK EQU 0x02
+
+; SCSI_Out
+SCSI_Out__0__AG EQU CYREG_PRT15_AG
+SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out__0__BIE EQU CYREG_PRT15_BIE
+SCSI_Out__0__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out__0__BYP EQU CYREG_PRT15_BYP
+SCSI_Out__0__CTL EQU CYREG_PRT15_CTL
+SCSI_Out__0__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out__0__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out__0__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out__0__DR EQU CYREG_PRT15_DR
+SCSI_Out__0__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out__0__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out__0__MASK EQU 0x20
+SCSI_Out__0__PC EQU CYREG_IO_PC_PRT15_PC5
+SCSI_Out__0__PORT EQU 15
+SCSI_Out__0__PRT EQU CYREG_PRT15_PRT
+SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out__0__PS EQU CYREG_PRT15_PS
+SCSI_Out__0__SHIFT EQU 5
+SCSI_Out__0__SLW EQU CYREG_PRT15_SLW
+SCSI_Out__1__AG EQU CYREG_PRT15_AG
+SCSI_Out__1__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out__1__BIE EQU CYREG_PRT15_BIE
+SCSI_Out__1__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out__1__BYP EQU CYREG_PRT15_BYP
+SCSI_Out__1__CTL EQU CYREG_PRT15_CTL
+SCSI_Out__1__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out__1__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out__1__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out__1__DR EQU CYREG_PRT15_DR
+SCSI_Out__1__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out__1__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out__1__MASK EQU 0x10
+SCSI_Out__1__PC EQU CYREG_IO_PC_PRT15_PC4
+SCSI_Out__1__PORT EQU 15
+SCSI_Out__1__PRT EQU CYREG_PRT15_PRT
+SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out__1__PS EQU CYREG_PRT15_PS
+SCSI_Out__1__SHIFT EQU 4
+SCSI_Out__1__SLW EQU CYREG_PRT15_SLW
+SCSI_Out__2__AG EQU CYREG_PRT6_AG
+SCSI_Out__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__2__DR EQU CYREG_PRT6_DR
+SCSI_Out__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__2__MASK EQU 0x02
+SCSI_Out__2__PC EQU CYREG_PRT6_PC1
+SCSI_Out__2__PORT EQU 6
+SCSI_Out__2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__2__PS EQU CYREG_PRT6_PS
+SCSI_Out__2__SHIFT EQU 1
+SCSI_Out__2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__3__AG EQU CYREG_PRT6_AG
+SCSI_Out__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__3__DR EQU CYREG_PRT6_DR
+SCSI_Out__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__3__MASK EQU 0x01
+SCSI_Out__3__PC EQU CYREG_PRT6_PC0
+SCSI_Out__3__PORT EQU 6
+SCSI_Out__3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__3__PS EQU CYREG_PRT6_PS
+SCSI_Out__3__SHIFT EQU 0
+SCSI_Out__3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__4__AG EQU CYREG_PRT4_AG
+SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__4__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__4__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__4__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__4__DR EQU CYREG_PRT4_DR
+SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__4__MASK EQU 0x20
+SCSI_Out__4__PC EQU CYREG_PRT4_PC5
+SCSI_Out__4__PORT EQU 4
+SCSI_Out__4__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__4__PS EQU CYREG_PRT4_PS
+SCSI_Out__4__SHIFT EQU 5
+SCSI_Out__4__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__5__AG EQU CYREG_PRT4_AG
+SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__5__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__5__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__5__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__5__DR EQU CYREG_PRT4_DR
+SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__5__MASK EQU 0x10
+SCSI_Out__5__PC EQU CYREG_PRT4_PC4
+SCSI_Out__5__PORT EQU 4
+SCSI_Out__5__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__5__PS EQU CYREG_PRT4_PS
+SCSI_Out__5__SHIFT EQU 4
+SCSI_Out__5__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__6__AG EQU CYREG_PRT0_AG
+SCSI_Out__6__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__6__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__6__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__6__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__6__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__6__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__6__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__6__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__6__DR EQU CYREG_PRT0_DR
+SCSI_Out__6__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__6__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__6__MASK EQU 0x80
+SCSI_Out__6__PC EQU CYREG_PRT0_PC7
+SCSI_Out__6__PORT EQU 0
+SCSI_Out__6__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__6__PS EQU CYREG_PRT0_PS
+SCSI_Out__6__SHIFT EQU 7
+SCSI_Out__6__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__7__AG EQU CYREG_PRT0_AG
+SCSI_Out__7__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__7__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__7__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__7__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__7__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__7__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__7__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__7__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__7__DR EQU CYREG_PRT0_DR
+SCSI_Out__7__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__7__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__7__MASK EQU 0x40
+SCSI_Out__7__PC EQU CYREG_PRT0_PC6
+SCSI_Out__7__PORT EQU 0
+SCSI_Out__7__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__7__PS EQU CYREG_PRT0_PS
+SCSI_Out__7__SHIFT EQU 6
+SCSI_Out__7__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__8__AG EQU CYREG_PRT0_AG
+SCSI_Out__8__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__8__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__8__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__8__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__8__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__8__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__8__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__8__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__8__DR EQU CYREG_PRT0_DR
+SCSI_Out__8__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__8__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__8__MASK EQU 0x08
+SCSI_Out__8__PC EQU CYREG_PRT0_PC3
+SCSI_Out__8__PORT EQU 0
+SCSI_Out__8__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__8__PS EQU CYREG_PRT0_PS
+SCSI_Out__8__SHIFT EQU 3
+SCSI_Out__8__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__9__AG EQU CYREG_PRT0_AG
+SCSI_Out__9__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__9__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__9__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__9__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__9__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__9__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__9__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__9__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__9__DR EQU CYREG_PRT0_DR
+SCSI_Out__9__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__9__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__9__MASK EQU 0x04
+SCSI_Out__9__PC EQU CYREG_PRT0_PC2
+SCSI_Out__9__PORT EQU 0
+SCSI_Out__9__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__9__PS EQU CYREG_PRT0_PS
+SCSI_Out__9__SHIFT EQU 2
+SCSI_Out__9__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__ACK__AG EQU CYREG_PRT6_AG
+SCSI_Out__ACK__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__ACK__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__ACK__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__ACK__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__ACK__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__ACK__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__ACK__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__ACK__DR EQU CYREG_PRT6_DR
+SCSI_Out__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__ACK__MASK EQU 0x01
+SCSI_Out__ACK__PC EQU CYREG_PRT6_PC0
+SCSI_Out__ACK__PORT EQU 6
+SCSI_Out__ACK__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__ACK__PS EQU CYREG_PRT6_PS
+SCSI_Out__ACK__SHIFT EQU 0
+SCSI_Out__ACK__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__ATN__AG EQU CYREG_PRT15_AG
+SCSI_Out__ATN__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out__ATN__BIE EQU CYREG_PRT15_BIE
+SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out__ATN__BYP EQU CYREG_PRT15_BYP
+SCSI_Out__ATN__CTL EQU CYREG_PRT15_CTL
+SCSI_Out__ATN__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out__ATN__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out__ATN__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out__ATN__DR EQU CYREG_PRT15_DR
+SCSI_Out__ATN__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out__ATN__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out__ATN__MASK EQU 0x10
+SCSI_Out__ATN__PC EQU CYREG_IO_PC_PRT15_PC4
+SCSI_Out__ATN__PORT EQU 15
+SCSI_Out__ATN__PRT EQU CYREG_PRT15_PRT
+SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out__ATN__PS EQU CYREG_PRT15_PS
+SCSI_Out__ATN__SHIFT EQU 4
+SCSI_Out__ATN__SLW EQU CYREG_PRT15_SLW
+SCSI_Out__BSY__AG EQU CYREG_PRT6_AG
+SCSI_Out__BSY__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out__BSY__BIE EQU CYREG_PRT6_BIE
+SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out__BSY__BYP EQU CYREG_PRT6_BYP
+SCSI_Out__BSY__CTL EQU CYREG_PRT6_CTL
+SCSI_Out__BSY__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out__BSY__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out__BSY__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out__BSY__DR EQU CYREG_PRT6_DR
+SCSI_Out__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out__BSY__MASK EQU 0x02
+SCSI_Out__BSY__PC EQU CYREG_PRT6_PC1
+SCSI_Out__BSY__PORT EQU 6
+SCSI_Out__BSY__PRT EQU CYREG_PRT6_PRT
+SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out__BSY__PS EQU CYREG_PRT6_PS
+SCSI_Out__BSY__SHIFT EQU 1
+SCSI_Out__BSY__SLW EQU CYREG_PRT6_SLW
+SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__CD_raw__MASK EQU 0x40
+SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC6
+SCSI_Out__CD_raw__PORT EQU 0
+SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__CD_raw__SHIFT EQU 6
+SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__DBP_raw__AG EQU CYREG_PRT15_AG
+SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT15_AMUX
+SCSI_Out__DBP_raw__BIE EQU CYREG_PRT15_BIE
+SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+SCSI_Out__DBP_raw__BYP EQU CYREG_PRT15_BYP
+SCSI_Out__DBP_raw__CTL EQU CYREG_PRT15_CTL
+SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT15_DM0
+SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT15_DM1
+SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT15_DM2
+SCSI_Out__DBP_raw__DR EQU CYREG_PRT15_DR
+SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT15_INP_DIS
+SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT15_LCD_EN
+SCSI_Out__DBP_raw__MASK EQU 0x20
+SCSI_Out__DBP_raw__PC EQU CYREG_IO_PC_PRT15_PC5
+SCSI_Out__DBP_raw__PORT EQU 15
+SCSI_Out__DBP_raw__PRT EQU CYREG_PRT15_PRT
+SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+SCSI_Out__DBP_raw__PS EQU CYREG_PRT15_PS
+SCSI_Out__DBP_raw__SHIFT EQU 5
+SCSI_Out__DBP_raw__SLW EQU CYREG_PRT15_SLW
+SCSI_Out__IO_raw__AG EQU CYREG_PRT0_AG
+SCSI_Out__IO_raw__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__IO_raw__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__IO_raw__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__IO_raw__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__IO_raw__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__IO_raw__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__IO_raw__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__IO_raw__DR EQU CYREG_PRT0_DR
+SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__IO_raw__MASK EQU 0x04
+SCSI_Out__IO_raw__PC EQU CYREG_PRT0_PC2
+SCSI_Out__IO_raw__PORT EQU 0
+SCSI_Out__IO_raw__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__IO_raw__PS EQU CYREG_PRT0_PS
+SCSI_Out__IO_raw__SHIFT EQU 2
+SCSI_Out__IO_raw__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__MSG_raw__AG EQU CYREG_PRT4_AG
+SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__MSG_raw__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__MSG_raw__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__MSG_raw__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__MSG_raw__DR EQU CYREG_PRT4_DR
+SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__MSG_raw__MASK EQU 0x10
+SCSI_Out__MSG_raw__PC EQU CYREG_PRT4_PC4
+SCSI_Out__MSG_raw__PORT EQU 4
+SCSI_Out__MSG_raw__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__MSG_raw__PS EQU CYREG_PRT4_PS
+SCSI_Out__MSG_raw__SHIFT EQU 4
+SCSI_Out__MSG_raw__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__REQ__AG EQU CYREG_PRT0_AG
+SCSI_Out__REQ__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__REQ__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__REQ__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__REQ__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__REQ__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__REQ__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__REQ__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__REQ__DR EQU CYREG_PRT0_DR
+SCSI_Out__REQ__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__REQ__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__REQ__MASK EQU 0x08
+SCSI_Out__REQ__PC EQU CYREG_PRT0_PC3
+SCSI_Out__REQ__PORT EQU 0
+SCSI_Out__REQ__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__REQ__PS EQU CYREG_PRT0_PS
+SCSI_Out__REQ__SHIFT EQU 3
+SCSI_Out__REQ__SLW EQU CYREG_PRT0_SLW
+SCSI_Out__RST__AG EQU CYREG_PRT4_AG
+SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE
+SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP
+SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL
+SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0
+SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1
+SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2
+SCSI_Out__RST__DR EQU CYREG_PRT4_DR
+SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Out__RST__MASK EQU 0x20
+SCSI_Out__RST__PC EQU CYREG_PRT4_PC5
+SCSI_Out__RST__PORT EQU 4
+SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT
+SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Out__RST__PS EQU CYREG_PRT4_PS
+SCSI_Out__RST__SHIFT EQU 5
+SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW
+SCSI_Out__SEL__AG EQU CYREG_PRT0_AG
+SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX
+SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE
+SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP
+SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL
+SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0
+SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1
+SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2
+SCSI_Out__SEL__DR EQU CYREG_PRT0_DR
+SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS
+SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN
+SCSI_Out__SEL__MASK EQU 0x80
+SCSI_Out__SEL__PC EQU CYREG_PRT0_PC7
+SCSI_Out__SEL__PORT EQU 0
+SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT
+SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+SCSI_Out__SEL__PS EQU CYREG_PRT0_PS
+SCSI_Out__SEL__SHIFT EQU 7
+SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
+
+; SCSI_Out_Bits
+SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
+SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
+SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
+SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
+SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
+SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3
+SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10
+SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4
+SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20
+SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5
+SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
+SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
+SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
+SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
+
+; SCSI_Out_Ctl
+SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
+
+; SCSI_Out_DBx
+SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__0__MASK EQU 0x02
+SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1
+SCSI_Out_DBx__0__PORT EQU 5
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__0__SHIFT EQU 1
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__1__MASK EQU 0x01
+SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0
+SCSI_Out_DBx__1__PORT EQU 5
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__1__SHIFT EQU 0
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__2__MASK EQU 0x20
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__2__PORT EQU 6
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__2__SHIFT EQU 5
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__3__MASK EQU 0x10
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4
+SCSI_Out_DBx__3__PORT EQU 6
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__3__SHIFT EQU 4
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__4__MASK EQU 0x80
+SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__4__PORT EQU 2
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__4__SHIFT EQU 7
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__5__MASK EQU 0x40
+SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6
+SCSI_Out_DBx__5__PORT EQU 2
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__5__SHIFT EQU 6
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__6__MASK EQU 0x08
+SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__6__PORT EQU 2
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__6__SHIFT EQU 3
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__7__MASK EQU 0x04
+SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2
+SCSI_Out_DBx__7__PORT EQU 2
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__7__SHIFT EQU 2
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__DB0__MASK EQU 0x02
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1
+SCSI_Out_DBx__DB0__PORT EQU 5
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__DB0__SHIFT EQU 1
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__DB1__MASK EQU 0x01
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0
+SCSI_Out_DBx__DB1__PORT EQU 5
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__DB1__SHIFT EQU 0
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB2__MASK EQU 0x20
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__DB2__PORT EQU 6
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB2__SHIFT EQU 5
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB3__MASK EQU 0x10
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4
+SCSI_Out_DBx__DB3__PORT EQU 6
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB3__SHIFT EQU 4
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB4__MASK EQU 0x80
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__DB4__PORT EQU 2
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB4__SHIFT EQU 7
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB5__MASK EQU 0x40
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6
+SCSI_Out_DBx__DB5__PORT EQU 2
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB5__SHIFT EQU 6
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB6__MASK EQU 0x08
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__DB6__PORT EQU 2
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB6__SHIFT EQU 3
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB7__MASK EQU 0x04
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2
+SCSI_Out_DBx__DB7__PORT EQU 2
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB7__SHIFT EQU 2
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
+
+; SD_RX_DMA
+SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SD_RX_DMA__DRQ_NUMBER EQU 2
+SD_RX_DMA__NUMBEROF_TDS EQU 0
+SD_RX_DMA__PRIORITY EQU 2
+SD_RX_DMA__TERMIN_EN EQU 0
+SD_RX_DMA__TERMIN_SEL EQU 0
+SD_RX_DMA__TERMOUT0_EN EQU 1
+SD_RX_DMA__TERMOUT0_SEL EQU 2
+SD_RX_DMA__TERMOUT1_EN EQU 0
+SD_RX_DMA__TERMOUT1_SEL EQU 0
+
+; SD_RX_DMA_COMPLETE
+SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x10
+SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 4
+SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4
+SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; SD_TX_DMA
+SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SD_TX_DMA__DRQ_NUMBER EQU 3
+SD_TX_DMA__NUMBEROF_TDS EQU 0
+SD_TX_DMA__PRIORITY EQU 2
+SD_TX_DMA__TERMIN_EN EQU 0
+SD_TX_DMA__TERMIN_SEL EQU 0
+SD_TX_DMA__TERMOUT0_EN EQU 1
+SD_TX_DMA__TERMOUT0_SEL EQU 3
+SD_TX_DMA__TERMOUT1_EN EQU 0
+SD_TX_DMA__TERMOUT1_SEL EQU 0
+
+; SD_TX_DMA_COMPLETE
+SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x20
+SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 5
+SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5
+SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; SCSI_Noise
+SCSI_Noise__0__AG EQU CYREG_PRT2_AG
+SCSI_Noise__0__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Noise__0__BIE EQU CYREG_PRT2_BIE
+SCSI_Noise__0__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Noise__0__BYP EQU CYREG_PRT2_BYP
+SCSI_Noise__0__CTL EQU CYREG_PRT2_CTL
+SCSI_Noise__0__DM0 EQU CYREG_PRT2_DM0
+SCSI_Noise__0__DM1 EQU CYREG_PRT2_DM1
+SCSI_Noise__0__DM2 EQU CYREG_PRT2_DM2
+SCSI_Noise__0__DR EQU CYREG_PRT2_DR
+SCSI_Noise__0__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Noise__0__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Noise__0__MASK EQU 0x01
+SCSI_Noise__0__PC EQU CYREG_PRT2_PC0
+SCSI_Noise__0__PORT EQU 2
+SCSI_Noise__0__PRT EQU CYREG_PRT2_PRT
+SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Noise__0__PS EQU CYREG_PRT2_PS
+SCSI_Noise__0__SHIFT EQU 0
+SCSI_Noise__0__SLW EQU CYREG_PRT2_SLW
+SCSI_Noise__1__AG EQU CYREG_PRT6_AG
+SCSI_Noise__1__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__1__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__1__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__1__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__1__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__1__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__1__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__1__DR EQU CYREG_PRT6_DR
+SCSI_Noise__1__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__1__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__1__MASK EQU 0x08
+SCSI_Noise__1__PC EQU CYREG_PRT6_PC3
+SCSI_Noise__1__PORT EQU 6
+SCSI_Noise__1__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__1__PS EQU CYREG_PRT6_PS
+SCSI_Noise__1__SHIFT EQU 3
+SCSI_Noise__1__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__2__AG EQU CYREG_PRT4_AG
+SCSI_Noise__2__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__2__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__2__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__2__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__2__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__2__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__2__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__2__DR EQU CYREG_PRT4_DR
+SCSI_Noise__2__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__2__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__2__MASK EQU 0x08
+SCSI_Noise__2__PC EQU CYREG_PRT4_PC3
+SCSI_Noise__2__PORT EQU 4
+SCSI_Noise__2__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__2__PS EQU CYREG_PRT4_PS
+SCSI_Noise__2__SHIFT EQU 3
+SCSI_Noise__2__SLW EQU CYREG_PRT4_SLW
+SCSI_Noise__3__AG EQU CYREG_PRT4_AG
+SCSI_Noise__3__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__3__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__3__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__3__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__3__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__3__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__3__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__3__DR EQU CYREG_PRT4_DR
+SCSI_Noise__3__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__3__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__3__MASK EQU 0x80
+SCSI_Noise__3__PC EQU CYREG_PRT4_PC7
+SCSI_Noise__3__PORT EQU 4
+SCSI_Noise__3__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__3__PS EQU CYREG_PRT4_PS
+SCSI_Noise__3__SHIFT EQU 7
+SCSI_Noise__3__SLW EQU CYREG_PRT4_SLW
+SCSI_Noise__4__AG EQU CYREG_PRT6_AG
+SCSI_Noise__4__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__4__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__4__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__4__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__4__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__4__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__4__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__4__DR EQU CYREG_PRT6_DR
+SCSI_Noise__4__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__4__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__4__MASK EQU 0x04
+SCSI_Noise__4__PC EQU CYREG_PRT6_PC2
+SCSI_Noise__4__PORT EQU 6
+SCSI_Noise__4__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__4__PS EQU CYREG_PRT6_PS
+SCSI_Noise__4__SHIFT EQU 2
+SCSI_Noise__4__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__ACK__AG EQU CYREG_PRT6_AG
+SCSI_Noise__ACK__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__ACK__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__ACK__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__ACK__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__ACK__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__ACK__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__ACK__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__ACK__DR EQU CYREG_PRT6_DR
+SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__ACK__MASK EQU 0x04
+SCSI_Noise__ACK__PC EQU CYREG_PRT6_PC2
+SCSI_Noise__ACK__PORT EQU 6
+SCSI_Noise__ACK__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__ACK__PS EQU CYREG_PRT6_PS
+SCSI_Noise__ACK__SHIFT EQU 2
+SCSI_Noise__ACK__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__ATN__AG EQU CYREG_PRT2_AG
+SCSI_Noise__ATN__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Noise__ATN__BIE EQU CYREG_PRT2_BIE
+SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Noise__ATN__BYP EQU CYREG_PRT2_BYP
+SCSI_Noise__ATN__CTL EQU CYREG_PRT2_CTL
+SCSI_Noise__ATN__DM0 EQU CYREG_PRT2_DM0
+SCSI_Noise__ATN__DM1 EQU CYREG_PRT2_DM1
+SCSI_Noise__ATN__DM2 EQU CYREG_PRT2_DM2
+SCSI_Noise__ATN__DR EQU CYREG_PRT2_DR
+SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Noise__ATN__MASK EQU 0x01
+SCSI_Noise__ATN__PC EQU CYREG_PRT2_PC0
+SCSI_Noise__ATN__PORT EQU 2
+SCSI_Noise__ATN__PRT EQU CYREG_PRT2_PRT
+SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Noise__ATN__PS EQU CYREG_PRT2_PS
+SCSI_Noise__ATN__SHIFT EQU 0
+SCSI_Noise__ATN__SLW EQU CYREG_PRT2_SLW
+SCSI_Noise__BSY__AG EQU CYREG_PRT6_AG
+SCSI_Noise__BSY__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Noise__BSY__BIE EQU CYREG_PRT6_BIE
+SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Noise__BSY__BYP EQU CYREG_PRT6_BYP
+SCSI_Noise__BSY__CTL EQU CYREG_PRT6_CTL
+SCSI_Noise__BSY__DM0 EQU CYREG_PRT6_DM0
+SCSI_Noise__BSY__DM1 EQU CYREG_PRT6_DM1
+SCSI_Noise__BSY__DM2 EQU CYREG_PRT6_DM2
+SCSI_Noise__BSY__DR EQU CYREG_PRT6_DR
+SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Noise__BSY__MASK EQU 0x08
+SCSI_Noise__BSY__PC EQU CYREG_PRT6_PC3
+SCSI_Noise__BSY__PORT EQU 6
+SCSI_Noise__BSY__PRT EQU CYREG_PRT6_PRT
+SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Noise__BSY__PS EQU CYREG_PRT6_PS
+SCSI_Noise__BSY__SHIFT EQU 3
+SCSI_Noise__BSY__SLW EQU CYREG_PRT6_SLW
+SCSI_Noise__RST__AG EQU CYREG_PRT4_AG
+SCSI_Noise__RST__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__RST__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__RST__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__RST__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__RST__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__RST__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__RST__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__RST__DR EQU CYREG_PRT4_DR
+SCSI_Noise__RST__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__RST__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__RST__MASK EQU 0x80
+SCSI_Noise__RST__PC EQU CYREG_PRT4_PC7
+SCSI_Noise__RST__PORT EQU 4
+SCSI_Noise__RST__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__RST__PS EQU CYREG_PRT4_PS
+SCSI_Noise__RST__SHIFT EQU 7
+SCSI_Noise__RST__SLW EQU CYREG_PRT4_SLW
+SCSI_Noise__SEL__AG EQU CYREG_PRT4_AG
+SCSI_Noise__SEL__AMUX EQU CYREG_PRT4_AMUX
+SCSI_Noise__SEL__BIE EQU CYREG_PRT4_BIE
+SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT4_BIT_MASK
+SCSI_Noise__SEL__BYP EQU CYREG_PRT4_BYP
+SCSI_Noise__SEL__CTL EQU CYREG_PRT4_CTL
+SCSI_Noise__SEL__DM0 EQU CYREG_PRT4_DM0
+SCSI_Noise__SEL__DM1 EQU CYREG_PRT4_DM1
+SCSI_Noise__SEL__DM2 EQU CYREG_PRT4_DM2
+SCSI_Noise__SEL__DR EQU CYREG_PRT4_DR
+SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT4_INP_DIS
+SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG
+SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT4_LCD_EN
+SCSI_Noise__SEL__MASK EQU 0x08
+SCSI_Noise__SEL__PC EQU CYREG_PRT4_PC3
+SCSI_Noise__SEL__PORT EQU 4
+SCSI_Noise__SEL__PRT EQU CYREG_PRT4_PRT
+SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL
+SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN
+SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0
+SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1
+SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0
+SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1
+SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT
+SCSI_Noise__SEL__PS EQU CYREG_PRT4_PS
+SCSI_Noise__SEL__SHIFT EQU 3
+SCSI_Noise__SEL__SLW EQU CYREG_PRT4_SLW
+
+; scsiTarget
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_StatusReg__0__MASK EQU 0x01
+scsiTarget_StatusReg__0__POS EQU 0
+scsiTarget_StatusReg__1__MASK EQU 0x02
+scsiTarget_StatusReg__1__POS EQU 1
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST
+scsiTarget_StatusReg__2__MASK EQU 0x04
+scsiTarget_StatusReg__2__POS EQU 2
+scsiTarget_StatusReg__3__MASK EQU 0x08
+scsiTarget_StatusReg__3__POS EQU 3
+scsiTarget_StatusReg__4__MASK EQU 0x10
+scsiTarget_StatusReg__4__POS EQU 4
+scsiTarget_StatusReg__MASK EQU 0x1F
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST
-; SD_MOSI
-SD_MOSI__0__MASK EQU 0x08
-SD_MOSI__0__PC EQU CYREG_PRT3_PC3
-SD_MOSI__0__PORT EQU 3
-SD_MOSI__0__SHIFT EQU 3
-SD_MOSI__AG EQU CYREG_PRT3_AG
-SD_MOSI__AMUX EQU CYREG_PRT3_AMUX
-SD_MOSI__BIE EQU CYREG_PRT3_BIE
-SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_MOSI__BYP EQU CYREG_PRT3_BYP
-SD_MOSI__CTL EQU CYREG_PRT3_CTL
-SD_MOSI__DM0 EQU CYREG_PRT3_DM0
-SD_MOSI__DM1 EQU CYREG_PRT3_DM1
-SD_MOSI__DM2 EQU CYREG_PRT3_DM2
-SD_MOSI__DR EQU CYREG_PRT3_DR
-SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_MOSI__MASK EQU 0x08
-SD_MOSI__PORT EQU 3
-SD_MOSI__PRT EQU CYREG_PRT3_PRT
-SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_MOSI__PS EQU CYREG_PRT3_PS
-SD_MOSI__SHIFT EQU 3
-SD_MOSI__SLW EQU CYREG_PRT3_SLW
+; Debug_Timer_Interrupt
+Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+Debug_Timer_Interrupt__INTC_MASK EQU 0x02
+Debug_Timer_Interrupt__INTC_NUMBER EQU 1
+Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7
+Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
+Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; Debug_Timer_TimerHW
+Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0
+Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1
+Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0
+Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1
+Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2
+Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0
+Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1
+Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0
+Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1
+Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3
+Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01
+Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3
+Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01
+Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0
+Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1
+Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0
+
+; SCSI_RX_DMA
+SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SCSI_RX_DMA__DRQ_NUMBER EQU 0
+SCSI_RX_DMA__NUMBEROF_TDS EQU 0
+SCSI_RX_DMA__PRIORITY EQU 2
+SCSI_RX_DMA__TERMIN_EN EQU 0
+SCSI_RX_DMA__TERMIN_SEL EQU 0
+SCSI_RX_DMA__TERMOUT0_EN EQU 1
+SCSI_RX_DMA__TERMOUT0_SEL EQU 0
+SCSI_RX_DMA__TERMOUT1_EN EQU 0
+SCSI_RX_DMA__TERMOUT1_SEL EQU 0
+
+; SCSI_RX_DMA_COMPLETE
+SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x01
+SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 0
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
+SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; SCSI_TX_DMA
+SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0
+SCSI_TX_DMA__DRQ_NUMBER EQU 1
+SCSI_TX_DMA__NUMBEROF_TDS EQU 0
+SCSI_TX_DMA__PRIORITY EQU 2
+SCSI_TX_DMA__TERMIN_EN EQU 0
+SCSI_TX_DMA__TERMIN_SEL EQU 0
+SCSI_TX_DMA__TERMOUT0_EN EQU 1
+SCSI_TX_DMA__TERMOUT0_SEL EQU 1
+SCSI_TX_DMA__TERMOUT1_EN EQU 0
+SCSI_TX_DMA__TERMOUT1_SEL EQU 0
+
+; SCSI_TX_DMA_COMPLETE
+SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x08
+SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 3
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7
+SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3
+SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; SD_Data_Clk
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2
+SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07
+SD_Data_Clk__INDEX EQU 0x00
+SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SD_Data_Clk__PM_ACT_MSK EQU 0x01
+SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SD_Data_Clk__PM_STBY_MSK EQU 0x01
-; EXTLED
-EXTLED__0__MASK EQU 0x01
-EXTLED__0__PC EQU CYREG_PRT0_PC0
-EXTLED__0__PORT EQU 0
-EXTLED__0__SHIFT EQU 0
-EXTLED__AG EQU CYREG_PRT0_AG
-EXTLED__AMUX EQU CYREG_PRT0_AMUX
-EXTLED__BIE EQU CYREG_PRT0_BIE
-EXTLED__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-EXTLED__BYP EQU CYREG_PRT0_BYP
-EXTLED__CTL EQU CYREG_PRT0_CTL
-EXTLED__DM0 EQU CYREG_PRT0_DM0
-EXTLED__DM1 EQU CYREG_PRT0_DM1
-EXTLED__DM2 EQU CYREG_PRT0_DM2
-EXTLED__DR EQU CYREG_PRT0_DR
-EXTLED__INP_DIS EQU CYREG_PRT0_INP_DIS
-EXTLED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-EXTLED__LCD_EN EQU CYREG_PRT0_LCD_EN
-EXTLED__MASK EQU 0x01
-EXTLED__PORT EQU 0
-EXTLED__PRT EQU CYREG_PRT0_PRT
-EXTLED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-EXTLED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-EXTLED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-EXTLED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-EXTLED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-EXTLED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-EXTLED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-EXTLED__PS EQU CYREG_PRT0_PS
-EXTLED__SHIFT EQU 0
-EXTLED__SLW EQU CYREG_PRT0_SLW
+; timer_clock
+timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
+timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
+timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
+timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
+timer_clock__INDEX EQU 0x02
+timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+timer_clock__PM_ACT_MSK EQU 0x04
+timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+timer_clock__PM_STBY_MSK EQU 0x04
-; SD_SCK
-SD_SCK__0__MASK EQU 0x04
-SD_SCK__0__PC EQU CYREG_PRT3_PC2
-SD_SCK__0__PORT EQU 3
-SD_SCK__0__SHIFT EQU 2
-SD_SCK__AG EQU CYREG_PRT3_AG
-SD_SCK__AMUX EQU CYREG_PRT3_AMUX
-SD_SCK__BIE EQU CYREG_PRT3_BIE
-SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_SCK__BYP EQU CYREG_PRT3_BYP
-SD_SCK__CTL EQU CYREG_PRT3_CTL
-SD_SCK__DM0 EQU CYREG_PRT3_DM0
-SD_SCK__DM1 EQU CYREG_PRT3_DM1
-SD_SCK__DM2 EQU CYREG_PRT3_DM2
-SD_SCK__DR EQU CYREG_PRT3_DR
-SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_SCK__MASK EQU 0x04
-SD_SCK__PORT EQU 3
-SD_SCK__PRT EQU CYREG_PRT3_PRT
-SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_SCK__PS EQU CYREG_PRT3_PS
-SD_SCK__SHIFT EQU 2
-SD_SCK__SLW EQU CYREG_PRT3_SLW
+; SCSI_RST_ISR
+SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+SCSI_RST_ISR__INTC_MASK EQU 0x04
+SCSI_RST_ISR__INTC_NUMBER EQU 2
+SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
+SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2
+SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-; SD_CD
-SD_CD__0__MASK EQU 0x20
-SD_CD__0__PC EQU CYREG_PRT3_PC5
-SD_CD__0__PORT EQU 3
-SD_CD__0__SHIFT EQU 5
-SD_CD__AG EQU CYREG_PRT3_AG
-SD_CD__AMUX EQU CYREG_PRT3_AMUX
-SD_CD__BIE EQU CYREG_PRT3_BIE
-SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_CD__BYP EQU CYREG_PRT3_BYP
-SD_CD__CTL EQU CYREG_PRT3_CTL
-SD_CD__DM0 EQU CYREG_PRT3_DM0
-SD_CD__DM1 EQU CYREG_PRT3_DM1
-SD_CD__DM2 EQU CYREG_PRT3_DM2
-SD_CD__DR EQU CYREG_PRT3_DR
-SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_CD__MASK EQU 0x20
-SD_CD__PORT EQU 3
-SD_CD__PRT EQU CYREG_PRT3_PRT
-SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_CD__PS EQU CYREG_PRT3_PS
-SD_CD__SHIFT EQU 5
-SD_CD__SLW EQU CYREG_PRT3_SLW
+; SCSI_Filtered
+SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Filtered_sts_sts_reg__0__POS EQU 0
+SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
+SCSI_Filtered_sts_sts_reg__1__POS EQU 1
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
+SCSI_Filtered_sts_sts_reg__2__POS EQU 2
+SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
+SCSI_Filtered_sts_sts_reg__3__POS EQU 3
+SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
+SCSI_Filtered_sts_sts_reg__4__POS EQU 4
+SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST
-; SD_CS
-SD_CS__0__MASK EQU 0x10
-SD_CS__0__PC EQU CYREG_PRT3_PC4
-SD_CS__0__PORT EQU 3
-SD_CS__0__SHIFT EQU 4
-SD_CS__AG EQU CYREG_PRT3_AG
-SD_CS__AMUX EQU CYREG_PRT3_AMUX
-SD_CS__BIE EQU CYREG_PRT3_BIE
-SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_CS__BYP EQU CYREG_PRT3_BYP
-SD_CS__CTL EQU CYREG_PRT3_CTL
-SD_CS__DM0 EQU CYREG_PRT3_DM0
-SD_CS__DM1 EQU CYREG_PRT3_DM1
-SD_CS__DM2 EQU CYREG_PRT3_DM2
-SD_CS__DR EQU CYREG_PRT3_DR
-SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_CS__MASK EQU 0x10
-SD_CS__PORT EQU 3
-SD_CS__PRT EQU CYREG_PRT3_PRT
-SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_CS__PS EQU CYREG_PRT3_PS
-SD_CS__SHIFT EQU 4
-SD_CS__SLW EQU CYREG_PRT3_SLW
+; SCSI_CTL_PHASE
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
+SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
+SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
+SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
-; LED1
-LED1__0__MASK EQU 0x02
-LED1__0__PC EQU CYREG_PRT0_PC1
-LED1__0__PORT EQU 0
-LED1__0__SHIFT EQU 1
-LED1__AG EQU CYREG_PRT0_AG
-LED1__AMUX EQU CYREG_PRT0_AMUX
-LED1__BIE EQU CYREG_PRT0_BIE
-LED1__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-LED1__BYP EQU CYREG_PRT0_BYP
-LED1__CTL EQU CYREG_PRT0_CTL
-LED1__DM0 EQU CYREG_PRT0_DM0
-LED1__DM1 EQU CYREG_PRT0_DM1
-LED1__DM2 EQU CYREG_PRT0_DM2
-LED1__DR EQU CYREG_PRT0_DR
-LED1__INP_DIS EQU CYREG_PRT0_INP_DIS
-LED1__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-LED1__LCD_EN EQU CYREG_PRT0_LCD_EN
-LED1__MASK EQU 0x02
-LED1__PORT EQU 0
-LED1__PRT EQU CYREG_PRT0_PRT
-LED1__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-LED1__PS EQU CYREG_PRT0_PS
-LED1__SHIFT EQU 1
-LED1__SLW EQU CYREG_PRT0_SLW
+; SCSI_Parity_Error
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB03_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB03_ST
; Miscellaneous
-; -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release
-CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
-CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
-CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
-CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
-CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
-CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
-CYDEV_CHIP_MEMBER_5B EQU 4
-CYDEV_CHIP_FAMILY_PSOC5 EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 4
-CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP
BCLK__BUS_CLK__HZ EQU 50000000
BCLK__BUS_CLK__KHZ EQU 50000
BCLK__BUS_CLK__MHZ EQU 50
-CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 3
-CYDEV_CHIP_DIE_PSOC4A EQU 2
+CYDEV_CHIP_DIE_PANTHER EQU 6
+CYDEV_CHIP_DIE_PSOC4A EQU 3
+CYDEV_CHIP_DIE_PSOC5LP EQU 5
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
+CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
CYDEV_CHIP_JTAG_ID EQU 0x2E133069
CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 2
-CYDEV_CHIP_MEMBER_5A EQU 3
+CYDEV_CHIP_MEMBER_4A EQU 3
+CYDEV_CHIP_MEMBER_4D EQU 2
+CYDEV_CHIP_MEMBER_4F EQU 4
+CYDEV_CHIP_MEMBER_5A EQU 6
+CYDEV_CHIP_MEMBER_5B EQU 5
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
+CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
+CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
+CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
+CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
+CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
+CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
+CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
+CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
+CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
+CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
+CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
+CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5B_ES0 EQU 0
+CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION
-CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
-CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
-CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
-CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
-CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
-CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
-CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
+CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
+CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
+CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
+CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_DMA EQU 0
CYDEV_CONFIGURATION_ECC EQU 0
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
+CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
-CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
-CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
-CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
+CYDEV_DEBUG_ENABLE_MASK EQU 0x20
+CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
CYDEV_DEBUGGING_DPS_SWD EQU 2
+CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
+CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DEBUGGING_XRES EQU 0
-CYDEV_DEBUG_ENABLE_MASK EQU 0x20
-CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
CYDEV_ECC_ENABLE EQU 0
-CYDEV_HEAP_SIZE EQU 0x1000
+CYDEV_HEAP_SIZE EQU 0x0400
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
CYDEV_INTR_RISING EQU 0x0000003E
CYDEV_PROJ_TYPE EQU 2
CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3
CYDEV_PROJ_TYPE_STANDARD EQU 0
CYDEV_PROTECTION_ENABLE EQU 0
-CYDEV_STACK_SIZE EQU 0x4000
+CYDEV_STACK_SIZE EQU 0x1000
CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1
CYDEV_USE_BUNDLED_CMSIS EQU 1
CYDEV_VARIABLE_VDDA EQU 0
CYDEV_VDDIO1_MV EQU 5000
CYDEV_VDDIO2_MV EQU 5000
CYDEV_VDDIO3_MV EQU 3300
-CYDEV_VIO0 EQU 5
CYDEV_VIO0_MV EQU 5000
-CYDEV_VIO1 EQU 5
CYDEV_VIO1_MV EQU 5000
-CYDEV_VIO2 EQU 5
CYDEV_VIO2_MV EQU 5000
CYDEV_VIO3_MV EQU 3300
+CYIPBLOCK_ARM_CM3_VERSION EQU 0
+CYIPBLOCK_P3_ANAIF_VERSION EQU 0
+CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0
+CYIPBLOCK_P3_COMP_VERSION EQU 0
+CYIPBLOCK_P3_DMA_VERSION EQU 0
+CYIPBLOCK_P3_DRQ_VERSION EQU 0
+CYIPBLOCK_P3_EMIF_VERSION EQU 0
+CYIPBLOCK_P3_I2C_VERSION EQU 0
+CYIPBLOCK_P3_LCD_VERSION EQU 0
+CYIPBLOCK_P3_LPF_VERSION EQU 0
+CYIPBLOCK_P3_PM_VERSION EQU 0
+CYIPBLOCK_P3_TIMER_VERSION EQU 0
+CYIPBLOCK_P3_USB_VERSION EQU 0
+CYIPBLOCK_P3_VIDAC_VERSION EQU 0
+CYIPBLOCK_P3_VREF_VERSION EQU 0
+CYIPBLOCK_S8_GPIO_VERSION EQU 0
+CYIPBLOCK_S8_IRQ_VERSION EQU 0
+CYIPBLOCK_S8_SAR_VERSION EQU 0
+CYIPBLOCK_S8_SIO_VERSION EQU 0
+CYIPBLOCK_S8_UDB_VERSION EQU 0
DMA_CHANNELS_USED__MASK0 EQU 0x0000000F
CYDEV_BOOTLOADER_ENABLE EQU 0
ENDIF
/*******************************************************************************
* FILENAME: cymetadata.c
*
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator 3.1
*
* DESCRIPTION:
* This file defines all extra memory spaces that need to be included.
const uint8 cy_meta_loadable[] = {
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
- 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x03u, 0x04u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x10u, 0x04u,
0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
/*******************************************************************************
* File Name: cypins.h
-* Version 4.0
+* Version 4.20
*
* Description:
-* This file contains the function prototypes and constants used for port/pin
+* This file contains the function prototypes and constants used for a port/pin
* in access and control.
*
* Note:
* System Reference Guide provided with PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Note that this only has an effect for pins configured as software pins that
* are not driven by hardware.
*
+* The macro operation is not atomic. It is not guaranteed that shared register
+* will remain uncorrupted during simultaneous read-modify-write operations
+* performed by two threads (main and interrupt threads). To guarantee data
+* integrity in such cases, the macro should be invoked while the specific
+* interrupt is disabled or within critical section (all interrupts are
+* disabled).
+*
* Parameters:
* pinPC: Port pin configuration register (uint16).
* #defines for each pin on a chip are provided in the cydevice_trm.h file
********************************************************************************
*
* Summary:
-* This macro sets the state of the specified pin to 0
+* This macro sets the state of the specified pin to 0.
+*
+* The macro operation is not atomic. It is not guaranteed that shared register
+* will remain uncorrupted during simultaneous read-modify-write operations
+* performed by two threads (main and interrupt threads). To guarantee data
+* integrity in such cases, the macro should be invoked while the specific
+* interrupt is disabled or within critical section (all interrupts are
+* disabled).
*
* Parameters:
* pinPC: address of a Pin Configuration register.
* Summary:
* Sets the drive mode for the pin (DM).
*
+* The macro operation is not atomic. It is not guaranteed that shared register
+* will remain uncorrupted during simultaneous read-modify-write operations
+* performed by two threads (main and interrupt threads). To guarantee data
+* integrity in such cases, the macro should be invoked while the specific
+* interrupt is disabled or within critical section (all interrupts are
+* disabled).
+*
* Parameters:
* pinPC: Port pin configuration register (uint16)
* #defines for each pin on a chip are provided in the cydevice_trm.h file
*
*
* Return:
-* mode: Current drive mode for the pin
+* mode: The current drive mode for the pin
*
* Define Source
* PIN_DM_ALG_HIZ Analog HiZ
********************************************************************************
*
* Summary:
-* Set the slew rate for the pin to fast edge rate.
+* Set the slew rate for the pin to fast the edge rate.
* Note that this only applies for pins in strong output drive modes,
* not to resistive drive modes.
*
+* The macro operation is not atomic. It is not guaranteed that shared register
+* will remain uncorrupted during simultaneous read-modify-write operations
+* performed by two threads (main and interrupt threads). To guarantee data
+* integrity in such cases, the macro should be invoked while the specific
+* interrupt is disabled or within critical section (all interrupts are
+* disabled).
+*
* Parameters:
* pinPC: address of a Pin Configuration register.
* #defines for each pin on a chip are provided in the cydevice_trm.h file
********************************************************************************
*
* Summary:
-* Set the slew rate for the pin to slow edge rate.
+* Set the slew rate for the pin to slow the edge rate.
* Note that this only applies for pins in strong output drive modes,
* not to resistive drive modes.
*
+* The macro operation is not atomic. It is not guaranteed that shared register
+* will remain uncorrupted during simultaneous read-modify-write operations
+* performed by two threads (main and interrupt threads). To guarantee data
+* integrity in such cases, the macro should be invoked while the specific
+* interrupt is disabled or within critical section (all interrupts are
+* disabled).
+*
* Parameters:
* pinPC: address of a Pin Configuration register.
* #defines for each pin on a chip are provided in the cydevice_trm.h file
/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+* #ifdef <OBSOLETED_DEFINE>
+* #undef <OBSOLETED_DEFINE>
+* #define <OBSOLETED_DEFINE> (<New Value>)
+* #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+* used in the application and their modification might lead to unexpected
+* consequences.
*******************************************************************************/
#define PC_DRIVE_MODE_SHIFT (CY_PINS_PC_DRIVE_MODE_SHIFT)
#define PC_DRIVE_MODE_MASK (CY_PINS_PC_DRIVE_MODE_MASK)
/*******************************************************************************
* FILENAME: cytypes.h
-* Version 4.0
+* Version 4.20
*
* Description:
* CyTypes provides register access macros and approved types for use in
* data the correct way.
*
* Register Access macros and functions perform their operations on an
-* input of type pointer to void. The arguments passed to it should be
+* input of the type pointer to void. The arguments passed to it should be
* pointers to the type associated with the register size.
* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value)
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#if defined( __ICCARM__ )
/* Suppress warning for multiple volatile variables in an expression. */
- /* This is common in component code and the usage is not order dependent. */
+ /* This is common in component code and usage is not order dependent. */
#pragma diag_suppress=Pa082
#endif /* defined( __ICCARM__ ) */
/*******************************************************************************
* MEMBER encodes both the family and the detailed architecture
*******************************************************************************/
-#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
#ifdef CYDEV_CHIP_MEMBER_4D
- #define CY_PSOC4D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
- #define CY_PSOC4SF (CY_PSOC4D)
+ #define CY_PSOC4_4000 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
#else
- #define CY_PSOC4D (0u != 0u)
- #define CY_PSOC4SF (CY_PSOC4D)
+ #define CY_PSOC4_4000 (0u != 0u)
#endif /* CYDEV_CHIP_MEMBER_4D */
-#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
-#ifdef CYDEV_CHIP_MEMBER_5B
- #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)
+#define CY_PSOC4_4100 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
+#define CY_PSOC4_4200 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
+
+#ifdef CYDEV_CHIP_MEMBER_4F
+ #define CY_PSOC4_4100BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F)
+ #define CY_PSOC4_4200BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F)
#else
- #define CY_PSOC5LP (0u != 0u)
-#endif /* CYDEV_CHIP_MEMBER_5B */
+ #define CY_PSOC4_4100BL (0u != 0u)
+ #define CY_PSOC4_4200BL (0u != 0u)
+#endif /* CYDEV_CHIP_MEMBER_4F */
/*******************************************************************************
-* UDB revisions
+* IP blocks
*******************************************************************************/
-#define CY_UDB_V0 (CY_PSOC5A)
-#define CY_UDB_V1 (!CY_UDB_V0)
+#if (CY_PSOC4)
+
+ /* Using SRSSv2 or SRS-Lite */
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+ #define CY_IP_SRSSV2 (0u == 0u)
+ #define CY_IP_SRSSLT (!CY_IP_SRSSV2)
+ #else
+ #define CY_IP_SRSSV2 (0u != 0u)
+ #define CY_IP_SRSSLT (!CY_IP_SRSSV2)
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+ #define CY_IP_CPUSSV2 (0u != 0u)
+ #define CY_IP_CPUSS (0u == 0u)
+ #else
+ #define CY_IP_CPUSSV2 (0u != 0u)
+ #define CY_IP_CPUSS (!CY_IP_CPUSSV2)
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+ /* Product uses FLASH-Lite or regular FLASH */
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+ #define CY_IP_FMLT (0u != 0u) /* FLASH-Lite */
+ #define CY_IP_FM (!CY_IP_FMLT) /* Regular FLASH */
+ #else
+ #define CY_IP_FMLT (-1u != 0u)
+ #define CY_IP_FM (!CY_IP_FMLT)
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+ /* Number of interrupt request inputs to CM0 */
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+ #define CY_IP_INT_NR (32u)
+ #else
+ #define CY_IP_INT_NR (-1u)
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+ /* Number of Flash macros used in the device (0, 1 or 2) */
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+ #define CY_IP_FLASH_MACROS (1u)
+ #else
+ #define CY_IP_FLASH_MACROS (-1u)
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+
+ /* Number of Flash macros used in the device (0, 1 or 2) */
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+ #define CY_IP_BLESS (0u != 0u)
+ #else
+ #define CY_IP_BLESS (0u != 0u)
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+ /* Watch Crystal Oscillator (WCO) is present (32kHz) */
+ #if (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200)
+ #define CY_IP_WCO (0u != 0u)
+ #elif CY_IP_BLESS || defined (CYIPBLOCK_s8swco_VERSION)
+ #define CY_IP_WCO (0u == 0u)
+ #elif (CY_IP_SRSSV2)
+ #define CY_IP_WCO (-1u)
+ #else
+ #define CY_IP_WCO (0u != 0u)
+ #endif /* (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+#endif /* (CY_PSOC4) */
+
+
+/*******************************************************************************
+* The components version defines. Available started from cy_boot 4.20
+* Use the following construction in order to identify cy_boot version:
+* (defined(CY_BOOT_VERSION) && CY_BOOT_VERSION >= CY_BOOT_4_20)
+*******************************************************************************/
+#define CY_BOOT_4_20 (420u)
+#define CY_BOOT_VERSION (CY_BOOT_4_20)
/*******************************************************************************
#endif /* (!CY_PSOC3) */
-/* Signed or unsigned depending on the compiler selection */
+/* Signed or unsigned depending on compiler selection */
typedef char char8;
#else
- /* Prototype for function to set a 24-bit register. Located at cyutils.c */
+ /* Prototype for function to set 24-bit register. Located at cyutils.c */
extern void CySetReg24(uint32 volatile * addr, uint32 value);
#if(CY_PSOC4)
#define XDATA
#if defined(__ARMCC_VERSION)
+
#define CY_NOINIT __attribute__ ((section(".noinit"), zero_init))
#define CY_NORETURN __attribute__ ((noreturn))
#define CY_SECTION(name) __attribute__ ((section(name)))
+
+ /* Specifies a minimum alignment (in bytes) for variables of the
+ * specified type.
+ */
#define CY_ALIGN(align) __align(align)
+
+
+ /* Attached to an enum, struct, or union type definition, specified that
+ * the minimum required memory be used to represent the type.
+ */
+ #define CY_PACKED
+ #define CY_PACKED_ATTR __attribute__ ((packed))
+ #define CY_INLINE __inline
#elif defined (__GNUC__)
+
#define CY_NOINIT __attribute__ ((section(".noinit")))
#define CY_NORETURN __attribute__ ((noreturn))
#define CY_SECTION(name) __attribute__ ((section(name)))
#define CY_ALIGN(align) __attribute__ ((aligned(align)))
+ #define CY_PACKED
+ #define CY_PACKED_ATTR __attribute__ ((packed))
+ #define CY_INLINE inline
#elif defined (__ICCARM__)
+
#define CY_NOINIT __no_init
#define CY_NORETURN __noreturn
+ #define CY_PACKED __packed
+ #define CY_PACKED_ATTR
+ #define CY_INLINE inline
#endif /* (__ARMCC_VERSION) */
#endif /* (CY_PSOC3) */
#if(CY_PSOC3)
- /* 8051 naturally returns an 8 bit value. */
+ /* 8051 naturally returns 8 bit value. */
typedef unsigned char cystatus;
#else
- /* ARM naturally returns a 32 bit value. */
+ /* ARM naturally returns 32 bit value. */
typedef unsigned long cystatus;
#endif /* (CY_PSOC3) */
* KEIL for the 8051 is a big endian compiler This causes problems as the on chip
* registers are little endian. Byte swapping for two and four byte registers is
* implemented in the functions below. This will require conditional compilation
- * of function prototypes in code.
+ * of function prototypes in the code.
*******************************************************************************/
/* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */
* Data manipulation defines
*******************************************************************************/
-/* Get 8 bits of a 16 bit value. */
+/* Get 8 bits of 16 bit value. */
#define LO8(x) ((uint8) ((x) & 0xFFu))
#define HI8(x) ((uint8) ((uint16)(x) >> 8))
-/* Get 16 bits of a 32 bit value. */
+/* Get 16 bits of 32 bit value. */
#define LO16(x) ((uint16) ((x) & 0xFFFFu))
#define HI16(x) ((uint16) ((uint32)(x) >> 16))
-/* Swap the byte ordering of a 32 bit value */
+/* Swap the byte ordering of 32 bit value */
#define CYSWAP_ENDIAN32(x) \
((uint32)(((x) >> 24) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24)))
-/* Swap the byte ordering of a 16 bit value */
+/* Swap the byte ordering of 16 bit value */
#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | ((x) >> 8)))
/*******************************************************************************
-* Defines the standard return values used PSoC content. A function is
+* Defines the standard return values used in PSoC content. A function is
* not limited to these return values but can use them when returning standard
* error values. Return values can be overloaded if documented in the function
* header. On the 8051 a function can use a larger return type but still use the
/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.10
+* The following code is OBSOLETE and must not be used starting from cy_boot 3.10
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+* #ifdef <OBSOLETED_DEFINE>
+* #undef <OBSOLETED_DEFINE>
+* #define <OBSOLETED_DEFINE> (<New Value>)
+* #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+* used in the application and their modification might lead to unexpected
+* consequences.
*******************************************************************************/
+#define CY_UDB_V0 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
+#define CY_UDB_V1 (!CY_UDB_V0)
+#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
+#ifdef CYDEV_CHIP_MEMBER_4D
+ #define CY_PSOC4D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
+ #define CY_PSOC4SF (CY_PSOC4D)
+#else
+ #define CY_PSOC4D (0u != 0u)
+ #define CY_PSOC4SF (CY_PSOC4D)
+#endif /* CYDEV_CHIP_MEMBER_4D */
+#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
+#ifdef CYDEV_CHIP_MEMBER_5B
+ #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)
+#else
+ #define CY_PSOC5LP (0u != 0u)
+#endif /* CYDEV_CHIP_MEMBER_5B */
+
+#if (!CY_PSOC4)
+
+ /* Device is PSoC 3 and the revision is ES2 or earlier */
+ #define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
+ (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2))
-/* Device is PSoC 3 and the revision is ES2 or earlier */
-#define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
- (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2))
+ /* Device is PSoC 3 and the revision is ES3 or later */
+ #define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
+ (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3))
-/* Device is PSoC 3 and the revision is ES3 or later */
-#define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
- (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3))
+ /* Device is PSoC 5 and the revision is ES1 or earlier */
+ #define CY_PSOC5_ES1 (CY_PSOC5A && \
+ (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1))
-/* Device is PSoC 5 and the revision is ES1 or earlier */
-#define CY_PSOC5_ES1 (CY_PSOC5A && \
- (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1))
+ /* Device is PSoC 5 and the revision is ES2 or later */
+ #define CY_PSOC5_ES2 (CY_PSOC5A && \
+ (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1))
-/* Device is PSoC 5 and the revision is ES2 or later */
-#define CY_PSOC5_ES2 (CY_PSOC5A && \
- (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1))
+#endif /* (!CY_PSOC4) */
#endif /* CY_BOOT_CYTYPES_H */
/*******************************************************************************
* FILENAME: cyutils.c
-* Version 4.0
+* Version 4.20
*
* Description:
-* CyUtils provides function to handle 24-bit value writes.
+* CyUtils provides a function to handle 24-bit value writes.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
****************************************************************************
*
* Summary:
- * Writes the 24-bit value to the specified register.
+ * Writes a 24-bit value to the specified register.
*
* Parameters:
- * addr : adress where data must be written
- * value: data that must be written
+ * addr : the address where data must be written.
+ * value: the data that must be written.
*
* Return:
* None
* Reads the 24-bit value from the specified register.
*
* Parameters:
- * addr : adress where data must be read
+ * addr : the address where data must be read.
*
* Return:
* None
/*******************************************************************************
* File Name: project.h
- * PSoC Creator 3.0 Component Pack 7
+ * PSoC Creator 3.1
*
* Description:
* This file is automatically generated by PSoC Creator and should not
/*******************************************************************************
* File Name: timer_clock.c
-* Version 2.10
+* Version 2.20
*
* Description:
* This file provides the source code to the API for the clock component.
/*******************************************************************************
* File Name: timer_clock.h
-* Version 2.10
+* Version 2.20
*
* Description:
* Provides the function and constant definitions for the clock component.
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
- #error Component cy_clock_v2_10 requires cy_boot v3.0 or later
+ #error Component cy_clock_v2_20 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5LP) */
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</Toolchain>
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<CMSIS_SVD_File>SCSI2SD.svd</CMSIS_SVD_File>
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<File BuildType="BUILD" Toolchain="">..\..\src\diagnostic.c</File>
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<File BuildType="BUILD" Toolchain="">.\device.h</File>
</Files>
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<Folder BuildType="EXCLUDE" Path=".\codegentemp">
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<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" />
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647E" bitWidth="8" desc="" />
</block>
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006474" bitWidth="8" desc="" />
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647F" bitWidth="8" desc="" />
</block>
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
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- <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006495" bitWidth="8" desc="">
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006463" bitWidth="8" desc="" />
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x40006483" bitWidth="8" desc="" />
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006493" bitWidth="8" desc="">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
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- <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006490" bitWidth="8" desc="">
+ <register name="SCSI_Filtered_STATUS_REG" address="0x40006464" bitWidth="8" desc="" />
+ <register name="SCSI_Filtered_MASK_REG" address="0x40006484" bitWidth="8" desc="" />
+ <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006494" bitWidth="8" desc="">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
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<value name="DISABLED" value="0" desc="Disable counter" />
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<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" />
</block>
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<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
- <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="VirtualMux_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="ZeroTerminal_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="ZeroTerminal_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />
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- <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
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-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@C/C++@Optimization@Split Sections" v="True" />
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-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Assembly@Command Line@Command Line" v="" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />
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+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Assembly@General@Generate Debugging Information" v="True" />
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
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-<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Assembly@Command Line@Command Line" v="" />
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Additional Libraries" v="" />
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@General@Generate Debugging Information" v="True" />
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<name_val_pair name="5bca58cd-5542-421c-b08d-9513dbb687fd@Release@CortexM3@Linker@Command Line@Command Line" v="" />
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+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Assembly@General@Generate Debugging Information" v="True" />
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@General@Additional Include Directories" v="" />
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@General@Generate Debugging Information" v="True" />
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM0@Linker@Command Line@Command Line" v="" />
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@General@Custom Linker Script" v="" />
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM0@Linker@Command Line@Command Line" v="" />
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+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Default Char Unsigned" v="False" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Generate Debugging Information" v="True" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Preprocessor Definitions" v="DEBUG" />
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-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@General@Strict Compilation" v="False" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Optimization@Split Sections" v="True" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />
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-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@General@Generate List Files" v="True" />
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Assembly@Command Line@Command Line" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Additional Libraries" v="" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Additional Library Directories" v="" />
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Generate Debugging Information" v="True" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Generate Map File" v="True" />
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Generate Debugging Information" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Linker@Command Line@Command Line" v="" />
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Generate Debugging Information" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Suppress Warnings" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@General@Generate List Files" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@Command Line@Command Line" v="" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Additional Include Directories" v="" />
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Strict Compilation" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Generate List Files" v="True" />
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Generate Debugging Information" v="True" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Preprocessor Definitions" v="NDEBUG" />
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-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@General@Strict Compilation" v="False" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@C/C++@Optimization@Split Sections" v="True" />
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-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Assembly@Command Line@Command Line" v="" />
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Additional Libraries" v="" />
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Map File" v="True" />
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<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Generate Debugging Information" v="True" />
+<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@General@Use Default Libs" v="True" />
<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Linker@Command Line@Command Line" v="" />
-<name_val_pair name="fdb8e1ae-f83a-46cf-9446-1d703716f38a@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
+</name>
+</platform>
+<platform>
+<name v="e9305a93-d091-4da5-bdc7-2813049dcdbf">
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Assembly@Command Line@Command Line" v="-s+ -M<> -w+ -r -DNDEBUG --fpu None" />
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@C/C++@Command Line@Command Line" v="-D NDEBUG --debug --endian=little -e --fpu=None --no_wrap_diagnostics" />
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
+<name_val_pair name="e9305a93-d091-4da5-bdc7-2813049dcdbf@Release@CortexM3@Linker@Command Line@Command Line" v="--semihosting --entry __iar_program_start --vfe" />
</name>
</platform>
</platforms>
<component_generation v="PSoC Creator 2.2 Component Pack 6" />
<last_selected_tab v="Cypress" />
<component_dependent_projects_generation v="(69eeda1b-ded5-4da3-a74d-3a98f2d5d4ab , 2.1PR) | (b1a3f413-e018-46a5-a51c-20818b2f118e , 3.0) | (cd381074-8dad-4f43-bb88-7719b3e16126 , 2.1) | (29420278-6fcc-46a7-a651-999ec5c253d2 , 2.1) | (e95576e7-780d-474a-b944-018db0492cc9 , 2.1)" />
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-</custom_data>
-</CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>
+<WriteAppVersionLastSavedWith v="3.1.0.1570" />
+<WriteAppMarketingVersionLastSavedWith v=" 3.1" />
+<project_id v="6e1f5cbb-a0ca-4f55-a1fa-7b20c5be3a3e" /><custom_data><CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectCustomData" version="1"><CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997 type_name="CyDesigner.Common.Base.CyCustomData" version="2"><userData /></CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997><properties /></CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111></custom_data></CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>
</CyGuid_60697ce6-dce2-4816-8680-4de0635742eb>
<top_block v="TopDesign" />
<selected_device v="CY8C5267AXI-LP051" />
<CyGuid_b0d670ad-d48f-47cb-9d0b-b1642bab195c type_name="CyDesigner.Common.Base.CyExprTypeMgr" version="1" />
<ignored_deps />
</CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>
-<boot_component v="cy_boot_v4_0" />
+<boot_component v="cy_boot_v4_20" />
<BootloaderTag hexFile="" elfFile="" />
<current_generation v="2" />
</CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
-</CyXmlSerializer>
+</CyXmlSerializer>
\ No newline at end of file
<peripheral>
<name>SCSI_Out_Ctl</name>
<description>No description available</description>
- <baseAddress>0x40006473</baseAddress>
+ <baseAddress>0x4000647E</baseAddress>
<addressBlock>
<offset>0</offset>
- <size>0x1</size>
+ <size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<peripheral>
<name>SCSI_Out_Bits</name>
<description>No description available</description>
- <baseAddress>0x40006474</baseAddress>
+ <baseAddress>0x4000647F</baseAddress>
<addressBlock>
<offset>0</offset>
- <size>0x1</size>
+ <size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<peripheral>
<name>Debug_Timer</name>
<description>No description available</description>
- <baseAddress>0x400043A3</baseAddress>
+ <baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
- <size>0xB64</size>
+ <size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>Debug_Timer_GLOBAL_ENABLE</name>
<description>PM.ACT.CFG</description>
- <addressOffset>0x0</addressOffset>
+ <addressOffset>0x400043A3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>Debug_Timer_CONTROL</name>
<description>TMRx.CFG0</description>
- <addressOffset>0xB5D</addressOffset>
+ <addressOffset>0x40004F00</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>Debug_Timer_CONTROL2</name>
<description>TMRx.CFG1</description>
- <addressOffset>0xB5E</addressOffset>
+ <addressOffset>0x40004F01</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>Debug_Timer_CONTROL3_</name>
<description>TMRx.CFG2</description>
- <addressOffset>0xB5F</addressOffset>
+ <addressOffset>0x40004F02</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>Debug_Timer_PERIOD</name>
<description>TMRx.PER0 - Assigned Period</description>
- <addressOffset>0xB61</addressOffset>
+ <addressOffset>0x40004F04</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>Debug_Timer_COUNTER</name>
<description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
- <addressOffset>0xB63</addressOffset>
+ <addressOffset>0x40004F06</addressOffset>
<size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<peripheral>
<name>SCSI_Parity_Error</name>
<description>No description available</description>
- <baseAddress>0x40006465</baseAddress>
+ <baseAddress>0x40006463</baseAddress>
<addressBlock>
<offset>0</offset>
- <size>0x31</size>
+ <size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<peripheral>
<name>SCSI_Filtered</name>
<description>No description available</description>
- <baseAddress>0x40006460</baseAddress>
+ <baseAddress>0x40006464</baseAddress>
<addressBlock>
<offset>0</offset>
- <size>0x31</size>
+ <size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<peripheral>
<name>SCSI_CTL_PHASE</name>
<description>No description available</description>
- <baseAddress>0x40006471</baseAddress>
+ <baseAddress>0x4000647C</baseAddress>
<addressBlock>
<offset>0</offset>
- <size>0x1</size>
+ <size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<peripheral>
<name>USBFS</name>
<description>USBFS</description>
- <baseAddress>0x40004394</baseAddress>
+ <baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
- <size>0x1D0A</size>
+ <size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>USBFS_PM_USB_CR0</name>
<description>USB Power Mode Control Register 0</description>
- <addressOffset>0x0</addressOffset>
+ <addressOffset>0x40004394</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_PM_ACT_CFG</name>
<description>Active Power Mode Configuration Register</description>
- <addressOffset>0x11</addressOffset>
+ <addressOffset>0x400043A5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_PM_STBY_CFG</name>
<description>Standby Power Mode Configuration Register</description>
- <addressOffset>0x21</addressOffset>
+ <addressOffset>0x400043B5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_PRT_PS</name>
<description>Port Pin State Register</description>
- <addressOffset>0xE5D</addressOffset>
+ <addressOffset>0x400051F1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_PRT_DM0</name>
<description>Port Drive Mode Register</description>
- <addressOffset>0xE5E</addressOffset>
+ <addressOffset>0x400051F2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_PRT_DM1</name>
<description>Port Drive Mode Register</description>
- <addressOffset>0xE5F</addressOffset>
+ <addressOffset>0x400051F3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_PRT_INP_DIS</name>
<description>Input buffer disable override</description>
- <addressOffset>0xE64</addressOffset>
+ <addressOffset>0x400051F8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP0_DR0</name>
<description>bmRequestType</description>
- <addressOffset>0x1C6C</addressOffset>
+ <addressOffset>0x40006000</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP0_DR1</name>
<description>bRequest</description>
- <addressOffset>0x1C6D</addressOffset>
+ <addressOffset>0x40006001</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP0_DR2</name>
<description>wValueLo</description>
- <addressOffset>0x1C6E</addressOffset>
+ <addressOffset>0x40006002</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP0_DR3</name>
<description>wValueHi</description>
- <addressOffset>0x1C6F</addressOffset>
+ <addressOffset>0x40006003</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP0_DR4</name>
<description>wIndexLo</description>
- <addressOffset>0x1C70</addressOffset>
+ <addressOffset>0x40006004</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP0_DR5</name>
<description>wIndexHi</description>
- <addressOffset>0x1C71</addressOffset>
+ <addressOffset>0x40006005</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP0_DR6</name>
<description>lengthLo</description>
- <addressOffset>0x1C72</addressOffset>
+ <addressOffset>0x40006006</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP0_DR7</name>
<description>lengthHi</description>
- <addressOffset>0x1C73</addressOffset>
+ <addressOffset>0x40006007</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_CR0</name>
<description>USB Control Register 0</description>
- <addressOffset>0x1C74</addressOffset>
+ <addressOffset>0x40006008</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<field>
<name>device_address</name>
<description>No description available</description>
- <lsb>6</lsb>
- <msb>0</msb>
+ <lsb>0</lsb>
+ <msb>6</msb>
<access>read-only</access>
</field>
<field>
<register>
<name>USBFS_CR1</name>
<description>USB Control Register 1</description>
- <addressOffset>0x1C75</addressOffset>
+ <addressOffset>0x40006009</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_SIE_EP1_CR0</name>
<description>The Endpoint1 Control Register</description>
- <addressOffset>0x1C7A</addressOffset>
+ <addressOffset>0x4000600E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_USBIO_CR0</name>
<description>USBIO Control Register 0</description>
- <addressOffset>0x1C7C</addressOffset>
+ <addressOffset>0x40006010</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_USBIO_CR1</name>
<description>USBIO Control Register 1</description>
- <addressOffset>0x1C7E</addressOffset>
+ <addressOffset>0x40006012</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_SIE_EP2_CR0</name>
<description>The Endpoint2 Control Register</description>
- <addressOffset>0x1C8A</addressOffset>
+ <addressOffset>0x4000601E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_SIE_EP3_CR0</name>
<description>The Endpoint3 Control Register</description>
- <addressOffset>0x1C9A</addressOffset>
+ <addressOffset>0x4000602E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_SIE_EP4_CR0</name>
<description>The Endpoint4 Control Register</description>
- <addressOffset>0x1CAA</addressOffset>
+ <addressOffset>0x4000603E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_SIE_EP5_CR0</name>
<description>The Endpoint5 Control Register</description>
- <addressOffset>0x1CBA</addressOffset>
+ <addressOffset>0x4000604E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_SIE_EP6_CR0</name>
<description>The Endpoint6 Control Register</description>
- <addressOffset>0x1CCA</addressOffset>
+ <addressOffset>0x4000605E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_SIE_EP7_CR0</name>
<description>The Endpoint7 Control Register</description>
- <addressOffset>0x1CDA</addressOffset>
+ <addressOffset>0x4000606E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_SIE_EP8_CR0</name>
<description>The Endpoint8 Control Register</description>
- <addressOffset>0x1CEA</addressOffset>
+ <addressOffset>0x4000607E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_BUF_SIZE</name>
<description>Dedicated Endpoint Buffer Size Register</description>
- <addressOffset>0x1CF8</addressOffset>
+ <addressOffset>0x4000608C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP_ACTIVE</name>
<description>Endpoint Active Indication Register</description>
- <addressOffset>0x1CFA</addressOffset>
+ <addressOffset>0x4000608E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP_TYPE</name>
<description>Endpoint Type (IN/OUT) Indication</description>
- <addressOffset>0x1CFB</addressOffset>
+ <addressOffset>0x4000608F</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_USB_CLK_EN</name>
<description>USB Block Clock Enable Register</description>
- <addressOffset>0x1D09</addressOffset>
+ <addressOffset>0x4000609D</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
/*******************************************************************************
* File Name: BL.c
-* Version 1.20
+* Version 1.30
*
* Description:
* Provides an API for the Bootloader component. The API includes functions
* jumping to the application.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* The Checksum and SizeBytes are forcefully set in code. We then post process
* the hex file from the linker and inject their values then. When the hex file
* is loaded onto the device these two variables should have valid values.
-* Because the compiler can do optimizations remove the constant
+* Because the compiler can do optimizations to remove the constant
* accesses, these should not be accessed directly. Instead, the variables
* CyBtldr_ChecksumAccess & CyBtldr_SizeBytesAccess should be used to get the
* proper values at runtime.
*******************************************************************************/
#if defined(__ARMCC_VERSION) || defined (__GNUC__)
- __attribute__((section (".bootloader")))
+ __attribute__((section (".bootloader"), used))
#elif defined (__ICCARM__)
#pragma location=".bootloader"
#endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) */
-const uint8 CYCODE BL_Checksum = 0u;
+#if defined(__ARMCC_VERSION) || defined (__GNUC__) || defined (__C51__)
+ const uint8 CYCODE BL_Checksum = 0u;
+#elif defined (__ICCARM__)
+ __root const uint8 CYCODE BL_Checksum = 0u;
+#endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) || defined (__C51__) */
const uint8 CYCODE *BL_ChecksumAccess = (const uint8 CYCODE *)(&BL_Checksum);
#if defined(__ARMCC_VERSION) || defined (__GNUC__)
- __attribute__((section (".bootloader")))
+ __attribute__((section (".bootloader"), used))
#elif defined (__ICCARM__)
#pragma location=".bootloader"
#endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) */
static uint16 BL_CalcPacketChecksum(const uint8 buffer[], uint16 size) CYSMALL \
;
-static uint8 BL_Calc8BitFlashSum(uint32 start, uint32 size) CYSMALL \
- ;
-#if(!CY_PSOC4)
-static uint8 BL_Calc8BitEepromSum(uint32 start, uint32 size) CYSMALL \
- ;
-#endif /* (!CY_PSOC4) */
-
static void BL_HostLink(uint8 timeOut) \
;
static void BL_LaunchApplication(void) CYSMALL \
;
-static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \
- ;
-
-static uint32 BL_GetMetadata(uint8 fieldName, uint8 appId)\
- ;
-
#if(!CY_PSOC3)
/* Implementation for the PSoC 3 resides in a BL_psoc3.a51 file. */
static void BL_LaunchBootloadable(uint32 appAddr);
* buffer:
* The buffer containing the data to compute the checksum for
* size:
-* The number of bytes in buffer to compute the checksum for
+* The number of bytes in the buffer to compute the checksum for
*
* Returns:
* 16 bit checksum for the provided data
/*******************************************************************************
-* Function Name: BL_Calc8BitFlashSum
+* Function Name: BL_Calc8BitSum
********************************************************************************
*
* Summary:
* This computes the 8 bit sum for the provided number of bytes contained in
-* flash.
+* FLASH (if baseAddr equals CY_FLASH_BASE) or EEPROM (if baseAddr equals
+* CY_EEPROM_BASE).
*
* Parameters:
+* baseAddr:
+* CY_FLASH_BASE
+* CY_EEPROM_BASE - applicable only for PSoC 3 / PSoC 5LP devices.
+*
* start:
* The starting address to start summing data for
* size:
* 8 bit sum for the provided data
*
*******************************************************************************/
-static uint8 BL_Calc8BitFlashSum(uint32 start, uint32 size) \
+uint8 BL_Calc8BitSum(uint32 baseAddr, uint32 start, uint32 size) \
CYSMALL
{
uint8 CYDATA sum = 0u;
+ #if(!CY_PSOC4)
+ CYASSERT((baseAddr == CY_EEPROM_BASE) || (baseAddr == CY_FLASH_BASE));
+ #else
+ CYASSERT(baseAddr == CY_FLASH_BASE);
+ #endif /* (!CY_PSOC4) */
+
while (size > 0u)
{
size--;
- sum += BL_GET_CODE_BYTE(start + size);
+ sum += (*((uint8 *)(baseAddr + start + size)));
}
return(sum);
}
-#if(!CY_PSOC4)
-
- /*******************************************************************************
- * Function Name: BL_Calc8BitEepromSum
- ********************************************************************************
- *
- * Summary:
- * This computes the 8 bit sum for the provided number of bytes contained in
- * EEPROM.
- *
- * Parameters:
- * start:
- * The starting address to start summing data for
- * size:
- * The number of bytes to read and compute the sum for
- *
- * Returns:
- * 8 bit sum for the provided data
- *
- *******************************************************************************/
- static uint8 BL_Calc8BitEepromSum(uint32 start, uint32 size) \
- CYSMALL
- {
- uint8 CYDATA sum = 0u;
-
- while (size > 0u)
- {
- size--;
- sum += BL_GET_EEPROM_BYTE(start + size);
- }
-
- return(sum);
- }
-
-#endif /* (!CY_PSOC4) */
-
-
/*******************************************************************************
* Function Name: BL_Start
********************************************************************************
* Summary:
-* This function is called in order executing following algorithm:
+* This function is called in order to execute the following algorithm:
*
-* - Identify active bootloadable application (applicable only to
-* Multi-application bootloader)
+* - Identify the active bootloadable application (applicable only to
+* the Multi-application bootloader)
*
-* - Validate bootloader application (desing-time configurable, Bootloader
+* - Validate the bootloader application (design-time configurable, Bootloader
* application validation option of the component customizer)
*
-* - Validate active bootloadable application
+* - Validate the active bootloadable application. If active bootloadable
+* application is not valid, and the other bootloadable application (inactive)
+* is valid, the last one is started.
*
-* - Run communication subroutine (desing-time configurable, Wait for command
+* - Run a communication subroutine (design-time configurable, Wait for command
* option of the component customizer)
*
-* - Schedule bootloadable and reset device
+* - Schedule the bootloadable and reset the device
*
* Parameters:
* None
*
* Return:
* This method will never return. It will either load a new application and
-* reset the device or it will jump directly to the existing application.
+* reset the device or jump directly to the existing application. The CPU is
+* halted, if validation failed when "Bootloader application validation" option
+* is enabled.
+* PSoC 3/PSoC 5: The CPU is halted if Flash initialization fails.
*
* Side Effects:
-* If this method determines that the bootloader appliation itself is corrupt,
-* this method will not return, instead it will simply hang the application.
+* If Bootloader application validation option is enabled and this method
+* determines that the bootloader application itself is corrupt, this method
+* will not return, instead it will simply hang the application.
*
*******************************************************************************/
void BL_Start(void) CYSMALL
#endif /* (0u != BL_BOOTLOADER_APP_VALIDATION) */
#if(!CY_PSOC4)
- uint8 CYXDATA BL_flashBuffer[BL_FROW_SIZE];
+ #if(0u != BL_FAST_APP_VALIDATION)
+ #if !defined(CY_BOOT_VERSION)
+
+ /* Not required starting from cy_boot 4.20 */
+ uint8 CYXDATA BL_flashBuffer[BL_FROW_SIZE];
+
+ #endif /* !defined(CY_BOOT_VERSION) */
+ #endif /* (0u != BL_FAST_APP_VALIDATION) */
#endif /* (!CY_PSOC4) */
- cystatus tmpStatus;
+ cystatus validApp = CYRET_BAD_DATA;
/* Identify active bootloadable application */
#if(0u != BL_DUAL_APP_BOOTLOADER)
- if(BL_MD_BTLDB_ACTIVE_VALUE(0u) == BL_MD_BTLDB_IS_ACTIVE)
+ /* Assumes no active bootloadable application. Bootloader is active. */
+ BL_activeApp = BL_MD_BTLDB_ACTIVE_NONE;
+
+ /* Bootloadable # A is active */
+ if(BL_GetMetadata(BL_GET_BTLDB_ACTIVE, 0u) == BL_MD_BTLDB_IS_ACTIVE)
{
- BL_activeApp = BL_MD_BTLDB_ACTIVE_0;
+ /*******************************************************************
+ * -----------------------------------------------------------
+ * | | Bootloadable A | Bootloadable B | |
+ * | Case |---------------------------------| Action |
+ * | | Active | Valid | Active | Valid | |
+ * |------|--------------------------------------------------|
+ * | 9 | 1 | 0 | 0 | 0 | Bootloader |
+ * | 10 | 1 | 0 | 0 | 1 | Bootloadable B |
+ * | 11 | 1 | 0 | 1 | 0 | Bootloader |
+ * | 12 | 1 | 0 | 1 | 1 | Bootloadable B |
+ * | 13 | 1 | 1 | 0 | 0 | Bootloadable A |
+ * | 14 | 1 | 1 | 0 | 1 | Bootloadable A |
+ * | 15 | 1 | 1 | 1 | 0 | Bootloadable A |
+ * | 16 | 1 | 1 | 1 | 1 | Bootloadable A |
+ * -----------------------------------------------------------
+ *******************************************************************/
+ if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0))
+ {
+ /* Cases # 13, 14, 15, and 16 */
+ BL_activeApp = BL_MD_BTLDB_ACTIVE_0;
+ validApp = CYRET_SUCCESS;
+ }
+ else
+ {
+ if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_1))
+ {
+ /* Cases # 10 and 12 */
+ BL_activeApp = BL_MD_BTLDB_ACTIVE_1;
+ validApp = CYRET_SUCCESS;
+ }
+ }
}
- else if (BL_MD_BTLDB_ACTIVE_VALUE(1u) == BL_MD_BTLDB_IS_ACTIVE)
+
+ /* Active bootloadable application is not identified */
+ if(BL_activeApp == BL_MD_BTLDB_ACTIVE_NONE)
{
- BL_activeApp = BL_MD_BTLDB_ACTIVE_1;
+ /*******************************************************************
+ * -----------------------------------------------------------
+ * | | Bootloadable A | Bootloadable B | |
+ * | Case |---------------------------------| Action |
+ * | | Active | Valid | Active | Valid | |
+ * |------|--------------------------------------------------|
+ * | 1 | 0 | 0 | 0 | 0 | Bootloader |
+ * | 2 | 0 | 0 | 0 | 1 | Bootloader |
+ * | 3 | 0 | 0 | 1 | 0 | Bootloader |
+ * | 4 | 0 | 0 | 1 | 1 | Bootloadable B |
+ * | 5 | 0 | 1 | 0 | 0 | Bootloader |
+ * | 6 | 0 | 1 | 0 | 1 | Bootloader |
+ * | 7 | 0 | 1 | 1 | 0 | Bootloadable A |
+ * | 8 | 0 | 1 | 1 | 1 | Bootloadable B |
+ * -----------------------------------------------------------
+ *******************************************************************/
+ if (BL_GetMetadata(BL_GET_BTLDB_ACTIVE, 1u) ==
+ BL_MD_BTLDB_IS_ACTIVE)
+ {
+ /* Cases # 3, 4, 7, and 8 */
+ if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_1))
+ {
+ /* Cases # 4 and 8 */
+ BL_activeApp = BL_MD_BTLDB_ACTIVE_1;
+ validApp = CYRET_SUCCESS;
+ }
+ else
+ {
+ if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0))
+ {
+ /* Cases # 7 */
+ BL_activeApp = BL_MD_BTLDB_ACTIVE_0;
+ validApp = CYRET_SUCCESS;
+ }
+ }
+ }
}
- else
+ #else
+ if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0))
{
- BL_activeApp = BL_MD_BTLDB_ACTIVE_NONE;
+ validApp = CYRET_SUCCESS;
}
-
#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */
/* Initialize Flash subsystem for non-PSoC 4 devices */
#if(!CY_PSOC4)
- if (CYRET_SUCCESS != CySetTemp())
- {
- CyHalt(0x00u);
- }
+ #if(0u != BL_FAST_APP_VALIDATION)
- if (CYRET_SUCCESS != CySetFlashEEBuffer(BL_flashBuffer))
- {
- CyHalt(0x00u);
- }
+ if (CYRET_SUCCESS != CySetTemp())
+ {
+ CyHalt(0x00u);
+ }
+
+ #if !defined(CY_BOOT_VERSION)
+
+ /* Not required with cy_boot 4.20 */
+ if (CYRET_SUCCESS != CySetFlashEEBuffer(BL_flashBuffer))
+ {
+ CyHalt(0x00u);
+ }
+
+ #endif /* !defined(CY_BOOT_VERSION) */
+ #endif /* (0u != BL_FAST_APP_VALIDATION) */
#endif /* (CY_PSOC4) */
/***********************************************************************
* Bootloader Application Validation
*
- * Halt device if:
- * - Calculated checksum does not much one stored in metadata section
- * - Invalid pointer to the place where bootloader application ends
- * - Flash subsystem where not initialized correctly
+ * Halt the device if:
+ * - A calculated checksum does not match the one stored in the metadata
+ * section.
+ * - There is an invalid pointer to the place where the bootloader
+ * application ends.
+ * - Flash subsystem was not initialized correctly
***********************************************************************/
#if(0u != BL_BOOTLOADER_APP_VALIDATION)
/* Calculate Bootloader application checksum */
- calcedChecksum = BL_Calc8BitFlashSum(BL_MD_BTLDR_ADDR_PTR,
+ calcedChecksum = BL_Calc8BitSum(CY_FLASH_BASE,
+ BL_MD_BTLDR_ADDR_PTR,
*BL_SizeBytesAccess - BL_MD_BTLDR_ADDR_PTR);
- /* we actually included the checksum, so remove it */
+ /* we included checksum, so remove it */
calcedChecksum -= *BL_ChecksumAccess;
calcedChecksum = ( uint8 )1u + ( uint8 )(~calcedChecksum);
/***********************************************************************
- * Active Bootloadable Application Validation
- *
- * If active bootloadable application is invalid or bootloader
+ * If the active bootloadable application is invalid or a bootloader
* application is scheduled - do the following:
- * - schedule bootloader application to be run after software reset
- * - Go to the communication subroutine. Will wait for commands forever
+ * - schedule the bootloader application to be run after software reset
+ * - Go to the communication subroutine. The HostLink() will wait for
+ * the commands forever.
***********************************************************************/
- tmpStatus = BL_ValidateBootloadable(BL_activeApp);
-
if ((BL_GET_RUN_TYPE == BL_START_BTLDR) ||
- (CYRET_SUCCESS != tmpStatus))
+ (CYRET_SUCCESS != validApp))
{
BL_SET_RUN_TYPE(0u);
}
- /* Go to the communication subroutine. Will wait for commands specifed time */
+ /* Go to communication subroutine. Will wait for commands for specifed time */
#if(0u != BL_WAIT_FOR_COMMAND)
- /* Timeout is in 100s of miliseconds */
+ /* Timeout is in 100s of milliseconds */
BL_HostLink(BL_WAIT_FOR_COMMAND_TIME);
#endif /* (0u != BL_WAIT_FOR_COMMAND) */
********************************************************************************
*
* Summary:
-* Jumps the PC to the start address of the user application in flash.
+* Schedules bootloadable application and resets device
*
* Parameters:
* None
*
* Returns:
-* This method will never return if it succesfully goes to the user application.
+* This method will never return.
*
*******************************************************************************/
static void BL_LaunchApplication(void) CYSMALL
}
+/*******************************************************************************
+* Function Name: BL_Exit
+********************************************************************************
+*
+* Summary:
+* Schedules the specified application and performs software reset to launch
+* a specified application.
+*
+* If the specified application is not valid, the Bootloader (the result of the
+* ValidateBootloadable() function execution returns other than CYRET_SUCCESS,
+* the bootloader application is launched.
+*
+* Parameters:
+* appId: application to be started:
+* BL_EXIT_TO_BTLDR - Bootloader application will be started on
+* software reset.
+* BL_EXIT_TO_BTLDB,
+* BL_EXIT_TO_BTLDB_1 - Bootloadable application # 1 will be
+* started on software reset.
+* BL_EXIT_TO_BTLDB_2 - Bootloadable application # 2 will be
+* started on software reset. Available only
+* if Multi-Application option is enabled in
+* the component customizer.
+* Returns:
+* This function never returns.
+*
+*******************************************************************************/
+void BL_Exit(uint8 appId) CYSMALL
+{
+ if(BL_EXIT_TO_BTLDR == appId)
+ {
+ BL_SET_RUN_TYPE(0x0u);
+ }
+ else
+ {
+ if(CYRET_SUCCESS == BL_ValidateBootloadable(appId))
+ {
+ /* Set active application in metadata */
+ uint8 CYDATA idx;
+ for(idx = 0u; idx < BL_MAX_NUM_OF_BTLDB; idx++)
+ {
+ BL_SetFlashByte((uint32) BL_MD_BTLDB_ACTIVE_OFFSET(idx),
+ (uint8 )(idx == appId));
+ }
+
+ #if(0u != BL_DUAL_APP_BOOTLOADER)
+ BL_activeApp = appId;
+ #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */
+
+ BL_SET_RUN_TYPE(BL_SCHEDULE_BTLDB);
+ }
+ else
+ {
+ BL_SET_RUN_TYPE(0u);
+ }
+ }
+
+ CySoftwareReset();
+}
+
+
/*******************************************************************************
* Function Name: CyBtldr_CheckLaunch
********************************************************************************
*
* Summary:
-* This routine checks to see if the bootloader or the bootloadable application
-* should be run. If the application is to be run, it will start executing.
-* If the bootloader is to be run, it will return so the bootloader can
+* This routine checks if the bootloader or the bootloadable application has to
+* be run. If the application has to be run, it will start executing.
+* If the bootloader is to be run, it will return, so the bootloader can
* continue starting up.
*
* Parameters:
* None
*
* Returns:
-* None
+* It will not return if it determines that the bootloadable application should
+* be run.
*
*******************************************************************************/
void CyBtldr_CheckLaunch(void) CYSMALL
#if(CY_PSOC4)
/*******************************************************************************
- * Set cyBtldrRunType to zero in case of non-software reset occured. This means
+ * Set cyBtldrRunType to zero in case of non-software reset occurred. This means
* that bootloader application is scheduled - that is initial clean state. The
* value of cyBtldrRunType is valid only in case of software reset.
*******************************************************************************/
* application. We just check to make sure that the value at CY_APP_ADDR_ADDRESS
* is something other than 0.
*******************************************************************************/
- if(0u != BL_GetMetadata(BL_GET_METADATA_BTLDB_ADDR, BL_activeApp))
+ if(0u != BL_GetMetadata(BL_GET_BTLDB_ADDR, BL_activeApp))
{
/* Never return from this method */
- BL_LaunchBootloadable(BL_GetMetadata(BL_GET_METADATA_BTLDB_ADDR,
+ BL_LaunchBootloadable(BL_GetMetadata(BL_GET_BTLDB_ADDR,
BL_activeApp));
}
}
}
-/* Moves the arguement appAddr (RO) into PC, moving execution to the appAddr */
+/* Moves argument appAddr (RO) into PC, moving execution to appAddr */
#if defined (__ARMCC_VERSION)
__asm static void BL_LaunchBootloadable(uint32 appAddr)
* Function Name: BL_ValidateBootloadable
********************************************************************************
* Summary:
-* This routine computes the checksum, zero check, 0xFF check of the
-* application area to determine whether a valid application is loaded.
+* Performs the bootloadable application validation by calculating the
+* application image checksum and comparing it with the checksum value stored
+* in the Bootloadable Application Checksum field of the metadata section.
+*
+* If the Fast bootloadable application validation option is enabled in the
+* component customizer and bootloadable application successfully passes
+* validation, the Bootloadable Application Verification Status field of the
+* metadata section is updated. Refer to the Metadata Layout section for the
+* details.
+*
+* If the Fast bootloadable application validation option is enabled and
+* Bootloadable Application Verification Status field of the metadata section
+* claims that bootloadable application is valid, the function returns
+* CYRET_SUCCESS without further checksum calculation.
*
* Parameters:
* appId:
-* The application number to verify
+* The number of the bootloadable application should be 0 for the normal
+* bootloader and 0 or 1 for the Multi-Application bootloader.
*
* Returns:
-* CYRET_SUCCESS - if successful
-* CYRET_BAD_DATA - if the bootloadable is corrupt
+* Returns CYRET_SUCCESS if the specified bootloadable application is valid.
*
*******************************************************************************/
-static cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \
+cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \
{
uint32 CYDATA idx;
uint32 CYDATA end = BL_FIRST_APP_BYTE(appId) +
- BL_GetMetadata(BL_GET_METADATA_BTLDB_LENGTH,
+ BL_GetMetadata(BL_GET_BTLDB_LENGTH,
appId);
CYBIT valid = 0u; /* Assume bad flash image */
#if(0u != BL_FAST_APP_VALIDATION)
- if(BL_MD_BTLDB_VERIFIED_VALUE(appId) == BL_MD_BTLDB_IS_VERIFIED)
+
+ if(BL_GetMetadata(BL_GET_BTLDB_STATUS, appId) ==
+ BL_MD_BTLDB_IS_VERIFIED)
{
return(CYRET_SUCCESS);
}
/* Add ECC data to checksum */
idx = ((BL_FIRST_APP_BYTE(appId)) >> 3u);
- /* Flash may run into meta data, ECC does not so use full row */
+ /* Flash may run into meta data, so ECC does not use full row */
end = (end == (CY_FLASH_SIZE - BL_MD_SIZEOF))
? (CY_FLASH_SIZE >> 3u)
: (end >> 3u);
calcedChecksum = ( uint8 )1u + ( uint8 )(~calcedChecksum);
- if((calcedChecksum != BL_MD_BTLDB_CHECKSUM_VALUE(appId)) ||
+
+ if((calcedChecksum != BL_GetMetadata(BL_GET_BTLDB_CHECKSUM, appId)) ||
(0u == valid))
{
return(CYRET_BAD_DATA);
* Parameters:
* timeOut:
* The amount of time to listen for data before giving up. Timeout is
-* measured in 10s of ms. Use 0 for infinite wait.
+* measured in 10s of ms. Use 0 for an infinite wait.
*
* Return:
* None
uint16 CYDATA dataOffset = 0u;
uint8 CYDATA timeOutCnt = 10u;
- #if(0u == BL_DUAL_APP_BOOTLOADER)
+ #if(0u != BL_FAST_APP_VALIDATION)
uint8 CYDATA clearedMetaData = 0u;
- #endif /* (0u == BL_DUAL_APP_BOOTLOADER) */
+ #endif /* (0u != BL_FAST_APP_VALIDATION) */
CYBIT communicationState = BL_COMMUNICATION_STATE_IDLE;
uint8 dataBuffer [BL_SIZEOF_COMMAND_BUFFER];
+ #if(!CY_PSOC4)
+ #if(0u == BL_FAST_APP_VALIDATION)
+ #if !defined(CY_BOOT_VERSION)
+
+ /* Not required with cy_boot 4.20 */
+ uint8 CYXDATA BL_flashBuffer[BL_FROW_SIZE];
+
+ #endif /* !defined(CY_BOOT_VERSION) */
+ #endif /* (0u == BL_FAST_APP_VALIDATION) */
+ #endif /* (CY_PSOC4) */
+
+
+
+ #if(!CY_PSOC4)
+ #if(0u == BL_FAST_APP_VALIDATION)
+
+ /* Initialize Flash subsystem for non-PSoC 4 devices */
+ if (CYRET_SUCCESS != CySetTemp())
+ {
+ CyHalt(0x00u);
+ }
+
+ #if !defined(CY_BOOT_VERSION)
+
+ /* Not required with cy_boot 4.20 */
+ if (CYRET_SUCCESS != CySetFlashEEBuffer(BL_flashBuffer))
+ {
+ CyHalt(0x00u);
+ }
+
+ #endif /* !defined(CY_BOOT_VERSION) */
+ #endif /* (0u == BL_FAST_APP_VALIDATION) */
+ #endif /* (CY_PSOC4) */
+
/* Initialize communications channel. */
CyBtldrCommStart();
{
#if(CY_PSOC3)
(void) memcpy(&packetBuffer[BL_DATA_ADDR],
- ((uint8 CYCODE *) (BL_META_BASE(btldrData))), 56);
+ ((uint8 CYCODE *) (BL_META_BASE(btldrData))),
+ BL_GET_METADATA_RESPONSE_SIZE);
#else
(void) memcpy(&packetBuffer[BL_DATA_ADDR],
- (uint8 *) BL_META_BASE(btldrData), 56u);
+ (uint8 *) BL_META_BASE(btldrData),
+ BL_GET_METADATA_RESPONSE_SIZE);
#endif /* (CY_PSOC3) */
rspSize = 56u;
/***************************************************************************
* Get flash size
***************************************************************************/
+
+ /* Replace BL_NUM_OF_FLASH_ARRAYS with CY_FLASH_NUMBER_ARRAYS */
+
+
#if(0u != BL_CMD_GET_FLASH_SIZE_AVAIL)
case BL_COMMAND_REPORT_SIZE:
+ /* btldrData - holds flash array ID sent by host */
+
if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u))
{
- /* btldrData holds flash array ID sent by host */
- if(btldrData < BL_NUM_OF_FLASH_ARRAYS)
+ if(btldrData < CY_FLASH_NUMBER_ARRAYS)
{
- #if (1u == BL_NUM_OF_FLASH_ARRAYS)
- uint16 CYDATA startRow = (uint16)*BL_SizeBytesAccess / CYDEV_FLS_ROW_SIZE;
- #else
- uint16 CYDATA startRow = 0u;
- #endif /* (1u == BL_NUM_OF_FLASH_ARRAYS) */
+ uint16 CYDATA startRow;
+ uint8 CYDATA ArrayIdBtlderEnds;
+
+
+ /*******************************************************************************
+ * - For the flash array where bootloader application ends, return the first
+ * full row after the bootloader application.
+ *
+ * - For the fully occupied flash array, the number of rows in array is returned.
+ * As there is no space for the bootloadable application in this array.
+ *
+ * - For the arrays next to the occupied array, zero is returned.
+ * The bootloadable application can written from the their beginning.
+ *
+ *******************************************************************************/
+ ArrayIdBtlderEnds = (uint8) (*BL_SizeBytesAccess / CY_FLASH_SIZEOF_ARRAY);
+
+ if (btldrData == ArrayIdBtlderEnds)
+ {
+ startRow = (uint16) (*BL_SizeBytesAccess / CY_FLASH_SIZEOF_ROW) %
+ BL_NUMBER_OF_ROWS_IN_ARRAY;
+ }
+ else if (btldrData > ArrayIdBtlderEnds)
+ {
+ startRow = BL_FIRST_ROW_IN_ARRAY;
+ }
+ else /* (btldrData < ArrayIdBtlderEnds) */
+ {
+ startRow = BL_NUMBER_OF_ROWS_IN_ARRAY;
+ }
packetBuffer[BL_DATA_ADDR] = LO8(startRow);
packetBuffer[BL_DATA_ADDR + 1u] = HI8(startRow);
- packetBuffer[BL_DATA_ADDR + 2u] = LO8(CY_FLASH_NUMBER_ROWS - 1u);
- packetBuffer[BL_DATA_ADDR + 3u] = HI8(CY_FLASH_NUMBER_ROWS - 1u);
+
+ packetBuffer[BL_DATA_ADDR + 2u] =
+ LO8(BL_NUMBER_OF_ROWS_IN_ARRAY - 1u);
+
+ packetBuffer[BL_DATA_ADDR + 3u] =
+ HI8(BL_NUMBER_OF_ROWS_IN_ARRAY - 1u);
rspSize = 4u;
ackCode = CYRET_SUCCESS;
(uint8)BL_ValidateBootloadable(btldrData);
packetBuffer[BL_DATA_ADDR + 1u] =
- (uint8)BL_MD_BTLDB_ACTIVE_VALUE(btldrData);
+ (uint8) BL_GetMetadata(BL_GET_BTLDB_ACTIVE, btldrData);
rspSize = 2u;
ackCode = CYRET_SUCCESS;
#if(CY_PSOC3)
(void) memset(dataBuffer, (char8) 0, (int16) dataOffset);
#else
- (void) memset(dataBuffer, 0, dataOffset);
+ (void) memset(dataBuffer, 0, (uint32) dataOffset);
#endif /* (CY_PSOC3) */
}
else
#if(CY_PSOC3)
(void) memcpy(&dataBuffer[dataOffset],
&packetBuffer[BL_DATA_ADDR + 3u],
- ( int16 )pktSize - 3);
+ (int16) pktSize - 3);
#else
(void) memcpy(&dataBuffer[dataOffset],
&packetBuffer[BL_DATA_ADDR + 3u],
- pktSize - 3u);
+ (uint32) pktSize - 3u);
#endif /* (CY_PSOC3) */
dataOffset += (pktSize - 3u);
/* Check if we have all data to program */
if(dataOffset == pktSize)
{
- /* Get FLASH/EEPROM row number */
+ uint16 row;
+ uint16 firstRow;
+
+ /* Get FLASH/EEPROM row number inside of the array */
dataOffset = ((uint16)((uint16)packetBuffer[BL_DATA_ADDR + 2u] << 8u)) |
packetBuffer[BL_DATA_ADDR + 1u];
+
+ /* Metadata section resides in Flash (cannot be in EEPROM). */
#if(!CY_PSOC4)
if(btldrData <= BL_LAST_FLASH_ARRAYID)
{
#endif /* (!CY_PSOC4) */
- #if(0u == BL_DUAL_APP_BOOTLOADER)
- if(0u == clearedMetaData)
- {
- /* Metadata section must be filled with zeroes */
+ /* btldrData - holds flash array Id sent by host */
+ /* dataOffset - holds flash row Id sent by host */
+ row = (uint16)(btldrData * BL_NUMBER_OF_ROWS_IN_ARRAY) + dataOffset;
- uint8 erase[BL_FROW_SIZE];
- #if(CY_PSOC3)
- (void) memset(erase, (char8) 0, (int16) BL_FROW_SIZE);
- #else
- (void) memset(erase, 0, BL_FROW_SIZE);
- #endif /* (CY_PSOC3) */
+ /*******************************************************************************
+ * Refuse to write to the row within range of the bootloader application
+ *******************************************************************************/
- #if(CY_PSOC4)
- (void) CySysFlashWriteRow(BL_MD_ROW, erase);
- #else
- (void) CyWriteRowFull((uint8) BL_MD_FLASH_ARRAY_NUM,
- (uint16) BL_MD_ROW,
- erase,
- BL_FROW_SIZE);
- #endif /* (CY_PSOC4) */
+ /* First empty flash row after bootloader application */
+ firstRow = (uint16) (*BL_SizeBytesAccess / CYDEV_FLS_ROW_SIZE);
+ if ((*BL_SizeBytesAccess % CYDEV_FLS_ROW_SIZE) != 0u)
+ {
+ firstRow++;
+ }
- /* Set up flag that metadata was cleared */
- clearedMetaData = 1u;
- }
+ /* Check to see if the row to program will not corrupt the bootloader application */
+ if(row < firstRow)
+ {
+ ackCode = BL_ERR_ROW;
+ dataOffset = 0u;
+ break;
+ }
- #else
+
+ #if(0u != BL_DUAL_APP_BOOTLOADER)
if(BL_activeApp < BL_MD_BTLDB_ACTIVE_NONE)
{
- /* First active bootloadable application row */
- uint16 firstRow = (uint16) 1u +
- (uint16) BL_GetMetadata(BL_GET_METADATA_BTLDR_LAST_ROW,
+ uint16 lastRow;
+
+
+ /*******************************************************************************
+ * For the first bootloadable application gets the last flash row occupied by
+ * the bootloader application image:
+ * ---------------------------------------------------------------------------
+ * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 |
+ * ---------------------------------------------------------------------------
+ * |<--firstRow---|>
+ *
+ * For the second bootloadable application gets the last flash row occupied by
+ * the first bootloadable application:
+ * ---------------------------------------------------------------------------
+ * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 |
+ * ---------------------------------------------------------------------------
+ * |<-------------firstRow-----------------|>
+ *
+ * Incremented by 1 to get the first available row.
+ *
+ * Note: M1 and M2 stands for the metadata # 1 and metadata # 2, metadata
+ * sections for the 1st and 2nd bootloadable applications.
+ *******************************************************************************/
+ firstRow = (uint16) 1u +
+ (uint16) BL_GetMetadata(BL_GET_BTLDR_LAST_ROW,
BL_activeApp);
- #if(CY_PSOC4)
- uint16 row = dataOffset;
- #else
- uint16 row = (uint16)(btldrData * (CYDEV_FLS_SECTOR_SIZE / CYDEV_FLS_ROW_SIZE)) +
- dataOffset;
- #endif /* (CY_PSOC4) */
+
+ /*******************************************************************************
+ * The number of flash rows available for the both bootloadable applications:
+ *
+ * First bootloadable application is active:
+ * ---------------------------------------------------------------------------
+ * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 |
+ * ---------------------------------------------------------------------------
+ * |<-------------------lastRow -------------------->|
+ *
+ * Second bootloadable application is active:
+ * ---------------------------------------------------------------------------
+ * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 |
+ * ---------------------------------------------------------------------------
+ * |<-------lastRow-------->|
+ *******************************************************************************/
+ lastRow = (uint16)(CY_FLASH_NUMBER_ROWS -
+ BL_NUMBER_OF_METADATA_ROWS -
+ firstRow);
/*******************************************************************************
- * Last row is equal to the first row plus the number of rows available for each
- * app. To compute this, we first subtract the number of appliaction images from
- * the total flash rows: (CY_FLASH_NUMBER_ROWS - 2u).
+ * The number of flash rows available for the active bootloadable application:
*
- * Then subtract off the first row:
- * App Rows = (CY_FLASH_NUMBER_ROWS - 2u - firstRow)
- * Then divide that number by the number of application that must fit within the
- * space, if we are app1 then that number is 2, if app2 then 1. Our divisor is
- * then: (2u - BL_activeApp).
+ * First bootloadable application is active: the number of flash rows available
+ * for the both bootloadable applications should be divided by 2 - 2 bootloadable
+ * applications should fit there.
*
- * Adding this number to firstRow gives the address right beyond our valid range
- * so we subtract 1.
+ * Second bootloadable application is active: the number of flash rows available
+ * for the both bootloadable applications should be divided by 1 - 1 bootloadable
+ * application should fit there.
*******************************************************************************/
- uint16 lastRow = (firstRow - 1u) +
- ((uint16)((CYDEV_FLASH_SIZE / CYDEV_FLS_ROW_SIZE) - 2u - firstRow) /
- ((uint16)2u - (uint16)BL_activeApp));
+ lastRow = lastRow / (BL_NUMBER_OF_BTLDBLE_APPS -
+ BL_activeApp);
/*******************************************************************************
- * Check to see if the row to program is within the range of the active
- * application, or if it maches the active application's metadata row. If so,
- * refuse to program as it would corrupt the active app.
+ * The last row equals to the first row plus the number of rows available for
+ * the each bootloadable application. That gives the flash row number right
+ * beyond the valid range, so we subtract 1.
+ *
+ * First bootloadable application is active:
+ * ---------------------------------------------------------------------------
+ * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 |
+ * ---------------------------------------------------------------------------
+ * |<----------------lastRow ------------->|
+ *
+ * Second bootloadable application is active:
+ * ---------------------------------------------------------------------------
+ * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 |
+ * ---------------------------------------------------------------------------
+ * |<-----------------------------lastRow-------------------------->|
+ *******************************************************************************/
+ lastRow = (firstRow + lastRow) - 1u;
+
+
+ /*******************************************************************************
+ * 1. Refuse to write row within the range of the active application
+ *
+ * First bootloadable application is active:
+ * ---------------------------------------------------------------------------
+ * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 |
+ * ---------------------------------------------------------------------------
+ * |<----------------lastRow ------------->|
+ * |<--firstRow---|>
+ * |<-------protected------>|
+ *
+ * Second bootloadable application is active:
+ * ---------------------------------------------------------------------------
+ * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 |
+ * ---------------------------------------------------------------------------
+ * |<-------------firstRow-----------------|>
+ * |<-----------------------------lastRow-------------------------->|
+ * |<-------protected------>|
+ *
+ * 2. Refuse to write to the row that contains metadata of the active
+ * bootloadable application.
+ *
*******************************************************************************/
if(((row >= firstRow) && (row <= lastRow)) ||
((btldrData == BL_MD_FLASH_ARRAY_NUM) &&
}
}
- #endif /* (0u == BL_DUAL_APP_BOOTLOADER) */
+ #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */
- #if(!CY_PSOC4)
+
+
+ /*******************************************************************************
+ * Clear row that contains the metadata, when 'Fast bootloadable application
+ * validation' option is enabled.
+ *
+ * If 'Fast bootloadable application validation' option is enabled, the
+ * bootloader only computes the checksum the first time and assumes that it
+ * remains valid in each future startup. The metadata row is cleared because the
+ * bootloadable application might become corrupted during update, while
+ * 'Bootloadable Application Verification Status' field will still report that
+ * application is valid.
+ *******************************************************************************/
+ #if(0u != BL_FAST_APP_VALIDATION)
+
+ if(0u == clearedMetaData)
+ {
+ /* Metadata section must be filled with zeros */
+
+ uint8 erase[BL_FROW_SIZE];
+ uint8 BL_notActiveApp;
+
+
+ #if(CY_PSOC3)
+ (void) memset(erase, (char8) 0, (int16) BL_FROW_SIZE);
+ #else
+ (void) memset(erase, 0, BL_FROW_SIZE);
+ #endif /* (CY_PSOC3) */
+
+
+ #if(0u != BL_DUAL_APP_BOOTLOADER)
+ if (BL_MD_BTLDB_ACTIVE_0 == BL_activeApp)
+ {
+ BL_notActiveApp = BL_MD_BTLDB_ACTIVE_1;
+ }
+ else
+ {
+ BL_notActiveApp = BL_MD_BTLDB_ACTIVE_0;
+ }
+ #else
+ BL_notActiveApp = BL_MD_BTLDB_ACTIVE_0;
+ #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */
+
+
+ #if(CY_PSOC4)
+ (void) CySysFlashWriteRow(
+ BL_MD_ROW_NUM(BL_notActiveApp),
+ erase);
+ #else
+ (void) CyWriteRowFull(
+ (uint8) BL_MD_FLASH_ARRAY_NUM,
+ (uint16) BL_MD_ROW_NUM(BL_notActiveApp),
+ erase,
+ BL_FROW_SIZE);
+ #endif /* (CY_PSOC4) */
+
+ /* PSoC 5: Do not care about flushing the cache as flash row has been erased. */
+
+ /* Set up flag that metadata was cleared */
+ clearedMetaData = 1u;
}
+
+ #endif /* (0u != BL_FAST_APP_VALIDATION) */
+
+
+ #if(!CY_PSOC4)
+ } /* (btldrData <= BL_LAST_FLASH_ARRAYID) */
#endif /* (!CY_PSOC4) */
- #if(CY_PSOC4)
- ackCode = (CYRET_SUCCESS != CySysFlashWriteRow((uint32) dataOffset, dataBuffer)) \
+ #if(CY_PSOC4)
+ ackCode = (CYRET_SUCCESS != CySysFlashWriteRow((uint32) row, dataBuffer)) \
? BL_ERR_ROW \
: CYRET_SUCCESS;
-
#else
-
ackCode = (CYRET_SUCCESS != CyWriteRowFull(btldrData, dataOffset, dataBuffer, pktSize)) \
? BL_ERR_ROW \
: CYRET_SUCCESS;
-
#endif /* (CY_PSOC4) */
+
+ #if(CY_PSOC5)
+ /***************************************************************************
+ * When writing Flash, data in the instruction cache can become stale.
+ * Therefore, the cache data does not correlate to the data just written to
+ * Flash. A call to CyFlushCache() is required to invalidate the data in the
+ * cache and force fresh information to be loaded from Flash.
+ ***************************************************************************/
+ CyFlushCache();
+ #endif /* (CY_PSOC5) */
+
}
else
{
/* If something failed the host would send this command to reset the bootloader. */
dataOffset = 0u;
- /* Don't ack the packet, just get ready to accept the next one */
+ /* Don't acknowledge the packet, just get ready to accept the next one */
continue;
}
break;
/***************************************************************************
- * Set active application
+ * Set an active application
***************************************************************************/
#if(0u != BL_DUAL_APP_BOOTLOADER)
#else
(void) memcpy(&dataBuffer[dataOffset],
&packetBuffer[BL_DATA_ADDR],
- pktSize);
+ (uint32) pktSize);
#endif /* (CY_PSOC3) */
dataOffset += pktSize;
#else
(void) memcpy(&packetBuffer[BL_DATA_ADDR],
&BtldrVersion,
- rspSize);
+ (uint32) rspSize);
#endif /* (CY_PSOC3) */
ackCode = CYRET_SUCCESS;
/***************************************************************************
* Verify row
***************************************************************************/
+ #if (0u != BL_CMD_VERIFY_ROW_AVAIL)
+
case BL_COMMAND_VERIFY:
if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 3u))
/* Both PSoC 3 and PSoC 5LP architectures have one EEPROM array. */
rowAddr = (uint32)rowNum * CYDEV_EEPROM_ROW_SIZE;
- checksum = BL_Calc8BitEepromSum(rowAddr, CYDEV_EEPROM_ROW_SIZE);
+ checksum = BL_Calc8BitSum(CY_EEPROM_BASE, rowAddr, CYDEV_EEPROM_ROW_SIZE);
}
else
{
rowAddr = ((uint32)btldrData * CYDEV_FLS_SECTOR_SIZE)
+ ((uint32)rowNum * CYDEV_FLS_ROW_SIZE);
- checksum = BL_Calc8BitFlashSum(rowAddr, CYDEV_FLS_ROW_SIZE);
+ checksum = BL_Calc8BitSum(CY_FLASH_BASE, rowAddr, CYDEV_FLS_ROW_SIZE);
}
#else
uint32 CYDATA rowAddr = ((uint32)btldrData * CYDEV_FLS_SECTOR_SIZE)
+ ((uint32)rowNum * CYDEV_FLS_ROW_SIZE);
- uint8 CYDATA checksum = BL_Calc8BitFlashSum(rowAddr, CYDEV_FLS_ROW_SIZE);
+ uint8 CYDATA checksum = BL_Calc8BitSum(CY_FLASH_BASE,
+ rowAddr,
+ CYDEV_FLS_ROW_SIZE);
#endif /* (!CY_PSOC4) */
/*******************************************************************************
- * App Verified & App Active are information that is updated in flash at runtime
- * remove these items from the checksum to allow the host to verify everything is
+ * App Verified & App Active are information that is updated in Flash at runtime.
+ * Remove these items from the checksum to allow the host to verify everything is
* correct.
******************************************************************************/
if((BL_MD_FLASH_ARRAY_NUM == btldrData) &&
(BL_CONTAIN_METADATA(rowNum)))
{
- checksum -= BL_MD_BTLDB_ACTIVE_VALUE (BL_GET_APP_ID(rowNum));
- checksum -= BL_MD_BTLDB_VERIFIED_VALUE(BL_GET_APP_ID(rowNum));
+
+ checksum -= (uint8)BL_GetMetadata(BL_GET_BTLDB_ACTIVE,
+ BL_GET_APP_ID(rowNum));
+
+ checksum -= (uint8)BL_GetMetadata(BL_GET_BTLDB_STATUS,
+ BL_GET_APP_ID(rowNum));
}
packetBuffer[BL_DATA_ADDR] = (uint8)1u + (uint8)(~checksum);
}
break;
+ #endif /* (0u != BL_CMD_VERIFY_ROW_AVAIL) */
+
/***************************************************************************
* Exit bootloader
if(CYRET_SUCCESS == BL_ValidateBootloadable(BL_activeApp))
{
- BL_SET_RUN_TYPE(BL_START_APP);
+ BL_SET_RUN_TYPE(BL_SCHEDULE_BTLDB);
}
CySoftwareReset();
}
}
- /* ?CK the packet and function. */
+ /* Reply with acknowledge or not acknowledge packet */
(void) BL_WritePacket(ackCode, packetBuffer, rspSize);
} while ((0u == timeOut) || (BL_COMMUNICATION_STATE_ACTIVE == communicationState));
********************************************************************************
*
* Summary:
-* Creates a bootloader responce packet and transmits it back to the bootloader
+* Creates a bootloader response packet and transmits it back to the bootloader
* host application over the already established communications protocol.
*
* Parameters:
* The number of bytes contained within the buffer to pass back
*
* Return:
-* CYRET_SUCCESS if successful.
-* CYRET_UNKNOWN if there was an error tranmitting the packet.
+* CYRET_SUCCESS if successful. Any other non-zero value if failure occurred.
*
*******************************************************************************/
static cystatus BL_WritePacket(uint8 status, uint8 buffer[], uint16 size) CYSMALL \
{
uint16 CYDATA checksum;
- /* Start of the packet. */
+ /* Start of packet. */
buffer[BL_SOP_ADDR] = BL_SOP;
buffer[BL_CMD_ADDR] = status;
buffer[BL_SIZE_ADDR] = LO8(size);
buffer[BL_SIZE_ADDR + 1u] = HI8(size);
- /* Compute the checksum. */
+ /* Compute checksum. */
checksum = BL_CalcPacketChecksum(buffer, size + BL_DATA_ADDR);
buffer[BL_CHK_ADDR(size)] = LO8(checksum);
buffer[BL_CHK_ADDR(1u + size)] = HI8(checksum);
buffer[BL_EOP_ADDR(size)] = BL_EOP;
- /* Start the packet transmit. */
+ /* Start packet transmit. */
return(CyBtldrCommWrite(buffer, size + BL_MIN_PKT_SIZE, &size, 150u));
}
********************************************************************************
*
* Summary:
-* Writes byte a flash memory location
+* Writes a byte to the specified Flash memory location.
*
* Parameters:
* address:
-* Address in Flash memory where data will be written
+* The address in Flash memory where data will be written
*
* runType:
* Byte to be written
uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE);
#endif /* !(CY_PSOC4) */
- uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);
+ #if (CY_PSOC4)
+ uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE);
+ #else
+ uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE);
+ #endif /* (CY_PSOC4) */
+
uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE);
uint16 idx;
#else
(void) CyWriteRowData(arrayId, rowNum, rowData);
#endif /* (CY_PSOC4) */
+
+ #if(CY_PSOC5)
+ /***************************************************************************
+ * When writing Flash, data in the instruction cache can become stale.
+ * Therefore, the cache data does not correlate to the data just written to
+ * Flash. A call to CyFlushCache() is required to invalidate the data in the
+ * cache and force fresh information to be loaded from Flash.
+ ***************************************************************************/
+ CyFlushCache();
+ #endif /* (CY_PSOC5) */
}
********************************************************************************
*
* Summary:
-* Returns value of the multi-byte field.
+* Returns the value of the specified field of the metadata section.
*
* Parameters:
-* fieldName:
+* field:
* The field to get data from:
-* BL_GET_METADATA_BTLDB_ADDR
-* BL_GET_METADATA_BTLDR_LAST_ROW
-* BL_GET_METADATA_BTLDB_LENGTH
-* BL_GET_METADATA_BTLDR_APP_VERSION
-* BL_GET_METADATA_BTLDB_APP_VERSION
-* BL_GET_METADATA_BTLDB_APP_ID
-* BL_GET_METADATA_BTLDB_APP_CUST_ID
+* BL_GET_BTLDB_CHECKSUM - Bootloadable Application Checksum
+* BL_GET_BTLDB_ADDR - Bootloadable Application Start
+* Routine Address
+* BL_GET_BTLDR_LAST_ROW - Bootloader Last Flash Row
+* BL_GET_BTLDB_LENGTH - Bootloadable Application Length
+* BL_GET_BTLDB_ACTIVE - Active Bootloadable Application
+* BL_GET_BTLDB_STATUS - Bootloadable Application
+* Verification Status
+* BL_GET_BTLDR_APP_VERSION - Bootloader Application Version
+* BL_GET_BTLDB_APP_VERSION - Bootloadable Application Version
+* BL_GET_BTLDB_APP_ID - Bootloadable Application ID
+* BL_GET_BTLDB_APP_CUST_ID - Bootloadable Application Custom ID
*
* appId:
-* Number of the bootlodable application.
+* Number of the bootlodable application. Should be 0 for the normal
+* bootloader and 0 or 1 for the Multi-Application bootloader.
*
* Return:
-* None
+* The value of the specified field of the specified application.
*
*******************************************************************************/
-static uint32 BL_GetMetadata(uint8 fieldName, uint8 appId)
+uint32 BL_GetMetadata(uint8 field, uint8 appId)
{
uint32 fieldPtr;
uint8 fieldSize = 2u;
- uint32 result;
+ uint32 result = 0u;
- switch (fieldName)
+ switch (field)
{
- case BL_GET_METADATA_BTLDB_APP_CUST_ID:
- fieldPtr = BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId);
- fieldSize = 4u;
- break;
-
- case BL_GET_METADATA_BTLDR_APP_VERSION:
- fieldPtr = BL_MD_BTLDR_APP_VERSION_OFFSET(appId);
+ case BL_GET_BTLDB_CHECKSUM:
+ fieldPtr = BL_MD_BTLDB_CHECKSUM_OFFSET(appId);
+ fieldSize = 1u;
break;
- case BL_GET_METADATA_BTLDB_ADDR:
+ case BL_GET_BTLDB_ADDR:
fieldPtr = BL_MD_BTLDB_ADDR_OFFSET(appId);
#if(!CY_PSOC3)
fieldSize = 4u;
#endif /* (!CY_PSOC3) */
break;
- case BL_GET_METADATA_BTLDR_LAST_ROW:
+ case BL_GET_BTLDR_LAST_ROW:
fieldPtr = BL_MD_BTLDR_LAST_ROW_OFFSET(appId);
break;
- case BL_GET_METADATA_BTLDB_LENGTH:
+ case BL_GET_BTLDB_LENGTH:
fieldPtr = BL_MD_BTLDB_LENGTH_OFFSET(appId);
#if(!CY_PSOC3)
fieldSize = 4u;
#endif /* (!CY_PSOC3) */
break;
- case BL_GET_METADATA_BTLDB_APP_VERSION:
+ case BL_GET_BTLDB_ACTIVE:
+ fieldPtr = BL_MD_BTLDB_ACTIVE_OFFSET(appId);
+ fieldSize = 1u;
+ break;
+
+ case BL_GET_BTLDB_STATUS:
+ fieldPtr = BL_MD_BTLDB_VERIFIED_OFFSET(appId);
+ fieldSize = 1u;
+ break;
+
+ case BL_GET_BTLDB_APP_VERSION:
fieldPtr = BL_MD_BTLDB_APP_VERSION_OFFSET(appId);
break;
- case BL_GET_METADATA_BTLDB_APP_ID:
+ case BL_GET_BTLDR_APP_VERSION:
+ fieldPtr = BL_MD_BTLDR_APP_VERSION_OFFSET(appId);
+ break;
+
+ case BL_GET_BTLDB_APP_ID:
fieldPtr = BL_MD_BTLDB_APP_ID_OFFSET(appId);
break;
+ case BL_GET_BTLDB_APP_CUST_ID:
+ fieldPtr = BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId);
+ fieldSize = 4u;
+ break;
+
default:
/* Should never be here */
CYASSERT(0u != 0u);
}
- /* Read all fields as big-endian */
- if (2u == fieldSize)
- {
- result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u));
- result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *) fieldPtr ) << 8u;
- }
- else
+ if (1u == fieldSize)
{
- result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 3u));
- result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 2u)) << 8u;
- result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)) << 16u;
- result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr )) << 24u;
+ result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)fieldPtr);
}
- /* Following fields should be little-endian */
-#if(!CY_PSOC3)
- switch (fieldName)
- {
- case BL_GET_METADATA_BTLDR_LAST_ROW:
- result = CYSWAP_ENDIAN16(result);
- break;
+ #if(CY_PSOC3) /* Big-endian */
- case BL_GET_METADATA_BTLDB_ADDR:
- case BL_GET_METADATA_BTLDB_LENGTH:
- result = CYSWAP_ENDIAN32(result);
- break;
+ if (2u == fieldSize)
+ {
+ result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u));
+ result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr )) << 8u;
+ }
- default:
- break;
- }
+ if (4u == fieldSize)
+ {
+ result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 3u));
+ result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 2u)) << 8u;
+ result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)) << 16u;
+ result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr )) << 24u;
+ }
-#endif /* (!CY_PSOC3) */
+ #else /* PSoC 4 and PSoC 5: Little-endian */
+
+ if (2u == fieldSize)
+ {
+ result = (uint32) CY_GET_XTND_REG8((volatile uint8 *) (fieldPtr ));
+ result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *) (fieldPtr + 1u)) << 8u;
+ }
+
+ if (4u == fieldSize)
+ {
+ result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr ));
+ result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)) << 8u;
+ result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 2u)) << 16u;
+ result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 3u)) << 24u;
+ }
+
+ #endif /* (CY_PSOC3) */
return (result);
}
/*******************************************************************************
* File Name: BL.h
-* Version 1.20
+* Version 1.30
*
* Description:
* Provides an API for the Bootloader. The API includes functions for starting
* application.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#define CY_BOOTLOADER_BL_H
#include "cytypes.h"
-
-
-/* Check to see if required defines such as CY_PSOC5LP are available */
-/* They are defined starting with cy_boot v3.0 */
-#if !defined (CY_PSOC5LP)
- #error Component Bootloader_v1_20 requires cy_boot v3.0 or later
-#endif /* (CY_ PSOC5X) */
-
+#include "CyFlash.h"
#define BL_DUAL_APP_BOOTLOADER (0u)
#define BL_BOOTLOADER_APP_VERSION (0u)
#define BL_SCHEDULE_BTLDR (0x40u)
#define BL_SCHEDULE_MASK (0xC0u)
-
#if defined(__ARMCC_VERSION) || defined (__GNUC__)
__attribute__((section (".bootloader")))
#elif defined (__ICCARM__)
/*******************************************************************************
* Get the reason of the device reset
-* Return cyBtldrRunType in case if software reset was reset reason and
+* Return cyBtldrRunType in the case if software reset was the reset reason and
* set cyBtldrRunType to zero (bootloader application is scheduled - that is
-* initial clean state) and return zero.
+* the initial clean state) and return zero.
*******************************************************************************/
#if(CY_PSOC4)
#define BL_GET_RUN_TYPE (cyBtldrRunType)
#endif /* (CY_PSOC4) */
-/* Returns the number of Flash arrays availalbe in the device */
-#define BL_NUM_OF_FLASH_ARRAYS (CYDEV_FLASH_SIZE / CYDEV_FLS_SECTOR_SIZE)
+/* Returns the number of Flash arrays available in the device */
+#ifndef CY_FLASH_NUMBER_ARRAYS
+ #define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLASH_SIZE / CYDEV_FLS_SECTOR_SIZE)
+#endif /* CY_FLASH_NUMBER_ARRAYS */
/*******************************************************************************
void BL_SetFlashByte(uint32 address, uint8 runType);
void CyBtldr_CheckLaunch(void) CYSMALL ;
void BL_Start(void) CYSMALL ;
+cystatus BL_ValidateBootloadable(uint8 appId) \
+ CYSMALL ;
+uint8 BL_Calc8BitSum(uint32 baseAddr, uint32 start, uint32 size) CYSMALL \
+ ;
+uint32 BL_GetMetadata(uint8 field, uint8 appId) \
+ ;
+void BL_Exit(uint8 appId) CYSMALL ;
#if(CY_PSOC3)
/* Implementation for the PSoC 3 resides in a BL_psoc3.a51 file. */
- extern void BL_LaunchBootloadable(uint32 appAddr);
+ void BL_LaunchBootloadable(uint32 appAddr);
#endif /* (CY_PSOC3) */
-/* If using custom interface as the IO Component, user must provide these functions */
+/* When using a custom interface as the IO Component, the user must provide these functions */
#if defined(CYDEV_BOOTLOADER_IO_COMP) && (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)
extern void CyBtldrCommStart(void);
#endif /* defined(CYDEV_BOOTLOADER_IO_COMP) && (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface) */
+/*******************************************************************************
+* BL_GetMetadata()
+*******************************************************************************/
+#define BL_GET_BTLDB_CHECKSUM (1u)
+#define BL_GET_BTLDB_ADDR (2u)
+#define BL_GET_BTLDR_LAST_ROW (3u)
+#define BL_GET_BTLDB_LENGTH (4u)
+#define BL_GET_BTLDB_ACTIVE (5u)
+#define BL_GET_BTLDB_STATUS (6u)
+#define BL_GET_BTLDR_APP_VERSION (7u)
+#define BL_GET_BTLDB_APP_VERSION (8u)
+#define BL_GET_BTLDB_APP_ID (9u)
+#define BL_GET_BTLDB_APP_CUST_ID (10u)
+
+#define BL_GET_METADATA_RESPONSE_SIZE (56u)
+
+/*******************************************************************************
+* BL_Exit()
+*******************************************************************************/
+#define BL_EXIT_TO_BTLDR (2u)
+#define BL_EXIT_TO_BTLDB (0u)
+#if(0u != BL_DUAL_APP_BOOTLOADER)
+ #define BL_EXIT_TO_BTLDB_1 (0u)
+ #define BL_EXIT_TO_BTLDB_2 (1u)
+#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */
+
+
/*******************************************************************************
* Kept for backward compatibility.
*******************************************************************************/
#if(0u != BL_DUAL_APP_BOOTLOADER)
#define BL_ValidateApp(x) BL_ValidateBootloadable((x))
- #define BL_ValidateApplication \
+ #define BL_ValidateApplication() \
BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0)
#else
- #define BL_ValidateApplication \
+ #define BL_ValidateApplication() \
BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0)
#define BL_ValidateApp(x) BL_ValidateBootloadable((x))
#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */
+#define BL_Calc8BitFlashSum(start, size) BL_Calc8BitSum(CY_FLASH_BASE, (start), (size))
/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from version 1.10
+* The following code is DEPRECATED and must not be used.
*******************************************************************************/
#define BL_BOOTLOADABLE_APP_VALID (BL_BOOTLOADER_APP_VALIDATION)
#define CyBtldr_Start BL_Start
-
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from version 1.20
-*******************************************************************************/
+#define BL_NUM_OF_FLASH_ARRAYS (CYDEV_FLASH_SIZE / CYDEV_FLS_SECTOR_SIZE)
#define BL_META_BASE(x) (CYDEV_FLASH_BASE + \
(CYDEV_FLASH_SIZE - (( uint32 )(x) * CYDEV_FLS_ROW_SIZE) - \
BL_META_DATA_SIZE))
BL_META_APP_CHECKSUM_OFFSET)
#if(0u == BL_DUAL_APP_BOOTLOADER)
#define BL_MD_BASE BL_META_BASE(0u)
- #define BL_MD_ROW ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \
- - 1u)
+
+ #if(!CY_PSOC4)
+ #define BL_MD_ROW ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \
+ - 1u)
+ #else
+ #define BL_MD_ROW (CY_FLASH_NUMBER_ROWS - 1u)
+ #endif /* (CY_PSOC4) */
+
#define BL_MD_CHECKSUM_ADDR BL_META_CHECKSUM_ADDR(0u)
#define BL_MD_LAST_BLDR_ROW_ADDR BL_META_LAST_BLDR_ROW_ADDR(0u)
#define BL_MD_APP_BYTE_LEN BL_META_APP_BYTE_LEN(0u)
#define BL_MD_APP_ENTRY_POINT_ADDR BL_META_APP_ENTRY_POINT_ADDR(0u)
#define BL_MD_APP_RUN_ADDR BL_META_APP_RUN_ADDR(0u)
#else
- #define BL_MD_ROW(x) ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \
- - 1u - ( uint32 )(x))
+ #if(!CY_PSOC4)
+ #define BL_MD_ROW(x) ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \
+ - 1u - ( uint32 )(x))
+ #else
+ #define BL_MD_ROW(x) (CY_FLASH_NUMBER_ROWS - 1u - ( uint32 )(x))
+ #endif /* (CY_PSOC4) */
+
#define BL_MD_CHECKSUM_ADDR BL_META_CHECKSUM_ADDR(appId)
#define BL_MD_LAST_BLDR_ROW_ADDR BL_META_LAST_BLDR_ROW_ADDR(appId)
#define BL_MD_APP_BYTE_LEN BL_META_APP_BYTE_LEN(appId)
#define BL_START_APP (BL_SCHEDULE_BTLDB)
#define BL_START_BTLDR (BL_SCHEDULE_BTLDR)
-/* Some PSoC Creator versions used to generate only one name types */
+/* Some PSoC Creator versions are used to generate only one name types */
#if !defined (CYDEV_FLASH_BASE)
#define CYDEV_FLASH_BASE (CYDEV_FLS_BASE)
#endif /* !defined (CYDEV_FLASH_BASE) */
/*******************************************************************************
* File Name: BL_PVT.h
-* Version 1.20
+* Version 1.30
*
* Description:
* Provides an API for the Bootloader.
*
********************************************************************************
-* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#define BL_VERSION {\
- (uint8)20, \
+ (uint8)30, \
(uint8)1, \
(uint8)0x01u \
}
#define BL_EOP (0x17u) /* End of Packet */
-/* Bootloader command responces */
+/* Bootloader command responses */
#define BL_ERR_KEY (0x01u) /* The provided key does not match the expected value */
#define BL_ERR_VERIFY (0x02u) /* The verification of flash failed */
#define BL_ERR_LENGTH (0x03u) /* The amount of data available is outside the expected range */
BL_ValidateBootloadable()
*******************************************************************************/
#define BL_FIRST_APP_BYTE(appId) ((uint32)CYDEV_FLS_ROW_SIZE * \
- ((uint32) BL_GetMetadata(BL_GET_METADATA_BTLDR_LAST_ROW, appId) + \
+ ((uint32) BL_GetMetadata(BL_GET_BTLDR_LAST_ROW, appId) + \
(uint32) 1u))
#define BL_MD_BTLDB_IS_VERIFIED (0x01u)
#define BL_WAIT_FOR_COMMAND_FOREVER (0x00u)
- /* Maximum number of bytes accepted in a packet plus some */
+ /* The maximum number of bytes accepted in a packet plus some */
#define BL_SIZEOF_COMMAND_BUFFER (300u)
#endif /* (0u != BL_PACKET_CHECKSUM_CRC) */
-/*******************************************************************************
-* BL_GetMetadata()
-*******************************************************************************/
-#define BL_GET_METADATA_BTLDB_ADDR (1u)
-#define BL_GET_METADATA_BTLDR_LAST_ROW (2u)
-#define BL_GET_METADATA_BTLDB_LENGTH (3u)
-#define BL_GET_METADATA_BTLDR_APP_VERSION (4u)
-#define BL_GET_METADATA_BTLDB_APP_VERSION (5u)
-#define BL_GET_METADATA_BTLDB_APP_ID (6u)
-#define BL_GET_METADATA_BTLDB_APP_CUST_ID (7u)
-
-
/*******************************************************************************
* CyBtldr_CheckLaunch()
*******************************************************************************/
/*******************************************************************************
-* Metadata base address. In case of bootloader application, the metadata is
-* placed at row N-1; in case of multi-application bootloader, the bootloadable
-* application number 1 will use row N-1, and application number 2 will use row
-* N-2 to store its metadata, where N is the total number of rows for the
-* selected device.
+* The Metadata base address. In the case of the bootloader application, the
+* metadata is placed at row N-1; in the case of the multi-application
+* bootloader, the bootloadable application number 1 will use row N-1, and
+* application number 2 will use row N-2 to store its metadata, where N is the
+* total number of the rows for the selected device.
*******************************************************************************/
#define BL_MD_BASE_ADDR(appId) (CYDEV_FLASH_BASE + \
(CYDEV_FLASH_SIZE - ((uint32)(appId) * CYDEV_FLS_ROW_SIZE) - \
#define BL_MD_FLASH_ARRAY_NUM (BL_NUM_OF_FLASH_ARRAYS - 1u)
-#define BL_MD_ROW_NUM(appId) ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) - \
- 1u - (uint32)(appId))
+#if(!CY_PSOC4)
+ #define BL_MD_ROW_NUM(appId) ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) - \
+ 1u - (uint32)(appId))
+#else
+ #define BL_MD_ROW_NUM(appId) (CY_FLASH_NUMBER_ROWS - 1u - (uint32)(appId))
+#endif /* (!CY_PSOC4) */
+
#define BL_MD_BTLDB_CHECKSUM_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 0u)
#if(CY_PSOC3)
#define BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 24u)
-/*******************************************************************************
-* Macro for 1 byte long metadata fields
-*******************************************************************************/
-#define BL_MD_BTLDB_CHECKSUM_PTR (appId) \
- ((reg8 *)(BL_MD_BTLDB_CHECKSUM_OFFSET(appId)))
-#define BL_MD_BTLDB_CHECKSUM_VALUE(appId) \
- (CY_GET_XTND_REG8(BL_MD_BTLDB_CHECKSUM_OFFSET(appId)))
-
-#define BL_MD_BTLDB_ACTIVE_PTR(appId) \
- ((reg8 *)(BL_MD_BTLDB_ACTIVE_OFFSET(appId)))
-#define BL_MD_BTLDB_ACTIVE_VALUE(appId) \
- (CY_GET_XTND_REG8(BL_MD_BTLDB_ACTIVE_OFFSET(appId)))
-
-#define BL_MD_BTLDB_VERIFIED_PTR(appId) \
- ((reg8 *)(BL_MD_BTLDB_VERIFIED_OFFSET(appId)))
-#define BL_MD_BTLDB_VERIFIED_VALUE(appId) \
- (CY_GET_XTND_REG8(BL_MD_BTLDB_VERIFIED_OFFSET(appId)))
-
-
-/*******************************************************************************
-* Macro for multiple bytes long metadata fields pointers
-*******************************************************************************/
-#define BL_MD_BTLDB_ADDR_PTR (appId) \
- ((reg8 *)(BL_MD_BTLDB_ADDR_OFFSET(appId)))
-
-#define BL_MD_BTLDR_LAST_ROW_PTR (appId) \
- ((reg8 *)(BL_MD_BTLDR_LAST_ROW_OFFSET(appId)))
-
-#define BL_MD_BTLDB_LENGTH_PTR(appId) \
- ((reg8 *)(BL_MD_BTLDB_LENGTH_OFFSET(appId)))
-
-#define BL_MD_BTLDR_APP_VERSION_PTR(appId) \
- ((reg8 *)(BL_MD_BTLDR_APP_VERSION_OFFSET(appId)))
-
-#define BL_MD_BTLDB_APP_ID_PTR(appId) \
- ((reg8 *)(BL_MD_BTLDB_APP_ID_OFFSET(appId)))
-
-#define BL_MD_BTLDB_APP_VERSION_PTR(appId) \
- ((reg8 *)(BL_MD_BTLDB_APP_VERSION_OFFSET(appId)))
-
-#define BL_MD_BTLDB_APP_CUST_ID_PTR(appId) \
- ((reg8 *)(BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId)))
-
-
/*******************************************************************************
* Get data byte from FLASH
*******************************************************************************/
/*******************************************************************************
-* Offset of the Bootloader application in flash
+* Number of addresses remapped from Flash to RAM, when interrupt vectors are
+* configured to be stored in RAM (default setting, configured by cy_boot).
*******************************************************************************/
#if(CY_PSOC4)
#define BL_MD_BTLDR_ADDR_PTR (0xC0u) /* Exclude the vector */
/*******************************************************************************
-* Maximum number of Bootloadable applications
+* The maximum number of Bootloadable applications
*******************************************************************************/
#if(1u == BL_DUAL_APP_BOOTLOADER)
#define BL_MAX_NUM_OF_BTLDB (0x02u)
/*******************************************************************************
-* Returns TRUE if row specified as parameter contains metadata section
+* Returns TRUE if the row specified as a parameter contains a metadata section
*******************************************************************************/
#if(0u != BL_DUAL_APP_BOOTLOADER)
#define BL_CONTAIN_METADATA(row) \
/*******************************************************************************
-* Metadata section is located at the last flash row for the Boootloader, for the
-* Multi-Application Bootloader, metadata section of the Bootloadable application
-* # 0 is located at the last flash row, and metadata section of the Bootloadable
-* application # 1 is located in the flash row before last.
+* The Metadata section is located in the last flash row for the Boootloader, for
+* the Multi-Application Bootloader, the metadata section of the Bootloadable
+* application # 0 is located in the last flash row, and the metadata section of
+* the Bootloadable application # 1 is located in the flash row before last.
*******************************************************************************/
#if(0u != BL_DUAL_APP_BOOTLOADER)
#define BL_GET_APP_ID(row) \
#define BL_GET_APP_ID(row) (BL_MD_BTLDB_ACTIVE_0)
#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */
+
+/*******************************************************************************
+* Defines the number of flash rows reserved for the metadata section
+*******************************************************************************/
+#if(0u == BL_DUAL_APP_BOOTLOADER)
+ #define BL_NUMBER_OF_METADATA_ROWS (1u)
+#else
+ #define BL_NUMBER_OF_METADATA_ROWS (2u)
+#endif /* (0u == BL_DUAL_APP_BOOTLOADER) */
+
+
+/*******************************************************************************
+* Defines the number of possible bootloadable applications
+*******************************************************************************/
+#if(0u == BL_DUAL_APP_BOOTLOADER)
+ #define BL_NUMBER_OF_BTLDBLE_APPS (1u)
+#else
+ #define BL_NUMBER_OF_BTLDBLE_APPS (2u)
+#endif /* (0u == BL_DUAL_APP_BOOTLOADER) */
+
+#define BL_NUMBER_OF_ROWS_IN_ARRAY ((uint16)(CY_FLASH_SIZEOF_ARRAY/CY_FLASH_SIZEOF_ROW))
+#define BL_FIRST_ROW_IN_ARRAY (0u)
+
#endif /* CY_BOOTLOADER_BL_PVT_H */
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, last block CSTACK};
+if (CY_APPL_LOADABLE)
+{
define block LOADER { readonly section .cybootloader };
+}
define block APPL with fixed order {readonly section .romvectors, readonly};
/* The address of Flash row next after Bootloader image */
do not initialize { readwrite section .ramvectors };
/******** Placements *********/
+if (CY_APPL_LOADABLE)
+{
".cybootloader" : place at start of ROM_region {block LOADER};
+}
+
"APPL" : place at start of APPL_region {block APPL};
"RAMVEC" : place at start of RAM_region { readwrite section .ramvectors };
section .cymeta };
".cyloadermeta" : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };
+if (CY_APPL_LOADABLE)
+{
".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };
+}
".cyconfigecc" : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc };
".cycustnvl" : place at address mem : 0x90000000 { readonly section .cycustnvl };
".cywolatch" : place at address mem : 0x90100000 { readonly section .cywolatch };
;********************************************************************************
;* File Name: Cm3RealView.scat
-;* Version 4.0
+;* Version 4.20
;*
;* Description:
;* This Linker Descriptor file describes the memory layout of the PSoC5
;*
;* Note:
;*
-;* romvectors: Cypress default Interrupt sevice routine vector table.
+;* romvectors: Cypress default Interrupt service routine vector table.
;*
;* This is the ISR vector table at bootup. Used only for the reset vector.
;*
;*
;*
;********************************************************************************
-;* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+;* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
;* You may use this file only in accordance with the license, terms, conditions,
;* disclaimers, and limitations in the end user license agreement accompanying
;* the software package with which this file was provided.
/*******************************************************************************
* File Name: Cm3Start.c
-* Version 4.0
+* Version 4.20
*
* Description:
* Startup code for the ARM CM3.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
extern void __iar_data_init3 (void);
#endif /* (__ARMCC_VERSION) */
+#if defined(__GNUC__)
+ #include <errno.h>
+ extern int errno;
+ extern int end;
+#endif /* defined(__GNUC__) */
+
/* Global variables */
#if !defined (__ICCARM__)
CY_NOINIT static uint32 cySysNoInitDataValid;
********************************************************************************
*
* Summary:
-* This function is called for all interrupts, other than reset, that get
+* This function is called for all interrupts, other than a reset that gets
* called before the system is setup.
*
* Parameters:
while(1)
{
/***********************************************************************
- * We should never get here. If we do, a serious problem occured, so go
+ * We must not get here. If we do, a serious problem occurs, so go
* into an infinite loop.
***********************************************************************/
}
#if defined(__ARMCC_VERSION)
-/* Local function for the device reset. */
+/* Local function for device reset. */
extern void Reset(void);
/* Application entry point. */
********************************************************************************
*
* Summary:
-* This function is called imediatly before the users main
+* This function is called immediately before the users main
*
* Parameters:
* None
while (1)
{
- /* If main returns it is undefined what we should do. */
+ /* If main returns, it is undefined what we should do. */
}
}
/* Application entry point. */
extern int main(void);
-/* The static objects constructors initializer */
+/* Static objects constructors initializer */
extern void __libc_init_array(void);
typedef unsigned char __cy_byte_align8 __attribute ((aligned (8)));
#define __cy_region_num ((size_t)&__cy_region_num)
+/*******************************************************************************
+* System Calls of the Red Hat newlib C Library
+*******************************************************************************/
+
+
+/*******************************************************************************
+* Function Name: _exit
+********************************************************************************
+*
+* Summary:
+* Exit a program without cleaning up files. If your system doesn't provide
+* this, it is best to avoid linking with subroutines that require it (exit,
+* system).
+*
+* Parameters:
+* status: Status caused program exit.
+*
+* Return:
+* None
+*
+*******************************************************************************/
+__attribute__((weak))
+void _exit(int status)
+{
+ /* Cause divide by 0 exception */
+ int x = status / (int) INT_MAX;
+ x = 4 / x;
+
+ while(1)
+ {
+
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: _sbrk
+********************************************************************************
+*
+* Summary:
+* Increase program data space. As malloc and related functions depend on this,
+* it is useful to have a working implementation. The following suffices for a
+* standalone system; it exploits the symbol end automatically defined by the
+* GNU linker.
+*
+* Parameters:
+* nbytes: The number of bytes requested (if the parameter value is positive)
+* from the heap or returned back to the heap (if the parameter value is
+* negative).
+*
+* Return:
+* None
+*
+*******************************************************************************/
+__attribute__((weak))
+void * _sbrk (int nbytes)
+{
+ extern int end; /* Symbol defined by linker map. Start of free memory (as symbol). */
+ void * returnValue;
+
+ /* The statically held previous end of the heap, with its initialization. */
+ static void *heapPointer = (void *) &end; /* Previous end */
+
+ if (((heapPointer + nbytes) - (void *) &end) <= CYDEV_HEAP_SIZE)
+ {
+ returnValue = heapPointer;
+ heapPointer += nbytes;
+ }
+ else
+ {
+ errno = ENOMEM;
+ returnValue = (void *) -1;
+ }
+
+ return (returnValue);
+}
+
+
/*******************************************************************************
* Function Name: Reset
********************************************************************************
Start_c();
}
-__attribute__((weak))
-void _exit(int status)
-{
- /* Cause a divide by 0 exception */
- int x = status / INT_MAX;
- x = 4 / x;
-
- while(1)
- {
- }
-}
/*******************************************************************************
* Function Name: Start_c
*
* Summary:
* This function handles initializing the .data and .bss sections in
-* preperation for running standard C code. Once initialization is complete
+* preparation for running the standard C code. Once initialization is complete
* it will call main(). This function will never return.
*
* Parameters:
const struct __cy_region *rptr = __cy_regions;
/* Initialize memory */
- for (regions = __cy_region_num, rptr = __cy_regions; regions--; rptr++)
+ for (regions = __cy_region_num; regions != 0u; regions--)
{
uint32 *src = (uint32 *)rptr->init;
uint32 *dst = (uint32 *)rptr->data;
for (count = 0u; count != limit; count += sizeof (uint32))
{
- *dst++ = *src++;
+ *dst = *src;
+ dst++;
+ src++;
}
limit = rptr->zero_size;
for (count = 0u; count != limit; count += sizeof (uint32))
{
- *dst++ = 0u;
+ *dst = 0u;
+ dst++;
}
+
+ rptr++;
}
/* Invoke static objects constructors */
********************************************************************************
*
* Summary:
-* This function perform early initializations for the IAR Embedded
-* Workbench IDE. It is executed in the context of reset interrupt handler
+* This function performs early initializations for the IAR Embedded
+* Workbench IDE. It is executed in the context of a reset interrupt handler
* before the data sections are initialized.
*
* Parameters:
const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] =
#endif /* defined (__ICCARM__) */
{
- INITIAL_STACK_POINTER, /* The initial stack pointer 0 */
- #if defined (__ICCARM__) /* The reset handler 1 */
+ INITIAL_STACK_POINTER, /* Initial stack pointer 0 */
+ #if defined (__ICCARM__) /* Reset handler 1 */
__iar_program_start,
#else
(cyisraddress)&Reset,
#endif /* defined (__ICCARM__) */
- &IntDefaultHandler, /* The NMI handler 2 */
- &IntDefaultHandler, /* The hard fault handler 3 */
+ &IntDefaultHandler, /* NMI handler 2 */
+ &IntDefaultHandler, /* Hard fault handler 3 */
};
#if defined(__ARMCC_VERSION)
/* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */
CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1);
- /* Point NVIC at the RAM vector table. */
+ /* Point NVIC at RAM vector table. */
*CYINT_VECT_TABLE = CyRamVectors;
/* Initialize the configuration registers. */
#if(0u != DMA_CHANNELS_USED__MASK0)
- /* Setup DMA - only necessary if the design contains a DMA component. */
+ /* Setup DMA - only necessary if design contains DMA component. */
CyDmacConfigure();
#endif /* (0u != DMA_CHANNELS_USED__MASK0) */
/*******************************************************************************
* File Name: CyBootAsmGnu.s
-* Version 4.0
+* Version 4.20
*
* Description:
* Assembly routines for GNU as.
*
********************************************************************************
-* Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2010-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
;-------------------------------------------------------------------------------
; FILENAME: CyBootAsmIar.s
-; Version 4.0
+; Version 4.20
;
; DESCRIPTION:
; Assembly routines for IAR Embedded Workbench IDE.
;
;-------------------------------------------------------------------------------
-; Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.
+; Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
;
; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
; with interrupts still enabled. The test and set of the interrupt bits is not
-; atomic. Therefore, to avoid corrupting processor state, it must be the policy
+; atomic. Therefore, to avoid a corrupting processor state, it must be the policy
; that all interrupt routines restore the interrupt enable bits as they were
; found on entry.
;
;-------------------------------------------------------------------------------
; FILENAME: CyBootAsmRv.s
-; Version 4.0
+; Version 4.20
;
; DESCRIPTION:
; Assembly routines for RealView.
;
;-------------------------------------------------------------------------------
-; Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved.
+; Copyright 2010-2014, Cypress Semiconductor Corporation. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
;
; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
; with interrupts still enabled. The test and set of the interrupt bits is not
-; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid
+; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a
; corrupting processor state, it must be the policy that all interrupt routines
; restore the interrupt enable bits as they were found on entry.
;
/*******************************************************************************
* File Name: CyDmac.c
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides an API for the DMAC component. The API includes functions for the
* not being used.
*
* This code uses the first byte of each TD to manage the free list of TD's.
-* The user can over write this once the TD is allocated.
+* The user can overwrite this once the TD is allocated.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* are initialized. To avoid zeroing, these variables should be initialized
* properly during segments initialization as well.
*******************************************************************************/
-static uint8 CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; /* Current Number of free elements in the list */
-static uint8 CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of the first available TD */
+static uint8 CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; /* Current Number of free elements on list */
+static uint8 CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of first available TD */
static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0; /* Bit map of DMA channel ownership */
*
* Summary:
* Creates a linked list of all the TDs to be allocated. This function is called
-* by the startup code; you do not normally need to call it. You could call this
+* by the startup code; you do not normally need to call it. You can call this
* function if all of the DMA channels are inactive.
*
* Parameters:
CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u);
}
- /* Make the last one point to zero. */
+ /* Make last one point to zero. */
CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = 0u;
}
* are determined by the BUS_TIMEOUT field in the PHUBCFG register.
*
* Theory:
-* Once an error occurs the error bits are sticky and are only cleared by a
-* write 1 to the error register.
+* Once an error occurs the error bits are sticky and are only cleared by
+* writing 1 to the error register.
*
*******************************************************************************/
uint8 CyDmacError(void)
* Set to 1 when an access is attempted to an invalid address.
*
* DMAC_BUS_TIMEOUT:
-* Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values
+* Set to 1 when a bus timeout occurs. Cleared by writing 1. Timeout values
* are determined by the BUS_TIMEOUT field in the PHUBCFG register.
*
* Return:
* None
*
* Theory:
-* Once an error occurs the error bits are sticky and are only cleared by a
-* write 1 to the error register.
+* Once an error occurs the error bits are sticky and are only cleared by
+* writing 1 to the error register.
*
*******************************************************************************/
void CyDmacClearError(uint8 error)
********************************************************************************
*
* Summary:
-* When an DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC and DMAC_PERIPH_ERR occurs the
+* When DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC, and DMAC_PERIPH_ERR occur the
* address of the error is written to the error address register and can be read
* with this function.
*
/* Enter critical section! */
interruptState = CyEnterCriticalSection();
- /* Look for a free channel. */
+ /* Look for free channel. */
for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++)
{
if(0uL == (CyDmaChannels & channel))
{
- /* Mark the channel as used. */
+ /* Mark channel as used. */
CyDmaChannels |= channel;
break;
}
/* Enter critical section */
interruptState = CyEnterCriticalSection();
- /* Clear the bit mask that keeps track of ownership. */
+ /* Clear bit mask that keeps track of ownership. */
CyDmaChannels &= ~(((uint32) 1u) << chHandle);
/* Exit critical section */
* Preserves the original TD state when the TD has completed. This parameter
* applies to all TDs in the channel.
*
-* 0 - When a TD is completed, the DMAC leaves the TD configuration values in
+* 0 - When TD is completed, the DMAC leaves the TD configuration values in
* their current state, and does not restore them to their original state.
*
-* 1 - When a TD is completed, the DMAC restores the original configuration
+* 1 - When TD is completed, the DMAC restores the original configuration
* values of the TD.
*
* When preserveTds is set, the TD slot that equals the channel number becomes
{
if (0u != preserveTds)
{
- /* Store the intermediate TD states separately in CHn_SEP_TD0/1 to
- * preserve the original TD chain
+ /* Store intermediate TD states separately in CHn_SEP_TD0/1 to
+ * preserve original TD chain
*/
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP;
}
else
{
- /* Store the intermediate and final TD states on top of the original TD chain */
+ /* Store intermediate and final TD states on top of original TD chain */
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP);
}
/* Disable channel */
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN));
- /* Store the intermediate and final TD states on top of the original TD chain */
+ /* Store intermediate and final TD states on top of original TD chain */
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP));
status = CYRET_SUCCESS;
}
********************************************************************************
*
* Summary:
-* Clears pending DMA data request.
+* Clears pending the DMA data request.
*
* Parameters:
* uint8 chHandle:
* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().
*
* uint8 startTd:
-* The index of TD to set as the first TD associated with the channel. Zero is
+* Set the TD index as the first TD associated with the channel. Zero is
* a valid TD index.
*
* Return:
if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS)
{
- /* Get pointer to the Next available. */
+ /* Get pointer to Next available. */
element = CyDmaTdFreeIndex;
/* Decrement the count. */
CyDmaTdCurrentNumber--;
- /* Update the next available pointer. */
+ /* Update next available pointer. */
CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0];
}
/* Enter critical section! */
uint8 interruptState = CyEnterCriticalSection();
- /* Get pointer to the Next available. */
+ /* Get pointer to Next available. */
CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex;
/* Set new Next Available. */
* CYRET_BAD_PARAM if tdHandle is invalid.
*
* Side Effects:
-* If a TD has a transfer count of N and is executed, the transfer count becomes
+* If TD has a transfer count of N and is executed, the transfer count becomes
* 0. If it is reexecuted, the Transfer count of zero will be interpreted as a
-* request for indefinite transfer. Be careful when requesting a TD with a
+* request for indefinite transfer. Be careful when requesting TD with a
* transfer count of zero.
*
*******************************************************************************/
if(tdHandle < CY_DMA_NUMBEROF_TDS)
{
- /* If we have a pointer */
+ /* If we have pointer */
if(NULL != transferCount)
{
- /* Get the 12 bits of the transfer count */
+ /* Get 12 bits of transfer count */
reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0];
*transferCount = 0x0FFFu & CY_GET_REG16(convert);
}
- /* If we have a pointer */
+ /* If we have pointer */
if(NULL != nextTd)
{
- /* Get the Next TD pointer */
+ /* Get Next TD pointer */
*nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u];
}
- /* If we have a pointer */
+ /* If we have pointer */
if(NULL != configuration)
{
- /* Get the configuration the TD */
+ /* Get configuration TD */
*configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u];
}
/*******************************************************************************
* File Name: CyDmac.h
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides the function definitions for the DMA Controller.
* System Reference Guide provided with PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#define CY_DMA_TD_SIZE 0x08u
-/* The "u" was removed as workaround for Keil compiler bug */
+/* "u" was removed as workaround for Keil compiler bug */
#define CY_DMA_TD_SWAP_EN 0x80
#define CY_DMA_TD_SWAP_SIZE4 0x40
#define CY_DMA_TD_AUTO_EXEC_NEXT 0x20
/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+* #ifdef <OBSOLETED_DEFINE>
+* #undef <OBSOLETED_DEFINE>
+* #define <OBSOLETED_DEFINE> (<New Value>)
+* #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+* used in the application and their modification might lead to unexpected
+* consequences.
*******************************************************************************/
#define DMA_INVALID_CHANNEL (CY_DMA_INVALID_CHANNEL)
#define DMA_INVALID_TD (CY_DMA_INVALID_TD)
/*******************************************************************************
* File Name: CyFlash.c
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides an API for the FLASH/EEPROM.
* System Reference Guide provided with PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "CyFlash.h"
+/* The number of EEPROM arrays */
+#define CY_FLASH_EEPROM_NUMBER_ARRAYS (1u)
+
/*******************************************************************************
-* Holds die temperature, updated by CySetTemp(). Used for flash writting.
+* Holds the die temperature, updated by CySetTemp(). Used for flash writing.
* The first byte is the sign of the temperature (0 = negative, 1 = positive).
* The second byte is the magnitude.
*******************************************************************************/
static cystatus CySetTempInt(void);
+static cystatus CyFlashGetSpcAlgorithm(void);
/*******************************************************************************
*******************************************************************************/
void CyFlash_Start(void)
{
- /* Active Power Mode */
- *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
+ uint8 interruptState;
+
+ interruptState = CyEnterCriticalSection();
+
+
+ /***************************************************************************
+ * Enable SPC clock. This also internally enables the 36MHz IMO, since this
+ * is required for the SPC to function.
+ ***************************************************************************/
+ CY_FLASH_PM_ACT_CFG0_REG |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
+ CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
+
- /* Standby Power Mode */
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
+ /***************************************************************************
+ * The wake count defines the number of Bus Clock cycles it takes for the
+ * flash or eeprom to wake up from a low power mode independent of the chip
+ * power mode. Wake up time for these blocks is 5 us.
+ * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
+ * (30d) defines the wake up time as 60 cycles of the Bus Clock.
+ * This register needs to be written with a value dependent on the Bus Clock
+ * frequency so that the duration of the cycles is equal to or greater than
+ * the 5 us delay required.
+ ***************************************************************************/
+ CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
+
+
+ /***************************************************************************
+ * Enable flash. Active flash macros consume current, but re-enabling a
+ * disabled flash macro takes 5us. If the CPU attempts to fetch out of the
+ * macro during that time, it will be stalled. This bit allows the flash to
+ * be enabled even if the CPU is disabled, which allows a quicker return to
+ * code execution.
+ ***************************************************************************/
+ CY_FLASH_PM_ACT_CFG12_REG |= CY_FLASH_PM_ACT_CFG12_EN_FM;
+ CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_FM;
+
+ while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
+ {
+ /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
+ }
- CyDelayUs(CY_FLASH_EE_STARTUP_DELAY);
+ CyExitCriticalSection(interruptState);
}
*******************************************************************************/
void CyFlash_Stop(void)
{
- /* Active Power Mode */
- *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
+ uint8 interruptState;
+
+ interruptState = CyEnterCriticalSection();
+
+ CY_FLASH_PM_ACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_FM));
+ CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_FM));
- /* Standby Power Mode */
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
+ CyExitCriticalSection(interruptState);
}
*
* Summary:
* Sends a command to the SPC to read the die temperature. Sets a global value
-* used by the Write functions. This function must be called once before
+* used by the Write function. This function must be called once before
* executing a series of Flash writing functions.
*
* Parameters:
}
+/*******************************************************************************
+* Function Name: CyFlashGetSpcAlgorithm
+********************************************************************************
+*
+* Summary:
+* Sends a command to the SPC to download code into RAM.
+*
+* Parameters:
+* None
+*
+* Return:
+* status:
+* CYRET_SUCCESS - if successful
+* CYRET_LOCKED - if Flash writing already in use
+* CYRET_UNKNOWN - if there was an SPC error
+*
+*******************************************************************************/
+static cystatus CyFlashGetSpcAlgorithm(void)
+{
+ cystatus status;
+
+ /* Make sure SPC is powered */
+ CySpcStart();
+
+ if(CySpcLock() == CYRET_SUCCESS)
+ {
+ status = CySpcGetAlgorithm();
+
+ if(CYRET_STARTED == status)
+ {
+ while(CY_SPC_BUSY)
+ {
+ /* Spin until idle. */
+ CyDelayUs(1u);
+ }
+
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+ {
+ status = CYRET_SUCCESS;
+ }
+ }
+ CySpcUnlock();
+ }
+ else
+ {
+ status = CYRET_LOCKED;
+ }
+
+ return (status);
+}
+
+
/*******************************************************************************
* Function Name: CySetTemp
********************************************************************************
*
* Summary:
-* This is a wraparound for CySetTempInt(). It is used to return second
-* successful read of temperature value.
+* This is a wraparound for CySetTempInt(). It is used to return the second
+* successful read of the temperature value.
*
* Parameters:
* None
* CYRET_UNKNOWN if there was an SPC error.
*
* uint8 dieTemperature[2]:
-* Holds die temperature for the flash writting algorithm. The first byte is
+* Holds the die temperature for the flash writing algorithm. The first byte is
* the sign of the temperature (0 = negative, 1 = positive). The second byte is
* the magnitude.
*
*******************************************************************************/
cystatus CySetTemp(void)
{
- cystatus status = CySetTempInt();
+ cystatus status = CyFlashGetSpcAlgorithm();
if(status == CYRET_SUCCESS)
{
*
* Summary:
* Sets the user supplied temporary buffer to store SPC data while performing
-* flash and EEPROM commands. This buffer is only necessary when Flash ECC is
+* Flash and EEPROM commands. This buffer is only necessary when the Flash ECC is
* disabled.
*
* Parameters:
* buffer:
-* Address of block of memory to store temporary memory. The size of the block
+* The address of a block of memory to store temporary memory. The size of the block
* of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE.
*
* Return:
if(NULL == buffer)
{
+ rowBuffer = rowBuffer;
status = CYRET_BAD_PARAM;
}
else if(CySpcLock() != CYRET_SUCCESS)
{
+ rowBuffer = rowBuffer;
status = CYRET_LOCKED;
}
else
#else
- /* To supress the warning */
+ /* To suppress warning */
buffer = buffer;
#endif /* (CYDEV_ECC_ENABLE == 0u) */
}
-#if(CYDEV_ECC_ENABLE == 1)
-
- /*******************************************************************************
- * Function Name: CyWriteRowData
- ********************************************************************************
- *
- * Summary:
- * Sends a command to the SPC to load and program a row of data in
- * Flash or EEPROM.
- *
- * Parameters:
- * arrayID: ID of the array to write.
- * The type of write, Flash or EEPROM, is determined from the array ID.
- * The arrays in the part are sequential starting at the first ID for the
- * specific memory type. The array ID for the Flash memory lasts from 0x00 to
- * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
- * rowAddress: rowAddress of flash row to program.
- * rowData: Array of bytes to write.
- *
- * Return:
- * status:
- * CYRET_SUCCESS if successful.
- * CYRET_LOCKED if the SPC is already in use.
- * CYRET_CANCELED if command not accepted
- * CYRET_UNKNOWN if there was an SPC error.
- *
- *******************************************************************************/
- cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData)
- {
- uint16 rowSize;
- cystatus status;
-
- rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;
- status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);
-
- return(status);
- }
-
-#else
-
- /*******************************************************************************
- * Function Name: CyWriteRowData
- ********************************************************************************
- *
- * Summary:
- * Sends a command to the SPC to load and program a row of data in
- * Flash or EEPROM.
- *
- * Parameters:
- * arrayID : ID of the array to write.
- * The type of write, Flash or EEPROM, is determined from the array ID.
- * The arrays in the part are sequential starting at the first ID for the
- * specific memory type. The array ID for the Flash memory lasts from 0x00 to
- * 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
- * rowAddress : rowAddress of flash row to program.
- * rowData : Array of bytes to write.
- *
- * Return:
- * status:
- * CYRET_SUCCESS if successful.
- * CYRET_LOCKED if the SPC is already in use.
- * CYRET_CANCELED if command not accepted
- * CYRET_UNKNOWN if there was an SPC error.
- *
- *******************************************************************************/
- cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData)
- {
- uint8 i;
- uint32 offset;
- uint16 rowSize;
- cystatus status;
-
- /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */
- if(NULL != rowBuffer)
- {
- if(arrayId > CY_SPC_LAST_FLASH_ARRAYID)
- {
- rowSize = CYDEV_EEPROM_ROW_SIZE;
- }
- else
- {
- rowSize = CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE;
-
- /* Save the ECC area. */
- offset = CYDEV_ECC_BASE +
- ((uint32)arrayId * CYDEV_ECC_SECTOR_SIZE) +
- ((uint32)rowAddress * CYDEV_ECC_ROW_SIZE);
-
- for(i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
- {
- *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
- }
- }
-
- /* Copy the rowdata to the temporary buffer. */
- #if(CY_PSOC3)
- (void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE);
- #else
- (void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE);
- #endif /* (CY_PSOC3) */
-
- status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize);
- }
- else
- {
- status = CYRET_UNKNOWN;
- }
+/*******************************************************************************
+* Function Name: CyWriteRowData
+********************************************************************************
+*
+* Summary:
+* Sends a command to the SPC to load and program a row of data in
+* Flash or EEPROM.
+*
+* Parameters:
+* arrayID: ID of the array to write.
+* The type of write, Flash or EEPROM, is determined from the array ID.
+* The arrays in the part are sequential starting at the first ID for the
+* specific memory type. The array ID for the Flash memory lasts from 0x00 to
+* 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
+* rowAddress: rowAddress of flash row to program.
+* rowData: Array of bytes to write.
+*
+* Return:
+* status:
+* CYRET_SUCCESS if successful.
+* CYRET_LOCKED if the SPC is already in use.
+* CYRET_CANCELED if command not accepted
+* CYRET_UNKNOWN if there was an SPC error.
+*
+*******************************************************************************/
+cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData)
+{
+ uint16 rowSize;
+ cystatus status;
- return(status);
- }
+ rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;
+ status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);
-#endif /* (CYDEV_ECC_ENABLE == 0u) */
+ return(status);
+}
+/*******************************************************************
+* If "Enable Error Correcting Code (ECC)" and "Store Configuration
+* Data in ECC" DWR options are disabled, ECC section is available
+* for user data.
+*******************************************************************/
#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
/*******************************************************************************
********************************************************************************
*
* Summary:
- * Sends a command to the SPC to load and program a row of config data in flash.
+ * Sends a command to the SPC to load and program a row of config data in the Flash.
* This function is only valid for Flash array IDs (not for EEPROM).
*
* Parameters:
* The arrays in the part are sequential starting at the first ID for the
* specific memory type. The array ID for the Flash memory lasts
* from 0x00 to 0x3F.
- * rowAddress: Address of the sector to erase.
- * rowECC: Array of bytes to write.
+ * rowAddress: The address of the sector to erase.
+ * rowECC: The array of bytes to write.
*
* Return:
* status:
cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\
{
- uint32 offset;
- uint16 i;
cystatus status;
- /* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */
- if(NULL != rowBuffer)
- {
- /* Read the existing flash data. */
- offset = ((uint32)arrayId * CYDEV_FLS_SECTOR_SIZE) +
- ((uint32)rowAddress * CYDEV_FLS_ROW_SIZE);
-
- #if (CYDEV_FLS_BASE != 0u)
- offset += CYDEV_FLS_BASE;
- #endif /* (CYDEV_FLS_BASE != 0u) */
-
- for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
- {
- rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
- }
-
- #if(CY_PSOC3)
- (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],
- (void *)(uint32)rowECC,
- (int16)CYDEV_ECC_ROW_SIZE);
- #else
- (void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],
- (const void *)rowECC,
- CYDEV_ECC_ROW_SIZE);
- #endif /* (CY_PSOC3) */
-
- status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);
- }
- else
- {
- status = CYRET_UNKNOWN;
- }
+ status = CyWriteRowFull(arrayId, rowAddress, rowECC, CYDEV_ECC_ROW_SIZE);
return (status);
}
* Function Name: CyWriteRowFull
********************************************************************************
* Summary:
-* Sends a command to the SPC to load and program a row of data in flash.
+* Sends a command to the SPC to load and program a row of data in the Flash.
* rowData array is expected to contain Flash and ECC data if needed.
*
* Parameters:
cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \
{
- cystatus status;
+ cystatus status = CYRET_SUCCESS;
- if(CySpcLock() == CYRET_SUCCESS)
+ if((arrayId <= CY_SPC_LAST_FLASH_ARRAYID) && (arrayId > (CY_FLASH_NUMBER_ARRAYS + CY_SPC_FIRST_FLASH_ARRAYID)))
{
- /* Load row data into SPC internal latch */
- status = CySpcLoadRow(arrayId, rowData, rowSize);
+ status = CYRET_BAD_PARAM;
+ }
- if(CYRET_STARTED == status)
+ if(arrayId > CY_SPC_LAST_EE_ARRAYID)
+ {
+ status = CYRET_BAD_PARAM;
+ }
+
+ if((arrayId >= CY_SPC_FIRST_EE_ARRAYID) && (arrayId > (CY_FLASH_EEPROM_NUMBER_ARRAYS + CY_SPC_FIRST_EE_ARRAYID)))
+ {
+ status = CYRET_BAD_PARAM;
+ }
+
+ if(arrayId <= CY_SPC_LAST_FLASH_ARRAYID)
+ {
+ /* Flash */
+ if(rowNumber > (CY_FLASH_NUMBER_ROWS/CY_FLASH_NUMBER_ARRAYS))
{
- while(CY_SPC_BUSY)
- {
- /* Wait for SPC to finish and get SPC status */
- CyDelayUs(1u);
- }
+ status = CYRET_BAD_PARAM;
+ }
+ }
+ else
+ {
+ /* EEPROM */
+ if(rowNumber > (CY_EEPROM_NUMBER_ROWS/CY_FLASH_EEPROM_NUMBER_ARRAYS))
+ {
+ status = CYRET_BAD_PARAM;
+ }
- /* Hide SPC status */
- if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
- {
- status = CYRET_SUCCESS;
- }
- else
- {
- status = CYRET_UNKNOWN;
- }
+ if(CY_EEPROM_SIZEOF_ROW != rowSize)
+ {
+ status = CYRET_BAD_PARAM;
+ }
+ }
- if(CYRET_SUCCESS == status)
+ if(rowData == NULL)
+ {
+ status = CYRET_BAD_PARAM;
+ }
+
+
+ if(status == CYRET_SUCCESS)
+ {
+ if(CySpcLock() == CYRET_SUCCESS)
+ {
+ /* Load row data into SPC internal latch */
+ status = CySpcLoadRowFull(arrayId, rowNumber, rowData, rowSize);
+
+ if(CYRET_STARTED == status)
{
- /* Erase and program flash with the data from SPC interval latch */
- status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);
+ while(CY_SPC_BUSY)
+ {
+ /* Wait for SPC to finish and get SPC status */
+ CyDelayUs(1u);
+ }
- if(CYRET_STARTED == status)
+ /* Hide SPC status */
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
{
- while(CY_SPC_BUSY)
- {
- /* Wait for SPC to finish and get SPC status */
- CyDelayUs(1u);
- }
+ status = CYRET_SUCCESS;
+ }
+ else
+ {
+ status = CYRET_UNKNOWN;
+ }
- /* Hide SPC status */
- if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
- {
- status = CYRET_SUCCESS;
- }
- else
+ if(CYRET_SUCCESS == status)
+ {
+ /* Erase and program flash with data from SPC interval latch */
+ status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);
+
+ if(CYRET_STARTED == status)
{
- status = CYRET_UNKNOWN;
+ while(CY_SPC_BUSY)
+ {
+ /* Wait for SPC to finish and get SPC status */
+ CyDelayUs(1u);
+ }
+
+ /* Hide SPC status */
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)
+ {
+ status = CYRET_SUCCESS;
+ }
+ else
+ {
+ status = CYRET_UNKNOWN;
+ }
}
}
}
-
+ CySpcUnlock();
+ } /* if(CySpcLock() == CYRET_SUCCESS) */
+ else
+ {
+ status = CYRET_LOCKED;
}
-
- CySpcUnlock();
- }
- else
- {
- status = CYRET_LOCKED;
}
return(status);
*
* Summary:
* Sets the number of clock cycles the cache will wait before it samples data
-* coming back from Flash. This function must be called before increasing CPU
-* clock frequency. It can optionally be called after lowering CPU clock
-* frequency in order to improve CPU performance.
+* coming back from the Flash. This function must be called before increasing the CPU
+* clock frequency. It can optionally be called after lowering the CPU clock
+* frequency in order to improve the CPU performance.
*
* Parameters:
* uint8 freq:
/***************************************************************************
* The number of clock cycles the cache will wait before it samples data
- * coming back from Flash must be equal or greater to to the CPU frequency
+ * coming back from the Flash must be equal or greater to to the CPU frequency
* outlined in clock cycles.
***************************************************************************/
- #if (CY_PSOC3)
-
- if (freq <= 22u)
- {
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_22MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
- }
- else if (freq <= 44u)
- {
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
- }
- else
- {
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
- ((uint8)(CY_FLASH_GREATER_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
- }
-
- #endif /* (CY_PSOC3) */
-
-
- #if (CY_PSOC5)
-
- if (freq <= 16u)
- {
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
- }
- else if (freq <= 33u)
- {
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
- }
- else if (freq <= 50u)
- {
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
- ((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
- }
- else
- {
- *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
- ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
- }
-
- #endif /* (CY_PSOC5) */
+ if (freq < CY_FLASH_CACHE_WS_1_FREQ_MAX)
+ {
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+ CY_FLASH_CACHE_WS_1_VALUE_MASK;
+ }
+ else if (freq < CY_FLASH_CACHE_WS_2_FREQ_MAX)
+ {
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+ CY_FLASH_CACHE_WS_2_VALUE_MASK;
+ }
+ else if (freq < CY_FLASH_CACHE_WS_3_FREQ_MAX)
+ {
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+ CY_FLASH_CACHE_WS_3_VALUE_MASK;
+ }
+#if (CY_PSOC5)
+ else if (freq < CY_FLASH_CACHE_WS_4_FREQ_MAX)
+ {
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+ CY_FLASH_CACHE_WS_4_VALUE_MASK;
+ }
+ else if (freq <= CY_FLASH_CACHE_WS_5_FREQ_MAX)
+ {
+ CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) |
+ CY_FLASH_CACHE_WS_5_VALUE_MASK;
+ }
+#endif /* (CY_PSOC5) */
+ else
+ {
+ /* Halt CPU in debug mode if frequency is invalid */
+ CYASSERT(0u != 0u);
+ }
/* Restore global interrupt enable state */
CyExitCriticalSection(interruptState);
*******************************************************************************/
void CyEEPROM_Start(void)
{
- /* Active Power Mode */
- *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
+ uint8 interruptState;
+
+ interruptState = CyEnterCriticalSection();
+
+
+ /***************************************************************************
+ * Enable SPC clock. This also internally enables the 36MHz IMO, since this
+ * is required for the SPC to function.
+ ***************************************************************************/
+ CY_FLASH_PM_ACT_CFG0_REG |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC;
+ CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC;
- /* Standby Power Mode */
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
+
+ /***************************************************************************
+ * The wake count defines the number of Bus Clock cycles it takes for the
+ * flash or EEPROM to wake up from a low power mode independent of the chip
+ * power mode. Wake up time for these blocks is 5 us.
+ * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E
+ * (30d) defines the wake up time as 60 cycles of the Bus Clock.
+ * This register needs to be written with a value dependent on the Bus Clock
+ * frequency so that the duration of the cycles is equal to or greater than
+ * the 5 us delay required.
+ ***************************************************************************/
+ CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ;
+
+
+ /***************************************************************************
+ * Enable EEPROM. Re-enabling an EEPROM macro takes 5us. During this time,
+ * the EE will not acknowledge a PHUB request.
+ ***************************************************************************/
+ CY_FLASH_PM_ACT_CFG12_REG |= CY_FLASH_PM_ACT_CFG12_EN_EE;
+ CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_EE;
+
+ while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE))
+ {
+ /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */
+ }
+
+ CyExitCriticalSection(interruptState);
}
*******************************************************************************/
void CyEEPROM_Stop (void)
{
- /* Active Power Mode */
- *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
+ uint8 interruptState;
- /* Standby Power Mode */
- *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
+ interruptState = CyEnterCriticalSection();
+
+ CY_FLASH_PM_ACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_EE));
+ CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_EE));
+
+ CyExitCriticalSection(interruptState);
}
*******************************************************************************/
void CyEEPROM_ReadReserve(void)
{
- /* Make a request for PHUB to have access */
- *CY_FLASH_EE_SCR_PTR |= CY_FLASH_EE_SCR_AHB_EE_REQ;
+ /* Make request for PHUB to have access */
+ CY_FLASH_EE_SCR_REG |= CY_FLASH_EE_SCR_AHB_EE_REQ;
- while (0u == (*CY_FLASH_EE_SCR_PTR & CY_FLASH_EE_SCR_AHB_EE_ACK))
+ while (0u == (CY_FLASH_EE_SCR_REG & CY_FLASH_EE_SCR_AHB_EE_ACK))
{
- /* Wait for acknowledgement from PHUB */
+ /* Wait for acknowledgment from PHUB */
}
}
*******************************************************************************/
void CyEEPROM_ReadRelease(void)
{
- *CY_FLASH_EE_SCR_PTR |= 0x00u;
+ CY_FLASH_EE_SCR_REG &= (uint8)(~CY_FLASH_EE_SCR_AHB_EE_REQ);
}
/*******************************************************************************
* File Name: CyFlash.h
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides the function definitions for the FLASH/EEPROM.
* System Reference Guide provided with PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#define CY_FLASH_NUMBER_ROWS (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE)
#define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE)
+#if(CYDEV_ECC_ENABLE == 0)
+ #define CY_FLASH_SIZEOF_FULL_ROW (CY_FLASH_SIZEOF_ROW + CY_FLASH_SIZEOF_ECC_ROW)
+#else
+ #define CY_FLASH_SIZEOF_FULL_ROW (CY_FLASH_SIZEOF_ROW)
+#endif /* (CYDEV_ECC_ENABLE == 0) */
#define CY_EEPROM_BASE (CYDEV_EE_BASE)
#define CY_EEPROM_SIZE (CYDEV_EE_SIZE)
#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EEPROM_SECTOR_SIZE)
#define CY_EEPROM_SIZEOF_ROW (CYDEV_EEPROM_ROW_SIZE)
-#define CY_EEPROM_NUMBER_ROWS (EEPROM_SIZE / CYDEV_EEPROM_ROW_SIZE)
+#define CY_EEPROM_NUMBER_ROWS (CYDEV_EE_SIZE / CYDEV_EEPROM_ROW_SIZE)
#define CY_EEPROM_NUMBER_ARRAYS (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY)
-
+#define CY_EEPROM_NUMBER_SECTORS (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE)
+#define CY_EEPROM_SIZEOF_SECTOR (CYDEV_EEPROM_SECTOR_SIZE)
#if !defined(CYDEV_FLS_BASE)
#define CYDEV_FLS_BASE CYDEV_FLASH_BASE
/***************************************
* Registers
***************************************/
+/* Active Power Mode Configuration Register 0 */
+#define CY_FLASH_PM_ACT_CFG0_REG (* (reg8 *) CYREG_PM_ACT_CFG0)
+#define CY_FLASH_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)
+
+/* Alternate Active Power Mode Configuration Register 0 */
+#define CY_FLASH_PM_ALTACT_CFG0_REG (* (reg8 *) CYREG_PM_STBY_CFG0)
+#define CY_FLASH_PM_ALTACT_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0)
+
/* Active Power Mode Configuration Register 12 */
-#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12)
-#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_CFG12_REG (* (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_CFG12_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)
/* Alternate Active Power Mode Configuration Register 12 */
-#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12)
-#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_CFG12_REG (* (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_CFG12_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)
+
+/* Wake count (BUS_CLK cycles) it takes for the Flash and EEPROM to wake up */
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_REG (* (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_PTR ( (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT)
+
+/* Flash macro control register */
+#define CY_FLASH_SPC_FM_EE_CR_REG (* (reg8 *) CYREG_SPC_FM_EE_CR)
+#define CY_FLASH_SPC_FM_EE_CR_PTR ( (reg8 *) CYREG_SPC_FM_EE_CR)
/* Cache Control Register */
***************************************/
/* Power Mode Masks */
-#define CY_FLASH_PM_EE_MASK (0x10u)
-#define CY_FLASH_PM_FLASH_MASK (0x01u)
-/* Frequency Constants */
+/* Enable EEPROM */
+#define CY_FLASH_PM_ACT_CFG12_EN_EE (0x10u)
+#define CY_FLASH_PM_ALTACT_CFG12_EN_EE (0x10u)
+
+/* Enable Flash */
#if (CY_PSOC3)
+ #define CY_FLASH_PM_ACT_CFG12_EN_FM (0x01u)
+ #define CY_FLASH_PM_ALTACT_CFG12_EN_FM (0x01u)
+#else
+ #define CY_FLASH_PM_ACT_CFG12_EN_FM (0x0Fu)
+ #define CY_FLASH_PM_ALTACT_CFG12_EN_FM (0x0Fu)
+#endif /* (CY_PSOC3) */
+
- #define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u)
- #define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u)
- #define CY_FLASH_GREATER_44MHz (0x03u)
+/* Frequency Constants */
+#if (CY_PSOC3)
+ #define CY_FLASH_CACHE_WS_VALUE_MASK (0xC0u)
+ #define CY_FLASH_CACHE_WS_1_VALUE_MASK (0x40u)
+ #define CY_FLASH_CACHE_WS_2_VALUE_MASK (0x80u)
+ #define CY_FLASH_CACHE_WS_3_VALUE_MASK (0xC0u)
+
+ #define CY_FLASH_CACHE_WS_1_FREQ_MAX (22u)
+ #define CY_FLASH_CACHE_WS_2_FREQ_MAX (44u)
+ #define CY_FLASH_CACHE_WS_3_FREQ_MAX (67u)
#endif /* (CY_PSOC3) */
#if (CY_PSOC5)
-
- #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u)
- #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u)
- #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u)
- #define CY_FLASH_GREATER_51MHz (0x00u)
-
+ #define CY_FLASH_CACHE_WS_VALUE_MASK (0xE0u)
+ #define CY_FLASH_CACHE_WS_1_VALUE_MASK (0x40u)
+ #define CY_FLASH_CACHE_WS_2_VALUE_MASK (0x80u)
+ #define CY_FLASH_CACHE_WS_3_VALUE_MASK (0xC0u)
+ #define CY_FLASH_CACHE_WS_4_VALUE_MASK (0x00u)
+ #define CY_FLASH_CACHE_WS_5_VALUE_MASK (0x20u)
+
+ #define CY_FLASH_CACHE_WS_1_FREQ_MAX (16u)
+ #define CY_FLASH_CACHE_WS_2_FREQ_MAX (33u)
+ #define CY_FLASH_CACHE_WS_3_FREQ_MAX (50u)
+ #define CY_FLASH_CACHE_WS_4_FREQ_MAX (67u)
+ #define CY_FLASH_CACHE_WS_5_FREQ_MAX (83u)
#endif /* (CY_PSOC5) */
#define CY_FLASH_CYCLES_MASK_SHIFT (0x06u)
#define CY_FLASH_CYCLES_MASK ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT)))
-#define CY_FLASH_EE_STARTUP_DELAY (5u)
#define CY_FLASH_EE_SCR_AHB_EE_REQ (0x01u)
#define CY_FLASH_EE_SCR_AHB_EE_ACK (0x02u)
+#define CY_FLASH_EE_EE_AWAKE (0x20u)
+
+/* 5(us) * BUS_CLK(80 MHz) / granularity(2) */
+#define CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ (0xC8u)
+
+/* Enable clk_spc. This also internally enables the 36MHz IMO. */
+#define CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC (0x08u)
+#define CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC (0x08u)
/* Default values for getting temperature. */
/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
+* Thne following code is OBSOLETE and must not be used starting with cy_boot
+* 4.20.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+* #ifdef <OBSOLETED_DEFINE>
+* #undef <OBSOLETED_DEFINE>
+* #define <OBSOLETED_DEFINE> (<New Value>)
+* #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+* used in the application and their modification might lead to unexpected
+* consequences.
+*******************************************************************************/
+#if (CY_PSOC5)
+ #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u)
+ #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u)
+ #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u)
+ #define CY_FLASH_GREATER_51MHz (0x00u)
+#endif /* (CY_PSOC5) */
+
+#if (CY_PSOC3)
+ #define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u)
+ #define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u)
+ #define CY_FLASH_GREATER_44MHz (0x03u)
+#endif /* (CY_PSOC3) */
+
+#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)
+#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)
+#define CY_FLASH_PM_EE_MASK (0x10u)
+#define CY_FLASH_PM_FLASH_MASK (0x01u)
+
+/*******************************************************************************
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.0
*******************************************************************************/
#define FLASH_SIZE (CY_FLASH_SIZE)
#define FLASH_SIZEOF_SECTOR (CY_FLASH_SIZEOF_ARRAY)
#define EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY)
#define EEPROM_NUMBER_ROWS (CY_EEPROM_NUMBER_ROWS)
#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS)
-#define CY_EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS)
-#define CY_EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY)
/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.30
*******************************************************************************/
#define FLASH_CYCLES_PTR (CY_FLASH_CONTROL_PTR)
/*******************************************************************************
* File Name: CyLib.c
-* Version 4.0
+* Version 4.20
*
* Description:
-* Provides system API for the clocking, interrupts and watchdog timer.
+* Provides a system API for the clocking, interrupts and watchdog timer.
*
* Note:
* Documentation of the API's in this file is located in the
* System Reference Guide provided with PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
static void CyIMO_SetTrimValue(uint8 freq) ;
static void CyBusClk_Internal_SetDivider(uint16 divider);
+#if(CY_PSOC5)
+ static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS];
+ static void CySysTickServiceCallbacks(void);
+ uint32 CySysTickInitVar = 0u;
+#endif /* (CY_PSOC5) */
+
/*******************************************************************************
* Function Name: CyPLL_OUT_Start
* clock can still be used.
*
* Side Effects:
-* If wait is enabled: This function wses the Fast Time Wheel to time the wait.
+* If wait is enabled: This function uses the Fast Time Wheel to time the wait.
* Any other use of the Fast Time Wheel will be stopped during the period of
* this function and then restored. This function also uses the 100 KHz ILO.
* If not enabled, this function will enable the 100 KHz ILO for the period of
uint8 pmTwCfg2State;
- /* Enables the PLL circuit */
+ /* Enables PLL circuit */
CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE;
if(wait != 0u)
while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
{
- /* Wait for the interrupt status */
+ /* Wait for interrupt status */
if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))
{
if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))
* None
*
* Side Effects:
-* If as result of this function execution the CPU clock frequency is increased
+* If this function execution results in the CPU clock frequency increasing,
* then the number of clock cycles the cache will wait before it samples data
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-* with appropriate parameter. It can be optionally called if CPU clock
-* frequency is lowered in order to improve CPU performance.
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+* with an appropriate parameter. It can be optionally called if the CPU clock
+* frequency is lowered in order to improve the CPU performance.
* See CyFlash_SetWaitCycles() description for more information.
*
*******************************************************************************/
* None
*
* Side Effects:
-* If as result of this function execution the CPU clock frequency is increased
+* If this function execution results in the CPU clock frequency increasing,
* then the number of clock cycles the cache will wait before it samples data
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-* with appropriate parameter. It can be optionally called if CPU clock
-* frequency is lowered in order to improve CPU performance.
+* coming back from the3 Flash must be adjusted by calling CyFlash_SetWaitCycles()
+* with an appropriate parameter. It can be optionally called if the CPU clock
+* frequency is lowered in order to improve the CPU performance.
* See CyFlash_SetWaitCycles() description for more information.
*
*******************************************************************************/
* None
*
* Side Effects:
-* If wait is enabled: This function wses the Fast Time Wheel to time the wait.
+* If wait is enabled: This function uses the Fast Time Wheel to time the wait.
* Any other use of the Fast Time Wheel will be stopped during the period of
* this function and then restored. This function also uses the 100 KHz ILO.
* If not enabled, this function will enable the 100 KHz ILO for the period of
if(0u != wait)
{
- /* Need to turn on the 100KHz ILO if it happens to not already be running.*/
+ /* Need to turn on 100KHz ILO if it happens to not already be running.*/
ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ;
pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG;
pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG;
while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
{
- /* Wait for the interrupt status */
+ /* Wait for interrupt status */
}
if(0u == ilo100KhzEnable)
/* If USB is powered */
if(usbPowerOn == 1u)
{
- /* Lock the USB Oscillator */
+ /* Lock USB Oscillator */
CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN;
}
break;
* None
*
* Side Effects:
-* If as result of this function execution the CPU clock frequency is increased
+* If this function execution results in the CPU clock frequency increasing,
* then the number of clock cycles the cache will wait before it samples data
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-* with appropriate parameter. It can be optionally called if CPU clock
-* frequency is lowered in order to improve CPU performance.
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+* with an appropriate parameter. It can be optionally called if the CPU clock
+* frequency is lowered in order to improve the CPU performance.
* See CyFlash_SetWaitCycles() description for more information.
*
* When the USB setting is chosen, the USB clock locking circuit is enabled.
uint8 nextFreq;
/***************************************************************************
- * When changing the IMO frequency the Trim values must also be set
+ * If the IMO frequency is changed,the Trim values must also be set
* accordingly.This requires reading the current frequency. If the new
- * frequency is faster, then set the new trim and then change the frequency,
- * otherwise change the frequency and then set the new trim values.
+ * frequency is faster, then set a new trim and then change the frequency,
+ * otherwise change the frequency and then set new trim values.
***************************************************************************/
currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK));
- /* Check if the requested frequency is USB. */
+ /* Check if requested frequency is USB. */
nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq;
switch (currentFreq)
if (nextFreq >= currentFreq)
{
- /* Set the new trim first */
+ /* Set new trim first */
CyIMO_SetTrimValue(freq);
}
- /* Set the usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */
+ /* Set usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */
switch(freq)
{
case CY_IMO_FREQ_3MHZ:
break;
}
- /* Turn on the IMO Doubler, if switching to CY_IMO_FREQ_USB */
+ /* Tu rn onIMO Doubler, if switching to CY_IMO_FREQ_USB */
if (freq == CY_IMO_FREQ_USB)
{
CyIMO_EnableDoubler();
if (nextFreq < currentFreq)
{
- /* Set the new trim after setting the frequency */
+ /* Set the trim after setting frequency */
CyIMO_SetTrimValue(freq);
}
}
* Sets the source of the clock output from the IMO block.
*
* The output from the IMO is by default the IMO itself. Optionally the MHz
-* Crystal or a DSI input can be the source of the IMO output instead.
+* Crystal or DSI input can be the source of the IMO output instead.
*
* Parameters:
* source: CY_IMO_SOURCE_DSI to set the DSI as source.
* None
*
* Side Effects:
-* If as result of this function execution the CPU clock frequency is increased
+* If this function execution resulted in the CPU clock frequency increasing,
* then the number of clock cycles the cache will wait before it samples data
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-* with appropriate parameter. It can be optionally called if CPU clock
-* frequency is lowered in order to improve CPU performance.
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+* with an appropriate parameter. It can be optionally called if the CPU clock
+* frequency is lowered in order to improve the CPU performance.
* See CyFlash_SetWaitCycles() description for more information.
*
*******************************************************************************/
*******************************************************************************/
void CyIMO_EnableDoubler(void)
{
- /* Set the FASTCLK_IMO_CR_PTR regigster's 4th bit */
+ /* Set FASTCLK_IMO_CR_PTR regigster's 4th bit */
CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER;
}
* The current source and the new source must both be running and stable before
* calling this function.
*
-* If as result of this function execution the CPU clock frequency is increased
+* If this function execution resulted in the CPU clock frequency increasing,
* then the number of clock cycles the cache will wait before it samples data
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-* with appropriate parameter. It can be optionally called if CPU clock
-* frequency is lowered in order to improve CPU performance.
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+* with an appropriate parameter. It can be optionally called if the CPU clock
+* frequency is lowered in order to improve the CPU performance.
* See CyFlash_SetWaitCycles() description for more information.
*
*******************************************************************************/
*
* Parameters:
* uint8 divider:
-* Valid range [0-255]. The clock will be divided by this value + 1.
-* For example to divide by 2 this parameter should be set to 1.
+* The valid range is [0-255]. The clock will be divided by this value + 1.
+* For example to divide this parameter by two should be set to 1.
*
* Return:
* None
*
* Side Effects:
-* If as result of this function execution the CPU clock frequency is increased
+* If this function execution resulted in the CPU clock frequency increasing,
* then the number of clock cycles the cache will wait before it samples data
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-* with appropriate parameter. It can be optionally called if CPU clock
-* frequency is lowered in order to improve CPU performance.
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+* with an appropriate parameter. It can be optionally called if the CPU clock
+* frequency is lowered in order to improve the CPU performance.
* See CyFlash_SetWaitCycles() description for more information.
*
* When changing the Master or Bus clock divider value from div-by-n to div-by-1
********************************************************************************
*
* Summary:
-* Function used by CyBusClk_SetDivider(). For internal use only.
+* The function used by CyBusClk_SetDivider(). For internal use only.
*
* Parameters:
* divider: Valid range [0-65535].
* The clock will be divided by this value + 1.
-* For example to divide by 2 this parameter should be set to 1.
+* For example, to divide this parameter by two should be set to 1.
*
* Return:
* None
/* Enable mask bits to enable shadow loads */
CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK;
- /* Update Shadow Divider Value Register with the new divider */
+ /* Update Shadow Divider Value Register with new divider */
CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider);
CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider);
********************************************************************************
*
* Summary:
-* Sets the divider value used to generate Bus Clock.
+* Sets the divider value used to generate the Bus Clock.
*
* Parameters:
* divider: Valid range [0-65535]. The clock will be divided by this value + 1.
-* For example to divide by 2 this parameter should be set to 1.
+* For example, to divide this parameter by two should be set to 1.
*
* Return:
* None
*
* Side Effects:
-* If as result of this function execution the CPU clock frequency is increased
+* If this function execution resulted in the CPU clock frequency increasing,
* then the number of clock cycles the cache will wait before it samples data
-* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
-* with appropriate parameter. It can be optionally called if CPU clock
-* frequency is lowered in order to improve CPU performance.
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+* with an appropriate parameter. It can be optionally called if the CPU clock
+* frequency is lowered in order to improve the CPU performance.
* See CyFlash_SetWaitCycles() description for more information.
*
*******************************************************************************/
interruptState = CyEnterCriticalSection();
- /* Work around to set the bus clock divider value */
+ /* Work around to set bus clock divider value */
busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u);
busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG;
if ((divider == 0u) || (busClkDiv == 0u))
{
- /* Save away the master clock divider value */
+ /* Save away master clock divider value */
masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG;
if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV)
if (divider == 0u)
{
- /* Set the SSS bit and the divider register desired value */
+ /* Set SSS bit and divider register desired value */
CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS;
CyBusClk_Internal_SetDivider(divider);
}
CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS));
}
- /* Restore the master clock */
+ /* Restore master clock */
CyMasterClk_SetDivider(masterClkDiv);
}
else
*
* Parameters:
* divider: Valid range [0-15]. The clock will be divided by this value + 1.
- * For example to divide by 2 this parameter should be set to 1.
+ * For example, to divide this parameter by two should be set to 1.
*
* Return:
* None
*
* Side Effects:
- * If as result of this function execution the CPU clock frequency is increased
- * then the number of clock cycles the cache will wait before it samples data
- * coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()
- * with appropriate parameter. It can be optionally called if CPU clock
- * frequency is lowered in order to improve CPU performance.
+ * If this function execution resulted in the CPU clock frequency increasing,
+* then the number of clock cycles the cache will wait before it samples data
+* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles()
+* with an appropriate parameter. It can be optionally called if the CPU clock
+* frequency is lowered in order to improve the CPU performance.
* See CyFlash_SetWaitCycles() description for more information.
*
*******************************************************************************/
*******************************************************************************/
void CyILO_Start1K(void)
{
- /* Set the bit 1 of ILO RS */
+ /* Set bit 1 of ILO RS */
CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ;
}
* Summary:
* Disables the ILO 1 KHz oscillator.
*
-* Note The ILO 1 KHz oscillator must be enabled if Sleep or Hibernate low power
+* Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low power
* mode APIs are expected to be used. For more information, refer to the Power
* Management section of this document.
*
*******************************************************************************/
void CyILO_Stop1K(void)
{
- /* Clear the bit 1 of ILO RS */
+ /* Clear bit 1 of ILO RS */
CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ));
}
*******************************************************************************/
void CyILO_Enable33K(void)
{
- /* Set the bit 5 of ILO RS */
+ /* Set bit 5 of ILO RS */
CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ;
}
/* Get current state. */
state = CY_LIB_SLOWCLK_ILO_CR0_REG;
- /* Set the the oscillator power mode. */
+ /* Set the oscillator power mode. */
if(mode != CY_ILO_FAST_START)
{
CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE);
CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE)));
}
- /* Return the old mode. */
+ /* Return old mode. */
return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION);
}
CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN;
#endif /* (CY_PSOC3) */
- /* Enable operation of the 32K Crystal Oscillator */
+ /* Enable operation of 32K Crystal Oscillator */
CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN;
for (i = 1000u; i > 0u; i--)
{
if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT))
{
- /* Ready - switch to the hign power mode */
+ /* Ready - switch to high power mode */
(void) CyXTAL_32KHZ_SetPowerMode(0u);
break;
********************************************************************************
*
* Summary:
-* Sets the power mode for the 32 KHz oscillator used during sleep mode.
+* Sets the power mode for the 32 KHz oscillator used during the sleep mode.
* Allows for lower power during sleep when there are fewer sources of noise.
-* During active mode the oscillator is always run in high power mode.
+* During the active mode the oscillator is always run in the high power mode.
*
* Parameters:
* uint8 mode
uint8 pmTwCfg2Tmp;
- /* Enables the MHz crystal oscillator circuit */
+ /* Enables MHz crystal oscillator circuit */
CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE;
/* Read XERR bit to clear it */
(void) CY_CLK_XMHZ_CSR_REG;
- /* Wait for a millisecond - 4 x 250 us */
+ /* Wait for 1 millisecond - 4 x 250 us */
for(count = 4u; count > 0u; count--)
{
while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT)))
{
- /* Wait for the FTW interrupt event */
+ /* Wait for FTW interrupt event */
}
}
/*******************************************************************
- * High output indicates oscillator failure.
- * Only can be used after start-up interval (1 ms) is completed.
+ * High output indicates an oscillator failure.
+ * Only can be used after a start-up interval (1 ms) is completed.
*******************************************************************/
if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR))
{
*******************************************************************************/
void CyXTAL_Stop(void)
{
- /* Disable the the oscillator. */
+ /* Disable oscillator. */
FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE));
}
*
* Summary:
* Reads the XERR status bit for the megahertz crystal. This status bit is a
-* sticky clear on read value. This function is not available for PSoC5.
+* sticky, clear on read. This function is not available for PSoC5.
*
* Parameters:
* None
uint8 CyXTAL_ReadStatus(void)
{
/***************************************************************************
- * High output indicates oscillator failure. Only use this after start-up
- * interval is completed. This can be used for status and failure recovery.
+ * High output indicates an oscillator failure. Only use this after a start-up
+ * interval is completed. This can be used for the status and failure recovery.
***************************************************************************/
return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u);
}
* Enables the fault recovery circuit which will switch to the IMO in the case
* of a fault in the megahertz crystal circuit. The crystal must be up and
* running with the XERR bit at 0, before calling this function to prevent
-* immediate fault switchover. This function is not available for PSoC5.
+* an immediate fault switchover. This function is not available for PSoC5.
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* Sets the startup settings for the crystal. Logic model outputs a frequency
+* Sets the startup settings for the crystal. The logic model outputs a frequency
* (setting + 4) MHz when enabled.
*
* This is artificial as the actual frequency is determined by an attached
*
* Parameters:
* setting: Valid range [0-31].
-* Value is dependent on the frequency and quality of the crystal being used.
+* The value is dependent on the frequency and quality of the crystal being used.
* Refer to the device TRM and datasheet for more information.
*
* Return:
********************************************************************************
*
* Summary:
-* Forces a software reset of the device.
+* Forces a device software reset.
*
* Parameters:
* None
*
* Note:
* CyDelay has been implemented with the instruction cache assumed enabled. When
-* instruction cache is disabled on PSoC5, CyDelay will be two times larger. For
-* example, with instruction cache disabled CyDelay(100) would result in about
-* 200 ms delay instead of 100 ms.
+* the instruction cache is disabled on PSoC5, CyDelay will be two times larger.
+* For example, with instruction cache disabled CyDelay(100) would result in
+* about 200 ms delay instead of 100 ms.
*
* Parameters:
* milliseconds: number of milliseconds to delay.
*
* Side Effects:
* CyDelayUS has been implemented with the instruction cache assumed enabled.
- * When instruction cache is disabled on PSoC 5, CyDelayUs will be two times
- * larger. For example, with instruction cache disabled CyDelayUs(100) would
+ * When the instruction cache is disabled on PSoC 5, CyDelayUs will be two times
+ * larger. For example, with the instruction cache disabled CyDelayUs(100) would
* result in about 200 us delay instead of 100 us.
*
* If the bus clock frequency is a small non-integer number, the actual delay
********************************************************************************
*
* Summary:
-* Sets clock frequency for CyDelay.
+* Sets the clock frequency for CyDelay.
*
* Parameters:
-* freq: Frequency of bus clock in Hertz.
+* freq: The frequency of the bus clock in Hertz.
*
* Return:
* None
* Enables the watchdog timer.
*
* The timer is configured for the specified count interval, the central
-* timewheel is cleared, the setting for low power mode is configured and the
+* timewheel is cleared, the setting for the low power mode is configured and the
* watchdog timer is enabled.
*
* Once enabled the watchdog cannot be disabled. The watchdog counts each time
CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET;
CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET));
- /* Setting the low power mode */
+ /* Setting low power mode */
CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) |
(CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK)));
- /* Enables the watchdog reset */
+ /* Enables watchdog reset */
CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN;
}
*
* Summary:
* Enables the digital low voltage monitors to generate interrupt on Vddd
-* archives specified threshold and optionally resets device.
+* archives specified threshold and optionally resets the device.
*
* Parameters:
-* reset: Option to reset device at a specified Vddd threshold:
+* reset: The option to reset the device at a specified Vddd threshold:
* 0 - Device is not reset.
* 1 - Device is reset.
*
* threshold: Sets the trip level for the voltage monitor.
-* Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV
-* interval.
+* Values from 1.70 V to 5.45 V are accepted with an interval of approximately
+* 250 mV.
*
* Return:
* None
(CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK)));
CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN;
- /* Timeout to eliminate glitches on the LVI/HVI when enabling */
+ /* Timeout to eliminate glitches on LVI/HVI when enabling */
CyDelayUs(1u);
(void)CY_VD_PERSISTENT_STATUS_REG;
*
* Summary:
* Enables the analog low voltage monitors to generate interrupt on Vdda
-* archives specified threshold and optionally resets device.
+* archives specified threshold and optionally resets the device.
*
* Parameters:
-* reset: Option to reset device at a specified Vdda threshold:
+* reset: The option to reset the device at a specified Vdda threshold:
* 0 - Device is not reset.
* 1 - Device is reset.
*
CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu);
CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN;
- /* Timeout to eliminate glitches on the LVI/HVI when enabling */
+ /* Timeout to eliminate glitches on LVI/HVI when enabling */
CyDelayUs(1u);
(void)CY_VD_PERSISTENT_STATUS_REG;
CY_NOP;
CY_NOP;
- /* All entries in the cache are invalidated on the next clock cycle. */
+ /* All entries in cache are invalidated on next clock cycle. */
CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH;
+ /* Once this is executed it's guaranteed the cache has been flushed */
+ (void) CY_CACHE_CONTROL_REG;
- /***********************************************************************
- * The prefetch unit could/would be filled with the instructions that
- * succeed the flush. Since a flush is desired then theoretically those
- * instructions might be considered stale/invalid.
- ***********************************************************************/
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
- CY_NOP;
+ /* Flush the pipeline */
+ CY_SYS_ISB;
/* Restore global interrupt enable state */
CyExitCriticalSection(interruptState);
* SysTick, PendSV and others.
*
* Parameters:
- * number: Interrupt number, valid range [0-15].
- address: Pointer to an interrupt service routine.
+ * number: System interrupt number:
+ * CY_INT_NMI_IRQN - Non Maskable Interrupt
+ * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt
+ * CY_INT_MEM_MANAGE_IRQN - Memory Management Interrupt
+ * CY_INT_BUS_FAULT_IRQN - Bus Fault Interrupt
+ * CY_INT_USAGE_FAULT_IRQN - Usage Fault Interrupt
+ * CY_INT_SVCALL_IRQN - SV Call Interrupt
+ * CY_INT_DEBUG_MONITOR_IRQN - Debug Monitor Interrupt
+ * CY_INT_PEND_SV_IRQN - Pend SV Interrupt
+ * CY_INT_SYSTICK_IRQN - System Tick Interrupt
+ *
+ * address: Pointer to an interrupt service routine.
*
* Return:
* The old ISR vector at this location.
* SysTick, PendSV and others.
*
* Parameters:
- * number: The interrupt number, valid range [0-15].
+ * number: System interrupt number:
+ * CY_INT_NMI_IRQN - Non Maskable Interrupt
+ * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt
+ * CY_INT_MEMORY_MANAGEMENT_IRQN - Memory Management Interrupt
+ * CY_INT_BUS_FAULT_IRQN - Bus Fault Interrupt
+ * CY_INT_USAGE_FAULT_IRQN - Usage Fault Interrupt
+ * CY_INT_SVCALL_IRQN - SV Call Interrupt
+ * CY_INT_DEBUG_MONITOR_IRQN - Debug Monitor Interrupt
+ * CY_INT_PEND_SV_IRQN - Pend SV Interrupt
+ * CY_INT_SYSTICK_IRQN - System Tick Interrupt
*
* Return:
* Address of the ISR in the interrupt vector table.
* number: Valid range [0-31]. Interrupt number
*
* Return:
- * Address of the ISR in the interrupt vector table.
+ * The address of the ISR in the interrupt vector table.
*
*******************************************************************************/
cyisraddress CyIntGetVector(uint8 number)
CYASSERT(number <= CY_INT_NUMBER_MAX);
- /* Get a pointer to the Interrupt enable register. */
+ /* Get pointer to Interrupt enable register. */
stateReg = CY_INT_ENABLE_PTR;
- /* Get the state of the interrupt. */
+ /* Get state of interrupt. */
return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u));
}
CYASSERT(number <= CY_INT_NUMBER_MAX);
- /* Get a pointer to the Interrupt enable register. */
+ /* Get pointer to Interrupt enable register. */
stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u);
- /* Get the state of the interrupt. */
+ /* Get state of interrupt. */
return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u)));
}
* If 1 is passed as a parameter:
* - if any of the SC blocks are used - enable pumps for the SC blocks and
* start boost clock.
- * - For the each enabled SC block set boost clock index and enable boost
+ * - For each enabled SC block set a boost clock index and enable the boost
* clock.
*
* If non-1 value is passed as a parameter:
* - If all SC blocks are not used - disable pumps for the SC blocks and
- * stop boost clock.
- * - For the each enabled SC block clear boost clock index and disable boost
+ * stop the boost clock.
+ * - For each enabled SC block clear the boost clock index and disable the boost
* clock.
*
- * The global variable CyScPumpEnabled is updated to be equal to passed
+ * The global variable CyScPumpEnabled is updated to be equal to passed the
* parameter.
*
* Parameters:
- * uint8 enable: Enable/disable SC pumps and boost clock for enabled SC block.
+ * uint8 enable: Enable/disable SC pumps and the boost clock for the enabled SC block.
* 1 - Enable
* 0 - Disable
*
#endif /* (CYDEV_VARIABLE_VDDA == 1) */
+#if(CY_PSOC5)
+ /*******************************************************************************
+ * Function Name: CySysTickStart
+ ********************************************************************************
+ *
+ * Summary:
+ * Configures the SysTick timer to generate interrupt every 1 ms by call to the
+ * CySysTickInit() function and starts it by calling CySysTickEnable() function.
+ * Refer to the corresponding function description for the details.
+
+ * Parameters:
+ * None
+ *
+ * Return:
+ * None
+ *
+ * Side Effects:
+ * Clears SysTick count flag if it was set
+ *
+ *******************************************************************************/
+ void CySysTickStart(void)
+ {
+ if (0u == CySysTickInitVar)
+ {
+ CySysTickInit();
+ CySysTickInitVar = 1u;
+ }
+
+ CySysTickEnable();
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickInit
+ ********************************************************************************
+ *
+ * Summary:
+ * Initializes the callback addresses with pointers to NULL, associates the
+ * SysTick system vector with the function that is responsible for calling
+ * registered callback functions, configures SysTick timer to generate interrupt
+ * every 1 ms.
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * None
+ *
+ * Side Effects:
+ * Clears SysTick count flag if it was set.
+ *
+ * The 1 ms interrupt interval is configured based on the frequency determined
+ * by PSoC Creator at build time. If System clock frequency is changed in
+ * runtime, the CyDelayFreq() with the appropriate parameter should be called.
+ *
+ *******************************************************************************/
+ void CySysTickInit(void)
+ {
+ uint32 i;
+
+ for (i = 0u; i<CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+ {
+ CySysTickCallbacks[i] = (void *) 0;
+ }
+
+ (void) CyIntSetSysVector(CY_INT_SYSTICK_IRQN, &CySysTickServiceCallbacks);
+ CySysTickSetClockSource(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK);
+ CySysTickSetReload(cydelay_freq_hz/1000u);
+ CySysTickClear();
+ CyIntEnable(CY_INT_SYSTICK_IRQN);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickEnable
+ ********************************************************************************
+ *
+ * Summary:
+ * Enables the SysTick timer and its interrupt.
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * None
+ *
+ * Side Effects:
+ * Clears SysTick count flag if it was set
+ *
+ *******************************************************************************/
+ void CySysTickEnable(void)
+ {
+ CySysTickEnableInterrupt();
+ CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE;
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickStop
+ ********************************************************************************
+ *
+ * Summary:
+ * Stops the system timer (SysTick).
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * None
+ *
+ * Side Effects:
+ * Clears SysTick count flag if it was set
+ *
+ *******************************************************************************/
+ void CySysTickStop(void)
+ {
+ CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE));
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickEnableInterrupt
+ ********************************************************************************
+ *
+ * Summary:
+ * Enables the SysTick interrupt.
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * None
+ *
+ * Side Effects:
+ * Clears SysTick count flag if it was set
+ *
+ *******************************************************************************/
+ void CySysTickEnableInterrupt(void)
+ {
+ CY_SYS_SYST_CSR_REG |= CY_SYS_SYST_CSR_ENABLE_INT;
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickDisableInterrupt
+ ********************************************************************************
+ *
+ * Summary:
+ * Disables the SysTick interrupt.
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * None
+ *
+ * Side Effects:
+ * Clears SysTick count flag if it was set
+ *
+ *******************************************************************************/
+ void CySysTickDisableInterrupt(void)
+ {
+ CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_ENABLE_INT));
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickSetReload
+ ********************************************************************************
+ *
+ * Summary:
+ * Sets value the counter is set to on startup and after it reaches zero. This
+ * function do not change or reset current sysTick counter value, so it should
+ * be cleared using CySysTickClear() API.
+ *
+ * Parameters:
+ * value: Valid range [0x0-0x00FFFFFF]. Counter reset value.
+ *
+ * Return:
+ * None
+ *
+ *******************************************************************************/
+ void CySysTickSetReload(uint32 value)
+ {
+ CY_SYS_SYST_RVR_REG = (value & CY_SYS_SYST_RVR_CNT_MASK);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickGetReload
+ ********************************************************************************
+ *
+ * Summary:
+ * Sets value the counter is set to on startup and after it reaches zero.
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * Counter reset value
+ *
+ *******************************************************************************/
+ uint32 CySysTickGetReload(void)
+ {
+ return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_RVR_CNT_MASK);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickGetValue
+ ********************************************************************************
+ *
+ * Summary:
+ * Gets current SysTick counter value.
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * Current SysTick counter value
+ *
+ *******************************************************************************/
+ uint32 CySysTickGetValue(void)
+ {
+ return(CY_SYS_SYST_RVR_REG & CY_SYS_SYST_CVR_REG);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickSetClockSource
+ ********************************************************************************
+ *
+ * Summary:
+ * Sets the clock source for the SysTick counter.
+ *
+ * Parameters:
+ * clockSource: Clock source for SysTick counter
+ * Define Clock Source
+ * CY_SYS_SYST_CSR_CLK_SRC_SYSCLK SysTick is clocked by CPU clock.
+ * CY_SYS_SYST_CSR_CLK_SRC_LFCLK SysTick is clocked by the low frequency
+ * clock (ILO 100 KHz for PSoC 5LP, LFCLK for PSoC 4).
+ *
+ * Return:
+ * None
+ *
+ * Side Effects:
+ * Clears SysTick count flag if it was set. If clock source is not ready this
+ * function call will have no effect. After changing clock source to the low frequency
+ * clock the counter and reload register values will remain unchanged so time to
+ * the interrupt will be significantly bigger and vice versa.
+ *
+ *******************************************************************************/
+ void CySysTickSetClockSource(uint32 clockSource)
+ {
+ if (clockSource == CY_SYS_SYST_CSR_CLK_SRC_SYSCLK)
+ {
+ CY_SYS_SYST_CSR_REG |= (uint32)(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT);
+ }
+ else
+ {
+ CY_SYS_SYST_CSR_REG &= ((uint32) ~(CY_SYS_SYST_CSR_CLK_SRC_SYSCLK << CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT));
+ }
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickGetCountFlag
+ ********************************************************************************
+ *
+ * Summary:
+ * The count flag is set once SysTick counter reaches zero.
+ * The flag cleared on read.
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * Returns non-zero value if counter is set, otherwise zero is returned.
+ *
+ *******************************************************************************/
+ uint32 CySysTickGetCountFlag(void)
+ {
+ return ((CY_SYS_SYST_CSR_REG>>CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickClear
+ ********************************************************************************
+ *
+ * Summary:
+ * Clears the SysTick counter for well-defined startup.
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * None
+ *
+ *******************************************************************************/
+ void CySysTickClear(void)
+ {
+ CY_SYS_SYST_CVR_REG = 0u;
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickSetCallback
+ ********************************************************************************
+ *
+ * Summary:
+ * The function set the pointers to the functions that will be called on
+ * SysTick interrupt.
+ *
+ * Parameters:
+ * number: The number of callback function address to be set.
+ * The valid range is from 0 to 4.
+ * CallbackFunction: Function address.
+ *
+ * Return:
+ * Returns the address of the previous callback function.
+ * The NULL is returned if the specified address in not set.
+ *
+ *******************************************************************************/
+ cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function)
+ {
+ cySysTickCallback retVal;
+
+ retVal = CySysTickCallbacks[number];
+ CySysTickCallbacks[number] = function;
+ return (retVal);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickGetCallback
+ ********************************************************************************
+ *
+ * Summary:
+ * The function get the specified callback pointer.
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * None
+ *
+ *******************************************************************************/
+ cySysTickCallback CySysTickGetCallback(uint32 number)
+ {
+ return ((cySysTickCallback) CySysTickCallbacks[number]);
+ }
+
+
+ /*******************************************************************************
+ * Function Name: CySysTickServiceCallbacks
+ ********************************************************************************
+ *
+ * Summary:
+ * System Tick timer interrupt routine
+ *
+ * Parameters:
+ * None
+ *
+ * Return:
+ * None
+ *
+ *******************************************************************************/
+ static void CySysTickServiceCallbacks(void)
+ {
+ uint32 i;
+
+ /* Verify that tick timer flag was set */
+ if (1u == CySysTickGetCountFlag())
+ {
+ for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++)
+ {
+ if (CySysTickCallbacks[i] != (void *) 0)
+ {
+ (void)(CySysTickCallbacks[i])();
+ }
+ }
+ }
+ }
+#endif /* (CY_PSOC5) */
+
+
/* [] END OF FILE */
/*******************************************************************************
* File Name: CyLib.h
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides the function definitions for the system, clocking, interrupts and
* Guide provided with PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
void CySetScPumps(uint8 enable) ;
+#if(CY_PSOC5)
+ /* Default interrupt handler */
+ CY_ISR_PROTO(IntDefaultHandler);
+#endif /* (CY_PSOC5) */
+
+#if(CY_PSOC5)
+ /* System tick timer APIs */
+ typedef void (*cySysTickCallback)(void);
+
+ void CySysTickStart(void);
+ void CySysTickInit(void);
+ void CySysTickEnable(void);
+ void CySysTickStop(void);
+ void CySysTickEnableInterrupt(void);
+ void CySysTickDisableInterrupt(void);
+ void CySysTickSetReload(uint32 value);
+ uint32 CySysTickGetReload(void);
+ uint32 CySysTickGetValue(void);
+ cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function);
+ cySysTickCallback CySysTickGetCallback(uint32 number);
+ void CySysTickSetClockSource(uint32 clockSource);
+ uint32 CySysTickGetCountFlag(void);
+ void CySysTickClear(void);
+#endif /* (CY_PSOC5) */
/***************************************
* API Constants
#define CY_ALT_ACT_USB_ENABLED (0x01u)
+#if(CY_PSOC5)
+
+ /***************************************************************************
+ * Instruction Synchronization Barrier flushes the pipeline in the processor,
+ * so that all instructions following the ISB are fetched from cache or
+ * memory, after the instruction has been completed.
+ ***************************************************************************/
+
+ #if defined(__ARMCC_VERSION)
+ #define CY_SYS_ISB __isb(0x0f)
+ #else /* ASM for GCC & IAR */
+ #define CY_SYS_ISB asm volatile ("isb \n")
+ #endif /* (__ARMCC_VERSION) */
+
+#endif /* (CY_PSOC5) */
+
+
/***************************************
* Registers
***************************************/
#define CY_CACHE_CONTROL_REG (* (reg16 *) CYREG_CACHE_CC_CTL )
#define CY_CACHE_CONTROL_PTR ( (reg16 *) CYREG_CACHE_CC_CTL )
+ /* System tick registers */
+ #define CY_SYS_SYST_CSR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CTL)
+ #define CY_SYS_SYST_CSR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CTL)
+
+ #define CY_SYS_SYST_RVR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_RELOAD)
+ #define CY_SYS_SYST_RVR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_RELOAD)
+
+ #define CY_SYS_SYST_CVR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CURRENT)
+ #define CY_SYS_SYST_CVR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CURRENT)
+
+ #define CY_SYS_SYST_CALIB_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CAL)
+ #define CY_SYS_SYST_CALIB_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CAL)
+
#elif (CY_PSOC3)
/* Interrupt Address Vector registers */
#define CY_INT_VECT_TABLE ((cyisraddress CYXDATA *) CYREG_INTC_VECT_MBASE)
- /* Interrrupt Controller Priority Registers */
+ /* Interrupt Controller Priority Registers */
#define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_INTC_PRIOR0)
#define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_INTC_PRIOR0)
- /* Interrrupt Controller Set Enable Registers */
+ /* Interrupt Controller Set Enable Registers */
#define CY_INT_ENABLE_REG (* (reg8 *) CYREG_INTC_SET_EN0)
#define CY_INT_ENABLE_PTR ( (reg8 *) CYREG_INTC_SET_EN0)
#define CY_INT_SET_EN3_REG (* (reg8 *) CYREG_INTC_SET_EN3)
#define CY_INT_SET_EN3_PTR ( (reg8 *) CYREG_INTC_SET_EN3)
- /* Interrrupt Controller Clear Enable Registers */
+ /* Interrupt Controller Clear Enable Registers */
#define CY_INT_CLEAR_REG (* (reg8 *) CYREG_INTC_CLR_EN0)
#define CY_INT_CLEAR_PTR ( (reg8 *) CYREG_INTC_CLR_EN0)
#define CY_INT_CLR_EN3_PTR ( (reg8 *) CYREG_INTC_CLR_EN3)
- /* Interrrupt Controller Set Pend Registers */
+ /* Interrupt Controller Set Pend Registers */
#define CY_INT_SET_PEND_REG (* (reg8 *) CYREG_INTC_SET_PD0)
#define CY_INT_SET_PEND_PTR ( (reg8 *) CYREG_INTC_SET_PD0)
- /* Interrrupt Controller Clear Pend Registers */
+ /* Interrupt Controller Clear Pend Registers */
#define CY_INT_CLR_PEND_REG (* (reg8 *) CYREG_INTC_CLR_PD0)
#define CY_INT_CLR_PEND_PTR ( (reg8 *) CYREG_INTC_CLR_PD0)
* Macro Name: CyAssert
********************************************************************************
* Summary:
-* Macro that evaluates the expression and if it is false (evaluates to 0) then
-* the processor is halted.
+* The macro that evaluates the expression and if it is false (evaluates to 0)
+* then the processor is halted.
*
* This macro is evaluated unless NDEBUG is defined.
*
#define CY_RESET_GPIO1 (0x80u)
-/* Interrrupt Controller Configuration and Status Register */
+/* Interrupt Controller Configuration and Status Register */
#if(CY_PSOC3)
#define INTERRUPT_CSR ((reg8 *) CYREG_INTC_CSR_EN)
#define DISABLE_IRQ_SET ((uint8)(0x01u << 1u)) /* INTC_CSR_EN */
#define CY_CACHE_CONTROL_FLUSH (0x0004u)
#define CY_LIB_RESET_CR2_RESET (0x01u)
+#if(CY_PSOC5)
+ /* System tick API constants */
+ #define CY_SYS_SYST_CSR_ENABLE ((uint32) (0x01u))
+ #define CY_SYS_SYST_CSR_ENABLE_INT ((uint32) (0x02u))
+ #define CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT ((uint32) (0x02u))
+ #define CY_SYS_SYST_CSR_COUNTFLAG_SHIFT ((uint32) (16u))
+ #define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ((uint32) (1u))
+ #define CY_SYS_SYST_CSR_CLK_SRC_LFCLK ((uint32) (0u))
+ #define CY_SYS_SYST_RVR_CNT_MASK ((uint32) (0x00FFFFFFu))
+ #define CY_SYS_SYST_NUM_OF_CALLBACKS ((uint32) (5u))
+#endif /* (CY_PSOC5) */
+
+
/*******************************************************************************
* Interrupt API constants
/* Mask to get valid range of system interrupt 0-15 */
#define CY_INT_SYS_NUMBER_MASK (0xFu)
+#if(CY_PSOC5)
+
+ /* CyIntSetSysVector()/CyIntGetSysVector() - parameter definitions */
+ #define CY_INT_NMI_IRQN ( 2u) /* Non Maskable Interrupt */
+ #define CY_INT_HARD_FAULT_IRQN ( 3u) /* Hard Fault Interrupt */
+ #define CY_INT_MEM_MANAGE_IRQN ( 4u) /* Memory Management Interrupt */
+ #define CY_INT_BUS_FAULT_IRQN ( 5u) /* Bus Fault Interrupt */
+ #define CY_INT_USAGE_FAULT_IRQN ( 6u) /* Usage Fault Interrupt */
+ #define CY_INT_SVCALL_IRQN (11u) /* SV Call Interrupt */
+ #define CY_INT_DEBUG_MONITOR_IRQN (12u) /* Debug Monitor Interrupt */
+ #define CY_INT_PEND_SV_IRQN (14u) /* Pend SV Interrupt */
+ #define CY_INT_SYSTICK_IRQN (15u) /* System Tick Interrupt */
+
+#endif /* (CY_PSOC5) */
/*******************************************************************************
* Interrupt Macros
/*******************************************************************************
-* Following code are OBSOLETE and must not be used.
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+* #ifdef <OBSOLETED_DEFINE>
+* #undef <OBSOLETED_DEFINE>
+* #define <OBSOLETED_DEFINE> (<New Value>)
+* #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+* used in the application and their modification might lead to unexpected
+* consequences.
*******************************************************************************/
+
#define CYGlobalIntEnable CyGlobalIntEnable
#define CYGlobalIntDisable CyGlobalIntDisable
#define cymemset(s,c,n) memset((s),(c),(n))
#define cymemcpy(d,s,n) memcpy((d),(s),(n))
-
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
-*******************************************************************************/
#define MFGCFG_X32_TR_PTR (CY_CLK_XTAL32_TR_PTR)
#define MFGCFG_X32_TR (CY_CLK_XTAL32_TR_REG)
#define SLOWCLK_X32_TST_PTR (CY_CLK_XTAL32_TST_PTR)
#define CY_VD_PRESISTENT_STATUS_PTR (CY_VD_PERSISTENT_STATUS_PTR)
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.20
-*******************************************************************************/
-
#if(CY_PSOC5)
#define CYINT_IRQ_BASE (CY_INT_IRQ_BASE)
#endif /* (CY_PSOC5) */
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
-*******************************************************************************/
+
#define BUS_AMASK_CLEAR (0xF0u)
#define BUS_DMASK_CLEAR (0x00u)
#define CLKDIST_LD_LOAD_SET (0x01u)
#define CLKDIST_CR (*(reg8 *) CYREG_CLKDIST_CR)
-/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.50
-*******************************************************************************/
#define IMO_PM_ENABLE (0x10u)
#define PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)
#define PM_ACT_CFG0 (*(reg8 *) CYREG_PM_ACT_CFG0)
/*******************************************************************************
* File Name: CySpc.c
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides an API for the System Performance Component.
* application.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Summary:
* Loads a row of data into the row latch of a Flash/EEPROM array.
*
+* The buffer pointer should point to the data that should be written to the
+* flash row directly (no data in ECC/flash will be preserved). It is Flash API
+* responsibility to prepare data: the preserved data are copied from flash into
+* array with the modified data.
+*
* Parameters:
* uint8 array:
* Id of the array.
}
+/*******************************************************************************
+* Function Name: CySpcLoadRowFull
+********************************************************************************
+* Summary:
+* Loads a row of data into the row latch of a Flash/EEPROM array.
+*
+* The only data that are going to be changed should be passed. The function
+* will handle unmodified data preservation based on DWR settings and input
+* parameters.
+*
+* Parameters:
+* uint8 array:
+* Id of the array.
+*
+* uint16 row:
+* Flash row number to be loaded.
+*
+* uint8* buffer:
+* Data to be loaded to the row latch
+*
+* uint8 size:
+* The number of data bytes that the SPC expects to be written. Depends on the
+* type of the array and, if the array is Flash, whether ECC is being enabled
+* or not. There are following values: flash row latch size with ECC enabled,
+* flash row latch size with ECC disabled and EEPROM row latch size.
+*
+* Return:
+* CYRET_STARTED
+* CYRET_CANCELED
+* CYRET_LOCKED
+*
+*******************************************************************************/
+cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\
+
+{
+ cystatus status = CYRET_STARTED;
+ uint16 i;
+
+ #if (CYDEV_ECC_ENABLE == 0)
+ uint32 offset;
+ #endif /* (CYDEV_ECC_ENABLE == 0) */
+
+ /* Make sure the SPC is ready to accept command */
+ if(CY_SPC_IDLE)
+ {
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW);
+ CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW;
+
+ /* Make sure the command was accepted */
+ if(CY_SPC_BUSY)
+ {
+ CY_SPC_CPU_DATA_REG = array;
+
+ /*******************************************************************
+ * If "Enable Error Correcting Code (ECC)" and "Store Configuration
+ * Data in ECC" DWR options are disabled, ECC section is available
+ * for user data.
+ *******************************************************************/
+ #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))
+
+ /*******************************************************************
+ * If size parameter equals size of the ECC row and selected array
+ * identification corresponds to the flash array (but not to EEPROM
+ * array) then data are going to be written to the ECC section.
+ * In this case flash data must be preserved. The flash data copied
+ * from flash data section to the SPC data register.
+ *******************************************************************/
+ if ((size == CYDEV_ECC_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))
+ {
+ offset = CYDEV_FLS_BASE +
+ ((uint32) array * CYDEV_FLS_SECTOR_SIZE) +
+ ((uint32) row * CYDEV_FLS_ROW_SIZE );
+
+ for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
+ {
+ CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
+ }
+ }
+
+ #endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */
+
+
+ for(i = 0u; i < size; i++)
+ {
+ CY_SPC_CPU_DATA_REG = buffer[i];
+ }
+
+
+ /*******************************************************************
+ * If "Enable Error Correcting Code (ECC)" DWR option is disabled,
+ * ECC section can be used for storing device configuration data
+ * ("Store Configuration Data in ECC" DWR option is enabled) or for
+ * storing user data in the ECC section ("Store Configuration Data in
+ * ECC" DWR option is enabled). In both cases, the data in the ECC
+ * section must be preserved if flash data is written.
+ *******************************************************************/
+ #if (CYDEV_ECC_ENABLE == 0)
+
+
+ /*******************************************************************
+ * If size parameter equals size of the flash row and selected array
+ * identification corresponds to the flash array (but not to EEPROM
+ * array) then data are going to be written to the flash data
+ * section. In this case, ECC section data must be preserved.
+ * The ECC section data copied from ECC section to the SPC data
+ * register.
+ *******************************************************************/
+ if ((size == CYDEV_FLS_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID))
+ {
+ offset = CYDEV_ECC_BASE +
+ ((uint32) array * CYDEV_ECC_SECTOR_SIZE) +
+ ((uint32) row * CYDEV_ECC_ROW_SIZE );
+
+ for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
+ {
+ CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
+ }
+ }
+
+ #else
+
+ if(0u != row)
+ {
+ /* To remove unreferenced local variable warning */
+ }
+
+ #endif /* (CYDEV_ECC_ENABLE == 0) */
+ }
+ else
+ {
+ status = CYRET_CANCELED;
+ }
+ }
+ else
+ {
+ status = CYRET_LOCKED;
+ }
+
+ return(status);
+}
+
+
/*******************************************************************************
* Function Name: CySpcWriteRow
********************************************************************************
}
+/*******************************************************************************
+* Function Name: CySpcGetAlgorithm
+********************************************************************************
+* Summary:
+* Downloads SPC algorithm from SPC SROM into SRAM.
+*
+* Parameters:
+* None
+*
+* Return:
+* CYRET_STARTED
+* CYRET_LOCKED
+*
+*******************************************************************************/
+cystatus CySpcGetAlgorithm(void)
+{
+ cystatus status = CYRET_STARTED;
+
+ /* Make sure the SPC is ready to accept command */
+ if(CY_SPC_IDLE)
+ {
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_DWNLD_ALGORITHM);
+ CY_SPC_CPU_DATA_REG = CY_SPC_CMD_DWNLD_ALGORITHM;
+ }
+ else
+ {
+ status = CYRET_LOCKED;
+ }
+
+ return(status);
+}
+
/* [] END OF FILE */
+
/*******************************************************************************
* File Name: CySpc.c
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides definitions for the System Performance Component API.
* application.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\
;
cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size);
+cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\
+;
cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\
;
cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber);
cystatus CySpcGetTemp(uint8 numSamples);
+cystatus CySpcGetAlgorithm(void);
cystatus CySpcLock(void);
void CySpcUnlock(void);
#define CY_SPC_STATUS_CODE_MASK (0xFCu)
#define CY_SPC_STATUS_CODE_SHIFT (0x02u)
-/* Status codes for the SPC. */
+/* Status codes for SPC. */
#define CY_SPC_STATUS_SUCCESS (0x00u) /* Operation Successful */
#define CY_SPC_STATUS_INVALID_ARRAY_ID (0x01u) /* Invalid Array ID for given command */
#define CY_SPC_STATUS_INVALID_2BYTEKEY (0x02u) /* Invalid 2-byte key */
/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.0
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+* #ifdef <OBSOLETED_DEFINE>
+* #undef <OBSOLETED_DEFINE>
+* #define <OBSOLETED_DEFINE> (<New Value>)
+* #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+* used in the application and their modification might lead to unexpected
+* consequences.
*******************************************************************************/
#define FIRST_FLASH_ARRAYID (CY_SPC_FIRST_FLASH_ARRAYID)
#define LAST_FLASH_ARRAYID (CY_SPC_LAST_FLASH_ARRAYID)
/*******************************************************************************
* File Name: LED.c
-* Version 1.90
+* Version 2.10
*
* Description:
* This file contains API to enable firmware control of a Pins component.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Change the drive mode on the pins of the port.
*
* Parameters:
-* mode: Change the pins to this drive mode.
+* mode: Change the pins to one of the following drive modes.
+*
+* LED_DM_STRONG Strong Drive
+* LED_DM_OD_HI Open Drain, Drives High
+* LED_DM_OD_LO Open Drain, Drives Low
+* LED_DM_RES_UP Resistive Pull Up
+* LED_DM_RES_DWN Resistive Pull Down
+* LED_DM_RES_UPDWN Resistive Pull Up/Down
+* LED_DM_DIG_HIZ High Impedance Digital
+* LED_DM_ALG_HIZ High Impedance Analog
*
* Return:
* None
/*******************************************************************************
* File Name: LED.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
/*******************************************************************************
* File Name: LED.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define LED_0 LED__0__PC
+#define LED_0 (LED__0__PC)
#endif /* End Pins LED_ALIASES_H */
/*******************************************************************************
* File Name: SCSI_Out_DBx.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define SCSI_Out_DBx_0 SCSI_Out_DBx__0__PC
-#define SCSI_Out_DBx_1 SCSI_Out_DBx__1__PC
-#define SCSI_Out_DBx_2 SCSI_Out_DBx__2__PC
-#define SCSI_Out_DBx_3 SCSI_Out_DBx__3__PC
-#define SCSI_Out_DBx_4 SCSI_Out_DBx__4__PC
-#define SCSI_Out_DBx_5 SCSI_Out_DBx__5__PC
-#define SCSI_Out_DBx_6 SCSI_Out_DBx__6__PC
-#define SCSI_Out_DBx_7 SCSI_Out_DBx__7__PC
-
-#define SCSI_Out_DBx_DB0 SCSI_Out_DBx__DB0__PC
-#define SCSI_Out_DBx_DB1 SCSI_Out_DBx__DB1__PC
-#define SCSI_Out_DBx_DB2 SCSI_Out_DBx__DB2__PC
-#define SCSI_Out_DBx_DB3 SCSI_Out_DBx__DB3__PC
-#define SCSI_Out_DBx_DB4 SCSI_Out_DBx__DB4__PC
-#define SCSI_Out_DBx_DB5 SCSI_Out_DBx__DB5__PC
-#define SCSI_Out_DBx_DB6 SCSI_Out_DBx__DB6__PC
-#define SCSI_Out_DBx_DB7 SCSI_Out_DBx__DB7__PC
+#define SCSI_Out_DBx_0 (SCSI_Out_DBx__0__PC)
+#define SCSI_Out_DBx_1 (SCSI_Out_DBx__1__PC)
+#define SCSI_Out_DBx_2 (SCSI_Out_DBx__2__PC)
+#define SCSI_Out_DBx_3 (SCSI_Out_DBx__3__PC)
+#define SCSI_Out_DBx_4 (SCSI_Out_DBx__4__PC)
+#define SCSI_Out_DBx_5 (SCSI_Out_DBx__5__PC)
+#define SCSI_Out_DBx_6 (SCSI_Out_DBx__6__PC)
+#define SCSI_Out_DBx_7 (SCSI_Out_DBx__7__PC)
+
+#define SCSI_Out_DBx_DB0 (SCSI_Out_DBx__DB0__PC)
+#define SCSI_Out_DBx_DB1 (SCSI_Out_DBx__DB1__PC)
+#define SCSI_Out_DBx_DB2 (SCSI_Out_DBx__DB2__PC)
+#define SCSI_Out_DBx_DB3 (SCSI_Out_DBx__DB3__PC)
+#define SCSI_Out_DBx_DB4 (SCSI_Out_DBx__DB4__PC)
+#define SCSI_Out_DBx_DB5 (SCSI_Out_DBx__DB5__PC)
+#define SCSI_Out_DBx_DB6 (SCSI_Out_DBx__DB6__PC)
+#define SCSI_Out_DBx_DB7 (SCSI_Out_DBx__DB7__PC)
#endif /* End Pins SCSI_Out_DBx_ALIASES_H */
/*******************************************************************************
* File Name: SCSI_Out.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define SCSI_Out_0 SCSI_Out__0__PC
-#define SCSI_Out_1 SCSI_Out__1__PC
-#define SCSI_Out_2 SCSI_Out__2__PC
-#define SCSI_Out_3 SCSI_Out__3__PC
-#define SCSI_Out_4 SCSI_Out__4__PC
-#define SCSI_Out_5 SCSI_Out__5__PC
-#define SCSI_Out_6 SCSI_Out__6__PC
-#define SCSI_Out_7 SCSI_Out__7__PC
-#define SCSI_Out_8 SCSI_Out__8__PC
-#define SCSI_Out_9 SCSI_Out__9__PC
-
-#define SCSI_Out_DBP_raw SCSI_Out__DBP_raw__PC
-#define SCSI_Out_ATN SCSI_Out__ATN__PC
-#define SCSI_Out_BSY SCSI_Out__BSY__PC
-#define SCSI_Out_ACK SCSI_Out__ACK__PC
-#define SCSI_Out_RST SCSI_Out__RST__PC
-#define SCSI_Out_MSG SCSI_Out__MSG__PC
-#define SCSI_Out_SEL SCSI_Out__SEL__PC
-#define SCSI_Out_CD SCSI_Out__CD__PC
-#define SCSI_Out_REQ SCSI_Out__REQ__PC
-#define SCSI_Out_IO_raw SCSI_Out__IO_raw__PC
+#define SCSI_Out_0 (SCSI_Out__0__PC)
+#define SCSI_Out_1 (SCSI_Out__1__PC)
+#define SCSI_Out_2 (SCSI_Out__2__PC)
+#define SCSI_Out_3 (SCSI_Out__3__PC)
+#define SCSI_Out_4 (SCSI_Out__4__PC)
+#define SCSI_Out_5 (SCSI_Out__5__PC)
+#define SCSI_Out_6 (SCSI_Out__6__PC)
+#define SCSI_Out_7 (SCSI_Out__7__PC)
+#define SCSI_Out_8 (SCSI_Out__8__PC)
+#define SCSI_Out_9 (SCSI_Out__9__PC)
+
+#define SCSI_Out_DBP_raw (SCSI_Out__DBP_raw__PC)
+#define SCSI_Out_ATN (SCSI_Out__ATN__PC)
+#define SCSI_Out_BSY (SCSI_Out__BSY__PC)
+#define SCSI_Out_ACK (SCSI_Out__ACK__PC)
+#define SCSI_Out_RST (SCSI_Out__RST__PC)
+#define SCSI_Out_MSG (SCSI_Out__MSG__PC)
+#define SCSI_Out_SEL (SCSI_Out__SEL__PC)
+#define SCSI_Out_CD (SCSI_Out__CD__PC)
+#define SCSI_Out_REQ (SCSI_Out__REQ__PC)
+#define SCSI_Out_IO_raw (SCSI_Out__IO_raw__PC)
#endif /* End Pins SCSI_Out_ALIASES_H */
/*******************************************************************************
* File Name: SD_PULLUP.c
-* Version 1.90
+* Version 2.10
*
* Description:
* This file contains API to enable firmware control of a Pins component.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Change the drive mode on the pins of the port.
*
* Parameters:
-* mode: Change the pins to this drive mode.
+* mode: Change the pins to one of the following drive modes.
+*
+* SD_PULLUP_DM_STRONG Strong Drive
+* SD_PULLUP_DM_OD_HI Open Drain, Drives High
+* SD_PULLUP_DM_OD_LO Open Drain, Drives Low
+* SD_PULLUP_DM_RES_UP Resistive Pull Up
+* SD_PULLUP_DM_RES_DWN Resistive Pull Down
+* SD_PULLUP_DM_RES_UPDWN Resistive Pull Up/Down
+* SD_PULLUP_DM_DIG_HIZ High Impedance Digital
+* SD_PULLUP_DM_ALG_HIZ High Impedance Analog
*
* Return:
* None
/*******************************************************************************
* File Name: SD_PULLUP.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
/*******************************************************************************
* File Name: SD_PULLUP.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define SD_PULLUP_0 SD_PULLUP__0__PC
-#define SD_PULLUP_1 SD_PULLUP__1__PC
-#define SD_PULLUP_2 SD_PULLUP__2__PC
-#define SD_PULLUP_3 SD_PULLUP__3__PC
-#define SD_PULLUP_4 SD_PULLUP__4__PC
+#define SD_PULLUP_0 (SD_PULLUP__0__PC)
+#define SD_PULLUP_1 (SD_PULLUP__1__PC)
+#define SD_PULLUP_2 (SD_PULLUP__2__PC)
+#define SD_PULLUP_3 (SD_PULLUP__3__PC)
+#define SD_PULLUP_4 (SD_PULLUP__4__PC)
#endif /* End Pins SD_PULLUP_ALIASES_H */
/*******************************************************************************
* File Name: USBFS.c
-* Version 2.60
+* Version 2.80
*
* Description:
* API for USBFS Component.
* registers are indexed by variations of epNumber - 1.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "USBFS_hid.h"
#if(USBFS_DMA1_REMOVE == 0u)
#include "USBFS_ep1_dma.h"
-#endif /* End USBFS_DMA1_REMOVE */
+#endif /* USBFS_DMA1_REMOVE */
#if(USBFS_DMA2_REMOVE == 0u)
#include "USBFS_ep2_dma.h"
-#endif /* End USBFS_DMA2_REMOVE */
+#endif /* USBFS_DMA2_REMOVE */
#if(USBFS_DMA3_REMOVE == 0u)
#include "USBFS_ep3_dma.h"
-#endif /* End USBFS_DMA3_REMOVE */
+#endif /* USBFS_DMA3_REMOVE */
#if(USBFS_DMA4_REMOVE == 0u)
#include "USBFS_ep4_dma.h"
-#endif /* End USBFS_DMA4_REMOVE */
+#endif /* USBFS_DMA4_REMOVE */
#if(USBFS_DMA5_REMOVE == 0u)
#include "USBFS_ep5_dma.h"
-#endif /* End USBFS_DMA5_REMOVE */
+#endif /* USBFS_DMA5_REMOVE */
#if(USBFS_DMA6_REMOVE == 0u)
#include "USBFS_ep6_dma.h"
-#endif /* End USBFS_DMA6_REMOVE */
+#endif /* USBFS_DMA6_REMOVE */
#if(USBFS_DMA7_REMOVE == 0u)
#include "USBFS_ep7_dma.h"
-#endif /* End USBFS_DMA7_REMOVE */
+#endif /* USBFS_DMA7_REMOVE */
#if(USBFS_DMA8_REMOVE == 0u)
#include "USBFS_ep8_dma.h"
-#endif /* End USBFS_DMA8_REMOVE */
+#endif /* USBFS_DMA8_REMOVE */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ #include "USBFS_EP_DMA_Done_isr.h"
+ #include "USBFS_EP8_DMA_Done_SR.h"
+ #include "USBFS_EP17_DMA_Done_SR.h"
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
/***************************************
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
uint8 USBFS_DmaChan[USBFS_MAX_EP];
uint8 USBFS_DmaTd[USBFS_MAX_EP];
-#endif /* End USBFS_EP_MM */
+#endif /* USBFS_EP_MM */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ static uint8 clearInDataRdyStatus = USBFS_ARB_EPX_CFG_DEFAULT;
+ uint8 USBFS_DmaNextTd[USBFS_MAX_EP];
+ const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP] =
+ { 0u,
+ USBFS_ep1_TD_TERMOUT_EN,
+ USBFS_ep2_TD_TERMOUT_EN,
+ USBFS_ep3_TD_TERMOUT_EN,
+ USBFS_ep4_TD_TERMOUT_EN,
+ USBFS_ep5_TD_TERMOUT_EN,
+ USBFS_ep6_TD_TERMOUT_EN,
+ USBFS_ep7_TD_TERMOUT_EN,
+ USBFS_ep8_TD_TERMOUT_EN
+ };
+ volatile uint16 USBFS_inLength[USBFS_MAX_EP];
+ const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];
+ volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
/*******************************************************************************
uint8 enableInterrupts;
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
uint16 i;
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
enableInterrupts = CyEnterCriticalSection();
for (i = 0u; i < USBFS_MAX_EP; i++)
{
USBFS_DmaTd[i] = DMA_INVALID_TD;
+ #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ USBFS_DmaNextTd[i] = DMA_INVALID_TD;
+ #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
}
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
CyExitCriticalSection(enableInterrupts);
#if(USBFS_SOF_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBFS_SOF_VECT_NUM, &USBFS_SOF_ISR);
CyIntSetPriority(USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR);
- #endif /* End USBFS_SOF_ISR_REMOVE */
+ #endif /* USBFS_SOF_ISR_REMOVE */
/* Set the Control Endpoint Interrupt. */
(void) CyIntSetVector(USBFS_EP_0_VECT_NUM, &USBFS_EP_0_ISR);
#if(USBFS_EP1_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBFS_EP_1_VECT_NUM, &USBFS_EP_1_ISR);
CyIntSetPriority(USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR);
- #endif /* End USBFS_EP1_ISR_REMOVE */
+ #endif /* USBFS_EP1_ISR_REMOVE */
/* Set the Data Endpoint 2 Interrupt. */
#if(USBFS_EP2_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBFS_EP_2_VECT_NUM, &USBFS_EP_2_ISR);
CyIntSetPriority(USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR);
- #endif /* End USBFS_EP2_ISR_REMOVE */
+ #endif /* USBFS_EP2_ISR_REMOVE */
/* Set the Data Endpoint 3 Interrupt. */
#if(USBFS_EP3_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBFS_EP_3_VECT_NUM, &USBFS_EP_3_ISR);
CyIntSetPriority(USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR);
- #endif /* End USBFS_EP3_ISR_REMOVE */
+ #endif /* USBFS_EP3_ISR_REMOVE */
/* Set the Data Endpoint 4 Interrupt. */
#if(USBFS_EP4_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBFS_EP_4_VECT_NUM, &USBFS_EP_4_ISR);
CyIntSetPriority(USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR);
- #endif /* End USBFS_EP4_ISR_REMOVE */
+ #endif /* USBFS_EP4_ISR_REMOVE */
/* Set the Data Endpoint 5 Interrupt. */
#if(USBFS_EP5_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBFS_EP_5_VECT_NUM, &USBFS_EP_5_ISR);
CyIntSetPriority(USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR);
- #endif /* End USBFS_EP5_ISR_REMOVE */
+ #endif /* USBFS_EP5_ISR_REMOVE */
/* Set the Data Endpoint 6 Interrupt. */
#if(USBFS_EP6_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBFS_EP_6_VECT_NUM, &USBFS_EP_6_ISR);
CyIntSetPriority(USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR);
- #endif /* End USBFS_EP6_ISR_REMOVE */
+ #endif /* USBFS_EP6_ISR_REMOVE */
/* Set the Data Endpoint 7 Interrupt. */
#if(USBFS_EP7_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBFS_EP_7_VECT_NUM, &USBFS_EP_7_ISR);
CyIntSetPriority(USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR);
- #endif /* End USBFS_EP7_ISR_REMOVE */
+ #endif /* USBFS_EP7_ISR_REMOVE */
/* Set the Data Endpoint 8 Interrupt. */
#if(USBFS_EP8_ISR_REMOVE == 0u)
(void) CyIntSetVector(USBFS_EP_8_VECT_NUM, &USBFS_EP_8_ISR);
CyIntSetPriority(USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR);
- #endif /* End USBFS_EP8_ISR_REMOVE */
+ #endif /* USBFS_EP8_ISR_REMOVE */
#if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))
/* Set the ARB Interrupt. */
(void) CyIntSetVector(USBFS_ARB_VECT_NUM, &USBFS_ARB_ISR);
CyIntSetPriority(USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR);
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
}
CyIntEnable(USBFS_EP_0_VECT_NUM);
#if(USBFS_EP1_ISR_REMOVE == 0u)
CyIntEnable(USBFS_EP_1_VECT_NUM);
- #endif /* End USBFS_EP1_ISR_REMOVE */
+ #endif /* USBFS_EP1_ISR_REMOVE */
#if(USBFS_EP2_ISR_REMOVE == 0u)
CyIntEnable(USBFS_EP_2_VECT_NUM);
- #endif /* End USBFS_EP2_ISR_REMOVE */
+ #endif /* USBFS_EP2_ISR_REMOVE */
#if(USBFS_EP3_ISR_REMOVE == 0u)
CyIntEnable(USBFS_EP_3_VECT_NUM);
- #endif /* End USBFS_EP3_ISR_REMOVE */
+ #endif /* USBFS_EP3_ISR_REMOVE */
#if(USBFS_EP4_ISR_REMOVE == 0u)
CyIntEnable(USBFS_EP_4_VECT_NUM);
- #endif /* End USBFS_EP4_ISR_REMOVE */
+ #endif /* USBFS_EP4_ISR_REMOVE */
#if(USBFS_EP5_ISR_REMOVE == 0u)
CyIntEnable(USBFS_EP_5_VECT_NUM);
- #endif /* End USBFS_EP5_ISR_REMOVE */
+ #endif /* USBFS_EP5_ISR_REMOVE */
#if(USBFS_EP6_ISR_REMOVE == 0u)
CyIntEnable(USBFS_EP_6_VECT_NUM);
- #endif /* End USBFS_EP6_ISR_REMOVE */
+ #endif /* USBFS_EP6_ISR_REMOVE */
#if(USBFS_EP7_ISR_REMOVE == 0u)
CyIntEnable(USBFS_EP_7_VECT_NUM);
- #endif /* End USBFS_EP7_ISR_REMOVE */
+ #endif /* USBFS_EP7_ISR_REMOVE */
#if(USBFS_EP8_ISR_REMOVE == 0u)
CyIntEnable(USBFS_EP_8_VECT_NUM);
- #endif /* End USBFS_EP8_ISR_REMOVE */
+ #endif /* USBFS_EP8_ISR_REMOVE */
#if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u))
/* usb arb interrupt enable */
USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;
CyIntEnable(USBFS_ARB_VECT_NUM);
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
/* Arbiter configuration for DMA transfers */
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
-
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
/*Set cfg cmplt this rises DMA request when the full configuration is done */
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+ #if(USBFS_EP_DMA_AUTO_OPT == 0u)
+ /* Init interrupt which handles verification of the successful DMA transaction */
+ USBFS_EP_DMA_Done_isr_StartEx(&USBFS_EP_DMA_DONE_ISR);
+ USBFS_EP17_DMA_Done_SR_InterruptEnable();
+ USBFS_EP8_DMA_Done_SR_InterruptEnable();
+ #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
USBFS_transferState = USBFS_TRANS_STATE_IDLE;
USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK;
#else
USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE;
- #endif /* End USBFS_VDDD_MV < USBFS_3500MV */
+ #endif /* USBFS_VDDD_MV < USBFS_3500MV */
break;
}
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
/* Disable the SIE */
USBFS_CR0_REG &= (uint8)(~USBFS_CR0_ENABLE);
CyIntDisable(USBFS_EP_0_VECT_NUM);
#if(USBFS_EP1_ISR_REMOVE == 0u)
CyIntDisable(USBFS_EP_1_VECT_NUM);
- #endif /* End USBFS_EP1_ISR_REMOVE */
+ #endif /* USBFS_EP1_ISR_REMOVE */
#if(USBFS_EP2_ISR_REMOVE == 0u)
CyIntDisable(USBFS_EP_2_VECT_NUM);
- #endif /* End USBFS_EP2_ISR_REMOVE */
+ #endif /* USBFS_EP2_ISR_REMOVE */
#if(USBFS_EP3_ISR_REMOVE == 0u)
CyIntDisable(USBFS_EP_3_VECT_NUM);
- #endif /* End USBFS_EP3_ISR_REMOVE */
+ #endif /* USBFS_EP3_ISR_REMOVE */
#if(USBFS_EP4_ISR_REMOVE == 0u)
CyIntDisable(USBFS_EP_4_VECT_NUM);
- #endif /* End USBFS_EP4_ISR_REMOVE */
+ #endif /* USBFS_EP4_ISR_REMOVE */
#if(USBFS_EP5_ISR_REMOVE == 0u)
CyIntDisable(USBFS_EP_5_VECT_NUM);
- #endif /* End USBFS_EP5_ISR_REMOVE */
+ #endif /* USBFS_EP5_ISR_REMOVE */
#if(USBFS_EP6_ISR_REMOVE == 0u)
CyIntDisable(USBFS_EP_6_VECT_NUM);
- #endif /* End USBFS_EP6_ISR_REMOVE */
+ #endif /* USBFS_EP6_ISR_REMOVE */
#if(USBFS_EP7_ISR_REMOVE == 0u)
CyIntDisable(USBFS_EP_7_VECT_NUM);
- #endif /* End USBFS_EP7_ISR_REMOVE */
+ #endif /* USBFS_EP7_ISR_REMOVE */
#if(USBFS_EP8_ISR_REMOVE == 0u)
CyIntDisable(USBFS_EP_8_VECT_NUM);
- #endif /* End USBFS_EP8_ISR_REMOVE */
+ #endif /* USBFS_EP8_ISR_REMOVE */
/* Clear all of the component data */
USBFS_configuration = 0u;
* No.
*
*******************************************************************************/
- void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData)
+ void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)
{
uint16 src;
src = HI16(CYDEV_PERIPH_BASE);
dst = HI16(pData);
}
- #endif /* End C51 */
+ #endif /* C51 */
switch(epNumber)
{
case USBFS_EP1:
#if(USBFS_DMA1_REMOVE == 0u)
USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize(
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
- #endif /* End USBFS_DMA1_REMOVE */
+ #endif /* USBFS_DMA1_REMOVE */
break;
case USBFS_EP2:
#if(USBFS_DMA2_REMOVE == 0u)
USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize(
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
- #endif /* End USBFS_DMA2_REMOVE */
+ #endif /* USBFS_DMA2_REMOVE */
break;
case USBFS_EP3:
#if(USBFS_DMA3_REMOVE == 0u)
USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize(
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
- #endif /* End USBFS_DMA3_REMOVE */
+ #endif /* USBFS_DMA3_REMOVE */
break;
case USBFS_EP4:
#if(USBFS_DMA4_REMOVE == 0u)
USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize(
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
- #endif /* End USBFS_DMA4_REMOVE */
+ #endif /* USBFS_DMA4_REMOVE */
break;
case USBFS_EP5:
#if(USBFS_DMA5_REMOVE == 0u)
USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize(
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
- #endif /* End USBFS_DMA5_REMOVE */
+ #endif /* USBFS_DMA5_REMOVE */
break;
case USBFS_EP6:
#if(USBFS_DMA6_REMOVE == 0u)
USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize(
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
- #endif /* End USBFS_DMA6_REMOVE */
+ #endif /* USBFS_DMA6_REMOVE */
break;
case USBFS_EP7:
#if(USBFS_DMA7_REMOVE == 0u)
USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize(
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
- #endif /* End USBFS_DMA7_REMOVE */
+ #endif /* USBFS_DMA7_REMOVE */
break;
case USBFS_EP8:
#if(USBFS_DMA8_REMOVE == 0u)
USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize(
USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst);
- #endif /* End USBFS_DMA8_REMOVE */
+ #endif /* USBFS_DMA8_REMOVE */
break;
default:
/* Do not support EP0 DMA transfers */
if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
{
USBFS_DmaTd[epNumber] = CyDmaTdAllocate();
+ #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ USBFS_DmaNextTd[epNumber] = CyDmaTdAllocate();
+ #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
+
}
}
CyDmaTdFree(USBFS_DmaTd[i]);
USBFS_DmaTd[i] = DMA_INVALID_TD;
}
+ #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ if(USBFS_DmaNextTd[i] != DMA_INVALID_TD)
+ {
+ CyDmaTdFree(USBFS_DmaNextTd[i]);
+ USBFS_DmaNextTd[i] = DMA_INVALID_TD;
+ }
+ #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
i++;
}while((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP));
}
-#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+#endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
+
+
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+
+
+ /*******************************************************************************
+ * Function Name: USBFS_LoadNextInEP
+ ********************************************************************************
+ *
+ * Summary:
+ * This internal function is used for IN endpoint DMA reconfiguration in
+ * Auto DMA mode.
+ *
+ * Parameters:
+ * epNumber: Contains the data endpoint number.
+ * mode: 0 - Configure DMA to send the the rest of data.
+ * 1 - Configure DMA to repeat 2 last bytes of the first burst.
+ *
+ * Return:
+ * None.
+ *
+ *******************************************************************************/
+ void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode)
+ {
+ reg16 *convert;
+
+ if(mode == 0u)
+ {
+ /* Configure DMA to send the the rest of data */
+ /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];
+ /* Set transfer length */
+ CY_SET_REG16(convert, USBFS_inLength[epNumber] - USBFS_DMA_BYTES_PER_BURST);
+ /* CyDmaTdSetAddress API is optimized to change only source address */
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];
+ CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] +
+ USBFS_DMA_BYTES_PER_BURST));
+ USBFS_inBufFull[epNumber] = 1u;
+ }
+ else
+ {
+ /* Configure DMA to repeat 2 last bytes of the first burst. */
+ /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u];
+ /* Set transfer length */
+ CY_SET_REG16(convert, USBFS_DMA_BYTES_REPEAT);
+ /* CyDmaTdSetAddress API is optimized to change only source address */
+ convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u];
+ CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] +
+ USBFS_DMA_BYTES_PER_BURST - USBFS_DMA_BYTES_REPEAT));
+ }
+
+ /* CyDmaChSetInitialTd API is optimised to init TD */
+ CY_DMA_CH_STRUCT_PTR[USBFS_DmaChan[epNumber]].basic_status[1u] = USBFS_DmaTd[epNumber];
+ }
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
/*******************************************************************************
********************************************************************************
*
* Summary:
-* Loads and enables the specified USB data endpoint for an IN interrupt or bulk
-* transfer.
+* Loads and enables the specified USB data endpoint for an IN transfer.
*
* Parameters:
* epNumber: Contains the data endpoint number.
reg8 *p;
#if(USBFS_EP_MM == USBFS__EP_MANUAL)
uint16 i;
- #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */
if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP))
{
{
length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset;
}
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */
/* Set the count and data toggle */
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri),
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
#else
/* Init DMA if it was not initialized */
- if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD)
+ if (USBFS_DmaTd[epNumber] == DMA_INVALID_TD)
{
USBFS_InitEP_DMA(epNumber, pData);
}
- #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
- if((pData != NULL) && (length > 0u))
+ if ((pData != NULL) && (length > 0u))
{
/* Enable DMA in mode2 for transferring data */
(void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
/* When zero-length packet - write the Mode register directly */
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
}
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
- if(pData != NULL)
+ if (pData != NULL)
{
/* Enable DMA in mode3 for transferring data */
(void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)
+ USBFS_inLength[epNumber] = length;
+ USBFS_inDataPointer[epNumber] = pData;
+ /* Configure DMA to send the data only for the first burst */
+ (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber],
+ (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length,
+ USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));
+ /* The second TD will be executed only when the first one fails.
+ * The intention of this TD is to generate NRQ interrupt
+ * and repeat 2 last bytes of the first burst.
+ */
+ (void) CyDmaTdSetConfiguration(USBFS_DmaNextTd[epNumber], 1u,
+ USBFS_DmaNextTd[epNumber],
+ USBFS_epX_TD_TERMOUT_EN[epNumber]);
+ /* Configure DmaNextTd to clear Data ready status */
+ (void) CyDmaTdSetAddress(USBFS_DmaNextTd[epNumber], LO16((uint32)&clearInDataRdyStatus),
+ LO16((uint32)(USBFS_ARB_EP1_CFG_IND + ri)));
+ #else /* Configure DMA to send all data*/
(void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length,
USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR);
(void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p));
+ #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */
+
/* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
(void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);
/* Enable the DMA */
USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING;
if(length > 0u)
{
+ #if (USBFS_EP_DMA_AUTO_OPT == 0u)
+ USBFS_inLength[epNumber] = length;
+ USBFS_inBufFull[epNumber] = 0u;
+ (void) CyDmaChDisable(USBFS_DmaChan[epNumber]);
+ /* Configure DMA to send the data only for the first burst */
+ (void) CyDmaTdSetConfiguration(
+ USBFS_DmaTd[epNumber], (length > USBFS_DMA_BYTES_PER_BURST) ?
+ USBFS_DMA_BYTES_PER_BURST : length,
+ USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR );
+ (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber],
+ LO16((uint32)USBFS_inDataPointer[epNumber]), LO16((uint32)p));
+ /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */
+ (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]);
+ /* Enable the DMA */
+ (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
+ (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
+ #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */
+
/* Set Data ready status, This will generate DMA request */
- * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+ #ifndef USBFS_MANUAL_IN_EP_ARM
+ * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+ #endif /* USBFS_MANUAL_IN_EP_ARM */
/* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */
}
else
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode);
}
}
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
-
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
}
}
reg8 *p;
#if(USBFS_EP_MM == USBFS__EP_MANUAL)
uint16 i;
- #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */
#if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
uint16 xferCount;
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */
if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL))
{
{
length = xferCount;
}
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */
#if(USBFS_EP_MM == USBFS__EP_MANUAL)
/* Copy the data using the arbiter data register */
{
USBFS_InitEP_DMA(epNumber, pData);
}
- #endif /* End USBFS_EP_MM == USBFS__EP_MANUAL */
+
+ #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
/* Enable DMA in mode2 for transferring data */
* (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ;
* (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ));
/* Out EP will be (re)armed in arb ISR after transfer complete */
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
/* Enable DMA in mode3 for transferring data */
(void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]);
(void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u);
/* Out EP will be (re)armed in arb ISR after transfer complete */
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
}
else
/*******************************************************************************
* File Name: USBFS.h
-* Version 2.60
+* Version 2.80
*
* Description:
-* Header File for the USFS component. Contains prototypes and constant values.
+* Header File for the USBFS component. Contains prototypes and constant values.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "cyfitter.h"
#include "CyLib.h"
+/* User supplied definitions. */
+/* `#START USER_DEFINITIONS` Place your declaration here */
+
+/* `#END` */
+
/***************************************
* Conditional Compilation Parameters
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
- #error Component USBFS_v2_60 requires cy_boot v3.0 or later
+ #error Component USBFS_v2_80 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5LP) */
#else
#define USBFS_DATA
#define USBFS_XDATA
-#endif /* End __C51__ */
+#endif /* __C51__ */
#define USBFS_NULL NULL
#define USBFS_EP8_ISR_REMOVE (1u)
#define USBFS_EP_MM (0u)
#define USBFS_EP_MA (0u)
+#define USBFS_EP_DMA_AUTO_OPT (0u)
#define USBFS_DMA1_REMOVE (1u)
#define USBFS_DMA2_REMOVE (1u)
#define USBFS_DMA3_REMOVE (1u)
#endif /* USBFS_ENABLE_FWSN_STRING */
#if (USBFS_MON_VBUS == 1u)
uint8 USBFS_VBusPresent(void) ;
-#endif /* End USBFS_MON_VBUS */
+#endif /* USBFS_MON_VBUS */
#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \
(CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))
void USBFS_CyBtldrCommStart(void) ;
void USBFS_CyBtldrCommStop(void) ;
void USBFS_CyBtldrCommReset(void) ;
- cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+ cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
;
- cystatus USBFS_CyBtldrCommRead( uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+ cystatus USBFS_CyBtldrCommRead (uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
;
- #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* EP 1 OUT */
- #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* EP 2 IN */
- #define USBFS_BTLDR_MAX_PACKET_SIZE USBFS_BTLDR_SIZEOF_WRITE_BUFFER
+ #define USBFS_BTLDR_OUT_EP (0x01u)
+ #define USBFS_BTLDR_IN_EP (0x02u)
+
+ #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* EP 1 OUT */
+ #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* EP 2 IN */
+ #define USBFS_BTLDR_MAX_PACKET_SIZE USBFS_BTLDR_SIZEOF_WRITE_BUFFER
+
+ #define USBFS_BTLDR_WAIT_1_MS (1u) /* Time Out quantity equal 1mS */
/* These defines active if used USBFS interface as an
* IO Component for bootloading. When Custom_Interface selected
* in Bootloder configuration as the IO Component, user must
- * provide these functions
+ * provide these functions.
*/
#if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS)
#define CyBtldrCommStart USBFS_CyBtldrCommStart
#define CyBtldrCommRead USBFS_CyBtldrCommRead
#endif /*End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
-#endif /* End CYDEV_BOOTLOADER_IO_COMP */
+#endif /* CYDEV_BOOTLOADER_IO_COMP */
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
- void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData)
+ void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData)
;
void USBFS_Stop_DMA(uint8 epNumber) ;
-#endif /* End USBFS_EP_MM != USBFS__EP_MANUAL) */
+#endif /* USBFS_EP_MM != USBFS__EP_MANUAL) */
#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)
void USBFS_MIDI_EP_Init(void) ;
void USBFS_MIDI_OUT_EP_Service(void) ;
#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
-#endif /* End USBFS_ENABLE_MIDI_API != 0u */
+#endif /* USBFS_ENABLE_MIDI_API != 0u */
/* Renamed Functions for backward compatibility.
* Should not be used in new designs.
#define USBFS_EP_USAGE_TYPE_RESERVED (0x30u)
#define USBFS_EP_USAGE_TYPE_MASK (0x30u)
-/* Endpoint Status defines */
+/* point Status defines */
#define USBFS_EP_STATUS_LENGTH (0x02u)
-/* Endpoint Device defines */
+/* point Device defines */
#define USBFS_DEVICE_STATUS_LENGTH (0x02u)
#define USBFS_STATUS_LENGTH_MAX \
/* DMA manual mode defines */
#define USBFS_DMA_BYTES_PER_BURST (0u)
#define USBFS_DMA_REQUEST_PER_BURST (0u)
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+#endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
/* DMA automatic mode defines */
#define USBFS_DMA_BYTES_PER_BURST (32u)
+ #define USBFS_DMA_BYTES_REPEAT (2u)
/* BUF_SIZE-BYTES_PER_BURST examples: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */
#define USBFS_DMA_BUF_SIZE (0x55u)
#define USBFS_DMA_REQUEST_PER_BURST (1u)
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+
+ #if(USBFS_DMA1_REMOVE == 0u)
+ #define USBFS_ep1_TD_TERMOUT_EN USBFS_ep1__TD_TERMOUT_EN
+ #else
+ #define USBFS_ep1_TD_TERMOUT_EN (0u)
+ #endif /* USBFS_DMA1_REMOVE == 0u */
+ #if(USBFS_DMA2_REMOVE == 0u)
+ #define USBFS_ep2_TD_TERMOUT_EN USBFS_ep2__TD_TERMOUT_EN
+ #else
+ #define USBFS_ep2_TD_TERMOUT_EN (0u)
+ #endif /* USBFS_DMA2_REMOVE == 0u */
+ #if(USBFS_DMA3_REMOVE == 0u)
+ #define USBFS_ep3_TD_TERMOUT_EN USBFS_ep3__TD_TERMOUT_EN
+ #else
+ #define USBFS_ep3_TD_TERMOUT_EN (0u)
+ #endif /* USBFS_DMA3_REMOVE == 0u */
+ #if(USBFS_DMA4_REMOVE == 0u)
+ #define USBFS_ep4_TD_TERMOUT_EN USBFS_ep4__TD_TERMOUT_EN
+ #else
+ #define USBFS_ep4_TD_TERMOUT_EN (0u)
+ #endif /* USBFS_DMA4_REMOVE == 0u */
+ #if(USBFS_DMA5_REMOVE == 0u)
+ #define USBFS_ep5_TD_TERMOUT_EN USBFS_ep5__TD_TERMOUT_EN
+ #else
+ #define USBFS_ep5_TD_TERMOUT_EN (0u)
+ #endif /* USBFS_DMA5_REMOVE == 0u */
+ #if(USBFS_DMA6_REMOVE == 0u)
+ #define USBFS_ep6_TD_TERMOUT_EN USBFS_ep6__TD_TERMOUT_EN
+ #else
+ #define USBFS_ep6_TD_TERMOUT_EN (0u)
+ #endif /* USBFS_DMA6_REMOVE == 0u */
+ #if(USBFS_DMA7_REMOVE == 0u)
+ #define USBFS_ep7_TD_TERMOUT_EN USBFS_ep7__TD_TERMOUT_EN
+ #else
+ #define USBFS_ep7_TD_TERMOUT_EN (0u)
+ #endif /* USBFS_DMA7_REMOVE == 0u */
+ #if(USBFS_DMA8_REMOVE == 0u)
+ #define USBFS_ep8_TD_TERMOUT_EN USBFS_ep8__TD_TERMOUT_EN
+ #else
+ #define USBFS_ep8_TD_TERMOUT_EN (0u)
+ #endif /* USBFS_DMA8_REMOVE == 0u */
+
+ #define USBFS_EP17_SR_MASK (0x7fu)
+ #define USBFS_EP8_SR_MASK (0x03u)
+
+#endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
/* DIE ID string descriptor defines */
#if defined(USBFS_ENABLE_IDSN_STRING)
#if(!CY_PSOC5LP)
#define USBFS_USBIO_CR2_PTR ( (reg8 *) USBFS_USB__USBIO_CR2)
#define USBFS_USBIO_CR2_REG (* (reg8 *) USBFS_USB__USBIO_CR2)
-#endif /* End CY_PSOC5LP */
+#endif /* CY_PSOC5LP */
#define USBFS_DIE_ID CYDEV_FLSHID_CUST_TABLES_BASE
#else
#define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG )
#define USBFS_VBUS_MASK (0x01u)
- #endif /* End USBFS_EXTERN_VBUS == 0u */
-#endif /* End USBFS_MON_VBUS */
+ #endif /* USBFS_EXTERN_VBUS == 0u */
+#endif /* USBFS_MON_VBUS */
/* Renamed Registers for backward compatibility.
* Should not be used in new designs.
#define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0)
#define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0)
#define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET)
-#endif /* End CYDEV_CHIP_DIE_EXPECT */
+#endif /* CYDEV_CHIP_DIE_EXPECT */
/***************************************
#define USBFS_ARB_EPX_CFG_CRC_BYPASS (0x04u)
#define USBFS_ARB_EPX_CFG_DMA_REQ (0x02u)
#define USBFS_ARB_EPX_CFG_IN_DATA_RDY (0x01u)
+#define USBFS_ARB_EPX_CFG_DEFAULT (USBFS_ARB_EPX_CFG_RESET | \
+ USBFS_ARB_EPX_CFG_CRC_BYPASS)
#define USBFS_ARB_EPX_SR_IN_BUF_FULL (0x01u)
#define USBFS_ARB_EPX_SR_DMA_GNT (0x02u)
#define USBFS_ARB_EPX_INT_MASK (0x1Du)
#else
#define USBFS_ARB_EPX_INT_MASK (0x1Fu)
-#endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+#endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
#define USBFS_ARB_INT_MASK (uint8)((USBFS_DMA1_REMOVE ^ 1u) | \
(uint8)((USBFS_DMA2_REMOVE ^ 1u) << 1u) | \
(uint8)((USBFS_DMA3_REMOVE ^ 1u) << 2u) | \
#define USBFS_DYN_RECONFIG_RDY_STS (0x10u)
-#endif /* End CY_USBFS_USBFS_H */
+#endif /* CY_USBFS_USBFS_H */
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_Dm.c
-* Version 1.90
+* Version 2.10
*
* Description:
* This file contains API to enable firmware control of a Pins component.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Change the drive mode on the pins of the port.
*
* Parameters:
-* mode: Change the pins to this drive mode.
+* mode: Change the pins to one of the following drive modes.
+*
+* USBFS_Dm_DM_STRONG Strong Drive
+* USBFS_Dm_DM_OD_HI Open Drain, Drives High
+* USBFS_Dm_DM_OD_LO Open Drain, Drives Low
+* USBFS_Dm_DM_RES_UP Resistive Pull Up
+* USBFS_Dm_DM_RES_DWN Resistive Pull Down
+* USBFS_Dm_DM_RES_UPDWN Resistive Pull Up/Down
+* USBFS_Dm_DM_DIG_HIZ High Impedance Digital
+* USBFS_Dm_DM_ALG_HIZ High Impedance Analog
*
* Return:
* None
/*******************************************************************************
* File Name: USBFS_Dm.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
/*******************************************************************************
* File Name: USBFS_Dm.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define USBFS_Dm_0 USBFS_Dm__0__PC
+#define USBFS_Dm_0 (USBFS_Dm__0__PC)
#endif /* End Pins USBFS_Dm_ALIASES_H */
/*******************************************************************************
* File Name: USBFS_Dp.c
-* Version 1.90
+* Version 2.10
*
* Description:
* This file contains API to enable firmware control of a Pins component.
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Change the drive mode on the pins of the port.
*
* Parameters:
-* mode: Change the pins to this drive mode.
+* mode: Change the pins to one of the following drive modes.
+*
+* USBFS_Dp_DM_STRONG Strong Drive
+* USBFS_Dp_DM_OD_HI Open Drain, Drives High
+* USBFS_Dp_DM_OD_LO Open Drain, Drives Low
+* USBFS_Dp_DM_RES_UP Resistive Pull Up
+* USBFS_Dp_DM_RES_DWN Resistive Pull Down
+* USBFS_Dp_DM_RES_UPDWN Resistive Pull Up/Down
+* USBFS_Dp_DM_DIG_HIZ High Impedance Digital
+* USBFS_Dp_DM_ALG_HIZ High Impedance Analog
*
* Return:
* None
/*******************************************************************************
* File Name: USBFS_Dp.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
- #error Component cy_pins_v1_90 requires cy_boot v3.0 or later
+ #error Component cy_pins_v2_10 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
/*******************************************************************************
* File Name: USBFS_Dp.h
-* Version 1.90
+* Version 2.10
*
* Description:
* This file containts Control Register function prototypes and register defines
* Note:
*
********************************************************************************
-* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
* Constants
***************************************/
-#define USBFS_Dp_0 USBFS_Dp__0__PC
+#define USBFS_Dp_0 (USBFS_Dp__0__PC)
#endif /* End Pins USBFS_Dp_ALIASES_H */
/*******************************************************************************
* File Name: USBFS_audio.c
-* Version 2.60
+* Version 2.80
*
* Description:
* USB AUDIO Class request handler.
*
-* Note:
+* Related Document:
+* Universal Serial Bus Device Class Definition for Audio Devices Release 1.0
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "USBFS_audio.h"
#include "USBFS_pvt.h"
-#if defined(USBFS_ENABLE_MIDI_STREAMING)
+#if defined(USBFS_ENABLE_MIDI_STREAMING)
#include "USBFS_midi.h"
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+#endif /* USBFS_ENABLE_MIDI_STREAMING*/
/***************************************
USBFS_VOL_MAX_MSB};
volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_RES_LSB,
USBFS_VOL_RES_MSB};
-#endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+#endif /* USBFS_ENABLE_AUDIO_STREAMING */
/*******************************************************************************
uint8 USBFS_DispatchAUDIOClassRqst(void)
{
uint8 requestHandled = USBFS_FALSE;
+ uint8 bmRequestType = CY_GET_REG8(USBFS_bmRequestType);
#if defined(USBFS_ENABLE_AUDIO_STREAMING)
uint8 epNumber;
epNumber = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED;
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */
- if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)
+
+ if ((bmRequestType & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H)
{
/* Control Read */
- if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
- USBFS_RQST_RCPT_EP)
+ if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)
{
/* Endpoint */
switch (CY_GET_REG8(USBFS_bRequest))
#if defined(USBFS_ENABLE_AUDIO_STREAMING)
if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)
{
- /* Endpoint Control Selector is Sampling Frequency */
+ /* point Control Selector is Sampling Frequency */
USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;
USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber];
requestHandled = USBFS_InitControlRead();
}
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */
/* `#START AUDIO_READ_REQUESTS` Place other request handler here */
break;
}
}
- else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
- USBFS_RQST_RCPT_IFC)
+ else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)
{
/* Interface or Entity ID */
switch (CY_GET_REG8(USBFS_bRequest))
/* `#START MUTE_CONTROL_GET_REQUEST` Place multi-channel handler here */
/* `#END` */
-
+
/* Entity ID Control Selector is MUTE */
USBFS_currentTD.wCount = 1u;
USBFS_currentTD.pData = &USBFS_currentMute;
USBFS_currentTD.wCount = 0u;
requestHandled = USBFS_InitControlWrite();
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */
/* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */
{ /* USBFS_RQST_RCPT_OTHER */
}
}
- else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == \
- USBFS_RQST_DIR_H2D)
+ else
{
/* Control Write */
- if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
- USBFS_RQST_RCPT_EP)
+ if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP)
{
- /* Endpoint */
+ /* point */
switch (CY_GET_REG8(USBFS_bRequest))
{
case USBFS_SET_CUR:
#if defined(USBFS_ENABLE_AUDIO_STREAMING)
if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL)
{
- /* Endpoint Control Selector is Sampling Frequency */
+ /* point Control Selector is Sampling Frequency */
USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN;
USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber];
requestHandled = USBFS_InitControlWrite();
USBFS_frequencyChanged = epNumber;
}
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */
/* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */
break;
}
}
- else if((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) == \
- USBFS_RQST_RCPT_IFC)
+ else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC)
{
/* Interface or Entity ID */
switch (CY_GET_REG8(USBFS_bRequest))
/* `#END` */
}
- #endif /* End USBFS_ENABLE_AUDIO_STREAMING */
+ #endif /* USBFS_ENABLE_AUDIO_STREAMING */
/* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */
}
}
else
- { /* USBFS_RQST_RCPT_OTHER */
+ {
+ /* USBFS_RQST_RCPT_OTHER */
}
}
- else
- { /* requestHandled is initialized as FALSE by default */
- }
return(requestHandled);
}
-
#endif /* USER_SUPPLIED_AUDIO_HANDLER */
/* `#END` */
-#endif /* End USBFS_ENABLE_AUDIO_CLASS*/
+#endif /* USBFS_ENABLE_AUDIO_CLASS */
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_audio.h
-* Version 2.60
+* Version 2.80
*
* Description:
-* Header File for the USFS component. Contains prototypes and constant values.
+* Header File for the USBFS component. Contains prototypes and constant values.
+*
+* Related Document:
+* Universal Serial Bus Device Class Definition for Audio Devices Release 1.0
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#define USBFS_GET_MEM (0x85u)
#define USBFS_GET_STAT (0xFFu)
-/* Endpoint Control Selectors (AUDIO Table A-19) */
+/* point Control Selectors (AUDIO Table A-19) */
#define USBFS_EP_CONTROL_UNDEFINED (0x00u)
#define USBFS_SAMPLING_FREQ_CONTROL (0x01u)
#define USBFS_PITCH_CONTROL (0x02u)
extern volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN];
extern volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN];
-#endif /* End CY_USBFS_USBFS_audio_H */
+#endif /* CY_USBFS_USBFS_audio_H */
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_boot.c
-* Version 2.60
+* Version 2.80
*
* Description:
* Boot loader API for USBFS Component.
* Note:
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
(CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface))
-/***************************************
-* Bootloader defines
-***************************************/
-
-#define USBFS_CyBtLdrStarttimer(X, T) {USBFS_universalTime = T * 10; X = 0u;}
-#define USBFS_CyBtLdrChecktimer(X) ((X++ < USBFS_universalTime) ? 1u : 0u)
-
-#define USBFS_BTLDR_OUT_EP (0x01u)
-#define USBFS_BTLDR_IN_EP (0x02u)
-
-
/***************************************
* Bootloader Variables
***************************************/
-static uint16 USBFS_universalTime;
-static uint8 USBFS_started = 0u;
+static uint8 USBFS_started = 0u;
/*******************************************************************************
/* USB component started, the correct enumeration will be checked in first Read operation */
USBFS_started = 1u;
-
}
* Resets the receive and transmit communication Buffers.
*
* Parameters:
-* None.
+* None
*
* Return:
-* None.
+* None
*
* Reentrant:
-* No.
+* No
*
*******************************************************************************/
void USBFS_CyBtldrCommReset(void)
* Returns the value that best describes the problem.
*
* Reentrant:
-* No.
+* No
*
*******************************************************************************/
-cystatus USBFS_CyBtldrCommWrite(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
{
- uint16 time;
- cystatus status;
+ cystatus retCode;
+ uint16 timeoutMs;
+
+ timeoutMs = ((uint16) 10u * timeOut); /* Convert from 10mS check to number 1mS checks */
/* Enable IN transfer */
USBFS_LoadInEP(USBFS_BTLDR_IN_EP, pData, USBFS_BTLDR_SIZEOF_READ_BUFFER);
- /* Start a timer to wait on. */
- USBFS_CyBtLdrStarttimer(time, timeOut);
-
/* Wait for the master to read it. */
- while((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) && \
- USBFS_CyBtLdrChecktimer(time))
+ while ((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) &&
+ (0u != timeoutMs))
{
- CyDelay(1u); /* 1ms delay */
+ CyDelay(USBFS_BTLDR_WAIT_1_MS);
+ timeoutMs--;
}
if (USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL)
{
- status = CYRET_TIMEOUT;
+ retCode = CYRET_TIMEOUT;
}
else
{
*count = size;
- status = CYRET_SUCCESS;
+ retCode = CYRET_SUCCESS;
}
- return(status);
+ return(retCode);
}
* Returns the value that best describes the problem.
*
* Reentrant:
-* No.
+* No
*
*******************************************************************************/
-cystatus USBFS_CyBtldrCommRead(uint8 *pData, uint16 size, uint16 *count, uint8 timeOut) CYSMALL
+cystatus USBFS_CyBtldrCommRead(uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL
{
- cystatus status;
- uint16 time;
+ cystatus retCode;
+ uint16 timeoutMs;
+
+ timeoutMs = ((uint16) 10u * timeOut); /* Convert from 10mS check to number 1mS checks */
- if(size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER)
+ if (size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER)
{
size = USBFS_BTLDR_SIZEOF_WRITE_BUFFER;
}
- /* Start a timer to wait on. */
- USBFS_CyBtLdrStarttimer(time, timeOut);
/* Wait on enumeration in first time */
- if(USBFS_started)
+ if (0u != USBFS_started)
{
/* Wait for Device to enumerate */
- while(!USBFS_GetConfiguration() && USBFS_CyBtLdrChecktimer(time))
+ while ((0u ==USBFS_GetConfiguration()) && (0u != timeoutMs))
{
- CyDelay(1u); /* 1ms delay */
+ CyDelay(USBFS_BTLDR_WAIT_1_MS);
+ timeoutMs--;
}
+
/* Enable first OUT, if enumeration complete */
- if(USBFS_GetConfiguration())
+ if (0u != USBFS_GetConfiguration())
{
- USBFS_IsConfigurationChanged(); /* Clear configuration changes state status */
+ (void) USBFS_IsConfigurationChanged(); /* Clear configuration changes state status */
USBFS_CyBtldrCommReset();
USBFS_started = 0u;
}
}
else /* Check for configuration changes, has been done by Host */
{
- if(USBFS_IsConfigurationChanged() != 0u) /* Host could send double SET_INTERFACE request or RESET */
+ if (0u != USBFS_IsConfigurationChanged()) /* Host could send double SET_INTERFACE request or RESET */
{
- if(USBFS_GetConfiguration() != 0u) /* Init OUT endpoints when device reconfigured */
+ if (0u != USBFS_GetConfiguration()) /* Init OUT endpoints when device reconfigured */
{
USBFS_CyBtldrCommReset();
}
}
}
+
+ timeoutMs = ((uint16) 10u * timeOut); /* Re-arm timeout */
+
/* Wait on next packet */
while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \
- USBFS_CyBtLdrChecktimer(time))
+ (0u != timeoutMs))
{
- CyDelay(1u); /* 1ms delay */
+ CyDelay(USBFS_BTLDR_WAIT_1_MS);
+ timeoutMs--;
}
/* OUT EP has completed */
if (USBFS_GetEPState(USBFS_BTLDR_OUT_EP) == USBFS_OUT_BUFFER_FULL)
{
*count = USBFS_ReadOutEP(USBFS_BTLDR_OUT_EP, pData, size);
- status = CYRET_SUCCESS;
+ retCode = CYRET_SUCCESS;
}
else
{
*count = 0u;
- status = CYRET_TIMEOUT;
+ retCode = CYRET_TIMEOUT;
}
- return(status);
+
+ return(retCode);
}
-#endif /* End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
+#endif /* CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_cdc.c
-* Version 2.60
+* Version 2.80
*
* Description:
-* USB HID Class request handler.
+* USB CDC class request handler.
*
-* Note:
+* Related Document:
+* Universal Serial Bus Class Definitions for Communication Devices Version 1.1
*
********************************************************************************
-* Copyright 2012-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2012-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* CDC Variables
***************************************/
-volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE];
+volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE] =
+{
+ 0x00u, 0xC2u, 0x01u, 0x00u, /* Data terminal rate 115200 */
+ 0x00u, /* 1 Stop bit */
+ 0x00u, /* None parity */
+ 0x08u /* 8 data bits */
+};
volatile uint8 USBFS_lineChanged;
volatile uint16 USBFS_lineControlBitmap;
volatile uint8 USBFS_cdc_data_in_ep;
/***************************************
* Static Function Prototypes
***************************************/
-static uint16 USBFS_StrLen(const char8 string[]) ;
+#if (USBFS_ENABLE_CDC_CLASS_API != 0u)
+ static uint16 USBFS_StrLen(const char8 string[]) ;
+#endif /* (USBFS_ENABLE_CDC_CLASS_API != 0u) */
/***************************************
***************************************/
#if (USBFS_ENABLE_CDC_CLASS_API != 0u)
-
/*******************************************************************************
* Function Name: USBFS_CDC_Init
********************************************************************************
********************************************************************************
*
* Summary:
- * Sends a specified number of bytes from the location specified by a
- * pointer to the PC.
+ * This function sends a specified number of bytes from the location specified
+ * by a pointer to the PC. The USBFS_CDCIsReady() function should be
+ * called before sending new data, to be sure that the previous data has
+ * finished sending.
+ * If the last sent packet is less than maximum packet size the USB transfer
+ * of this short packet will identify the end of the segment. If the last sent
+ * packet is exactly maximum packet size, it shall be followed by a zero-length
+ * packet (which is a short packet) to assure the end of segment is properly
+ * identified. To send zero-length packet, use USBFS_PutData() API
+ * with length parameter set to zero.
*
* Parameters:
* pData: pointer to the buffer containing data to be sent.
* length: Specifies the number of bytes to send from the pData
* buffer. Maximum length will be limited by the maximum packet
- * size for the endpoint.
+ * size for the endpoint. Data will be lost if length is greater than Max
+ * Packet Size.
*
* Return:
* None.
********************************************************************************
*
* Summary:
- * Sends a null terminated string to the PC.
+ * This function sends a null terminated string to the PC. This function will
+ * block if there is not enough memory to place the whole string. It will block
+ * until the entire string has been written to the transmit buffer.
+ * The USBUART_CDCIsReady() function should be called before sending data with
+ * a new call to USBFS_PutString(), to be sure that the previous data
+ * has finished sending.
*
* Parameters:
- * string: pointer to the string to be sent to the PC
+ * string: pointer to the string to be sent to the PC.
*
* Return:
* None.
* Reentrant:
* No.
*
- * Theory:
- * This function will block if there is not enough memory to place the whole
- * string, it will block until the entire string has been written to the
- * transmit buffer.
- *
*******************************************************************************/
void USBFS_PutString(const char8 string[])
{
- uint16 str_length;
- uint16 send_length;
- uint16 buf_index = 0u;
+ uint16 strLength;
+ uint16 sendLength;
+ uint16 bufIndex = 0u;
/* Get length of the null terminated string */
- str_length = USBFS_StrLen(string);
+ strLength = USBFS_StrLen(string);
do
{
/* Limits length to maximum packet size for the EP */
- send_length = (str_length > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ?
- USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : str_length;
+ sendLength = (strLength > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ?
+ USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : strLength;
/* Enable IN transfer */
- USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[buf_index], send_length);
- str_length -= send_length;
+ USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[bufIndex], sendLength);
+ strLength -= sendLength;
- /* If more data are present to send */
- if(str_length > 0u)
+ /* If more data are present to send or full packet was sent */
+ if((strLength > 0u) || (sendLength == USBFS_EP[USBFS_cdc_data_in_ep].bufferSize))
{
- buf_index += send_length;
+ bufIndex += sendLength;
/* Wait for the Host to read it. */
while(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState ==
USBFS_IN_BUFFER_FULL)
{
;
}
+ /* If the last sent packet is exactly maximum packet size,
+ * it shall be followed by a zero-length packet to assure the
+ * end of segment is properly identified by the terminal.
+ */
+ if(strLength == 0u)
+ {
+ USBFS_LoadInEP(USBFS_cdc_data_in_ep, NULL, 0u);
+ }
}
- }while(str_length > 0u);
+ }while(strLength > 0u);
}
*
* Summary:
* This function returns the number of bytes that were received from the PC.
+ * The returned length value should be passed to USBFS_GetData() as
+ * a parameter to read all received data. If all of the received data is not
+ * read at one time by the USBFS_GetData() API, the unread data will
+ * be lost.
*
* Parameters:
* None.
*
* Return:
- * Returns the number of received bytes.
+ * Returns the number of received bytes. The maximum amount of received data at
+ * a time is limited by the maximum packet size for the endpoint.
*
* Global variables:
* USBFS_cdc_data_out_ep: CDC OUT endpoint number used.
*******************************************************************************/
uint16 USBFS_GetCount(void)
{
- uint16 bytesCount = 0u;
+ uint16 bytesCount;
if (USBFS_EP[USBFS_cdc_data_out_ep].apiEpState == USBFS_OUT_BUFFER_FULL)
{
bytesCount = USBFS_GetEPCount(USBFS_cdc_data_out_ep);
}
+ else
+ {
+ bytesCount = 0u;
+ }
return(bytesCount);
}
*
* Summary:
* Returns a nonzero value if the component received data or received
- * zero-length packet. The GetAll() or GetData() API should be called to read
- * data from the buffer and re-init OUT endpoint even when zero-length packet
- * received.
+ * zero-length packet. The USBFS_GetAll() or
+ * USBFS_GetData() API should be called to read data from the buffer
+ * and re-init OUT endpoint even when zero-length packet received.
*
* Parameters:
* None.
********************************************************************************
*
* Summary:
- * Returns a nonzero value if the component is ready to send more data to the
- * PC. Otherwise returns zero. Should be called before sending new data to
- * ensure the previous data has finished sending.This function returns the
- * number of bytes that were received from the PC.
+ * This function returns a nonzero value if the component is ready to send more
+ * data to the PC; otherwise, it returns zero. The function should be called
+ * before sending new data when using any of the following APIs:
+ * USBFS_PutData(),USBFS_PutString(),
+ * USBFS_PutChar or USBFS_PutCRLF(),
+ * to be sure that the previous data has finished sending.
*
* Parameters:
* None.
*
* Return:
- * If the buffer can accept new data then this function returns a nonzero value.
- * Otherwise zero is returned.
+ * If the buffer can accept new data, this function returns a nonzero value.
+ * Otherwise, it returns zero.
*
* Global variables:
* USBFS_cdc_data_in_ep: CDC IN endpoint number used.
********************************************************************************
*
* Summary:
- * Gets a specified number of bytes from the input buffer and places it in a
- * data array specified by the passed pointer.
- * USBFS_DataIsReady() API should be called before, to be sure
- * that data is received from the Host.
+ * This function gets a specified number of bytes from the input buffer and
+ * places them in a data array specified by the passed pointer.
+ * The USBFS_DataIsReady() API should be called first, to be sure
+ * that data is received from the host. If all received data will not be read at
+ * once, the unread data will be lost. The USBFS_GetData() API should
+ * be called to get the number of bytes that were received.
*
* Parameters:
* pData: Pointer to the data array where data will be placed.
********************************************************************************
*
* Summary:
- * Reads one byte of received data from the buffer.
+ * This function reads one byte of received data from the buffer. If more than
+ * one byte has been received from the host, the rest of the data will be lost.
*
* Parameters:
* None.
********************************************************************************
*
* Summary:
- * This function returns clear on read status of the line.
+ * This function returns clear on read status of the line. It returns not zero
+ * value when the host sends updated coding or control information to the
+ * device. The USBFS_GetDTERate(), USBFS_GetCharFormat()
+ * or USBFS_GetParityType() or USBFS_GetDataBits() API
+ * should be called to read data coding information.
+ * The USBFS_GetLineControl() API should be called to read line
+ * control information.
*
* Parameters:
* None.
*
* Return:
- * If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE request received then not
- * zero value returned. Otherwise zero is returned.
+ * If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE requests are received, it
+ * returns a nonzero value. Otherwise, it returns zero.
*
* Global variables:
- * USBFS_transferState - it is checked to be sure then OUT data
+ * USBFS_transferState: it is checked to be sure then OUT data
* phase has been complete, and data written to the lineCoding or Control
* Bitmap buffer.
* USBFS_lineChanged: used as a flag to be aware that Host has been
return(USBFS_lineControlBitmap);
}
-#endif /* End USBFS_ENABLE_CDC_CLASS_API*/
+#endif /* USBFS_ENABLE_CDC_CLASS_API*/
/*******************************************************************************
/* `#END` */
-#endif /* End USBFS_ENABLE_CDC_CLASS*/
+#endif /* USBFS_ENABLE_CDC_CLASS*/
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_cdc.h
-* Version 2.60
+* Version 2.80
*
* Description:
-* Header File for the USFS component.
+* Header File for the USBFS component.
* Contains CDC class prototypes and constant values.
*
+* Related Document:
+* Universal Serial Bus Class Definitions for Communication Devices Version 1.1
+*
********************************************************************************
-* Copyright 2012-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2012-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
uint8 USBFS_GetParityType(void) ;
uint8 USBFS_GetDataBits(void) ;
uint16 USBFS_GetLineControl(void) ;
-#endif /* End USBFS_ENABLE_CDC_CLASS_API*/
+#endif /* USBFS_ENABLE_CDC_CLASS_API */
/***************************************
extern volatile uint8 USBFS_cdc_data_in_ep;
extern volatile uint8 USBFS_cdc_data_out_ep;
-#endif /* End CY_USBFS_USBFS_cdc_H */
+#endif /* CY_USBFS_USBFS_cdc_H */
/* [] END OF FILE */
;******************************************************************************
; File Name: USBFS_cdc.inf
-; Version 2.60
+; Version 2.80
;
; Description:
; Windows USB CDC setup file for USBUART Device.
;
;******************************************************************************
-; Copyright 2007-2013, Cypress Semiconductor Corporation. All rights reserved.
+; Copyright 2007-2014, Cypress Semiconductor Corporation. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
/*******************************************************************************
* File Name: USBFS_cls.c
-* Version 2.60
+* Version 2.80
*
* Description:
* USB Class request handler.
* Note:
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
break;
case USBFS_RQST_RCPT_EP: /* Class-specific request directed to the endpoint */
/* Find related interface to the endpoint, wIndexLo contain EP number */
- interfaceNumber =
- USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].interface;
+ interfaceNumber = USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) &
+ USBFS_DIR_UNUSED].interface;
break;
default: /* RequestHandled is initialized as FALSE by default */
break;
case USBFS_CLASS_AUDIO:
#if defined(USBFS_ENABLE_AUDIO_CLASS)
requestHandled = USBFS_DispatchAUDIOClassRqst();
- #endif /* USBFS_ENABLE_HID_CLASS */
+ #endif /* USBFS_CLASS_AUDIO */
break;
case USBFS_CLASS_CDC:
#if defined(USBFS_ENABLE_CDC_CLASS)
/*******************************************************************************
* File Name: USBFS_descr.c
-* Version 2.60
+* Version 2.80
*
* Description:
* USB descriptors and storage.
* Note:
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*****************************************************************************
* User supplied descriptors. If you want to specify your own descriptors,
-* remove the comments around the define USER_SUPPLIED_DESCRIPTORS below and
-* add your descriptors.
+* define USER_SUPPLIED_DESCRIPTORS below and add your descriptors.
*****************************************************************************/
/* `#START USER_DESCRIPTORS_DECLARATIONS` Place your declaration here */
/*******************************************************************************
* File Name: USBFS_drv.c
-* Version 2.60
+* Version 2.80
*
* Description:
* Endpoint 0 Driver for the USBFS Component.
* Note:
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************************
* File Name: USBFS_episr.c
-* Version 2.60
+* Version 2.80
*
* Description:
* Data endpoint Interrupt Service Routines
* Note:
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "USBFS.h"
#include "USBFS_pvt.h"
-#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)
+#if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u))
#include "USBFS_midi.h"
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+#endif /* (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)) */
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ #include "USBFS_EP8_DMA_Done_SR.h"
+ #include "USBFS_EP17_DMA_Done_SR.h"
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */
/***************************************
******************************************************************************/
CY_ISR(USBFS_EP_1_ISR)
{
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
uint8 int_en;
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
int_en = EA;
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) &
(uint8)~USBFS_SIE_EP_INT_EP1_MASK);
- #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT )
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT)
if(USBFS_midi_out_ep == USBFS_EP1)
{
USBFS_MIDI_OUT_EP_Service();
}
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */
/* `#START EP1_END_USER_CODE` Place your code here */
/* `#END` */
- #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 )
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
}
-#endif /* End USBFS_EP1_ISR_REMOVE */
+#endif /* USBFS_EP1_ISR_REMOVE */
#if(USBFS_EP2_ISR_REMOVE == 0u)
*******************************************************************************/
CY_ISR(USBFS_EP_2_ISR)
{
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
uint8 int_en;
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 )
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
int_en = EA;
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
& (uint8)~USBFS_SIE_EP_INT_EP2_MASK);
- #if( defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT )
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT)
if(USBFS_midi_out_ep == USBFS_EP2)
{
USBFS_MIDI_OUT_EP_Service();
}
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */
/* `#START EP2_END_USER_CODE` Place your code here */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
}
-#endif /* End USBFS_EP2_ISR_REMOVE */
+#endif /* USBFS_EP2_ISR_REMOVE */
#if(USBFS_EP3_ISR_REMOVE == 0u)
*******************************************************************************/
CY_ISR(USBFS_EP_3_ISR)
{
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
uint8 int_en;
#endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
int_en = EA;
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
& (uint8)~USBFS_SIE_EP_INT_EP3_MASK);
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT)
if(USBFS_midi_out_ep == USBFS_EP3)
{
USBFS_MIDI_OUT_EP_Service();
}
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */
/* `#START EP3_END_USER_CODE` Place your code here */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
}
-#endif /* End USBFS_EP3_ISR_REMOVE */
+#endif /* USBFS_EP3_ISR_REMOVE */
#if(USBFS_EP4_ISR_REMOVE == 0u)
*******************************************************************************/
CY_ISR(USBFS_EP_4_ISR)
{
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
int_en = EA;
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
& (uint8)~USBFS_SIE_EP_INT_EP4_MASK);
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT)
if(USBFS_midi_out_ep == USBFS_EP4)
{
USBFS_MIDI_OUT_EP_Service();
}
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */
/* `#START EP4_END_USER_CODE` Place your code here */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
}
-#endif /* End USBFS_EP4_ISR_REMOVE */
+#endif /* USBFS_EP4_ISR_REMOVE */
#if(USBFS_EP5_ISR_REMOVE == 0u)
*******************************************************************************/
CY_ISR(USBFS_EP_5_ISR)
{
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
int_en = EA;
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
& (uint8)~USBFS_SIE_EP_INT_EP5_MASK);
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT)
if(USBFS_midi_out_ep == USBFS_EP5)
{
USBFS_MIDI_OUT_EP_Service();
}
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */
/* `#START EP5_END_USER_CODE` Place your code here */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
}
-#endif /* End USBFS_EP5_ISR_REMOVE */
+#endif /* USBFS_EP5_ISR_REMOVE */
#if(USBFS_EP6_ISR_REMOVE == 0u)
*******************************************************************************/
CY_ISR(USBFS_EP_6_ISR)
{
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
int_en = EA;
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
& (uint8)~USBFS_SIE_EP_INT_EP6_MASK);
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT)
if(USBFS_midi_out_ep == USBFS_EP6)
{
USBFS_MIDI_OUT_EP_Service();
}
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */
/* `#START EP6_END_USER_CODE` Place your code here */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
}
-#endif /* End USBFS_EP6_ISR_REMOVE */
+#endif /* USBFS_EP6_ISR_REMOVE */
#if(USBFS_EP7_ISR_REMOVE == 0u)
*******************************************************************************/
CY_ISR(USBFS_EP_7_ISR)
{
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
int_en = EA;
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
& (uint8)~USBFS_SIE_EP_INT_EP7_MASK);
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT)
if(USBFS_midi_out_ep == USBFS_EP7)
{
USBFS_MIDI_OUT_EP_Service();
}
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */
/* `#START EP7_END_USER_CODE` Place your code here */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
}
-#endif /* End USBFS_EP7_ISR_REMOVE */
+#endif /* USBFS_EP7_ISR_REMOVE */
#if(USBFS_EP8_ISR_REMOVE == 0u)
*******************************************************************************/
CY_ISR(USBFS_EP_8_ISR)
{
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
uint8 int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
int_en = EA;
CyGlobalIntEnable; /* Make sure nested interrupt is enabled */
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR)
& (uint8)~USBFS_SIE_EP_INT_EP8_MASK);
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT)
if(USBFS_midi_out_ep == USBFS_EP8)
{
USBFS_MIDI_OUT_EP_Service();
}
- #endif /* End USBFS_ISR_SERVICE_MIDI_OUT */
+ #endif /* USBFS_ISR_SERVICE_MIDI_OUT */
/* `#START EP8_END_USER_CODE` Place your code here */
/* `#END` */
- #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
+ #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \
+ USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3)
EA = int_en;
#endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */
}
-#endif /* End USBFS_EP8_ISR_REMOVE */
+#endif /* USBFS_EP8_ISR_REMOVE */
/*******************************************************************************
/* Clear Data ready status */
*(reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) &=
(uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+ #if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ /* Setup common area DMA with rest of the data */
+ if(USBFS_inLength[ep] > USBFS_DMA_BYTES_PER_BURST)
+ {
+ USBFS_LoadNextInEP(ep, 0u);
+ }
+ else
+ {
+ USBFS_inBufFull[ep] = 1u;
+ }
+ #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
/* Write the Mode register */
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), USBFS_EP[ep].epMode);
#if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN)
{ /* Clear MIDI input pointer */
USBFS_midiInPointer = 0u;
}
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/
}
}
/* (re)arm Out EP only for mode2 */
USBFS_EP[ep].epMode);
}
}
- #endif /* End USBFS_EP_MM */
+ #endif /* USBFS_EP_MM */
/* `#START ARB_USER_CODE` Place your code here for handle Buffer Underflow/Overflow */
/* `#END` */
}
-#endif /* End USBFS_EP_MM */
+#endif /* USBFS_EP_MM */
+
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ /******************************************************************************
+ * Function Name: USBFS_EP_DMA_DONE_ISR
+ *******************************************************************************
+ *
+ * Summary:
+ * Endpoint 1 DMA Done Interrupt Service Routine
+ *
+ * Parameters:
+ * None.
+ *
+ * Return:
+ * None.
+ *
+ ******************************************************************************/
+ CY_ISR(USBFS_EP_DMA_DONE_ISR)
+ {
+ uint8 int8Status;
+ uint8 int17Status;
+ uint8 ep_status;
+ uint8 ep = USBFS_EP1;
+ uint8 ptr = 0u;
+
+ /* `#START EP_DMA_DONE_BEGIN_USER_CODE` Place your code here */
+
+ /* `#END` */
+
+ /* Read clear on read status register with the EP source of interrupt */
+ int17Status = USBFS_EP17_DMA_Done_SR_Read() & USBFS_EP17_SR_MASK;
+ int8Status = USBFS_EP8_DMA_Done_SR_Read() & USBFS_EP8_SR_MASK;
+
+ while(int8Status != 0u)
+ {
+ while(int17Status != 0u)
+ {
+ if((int17Status & 1u) != 0u) /* If EpX interrupt present */
+ {
+ /* Read Endpoint Status Register */
+ ep_status = CY_GET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr));
+ if( ((ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL) == 0u) &&
+ (USBFS_inBufFull[ep] == 0u))
+ {
+ /* `#START EP_DMA_DONE_USER_CODE` Place your code here */
+
+ /* `#END` */
+
+ CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ptr), 0x00u);
+ /* repeat 2 last bytes to prefetch endpoint area */
+ CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ptr),
+ USBFS_DMA_BYTES_PER_BURST * ep - USBFS_DMA_BYTES_REPEAT);
+ USBFS_LoadNextInEP(ep, 1);
+ /* Set Data ready status, This will generate DMA request */
+ * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY;
+ }
+ }
+ ptr += USBFS_EPX_CNTX_ADDR_OFFSET; /* prepare pointer for next EP */
+ ep++;
+ int17Status >>= 1u;
+ }
+ int8Status >>= 1u;
+ if(int8Status != 0u)
+ {
+ /* Prepare pointer for EP8 */
+ ptr = ((USBFS_EP8 - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
+ ep = USBFS_EP8;
+ int17Status = int8Status & 0x01u;
+ }
+ }
+
+ /* `#START EP_DMA_DONE_END_USER_CODE` Place your code here */
+
+ /* `#END` */
+ }
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_hid.c
-* Version 2.60
+* Version 2.80
*
* Description:
* USB HID Class request handler.
*
+* Related Document:
+* Device Class Definition for Human Interface Devices (HID) Version 1.11
+*
* Note:
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/* `#END` */
-#endif /* End USBFS_ENABLE_HID_CLASS */
+#endif /* USBFS_ENABLE_HID_CLASS */
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_hid.h
-* Version 2.60
+* Version 2.80
*
* Description:
-* Header File for the USFS component. Contains prototypes and constant values.
+* Header File for the USBFS component. Contains prototypes and constant values.
+*
+* Related Document:
+* Device Class Definition for Human Interface Devices (HID) Version 1.11
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#define USBFS_HID_GET_REPORT_OUTPUT (0x02u)
#define USBFS_HID_GET_REPORT_FEATURE (0x03u)
-#endif /* End CY_USBFS_USBFS_hid_H */
+#endif /* CY_USBFS_USBFS_hid_H */
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_midi.c
-* Version 2.60
+* Version 2.80
*
* Description:
* MIDI Streaming request handler.
* This file contains routines for sending and receiving MIDI
* messages, and handles running status in both directions.
*
+* Related Document:
+* Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0
+* MIDI 1.0 Detailed Specification Document Version 4.2
+*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */
#else
volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */
- #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */
+ #endif /* (USBFS_MIDI_IN_BUFF_SIZE >= 256) */
volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */
uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */
-#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
+#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */
uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */
-#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
+#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)
static USBFS_MIDI_RX_STATUS USBFS_MIDI1_Event; /* MIDI RX status structure */
static USBFS_MIDI_RX_STATUS USBFS_MIDI2_Event; /* MIDI RX status structure */
static volatile uint8 USBFS_MIDI2_TxRunStat; /* MIDI Output running status */
volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
/***************************************
{
#if (USBFS_MIDI_IN_BUFF_SIZE > 0)
USBFS_midiInPointer = 0u;
- #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
+ #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
#if (USBFS_MIDI_IN_BUFF_SIZE > 0)
/* Init DMA configurations for IN EP*/
USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer,
USBFS_MIDI_IN_BUFF_SIZE);
-
- #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
+
+ #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
/* Init DMA configurations for OUT EP*/
(void)USBFS_ReadOutEP(USBFS_midi_out_ep, USBFS_midiOutBuffer,
USBFS_MIDI_OUT_BUFF_SIZE);
- #endif /*USBFS_MIDI_OUT_BUFF_SIZE > 0 */
- #endif /* End USBFS__EP_DMAAUTO */
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */
+ #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
USBFS_EnableOutEP(USBFS_midi_out_ep);
- #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */
/* Initialize the MIDI port(s) */
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)
USBFS_MIDI_Init();
- #endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
}
#if (USBFS_MIDI_OUT_BUFF_SIZE > 0)
#else
uint8 outLength;
uint8 outPointer;
- #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >=256 */
+ #endif /* USBFS_MIDI_OUT_BUFF_SIZE >=256 */
uint8 dmaState = 0u;
/* Service the USB MIDI output endpoint */
if (USBFS_GetEPState(USBFS_midi_out_ep) == USBFS_OUT_BUFFER_FULL)
{
- #if USBFS_MIDI_OUT_BUFF_SIZE >= 256
+ #if(USBFS_MIDI_OUT_BUFF_SIZE >= 256)
outLength = USBFS_GetEPCount(USBFS_midi_out_ep);
#else
outLength = (uint8)USBFS_GetEPCount(USBFS_midi_out_ep);
- #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */
+
#if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
- #if USBFS_MIDI_OUT_BUFF_SIZE >= 256
+ #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256)
outLength = USBFS_ReadOutEP(USBFS_midi_out_ep,
USBFS_midiOutBuffer, outLength);
#else
outLength = (uint8)USBFS_ReadOutEP(USBFS_midi_out_ep,
USBFS_midiOutBuffer, (uint16)outLength);
- #endif /* End USBFS_MIDI_OUT_BUFF_SIZE >= 256 */
+ #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */
+
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
do /* wait for DMA transfer complete */
{
- (void)CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState);
- }while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u);
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+ (void) CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState);
+ }
+ while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u);
+ #endif /* (USBFS_EP_MM == USBFS__EP_DMAMANUAL) */
+
+ #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */
+
if(dmaState != 0u)
{
/* Suppress compiler warning */
}
+
if (outLength >= USBFS_EVENT_LENGTH)
{
outPointer = 0u;
{
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
USBFS_MIDI2_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]);
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
}
else
{
/* `#END` */
}
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
/* Process any local MIDI output functions */
USBFS_callbackLocalMidiEvent(
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
/* Enable Out EP*/
USBFS_EnableOutEP(USBFS_midi_out_ep);
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+ #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */
}
}
#else /* USBFS_EP_MM != USBFS__EP_DMAAUTO */
/* rearm IN EP */
USBFS_LoadInEP(USBFS_midi_in_ep, NULL, (uint16)USBFS_midiInPointer);
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO*/
+ #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */
/* Clear the midiInPointer. For DMA mode, clear this pointer in the ARB ISR when data are moved by DMA */
#if(USBFS_EP_MM == USBFS__EP_MANUAL)
USBFS_midiInPointer = 0u;
- #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */
+ #endif /* (USBFS_EP_MM == USBFS__EP_MANUAL) */
}
}
}
uint8 m2 = 0u;
do
{
- if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
+ if (USBFS_midiInPointer <=
+ (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
{
/* Check MIDI1 input port for a complete event */
m1 = USBFS_MIDI1_GetEvent();
}
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
- if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
+ if (USBFS_midiInPointer <=
+ (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
{
/* Check MIDI2 input port for a complete event */
m2 = USBFS_MIDI2_GetEvent();
USBFS_MIDI2_Event.size, USBFS_MIDI_CABLE_01);
}
}
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
- }while( (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH))
- && ((m1 != 0u) || (m2 != 0u)) );
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+ }while( (USBFS_midiInPointer <=
+ (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) &&
+ ((m1 != 0u) || (m2 != 0u)) );
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
/* Service the USB MIDI input endpoint */
USBFS_MIDI_IN_EP_Service();
MIDI1_UART_DisableRxInt();
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
MIDI2_UART_DisableRxInt();
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
if (USBFS_midiInPointer >
(USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
(USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
{
USBFS_MIDI_IN_EP_Service();
- if (USBFS_midiInPointer >
- (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
+ if(USBFS_midiInPointer >
+ (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH))
{
/* Error condition. HOST is not ready to receive this packet. */
retError = USBFS_TRUE;
break;
}
}
- }while(ic > USBFS_EVENT_BYTE3);
+ }
+ while(ic > USBFS_EVENT_BYTE3);
if(retError == USBFS_FALSE)
{
MIDI1_UART_EnableRxInt();
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
MIDI2_UART_EnableRxInt();
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+ #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
return (retError);
}
/* Change the priority of the UART TX interrupt */
CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM);
CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM);
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/
/* `#START MIDI_INIT_CUSTOM` Init other extended UARTs here */
uint8 rxData;
#if (MIDI1_UART_RXBUFFERSIZE >= 256u)
uint16 rxBufferRead;
- #if CY_PSOC3 /* This local variable is required only for PSOC3 and large buffer */
+ #if (CY_PSOC3) /* This local variable is required only for PSOC3 and large buffer */
uint16 rxBufferWrite;
- #endif /* end CY_PSOC3 */
+ #endif /* (CY_PSOC3) */
#else
uint8 rxBufferRead;
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+ #endif /* (MIDI1_UART_RXBUFFERSIZE >= 256u) */
+
uint8 rxBufferLoopDetect;
/* Read buffer loop condition to the local variable */
rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect;
/* Protect variables that could change on interrupt by disabling Rx interrupt.*/
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntDisable(MIDI1_UART_RX_VECT_NUM);
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
rxBufferRead = MIDI1_UART_rxBufferRead;
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
rxBufferWrite = MIDI1_UART_rxBufferWrite;
CyIntEnable(MIDI1_UART_RX_VECT_NUM);
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
/* Stay here until either the buffer is empty or we have a complete message
* in the message buffer. Note that we must use a temporary buffer pointer
while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
#else
while ( ((rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
{
rxData = MIDI1_UART_rxBuffer[rxBufferRead];
/* Increment pointer with a wrap */
MIDI1_UART_rxBufferLoopDetect = 0u;
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntDisable(MIDI1_UART_RX_VECT_NUM);
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+ #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */
MIDI1_UART_rxBufferRead = rxBufferRead;
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntEnable(MIDI1_UART_RX_VECT_NUM);
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+ #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */
}
msgRtn = USBFS_ProcessMidiIn(rxData,
*/
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntDisable(MIDI1_UART_RX_VECT_NUM);
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
MIDI1_UART_rxBufferRead = rxBufferRead;
#if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntEnable(MIDI1_UART_RX_VECT_NUM);
- #endif /* End MIDI1_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
}
return (msgRtn);
/* `#END` */
}
+
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
uint8 rxData;
#if (MIDI2_UART_RXBUFFERSIZE >= 256u)
uint16 rxBufferRead;
- #if CY_PSOC3 /* This local variable required only for PSOC3 and large buffer */
+ #if (CY_PSOC3) /* This local variable required only for PSOC3 and large buffer */
uint16 rxBufferWrite;
- #endif /* end CY_PSOC3 */
+ #endif /* (CY_PSOC3) */
#else
uint8 rxBufferRead;
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+ #endif /* (MIDI2_UART_RXBUFFERSIZE >= 256) */
+
uint8 rxBufferLoopDetect;
/* Read buffer loop condition to the local variable */
rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect;
/* Protect variables that could change on interrupt by disabling Rx interrupt.*/
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntDisable(MIDI2_UART_RX_VECT_NUM);
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
rxBufferRead = MIDI2_UART_rxBufferRead;
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
rxBufferWrite = MIDI2_UART_rxBufferWrite;
CyIntEnable(MIDI2_UART_RX_VECT_NUM);
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
/* Stay here until either the buffer is empty or we have a complete message
* in the message buffer. Note that we must use a temporary output pointer to
while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
#else
while ( ((rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) )
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 && CY_PSOC3 */
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
{
rxData = MIDI2_UART_rxBuffer[rxBufferRead];
rxBufferRead++;
MIDI2_UART_rxBufferLoopDetect = 0u;
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntDisable(MIDI2_UART_RX_VECT_NUM);
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
MIDI2_UART_rxBufferRead = rxBufferRead;
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntEnable(MIDI2_UART_RX_VECT_NUM);
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
}
msgRtn = USBFS_ProcessMidiIn(rxData,
*/
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntDisable(MIDI2_UART_RX_VECT_NUM);
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
MIDI2_UART_rxBufferRead = rxBufferRead;
#if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3))
CyIntEnable(MIDI2_UART_RX_VECT_NUM);
- #endif /* End MIDI2_UART_RXBUFFERSIZE >= 256 */
+ #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */
}
return (msgRtn);
/* `#END` */
}
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */
+#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */
-#endif /* End (USBFS_ENABLE_MIDI_API != 0u) */
+#endif /* (USBFS_ENABLE_MIDI_API != 0u) */
/* `#START MIDI_FUNCTIONS` Place any additional functions here */
/* `#END` */
-#endif /* End defined(USBFS_ENABLE_MIDI_STREAMING) */
+#endif /* defined(USBFS_ENABLE_MIDI_STREAMING) */
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_midi.h
-* Version 2.60
+* Version 2.80
*
* Description:
* Header File for the USBFS MIDI module.
* Contains prototypes and constant values.
*
+* Related Document:
+* Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0
+* MIDI 1.0 Detailed Specification Document Version 4.2
+*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/***************************************
-* Data Struct Definition
+* Data Structure Definition
***************************************/
/* The following structure is used to hold status information for
#define USBFS_CUSTOM_UART_TX_PRIOR_NUM (0x04u)
#define USBFS_CUSTOM_UART_RX_PRIOR_NUM (0x02u)
-#define USBFS_ISR_SERVICE_MIDI_OUT \
+#define USBFS_ISR_SERVICE_MIDI_OUT \
( (USBFS_ENABLE_MIDI_API != 0u) && \
- (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO) )
+ (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO))
#define USBFS_ISR_SERVICE_MIDI_IN \
( (USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_IN_BUFF_SIZE > 0) )
+
/***************************************
* External function references
***************************************/
#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF)
#include "MIDI1_UART.h"
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
#include "MIDI2_UART.h"
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+#endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
#include <CyDmac.h>
-#endif /* End USBFS_EP_MM */
+#endif /* USBFS_EP_MM */
/***************************************
uint8 USBFS_MIDI2_GetEvent(void) ;
void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[])
;
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
/***************************************
extern volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */
#else
extern volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */
- #endif /* End USBFS_MIDI_IN_BUFF_SIZE >=256 */
+ #endif /* USBFS_MIDI_IN_BUFF_SIZE >=256 */
extern volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */
extern uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */
#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */
extern volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */
#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF)
extern volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */
- #endif /* End USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
-#endif /* End USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
+ #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */
+#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */
#endif /* USBFS_ENABLE_MIDI_STREAMING */
-#endif /* End CY_USBFS_USBFS_midi_H */
+#endif /* CY_USBFS_USBFS_midi_H */
/* [] END OF FILE */
/*******************************************************************************
* File Name: USBFS_pm.c
-* Version 2.60
+* Version 2.80
*
* Description:
* This file provides Suspend/Resume APIs functionality.
* Note:
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#if(USBFS_DP_ISR_REMOVE == 0u)
-
/*******************************************************************************
* Function Name: USBFS_DP_Interrupt
********************************************************************************
********************************************************************************
*
* Summary:
-* This function disables the USBFS block and prepares for power donwn mode.
+* This function disables the USBFS block and prepares for power down mode.
*
* Parameters:
* None.
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
/* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */
USBFS_USBIO_CR0_REG &= (uint8)~USBFS_USBIO_CR0_TEN;
/* Disable the SIE */
USBFS_CR0_REG &= (uint8)~USBFS_CR0_ENABLE;
- CyDelayUs(0u); /*~50ns delay */
+ CyDelayUs(0u); /* ~50ns delay */
/* Store mode and Disable VRegulator*/
USBFS_backup.mode = USBFS_CR1_REG & USBFS_CR1_REG_ENABLE;
USBFS_CR1_REG &= (uint8)~USBFS_CR1_REG_ENABLE;
{
USBFS_backup.enableState = 0u;
}
+
CyExitCriticalSection(enableInterrupts);
/* Set the DP Interrupt for wake-up from sleep mode. */
#if(USBFS_DP_ISR_REMOVE == 0u)
- (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR);
+ (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR);
CyIntSetPriority(USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIOR);
CyIntClearPending(USBFS_DP_INTC_VECT_NUM);
CyIntEnable(USBFS_DP_INTC_VECT_NUM);
#endif /* (USBFS_DP_ISR_REMOVE == 0u) */
-
}
{
#if(USBFS_DP_ISR_REMOVE == 0u)
CyIntDisable(USBFS_DP_INTC_VECT_NUM);
- #endif /* End USBFS_DP_ISR_REMOVE */
+ #endif /* USBFS_DP_ISR_REMOVE */
/* Enable USB block */
USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB;
/* Set the USBIO pull-up enable */
USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N;
- /* Reinit Arbiter configuration for DMA transfers */
+ /* Re-init Arbiter configuration for DMA transfers */
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
- /* usb arb interrupt enable */
+ /* Usb arb interrupt enable */
USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK;
#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL)
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA;
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAMANUAL */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
/*Set cfg cmplt this rises DMA request when the full configuration is done */
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
/* STALL_IN_OUT */
CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT);
/* Restore USB register settings */
USBFS_RestoreConfig();
-
}
+
CyExitCriticalSection(enableInterrupts);
}
/*******************************************************************************
* File Name: .h
-* Version 2.60
+* Version 2.80
*
* Description:
* This private file provides constants and parameter values for the
* Note:
*
********************************************************************************
-* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
extern uint8 USBFS_DmaChan[USBFS_MAX_EP];
extern uint8 USBFS_DmaTd[USBFS_MAX_EP];
-#endif /* End USBFS_EP_MM */
+#endif /* USBFS_EP_MM */
+#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ extern uint8 USBFS_DmaNextTd[USBFS_MAX_EP];
+ extern const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP];
+ extern volatile uint16 USBFS_inLength[USBFS_MAX_EP];
+ extern const uint8 *USBFS_inDataPointer[USBFS_MAX_EP];
+ extern volatile uint8 USBFS_inBufFull[USBFS_MAX_EP];
+#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */
extern volatile uint8 USBFS_ep0Toggle;
extern volatile uint8 USBFS_lastPacketSize;
void USBFS_ConfigAltChanged(void) ;
void USBFS_ConfigReg(void) ;
-const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)
+const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)
;
const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void)
;
void USBFS_SaveConfig(void) ;
void USBFS_RestoreConfig(void) ;
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) ;
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */
+
#if defined(USBFS_ENABLE_IDSN_STRING)
void USBFS_ReadDieID(uint8 descr[]) ;
#endif /* USBFS_ENABLE_IDSN_STRING */
#if defined(USBFS_ENABLE_HID_CLASS)
uint8 USBFS_DispatchHIDClassRqst(void);
-#endif /* End USBFS_ENABLE_HID_CLASS */
+#endif /* USBFS_ENABLE_HID_CLASS */
#if defined(USBFS_ENABLE_AUDIO_CLASS)
uint8 USBFS_DispatchAUDIOClassRqst(void);
-#endif /* End USBFS_ENABLE_HID_CLASS */
+#endif /* USBFS_ENABLE_HID_CLASS */
#if defined(USBFS_ENABLE_CDC_CLASS)
uint8 USBFS_DispatchCDCClassRqst(void);
-#endif /* End USBFS_ENABLE_CDC_CLASS */
+#endif /* USBFS_ENABLE_CDC_CLASS */
CY_ISR_PROTO(USBFS_EP_0_ISR);
#if(USBFS_EP1_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_EP_1_ISR);
-#endif /* End USBFS_EP1_ISR_REMOVE */
+#endif /* USBFS_EP1_ISR_REMOVE */
#if(USBFS_EP2_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_EP_2_ISR);
-#endif /* End USBFS_EP2_ISR_REMOVE */
+#endif /* USBFS_EP2_ISR_REMOVE */
#if(USBFS_EP3_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_EP_3_ISR);
-#endif /* End USBFS_EP3_ISR_REMOVE */
+#endif /* USBFS_EP3_ISR_REMOVE */
#if(USBFS_EP4_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_EP_4_ISR);
-#endif /* End USBFS_EP4_ISR_REMOVE */
+#endif /* USBFS_EP4_ISR_REMOVE */
#if(USBFS_EP5_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_EP_5_ISR);
-#endif /* End USBFS_EP5_ISR_REMOVE */
+#endif /* USBFS_EP5_ISR_REMOVE */
#if(USBFS_EP6_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_EP_6_ISR);
-#endif /* End USBFS_EP6_ISR_REMOVE */
+#endif /* USBFS_EP6_ISR_REMOVE */
#if(USBFS_EP7_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_EP_7_ISR);
-#endif /* End USBFS_EP7_ISR_REMOVE */
+#endif /* USBFS_EP7_ISR_REMOVE */
#if(USBFS_EP8_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_EP_8_ISR);
-#endif /* End USBFS_EP8_ISR_REMOVE */
+#endif /* USBFS_EP8_ISR_REMOVE */
CY_ISR_PROTO(USBFS_BUS_RESET_ISR);
#if(USBFS_SOF_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_SOF_ISR);
-#endif /* End USBFS_SOF_ISR_REMOVE */
+#endif /* USBFS_SOF_ISR_REMOVE */
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
CY_ISR_PROTO(USBFS_ARB_ISR);
-#endif /* End USBFS_EP_MM */
+#endif /* USBFS_EP_MM */
#if(USBFS_DP_ISR_REMOVE == 0u)
CY_ISR_PROTO(USBFS_DP_ISR);
-#endif /* End USBFS_DP_ISR_REMOVE */
-
+#endif /* USBFS_DP_ISR_REMOVE */
+#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u))
+ CY_ISR_PROTO(USBFS_EP_DMA_DONE_ISR);
+#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */
/***************************************
* Request Handlers
/***************************************
* HID Internal references
***************************************/
+
#if defined(USBFS_ENABLE_HID_CLASS)
void USBFS_FindReport(void) ;
void USBFS_FindReportDescriptor(void) ;
/***************************************
* MIDI Internal references
***************************************/
+
#if defined(USBFS_ENABLE_MIDI_STREAMING)
void USBFS_MIDI_IN_EP_Service(void) ;
#endif /* USBFS_ENABLE_MIDI_STREAMING */
/*******************************************************************************
* File Name: USBFS_std.c
-* Version 2.60
+* Version 2.80
*
* Description:
* USB Standard request handler.
* Note:
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#include "USBFS.h"
#include "USBFS_cdc.h"
#include "USBFS_pvt.h"
-#if defined(USBFS_ENABLE_MIDI_STREAMING)
+#if defined(USBFS_ENABLE_MIDI_STREAMING)
#include "USBFS_midi.h"
-#endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+#endif /* USBFS_ENABLE_MIDI_STREAMING*/
/***************************************
#if defined(USBFS_ENABLE_FWSN_STRING)
-
/*******************************************************************************
* Function Name: USBFS_SerialNumString
********************************************************************************
USBFS_snStringConfirm = USBFS_FALSE;
if(snString != NULL)
{
- USBFS_fwSerialNumberStringDescriptor = snString;
/* Check descriptor validation */
if( (snString[0u] > 1u ) && (snString[1u] == USBFS_DESCR_STRING) )
{
+ USBFS_fwSerialNumberStringDescriptor = snString;
USBFS_snStringConfirm = USBFS_TRUE;
}
}
{
uint8 requestHandled = USBFS_FALSE;
uint8 interfaceNumber;
+ uint8 configurationN;
#if defined(USBFS_ENABLE_STRINGS)
volatile uint8 *pStr = 0u;
#if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS)
else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_CONFIG)
{
pTmp = USBFS_GetConfigTablePtr(CY_GET_REG8(USBFS_wValueLo));
- USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;
- USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \
- USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \
- (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];
- requestHandled = USBFS_InitControlRead();
+ if( pTmp != NULL ) /* Verify that requested descriptor exists */
+ {
+ USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list;
+ USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \
+ USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \
+ (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW];
+ requestHandled = USBFS_InitControlRead();
+ }
}
#if defined(USBFS_ENABLE_STRINGS)
else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_STRING)
pStr = &pStr[descrLength];
nStr++;
}
- #endif /* End USBFS_ENABLE_DESCRIPTOR_STRINGS */
+ #endif /* USBFS_ENABLE_DESCRIPTOR_STRINGS */
/* Microsoft OS String*/
#if defined(USBFS_ENABLE_MSOS_STRING)
if( CY_GET_REG8(USBFS_wValueLo) == USBFS_STRING_MSOS )
{
pStr = (volatile uint8 *)&USBFS_MSOS_DESCRIPTOR[0u];
}
- #endif /* End USBFS_ENABLE_MSOS_STRING*/
+ #endif /* USBFS_ENABLE_MSOS_STRING*/
/* SN string */
#if defined(USBFS_ENABLE_SN_STRING)
if( (CY_GET_REG8(USBFS_wValueLo) != 0u) &&
(CY_GET_REG8(USBFS_wValueLo) ==
USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT]) )
{
- pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];
- #if defined(USBFS_ENABLE_FWSN_STRING)
- if(USBFS_snStringConfirm != USBFS_FALSE)
- {
- pStr = USBFS_fwSerialNumberStringDescriptor;
- }
- #endif /* USBFS_ENABLE_FWSN_STRING */
+
#if defined(USBFS_ENABLE_IDSN_STRING)
/* Read DIE ID and generate string descriptor in RAM */
USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor);
pStr = USBFS_idSerialNumberStringDescriptor;
- #endif /* End USBFS_ENABLE_IDSN_STRING */
+ #elif defined(USBFS_ENABLE_FWSN_STRING)
+ if(USBFS_snStringConfirm != USBFS_FALSE)
+ {
+ pStr = USBFS_fwSerialNumberStringDescriptor;
+ }
+ else
+ {
+ pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];
+ }
+ #else
+ pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u];
+ #endif /* defined(USBFS_ENABLE_IDSN_STRING) */
}
- #endif /* End USBFS_ENABLE_SN_STRING */
+ #endif /* USBFS_ENABLE_SN_STRING */
if (*pStr != 0u)
{
USBFS_currentTD.count = *pStr;
requestHandled = USBFS_InitControlRead();
}
}
- #endif /* End USBFS_ENABLE_STRINGS */
+ #endif /* USBFS_ENABLE_STRINGS */
else
{
requestHandled = USBFS_DispatchClassRqst();
requestHandled = USBFS_InitNoDataControlTransfer();
break;
case USBFS_SET_CONFIGURATION:
- USBFS_configuration = CY_GET_REG8(USBFS_wValueLo);
- USBFS_configurationChanged = USBFS_TRUE;
- USBFS_Config(USBFS_TRUE);
- requestHandled = USBFS_InitNoDataControlTransfer();
+ configurationN = CY_GET_REG8(USBFS_wValueLo);
+ if(configurationN > 0u)
+ { /* Verify that configuration descriptor exists */
+ pTmp = USBFS_GetConfigTablePtr(configurationN - 1u);
+ }
+ /* Responds with a Request Error when configuration number is invalid */
+ if (((configurationN > 0u) && (pTmp != NULL)) || (configurationN == 0u))
+ {
+ /* Set new configuration if it has been changed */
+ if(configurationN != USBFS_configuration)
+ {
+ USBFS_configuration = configurationN;
+ USBFS_configurationChanged = USBFS_TRUE;
+ USBFS_Config(USBFS_TRUE);
+ }
+ requestHandled = USBFS_InitNoDataControlTransfer();
+ }
break;
case USBFS_SET_INTERFACE:
if (USBFS_ValidateAlternateSetting() != 0u)
USBFS_Config(USBFS_FALSE);
#else
USBFS_ConfigAltChanged();
- #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
+ #endif /* (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
/* Update handled Alt setting changes status */
USBFS_interfaceSetting_last[interfaceNumber] =
USBFS_interfaceSetting[interfaceNumber];
uint8 value;
const char8 CYCODE hex[16u] = "0123456789ABCDEF";
-
/* Check descriptor validation */
if( descr != NULL)
{
}
}
-#endif /* End USBFS_ENABLE_IDSN_STRING */
+#endif /* USBFS_ENABLE_IDSN_STRING */
/*******************************************************************************
uint8 ep;
uint8 i;
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
- uint8 ep_type = 0u;
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+ uint8 epType = 0u;
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
/* Set the endpoint buffer addresses */
ep = USBFS_EP1;
for (i = 0u; i < 0x80u; i+= 0x10u)
{
- CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_CRC_BYPASS |
- USBFS_ARB_EPX_CFG_RESET);
-
+ CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_DEFAULT);
#if(USBFS_EP_MM != USBFS__EP_MANUAL)
/* Enable all Arbiter EP Interrupts : err, buf under, buf over, dma gnt(mode2 only), in buf full */
CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_INT_EN_IND + i), USBFS_ARB_EPX_INT_MASK);
- #endif /* End USBFS_EP_MM != USBFS__EP_MANUAL */
+ #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */
if(USBFS_EP[ep].epMode != USBFS_MODE_DISABLE)
{
CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_OUT);
/* Prepare EP type mask for automatic memory allocation */
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
- ep_type |= (uint8)(0x01u << (ep - USBFS_EP1));
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+ epType |= (uint8)(0x01u << (ep - USBFS_EP1));
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
}
}
else
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu);
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u);
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */
ep++;
}
USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST; /* DMA burst threshold */
USBFS_DMA_THRES_MSB_REG = 0u;
USBFS_EP_ACTIVE_REG = USBFS_ARB_INT_MASK;
- USBFS_EP_TYPE_REG = ep_type;
+ USBFS_EP_TYPE_REG = epType;
/* Cfg_cmp bit set to 1 once configuration is complete. */
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM |
USBFS_ARB_CFG_CFG_CPM;
/* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */
USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM;
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
CY_SET_REG8(USBFS_SIE_EP_INT_EN_PTR, 0xFFu);
}
uint8 ep;
uint8 cur_ep;
uint8 i;
- uint8 ep_type;
+ uint8 epType;
const uint8 *pDescr;
#if(USBFS_EP_MM != USBFS__EP_DMAAUTO)
uint16 buffCount = 0u;
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */
const T_USBFS_LUT CYCODE *pTmp;
const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP;
pEP = (T_USBFS_EP_SETTINGS_BLOCK *) pTmp->p_list;
for (i = 0u; i < ep; i++)
{
- /* Compare current Alternate setting with EP Alt*/
+ /* Compare current Alternate setting with EP Alt */
if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)
{
cur_ep = pEP->addr & USBFS_DIR_UNUSED;
- ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;
+ epType = pEP->attributes & USBFS_EP_TYPE_MASK;
if (pEP->addr & USBFS_DIR_IN)
{
/* IN Endpoint */
USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;
- USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+ USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;
#if defined(USBFS_ENABLE_CDC_CLASS)
if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
(pEP->bMisc == USBFS_CLASS_CDC)) &&
- (ep_type != USBFS_EP_TYPE_INT))
+ (epType != USBFS_EP_TYPE_INT))
{
USBFS_cdc_data_in_ep = cur_ep;
}
- #endif /* End USBFS_ENABLE_CDC_CLASS*/
+ #endif /* USBFS_ENABLE_CDC_CLASS*/
#if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
(USBFS_MIDI_IN_BUFF_SIZE > 0) )
if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
- (ep_type == USBFS_EP_TYPE_BULK))
+ (epType == USBFS_EP_TYPE_BULK))
{
USBFS_midi_in_ep = cur_ep;
}
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/
}
else
{
/* OUT Endpoint */
USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;
- USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+ USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;
#if defined(USBFS_ENABLE_CDC_CLASS)
if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
(pEP->bMisc == USBFS_CLASS_CDC)) &&
- (ep_type != USBFS_EP_TYPE_INT))
+ (epType != USBFS_EP_TYPE_INT))
{
USBFS_cdc_data_out_ep = cur_ep;
}
- #endif /* End USBFS_ENABLE_CDC_CLASS*/
+ #endif /* USBFS_ENABLE_CDC_CLASS*/
#if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
(USBFS_MIDI_OUT_BUFF_SIZE > 0) )
if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
- (ep_type == USBFS_EP_TYPE_BULK))
+ (epType == USBFS_EP_TYPE_BULK))
{
USBFS_midi_out_ep = cur_ep;
}
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/
}
USBFS_EP[cur_ep].bufferSize = pEP->bufferSize;
USBFS_EP[cur_ep].addr = pEP->addr;
}
pEP = &pEP[1u];
}
- #else /* Config for static EP memory allocation */
+ #else /* Configure for static EP memory allocation */
for (i = USBFS_EP1; i < USBFS_MAX_EP; i++)
{
/* p_list points the endpoint setting table. */
/* Compare current Alternate setting with EP Alt*/
if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting)
{
- ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;
+ epType = pEP->attributes & USBFS_EP_TYPE_MASK;
if ((pEP->addr & USBFS_DIR_IN) != 0u)
{
/* IN Endpoint */
USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING;
- USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+ USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;
- /* Find and init CDC IN endpoint number */
+ /* Find and initialize CDC IN endpoint number */
#if defined(USBFS_ENABLE_CDC_CLASS)
if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
(pEP->bMisc == USBFS_CLASS_CDC)) &&
- (ep_type != USBFS_EP_TYPE_INT))
+ (epType != USBFS_EP_TYPE_INT))
{
USBFS_cdc_data_in_ep = i;
}
- #endif /* End USBFS_ENABLE_CDC_CLASS*/
+ #endif /* USBFS_ENABLE_CDC_CLASS*/
#if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
(USBFS_MIDI_IN_BUFF_SIZE > 0) )
if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
- (ep_type == USBFS_EP_TYPE_BULK))
+ (epType == USBFS_EP_TYPE_BULK))
{
USBFS_midi_in_ep = i;
}
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/
}
else
{
/* OUT Endpoint */
USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING;
- USBFS_EP[i].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+ USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;
- /* Find and init CDC IN endpoint number */
+ /* Find and initialize CDC IN endpoint number */
#if defined(USBFS_ENABLE_CDC_CLASS)
if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||
(pEP->bMisc == USBFS_CLASS_CDC)) &&
- (ep_type != USBFS_EP_TYPE_INT))
+ (epType != USBFS_EP_TYPE_INT))
{
USBFS_cdc_data_out_ep = i;
}
- #endif /* End USBFS_ENABLE_CDC_CLASS*/
+ #endif /* USBFS_ENABLE_CDC_CLASS*/
#if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \
(USBFS_MIDI_OUT_BUFF_SIZE > 0) )
if((pEP->bMisc == USBFS_CLASS_AUDIO) &&
- (ep_type == USBFS_EP_TYPE_BULK))
+ (epType == USBFS_EP_TYPE_BULK))
{
USBFS_midi_out_ep = i;
}
- #endif /* End USBFS_ENABLE_MIDI_STREAMING*/
+ #endif /* USBFS_ENABLE_MIDI_STREAMING*/
}
USBFS_EP[i].addr = pEP->addr;
USBFS_EP[i].attrib = pEP->attributes;
#if(USBFS_EP_MM == USBFS__EP_DMAAUTO)
break; /* use first EP setting in Auto memory managment */
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
}
}
pEP = &pEP[1u];
}
}
- #endif /* End (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
+ #endif /* (USBFS_EP_MA == USBFS__MA_DYNAMIC) */
/* Init class array for each interface and interface number for each EP.
* It is used for handling Class specific requests directed to either an
USBFS_EP[ep].buffOffset = buffCount;
buffCount += USBFS_EP[ep].bufferSize;
}
- #endif /* End USBFS_EP_MM != USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */
/* Configure hardware registers */
USBFS_ConfigReg();
uint8 ep;
uint8 cur_ep;
uint8 i;
- uint8 ep_type;
+ uint8 epType;
uint8 ri;
const T_USBFS_LUT CYCODE *pTmp;
{
cur_ep = pEP->addr & USBFS_DIR_UNUSED;
ri = ((cur_ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT);
- ep_type = pEP->attributes & USBFS_EP_TYPE_MASK;
+ epType = pEP->attributes & USBFS_EP_TYPE_MASK;
if ((pEP->addr & USBFS_DIR_IN) != 0u)
{
/* IN Endpoint */
USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING;
- USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+ USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN;
}
else
{
/* OUT Endpoint */
USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING;
- USBFS_EP[cur_ep].epMode = (ep_type == USBFS_EP_TYPE_ISOC) ?
+ USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ?
USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT;
}
/* Change the SIE mode for the selected EP to NAK ALL */
USBFS_EP[cur_ep].buffOffset & 0xFFu);
CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ri),
USBFS_EP[cur_ep].buffOffset >> 8u);
- #endif /* End USBFS_EP_MM == USBFS__EP_DMAAUTO */
+ #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */
}
/* Get next EP element */
pEP = &pEP[1u];
* This routine returns a pointer a configuration table entry
*
* Parameters:
-* c: Configuration Index
+* confIndex: Configuration Index
*
* Return:
-* Device Descriptor pointer.
+* Device Descriptor pointer or NULL when descriptor isn't exists.
*
*******************************************************************************/
-const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 c)
+const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex)
{
/* Device Table */
/* The first entry points to the Device Descriptor,
* the rest configuration entries.
- */
- return( (const T_USBFS_LUT CYCODE *) pTmp[c + 1u].p_list );
+ * Set pointer to the first Configuration Descriptor
+ */
+ pTmp = &pTmp[1u];
+ /* For this table, c is the number of configuration descriptors */
+ if(confIndex >= pTmp->c) /* Verify that required configuration descriptor exists */
+ {
+ pTmp = (const T_USBFS_LUT CYCODE *) NULL;
+ }
+ else
+ {
+ pTmp = (const T_USBFS_LUT CYCODE *) pTmp[confIndex].p_list;
+ }
+
+ return( pTmp );
}
{
const T_USBFS_LUT CYCODE *pTmp;
+ const uint8 CYCODE *pInterfaceClass;
uint8 currentInterfacesNum;
pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u);
- currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];
- /* Third entry in the LUT starts the Interface Table pointers */
- /* The INTERFACE_CLASS table is located after all interfaces */
- pTmp = &pTmp[currentInterfacesNum + 2u];
- return( (const uint8 CYCODE *) pTmp->p_list );
+ if( pTmp != NULL )
+ {
+ currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES];
+ /* Third entry in the LUT starts the Interface Table pointers */
+ /* The INTERFACE_CLASS table is located after all interfaces */
+ pTmp = &pTmp[currentInterfacesNum + 2u];
+ pInterfaceClass = (const uint8 CYCODE *) pTmp->p_list;
+ }
+ else
+ {
+ pInterfaceClass = (const uint8 CYCODE *) NULL;
+ }
+
+ return( pInterfaceClass );
}
/*******************************************************************************
* File Name: USBFS_vnd.c
-* Version 2.60
+* Version 2.80
*
* Description:
* USB vendor request handler.
* Note:
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************
*
* Summary:
-* This routine provide users with a method to implement vendor specifc
+* This routine provide users with a method to implement vendor specific
* requests.
*
* To implement vendor specific requests, add your code in this function to
USBFS_currentTD.pData = (volatile uint8 *)&USBFS_MSOS_CONFIGURATION_DESCR[0u];
USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u];
requestHandled = USBFS_InitControlRead();
- #endif /* End USBFS_ENABLE_MSOS_STRING */
+ #endif /* USBFS_ENABLE_MSOS_STRING */
break;
default:
break;
*/
EXTERN(Reset)
-/* Bring in the interrupt routines & vector */
+/* Bring in interrupt routines & vector */
EXTERN(main)
-/* Bring in the meta data */
+/* Bring in meta data */
EXTERN(cy_meta_loader cy_bootloader cy_meta_loadable cy_meta_bootloader)
EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata)
/* Make sure we pulled in some reset code. */
ASSERT (. != __cy_reset, "No reset code");
- /* Place the DMA initialization before text to ensure it gets placed in first 64K of flash */
+ /* Place DMA initialization before text to ensure it gets placed in first 64K of flash */
*(.dma_init)
ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash");
/*******************************************************************************
* File Name: core_cm3_psoc5.h
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides important type information for the PSoC5. This includes types
* System Reference Guide provided with PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************************
* File Name: cyPm.c
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides an API for the power management.
* System Reference Guide provided with PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
/*******************************************************************
-* Place your includes, defines and code here. Do not use merge
-* region below unless any component datasheet suggest to do so.
+* Place your includes, defines, and code here. Do not use the merge
+* region below unless any component datasheet suggests doing so.
*******************************************************************/
/* `#START CY_PM_HEADER_INCLUDE` */
*
* Summary:
* This function is called in preparation for entering sleep or hibernate low
-* power modes. Saves all state of the clocking system that does not persist
-* during sleep/hibernate or that needs to be altered in preparation for
+* power modes. Saves all the states of the clocking system that do not persist
+* during sleep/hibernate or that need to be altered in preparation for
* sleep/hibernate. Shutdowns all the digital and analog clock dividers for the
* active power mode configuration.
*
cyPmClockBackup.imo2x = CY_PM_DISABLED;
}
+ /* Master clock - save source */
+ cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK;
+
+ /* Switch Master clock's source from PLL's output to PLL's source */
+ if(CY_MASTER_SOURCE_PLL == cyPmClockBackup.masterClkSrc)
+ {
+ switch (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_PLL_SRC_MASK)
+ {
+ case CY_PM_CLKDIST_PLL_SRC_IMO:
+ CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO);
+ break;
+
+ case CY_PM_CLKDIST_PLL_SRC_XTAL:
+ CyMasterClk_SetSource(CY_MASTER_SOURCE_XTAL);
+ break;
+
+ case CY_PM_CLKDIST_PLL_SRC_DSI:
+ CyMasterClk_SetSource(CY_MASTER_SOURCE_DSI);
+ break;
+
+ default:
+ CYASSERT(0u != 0u);
+ break;
+ }
+ }
+
+ /* PLL - check enable state, disable if needed */
+ if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE))
+ {
+ /* PLL is enabled - save state and disable */
+ cyPmClockBackup.pllEnableState = CY_PM_ENABLED;
+ CyPLL_OUT_Stop();
+ }
+ else
+ {
+ /* PLL is disabled - save state */
+ cyPmClockBackup.pllEnableState = CY_PM_DISABLED;
+ }
+
/* IMO - set appropriate frequency for LPM */
CyIMO_SetFreq(CY_PM_IMO_FREQ_LPM);
/* IMO - save disabled state */
cyPmClockBackup.imoEnable = CY_PM_DISABLED;
- /* IMO - enable */
+ /* Enable the IMO. Use software delay instead of the FTW-based inside */
CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE);
+
+ /* Settling time of the IMO is of the order of less than 6us */
+ CyDelayUs(6u);
}
/* IMO - save the current IMOCLK source and set to IMO if not yet */
cyPmClockBackup.imoClkSrc =
(0u == (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO2X_SRC)) ? CY_IMO_SOURCE_DSI : CY_IMO_SOURCE_XTAL;
- /* IMO - set IMOCLK source to MHz OSC */
+ /* IMO - set IMOCLK source to IMO */
CyIMO_SetSource(CY_IMO_SOURCE_IMO);
}
else
if(CY_PM_DIV_BY_ONE != cyPmClockBackup.clkSyncDiv)
{
CyMasterClk_SetDivider(CY_PM_DIV_BY_ONE);
- } /* Need to change nothing if master clock divider is 1 */
-
- /* Master clock - save current source */
- cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK;
+ } /* No change if master clock divider is 1 */
/* Master clock source - set it to IMO if not yet. */
if(CY_MASTER_SOURCE_IMO != cyPmClockBackup.masterClkSrc)
{
CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO);
- } /* Need to change nothing if master clock source is IMO */
+ } /* No change if master clock source is IMO */
/* Bus clock - save divider and set it, if needed, to divide-by-one */
cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u);
CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE);
} /* Do nothing if saved and actual values are equal */
- /* Set number of wait cycles for the flash according CPU frequency in MHz */
+ /* Set number of wait cycles for flash according to CPU frequency in MHz */
CyFlash_SetWaitCycles((uint8)CY_PM_GET_CPU_FREQ_MHZ);
- /* PLL - check enable state, disable if needed */
- if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE))
- {
- /* PLL is enabled - save state and disable */
- cyPmClockBackup.pllEnableState = CY_PM_ENABLED;
- CyPLL_OUT_Stop();
- }
- else
- {
- /* PLL is disabled - save state */
- cyPmClockBackup.pllEnableState = CY_PM_DISABLED;
- }
-
/* MHz ECO - check enable state and disable if needed */
if(0u != (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_ENABLE))
{
/***************************************************************************
- * Save enable state of delay between the system bus clock and each of the
- * 4 individual analog clocks. This bit non-retention and it's value should
+ * Save the enable state of delay between the system bus clock and each of the
+ * 4 individual analog clocks. This bit non-retention and its value should
* be restored on wakeup.
***************************************************************************/
if(0u != (CY_PM_CLKDIST_DELAY_REG & CY_PM_CLKDIST_DELAY_EN))
*
* PSoC 3 and PSoC 5LP:
* The merge region could be used to process state when the megahertz crystal is
-* not ready after the hold-off timeout.
+* not ready after a hold-off timeout.
*
* PSoC 5:
-* The 130 ms is given for the megahertz crystal to stabilize. It's readiness is
-* not verified after the hold-off timeout.
+* The 130 ms is given for the megahertz crystal to stabilize. Its readiness is
+* not verified after a hold-off timeout.
*
* Parameters:
* None
CY_IMO_FREQ_12MHZ, CY_IMO_FREQ_6MHZ, CY_IMO_FREQ_24MHZ, CY_IMO_FREQ_3MHZ,
CY_IMO_FREQ_48MHZ, 5u, 6u};
- /* Restore enable state of delay between the system bus clock and ACLKs. */
+ /* Restore enable state of delay between system bus clock and ACLKs. */
if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay)
{
- /* Delay for both the bandgap and the delay line to settle out */
+ /* Delay for both bandgap and delay line to settle out */
CyDelayCycles((uint32)(CY_PM_CLK_DELAY_BANDGAP_SETTLE_US + CY_PM_CLK_DELAY_BIAS_SETTLE_US) *
CY_PM_GET_CPU_FREQ_MHZ);
if(CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState)
{
/***********************************************************************
- * Enabling XMHZ XTAL. The actual CyXTAL_Start() with non zero wait
+ * Enabling XMHZ XTAL. The actual CyXTAL_Start() with a non zero wait
* period uses FTW for period measurement. This could cause a problem
* if CTW/FTW is used as a wake up time in the low power modes APIs.
* So, the XTAL wait procedure is implemented with a software delay.
{
/*******************************************************************
* Process the situation when megahertz crystal is not ready.
- * Time to stabialize value is crystal specific.
+ * Time to stabilize the value is crystal specific.
*******************************************************************/
/* `#START_MHZ_ECO_TIMEOUT` */
} /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */
- /* Temprorary set the maximum flash wait cycles */
+ /* Temprorary set maximum flash wait cycles */
CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES);
- /* The XTAL and DSI clocks are ready to be source for Master clock. */
+ /* XTAL and DSI clocks are ready to be source for Master clock. */
if((CY_PM_MASTER_CLK_SRC_XTAL == cyPmClockBackup.masterClkSrc) ||
(CY_PM_MASTER_CLK_SRC_DSI == cyPmClockBackup.masterClkSrc))
{
CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE);
}
- /* IMO - restore disable state if needed */
- if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) &&
- (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)))
- {
- CyIMO_Stop();
- }
-
/* IMO - restore IMOCLK source */
CyIMO_SetSource(cyPmClockBackup.imoClkSrc);
cyPmClockBackup.clkImoSrc;
}
+
/* PLL restore state */
if(CY_PM_ENABLED == cyPmClockBackup.pllEnableState)
{
* as a wakeup time in the low power modes APIs. To omit this issue PLL
* wait procedure is implemented with a software delay.
***********************************************************************/
+ status = CYRET_TIMEOUT;
/* Enable PLL */
(void) CyPLL_OUT_Start(CY_PM_PLL_OUT_NO_WAIT);
- /* Make a 250 us delay */
- CyDelayCycles((uint32)CY_PM_WAIT_250_US * CY_PM_GET_CPU_FREQ_MHZ);
+ /* Read to clear lock status after delay */
+ CyDelayUs((uint32)80u);
+ (void) CY_PM_FASTCLK_PLL_SR_REG;
+
+ /* It should take 250 us lock: 251-80 = 171 */
+ for(i = 171u; i > 0u; i--)
+ {
+ CyDelayUs((uint32)1u);
+
+ /* Accept PLL is OK after two consecutive polls indicate PLL lock */
+ if((0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED)) &&
+ (0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED)))
+ {
+ status = CYRET_SUCCESS;
+ break;
+ }
+ }
+
+ if(CYRET_TIMEOUT == status)
+ {
+ /*******************************************************************
+ * Process the situation when PLL is not ready.
+ *******************************************************************/
+ /* `#START_PLL_TIMEOUT` */
+
+ /* `#END` */
+ }
} /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */
CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc);
}
+ /* IMO - disable if it was originally disabled */
+ if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) &&
+ (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)))
+ {
+ CyIMO_Stop();
+ }
+
/* Bus clock - restore divider, if needed */
clkBusDivTmp = (uint16) ((uint16)CY_PM_CLK_BUS_MSB_DIV_REG << 8u);
clkBusDivTmp |= CY_PM_CLK_BUS_LSB_DIV_REG;
* Sleep Timer component and one second interval should be configured with the
* RTC component.
*
-* The wakeup behavior depends on wakeupSource parameter in the following
+* The wakeup behavior depends on the wakeupSource parameter in the following
* manner: upon function execution the device will be switched from Active to
* Alternate Active mode and then the CPU will be halted. When an enabled wakeup
* event occurs the device will return to Active mode. Similarly when an
For PSoC 3 silicon the valid range of values is 1 to 256.
*
* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if
-* a wakeupTime has been specified the associated timer will be
+* a wakeupTime has been specified, the associated timer will be
* included as a wakeup source.
*
* Define Source
* *Note : FTW and HVI/LVI wakeup signals are in the same mask bit.
* **Note: CTW and One PPS wakeup signals are in the same mask bit.
*
-* When specifying a Comparator as the wakeupSource an instance specific define
-* should be used that will track with the specific comparator that the instance
-* is placed into. As an example, for a Comparator instance named MyComp the
+* When specifying a Comparator as the wakeupSource, an instance specific define
+* that will track with the specific comparator that the instance
+* is placed into should be used. As an example, for a Comparator instance named MyComp the
* value to OR into the mask is: MyComp_ctComp__CMP_MASK.
*
* When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus()
-* function must be called upon wakeup with corresponding parameter. Please
+* function must be called upon wakeup with a corresponding parameter. Please
* refer to the CyPmReadStatus() API in the System Reference Guide for more
* information.
*
* If a wakeupTime other than NONE is specified, then upon exit the state of the
* specified timer will be left as specified by wakeupTime with the timer
* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is
-* used as wakeup time) or ILO 100 KHz (if FTW timer is used as wakeup time)
+* used as wakeup time) or ILO 100 KHz (if the FTW timer is used as wakeup time)
* will be left started.
*
*******************************************************************************/
{
CyPmFtwSetInterval(PM_ALT_ACT_FTW_INTERVAL(wakeupTime));
- /* Include associated timer to the wakeupSource */
+ /* Include associated timer to wakeupSource */
wakeupSource |= PM_ALT_ACT_SRC_FTW;
}
/* Save current CTW configuration and set new one */
CyPmCtwSetInterval((uint8)(wakeupTime - 1u));
- /* Include associated timer to the wakeupSource */
+ /* Include associated timer to wakeupSource */
wakeupSource |= PM_ALT_ACT_SRC_CTW;
}
/* Save current 1PPS configuration and set new one */
CyPmOppsSet();
- /* Include associated timer to the wakeupSource */
+ /* Include associated timer to wakeupSource */
wakeupSource |= PM_ALT_ACT_SRC_ONE_PPS;
}
* Puts the part into the Sleep state.
*
* Note Before calling this function, you must manually configure the power
-* mode of the source clocks for the timer that is used as wakeup timer.
+* mode of the source clocks for the timer that is used as the wakeup timer.
*
* Note Before calling this function, you must prepare clock tree configuration
* for the low power mode by calling CyPmSaveClocks(). And restore clock
* PSoC 3:
* Before switching to Sleep, if a wakeupTime other than NONE is specified,
* then the appropriate timer state is configured as specified with the
-* interrupt for that timer disabled. The wakeup source will be the combination
+* interrupt for that timer disabled. The wakeup source will be a combination
* of the values specified in the wakeupSource and any timer specified in the
* wakeupTime argument. Once the wakeup condition is satisfied, then all saved
* state is restored and the function returns in the Active state.
* The wakeupTime parameter is not used and the only NONE can be specified.
* The wakeup time must be configured with the component, SleepTimer for CTW
* intervals and RTC for 1PPS interval. The component must be configured to
-* generate an interrrupt.
+* generate interrupt.
*
* Parameters:
* wakeupTime: Specifies a timer wakeup source and the frequency of that
* detect (power supply supervising capabilities) are required in a design
* during sleep, use the Central Time Wheel (CTW) to periodically wake the
* device, perform software buzz, and refresh the supervisory services. If LVI,
-* HVI, or Brown Out is not required, then use of the CTW is not required.
+* HVI, or Brown Out is not required, then CTW is not required.
* Refer to the device errata for more information.
*
*******************************************************************************/
/***********************************************************************
* PSoC3 < TO6:
- * - Hardware buzz must be disabled before sleep mode entry.
+ * - Hardware buzz must be disabled before the sleep mode entry.
* - Voltage supervision (HVI/LVI) requires hardware buzz, so they must
- * be aslo disabled.
+ * be also disabled.
*
* PSoC3 >= TO6:
- * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware buzz must be
- * enabled before sleep mode entry and restored on wakeup.
+ * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware
+ * buzz must be enabled before the sleep mode entry and restored on
+ * the wakeup.
***********************************************************************/
#if(CY_PSOC3)
/*******************************************************************************
- * For ARM-based devices, an interrupt is required for the CPU to wake up. The
+ * For ARM-based devices,interrupt is required for the CPU to wake up. The
* Power Management implementation assumes that wakeup time is configured with a
- * separate component (component-based wakeup time configuration) for an
+ * separate component (component-based wakeup time configuration) for
* interrupt to be issued on terminal count. For more information, refer to the
* Wakeup Time Configuration section of System Reference Guide.
*******************************************************************************/
/* CTW - save current and set new configuration */
if((wakeupTime >= PM_SLEEP_TIME_CTW_2MS) && (wakeupTime <= PM_SLEEP_TIME_CTW_4096MS))
{
- /* Save current and set new configuration of the CTW */
+ /* Save current and set new configuration of CTW */
CyPmCtwSetInterval((uint8)(wakeupTime - 1u));
- /* Include associated timer to the wakeupSource */
+ /* Include associated timer to wakeupSource */
wakeupSource |= PM_SLEEP_SRC_CTW;
}
/* Save current and set new configuration of the 1PPS */
CyPmOppsSet();
- /* Include associated timer to the wakeupSource */
+ /* Include associated timer to wakeupSource */
wakeupSource |= PM_SLEEP_SRC_ONE_PPS;
}
/*******************************************************************
- * Do not use merge region below unless any component datasheet
- * suggest to do so.
+ * Do not use the merge region below unless any component datasheet
+ * suggests doing so.
*******************************************************************/
/* `#START CY_PM_JUST_BEFORE_SLEEP` */
CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK));
}
- /* Switch to the Sleep mode */
+ /* Switch to Sleep mode */
CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_SLEEP);
/* Recommended readback. */
(void) CY_PM_MODE_CSR_REG;
- /* Two recommended NOPs to get into the mode. */
+ /* Two recommended NOPs to get into mode. */
CY_NOP;
CY_NOP;
* PSoC 3 and PSoC 5LP:
* Before switching to Hibernate, the current status of the PICU wakeup source
* bit is saved and then set. This configures the device to wake up from the
-* PICU. Make sure you have at least one pin configured to generate a PICU
+* PICU. Make sure you have at least one pin configured to generate PICU
* interrupt. For pin Px.y, the register "PICU_INTTYPE_PICUx_INTTYPEy" controls
* the PICU behavior. In the TRM, this register is "PICU[0..15]_INTTYPE[0..7]."
* In the Pins component datasheet, this register is referred to as the IRQ
* requirement begins when the device wakes up. There is no hardware check that
* this requirement is met. The specified delay should be done on ISR entry.
*
-* After wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is
+* After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is
* instance name of the Pins component) function must be called to clear the
-* latched pin events to allow proper Hibernate mode entry andd to enable
+* latched pin events to allow the proper Hibernate mode entry and to enable
* detection of future events.
*
* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to
* measure Hibernate/Sleep regulator settling time after a reset. The holdoff
-* delay is measured using rising edges of the 1 kHz ILO.
+* delay is measured using the rising edges of the 1 kHz ILO.
*
*******************************************************************************/
void CyPmHibernate(void)
/***********************************************************************
* The Hibernate/Sleep regulator has a settling time after a reset.
- * During this time, the system ignores requests to enter Sleep and
- * Hibernate modes. The holdoff delay is measured using rising edges of
+ * During this time, the system ignores requests to enter the Sleep and
+ * Hibernate modes. The holdoff delay is measured using the rising edges of
* the 1 kHz ILO.
***********************************************************************/
if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q))
/* Recommended readback. */
(void) CY_PM_MODE_CSR_REG;
- /* Two recommended NOPs to get into the mode. */
+ /* Two recommended NOPs to get into mode. */
CY_NOP;
CY_NOP;
/* Enter critical section */
interruptState = CyEnterCriticalSection();
- /* Save value of the register, copy it and clear desired bit */
+ /* Save value of register, copy it and clear desired bit */
interruptStatus |= CY_PM_INT_SR_REG;
tmpStatus = interruptStatus;
interruptStatus &= ((uint8)(~mask));
if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP))
{
/***********************************************************************
- * If I2C backup regulator is enabled, all the fixed-function registers
- * store their values while device is in low power mode, otherwise their
+ * If the I2C backup regulator is enabled, all the fixed-function registers
+ * store their values while the device is in the low power mode, otherwise their
* configuration is lost. The I2C API makes a decision to restore or not
* to restore I2C registers based on this. If this regulator will be
- * disabled and then enabled, I2C API will suppose that I2C block
+ * disabled and then enabled, I2C API will suppose that the I2C block
* registers preserved their values, while this is not true. So, the
* backup regulator is disabled. The I2C sleep APIs is responsible for
* restoration.
/***************************************************************************
- * Save and set power mode wakeup trim registers
+ * Save and set the power mode wakeup trim registers
***************************************************************************/
cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG;
cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG;
********************************************************************************
*
* Summary:
-* Restore device for proper Hibernate mode exit:
-* - Restore LVI/HVI configuration - call CyPmHviLviRestore()
+* Restores the device for the proper Hibernate mode exit:
+* - Restores LVI/HVI configuration - calsl CyPmHviLviRestore()
* - CyPmHibSlpSaveRestore() function is called
-* - Restores ILO power down mode state and enable it
-* - Restores state of 1 kHz and 100 kHz ILO and disable them
-* - Restores sleep regulator settings
+* - Restores ILO power down mode state and enables it
+* - Restores the state of 1 kHz and 100 kHz ILO and disables them
+* - Restores the sleep regulator settings
*
* Parameters:
* None
/***************************************************************************
- * Restore power mode wakeup trim registers
+ * Restore the power mode wakeup trim registers
***************************************************************************/
CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0;
CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1;
********************************************************************************
*
* Summary:
-* Performs CTW configuration:
-* - Disables CTW interrupt
+* Performs the CTW configuration:
+* - Disables the CTW interrupt
* - Enables 1 kHz ILO
-* - Sets new CTW interval
+* - Sets a new CTW interval
*
* Parameters:
* ctwInterval: the CTW interval to be set.
/* Set CTW interval if needed */
if(CY_PM_TW_CFG1_REG != ctwInterval)
{
- /* Set the new CTW interval. Could be changed if CTW is disabled */
+ /* Set new CTW interval. Could be changed if CTW is disabled */
CY_PM_TW_CFG1_REG = ctwInterval;
} /* Required interval is already set */
- /* Enable the CTW */
+ /* Enable CTW */
CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN;
}
}
* Summary:
* Performs 1PPS configuration:
* - Starts 32 KHz XTAL
-* - Disables 1PPS interupts
+* - Disables 1PPS interrupts
* - Enables 1PPS
*
* Parameters:
********************************************************************************
*
* Summary:
-* Performs FTW configuration:
-* - Disables FTW interrupt
+* Performs the FTW configuration:
+* - Disables the FTW interrupt
* - Enables 100 kHz ILO
-* - Sets new FTW interval.
+* - Sets a new FTW interval.
*
* Parameters:
* ftwInterval - FTW counter interval.
* None
*
* Side Effects:
-* Enables ILO 100 KHz clock and leaves it enabled.
+* Enables the ILO 100 KHz clock and leaves it enabled.
*
*******************************************************************************/
void CyPmFtwSetInterval(uint8 ftwInterval)
/* Enable 100kHz ILO */
CyILO_Start100K();
- /* Iterval could be set only while FTW is disabled */
+ /* Interval could be set only while FTW is disabled */
if(0u != (CY_PM_TW_CFG2_REG & CY_PM_FTW_EN))
{
/* Disable FTW, set new FTW interval if needed and enable it again */
if(CY_PM_TW_CFG0_REG != ftwInterval)
{
- /* Disable the CTW, set new CTW interval and enable it again */
+ /* Disable CTW, set new CTW interval and enable it again */
CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_EN));
CY_PM_TW_CFG0_REG = ftwInterval;
CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN;
/* Set new FTW counter interval if needed. FTW is disabled. */
if(CY_PM_TW_CFG0_REG != ftwInterval)
{
- /* Set the new CTW interval. Could be changed if CTW is disabled */
+ /* Set new CTW interval. Could be changed if CTW is disabled */
CY_PM_TW_CFG0_REG = ftwInterval;
} /* Required interval is already set */
- /* Enable the FTW */
+ /* Enable FTW */
CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN;
}
}
********************************************************************************
*
* Summary:
-* This API is used for preparing device for Sleep and Hibernate low power
+* This API is used for preparing the device for the Sleep and Hibernate low power
* modes entry:
-* - Saves COMP, VIDAC, DSM and SAR routing connections (PSoC 5)
-* - Saves SC/CT routing connections (PSoC 3/5/5LP)
-* - Disables Serial Wire Viewer (SWV) (PSoC 3)
-* - Save boost reference selection and set it to internal
+* - Saves the COMP, VIDAC, DSM, and SAR routing connections (PSoC 5)
+* - Saves the SC/CT routing connections (PSoC 3/5/5LP)
+* - Disables the Serial Wire Viewer (SWV) (PSoC 3)
+* - Saves the boost reference selection and sets it to internal
*
* Parameters:
* None
********************************************************************************
*
* Summary:
-* This API is used for restoring device configurations after wakeup from Sleep
+* This API is used for restoring the device configurations after wakeup from the Sleep
* and Hibernate low power modes:
-* - Restores SC/CT routing connections
-* - Restores enable state of Serial Wire Viewer (SWV) (PSoC 3)
-* - Restore boost reference selection
+* - Restores the SC/CT routing connections
+* - Restores the enable state of the Serial Wire Viewer (SWV) (PSoC 3)
+* - Restores the boost reference selection
*
* Parameters:
* None
cyPmBackup.lvidEn = CY_PM_ENABLED;
cyPmBackup.lvidTrip = CY_VD_LVI_TRIP_REG & CY_VD_LVI_TRIP_LVID_MASK;
- /* Save state of reset device at a specified Vddd threshold */
+ /* Save state of reset device at specified Vddd threshold */
cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \
CY_PM_DISABLED : CY_PM_ENABLED;
cyPmBackup.lviaEn = CY_PM_ENABLED;
cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u;
- /* Save state of reset device at a specified Vdda threshold */
+ /* Save state of reset device at specified Vdda threshold */
cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \
CY_PM_DISABLED : CY_PM_ENABLED;
********************************************************************************
*
* Summary:
-* Restores analog and digital LVI and HVI configuration.
+* Restores the analog and digital LVI and HVI configuration.
*
* Parameters:
* None
/*******************************************************************************
* File Name: cyPm.h
-* Version 4.0
+* Version 4.20
*
* Description:
* Provides the function definitions for the power management API.
* System Reference Guide provided with PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#if(CY_PSOC3)
- /* Wake up time for the Sleep mode */
+ /* Wake up time for Sleep mode */
#define PM_SLEEP_TIME_ONE_PPS (0x01u)
#define PM_SLEEP_TIME_CTW_2MS (0x02u)
#define PM_SLEEP_TIME_CTW_4MS (0x03u)
/* Difference between parameter's value and register's one */
#define CY_PM_FTW_INTERVAL_SHIFT (0x000Eu)
- /* Wake up time for the Alternate Active mode */
+ /* Wake up time for Alternate Active mode */
#define PM_ALT_ACT_TIME_ONE_PPS (0x0001u)
#define PM_ALT_ACT_TIME_CTW_2MS (0x0002u)
#define PM_ALT_ACT_TIME_CTW_4MS (0x0003u)
#endif /* (CY_PSOC3) */
-/* Wake up sources for the Sleep mode */
+/* Wake up sources for Sleep mode */
#define PM_SLEEP_SRC_COMPARATOR0 (0x0001u)
#define PM_SLEEP_SRC_COMPARATOR1 (0x0002u)
#define PM_SLEEP_SRC_COMPARATOR2 (0x0004u)
#define PM_SLEEP_SRC_ONE_PPS (0x0800u)
#define PM_SLEEP_SRC_LCD (0x1000u)
-/* Wake up sources for the Alternate Active mode */
+/* Wake up sources for Alternate Active mode */
#define PM_ALT_ACT_SRC_COMPARATOR0 (0x0001u)
#define PM_ALT_ACT_SRC_COMPARATOR1 (0x0002u)
#define PM_ALT_ACT_SRC_COMPARATOR2 (0x0004u)
#define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (5u)
-/* Delay line bandgap current settling time starting from a wakeup event */
+/* Delay line bandgap current settling time starting from wakeup event */
#define CY_PM_CLK_DELAY_BANDGAP_SETTLE_US (50u)
/* Delay line internal bias settling */
#if(CY_PSOC5)
- /* The CPU clock is directly derived from bus clock */
+ /* CPU clock is directly derived from bus clock */
#define CY_PM_GET_CPU_FREQ_MHZ (cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK])
#endif /* (CY_PSOC5) */
/*******************************************************************************
* The low power mode entry is different for PSoC 3 and PSoC 5 devices. The low
* power modes in PSoC 5 devices are invoked by Wait-For-Interrupt (WFI)
-* instruction. The ARM compilers has __wfi() instristic that inserts a WFI
+* instruction. The ARM compilers has __wfi() intrinsic that inserts a WFI
* instruction into the instruction stream generated by the compiler. The GCC
* compiler has to execute assembly language instruction.
*******************************************************************************/
/*******************************************************************************
* This macro defines the IMO frequency that will be set by CyPmSaveClocks()
* function based on Enable Fast IMO during Startup option from the DWR file.
-* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering
+* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering the
* low power mode and restore IMO back to the value set by CyPmSaveClocks()
* immediately on wakeup.
*******************************************************************************/
/* CyPmSaveClocks()/CyPmRestoreClocks() */
uint8 enClkA; /* Analog clocks enable */
uint8 enClkD; /* Digital clocks enable */
- uint8 masterClkSrc; /* The Master clock source */
+ uint8 masterClkSrc; /* Master clock source */
uint8 imoFreq; /* IMO frequency (reg's value) */
uint8 imoUsbClk; /* IMO USB CLK (reg's value) */
uint8 flashWaitCycles; /* Flash wait cycles */
uint8 clkImoSrc;
uint8 imo2x; /* IMO doubler enable state */
uint8 clkSyncDiv; /* Master clk divider */
- uint16 clkBusDiv; /* The clk_bus divider */
+ uint16 clkBusDiv; /* clk_bus divider */
uint8 pllEnableState; /* PLL enable state */
uint8 xmhzEnableState; /* XM HZ enable state */
uint8 clkDistDelay; /* Delay for clk_bus and ACLKs */
#define CY_PM_BOOST_CR2_REG (* (reg8 *) CYREG_BOOST_CR2 )
#define CY_PM_BOOST_CR2_PTR ( (reg8 *) CYREG_BOOST_CR2 )
+#if(CY_PSOC3)
+
+ /* Interrrupt Controller Configuration and Status Register */
+ #define CY_PM_INTC_CSR_EN_REG (* (reg8 *) CYREG_INTC_CSR_EN )
+ #define CY_PM_INTC_CSR_EN_PTR ( (reg8 *) CYREG_INTC_CSR_EN )
+
+#endif /* (CY_PSOC3) */
+
/***************************************
* Register Constants
#define CY_PM_CLKDIST_IMO_OUT_IMO (0x00u)
#define CY_PM_CLKDIST_IMO2X_SRC (0x40u)
-/* Waiting for the hibernate/sleep regulator to stabilize */
+#define CY_PM_CLKDIST_PLL_SRC_MASK (0x03u)
+#define CY_PM_CLKDIST_PLL_SRC_IMO (0x00u)
+#define CY_PM_CLKDIST_PLL_SRC_XTAL (0x01u)
+#define CY_PM_CLKDIST_PLL_SRC_DSI (0x02u)
+
+/* Waiting for hibernate/sleep regulator to stabilize */
#define CY_PM_MODE_CSR_PWRUP_PULSE_Q (0x08u)
#define CY_PM_MODE_CSR_ACTIVE (0x00u) /* Active power mode */
/* I2C regulator backup enable */
#define CY_PM_PWRSYS_CR1_I2CREG_BACKUP (0x04u)
-/* When set, prepares the system to disable the LDO-A */
+/* When set, prepares system to disable LDO-A */
#define CY_PM_PWRSYS_CR1_LDOA_ISO (0x01u)
-/* When set, disables the analog LDO regulator */
+/* When set, disables analog LDO regulator */
#define CY_PM_PWRSYS_CR1_LDOA_DIS (0x02u)
#define CY_PM_PWRSYS_WAKE_TR2_VCCD_CLK_DET (0x04u)
/* Bus Clock divider to divide-by-one */
#define CY_PM_BUS_CLK_DIV_BY_ONE (0x00u)
-/* HVI/LVI feature on the external analog and digital supply mask */
+/* HVI/LVI feature on external analog and digital supply mask */
#define CY_PM_RESET_CR1_HVI_LVI_EN_MASK (0x07u)
-/* The high-voltage-interrupt feature on the external analog supply */
+/* High-voltage-interrupt feature on external analog supply */
#define CY_PM_RESET_CR1_HVIA_EN (0x04u)
-/* The low-voltage-interrupt feature on the external analog supply */
+/* Low-voltage-interrupt feature on external analog supply */
#define CY_PM_RESET_CR1_LVIA_EN (0x02u)
-/* The low-voltage-interrupt feature on the external digital supply */
+/* Low-voltage-interrupt feature on external digital supply */
#define CY_PM_RESET_CR1_LVID_EN (0x01u)
-/* Allows the system to program delays on clk_sync_d */
+/* Allows system to program delays on clk_sync_d */
#define CY_PM_CLKDIST_DELAY_EN (0x04u)
#endif /* (CY_PSOC3) */
-/* Disable the sleep regulator and shorts vccd to vpwrsleep */
+/* Disables sleep regulator and shorts vccd to vpwrsleep */
#define CY_PM_PWRSYS_SLP_TR_BYPASS (0x10u)
/* Boost Control 2: Select external precision reference */
#endif /* (CY_PSOC5) */
+#if(CY_PSOC3)
+
+ /* Interrrupt Controller Configuration and Status Register */
+ #define CY_PM_INTC_CSR_EN_CLK (0x01u)
+
+#endif /* (CY_PSOC3) */
+
+
+/*******************************************************************************
+* Lock Status Flag. If lock is acquired this flag will stay set (regardless of
+* whether lock is subsequently lost) until it is read. Upon reading it will
+* clear. If lock is still true then the bit will simply set again. If lock
+* happens to be false when the clear on read occurs then the bit will stay
+* cleared until the next lock event.
+*******************************************************************************/
+#define CY_PM_FASTCLK_PLL_LOCKED (0x01u)
+
/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
+* The following code is OBSOLETE and must not be used starting with cy_boot 3.30
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+* #ifdef <OBSOLETED_DEFINE>
+* #undef <OBSOLETED_DEFINE>
+* #define <OBSOLETED_DEFINE> (<New Value>)
+* #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+* used in the application and their modification might lead to unexpected
+* consequences.
*******************************************************************************/
#if(CY_PSOC3)
/*******************************************************************************
* FILENAME: cydevice.h
* OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator 3.1
*
* DESCRIPTION:
* This file provides all of the address values for the entire PSoC device.
/*******************************************************************************
* FILENAME: cydevice_trm.h
*
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator 3.1
*
* DESCRIPTION:
* This file provides all of the address values for the entire PSoC device.
/*******************************************************************************
* FILENAME: cydevicegnu.inc
* OBSOLETE: Do not use this file. Use the _trm version instead.
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator 3.1
*
* DESCRIPTION:
* This file provides all of the address values for the entire PSoC device.
/*******************************************************************************
* FILENAME: cydevicegnu_trm.inc
*
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator 3.1
*
* DESCRIPTION:
* This file provides all of the address values for the entire PSoC device.
;
; FILENAME: cydeviceiar.inc
; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator 3.1
;
; DESCRIPTION:
; This file provides all of the address values for the entire PSoC device.
;
; FILENAME: cydeviceiar_trm.inc
;
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator 3.1
;
; DESCRIPTION:
; This file provides all of the address values for the entire PSoC device.
;
; FILENAME: cydevicerv.inc
; OBSOLETE: Do not use this file. Use the _trm version instead.
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator 3.1
;
; DESCRIPTION:
; This file provides all of the address values for the entire PSoC device.
;
; FILENAME: cydevicerv_trm.inc
;
-; PSoC Creator 3.0 Component Pack 7
+; PSoC Creator 3.1
;
; DESCRIPTION:
; This file provides all of the address values for the entire PSoC device.
#include <cydevice.h>
#include <cydevice_trm.h>
-/* USBFS_bus_reset */
-#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_bus_reset__INTC_MASK 0x800000u
-#define USBFS_bus_reset__INTC_NUMBER 23u
-#define USBFS_bus_reset__INTC_PRIOR_NUM 7u
-#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23
-#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* LED */
+#define LED__0__MASK 0x02u
+#define LED__0__PC CYREG_PRT0_PC1
+#define LED__0__PORT 0u
+#define LED__0__SHIFT 1
+#define LED__AG CYREG_PRT0_AG
+#define LED__AMUX CYREG_PRT0_AMUX
+#define LED__BIE CYREG_PRT0_BIE
+#define LED__BIT_MASK CYREG_PRT0_BIT_MASK
+#define LED__BYP CYREG_PRT0_BYP
+#define LED__CTL CYREG_PRT0_CTL
+#define LED__DM0 CYREG_PRT0_DM0
+#define LED__DM1 CYREG_PRT0_DM1
+#define LED__DM2 CYREG_PRT0_DM2
+#define LED__DR CYREG_PRT0_DR
+#define LED__INP_DIS CYREG_PRT0_INP_DIS
+#define LED__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
+#define LED__LCD_EN CYREG_PRT0_LCD_EN
+#define LED__MASK 0x02u
+#define LED__PORT 0u
+#define LED__PRT CYREG_PRT0_PRT
+#define LED__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
+#define LED__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
+#define LED__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
+#define LED__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
+#define LED__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
+#define LED__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
+#define LED__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
+#define LED__PS CYREG_PRT0_PS
+#define LED__SHIFT 1
+#define LED__SLW CYREG_PRT0_SLW
/* USBFS_arb_int */
#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* USBFS_bus_reset */
+#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_bus_reset__INTC_MASK 0x800000u
+#define USBFS_bus_reset__INTC_NUMBER 23u
+#define USBFS_bus_reset__INTC_PRIOR_NUM 7u
+#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23
+#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_Dm */
+#define USBFS_Dm__0__MASK 0x80u
+#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
+#define USBFS_Dm__0__PORT 15u
+#define USBFS_Dm__0__SHIFT 7
+#define USBFS_Dm__AG CYREG_PRT15_AG
+#define USBFS_Dm__AMUX CYREG_PRT15_AMUX
+#define USBFS_Dm__BIE CYREG_PRT15_BIE
+#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK
+#define USBFS_Dm__BYP CYREG_PRT15_BYP
+#define USBFS_Dm__CTL CYREG_PRT15_CTL
+#define USBFS_Dm__DM0 CYREG_PRT15_DM0
+#define USBFS_Dm__DM1 CYREG_PRT15_DM1
+#define USBFS_Dm__DM2 CYREG_PRT15_DM2
+#define USBFS_Dm__DR CYREG_PRT15_DR
+#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS
+#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN
+#define USBFS_Dm__MASK 0x80u
+#define USBFS_Dm__PORT 15u
+#define USBFS_Dm__PRT CYREG_PRT15_PRT
+#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define USBFS_Dm__PS CYREG_PRT15_PS
+#define USBFS_Dm__SHIFT 7
+#define USBFS_Dm__SLW CYREG_PRT15_SLW
+
+/* USBFS_Dp */
+#define USBFS_Dp__0__MASK 0x40u
+#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
+#define USBFS_Dp__0__PORT 15u
+#define USBFS_Dp__0__SHIFT 6
+#define USBFS_Dp__AG CYREG_PRT15_AG
+#define USBFS_Dp__AMUX CYREG_PRT15_AMUX
+#define USBFS_Dp__BIE CYREG_PRT15_BIE
+#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK
+#define USBFS_Dp__BYP CYREG_PRT15_BYP
+#define USBFS_Dp__CTL CYREG_PRT15_CTL
+#define USBFS_Dp__DM0 CYREG_PRT15_DM0
+#define USBFS_Dp__DM1 CYREG_PRT15_DM1
+#define USBFS_Dp__DM2 CYREG_PRT15_DM2
+#define USBFS_Dp__DR CYREG_PRT15_DR
+#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS
+#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT
+#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
+#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN
+#define USBFS_Dp__MASK 0x40u
+#define USBFS_Dp__PORT 15u
+#define USBFS_Dp__PRT CYREG_PRT15_PRT
+#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
+#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
+#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
+#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
+#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
+#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
+#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
+#define USBFS_Dp__PS CYREG_PRT15_PS
+#define USBFS_Dp__SHIFT 6
+#define USBFS_Dp__SLW CYREG_PRT15_SLW
+#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15
+
+/* USBFS_dp_int */
+#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_dp_int__INTC_MASK 0x1000u
+#define USBFS_dp_int__INTC_NUMBER 12u
+#define USBFS_dp_int__INTC_PRIOR_NUM 7u
+#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12
+#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_0 */
+#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_0__INTC_MASK 0x1000000u
+#define USBFS_ep_0__INTC_NUMBER 24u
+#define USBFS_ep_0__INTC_PRIOR_NUM 7u
+#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24
+#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_1 */
+#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_1__INTC_MASK 0x01u
+#define USBFS_ep_1__INTC_NUMBER 0u
+#define USBFS_ep_1__INTC_PRIOR_NUM 7u
+#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0
+#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_2 */
+#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
+#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
+#define USBFS_ep_2__INTC_MASK 0x02u
+#define USBFS_ep_2__INTC_NUMBER 1u
+#define USBFS_ep_2__INTC_PRIOR_NUM 7u
+#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1
+#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
+#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+
/* USBFS_sof_int */
#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-/* SCSI_Out_DBx */
-#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
-#define SCSI_Out_DBx__0__AMUX CYREG_PRT5_AMUX
-#define SCSI_Out_DBx__0__BIE CYREG_PRT5_BIE
-#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_Out_DBx__0__BYP CYREG_PRT5_BYP
-#define SCSI_Out_DBx__0__CTL CYREG_PRT5_CTL
-#define SCSI_Out_DBx__0__DM0 CYREG_PRT5_DM0
-#define SCSI_Out_DBx__0__DM1 CYREG_PRT5_DM1
-#define SCSI_Out_DBx__0__DM2 CYREG_PRT5_DM2
-#define SCSI_Out_DBx__0__DR CYREG_PRT5_DR
-#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_Out_DBx__0__MASK 0x02u
-#define SCSI_Out_DBx__0__PC CYREG_PRT5_PC1
-#define SCSI_Out_DBx__0__PORT 5u
-#define SCSI_Out_DBx__0__PRT CYREG_PRT5_PRT
-#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_Out_DBx__0__PS CYREG_PRT5_PS
-#define SCSI_Out_DBx__0__SHIFT 1
-#define SCSI_Out_DBx__0__SLW CYREG_PRT5_SLW
-#define SCSI_Out_DBx__1__AG CYREG_PRT5_AG
-#define SCSI_Out_DBx__1__AMUX CYREG_PRT5_AMUX
-#define SCSI_Out_DBx__1__BIE CYREG_PRT5_BIE
-#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_Out_DBx__1__BYP CYREG_PRT5_BYP
-#define SCSI_Out_DBx__1__CTL CYREG_PRT5_CTL
-#define SCSI_Out_DBx__1__DM0 CYREG_PRT5_DM0
-#define SCSI_Out_DBx__1__DM1 CYREG_PRT5_DM1
-#define SCSI_Out_DBx__1__DM2 CYREG_PRT5_DM2
-#define SCSI_Out_DBx__1__DR CYREG_PRT5_DR
-#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_Out_DBx__1__MASK 0x01u
-#define SCSI_Out_DBx__1__PC CYREG_PRT5_PC0
-#define SCSI_Out_DBx__1__PORT 5u
-#define SCSI_Out_DBx__1__PRT CYREG_PRT5_PRT
-#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_Out_DBx__1__PS CYREG_PRT5_PS
-#define SCSI_Out_DBx__1__SHIFT 0
-#define SCSI_Out_DBx__1__SLW CYREG_PRT5_SLW
-#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__2__MASK 0x20u
-#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC5
-#define SCSI_Out_DBx__2__PORT 6u
-#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__2__SHIFT 5
-#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__3__MASK 0x10u
-#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC4
-#define SCSI_Out_DBx__3__PORT 6u
-#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__3__SHIFT 4
-#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__4__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__4__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__4__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__4__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__4__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__4__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__4__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__4__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__4__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__4__MASK 0x80u
-#define SCSI_Out_DBx__4__PC CYREG_PRT2_PC7
-#define SCSI_Out_DBx__4__PORT 2u
-#define SCSI_Out_DBx__4__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__4__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__4__SHIFT 7
-#define SCSI_Out_DBx__4__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__5__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__5__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__5__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__5__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__5__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__5__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__5__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__5__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__5__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__5__MASK 0x40u
-#define SCSI_Out_DBx__5__PC CYREG_PRT2_PC6
-#define SCSI_Out_DBx__5__PORT 2u
-#define SCSI_Out_DBx__5__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__5__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__5__SHIFT 6
-#define SCSI_Out_DBx__5__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__6__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__6__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__6__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__6__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__6__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__6__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__6__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__6__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__6__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__6__MASK 0x08u
-#define SCSI_Out_DBx__6__PC CYREG_PRT2_PC3
-#define SCSI_Out_DBx__6__PORT 2u
-#define SCSI_Out_DBx__6__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__6__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__6__SHIFT 3
-#define SCSI_Out_DBx__6__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__7__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__7__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__7__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__7__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__7__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__7__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__7__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__7__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__7__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__7__MASK 0x04u
-#define SCSI_Out_DBx__7__PC CYREG_PRT2_PC2
-#define SCSI_Out_DBx__7__PORT 2u
-#define SCSI_Out_DBx__7__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__7__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__7__SHIFT 2
-#define SCSI_Out_DBx__7__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB0__AG CYREG_PRT5_AG
-#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT5_AMUX
-#define SCSI_Out_DBx__DB0__BIE CYREG_PRT5_BIE
-#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_Out_DBx__DB0__BYP CYREG_PRT5_BYP
-#define SCSI_Out_DBx__DB0__CTL CYREG_PRT5_CTL
-#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT5_DM0
-#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT5_DM1
-#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT5_DM2
-#define SCSI_Out_DBx__DB0__DR CYREG_PRT5_DR
-#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_Out_DBx__DB0__MASK 0x02u
-#define SCSI_Out_DBx__DB0__PC CYREG_PRT5_PC1
-#define SCSI_Out_DBx__DB0__PORT 5u
-#define SCSI_Out_DBx__DB0__PRT CYREG_PRT5_PRT
-#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_Out_DBx__DB0__PS CYREG_PRT5_PS
-#define SCSI_Out_DBx__DB0__SHIFT 1
-#define SCSI_Out_DBx__DB0__SLW CYREG_PRT5_SLW
-#define SCSI_Out_DBx__DB1__AG CYREG_PRT5_AG
-#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT5_AMUX
-#define SCSI_Out_DBx__DB1__BIE CYREG_PRT5_BIE
-#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT5_BIT_MASK
-#define SCSI_Out_DBx__DB1__BYP CYREG_PRT5_BYP
-#define SCSI_Out_DBx__DB1__CTL CYREG_PRT5_CTL
-#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT5_DM0
-#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT5_DM1
-#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT5_DM2
-#define SCSI_Out_DBx__DB1__DR CYREG_PRT5_DR
-#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS
-#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
-#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN
-#define SCSI_Out_DBx__DB1__MASK 0x01u
-#define SCSI_Out_DBx__DB1__PC CYREG_PRT5_PC0
-#define SCSI_Out_DBx__DB1__PORT 5u
-#define SCSI_Out_DBx__DB1__PRT CYREG_PRT5_PRT
-#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
-#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
-#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
-#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
-#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
-#define SCSI_Out_DBx__DB1__PS CYREG_PRT5_PS
-#define SCSI_Out_DBx__DB1__SHIFT 0
-#define SCSI_Out_DBx__DB1__SLW CYREG_PRT5_SLW
-#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__DB2__MASK 0x20u
-#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC5
-#define SCSI_Out_DBx__DB2__PORT 6u
-#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__DB2__SHIFT 5
-#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG
-#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX
-#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE
-#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK
-#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP
-#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL
-#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0
-#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1
-#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2
-#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR
-#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS
-#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
-#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN
-#define SCSI_Out_DBx__DB3__MASK 0x10u
-#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC4
-#define SCSI_Out_DBx__DB3__PORT 6u
-#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT
-#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
-#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
-#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
-#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
-#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
-#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS
-#define SCSI_Out_DBx__DB3__SHIFT 4
-#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW
-#define SCSI_Out_DBx__DB4__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB4__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB4__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB4__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB4__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB4__MASK 0x80u
-#define SCSI_Out_DBx__DB4__PC CYREG_PRT2_PC7
-#define SCSI_Out_DBx__DB4__PORT 2u
-#define SCSI_Out_DBx__DB4__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB4__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB4__SHIFT 7
-#define SCSI_Out_DBx__DB4__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB5__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB5__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB5__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB5__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB5__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB5__MASK 0x40u
-#define SCSI_Out_DBx__DB5__PC CYREG_PRT2_PC6
-#define SCSI_Out_DBx__DB5__PORT 2u
-#define SCSI_Out_DBx__DB5__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB5__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB5__SHIFT 6
-#define SCSI_Out_DBx__DB5__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB6__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB6__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB6__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB6__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB6__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB6__MASK 0x08u
-#define SCSI_Out_DBx__DB6__PC CYREG_PRT2_PC3
-#define SCSI_Out_DBx__DB6__PORT 2u
-#define SCSI_Out_DBx__DB6__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB6__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB6__SHIFT 3
-#define SCSI_Out_DBx__DB6__SLW CYREG_PRT2_SLW
-#define SCSI_Out_DBx__DB7__AG CYREG_PRT2_AG
-#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT2_AMUX
-#define SCSI_Out_DBx__DB7__BIE CYREG_PRT2_BIE
-#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK
-#define SCSI_Out_DBx__DB7__BYP CYREG_PRT2_BYP
-#define SCSI_Out_DBx__DB7__CTL CYREG_PRT2_CTL
-#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT2_DM0
-#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT2_DM1
-#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT2_DM2
-#define SCSI_Out_DBx__DB7__DR CYREG_PRT2_DR
-#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS
-#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
-#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN
-#define SCSI_Out_DBx__DB7__MASK 0x04u
-#define SCSI_Out_DBx__DB7__PC CYREG_PRT2_PC2
-#define SCSI_Out_DBx__DB7__PORT 2u
-#define SCSI_Out_DBx__DB7__PRT CYREG_PRT2_PRT
-#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
-#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
-#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
-#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
-#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
-#define SCSI_Out_DBx__DB7__PS CYREG_PRT2_PS
-#define SCSI_Out_DBx__DB7__SHIFT 2
-#define SCSI_Out_DBx__DB7__SLW CYREG_PRT2_SLW
-
-/* USBFS_dp_int */
-#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_dp_int__INTC_MASK 0x1000u
-#define USBFS_dp_int__INTC_NUMBER 12u
-#define USBFS_dp_int__INTC_PRIOR_NUM 7u
-#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12
-#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_0 */
-#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_0__INTC_MASK 0x1000000u
-#define USBFS_ep_0__INTC_NUMBER 24u
-#define USBFS_ep_0__INTC_PRIOR_NUM 7u
-#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24
-#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_1 */
-#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_1__INTC_MASK 0x01u
-#define USBFS_ep_1__INTC_NUMBER 0u
-#define USBFS_ep_1__INTC_PRIOR_NUM 7u
-#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0
-#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_2 */
-#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
-#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
-#define USBFS_ep_2__INTC_MASK 0x02u
-#define USBFS_ep_2__INTC_NUMBER 1u
-#define USBFS_ep_2__INTC_PRIOR_NUM 7u
-#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1
-#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0
-#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
-
-/* SD_PULLUP */
-#define SD_PULLUP__0__MASK 0x02u
-#define SD_PULLUP__0__PC CYREG_PRT3_PC1
-#define SD_PULLUP__0__PORT 3u
-#define SD_PULLUP__0__SHIFT 1
-#define SD_PULLUP__1__MASK 0x04u
-#define SD_PULLUP__1__PC CYREG_PRT3_PC2
-#define SD_PULLUP__1__PORT 3u
-#define SD_PULLUP__1__SHIFT 2
-#define SD_PULLUP__2__MASK 0x08u
-#define SD_PULLUP__2__PC CYREG_PRT3_PC3
-#define SD_PULLUP__2__PORT 3u
-#define SD_PULLUP__2__SHIFT 3
-#define SD_PULLUP__3__MASK 0x10u
-#define SD_PULLUP__3__PC CYREG_PRT3_PC4
-#define SD_PULLUP__3__PORT 3u
-#define SD_PULLUP__3__SHIFT 4
-#define SD_PULLUP__4__MASK 0x20u
-#define SD_PULLUP__4__PC CYREG_PRT3_PC5
-#define SD_PULLUP__4__PORT 3u
-#define SD_PULLUP__4__SHIFT 5
-#define SD_PULLUP__AG CYREG_PRT3_AG
-#define SD_PULLUP__AMUX CYREG_PRT3_AMUX
-#define SD_PULLUP__BIE CYREG_PRT3_BIE
-#define SD_PULLUP__BIT_MASK CYREG_PRT3_BIT_MASK
-#define SD_PULLUP__BYP CYREG_PRT3_BYP
-#define SD_PULLUP__CTL CYREG_PRT3_CTL
-#define SD_PULLUP__DM0 CYREG_PRT3_DM0
-#define SD_PULLUP__DM1 CYREG_PRT3_DM1
-#define SD_PULLUP__DM2 CYREG_PRT3_DM2
-#define SD_PULLUP__DR CYREG_PRT3_DR
-#define SD_PULLUP__INP_DIS CYREG_PRT3_INP_DIS
-#define SD_PULLUP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
-#define SD_PULLUP__LCD_EN CYREG_PRT3_LCD_EN
-#define SD_PULLUP__MASK 0x3Eu
-#define SD_PULLUP__PORT 3u
-#define SD_PULLUP__PRT CYREG_PRT3_PRT
-#define SD_PULLUP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
-#define SD_PULLUP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
-#define SD_PULLUP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
-#define SD_PULLUP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
-#define SD_PULLUP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
-#define SD_PULLUP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
-#define SD_PULLUP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
-#define SD_PULLUP__PS CYREG_PRT3_PS
-#define SD_PULLUP__SHIFT 1
-#define SD_PULLUP__SLW CYREG_PRT3_SLW
-
/* USBFS_USB */
#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG
#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG
#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES
#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB
#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG
+#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
+#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE
#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT
#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR
#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0
#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5
#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6
#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7
-#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE
-#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE
#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE
#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5
#define USBFS_USB__PM_ACT_MSK 0x01u
#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5
#define USBFS_USB__PM_STBY_MSK 0x01u
+#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
+#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0
#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1
#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0
#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0
#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1
#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0
-#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN
-#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR
#define USBFS_USB__SOF0 CYREG_USB_SOF0
#define USBFS_USB__SOF1 CYREG_USB_SOF1
+#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0
#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
-#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN
/* SCSI_Out */
#define SCSI_Out__0__AG CYREG_PRT15_AG
#define SCSI_Out__SEL__SHIFT 7
#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW
-/* USBFS_Dm */
-#define USBFS_Dm__0__MASK 0x80u
-#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1
-#define USBFS_Dm__0__PORT 15u
-#define USBFS_Dm__0__SHIFT 7
-#define USBFS_Dm__AG CYREG_PRT15_AG
-#define USBFS_Dm__AMUX CYREG_PRT15_AMUX
-#define USBFS_Dm__BIE CYREG_PRT15_BIE
-#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK
-#define USBFS_Dm__BYP CYREG_PRT15_BYP
-#define USBFS_Dm__CTL CYREG_PRT15_CTL
-#define USBFS_Dm__DM0 CYREG_PRT15_DM0
-#define USBFS_Dm__DM1 CYREG_PRT15_DM1
-#define USBFS_Dm__DM2 CYREG_PRT15_DM2
-#define USBFS_Dm__DR CYREG_PRT15_DR
-#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS
-#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN
-#define USBFS_Dm__MASK 0x80u
-#define USBFS_Dm__PORT 15u
-#define USBFS_Dm__PRT CYREG_PRT15_PRT
-#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define USBFS_Dm__PS CYREG_PRT15_PS
-#define USBFS_Dm__SHIFT 7
-#define USBFS_Dm__SLW CYREG_PRT15_SLW
-
-/* USBFS_Dp */
-#define USBFS_Dp__0__MASK 0x40u
-#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0
-#define USBFS_Dp__0__PORT 15u
-#define USBFS_Dp__0__SHIFT 6
-#define USBFS_Dp__AG CYREG_PRT15_AG
-#define USBFS_Dp__AMUX CYREG_PRT15_AMUX
-#define USBFS_Dp__BIE CYREG_PRT15_BIE
-#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK
-#define USBFS_Dp__BYP CYREG_PRT15_BYP
-#define USBFS_Dp__CTL CYREG_PRT15_CTL
-#define USBFS_Dp__DM0 CYREG_PRT15_DM0
-#define USBFS_Dp__DM1 CYREG_PRT15_DM1
-#define USBFS_Dp__DM2 CYREG_PRT15_DM2
-#define USBFS_Dp__DR CYREG_PRT15_DR
-#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS
-#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT
-#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG
-#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN
-#define USBFS_Dp__MASK 0x40u
-#define USBFS_Dp__PORT 15u
-#define USBFS_Dp__PRT CYREG_PRT15_PRT
-#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL
-#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN
-#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0
-#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1
-#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0
-#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1
-#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT
-#define USBFS_Dp__PS CYREG_PRT15_PS
-#define USBFS_Dp__SHIFT 6
-#define USBFS_Dp__SLW CYREG_PRT15_SLW
-#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15
+/* SCSI_Out_DBx */
+#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
+#define SCSI_Out_DBx__0__AMUX CYREG_PRT5_AMUX
+#define SCSI_Out_DBx__0__BIE CYREG_PRT5_BIE
+#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_Out_DBx__0__BYP CYREG_PRT5_BYP
+#define SCSI_Out_DBx__0__CTL CYREG_PRT5_CTL
+#define SCSI_Out_DBx__0__DM0 CYREG_PRT5_DM0
+#define SCSI_Out_DBx__0__DM1 CYREG_PRT5_DM1
+#define SCSI_Out_DBx__0__DM2 CYREG_PRT5_DM2
+#define SCSI_Out_DBx__0__DR CYREG_PRT5_DR
+#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_Out_DBx__0__MASK 0x02u
+#define SCSI_Out_DBx__0__PC CYREG_PRT5_PC1
+#define SCSI_Out_DBx__0__PORT 5u
+#define SCSI_Out_DBx__0__PRT CYREG_PRT5_PRT
+#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_Out_DBx__0__PS CYREG_PRT5_PS
+#define SCSI_Out_DBx__0__SHIFT 1
+#define SCSI_Out_DBx__0__SLW CYREG_PRT5_SLW
+#define SCSI_Out_DBx__1__AG CYREG_PRT5_AG
+#define SCSI_Out_DBx__1__AMUX CYREG_PRT5_AMUX
+#define SCSI_Out_DBx__1__BIE CYREG_PRT5_BIE
+#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_Out_DBx__1__BYP CYREG_PRT5_BYP
+#define SCSI_Out_DBx__1__CTL CYREG_PRT5_CTL
+#define SCSI_Out_DBx__1__DM0 CYREG_PRT5_DM0
+#define SCSI_Out_DBx__1__DM1 CYREG_PRT5_DM1
+#define SCSI_Out_DBx__1__DM2 CYREG_PRT5_DM2
+#define SCSI_Out_DBx__1__DR CYREG_PRT5_DR
+#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_Out_DBx__1__MASK 0x01u
+#define SCSI_Out_DBx__1__PC CYREG_PRT5_PC0
+#define SCSI_Out_DBx__1__PORT 5u
+#define SCSI_Out_DBx__1__PRT CYREG_PRT5_PRT
+#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_Out_DBx__1__PS CYREG_PRT5_PS
+#define SCSI_Out_DBx__1__SHIFT 0
+#define SCSI_Out_DBx__1__SLW CYREG_PRT5_SLW
+#define SCSI_Out_DBx__2__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__2__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__2__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__2__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__2__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__2__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__2__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__2__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__2__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__2__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__2__MASK 0x20u
+#define SCSI_Out_DBx__2__PC CYREG_PRT6_PC5
+#define SCSI_Out_DBx__2__PORT 6u
+#define SCSI_Out_DBx__2__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__2__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__2__SHIFT 5
+#define SCSI_Out_DBx__2__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__3__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__3__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__3__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__3__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__3__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__3__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__3__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__3__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__3__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__3__MASK 0x10u
+#define SCSI_Out_DBx__3__PC CYREG_PRT6_PC4
+#define SCSI_Out_DBx__3__PORT 6u
+#define SCSI_Out_DBx__3__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__3__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__3__SHIFT 4
+#define SCSI_Out_DBx__3__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__4__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__4__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__4__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__4__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__4__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__4__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__4__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__4__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__4__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__4__MASK 0x80u
+#define SCSI_Out_DBx__4__PC CYREG_PRT2_PC7
+#define SCSI_Out_DBx__4__PORT 2u
+#define SCSI_Out_DBx__4__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__4__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__4__SHIFT 7
+#define SCSI_Out_DBx__4__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__5__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__5__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__5__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__5__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__5__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__5__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__5__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__5__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__5__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__5__MASK 0x40u
+#define SCSI_Out_DBx__5__PC CYREG_PRT2_PC6
+#define SCSI_Out_DBx__5__PORT 2u
+#define SCSI_Out_DBx__5__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__5__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__5__SHIFT 6
+#define SCSI_Out_DBx__5__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__6__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__6__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__6__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__6__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__6__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__6__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__6__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__6__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__6__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__6__MASK 0x08u
+#define SCSI_Out_DBx__6__PC CYREG_PRT2_PC3
+#define SCSI_Out_DBx__6__PORT 2u
+#define SCSI_Out_DBx__6__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__6__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__6__SHIFT 3
+#define SCSI_Out_DBx__6__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__7__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__7__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__7__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__7__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__7__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__7__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__7__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__7__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__7__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__7__MASK 0x04u
+#define SCSI_Out_DBx__7__PC CYREG_PRT2_PC2
+#define SCSI_Out_DBx__7__PORT 2u
+#define SCSI_Out_DBx__7__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__7__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__7__SHIFT 2
+#define SCSI_Out_DBx__7__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB0__AG CYREG_PRT5_AG
+#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT5_AMUX
+#define SCSI_Out_DBx__DB0__BIE CYREG_PRT5_BIE
+#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_Out_DBx__DB0__BYP CYREG_PRT5_BYP
+#define SCSI_Out_DBx__DB0__CTL CYREG_PRT5_CTL
+#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT5_DM0
+#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT5_DM1
+#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT5_DM2
+#define SCSI_Out_DBx__DB0__DR CYREG_PRT5_DR
+#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_Out_DBx__DB0__MASK 0x02u
+#define SCSI_Out_DBx__DB0__PC CYREG_PRT5_PC1
+#define SCSI_Out_DBx__DB0__PORT 5u
+#define SCSI_Out_DBx__DB0__PRT CYREG_PRT5_PRT
+#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_Out_DBx__DB0__PS CYREG_PRT5_PS
+#define SCSI_Out_DBx__DB0__SHIFT 1
+#define SCSI_Out_DBx__DB0__SLW CYREG_PRT5_SLW
+#define SCSI_Out_DBx__DB1__AG CYREG_PRT5_AG
+#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT5_AMUX
+#define SCSI_Out_DBx__DB1__BIE CYREG_PRT5_BIE
+#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT5_BIT_MASK
+#define SCSI_Out_DBx__DB1__BYP CYREG_PRT5_BYP
+#define SCSI_Out_DBx__DB1__CTL CYREG_PRT5_CTL
+#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT5_DM0
+#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT5_DM1
+#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT5_DM2
+#define SCSI_Out_DBx__DB1__DR CYREG_PRT5_DR
+#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT5_INP_DIS
+#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
+#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT5_LCD_EN
+#define SCSI_Out_DBx__DB1__MASK 0x01u
+#define SCSI_Out_DBx__DB1__PC CYREG_PRT5_PC0
+#define SCSI_Out_DBx__DB1__PORT 5u
+#define SCSI_Out_DBx__DB1__PRT CYREG_PRT5_PRT
+#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
+#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
+#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
+#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
+#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
+#define SCSI_Out_DBx__DB1__PS CYREG_PRT5_PS
+#define SCSI_Out_DBx__DB1__SHIFT 0
+#define SCSI_Out_DBx__DB1__SLW CYREG_PRT5_SLW
+#define SCSI_Out_DBx__DB2__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__DB2__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__DB2__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__DB2__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__DB2__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__DB2__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__DB2__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__DB2__MASK 0x20u
+#define SCSI_Out_DBx__DB2__PC CYREG_PRT6_PC5
+#define SCSI_Out_DBx__DB2__PORT 6u
+#define SCSI_Out_DBx__DB2__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__DB2__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__DB2__SHIFT 5
+#define SCSI_Out_DBx__DB2__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__DB3__AG CYREG_PRT6_AG
+#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT6_AMUX
+#define SCSI_Out_DBx__DB3__BIE CYREG_PRT6_BIE
+#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT6_BIT_MASK
+#define SCSI_Out_DBx__DB3__BYP CYREG_PRT6_BYP
+#define SCSI_Out_DBx__DB3__CTL CYREG_PRT6_CTL
+#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT6_DM0
+#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT6_DM1
+#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT6_DM2
+#define SCSI_Out_DBx__DB3__DR CYREG_PRT6_DR
+#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT6_INP_DIS
+#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
+#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT6_LCD_EN
+#define SCSI_Out_DBx__DB3__MASK 0x10u
+#define SCSI_Out_DBx__DB3__PC CYREG_PRT6_PC4
+#define SCSI_Out_DBx__DB3__PORT 6u
+#define SCSI_Out_DBx__DB3__PRT CYREG_PRT6_PRT
+#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
+#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
+#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
+#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
+#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
+#define SCSI_Out_DBx__DB3__PS CYREG_PRT6_PS
+#define SCSI_Out_DBx__DB3__SHIFT 4
+#define SCSI_Out_DBx__DB3__SLW CYREG_PRT6_SLW
+#define SCSI_Out_DBx__DB4__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB4__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB4__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB4__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB4__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB4__MASK 0x80u
+#define SCSI_Out_DBx__DB4__PC CYREG_PRT2_PC7
+#define SCSI_Out_DBx__DB4__PORT 2u
+#define SCSI_Out_DBx__DB4__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB4__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB4__SHIFT 7
+#define SCSI_Out_DBx__DB4__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB5__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB5__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB5__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB5__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB5__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB5__MASK 0x40u
+#define SCSI_Out_DBx__DB5__PC CYREG_PRT2_PC6
+#define SCSI_Out_DBx__DB5__PORT 2u
+#define SCSI_Out_DBx__DB5__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB5__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB5__SHIFT 6
+#define SCSI_Out_DBx__DB5__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB6__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB6__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB6__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB6__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB6__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB6__MASK 0x08u
+#define SCSI_Out_DBx__DB6__PC CYREG_PRT2_PC3
+#define SCSI_Out_DBx__DB6__PORT 2u
+#define SCSI_Out_DBx__DB6__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB6__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB6__SHIFT 3
+#define SCSI_Out_DBx__DB6__SLW CYREG_PRT2_SLW
+#define SCSI_Out_DBx__DB7__AG CYREG_PRT2_AG
+#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT2_AMUX
+#define SCSI_Out_DBx__DB7__BIE CYREG_PRT2_BIE
+#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT2_BIT_MASK
+#define SCSI_Out_DBx__DB7__BYP CYREG_PRT2_BYP
+#define SCSI_Out_DBx__DB7__CTL CYREG_PRT2_CTL
+#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT2_DM0
+#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT2_DM1
+#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT2_DM2
+#define SCSI_Out_DBx__DB7__DR CYREG_PRT2_DR
+#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT2_INP_DIS
+#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG
+#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT2_LCD_EN
+#define SCSI_Out_DBx__DB7__MASK 0x04u
+#define SCSI_Out_DBx__DB7__PC CYREG_PRT2_PC2
+#define SCSI_Out_DBx__DB7__PORT 2u
+#define SCSI_Out_DBx__DB7__PRT CYREG_PRT2_PRT
+#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL
+#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0
+#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0
+#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
+#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
+#define SCSI_Out_DBx__DB7__PS CYREG_PRT2_PS
+#define SCSI_Out_DBx__DB7__SHIFT 2
+#define SCSI_Out_DBx__DB7__SLW CYREG_PRT2_SLW
-/* LED */
-#define LED__0__MASK 0x02u
-#define LED__0__PC CYREG_PRT0_PC1
-#define LED__0__PORT 0u
-#define LED__0__SHIFT 1
-#define LED__AG CYREG_PRT0_AG
-#define LED__AMUX CYREG_PRT0_AMUX
-#define LED__BIE CYREG_PRT0_BIE
-#define LED__BIT_MASK CYREG_PRT0_BIT_MASK
-#define LED__BYP CYREG_PRT0_BYP
-#define LED__CTL CYREG_PRT0_CTL
-#define LED__DM0 CYREG_PRT0_DM0
-#define LED__DM1 CYREG_PRT0_DM1
-#define LED__DM2 CYREG_PRT0_DM2
-#define LED__DR CYREG_PRT0_DR
-#define LED__INP_DIS CYREG_PRT0_INP_DIS
-#define LED__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG
-#define LED__LCD_EN CYREG_PRT0_LCD_EN
-#define LED__MASK 0x02u
-#define LED__PORT 0u
-#define LED__PRT CYREG_PRT0_PRT
-#define LED__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL
-#define LED__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN
-#define LED__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0
-#define LED__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1
-#define LED__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0
-#define LED__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
-#define LED__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
-#define LED__PS CYREG_PRT0_PS
-#define LED__SHIFT 1
-#define LED__SLW CYREG_PRT0_SLW
+/* SD_PULLUP */
+#define SD_PULLUP__0__MASK 0x02u
+#define SD_PULLUP__0__PC CYREG_PRT3_PC1
+#define SD_PULLUP__0__PORT 3u
+#define SD_PULLUP__0__SHIFT 1
+#define SD_PULLUP__1__MASK 0x04u
+#define SD_PULLUP__1__PC CYREG_PRT3_PC2
+#define SD_PULLUP__1__PORT 3u
+#define SD_PULLUP__1__SHIFT 2
+#define SD_PULLUP__2__MASK 0x08u
+#define SD_PULLUP__2__PC CYREG_PRT3_PC3
+#define SD_PULLUP__2__PORT 3u
+#define SD_PULLUP__2__SHIFT 3
+#define SD_PULLUP__3__MASK 0x10u
+#define SD_PULLUP__3__PC CYREG_PRT3_PC4
+#define SD_PULLUP__3__PORT 3u
+#define SD_PULLUP__3__SHIFT 4
+#define SD_PULLUP__4__MASK 0x20u
+#define SD_PULLUP__4__PC CYREG_PRT3_PC5
+#define SD_PULLUP__4__PORT 3u
+#define SD_PULLUP__4__SHIFT 5
+#define SD_PULLUP__AG CYREG_PRT3_AG
+#define SD_PULLUP__AMUX CYREG_PRT3_AMUX
+#define SD_PULLUP__BIE CYREG_PRT3_BIE
+#define SD_PULLUP__BIT_MASK CYREG_PRT3_BIT_MASK
+#define SD_PULLUP__BYP CYREG_PRT3_BYP
+#define SD_PULLUP__CTL CYREG_PRT3_CTL
+#define SD_PULLUP__DM0 CYREG_PRT3_DM0
+#define SD_PULLUP__DM1 CYREG_PRT3_DM1
+#define SD_PULLUP__DM2 CYREG_PRT3_DM2
+#define SD_PULLUP__DR CYREG_PRT3_DR
+#define SD_PULLUP__INP_DIS CYREG_PRT3_INP_DIS
+#define SD_PULLUP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG
+#define SD_PULLUP__LCD_EN CYREG_PRT3_LCD_EN
+#define SD_PULLUP__MASK 0x3Eu
+#define SD_PULLUP__PORT 3u
+#define SD_PULLUP__PRT CYREG_PRT3_PRT
+#define SD_PULLUP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL
+#define SD_PULLUP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN
+#define SD_PULLUP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0
+#define SD_PULLUP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1
+#define SD_PULLUP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0
+#define SD_PULLUP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1
+#define SD_PULLUP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT
+#define SD_PULLUP__PS CYREG_PRT3_PS
+#define SD_PULLUP__SHIFT 1
+#define SD_PULLUP__SLW CYREG_PRT3_SLW
/* Miscellaneous */
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
-#define CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO 0
-#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
-#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
-#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
-#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
-#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
-#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
-#define CYDEV_CHIP_MEMBER_5B 4u
-#define CYDEV_CHIP_FAMILY_PSOC5 3u
-#define CYDEV_CHIP_DIE_PSOC5LP 4u
-#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP
-#define CYDEV_BOOTLOADER_IO_COMP_USBFS 1
#define BCLK__BUS_CLK__HZ 64000000U
#define BCLK__BUS_CLK__KHZ 64000U
#define BCLK__BUS_CLK__MHZ 64U
+#define CY_VERSION "PSoC Creator 3.1"
#define CYDEV_BOOTLOADER_APPLICATIONS 1u
#define CYDEV_BOOTLOADER_CHECKSUM_BASIC 0
#define CYDEV_BOOTLOADER_CHECKSUM_CRC 1
+#define CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO 0
+#define CyBtldr_Custom_Interface CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
+#define CYDEV_BOOTLOADER_IO_COMP_USBFS 1
+#define CyBtldr_USBFS CYDEV_BOOTLOADER_IO_COMP_USBFS
#define CYDEV_BOOTLOADER_IO_COMP CYDEV_BOOTLOADER_IO_COMP_USBFS
-#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
#define CYDEV_CHIP_DIE_LEOPARD 1u
-#define CYDEV_CHIP_DIE_PANTHER 3u
-#define CYDEV_CHIP_DIE_PSOC4A 2u
+#define CYDEV_CHIP_DIE_PANTHER 6u
+#define CYDEV_CHIP_DIE_PSOC4A 3u
+#define CYDEV_CHIP_DIE_PSOC5LP 5u
#define CYDEV_CHIP_DIE_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_PSOC3 1u
#define CYDEV_CHIP_FAMILY_PSOC4 2u
+#define CYDEV_CHIP_FAMILY_PSOC5 3u
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5
#define CYDEV_CHIP_JTAG_ID 0x2E133069u
#define CYDEV_CHIP_MEMBER_3A 1u
-#define CYDEV_CHIP_MEMBER_4A 2u
-#define CYDEV_CHIP_MEMBER_5A 3u
+#define CYDEV_CHIP_MEMBER_4A 3u
+#define CYDEV_CHIP_MEMBER_4D 2u
+#define CYDEV_CHIP_MEMBER_4F 4u
+#define CYDEV_CHIP_MEMBER_5A 6u
+#define CYDEV_CHIP_MEMBER_5B 5u
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B
+#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
+#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
+#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
+#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
+#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
+#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
+#define CYDEV_CHIP_REV_PANTHER_ES0 0u
+#define CYDEV_CHIP_REV_PANTHER_ES1 1u
+#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
+#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
+#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
+#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
+#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_3A_ES1 0u
#define CYDEV_CHIP_REVISION_3A_ES2 1u
#define CYDEV_CHIP_REVISION_3A_ES3 3u
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
#define CYDEV_CHIP_REVISION_4A_ES0 17u
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
+#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
+#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_5A_ES0 0u
#define CYDEV_CHIP_REVISION_5A_ES1 1u
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
#define CYDEV_CHIP_REVISION_5B_ES0 0u
+#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION
-#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
-#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
-#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
-#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
-#define CYDEV_CHIP_REV_PANTHER_ES0 0u
-#define CYDEV_CHIP_REV_PANTHER_ES1 1u
-#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
-#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
-#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
-#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
+#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
+#define CYDEV_CONFIG_FASTBOOT_ENABLED 1
+#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
+#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
+#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
#define CYDEV_CONFIGURATION_COMPRESSED 1
#define CYDEV_CONFIGURATION_DMA 0
#define CYDEV_CONFIGURATION_ECC 0
#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED
+#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
#define CYDEV_CONFIGURATION_MODE_DMA 2
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
-#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
-#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
-#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
+#define CYDEV_DEBUG_ENABLE_MASK 0x20u
+#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
#define CYDEV_DEBUGGING_DPS_Disable 3
#define CYDEV_DEBUGGING_DPS_JTAG_4 1
#define CYDEV_DEBUGGING_DPS_JTAG_5 0
#define CYDEV_DEBUGGING_DPS_SWD 2
+#define CYDEV_DEBUGGING_DPS_SWD_SWV 6
+#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV
#define CYDEV_DEBUGGING_ENABLE 1
#define CYDEV_DEBUGGING_XRES 0
-#define CYDEV_DEBUG_ENABLE_MASK 0x20u
-#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
#define CYDEV_DMA_CHANNELS_AVAILABLE 24u
#define CYDEV_ECC_ENABLE 0
#define CYDEV_HEAP_SIZE 0x0800
#define CYDEV_VDDIO2_MV 5000
#define CYDEV_VDDIO3 5.0
#define CYDEV_VDDIO3_MV 5000
-#define CYDEV_VIO0 5
+#define CYDEV_VIO0 5.0
#define CYDEV_VIO0_MV 5000
-#define CYDEV_VIO1 5
+#define CYDEV_VIO1 5.0
#define CYDEV_VIO1_MV 5000
-#define CYDEV_VIO2 5
+#define CYDEV_VIO2 5.0
#define CYDEV_VIO2_MV 5000
-#define CYDEV_VIO3 5
+#define CYDEV_VIO3 5.0
#define CYDEV_VIO3_MV 5000
-#define CyBtldr_Custom_Interface CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
-#define CyBtldr_USBFS CYDEV_BOOTLOADER_IO_COMP_USBFS
+#define CYIPBLOCK_ARM_CM3_VERSION 0
+#define CYIPBLOCK_P3_ANAIF_VERSION 0
+#define CYIPBLOCK_P3_CAPSENSE_VERSION 0
+#define CYIPBLOCK_P3_COMP_VERSION 0
+#define CYIPBLOCK_P3_DMA_VERSION 0
+#define CYIPBLOCK_P3_DRQ_VERSION 0
+#define CYIPBLOCK_P3_EMIF_VERSION 0
+#define CYIPBLOCK_P3_I2C_VERSION 0
+#define CYIPBLOCK_P3_LCD_VERSION 0
+#define CYIPBLOCK_P3_LPF_VERSION 0
+#define CYIPBLOCK_P3_PM_VERSION 0
+#define CYIPBLOCK_P3_TIMER_VERSION 0
+#define CYIPBLOCK_P3_USB_VERSION 0
+#define CYIPBLOCK_P3_VIDAC_VERSION 0
+#define CYIPBLOCK_P3_VREF_VERSION 0
+#define CYIPBLOCK_S8_GPIO_VERSION 0
+#define CYIPBLOCK_S8_IRQ_VERSION 0
+#define CYIPBLOCK_S8_SAR_VERSION 0
+#define CYIPBLOCK_S8_SIO_VERSION 0
+#define CYIPBLOCK_S8_UDB_VERSION 0
#define DMA_CHANNELS_USED__MASK0 0x00000000u
#define CYDEV_BOOTLOADER_ENABLE 1
/*******************************************************************************
* FILENAME: cyfitter_cfg.c
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator 3.1
*
* Description:
* This file is automatically generated by PSoC Creator with device
for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)
{
const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];
- CYMEMZERO(ms->address, (uint32)(ms->size));
+ CYMEMZERO(ms->address, (size_t)(uint32)(ms->size));
}
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/*******************************************************************************
* FILENAME: cyfitter_cfg.h
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator 3.1
*
* Description:
* This file is automatically generated by PSoC Creator.
.include "cydevicegnu.inc"
.include "cydevicegnu_trm.inc"
-/* USBFS_bus_reset */
-.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_bus_reset__INTC_MASK, 0x800000
-.set USBFS_bus_reset__INTC_NUMBER, 23
-.set USBFS_bus_reset__INTC_PRIOR_NUM, 7
-.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23
-.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* LED */
+.set LED__0__MASK, 0x02
+.set LED__0__PC, CYREG_PRT0_PC1
+.set LED__0__PORT, 0
+.set LED__0__SHIFT, 1
+.set LED__AG, CYREG_PRT0_AG
+.set LED__AMUX, CYREG_PRT0_AMUX
+.set LED__BIE, CYREG_PRT0_BIE
+.set LED__BIT_MASK, CYREG_PRT0_BIT_MASK
+.set LED__BYP, CYREG_PRT0_BYP
+.set LED__CTL, CYREG_PRT0_CTL
+.set LED__DM0, CYREG_PRT0_DM0
+.set LED__DM1, CYREG_PRT0_DM1
+.set LED__DM2, CYREG_PRT0_DM2
+.set LED__DR, CYREG_PRT0_DR
+.set LED__INP_DIS, CYREG_PRT0_INP_DIS
+.set LED__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
+.set LED__LCD_EN, CYREG_PRT0_LCD_EN
+.set LED__MASK, 0x02
+.set LED__PORT, 0
+.set LED__PRT, CYREG_PRT0_PRT
+.set LED__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
+.set LED__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
+.set LED__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
+.set LED__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
+.set LED__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
+.set LED__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
+.set LED__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
+.set LED__PS, CYREG_PRT0_PS
+.set LED__SHIFT, 1
+.set LED__SLW, CYREG_PRT0_SLW
/* USBFS_arb_int */
.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* USBFS_bus_reset */
+.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_bus_reset__INTC_MASK, 0x800000
+.set USBFS_bus_reset__INTC_NUMBER, 23
+.set USBFS_bus_reset__INTC_PRIOR_NUM, 7
+.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23
+.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_Dm */
+.set USBFS_Dm__0__MASK, 0x80
+.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1
+.set USBFS_Dm__0__PORT, 15
+.set USBFS_Dm__0__SHIFT, 7
+.set USBFS_Dm__AG, CYREG_PRT15_AG
+.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX
+.set USBFS_Dm__BIE, CYREG_PRT15_BIE
+.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set USBFS_Dm__BYP, CYREG_PRT15_BYP
+.set USBFS_Dm__CTL, CYREG_PRT15_CTL
+.set USBFS_Dm__DM0, CYREG_PRT15_DM0
+.set USBFS_Dm__DM1, CYREG_PRT15_DM1
+.set USBFS_Dm__DM2, CYREG_PRT15_DM2
+.set USBFS_Dm__DR, CYREG_PRT15_DR
+.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS
+.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN
+.set USBFS_Dm__MASK, 0x80
+.set USBFS_Dm__PORT, 15
+.set USBFS_Dm__PRT, CYREG_PRT15_PRT
+.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set USBFS_Dm__PS, CYREG_PRT15_PS
+.set USBFS_Dm__SHIFT, 7
+.set USBFS_Dm__SLW, CYREG_PRT15_SLW
+
+/* USBFS_Dp */
+.set USBFS_Dp__0__MASK, 0x40
+.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0
+.set USBFS_Dp__0__PORT, 15
+.set USBFS_Dp__0__SHIFT, 6
+.set USBFS_Dp__AG, CYREG_PRT15_AG
+.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX
+.set USBFS_Dp__BIE, CYREG_PRT15_BIE
+.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK
+.set USBFS_Dp__BYP, CYREG_PRT15_BYP
+.set USBFS_Dp__CTL, CYREG_PRT15_CTL
+.set USBFS_Dp__DM0, CYREG_PRT15_DM0
+.set USBFS_Dp__DM1, CYREG_PRT15_DM1
+.set USBFS_Dp__DM2, CYREG_PRT15_DM2
+.set USBFS_Dp__DR, CYREG_PRT15_DR
+.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS
+.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT
+.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
+.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN
+.set USBFS_Dp__MASK, 0x40
+.set USBFS_Dp__PORT, 15
+.set USBFS_Dp__PRT, CYREG_PRT15_PRT
+.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
+.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
+.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
+.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
+.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
+.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
+.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
+.set USBFS_Dp__PS, CYREG_PRT15_PS
+.set USBFS_Dp__SHIFT, 6
+.set USBFS_Dp__SLW, CYREG_PRT15_SLW
+.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15
+
+/* USBFS_dp_int */
+.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_dp_int__INTC_MASK, 0x1000
+.set USBFS_dp_int__INTC_NUMBER, 12
+.set USBFS_dp_int__INTC_PRIOR_NUM, 7
+.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12
+.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_0 */
+.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_0__INTC_MASK, 0x1000000
+.set USBFS_ep_0__INTC_NUMBER, 24
+.set USBFS_ep_0__INTC_PRIOR_NUM, 7
+.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24
+.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_1 */
+.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_1__INTC_MASK, 0x01
+.set USBFS_ep_1__INTC_NUMBER, 0
+.set USBFS_ep_1__INTC_PRIOR_NUM, 7
+.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
+.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_2 */
+.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
+.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
+.set USBFS_ep_2__INTC_MASK, 0x02
+.set USBFS_ep_2__INTC_NUMBER, 1
+.set USBFS_ep_2__INTC_PRIOR_NUM, 7
+.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
+.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
+.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+
/* USBFS_sof_int */
.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-/* SCSI_Out_DBx */
-.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
-.set SCSI_Out_DBx__0__AMUX, CYREG_PRT5_AMUX
-.set SCSI_Out_DBx__0__BIE, CYREG_PRT5_BIE
-.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_Out_DBx__0__BYP, CYREG_PRT5_BYP
-.set SCSI_Out_DBx__0__CTL, CYREG_PRT5_CTL
-.set SCSI_Out_DBx__0__DM0, CYREG_PRT5_DM0
-.set SCSI_Out_DBx__0__DM1, CYREG_PRT5_DM1
-.set SCSI_Out_DBx__0__DM2, CYREG_PRT5_DM2
-.set SCSI_Out_DBx__0__DR, CYREG_PRT5_DR
-.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_Out_DBx__0__MASK, 0x02
-.set SCSI_Out_DBx__0__PC, CYREG_PRT5_PC1
-.set SCSI_Out_DBx__0__PORT, 5
-.set SCSI_Out_DBx__0__PRT, CYREG_PRT5_PRT
-.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_Out_DBx__0__PS, CYREG_PRT5_PS
-.set SCSI_Out_DBx__0__SHIFT, 1
-.set SCSI_Out_DBx__0__SLW, CYREG_PRT5_SLW
-.set SCSI_Out_DBx__1__AG, CYREG_PRT5_AG
-.set SCSI_Out_DBx__1__AMUX, CYREG_PRT5_AMUX
-.set SCSI_Out_DBx__1__BIE, CYREG_PRT5_BIE
-.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_Out_DBx__1__BYP, CYREG_PRT5_BYP
-.set SCSI_Out_DBx__1__CTL, CYREG_PRT5_CTL
-.set SCSI_Out_DBx__1__DM0, CYREG_PRT5_DM0
-.set SCSI_Out_DBx__1__DM1, CYREG_PRT5_DM1
-.set SCSI_Out_DBx__1__DM2, CYREG_PRT5_DM2
-.set SCSI_Out_DBx__1__DR, CYREG_PRT5_DR
-.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_Out_DBx__1__MASK, 0x01
-.set SCSI_Out_DBx__1__PC, CYREG_PRT5_PC0
-.set SCSI_Out_DBx__1__PORT, 5
-.set SCSI_Out_DBx__1__PRT, CYREG_PRT5_PRT
-.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_Out_DBx__1__PS, CYREG_PRT5_PS
-.set SCSI_Out_DBx__1__SHIFT, 0
-.set SCSI_Out_DBx__1__SLW, CYREG_PRT5_SLW
-.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__2__MASK, 0x20
-.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC5
-.set SCSI_Out_DBx__2__PORT, 6
-.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__2__SHIFT, 5
-.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__3__MASK, 0x10
-.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC4
-.set SCSI_Out_DBx__3__PORT, 6
-.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__3__SHIFT, 4
-.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__4__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__4__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__4__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__4__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__4__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__4__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__4__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__4__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__4__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__4__MASK, 0x80
-.set SCSI_Out_DBx__4__PC, CYREG_PRT2_PC7
-.set SCSI_Out_DBx__4__PORT, 2
-.set SCSI_Out_DBx__4__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__4__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__4__SHIFT, 7
-.set SCSI_Out_DBx__4__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__5__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__5__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__5__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__5__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__5__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__5__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__5__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__5__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__5__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__5__MASK, 0x40
-.set SCSI_Out_DBx__5__PC, CYREG_PRT2_PC6
-.set SCSI_Out_DBx__5__PORT, 2
-.set SCSI_Out_DBx__5__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__5__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__5__SHIFT, 6
-.set SCSI_Out_DBx__5__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__6__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__6__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__6__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__6__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__6__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__6__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__6__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__6__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__6__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__6__MASK, 0x08
-.set SCSI_Out_DBx__6__PC, CYREG_PRT2_PC3
-.set SCSI_Out_DBx__6__PORT, 2
-.set SCSI_Out_DBx__6__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__6__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__6__SHIFT, 3
-.set SCSI_Out_DBx__6__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__7__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__7__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__7__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__7__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__7__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__7__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__7__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__7__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__7__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__7__MASK, 0x04
-.set SCSI_Out_DBx__7__PC, CYREG_PRT2_PC2
-.set SCSI_Out_DBx__7__PORT, 2
-.set SCSI_Out_DBx__7__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__7__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__7__SHIFT, 2
-.set SCSI_Out_DBx__7__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB0__AG, CYREG_PRT5_AG
-.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT5_AMUX
-.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT5_BIE
-.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT5_BYP
-.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT5_CTL
-.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT5_DM0
-.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT5_DM1
-.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT5_DM2
-.set SCSI_Out_DBx__DB0__DR, CYREG_PRT5_DR
-.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_Out_DBx__DB0__MASK, 0x02
-.set SCSI_Out_DBx__DB0__PC, CYREG_PRT5_PC1
-.set SCSI_Out_DBx__DB0__PORT, 5
-.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT5_PRT
-.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_Out_DBx__DB0__PS, CYREG_PRT5_PS
-.set SCSI_Out_DBx__DB0__SHIFT, 1
-.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT5_SLW
-.set SCSI_Out_DBx__DB1__AG, CYREG_PRT5_AG
-.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT5_AMUX
-.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT5_BIE
-.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT5_BIT_MASK
-.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT5_BYP
-.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT5_CTL
-.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT5_DM0
-.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT5_DM1
-.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT5_DM2
-.set SCSI_Out_DBx__DB1__DR, CYREG_PRT5_DR
-.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS
-.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
-.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN
-.set SCSI_Out_DBx__DB1__MASK, 0x01
-.set SCSI_Out_DBx__DB1__PC, CYREG_PRT5_PC0
-.set SCSI_Out_DBx__DB1__PORT, 5
-.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT5_PRT
-.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
-.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
-.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
-.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
-.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
-.set SCSI_Out_DBx__DB1__PS, CYREG_PRT5_PS
-.set SCSI_Out_DBx__DB1__SHIFT, 0
-.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT5_SLW
-.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__DB2__MASK, 0x20
-.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC5
-.set SCSI_Out_DBx__DB2__PORT, 6
-.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__DB2__SHIFT, 5
-.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG
-.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX
-.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE
-.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK
-.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP
-.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL
-.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0
-.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1
-.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2
-.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR
-.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS
-.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
-.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN
-.set SCSI_Out_DBx__DB3__MASK, 0x10
-.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC4
-.set SCSI_Out_DBx__DB3__PORT, 6
-.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT
-.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
-.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
-.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
-.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
-.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
-.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS
-.set SCSI_Out_DBx__DB3__SHIFT, 4
-.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW
-.set SCSI_Out_DBx__DB4__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB4__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB4__MASK, 0x80
-.set SCSI_Out_DBx__DB4__PC, CYREG_PRT2_PC7
-.set SCSI_Out_DBx__DB4__PORT, 2
-.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB4__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB4__SHIFT, 7
-.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB5__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB5__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB5__MASK, 0x40
-.set SCSI_Out_DBx__DB5__PC, CYREG_PRT2_PC6
-.set SCSI_Out_DBx__DB5__PORT, 2
-.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB5__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB5__SHIFT, 6
-.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB6__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB6__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB6__MASK, 0x08
-.set SCSI_Out_DBx__DB6__PC, CYREG_PRT2_PC3
-.set SCSI_Out_DBx__DB6__PORT, 2
-.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB6__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB6__SHIFT, 3
-.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT2_SLW
-.set SCSI_Out_DBx__DB7__AG, CYREG_PRT2_AG
-.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT2_AMUX
-.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT2_BIE
-.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK
-.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT2_BYP
-.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT2_CTL
-.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT2_DM0
-.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT2_DM1
-.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT2_DM2
-.set SCSI_Out_DBx__DB7__DR, CYREG_PRT2_DR
-.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS
-.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
-.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN
-.set SCSI_Out_DBx__DB7__MASK, 0x04
-.set SCSI_Out_DBx__DB7__PC, CYREG_PRT2_PC2
-.set SCSI_Out_DBx__DB7__PORT, 2
-.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT2_PRT
-.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
-.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
-.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
-.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
-.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
-.set SCSI_Out_DBx__DB7__PS, CYREG_PRT2_PS
-.set SCSI_Out_DBx__DB7__SHIFT, 2
-.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT2_SLW
-
-/* USBFS_dp_int */
-.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_dp_int__INTC_MASK, 0x1000
-.set USBFS_dp_int__INTC_NUMBER, 12
-.set USBFS_dp_int__INTC_PRIOR_NUM, 7
-.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12
-.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_0 */
-.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_0__INTC_MASK, 0x1000000
-.set USBFS_ep_0__INTC_NUMBER, 24
-.set USBFS_ep_0__INTC_PRIOR_NUM, 7
-.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24
-.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_1 */
-.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_1__INTC_MASK, 0x01
-.set USBFS_ep_1__INTC_NUMBER, 0
-.set USBFS_ep_1__INTC_PRIOR_NUM, 7
-.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
-.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_2 */
-.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
-.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
-.set USBFS_ep_2__INTC_MASK, 0x02
-.set USBFS_ep_2__INTC_NUMBER, 1
-.set USBFS_ep_2__INTC_PRIOR_NUM, 7
-.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
-.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
-.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
-
-/* SD_PULLUP */
-.set SD_PULLUP__0__MASK, 0x02
-.set SD_PULLUP__0__PC, CYREG_PRT3_PC1
-.set SD_PULLUP__0__PORT, 3
-.set SD_PULLUP__0__SHIFT, 1
-.set SD_PULLUP__1__MASK, 0x04
-.set SD_PULLUP__1__PC, CYREG_PRT3_PC2
-.set SD_PULLUP__1__PORT, 3
-.set SD_PULLUP__1__SHIFT, 2
-.set SD_PULLUP__2__MASK, 0x08
-.set SD_PULLUP__2__PC, CYREG_PRT3_PC3
-.set SD_PULLUP__2__PORT, 3
-.set SD_PULLUP__2__SHIFT, 3
-.set SD_PULLUP__3__MASK, 0x10
-.set SD_PULLUP__3__PC, CYREG_PRT3_PC4
-.set SD_PULLUP__3__PORT, 3
-.set SD_PULLUP__3__SHIFT, 4
-.set SD_PULLUP__4__MASK, 0x20
-.set SD_PULLUP__4__PC, CYREG_PRT3_PC5
-.set SD_PULLUP__4__PORT, 3
-.set SD_PULLUP__4__SHIFT, 5
-.set SD_PULLUP__AG, CYREG_PRT3_AG
-.set SD_PULLUP__AMUX, CYREG_PRT3_AMUX
-.set SD_PULLUP__BIE, CYREG_PRT3_BIE
-.set SD_PULLUP__BIT_MASK, CYREG_PRT3_BIT_MASK
-.set SD_PULLUP__BYP, CYREG_PRT3_BYP
-.set SD_PULLUP__CTL, CYREG_PRT3_CTL
-.set SD_PULLUP__DM0, CYREG_PRT3_DM0
-.set SD_PULLUP__DM1, CYREG_PRT3_DM1
-.set SD_PULLUP__DM2, CYREG_PRT3_DM2
-.set SD_PULLUP__DR, CYREG_PRT3_DR
-.set SD_PULLUP__INP_DIS, CYREG_PRT3_INP_DIS
-.set SD_PULLUP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
-.set SD_PULLUP__LCD_EN, CYREG_PRT3_LCD_EN
-.set SD_PULLUP__MASK, 0x3E
-.set SD_PULLUP__PORT, 3
-.set SD_PULLUP__PRT, CYREG_PRT3_PRT
-.set SD_PULLUP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
-.set SD_PULLUP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
-.set SD_PULLUP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
-.set SD_PULLUP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
-.set SD_PULLUP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
-.set SD_PULLUP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
-.set SD_PULLUP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
-.set SD_PULLUP__PS, CYREG_PRT3_PS
-.set SD_PULLUP__SHIFT, 1
-.set SD_PULLUP__SLW, CYREG_PRT3_SLW
-
/* USBFS_USB */
.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG
.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG
.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES
.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB
.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG
+.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE
+.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE
.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT
.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR
.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0
.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5
.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6
.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7
-.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE
-.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE
.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE
.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5
.set USBFS_USB__PM_ACT_MSK, 0x01
.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5
.set USBFS_USB__PM_STBY_MSK, 0x01
+.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN
+.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR
.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0
.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1
.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0
.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0
.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1
.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0
-.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN
-.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR
.set USBFS_USB__SOF0, CYREG_USB_SOF0
.set USBFS_USB__SOF1, CYREG_USB_SOF1
+.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN
.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0
.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
-.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN
/* SCSI_Out */
.set SCSI_Out__0__AG, CYREG_PRT15_AG
.set SCSI_Out__SEL__SHIFT, 7
.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW
-/* USBFS_Dm */
-.set USBFS_Dm__0__MASK, 0x80
-.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1
-.set USBFS_Dm__0__PORT, 15
-.set USBFS_Dm__0__SHIFT, 7
-.set USBFS_Dm__AG, CYREG_PRT15_AG
-.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX
-.set USBFS_Dm__BIE, CYREG_PRT15_BIE
-.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set USBFS_Dm__BYP, CYREG_PRT15_BYP
-.set USBFS_Dm__CTL, CYREG_PRT15_CTL
-.set USBFS_Dm__DM0, CYREG_PRT15_DM0
-.set USBFS_Dm__DM1, CYREG_PRT15_DM1
-.set USBFS_Dm__DM2, CYREG_PRT15_DM2
-.set USBFS_Dm__DR, CYREG_PRT15_DR
-.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS
-.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN
-.set USBFS_Dm__MASK, 0x80
-.set USBFS_Dm__PORT, 15
-.set USBFS_Dm__PRT, CYREG_PRT15_PRT
-.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set USBFS_Dm__PS, CYREG_PRT15_PS
-.set USBFS_Dm__SHIFT, 7
-.set USBFS_Dm__SLW, CYREG_PRT15_SLW
-
-/* USBFS_Dp */
-.set USBFS_Dp__0__MASK, 0x40
-.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0
-.set USBFS_Dp__0__PORT, 15
-.set USBFS_Dp__0__SHIFT, 6
-.set USBFS_Dp__AG, CYREG_PRT15_AG
-.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX
-.set USBFS_Dp__BIE, CYREG_PRT15_BIE
-.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK
-.set USBFS_Dp__BYP, CYREG_PRT15_BYP
-.set USBFS_Dp__CTL, CYREG_PRT15_CTL
-.set USBFS_Dp__DM0, CYREG_PRT15_DM0
-.set USBFS_Dp__DM1, CYREG_PRT15_DM1
-.set USBFS_Dp__DM2, CYREG_PRT15_DM2
-.set USBFS_Dp__DR, CYREG_PRT15_DR
-.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS
-.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT
-.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG
-.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN
-.set USBFS_Dp__MASK, 0x40
-.set USBFS_Dp__PORT, 15
-.set USBFS_Dp__PRT, CYREG_PRT15_PRT
-.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL
-.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN
-.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0
-.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1
-.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0
-.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1
-.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT
-.set USBFS_Dp__PS, CYREG_PRT15_PS
-.set USBFS_Dp__SHIFT, 6
-.set USBFS_Dp__SLW, CYREG_PRT15_SLW
-.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15
+/* SCSI_Out_DBx */
+.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
+.set SCSI_Out_DBx__0__AMUX, CYREG_PRT5_AMUX
+.set SCSI_Out_DBx__0__BIE, CYREG_PRT5_BIE
+.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_Out_DBx__0__BYP, CYREG_PRT5_BYP
+.set SCSI_Out_DBx__0__CTL, CYREG_PRT5_CTL
+.set SCSI_Out_DBx__0__DM0, CYREG_PRT5_DM0
+.set SCSI_Out_DBx__0__DM1, CYREG_PRT5_DM1
+.set SCSI_Out_DBx__0__DM2, CYREG_PRT5_DM2
+.set SCSI_Out_DBx__0__DR, CYREG_PRT5_DR
+.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_Out_DBx__0__MASK, 0x02
+.set SCSI_Out_DBx__0__PC, CYREG_PRT5_PC1
+.set SCSI_Out_DBx__0__PORT, 5
+.set SCSI_Out_DBx__0__PRT, CYREG_PRT5_PRT
+.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_Out_DBx__0__PS, CYREG_PRT5_PS
+.set SCSI_Out_DBx__0__SHIFT, 1
+.set SCSI_Out_DBx__0__SLW, CYREG_PRT5_SLW
+.set SCSI_Out_DBx__1__AG, CYREG_PRT5_AG
+.set SCSI_Out_DBx__1__AMUX, CYREG_PRT5_AMUX
+.set SCSI_Out_DBx__1__BIE, CYREG_PRT5_BIE
+.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_Out_DBx__1__BYP, CYREG_PRT5_BYP
+.set SCSI_Out_DBx__1__CTL, CYREG_PRT5_CTL
+.set SCSI_Out_DBx__1__DM0, CYREG_PRT5_DM0
+.set SCSI_Out_DBx__1__DM1, CYREG_PRT5_DM1
+.set SCSI_Out_DBx__1__DM2, CYREG_PRT5_DM2
+.set SCSI_Out_DBx__1__DR, CYREG_PRT5_DR
+.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_Out_DBx__1__MASK, 0x01
+.set SCSI_Out_DBx__1__PC, CYREG_PRT5_PC0
+.set SCSI_Out_DBx__1__PORT, 5
+.set SCSI_Out_DBx__1__PRT, CYREG_PRT5_PRT
+.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_Out_DBx__1__PS, CYREG_PRT5_PS
+.set SCSI_Out_DBx__1__SHIFT, 0
+.set SCSI_Out_DBx__1__SLW, CYREG_PRT5_SLW
+.set SCSI_Out_DBx__2__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__2__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__2__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__2__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__2__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__2__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__2__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__2__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__2__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__2__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__2__MASK, 0x20
+.set SCSI_Out_DBx__2__PC, CYREG_PRT6_PC5
+.set SCSI_Out_DBx__2__PORT, 6
+.set SCSI_Out_DBx__2__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__2__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__2__SHIFT, 5
+.set SCSI_Out_DBx__2__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__3__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__3__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__3__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__3__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__3__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__3__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__3__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__3__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__3__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__3__MASK, 0x10
+.set SCSI_Out_DBx__3__PC, CYREG_PRT6_PC4
+.set SCSI_Out_DBx__3__PORT, 6
+.set SCSI_Out_DBx__3__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__3__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__3__SHIFT, 4
+.set SCSI_Out_DBx__3__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__4__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__4__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__4__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__4__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__4__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__4__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__4__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__4__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__4__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__4__MASK, 0x80
+.set SCSI_Out_DBx__4__PC, CYREG_PRT2_PC7
+.set SCSI_Out_DBx__4__PORT, 2
+.set SCSI_Out_DBx__4__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__4__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__4__SHIFT, 7
+.set SCSI_Out_DBx__4__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__5__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__5__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__5__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__5__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__5__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__5__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__5__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__5__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__5__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__5__MASK, 0x40
+.set SCSI_Out_DBx__5__PC, CYREG_PRT2_PC6
+.set SCSI_Out_DBx__5__PORT, 2
+.set SCSI_Out_DBx__5__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__5__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__5__SHIFT, 6
+.set SCSI_Out_DBx__5__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__6__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__6__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__6__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__6__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__6__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__6__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__6__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__6__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__6__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__6__MASK, 0x08
+.set SCSI_Out_DBx__6__PC, CYREG_PRT2_PC3
+.set SCSI_Out_DBx__6__PORT, 2
+.set SCSI_Out_DBx__6__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__6__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__6__SHIFT, 3
+.set SCSI_Out_DBx__6__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__7__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__7__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__7__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__7__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__7__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__7__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__7__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__7__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__7__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__7__MASK, 0x04
+.set SCSI_Out_DBx__7__PC, CYREG_PRT2_PC2
+.set SCSI_Out_DBx__7__PORT, 2
+.set SCSI_Out_DBx__7__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__7__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__7__SHIFT, 2
+.set SCSI_Out_DBx__7__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB0__AG, CYREG_PRT5_AG
+.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT5_AMUX
+.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT5_BIE
+.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT5_BYP
+.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT5_CTL
+.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT5_DM0
+.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT5_DM1
+.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT5_DM2
+.set SCSI_Out_DBx__DB0__DR, CYREG_PRT5_DR
+.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_Out_DBx__DB0__MASK, 0x02
+.set SCSI_Out_DBx__DB0__PC, CYREG_PRT5_PC1
+.set SCSI_Out_DBx__DB0__PORT, 5
+.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT5_PRT
+.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_Out_DBx__DB0__PS, CYREG_PRT5_PS
+.set SCSI_Out_DBx__DB0__SHIFT, 1
+.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT5_SLW
+.set SCSI_Out_DBx__DB1__AG, CYREG_PRT5_AG
+.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT5_AMUX
+.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT5_BIE
+.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT5_BIT_MASK
+.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT5_BYP
+.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT5_CTL
+.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT5_DM0
+.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT5_DM1
+.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT5_DM2
+.set SCSI_Out_DBx__DB1__DR, CYREG_PRT5_DR
+.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT5_INP_DIS
+.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
+.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT5_LCD_EN
+.set SCSI_Out_DBx__DB1__MASK, 0x01
+.set SCSI_Out_DBx__DB1__PC, CYREG_PRT5_PC0
+.set SCSI_Out_DBx__DB1__PORT, 5
+.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT5_PRT
+.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
+.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
+.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
+.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
+.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
+.set SCSI_Out_DBx__DB1__PS, CYREG_PRT5_PS
+.set SCSI_Out_DBx__DB1__SHIFT, 0
+.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT5_SLW
+.set SCSI_Out_DBx__DB2__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__DB2__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__DB2__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__DB2__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__DB2__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__DB2__MASK, 0x20
+.set SCSI_Out_DBx__DB2__PC, CYREG_PRT6_PC5
+.set SCSI_Out_DBx__DB2__PORT, 6
+.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__DB2__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__DB2__SHIFT, 5
+.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__DB3__AG, CYREG_PRT6_AG
+.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT6_AMUX
+.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT6_BIE
+.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT6_BIT_MASK
+.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT6_BYP
+.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT6_CTL
+.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT6_DM0
+.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT6_DM1
+.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT6_DM2
+.set SCSI_Out_DBx__DB3__DR, CYREG_PRT6_DR
+.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT6_INP_DIS
+.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
+.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT6_LCD_EN
+.set SCSI_Out_DBx__DB3__MASK, 0x10
+.set SCSI_Out_DBx__DB3__PC, CYREG_PRT6_PC4
+.set SCSI_Out_DBx__DB3__PORT, 6
+.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT6_PRT
+.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
+.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
+.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
+.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
+.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
+.set SCSI_Out_DBx__DB3__PS, CYREG_PRT6_PS
+.set SCSI_Out_DBx__DB3__SHIFT, 4
+.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT6_SLW
+.set SCSI_Out_DBx__DB4__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB4__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB4__MASK, 0x80
+.set SCSI_Out_DBx__DB4__PC, CYREG_PRT2_PC7
+.set SCSI_Out_DBx__DB4__PORT, 2
+.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB4__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB4__SHIFT, 7
+.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB5__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB5__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB5__MASK, 0x40
+.set SCSI_Out_DBx__DB5__PC, CYREG_PRT2_PC6
+.set SCSI_Out_DBx__DB5__PORT, 2
+.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB5__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB5__SHIFT, 6
+.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB6__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB6__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB6__MASK, 0x08
+.set SCSI_Out_DBx__DB6__PC, CYREG_PRT2_PC3
+.set SCSI_Out_DBx__DB6__PORT, 2
+.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB6__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB6__SHIFT, 3
+.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT2_SLW
+.set SCSI_Out_DBx__DB7__AG, CYREG_PRT2_AG
+.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT2_AMUX
+.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT2_BIE
+.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT2_BIT_MASK
+.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT2_BYP
+.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT2_CTL
+.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT2_DM0
+.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT2_DM1
+.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT2_DM2
+.set SCSI_Out_DBx__DB7__DR, CYREG_PRT2_DR
+.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT2_INP_DIS
+.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG
+.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT2_LCD_EN
+.set SCSI_Out_DBx__DB7__MASK, 0x04
+.set SCSI_Out_DBx__DB7__PC, CYREG_PRT2_PC2
+.set SCSI_Out_DBx__DB7__PORT, 2
+.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT2_PRT
+.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL
+.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0
+.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0
+.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
+.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
+.set SCSI_Out_DBx__DB7__PS, CYREG_PRT2_PS
+.set SCSI_Out_DBx__DB7__SHIFT, 2
+.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT2_SLW
-/* LED */
-.set LED__0__MASK, 0x02
-.set LED__0__PC, CYREG_PRT0_PC1
-.set LED__0__PORT, 0
-.set LED__0__SHIFT, 1
-.set LED__AG, CYREG_PRT0_AG
-.set LED__AMUX, CYREG_PRT0_AMUX
-.set LED__BIE, CYREG_PRT0_BIE
-.set LED__BIT_MASK, CYREG_PRT0_BIT_MASK
-.set LED__BYP, CYREG_PRT0_BYP
-.set LED__CTL, CYREG_PRT0_CTL
-.set LED__DM0, CYREG_PRT0_DM0
-.set LED__DM1, CYREG_PRT0_DM1
-.set LED__DM2, CYREG_PRT0_DM2
-.set LED__DR, CYREG_PRT0_DR
-.set LED__INP_DIS, CYREG_PRT0_INP_DIS
-.set LED__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG
-.set LED__LCD_EN, CYREG_PRT0_LCD_EN
-.set LED__MASK, 0x02
-.set LED__PORT, 0
-.set LED__PRT, CYREG_PRT0_PRT
-.set LED__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL
-.set LED__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN
-.set LED__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0
-.set LED__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1
-.set LED__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0
-.set LED__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
-.set LED__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
-.set LED__PS, CYREG_PRT0_PS
-.set LED__SHIFT, 1
-.set LED__SLW, CYREG_PRT0_SLW
+/* SD_PULLUP */
+.set SD_PULLUP__0__MASK, 0x02
+.set SD_PULLUP__0__PC, CYREG_PRT3_PC1
+.set SD_PULLUP__0__PORT, 3
+.set SD_PULLUP__0__SHIFT, 1
+.set SD_PULLUP__1__MASK, 0x04
+.set SD_PULLUP__1__PC, CYREG_PRT3_PC2
+.set SD_PULLUP__1__PORT, 3
+.set SD_PULLUP__1__SHIFT, 2
+.set SD_PULLUP__2__MASK, 0x08
+.set SD_PULLUP__2__PC, CYREG_PRT3_PC3
+.set SD_PULLUP__2__PORT, 3
+.set SD_PULLUP__2__SHIFT, 3
+.set SD_PULLUP__3__MASK, 0x10
+.set SD_PULLUP__3__PC, CYREG_PRT3_PC4
+.set SD_PULLUP__3__PORT, 3
+.set SD_PULLUP__3__SHIFT, 4
+.set SD_PULLUP__4__MASK, 0x20
+.set SD_PULLUP__4__PC, CYREG_PRT3_PC5
+.set SD_PULLUP__4__PORT, 3
+.set SD_PULLUP__4__SHIFT, 5
+.set SD_PULLUP__AG, CYREG_PRT3_AG
+.set SD_PULLUP__AMUX, CYREG_PRT3_AMUX
+.set SD_PULLUP__BIE, CYREG_PRT3_BIE
+.set SD_PULLUP__BIT_MASK, CYREG_PRT3_BIT_MASK
+.set SD_PULLUP__BYP, CYREG_PRT3_BYP
+.set SD_PULLUP__CTL, CYREG_PRT3_CTL
+.set SD_PULLUP__DM0, CYREG_PRT3_DM0
+.set SD_PULLUP__DM1, CYREG_PRT3_DM1
+.set SD_PULLUP__DM2, CYREG_PRT3_DM2
+.set SD_PULLUP__DR, CYREG_PRT3_DR
+.set SD_PULLUP__INP_DIS, CYREG_PRT3_INP_DIS
+.set SD_PULLUP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG
+.set SD_PULLUP__LCD_EN, CYREG_PRT3_LCD_EN
+.set SD_PULLUP__MASK, 0x3E
+.set SD_PULLUP__PORT, 3
+.set SD_PULLUP__PRT, CYREG_PRT3_PRT
+.set SD_PULLUP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL
+.set SD_PULLUP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN
+.set SD_PULLUP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0
+.set SD_PULLUP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1
+.set SD_PULLUP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0
+.set SD_PULLUP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1
+.set SD_PULLUP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT
+.set SD_PULLUP__PS, CYREG_PRT3_PS
+.set SD_PULLUP__SHIFT, 1
+.set SD_PULLUP__SLW, CYREG_PRT3_SLW
/* Miscellaneous */
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
-.set CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO, 0
-.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6
-.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0
-.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
-.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1
-.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
-.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0
-.set CYDEV_CHIP_MEMBER_5B, 4
-.set CYDEV_CHIP_FAMILY_PSOC5, 3
-.set CYDEV_CHIP_DIE_PSOC5LP, 4
-.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP
-.set CYDEV_BOOTLOADER_IO_COMP_USBFS, 1
.set BCLK__BUS_CLK__HZ, 64000000
.set BCLK__BUS_CLK__KHZ, 64000
.set BCLK__BUS_CLK__MHZ, 64
.set CYDEV_BOOTLOADER_APPLICATIONS, 1
.set CYDEV_BOOTLOADER_CHECKSUM_BASIC, 0
.set CYDEV_BOOTLOADER_CHECKSUM_CRC, 1
+.set CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO, 0
+.set CyBtldr_Custom_Interface, CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
+.set CYDEV_BOOTLOADER_IO_COMP_USBFS, 1
+.set CyBtldr_USBFS, CYDEV_BOOTLOADER_IO_COMP_USBFS
.set CYDEV_BOOTLOADER_IO_COMP, CYDEV_BOOTLOADER_IO_COMP_USBFS
-.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
.set CYDEV_CHIP_DIE_LEOPARD, 1
-.set CYDEV_CHIP_DIE_PANTHER, 3
-.set CYDEV_CHIP_DIE_PSOC4A, 2
+.set CYDEV_CHIP_DIE_PANTHER, 6
+.set CYDEV_CHIP_DIE_PSOC4A, 3
+.set CYDEV_CHIP_DIE_PSOC5LP, 5
.set CYDEV_CHIP_DIE_UNKNOWN, 0
.set CYDEV_CHIP_FAMILY_PSOC3, 1
.set CYDEV_CHIP_FAMILY_PSOC4, 2
+.set CYDEV_CHIP_FAMILY_PSOC5, 3
.set CYDEV_CHIP_FAMILY_UNKNOWN, 0
.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5
.set CYDEV_CHIP_JTAG_ID, 0x2E133069
.set CYDEV_CHIP_MEMBER_3A, 1
-.set CYDEV_CHIP_MEMBER_4A, 2
-.set CYDEV_CHIP_MEMBER_5A, 3
+.set CYDEV_CHIP_MEMBER_4A, 3
+.set CYDEV_CHIP_MEMBER_4D, 2
+.set CYDEV_CHIP_MEMBER_4F, 4
+.set CYDEV_CHIP_MEMBER_5A, 6
+.set CYDEV_CHIP_MEMBER_5B, 5
.set CYDEV_CHIP_MEMBER_UNKNOWN, 0
.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B
+.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED
+.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT
+.set CYDEV_CHIP_REV_LEOPARD_ES1, 0
+.set CYDEV_CHIP_REV_LEOPARD_ES2, 1
+.set CYDEV_CHIP_REV_LEOPARD_ES3, 3
+.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3
+.set CYDEV_CHIP_REV_PANTHER_ES0, 0
+.set CYDEV_CHIP_REV_PANTHER_ES1, 1
+.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1
+.set CYDEV_CHIP_REV_PSOC4A_ES0, 17
+.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
+.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
+.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_3A_ES1, 0
.set CYDEV_CHIP_REVISION_3A_ES2, 1
.set CYDEV_CHIP_REVISION_3A_ES3, 3
.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3
.set CYDEV_CHIP_REVISION_4A_ES0, 17
.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17
+.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0
+.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_5A_ES0, 0
.set CYDEV_CHIP_REVISION_5A_ES1, 1
.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1
.set CYDEV_CHIP_REVISION_5B_ES0, 0
+.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0
.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION
-.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-.set CYDEV_CHIP_REV_LEOPARD_ES1, 0
-.set CYDEV_CHIP_REV_LEOPARD_ES2, 1
-.set CYDEV_CHIP_REV_LEOPARD_ES3, 3
-.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3
-.set CYDEV_CHIP_REV_PANTHER_ES0, 0
-.set CYDEV_CHIP_REV_PANTHER_ES1, 1
-.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1
-.set CYDEV_CHIP_REV_PSOC4A_ES0, 17
-.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17
-.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0
+.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED
+.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1
+.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0
+.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1
+.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
.set CYDEV_CONFIGURATION_COMPRESSED, 1
.set CYDEV_CONFIGURATION_DMA, 0
.set CYDEV_CONFIGURATION_ECC, 0
.set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED
+.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0
.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED
.set CYDEV_CONFIGURATION_MODE_DMA, 2
.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1
-.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1
-.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2
-.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV
+.set CYDEV_DEBUG_ENABLE_MASK, 0x20
+.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
.set CYDEV_DEBUGGING_DPS_Disable, 3
.set CYDEV_DEBUGGING_DPS_JTAG_4, 1
.set CYDEV_DEBUGGING_DPS_JTAG_5, 0
.set CYDEV_DEBUGGING_DPS_SWD, 2
+.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6
+.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV
.set CYDEV_DEBUGGING_ENABLE, 1
.set CYDEV_DEBUGGING_XRES, 0
-.set CYDEV_DEBUG_ENABLE_MASK, 0x20
-.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
.set CYDEV_DMA_CHANNELS_AVAILABLE, 24
.set CYDEV_ECC_ENABLE, 0
.set CYDEV_HEAP_SIZE, 0x0800
.set CYDEV_VDDIO1_MV, 5000
.set CYDEV_VDDIO2_MV, 5000
.set CYDEV_VDDIO3_MV, 5000
-.set CYDEV_VIO0, 5
.set CYDEV_VIO0_MV, 5000
-.set CYDEV_VIO1, 5
.set CYDEV_VIO1_MV, 5000
-.set CYDEV_VIO2, 5
.set CYDEV_VIO2_MV, 5000
-.set CYDEV_VIO3, 5
.set CYDEV_VIO3_MV, 5000
-.set CyBtldr_Custom_Interface, CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
-.set CyBtldr_USBFS, CYDEV_BOOTLOADER_IO_COMP_USBFS
+.set CYIPBLOCK_ARM_CM3_VERSION, 0
+.set CYIPBLOCK_P3_ANAIF_VERSION, 0
+.set CYIPBLOCK_P3_CAPSENSE_VERSION, 0
+.set CYIPBLOCK_P3_COMP_VERSION, 0
+.set CYIPBLOCK_P3_DMA_VERSION, 0
+.set CYIPBLOCK_P3_DRQ_VERSION, 0
+.set CYIPBLOCK_P3_EMIF_VERSION, 0
+.set CYIPBLOCK_P3_I2C_VERSION, 0
+.set CYIPBLOCK_P3_LCD_VERSION, 0
+.set CYIPBLOCK_P3_LPF_VERSION, 0
+.set CYIPBLOCK_P3_PM_VERSION, 0
+.set CYIPBLOCK_P3_TIMER_VERSION, 0
+.set CYIPBLOCK_P3_USB_VERSION, 0
+.set CYIPBLOCK_P3_VIDAC_VERSION, 0
+.set CYIPBLOCK_P3_VREF_VERSION, 0
+.set CYIPBLOCK_S8_GPIO_VERSION, 0
+.set CYIPBLOCK_S8_IRQ_VERSION, 0
+.set CYIPBLOCK_S8_SAR_VERSION, 0
+.set CYIPBLOCK_S8_SIO_VERSION, 0
+.set CYIPBLOCK_S8_UDB_VERSION, 0
.set DMA_CHANNELS_USED__MASK0, 0x00000000
.set CYDEV_BOOTLOADER_ENABLE, 1
.endif
INCLUDE cydeviceiar.inc
INCLUDE cydeviceiar_trm.inc
-/* USBFS_bus_reset */
-USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_bus_reset__INTC_MASK EQU 0x800000
-USBFS_bus_reset__INTC_NUMBER EQU 23
-USBFS_bus_reset__INTC_PRIOR_NUM EQU 7
-USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
-USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* LED */
+LED__0__MASK EQU 0x02
+LED__0__PC EQU CYREG_PRT0_PC1
+LED__0__PORT EQU 0
+LED__0__SHIFT EQU 1
+LED__AG EQU CYREG_PRT0_AG
+LED__AMUX EQU CYREG_PRT0_AMUX
+LED__BIE EQU CYREG_PRT0_BIE
+LED__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+LED__BYP EQU CYREG_PRT0_BYP
+LED__CTL EQU CYREG_PRT0_CTL
+LED__DM0 EQU CYREG_PRT0_DM0
+LED__DM1 EQU CYREG_PRT0_DM1
+LED__DM2 EQU CYREG_PRT0_DM2
+LED__DR EQU CYREG_PRT0_DR
+LED__INP_DIS EQU CYREG_PRT0_INP_DIS
+LED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+LED__LCD_EN EQU CYREG_PRT0_LCD_EN
+LED__MASK EQU 0x02
+LED__PORT EQU 0
+LED__PRT EQU CYREG_PRT0_PRT
+LED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+LED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+LED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+LED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+LED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+LED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+LED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+LED__PS EQU CYREG_PRT0_PS
+LED__SHIFT EQU 1
+LED__SLW EQU CYREG_PRT0_SLW
/* USBFS_arb_int */
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* USBFS_bus_reset */
+USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_bus_reset__INTC_MASK EQU 0x800000
+USBFS_bus_reset__INTC_NUMBER EQU 23
+USBFS_bus_reset__INTC_PRIOR_NUM EQU 7
+USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
+USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_Dm */
+USBFS_Dm__0__MASK EQU 0x80
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
+USBFS_Dm__0__PORT EQU 15
+USBFS_Dm__0__SHIFT EQU 7
+USBFS_Dm__AG EQU CYREG_PRT15_AG
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dm__DR EQU CYREG_PRT15_DR
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dm__MASK EQU 0x80
+USBFS_Dm__PORT EQU 15
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dm__PS EQU CYREG_PRT15_PS
+USBFS_Dm__SHIFT EQU 7
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW
+
+/* USBFS_Dp */
+USBFS_Dp__0__MASK EQU 0x40
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
+USBFS_Dp__0__PORT EQU 15
+USBFS_Dp__0__SHIFT EQU 6
+USBFS_Dp__AG EQU CYREG_PRT15_AG
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dp__DR EQU CYREG_PRT15_DR
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dp__MASK EQU 0x40
+USBFS_Dp__PORT EQU 15
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dp__PS EQU CYREG_PRT15_PS
+USBFS_Dp__SHIFT EQU 6
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+
+/* USBFS_dp_int */
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_dp_int__INTC_MASK EQU 0x1000
+USBFS_dp_int__INTC_NUMBER EQU 12
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_0 */
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_0__INTC_MASK EQU 0x1000000
+USBFS_ep_0__INTC_NUMBER EQU 24
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_1 */
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_1__INTC_MASK EQU 0x01
+USBFS_ep_1__INTC_NUMBER EQU 0
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+/* USBFS_ep_2 */
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_2__INTC_MASK EQU 0x02
+USBFS_ep_2__INTC_NUMBER EQU 1
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
/* USBFS_sof_int */
USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-/* SCSI_Out_DBx */
-SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__0__MASK EQU 0x02
-SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1
-SCSI_Out_DBx__0__PORT EQU 5
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__0__SHIFT EQU 1
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__1__MASK EQU 0x01
-SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0
-SCSI_Out_DBx__1__PORT EQU 5
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__1__SHIFT EQU 0
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__2__MASK EQU 0x20
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__2__PORT EQU 6
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__2__SHIFT EQU 5
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__3__MASK EQU 0x10
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4
-SCSI_Out_DBx__3__PORT EQU 6
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__3__SHIFT EQU 4
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__4__MASK EQU 0x80
-SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__4__PORT EQU 2
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__4__SHIFT EQU 7
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__5__MASK EQU 0x40
-SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6
-SCSI_Out_DBx__5__PORT EQU 2
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__5__SHIFT EQU 6
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__6__MASK EQU 0x08
-SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__6__PORT EQU 2
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__6__SHIFT EQU 3
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__7__MASK EQU 0x04
-SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2
-SCSI_Out_DBx__7__PORT EQU 2
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__7__SHIFT EQU 2
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__DB0__MASK EQU 0x02
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1
-SCSI_Out_DBx__DB0__PORT EQU 5
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__DB0__SHIFT EQU 1
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__DB1__MASK EQU 0x01
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0
-SCSI_Out_DBx__DB1__PORT EQU 5
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__DB1__SHIFT EQU 0
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB2__MASK EQU 0x20
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__DB2__PORT EQU 6
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB2__SHIFT EQU 5
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB3__MASK EQU 0x10
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4
-SCSI_Out_DBx__DB3__PORT EQU 6
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB3__SHIFT EQU 4
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB4__MASK EQU 0x80
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__DB4__PORT EQU 2
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB4__SHIFT EQU 7
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB5__MASK EQU 0x40
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6
-SCSI_Out_DBx__DB5__PORT EQU 2
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB5__SHIFT EQU 6
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB6__MASK EQU 0x08
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__DB6__PORT EQU 2
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB6__SHIFT EQU 3
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB7__MASK EQU 0x04
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2
-SCSI_Out_DBx__DB7__PORT EQU 2
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB7__SHIFT EQU 2
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
-
-/* USBFS_dp_int */
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_dp_int__INTC_MASK EQU 0x1000
-USBFS_dp_int__INTC_NUMBER EQU 12
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_0 */
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_0__INTC_MASK EQU 0x1000000
-USBFS_ep_0__INTC_NUMBER EQU 24
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_1 */
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x01
-USBFS_ep_1__INTC_NUMBER EQU 0
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* USBFS_ep_2 */
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x02
-USBFS_ep_2__INTC_NUMBER EQU 1
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-/* SD_PULLUP */
-SD_PULLUP__0__MASK EQU 0x02
-SD_PULLUP__0__PC EQU CYREG_PRT3_PC1
-SD_PULLUP__0__PORT EQU 3
-SD_PULLUP__0__SHIFT EQU 1
-SD_PULLUP__1__MASK EQU 0x04
-SD_PULLUP__1__PC EQU CYREG_PRT3_PC2
-SD_PULLUP__1__PORT EQU 3
-SD_PULLUP__1__SHIFT EQU 2
-SD_PULLUP__2__MASK EQU 0x08
-SD_PULLUP__2__PC EQU CYREG_PRT3_PC3
-SD_PULLUP__2__PORT EQU 3
-SD_PULLUP__2__SHIFT EQU 3
-SD_PULLUP__3__MASK EQU 0x10
-SD_PULLUP__3__PC EQU CYREG_PRT3_PC4
-SD_PULLUP__3__PORT EQU 3
-SD_PULLUP__3__SHIFT EQU 4
-SD_PULLUP__4__MASK EQU 0x20
-SD_PULLUP__4__PC EQU CYREG_PRT3_PC5
-SD_PULLUP__4__PORT EQU 3
-SD_PULLUP__4__SHIFT EQU 5
-SD_PULLUP__AG EQU CYREG_PRT3_AG
-SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX
-SD_PULLUP__BIE EQU CYREG_PRT3_BIE
-SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_PULLUP__BYP EQU CYREG_PRT3_BYP
-SD_PULLUP__CTL EQU CYREG_PRT3_CTL
-SD_PULLUP__DM0 EQU CYREG_PRT3_DM0
-SD_PULLUP__DM1 EQU CYREG_PRT3_DM1
-SD_PULLUP__DM2 EQU CYREG_PRT3_DM2
-SD_PULLUP__DR EQU CYREG_PRT3_DR
-SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_PULLUP__MASK EQU 0x3E
-SD_PULLUP__PORT EQU 3
-SD_PULLUP__PRT EQU CYREG_PRT3_PRT
-SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_PULLUP__PS EQU CYREG_PRT3_PS
-SD_PULLUP__SHIFT EQU 1
-SD_PULLUP__SLW EQU CYREG_PRT3_SLW
-
/* USBFS_USB */
USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
USBFS_USB__PM_ACT_MSK EQU 0x01
USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
USBFS_USB__PM_STBY_MSK EQU 0x01
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
USBFS_USB__SOF0 EQU CYREG_USB_SOF0
USBFS_USB__SOF1 EQU CYREG_USB_SOF1
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
/* SCSI_Out */
SCSI_Out__0__AG EQU CYREG_PRT15_AG
SCSI_Out__SEL__SHIFT EQU 7
SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
-/* USBFS_Dm */
-USBFS_Dm__0__MASK EQU 0x80
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
-USBFS_Dm__0__PORT EQU 15
-USBFS_Dm__0__SHIFT EQU 7
-USBFS_Dm__AG EQU CYREG_PRT15_AG
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dm__DR EQU CYREG_PRT15_DR
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dm__MASK EQU 0x80
-USBFS_Dm__PORT EQU 15
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dm__PS EQU CYREG_PRT15_PS
-USBFS_Dm__SHIFT EQU 7
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW
-
-/* USBFS_Dp */
-USBFS_Dp__0__MASK EQU 0x40
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
-USBFS_Dp__0__PORT EQU 15
-USBFS_Dp__0__SHIFT EQU 6
-USBFS_Dp__AG EQU CYREG_PRT15_AG
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dp__DR EQU CYREG_PRT15_DR
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dp__MASK EQU 0x40
-USBFS_Dp__PORT EQU 15
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dp__PS EQU CYREG_PRT15_PS
-USBFS_Dp__SHIFT EQU 6
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+/* SCSI_Out_DBx */
+SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__0__MASK EQU 0x02
+SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1
+SCSI_Out_DBx__0__PORT EQU 5
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__0__SHIFT EQU 1
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__1__MASK EQU 0x01
+SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0
+SCSI_Out_DBx__1__PORT EQU 5
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__1__SHIFT EQU 0
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__2__MASK EQU 0x20
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__2__PORT EQU 6
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__2__SHIFT EQU 5
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__3__MASK EQU 0x10
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4
+SCSI_Out_DBx__3__PORT EQU 6
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__3__SHIFT EQU 4
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__4__MASK EQU 0x80
+SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__4__PORT EQU 2
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__4__SHIFT EQU 7
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__5__MASK EQU 0x40
+SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6
+SCSI_Out_DBx__5__PORT EQU 2
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__5__SHIFT EQU 6
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__6__MASK EQU 0x08
+SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__6__PORT EQU 2
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__6__SHIFT EQU 3
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__7__MASK EQU 0x04
+SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2
+SCSI_Out_DBx__7__PORT EQU 2
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__7__SHIFT EQU 2
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__DB0__MASK EQU 0x02
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1
+SCSI_Out_DBx__DB0__PORT EQU 5
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__DB0__SHIFT EQU 1
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__DB1__MASK EQU 0x01
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0
+SCSI_Out_DBx__DB1__PORT EQU 5
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__DB1__SHIFT EQU 0
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB2__MASK EQU 0x20
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__DB2__PORT EQU 6
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB2__SHIFT EQU 5
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB3__MASK EQU 0x10
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4
+SCSI_Out_DBx__DB3__PORT EQU 6
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB3__SHIFT EQU 4
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB4__MASK EQU 0x80
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__DB4__PORT EQU 2
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB4__SHIFT EQU 7
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB5__MASK EQU 0x40
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6
+SCSI_Out_DBx__DB5__PORT EQU 2
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB5__SHIFT EQU 6
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB6__MASK EQU 0x08
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__DB6__PORT EQU 2
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB6__SHIFT EQU 3
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB7__MASK EQU 0x04
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2
+SCSI_Out_DBx__DB7__PORT EQU 2
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB7__SHIFT EQU 2
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
-/* LED */
-LED__0__MASK EQU 0x02
-LED__0__PC EQU CYREG_PRT0_PC1
-LED__0__PORT EQU 0
-LED__0__SHIFT EQU 1
-LED__AG EQU CYREG_PRT0_AG
-LED__AMUX EQU CYREG_PRT0_AMUX
-LED__BIE EQU CYREG_PRT0_BIE
-LED__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-LED__BYP EQU CYREG_PRT0_BYP
-LED__CTL EQU CYREG_PRT0_CTL
-LED__DM0 EQU CYREG_PRT0_DM0
-LED__DM1 EQU CYREG_PRT0_DM1
-LED__DM2 EQU CYREG_PRT0_DM2
-LED__DR EQU CYREG_PRT0_DR
-LED__INP_DIS EQU CYREG_PRT0_INP_DIS
-LED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-LED__LCD_EN EQU CYREG_PRT0_LCD_EN
-LED__MASK EQU 0x02
-LED__PORT EQU 0
-LED__PRT EQU CYREG_PRT0_PRT
-LED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-LED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-LED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-LED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-LED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-LED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-LED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-LED__PS EQU CYREG_PRT0_PS
-LED__SHIFT EQU 1
-LED__SLW EQU CYREG_PRT0_SLW
+/* SD_PULLUP */
+SD_PULLUP__0__MASK EQU 0x02
+SD_PULLUP__0__PC EQU CYREG_PRT3_PC1
+SD_PULLUP__0__PORT EQU 3
+SD_PULLUP__0__SHIFT EQU 1
+SD_PULLUP__1__MASK EQU 0x04
+SD_PULLUP__1__PC EQU CYREG_PRT3_PC2
+SD_PULLUP__1__PORT EQU 3
+SD_PULLUP__1__SHIFT EQU 2
+SD_PULLUP__2__MASK EQU 0x08
+SD_PULLUP__2__PC EQU CYREG_PRT3_PC3
+SD_PULLUP__2__PORT EQU 3
+SD_PULLUP__2__SHIFT EQU 3
+SD_PULLUP__3__MASK EQU 0x10
+SD_PULLUP__3__PC EQU CYREG_PRT3_PC4
+SD_PULLUP__3__PORT EQU 3
+SD_PULLUP__3__SHIFT EQU 4
+SD_PULLUP__4__MASK EQU 0x20
+SD_PULLUP__4__PC EQU CYREG_PRT3_PC5
+SD_PULLUP__4__PORT EQU 3
+SD_PULLUP__4__SHIFT EQU 5
+SD_PULLUP__AG EQU CYREG_PRT3_AG
+SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX
+SD_PULLUP__BIE EQU CYREG_PRT3_BIE
+SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_PULLUP__BYP EQU CYREG_PRT3_BYP
+SD_PULLUP__CTL EQU CYREG_PRT3_CTL
+SD_PULLUP__DM0 EQU CYREG_PRT3_DM0
+SD_PULLUP__DM1 EQU CYREG_PRT3_DM1
+SD_PULLUP__DM2 EQU CYREG_PRT3_DM2
+SD_PULLUP__DR EQU CYREG_PRT3_DR
+SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_PULLUP__MASK EQU 0x3E
+SD_PULLUP__PORT EQU 3
+SD_PULLUP__PRT EQU CYREG_PRT3_PRT
+SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_PULLUP__PS EQU CYREG_PRT3_PS
+SD_PULLUP__SHIFT EQU 1
+SD_PULLUP__SLW EQU CYREG_PRT3_SLW
/* Miscellaneous */
-/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */
-CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0
-CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
-CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
-CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
-CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
-CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
-CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
-CYDEV_CHIP_MEMBER_5B EQU 4
-CYDEV_CHIP_FAMILY_PSOC5 EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 4
-CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP
-CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1
BCLK__BUS_CLK__HZ EQU 64000000
BCLK__BUS_CLK__KHZ EQU 64000
BCLK__BUS_CLK__MHZ EQU 64
CYDEV_BOOTLOADER_APPLICATIONS EQU 1
CYDEV_BOOTLOADER_CHECKSUM_BASIC EQU 0
CYDEV_BOOTLOADER_CHECKSUM_CRC EQU 1
+CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0
+CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
+CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1
+CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
-CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 3
-CYDEV_CHIP_DIE_PSOC4A EQU 2
+CYDEV_CHIP_DIE_PANTHER EQU 6
+CYDEV_CHIP_DIE_PSOC4A EQU 3
+CYDEV_CHIP_DIE_PSOC5LP EQU 5
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
+CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
CYDEV_CHIP_JTAG_ID EQU 0x2E133069
CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 2
-CYDEV_CHIP_MEMBER_5A EQU 3
+CYDEV_CHIP_MEMBER_4A EQU 3
+CYDEV_CHIP_MEMBER_4D EQU 2
+CYDEV_CHIP_MEMBER_4F EQU 4
+CYDEV_CHIP_MEMBER_5A EQU 6
+CYDEV_CHIP_MEMBER_5B EQU 5
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
+CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
+CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
+CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
+CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
+CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
+CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
+CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
+CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
+CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
+CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
+CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
+CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5B_ES0 EQU 0
+CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION
-CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
-CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
-CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
-CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
-CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
-CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
-CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
+CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
+CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
+CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
+CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_DMA EQU 0
CYDEV_CONFIGURATION_ECC EQU 0
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
+CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
-CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
-CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
-CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
+CYDEV_DEBUG_ENABLE_MASK EQU 0x20
+CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
CYDEV_DEBUGGING_DPS_SWD EQU 2
+CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
+CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DEBUGGING_XRES EQU 0
-CYDEV_DEBUG_ENABLE_MASK EQU 0x20
-CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x0800
CYDEV_VDDIO1_MV EQU 5000
CYDEV_VDDIO2_MV EQU 5000
CYDEV_VDDIO3_MV EQU 5000
-CYDEV_VIO0 EQU 5
CYDEV_VIO0_MV EQU 5000
-CYDEV_VIO1 EQU 5
CYDEV_VIO1_MV EQU 5000
-CYDEV_VIO2 EQU 5
CYDEV_VIO2_MV EQU 5000
-CYDEV_VIO3 EQU 5
CYDEV_VIO3_MV EQU 5000
-CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
-CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
+CYIPBLOCK_ARM_CM3_VERSION EQU 0
+CYIPBLOCK_P3_ANAIF_VERSION EQU 0
+CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0
+CYIPBLOCK_P3_COMP_VERSION EQU 0
+CYIPBLOCK_P3_DMA_VERSION EQU 0
+CYIPBLOCK_P3_DRQ_VERSION EQU 0
+CYIPBLOCK_P3_EMIF_VERSION EQU 0
+CYIPBLOCK_P3_I2C_VERSION EQU 0
+CYIPBLOCK_P3_LCD_VERSION EQU 0
+CYIPBLOCK_P3_LPF_VERSION EQU 0
+CYIPBLOCK_P3_PM_VERSION EQU 0
+CYIPBLOCK_P3_TIMER_VERSION EQU 0
+CYIPBLOCK_P3_USB_VERSION EQU 0
+CYIPBLOCK_P3_VIDAC_VERSION EQU 0
+CYIPBLOCK_P3_VREF_VERSION EQU 0
+CYIPBLOCK_S8_GPIO_VERSION EQU 0
+CYIPBLOCK_S8_IRQ_VERSION EQU 0
+CYIPBLOCK_S8_SAR_VERSION EQU 0
+CYIPBLOCK_S8_SIO_VERSION EQU 0
+CYIPBLOCK_S8_UDB_VERSION EQU 0
DMA_CHANNELS_USED__MASK0 EQU 0x00000000
CYDEV_BOOTLOADER_ENABLE EQU 1
GET cydevicerv.inc
GET cydevicerv_trm.inc
-; USBFS_bus_reset
-USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_bus_reset__INTC_MASK EQU 0x800000
-USBFS_bus_reset__INTC_NUMBER EQU 23
-USBFS_bus_reset__INTC_PRIOR_NUM EQU 7
-USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
-USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; LED
+LED__0__MASK EQU 0x02
+LED__0__PC EQU CYREG_PRT0_PC1
+LED__0__PORT EQU 0
+LED__0__SHIFT EQU 1
+LED__AG EQU CYREG_PRT0_AG
+LED__AMUX EQU CYREG_PRT0_AMUX
+LED__BIE EQU CYREG_PRT0_BIE
+LED__BIT_MASK EQU CYREG_PRT0_BIT_MASK
+LED__BYP EQU CYREG_PRT0_BYP
+LED__CTL EQU CYREG_PRT0_CTL
+LED__DM0 EQU CYREG_PRT0_DM0
+LED__DM1 EQU CYREG_PRT0_DM1
+LED__DM2 EQU CYREG_PRT0_DM2
+LED__DR EQU CYREG_PRT0_DR
+LED__INP_DIS EQU CYREG_PRT0_INP_DIS
+LED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
+LED__LCD_EN EQU CYREG_PRT0_LCD_EN
+LED__MASK EQU 0x02
+LED__PORT EQU 0
+LED__PRT EQU CYREG_PRT0_PRT
+LED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
+LED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
+LED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
+LED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
+LED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
+LED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
+LED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
+LED__PS EQU CYREG_PRT0_PS
+LED__SHIFT EQU 1
+LED__SLW EQU CYREG_PRT0_SLW
; USBFS_arb_int
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; USBFS_bus_reset
+USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_bus_reset__INTC_MASK EQU 0x800000
+USBFS_bus_reset__INTC_NUMBER EQU 23
+USBFS_bus_reset__INTC_PRIOR_NUM EQU 7
+USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23
+USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_Dm
+USBFS_Dm__0__MASK EQU 0x80
+USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
+USBFS_Dm__0__PORT EQU 15
+USBFS_Dm__0__SHIFT EQU 7
+USBFS_Dm__AG EQU CYREG_PRT15_AG
+USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dm__BIE EQU CYREG_PRT15_BIE
+USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dm__BYP EQU CYREG_PRT15_BYP
+USBFS_Dm__CTL EQU CYREG_PRT15_CTL
+USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dm__DR EQU CYREG_PRT15_DR
+USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dm__MASK EQU 0x80
+USBFS_Dm__PORT EQU 15
+USBFS_Dm__PRT EQU CYREG_PRT15_PRT
+USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dm__PS EQU CYREG_PRT15_PS
+USBFS_Dm__SHIFT EQU 7
+USBFS_Dm__SLW EQU CYREG_PRT15_SLW
+
+; USBFS_Dp
+USBFS_Dp__0__MASK EQU 0x40
+USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
+USBFS_Dp__0__PORT EQU 15
+USBFS_Dp__0__SHIFT EQU 6
+USBFS_Dp__AG EQU CYREG_PRT15_AG
+USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
+USBFS_Dp__BIE EQU CYREG_PRT15_BIE
+USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
+USBFS_Dp__BYP EQU CYREG_PRT15_BYP
+USBFS_Dp__CTL EQU CYREG_PRT15_CTL
+USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
+USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
+USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
+USBFS_Dp__DR EQU CYREG_PRT15_DR
+USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
+USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
+USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
+USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
+USBFS_Dp__MASK EQU 0x40
+USBFS_Dp__PORT EQU 15
+USBFS_Dp__PRT EQU CYREG_PRT15_PRT
+USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
+USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
+USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
+USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
+USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
+USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
+USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
+USBFS_Dp__PS EQU CYREG_PRT15_PS
+USBFS_Dp__SHIFT EQU 6
+USBFS_Dp__SLW EQU CYREG_PRT15_SLW
+USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+
+; USBFS_dp_int
+USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_dp_int__INTC_MASK EQU 0x1000
+USBFS_dp_int__INTC_NUMBER EQU 12
+USBFS_dp_int__INTC_PRIOR_NUM EQU 7
+USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
+USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_0
+USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_0__INTC_MASK EQU 0x1000000
+USBFS_ep_0__INTC_NUMBER EQU 24
+USBFS_ep_0__INTC_PRIOR_NUM EQU 7
+USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
+USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_1
+USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_1__INTC_MASK EQU 0x01
+USBFS_ep_1__INTC_NUMBER EQU 0
+USBFS_ep_1__INTC_PRIOR_NUM EQU 7
+USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
+USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
+; USBFS_ep_2
+USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
+USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
+USBFS_ep_2__INTC_MASK EQU 0x02
+USBFS_ep_2__INTC_NUMBER EQU 1
+USBFS_ep_2__INTC_PRIOR_NUM EQU 7
+USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
+USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
+USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+
; USBFS_sof_int
USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-; SCSI_Out_DBx
-SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__0__MASK EQU 0x02
-SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1
-SCSI_Out_DBx__0__PORT EQU 5
-SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__0__SHIFT EQU 1
-SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__1__MASK EQU 0x01
-SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0
-SCSI_Out_DBx__1__PORT EQU 5
-SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__1__SHIFT EQU 0
-SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__2__MASK EQU 0x20
-SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__2__PORT EQU 6
-SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__2__SHIFT EQU 5
-SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__3__MASK EQU 0x10
-SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4
-SCSI_Out_DBx__3__PORT EQU 6
-SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__3__SHIFT EQU 4
-SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__4__MASK EQU 0x80
-SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__4__PORT EQU 2
-SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__4__SHIFT EQU 7
-SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__5__MASK EQU 0x40
-SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6
-SCSI_Out_DBx__5__PORT EQU 2
-SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__5__SHIFT EQU 6
-SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__6__MASK EQU 0x08
-SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__6__PORT EQU 2
-SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__6__SHIFT EQU 3
-SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__7__MASK EQU 0x04
-SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2
-SCSI_Out_DBx__7__PORT EQU 2
-SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__7__SHIFT EQU 2
-SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__DB0__MASK EQU 0x02
-SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1
-SCSI_Out_DBx__DB0__PORT EQU 5
-SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__DB0__SHIFT EQU 1
-SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG
-SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
-SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE
-SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
-SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP
-SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL
-SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
-SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
-SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
-SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
-SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
-SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
-SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
-SCSI_Out_DBx__DB1__MASK EQU 0x01
-SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0
-SCSI_Out_DBx__DB1__PORT EQU 5
-SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT
-SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
-SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
-SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
-SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
-SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS
-SCSI_Out_DBx__DB1__SHIFT EQU 0
-SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW
-SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB2__MASK EQU 0x20
-SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5
-SCSI_Out_DBx__DB2__PORT EQU 6
-SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB2__SHIFT EQU 5
-SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
-SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
-SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
-SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
-SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
-SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
-SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
-SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
-SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
-SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
-SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
-SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
-SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
-SCSI_Out_DBx__DB3__MASK EQU 0x10
-SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4
-SCSI_Out_DBx__DB3__PORT EQU 6
-SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
-SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
-SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
-SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
-SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
-SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
-SCSI_Out_DBx__DB3__SHIFT EQU 4
-SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
-SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB4__MASK EQU 0x80
-SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7
-SCSI_Out_DBx__DB4__PORT EQU 2
-SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB4__SHIFT EQU 7
-SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB5__MASK EQU 0x40
-SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6
-SCSI_Out_DBx__DB5__PORT EQU 2
-SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB5__SHIFT EQU 6
-SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB6__MASK EQU 0x08
-SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3
-SCSI_Out_DBx__DB6__PORT EQU 2
-SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB6__SHIFT EQU 3
-SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
-SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG
-SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
-SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE
-SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
-SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP
-SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL
-SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
-SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
-SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
-SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
-SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
-SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
-SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
-SCSI_Out_DBx__DB7__MASK EQU 0x04
-SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2
-SCSI_Out_DBx__DB7__PORT EQU 2
-SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT
-SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
-SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
-SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
-SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
-SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS
-SCSI_Out_DBx__DB7__SHIFT EQU 2
-SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
-
-; USBFS_dp_int
-USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_dp_int__INTC_MASK EQU 0x1000
-USBFS_dp_int__INTC_NUMBER EQU 12
-USBFS_dp_int__INTC_PRIOR_NUM EQU 7
-USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12
-USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_0
-USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_0__INTC_MASK EQU 0x1000000
-USBFS_ep_0__INTC_NUMBER EQU 24
-USBFS_ep_0__INTC_PRIOR_NUM EQU 7
-USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24
-USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_1
-USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_1__INTC_MASK EQU 0x01
-USBFS_ep_1__INTC_NUMBER EQU 0
-USBFS_ep_1__INTC_PRIOR_NUM EQU 7
-USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
-USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; USBFS_ep_2
-USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
-USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
-USBFS_ep_2__INTC_MASK EQU 0x02
-USBFS_ep_2__INTC_NUMBER EQU 1
-USBFS_ep_2__INTC_PRIOR_NUM EQU 7
-USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
-USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
-USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
-
-; SD_PULLUP
-SD_PULLUP__0__MASK EQU 0x02
-SD_PULLUP__0__PC EQU CYREG_PRT3_PC1
-SD_PULLUP__0__PORT EQU 3
-SD_PULLUP__0__SHIFT EQU 1
-SD_PULLUP__1__MASK EQU 0x04
-SD_PULLUP__1__PC EQU CYREG_PRT3_PC2
-SD_PULLUP__1__PORT EQU 3
-SD_PULLUP__1__SHIFT EQU 2
-SD_PULLUP__2__MASK EQU 0x08
-SD_PULLUP__2__PC EQU CYREG_PRT3_PC3
-SD_PULLUP__2__PORT EQU 3
-SD_PULLUP__2__SHIFT EQU 3
-SD_PULLUP__3__MASK EQU 0x10
-SD_PULLUP__3__PC EQU CYREG_PRT3_PC4
-SD_PULLUP__3__PORT EQU 3
-SD_PULLUP__3__SHIFT EQU 4
-SD_PULLUP__4__MASK EQU 0x20
-SD_PULLUP__4__PC EQU CYREG_PRT3_PC5
-SD_PULLUP__4__PORT EQU 3
-SD_PULLUP__4__SHIFT EQU 5
-SD_PULLUP__AG EQU CYREG_PRT3_AG
-SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX
-SD_PULLUP__BIE EQU CYREG_PRT3_BIE
-SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK
-SD_PULLUP__BYP EQU CYREG_PRT3_BYP
-SD_PULLUP__CTL EQU CYREG_PRT3_CTL
-SD_PULLUP__DM0 EQU CYREG_PRT3_DM0
-SD_PULLUP__DM1 EQU CYREG_PRT3_DM1
-SD_PULLUP__DM2 EQU CYREG_PRT3_DM2
-SD_PULLUP__DR EQU CYREG_PRT3_DR
-SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS
-SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
-SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN
-SD_PULLUP__MASK EQU 0x3E
-SD_PULLUP__PORT EQU 3
-SD_PULLUP__PRT EQU CYREG_PRT3_PRT
-SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
-SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
-SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
-SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
-SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
-SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
-SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
-SD_PULLUP__PS EQU CYREG_PRT3_PS
-SD_PULLUP__SHIFT EQU 1
-SD_PULLUP__SLW EQU CYREG_PRT3_SLW
-
; USBFS_USB
USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG
USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG
USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES
USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB
USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG
+USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
+USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT
USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR
USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0
USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5
USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6
USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7
-USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE
-USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE
USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE
USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5
USBFS_USB__PM_ACT_MSK EQU 0x01
USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5
USBFS_USB__PM_STBY_MSK EQU 0x01
+USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
+USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0
USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1
USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0
USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0
USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1
USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0
-USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN
-USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR
USBFS_USB__SOF0 EQU CYREG_USB_SOF0
USBFS_USB__SOF1 EQU CYREG_USB_SOF1
+USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
-USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN
; SCSI_Out
SCSI_Out__0__AG EQU CYREG_PRT15_AG
SCSI_Out__SEL__SHIFT EQU 7
SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW
-; USBFS_Dm
-USBFS_Dm__0__MASK EQU 0x80
-USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1
-USBFS_Dm__0__PORT EQU 15
-USBFS_Dm__0__SHIFT EQU 7
-USBFS_Dm__AG EQU CYREG_PRT15_AG
-USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dm__BIE EQU CYREG_PRT15_BIE
-USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dm__BYP EQU CYREG_PRT15_BYP
-USBFS_Dm__CTL EQU CYREG_PRT15_CTL
-USBFS_Dm__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dm__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dm__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dm__DR EQU CYREG_PRT15_DR
-USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dm__MASK EQU 0x80
-USBFS_Dm__PORT EQU 15
-USBFS_Dm__PRT EQU CYREG_PRT15_PRT
-USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dm__PS EQU CYREG_PRT15_PS
-USBFS_Dm__SHIFT EQU 7
-USBFS_Dm__SLW EQU CYREG_PRT15_SLW
-
-; USBFS_Dp
-USBFS_Dp__0__MASK EQU 0x40
-USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0
-USBFS_Dp__0__PORT EQU 15
-USBFS_Dp__0__SHIFT EQU 6
-USBFS_Dp__AG EQU CYREG_PRT15_AG
-USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX
-USBFS_Dp__BIE EQU CYREG_PRT15_BIE
-USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK
-USBFS_Dp__BYP EQU CYREG_PRT15_BYP
-USBFS_Dp__CTL EQU CYREG_PRT15_CTL
-USBFS_Dp__DM0 EQU CYREG_PRT15_DM0
-USBFS_Dp__DM1 EQU CYREG_PRT15_DM1
-USBFS_Dp__DM2 EQU CYREG_PRT15_DM2
-USBFS_Dp__DR EQU CYREG_PRT15_DR
-USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS
-USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT
-USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG
-USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN
-USBFS_Dp__MASK EQU 0x40
-USBFS_Dp__PORT EQU 15
-USBFS_Dp__PRT EQU CYREG_PRT15_PRT
-USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL
-USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN
-USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0
-USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1
-USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0
-USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1
-USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT
-USBFS_Dp__PS EQU CYREG_PRT15_PS
-USBFS_Dp__SHIFT EQU 6
-USBFS_Dp__SLW EQU CYREG_PRT15_SLW
-USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15
+; SCSI_Out_DBx
+SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__0__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__0__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__0__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__0__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__0__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__0__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__0__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__0__MASK EQU 0x02
+SCSI_Out_DBx__0__PC EQU CYREG_PRT5_PC1
+SCSI_Out_DBx__0__PORT EQU 5
+SCSI_Out_DBx__0__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__0__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__0__SHIFT EQU 1
+SCSI_Out_DBx__0__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__1__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__1__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__1__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__1__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__1__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__1__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__1__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__1__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__1__MASK EQU 0x01
+SCSI_Out_DBx__1__PC EQU CYREG_PRT5_PC0
+SCSI_Out_DBx__1__PORT EQU 5
+SCSI_Out_DBx__1__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__1__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__1__SHIFT EQU 0
+SCSI_Out_DBx__1__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__2__MASK EQU 0x20
+SCSI_Out_DBx__2__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__2__PORT EQU 6
+SCSI_Out_DBx__2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__2__SHIFT EQU 5
+SCSI_Out_DBx__2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__3__MASK EQU 0x10
+SCSI_Out_DBx__3__PC EQU CYREG_PRT6_PC4
+SCSI_Out_DBx__3__PORT EQU 6
+SCSI_Out_DBx__3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__3__SHIFT EQU 4
+SCSI_Out_DBx__3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__4__MASK EQU 0x80
+SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__4__PORT EQU 2
+SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__4__SHIFT EQU 7
+SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__5__MASK EQU 0x40
+SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC6
+SCSI_Out_DBx__5__PORT EQU 2
+SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__5__SHIFT EQU 6
+SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__6__MASK EQU 0x08
+SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__6__PORT EQU 2
+SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__6__SHIFT EQU 3
+SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__7__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__7__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__7__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__7__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__7__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__7__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__7__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__7__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__7__MASK EQU 0x04
+SCSI_Out_DBx__7__PC EQU CYREG_PRT2_PC2
+SCSI_Out_DBx__7__PORT EQU 2
+SCSI_Out_DBx__7__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__7__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__7__SHIFT EQU 2
+SCSI_Out_DBx__7__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB0__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__DB0__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__DB0__MASK EQU 0x02
+SCSI_Out_DBx__DB0__PC EQU CYREG_PRT5_PC1
+SCSI_Out_DBx__DB0__PORT EQU 5
+SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__DB0__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__DB0__SHIFT EQU 1
+SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__DB1__AG EQU CYREG_PRT5_AG
+SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT5_AMUX
+SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT5_BIE
+SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT5_BIT_MASK
+SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT5_BYP
+SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT5_CTL
+SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT5_DM0
+SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT5_DM1
+SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT5_DM2
+SCSI_Out_DBx__DB1__DR EQU CYREG_PRT5_DR
+SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT5_INP_DIS
+SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
+SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT5_LCD_EN
+SCSI_Out_DBx__DB1__MASK EQU 0x01
+SCSI_Out_DBx__DB1__PC EQU CYREG_PRT5_PC0
+SCSI_Out_DBx__DB1__PORT EQU 5
+SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT5_PRT
+SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
+SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
+SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
+SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
+SCSI_Out_DBx__DB1__PS EQU CYREG_PRT5_PS
+SCSI_Out_DBx__DB1__SHIFT EQU 0
+SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT5_SLW
+SCSI_Out_DBx__DB2__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB2__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB2__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB2__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB2__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB2__MASK EQU 0x20
+SCSI_Out_DBx__DB2__PC EQU CYREG_PRT6_PC5
+SCSI_Out_DBx__DB2__PORT EQU 6
+SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB2__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB2__SHIFT EQU 5
+SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB3__AG EQU CYREG_PRT6_AG
+SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT6_AMUX
+SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT6_BIE
+SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT6_BIT_MASK
+SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT6_BYP
+SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT6_CTL
+SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT6_DM0
+SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT6_DM1
+SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT6_DM2
+SCSI_Out_DBx__DB3__DR EQU CYREG_PRT6_DR
+SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT6_INP_DIS
+SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
+SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT6_LCD_EN
+SCSI_Out_DBx__DB3__MASK EQU 0x10
+SCSI_Out_DBx__DB3__PC EQU CYREG_PRT6_PC4
+SCSI_Out_DBx__DB3__PORT EQU 6
+SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT6_PRT
+SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
+SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
+SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
+SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
+SCSI_Out_DBx__DB3__PS EQU CYREG_PRT6_PS
+SCSI_Out_DBx__DB3__SHIFT EQU 4
+SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT6_SLW
+SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB4__MASK EQU 0x80
+SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC7
+SCSI_Out_DBx__DB4__PORT EQU 2
+SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB4__SHIFT EQU 7
+SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB5__MASK EQU 0x40
+SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC6
+SCSI_Out_DBx__DB5__PORT EQU 2
+SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB5__SHIFT EQU 6
+SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB6__MASK EQU 0x08
+SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC3
+SCSI_Out_DBx__DB6__PORT EQU 2
+SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB6__SHIFT EQU 3
+SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW
+SCSI_Out_DBx__DB7__AG EQU CYREG_PRT2_AG
+SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT2_AMUX
+SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT2_BIE
+SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT2_BIT_MASK
+SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT2_BYP
+SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT2_CTL
+SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT2_DM0
+SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT2_DM1
+SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT2_DM2
+SCSI_Out_DBx__DB7__DR EQU CYREG_PRT2_DR
+SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT2_INP_DIS
+SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG
+SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT2_LCD_EN
+SCSI_Out_DBx__DB7__MASK EQU 0x04
+SCSI_Out_DBx__DB7__PC EQU CYREG_PRT2_PC2
+SCSI_Out_DBx__DB7__PORT EQU 2
+SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT2_PRT
+SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL
+SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
+SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
+SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
+SCSI_Out_DBx__DB7__PS EQU CYREG_PRT2_PS
+SCSI_Out_DBx__DB7__SHIFT EQU 2
+SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT2_SLW
-; LED
-LED__0__MASK EQU 0x02
-LED__0__PC EQU CYREG_PRT0_PC1
-LED__0__PORT EQU 0
-LED__0__SHIFT EQU 1
-LED__AG EQU CYREG_PRT0_AG
-LED__AMUX EQU CYREG_PRT0_AMUX
-LED__BIE EQU CYREG_PRT0_BIE
-LED__BIT_MASK EQU CYREG_PRT0_BIT_MASK
-LED__BYP EQU CYREG_PRT0_BYP
-LED__CTL EQU CYREG_PRT0_CTL
-LED__DM0 EQU CYREG_PRT0_DM0
-LED__DM1 EQU CYREG_PRT0_DM1
-LED__DM2 EQU CYREG_PRT0_DM2
-LED__DR EQU CYREG_PRT0_DR
-LED__INP_DIS EQU CYREG_PRT0_INP_DIS
-LED__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG
-LED__LCD_EN EQU CYREG_PRT0_LCD_EN
-LED__MASK EQU 0x02
-LED__PORT EQU 0
-LED__PRT EQU CYREG_PRT0_PRT
-LED__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL
-LED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN
-LED__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0
-LED__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1
-LED__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
-LED__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
-LED__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
-LED__PS EQU CYREG_PRT0_PS
-LED__SHIFT EQU 1
-LED__SLW EQU CYREG_PRT0_SLW
+; SD_PULLUP
+SD_PULLUP__0__MASK EQU 0x02
+SD_PULLUP__0__PC EQU CYREG_PRT3_PC1
+SD_PULLUP__0__PORT EQU 3
+SD_PULLUP__0__SHIFT EQU 1
+SD_PULLUP__1__MASK EQU 0x04
+SD_PULLUP__1__PC EQU CYREG_PRT3_PC2
+SD_PULLUP__1__PORT EQU 3
+SD_PULLUP__1__SHIFT EQU 2
+SD_PULLUP__2__MASK EQU 0x08
+SD_PULLUP__2__PC EQU CYREG_PRT3_PC3
+SD_PULLUP__2__PORT EQU 3
+SD_PULLUP__2__SHIFT EQU 3
+SD_PULLUP__3__MASK EQU 0x10
+SD_PULLUP__3__PC EQU CYREG_PRT3_PC4
+SD_PULLUP__3__PORT EQU 3
+SD_PULLUP__3__SHIFT EQU 4
+SD_PULLUP__4__MASK EQU 0x20
+SD_PULLUP__4__PC EQU CYREG_PRT3_PC5
+SD_PULLUP__4__PORT EQU 3
+SD_PULLUP__4__SHIFT EQU 5
+SD_PULLUP__AG EQU CYREG_PRT3_AG
+SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX
+SD_PULLUP__BIE EQU CYREG_PRT3_BIE
+SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK
+SD_PULLUP__BYP EQU CYREG_PRT3_BYP
+SD_PULLUP__CTL EQU CYREG_PRT3_CTL
+SD_PULLUP__DM0 EQU CYREG_PRT3_DM0
+SD_PULLUP__DM1 EQU CYREG_PRT3_DM1
+SD_PULLUP__DM2 EQU CYREG_PRT3_DM2
+SD_PULLUP__DR EQU CYREG_PRT3_DR
+SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS
+SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG
+SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN
+SD_PULLUP__MASK EQU 0x3E
+SD_PULLUP__PORT EQU 3
+SD_PULLUP__PRT EQU CYREG_PRT3_PRT
+SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL
+SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN
+SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0
+SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1
+SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0
+SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1
+SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT
+SD_PULLUP__PS EQU CYREG_PRT3_PS
+SD_PULLUP__SHIFT EQU 1
+SD_PULLUP__SLW EQU CYREG_PRT3_SLW
; Miscellaneous
-; -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release
-CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0
-CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
-CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
-CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
-CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
-CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
-CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
-CYDEV_CHIP_MEMBER_5B EQU 4
-CYDEV_CHIP_FAMILY_PSOC5 EQU 3
-CYDEV_CHIP_DIE_PSOC5LP EQU 4
-CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP
-CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1
BCLK__BUS_CLK__HZ EQU 64000000
BCLK__BUS_CLK__KHZ EQU 64000
BCLK__BUS_CLK__MHZ EQU 64
CYDEV_BOOTLOADER_APPLICATIONS EQU 1
CYDEV_BOOTLOADER_CHECKSUM_BASIC EQU 0
CYDEV_BOOTLOADER_CHECKSUM_CRC EQU 1
+CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0
+CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
+CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 1
+CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
-CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
CYDEV_CHIP_DIE_LEOPARD EQU 1
-CYDEV_CHIP_DIE_PANTHER EQU 3
-CYDEV_CHIP_DIE_PSOC4A EQU 2
+CYDEV_CHIP_DIE_PANTHER EQU 6
+CYDEV_CHIP_DIE_PSOC4A EQU 3
+CYDEV_CHIP_DIE_PSOC5LP EQU 5
CYDEV_CHIP_DIE_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_PSOC3 EQU 1
CYDEV_CHIP_FAMILY_PSOC4 EQU 2
+CYDEV_CHIP_FAMILY_PSOC5 EQU 3
CYDEV_CHIP_FAMILY_UNKNOWN EQU 0
CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5
CYDEV_CHIP_JTAG_ID EQU 0x2E133069
CYDEV_CHIP_MEMBER_3A EQU 1
-CYDEV_CHIP_MEMBER_4A EQU 2
-CYDEV_CHIP_MEMBER_5A EQU 3
+CYDEV_CHIP_MEMBER_4A EQU 3
+CYDEV_CHIP_MEMBER_4D EQU 2
+CYDEV_CHIP_MEMBER_4F EQU 4
+CYDEV_CHIP_MEMBER_5A EQU 6
+CYDEV_CHIP_MEMBER_5B EQU 5
CYDEV_CHIP_MEMBER_UNKNOWN EQU 0
CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B
+CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED
+CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT
+CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
+CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
+CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
+CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
+CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
+CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
+CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
+CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
+CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
+CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_3A_ES1 EQU 0
CYDEV_CHIP_REVISION_3A_ES2 EQU 1
CYDEV_CHIP_REVISION_3A_ES3 EQU 3
CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3
CYDEV_CHIP_REVISION_4A_ES0 EQU 17
CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17
+CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0
+CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_5A_ES0 EQU 0
CYDEV_CHIP_REVISION_5A_ES1 EQU 1
CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1
CYDEV_CHIP_REVISION_5B_ES0 EQU 0
+CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0
CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION
-CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION
-CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0
-CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1
-CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3
-CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3
-CYDEV_CHIP_REV_PANTHER_ES0 EQU 0
-CYDEV_CHIP_REV_PANTHER_ES1 EQU 1
-CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1
-CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17
-CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17
-CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0
+CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED
+CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1
+CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0
+CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
+CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
+CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
CYDEV_CONFIGURATION_COMPRESSED EQU 1
CYDEV_CONFIGURATION_DMA EQU 0
CYDEV_CONFIGURATION_ECC EQU 0
CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED
+CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0
CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED
CYDEV_CONFIGURATION_MODE_DMA EQU 2
CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1
-CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn
-CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1
-CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2
-CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
+CYDEV_DEBUG_ENABLE_MASK EQU 0x20
+CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
CYDEV_DEBUGGING_DPS_Disable EQU 3
CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
CYDEV_DEBUGGING_DPS_SWD EQU 2
+CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6
+CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DEBUGGING_XRES EQU 0
-CYDEV_DEBUG_ENABLE_MASK EQU 0x20
-CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x0800
CYDEV_VDDIO1_MV EQU 5000
CYDEV_VDDIO2_MV EQU 5000
CYDEV_VDDIO3_MV EQU 5000
-CYDEV_VIO0 EQU 5
CYDEV_VIO0_MV EQU 5000
-CYDEV_VIO1 EQU 5
CYDEV_VIO1_MV EQU 5000
-CYDEV_VIO2 EQU 5
CYDEV_VIO2_MV EQU 5000
-CYDEV_VIO3 EQU 5
CYDEV_VIO3_MV EQU 5000
-CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO
-CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS
+CYIPBLOCK_ARM_CM3_VERSION EQU 0
+CYIPBLOCK_P3_ANAIF_VERSION EQU 0
+CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0
+CYIPBLOCK_P3_COMP_VERSION EQU 0
+CYIPBLOCK_P3_DMA_VERSION EQU 0
+CYIPBLOCK_P3_DRQ_VERSION EQU 0
+CYIPBLOCK_P3_EMIF_VERSION EQU 0
+CYIPBLOCK_P3_I2C_VERSION EQU 0
+CYIPBLOCK_P3_LCD_VERSION EQU 0
+CYIPBLOCK_P3_LPF_VERSION EQU 0
+CYIPBLOCK_P3_PM_VERSION EQU 0
+CYIPBLOCK_P3_TIMER_VERSION EQU 0
+CYIPBLOCK_P3_USB_VERSION EQU 0
+CYIPBLOCK_P3_VIDAC_VERSION EQU 0
+CYIPBLOCK_P3_VREF_VERSION EQU 0
+CYIPBLOCK_S8_GPIO_VERSION EQU 0
+CYIPBLOCK_S8_IRQ_VERSION EQU 0
+CYIPBLOCK_S8_SAR_VERSION EQU 0
+CYIPBLOCK_S8_SIO_VERSION EQU 0
+CYIPBLOCK_S8_UDB_VERSION EQU 0
DMA_CHANNELS_USED__MASK0 EQU 0x00000000
CYDEV_BOOTLOADER_ENABLE EQU 1
ENDIF
/*******************************************************************************
* FILENAME: cymetadata.c
*
-* PSoC Creator 3.0 Component Pack 7
+* PSoC Creator 3.1
*
* DESCRIPTION:
* This file defines all extra memory spaces that need to be included.
/*******************************************************************************
* File Name: cypins.h
-* Version 4.0
+* Version 4.20
*
* Description:
-* This file contains the function prototypes and constants used for port/pin
+* This file contains the function prototypes and constants used for a port/pin
* in access and control.
*
* Note:
* System Reference Guide provided with PSoC Creator.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
* Note that this only has an effect for pins configured as software pins that
* are not driven by hardware.
*
+* The macro operation is not atomic. It is not guaranteed that shared register
+* will remain uncorrupted during simultaneous read-modify-write operations
+* performed by two threads (main and interrupt threads). To guarantee data
+* integrity in such cases, the macro should be invoked while the specific
+* interrupt is disabled or within critical section (all interrupts are
+* disabled).
+*
* Parameters:
* pinPC: Port pin configuration register (uint16).
* #defines for each pin on a chip are provided in the cydevice_trm.h file
********************************************************************************
*
* Summary:
-* This macro sets the state of the specified pin to 0
+* This macro sets the state of the specified pin to 0.
+*
+* The macro operation is not atomic. It is not guaranteed that shared register
+* will remain uncorrupted during simultaneous read-modify-write operations
+* performed by two threads (main and interrupt threads). To guarantee data
+* integrity in such cases, the macro should be invoked while the specific
+* interrupt is disabled or within critical section (all interrupts are
+* disabled).
*
* Parameters:
* pinPC: address of a Pin Configuration register.
* Summary:
* Sets the drive mode for the pin (DM).
*
+* The macro operation is not atomic. It is not guaranteed that shared register
+* will remain uncorrupted during simultaneous read-modify-write operations
+* performed by two threads (main and interrupt threads). To guarantee data
+* integrity in such cases, the macro should be invoked while the specific
+* interrupt is disabled or within critical section (all interrupts are
+* disabled).
+*
* Parameters:
* pinPC: Port pin configuration register (uint16)
* #defines for each pin on a chip are provided in the cydevice_trm.h file
*
*
* Return:
-* mode: Current drive mode for the pin
+* mode: The current drive mode for the pin
*
* Define Source
* PIN_DM_ALG_HIZ Analog HiZ
********************************************************************************
*
* Summary:
-* Set the slew rate for the pin to fast edge rate.
+* Set the slew rate for the pin to fast the edge rate.
* Note that this only applies for pins in strong output drive modes,
* not to resistive drive modes.
*
+* The macro operation is not atomic. It is not guaranteed that shared register
+* will remain uncorrupted during simultaneous read-modify-write operations
+* performed by two threads (main and interrupt threads). To guarantee data
+* integrity in such cases, the macro should be invoked while the specific
+* interrupt is disabled or within critical section (all interrupts are
+* disabled).
+*
* Parameters:
* pinPC: address of a Pin Configuration register.
* #defines for each pin on a chip are provided in the cydevice_trm.h file
********************************************************************************
*
* Summary:
-* Set the slew rate for the pin to slow edge rate.
+* Set the slew rate for the pin to slow the edge rate.
* Note that this only applies for pins in strong output drive modes,
* not to resistive drive modes.
*
+* The macro operation is not atomic. It is not guaranteed that shared register
+* will remain uncorrupted during simultaneous read-modify-write operations
+* performed by two threads (main and interrupt threads). To guarantee data
+* integrity in such cases, the macro should be invoked while the specific
+* interrupt is disabled or within critical section (all interrupts are
+* disabled).
+*
* Parameters:
* pinPC: address of a Pin Configuration register.
* #defines for each pin on a chip are provided in the cydevice_trm.h file
/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.30
+* The following code is OBSOLETE and must not be used.
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+* #ifdef <OBSOLETED_DEFINE>
+* #undef <OBSOLETED_DEFINE>
+* #define <OBSOLETED_DEFINE> (<New Value>)
+* #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+* used in the application and their modification might lead to unexpected
+* consequences.
*******************************************************************************/
#define PC_DRIVE_MODE_SHIFT (CY_PINS_PC_DRIVE_MODE_SHIFT)
#define PC_DRIVE_MODE_MASK (CY_PINS_PC_DRIVE_MODE_MASK)
/*******************************************************************************
* FILENAME: cytypes.h
-* Version 4.0
+* Version 4.20
*
* Description:
* CyTypes provides register access macros and approved types for use in
* data the correct way.
*
* Register Access macros and functions perform their operations on an
-* input of type pointer to void. The arguments passed to it should be
+* input of the type pointer to void. The arguments passed to it should be
* pointers to the type associated with the register size.
* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value)
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
#if defined( __ICCARM__ )
/* Suppress warning for multiple volatile variables in an expression. */
- /* This is common in component code and the usage is not order dependent. */
+ /* This is common in component code and usage is not order dependent. */
#pragma diag_suppress=Pa082
#endif /* defined( __ICCARM__ ) */
/*******************************************************************************
* MEMBER encodes both the family and the detailed architecture
*******************************************************************************/
-#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
#ifdef CYDEV_CHIP_MEMBER_4D
- #define CY_PSOC4D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
- #define CY_PSOC4SF (CY_PSOC4D)
+ #define CY_PSOC4_4000 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
#else
- #define CY_PSOC4D (0u != 0u)
- #define CY_PSOC4SF (CY_PSOC4D)
+ #define CY_PSOC4_4000 (0u != 0u)
#endif /* CYDEV_CHIP_MEMBER_4D */
-#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
-#ifdef CYDEV_CHIP_MEMBER_5B
- #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)
+#define CY_PSOC4_4100 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
+#define CY_PSOC4_4200 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
+
+#ifdef CYDEV_CHIP_MEMBER_4F
+ #define CY_PSOC4_4100BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F)
+ #define CY_PSOC4_4200BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F)
#else
- #define CY_PSOC5LP (0u != 0u)
-#endif /* CYDEV_CHIP_MEMBER_5B */
+ #define CY_PSOC4_4100BL (0u != 0u)
+ #define CY_PSOC4_4200BL (0u != 0u)
+#endif /* CYDEV_CHIP_MEMBER_4F */
/*******************************************************************************
-* UDB revisions
+* IP blocks
*******************************************************************************/
-#define CY_UDB_V0 (CY_PSOC5A)
-#define CY_UDB_V1 (!CY_UDB_V0)
+#if (CY_PSOC4)
+
+ /* Using SRSSv2 or SRS-Lite */
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+ #define CY_IP_SRSSV2 (0u == 0u)
+ #define CY_IP_SRSSLT (!CY_IP_SRSSV2)
+ #else
+ #define CY_IP_SRSSV2 (0u != 0u)
+ #define CY_IP_SRSSLT (!CY_IP_SRSSV2)
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+ #define CY_IP_CPUSSV2 (0u != 0u)
+ #define CY_IP_CPUSS (0u == 0u)
+ #else
+ #define CY_IP_CPUSSV2 (0u != 0u)
+ #define CY_IP_CPUSS (!CY_IP_CPUSSV2)
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+ /* Product uses FLASH-Lite or regular FLASH */
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+ #define CY_IP_FMLT (0u != 0u) /* FLASH-Lite */
+ #define CY_IP_FM (!CY_IP_FMLT) /* Regular FLASH */
+ #else
+ #define CY_IP_FMLT (-1u != 0u)
+ #define CY_IP_FM (!CY_IP_FMLT)
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+ /* Number of interrupt request inputs to CM0 */
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+ #define CY_IP_INT_NR (32u)
+ #else
+ #define CY_IP_INT_NR (-1u)
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+ /* Number of Flash macros used in the device (0, 1 or 2) */
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+ #define CY_IP_FLASH_MACROS (1u)
+ #else
+ #define CY_IP_FLASH_MACROS (-1u)
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+
+ /* Number of Flash macros used in the device (0, 1 or 2) */
+ #if (CY_PSOC4_4100 || CY_PSOC4_4200)
+ #define CY_IP_BLESS (0u != 0u)
+ #else
+ #define CY_IP_BLESS (0u != 0u)
+ #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+ /* Watch Crystal Oscillator (WCO) is present (32kHz) */
+ #if (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200)
+ #define CY_IP_WCO (0u != 0u)
+ #elif CY_IP_BLESS || defined (CYIPBLOCK_s8swco_VERSION)
+ #define CY_IP_WCO (0u == 0u)
+ #elif (CY_IP_SRSSV2)
+ #define CY_IP_WCO (-1u)
+ #else
+ #define CY_IP_WCO (0u != 0u)
+ #endif /* (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200) */
+
+#endif /* (CY_PSOC4) */
+
+
+/*******************************************************************************
+* The components version defines. Available started from cy_boot 4.20
+* Use the following construction in order to identify cy_boot version:
+* (defined(CY_BOOT_VERSION) && CY_BOOT_VERSION >= CY_BOOT_4_20)
+*******************************************************************************/
+#define CY_BOOT_4_20 (420u)
+#define CY_BOOT_VERSION (CY_BOOT_4_20)
/*******************************************************************************
#endif /* (!CY_PSOC3) */
-/* Signed or unsigned depending on the compiler selection */
+/* Signed or unsigned depending on compiler selection */
typedef char char8;
#else
- /* Prototype for function to set a 24-bit register. Located at cyutils.c */
+ /* Prototype for function to set 24-bit register. Located at cyutils.c */
extern void CySetReg24(uint32 volatile * addr, uint32 value);
#if(CY_PSOC4)
#define XDATA
#if defined(__ARMCC_VERSION)
+
#define CY_NOINIT __attribute__ ((section(".noinit"), zero_init))
#define CY_NORETURN __attribute__ ((noreturn))
#define CY_SECTION(name) __attribute__ ((section(name)))
+
+ /* Specifies a minimum alignment (in bytes) for variables of the
+ * specified type.
+ */
#define CY_ALIGN(align) __align(align)
+
+
+ /* Attached to an enum, struct, or union type definition, specified that
+ * the minimum required memory be used to represent the type.
+ */
+ #define CY_PACKED
+ #define CY_PACKED_ATTR __attribute__ ((packed))
+ #define CY_INLINE __inline
#elif defined (__GNUC__)
+
#define CY_NOINIT __attribute__ ((section(".noinit")))
#define CY_NORETURN __attribute__ ((noreturn))
#define CY_SECTION(name) __attribute__ ((section(name)))
#define CY_ALIGN(align) __attribute__ ((aligned(align)))
+ #define CY_PACKED
+ #define CY_PACKED_ATTR __attribute__ ((packed))
+ #define CY_INLINE inline
#elif defined (__ICCARM__)
+
#define CY_NOINIT __no_init
#define CY_NORETURN __noreturn
+ #define CY_PACKED __packed
+ #define CY_PACKED_ATTR
+ #define CY_INLINE inline
#endif /* (__ARMCC_VERSION) */
#endif /* (CY_PSOC3) */
#if(CY_PSOC3)
- /* 8051 naturally returns an 8 bit value. */
+ /* 8051 naturally returns 8 bit value. */
typedef unsigned char cystatus;
#else
- /* ARM naturally returns a 32 bit value. */
+ /* ARM naturally returns 32 bit value. */
typedef unsigned long cystatus;
#endif /* (CY_PSOC3) */
* KEIL for the 8051 is a big endian compiler This causes problems as the on chip
* registers are little endian. Byte swapping for two and four byte registers is
* implemented in the functions below. This will require conditional compilation
- * of function prototypes in code.
+ * of function prototypes in the code.
*******************************************************************************/
/* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */
* Data manipulation defines
*******************************************************************************/
-/* Get 8 bits of a 16 bit value. */
+/* Get 8 bits of 16 bit value. */
#define LO8(x) ((uint8) ((x) & 0xFFu))
#define HI8(x) ((uint8) ((uint16)(x) >> 8))
-/* Get 16 bits of a 32 bit value. */
+/* Get 16 bits of 32 bit value. */
#define LO16(x) ((uint16) ((x) & 0xFFFFu))
#define HI16(x) ((uint16) ((uint32)(x) >> 16))
-/* Swap the byte ordering of a 32 bit value */
+/* Swap the byte ordering of 32 bit value */
#define CYSWAP_ENDIAN32(x) \
((uint32)(((x) >> 24) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24)))
-/* Swap the byte ordering of a 16 bit value */
+/* Swap the byte ordering of 16 bit value */
#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | ((x) >> 8)))
/*******************************************************************************
-* Defines the standard return values used PSoC content. A function is
+* Defines the standard return values used in PSoC content. A function is
* not limited to these return values but can use them when returning standard
* error values. Return values can be overloaded if documented in the function
* header. On the 8051 a function can use a larger return type but still use the
/*******************************************************************************
-* Following code are OBSOLETE and must not be used starting from cy_boot 3.10
+* The following code is OBSOLETE and must not be used starting from cy_boot 3.10
+*
+* If the obsoleted macro definitions intended for use in the application use the
+* following scheme, redefine your own versions of these definitions:
+* #ifdef <OBSOLETED_DEFINE>
+* #undef <OBSOLETED_DEFINE>
+* #define <OBSOLETED_DEFINE> (<New Value>)
+* #endif
+*
+* Note: Redefine obsoleted macro definitions with caution. They might still be
+* used in the application and their modification might lead to unexpected
+* consequences.
*******************************************************************************/
+#define CY_UDB_V0 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
+#define CY_UDB_V1 (!CY_UDB_V0)
+#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
+#ifdef CYDEV_CHIP_MEMBER_4D
+ #define CY_PSOC4D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
+ #define CY_PSOC4SF (CY_PSOC4D)
+#else
+ #define CY_PSOC4D (0u != 0u)
+ #define CY_PSOC4SF (CY_PSOC4D)
+#endif /* CYDEV_CHIP_MEMBER_4D */
+#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
+#ifdef CYDEV_CHIP_MEMBER_5B
+ #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)
+#else
+ #define CY_PSOC5LP (0u != 0u)
+#endif /* CYDEV_CHIP_MEMBER_5B */
+
+#if (!CY_PSOC4)
+
+ /* Device is PSoC 3 and the revision is ES2 or earlier */
+ #define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
+ (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2))
-/* Device is PSoC 3 and the revision is ES2 or earlier */
-#define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
- (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2))
+ /* Device is PSoC 3 and the revision is ES3 or later */
+ #define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
+ (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3))
-/* Device is PSoC 3 and the revision is ES3 or later */
-#define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \
- (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3))
+ /* Device is PSoC 5 and the revision is ES1 or earlier */
+ #define CY_PSOC5_ES1 (CY_PSOC5A && \
+ (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1))
-/* Device is PSoC 5 and the revision is ES1 or earlier */
-#define CY_PSOC5_ES1 (CY_PSOC5A && \
- (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1))
+ /* Device is PSoC 5 and the revision is ES2 or later */
+ #define CY_PSOC5_ES2 (CY_PSOC5A && \
+ (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1))
-/* Device is PSoC 5 and the revision is ES2 or later */
-#define CY_PSOC5_ES2 (CY_PSOC5A && \
- (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1))
+#endif /* (!CY_PSOC4) */
#endif /* CY_BOOT_CYTYPES_H */
/*******************************************************************************
* FILENAME: cyutils.c
-* Version 4.0
+* Version 4.20
*
* Description:
-* CyUtils provides function to handle 24-bit value writes.
+* CyUtils provides a function to handle 24-bit value writes.
*
********************************************************************************
-* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
+* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
****************************************************************************
*
* Summary:
- * Writes the 24-bit value to the specified register.
+ * Writes a 24-bit value to the specified register.
*
* Parameters:
- * addr : adress where data must be written
- * value: data that must be written
+ * addr : the address where data must be written.
+ * value: the data that must be written.
*
* Return:
* None
* Reads the 24-bit value from the specified register.
*
* Parameters:
- * addr : adress where data must be read
+ * addr : the address where data must be read.
*
* Return:
* None
/*******************************************************************************
* File Name: project.h
- * PSoC Creator 3.0 Component Pack 7
+ * PSoC Creator 3.1
*
* Description:
* This file is automatically generated by PSoC Creator and should not
<block name="SD_PULLUP" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="LED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
- <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="ZeroTerminal_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="VirtualMux_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="VirtualMux_5" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="VirtualMux_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="VirtualMux_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="ZeroTerminal_6" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="VirtualMux_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="ZeroTerminal_4" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="ZeroTerminal_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="ZeroTerminal_7" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="dp_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="ZeroTerminal_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="sof_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="USB" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Dp" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ep_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Dm" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="ep_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="arb_int" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Clock_vbus" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="ZeroTerminal_8" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<register name="USBFS_PM_USB_CR0" address="0x40004394" bitWidth="8" desc="USB Power Mode Control Register 0">
<field name="fsusbio_ref_en" from="0" to="0" access="RW" resetVal="" desc="" />
<field name="fsusbio_pd_n" from="1" to="1" access="RW" resetVal="" desc="" />
<register name="USBFS_EP0_DR6" address="0x40006006" bitWidth="8" desc="lengthLo" />
<register name="USBFS_EP0_DR7" address="0x40006007" bitWidth="8" desc="lengthHi" />
<register name="USBFS_CR0" address="0x40006008" bitWidth="8" desc="USB Control Register 0">
- <field name="device_address" from="0" to="6" access="R" resetVal="" desc="" />
+ <field name="device_address" from="6" to="0" access="R" resetVal="" desc="" />
<field name="usb_enable" from="7" to="7" access="RW" resetVal="" desc="" />
</register>
<register name="USBFS_CR1" address="0x40006009" bitWidth="8" desc="USB Control Register 1">
<GlobalPages />
<GlobalTools name="Code Generation">
<GlobalPages>
+<name_val_pair name="General@Application Type" v="Bootloader" />
+<name_val_pair name="General@Custom Code Gen Options" v="" />
+<name_val_pair name="General@Skip Code Generation" v="False" />
+<name_val_pair name="General@Custom Synthesis Options" v="" />
+<name_val_pair name="General@Quiet Output" v="True" />
<name_val_pair name="General@Synthesis Goal" v="Speed" />
<name_val_pair name="General@Synthesis Optimization Effort" v="Exhaustive" />
-<name_val_pair name="General@Quiet Output" v="True" />
-<name_val_pair name="General@Custom Synthesis Options" v="" />
-<name_val_pair name="General@Skip Code Generation" v="False" />
-<name_val_pair name="General@Custom Code Gen Options" v="" />
<name_val_pair name="General@Virtual Node Substitution" v="3" />
-<name_val_pair name="General@Application Type" v="Bootloader" />
<name_val_pair name="General@Custom Fitter Options" v="" />
</GlobalPages>
</GlobalTools>
</GlobalTools>
<GlobalTools name="Customizer">
<GlobalPages>
-<name_val_pair name="General@Customizer Build Mode" v="Release" />
-<name_val_pair name="General@Command Line Options" v="" />
<name_val_pair name="General@Assembly References" v="" />
+<name_val_pair name="General@Command Line Options" v="" />
+<name_val_pair name="General@Customizer Build Mode" v="Release" />
</GlobalPages>
</GlobalTools>
</name>
<platform>
<name v="c9323d49-d323-40b8-9b59-cc008d68a989">
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Additional Include Directories" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Create Listing File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Generate Debugging Information" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Join Data and Text Sections" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Suppress Warnings" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Additional Include Directories" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Warnings as Errors" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Warning Level" v="High" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Pedantic Compilation" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Create Listing File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Default Char Unsigned" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Generate Debugging Information" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Preprocessor Definitions" v="DEBUG" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Default Char Unsigned" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Create Listing File" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Pedantic Compilation" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Warning Level" v="High" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Warnings as Errors" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Struct Return Method" v="System Default" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Verbose Asm" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Code Generation@Struct Return Method" v="System Default" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Code Generation@Verbose Asm" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Optimization Level" v="None" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Optimization@Link Time Optimization" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Additional Include Directories" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Suppress Warnings" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Generate Debugging Information" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Join Data and Text Sections" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Create Listing File" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@Command Line@Command Line" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Link Files" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Libraries" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Library Directories" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Debugging Information" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Additional Link Files" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Generate Map File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Debugging Information" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Default Libs" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Nano Lib" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Remove Unused Functions" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Enable printf Float" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@Optimization Level" v="None" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Command Line@Command Line" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Additional Include Directories" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Create Listing File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Generate Debugging Information" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Join Data and Text Sections" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Suppress Warnings" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Additional Include Directories" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Warnings as Errors" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Warning Level" v="High" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Pedantic Compilation" v="False" />
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+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Default Char Unsigned" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Generate Debugging Information" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Preprocessor Definitions" v="NDEBUG" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Default Char Unsigned" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Create Listing File" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Inline Functions" v="False" />
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+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Warnings as Errors" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Struct Return Method" v="System Default" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@General@Verbose Asm" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Remove Unused Functions" v="True" />
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-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Code Generation@Verbose Asm" v="False" />
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+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Optimization@Optimization Level" v="Size" />
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<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Command Line@Command Line" v="" />
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-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Suppress Warnings" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Generate Debugging Information" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Join Data and Text Sections" v="False" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Create Listing File" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@Command Line@Command Line" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Additional Link Files" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Additional Libraries" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Additional Library Directories" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Use Debugging Information" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Additional Link Files" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Generate Map File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Use Debugging Information" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Use Default Libs" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Use Nano Lib" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Remove Unused Functions" v="True" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Custom Linker Script" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Enable printf Float" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@Optimization Level" v="None" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Optimization@Remove Unused Functions" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Command Line@Command Line" v="" />
-<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Additional Include Directories" v="" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Create Listing File" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Generate Debugging Information" v="True" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Join Data and Text Sections" v="False" />
+<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Suppress Warnings" v="False" />
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+<WriteAppVersionLastSavedWith v="3.1.0.1570" />
+<WriteAppMarketingVersionLastSavedWith v=" 3.1" />
+<project_id v="61ede17a-ffe1-47e5-a8cd-0424bf996857" /><custom_data><CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectCustomData" version="1"><CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997 type_name="CyDesigner.Common.Base.CyCustomData" version="2"><userData /></CyGuid_fdba8dfd-b15b-4469-9bbb-9e40c3e70997><properties /></CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111></custom_data></CyGuid_49cfd574-032a-4a64-b7be-d4eeeaf25e43>
</CyGuid_60697ce6-dce2-4816-8680-4de0635742eb>
<top_block v="TopDesign" />
<selected_device v="CY8C5267AXI-LP051" />
<CyGuid_b0d670ad-d48f-47cb-9d0b-b1642bab195c type_name="CyDesigner.Common.Base.CyExprTypeMgr" version="1" />
<ignored_deps />
</CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>
-<boot_component v="cy_boot_v4_0" />
+<boot_component v="cy_boot_v4_20" />
<BootloaderTag hexFile="" elfFile="" />
<current_generation v="0" />
</CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
-</CyXmlSerializer>
+</CyXmlSerializer>
\ No newline at end of file
<peripheral>
<name>USBFS</name>
<description>USBFS</description>
- <baseAddress>0x40004394</baseAddress>
+ <baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
- <size>0x1D0A</size>
+ <size>0x0</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>USBFS_PM_USB_CR0</name>
<description>USB Power Mode Control Register 0</description>
- <addressOffset>0x0</addressOffset>
+ <addressOffset>0x40004394</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_PM_ACT_CFG</name>
<description>Active Power Mode Configuration Register</description>
- <addressOffset>0x11</addressOffset>
+ <addressOffset>0x400043A5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_PM_STBY_CFG</name>
<description>Standby Power Mode Configuration Register</description>
- <addressOffset>0x21</addressOffset>
+ <addressOffset>0x400043B5</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_PRT_PS</name>
<description>Port Pin State Register</description>
- <addressOffset>0xE5D</addressOffset>
+ <addressOffset>0x400051F1</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_PRT_DM0</name>
<description>Port Drive Mode Register</description>
- <addressOffset>0xE5E</addressOffset>
+ <addressOffset>0x400051F2</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_PRT_DM1</name>
<description>Port Drive Mode Register</description>
- <addressOffset>0xE5F</addressOffset>
+ <addressOffset>0x400051F3</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_PRT_INP_DIS</name>
<description>Input buffer disable override</description>
- <addressOffset>0xE64</addressOffset>
+ <addressOffset>0x400051F8</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP0_DR0</name>
<description>bmRequestType</description>
- <addressOffset>0x1C6C</addressOffset>
+ <addressOffset>0x40006000</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP0_DR1</name>
<description>bRequest</description>
- <addressOffset>0x1C6D</addressOffset>
+ <addressOffset>0x40006001</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP0_DR2</name>
<description>wValueLo</description>
- <addressOffset>0x1C6E</addressOffset>
+ <addressOffset>0x40006002</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP0_DR3</name>
<description>wValueHi</description>
- <addressOffset>0x1C6F</addressOffset>
+ <addressOffset>0x40006003</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP0_DR4</name>
<description>wIndexLo</description>
- <addressOffset>0x1C70</addressOffset>
+ <addressOffset>0x40006004</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP0_DR5</name>
<description>wIndexHi</description>
- <addressOffset>0x1C71</addressOffset>
+ <addressOffset>0x40006005</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP0_DR6</name>
<description>lengthLo</description>
- <addressOffset>0x1C72</addressOffset>
+ <addressOffset>0x40006006</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP0_DR7</name>
<description>lengthHi</description>
- <addressOffset>0x1C73</addressOffset>
+ <addressOffset>0x40006007</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_CR0</name>
<description>USB Control Register 0</description>
- <addressOffset>0x1C74</addressOffset>
+ <addressOffset>0x40006008</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<field>
<name>device_address</name>
<description>No description available</description>
- <lsb>6</lsb>
- <msb>0</msb>
+ <lsb>0</lsb>
+ <msb>6</msb>
<access>read-only</access>
</field>
<field>
<register>
<name>USBFS_CR1</name>
<description>USB Control Register 1</description>
- <addressOffset>0x1C75</addressOffset>
+ <addressOffset>0x40006009</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_SIE_EP1_CR0</name>
<description>The Endpoint1 Control Register</description>
- <addressOffset>0x1C7A</addressOffset>
+ <addressOffset>0x4000600E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_USBIO_CR0</name>
<description>USBIO Control Register 0</description>
- <addressOffset>0x1C7C</addressOffset>
+ <addressOffset>0x40006010</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_USBIO_CR1</name>
<description>USBIO Control Register 1</description>
- <addressOffset>0x1C7E</addressOffset>
+ <addressOffset>0x40006012</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_SIE_EP2_CR0</name>
<description>The Endpoint2 Control Register</description>
- <addressOffset>0x1C8A</addressOffset>
+ <addressOffset>0x4000601E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_SIE_EP3_CR0</name>
<description>The Endpoint3 Control Register</description>
- <addressOffset>0x1C9A</addressOffset>
+ <addressOffset>0x4000602E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_SIE_EP4_CR0</name>
<description>The Endpoint4 Control Register</description>
- <addressOffset>0x1CAA</addressOffset>
+ <addressOffset>0x4000603E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_SIE_EP5_CR0</name>
<description>The Endpoint5 Control Register</description>
- <addressOffset>0x1CBA</addressOffset>
+ <addressOffset>0x4000604E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_SIE_EP6_CR0</name>
<description>The Endpoint6 Control Register</description>
- <addressOffset>0x1CCA</addressOffset>
+ <addressOffset>0x4000605E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_SIE_EP7_CR0</name>
<description>The Endpoint7 Control Register</description>
- <addressOffset>0x1CDA</addressOffset>
+ <addressOffset>0x4000606E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_SIE_EP8_CR0</name>
<description>The Endpoint8 Control Register</description>
- <addressOffset>0x1CEA</addressOffset>
+ <addressOffset>0x4000607E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_BUF_SIZE</name>
<description>Dedicated Endpoint Buffer Size Register</description>
- <addressOffset>0x1CF8</addressOffset>
+ <addressOffset>0x4000608C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP_ACTIVE</name>
<description>Endpoint Active Indication Register</description>
- <addressOffset>0x1CFA</addressOffset>
+ <addressOffset>0x4000608E</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_EP_TYPE</name>
<description>Endpoint Type (IN/OUT) Indication</description>
- <addressOffset>0x1CFB</addressOffset>
+ <addressOffset>0x4000608F</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>USBFS_USB_CLK_EN</name>
<description>USB Block Clock Enable Register</description>
- <addressOffset>0x1D09</addressOffset>
+ <addressOffset>0x4000609D</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
// Command content:
// uint8_t CONFIG_REBOOT
// Response: None.
- CONFIG_REBOOT
+ CONFIG_REBOOT,
+
+ // Command content:
+ // uint8_t CONFIG_INFO
+ // Response:
+ // uint8_t[16] CSD
+ // uint8_t[16] CID
+ CONFIG_SDINFO
} CONFIG_COMMAND;
typedef enum
projects / SCSI2SD-V6.git / commitdiff