]> localhost Git - SCSI2SD-V6.git/commitdiff
Improve self-test function
authorMichael McMaster <michael@codesrc.com>
Sat, 2 Mar 2019 05:13:54 +0000 (15:13 +1000)
committerMichael McMaster <michael@codesrc.com>
Sat, 2 Mar 2019 05:13:54 +0000 (15:13 +1000)
src/firmware/scsiPhy.c

index 5463968a1dea17db8e4ad20a5a715b689483e5c1..48bf535c7b1f017c998ef15c1b82ae487c77e5ac 100755 (executable)
@@ -820,76 +820,31 @@ int scsiSelfTest()
 \r
        int result = 0;\r
 \r
-       // TEST DBx\r
-       // TODO test DBp\r
-       int i;\r
-       for (i = 0; i < 256; ++i)\r
+       *SCSI_CTRL_DBX = 0;\r
+       busSettleDelay();\r
+       if ((*SCSI_STS_DBX & 0xff) != 0)\r
        {\r
-               *SCSI_CTRL_DBX = i;\r
-               busSettleDelay();\r
-               // STS_DBX is 16 bit!\r
-               if ((*SCSI_STS_DBX & 0xff) != (i & 0xff))\r
-               {\r
-                       result |= 1;\r
-               }\r
-               /*if (Lookup_OddParity[i & 0xff] != SCSI_ReadPin(SCSI_In_DBP))\r
-               {\r
-                       result |= 2;\r
-               }*/\r
+               result = 1;\r
        }\r
-       *SCSI_CTRL_DBX = 0;\r
 \r
-       // TEST MSG, CD, IO\r
-       /* TODO\r
+       // TEST DBx\r
+       int i;\r
        for (i = 0; i < 8; ++i)\r
        {\r
-               SCSI_CTL_PHASE_Write(i);\r
-               scsiDeskewDelay();\r
-\r
-               if (SCSI_ReadPin(SCSI_In_MSG) != !!(i & __scsiphase_msg))\r
-               {\r
-                       result |= 4;\r
-               }\r
-               if (SCSI_ReadPin(SCSI_In_CD) != !!(i & __scsiphase_cd))\r
-               {\r
-                       result |= 8;\r
-               }\r
-               if (SCSI_ReadPin(SCSI_In_IO) != !!(i & __scsiphase_io))\r
+               uint8_t data = 1 << i;\r
+               *SCSI_CTRL_DBX = 0;\r
+               busSettleDelay();\r
+               *SCSI_CTRL_DBX = data;\r
+               busSettleDelay();\r
+               // STS_DBX is 16 bit!\r
+               if ((*SCSI_STS_DBX & 0xff) != data)\r
                {\r
-                       result |= 16;\r
+                       result = i + 2;\r
                }\r
        }\r
-       SCSI_CTL_PHASE_Write(0);\r
-\r
-       uint32_t signalsOut[] = { SCSI_Out_ATN, SCSI_Out_BSY, SCSI_Out_RST, SCSI_Out_SEL };\r
-       uint32_t signalsIn[] = { SCSI_Filt_ATN, SCSI_Filt_BSY, SCSI_Filt_RST, SCSI_Filt_SEL };\r
 \r
-       for (i = 0; i < 4; ++i)\r
-       {\r
-               SCSI_SetPin(signalsOut[i]);\r
-               scsiDeskewDelay();\r
-\r
-               int j;\r
-               for (j = 0; j < 4; ++j)\r
-               {\r
-                       if (i == j)\r
-                       {\r
-                               if (! SCSI_ReadFilt(signalsIn[j]))\r
-                               {\r
-                                       result |= 32;\r
-                               }\r
-                       }\r
-                       else\r
-                       {\r
-                               if (SCSI_ReadFilt(signalsIn[j]))\r
-                               {\r
-                                       result |= 32;\r
-                               }\r
-                       }\r
-               }\r
-               SCSI_ClearPin(signalsOut[i]);\r
-       }\r
-       */\r
+       // TODO Test DBP\r
+       *SCSI_CTRL_DBX = 0;\r
 \r
        // FPGA comms test code\r
        for(i = 0; i < 10000; ++i)\r