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+ GNU GENERAL PUBLIC LICENSE
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+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Programs
+
+ If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+ To do so, attach the following notices to the program. It is safest
+to attach them to the start of each source file to most effectively
+state the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+ <one line to give the program's name and a brief idea of what it does.>
+ Copyright (C) <year> <name of author>
+
+ This program is free software: you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation, either version 3 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
+
+ If the program does terminal interaction, make it output a short
+notice like this when it starts in an interactive mode:
+
+ <program> Copyright (C) <year> <name of author>
+ This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+ This is free software, and you are welcome to redistribute it
+ under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, your program's commands
+might be different; for a GUI interface, you would use an "about box".
+
+ You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU GPL, see
+<http://www.gnu.org/licenses/>.
+
+ The GNU General Public License does not permit incorporating your program
+into proprietary programs. If your program is a subroutine library, you
+may consider it more useful to permit linking proprietary applications with
+the library. If this is what you want to do, use the GNU Lesser General
+Public License instead of this License. But first, please read
+<http://www.gnu.org/philosophy/why-not-lgpl.html>.
--- /dev/null
+*.sch~
+*.bak
+*.bak0
+*.pcb.old
+
--- /dev/null
+JUNK =\
+ scsi2sd.pcb.bak \
+ scsi2sd.pcb.bak0 \
+ scsi2sd.pcb.old \
+ scsi2sd.sch~ \
+
+
+SYMBOLS =\
+ symbols/7406.sym \
+ symbols/CY8C53.sym \
+ symbols/FCI-10067847.sym \
+ symbols/LD1117.sym \
+ symbols/MOLEX8981.sym \
+ symbols/SCDA7A0101.sym \
+ symbols/wurth-microsd.sym \
+
+
+all: $(SYMBOLS) scsi2sd.bom scsi2sd.pcb
+
+symbols/%.sym : symbols/%.tragesym
+ tragesym $< $@
+
+scsi2sd.bom : scsi2sd.sch
+ gnetlist -g partslist3 -o scsi2sd.bom scsi2sd.sch
+
+scsi2sd.pcb : scsi2sd.sch
+ gsch2pcb -d symbols scsi2sd.sch
+
+clean:
+ rm $(JUNK)
+
+realclean:
+ rm $(JUNK)
+ rm $(SYMBOLS)
+
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+
+
+$fa = 3; // 4-times as many angles per circle.
+$fs = 0.1; // 0.1mm accuracy
+
+ // A* taken from SFF-8301 Specification for Form Factor of 3.5" Disk Drives
+
+ A3 = 101.6; // width
+ A5 = 3.19; // Distance from side to bottom hole.
+ A6 = 44.45; // Distance from A7 to second bottom hole.
+ A7 = 41.28; // Distance from front to bottom holes.
+ A8 = 28.5; // Distance from front to side holes
+ A9 = 101.60; // Distance between side holes.
+ A10 = 6.35; // Height from base to site holes.
+ A13 = 76.2; // Distance from A7 to third bottom hole.
+ m3HoleRadius=2.667/2; // M3x0.50 minimum hole size (aluminium or softer material)
+ holeBulk=4; // Extra around holes
+ tmp = 10;
+ wallWidth = 1.3;
+ screwWidth = 3;
+ foo = 6;
+ bar = 4; // PSOC MOUNT
+
+PCB_DIFF=90.42; // Clearance line of "fat" via is 10mil from edge.
+PCB_off = (A3 - PCB_DIFF) / 2;
+// from front = A7 + foo = 47.28
+// second = 47.28 + A6 = 91.73. Perfect!
+// Height between board and screw:
+// screwWidth + 1.6mm pcb only = 3 + 1.6 =4.6. Not a problem!
+// Width of PCB vs side hole bulk: 101.6 - 97.5360 = 4.064
+// only 2mm to spare on either side.
+// TODO Made a NOTCH in the PCB to handle this!
+// notch: A8 +- holeBulk = 28.5 - 4, 28.5 + 4 = 24 -> 33mm. 3mm in.
+
+
+
+module hdd_side()
+{
+ difference()
+ {
+ union()
+ {
+ cube([A8 + A9 + tmp, wallWidth, A10 + holeBulk]);
+
+ // Bottom mount 1
+ translate([A7 - (foo / 2), 0, 0])
+ {
+ cube([foo, foo, screwWidth]);
+ }
+
+ // Bottom mount 2
+ translate([A6 + A7 - (foo / 2), 0, 0])
+ {
+ cube([foo, foo, screwWidth]);
+ }
+
+ // Bottom mount 3
+ translate([A13 + A7 - (foo / 2), 0, 0])
+ {
+ cube([foo, foo, screwWidth]);
+ }
+
+ // psoc mount 1
+ translate([A7 - (foo / 2) + foo, 0, 0])
+ {
+ cube([foo, foo + bar, screwWidth]);
+ }
+
+ // psoc mount 2
+ translate([A6 + A7 - (foo / 2) + foo, 0, 0])
+ {
+ cube([foo, foo + bar, screwWidth]);
+ }
+
+ // Extra bulk behind side holes
+ translate([A8, 0, A10])
+ {
+ rotate([270, 0, 0])
+ {
+ cylinder(h=screwWidth, r=holeBulk);
+ }
+ }
+
+ translate([A8 + A9, 0, A10])
+ {
+ rotate([270, 0, 0])
+ {
+ cylinder(h=screwWidth, r=holeBulk);
+ }
+ }
+ }
+
+ // Remove excess material from the side
+ translate([-0.5, -0.5,screwWidth + wallWidth])
+ {
+ cube([A8 - tmp + 0.5, wallWidth + 1, A10 + holeBulk]);
+ }
+ translate([A8 + tmp, -0.5, screwWidth + wallWidth])
+ {
+ cube([A9 - (tmp * 2), wallWidth + 1, A10 + holeBulk]);
+ }
+
+
+ // SIDE HOLES
+
+ translate([A8, -0.5, A10])
+ {
+ rotate([270, 0, 0])
+ {
+ cylinder(h=screwWidth + 1, r=m3HoleRadius);
+ }
+ }
+
+ translate([A8 + A9, -0.5, A10])
+ {
+ rotate([270, 0, 0])
+ {
+ cylinder(h=screwWidth + 1, r=m3HoleRadius);
+ }
+ }
+
+ // BOTTOM HOLES
+ // Bottom hole 1
+ translate([A7, A5, -0.5])
+ {
+ cylinder(h=screwWidth + 1, r = m3HoleRadius);
+ }
+
+ // Bottom hole 2
+ translate([A6 + A7, A5, -0.5])
+ {
+ cylinder(h=screwWidth + 1, r = m3HoleRadius);
+ }
+
+ // Bottom hole 3
+ translate([A13 + A7, A5, -0.5])
+ {
+ cylinder(h=screwWidth + 1, r = m3HoleRadius);
+ }
+
+ // PSOC hole1
+ translate([A7 + foo, PCB_off, -0.5])
+ {
+ cylinder(h=screwWidth + 1, r = m3HoleRadius);
+ }
+ // PSOC hole2
+ translate([A6 + A7 + foo, PCB_off, -0.5])
+ {
+ cylinder(h=screwWidth + 1, r = m3HoleRadius);
+ }
+ }
+}
+
+union()
+{
+ hdd_side();
+ translate([0, A3, 0])
+ {
+ mirror([0, 1, 0])
+ {
+ hdd_side();
+ }
+ }
+
+ cube([wallWidth * 2, A3, wallWidth]);
+
+ translate([A8 + A9 + tmp - wallWidth * 2, 0, 0])
+ {
+ cube([wallWidth * 2, A3, wallWidth]);
+ }
+
+ // Bottom hole 1
+ translate([A7 + foo, foo + bar, 0])
+ {
+ cube([wallWidth * 2, A3 - ((foo + bar) * 2), wallWidth]);
+ }
+
+ // Bottom hole 2
+ translate([A6 + A7 + foo, foo + bar, 0])
+ {
+ cube([wallWidth * 2, A3 - ((foo + bar) * 2), wallWidth]);
+ }
+
+
+ for (i = [0:3])
+ {
+ translate([0, (i * (A3 - wallWidth) / 3), 0])
+ {
+ cube([A8 + A9 + tmp, wallWidth, wallWidth]);
+ }
+ }
+}
--- /dev/null
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--- /dev/null
+(component-library "./symbols")
+
+(load (string-append geda-data-path "/scheme/auto-uref.scm")) ; load the autonumbering script
+(add-hook! add-component-hook auto-uref) ; autonumber when adding a component
+(add-hook! copy-component-hook auto-uref) ; autonumber when copying a component
+
+(output-color "enabled")
--- /dev/null
+G04 start of page 3 for group 1 idx 1 *\r
+G04 Title: (unknown), solder *\r
+G04 Creator: pcb 20110918 *\r
+G04 CreationDate: Wed 02 Oct 2013 12:02:09 GMT UTC *\r
+G04 For: michael *\r
+G04 Format: Gerber/RS-274X *\r
+G04 PCB-Dimensions: 384000 393500 *\r
+G04 PCB-Coordinate-Origin: lower left *\r
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--- /dev/null
+G04 start of page 14 for group -4078 idx -4078 *\r
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--- /dev/null
+G04 start of page 8 for group -4062 idx -4062 *\r
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--- /dev/null
+G04 start of page 2 for group 0 idx 0 *\r
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--- /dev/null
+G04 start of page 9 for group -4079 idx -4079 *\r
+G04 Title: (unknown), topsilk *\r
+G04 Creator: pcb 20110918 *\r
+G04 CreationDate: Wed 02 Oct 2013 12:02:10 GMT UTC *\r
+G04 For: michael *\r
+G04 Format: Gerber/RS-274X *\r
+G04 PCB-Dimensions: 384000 393500 *\r
+G04 PCB-Coordinate-Origin: lower left *\r
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--- /dev/null
+G04 start of page 7 for group -4063 idx -4063 *\r
+G04 Title: (unknown), componentmask *\r
+G04 Creator: pcb 20110918 *\r
+G04 CreationDate: Wed 02 Oct 2013 12:02:10 GMT UTC *\r
+G04 For: michael *\r
+G04 Format: Gerber/RS-274X *\r
+G04 PCB-Dimensions: 384000 393500 *\r
+G04 PCB-Coordinate-Origin: lower left *\r
+%MOIN*%\r
+%FSLAX25Y25*%\r
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--- /dev/null
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--- /dev/null
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--- /dev/null
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+Y207048D02*Y205078D01*\r
+X232484D01*\r
+Y207048D01*\r
+X230516D01*\r
+G37*\r
+G54D105*X226000Y226000D02*Y219500D01*\r
+X221000Y226000D02*Y219500D01*\r
+X216000Y226000D02*Y219500D01*\r
+X211000Y226000D02*Y219500D01*\r
+X206000Y226000D02*Y219500D01*\r
+X201000Y226000D02*Y219500D01*\r
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+Y205500D02*Y199000D01*\r
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+X226000Y205500D02*Y199000D01*\r
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+X143000Y155200D02*Y153800D01*\r
+X314300Y100000D02*X315700D01*\r
+X314300Y108000D02*X315700D01*\r
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+X339750Y148250D02*Y136750D01*\r
+X351250D01*\r
+Y148250D01*\r
+X339750D01*\r
+G37*\r
+G36*\r
+X324750D02*Y136750D01*\r
+X336250D01*\r
+Y148250D01*\r
+X324750D01*\r
+G37*\r
+G36*\r
+X339750Y133250D02*Y121750D01*\r
+X351250D01*\r
+Y133250D01*\r
+X339750D01*\r
+G37*\r
+G36*\r
+X324750D02*Y121750D01*\r
+X336250D01*\r
+Y133250D01*\r
+X324750D01*\r
+G37*\r
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+X329000Y111500D02*Y106000D01*\r
+G54D104*X168500Y64200D02*Y62800D01*\r
+X176500Y64200D02*Y62800D01*\r
+X168439Y74952D02*Y73552D01*\r
+X176439Y74952D02*Y73552D01*\r
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+X177843Y18902D02*Y15162D01*\r
+X167607Y18902D02*Y15162D01*\r
+X175284Y18902D02*Y15162D01*\r
+X170166Y18902D02*Y15162D01*\r
+G54D110*X159536Y16540D02*X161504D01*\r
+X183945D02*X185914D01*\r
+G54D111*X157764Y6697D02*Y6303D01*\r
+G54D107*G36*\r
+X164260Y10240D02*Y2760D01*\r
+X171740D01*\r
+Y10240D01*\r
+X164260D01*\r
+G37*\r
+G36*\r
+X173709D02*Y2760D01*\r
+X181189D01*\r
+Y10240D01*\r
+X173709D01*\r
+G37*\r
+G54D111*X187685Y6697D02*Y6303D01*\r
+G54D112*X157000Y34000D02*Y33000D01*\r
+X145000Y34000D02*Y33000D01*\r
+X20500Y321000D02*X21500D01*\r
+X20500Y309000D02*X21500D01*\r
+G54D104*X343800Y71500D02*X345200D01*\r
+X343800Y79500D02*X345200D01*\r
+X333300Y71500D02*X334700D01*\r
+X333300Y79500D02*X334700D01*\r
+X322800Y71500D02*X324200D01*\r
+X322800Y79500D02*X324200D01*\r
+X240500Y74700D02*Y73300D01*\r
+X232500Y74700D02*Y73300D01*\r
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+X301300Y71500D02*X302700D01*\r
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+X290300Y79500D02*X291700D01*\r
+X287500Y169700D02*Y168300D01*\r
+X279500Y169700D02*Y168300D01*\r
+G54D107*G36*\r
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+X193984D01*\r
+Y78484D01*\r
+X192016D01*\r
+G37*\r
+G36*\r
+Y82422D02*Y80452D01*\r
+X193984D01*\r
+Y82422D01*\r
+X192016D01*\r
+G37*\r
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+X247224Y25276D02*Y22520D01*\r
+X242894Y23701D02*Y20945D01*\r
+X238563Y22913D02*Y20157D01*\r
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+X229902Y22913D02*Y20157D01*\r
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+X221240Y23701D02*Y20945D01*\r
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+X351750D01*\r
+Y260750D01*\r
+X340250D01*\r
+G37*\r
+G36*\r
+X325250D02*Y249250D01*\r
+X336750D01*\r
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+G37*\r
+G36*\r
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+Y245750D01*\r
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+G36*\r
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+X336750D01*\r
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+X325250D01*\r
+G37*\r
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+X20500Y234894D02*Y234107D01*\r
+Y251823D02*Y251036D01*\r
+M02*\r
--- /dev/null
+.START
+..device value footprint quantity refdes
+7406 unknown SO14 3 U3 U4 U5
+CAPACITOR 100nF cap_0402 11 C10 C11 C17 C19 C21 C22 C23 C24 C28 C3 C9
+CAPACITOR 10uF SMD_SIMPLE 80 50 8 C1 C12 C13 C14 C2 C4 C5 C7
+CAPACITOR 1uF cap_0402 4 C20 C26 C27 C8
+CY8C53 unknown TQFP100_14 1 U1
+DIODE unknown diode-DO-214AA-SMB 3 D1 D2 D3
+FUSE 1.5A Hold SMD_SIMPLE 120 60 1 F1
+FUSE 500mA Hold SMD_SIMPLE 120 60 1 F2
+HEADER10 unknown FTSH-105-01-L-DV-K 1 J4
+HEADER50 unknown HEADER50_2_RA 1 J2
+JUMPER unknown HEADER2_2 1 J3
+LD1117 unknown DPAK 2 U2 U6
+LED unknown SMD_DIODE 80 50 1 LED1
+MOLEX8981 unknown MOLEX8981 1 J1
+RESISTOR 10K SMD_SIMPLE 80 50 7 R10 R11 R12 R6 R7 R8 R9
+RESISTOR 1600 SMD_SIMPLE 80 50 1 R3
+RESISTOR 22Ω SMD_SIMPLE 80 50 2 R4 R5
+RESISTORPACK_10 unknown SIP10 2 R1 R2
+USB unknown fci-10118192-0001LF 1 J5
+wurth-693071010811 unknown wurth-microsd 1 J6
+.END
--- /dev/null
+# Pin name action command file
+
+# Start of element J6
+ChangePinName(J6, 10, \_CD\_)
+ChangePinName(J6, 9, GND)
+ChangePinName(J6, 8, DAT1)
+ChangePinName(J6, 7, DAT0)
+ChangePinName(J6, 6, GND)
+ChangePinName(J6, 5, CLK)
+ChangePinName(J6, 4, Vcc)
+ChangePinName(J6, 3, CMD)
+ChangePinName(J6, 2, DAT3)
+ChangePinName(J6, 1, DAT2)
+
+# Start of element R2
+ChangePinName(R2, 10, 10)
+ChangePinName(R2, 9, 9)
+ChangePinName(R2, 8, 8)
+ChangePinName(R2, 7, 7)
+ChangePinName(R2, 6, 6)
+ChangePinName(R2, 1, 1)
+ChangePinName(R2, 5, 5)
+ChangePinName(R2, 4, 4)
+ChangePinName(R2, 3, 3)
+ChangePinName(R2, 2, 2)
+
+# Start of element R1
+ChangePinName(R1, 10, 10)
+ChangePinName(R1, 9, 9)
+ChangePinName(R1, 8, 8)
+ChangePinName(R1, 7, 7)
+ChangePinName(R1, 6, 6)
+ChangePinName(R1, 1, 1)
+ChangePinName(R1, 5, 5)
+ChangePinName(R1, 4, 4)
+ChangePinName(R1, 3, 3)
+ChangePinName(R1, 2, 2)
+
+# Start of element R5
+ChangePinName(R5, 1, 1)
+ChangePinName(R5, 2, 2)
+
+# Start of element R4
+ChangePinName(R4, 1, 1)
+ChangePinName(R4, 2, 2)
+
+# Start of element J5
+ChangePinName(J5, 5, GND)
+ChangePinName(J5, 1, VCC)
+ChangePinName(J5, 2, D-)
+ChangePinName(J5, 3, D+)
+ChangePinName(J5, 4, ID)
+
+# Start of element D3
+ChangePinName(D3, 1, cathode)
+ChangePinName(D3, 2, anode)
+
+# Start of element F2
+ChangePinName(F2, 2, 2)
+ChangePinName(F2, 1, 1)
+
+# Start of element F1
+ChangePinName(F1, 2, 2)
+ChangePinName(F1, 1, 1)
+
+# Start of element D1
+ChangePinName(D1, 1, cathode)
+ChangePinName(D1, 2, anode)
+
+# Start of element D2
+ChangePinName(D2, 1, cathode)
+ChangePinName(D2, 2, anode)
+
+# Start of element J3
+ChangePinName(J3, 1, 1)
+ChangePinName(J3, 2, 2)
+
+# Start of element C14
+ChangePinName(C14, 2, 2)
+ChangePinName(C14, 1, 1)
+
+# Start of element C4
+ChangePinName(C4, 2, 2)
+ChangePinName(C4, 1, 1)
+
+# Start of element C7
+ChangePinName(C7, 2, 2)
+ChangePinName(C7, 1, 1)
+
+# Start of element U6
+ChangePinName(U6, 3, IN)
+ChangePinName(U6, 2, OUT)
+ChangePinName(U6, 1, GND)
+
+# Start of element U2
+ChangePinName(U2, 3, IN)
+ChangePinName(U2, 2, OUT)
+ChangePinName(U2, 1, GND)
+
+# Start of element C12
+ChangePinName(C12, 2, 2)
+ChangePinName(C12, 1, 1)
+
+# Start of element C13
+ChangePinName(C13, 2, 2)
+ChangePinName(C13, 1, 1)
+
+# Start of element C5
+ChangePinName(C5, 2, 2)
+ChangePinName(C5, 1, 1)
+
+# Start of element C8
+ChangePinName(C8, 2, 2)
+ChangePinName(C8, 1, 1)
+
+# Start of element U1
+ChangePinName(U1, 76, P0[4])
+ChangePinName(U1, 77, P0[5])
+ChangePinName(U1, 78, P0[6])
+ChangePinName(U1, 79, P0[7])
+ChangePinName(U1, 80, P4[2])
+ChangePinName(U1, 81, P4[3])
+ChangePinName(U1, 82, P4[4])
+ChangePinName(U1, 83, P4[5])
+ChangePinName(U1, 84, P4[6])
+ChangePinName(U1, 85, P4[7])
+ChangePinName(U1, 86, VCCD)
+ChangePinName(U1, 87, VSSD)
+ChangePinName(U1, 88, VDDD)
+ChangePinName(U1, 89, P6[0])
+ChangePinName(U1, 90, P6[1])
+ChangePinName(U1, 91, P6[2])
+ChangePinName(U1, 92, P6[3])
+ChangePinName(U1, 93, P15[4])
+ChangePinName(U1, 94, P15[5])
+ChangePinName(U1, 95, P2[0])
+ChangePinName(U1, 96, P2[1])
+ChangePinName(U1, 97, P2[2])
+ChangePinName(U1, 98, P2[3])
+ChangePinName(U1, 99, P2[4])
+ChangePinName(U1, 100, VDDIO2)
+ChangePinName(U1, 51, P3[6])
+ChangePinName(U1, 52, P3[7])
+ChangePinName(U1, 53, P12[0])
+ChangePinName(U1, 54, P12[1])
+ChangePinName(U1, 55, "XO XTAL P15[2],KHZ")
+ChangePinName(U1, 56, "XI XTAL P15[3],KHZ")
+ChangePinName(U1, 57, NC)
+ChangePinName(U1, 58, NC)
+ChangePinName(U1, 59, NC)
+ChangePinName(U1, 60, NC)
+ChangePinName(U1, 61, NC)
+ChangePinName(U1, 62, NC)
+ChangePinName(U1, 63, VCCA)
+ChangePinName(U1, 64, VSSA)
+ChangePinName(U1, 65, VDDA)
+ChangePinName(U1, 66, VSSD)
+ChangePinName(U1, 67, P12[2])
+ChangePinName(U1, 68, P12[3])
+ChangePinName(U1, 69, P4[0])
+ChangePinName(U1, 70, P4[1])
+ChangePinName(U1, 71, P0[0])
+ChangePinName(U1, 72, P0[1])
+ChangePinName(U1, 73, P0[2])
+ChangePinName(U1, 74, P0[3])
+ChangePinName(U1, 75, VDDIO0)
+ChangePinName(U1, 50, VDDIO3)
+ChangePinName(U1, 49, P3[5])
+ChangePinName(U1, 48, P3[4])
+ChangePinName(U1, 47, P3[3])
+ChangePinName(U1, 46, P3[2])
+ChangePinName(U1, 45, P3[1])
+ChangePinName(U1, 44, P3[0])
+ChangePinName(U1, 43, MHZ XTAL XI)
+ChangePinName(U1, 42, MHZ XTAL XO)
+ChangePinName(U1, 41, NC)
+ChangePinName(U1, 40, NC)
+ChangePinName(U1, 39, VCCD)
+ChangePinName(U1, 38, VSSD)
+ChangePinName(U1, 37, VDDD)
+ChangePinName(U1, 36, "SWDCK,USB D-")
+ChangePinName(U1, 35, "SWDIO,USB D+")
+ChangePinName(U1, 34, P5[7])
+ChangePinName(U1, 33, P5[6])
+ChangePinName(U1, 32, P5[5])
+ChangePinName(U1, 31, P5[4])
+ChangePinName(U1, 30, P12[7])
+ChangePinName(U1, 29, P12[6])
+ChangePinName(U1, 28, P1[7])
+ChangePinName(U1, 27, P1[6])
+ChangePinName(U1, 26, VDDIO1)
+ChangePinName(U1, 25, P1[5])
+ChangePinName(U1, 24, P1[4])
+ChangePinName(U1, 23, "SWV,P1[3]")
+ChangePinName(U1, 22, P1[2])
+ChangePinName(U1, 21, "SWDCK,P1[1]")
+ChangePinName(U1, 20, "SWDIO,P1[0]")
+ChangePinName(U1, 19, P5[3])
+ChangePinName(U1, 18, P5[2])
+ChangePinName(U1, 17, P5[1])
+ChangePinName(U1, 16, P5[0])
+ChangePinName(U1, 15, \_XRES\_)
+ChangePinName(U1, 14, VSSD)
+ChangePinName(U1, 13, VSSD)
+ChangePinName(U1, 12, VSSD)
+ChangePinName(U1, 11, NC)
+ChangePinName(U1, 10, VSSD)
+ChangePinName(U1, 9, P6[7])
+ChangePinName(U1, 8, P6[6])
+ChangePinName(U1, 7, P6[5])
+ChangePinName(U1, 6, P6[4])
+ChangePinName(U1, 5, P12[5])
+ChangePinName(U1, 4, P12[4])
+ChangePinName(U1, 3, P2[7])
+ChangePinName(U1, 2, P2[6])
+ChangePinName(U1, 1, P2[5])
+
+# Start of element R12
+ChangePinName(R12, 1, 1)
+ChangePinName(R12, 2, 2)
+
+# Start of element R11
+ChangePinName(R11, 1, 1)
+ChangePinName(R11, 2, 2)
+
+# Start of element R10
+ChangePinName(R10, 1, 1)
+ChangePinName(R10, 2, 2)
+
+# Start of element R9
+ChangePinName(R9, 1, 1)
+ChangePinName(R9, 2, 2)
+
+# Start of element R8
+ChangePinName(R8, 1, 1)
+ChangePinName(R8, 2, 2)
+
+# Start of element R7
+ChangePinName(R7, 1, 1)
+ChangePinName(R7, 2, 2)
+
+# Start of element R6
+ChangePinName(R6, 1, 1)
+ChangePinName(R6, 2, 2)
+
+# Start of element C26
+ChangePinName(C26, 2, 2)
+ChangePinName(C26, 1, 1)
+
+# Start of element C20
+ChangePinName(C20, 2, 2)
+ChangePinName(C20, 1, 1)
+
+# Start of element C27
+ChangePinName(C27, 2, 2)
+ChangePinName(C27, 1, 1)
+
+# Start of element C19
+ChangePinName(C19, 2, 2)
+ChangePinName(C19, 1, 1)
+
+# Start of element C24
+ChangePinName(C24, 2, 2)
+ChangePinName(C24, 1, 1)
+
+# Start of element C23
+ChangePinName(C23, 2, 2)
+ChangePinName(C23, 1, 1)
+
+# Start of element C17
+ChangePinName(C17, 2, 2)
+ChangePinName(C17, 1, 1)
+
+# Start of element C21
+ChangePinName(C21, 2, 2)
+ChangePinName(C21, 1, 1)
+
+# Start of element C28
+ChangePinName(C28, 2, 2)
+ChangePinName(C28, 1, 1)
+
+# Start of element R3
+ChangePinName(R3, 1, 1)
+ChangePinName(R3, 2, 2)
+
+# Start of element LED1
+ChangePinName(LED1, 2, K)
+ChangePinName(LED1, 1, A)
+
+# Start of element C11
+ChangePinName(C11, 2, 2)
+ChangePinName(C11, 1, 1)
+
+# Start of element C10
+ChangePinName(C10, 2, 2)
+ChangePinName(C10, 1, 1)
+
+# Start of element C3
+ChangePinName(C3, 2, 2)
+ChangePinName(C3, 1, 1)
+
+# Start of element C9
+ChangePinName(C9, 2, 2)
+ChangePinName(C9, 1, 1)
+
+# Start of element J4
+ChangePinName(J4, 6, 6)
+ChangePinName(J4, 7, 7)
+ChangePinName(J4, 8, 8)
+ChangePinName(J4, 9, 9)
+ChangePinName(J4, 10, 10)
+ChangePinName(J4, 5, 5)
+ChangePinName(J4, 1, 1)
+ChangePinName(J4, 4, 4)
+ChangePinName(J4, 3, 3)
+ChangePinName(J4, 2, 2)
+
+# Start of element C1
+ChangePinName(C1, 2, 2)
+ChangePinName(C1, 1, 1)
+
+# Start of element U5
+ChangePinName(U5, 8, \_Y3\_)
+ChangePinName(U5, 9, A3)
+ChangePinName(U5, 10, \_Y4\_)
+ChangePinName(U5, 11, A4)
+ChangePinName(U5, 12, \_Y5\_)
+ChangePinName(U5, 13, A5)
+ChangePinName(U5, 14, Vcc)
+ChangePinName(U5, 7, GND)
+ChangePinName(U5, 6, \_Y2\_)
+ChangePinName(U5, 5, A2)
+ChangePinName(U5, 4, \_Y1\_)
+ChangePinName(U5, 3, A1)
+ChangePinName(U5, 2, \_Y0\_)
+ChangePinName(U5, 1, A0)
+
+# Start of element U4
+ChangePinName(U4, 8, \_Y3\_)
+ChangePinName(U4, 9, A3)
+ChangePinName(U4, 10, \_Y4\_)
+ChangePinName(U4, 11, A4)
+ChangePinName(U4, 12, \_Y5\_)
+ChangePinName(U4, 13, A5)
+ChangePinName(U4, 14, Vcc)
+ChangePinName(U4, 7, GND)
+ChangePinName(U4, 6, \_Y2\_)
+ChangePinName(U4, 5, A2)
+ChangePinName(U4, 4, \_Y1\_)
+ChangePinName(U4, 3, A1)
+ChangePinName(U4, 2, \_Y0\_)
+ChangePinName(U4, 1, A0)
+
+# Start of element U3
+ChangePinName(U3, 8, \_Y3\_)
+ChangePinName(U3, 9, A3)
+ChangePinName(U3, 10, \_Y4\_)
+ChangePinName(U3, 11, A4)
+ChangePinName(U3, 12, \_Y5\_)
+ChangePinName(U3, 13, A5)
+ChangePinName(U3, 14, Vcc)
+ChangePinName(U3, 7, GND)
+ChangePinName(U3, 6, \_Y2\_)
+ChangePinName(U3, 5, A2)
+ChangePinName(U3, 4, \_Y1\_)
+ChangePinName(U3, 3, A1)
+ChangePinName(U3, 2, \_Y0\_)
+ChangePinName(U3, 1, A0)
+
+# Start of element C2
+ChangePinName(C2, 2, 2)
+ChangePinName(C2, 1, 1)
+
+# Start of element C22
+ChangePinName(C22, 2, 2)
+ChangePinName(C22, 1, 1)
+
+# Start of element J1
+ChangePinName(J1, 4, +5V)
+ChangePinName(J1, 3, GND)
+ChangePinName(J1, 2, GND)
+ChangePinName(J1, 1, +12V)
+
+# Start of element J2
+ChangePinName(J2, 50, 50)
+ChangePinName(J2, 49, 49)
+ChangePinName(J2, 48, 48)
+ChangePinName(J2, 47, 47)
+ChangePinName(J2, 46, 46)
+ChangePinName(J2, 45, 45)
+ChangePinName(J2, 44, 44)
+ChangePinName(J2, 43, 43)
+ChangePinName(J2, 42, 42)
+ChangePinName(J2, 41, 41)
+ChangePinName(J2, 40, 40)
+ChangePinName(J2, 39, 39)
+ChangePinName(J2, 38, 38)
+ChangePinName(J2, 37, 37)
+ChangePinName(J2, 36, 36)
+ChangePinName(J2, 35, 35)
+ChangePinName(J2, 34, 34)
+ChangePinName(J2, 33, 33)
+ChangePinName(J2, 32, 32)
+ChangePinName(J2, 31, 31)
+ChangePinName(J2, 30, 30)
+ChangePinName(J2, 29, 29)
+ChangePinName(J2, 28, 28)
+ChangePinName(J2, 27, 27)
+ChangePinName(J2, 26, 26)
+ChangePinName(J2, 25, 25)
+ChangePinName(J2, 24, 24)
+ChangePinName(J2, 23, 23)
+ChangePinName(J2, 22, 22)
+ChangePinName(J2, 21, 21)
+ChangePinName(J2, 20, 20)
+ChangePinName(J2, 19, 19)
+ChangePinName(J2, 18, 18)
+ChangePinName(J2, 17, 17)
+ChangePinName(J2, 16, 16)
+ChangePinName(J2, 15, 15)
+ChangePinName(J2, 14, 14)
+ChangePinName(J2, 13, 13)
+ChangePinName(J2, 12, 12)
+ChangePinName(J2, 11, 11)
+ChangePinName(J2, 10, 10)
+ChangePinName(J2, 9, 9)
+ChangePinName(J2, 8, 8)
+ChangePinName(J2, 7, 7)
+ChangePinName(J2, 6, 6)
+ChangePinName(J2, 5, 5)
+ChangePinName(J2, 4, 4)
+ChangePinName(J2, 3, 3)
+ChangePinName(J2, 2, 2)
+ChangePinName(J2, 1, 1)
--- /dev/null
+unnamed_net28 R5-1 J5-2
+unnamed_net27 R4-1 J5-3
+unnamed_net26 J5-4
+unnamed_net25 D3-2 F2-2
+unnamed_net24 J5-1 F2-1
+unnamed_net23 D1-2 J3-1
+drive_5V F1-2 D2-2 J3-2
+unnamed_net22 R1-1 R2-1 C14-2 C7-2 U2-2
+unnamed_net21 U1-55
+unnamed_net20 U1-42
+unnamed_net19 R5-2 U1-36
+unnamed_net18 R4-2 U1-35
+unnamed_net17 U1-25
+unnamed_net16 U1-24
+unnamed_net15 U1-22
+unnamed_net14 U1-11
+SD_DAT2 J6-1 U1-49 R12-1
+\_SD_CS\_ J6-2 U1-48 R11-1
+SD_MOSI J6-3 U1-47 R10-1
+\_SD_CD\_ J6-10 U1-51 R9-1
+SD_SCK J6-5 U1-46 R8-1
+SD_MISO J6-7 U1-45 R7-1
+SD_DAT1 J6-8 U1-44 R6-1
+unnamed_net13 U1-86 U1-39 C20-2
+unnamed_net12 U1-63 C27-2
+unnamed_net11 U1-68 LED1-2
+unnamed_net10 R3-1 LED1-1
+unnamed_net9 U1-23 J4-6
+unnamed_net8 J4-8
+unnamed_net7 U1-15 J4-10
+unnamed_net6 U1-21 J4-4
+unnamed_net5 U1-20 J4-2
+DB0 U1-92 U5-9
+DB2 U1-90 U5-11
+DB4 U1-85 U5-13
+DB1 U1-91 U5-5
+DB3 U1-89 U5-3
+DB5 U1-84 U5-1
+DB6 U1-83 U4-9
+DBP U1-81 U4-11
+BSY U1-79 U4-13
+DB7 U1-82 U4-5
+ATN U1-80 U4-3
+ACK U1-78 U4-1
+RST U1-77 U3-9
+SEL U1-74 U3-11
+REQ U1-72 U3-13
+MSG U1-76 U3-5
+C/D U1-73 U3-3
+I/O U1-71 U3-1
+5V D3-1 U6-3 C12-2 C26-2 U1-65 C24-2 U1-88 C8-2 C19-2 U1-37 C23-2 U1-100 C17-2 U1-75 C21-2 R3-2 U1-26 C9-2 J4-1 C11-2 U5-14 C10-2 U4-14 C3-2 U3-14 D2-1 C4-2 C2-2
+3.3V U6-2 C13-2 R12-2 R11-2 R10-2 R9-2 R8-2 R7-2 R6-2 U1-50 C28-2 J6-4 C22-2
+unnamed_net4 F1-1 J1-4
+unnamed_net3 J1-1
+\_I/O\_ R2-2 U1-19 U3-2 J2-50
+\_REQ\_ R2-3 U1-18 U3-12 J2-48
+\_C/D\_ R2-4 U1-17 U3-4 J2-46
+\_SEL\_ R2-5 U1-16 U3-10 J2-44
+\_MSG\_ R2-6 U1-9 U3-6 J2-42
+\_RST\_ R2-7 U1-8 U3-8 J2-40
+\_ACK\_ R2-8 U1-7 U4-2 J2-38
+\_BSY\_ R2-9 U1-6 U4-12 J2-36
+\_ATN\_ R2-10 U1-5 U4-4 J2-32
+unnamed_net2 D1-1 U2-3 C5-2 C1-2 J2-26
+unnamed_net1 J2-25
+\_DBP\_ R1-2 U1-95 U4-10 J2-18
+\_DB7\_ R1-3 U1-96 U4-6 J2-16
+\_DB6\_ R1-4 U1-97 U4-8 J2-14
+\_DB5\_ R1-5 U1-98 U5-2 J2-12
+\_DB4\_ R1-6 U1-99 U5-12 J2-10
+\_DB3\_ R1-7 U1-1 U5-4 J2-8
+\_DB2\_ R1-8 U1-2 U5-10 J2-6
+\_DB1\_ R1-9 U1-3 U5-6 J2-4
+\_DB0\_ R1-10 U1-4 U5-8 J2-2
+GND J6-9 J6-6 J5-5 C14-1 C4-1 C7-1 U6-1 U2-1 C12-1 C13-1 C5-1 C8-1 U1-87 U1-93 U1-94 U1-52 U1-53 U1-54 U1-56 U1-57 U1-58 U1-59 U1-60 U1-61 U1-62 U1-64 U1-66 U1-67 U1-69 U1-70 U1-43 U1-41 U1-40 U1-38 \
+ U1-34 U1-33 U1-32 U1-31 U1-30 U1-29 U1-28 U1-27 U1-14 U1-13 U1-12 U1-10 C26-1 C20-1 C27-1 C19-1 C24-1 C23-1 C17-1 C21-1 C28-1 C11-1 C10-1 C3-1 C9-1 J4-7 J4-9 J4-5 J4-3 C1-1 U5-7 U4-7 U3-7 C2-1 C22-1 \
+ J1-3 J1-2 J2-34 J2-30 J2-28 J2-22 J2-24 J2-20 J2-49 J2-47 J2-45 J2-43 J2-41 J2-39 J2-37 J2-35 J2-33 J2-31 J2-29 J2-27 J2-19 J2-17 J2-15 J2-13 J2-11 J2-9 J2-7 J2-5 J2-3 J2-23 J2-21 J2-1
--- /dev/null
+# release: pcb 20110918
+
+# To read pcb files, the pcb version (or the git source date) must be >= the file version
+FileVersion[20070407]
+
+PCB["" 384000 393500]
+
+Grid[500.0 0 0 1]
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+Attribute("PCB::grid::unit" "mil")
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+ )
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+ Pad[5000 -13500 5000 -7000 2000 1800 3000 "A1" "3" "square"]
+ Pad[0 -13500 0 -7000 2000 1800 3000 "_Y1_" "4" "square"]
+ Pad[-5000 -13500 -5000 -7000 2000 1800 3000 "A2" "5" "square"]
+ Pad[-10000 -13500 -10000 -7000 2000 1800 3000 "_Y2_" "6" "square"]
+ Pad[-15000 -13500 -15000 -7000 2000 1800 3000 "GND" "7" "square"]
+ Pad[-15000 7000 -15000 13500 2000 1800 3000 "_Y3_" "8" "square,edge2"]
+ Pad[-10000 7000 -10000 13500 2000 1800 3000 "A3" "9" "square,edge2"]
+ Pad[-5000 7000 -5000 13500 2000 1800 3000 "_Y4_" "10" "square,edge2"]
+ Pad[0 7000 0 13500 2000 1800 3000 "A4" "11" "square,edge2"]
+ Pad[5000 7000 5000 13500 2000 1800 3000 "_Y5_" "12" "square,edge2"]
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+
+ )
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+ )
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+ Pad[0 -13500 0 -7000 2000 1800 3000 "_Y1_" "4" "square"]
+ Pad[-5000 -13500 -5000 -7000 2000 1800 3000 "A2" "5" "square"]
+ Pad[-10000 -13500 -10000 -7000 2000 1800 3000 "_Y2_" "6" "square"]
+ Pad[-15000 -13500 -15000 -7000 2000 1800 3000 "GND" "7" "square"]
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+ Pad[-5000 7000 -5000 13500 2000 1800 3000 "_Y4_" "10" "square,edge2"]
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+ )
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+ )
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+ Pad[-35008 -5906 -30110 -5906 1102 3000 1402 "VSSD" "10" "square"]
+ Pad[-35008 -3937 -30110 -3937 1102 3000 1402 "NC" "11" "square"]
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+ Pad[-35008 0 -30110 0 1102 3000 1402 "VSSD" "13" "square"]
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+ Pad[-35008 3937 -30110 3937 1102 3000 1402 "_XRES_" "15" "square"]
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+ Pad[-35008 9842 -30110 9842 1102 3000 1402 "P5[2]" "18" "square"]
+ Pad[-35008 11811 -30110 11811 1102 3000 1402 "P5[3]" "19" "square"]
+ Pad[-35008 13779 -30110 13779 1102 3000 1402 "SWDIO,P1[0]" "20" "square"]
+ Pad[-35008 15748 -30110 15748 1102 3000 1402 "SWDCK,P1[1]" "21" "square"]
+ Pad[-35008 17716 -30110 17716 1102 3000 1402 "P1[2]" "22" "square"]
+ Pad[-35008 19685 -30110 19685 1102 3000 1402 "SWV,P1[3]" "23" "square"]
+ Pad[-35008 21653 -30110 21653 1102 3000 1402 "P1[4]" "24" "square"]
+ Pad[-35008 23622 -30110 23622 1102 3000 1402 "P1[5]" "25" "square"]
+ Pad[-23622 30110 -23622 35008 1102 3000 1402 "VDDIO1" "26" "square,octagon,edge2"]
+ Pad[-21654 30110 -21654 35008 1102 3000 1402 "P1[6]" "27" "square,octagon,edge2"]
+ Pad[-19685 30110 -19685 35008 1102 3000 1402 "P1[7]" "28" "square,octagon,edge2"]
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+ Pad[-15748 30110 -15748 35008 1102 3000 1402 "P12[7]" "30" "square,octagon,edge2"]
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+ Pad[-11811 30110 -11811 35008 1102 3000 1402 "P5[5]" "32" "square,octagon,edge2"]
+ Pad[-9843 30110 -9843 35008 1102 3000 1402 "P5[6]" "33" "square,octagon,edge2"]
+ Pad[-7874 30110 -7874 35008 1102 3000 1402 "P5[7]" "34" "square,octagon,edge2"]
+ Pad[-5906 30110 -5906 35008 1102 3000 1402 "SWDIO,USB D+" "35" "square,octagon,edge2"]
+ Pad[-3937 30110 -3937 35008 1102 3000 1402 "SWDCK,USB D-" "36" "square,octagon,edge2"]
+ Pad[-1969 30110 -1969 35008 1102 3000 1402 "VDDD" "37" "square,octagon,edge2"]
+ Pad[0 30110 0 35008 1102 3000 1402 "VSSD" "38" "square,octagon,edge2"]
+ Pad[1968 30110 1968 35008 1102 3000 1402 "VCCD" "39" "square,octagon,edge2"]
+ Pad[3937 30110 3937 35008 1102 3000 1402 "NC" "40" "square,octagon,edge2"]
+ Pad[5905 30110 5905 35008 1102 3000 1402 "NC" "41" "square,octagon,edge2"]
+ Pad[7874 30110 7874 35008 1102 3000 1402 "MHZ XTAL XO" "42" "square,octagon,edge2"]
+ Pad[9842 30110 9842 35008 1102 3000 1402 "MHZ XTAL XI" "43" "square,octagon,edge2"]
+ Pad[11811 30110 11811 35008 1102 3000 1402 "P3[0]" "44" "square,octagon,edge2"]
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+ Pad[15748 30110 15748 35008 1102 3000 1402 "P3[2]" "46" "square,octagon,edge2"]
+ Pad[17716 30110 17716 35008 1102 3000 1402 "P3[3]" "47" "square,octagon,edge2"]
+ Pad[19685 30110 19685 35008 1102 3000 1402 "P3[4]" "48" "square,octagon,edge2"]
+ Pad[21653 30110 21653 35008 1102 3000 1402 "P3[5]" "49" "square,octagon,edge2"]
+ Pad[23622 30110 23622 35008 1102 3000 1402 "VDDIO3" "50" "square,octagon,edge2"]
+ Pad[30110 23622 35008 23622 1102 3000 1402 "P3[6]" "51" "square,edge2"]
+ Pad[30110 21654 35008 21654 1102 3000 1402 "P3[7]" "52" "square,edge2"]
+ Pad[30110 19685 35008 19685 1102 3000 1402 "P12[0]" "53" "square,edge2"]
+ Pad[30110 17717 35008 17717 1102 3000 1402 "P12[1]" "54" "square,edge2"]
+ Pad[30110 15748 35008 15748 1102 3000 1402 "XO XTAL P15[2],KHZ" "55" "square,edge2"]
+ Pad[30110 13780 35008 13780 1102 3000 1402 "XI XTAL P15[3],KHZ" "56" "square,edge2"]
+ Pad[30110 11811 35008 11811 1102 3000 1402 "NC" "57" "square,edge2"]
+ Pad[30110 9843 35008 9843 1102 3000 1402 "NC" "58" "square,edge2"]
+ Pad[30110 7874 35008 7874 1102 3000 1402 "NC" "59" "square,edge2"]
+ Pad[30110 5906 35008 5906 1102 3000 1402 "NC" "60" "square,edge2"]
+ Pad[30110 3937 35008 3937 1102 3000 1402 "NC" "61" "square,edge2"]
+ Pad[30110 1969 35008 1969 1102 3000 1402 "NC" "62" "square,edge2"]
+ Pad[30110 0 35008 0 1102 3000 1402 "VCCA" "63" "square,edge2"]
+ Pad[30110 -1968 35008 -1968 1102 3000 1402 "VSSA" "64" "square,edge2"]
+ Pad[30110 -3937 35008 -3937 1102 3000 1402 "VDDA" "65" "square,edge2"]
+ Pad[30110 -5905 35008 -5905 1102 3000 1402 "VSSD" "66" "square,edge2"]
+ Pad[30110 -7874 35008 -7874 1102 3000 1402 "P12[2]" "67" "square,edge2"]
+ Pad[30110 -9842 35008 -9842 1102 3000 1402 "P12[3]" "68" "square,edge2"]
+ Pad[30110 -11811 35008 -11811 1102 3000 1402 "P4[0]" "69" "square,edge2"]
+ Pad[30110 -13779 35008 -13779 1102 3000 1402 "P4[1]" "70" "square,edge2"]
+ Pad[30110 -15748 35008 -15748 1102 3000 1402 "P0[0]" "71" "square,edge2"]
+ Pad[30110 -17716 35008 -17716 1102 3000 1402 "P0[1]" "72" "square,edge2"]
+ Pad[30110 -19685 35008 -19685 1102 3000 1402 "P0[2]" "73" "square,edge2"]
+ Pad[30110 -21653 35008 -21653 1102 3000 1402 "P0[3]" "74" "square,edge2"]
+ Pad[30110 -23622 35008 -23622 1102 3000 1402 "VDDIO0" "75" "square,edge2"]
+ Pad[23622 -35008 23622 -30110 1102 3000 1402 "P0[4]" "76" "square,octagon"]
+ Pad[21654 -35008 21654 -30110 1102 3000 1402 "P0[5]" "77" "square,octagon"]
+ Pad[19685 -35008 19685 -30110 1102 3000 1402 "P0[6]" "78" "square,octagon"]
+ Pad[17717 -35008 17717 -30110 1102 3000 1402 "P0[7]" "79" "square,octagon"]
+ Pad[15748 -35008 15748 -30110 1102 3000 1402 "P4[2]" "80" "square,octagon"]
+ Pad[13780 -35008 13780 -30110 1102 3000 1402 "P4[3]" "81" "square,octagon"]
+ Pad[11811 -35008 11811 -30110 1102 3000 1402 "P4[4]" "82" "square,octagon"]
+ Pad[9843 -35008 9843 -30110 1102 3000 1402 "P4[5]" "83" "square,octagon"]
+ Pad[7874 -35008 7874 -30110 1102 3000 1402 "P4[6]" "84" "square,octagon"]
+ Pad[5906 -35008 5906 -30110 1102 3000 1402 "P4[7]" "85" "square,octagon"]
+ Pad[3937 -35008 3937 -30110 1102 3000 1402 "VCCD" "86" "square,octagon"]
+ Pad[1969 -35008 1969 -30110 1102 3000 1402 "VSSD" "87" "square,octagon"]
+ Pad[0 -35008 0 -30110 1102 3000 1402 "VDDD" "88" "square,octagon"]
+ Pad[-1968 -35008 -1968 -30110 1102 3000 1402 "P6[0]" "89" "square,octagon"]
+ Pad[-3937 -35008 -3937 -30110 1102 3000 1402 "P6[1]" "90" "square,octagon"]
+ Pad[-5905 -35008 -5905 -30110 1102 3000 1402 "P6[2]" "91" "square,octagon"]
+ Pad[-7874 -35008 -7874 -30110 1102 3000 1402 "P6[3]" "92" "square,octagon"]
+ Pad[-9842 -35008 -9842 -30110 1102 3000 1402 "P15[4]" "93" "square,octagon"]
+ Pad[-11811 -35008 -11811 -30110 1102 3000 1402 "P15[5]" "94" "square,octagon"]
+ Pad[-13779 -35008 -13779 -30110 1102 3000 1402 "P2[0]" "95" "square,octagon"]
+ Pad[-15748 -35008 -15748 -30110 1102 3000 1402 "P2[1]" "96" "square,octagon"]
+ Pad[-17716 -35008 -17716 -30110 1102 3000 1402 "P2[2]" "97" "square,octagon"]
+ Pad[-19685 -35008 -19685 -30110 1102 3000 1402 "P2[3]" "98" "square,octagon"]
+ Pad[-21653 -35008 -21653 -30110 1102 3000 1402 "P2[4]" "99" "square,octagon"]
+ Pad[-23622 -35008 -23622 -30110 1102 3000 1402 "VDDIO2" "100" "square,octagon"]
+ ElementLine [-24259 -27159 27159 -27159 800]
+ ElementLine [27159 -27159 27159 27159 800]
+ ElementLine [27159 27159 -27159 27159 800]
+ ElementLine [-27159 27159 -27159 -24259 800]
+ ElementLine [-27159 -24259 -24259 -27159 800]
+ ElementArc [-24259 -24259 1000 1000 0 360 800]
+
+ )
+
+Element["" "cap_0402" "C19" "100nF" 192465 232435 4100 -5970 0 100 ""]
+(
+ Pad[35 -3872 35 -3872 1969 1200 2569 "1" "1" "square,edge2"]
+ Pad[35 65 35 65 1969 1200 2569 "2" "2" "square,edge2"]
+ ElementLine [-1737 1837 1806 1837 600]
+ ElementLine [1806 -5643 1806 1837 600]
+ ElementLine [-1737 -5643 1806 -5643 600]
+ ElementLine [-1737 -5643 -1737 1837 600]
+
+ )
+
+Element["" "cap_0402" "C17" "100nF" 161035 237128 -3970 -9100 0 100 ""]
+(
+ Pad[-35 3872 -35 3872 1969 1200 2569 "1" "1" "square"]
+ Pad[-35 -65 -35 -65 1969 1200 2569 "2" "2" "square"]
+ ElementLine [-1806 -1837 1737 -1837 600]
+ ElementLine [-1806 -1837 -1806 5643 600]
+ ElementLine [-1806 5643 1737 5643 600]
+ ElementLine [1737 -1837 1737 5643 600]
+
+ )
+
+Element["" "cap_0402" "C21" "100nF" 221965 240935 -3900 -12470 0 100 ""]
+(
+ Pad[35 -3872 35 -3872 1969 1200 2569 "1" "1" "square,edge2"]
+ Pad[35 65 35 65 1969 1200 2569 "2" "2" "square,edge2"]
+ ElementLine [-1737 1837 1806 1837 600]
+ ElementLine [1806 -5643 1806 1837 600]
+ ElementLine [-1737 -5643 1806 -5643 600]
+ ElementLine [-1737 -5643 -1737 1837 600]
+
+ )
+
+Element["" "cap_0402" "C28" "100nF" 221965 305872 5537 -4407 0 100 ""]
+(
+ Pad[35 -3872 35 -3872 1969 1200 2569 "1" "1" "square,edge2"]
+ Pad[35 65 35 65 1969 1200 2569 "2" "2" "square,edge2"]
+ ElementLine [-1737 1837 1806 1837 600]
+ ElementLine [1806 -5643 1806 1837 600]
+ ElementLine [-1737 -5643 1806 -5643 600]
+ ElementLine [-1737 -5643 -1737 1837 600]
+
+ )
+
+Element["" "cap_0402" "C11" "100nF" 153465 187372 8070 -5744 3 100 ""]
+(
+ Pad[35 -3872 35 -3872 1969 1200 2569 "1" "1" "square,edge2"]
+ Pad[35 65 35 65 1969 1200 2569 "2" "2" "square,edge2"]
+ ElementLine [-1737 1837 1806 1837 600]
+ ElementLine [1806 -5643 1806 1837 600]
+ ElementLine [-1737 -5643 1806 -5643 600]
+ ElementLine [-1737 -5643 -1737 1837 600]
+
+ )
+
+Element["" "cap_0402" "C3" "100nF" 292965 188935 8000 -4000 3 100 ""]
+(
+ Pad[35 -3872 35 -3872 1969 1200 2569 "1" "1" "square,edge2"]
+ Pad[35 65 35 65 1969 1200 2569 "2" "2" "square,edge2"]
+ ElementLine [-1737 1837 1806 1837 600]
+ ElementLine [1806 -5643 1806 1837 600]
+ ElementLine [-1737 -5643 1806 -5643 600]
+ ElementLine [-1737 -5643 -1737 1837 600]
+
+ )
+
+Element["" "cap_0402" "C9" "100nF" 160965 305935 -8900 -4470 0 100 ""]
+(
+ Pad[35 -3872 35 -3872 1969 1200 2569 "1" "1" "square,edge2"]
+ Pad[35 65 35 65 1969 1200 2569 "2" "2" "square,edge2"]
+ ElementLine [-1737 1837 1806 1837 600]
+ ElementLine [1806 -5643 1806 1837 600]
+ ElementLine [-1737 -5643 1806 -5643 600]
+ ElementLine [-1737 -5643 -1737 1837 600]
+
+ )
+
+Element["" "cap_0402" "C22" "100nF" 276628 377465 7938 -3069 0 100 ""]
+(
+ Pad[3872 35 3872 35 1969 2000 2569 "1" "1" "square,edge2"]
+ Pad[-65 35 -65 35 1969 2000 2569 "2" "2" "square"]
+ ElementLine [-1837 -1737 -1837 1806 600]
+ ElementLine [-1837 1806 5643 1806 600]
+ ElementLine [5643 -1737 5643 1806 600]
+ ElementLine [-1837 -1737 5643 -1737 600]
+
+ )
+
+Element["" "cap_0402" "C24" "100nF" 230465 267935 -1400 -12470 0 100 ""]
+(
+ Pad[35 -3872 35 -3872 1969 1200 2569 "1" "1" "square,edge2"]
+ Pad[35 65 35 65 1969 1200 2569 "2" "2" "square,edge2"]
+ ElementLine [-1737 1837 1806 1837 600]
+ ElementLine [1806 -5643 1806 1837 600]
+ ElementLine [-1737 -5643 1806 -5643 600]
+ ElementLine [-1737 -5643 -1737 1837 600]
+
+ )
+
+Element["" "cap_0402" "C8" "1uF" 193065 321465 8000 -3000 0 100 ""]
+(
+ Pad[3872 35 3872 35 1969 1200 2569 "1" "1" "square,edge2"]
+ Pad[-65 35 -65 35 1969 1200 2569 "2" "2" "square"]
+ ElementLine [-1837 1806 -1837 -1737 600]
+ ElementLine [5643 1806 -1837 1806 600]
+ ElementLine [5643 -1737 5643 1806 600]
+ ElementLine [-1837 -1737 5643 -1737 600]
+
+ )
+
+Element["" "cap_0402" "C26" "1uF" 236037 268007 2956 -7470 0 100 ""]
+(
+ Pad[35 -3872 35 -3872 1969 1200 2569 "1" "1" "square,edge2"]
+ Pad[35 65 35 65 1969 1200 2569 "2" "2" "square,edge2"]
+ ElementLine [-1737 1837 1806 1837 600]
+ ElementLine [1806 -5643 1806 1837 600]
+ ElementLine [-1737 -5643 1806 -5643 600]
+ ElementLine [-1737 -5643 -1737 1837 600]
+
+ )
+
+Element["" "cap_0402" "C20" "1uF" 198535 312128 3593 -1163 0 100 ""]
+(
+ Pad[-35 3872 -35 3872 1969 1200 2569 "1" "1" "square"]
+ Pad[-35 -65 -35 -65 1969 1200 2569 "2" "2" "square"]
+ ElementLine [-1806 -1837 1737 -1837 600]
+ ElementLine [-1806 -1837 -1806 5643 600]
+ ElementLine [-1806 5643 1737 5643 600]
+ ElementLine [1737 -1837 1737 5643 600]
+
+ )
+
+Element["" "cap_0402" "C27" "1uF" 230535 273065 2530 -600 0 100 ""]
+(
+ Pad[-35 3872 -35 3872 1969 1200 2569 "1" "1" "square"]
+ Pad[-35 -65 -35 -65 1969 1200 2569 "2" "2" "square"]
+ ElementLine [-1806 -1837 1737 -1837 600]
+ ElementLine [-1806 -1837 -1806 5643 600]
+ ElementLine [-1806 5643 1737 5643 600]
+ ElementLine [1737 -1837 1737 5643 600]
+
+ )
+
+Element["lock" "MOLEX8981" "J1" "unknown" 21000 54000 27500 -24000 0 100 "selected"]
+(
+ Pin[0 0 10000 3000 11000 6000 "+5V" "4" "lock,edge2"]
+ Pin[20000 0 10000 3000 11000 6000 "GND" "3" "lock,edge2,thermal(0X,1X)"]
+ Pin[40000 0 10000 3000 11000 6000 "GND" "2" "lock,edge2,thermal(0X,1X)"]
+ Pin[60000 0 10000 3000 11000 6000 "+12V" "1" "lock,edge2"]
+ Pin[-10000 -10000 11000 3000 11000 10000 "LeftHole" "" "lock,edge2"]
+ Pin[70000 -10000 11000 3000 11000 10000 "RightHole" "" "lock,edge2"]
+ Pin[10000 -40000 16000 3000 16000 15700 "BackLeftHole" "" "lock,edge2"]
+ Pin[50000 -40000 16000 3000 16000 15700 "BackRightHole" "" "lock,edge2"]
+ ElementLine [-16000 9000 76000 9000 1000]
+ ElementLine [-16000 9000 -16000 -50000 1000]
+ ElementLine [-16000 -50000 76000 -50000 1000]
+ ElementLine [76000 -50000 76000 9000 1000]
+
+ )
+
+Element["lock" "HEADER50_2_RA" "J2" "unknown" 362000 44000 -119500 -24500 0 100 ""]
+(
+ Pin[-240000 10000 6000 3000 6600 3800 "1" "1" "lock,edge2,thermal(0X,1X)"]
+ Pin[-240000 0 6000 3000 6600 3800 "2" "2" "lock,edge2"]
+ Pin[-230000 10000 6000 3000 6600 3800 "3" "3" "lock,edge2,thermal(0X,1X)"]
+ Pin[-230000 0 6000 3000 6600 3800 "4" "4" "lock,edge2"]
+ Pin[-220000 10000 6000 3000 6600 3800 "5" "5" "lock,edge2,thermal(0X,1X)"]
+ Pin[-220000 0 6000 3000 6600 3800 "6" "6" "lock,edge2"]
+ Pin[-210000 10000 6000 3000 6600 3800 "7" "7" "lock,edge2,thermal(0X,1X)"]
+ Pin[-210000 0 6000 3000 6600 3800 "8" "8" "lock,edge2"]
+ Pin[-200000 10000 6000 3000 6600 3800 "9" "9" "lock,edge2,thermal(0X,1X)"]
+ Pin[-200000 0 6000 3000 6600 3800 "10" "10" "lock,edge2"]
+ Pin[-190000 10000 6000 3000 6600 3800 "11" "11" "lock,edge2,thermal(0X,1X)"]
+ Pin[-190000 0 6000 3000 6600 3800 "12" "12" "lock,edge2"]
+ Pin[-180000 10000 6000 3000 6600 3800 "13" "13" "lock,edge2,thermal(0X,1X)"]
+ Pin[-180000 0 6000 3000 6600 3800 "14" "14" "lock,edge2"]
+ Pin[-170000 10000 6000 3000 6600 3800 "15" "15" "lock,edge2,thermal(0X,1X)"]
+ Pin[-170000 0 6000 3000 6600 3800 "16" "16" "lock,edge2"]
+ Pin[-160000 10000 6000 3000 6600 3800 "17" "17" "lock,edge2,thermal(0X,1X)"]
+ Pin[-160000 0 6000 3000 6600 3800 "18" "18" "lock,edge2"]
+ Pin[-150000 10000 6000 3000 6600 3800 "19" "19" "lock,edge2,thermal(0X,1X)"]
+ Pin[-150000 0 6000 3000 6600 3800 "20" "20" "lock,edge2,thermal(0X,1X)"]
+ Pin[-140000 10000 6000 3000 6600 3800 "21" "21" "lock,edge2,thermal(0X,1X)"]
+ Pin[-140000 0 6000 3000 6600 3800 "22" "22" "lock,edge2,thermal(0X,1X)"]
+ Pin[-130000 10000 6000 3000 6600 3800 "23" "23" "lock,edge2,thermal(0X,1X)"]
+ Pin[-130000 0 6000 3000 6600 3800 "24" "24" "lock,edge2,thermal(0X,1X)"]
+ Pin[-120000 10000 6000 3000 6600 3800 "25" "25" "lock,edge2"]
+ Pin[-120000 0 6000 3000 6600 3800 "26" "26" "lock,edge2"]
+ Pin[-110000 10000 6000 3000 6600 3800 "27" "27" "lock,edge2,thermal(0X,1X)"]
+ Pin[-110000 0 6000 3000 6600 3800 "28" "28" "lock,edge2,thermal(0X,1X)"]
+ Pin[-100000 10000 6000 3000 6600 3800 "29" "29" "lock,edge2,thermal(0X,1X)"]
+ Pin[-100000 0 6000 3000 6600 3800 "30" "30" "lock,edge2,thermal(0X,1X)"]
+ Pin[-90000 10000 6000 3000 6600 3800 "31" "31" "lock,edge2,thermal(0X,1X)"]
+ Pin[-90000 0 6000 3000 6600 3800 "32" "32" "lock,edge2"]
+ Pin[-80000 10000 6000 3000 6600 3800 "33" "33" "lock,edge2,thermal(0X,1X)"]
+ Pin[-80000 0 6000 3000 6600 3800 "34" "34" "lock,edge2,thermal(0X,1X)"]
+ Pin[-70000 10000 6000 3000 6600 3800 "35" "35" "lock,edge2,thermal(0X,1X)"]
+ Pin[-70000 0 6000 3000 6600 3800 "36" "36" "lock,edge2"]
+ Pin[-60000 10000 6000 3000 6600 3800 "37" "37" "lock,edge2,thermal(0X,1X)"]
+ Pin[-60000 0 6000 3000 6600 3800 "38" "38" "lock,edge2"]
+ Pin[-50000 10000 6000 3000 6600 3800 "39" "39" "lock,edge2,thermal(0X,1X)"]
+ Pin[-50000 0 6000 3000 6600 3800 "40" "40" "lock,edge2"]
+ Pin[-40000 10000 6000 3000 6600 3800 "41" "41" "lock,edge2,thermal(0X,1X)"]
+ Pin[-40000 0 6000 3000 6600 3800 "42" "42" "lock,edge2"]
+ Pin[-30000 10000 6000 3000 6600 3800 "43" "43" "lock,edge2,thermal(0X,1X)"]
+ Pin[-30000 0 6000 3000 6600 3800 "44" "44" "lock,edge2"]
+ Pin[-20000 10000 6000 3000 6600 3800 "45" "45" "lock,edge2,thermal(0X,1X)"]
+ Pin[-20000 0 6000 3000 6600 3800 "46" "46" "lock,edge2"]
+ Pin[-10000 10000 6000 3000 6600 3800 "47" "47" "lock,edge2,thermal(0X,1X)"]
+ Pin[-10000 0 6000 3000 6600 3800 "48" "48" "lock,edge2"]
+ Pin[0 10000 6000 3000 6600 3800 "49" "49" "lock,edge2,thermal(0X,1X)"]
+ Pin[0 0 6000 3000 6600 3800 "50" "50" "square,lock,edge2"]
+ ElementLine [-245000 -5000 5000 -5000 1000]
+ ElementLine [-245000 -5000 -245000 15000 1000]
+ ElementLine [-245000 15000 5000 15000 1000]
+ ElementLine [5000 -5000 5000 15000 1000]
+ ElementLine [-5000 -5000 -5000 5000 1000]
+ ElementLine [-5000 5000 5000 5000 1000]
+ ElementLine [5000 -40000 5000 -5000 1000]
+ ElementLine [-245000 -40000 5000 -40000 1000]
+ ElementLine [-245000 -40000 -245000 -5000 1000]
+
+ )
+
+Element["" "SMD_SIMPLE-80-50" "C5" "10uF" 339500 199000 -11300 -2600 0 100 ""]
+(
+ Pad[-700 0 700 0 4500 3000 5100 "1" "1" "square"]
+ Pad[-700 -8000 700 -8000 4500 3000 5100 "2" "2" "square"]
+ ElementLine [-4400 3700 4400 3700 800]
+ ElementLine [4400 -11700 4400 3700 800]
+ ElementLine [-4400 -11700 4400 -11700 800]
+ ElementLine [-4400 -11700 -4400 3700 800]
+
+ )
+
+Element["" "SMD_SIMPLE-80-50" "C2" "10uF" 74500 163500 -12800 400 0 100 ""]
+(
+ Pad[-700 0 700 0 4500 3000 5100 "1" "1" "square"]
+ Pad[-700 8000 700 8000 4500 3000 5100 "2" "2" "square"]
+ ElementLine [-4400 -3700 4400 -3700 800]
+ ElementLine [-4400 -3700 -4400 11700 800]
+ ElementLine [-4400 11700 4400 11700 800]
+ ElementLine [4400 -3700 4400 11700 800]
+
+ )
+
+Element["" "SMD_SIMPLE-80-50" "C7" "10uF" 306000 127500 7200 -2600 0 100 ""]
+(
+ Pad[-700 0 700 0 4500 3000 5100 "1" "1" "square"]
+ Pad[-700 8000 700 8000 4500 3000 5100 "2" "2" "square"]
+ ElementLine [-4400 -3700 4400 -3700 800]
+ ElementLine [-4400 -3700 -4400 11700 800]
+ ElementLine [-4400 11700 4400 11700 800]
+ ElementLine [4400 -3700 4400 11700 800]
+
+ )
+
+Element["" "HEADER2_2" "J3" "unknown" 41000 80000 -7500 16500 0 100 ""]
+(
+ Pin[0 0 6000 4400 6600 3800 "1" "1" "square"]
+ Pin[0 10000 6000 4200 6600 3800 "2" "2" ""]
+ ElementLine [-5000 -5000 5000 -5000 1000]
+ ElementLine [-5000 -5000 -5000 15000 1000]
+ ElementLine [-5000 15000 5000 15000 1000]
+ ElementLine [5000 -5000 5000 15000 1000]
+ ElementLine [-5000 -5000 -5000 5000 1000]
+ ElementLine [-5000 5000 5000 5000 1000]
+
+ )
+
+Element["" "cap_0402" "C10" "100nF" 231465 187372 8070 -6244 3 100 ""]
+(
+ Pad[35 -3872 35 -3872 1969 1200 2569 "1" "1" "square,edge2"]
+ Pad[35 65 35 65 1969 1200 2569 "2" "2" "square,edge2"]
+ ElementLine [-1737 1837 1806 1837 600]
+ ElementLine [1806 -5643 1806 1837 600]
+ ElementLine [-1737 -5643 1806 -5643 600]
+ ElementLine [-1737 -5643 -1737 1837 600]
+
+ )
+
+Element["" "SO14" "U4" "unknown" 211000 181000 10500 -21500 0 100 ""]
+(
+ Pad[15000 -13500 15000 -7000 2000 1800 3000 "A0" "1" "square"]
+ Pad[10000 -13500 10000 -7000 2000 1800 3000 "_Y0_" "2" "square"]
+ Pad[5000 -13500 5000 -7000 2000 1800 3000 "A1" "3" "square"]
+ Pad[0 -13500 0 -7000 2000 1800 3000 "_Y1_" "4" "square"]
+ Pad[-5000 -13500 -5000 -7000 2000 1800 3000 "A2" "5" "square"]
+ Pad[-10000 -13500 -10000 -7000 2000 1800 3000 "_Y2_" "6" "square"]
+ Pad[-15000 -13500 -15000 -7000 2000 1800 3000 "GND" "7" "square"]
+ Pad[-15000 7000 -15000 13500 2000 1800 3000 "_Y3_" "8" "square,edge2"]
+ Pad[-10000 7000 -10000 13500 2000 1800 3000 "A3" "9" "square,edge2"]
+ Pad[-5000 7000 -5000 13500 2000 1800 3000 "_Y4_" "10" "square,edge2"]
+ Pad[0 7000 0 13500 2000 1800 3000 "A4" "11" "square,edge2"]
+ Pad[5000 7000 5000 13500 2000 1800 3000 "_Y5_" "12" "square,edge2"]
+ Pad[10000 7000 10000 13500 2000 1800 3000 "A5" "13" "square,edge2"]
+ Pad[15000 7000 15000 13500 2000 1800 3000 "Vcc" "14" "square,edge2"]
+ ElementLine [-17000 -15500 17000 -15500 1000]
+ ElementLine [-17000 -15500 -17000 15500 1000]
+ ElementLine [-17000 15500 17000 15500 1000]
+ ElementLine [17000 -15500 17000 -2500 1000]
+ ElementLine [17000 2500 17000 15500 1000]
+ ElementArc [17000 0 2500 2500 270 180 1000]
+
+ )
+
+Element["" "SMD_SIMPLE-80-50" "C4" "10uF" 135000 239000 1700 -11600 0 100 ""]
+(
+ Pad[0 -700 0 700 4500 3000 5100 "1" "1" "square"]
+ Pad[8000 -700 8000 700 4500 3000 5100 "2" "2" "square"]
+ ElementLine [-3700 -4400 -3700 4400 800]
+ ElementLine [-3700 4400 11700 4400 800]
+ ElementLine [11700 -4400 11700 4400 800]
+ ElementLine [-3700 -4400 11700 -4400 800]
+
+ )
+
+Element["" "SMD_SIMPLE-80-50" "C13" "10uF" 315000 293500 -4300 -20100 0 100 ""]
+(
+ Pad[-700 0 700 0 4500 3000 5100 "1" "1" "square"]
+ Pad[-700 -8000 700 -8000 4500 3000 5100 "2" "2" "square"]
+ ElementLine [-4400 3700 4400 3700 800]
+ ElementLine [4400 -11700 4400 3700 800]
+ ElementLine [-4400 -11700 4400 -11700 800]
+ ElementLine [-4400 -11700 -4400 3700 800]
+
+ )
+
+Element["" "DPAK" "U6" "unknown" 348750 250250 -13500 -14500 0 100 ""]
+(
+ Pad[-10750 8250 -10750 8250 26500 0 27500 "OUT" "2" "square,nopaste"]
+ Pad[-3250 750 -3250 750 11500 2000 12500 "OUT" "2" "square,edge2"]
+ Pad[-18250 750 -18250 750 11500 2000 12500 "OUT" "2" "square"]
+ Pad[-3250 15750 -3250 15750 11500 2000 12500 "OUT" "2" "square,edge2"]
+ Pad[-18250 15750 -18250 15750 11500 2000 12500 "OUT" "2" "square"]
+ Pad[-1750 31750 -1750 37250 6500 3200 7500 "IN" "3" "square,edge2"]
+ Pad[-19750 31750 -19750 37250 6500 3200 7500 "GND" "1" "square,edge2"]
+ ElementLine [5000 -7500 5000 44500 1000]
+ ElementLine [-26500 44500 5000 44500 1000]
+ ElementLine [-26500 -7500 -26500 44500 1000]
+ ElementLine [-26500 -7500 5000 -7500 1000]
+ ElementLine [-10500 28500 -10500 32500 1000]
+
+ )
+
+Element["" "SIP10" "R2" "unknown" 307000 147500 6500 -3500 0 100 ""]
+(
+ Pin[0 0 6000 3000 6600 2800 "1" "1" "square,edge2,thermal(0X)"]
+ Pin[-10000 0 6000 3000 6600 2800 "2" "2" "edge2"]
+ Pin[-20000 0 6000 3000 6600 2800 "3" "3" "edge2"]
+ Pin[-30000 0 6000 3000 6600 2800 "4" "4" "edge2"]
+ Pin[-40000 0 6000 3000 6600 2800 "5" "5" "edge2"]
+ Pin[-50000 0 6000 3000 6600 2800 "6" "6" "edge2"]
+ Pin[-60000 0 6000 3000 6600 2800 "7" "7" "edge2"]
+ Pin[-70000 0 6000 3000 6600 2800 "8" "8" "edge2"]
+ Pin[-80000 0 6000 3000 6600 2800 "9" "9" "edge2"]
+ Pin[-90000 0 6000 3000 6600 2800 "10" "10" "edge2"]
+ ElementLine [-90000 -5000 0 -5000 2000]
+ ElementLine [-90000 5000 0 5000 2000]
+ ElementLine [-5000 -5000 -5000 5000 1000]
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+ Connect("U1-2")
+ Connect("U5-10")
+ )
+ Net("\\_DB3\\_" "(unknown)")
+ (
+ Connect("J2-8")
+ Connect("R1-7")
+ Connect("U1-1")
+ Connect("U5-4")
+ )
+ Net("\\_DB4\\_" "(unknown)")
+ (
+ Connect("J2-10")
+ Connect("R1-6")
+ Connect("U1-99")
+ Connect("U5-12")
+ )
+ Net("\\_DB5\\_" "(unknown)")
+ (
+ Connect("J2-12")
+ Connect("R1-5")
+ Connect("U1-98")
+ Connect("U5-2")
+ )
+ Net("\\_DB6\\_" "(unknown)")
+ (
+ Connect("J2-14")
+ Connect("R1-4")
+ Connect("U1-97")
+ Connect("U4-8")
+ )
+ Net("\\_DB7\\_" "(unknown)")
+ (
+ Connect("J2-16")
+ Connect("R1-3")
+ Connect("U1-96")
+ Connect("U4-6")
+ )
+ Net("\\_DBP\\_" "(unknown)")
+ (
+ Connect("J2-18")
+ Connect("R1-2")
+ Connect("U1-95")
+ Connect("U4-10")
+ )
+ Net("\\_I/O\\_" "(unknown)")
+ (
+ Connect("J2-50")
+ Connect("R2-2")
+ Connect("U1-19")
+ Connect("U3-2")
+ )
+ Net("\\_MSG\\_" "(unknown)")
+ (
+ Connect("J2-42")
+ Connect("R2-6")
+ Connect("U1-9")
+ Connect("U3-6")
+ )
+ Net("\\_REQ\\_" "(unknown)")
+ (
+ Connect("J2-48")
+ Connect("R2-3")
+ Connect("U1-18")
+ Connect("U3-12")
+ )
+ Net("\\_RST\\_" "(unknown)")
+ (
+ Connect("J2-40")
+ Connect("R2-7")
+ Connect("U1-8")
+ Connect("U3-8")
+ )
+ Net("\\_SD_CD\\_" "(unknown)")
+ (
+ Connect("J6-10")
+ Connect("R9-1")
+ Connect("U1-51")
+ )
+ Net("\\_SD_CS\\_" "(unknown)")
+ (
+ Connect("J6-2")
+ Connect("R11-1")
+ Connect("U1-48")
+ )
+ Net("\\_SEL\\_" "(unknown)")
+ (
+ Connect("J2-44")
+ Connect("R2-5")
+ Connect("U1-16")
+ Connect("U3-10")
+ )
+ Net("ACK" "(unknown)")
+ (
+ Connect("U1-78")
+ Connect("U4-1")
+ )
+ Net("ATN" "(unknown)")
+ (
+ Connect("U1-80")
+ Connect("U4-3")
+ )
+ Net("BSY" "(unknown)")
+ (
+ Connect("U1-79")
+ Connect("U4-13")
+ )
+ Net("C/D" "(unknown)")
+ (
+ Connect("U1-73")
+ Connect("U3-3")
+ )
+ Net("DB0" "(unknown)")
+ (
+ Connect("U1-92")
+ Connect("U5-9")
+ )
+ Net("DB1" "(unknown)")
+ (
+ Connect("U1-91")
+ Connect("U5-5")
+ )
+ Net("DB2" "(unknown)")
+ (
+ Connect("U1-90")
+ Connect("U5-11")
+ )
+ Net("DB3" "(unknown)")
+ (
+ Connect("U1-89")
+ Connect("U5-3")
+ )
+ Net("DB4" "(unknown)")
+ (
+ Connect("U1-85")
+ Connect("U5-13")
+ )
+ Net("DB5" "(unknown)")
+ (
+ Connect("U1-84")
+ Connect("U5-1")
+ )
+ Net("DB6" "(unknown)")
+ (
+ Connect("U1-83")
+ Connect("U4-9")
+ )
+ Net("DB7" "(unknown)")
+ (
+ Connect("U1-82")
+ Connect("U4-5")
+ )
+ Net("DBP" "(unknown)")
+ (
+ Connect("U1-81")
+ Connect("U4-11")
+ )
+ Net("drive_5V" "(unknown)")
+ (
+ Connect("D2-2")
+ Connect("F1-2")
+ Connect("J3-2")
+ )
+ Net("GND" "(unknown)")
+ (
+ Connect("C1-1")
+ Connect("C2-1")
+ Connect("C3-1")
+ Connect("C4-1")
+ Connect("C5-1")
+ Connect("C7-1")
+ Connect("C8-1")
+ Connect("C9-1")
+ Connect("C10-1")
+ Connect("C11-1")
+ Connect("C12-1")
+ Connect("C13-1")
+ Connect("C14-1")
+ Connect("C17-1")
+ Connect("C19-1")
+ Connect("C20-1")
+ Connect("C21-1")
+ Connect("C22-1")
+ Connect("C23-1")
+ Connect("C24-1")
+ Connect("C26-1")
+ Connect("C27-1")
+ Connect("C28-1")
+ Connect("J1-2")
+ Connect("J1-3")
+ Connect("J2-1")
+ Connect("J2-3")
+ Connect("J2-5")
+ Connect("J2-7")
+ Connect("J2-9")
+ Connect("J2-11")
+ Connect("J2-13")
+ Connect("J2-15")
+ Connect("J2-17")
+ Connect("J2-19")
+ Connect("J2-20")
+ Connect("J2-21")
+ Connect("J2-22")
+ Connect("J2-23")
+ Connect("J2-24")
+ Connect("J2-27")
+ Connect("J2-28")
+ Connect("J2-29")
+ Connect("J2-30")
+ Connect("J2-31")
+ Connect("J2-33")
+ Connect("J2-34")
+ Connect("J2-35")
+ Connect("J2-37")
+ Connect("J2-39")
+ Connect("J2-41")
+ Connect("J2-43")
+ Connect("J2-45")
+ Connect("J2-47")
+ Connect("J2-49")
+ Connect("J4-3")
+ Connect("J4-5")
+ Connect("J4-7")
+ Connect("J4-9")
+ Connect("J5-5")
+ Connect("J6-6")
+ Connect("J6-9")
+ Connect("U1-10")
+ Connect("U1-12")
+ Connect("U1-13")
+ Connect("U1-14")
+ Connect("U1-27")
+ Connect("U1-28")
+ Connect("U1-29")
+ Connect("U1-30")
+ Connect("U1-31")
+ Connect("U1-32")
+ Connect("U1-33")
+ Connect("U1-34")
+ Connect("U1-38")
+ Connect("U1-40")
+ Connect("U1-41")
+ Connect("U1-43")
+ Connect("U1-52")
+ Connect("U1-53")
+ Connect("U1-54")
+ Connect("U1-56")
+ Connect("U1-57")
+ Connect("U1-58")
+ Connect("U1-59")
+ Connect("U1-60")
+ Connect("U1-61")
+ Connect("U1-62")
+ Connect("U1-64")
+ Connect("U1-66")
+ Connect("U1-67")
+ Connect("U1-69")
+ Connect("U1-70")
+ Connect("U1-87")
+ Connect("U1-93")
+ Connect("U1-94")
+ Connect("U2-1")
+ Connect("U3-7")
+ Connect("U4-7")
+ Connect("U5-7")
+ Connect("U6-1")
+ )
+ Net("I/O" "(unknown)")
+ (
+ Connect("U1-71")
+ Connect("U3-1")
+ )
+ Net("MSG" "(unknown)")
+ (
+ Connect("U1-76")
+ Connect("U3-5")
+ )
+ Net("REQ" "(unknown)")
+ (
+ Connect("U1-72")
+ Connect("U3-13")
+ )
+ Net("RST" "(unknown)")
+ (
+ Connect("U1-77")
+ Connect("U3-9")
+ )
+ Net("SD_DAT1" "(unknown)")
+ (
+ Connect("J6-8")
+ Connect("R6-1")
+ Connect("U1-44")
+ )
+ Net("SD_DAT2" "(unknown)")
+ (
+ Connect("J6-1")
+ Connect("R12-1")
+ Connect("U1-49")
+ )
+ Net("SD_MISO" "(unknown)")
+ (
+ Connect("J6-7")
+ Connect("R7-1")
+ Connect("U1-45")
+ )
+ Net("SD_MOSI" "(unknown)")
+ (
+ Connect("J6-3")
+ Connect("R10-1")
+ Connect("U1-47")
+ )
+ Net("SD_SCK" "(unknown)")
+ (
+ Connect("J6-5")
+ Connect("R8-1")
+ Connect("U1-46")
+ )
+ Net("SEL" "(unknown)")
+ (
+ Connect("U1-74")
+ Connect("U3-11")
+ )
+ Net("unnamed_net1" "(unknown)")
+ (
+ Connect("J2-25")
+ )
+ Net("unnamed_net2" "(unknown)")
+ (
+ Connect("C1-2")
+ Connect("C5-2")
+ Connect("D1-1")
+ Connect("J2-26")
+ Connect("U2-3")
+ )
+ Net("unnamed_net3" "(unknown)")
+ (
+ Connect("J1-1")
+ )
+ Net("unnamed_net4" "(unknown)")
+ (
+ Connect("F1-1")
+ Connect("J1-4")
+ )
+ Net("unnamed_net5" "(unknown)")
+ (
+ Connect("J4-2")
+ Connect("U1-20")
+ )
+ Net("unnamed_net6" "(unknown)")
+ (
+ Connect("J4-4")
+ Connect("U1-21")
+ )
+ Net("unnamed_net7" "(unknown)")
+ (
+ Connect("J4-10")
+ Connect("U1-15")
+ )
+ Net("unnamed_net8" "(unknown)")
+ (
+ Connect("J4-8")
+ )
+ Net("unnamed_net9" "(unknown)")
+ (
+ Connect("J4-6")
+ Connect("U1-23")
+ )
+ Net("unnamed_net10" "(unknown)")
+ (
+ Connect("LED1-1")
+ Connect("R3-1")
+ )
+ Net("unnamed_net11" "(unknown)")
+ (
+ Connect("LED1-2")
+ Connect("U1-68")
+ )
+ Net("unnamed_net12" "(unknown)")
+ (
+ Connect("C27-2")
+ Connect("U1-63")
+ )
+ Net("unnamed_net13" "(unknown)")
+ (
+ Connect("C20-2")
+ Connect("U1-39")
+ Connect("U1-86")
+ )
+ Net("unnamed_net14" "(unknown)")
+ (
+ Connect("U1-11")
+ )
+ Net("unnamed_net15" "(unknown)")
+ (
+ Connect("U1-22")
+ )
+ Net("unnamed_net16" "(unknown)")
+ (
+ Connect("U1-24")
+ )
+ Net("unnamed_net17" "(unknown)")
+ (
+ Connect("U1-25")
+ )
+ Net("unnamed_net18" "(unknown)")
+ (
+ Connect("R4-2")
+ Connect("U1-35")
+ )
+ Net("unnamed_net19" "(unknown)")
+ (
+ Connect("R5-2")
+ Connect("U1-36")
+ )
+ Net("unnamed_net20" "(unknown)")
+ (
+ Connect("U1-42")
+ )
+ Net("unnamed_net21" "(unknown)")
+ (
+ Connect("U1-55")
+ )
+ Net("unnamed_net22" "(unknown)")
+ (
+ Connect("C7-2")
+ Connect("C14-2")
+ Connect("R1-1")
+ Connect("R2-1")
+ Connect("U2-2")
+ )
+ Net("unnamed_net23" "(unknown)")
+ (
+ Connect("D1-2")
+ Connect("J3-1")
+ )
+ Net("unnamed_net24" "(unknown)")
+ (
+ Connect("F2-1")
+ Connect("J5-1")
+ )
+ Net("unnamed_net25" "(unknown)")
+ (
+ Connect("D3-2")
+ Connect("F2-2")
+ )
+ Net("unnamed_net26" "(unknown)")
+ (
+ Connect("J5-4")
+ )
+ Net("unnamed_net27" "(unknown)")
+ (
+ Connect("J5-3")
+ Connect("R4-1")
+ )
+ Net("unnamed_net28" "(unknown)")
+ (
+ Connect("J5-2")
+ Connect("R5-1")
+ )
+)
--- /dev/null
+v 20110115 2
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+}
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+}
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+{
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+{
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+}
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+}
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+{
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+}
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+{
+T 69500 37900 5 10 0 0 270 0 1
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+}
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+{
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+}
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+{
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+}
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+{
+T 34900 52200 5 10 0 0 90 0 1
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+symversion=0.1
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+value=10uF
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+description=Ceramic decoupling cap
+T 35600 52000 5 10 0 0 0 0 1
+footprint=SMD_SIMPLE 80 50
+}
+U 34000 49400 34000 39400 10 -1
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+{
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+{
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
+C 38800 43000 1 270 0 busripper-1.sym
+{
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+T 33500 34200 5 10 0 2 90 0 1
+description=Ceramic decoupling cap
+T 33500 34200 5 10 0 0 0 0 1
+footprint=SMD_SIMPLE 80 50
+}
+C 33200 33900 1 0 0 gnd-1.sym
+{
+T 33200 33900 5 10 0 0 0 0 1
+net=GND:1
+}
+C 51400 55300 1 180 0 gnd-1.sym
+C 52100 55300 1 180 0 gnd-1.sym
+C 47700 35900 1 0 0 gnd-1.sym
+C 48400 35900 1 0 0 gnd-1.sym
+C 49100 35900 1 0 0 gnd-1.sym
+C 49800 35900 1 0 0 gnd-1.sym
+C 65100 38500 1 90 0 gnd-1.sym
+C 65100 39200 1 90 0 gnd-1.sym
+C 65100 48300 1 90 0 gnd-1.sym
+C 65100 49700 1 90 0 gnd-1.sym
+C 65100 50400 1 90 0 gnd-1.sym
+C 64800 39900 1 0 0 nc-right-1.sym
+{
+T 64900 40400 5 10 0 0 0 0 1
+value=NoConnection
+T 64900 40600 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 58900 35900 1 0 0 gnd-1.sym
+C 65100 40600 1 90 0 gnd-1.sym
+C 56800 35900 1 0 0 gnd-1.sym
+C 57500 35900 1 0 0 gnd-1.sym
+C 65100 41300 1 90 0 gnd-1.sym
+C 65100 42000 1 90 0 gnd-1.sym
+C 65100 42700 1 90 0 gnd-1.sym
+C 65100 43400 1 90 0 gnd-1.sym
+C 65100 44100 1 90 0 gnd-1.sym
+C 65100 44800 1 90 0 gnd-1.sym
+C 35300 45300 1 0 0 jumper-1.sym
+{
+T 35600 45800 5 8 0 0 0 0 1
+device=JUMPER
+T 35600 45800 5 10 1 1 0 0 1
+refdes=J3
+T 35300 45300 5 10 0 0 0 0 1
+footprint=HEADER2_2
+}
+C 46200 38000 1 180 0 nc-right-1.sym
+{
+T 46100 37500 5 10 0 0 180 0 1
+value=NoConnection
+T 46100 37300 5 10 0 0 180 0 1
+device=DRC_Directive
+}
+C 46200 37300 1 180 0 nc-right-1.sym
+{
+T 46100 36800 5 10 0 0 180 0 1
+value=NoConnection
+T 46100 36600 5 10 0 0 180 0 1
+device=DRC_Directive
+}
+N 54800 50000 55500 50000 4
+N 34900 52900 36100 52900 4
+C 33500 53300 1 0 0 generic-power.sym
+{
+T 33700 53550 5 10 1 1 0 3 1
+net=drive_5V:1
+}
+C 35200 46300 1 0 0 generic-power.sym
+{
+T 35400 46550 5 10 1 1 0 3 1
+net=drive_5V:1
+}
+C 34000 52700 1 0 0 schottky-1.sym
+{
+T 34322 53372 5 10 0 0 0 0 1
+device=DIODE
+T 34300 53200 5 10 1 1 0 0 1
+refdes=D2
+T 34341 53532 5 10 0 1 0 0 1
+footprint=diode-DO-214AA-SMB
+T 34000 52700 5 10 0 0 0 0 1
+description=Schottky diode
+}
+C 35200 45300 1 270 0 schottky-1.sym
+{
+T 35872 44978 5 10 0 0 270 0 1
+device=DIODE
+T 35700 45000 5 10 1 1 270 0 1
+refdes=D1
+T 36032 44959 5 10 0 1 270 0 1
+footprint=diode-DO-214AA-SMB
+T 35200 45300 5 10 0 0 0 0 1
+description=Schottky diode
+}
+C 32400 52900 1 0 0 fuse-1.sym
+{
+T 32600 53300 5 10 0 0 0 0 1
+device=FUSE
+T 32600 53100 5 10 1 1 0 0 1
+refdes=F1
+T 32600 53500 5 10 0 0 0 0 1
+symversion=0.1
+T 32400 52900 5 10 0 2 0 0 1
+documentation=PTC Fuse.
+T 32600 52600 5 10 1 1 0 0 1
+value=1.5A Hold
+T 32400 52900 5 10 0 0 0 0 1
+device=Bourns MF-NSMF200-2
+T 32400 52900 5 10 0 0 0 0 1
+footprint=SMD_SIMPLE 120 60
+}
+N 31600 52900 32400 52900 4
+N 33300 52900 34000 52900 4
+N 33700 53300 33700 52900 4
+C 50400 33800 1 0 0 fuse-1.sym
+{
+T 50600 34200 5 10 0 0 0 0 1
+device=FUSE
+T 50600 34000 5 10 1 1 0 0 1
+refdes=F2
+T 50600 34400 5 10 0 0 0 0 1
+symversion=0.1
+T 50400 33800 5 10 0 2 0 0 1
+documentation=PTC Fuse.
+T 50600 33500 5 10 1 1 0 0 1
+value=500mA Hold
+T 50400 33800 5 10 0 0 0 0 1
+device=Bourns MF-NSMF050-2
+T 50400 33800 5 10 0 0 0 0 1
+footprint=SMD_SIMPLE 120 60
+}
+C 51600 33600 1 0 0 schottky-1.sym
+{
+T 51922 34272 5 10 0 0 0 0 1
+device=DIODE
+T 51900 34100 5 10 1 1 0 0 1
+refdes=D3
+T 51941 34432 5 10 0 1 0 0 1
+footprint=diode-DO-214AA-SMB
+T 51600 33600 5 10 0 0 0 0 1
+description=Schottky diode
+}
+C 50700 35900 1 0 1 gnd-1.sym
+{
+T 50700 35900 5 10 0 0 0 6 1
+net=GND:1
+}
+C 51400 35900 1 0 1 gnd-1.sym
+{
+T 51400 35900 5 10 0 0 0 6 1
+net=GND:1
+}
+C 52100 35900 1 0 1 gnd-1.sym
+{
+T 52100 35900 5 10 0 0 0 6 1
+net=GND:1
+}
+C 52800 35900 1 0 1 gnd-1.sym
+{
+T 52800 35900 5 10 0 0 0 6 1
+net=GND:1
+}
+C 52800 33900 1 0 1 5V-plus-1.sym
+{
+T 52800 33900 5 10 0 0 0 6 1
+net=5V:1
+}
+N 52500 33800 52600 33800 4
+N 52600 33800 52600 33900 4
+N 53400 36200 53400 34600 4
+N 54100 36200 54100 34600 4
+C 49100 32500 1 0 0 usbmini.sym
+{
+T 49800 34100 5 10 1 1 0 0 1
+refdes=J5
+T 49200 34100 5 10 1 1 0 0 1
+device=USB
+T 49500 45150 5 10 0 0 0 0 1
+footprint=fci-10118192-0001LF
+}
+N 53400 33200 50400 33200 4
+N 54100 33500 50400 33500 4
+C 50400 32800 1 0 0 nc-right-1.sym
+{
+T 50500 33300 5 10 0 0 0 0 1
+value=NoConnection
+T 50500 33500 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+C 50500 32300 1 0 1 gnd-1.sym
+{
+T 50500 32300 5 10 0 0 0 6 1
+net=GND:1
+}
+C 53500 33700 1 90 0 resistor-1.sym
+{
+T 53100 34000 5 10 0 0 90 0 1
+device=RESISTOR
+T 53200 33900 5 10 1 1 90 0 1
+refdes=R4
+T 53500 33700 5 10 0 0 90 0 1
+footprint=SMD_SIMPLE 80 50
+T 53700 33900 5 10 1 1 90 0 1
+value=22Ω
+T 53500 33700 5 10 0 0 0 0 1
+description=1% precision required.
+}
+C 54200 33700 1 90 0 resistor-1.sym
+{
+T 53800 34000 5 10 0 0 90 0 1
+device=RESISTOR
+T 53900 33900 5 10 1 1 90 0 1
+refdes=R5
+T 54200 33700 5 10 0 0 90 0 1
+footprint=SMD_SIMPLE 80 50
+T 54400 33900 5 10 1 1 90 0 1
+value=22Ω
+T 54200 33700 5 10 0 0 0 0 1
+documentation=1% precision required.
+}
+N 53400 33700 53400 33200 4
+N 54100 33700 54100 33500 4
+N 51600 33800 51300 33800 4
+N 33700 38300 33700 35100 4
+N 33300 35100 33900 35100 4
+N 35800 35700 35000 35700 4
+{
+T 35000 35700 5 10 1 1 0 0 1
+netname=\_DB7\_
+}
+C 35800 35700 1 270 0 busripper-1.sym
+{
+T 36200 35700 5 8 0 0 270 0 1
+device=none
+}
+N 35800 37800 35000 37800 4
+{
+T 35000 37800 5 10 1 1 0 0 1
+netname=\_DB0\_
+}
+C 35800 37800 1 270 0 busripper-1.sym
+{
+T 36200 37800 5 8 0 0 270 0 1
+device=none
+}
+N 35000 37500 35800 37500 4
+{
+T 35000 37500 5 10 1 1 0 0 1
+netname=\_DB1\_
+}
+C 35800 37500 1 270 0 busripper-1.sym
+{
+T 36200 37500 5 8 0 0 270 0 1
+device=none
+}
+N 35000 37200 35800 37200 4
+{
+T 35000 37200 5 10 1 1 0 0 1
+netname=\_DB2\_
+}
+C 35800 37200 1 270 0 busripper-1.sym
+{
+T 36200 37200 5 8 0 0 270 0 1
+device=none
+}
+N 35000 36900 35800 36900 4
+{
+T 35000 36900 5 10 1 1 0 0 1
+netname=\_DB3\_
+}
+C 35800 36900 1 270 0 busripper-1.sym
+{
+T 36200 36900 5 8 0 0 270 0 1
+device=none
+}
+N 35000 36600 35800 36600 4
+{
+T 35000 36600 5 10 1 1 0 0 1
+netname=\_DB4\_
+}
+C 35800 36600 1 270 0 busripper-1.sym
+{
+T 36200 36600 5 8 0 0 270 0 1
+device=none
+}
+N 35000 36300 35800 36300 4
+{
+T 35000 36300 5 10 1 1 0 0 1
+netname=\_DB5\_
+}
+C 35800 36300 1 270 0 busripper-1.sym
+{
+T 36200 36300 5 8 0 0 270 0 1
+device=none
+}
+N 35000 36000 35800 36000 4
+{
+T 35000 36000 5 10 1 1 0 0 1
+netname=\_DB6\_
+}
+C 35800 36000 1 270 0 busripper-1.sym
+{
+T 36200 36000 5 8 0 0 270 0 1
+device=none
+}
+N 35000 34600 35800 34600 4
+{
+T 35000 34600 5 10 1 1 0 0 1
+netname=\_ATN\_
+}
+C 35800 34600 1 270 0 busripper-1.sym
+{
+T 36200 34600 5 8 0 0 270 0 1
+device=none
+}
+N 35000 34300 35800 34300 4
+{
+T 35000 34300 5 10 1 1 0 0 1
+netname=\_BSY\_
+}
+C 35800 34300 1 270 0 busripper-1.sym
+{
+T 36200 34300 5 8 0 0 270 0 1
+device=none
+}
+N 35000 34000 35800 34000 4
+{
+T 35000 34000 5 10 1 1 0 0 1
+netname=\_ACK\_
+}
+C 35800 34000 1 270 0 busripper-1.sym
+{
+T 36200 34000 5 8 0 0 270 0 1
+device=none
+}
+N 35000 33700 35800 33700 4
+{
+T 35000 33700 5 10 1 1 0 0 1
+netname=\_RST\_
+}
+C 35800 33700 1 270 0 busripper-1.sym
+{
+T 36200 33700 5 8 0 0 270 0 1
+device=none
+}
+N 35000 33400 35800 33400 4
+{
+T 35000 33400 5 10 1 1 0 0 1
+netname=\_MSG\_
+}
+C 35800 33400 1 270 0 busripper-1.sym
+{
+T 36200 33400 5 8 0 0 270 0 1
+device=none
+}
+N 35000 33100 35800 33100 4
+{
+T 35000 33100 5 10 1 1 0 0 1
+netname=\_SEL\_
+}
+C 35800 33100 1 270 0 busripper-1.sym
+{
+T 36200 33100 5 8 0 0 270 0 1
+device=none
+}
+N 35000 32800 35800 32800 4
+{
+T 35000 32800 5 10 1 1 0 0 1
+netname=\_C/D\_
+}
+C 35800 32800 1 270 0 busripper-1.sym
+{
+T 36200 32800 5 8 0 0 270 0 1
+device=none
+}
+N 35000 32500 35800 32500 4
+{
+T 35000 32500 5 10 1 1 0 0 1
+netname=\_REQ\_
+}
+C 35800 32500 1 270 0 busripper-1.sym
+{
+T 36200 32500 5 8 0 0 270 0 1
+device=none
+}
+C 35000 35300 1 90 0 resistorpack10-1.sym
+{
+T 33800 35400 5 10 0 0 90 0 1
+device=RESISTORPACK_10
+T 33800 35400 5 10 1 1 90 0 1
+refdes=R1
+T 35000 35300 5 10 0 0 0 0 1
+footprint=SIP10
+}
+C 35000 32100 1 90 0 resistorpack10-1.sym
+{
+T 33800 32200 5 10 0 0 90 0 1
+device=RESISTORPACK_10
+T 33800 32200 5 10 1 1 90 0 1
+refdes=R2
+T 35000 32100 5 10 0 0 0 0 1
+footprint=SIP10
+}
+N 35000 35400 35800 35400 4
+{
+T 35000 35400 5 10 1 1 0 0 1
+netname=\_DBP\_
+}
+C 35800 35400 1 270 0 busripper-1.sym
+{
+T 36200 35400 5 8 0 0 270 0 1
+device=none
+}
+N 35000 32200 35800 32200 4
+{
+T 35000 32200 5 10 1 1 0 0 1
+netname=\_I/O\_
+}
+C 35800 32200 1 270 0 busripper-1.sym
+{
+T 36200 32200 5 8 0 0 270 0 1
+device=none
+}
+C 68100 32500 1 0 0 gnd-1.sym
+C 68400 31300 1 0 0 gnd-1.sym
+N 68200 32800 68500 32800 4
+C 68400 30700 1 0 0 wurth-microsd.sym
+{
+T 69800 35300 5 10 1 1 0 6 1
+refdes=J6
+T 68800 35500 5 10 0 0 0 0 1
+device=wurth-693071010811
+T 68800 35700 5 10 0 0 0 0 1
+footprint=wurth-microsd
+}
+C 65100 37800 1 90 0 gnd-1.sym
--- /dev/null
+v 20060113 1
+P 100 2900 400 2900 1 0 0
+{
+T 300 2950 5 8 1 1 0 6 1
+pinnumber=1
+T 300 2850 5 8 0 1 0 8 1
+pinseq=1
+T 450 2900 9 8 1 1 0 0 1
+pinlabel=A0
+T 450 2900 5 8 0 1 0 2 1
+pintype=in
+}
+P 100 2500 400 2500 1 0 0
+{
+T 300 2550 5 8 1 1 0 6 1
+pinnumber=2
+T 300 2450 5 8 0 1 0 8 1
+pinseq=2
+T 450 2500 9 8 1 1 0 0 1
+pinlabel=\_Y0\_
+T 450 2500 5 8 0 1 0 2 1
+pintype=out
+}
+P 100 2100 400 2100 1 0 0
+{
+T 300 2150 5 8 1 1 0 6 1
+pinnumber=3
+T 300 2050 5 8 0 1 0 8 1
+pinseq=3
+T 450 2100 9 8 1 1 0 0 1
+pinlabel=A1
+T 450 2100 5 8 0 1 0 2 1
+pintype=in
+}
+P 100 1700 400 1700 1 0 0
+{
+T 300 1750 5 8 1 1 0 6 1
+pinnumber=4
+T 300 1650 5 8 0 1 0 8 1
+pinseq=4
+T 450 1700 9 8 1 1 0 0 1
+pinlabel=\_Y1\_
+T 450 1700 5 8 0 1 0 2 1
+pintype=out
+}
+P 100 1300 400 1300 1 0 0
+{
+T 300 1350 5 8 1 1 0 6 1
+pinnumber=5
+T 300 1250 5 8 0 1 0 8 1
+pinseq=5
+T 450 1300 9 8 1 1 0 0 1
+pinlabel=A2
+T 450 1300 5 8 0 1 0 2 1
+pintype=in
+}
+P 100 900 400 900 1 0 0
+{
+T 300 950 5 8 1 1 0 6 1
+pinnumber=6
+T 300 850 5 8 0 1 0 8 1
+pinseq=6
+T 450 900 9 8 1 1 0 0 1
+pinlabel=\_Y2\_
+T 450 900 5 8 0 1 0 2 1
+pintype=out
+}
+P 100 500 400 500 1 0 0
+{
+T 300 550 5 8 1 1 0 6 1
+pinnumber=7
+T 300 450 5 8 0 1 0 8 1
+pinseq=7
+T 450 500 9 8 1 1 0 0 1
+pinlabel=GND
+T 450 500 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 1700 2900 1400 2900 1 0 0
+{
+T 1500 2950 5 8 1 1 0 0 1
+pinnumber=14
+T 1500 2850 5 8 0 1 0 2 1
+pinseq=8
+T 1350 2900 9 8 1 1 0 6 1
+pinlabel=Vcc
+T 1350 2900 5 8 0 1 0 8 1
+pintype=pwr
+}
+P 1700 2500 1400 2500 1 0 0
+{
+T 1500 2550 5 8 1 1 0 0 1
+pinnumber=13
+T 1500 2450 5 8 0 1 0 2 1
+pinseq=9
+T 1350 2500 9 8 1 1 0 6 1
+pinlabel=A5
+T 1350 2500 5 8 0 1 0 8 1
+pintype=in
+}
+P 1700 2100 1400 2100 1 0 0
+{
+T 1500 2150 5 8 1 1 0 0 1
+pinnumber=12
+T 1500 2050 5 8 0 1 0 2 1
+pinseq=10
+T 1350 2100 9 8 1 1 0 6 1
+pinlabel=\_Y5\_
+T 1350 2100 5 8 0 1 0 8 1
+pintype=out
+}
+P 1700 1700 1400 1700 1 0 0
+{
+T 1500 1750 5 8 1 1 0 0 1
+pinnumber=11
+T 1500 1650 5 8 0 1 0 2 1
+pinseq=11
+T 1350 1700 9 8 1 1 0 6 1
+pinlabel=A4
+T 1350 1700 5 8 0 1 0 8 1
+pintype=in
+}
+P 1700 1300 1400 1300 1 0 0
+{
+T 1500 1350 5 8 1 1 0 0 1
+pinnumber=10
+T 1500 1250 5 8 0 1 0 2 1
+pinseq=12
+T 1350 1300 9 8 1 1 0 6 1
+pinlabel=\_Y4\_
+T 1350 1300 5 8 0 1 0 8 1
+pintype=out
+}
+P 1700 900 1400 900 1 0 0
+{
+T 1500 950 5 8 1 1 0 0 1
+pinnumber=9
+T 1500 850 5 8 0 1 0 2 1
+pinseq=13
+T 1350 900 9 8 1 1 0 6 1
+pinlabel=A3
+T 1350 900 5 8 0 1 0 8 1
+pintype=in
+}
+P 1700 500 1400 500 1 0 0
+{
+T 1500 550 5 8 1 1 0 0 1
+pinnumber=8
+T 1500 450 5 8 0 1 0 2 1
+pinseq=14
+T 1350 500 9 8 1 1 0 6 1
+pinlabel=\_Y3\_
+T 1350 500 5 8 0 1 0 8 1
+pintype=out
+}
+B 400 100 1000 3200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 1400 3400 8 10 1 1 0 6 1
+refdes=U?
+T 400 3400 9 10 1 0 0 0 1
+7406
+T 400 3600 5 10 0 0 0 0 1
+device=7406
+T 400 3800 5 10 0 0 0 0 1
+footprint=SO14
+T 400 4000 5 10 0 0 0 0 1
+author=Michael McMaster <michael@codesrc.com>
+T 400 4200 5 10 0 0 0 0 1
+documentation=http://www.nxp.com/products/logic/buffers_inverters_drivers/N74F06D.html
+T 400 4400 5 10 0 0 0 0 1
+description=Hex Inverter (Open Drain)
+T 400 4600 5 10 0 0 0 0 1
+numslots=0
+T 400 4800 5 10 0 0 0 0 1
+dist-license=gpl3+
+T 400 5000 5 10 0 0 0 0 1
+use-license=gpl3+
--- /dev/null
+# This is the template file for creating symbols with tragesym
+# every line starting with '#' is a comment line.
+
+[options]
+# wordswap swaps labels if the pin is on the right side an looks like this:
+# "PB1 (CLK)". That's useful for micro controller port labels
+# rotate_labels rotates the pintext of top and bottom pins
+# this is useful for large symbols like FPGAs with more than 100 pins
+# sort_labels will sort the pins by it's labels
+# useful for address ports, busses, ...
+wordswap=yes
+rotate_labels=yes
+sort_labels=no
+generate_pinseq=yes
+sym_width=1000
+pinwidthvertical=400
+pinwidthhorizontal=400
+
+[geda_attr]
+# name will be printed in the top of the symbol
+# name is only some graphical text, not an attribute
+# version specifies a gschem version.
+# if you have a device with slots, you'll have to use slot= and slotdef=
+# use comment= if there are special information you want to add
+version=20060113 1
+name=7406
+device=7406
+refdes=U?
+footprint=SO14
+description=Hex Inverter (Open Drain)
+documentation=http://www.nxp.com/products/logic/buffers_inverters_drivers/N74F06D.html
+author=Michael McMaster <michael@codesrc.com>
+dist-license=gpl3+
+use-license=gpl3+
+numslots=0
+#slot=1
+#slotdef=1:
+#slotdef=2:
+#slotdef=3:
+#slotdef=4:
+#comment=
+#comment=
+#comment=
+
+[pins]
+# tabseparated list of pin descriptions
+# ----------------------------------------
+# pinnr is the physical number of the pin
+# seq is the pinseq= attribute, leave it blank if it doesn't matter
+# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
+# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net
+# posit. can be (l,r,t,b) or empty for nets.
+# net specifies the name of the net. Vcc or GND for example.
+# label represents the pinlabel.
+# negation lines can be added with "\_" example: \_enable\_
+# if you want to write a "\" use "\\" as escape sequence
+#-----------------------------------------------------
+#pinnr seq type style posit. net label
+#-----------------------------------------------------
+1 in line l A0
+2 out line l \_Y0\_
+3 in line l A1
+4 out line l \_Y1\_
+5 in line l A2
+6 out line l \_Y2\_
+7 pwr line l GND GND
+14 pwr line r Vcc
+13 in line r A5
+12 out line r \_Y5\_
+11 in line r A4
+10 out line r \_Y4\_
+9 in line r A3
+8 out line r \_Y3\_
+
--- /dev/null
+v 20060113 1
+P 100 17900 400 17900 1 0 0
+{
+T 300 17950 5 8 1 1 0 6 1
+pinnumber=1
+T 300 17850 5 8 0 1 0 8 1
+pinseq=1
+T 450 17900 9 8 1 1 0 0 1
+pinlabel=P2[5]
+T 450 17900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 17200 400 17200 1 0 0
+{
+T 300 17250 5 8 1 1 0 6 1
+pinnumber=2
+T 300 17150 5 8 0 1 0 8 1
+pinseq=2
+T 450 17200 9 8 1 1 0 0 1
+pinlabel=P2[6]
+T 450 17200 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 16500 400 16500 1 0 0
+{
+T 300 16550 5 8 1 1 0 6 1
+pinnumber=3
+T 300 16450 5 8 0 1 0 8 1
+pinseq=3
+T 450 16500 9 8 1 1 0 0 1
+pinlabel=P2[7]
+T 450 16500 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 15800 400 15800 1 0 0
+{
+T 300 15850 5 8 1 1 0 6 1
+pinnumber=4
+T 300 15750 5 8 0 1 0 8 1
+pinseq=4
+T 450 15800 9 8 1 1 0 0 1
+pinlabel=P12[4]
+T 450 15800 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 15100 400 15100 1 0 0
+{
+T 300 15150 5 8 1 1 0 6 1
+pinnumber=5
+T 300 15050 5 8 0 1 0 8 1
+pinseq=5
+T 450 15100 9 8 1 1 0 0 1
+pinlabel=P12[5]
+T 450 15100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 14400 400 14400 1 0 0
+{
+T 300 14450 5 8 1 1 0 6 1
+pinnumber=6
+T 300 14350 5 8 0 1 0 8 1
+pinseq=6
+T 450 14400 9 8 1 1 0 0 1
+pinlabel=P6[4]
+T 450 14400 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 13700 400 13700 1 0 0
+{
+T 300 13750 5 8 1 1 0 6 1
+pinnumber=7
+T 300 13650 5 8 0 1 0 8 1
+pinseq=7
+T 450 13700 9 8 1 1 0 0 1
+pinlabel=P6[5]
+T 450 13700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 13000 400 13000 1 0 0
+{
+T 300 13050 5 8 1 1 0 6 1
+pinnumber=8
+T 300 12950 5 8 0 1 0 8 1
+pinseq=8
+T 450 13000 9 8 1 1 0 0 1
+pinlabel=P6[6]
+T 450 13000 5 8 0 1 0 2 1
+pintype=io
+}
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+{
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+{
+T 5150 18700 5 8 1 1 90 0 1
+pinnumber=94
+T 5250 18700 5 8 0 1 90 2 1
+pinseq=82
+T 5200 18550 9 8 1 1 90 6 1
+pinlabel=P15[5]
+T 5200 18550 5 8 0 1 90 8 1
+pintype=io
+}
+P 5900 18900 5900 18600 1 0 0
+{
+T 5850 18700 5 8 1 1 90 0 1
+pinnumber=93
+T 5950 18700 5 8 0 1 90 2 1
+pinseq=83
+T 5900 18550 9 8 1 1 90 6 1
+pinlabel=P15[4]
+T 5900 18550 5 8 0 1 90 8 1
+pintype=io
+}
+P 6600 18900 6600 18600 1 0 0
+{
+T 6550 18700 5 8 1 1 90 0 1
+pinnumber=92
+T 6650 18700 5 8 0 1 90 2 1
+pinseq=84
+T 6600 18550 9 8 1 1 90 6 1
+pinlabel=P6[3]
+T 6600 18550 5 8 0 1 90 8 1
+pintype=io
+}
+P 7300 18900 7300 18600 1 0 0
+{
+T 7250 18700 5 8 1 1 90 0 1
+pinnumber=91
+T 7350 18700 5 8 0 1 90 2 1
+pinseq=85
+T 7300 18550 9 8 1 1 90 6 1
+pinlabel=P6[2]
+T 7300 18550 5 8 0 1 90 8 1
+pintype=io
+}
+P 8000 18900 8000 18600 1 0 0
+{
+T 7950 18700 5 8 1 1 90 0 1
+pinnumber=90
+T 8050 18700 5 8 0 1 90 2 1
+pinseq=86
+T 8000 18550 9 8 1 1 90 6 1
+pinlabel=P6[1]
+T 8000 18550 5 8 0 1 90 8 1
+pintype=io
+}
+P 8700 18900 8700 18600 1 0 0
+{
+T 8650 18700 5 8 1 1 90 0 1
+pinnumber=89
+T 8750 18700 5 8 0 1 90 2 1
+pinseq=87
+T 8700 18550 9 8 1 1 90 6 1
+pinlabel=P6[0]
+T 8700 18550 5 8 0 1 90 8 1
+pintype=io
+}
+P 9400 18900 9400 18600 1 0 0
+{
+T 9350 18700 5 8 1 1 90 0 1
+pinnumber=88
+T 9450 18700 5 8 0 1 90 2 1
+pinseq=88
+T 9400 18550 9 8 1 1 90 6 1
+pinlabel=VDDD
+T 9400 18550 5 8 0 1 90 8 1
+pintype=pwr
+}
+P 10100 18900 10100 18600 1 0 0
+{
+T 10050 18700 5 8 1 1 90 0 1
+pinnumber=87
+T 10150 18700 5 8 0 1 90 2 1
+pinseq=89
+T 10100 18550 9 8 1 1 90 6 1
+pinlabel=VSSD
+T 10100 18550 5 8 0 1 90 8 1
+pintype=pwr
+}
+P 10800 18900 10800 18600 1 0 0
+{
+T 10750 18700 5 8 1 1 90 0 1
+pinnumber=86
+T 10850 18700 5 8 0 1 90 2 1
+pinseq=90
+T 10800 18550 9 8 1 1 90 6 1
+pinlabel=VCCD
+T 10800 18550 5 8 0 1 90 8 1
+pintype=pwr
+}
+P 11500 18900 11500 18600 1 0 0
+{
+T 11450 18700 5 8 1 1 90 0 1
+pinnumber=85
+T 11550 18700 5 8 0 1 90 2 1
+pinseq=91
+T 11500 18550 9 8 1 1 90 6 1
+pinlabel=P4[7]
+T 11500 18550 5 8 0 1 90 8 1
+pintype=io
+}
+P 12200 18900 12200 18600 1 0 0
+{
+T 12150 18700 5 8 1 1 90 0 1
+pinnumber=84
+T 12250 18700 5 8 0 1 90 2 1
+pinseq=92
+T 12200 18550 9 8 1 1 90 6 1
+pinlabel=P4[6]
+T 12200 18550 5 8 0 1 90 8 1
+pintype=io
+}
+P 12900 18900 12900 18600 1 0 0
+{
+T 12850 18700 5 8 1 1 90 0 1
+pinnumber=83
+T 12950 18700 5 8 0 1 90 2 1
+pinseq=93
+T 12900 18550 9 8 1 1 90 6 1
+pinlabel=P4[5]
+T 12900 18550 5 8 0 1 90 8 1
+pintype=io
+}
+P 13600 18900 13600 18600 1 0 0
+{
+T 13550 18700 5 8 1 1 90 0 1
+pinnumber=82
+T 13650 18700 5 8 0 1 90 2 1
+pinseq=94
+T 13600 18550 9 8 1 1 90 6 1
+pinlabel=P4[4]
+T 13600 18550 5 8 0 1 90 8 1
+pintype=io
+}
+P 14300 18900 14300 18600 1 0 0
+{
+T 14250 18700 5 8 1 1 90 0 1
+pinnumber=81
+T 14350 18700 5 8 0 1 90 2 1
+pinseq=95
+T 14300 18550 9 8 1 1 90 6 1
+pinlabel=P4[3]
+T 14300 18550 5 8 0 1 90 8 1
+pintype=io
+}
+P 15000 18900 15000 18600 1 0 0
+{
+T 14950 18700 5 8 1 1 90 0 1
+pinnumber=80
+T 15050 18700 5 8 0 1 90 2 1
+pinseq=96
+T 15000 18550 9 8 1 1 90 6 1
+pinlabel=P4[2]
+T 15000 18550 5 8 0 1 90 8 1
+pintype=io
+}
+P 15700 18900 15700 18600 1 0 0
+{
+T 15650 18700 5 8 1 1 90 0 1
+pinnumber=79
+T 15750 18700 5 8 0 1 90 2 1
+pinseq=97
+T 15700 18550 9 8 1 1 90 6 1
+pinlabel=P0[7]
+T 15700 18550 5 8 0 1 90 8 1
+pintype=io
+}
+P 16400 18900 16400 18600 1 0 0
+{
+T 16350 18700 5 8 1 1 90 0 1
+pinnumber=78
+T 16450 18700 5 8 0 1 90 2 1
+pinseq=98
+T 16400 18550 9 8 1 1 90 6 1
+pinlabel=P0[6]
+T 16400 18550 5 8 0 1 90 8 1
+pintype=io
+}
+P 17100 18900 17100 18600 1 0 0
+{
+T 17050 18700 5 8 1 1 90 0 1
+pinnumber=77
+T 17150 18700 5 8 0 1 90 2 1
+pinseq=99
+T 17100 18550 9 8 1 1 90 6 1
+pinlabel=P0[5]
+T 17100 18550 5 8 0 1 90 8 1
+pintype=io
+}
+P 17800 18900 17800 18600 1 0 0
+{
+T 17750 18700 5 8 1 1 90 0 1
+pinnumber=76
+T 17850 18700 5 8 0 1 90 2 1
+pinseq=100
+T 17800 18550 9 8 1 1 90 6 1
+pinlabel=P0[4]
+T 17800 18550 5 8 0 1 90 8 1
+pintype=io
+}
+B 400 400 18000 18200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 18400 18700 8 10 1 1 0 6 1
+refdes=U?
+T 9200 9400 9 10 1 0 0 0 1
+CY8C53
+T 9200 9700 5 10 0 0 0 0 1
+device=CY8C53
+T 9200 9900 5 10 0 0 0 0 1
+footprint=TQFP100_14
+T 9200 10100 5 10 0 0 0 0 1
+author=Michael McMaster <michael@codesrc.com>
+T 9200 10300 5 10 0 0 0 0 1
+documentation=http://www.cypress.com/?id=2233
+T 9200 10500 5 10 0 0 0 0 1
+description=Cypress PSoC5 CY8C53
+T 9200 10700 5 10 0 0 0 0 1
+numslots=0
+T 9200 10900 5 10 0 0 0 0 1
+dist-license=gpl3+
+T 9200 11100 5 10 0 0 0 0 1
+use-license=gpl3+
--- /dev/null
+# This is the template file for creating symbols with tragesym
+# every line starting with '#' is a comment line.
+
+[options]
+# wordswap swaps labels if the pin is on the right side an looks like this:
+# "PB1 (CLK)". That's useful for micro controller port labels
+# rotate_labels rotates the pintext of top and bottom pins
+# this is useful for large symbols like FPGAs with more than 100 pins
+# sort_labels will sort the pins by it's labels
+# useful for address ports, busses, ...
+wordswap=yes
+rotate_labels=yes
+sort_labels=no
+generate_pinseq=yes
+sym_width=18000
+pinwidthvertical=700
+pinwidthhorizontal=700
+
+[geda_attr]
+# name will be printed in the top of the symbol
+# name is only some graphical text, not an attribute
+# version specifies a gschem version.
+# if you have a device with slots, you'll have to use slot= and slotdef=
+# use comment= if there are special information you want to add
+version=20060113 1
+name=CY8C53
+device=CY8C53
+refdes=U?
+footprint=TQFP100_14
+description=Cypress PSoC5 CY8C53
+documentation=http://www.cypress.com/?id=2233
+author=Michael McMaster <michael@codesrc.com>
+dist-license=gpl3+
+use-license=gpl3+
+numslots=0
+#slot=1
+#slotdef=1:
+#slotdef=2:
+#slotdef=3:
+#slotdef=4:
+#comment=
+#comment=
+#comment=
+
+[pins]
+# tabseparated list of pin descriptions
+# ----------------------------------------
+# pinnr is the physical number of the pin
+# seq is the pinseq= attribute, leave it blank if it doesn't matter
+# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
+# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net
+# posit. can be (l,r,t,b) or empty for nets.
+# net specifies the name of the net. Vcc or GND for example.
+# label represents the pinlabel.
+# negation lines can be added with "\_" example: \_enable\_
+# if you want to write a "\" use "\\" as escape sequence
+#-----------------------------------------------------
+#pinnr seq type style posit. net label
+#-----------------------------------------------------
+1 io line l P2[5]
+2 io line l P2[6]
+3 io line l P2[7]
+4 io line l P12[4]
+5 io line l P12[5]
+6 io line l P6[4]
+7 io line l P6[5]
+8 io line l P6[6]
+9 io line l P6[7]
+10 pwr line l GND VSSD
+11 io line l NC
+12 pwr line l GND VSSD
+13 pwr line l GND VSSD
+14 pwr line l GND VSSD
+15 in line l \_XRES\_
+16 io line l P5[0]
+17 io line l P5[1]
+18 io line l P5[2]
+19 io line l P5[3]
+20 io line l SWDIO,P1[0]
+21 io line l SWDCK,P1[1]
+22 io line l P1[2]
+23 io line l SWV,P1[3]
+24 io line l P1[4]
+25 io line l P1[5]
+
+
+26 pwr line b VDDIO1
+27 io line b P1[6]
+28 io line b P1[7]
+29 io line b P12[6]
+30 io line b P12[7]
+31 io line b P5[4]
+32 io line b P5[5]
+33 io line b P5[6]
+34 io line b P5[7]
+35 io line b SWDIO,USB D+
+36 io line b SWDCK,USB D-
+37 pwr line b VDDD
+38 pwr line b GND VSSD
+39 pwr line b VCCD
+40 io line b NC
+41 io line b NC
+42 clk clk b MHZ XTAL XO
+43 clk clk b MHZ XTAL XI
+44 io line b P3[0]
+45 io line b P3[1]
+46 io line b P3[2]
+47 io line b P3[3]
+48 io line b P3[4]
+49 io line b P3[5]
+50 pwr line b VDDIO3
+
+75 pwr line r VDDIO0
+74 io line r P0[3]
+73 io line r P0[2]
+72 io line r P0[1]
+71 io line r P0[0]
+70 io line r P4[1]
+69 io line r P4[0]
+68 io line r P12[3]
+67 io line r P12[2]
+66 pwr line r GND VSSD
+65 pwr line r VDDA
+64 pwr line r GND VSSA
+63 pwr line r VCCA
+62 io line r NC
+61 io line r NC
+60 io line r NC
+59 io line r NC
+58 io line r NC
+57 io line r NC
+56 io line r P15[3],KHZ XTAL XI
+55 io line r P15[2],KHZ XTAL XO
+54 io line r P12[1]
+53 io line r P12[0]
+52 io line r P3[7]
+51 io line r P3[6]
+
+100 pwr line t VDDIO2
+99 io line t P2[4]
+98 io line t P2[3]
+97 io line t P2[2]
+96 io line t P2[1]
+95 io line t P2[0]
+94 io line t P15[5]
+93 io line t P15[4]
+92 io line t P6[3]
+91 io line t P6[2]
+90 io line t P6[1]
+89 io line t P6[0]
+88 pwr line t VDDD
+87 pwr line t GND VSSD
+86 pwr line t VCCD
+85 io line t P4[7]
+84 io line t P4[6]
+83 io line t P4[5]
+82 io line t P4[4]
+81 io line t P4[3]
+80 io line t P4[2]
+79 io line t P0[7]
+78 io line t P0[6]
+77 io line t P0[5]
+76 io line t P0[4]
+
--- /dev/null
+Element[0x00000000 "DIO__DO-41-vertical.fp" "D?" "" 172500 127500 -9900
+6050 0 100 0x00000000]
+(
+ Pin[-6200 0 9500 2000 10700 4200 "" "1" 0x0101]
+ Pin[6200 0 9500 2000 10700 4200 "" "2" 0x01]
+ ElementLine [-11450 -5300 6200 -5300 1000]
+ ElementLine [-11450 5300 6200 5300 1000]
+ ElementLine [-11450 -5300 -11450 5300 1000]
+ ElementArc [6200 0 5300 5300 90 180 1000]
+ )
--- /dev/null
+Element[0x00000000 "DO-41" "D?" "" 172500 127500 -9900 6050 0 100 0x00000000]
+(
+ Pin[-21250 0 9500 2000 10700 4200 "" "1" 0x0101]
+ Pin[21250 0 9500 2000 10700 4200 "" "2" 0x01]
+ ElementLine [-9850 -5050 9850 -5050 1000]
+ ElementLine [9850 -5050 9850 5050 1000]
+ ElementLine [9850 5050 -9850 5050 1000]
+ ElementLine [-9850 5050 -9850 -5050 1000]
+ ElementLine [-6800 -5050 -6800 5050 1000]
+ )
--- /dev/null
+
+Element["" "" "" "" 12750 8250 0 0 0 100 ""]
+(
+ Pad[8250 10750 8250 10750 26500 2000 27500 "2" "2" "square,nopaste"]
+
+ Pad[750 3250 750 3250 11500 2000 12500 "2_1" "2" "square"]
+ Pad[750 18250 750 18250 11500 2000 12500 "2_2" "2" "square"]
+ Pad[15750 3250 15750 3250 11500 2000 12500 "2_3" "2" "square,edge2"]
+ Pad[15750 18250 15750 18250 11500 2000 12500 "2_4" "2" "square,edge2"]
+
+ Pad[31750 1750 37250 1750 6500 2000 7500 "3" "3" "square,edge2"]
+ Pad[31750 19750 37250 19750 6500 2000 7500 "1" "1" "square,edge2"]
+ ElementLine [-7500 -5000 44500 -5000 1000]
+ ElementLine [44500 -5000 44500 26500 1000]
+ ElementLine [44500 26500 -7500 26500 1000]
+ ElementLine [-7500 26500 -7500 -5000 1000]
+ ElementLine [28500 10500 32500 10500 1000]
+
+ )
+
--- /dev/null
+
+Element["" "FCI SD Card 10067847" "" "" 88425 50698 0 0 0 100 ""]
+(
+ Pin[-56138 64233 7906 2 6906 5906 "" "" ""]
+ Pin[39138 64233 7906 2 6906 5906 "" "" ""]
+ Pad[-62044 53997 -62044 57934 4724 2 4725 "GND_SHIELD" "12" "square,edge2"]
+ Pad[28311 -32027 28311 -30451 4330 2 4331 "PIN9" "9" "square"]
+ Pad[-60074 -32224 -60074 -30254 3937 2 3938 "WP" "10" "square"]
+ Pad[-46886 -32026 -46886 -30452 4331 2 4332 "PIN8" "8" "square"]
+ Pad[-40192 -32026 -40192 -30452 4331 2 4332 "PIN7" "7" "square"]
+ Pad[-30744 -32027 -30744 -30451 4330 2 4331 "PIN6" "6" "square"]
+ Pad[-20902 -32026 -20902 -30452 4331 2 4332 "PIN5" "5" "square"]
+ Pad[-11059 -32027 -11059 -30451 4330 2 4331 "PIN4" "4" "square"]
+ Pad[8626 -32027 8626 -30451 4330 2 4331 "PIN2" "2" "square"]
+ Pad[2130 -32224 2130 -30254 3937 2 3938 "CD" "11" "square"]
+ Pad[-4366 -32027 -4366 -30451 4330 2 4331 "PIN3" "3" "square"]
+ Pad[18468 -32026 18468 -30452 4331 2 4332 "PIN1" "1" "square"]
+ Pad[48193 49272 48193 53210 4724 2 4725 "GND_SHIELD" "13" "square,edge2"]
+ ElementLine [50162 -29074 50162 45730 800]
+ ElementLine [50162 83918 50162 56843 800]
+ ElementLine [-63666 50697 -63666 -29082 800]
+ ElementLine [-63666 83918 -63666 61701 800]
+ ElementLine [-56592 -29082 -50304 -29082 800]
+ ElementLine [31841 -29074 31833 -29082 800]
+ ElementLine [50162 -29074 31841 -29074 800]
+ ElementLine [50162 83918 -63618 83918 800]
+ ElementLine [-49051 -7814 30476 -7814 800]
+ ElementLine [30476 -7814 30476 12265 800]
+ ElementLine [30476 12265 -49051 12265 800]
+ ElementLine [-49051 12265 -49051 -7814 800]
+ ElementLine [-46767 -4716 -46767 10218 800]
+ ElementLine [-46767 10218 28296 10218 800]
+ ElementLine [28296 10218 28296 -5895 800]
+ ElementLine [28296 -5895 -44016 -5895 800]
+ ElementLine [-44016 -5895 -44016 7860 800]
+ ElementLine [-44016 7860 25545 7860 800]
+ ElementLine [25545 7860 25545 -3930 800]
+ ElementLine [25545 -3930 -41658 -3930 800]
+ ElementLine [-41658 -3930 -41658 5502 800]
+ ElementLine [-41658 5502 23187 5502 800]
+ ElementLine [23187 5502 23187 -1965 800]
+ ElementLine [23187 -1965 -38907 -1965 800]
+ ElementLine [-38907 -1965 -38907 3537 800]
+ ElementLine [-38907 3537 20829 3537 800]
+ ElementLine [20829 3537 20829 0 800]
+ ElementLine [20829 0 -36942 0 800]
+ ElementLine [-36942 0 -36942 1965 800]
+ ElementLine [-36942 1965 18471 1965 800]
+ ElementLine [18471 1965 18864 1572 800]
+ ElementLine [-66375 7146 -61650 7146 800]
+ ElementLine [-61650 7146 -61650 31782 800]
+ ElementLine [-61650 31782 -61701 31833 800]
+ ElementLine [-61701 31833 -66417 31833 800]
+ ElementLine [-66417 31833 -66417 7188 800]
+ ElementLine [-66417 7188 -66375 7146 800]
+ ElementLine [-65631 8253 -62487 11397 800]
+ ElementLine [-62487 11397 -65631 14541 800]
+ ElementLine [-65631 14541 -62487 17685 800]
+ ElementLine [-62487 17685 -65631 20829 800]
+ ElementLine [-65631 20829 -62487 23973 800]
+ ElementLine [-62487 23973 -65631 27117 800]
+ ElementLine [-65631 27117 -62487 30261 800]
+ ElementLine [-62487 30261 -62880 30261 800]
+ ElementLine [-62880 30261 -64452 31833 800]
+
+ )
--- /dev/null
+v 20060113 1
+P 100 4900 400 4900 1 0 0
+{
+T 300 4950 5 8 1 1 0 6 1
+pinnumber=9
+T 300 4850 5 8 0 1 0 8 1
+pinseq=1
+T 450 4900 9 8 1 1 0 0 1
+pinlabel=DAT2
+T 450 4900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 4500 400 4500 1 0 0
+{
+T 300 4550 5 8 1 1 0 6 1
+pinnumber=1
+T 300 4450 5 8 0 1 0 8 1
+pinseq=2
+T 450 4500 9 8 1 1 0 0 1
+pinlabel=DAT3,\_CS\_
+T 450 4500 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 4100 400 4100 1 0 0
+{
+T 300 4150 5 8 1 1 0 6 1
+pinnumber=2
+T 300 4050 5 8 0 1 0 8 1
+pinseq=3
+T 450 4100 9 8 1 1 0 0 1
+pinlabel=CMD/DI,MOSI
+T 450 4100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 3700 400 3700 1 0 0
+{
+T 300 3750 5 8 1 1 0 6 1
+pinnumber=3
+T 300 3650 5 8 0 1 0 8 1
+pinseq=4
+T 450 3700 9 8 1 1 0 0 1
+pinlabel=GND
+T 450 3700 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 3300 400 3300 1 0 0
+{
+T 300 3350 5 8 1 1 0 6 1
+pinnumber=4
+T 300 3250 5 8 0 1 0 8 1
+pinseq=5
+T 450 3300 9 8 1 1 0 0 1
+pinlabel=Vcc
+T 450 3300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 2900 400 2900 1 0 0
+{
+T 300 2950 5 8 1 1 0 6 1
+pinnumber=5
+T 300 2850 5 8 0 1 0 8 1
+pinseq=6
+T 450 2900 9 8 1 1 0 0 1
+pinlabel=SCK
+T 450 2900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 2500 400 2500 1 0 0
+{
+T 300 2550 5 8 1 1 0 6 1
+pinnumber=6
+T 300 2450 5 8 0 1 0 8 1
+pinseq=7
+T 450 2500 9 8 1 1 0 0 1
+pinlabel=GND
+T 450 2500 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 2100 400 2100 1 0 0
+{
+T 300 2150 5 8 1 1 0 6 1
+pinnumber=7
+T 300 2050 5 8 0 1 0 8 1
+pinseq=8
+T 450 2100 9 8 1 1 0 0 1
+pinlabel=DAT0/DO,MISO
+T 450 2100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 1700 400 1700 1 0 0
+{
+T 300 1750 5 8 1 1 0 6 1
+pinnumber=8
+T 300 1650 5 8 0 1 0 8 1
+pinseq=9
+T 450 1700 9 8 1 1 0 0 1
+pinlabel=DAT1/IRQ
+T 450 1700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 1300 400 1300 1 0 0
+{
+T 300 1350 5 8 1 1 0 6 1
+pinnumber=11
+T 300 1250 5 8 0 1 0 8 1
+pinseq=10
+T 450 1300 9 8 1 1 0 0 1
+pinlabel=\_CD\_
+T 450 1300 5 8 0 1 0 2 1
+pintype=out
+}
+P 100 900 400 900 1 0 0
+{
+T 300 950 5 8 1 1 0 6 1
+pinnumber=12
+T 300 850 5 8 0 1 0 8 1
+pinseq=11
+T 450 900 9 8 1 1 0 0 1
+pinlabel=GND
+T 450 900 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 500 400 500 1 0 0
+{
+T 300 550 5 8 1 1 0 6 1
+pinnumber=10
+T 300 450 5 8 0 1 0 8 1
+pinseq=12
+T 450 500 9 8 1 1 0 0 1
+pinlabel=\_WP\_
+T 450 500 5 8 0 1 0 2 1
+pintype=out
+}
+B 400 100 1000 5200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 1400 5400 8 10 1 1 0 6 1
+refdes=J?
+T 400 5400 9 10 1 0 0 0 1
+FCI-10067847-001RLF
+T 400 5600 5 10 0 0 0 0 1
+device=FCI-10067847-001RLF
+T 400 5800 5 10 0 0 0 0 1
+footprint=FCI-10067847-001RLF
+T 400 6000 5 10 0 0 0 0 1
+author=Michael McMaster <michael@codesrc.com>
+T 400 6200 5 10 0 0 0 0 1
+documentation=http://www.alps.com/WebObjects/catalog.woa/E/HTML/Connector/SDMemoryCard/SCDA/SCDA7A0101.html
+T 400 6400 5 10 0 0 0 0 1
+description=FCI SD Card 10067847-001RLF
+T 400 6600 5 10 0 0 0 0 1
+numslots=0
+T 400 6800 5 10 0 0 0 0 1
+dist-license=gpl3+
+T 400 7000 5 10 0 0 0 0 1
+use-license=gpl3+
+T 400 7200 5 10 0 0 0 0 1
+net=GND:13
--- /dev/null
+# This is the template file for creating symbols with tragesym
+# every line starting with '#' is a comment line.
+
+[options]
+# wordswap swaps labels if the pin is on the right side an looks like this:
+# "PB1 (CLK)". That's useful for micro controller port labels
+# rotate_labels rotates the pintext of top and bottom pins
+# this is useful for large symbols like FPGAs with more than 100 pins
+# sort_labels will sort the pins by it's labels
+# useful for address ports, busses, ...
+wordswap=yes
+rotate_labels=yes
+sort_labels=no
+generate_pinseq=yes
+sym_width=1000
+pinwidthvertical=400
+pinwidthhorizontal=400
+
+[geda_attr]
+# name will be printed in the top of the symbol
+# name is only some graphical text, not an attribute
+# version specifies a gschem version.
+# if you have a device with slots, you'll have to use slot= and slotdef=
+# use comment= if there are special information you want to add
+version=20060113 1
+name=FCI-10067847-001RLF
+device=FCI-10067847-001RLF
+refdes=J?
+footprint=FCI-10067847-001RLF
+description=FCI SD Card 10067847-001RLF
+documentation=http://www.alps.com/WebObjects/catalog.woa/E/HTML/Connector/SDMemoryCard/SCDA/SCDA7A0101.html
+author=Michael McMaster <michael@codesrc.com>
+dist-license=gpl3+
+use-license=gpl3+
+numslots=0
+#slot=1
+#slotdef=1:
+#slotdef=2:
+#slotdef=3:
+#slotdef=4:
+#comment=
+#comment=
+#comment=
+
+[pins]
+# tabseparated list of pin descriptions
+# ----------------------------------------
+# pinnr is the physical number of the pin
+# seq is the pinseq= attribute, leave it blank if it doesn't matter
+# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
+# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net
+# posit. can be (l,r,t,b) or empty for nets.
+# net specifies the name of the net. Vcc or GND for example.
+# label represents the pinlabel.
+# negation lines can be added with "\_" example: \_enable\_
+# if you want to write a "\" use "\\" as escape sequence
+#-----------------------------------------------------
+#pinnr seq type style posit. net label
+#-----------------------------------------------------
+9 io line l DAT2
+1 io line l DAT3,\_CS\_
+2 io line l CMD/DI,MOSI
+3 PWR line l GND GND
+4 io line l Vcc
+5 io line l SCK
+6 PWR line l GND GND
+7 io line l DAT0/DO,MISO
+8 io line l DAT1/IRQ
+11 out line l \_CD\_
+12 pwr line l GND GND
+10 out line l \_WP\_
+13 pwr none r GND GND
+
--- /dev/null
+
+Element["" "" "" "" 12500 1700 0 0 0 100 ""]
+(
+ Pad[20550 356 20550 8456 2900 1200 4100 "" "10" ""]
+ Pad[15550 356 15550 8456 2900 1200 4100 "" "8" ""]
+ Pad[10550 356 10550 8456 2900 1200 4100 "" "6" ""]
+ Pad[5550 356 5550 8456 2900 1200 4100 "" "4" ""]
+ Pad[550 356 550 8456 2900 1200 4100 "" "2" ""]
+ Pad[20550 16356 20550 24456 2900 1200 4100 "" "9" "edge2"]
+ Pad[15550 16356 15550 24456 2900 1200 4100 "" "7" "edge2"]
+ Pad[10550 16356 10550 24456 2900 1200 4100 "" "5" "edge2"]
+ Pad[5550 16356 5550 24456 2900 1200 4100 "" "3" "edge2"]
+ Pad[550 16356 550 24456 2900 1200 4100 "" "1" "edge2"]
+ ElementLine [33000 19406 33000 5606 1000]
+ ElementLine [-12000 5606 -12000 19406 1000]
+ ElementLine [-12000 5606 -2906 5606 1000]
+ ElementLine [-2906 5606 -2900 5600 1000]
+ ElementLine [33000 5700 24200 5700 1000]
+ ElementLine [-12000 19400 -2900 19400 1000]
+ ElementLine [33000 19400 24300 19400 1000]
+ ElementLine [-2900 19400 -2900 14000 1000]
+ ElementLine [-2900 14000 24300 14000 1000]
+ ElementLine [24300 14000 24300 19400 1000]
+
+ )
--- /dev/null
+Element(0x00 "Right-angle Header connector, ribbon cable numbering" "" "HEADER50_2" 260 0 3 100 0x00)
+(
+ Pin(150 2450 60 38 "1" 0x01)
+ Pin(50 2450 60 38 "2" 0x01)
+ Pin(150 2350 60 38 "3" 0x01)
+ Pin(50 2350 60 38 "4" 0x01)
+ Pin(150 2250 60 38 "5" 0x01)
+ Pin(50 2250 60 38 "6" 0x01)
+ Pin(150 2150 60 38 "7" 0x01)
+ Pin(50 2150 60 38 "8" 0x01)
+ Pin(150 2050 60 38 "9" 0x01)
+ Pin(50 2050 60 38 "10" 0x01)
+ Pin(150 1950 60 38 "11" 0x01)
+ Pin(50 1950 60 38 "12" 0x01)
+ Pin(150 1850 60 38 "13" 0x01)
+ Pin(50 1850 60 38 "14" 0x01)
+ Pin(150 1750 60 38 "15" 0x01)
+ Pin(50 1750 60 38 "16" 0x01)
+ Pin(150 1650 60 38 "17" 0x01)
+ Pin(50 1650 60 38 "18" 0x01)
+ Pin(150 1550 60 38 "19" 0x01)
+ Pin(50 1550 60 38 "20" 0x01)
+ Pin(150 1450 60 38 "21" 0x01)
+ Pin(50 1450 60 38 "22" 0x01)
+ Pin(150 1350 60 38 "23" 0x01)
+ Pin(50 1350 60 38 "24" 0x01)
+ Pin(150 1250 60 38 "25" 0x01)
+ Pin(50 1250 60 38 "26" 0x01)
+ Pin(150 1150 60 38 "27" 0x01)
+ Pin(50 1150 60 38 "28" 0x01)
+ Pin(150 1050 60 38 "29" 0x01)
+ Pin(50 1050 60 38 "30" 0x01)
+ Pin(150 950 60 38 "31" 0x01)
+ Pin(50 950 60 38 "32" 0x01)
+ Pin(150 850 60 38 "33" 0x01)
+ Pin(50 850 60 38 "34" 0x01)
+ Pin(150 750 60 38 "35" 0x01)
+ Pin(50 750 60 38 "36" 0x01)
+ Pin(150 650 60 38 "37" 0x01)
+ Pin(50 650 60 38 "38" 0x01)
+ Pin(150 550 60 38 "39" 0x01)
+ Pin(50 550 60 38 "40" 0x01)
+ Pin(150 450 60 38 "41" 0x01)
+ Pin(50 450 60 38 "42" 0x01)
+ Pin(150 350 60 38 "43" 0x01)
+ Pin(50 350 60 38 "44" 0x01)
+ Pin(150 250 60 38 "45" 0x01)
+ Pin(50 250 60 38 "46" 0x01)
+ Pin(150 150 60 38 "47" 0x01)
+ Pin(50 150 60 38 "48" 0x01)
+ Pin(150 50 60 38 "49" 0x01)
+ Pin(50 50 60 38 "50" 0x101)
+ ElementLine(0 0 0 2500 10)
+ ElementLine(0 2500 200 2500 10)
+ ElementLine(200 2500 200 0 10)
+ ElementLine(200 0 0 0 10)
+ ElementLine(0 100 100 100 10)
+ ElementLine(100 100 100 0 10)
+ ElementLine(-350 0 0 0 10)
+ ElementLine(-350 0 -350 2500 10)
+ ElementLine(-350 2500 0 2500 10)
+ Mark(50 50)
+
+)
--- /dev/null
+v 20060113 1
+P 900 100 900 400 1 0 0
+{
+T 850 300 5 8 1 1 90 6 1
+pinnumber=1
+T 950 300 5 8 0 1 90 8 1
+pinseq=1
+T 900 450 9 8 1 1 90 0 1
+pinlabel=GND
+T 900 450 5 8 0 1 90 2 1
+pintype=pwr
+}
+P 1700 800 1400 800 1 0 0
+{
+T 1500 850 5 8 1 1 0 0 1
+pinnumber=2
+T 1500 750 5 8 0 1 0 2 1
+pinseq=2
+T 1350 800 9 8 1 1 0 6 1
+pinlabel=OUT
+T 1350 800 5 8 0 1 0 8 1
+pintype=pwr
+}
+P 100 800 400 800 1 0 0
+{
+T 300 850 5 8 1 1 0 6 1
+pinnumber=3
+T 300 750 5 8 0 1 0 8 1
+pinseq=3
+T 450 800 9 8 1 1 0 0 1
+pinlabel=IN
+T 450 800 5 8 0 1 0 2 1
+pintype=pwr
+}
+B 400 400 1000 800 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 1400 1300 8 10 1 1 0 6 1
+refdes=U?
+T 400 1300 9 10 1 0 0 0 1
+LD1117
+T 400 1500 5 10 0 0 0 0 1
+device=LD1117
+T 400 1700 5 10 0 0 0 0 1
+footprint=DPAK
+T 400 1900 5 10 0 0 0 0 1
+author=Michael McMaster <michael@codesrc.com>
+T 400 2100 5 10 0 0 0 0 1
+documentation=http://www.st.com/web/en/resource/technical/document/datasheet/CD00000544.pdf
+T 400 2300 5 10 0 0 0 0 1
+description=LDO Regulator, fixed
+T 400 2500 5 10 0 0 0 0 1
+numslots=0
+T 400 2700 5 10 0 0 0 0 1
+dist-license=gpl3+
+T 400 2900 5 10 0 0 0 0 1
+use-license=gpl3+
--- /dev/null
+# This is the template file for creating symbols with tragesym
+# every line starting with '#' is a comment line.
+
+[options]
+# wordswap swaps labels if the pin is on the right side an looks like this:
+# "PB1 (CLK)". That's useful for micro controller port labels
+# rotate_labels rotates the pintext of top and bottom pins
+# this is useful for large symbols like FPGAs with more than 100 pins
+# sort_labels will sort the pins by it's labels
+# useful for address ports, busses, ...
+wordswap=yes
+rotate_labels=yes
+sort_labels=no
+generate_pinseq=yes
+sym_width=1000
+pinwidthvertical=400
+pinwidthhorizontal=400
+
+[geda_attr]
+# name will be printed in the top of the symbol
+# name is only some graphical text, not an attribute
+# version specifies a gschem version.
+# if you have a device with slots, you'll have to use slot= and slotdef=
+# use comment= if there are special information you want to add
+version=20060113 1
+name=LD1117
+device=LD1117
+refdes=U?
+footprint=DPAK
+description=LDO Regulator, fixed
+documentation=http://www.st.com/web/en/resource/technical/document/datasheet/CD00000544.pdf
+author=Michael McMaster <michael@codesrc.com>
+dist-license=gpl3+
+use-license=gpl3+
+numslots=0
+#slot=1
+#slotdef=1:
+#slotdef=2:
+#slotdef=3:
+#slotdef=4:
+#comment=
+#comment=
+#comment=
+
+[pins]
+# tabseparated list of pin descriptions
+# ----------------------------------------
+# pinnr is the physical number of the pin
+# seq is the pinseq= attribute, leave it blank if it doesn't matter
+# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
+# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net
+# posit. can be (l,r,t,b) or empty for nets.
+# net specifies the name of the net. Vcc or GND for example.
+# label represents the pinlabel.
+# negation lines can be added with "\_" example: \_enable\_
+# if you want to write a "\" use "\\" as escape sequence
+#-----------------------------------------------------
+#pinnr seq type style posit. net label
+#-----------------------------------------------------
+1 pwr line b GND GND
+2 pwr line r OUT
+3 pwr line l IN
+
+
--- /dev/null
+Element ["" "Molex 15-24-4441" "" "" 10000 10000 8000 8000 0 100 ""] (
+ Pin [0 0 10000 3000 11000 6000 "Pin4" "4" ""]
+ Pin [20000 0 10000 3000 11000 6000 "Pin3" "3" ""]
+ Pin [40000 0 10000 3000 11000 6000 "Pin2" "2" ""]
+ Pin [60000 0 10000 3000 11000 6000 "Pin1" "1" ""]
+ Pin [-10000 -10000 11000 3000 11000 10000 "LeftHole" "" "hole"]
+ Pin [70000 -10000 11000 3000 11000 10000 "RightHole" "" "hole"]
+
+ Pin [10000 -40000 16000 3000 16000 15700 "BackLeftHole" "" "hole"]
+ Pin [50000 -40000 16000 3000 16000 15700 "BackRightHole" "" "hole"]
+
+ ElementLine[-16000 9000 76000 9000 1000]
+ ElementLine[-16000 9000 -16000 -50000 1000]
+ ElementLine[-16000 -50000 76000 -50000 1000]
+ ElementLine[76000 -50000 76000 9000 1000]
+)
+
+
--- /dev/null
+v 20060113 1
+P 100 1700 400 1700 1 0 0
+{
+T 300 1750 5 8 1 1 0 6 1
+pinnumber=1
+T 300 1650 5 8 0 1 0 8 1
+pinseq=1
+T 450 1700 9 8 1 1 0 0 1
+pinlabel=+12V
+T 450 1700 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 1300 400 1300 1 0 0
+{
+T 300 1350 5 8 1 1 0 6 1
+pinnumber=2
+T 300 1250 5 8 0 1 0 8 1
+pinseq=2
+T 450 1300 9 8 1 1 0 0 1
+pinlabel=GND
+T 450 1300 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 900 400 900 1 0 0
+{
+T 300 950 5 8 1 1 0 6 1
+pinnumber=3
+T 300 850 5 8 0 1 0 8 1
+pinseq=3
+T 450 900 9 8 1 1 0 0 1
+pinlabel=GND
+T 450 900 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 500 400 500 1 0 0
+{
+T 300 550 5 8 1 1 0 6 1
+pinnumber=4
+T 300 450 5 8 0 1 0 8 1
+pinseq=4
+T 450 500 9 8 1 1 0 0 1
+pinlabel=+5V
+T 450 500 5 8 0 1 0 2 1
+pintype=pwr
+}
+B 400 100 500 2000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 900 2200 8 10 1 1 0 6 1
+refdes=J?
+T 400 2200 9 10 1 0 0 0 1
+MOLEX8981
+T 400 2400 5 10 0 0 0 0 1
+device=MOLEX8981
+T 400 2600 5 10 0 0 0 0 1
+footprint=MOLEX
+T 400 2800 5 10 0 0 0 0 1
+author=Michael McMaster <michael@codesrc.com>
+T 400 3000 5 10 0 0 0 0 1
+description=Disk drive power connector
+T 400 3200 5 10 0 0 0 0 1
+numslots=0
+T 400 3400 5 10 0 0 0 0 1
+dist-license=gpl3+
+T 400 3600 5 10 0 0 0 0 1
+use-license=gpl3+
--- /dev/null
+# This is the template file for creating symbols with tragesym
+# every line starting with '#' is a comment line.
+
+[options]
+# wordswap swaps labels if the pin is on the right side an looks like this:
+# "PB1 (CLK)". That's useful for micro controller port labels
+# rotate_labels rotates the pintext of top and bottom pins
+# this is useful for large symbols like FPGAs with more than 100 pins
+# sort_labels will sort the pins by it's labels
+# useful for address ports, busses, ...
+wordswap=yes
+rotate_labels=yes
+sort_labels=no
+generate_pinseq=yes
+sym_width=500
+pinwidthvertical=400
+pinwidthhorizontal=400
+
+[geda_attr]
+# name will be printed in the top of the symbol
+# name is only some graphical text, not an attribute
+# version specifies a gschem version.
+# if you have a device with slots, you'll have to use slot= and slotdef=
+# use comment= if there are special information you want to add
+version=20060113 1
+name=MOLEX8981
+device=MOLEX8981
+refdes=J?
+footprint=MOLEX
+description=Disk drive power connector
+documentation=
+author=Michael McMaster <michael@codesrc.com>
+dist-license=gpl3+
+use-license=gpl3+
+numslots=0
+#slot=1
+#slotdef=1:
+#slotdef=2:
+#slotdef=3:
+#slotdef=4:
+#comment=
+#comment=
+#comment=
+
+[pins]
+# tabseparated list of pin descriptions
+# ----------------------------------------
+# pinnr is the physical number of the pin
+# seq is the pinseq= attribute, leave it blank if it doesn't matter
+# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
+# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net
+# posit. can be (l,r,t,b) or empty for nets.
+# net specifies the name of the net. Vcc or GND for example.
+# label represents the pinlabel.
+# negation lines can be added with "\_" example: \_enable\_
+# if you want to write a "\" use "\\" as escape sequence
+#-----------------------------------------------------
+#pinnr seq type style posit. net label
+#-----------------------------------------------------
+1 pwr line l +12V
+2 pwr line l GND
+3 pwr line l GND
+4 pwr line l +5V
--- /dev/null
+v 20060113 1
+P 100 4900 400 4900 1 0 0
+{
+T 300 4950 5 8 1 1 0 6 1
+pinnumber=9
+T 300 4850 5 8 0 1 0 8 1
+pinseq=1
+T 450 4900 9 8 1 1 0 0 1
+pinlabel=DAT2
+T 450 4900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 4500 400 4500 1 0 0
+{
+T 300 4550 5 8 1 1 0 6 1
+pinnumber=1
+T 300 4450 5 8 0 1 0 8 1
+pinseq=2
+T 450 4500 9 8 1 1 0 0 1
+pinlabel=DAT3,\_CS\_
+T 450 4500 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 4100 400 4100 1 0 0
+{
+T 300 4150 5 8 1 1 0 6 1
+pinnumber=2
+T 300 4050 5 8 0 1 0 8 1
+pinseq=3
+T 450 4100 9 8 1 1 0 0 1
+pinlabel=CMD/DI,MOSI
+T 450 4100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 3700 400 3700 1 0 0
+{
+T 300 3750 5 8 1 1 0 6 1
+pinnumber=3
+T 300 3650 5 8 0 1 0 8 1
+pinseq=4
+T 450 3700 9 8 1 1 0 0 1
+pinlabel=GND
+T 450 3700 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 3300 400 3300 1 0 0
+{
+T 300 3350 5 8 1 1 0 6 1
+pinnumber=4
+T 300 3250 5 8 0 1 0 8 1
+pinseq=5
+T 450 3300 9 8 1 1 0 0 1
+pinlabel=Vcc
+T 450 3300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 2900 400 2900 1 0 0
+{
+T 300 2950 5 8 1 1 0 6 1
+pinnumber=5
+T 300 2850 5 8 0 1 0 8 1
+pinseq=6
+T 450 2900 9 8 1 1 0 0 1
+pinlabel=SCK
+T 450 2900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 2500 400 2500 1 0 0
+{
+T 300 2550 5 8 1 1 0 6 1
+pinnumber=6
+T 300 2450 5 8 0 1 0 8 1
+pinseq=7
+T 450 2500 9 8 1 1 0 0 1
+pinlabel=GND
+T 450 2500 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 2100 400 2100 1 0 0
+{
+T 300 2150 5 8 1 1 0 6 1
+pinnumber=7
+T 300 2050 5 8 0 1 0 8 1
+pinseq=8
+T 450 2100 9 8 1 1 0 0 1
+pinlabel=DAT0/DO,MISO
+T 450 2100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 1700 400 1700 1 0 0
+{
+T 300 1750 5 8 1 1 0 6 1
+pinnumber=8
+T 300 1650 5 8 0 1 0 8 1
+pinseq=9
+T 450 1700 9 8 1 1 0 0 1
+pinlabel=DAT1/IRQ
+T 450 1700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 1300 400 1300 1 0 0
+{
+T 300 1350 5 8 1 1 0 6 1
+pinnumber=10
+T 300 1250 5 8 0 1 0 8 1
+pinseq=10
+T 450 1300 9 8 1 1 0 0 1
+pinlabel=\_CD\_
+T 450 1300 5 8 0 1 0 2 1
+pintype=out
+}
+P 100 900 400 900 1 0 0
+{
+T 300 950 5 8 1 1 0 6 1
+pinnumber=11
+T 300 850 5 8 0 1 0 8 1
+pinseq=11
+T 450 900 9 8 1 1 0 0 1
+pinlabel=GND
+T 450 900 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 500 400 500 1 0 0
+{
+T 300 550 5 8 1 1 0 6 1
+pinnumber=12
+T 300 450 5 8 0 1 0 8 1
+pinseq=12
+T 450 500 9 8 1 1 0 0 1
+pinlabel=\_WP\_
+T 450 500 5 8 0 1 0 2 1
+pintype=out
+}
+B 400 100 1000 5200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 1400 5400 8 10 1 1 0 6 1
+refdes=J?
+T 400 5400 9 10 1 0 0 0 1
+SCDA7A0101
+T 400 5600 5 10 0 0 0 0 1
+device=SCDA7A0101
+T 400 5800 5 10 0 0 0 0 1
+footprint=SCDA7A0101
+T 400 6000 5 10 0 0 0 0 1
+author=Michael McMaster <michael@codesrc.com>
+T 400 6200 5 10 0 0 0 0 1
+documentation=http://www.alps.com/WebObjects/catalog.woa/E/HTML/Connector/SDMemoryCard/SCDA/SCDA7A0101.html
+T 400 6400 5 10 0 0 0 0 1
+description=SD Memory Card Connector
+T 400 6600 5 10 0 0 0 0 1
+numslots=0
+T 400 6800 5 10 0 0 0 0 1
+dist-license=gpl3+
+T 400 7000 5 10 0 0 0 0 1
+use-license=gpl3+
+T 400 7200 5 10 0 0 0 0 1
+net=GND:13,14
--- /dev/null
+# This is the template file for creating symbols with tragesym
+# every line starting with '#' is a comment line.
+
+[options]
+# wordswap swaps labels if the pin is on the right side an looks like this:
+# "PB1 (CLK)". That's useful for micro controller port labels
+# rotate_labels rotates the pintext of top and bottom pins
+# this is useful for large symbols like FPGAs with more than 100 pins
+# sort_labels will sort the pins by it's labels
+# useful for address ports, busses, ...
+wordswap=yes
+rotate_labels=yes
+sort_labels=no
+generate_pinseq=yes
+sym_width=1000
+pinwidthvertical=400
+pinwidthhorizontal=400
+
+[geda_attr]
+# name will be printed in the top of the symbol
+# name is only some graphical text, not an attribute
+# version specifies a gschem version.
+# if you have a device with slots, you'll have to use slot= and slotdef=
+# use comment= if there are special information you want to add
+version=20060113 1
+name=SCDA7A0101
+device=SCDA7A0101
+refdes=J?
+footprint=SCDA7A0101
+description=SD Memory Card Connector
+documentation=http://www.alps.com/WebObjects/catalog.woa/E/HTML/Connector/SDMemoryCard/SCDA/SCDA7A0101.html
+author=Michael McMaster <michael@codesrc.com>
+dist-license=gpl3+
+use-license=gpl3+
+numslots=0
+#slot=1
+#slotdef=1:
+#slotdef=2:
+#slotdef=3:
+#slotdef=4:
+#comment=
+#comment=
+#comment=
+
+[pins]
+# tabseparated list of pin descriptions
+# ----------------------------------------
+# pinnr is the physical number of the pin
+# seq is the pinseq= attribute, leave it blank if it doesn't matter
+# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
+# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net
+# posit. can be (l,r,t,b) or empty for nets.
+# net specifies the name of the net. Vcc or GND for example.
+# label represents the pinlabel.
+# negation lines can be added with "\_" example: \_enable\_
+# if you want to write a "\" use "\\" as escape sequence
+#-----------------------------------------------------
+#pinnr seq type style posit. net label
+#-----------------------------------------------------
+9 io line l DAT2
+1 io line l DAT3,\_CS\_
+2 io line l CMD/DI,MOSI
+3 PWR line l GND GND
+4 io line l Vcc
+5 io line l SCK
+6 PWR line l GND GND
+7 io line l DAT0/DO,MISO
+8 io line l DAT1/IRQ
+10 out line l \_CD\_
+11 pwr line l GND GND
+12 out line l \_WP\_
+13 pwr none r GND GND
+14 pwr none r GND GND
+
--- /dev/null
+ # 78 for SOT23
+ # 82 for SOT23
+ # 41 for SOT23
+ # 34 for SOT23, 24 for SOT25
+Element(0x00 "SMT transistor, 3 pins" "" "SOT23" 148 0 3 100 0x00)
+(
+ ElementLine(0 0 0 139 10)
+ ElementLine(0 139 128 139 10)
+ ElementLine(128 139 128 0 10)
+ ElementLine(128 0 0 0 10)
+ # 1st side, 1st pin
+ Pad(25 107
+ 25 113
+ 34
+ "1" "G" 0x100)
+ # 1st side, 2nd pin
+ # 1st side, 3rd pin
+ Pad(103 107
+ 103 113
+ 34
+ "2" "S" 0x100)
+ # 2nd side, 3rd pin
+ # 2nd side, 2nd pin
+ Pad(64 25
+ 64 31
+ 34
+ "3" "D" 0x100)
+ # 2nd side, 1st pin
+ Mark(25 110)
+)
--- /dev/null
+ # 78 for SOT23
+ # 82 for SOT23
+ # 41 for SOT23
+ # 34 for SOT23, 24 for SOT25
+Element(0x00 "SMT transistor, 6 pins" "" "SOT26" 138 0 3 100 0x00)
+(
+ ElementLine(0 0 0 139 10)
+ ElementLine(0 139 118 139 10)
+ ElementLine(118 139 118 0 10)
+ ElementLine(118 0 0 0 10)
+ # 1st side, 1st pin
+ Pad(20 102
+ 20 118
+ 24 "1" "D" 0x100)
+ # 1st side, 2nd pin
+ Pad(59 102
+ 59 118
+ 24 "2" "D" 0x100)
+ # 1st side, 3rd pin
+ Pad(98 102
+ 98 118
+ 24 "3" "G" 0x100)
+ # 2nd side, 3rd pin
+ Pad(98 20
+ 98 36
+ 24 "4" "S" 0x100)
+ # 2nd side, 2nd pin
+ Pad(59 20
+ 59 36
+ 24 "5" "D" 0x100)
+ # 2nd side, 1st pin
+ Pad(20 20
+ 20 36
+ 24 "6" "D" 0x100)
+ Mark(20 110)
+)
--- /dev/null
+ Element(0x00 "Transistor" "" "TO220W" 0 10 0 100 0x00)
+(
+ Pin(100 200 90 60 "1" "B" 0x101)
+ Pin(200 200 90 60 "2" "C" 0x01)
+ Pin(300 200 90 60 "3" "E" 0x01)
+ # Gehaeuse
+ ElementLine( 0 80 400 80 20)
+ ElementLine(400 80 400 260 20)
+ ElementLine(400 260 0 260 20)
+ ElementLine( 0 260 0 80 20)
+ # Kuehlfahne icl. Bohrung
+ ElementLine( 0 80 400 80 20)
+ ElementLine(400 80 400 140 20)
+ ElementLine(400 140 0 140 20)
+ ElementLine( 0 140 0 80 20)
+ ElementLine(130 80 130 140 10)
+ ElementLine(270 80 270 140 10)
+ Mark(100 200)
+)
--- /dev/null
+
+Element["" "" "" "" 2137 2037 0 0 0 100 ""]
+(
+ Pad[3872 35 3872 35 1969 1200 2569 "1" "1" "square,edge2"]
+ Pad[-65 35 -65 35 1969 1200 2569 "2" "2" "square"]
+ ElementLine [-1837 1806 -1837 -1737 600]
+ ElementLine [5643 1806 -1837 1806 600]
+ ElementLine [5643 -1737 5643 1806 600]
+ ElementLine [-1837 -1737 5643 -1737 600]
+
+ )
--- /dev/null
+
+Element["" "" "" "" 235039 155118 0 0 0 100 ""]
+(
+ Pad[197 -591 984 -591 9055 2000 10055 "cathode" "1" "square"]
+ Pad[17126 -591 17913 -591 9055 2000 10055 "anode" "2" "square,edge2"]
+ ElementLine [-5118 -9843 -5118 9055 1000]
+ ElementLine [-5118 9055 23622 9055 1000]
+ ElementLine [23622 9055 23622 -9843 1000]
+ ElementLine [23622 -9843 -5118 -9843 1000]
+ ElementLine [-394 -9843 -394 -5906 1000]
+ ElementLine [-394 -5906 394 -5906 1000]
+ ElementLine [394 -5906 394 -9055 1000]
+ ElementLine [-394 9055 -394 5118 1000]
+ ElementLine [-394 5118 394 5118 1000]
+ ElementLine [394 5118 394 8268 1000]
+ ElementLine [10236 3937 7874 6299 1000]
+ ElementLine [7874 6299 10630 9055 1000]
+ ElementLine [10630 9055 10630 4331 1000]
+ ElementLine [10630 4331 10236 3937 1000]
+ ElementLine [10630 6299 16535 6299 1000]
+ ElementLine [7087 3543 7087 9055 1000]
+ ElementLine [4724 6299 7874 6299 1000]
+
+ )
--- /dev/null
+
+Element["" "" "" "" 275009 222794 0 0 0 100 ""]
+(
+ Pad[-63 -8271 -63 -4531 1575 1200 2175 "3" "3" "square"]
+ Pad[5055 -8271 5055 -4531 1575 1200 2175 "5" "5" "square"]
+ Pad[-5181 -8271 -5181 -4531 1575 1200 2175 "1" "1" "square"]
+ Pad[2496 -8271 2496 -4531 1575 1200 2175 "4" "4" "square"]
+ Pad[-2622 -8271 -2622 -4531 1575 1200 2175 "2" "2" "square"]
+ Pad[-13252 -5909 -11284 -5909 6299 1200 6899 "" "6" "square"]
+ Pad[11157 -5909 13126 -5909 6299 1200 6899 "" "7" "square,edge2"]
+ Pad[-15024 3934 -15024 4328 7087 1200 7687 "" "8" "square,edge2"]
+ Pad[-4788 4131 -4788 4131 7480 1200 8080 "" "9" "square"]
+ Pad[4661 4131 4661 4131 7480 1200 8080 "" "10" "square,edge2"]
+ Pad[14897 3934 14897 4328 7087 1200 7687 "" "11" "square,edge2"]
+ ElementLine [-18567 9840 18441 9840 600]
+ ElementLine [-15024 9840 -15024 8462 600]
+ ElementLine [-15024 -3 -15024 -2168 600]
+ ElementLine [15094 9840 15094 8462 600]
+ ElementLine [15094 -3 15094 -2168 600]
+ ElementLine [-7741 -7877 -6559 -7877 600]
+ ElementLine [6236 -7877 7614 -7877 600]
+
+ )
--- /dev/null
+v 20070818 1
+T 100 100 0 1 0 0 0 0 1
+gedasymbols::url=http://www.gedasymbols.org/user/sean_depagnier/symbols/usbmini.sym
+T 700 1600 8 10 1 1 0 0 1
+refdes=CONN?
+T 100 1600 9 10 1 1 0 0 1
+device=USB
+T 400 12650 8 10 0 0 0 0 1
+footprint=usbminib
+B 100 0 800 1500 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+P 1300 400 900 400 1 0 0
+{
+T 1100 490 5 10 1 1 0 0 1
+pinnumber=4
+T 600 380 5 10 1 1 0 0 1
+pinlabel=ID
+}
+P 1300 700 900 700 1 0 0
+{
+T 1100 730 5 10 1 1 0 0 1
+pinnumber=3
+T 600 720 5 10 1 1 0 0 1
+pinlabel=D+
+}
+P 1300 1000 900 1000 1 0 0
+{
+T 1100 1070 5 10 1 1 0 0 1
+pinnumber=2
+T 600 1060 5 10 1 1 0 0 1
+pinlabel=D-
+}
+P 1300 1300 900 1300 1 0 0
+{
+T 1100 1310 5 10 1 1 0 0 1
+pinnumber=1
+T 400 1300 5 10 1 1 0 0 1
+pinlabel=VCC
+}
+T 400 12450 8 10 0 0 0 0 1
+T 400 13650 8 10 0 0 0 0 1
+T 400 13850 8 10 0 0 0 0 1
+numslots=0
+T 400 14050 8 10 0 0 0 0 1
+author=Sean D'Epagnier
+P 1300 100 900 100 1 0 0
+{
+T 1100 190 5 10 1 1 0 0 1
+pinnumber=5
+T 400 80 5 10 1 1 0 0 1
+pinlabel=GND
+}
--- /dev/null
+
+Element["" "" "" "" 58000 53000 0 0 0 100 ""]
+(
+ Pad[-7555 -17555 -7555 -14799 3150 1200 3750 "1" "1" "square"]
+ Pad[-3224 -15980 -3224 -13224 3150 1200 3750 "2" "2" "square"]
+ Pad[1106 -17555 1106 -14799 3150 1200 3750 "3" "3" "square"]
+ Pad[5437 -18343 5437 -15587 3150 1200 3750 "4" "4" "square"]
+ Pad[9768 -17555 9768 -14799 3150 1200 3750 "5" "5" "square"]
+ Pad[14098 -18343 14098 -15587 3150 1200 3750 "6" "6" "square"]
+ Pad[18429 -17555 18429 -14799 3150 1200 3750 "7" "7" "square"]
+ Pad[22760 -17555 22760 -14799 3150 1200 3750 "8" "8" "square"]
+ Pad[25909 -28185 25909 -26217 5512 1200 6112 "9" "9" "square"]
+ Pad[18035 24571 19610 24571 5512 1200 6112 "10" "10" "square,edge2"]
+ Pad[-4406 24571 -2831 24571 5512 1200 6112 "10" "10" "square"]
+ Pad[-26453 -32516 -26453 -30547 5512 1200 6112 "9" "9" "square"]
+ ElementLine [-19000 -31500 -11000 -31500 600]
+ ElementLine [-11000 -31500 -11000 -26500 600]
+ ElementLine [-11000 -26500 19500 -26500 600]
+ ElementLine [19500 -26500 22000 -29000 600]
+ ElementLine [-19000 -31500 -19000 -34000 600]
+ ElementLine [-19000 -34000 -22500 -34000 600]
+ ElementLine [-28000 -27000 -28000 26000 600]
+ ElementLine [-28000 26000 -9000 26000 600]
+ ElementLine [1000 26000 14000 26000 600]
+ ElementLine [23500 26000 27500 26000 600]
+ ElementLine [27500 26000 27500 -22000 600]
+
+ )
--- /dev/null
+v 20060113 1
+P 100 4100 400 4100 1 0 0
+{
+T 300 4150 5 8 1 1 0 6 1
+pinnumber=1
+T 300 4050 5 8 0 1 0 8 1
+pinseq=1
+T 450 4100 9 8 1 1 0 0 1
+pinlabel=DAT2
+T 450 4100 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 3700 400 3700 1 0 0
+{
+T 300 3750 5 8 1 1 0 6 1
+pinnumber=2
+T 300 3650 5 8 0 1 0 8 1
+pinseq=2
+T 450 3700 9 8 1 1 0 0 1
+pinlabel=DAT3
+T 450 3700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 3300 400 3300 1 0 0
+{
+T 300 3350 5 8 1 1 0 6 1
+pinnumber=3
+T 300 3250 5 8 0 1 0 8 1
+pinseq=3
+T 450 3300 9 8 1 1 0 0 1
+pinlabel=CMD
+T 450 3300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 2900 400 2900 1 0 0
+{
+T 300 2950 5 8 1 1 0 6 1
+pinnumber=4
+T 300 2850 5 8 0 1 0 8 1
+pinseq=4
+T 450 2900 9 8 1 1 0 0 1
+pinlabel=Vcc
+T 450 2900 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 2500 400 2500 1 0 0
+{
+T 300 2550 5 8 1 1 0 6 1
+pinnumber=5
+T 300 2450 5 8 0 1 0 8 1
+pinseq=5
+T 450 2500 9 8 1 1 0 0 1
+pinlabel=CLK
+T 450 2500 5 8 0 1 0 2 1
+pintype=clk
+}
+P 100 2100 400 2100 1 0 0
+{
+T 300 2150 5 8 1 1 0 6 1
+pinnumber=6
+T 300 2050 5 8 0 1 0 8 1
+pinseq=6
+T 450 2100 9 8 1 1 0 0 1
+pinlabel=GND
+T 450 2100 5 8 0 1 0 2 1
+pintype=pwr
+}
+P 100 1700 400 1700 1 0 0
+{
+T 300 1750 5 8 1 1 0 6 1
+pinnumber=7
+T 300 1650 5 8 0 1 0 8 1
+pinseq=7
+T 450 1700 9 8 1 1 0 0 1
+pinlabel=DAT0
+T 450 1700 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 1300 400 1300 1 0 0
+{
+T 300 1350 5 8 1 1 0 6 1
+pinnumber=8
+T 300 1250 5 8 0 1 0 8 1
+pinseq=8
+T 450 1300 9 8 1 1 0 0 1
+pinlabel=DAT1
+T 450 1300 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 900 400 900 1 0 0
+{
+T 300 950 5 8 1 1 0 6 1
+pinnumber=9
+T 300 850 5 8 0 1 0 8 1
+pinseq=9
+T 450 900 9 8 1 1 0 0 1
+pinlabel=GND
+T 450 900 5 8 0 1 0 2 1
+pintype=io
+}
+P 100 500 400 500 1 0 0
+{
+T 300 550 5 8 1 1 0 6 1
+pinnumber=10
+T 300 450 5 8 0 1 0 8 1
+pinseq=10
+T 450 500 9 8 1 1 0 0 1
+pinlabel=\_CD\_
+T 450 500 5 8 0 1 0 2 1
+pintype=pwr
+}
+B 400 100 1000 4400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 1400 4600 8 10 1 1 0 6 1
+refdes=J?
+T 400 4600 9 10 1 0 0 0 1
+wurth-microsd
+T 400 4800 5 10 0 0 0 0 1
+device=wurth-693071010811
+T 400 5000 5 10 0 0 0 0 1
+footprint=wurth-microsd
+T 400 5200 5 10 0 0 0 0 1
+author=Michael McMaster <michael@codesrc.com>
+T 400 5400 5 10 0 0 0 0 1
+documentation=http://www.digikey.com/product-detail/en/693071010811/732-3819-1-ND/3124603
+T 400 5600 5 10 0 0 0 0 1
+description=Wurth MicroSD socket 693071010811
+T 400 5800 5 10 0 0 0 0 1
+numslots=0
+T 400 6000 5 10 0 0 0 0 1
+dist-license=gpl3+
+T 400 6200 5 10 0 0 0 0 1
+use-license=gpl3+
--- /dev/null
+# This is the template file for creating symbols with tragesym
+# every line starting with '#' is a comment line.
+
+[options]
+# wordswap swaps labels if the pin is on the right side an looks like this:
+# "PB1 (CLK)". That's useful for micro controller port labels
+# rotate_labels rotates the pintext of top and bottom pins
+# this is useful for large symbols like FPGAs with more than 100 pins
+# sort_labels will sort the pins by it's labels
+# useful for address ports, busses, ...
+wordswap=yes
+rotate_labels=yes
+sort_labels=no
+generate_pinseq=yes
+sym_width=1000
+pinwidthvertical=400
+pinwidthhorizontal=400
+
+[geda_attr]
+# name will be printed in the top of the symbol
+# name is only some graphical text, not an attribute
+# version specifies a gschem version.
+# if you have a device with slots, you'll have to use slot= and slotdef=
+# use comment= if there are special information you want to add
+version=20060113 1
+name=wurth-microsd
+device=wurth-693071010811
+refdes=J?
+footprint=wurth-microsd
+description=Wurth MicroSD socket 693071010811
+documentation=http://www.digikey.com/product-detail/en/693071010811/732-3819-1-ND/3124603
+author=Michael McMaster <michael@codesrc.com>
+dist-license=gpl3+
+use-license=gpl3+
+numslots=0
+#slot=1
+#slotdef=1:
+#slotdef=2:
+#slotdef=3:
+#slotdef=4:
+#comment=
+#comment=
+#comment=
+
+[pins]
+# tabseparated list of pin descriptions
+# ----------------------------------------
+# pinnr is the physical number of the pin
+# seq is the pinseq= attribute, leave it blank if it doesn't matter
+# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
+# style can be (line,dot,clk,dotclk,spacer,none). none if only want to add a net
+# posit. can be (l,r,t,b) or empty for nets.
+# net specifies the name of the net. Vcc or GND for example.
+# label represents the pinlabel.
+# negation lines can be added with "\_" example: \_enable\_
+# if you want to write a "\" use "\\" as escape sequence
+#-----------------------------------------------------
+#pinnr seq type style posit. net label
+#-----------------------------------------------------
+1 io line l DAT2
+2 io line l DAT3
+3 io line l CMD
+4 pwr line l Vcc
+5 clk line l CLK
+6 pwr line l GND GND
+7 io line l DAT0
+8 io line l DAT1
+9 io line l GND GND
+10 pwr line l \_CD\_
+
--- /dev/null
+SCSI2SD, The SCSI Hard Drive Emulator for retro computing.
+
+
+Traditional hard drives last X years. Maybe, if you're luckly, you'll get X years of
+service from a particular drive. The lubricants wear out, the spindles rust.
+SCSI2SD is a modern replacement for failed drives. It allows the use ofvintage
+computer hardware long after their mechanical drives fail. The use of SD memory cards
+solves the problem of transferring data between the retro computer and a
+modern PC (who still has access to a working floppy drive ?)
+
+Features:
+ Terminator, termpwr, firmware upgradable (via the SD card)
+ Selectable SCSI ID (via jumpers)
+ Emulates a non-removable hard drive (does not present as a removable memory card reader) for maximum compatibility.
+ Unit attention configurability.
+
+Technical Specifications:
+SCSI Interface: SCSI-2 Narrow 8-bit 50-pin connector.
+SD Card Support:
+ (state max size)
+ Currently SD standard (1GB), no SDHC/SDXC support.
+Power:
+Dimensions:
+
+Performance:
+Sequential read/write: 250kb/sec, 50kb/sec. Add some results of some SCSI hard drives
+for comparison. 160Mb, 250Mb, 1Gb.
+
+Compatibility:
+Tested with Linux, Apple Macintosh System 7.5 on LC-II, LC-III, and LC-475 hardware.
+Love to hear your success stories on other platforms.
+
+
--- /dev/null
+codegentemp
+CortexM3
+*.Micha_000
+*.rpt
+*.pdf
+*.html
+
--- /dev/null
+;********************************************************************************\r
+;* File Name: Cm3RealView.scat\r
+;* Version 3.40\r
+;*\r
+;* Description:\r
+;* This Linker Descriptor file describes the memory layout of the PSoC5\r
+;* device. The memory layout of the final binary and hex images as well as\r
+;* the placement in PSoC5 memory is described.\r
+;*\r
+;*\r
+;* Note:\r
+;*\r
+;* romvectors: Cypress default Interrupt sevice routine vector table.\r
+;*\r
+;* This is the ISR vector table at bootup. Used only for the reset vector.\r
+;*\r
+;*\r
+;* ramvectors: Cypress ram interrupt service routine vector table.\r
+;*\r
+;* This is the ISR vector table used by the application.\r
+;*\r
+;*\r
+;********************************************************************************\r
+;* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+;* You may use this file only in accordance with the license, terms, conditions,\r
+;* disclaimers, and limitations in the end user license agreement accompanying\r
+;* the software package with which this file was provided.\r
+;********************************************************************************/\r
+\r
+LOAD_ROM 0 (262144 - 0)\r
+{\r
+ VECTORS +0\r
+ {\r
+ * (.romvectors)\r
+ }\r
+\r
+ CODE +0\r
+ {\r
+ * (+RO)\r
+ }\r
+\r
+ ISRVECTORS (0x20000000 - (65536 / 2)) UNINIT\r
+ {\r
+ * (.ramvectors)\r
+ }\r
+\r
+ NOINIT_DATA +0 UNINIT\r
+ {\r
+ * (.noinit)\r
+ }\r
+\r
+ DATA +0\r
+ {\r
+ * (+RW, +ZI)\r
+ }\r
+\r
+ ARM_LIB_HEAP (0x20000000 + (65536 / 2) - 0x1000 - 0x4000) EMPTY 0x1000\r
+ {\r
+ }\r
+\r
+ ARM_LIB_STACK (0x20000000 + (65536 / 2)) EMPTY -0x4000\r
+ {\r
+ }\r
+}\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: Cm3Start.c\r
+* Version 3.40\r
+*\r
+* Description:\r
+* Startup code for the ARM CM3.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "cydevice_trm.h"\r
+#include "cytypes.h"\r
+#include "cyfitter_cfg.h"\r
+#include "CyLib.h"\r
+#include "CyDmac.h"\r
+#include "cyfitter.h"\r
+\r
+#define NUM_INTERRUPTS 32u\r
+#define NUM_VECTORS (CYINT_IRQ_BASE+NUM_INTERRUPTS)\r
+#define NUM_ROM_VECTORS 4u\r
+#define NVIC_APINT ((reg32 *) CYREG_NVIC_APPLN_INTR)\r
+#define NVIC_CFG_CTRL ((reg32 *) CYREG_NVIC_CFG_CONTROL)\r
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400u /* Priority group 3.5 split */\r
+#define NVIC_APINT_VECTKEY 0x05FA0000u /* This key is required in order to write the NVIC_APINT register */\r
+#define NVIC_CFG_STACKALIGN 0x00000200u /* This specifies that the exception stack must be 8 byte aligned */\r
+\r
+/* Extern functions */\r
+extern void CyBtldr_CheckLaunch(void);\r
+\r
+/* Function prototypes */\r
+void initialize_psoc(void);\r
+CY_ISR(IntDefaultHandler);\r
+void Reset(void);\r
+CY_ISR(IntDefaultHandler);\r
+\r
+#if defined(__ARMCC_VERSION)\r
+ #define INITIAL_STACK_POINTER (cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit\r
+#elif defined (__GNUC__)\r
+ #define INITIAL_STACK_POINTER __cs3_stack\r
+#endif /* (__ARMCC_VERSION) */\r
+\r
+/* Global variables */\r
+CY_NOINIT static uint32 cySysNoInitDataValid;\r
+\r
+\r
+/*******************************************************************************\r
+* Default Ram Interrupt Vector table storage area. Must be 256-byte aligned.\r
+*******************************************************************************/\r
+\r
+__attribute__ ((section(".ramvectors")))\r
+#if defined(__ARMCC_VERSION)\r
+__align(256)\r
+#elif defined (__GNUC__)\r
+__attribute__ ((aligned(256)))\r
+#endif\r
+cyisraddress CyRamVectors[NUM_VECTORS];\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: IntDefaultHandler\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* This function is called for all interrupts, other than reset, that get\r
+* called before the system is setup.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Theory:\r
+* Any value other than zero is acceptable.\r
+*\r
+*******************************************************************************/\r
+CY_ISR(IntDefaultHandler)\r
+{\r
+\r
+ while(1)\r
+ {\r
+ /***********************************************************************\r
+ * We should never get here. If we do, a serious problem occured, so go\r
+ * into an infinite loop.\r
+ ***********************************************************************/\r
+ }\r
+}\r
+\r
+\r
+#if defined(__ARMCC_VERSION)\r
+\r
+/* Local function for the device reset. */\r
+extern void Reset(void);\r
+\r
+/* Application entry point. */\r
+extern void $Super$$main(void);\r
+\r
+/* Linker-generated Stack Base addresses, Two Region and One Region */\r
+extern uint32 Image$$ARM_LIB_STACK$$ZI$$Limit;\r
+\r
+/* RealView C Library initialization. */\r
+extern int __main(void);\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: Reset\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* This function handles the reset interrupt for the RVDS/MDK toolchains.\r
+* This is the first bit of code that is executed at startup.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+__asm void Reset(void)\r
+{\r
+ PRESERVE8\r
+ EXTERN __main\r
+ EXTERN CyResetStatus\r
+\r
+ #if(CYDEV_BOOTLOADER_ENABLE)\r
+ EXTERN CyBtldr_CheckLaunch\r
+ #endif /* (CYDEV_BOOTLOADER_ENABLE) */\r
+\r
+\r
+ #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)\r
+ #if(CYDEV_DEBUGGING_ENABLE)\r
+ ldr r3, =0x400046e8 /* CYDEV_DEBUG_ENABLE_REGISTER */\r
+ ldrb r4, [r3, #0]\r
+ orr r4, r4, #01\r
+ strb r4, [r3, #0]\r
+debugEnabled\r
+ #endif /* (CYDEV_DEBUGGING_ENABLE) */\r
+\r
+ ldr r3, =0x400046fa /* CYREG_RESET_SR0 */\r
+ ldrb r2, [r3, #0]\r
+\r
+ #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */\r
+\r
+ ldr r3, =0x400076BC /* CYREG_PHUB_CFGMEM23_CFG1 */\r
+ strb r2, [r3, #0]\r
+\r
+ #if(CYDEV_BOOTLOADER_ENABLE)\r
+ bl CyBtldr_CheckLaunch\r
+ #endif /* (CYDEV_BOOTLOADER_ENABLE) */\r
+\r
+ /* Let RealView setup the libraries. */\r
+ bl __main\r
+\r
+ ALIGN\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: $Sub$$main\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* This function is called imediatly before the users main\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void $Sub$$main(void)\r
+{\r
+ initialize_psoc();\r
+\r
+ /* Call original main */\r
+ $Super$$main();\r
+\r
+ /* If main returns it is undefined what we should do. */\r
+ while (1);\r
+}\r
+\r
+#elif defined(__GNUC__)\r
+\r
+extern void __cs3_stack(void);\r
+extern void __cs3_start_c(void);\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: Reset\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* This function handles the reset interrupt for the GCC toolchain. This is the\r
+* first bit of code that is executed at startup.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+__attribute__ ((naked))\r
+void Reset(void)\r
+{\r
+ __asm volatile(\r
+#if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)\r
+\r
+ #if(CYDEV_DEBUGGING_ENABLE)\r
+ " ldr r3, =%0\n"\r
+ " ldrb r4, [r3, #0]\n"\r
+ " orr r4, r4, #01\n"\r
+ " strb r4, [r3, #0]\n"\r
+ "debugEnabled:\n"\r
+ #endif /* (CYDEV_DEBUGGING_ENABLE) */\r
+\r
+ " ldr r3, =%1\n"\r
+ " ldrb r2, [r3, #0]\n"\r
+ " uxtb r2, r2\n"\r
+#endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */\r
+\r
+ " ldr r3, =%2\n"\r
+ " strb r2, [r3, #0]\n"\r
+\r
+#if(CYDEV_BOOTLOADER_ENABLE)\r
+ " bl CyBtldr_CheckLaunch\n"\r
+#endif /* (CYDEV_BOOTLOADER_ENABLE) */\r
+\r
+ /* Switch to C initialization phase */\r
+ " bl __cs3_start_c\n" : : "i" (CYDEV_DEBUG_ENABLE_REGISTER), "i" (CYREG_RESET_SR0), "i" (CYREG_PHUB_CFGMEM23_CFG1));\r
+}\r
+\r
+#endif /* __GNUC__ */\r
+\r
+\r
+/*******************************************************************************\r
+*\r
+* Default Rom Interrupt Vector table.\r
+*\r
+*******************************************************************************/\r
+#if defined(__ARMCC_VERSION)\r
+ #pragma diag_suppress 1296\r
+#endif\r
+__attribute__ ((section(".romvectors")))\r
+const cyisraddress RomVectors[NUM_ROM_VECTORS] =\r
+{\r
+ #if defined(__ARMCC_VERSION)\r
+ INITIAL_STACK_POINTER, /* The initial stack pointer 0 */\r
+ #elif defined (__GNUC__)\r
+ &INITIAL_STACK_POINTER, /* The initial stack pointer 0 */\r
+ #endif /* (__ARMCC_VERSION) */\r
+ (cyisraddress)&Reset, /* The reset handler 1 */\r
+ &IntDefaultHandler, /* The NMI handler 2 */\r
+ &IntDefaultHandler, /* The hard fault handler 3 */\r
+};\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: initialize_psoc\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* This function used to initialize the PSoC chip before calling main.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+#if (defined(__GNUC__) && !defined(__ARMCC_VERSION))\r
+__attribute__ ((constructor(101)))\r
+#endif\r
+\r
+void initialize_psoc(void)\r
+{\r
+ uint32 i;\r
+\r
+ /* Set Priority group 5. */\r
+\r
+ /* Writes to NVIC_APINT register require the VECTKEY in the upper half */\r
+ *NVIC_APINT = NVIC_APINT_VECTKEY | NVIC_APINT_PRIGROUP_3_5;\r
+ *NVIC_CFG_CTRL |= NVIC_CFG_STACKALIGN;\r
+\r
+ /* Set Ram interrupt vectors to default functions. */\r
+ for(i = 0u; i < NUM_VECTORS; i++)\r
+ {\r
+ CyRamVectors[i] = (i < NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler;\r
+ }\r
+\r
+ /* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */\r
+ CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1);\r
+\r
+ /* Point NVIC at the RAM vector table. */\r
+ *CYINT_VECT_TABLE = CyRamVectors;\r
+\r
+ /* Initialize the configuration registers. */\r
+ cyfitter_cfg();\r
+\r
+ #if(0u != DMA_CHANNELS_USED__MASK0)\r
+\r
+ /* Setup DMA - only necessary if the design contains a DMA component. */\r
+ CyDmacConfigure();\r
+\r
+ #endif /* (0u != DMA_CHANNELS_USED__MASK0) */\r
+ \r
+ /* Actually, no need to clean this variable, just to make compiler happy. */\r
+ cySysNoInitDataValid = 0u;\r
+}\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: CyBootAsmGnu.s\r
+* Version 3.40\r
+*\r
+* Description:\r
+* Assembly routines for GNU as.\r
+*\r
+********************************************************************************\r
+* Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+.syntax unified\r
+.text\r
+.thumb\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDelayCycles\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Delays for the specified number of cycles.\r
+*\r
+* Parameters:\r
+* uint32 cycles: number of cycles to delay.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+/* void CyDelayCycles(uint32 cycles) */\r
+.align 3 /* Align to 8 byte boundary (2^n) */\r
+.global CyDelayCycles\r
+.func CyDelayCycles, CyDelayCycles\r
+.type CyDelayCycles, %function\r
+.thumb_func\r
+CyDelayCycles: /* cycles bytes */\r
+ ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */\r
+ LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */\r
+ BEQ CyDelayCycles_done /* 2 2 Skip if 0 */\r
+ NOP /* 1 2 Loop alignment padding */\r
+CyDelayCycles_loop:\r
+ SUBS r0, r0, #1 /* 1 2 */\r
+ MOV r0, r0 /* 1 2 Pad loop to power of two cycles */\r
+ BNE CyDelayCycles_loop /* 2 2 */\r
+CyDelayCycles_done:\r
+ BX lr /* 3 2 */\r
+.endfunc\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyEnterCriticalSection\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* CyEnterCriticalSection disables interrupts and returns a value indicating\r
+* whether interrupts were previously enabled (the actual value depends on\r
+* whether the device is PSoC 3 or PSoC 5).\r
+*\r
+* Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit\r
+* with interrupts still enabled. The test and set of the interrupt bits is not\r
+* atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid\r
+* corrupting processor state, it must be the policy that all interrupt routines\r
+* restore the interrupt enable bits as they were found on entry.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* uint8\r
+* Returns 0 if interrupts were previously enabled or 1 if interrupts\r
+* were previously disabled.\r
+*\r
+*******************************************************************************/\r
+/* uint8 CyEnterCriticalSection(void) */\r
+.global CyEnterCriticalSection\r
+.func CyEnterCriticalSection, CyEnterCriticalSection\r
+.type CyEnterCriticalSection, %function\r
+.thumb_func\r
+CyEnterCriticalSection:\r
+ MRS r0, PRIMASK /* Save and return interrupt state */\r
+ CPSID I /* Disable interrupts */\r
+ BX lr\r
+.endfunc\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyExitCriticalSection\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* CyExitCriticalSection re-enables interrupts if they were enabled before\r
+* CyEnterCriticalSection was called. The argument should be the value returned\r
+* from CyEnterCriticalSection.\r
+*\r
+* Parameters:\r
+* uint8 savedIntrStatus:\r
+* Saved interrupt status returned by the CyEnterCriticalSection function.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+/* void CyExitCriticalSection(uint8 savedIntrStatus) */\r
+.global CyExitCriticalSection\r
+.func CyExitCriticalSection, CyExitCriticalSection\r
+.type CyExitCriticalSection, %function\r
+.thumb_func\r
+CyExitCriticalSection:\r
+ MSR PRIMASK, r0 /* Restore interrupt state */\r
+ BX lr\r
+.endfunc\r
+\r
+.end\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+;-------------------------------------------------------------------------------\r
+; FILENAME: CyBootAsmRv.s\r
+; Version 3.40\r
+;\r
+; DESCRIPTION:\r
+; Assembly routines for RealView.\r
+;\r
+;-------------------------------------------------------------------------------\r
+; Copyright 2010-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; You may use this file only in accordance with the license, terms, conditions,\r
+; disclaimers, and limitations in the end user license agreement accompanying\r
+; the software package with which this file was provided.\r
+;-------------------------------------------------------------------------------\r
+\r
+ AREA |.text|,CODE,ALIGN=3\r
+ THUMB\r
+ EXTERN Reset\r
+\r
+;-------------------------------------------------------------------------------\r
+; Function Name: CyDelayCycles\r
+;-------------------------------------------------------------------------------\r
+;\r
+; Summary:\r
+; Delays for the specified number of cycles.\r
+;\r
+; Parameters:\r
+; uint32 cycles: number of cycles to delay.\r
+;\r
+; Return:\r
+; None\r
+;\r
+;-------------------------------------------------------------------------------\r
+; void CyDelayCycles(uint32 cycles)\r
+ ALIGN 8\r
+CyDelayCycles FUNCTION\r
+ EXPORT CyDelayCycles\r
+ ; cycles bytes\r
+ ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4\r
+ LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags\r
+ BEQ CyDelayCycles_done ; 2 2 Skip if 0\r
+ NOP ; 1 2 Loop alignment padding\r
+CyDelayCycles_loop\r
+ SUBS r0, r0, #1 ; 1 2\r
+ MOV r0, r0 ; 1 2 Pad loop to power of two cycles\r
+ BNE CyDelayCycles_loop ; 2 2\r
+CyDelayCycles_done\r
+ BX lr ; 3 2\r
+ ENDFUNC\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Function Name: CyEnterCriticalSection\r
+;-------------------------------------------------------------------------------\r
+;\r
+; Summary:\r
+; CyEnterCriticalSection disables interrupts and returns a value indicating\r
+; whether interrupts were previously enabled (the actual value depends on\r
+; whether the device is PSoC 3 or PSoC 5).\r
+;\r
+; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit\r
+; with interrupts still enabled. The test and set of the interrupt bits is not\r
+; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid\r
+; corrupting processor state, it must be the policy that all interrupt routines\r
+; restore the interrupt enable bits as they were found on entry.\r
+;\r
+; Parameters:\r
+; None\r
+;\r
+; Return:\r
+; uint8\r
+; Returns 0 if interrupts were previously enabled or 1 if interrupts\r
+; were previously disabled.\r
+;\r
+;-------------------------------------------------------------------------------\r
+; uint8 CyEnterCriticalSection(void)\r
+CyEnterCriticalSection FUNCTION\r
+ EXPORT CyEnterCriticalSection\r
+ MRS r0, PRIMASK ; Save and return interrupt state\r
+ CPSID I ; Disable interrupts\r
+ BX lr\r
+ ENDFUNC\r
+\r
+\r
+;-------------------------------------------------------------------------------\r
+; Function Name: CyExitCriticalSection\r
+;-------------------------------------------------------------------------------\r
+;\r
+; Summary:\r
+; CyExitCriticalSection re-enables interrupts if they were enabled before\r
+; CyEnterCriticalSection was called. The argument should be the value returned\r
+; from CyEnterCriticalSection.\r
+;\r
+; Parameters:\r
+; uint8 savedIntrStatus:\r
+; Saved interrupt status returned by the CyEnterCriticalSection function.\r
+;\r
+; Return:\r
+; None\r
+;\r
+;-------------------------------------------------------------------------------\r
+; void CyExitCriticalSection(uint8 savedIntrStatus)\r
+CyExitCriticalSection FUNCTION\r
+ EXPORT CyExitCriticalSection\r
+ MSR PRIMASK, r0 ; Restore interrupt state\r
+ BX lr\r
+ ENDFUNC\r
+\r
+ END\r
+\r
+; [] END OF FILE\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: CyDmac.c\r
+* Version 3.40\r
+*\r
+* Description:\r
+* Provides an API for the DMAC component. The API includes functions for the\r
+* DMA controller, DMA channels and Transfer Descriptors.\r
+*\r
+* This API is the library version not the auto generated code that gets\r
+* generated when the user places a DMA component on the schematic.\r
+*\r
+* The auto generated code would use the APi's in this module.\r
+*\r
+* Note:\r
+* This code is endian agnostic.\r
+*\r
+* The Transfer Descriptor memory can be used as regular memory if the TD's are\r
+* not being used.\r
+*\r
+* This code uses the first byte of each TD to manage the free list of TD's.\r
+* The user can over write this once the TD is allocated.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "CyDmac.h"\r
+\r
+static uint8 CyDmaTdCurrentNumber; /* Current Number of free elements in the list */\r
+static uint8 CyDmaTdFreeIndex; /* Index of the first available TD */\r
+static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0; /* Bit map of DMA channel ownership */\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmacConfigure\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Creates a linked list of all the TDs to be allocated. This function is called\r
+* by the startup code; you do not normally need to call it. You could call this\r
+* function if all of the DMA channels are inactive.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyDmacConfigure(void) \r
+{\r
+ uint8 dmaIndex;\r
+\r
+ /* Set TD list variables. */\r
+ CyDmaTdFreeIndex = ((uint8) (CY_DMA_NUMBEROF_TDS - 1u));\r
+ CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS;\r
+\r
+ /* Make TD free list. */\r
+ for(dmaIndex = ((uint8)(CY_DMA_NUMBEROF_TDS - 1u)); dmaIndex != 0u; dmaIndex--)\r
+ {\r
+ CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = ((uint8)(dmaIndex - 1u));\r
+ }\r
+\r
+ /* Make the last one point to zero. */\r
+ CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = 0u;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmacError\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Returns errors of the last failed DMA transaction.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* Errors of the last failed DMA transaction.\r
+*\r
+* DMAC_PERIPH_ERR:\r
+* Set to 1 when a peripheral responds to a bus transaction with an error\r
+* response.\r
+*\r
+* DMAC_UNPOP_ACC:\r
+* Set to 1 when an access is attempted to an invalid address.\r
+*\r
+* DMAC_BUS_TIMEOUT:\r
+* Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values\r
+* are determined by the BUS_TIMEOUT field in the PHUBCFG register.\r
+*\r
+* Theory:\r
+* Once an error occurs the error bits are sticky and are only cleared by a\r
+* write 1 to the error register.\r
+*\r
+*******************************************************************************/\r
+uint8 CyDmacError(void) \r
+{\r
+ return((uint8)(((uint32) 0x0Fu) & *CY_DMA_ERR_PTR));\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmacClearError\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Clears the error bits in the error register of the DMAC.\r
+*\r
+* Parameters:\r
+* error:\r
+* Clears the error bits in the DMAC error register.\r
+*\r
+* DMAC_PERIPH_ERR:\r
+* Set to 1 when a peripheral responds to a bus transaction with an error\r
+* response.\r
+*\r
+* DMAC_UNPOP_ACC:\r
+* Set to 1 when an access is attempted to an invalid address.\r
+*\r
+* DMAC_BUS_TIMEOUT:\r
+* Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values\r
+* are determined by the BUS_TIMEOUT field in the PHUBCFG register.\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Theory:\r
+* Once an error occurs the error bits are sticky and are only cleared by a\r
+* write 1 to the error register.\r
+*\r
+*******************************************************************************/\r
+void CyDmacClearError(uint8 error) \r
+{\r
+ *CY_DMA_ERR_PTR = (((uint32)0x0Fu) & ((uint32)error));\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmacErrorAddress\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* When an DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC and DMAC_PERIPH_ERR occurs the\r
+* address of the error is written to the error address register and can be read\r
+* with this function.\r
+*\r
+* If there are multiple errors, only the address of the first is saved.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* The address that caused the error.\r
+*\r
+*******************************************************************************/\r
+uint32 CyDmacErrorAddress(void) \r
+{\r
+ return(CY_GET_REG32(CY_DMA_ERR_ADR_PTR));\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaChAlloc\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Allocates a channel from the DMAC to be used in all functions that require a\r
+* channel handle.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* The allocated channel number. Zero is a valid channel number.\r
+* DMA_INVALID_CHANNEL is returned if there are no channels available.\r
+*\r
+*******************************************************************************/\r
+uint8 CyDmaChAlloc(void) \r
+{\r
+ uint8 interruptState;\r
+ uint8 dmaIndex;\r
+ uint32 channel = 1u;\r
+\r
+\r
+ /* Enter critical section! */\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ /* Look for a free channel. */\r
+ for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++)\r
+ {\r
+ if(0uL == (CyDmaChannels & channel))\r
+ {\r
+ /* Mark the channel as used. */\r
+ CyDmaChannels |= channel;\r
+ break;\r
+ }\r
+\r
+ channel <<= 1u;\r
+ }\r
+\r
+ if(dmaIndex >= CY_DMA_NUMBEROF_CHANNELS)\r
+ {\r
+ dmaIndex = CY_DMA_INVALID_CHANNEL;\r
+ }\r
+\r
+ /* Exit critical section! */\r
+ CyExitCriticalSection(interruptState);\r
+\r
+ return(dmaIndex);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaChFree\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Frees a channel allocated by DmaChAlloc().\r
+*\r
+* Parameters:\r
+* uint8 chHandle:\r
+* The handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+*\r
+* Return:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_BAD_PARAM if chHandle is invalid.\r
+*\r
+*******************************************************************************/\r
+cystatus CyDmaChFree(uint8 chHandle) \r
+{\r
+ cystatus status = CYRET_BAD_PARAM;\r
+ uint8 interruptState;\r
+\r
+ if(chHandle < CY_DMA_NUMBEROF_CHANNELS)\r
+ {\r
+ /* Enter critical section */\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ /* Clear the bit mask that keeps track of ownership. */\r
+ CyDmaChannels &= ~(((uint32) 1u) << chHandle);\r
+\r
+ /* Exit critical section */\r
+ CyExitCriticalSection(interruptState);\r
+ status = CYRET_SUCCESS;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaChEnable\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enables the DMA channel. A software or hardware request still must happen\r
+* before the channel is executed.\r
+*\r
+* Parameters:\r
+* uint8 chHandle:\r
+* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+*\r
+* uint8 preserveTds:\r
+* Preserves the original TD state when the TD has completed. This parameter\r
+* applies to all TDs in the channel.\r
+*\r
+* 0 - When a TD is completed, the DMAC leaves the TD configuration values in\r
+* their current state, and does not restore them to their original state.\r
+*\r
+* 1 - When a TD is completed, the DMAC restores the original configuration\r
+* values of the TD.\r
+*\r
+* When preserveTds is set, the TD slot that equals the channel number becomes\r
+* RESERVED and that becomes where the working registers exist. So, for example,\r
+* if you are using CH06 and preserveTds is set, you are not allowed to use TD\r
+* slot 6. That is reclaimed by the DMA engine for its private use.\r
+*\r
+* Note Do not chain back to a completed TD if the preserveTds for the channel\r
+* is set to 0. When a TD has completed preserveTds for the channel set to 0,\r
+* the transfer count will be at 0. If a TD with a transfer count of 0 is\r
+* started, the TD will transfer an indefinite amount of data.\r
+*\r
+* Take extra precautions when using the hardware request (DRQ) option when the\r
+* preserveTds is set to 0, as you might be requesting the wrong data.\r
+*\r
+* Return:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_BAD_PARAM if chHandle is invalid.\r
+*\r
+*******************************************************************************/\r
+cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) \r
+{\r
+ cystatus status = CYRET_BAD_PARAM;\r
+\r
+ if(chHandle < CY_DMA_NUMBEROF_CHANNELS)\r
+ {\r
+ CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] =\r
+ (CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~0x20u))) | ((0u != preserveTds) ? 0x21u : 0x01u);\r
+ status = CYRET_SUCCESS;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaChDisable\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disables the DMA channel. Once this function is called, CyDmaChStatus() may\r
+* be called to determine when the channel is disabled and which TDs were being\r
+* executed.\r
+*\r
+* If it is currently executing it will allow the current burst to finish\r
+* naturally.\r
+*\r
+* Parameters:\r
+* uint8 chHandle:\r
+* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+*\r
+* Return:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_BAD_PARAM if chHandle is invalid.\r
+*\r
+*******************************************************************************/\r
+cystatus CyDmaChDisable(uint8 chHandle) \r
+{\r
+ cystatus status = CYRET_BAD_PARAM;\r
+\r
+ if(chHandle < CY_DMA_NUMBEROF_CHANNELS)\r
+ {\r
+ CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~0x21u));\r
+ status = CYRET_SUCCESS;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaClearPendingDrq\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Clears pending DMA data request.\r
+*\r
+* Parameters:\r
+* uint8 chHandle:\r
+* Handle to the dma channel.\r
+*\r
+* Return:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_BAD_PARAM if chHandle is invalid.\r
+*\r
+*******************************************************************************/\r
+cystatus CyDmaClearPendingDrq(uint8 chHandle) \r
+{\r
+ cystatus status = CYRET_BAD_PARAM;\r
+\r
+ if(chHandle < CY_DMA_NUMBEROF_CHANNELS)\r
+ {\r
+ CY_DMA_CH_STRUCT_PTR[chHandle].action[0] |= CY_DMA_CPU_TERM_CHAIN;\r
+ CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] |= 0x01u;\r
+ status = CYRET_SUCCESS;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaChPriority\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the priority of a DMA channel. You can use this function when you want\r
+* to change the priority at run time. If the priority remains the same for a\r
+* DMA channel, then you can configure the priority in the .cydwr file.\r
+*\r
+* Parameters:\r
+* uint8 chHandle:\r
+* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+*\r
+* uint8 priority:\r
+* Priority to set the channel to, 0 - 7.\r
+*\r
+* Return:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_BAD_PARAM if chHandle is invalid.\r
+*\r
+*******************************************************************************/\r
+cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) \r
+{\r
+ uint8 value;\r
+ cystatus status = CYRET_BAD_PARAM;\r
+\r
+ if(chHandle < CY_DMA_NUMBEROF_CHANNELS)\r
+ {\r
+ value = CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~(0x0Eu)));\r
+\r
+ CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] = value | ((uint8) ((priority & 0x7u) << 0x01u));\r
+\r
+ status = CYRET_SUCCESS;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaChSetExtendedAddress\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the high 16 bits of the source and destination addresses for the DMA\r
+* channel (valid for all TDs in the chain).\r
+*\r
+* Parameters:\r
+* uint8 chHandle:\r
+* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+*\r
+* uint16 source:\r
+* Upper 16 bit address of the DMA transfer source.\r
+*\r
+* uint16 destination:\r
+* Upper 16 bit address of the DMA transfer destination.\r
+*\r
+* Return:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_BAD_PARAM if chHandle is invalid.\r
+*\r
+*******************************************************************************/\r
+cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination) \\r
+ \r
+{\r
+ cystatus status = CYRET_BAD_PARAM;\r
+\r
+ #if(CY_PSOC5)\r
+\r
+ /* 0x1FFF8000-0x1FFFFFFF needs to use alias at 0x20008000-0x2000FFFF */\r
+ if(source == 0x1FFFu)\r
+ {\r
+ source = 0x2000u;\r
+ }\r
+\r
+ if(destination == 0x1FFFu)\r
+ {\r
+ destination = 0x2000u;\r
+ }\r
+\r
+ #endif /* (CY_PSOC5) */\r
+\r
+\r
+ if(chHandle < CY_DMA_NUMBEROF_CHANNELS)\r
+ {\r
+ /* Set source address */\r
+ reg16 *convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[0];\r
+ CY_SET_REG16(convert, source);\r
+\r
+ /* Set destination address */\r
+ CY_SET_REG16((reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[2], destination);\r
+ status = CYRET_SUCCESS;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaChSetInitialTd\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the initial TD to be executed for the channel when the CyDmaChEnable()\r
+* function is called.\r
+*\r
+* Parameters:\r
+* uint8 chHandle:\r
+* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().\r
+*\r
+* uint8 startTd:\r
+* The index of TD to set as the first TD associated with the channel. Zero is\r
+* a valid TD index.\r
+*\r
+* Return:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_BAD_PARAM if chHandle is invalid.\r
+*\r
+*******************************************************************************/\r
+cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) \r
+{\r
+ cystatus status = CYRET_BAD_PARAM;\r
+\r
+ if(chHandle < CY_DMA_NUMBEROF_CHANNELS)\r
+ {\r
+ CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1u] = startTd;\r
+ status = CYRET_SUCCESS;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaChSetRequest\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Allows the caller to terminate a chain of TDs, terminate one TD, or create a\r
+* direct request to start the DMA channel.\r
+*\r
+* Parameters:\r
+* uint8 chHandle:\r
+* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+*\r
+* uint8 request:\r
+* One of the following constants. Each of the constants is a three-bit value.\r
+*\r
+* CPU_REQ - Create a direct request to start the DMA channel\r
+* CPU_TERM_TD - Terminate one TD\r
+* CPU_TERM_CHAIN - Terminate a chain of TDs\r
+*\r
+* Return:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_BAD_PARAM if chHandle is invalid.\r
+*\r
+*******************************************************************************/\r
+cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) \r
+{\r
+ cystatus status = CYRET_BAD_PARAM;\r
+\r
+ if(chHandle < CY_DMA_NUMBEROF_CHANNELS)\r
+ {\r
+ CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] |= (request & (CPU_REQ | CPU_TERM_TD | CPU_TERM_CHAIN));\r
+ status = CYRET_SUCCESS;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaChGetRequest\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* This function allows the caller of CyDmaChSetRequest() to determine if the\r
+* request was completed.\r
+*\r
+* Parameters:\r
+* uint8 chHandle:\r
+* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+*\r
+* Return:\r
+* Returns a three-bit field, corresponding to the three bits of the request,\r
+* which describes the state of the previously posted request. If the value is\r
+* zero, the request was completed. CY_DMA_INVALID_CHANNEL if the handle is\r
+* invalid.\r
+*\r
+*******************************************************************************/\r
+cystatus CyDmaChGetRequest(uint8 chHandle) \r
+{\r
+ cystatus status = CY_DMA_INVALID_CHANNEL;\r
+\r
+ if(chHandle < CY_DMA_NUMBEROF_CHANNELS)\r
+ {\r
+ status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] & \r
+ (uint32)(CY_DMA_CPU_REQ | CY_DMA_CPU_TERM_TD | CY_DMA_CPU_TERM_CHAIN));\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaChStatus\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Determines the status of the DMA channel.\r
+*\r
+* Parameters:\r
+* uint8 chHandle:\r
+* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize().\r
+*\r
+* uint8 * currentTd:\r
+* The address to store the index of the current TD. Can be NULL if the value\r
+* is not needed.\r
+*\r
+* uint8 * state:\r
+* The address to store the state of the channel. Can be NULL if the value is\r
+* not needed.\r
+*\r
+* STATUS_TD_ACTIVE\r
+* 0: Channel is not currently being serviced by DMAC\r
+* 1: Channel is currently being serviced by DMAC\r
+*\r
+* STATUS_CHAIN_ACTIVE\r
+* 0: TD chain is inactive; either no DMA requests have triggered a new chain\r
+* or the previous chain has completed.\r
+* 1: TD chain has been triggered by a DMA request\r
+*\r
+* Return:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_BAD_PARAM if chHandle is invalid.\r
+*\r
+* Theory:\r
+* The caller can check on the activity of the Current TD and the Chain.\r
+*\r
+*******************************************************************************/\r
+cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) \r
+{\r
+ cystatus status = CYRET_BAD_PARAM;\r
+\r
+ if(chHandle < CY_DMA_NUMBEROF_CHANNELS)\r
+ {\r
+ if(NULL != currentTd)\r
+ {\r
+ *currentTd = CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1] & 0x7Fu;\r
+ }\r
+\r
+ if(NULL != state)\r
+ {\r
+ *state= CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[0];\r
+ }\r
+\r
+ status = CYRET_SUCCESS;\r
+ }\r
+\r
+ return (status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaChSetConfiguration\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets configuration information of the channel.\r
+*\r
+* Parameters:\r
+* uint8 chHandle:\r
+* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize().\r
+*\r
+* uint8 burstCount:\r
+* Specifies the size of bursts (1 to 127) the data transfer should be divided\r
+* into. If this value is zero then the whole transfer is done in one burst.\r
+*\r
+* uint8 requestPerBurst:\r
+* The whole of the data can be split into multiple bursts, if this is\r
+* required to complete the transaction:\r
+* 0: All subsequent bursts after the first burst will be automatically\r
+* requested and carried out\r
+* 1: All subsequent bursts after the first burst must also be individually\r
+* requested.\r
+*\r
+* uint8 tdDone0:\r
+* Selects one of the TERMOUT0 interrupt lines to signal completion. The line\r
+* connected to the nrq terminal will determine the TERMOUT0_SEL definition and\r
+* should be used as supplied by cyfitter.h\r
+*\r
+* uint8 tdDone1:\r
+* Selects one of the TERMOUT1 interrupt lines to signal completion. The line\r
+* connected to the nrq terminal will determine the TERMOUT1_SEL definition and\r
+* should be used as supplied by cyfitter.h\r
+*\r
+* uint8 tdStop:\r
+* Selects one of the TERMIN interrupt lines to signal to the DMAC that the TD\r
+* should terminate. The signal connected to the trq terminal will determine\r
+* which TERMIN (termination request) is used.\r
+*\r
+* Return:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_BAD_PARAM if chHandle is invalid.\r
+*\r
+*******************************************************************************/\r
+cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst,\r
+ uint8 tdDone0, uint8 tdDone1, uint8 tdStop) \r
+{\r
+ cystatus status = CYRET_BAD_PARAM;\r
+\r
+ if(chHandle < CY_DMA_NUMBEROF_CHANNELS)\r
+ {\r
+ CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[0] = (burstCount & 0x7Fu) | ((uint8)((requestPerBurst & 0x1u) << 7u));\r
+ CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[1] = ((uint8)((tdDone1 & 0xFu) << 4u)) | (tdDone0 & 0xFu);\r
+ CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[2] = 0x0Fu & tdStop;\r
+ CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[3] = 0u; /* burstcount_remain. */\r
+\r
+ status = CYRET_SUCCESS;\r
+ }\r
+\r
+ return (status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaTdAllocate\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Allocates a TD for use with an allocated DMA channel.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* Zero-based index of the TD to be used by the caller. Since there are 128 TDs\r
+* minus the reserved TDs (0 to 23), the value returned would range from 24 to\r
+* 127 not 24 to 128. DMA_INVALID_TD is returned if there are no free TDs\r
+* available.\r
+*\r
+*******************************************************************************/\r
+uint8 CyDmaTdAllocate(void) \r
+{\r
+ uint8 interruptState;\r
+ uint8 element = CY_DMA_INVALID_TD;\r
+\r
+ /* Enter critical section! */\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS)\r
+ {\r
+ /* Get pointer to the Next available. */\r
+ element = CyDmaTdFreeIndex;\r
+\r
+ /* Decrement the count. */\r
+ CyDmaTdCurrentNumber--;\r
+\r
+ /* Update the next available pointer. */\r
+ CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0];\r
+ }\r
+\r
+ /* Exit critical section! */\r
+ CyExitCriticalSection(interruptState);\r
+\r
+ return(element);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaTdFree\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Returns a TD to the free list.\r
+*\r
+* Parameters:\r
+* uint8 tdHandle:\r
+* The TD handle returned by the CyDmaTdAllocate().\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyDmaTdFree(uint8 tdHandle) \r
+{\r
+ if(tdHandle < CY_DMA_NUMBEROF_TDS)\r
+ {\r
+ /* Enter critical section! */\r
+ uint8 interruptState = CyEnterCriticalSection();\r
+\r
+ /* Get pointer to the Next available. */\r
+ CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex;\r
+\r
+ /* Set new Next Available. */\r
+ CyDmaTdFreeIndex = tdHandle;\r
+\r
+ /* Keep track of how many left. */\r
+ CyDmaTdCurrentNumber++;\r
+\r
+ /* Exit critical section! */\r
+ CyExitCriticalSection(interruptState);\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaTdFreeCount\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Returns the number of free TDs available to be allocated.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* The number of free TDs.\r
+*\r
+*******************************************************************************/\r
+uint8 CyDmaTdFreeCount(void) \r
+{\r
+ return(CyDmaTdCurrentNumber - CY_DMA_NUMBEROF_CHANNELS);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaTdSetConfiguration\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Configures the TD.\r
+*\r
+* Parameters:\r
+* uint8 tdHandle:\r
+* A handle previously returned by CyDmaTdAlloc().\r
+*\r
+* uint16 transferCount:\r
+* The size of the data transfer (in bytes) for this TD. A size of zero will\r
+* cause the transfer to continue indefinitely. This parameter is limited to\r
+* 4095 bytes; the TD is not initialized at all when a higher value is passed.\r
+*\r
+* uint8 nextTd:\r
+* Zero based index of the next Transfer Descriptor in the TD chain. Zero is a\r
+* valid pointer to the next TD; DMA_END_CHAIN_TD is the end of the chain.\r
+* DMA_DISABLE_TD indicates an end to the chain and the DMA is disabled. No\r
+* further TDs are fetched. DMA_DISABLE_TD is only supported on PSoC3 and\r
+* PSoC 5LP silicons.\r
+*\r
+* uint8 configuration:\r
+* Stores the Bit field of configuration bits.\r
+*\r
+* CY_DMA_TD_SWAP_EN - Perform endian swap\r
+*\r
+* CY_DMA_TD_SWAP_SIZE4 - Swap size = 4 bytes\r
+*\r
+* CY_DMA_TD_AUTO_EXEC_NEXT - The next TD in the chain will trigger\r
+* automatically when the current TD completes.\r
+*\r
+* CY_DMA_TD_TERMIN_EN - Terminate this TD if a positive edge on the trq\r
+* input line occurs. The positive edge must occur\r
+* during a burst. That is the only time the DMAC\r
+* will listen for it.\r
+*\r
+* DMA__TD_TERMOUT_EN - When this TD completes, the TERMOUT signal will\r
+* generate a pulse. Note that this option is\r
+* instance specific with the instance name followed\r
+* by two underscores. In this example, the instance\r
+* name is DMA.\r
+*\r
+* CY_DMA_TD_INC_DST_ADR - Increment DST_ADR according to the size of each\r
+* data transaction in the burst.\r
+*\r
+* CY_DMA_TD_INC_SRC_ADR - Increment SRC_ADR according to the size of each\r
+* data transaction in the burst.\r
+*\r
+* Return:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_BAD_PARAM if tdHandle or transferCount is invalid.\r
+*\r
+*******************************************************************************/\r
+cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration) \\r
+ \r
+{\r
+ cystatus status = CYRET_BAD_PARAM;\r
+\r
+ if((tdHandle < CY_DMA_NUMBEROF_TDS) && (0u == (0xF000u & transferCount)))\r
+ {\r
+ /* Set 12 bits transfer count. */\r
+ reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u];\r
+ CY_SET_REG16(convert, transferCount);\r
+\r
+ /* Set Next TD pointer. */\r
+ CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u] = nextTd;\r
+\r
+ /* Configure the TD */\r
+ CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u] = configuration;\r
+\r
+ status = CYRET_SUCCESS;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaTdGetConfiguration\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Retrieves the configuration of the TD. If a NULL pointer is passed as a\r
+* parameter, that parameter is skipped. You may request only the values you are\r
+* interested in.\r
+*\r
+* Parameters:\r
+* uint8 tdHandle:\r
+* A handle previously returned by CyDmaTdAlloc().\r
+*\r
+* uint16 * transferCount:\r
+* The address to store the size of the data transfer (in bytes) for this TD.\r
+* A size of zero could indicate that the TD has completed its transfer, or\r
+* that the TD is doing an indefinite transfer.\r
+*\r
+* uint8 * nextTd:\r
+* The address to store the index of the next TD in the TD chain.\r
+*\r
+* uint8 * configuration:\r
+* The address to store the Bit field of configuration bits.\r
+* See CyDmaTdSetConfiguration() function description.\r
+*\r
+* Return:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_BAD_PARAM if tdHandle is invalid.\r
+*\r
+* Side Effects:\r
+* If a TD has a transfer count of N and is executed, the transfer count becomes\r
+* 0. If it is reexecuted, the Transfer count of zero will be interpreted as a\r
+* request for indefinite transfer. Be careful when requesting a TD with a\r
+* transfer count of zero.\r
+*\r
+*******************************************************************************/\r
+cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration) \\r
+ \r
+{\r
+ cystatus status = CYRET_BAD_PARAM;\r
+\r
+ if(tdHandle < CY_DMA_NUMBEROF_TDS)\r
+ {\r
+ /* If we have a pointer */\r
+ if(NULL != transferCount)\r
+ {\r
+ /* Get the 12 bits of the transfer count */\r
+ reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0];\r
+ *transferCount = 0x0FFFu & CY_GET_REG16(convert);\r
+ }\r
+\r
+ /* If we have a pointer */\r
+ if(NULL != nextTd)\r
+ {\r
+ /* Get the Next TD pointer */\r
+ *nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u];\r
+ }\r
+\r
+ /* If we have a pointer */\r
+ if(NULL != configuration)\r
+ {\r
+ /* Get the configuration the TD */\r
+ *configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u];\r
+ }\r
+\r
+ status = CYRET_SUCCESS;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaTdSetAddress\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the lower 16 bits of the source and destination addresses for this TD\r
+* only.\r
+*\r
+* Parameters:\r
+* uint8 tdHandle:\r
+* A handle previously returned by CyDmaTdAlloc().\r
+*\r
+* uint16 source:\r
+* The lower 16 address bits of the source of the data transfer.\r
+*\r
+* uint16 destination:\r
+* The lower 16 address bits of the destination of the data transfer.\r
+*\r
+* Return:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_BAD_PARAM if tdHandle is invalid.\r
+*\r
+*******************************************************************************/\r
+cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) \r
+{\r
+ cystatus status = CYRET_BAD_PARAM;\r
+\r
+ if(tdHandle < CY_DMA_NUMBEROF_TDS)\r
+ {\r
+ /* Set source address */\r
+ reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0];\r
+ CY_SET_REG16(convert, source);\r
+\r
+ /* Set destination address */\r
+ CY_SET_REG16((reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2], destination);\r
+\r
+ status = CYRET_SUCCESS;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaTdGetAddress\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Retrieves the lower 16 bits of the source and/or destination addresses for\r
+* this TD only. If NULL is passed for a pointer parameter, that value is\r
+* skipped. You may request only the values of interest.\r
+*\r
+* Parameters:\r
+* uint8 tdHandle:\r
+* A handle previously returned by CyDmaTdAlloc().\r
+*\r
+* uint16 * source:\r
+* The address to store the lower 16 address bits of the source of the data\r
+* transfer.\r
+*\r
+* uint16 * destination:\r
+* The address to store the lower 16 address bits of the destination of the\r
+* data transfer.\r
+*\r
+* Return:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_BAD_PARAM if tdHandle is invalid.\r
+*\r
+*******************************************************************************/\r
+cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) \r
+{\r
+ cystatus status = CYRET_BAD_PARAM;\r
+\r
+ if(tdHandle < CY_DMA_NUMBEROF_TDS)\r
+ {\r
+ /* If we have a pointer. */\r
+ if(NULL != source)\r
+ {\r
+ /* Get source address */\r
+ reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0];\r
+ *source = CY_GET_REG16(convert);\r
+ }\r
+\r
+ /* If we have a pointer. */\r
+ if(NULL != destination)\r
+ {\r
+ /* Get Destination address. */\r
+ *destination = CY_GET_REG16((reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2]);\r
+ }\r
+\r
+ status = CYRET_SUCCESS;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDmaChRoundRobin\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Either enables or disables the Round-Robin scheduling enforcement algorithm.\r
+* Within a priority level a Round-Robin fairness algorithm is enforced.\r
+*\r
+* Parameters:\r
+* uint8 chHandle:\r
+* A handle previously returned by CyDmaChAlloc() or Dma_DmaInitialize().\r
+*\r
+* uint8 enableRR:\r
+* 0: Disable Round-Robin fairness algorithm\r
+* 1: Enable Round-Robin fairness algorithm\r
+*\r
+* Return:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_BAD_PARAM if chHandle is invalid.\r
+*\r
+*******************************************************************************/\r
+cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) \r
+{\r
+ cystatus status = CYRET_BAD_PARAM;\r
+\r
+ if(chHandle < CY_DMA_NUMBEROF_CHANNELS)\r
+ {\r
+ CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] =\r
+ (CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~CY_DMA_ROUND_ROBIN_ENABLE))) |\r
+ ((0u != enableRR) ? CY_DMA_ROUND_ROBIN_ENABLE : ((uint8)(~CY_DMA_ROUND_ROBIN_ENABLE)));\r
+\r
+ status = CYRET_SUCCESS;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: CyDmac.h\r
+* Version 3.40\r
+*\r
+* Description:\r
+* Provides the function definitions for the DMA Controller.\r
+*\r
+* Note:\r
+* Documentation of the API's in this file is located in the\r
+* System Reference Guide provided with PSoC Creator.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_BOOT_CYDMAC_H)\r
+#define CY_BOOT_CYDMAC_H\r
+\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+#include "cydevice_trm.h"\r
+#include "CyLib.h"\r
+\r
+\r
+/***************************************\r
+* Function Prototypes\r
+***************************************/\r
+\r
+/* DMA Controller functions. */\r
+void CyDmacConfigure(void) ;\r
+uint8 CyDmacError(void) ;\r
+void CyDmacClearError(uint8 error) ;\r
+uint32 CyDmacErrorAddress(void) ;\r
+\r
+/* Channel specific functions. */\r
+uint8 CyDmaChAlloc(void) ;\r
+cystatus CyDmaChFree(uint8 chHandle) ;\r
+cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) ;\r
+cystatus CyDmaChDisable(uint8 chHandle) ;\r
+cystatus CyDmaClearPendingDrq(uint8 chHandle) ;\r
+cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) ;\r
+cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination);\r
+cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) ;\r
+cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) ;\r
+cystatus CyDmaChGetRequest(uint8 chHandle) ;\r
+cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) ;\r
+cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, uint8 tdDone0, uint8 tdDone1, uint8 tdStop) ;\r
+cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) ;\r
+\r
+/* Transfer Descriptor functions. */\r
+uint8 CyDmaTdAllocate(void) ;\r
+void CyDmaTdFree(uint8 tdHandle) ;\r
+uint8 CyDmaTdFreeCount(void) ;\r
+cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration) ;\r
+cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration) ;\r
+cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) ;\r
+cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) ;\r
+\r
+\r
+/***************************************\r
+* Data Struct Definitions\r
+***************************************/\r
+\r
+typedef struct dmac_ch_struct\r
+{\r
+ volatile uint8 basic_cfg[4];\r
+ volatile uint8 action[4];\r
+ volatile uint8 basic_status[4];\r
+ volatile uint8 reserved[4];\r
+\r
+} dmac_ch;\r
+\r
+\r
+typedef struct dmac_cfgmem_struct\r
+{\r
+ volatile uint8 CFG0[4];\r
+ volatile uint8 CFG1[4];\r
+\r
+} dmac_cfgmem;\r
+\r
+\r
+typedef struct dmac_tdmem_struct\r
+{\r
+ volatile uint8 TD0[4];\r
+ volatile uint8 TD1[4];\r
+\r
+} dmac_tdmem;\r
+\r
+\r
+typedef struct dmac_tdmem2_struct\r
+{\r
+ volatile uint16 xfercnt;\r
+ volatile uint8 next_td_ptr;\r
+ volatile uint8 flags;\r
+ volatile uint16 src_adr;\r
+ volatile uint16 dst_adr;\r
+} dmac_tdmem2;\r
+\r
+\r
+/***************************************\r
+* API Constants\r
+***************************************/\r
+\r
+#define CY_DMA_INVALID_CHANNEL 0xFFu /* Invalid Channel ID */\r
+#define CY_DMA_INVALID_TD 0xFFu /* Invalid TD */\r
+#define CY_DMA_END_CHAIN_TD 0xFFu /* End of chain TD */\r
+\r
+#if(CY_PSOC3 || CY_PSOC5LP)\r
+ #define CY_DMA_DISABLE_TD 0xFEu\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+#define CY_DMA_TD_SIZE 0x08u\r
+\r
+/* The "u" was removed as workaround for Keil compiler bug */\r
+#define CY_DMA_TD_SWAP_EN 0x80\r
+#define CY_DMA_TD_SWAP_SIZE4 0x40\r
+#define CY_DMA_TD_AUTO_EXEC_NEXT 0x20\r
+#define CY_DMA_TD_TERMIN_EN 0x10\r
+#define CY_DMA_TD_TERMOUT1_EN 0x08\r
+#define CY_DMA_TD_TERMOUT0_EN 0x04\r
+#define CY_DMA_TD_INC_DST_ADR 0x02\r
+#define CY_DMA_TD_INC_SRC_ADR 0x01\r
+\r
+#define CY_DMA_NUMBEROF_TDS 128u\r
+#define CY_DMA_NUMBEROF_CHANNELS ((uint8)(CYDEV_DMA_CHANNELS_AVAILABLE))\r
+\r
+/* Action register bits */\r
+#define CY_DMA_CPU_REQ ((uint8)(1u << 0u))\r
+#define CY_DMA_CPU_TERM_TD ((uint8)(1u << 1u))\r
+#define CY_DMA_CPU_TERM_CHAIN ((uint8)(1u << 2u))\r
+\r
+/* Basic Status register bits */\r
+#define CY_DMA_STATUS_CHAIN_ACTIVE ((uint8)(1u << 0u))\r
+#define CY_DMA_STATUS_TD_ACTIVE ((uint8)(1u << 1u))\r
+\r
+/* DMA controller register error bits */\r
+#define CY_DMA_BUS_TIMEOUT (1u << 1u)\r
+#define CY_DMA_UNPOP_ACC (1u << 2u)\r
+#define CY_DMA_PERIPH_ERR (1u << 3u)\r
+\r
+/* Round robin bits */\r
+#define CY_DMA_ROUND_ROBIN_ENABLE ((uint8)(1u << 4u))\r
+\r
+\r
+/***************************************\r
+* Registers\r
+***************************************/\r
+\r
+#define CY_DMA_CFG_REG (*(reg32 *) CYREG_PHUB_CFG)\r
+#define CY_DMA_CFG_PTR ( (reg32 *) CYREG_PHUB_CFG)\r
+\r
+#define CY_DMA_ERR_REG (*(reg32 *) CYREG_PHUB_ERR)\r
+#define CY_DMA_ERR_PTR ( (reg32 *) CYREG_PHUB_ERR)\r
+\r
+#define CY_DMA_ERR_ADR_REG (*(reg32 *) CYREG_PHUB_ERR_ADR)\r
+#define CY_DMA_ERR_ADR_PTR ( (reg32 *) CYREG_PHUB_ERR_ADR)\r
+\r
+#define CY_DMA_CH_STRUCT_REG (*(dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE)\r
+#define CY_DMA_CH_STRUCT_PTR ( (dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE)\r
+\r
+#define CY_DMA_CFGMEM_STRUCT_REG (*(dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE)\r
+#define CY_DMA_CFGMEM_STRUCT_PTR ( (dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE)\r
+\r
+#define CY_DMA_TDMEM_STRUCT_REG (*(dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE)\r
+#define CY_DMA_TDMEM_STRUCT_PTR ( (dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE)\r
+\r
+\r
+/*******************************************************************************\r
+* Following code are OBSOLETE and must not be used starting from cy_boot 3.0\r
+*******************************************************************************/\r
+#define DMA_INVALID_CHANNEL (CY_DMA_INVALID_CHANNEL)\r
+#define DMA_INVALID_TD (CY_DMA_INVALID_TD)\r
+#define DMA_END_CHAIN_TD (CY_DMA_END_CHAIN_TD)\r
+#define DMAC_TD_SIZE (CY_DMA_TD_SIZE)\r
+#define TD_SWAP_EN (CY_DMA_TD_SWAP_EN)\r
+#define TD_SWAP_SIZE4 (CY_DMA_TD_SWAP_SIZE4)\r
+#define TD_AUTO_EXEC_NEXT (CY_DMA_TD_AUTO_EXEC_NEXT)\r
+#define TD_TERMIN_EN (CY_DMA_TD_TERMIN_EN)\r
+#define TD_TERMOUT1_EN (CY_DMA_TD_TERMOUT1_EN)\r
+#define TD_TERMOUT0_EN (CY_DMA_TD_TERMOUT0_EN)\r
+#define TD_INC_DST_ADR (CY_DMA_TD_INC_DST_ADR)\r
+#define TD_INC_SRC_ADR (CY_DMA_TD_INC_SRC_ADR)\r
+#define NUMBEROF_TDS (CY_DMA_NUMBEROF_TDS)\r
+#define NUMBEROF_CHANNELS (CY_DMA_NUMBEROF_CHANNELS)\r
+#define CPU_REQ (CY_DMA_CPU_REQ)\r
+#define CPU_TERM_TD (CY_DMA_CPU_TERM_TD)\r
+#define CPU_TERM_CHAIN (CY_DMA_CPU_TERM_CHAIN)\r
+#define STATUS_CHAIN_ACTIVE (CY_DMA_STATUS_CHAIN_ACTIVE)\r
+#define STATUS_TD_ACTIVE (CY_DMA_STATUS_TD_ACTIVE)\r
+#define DMAC_BUS_TIMEOUT (CY_DMA_BUS_TIMEOUT)\r
+#define DMAC_UNPOP_ACC (CY_DMA_UNPOP_ACC)\r
+#define DMAC_PERIPH_ERR (CY_DMA_PERIPH_ERR)\r
+#define ROUND_ROBIN_ENABLE (CY_DMA_ROUND_ROBIN_ENABLE)\r
+#if(CY_PSOC3 || CY_PSOC5LP)\r
+ #define DMA_DISABLE_TD (CY_DMA_DISABLE_TD)\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+#define DMAC_CFG (CY_DMA_CFG_PTR)\r
+#define DMAC_ERR (CY_DMA_ERR_PTR)\r
+#define DMAC_ERR_ADR (CY_DMA_ERR_ADR_PTR)\r
+#define DMAC_CH (CY_DMA_CH_STRUCT_PTR)\r
+#define DMAC_CFGMEM (CY_DMA_CFGMEM_STRUCT_PTR)\r
+#define DMAC_TDMEM (CY_DMA_TDMEM_STRUCT_PTR)\r
+\r
+#endif /* (CY_BOOT_CYDMAC_H) */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: CyFlash.c\r
+* Version 3.40\r
+*\r
+* Description:\r
+* Provides an API for the FLASH/EEPROM.\r
+*\r
+* Note:\r
+* This code is endian agnostic.\r
+*\r
+* Note:\r
+* Documentation of the API's in this file is located in the\r
+* System Reference Guide provided with PSoC Creator.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "CyFlash.h"\r
+\r
+\r
+/*******************************************************************************\r
+* Holds die temperature, updated by CySetTemp(). Used for flash writting.\r
+* The first byte is the sign of the temperature (0 = negative, 1 = positive).\r
+* The second byte is the magnitude.\r
+*******************************************************************************/\r
+uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];\r
+\r
+#if(CYDEV_ECC_ENABLE == 0)\r
+ static uint8 * rowBuffer = 0;\r
+#endif /* (CYDEV_ECC_ENABLE == 0) */\r
+\r
+\r
+static cystatus CySetTempInt(void);\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyFlash_Start\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enable the EEPROM/Flash.\r
+*\r
+* Note: For PSoC 5, this will enable both Flash and EEPROM. For PSoC 3 and\r
+* PSOC 5LP this will enable only Flash.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyFlash_Start(void) \r
+{\r
+ #if(CY_PSOC5A)\r
+\r
+ /* Active Power Mode */\r
+ *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_EE_MASK;\r
+\r
+ /* Standby Power Mode */\r
+ *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_EE_MASK;\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+ #if(CY_PSOC3 || CY_PSOC5LP)\r
+\r
+ /* Active Power Mode */\r
+ *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;\r
+\r
+ /* Standby Power Mode */\r
+ *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;\r
+\r
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+ CyDelayUs(CY_FLASH_EE_STARTUP_DELAY);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyFlash_Stop\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disable the EEPROM/Flash.\r
+*\r
+* Note:\r
+* PSoC 5: disable both Flash and EEPROM.\r
+* PSoC 3 and PSOC 5LP: disable only Flash. Use CyEEPROM_Stop() to stop EEPROM.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Side Effects:\r
+* This setting is ignored as long as the CPU is currently running. This will\r
+* only take effect when the CPU is later disabled.\r
+*\r
+*******************************************************************************/\r
+void CyFlash_Stop(void) \r
+{\r
+ #if (CY_PSOC5A)\r
+\r
+ /* Active Power Mode */\r
+ *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_EE_MASK));\r
+\r
+ /* Standby Power Mode */\r
+ *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_EE_MASK));\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+ #if (CY_PSOC3 || CY_PSOC5LP)\r
+\r
+ /* Active Power Mode */\r
+ *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));\r
+\r
+ /* Standby Power Mode */\r
+ *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));\r
+\r
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CySetTempInt\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sends a command to the SPC to read the die temperature. Sets a global value\r
+* used by the Write functions. This function must be called once before\r
+* executing a series of Flash writing functions.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* status:\r
+* CYRET_SUCCESS - if successful\r
+* CYRET_LOCKED - if Flash writing already in use\r
+* CYRET_UNKNOWN - if there was an SPC error\r
+*\r
+*******************************************************************************/\r
+static cystatus CySetTempInt(void) \r
+{\r
+ cystatus status;\r
+\r
+ /* Make sure SPC is powered */\r
+ CySpcStart();\r
+\r
+ /* Plan for failure. */\r
+ status = CYRET_UNKNOWN;\r
+\r
+ if(CySpcLock() == CYRET_SUCCESS)\r
+ {\r
+ /* Write the command. */\r
+ #if(CY_PSOC5A)\r
+ if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES, CY_TEMP_TIMER_PERIOD, CY_TEMP_CLK_DIV_SELECT))\r
+ #else\r
+ if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES))\r
+ #endif /* (CY_PSOC5A) */\r
+ {\r
+ do\r
+ {\r
+ if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_DATA_SIZE)\r
+ {\r
+ status = CYRET_SUCCESS;\r
+\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Spin until idle. */\r
+ CyDelayUs(1u);\r
+ }\r
+ break;\r
+ }\r
+\r
+ } while(CY_SPC_BUSY);\r
+ }\r
+\r
+ CySpcUnlock();\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+\r
+ return (status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CySetTemp\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* This is a wraparound for CySetTempInt(). It is used to return second\r
+* successful read of temperature value.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* status:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_LOCKED if Flash writing already in use\r
+* CYRET_UNKNOWN if there was an SPC error.\r
+*\r
+* uint8 dieTemperature[2]:\r
+* Holds die temperature for the flash writting algorithm. The first byte is\r
+* the sign of the temperature (0 = negative, 1 = positive). The second byte is\r
+* the magnitude.\r
+*\r
+*******************************************************************************/\r
+cystatus CySetTemp(void) \r
+{\r
+ cystatus status = CySetTempInt();\r
+\r
+ if(status == CYRET_SUCCESS)\r
+ {\r
+ status = CySetTempInt();\r
+ }\r
+\r
+ return (status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CySetFlashEEBuffer\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the user supplied temporary buffer to store SPC data while performing\r
+* flash and EEPROM commands. This buffer is only necessary when Flash ECC is\r
+* disabled.\r
+*\r
+* Parameters:\r
+* buffer:\r
+* Address of block of memory to store temporary memory. The size of the block\r
+* of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE.\r
+*\r
+* Return:\r
+* status:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_BAD_PARAM if the buffer is NULL\r
+*\r
+*******************************************************************************/\r
+cystatus CySetFlashEEBuffer(uint8 * buffer) \r
+{\r
+ cystatus status = CYRET_SUCCESS;\r
+\r
+ CySpcStart();\r
+\r
+ #if(CYDEV_ECC_ENABLE == 0)\r
+\r
+ if(NULL == buffer)\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+ else if(CySpcLock() != CYRET_SUCCESS)\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+ else\r
+ {\r
+ rowBuffer = buffer;\r
+ CySpcUnlock();\r
+ }\r
+\r
+ #else\r
+\r
+ /* To supress the warning */\r
+ buffer = buffer;\r
+\r
+ #endif /* (CYDEV_ECC_ENABLE == 0u) */\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+#if(CYDEV_ECC_ENABLE == 1)\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyWriteRowData\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Sends a command to the SPC to load and program a row of data in flash.\r
+ *\r
+ * Parameters:\r
+ * arrayID:\r
+ * ID of the array to write.\r
+ * rowAddress:\r
+ * rowAddress of flash row to program.\r
+ * rowData:\r
+ * Array of bytes to write.\r
+ *\r
+ * Return:\r
+ * status:\r
+ * CYRET_SUCCESS if successful.\r
+ * CYRET_LOCKED if the SPC is already in use.\r
+ * CYRET_CANCELED if command not accepted\r
+ * CYRET_UNKNOWN if there was an SPC error.\r
+ *\r
+ *******************************************************************************/\r
+ cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) \r
+ {\r
+ uint16 rowSize;\r
+ cystatus status;\r
+\r
+ rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE;\r
+ status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize);\r
+\r
+ return(status);\r
+ }\r
+\r
+#else\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyWriteRowData\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Sends a command to the SPC to load and program a row of data in flash.\r
+ *\r
+ * Parameters:\r
+ * arrayID : ID of the array to write.\r
+ * rowAddress : rowAddress of flash row to program.\r
+ * rowData : Array of bytes to write.\r
+ *\r
+ * Return:\r
+ * status:\r
+ * CYRET_SUCCESS if successful.\r
+ * CYRET_LOCKED if the SPC is already in use.\r
+ * CYRET_CANCELED if command not accepted\r
+ * CYRET_UNKNOWN if there was an SPC error.\r
+ *\r
+ *******************************************************************************/\r
+ cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) \r
+ {\r
+ uint8 i;\r
+ uint32 offset;\r
+ uint16 rowSize;\r
+ cystatus status;\r
+\r
+ rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? \\r
+ CYDEV_EEPROM_ROW_SIZE : \\r
+ (CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);\r
+\r
+ if(rowSize != CYDEV_EEPROM_ROW_SIZE)\r
+ {\r
+ /* Save the ECC area. */\r
+ offset = CYDEV_ECC_BASE + ((uint32) arrayId * CYDEV_ECC_SECTOR_SIZE) +\r
+ ((uint32) rowAddress * CYDEV_ECC_ROW_SIZE);\r
+\r
+ for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)\r
+ {\r
+ *(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i));\r
+ }\r
+ }\r
+\r
+ /* Copy the rowdata to the temporary buffer. */\r
+ #if(CY_PSOC3)\r
+ (void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE);\r
+ #else\r
+ (void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE);\r
+ #endif /* (CY_PSOC3) */\r
+\r
+ status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize);\r
+\r
+ return(status);\r
+ }\r
+\r
+#endif /* (CYDEV_ECC_ENABLE == 0u) */\r
+\r
+\r
+#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyWriteRowConfig\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Sends a command to the SPC to load and program a row of config data in flash.\r
+ * This function is only valid for Flash array IDs (not for EEPROM).\r
+ *\r
+ * Parameters:\r
+ * arrayId:\r
+ * ID of the array to write\r
+ * rowAddress:\r
+ * Address of the sector to erase.\r
+ * rowECC:\r
+ * Array of bytes to write.\r
+ *\r
+ * Return:\r
+ * status:\r
+ * CYRET_SUCCESS if successful.\r
+ * CYRET_LOCKED if the SPC is already in use.\r
+ * CYRET_CANCELED if command not accepted\r
+ * CYRET_UNKNOWN if there was an SPC error.\r
+ *\r
+ *******************************************************************************/\r
+ cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) \r
+ {\r
+ uint32 offset;\r
+ uint16 i;\r
+ cystatus status;\r
+\r
+ /* Read the existing flash data. */\r
+ offset = ((uint32) arrayId * CYDEV_FLS_SECTOR_SIZE) +\r
+ ((uint32) rowAddress * CYDEV_FLS_ROW_SIZE);\r
+ \r
+ #if (CYDEV_FLS_BASE != 0u)\r
+ offset += CYDEV_FLS_BASE;\r
+ #endif\r
+\r
+ for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)\r
+ {\r
+ rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i));\r
+ }\r
+\r
+ #if(CY_PSOC3)\r
+ (void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (void *)((uint32)rowECC), (int16) CYDEV_ECC_ROW_SIZE);\r
+ #else\r
+ (void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (const void *) rowECC, CYDEV_ECC_ROW_SIZE);\r
+ #endif /* (CY_PSOC3) */\r
+\r
+ status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);\r
+\r
+ return (status);\r
+ }\r
+\r
+#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyWriteRowFull\r
+********************************************************************************\r
+* Summary:\r
+* Sends a command to the SPC to load and program a row of data in flash.\r
+* rowData array is expected to contain Flash and ECC data if needed.\r
+*\r
+* Parameters:\r
+* arrayId: FLASH or EEPROM array id.\r
+* rowData: pointer to a row of data to write.\r
+* rowNumber: Zero based number of the row.\r
+* rowSize: Size of the row.\r
+*\r
+* Return:\r
+* CYRET_SUCCESS if successful.\r
+* CYRET_LOCKED if the SPC is already in use.\r
+* CYRET_CANCELED if command not accepted\r
+* CYRET_UNKNOWN if there was an SPC error.\r
+*\r
+*******************************************************************************/\r
+cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \\r
+ \r
+{\r
+ cystatus status;\r
+\r
+ if(CySpcLock() == CYRET_SUCCESS)\r
+ {\r
+ /* Load row data into SPC internal latch */\r
+ status = CySpcLoadRow(arrayId, rowData, rowSize);\r
+\r
+ if(CYRET_STARTED == status)\r
+ {\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Wait for SPC to finish and get SPC status */\r
+ CyDelayUs(1u);\r
+ }\r
+\r
+ /* Hide SPC status */\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
+\r
+ if(CYRET_SUCCESS == status)\r
+ {\r
+ /* Erase and program flash with the data from SPC interval latch */\r
+ status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]);\r
+\r
+ if(CYRET_STARTED == status)\r
+ {\r
+ while(CY_SPC_BUSY)\r
+ {\r
+ /* Wait for SPC to finish and get SPC status */\r
+ CyDelayUs(1u);\r
+ }\r
+\r
+ /* Hide SPC status */\r
+ if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS)\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_UNKNOWN;\r
+ }\r
+ }\r
+ }\r
+\r
+ }\r
+\r
+ CySpcUnlock();\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyFlash_SetWaitCycles\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the number of clock cycles the cache will wait before it samples data\r
+* coming back from Flash. This function must be called before increasing CPU\r
+* clock frequency. It can optionally be called after lowering CPU clock\r
+* frequency in order to improve CPU performance.\r
+*\r
+* Parameters:\r
+* uint8 freq:\r
+* Frequency of operation in Megahertz.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyFlash_SetWaitCycles(uint8 freq) \r
+{\r
+ uint8 interruptState;\r
+\r
+ /* Save current global interrupt enable and disable it */\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ /***************************************************************************\r
+ * The number of clock cycles the cache will wait before it samples data\r
+ * coming back from Flash must be equal or greater to to the CPU frequency\r
+ * outlined in clock cycles.\r
+ ***************************************************************************/\r
+\r
+ #if (CY_PSOC3)\r
+\r
+ if (freq <= 22u)\r
+ {\r
+ *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
+ ((uint8)(CY_FLASH_LESSER_OR_EQUAL_22MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
+ }\r
+ else if (freq <= 44u)\r
+ {\r
+ *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
+ ((uint8)(CY_FLASH_LESSER_OR_EQUAL_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
+ }\r
+ else\r
+ {\r
+ *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
+ ((uint8)(CY_FLASH_GREATER_44MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
+ }\r
+\r
+ #endif /* (CY_PSOC3) */\r
+\r
+\r
+ #if (CY_PSOC5A)\r
+\r
+ if (freq <= 16u)\r
+ {\r
+ *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
+ ((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
+ }\r
+ else if (freq <= 33u)\r
+ {\r
+ *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
+ ((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
+ }\r
+ else if (freq <= 50u)\r
+ {\r
+ *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
+ ((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
+ }\r
+ else\r
+ {\r
+ *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
+ ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
+ }\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+\r
+ #if (CY_PSOC5LP)\r
+\r
+ if (freq <= 16u)\r
+ {\r
+ *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
+ ((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
+ }\r
+ else if (freq <= 33u)\r
+ {\r
+ *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
+ ((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
+ }\r
+ else if (freq <= 50u)\r
+ {\r
+ *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
+ ((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
+ }\r
+ else\r
+ {\r
+ *CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |\r
+ ((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT)));\r
+ }\r
+\r
+ #endif /* (CY_PSOC5LP) */\r
+\r
+ /* Restore global interrupt enable state */\r
+ CyExitCriticalSection(interruptState);\r
+}\r
+\r
+\r
+#if (CY_PSOC3 || CY_PSOC5LP)\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyEEPROM_Start\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Enable the EEPROM.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CyEEPROM_Start(void) \r
+ {\r
+ /* Active Power Mode */\r
+ *CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;\r
+\r
+ /* Standby Power Mode */\r
+ *CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyEEPROM_Stop\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Disable the EEPROM.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CyEEPROM_Stop (void) \r
+ {\r
+ /* Active Power Mode */\r
+ *CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));\r
+\r
+ /* Standby Power Mode */\r
+ *CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));\r
+ }\r
+\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyEEPROM_ReadReserve\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Request access to the EEPROM for reading and wait until access is available.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyEEPROM_ReadReserve(void) \r
+{\r
+ /* Make a request for PHUB to have access */\r
+ *CY_FLASH_EE_SCR_PTR |= CY_FLASH_EE_SCR_AHB_EE_REQ;\r
+\r
+ while (0u == (*CY_FLASH_EE_SCR_PTR & CY_FLASH_EE_SCR_AHB_EE_ACK))\r
+ {\r
+ /* Wait for acknowledgement from PHUB */\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyEEPROM_ReadRelease\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Release the read reservation of the EEPROM.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyEEPROM_ReadRelease(void) \r
+{\r
+ *CY_FLASH_EE_SCR_PTR |= 0x00u;\r
+}\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: CyFlash.h\r
+* Version 3.40\r
+*\r
+* Description:\r
+* Provides the function definitions for the FLASH/EEPROM.\r
+*\r
+* Note:\r
+* Documentation of the API's in this file is located in the\r
+* System Reference Guide provided with PSoC Creator.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_BOOT_CYFLASH_H)\r
+#define CY_BOOT_CYFLASH_H\r
+\r
+#include "cydevice_trm.h"\r
+#include "cytypes.h"\r
+#include "CyLib.h"\r
+#include "CySpc.h"\r
+\r
+#define CY_FLASH_DIE_TEMP_DATA_SIZE (2u) /* Die temperature data size */\r
+\r
+extern uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE];\r
+\r
+\r
+/***************************************\r
+* API Constants\r
+***************************************/\r
+\r
+#define CY_FLASH_BASE (CYDEV_FLASH_BASE)\r
+#define CY_FLASH_SIZE (CYDEV_FLS_SIZE)\r
+#define CY_FLASH_SIZEOF_ARRAY (CYDEV_FLS_SECTOR_SIZE)\r
+#define CY_FLASH_SIZEOF_ROW (CYDEV_FLS_ROW_SIZE)\r
+#define CY_FLASH_SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE)\r
+#define CY_FLASH_NUMBER_ROWS (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE)\r
+#define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE)\r
+\r
+#define CY_EEPROM_BASE (CYDEV_EE_BASE)\r
+#define CY_EEPROM_SIZE (CYDEV_EE_SIZE)\r
+#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EEPROM_SECTOR_SIZE)\r
+#define CY_EEPROM_SIZEOF_ROW (CYDEV_EEPROM_ROW_SIZE)\r
+#define CY_EEPROM_NUMBER_ROWS (EEPROM_SIZE / CYDEV_EEPROM_ROW_SIZE)\r
+#define CY_EEPROM_NUMBER_ARRAYS (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY)\r
+\r
+\r
+#if !defined(CYDEV_FLS_BASE)\r
+ #define CYDEV_FLS_BASE CYDEV_FLASH_BASE\r
+#endif /* !defined(CYDEV_FLS_BASE) */\r
+\r
+\r
+/***************************************\r
+* Function Prototypes\r
+***************************************/\r
+\r
+/* Flash Functions */\r
+void CyFlash_Start(void);\r
+void CyFlash_Stop(void);\r
+cystatus CySetTemp(void);\r
+cystatus CySetFlashEEBuffer(uint8 * buffer);\r
+cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8 * rowData, uint16 rowSize) \\r
+ ;\r
+cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData);\r
+\r
+#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u))\r
+ cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) \\r
+ ;\r
+#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */\r
+\r
+void CyFlash_SetWaitCycles(uint8 freq) ;\r
+\r
+/* EEPROM Functions */\r
+#if (CY_PSOC3 || CY_PSOC5LP)\r
+ void CyEEPROM_Start(void) ;\r
+ void CyEEPROM_Stop(void) ;\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+void CyEEPROM_ReadReserve(void) ;\r
+void CyEEPROM_ReadRelease(void) ;\r
+\r
+\r
+/***************************************\r
+* Registers\r
+***************************************/\r
+\r
+#if (CY_PSOC5A)\r
+\r
+ /* Active Power Mode Configuration Register 0 */\r
+ #define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG0)\r
+ #define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)\r
+\r
+ /* Alternate Active Power Mode Configuration Register 0 */\r
+ #define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG0)\r
+ #define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG0)\r
+\r
+#endif /* (CY_PSOC5A) */\r
+\r
+\r
+#if (CY_PSOC3 || CY_PSOC5LP)\r
+\r
+ /* Active Power Mode Configuration Register 12 */\r
+ #define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12)\r
+ #define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)\r
+\r
+ /* Alternate Active Power Mode Configuration Register 12 */\r
+ #define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12)\r
+ #define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)\r
+\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+\r
+/* Cache Control Register */\r
+#if (CY_PSOC3)\r
+\r
+ #define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CR )\r
+ #define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CR )\r
+\r
+#else\r
+\r
+ #define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CC_CTL )\r
+ #define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CC_CTL )\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
+/* EEPROM Status & Control Register */\r
+#define CY_FLASH_EE_SCR_REG (* (reg8 *) CYREG_SPC_EE_SCR)\r
+#define CY_FLASH_EE_SCR_PTR ( (reg8 *) CYREG_SPC_EE_SCR)\r
+\r
+\r
+\r
+/***************************************\r
+* Register Constants\r
+***************************************/\r
+\r
+/* Power Mode Masks */\r
+#if(CY_PSOC5A)\r
+\r
+ #define CY_FLASH_PM_FLASH_EE_MASK (0x80u)\r
+\r
+#endif /* (CY_PSOC5A) */\r
+\r
+#if (CY_PSOC3 || CY_PSOC5LP)\r
+\r
+ #define CY_FLASH_PM_EE_MASK (0x10u)\r
+ #define CY_FLASH_PM_FLASH_MASK (0x01u)\r
+\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+\r
+/* Frequency Constants */\r
+#if (CY_PSOC3)\r
+\r
+ #define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u)\r
+ #define CY_FLASH_GREATER_44MHz (0x03u)\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+#if (CY_PSOC5A)\r
+\r
+ #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u)\r
+ #define CY_FLASH_GREATER_51MHz (0x00u)\r
+\r
+#endif /* (CY_PSOC5A) */\r
+\r
+#if (CY_PSOC5LP)\r
+\r
+ #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u)\r
+ #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u)\r
+ #define CY_FLASH_GREATER_51MHz (0x00u)\r
+\r
+#endif /* (CY_PSOC5LP) */\r
+\r
+#define CY_FLASH_CYCLES_MASK_SHIFT (0x06u)\r
+#define CY_FLASH_CYCLES_MASK ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT)))\r
+#define CY_FLASH_EE_STARTUP_DELAY (5u)\r
+\r
+#define CY_FLASH_EE_SCR_AHB_EE_REQ (0x01u)\r
+#define CY_FLASH_EE_SCR_AHB_EE_ACK (0x02u)\r
+\r
+\r
+\r
+/* Default values for getting temperature. */\r
+\r
+#define CY_TEMP_NUMBER_OF_SAMPLES (0x1u)\r
+#define CY_TEMP_TIMER_PERIOD (0xFFFu)\r
+#define CY_TEMP_CLK_DIV_SELECT (0x4u)\r
+#define CY_TEMP_NUM_SAMPLES (1 << (CY_TEMP_NUMBER_OF_SAMPLES))\r
+#define CY_SPC_CLK_PERIOD (120u) /* nS */\r
+#define CY_SYS_ns_PER_TICK (1000u)\r
+#define CY_FRM_EXEC_TIME (1000u) /* nS */\r
+\r
+#define CY_GET_TEMP_TIME ((1 << (CY_TEMP_NUM_SAMPLES + 1)) * \\r
+ (CY_SPC_CLK_PERIOD * CY_TEMP_CLK_DIV_SELECT) * \\r
+ CY_TEMP_TIMER_PERIOD + CY_FRM_EXEC_TIME)\r
+\r
+#define CY_TEMP_MAX_WAIT ((CY_GET_TEMP_TIME) / CY_SYS_ns_PER_TICK) /* In system ticks. */\r
+\r
+\r
+/*******************************************************************************\r
+* Following code are OBSOLETE and must not be used starting from cy_boot 3.0\r
+*******************************************************************************/\r
+#define FLASH_SIZE (CY_FLASH_SIZE)\r
+#define FLASH_SIZEOF_SECTOR (CY_FLASH_SIZEOF_ARRAY)\r
+#define FLASH_NUMBER_ROWS (CY_FLASH_NUMBER_ROWS)\r
+#define FLASH_NUMBER_SECTORS (CY_FLASH_NUMBER_ARRAYS)\r
+#define EEPROM_SIZE (CY_EEPROM_SIZE)\r
+#define EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY)\r
+#define EEPROM_NUMBER_ROWS (CY_EEPROM_NUMBER_ROWS)\r
+#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS)\r
+#define CY_EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS)\r
+#define CY_EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY)\r
+\r
+\r
+/*******************************************************************************\r
+* Following code are OBSOLETE and must not be used starting from cy_boot 3.30\r
+*******************************************************************************/\r
+#define FLASH_CYCLES_PTR (CY_FLASH_CONTROL_PTR)\r
+\r
+#define TEMP_NUMBER_OF_SAMPLES (CY_TEMP_NUMBER_OF_SAMPLES)\r
+#define TEMP_TIMER_PERIOD (CY_TEMP_TIMER_PERIOD)\r
+#define TEMP_CLK_DIV_SELECT (CY_TEMP_CLK_DIV_SELECT)\r
+#define NUM_SAMPLES (CY_TEMP_NUM_SAMPLES)\r
+#define SPC_CLK_PERIOD (CY_SPC_CLK_PERIOD)\r
+#define FRM_EXEC_TIME (CY_FRM_EXEC_TIME)\r
+#define GET_TEMP_TIME (CY_GET_TEMP_TIME)\r
+#define TEMP_MAX_WAIT (CY_TEMP_MAX_WAIT)\r
+\r
+#define ECC_ADDR (0x80u)\r
+\r
+\r
+#if (CY_PSOC5A)\r
+\r
+ #define PM_ACT_EEFLASH (CY_FLASH_PM_ACT_EEFLASH_PTR)\r
+ #define PM_STBY_EEFLASH (CY_FLASH_PM_ALTACT_EEFLASH_PTR)\r
+\r
+#endif /* (CY_PSOC5A) */\r
+\r
+#if (CY_PSOC3 || CY_PSOC5LP)\r
+\r
+ #define PM_ACT_EE_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR)\r
+ #define PM_ACT_FLASH_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR)\r
+\r
+ #define PM_STBY_EE_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR)\r
+ #define PM_STBY_FLASH_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR)\r
+\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+\r
+#if(CY_PSOC5A)\r
+\r
+ #define PM_FLASH_EE_MASK (CY_FLASH_PM_FLASH_EE_MASK)\r
+\r
+#endif /* (CY_PSOC5A) */\r
+\r
+#if (CY_PSOC3 || CY_PSOC5LP)\r
+\r
+ #define PM_EE_MASK (CY_FLASH_PM_EE_MASK)\r
+ #define PM_FLASH_MASK (CY_FLASH_PM_FLASH_MASK)\r
+\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+\r
+#define FLASH_CYCLES_MASK_SHIFT (CY_FLASH_CYCLES_MASK_SHIFT)\r
+#define FLASH_CYCLES_MASK (CY_FLASH_CYCLES_MASK)\r
+\r
+\r
+#if (CY_PSOC3)\r
+\r
+ #define LESSER_OR_EQUAL_22MHz (CY_FLASH_LESSER_OR_EQUAL_22MHz)\r
+ #define LESSER_OR_EQUAL_44MHz (CY_FLASH_LESSER_OR_EQUAL_44MHz)\r
+ #define GREATER_44MHz (CY_FLASH_GREATER_44MHz)\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+#if (CY_PSOC5A)\r
+\r
+ #define LESSER_OR_EQUAL_16MHz (CY_FLASH_LESSER_OR_EQUAL_16MHz)\r
+ #define LESSER_OR_EQUAL_33MHz (CY_FLASH_LESSER_OR_EQUAL_33MHz)\r
+ #define LESSER_OR_EQUAL_50MHz (CY_FLASH_LESSER_OR_EQUAL_50MHz)\r
+ #define GREATER_51MHz (CY_FLASH_GREATER_51MHz)\r
+\r
+#endif /* (CY_PSOC5A) */\r
+\r
+#if (CY_PSOC5LP)\r
+\r
+ #define LESSER_OR_EQUAL_16MHz (CY_FLASH_LESSER_OR_EQUAL_16MHz)\r
+ #define LESSER_OR_EQUAL_33MHz (CY_FLASH_LESSER_OR_EQUAL_33MHz)\r
+ #define LESSER_OR_EQUAL_50MHz (CY_FLASH_LESSER_OR_EQUAL_50MHz)\r
+ #define LESSER_OR_EQUAL_67MHz (CY_FLASH_LESSER_OR_EQUAL_67MHz)\r
+ #define GREATER_67MHz (CY_FLASH_GREATER_67MHz)\r
+ #define GREATER_51MHz (CY_FLASH_GREATER_51MHz)\r
+\r
+#endif /* (CY_PSOC5LP) */\r
+\r
+#define AHUB_EE_REQ_ACK_PTR (CY_FLASH_EE_SCR_PTR)\r
+\r
+\r
+#endif /* (CY_BOOT_CYFLASH_H) */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: CyLib.c\r
+* Version 3.40\r
+*\r
+* Description:\r
+* Provides system API for the clocking, interrupts and watchdog timer.\r
+*\r
+* Note:\r
+* Documentation of the API's in this file is located in the\r
+* System Reference Guide provided with PSoC Creator.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "CyLib.h"\r
+\r
+\r
+/*******************************************************************************\r
+* The CyResetStatus variable is used to obtain value of RESET_SR0 register after\r
+* a device reset.\r
+*******************************************************************************/\r
+uint8 CYXDATA CyResetStatus;\r
+\r
+\r
+#if(!CY_PSOC5A)\r
+\r
+ /* Variable Vdda */\r
+ #if(CYDEV_VARIABLE_VDDA == 1)\r
+\r
+ uint8 CyScPumpEnabled = (uint8)(CYDEV_VDDA_MV < 2700);\r
+\r
+ #endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
+\r
+#endif /* (!CY_PSOC5A) */\r
+\r
+\r
+/* Do not use these definitions directly in your application */\r
+uint32 cydelay_freq_hz = BCLK__BUS_CLK__HZ;\r
+uint32 cydelay_freq_khz = (BCLK__BUS_CLK__HZ + 999u) / 1000u;\r
+uint8 cydelay_freq_mhz = (uint8)((BCLK__BUS_CLK__HZ + 999999u) / 1000000u);\r
+uint32 cydelay_32k_ms = 32768u * ((BCLK__BUS_CLK__HZ + 999u) / 1000u);\r
+\r
+\r
+/* Function Prototypes */\r
+static uint8 CyUSB_PowerOnCheck(void) ;\r
+static void CyIMO_SetTrimValue(uint8 freq) ;\r
+static void CyBusClk_Internal_SetDivider(uint16 divider);\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPLL_OUT_Start\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enables the PLL. Optionally waits for it to become stable.\r
+* Waits at least 250 us or until it is detected that the PLL is stable.\r
+*\r
+* Parameters:\r
+* wait:\r
+* 0: Return immediately after configuration\r
+* 1: Wait for PLL lock or timeout.\r
+*\r
+* Return:\r
+* Status\r
+* CYRET_SUCCESS - Completed successfully\r
+* CYRET_TIMEOUT - Timeout occurred without detecting a stable clock.\r
+* If the input source of the clock is jittery, then the lock indication\r
+* may not occur. However, after the timeout has expired the generated PLL\r
+* clock can still be used.\r
+*\r
+* Side Effects:\r
+* If wait is enabled: This function wses the Fast Time Wheel to time the wait.\r
+* Any other use of the Fast Time Wheel will be stopped during the period of\r
+* this function and then restored. This function also uses the 100 KHz ILO.\r
+* If not enabled, this function will enable the 100 KHz ILO for the period of\r
+* this function.\r
+*\r
+* No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or\r
+* Once Per Second interrupt may be made by interrupt routines during the period\r
+* of this function execution. The current operation of the ILO, Central Time\r
+* Wheel and Once Per Second interrupt are maintained during the operation of\r
+* this function provided the reading of the Power Manager Interrupt Status\r
+* Register is only done using the CyPmReadStatus() function.\r
+*\r
+*******************************************************************************/\r
+cystatus CyPLL_OUT_Start(uint8 wait) \r
+{\r
+ cystatus status = CYRET_SUCCESS;\r
+\r
+ uint8 iloEnableState;\r
+ uint8 pmTwCfg0State;\r
+ uint8 pmTwCfg2State;\r
+\r
+\r
+ /* Enables the PLL circuit */\r
+ CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE;\r
+\r
+ if(wait != 0u)\r
+ {\r
+ /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */\r
+ iloEnableState = SLOWCLK_ILO_CR0;\r
+ pmTwCfg0State = CY_PM_TW_CFG0_REG;\r
+ pmTwCfg2State = CY_PM_TW_CFG2_REG;\r
+\r
+ CyPmFtwSetInterval(CY_CLK_PLL_FTW_INTERVAL);\r
+\r
+ status = CYRET_TIMEOUT;\r
+\r
+\r
+ while(CyPmReadStatus(CY_PM_FTW_INT) != CY_PM_FTW_INT)\r
+ {\r
+ /* Wait for the interrupt status */\r
+ if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))\r
+ {\r
+ if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS))\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+\r
+ /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */\r
+ if(0u == (iloEnableState & ILO_CONTROL_100KHZ_ON))\r
+ {\r
+ CyILO_Stop100K();\r
+ }\r
+ CY_PM_TW_CFG0_REG = pmTwCfg0State;\r
+ CY_PM_TW_CFG2_REG = pmTwCfg2State;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPLL_OUT_Stop\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disables the PLL.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyPLL_OUT_Stop(void) \r
+{\r
+ CY_CLK_PLL_CFG0_REG &= ((uint8)(~CY_CLK_PLL_ENABLE));\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPLL_OUT_SetPQ\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the P and Q dividers and the charge pump current.\r
+* The Frequency Out will be P/Q * Frequency In.\r
+* The PLL must be disabled before calling this function.\r
+*\r
+* Parameters:\r
+* uint8 pDiv:\r
+* Valid range [8 - 255].\r
+*\r
+* uint8 qDiv:\r
+* Valid range [1 - 16]. Input Frequency / Q must be in range of 1 to 3 MHz.\r
+\r
+* uint8 current:\r
+* Valid range [1 - 7]. Charge pump current in uA. Refer to the device TRM and\r
+* datasheet for more information.\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Side Effects:\r
+* If as result of this function execution the CPU clock frequency is increased\r
+* then the number of clock cycles the cache will wait before it samples data\r
+* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with appropriate parameter. It can be optionally called if CPU clock\r
+* frequency is lowered in order to improve CPU performance.\r
+* See CyFlash_SetWaitCycles() description for more information.\r
+*\r
+*******************************************************************************/\r
+void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) \r
+{\r
+ /* Halt CPU in debug mode if PLL is enabled */\r
+ CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE));\r
+\r
+ if((pDiv >= CY_CLK_PLL_MIN_P_VALUE ) &&\r
+ (qDiv <= CY_CLK_PLL_MAX_Q_VALUE ) && (qDiv >= CY_CLK_PLL_MIN_Q_VALUE ) &&\r
+ (current >= CY_CLK_PLL_MIN_CUR_VALUE) && (current <= CY_CLK_PLL_MAX_CUR_VALUE))\r
+ {\r
+ /* Set new values */\r
+ CY_CLK_PLL_P_REG = pDiv;\r
+ CY_CLK_PLL_Q_REG = ((uint8)(qDiv - 1u));\r
+ CY_CLK_PLL_CFG1_REG = (CY_CLK_PLL_CFG1_REG & CY_CLK_PLL_CURRENT_MASK) |\r
+ ((uint8)(((uint8)(current - 1u)) << CY_CLK_PLL_CURRENT_POSITION));\r
+ }\r
+ else\r
+ {\r
+ /***********************************************************************\r
+ * Halt CPU in debug mode if:\r
+ * - P divider is less than required\r
+ * - Q divider is out of range\r
+ * - pump current is out of range\r
+ ***********************************************************************/\r
+ CYASSERT(0u != 0u);\r
+ }\r
+\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPLL_OUT_SetSource\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the input clock source to the PLL. The PLL must be disabled before\r
+* calling this function.\r
+*\r
+* Parameters:\r
+* source: One of the three available PLL clock sources\r
+* 0 : IMO\r
+* 1 : MHz Crystal\r
+* 2 : DSI\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Side Effects:\r
+* If as result of this function execution the CPU clock frequency is increased\r
+* then the number of clock cycles the cache will wait before it samples data\r
+* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with appropriate parameter. It can be optionally called if CPU clock\r
+* frequency is lowered in order to improve CPU performance.\r
+* See CyFlash_SetWaitCycles() description for more information.\r
+*\r
+*******************************************************************************/\r
+void CyPLL_OUT_SetSource(uint8 source) \r
+{\r
+ /* Halt CPU in debug mode if PLL is enabled */\r
+ CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE));\r
+\r
+ switch(source)\r
+ {\r
+ case CY_PLL_SOURCE_IMO:\r
+ case CY_PLL_SOURCE_XTAL:\r
+ case CY_PLL_SOURCE_DSI:\r
+ CY_LIB_CLKDIST_CR_REG = ((CY_LIB_CLKDIST_CR_REG & CY_LIB_CLKDIST_CR_PLL_SCR_MASK) | source);\r
+ break;\r
+\r
+ default:\r
+ CYASSERT(0u != 0u);\r
+ break;\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyIMO_Start\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enables the IMO. Optionally waits at least 6 us for it to settle.\r
+*\r
+* Parameters:\r
+* uint8 wait:\r
+* 0: Return immediately after configuration\r
+* 1: Wait for at least 6 us for the IMO to settle.\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Side Effects:\r
+* If wait is enabled: This function wses the Fast Time Wheel to time the wait.\r
+* Any other use of the Fast Time Wheel will be stopped during the period of\r
+* this function and then restored. This function also uses the 100 KHz ILO.\r
+* If not enabled, this function will enable the 100 KHz ILO for the period of\r
+* this function.\r
+*\r
+* No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or\r
+* Once Per Second interrupt may be made by interrupt routines during the period\r
+* of this function execution. The current operation of the ILO, Central Time\r
+* Wheel and Once Per Second interrupt are maintained during the operation of\r
+* this function provided the reading of the Power Manager Interrupt Status\r
+* Register is only done using the CyPmReadStatus() function.\r
+*\r
+*******************************************************************************/\r
+void CyIMO_Start(uint8 wait) \r
+{\r
+ uint8 pmFtwCfg2Reg;\r
+ uint8 pmFtwCfg0Reg;\r
+ uint8 iloControlReg;\r
+\r
+ /* Set the bit to enable the clock. */\r
+ PM_ACT_CFG0 |= IMO_PM_ENABLE;\r
+\r
+ /* Wait for 6 us */\r
+ if(0u != wait)\r
+ {\r
+ /* Need to turn on the 100KHz ILO if it happens to not already be running.*/\r
+ iloControlReg = SLOWCLK_ILO_CR0;\r
+\r
+ if(0u == (iloControlReg & ILO_CONTROL_100KHZ_ON))\r
+ {\r
+ CyILO_Start100K();\r
+ }\r
+\r
+ /* Use ILO 100 KHz */\r
+ pmFtwCfg2Reg = PM_TW_CFG2;\r
+ pmFtwCfg0Reg = PM_TW_CFG0;\r
+\r
+ /* FTW_EN (bit 0) must be clear to change the period*/\r
+ PM_TW_CFG2 &= FTW_CLEAR_FTW_BITS;\r
+\r
+ /* Set the FTW interval of 1 100KHz ILO clocks\r
+ Should result in status getting set at a (100/1)KHz rate*/\r
+ PM_TW_CFG0 = 0u;\r
+\r
+ /* Enable FTW, but not the interrupt */\r
+ PM_TW_CFG2 = FTW_ENABLE;\r
+\r
+ /* Read FTW value */\r
+ while (CyPmReadStatus(CY_PM_FTW_INT) == 0u)\r
+ {\r
+ /* Wait for the interrupt status */\r
+ }\r
+\r
+ /* Reset the clock */\r
+ if(0u == (iloControlReg & ILO_CONTROL_100KHZ_ON))\r
+ {\r
+ CyILO_Stop100K();\r
+ }\r
+\r
+ /* Restore the FTW */\r
+ PM_TW_CFG0 = pmFtwCfg0Reg;\r
+ PM_TW_CFG2 = pmFtwCfg2Reg;\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyIMO_Stop\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disables the IMO.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyIMO_Stop(void) \r
+{\r
+ /* Clear the bit to disable the clock. */\r
+ PM_ACT_CFG0 &= ((uint8)(~IMO_PM_ENABLE));\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyUSB_PowerOnCheck\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Returns the USB power status value. A private function to cy_boot.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* uint8: one if the USB is enabled, 0 if not enabled.\r
+*\r
+*******************************************************************************/\r
+static uint8 CyUSB_PowerOnCheck(void) \r
+{\r
+ uint8 poweredOn = 0u;\r
+\r
+ /* Check whether device is in Active or AltActiv and if USB is powered on */\r
+ if((((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ACTIVE ) &&\r
+ (0u != (CY_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED ))) ||\r
+ (((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ALT_ACT) &&\r
+ (0u != (CY_PM_STBY_CFG5_REG & CY_ALT_ACT_USB_ENABLED))))\r
+ {\r
+ poweredOn = 1u;\r
+ }\r
+\r
+ return (poweredOn);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyIMO_SetTrimValue\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the IMO factory trim values.\r
+*\r
+* Parameters:\r
+* uint8 freq - frequency for which trims must be set\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+static void CyIMO_SetTrimValue(uint8 freq) \r
+{\r
+ uint8 usb_power_on = CyUSB_PowerOnCheck();\r
+\r
+ /* If USB is powered */\r
+ if(usb_power_on == 1u)\r
+ {\r
+ /* Unlock USB write */\r
+ CY_USB_CR1 &= ((uint8)(~CLOCK_USB_ENABLE));\r
+ }\r
+ switch(freq)\r
+ {\r
+ case CY_IMO_FREQ_3MHZ:\r
+ IMO_TR1 = CY_GET_XTND_REG8(FLSHID_CUST_TABLES_IMO_3MHZ_PTR);\r
+ break;\r
+\r
+ case CY_IMO_FREQ_6MHZ:\r
+ IMO_TR1 = CY_GET_XTND_REG8(FLSHID_CUST_TABLES_IMO_6MHZ_PTR);\r
+ break;\r
+\r
+ case CY_IMO_FREQ_12MHZ:\r
+ IMO_TR1 = CY_GET_XTND_REG8(FLSHID_CUST_TABLES_IMO_12MHZ_PTR);\r
+ break;\r
+\r
+ case CY_IMO_FREQ_24MHZ:\r
+ IMO_TR1 = CY_GET_XTND_REG8(FLSHID_CUST_TABLES_IMO_24MHZ_PTR);\r
+ break;\r
+\r
+ case CY_IMO_FREQ_48MHZ:\r
+ IMO_TR1 = CY_GET_XTND_REG8(FLSHID_MFG_CFG_IMO_TR1_PTR);\r
+ break;\r
+\r
+ /* The IMO frequencies above 48 MHz are not supported by PSoC5 */\r
+ #if(!CY_PSOC5A)\r
+\r
+ case CY_IMO_FREQ_62MHZ:\r
+ IMO_TR1 = CY_GET_XTND_REG8(FLSHID_CUST_TABLES_IMO_67MHZ_PTR);\r
+ break;\r
+\r
+ #endif /* (!CY_PSOC5A) */\r
+\r
+ case CY_IMO_FREQ_USB:\r
+ IMO_TR1 = CY_GET_XTND_REG8(FLSHID_CUST_TABLES_IMO_USB_PTR);\r
+\r
+ /* If USB is powered */\r
+ if(usb_power_on == 1u)\r
+ {\r
+ /* Lock the USB Oscillator */\r
+ CY_USB_CR1 |= CLOCK_USB_ENABLE;\r
+ }\r
+ break;\r
+\r
+ default:\r
+ CYASSERT(0u != 0u);\r
+ break;\r
+ }\r
+\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyIMO_SetFreq\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the frequency of the IMO. Changes may be made while the IMO is running.\r
+*\r
+* Parameters:\r
+* freq: Frequency of IMO operation\r
+* CY_IMO_FREQ_3MHZ to set 3 MHz\r
+* CY_IMO_FREQ_6MHZ to set 6 MHz\r
+* CY_IMO_FREQ_12MHZ to set 12 MHz\r
+* CY_IMO_FREQ_24MHZ to set 24 MHz\r
+* CY_IMO_FREQ_48MHZ to set 48 MHz\r
+* CY_IMO_FREQ_62MHZ to set 62 MHz (unsupported by PSoC 5)\r
+* CY_IMO_FREQ_USB to set 24 MHz (Trimmed for USB operation)\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Side Effects:\r
+* If as result of this function execution the CPU clock frequency is increased\r
+* then the number of clock cycles the cache will wait before it samples data\r
+* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with appropriate parameter. It can be optionally called if CPU clock\r
+* frequency is lowered in order to improve CPU performance.\r
+* See CyFlash_SetWaitCycles() description for more information.\r
+*\r
+* When the USB setting is chosen, the USB clock locking circuit is enabled.\r
+* Otherwise this circuit is disabled. The USB block must be powered before\r
+* selecting the USB setting.\r
+*\r
+*******************************************************************************/\r
+void CyIMO_SetFreq(uint8 freq) \r
+{\r
+ uint8 currentFreq;\r
+ uint8 nextFreq;\r
+\r
+ /***************************************************************************\r
+ * When changing the IMO frequency the Trim values must also be set\r
+ * accordingly.This requires reading the current frequency. If the new\r
+ * frequency is faster, then set the new trim and then change the frequency,\r
+ * otherwise change the frequency and then set the new trim values.\r
+ ***************************************************************************/\r
+\r
+ currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK));\r
+\r
+ /* Check if the requested frequency is USB. */\r
+ nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq;\r
+\r
+ switch (currentFreq)\r
+ {\r
+ case 0u:\r
+ currentFreq = CY_IMO_FREQ_12MHZ;\r
+ break;\r
+\r
+ case 1u:\r
+ currentFreq = CY_IMO_FREQ_6MHZ;\r
+ break;\r
+\r
+ case 2u:\r
+ currentFreq = CY_IMO_FREQ_24MHZ;\r
+ break;\r
+\r
+ case 3u:\r
+ currentFreq = CY_IMO_FREQ_3MHZ;\r
+ break;\r
+\r
+ case 4u:\r
+ currentFreq = CY_IMO_FREQ_48MHZ;\r
+ break;\r
+\r
+ /* The IMO frequencies above 48 MHz are not supported by PSoC5 */\r
+ #if(!CY_PSOC5A)\r
+\r
+ case 5u:\r
+ currentFreq = CY_IMO_FREQ_62MHZ;\r
+ break;\r
+\r
+ #endif /* (!CY_PSOC5A) */\r
+\r
+ default:\r
+ CYASSERT(0u != 0u);\r
+ break;\r
+ }\r
+\r
+ if (nextFreq >= currentFreq)\r
+ {\r
+ /* Set the new trim first */\r
+ CyIMO_SetTrimValue(freq);\r
+ }\r
+\r
+ /* Set the usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */\r
+ switch(freq)\r
+ {\r
+ case CY_IMO_FREQ_3MHZ:\r
+ CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |\r
+ CLOCK_IMO_3MHZ_VALUE) & ((uint8)(~FASTCLK_IMO_USBCLK_ON_SET));\r
+ break;\r
+\r
+ case CY_IMO_FREQ_6MHZ:\r
+ CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |\r
+ CLOCK_IMO_6MHZ_VALUE) & ((uint8)(~FASTCLK_IMO_USBCLK_ON_SET));\r
+ break;\r
+\r
+ case CY_IMO_FREQ_12MHZ:\r
+ CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |\r
+ CLOCK_IMO_12MHZ_VALUE) & ((uint8)(~FASTCLK_IMO_USBCLK_ON_SET));\r
+ break;\r
+\r
+ case CY_IMO_FREQ_24MHZ:\r
+ CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |\r
+ CLOCK_IMO_24MHZ_VALUE) & ((uint8)(~FASTCLK_IMO_USBCLK_ON_SET));\r
+ break;\r
+\r
+ case CY_IMO_FREQ_48MHZ:\r
+ CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |\r
+ CLOCK_IMO_48MHZ_VALUE) & ((uint8)(~FASTCLK_IMO_USBCLK_ON_SET));\r
+ break;\r
+\r
+ /* The IMO frequencies above 48 MHz are not supported by PSoC5 */\r
+ #if(!CY_PSOC5A)\r
+\r
+ case CY_IMO_FREQ_62MHZ:\r
+ CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |\r
+ CLOCK_IMO_62MHZ_VALUE) & ((uint8)(~FASTCLK_IMO_USBCLK_ON_SET));\r
+ break;\r
+\r
+ #endif /* (!CY_PSOC5A) */\r
+\r
+ case CY_IMO_FREQ_USB:\r
+ CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) |\r
+ CLOCK_IMO_24MHZ_VALUE) | FASTCLK_IMO_USBCLK_ON_SET;\r
+ break;\r
+\r
+ default:\r
+ CYASSERT(0u != 0u);\r
+ break;\r
+ }\r
+\r
+ /* Turn on the IMO Doubler, if switching to CY_IMO_FREQ_USB */\r
+ if (freq == CY_IMO_FREQ_USB)\r
+ {\r
+ CyIMO_EnableDoubler();\r
+ }\r
+ else\r
+ {\r
+ CyIMO_DisableDoubler();\r
+ }\r
+\r
+ if (nextFreq < currentFreq)\r
+ {\r
+ /* Set the new trim after setting the frequency */\r
+ CyIMO_SetTrimValue(freq);\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyIMO_SetSource\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the source of the clock output from the IMO block.\r
+*\r
+* The output from the IMO is by default the IMO itself. Optionally the MHz\r
+* Crystal or a DSI input can be the source of the IMO output instead.\r
+*\r
+* Parameters:\r
+* source, CY_IMO_SOURCE_DSI to set the DSI as source.\r
+* CY_IMO_SOURCE_XTAL to set the MHz as source.\r
+* CY_IMO_SOURCE_IMO to set the IMO itself.\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Side Effects:\r
+* If as result of this function execution the CPU clock frequency is increased\r
+* then the number of clock cycles the cache will wait before it samples data\r
+* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with appropriate parameter. It can be optionally called if CPU clock\r
+* frequency is lowered in order to improve CPU performance.\r
+* See CyFlash_SetWaitCycles() description for more information.\r
+*\r
+*******************************************************************************/\r
+void CyIMO_SetSource(uint8 source) \r
+{\r
+ switch(source)\r
+ {\r
+ case CY_IMO_SOURCE_DSI:\r
+ CY_LIB_CLKDIST_CR_REG &= ((uint8)(~CY_LIB_CLKDIST_CR_IMO2X));\r
+ CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO;\r
+ break;\r
+\r
+ case CY_IMO_SOURCE_XTAL:\r
+ CY_LIB_CLKDIST_CR_REG |= CY_LIB_CLKDIST_CR_IMO2X;\r
+ CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO;\r
+ break;\r
+\r
+ case CY_IMO_SOURCE_IMO:\r
+ CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_IMO));\r
+ break;\r
+\r
+ default:\r
+ /* Incorrect source value */\r
+ CYASSERT(0u != 0u);\r
+ break;\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyIMO_EnableDoubler\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enables the IMO doubler. The 2x frequency clock is used to convert a 24 MHz\r
+* input to a 48 MHz output for use by the USB block.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyIMO_EnableDoubler(void) \r
+{\r
+ /* Set the FASTCLK_IMO_CR_PTR regigster's 4th bit */\r
+ CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyIMO_DisableDoubler\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disables the IMO doubler.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyIMO_DisableDoubler(void) \r
+{\r
+ CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_DOUBLER));\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyMasterClk_SetSource\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the source of the master clock.\r
+*\r
+* Parameters:\r
+* source: One of the four available Master clock sources.\r
+* CY_MASTER_SOURCE_IMO\r
+* CY_MASTER_SOURCE_PLL\r
+* CY_MASTER_SOURCE_XTAL\r
+* CY_MASTER_SOURCE_DSI\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Side Effects:\r
+* The current source and the new source must both be running and stable before\r
+* calling this function.\r
+*\r
+* If as result of this function execution the CPU clock frequency is increased\r
+* then the number of clock cycles the cache will wait before it samples data\r
+* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with appropriate parameter. It can be optionally called if CPU clock\r
+* frequency is lowered in order to improve CPU performance.\r
+* See CyFlash_SetWaitCycles() description for more information.\r
+*\r
+*******************************************************************************/\r
+void CyMasterClk_SetSource(uint8 source) \r
+{\r
+ #if(CY_PSOC5A)\r
+\r
+ uint8 masterReg0;\r
+\r
+ /* Read the current setting */\r
+ masterReg0 = CY_LIB_CLKDIST_MSTR0_REG;\r
+\r
+ /* Write a non-zero period to the master mux clock divider */\r
+ if (masterReg0 == 0x00u)\r
+ {\r
+ CY_LIB_CLKDIST_MSTR0_REG = 3u;\r
+ }\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+ CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & MASTER_CLK_SRC_CLEAR) |\r
+ (source & ((uint8)(~MASTER_CLK_SRC_CLEAR)));\r
+\r
+ #if(CY_PSOC5A)\r
+\r
+ /* Restore zero period (if desired) to the master mux clock divider */\r
+ if (masterReg0 == 0x00u)\r
+ {\r
+ CY_LIB_CLKDIST_MSTR0_REG = 0u;\r
+ }\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyMasterClk_SetDivider\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the divider value used to generate Master Clock.\r
+*\r
+* Parameters:\r
+* uint8 divider:\r
+* Valid range [0-255]. The clock will be divided by this value + 1.\r
+* For example to divide by 2 this parameter should be set to 1.\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Side Effects:\r
+* If as result of this function execution the CPU clock frequency is increased\r
+* then the number of clock cycles the cache will wait before it samples data\r
+* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with appropriate parameter. It can be optionally called if CPU clock\r
+* frequency is lowered in order to improve CPU performance.\r
+* See CyFlash_SetWaitCycles() description for more information.\r
+*\r
+* When changing the Master or Bus clock divider value from div-by-n to div-by-1\r
+* the first clock cycle output after the div-by-1 can be up to 4 ns shorter\r
+* than the final/expected div-by-1 period.\r
+*\r
+*******************************************************************************/\r
+void CyMasterClk_SetDivider(uint8 divider) \r
+{\r
+ CY_LIB_CLKDIST_MSTR0_REG = divider;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyBusClk_Internal_SetDivider\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Function used by CyBusClk_SetDivider(). For internal use only.\r
+*\r
+* Parameters:\r
+* divider: Valid range [0-65535].\r
+* The clock will be divided by this value + 1.\r
+* For example to divide by 2 this parameter should be set to 1.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+static void CyBusClk_Internal_SetDivider(uint16 divider)\r
+{\r
+ /* Mask bits to enable shadow loads */\r
+ CY_LIB_CLKDIST_AMASK_REG &= CY_LIB_CLKDIST_AMASK_MASK;\r
+ CY_LIB_CLKDIST_DMASK_REG = CY_LIB_CLKDIST_DMASK_MASK;\r
+\r
+ /* Enable mask bits to enable shadow loads */\r
+ CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK;\r
+\r
+ /* Update Shadow Divider Value Register with the new divider */\r
+ CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider);\r
+ CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider);\r
+\r
+\r
+ /***************************************************************************\r
+ * Copy shadow value defined in Shadow Divider Value Register\r
+ * (CY_LIB_CLKDIST_WRK_LSB_REG and CY_LIB_CLKDIST_WRK_MSB_REG) to all\r
+ * dividers selected in Analog and Digital Clock Mask Registers\r
+ * (CY_LIB_CLKDIST_AMASK_REG and CY_LIB_CLKDIST_DMASK_REG).\r
+ ***************************************************************************/\r
+ CY_LIB_CLKDIST_LD_REG |= CY_LIB_CLKDIST_LD_LOAD;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyBusClk_SetDivider\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the divider value used to generate Bus Clock.\r
+*\r
+* Parameters:\r
+* divider: Valid range [0-65535]. The clock will be divided by this value + 1.\r
+* For example to divide by 2 this parameter should be set to 1.\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Side Effects:\r
+* If as result of this function execution the CPU clock frequency is increased\r
+* then the number of clock cycles the cache will wait before it samples data\r
+* coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+* with appropriate parameter. It can be optionally called if CPU clock\r
+* frequency is lowered in order to improve CPU performance.\r
+* See CyFlash_SetWaitCycles() description for more information.\r
+*\r
+*******************************************************************************/\r
+void CyBusClk_SetDivider(uint16 divider) \r
+{\r
+ uint8 masterClkDiv;\r
+ uint16 busClkDiv;\r
+ uint8 interruptState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ /* Work around to set the bus clock divider value */\r
+ busClkDiv = ((uint16)(((uint16)(CY_LIB_CLKDIST_BCFG_MSB_REG)) << 8u)) | CY_LIB_CLKDIST_BCFG_LSB_REG;\r
+\r
+ if ((divider == 0u) || (busClkDiv == 0u))\r
+ {\r
+ /* Save away the master clock divider value */\r
+ masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG;\r
+\r
+ if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV)\r
+ {\r
+ /* Set master clock divider to 7 */\r
+ CyMasterClk_SetDivider(CY_LIB_CLKDIST_MASTERCLK_DIV);\r
+ }\r
+\r
+ if (divider == 0u)\r
+ {\r
+ /* Set the SSS bit and the divider register desired value */\r
+ CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS;\r
+ CyBusClk_Internal_SetDivider(divider);\r
+ }\r
+ else\r
+ {\r
+ CyBusClk_Internal_SetDivider(divider);\r
+ CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS));\r
+ }\r
+\r
+ /* Restore the master clock */\r
+ CyMasterClk_SetDivider(masterClkDiv);\r
+ }\r
+ else\r
+ {\r
+ CyBusClk_Internal_SetDivider(divider);\r
+ }\r
+\r
+ CyExitCriticalSection(interruptState);\r
+}\r
+\r
+\r
+#if(CY_PSOC3)\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyCpuClk_SetDivider\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Sets the divider value used to generate the CPU Clock. Only applicable for\r
+ * PSoC 3 parts.\r
+ *\r
+ * Parameters:\r
+ * divider: Valid range [0-15]. The clock will be divided by this value + 1.\r
+ * For example to divide by 2 this parameter should be set to 1.\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * If as result of this function execution the CPU clock frequency is increased\r
+ * then the number of clock cycles the cache will wait before it samples data\r
+ * coming back from Flash must be adjusted by calling CyFlash_SetWaitCycles()\r
+ * with appropriate parameter. It can be optionally called if CPU clock\r
+ * frequency is lowered in order to improve CPU performance.\r
+ * See CyFlash_SetWaitCycles() description for more information.\r
+ *\r
+ *******************************************************************************/\r
+ void CyCpuClk_SetDivider(uint8 divider) \r
+ {\r
+ CLKDIST_MSTR1 = (CLKDIST_MSTR1 & CLKDIST_MSTR1_DIV_CLEAR) |\r
+ ((uint8)(divider << CLKDIST_DIV_POSITION));\r
+ }\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyUsbClk_SetSource\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the source of the USB clock.\r
+*\r
+* Parameters:\r
+* source: One of the four available USB clock sources\r
+* USB_CLK_IMO2X - IMO 2x\r
+* USB_CLK_IMO - IMO\r
+* USB_CLK_PLL - PLL\r
+* USB_CLK_DSI - DSI\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyUsbClk_SetSource(uint8 source) \r
+{\r
+ CLKDIST_UCFG = (CLKDIST_UCFG & ((uint8)(~USB_CLKDIST_CONFIG_MASK))) |\r
+ (USB_CLKDIST_CONFIG_MASK & source);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyILO_Start1K\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enables the ILO 1 KHz oscillator.\r
+*\r
+* Note The ILO 1 KHz oscillator is always enabled by default, regardless of the\r
+* selection in the Clock Editor. Therefore, this API is only needed if the\r
+* oscillator was turned off manually.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyILO_Start1K(void) \r
+{\r
+ /* Set the bit 1 of ILO RS */\r
+ SLOWCLK_ILO_CR0 |= ILO_CONTROL_1KHZ_ON;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyILO_Stop1K\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disables the ILO 1 KHz oscillator.\r
+*\r
+* Note The ILO 1 KHz oscillator must be enabled if Sleep or Hibernate low power\r
+* mode APIs are expected to be used. For more information, refer to the Power\r
+* Management section of this document.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Side Effects:\r
+* PSoC5: Stopping the ILO 1 kHz could break the active WDT functionality.\r
+*\r
+*******************************************************************************/\r
+void CyILO_Stop1K(void) \r
+{\r
+ /* Clear the bit 1 of ILO RS */\r
+ SLOWCLK_ILO_CR0 &= ((uint8)(~ILO_CONTROL_1KHZ_ON));\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyILO_Start100K\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enables the ILO 100 KHz oscillator.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyILO_Start100K(void) \r
+{\r
+ /* Set the bit 2 of ILO RS */\r
+ SLOWCLK_ILO_CR0 |= ILO_CONTROL_100KHZ_ON;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyILO_Stop100K\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disables the ILO 100 KHz oscillator.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyILO_Stop100K(void) \r
+{\r
+ /* Clear the bit 2 of ILO RS */\r
+ SLOWCLK_ILO_CR0 &= ((uint8)(~ILO_CONTROL_100KHZ_ON));\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyILO_Enable33K\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enables the ILO 33 KHz divider.\r
+*\r
+* Note that the 33 KHz clock is generated from the 100 KHz oscillator,\r
+* so it must also be running in order to generate the 33 KHz output.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyILO_Enable33K(void) \r
+{\r
+ /* Set the bit 5 of ILO RS */\r
+ SLOWCLK_ILO_CR0 |= ILO_CONTROL_33KHZ_ON;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyILO_Disable33K\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disables the ILO 33 KHz divider.\r
+*\r
+* Note that the 33 KHz clock is generated from the 100 KHz oscillator, but this\r
+* API does not disable the 100 KHz clock.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyILO_Disable33K(void) \r
+{\r
+ /* Clear the bit 5 of ILO RS */\r
+ SLOWCLK_ILO_CR0 &= ((uint8)(~ILO_CONTROL_33KHZ_ON));\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyILO_SetSource\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the source of the clock output from the ILO block.\r
+*\r
+* Parameters:\r
+* source: One of the three available ILO output sources\r
+* Value Define Source\r
+* 0 CY_ILO_SOURCE_100K ILO 100 KHz\r
+* 1 CY_ILO_SOURCE_33K ILO 33 KHz\r
+* 2 CY_ILO_SOURCE_1K ILO 1 KHz\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyILO_SetSource(uint8 source) \r
+{\r
+ CLKDIST_CR = (CLKDIST_CR & CY_ILO_SOURCE_BITS_CLEAR) |\r
+ (((uint8) (source << 2u)) & ((uint8)(~CY_ILO_SOURCE_BITS_CLEAR)));\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyILO_SetPowerMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the power mode used by the ILO during power down. Allows for lower power\r
+* down power usage resulting in a slower startup time.\r
+*\r
+* Parameters:\r
+* uint8 mode\r
+* CY_ILO_FAST_START - Faster start-up, internal bias left on when powered down\r
+* CY_ILO_SLOW_START - Slower start-up, internal bias off when powered down\r
+*\r
+* Return:\r
+* Prevous power mode state.\r
+*\r
+*******************************************************************************/\r
+uint8 CyILO_SetPowerMode(uint8 mode) \r
+{\r
+ uint8 state;\r
+\r
+ /* Get current state. */\r
+ state = SLOWCLK_ILO_CR0;\r
+\r
+ /* Set the the oscillator power mode. */\r
+ if(mode != CY_ILO_FAST_START)\r
+ {\r
+ SLOWCLK_ILO_CR0 = (state | ILO_CONTROL_PD_MODE);\r
+ }\r
+ else\r
+ {\r
+ SLOWCLK_ILO_CR0 = (state & ((uint8)(~ILO_CONTROL_PD_MODE)));\r
+ }\r
+\r
+ /* Return the old mode. */\r
+ return ((state & ILO_CONTROL_PD_MODE) >> ILO_CONTROL_PD_POSITION);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyXTAL_32KHZ_Start\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enables the 32 KHz Crystal Oscillator.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyXTAL_32KHZ_Start(void) \r
+{\r
+ volatile uint16 i;\r
+\r
+ CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT;\r
+ CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_STARTUP;\r
+ CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) |\r
+ CY_CLK_XTAL32_CFG_LP_DEFAULT;\r
+\r
+ #if(CY_PSOC3)\r
+ CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN;\r
+ #endif /* (CY_PSOC3) */\r
+\r
+ /* Enable operation of the 32K Crystal Oscillator */\r
+ CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN;\r
+\r
+ for (i = 1000u; i > 0u; i--)\r
+ {\r
+ if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT))\r
+ {\r
+ /* Ready - switch to the hign power mode */\r
+ (void) CyXTAL_32KHZ_SetPowerMode(0u);\r
+\r
+ break;\r
+ }\r
+ CyDelayUs(1u);\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyXTAL_32KHZ_Stop\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disables the 32KHz Crystal Oscillator.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyXTAL_32KHZ_Stop(void) \r
+{\r
+ CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT;\r
+ CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_POWERDOWN;\r
+ CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | CY_CLK_XTAL32_CFG_LP_DEFAULT;\r
+ CY_CLK_XTAL32_CR_REG &= ((uint8)(~(CY_CLK_XTAL32_CR_EN | CY_CLK_XTAL32_CR_LPM)));\r
+\r
+ #if(CY_PSOC3)\r
+ CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_PDBEN));\r
+ #endif /* (CY_PSOC3) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyXTAL_32KHZ_ReadStatus\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Returns status of the 32 KHz oscillator.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* Value Define Source\r
+* 20 CY_XTAL32K_ANA_STAT Analog measurement\r
+* 1: Stable\r
+* 0: Not stable\r
+*\r
+*******************************************************************************/\r
+uint8 CyXTAL_32KHZ_ReadStatus(void) \r
+{\r
+ return(CY_CLK_XTAL32_CR_REG & CY_XTAL32K_ANA_STAT);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyXTAL_32KHZ_SetPowerMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the power mode for the 32 KHz oscillator used during sleep mode.\r
+* Allows for lower power during sleep when there are fewer sources of noise.\r
+* During active mode the oscillator is always run in high power mode.\r
+*\r
+* Parameters:\r
+* uint8 mode\r
+* 0: High power mode\r
+* 1: Low power mode during sleep\r
+*\r
+* Return:\r
+* Previous power mode.\r
+*\r
+*******************************************************************************/\r
+uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) \r
+{\r
+ uint8 state = (0u != (CY_CLK_XTAL32_CR_REG & CY_CLK_XTAL32_CR_LPM)) ? 1u : 0u;\r
+\r
+ CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT;\r
+\r
+ if(1u == mode)\r
+ {\r
+ /* Low power mode during Sleep */\r
+ CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_LOW_POWER;\r
+ CyDelayUs(10u);\r
+ CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | CY_CLK_XTAL32_CFG_LP_LOWPOWER;\r
+ CyDelayUs(20u);\r
+ CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_LPM;\r
+ }\r
+ else\r
+ {\r
+ /* High power mode */\r
+ CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_HIGH_POWER;\r
+ CyDelayUs(10u);\r
+ CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | CY_CLK_XTAL32_CFG_LP_DEFAULT;\r
+ CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_LPM));\r
+ }\r
+\r
+ return(state);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyXTAL_Start\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enables the megahertz crystal.\r
+*\r
+* PSoC3:\r
+* Waits until the XERR bit is low (no error) for a millisecond or until the\r
+* number of milliseconds specified by the wait parameter has expired.\r
+*\r
+* PSoC5:\r
+* Waits for CY_CLK_XMHZ_MIN_TIMEOUT milliseconds (or number of milliseconds\r
+* specified by parameter if it is greater than CY_CLK_XMHZ_MIN_TIMEOUT. The\r
+* XERR bit status is not checked.\r
+*\r
+* Parameters:\r
+* wait: Valid range [0-255].\r
+* This is the timeout value in milliseconds.\r
+* The appropriate value is crystal specific.\r
+*\r
+* Return:\r
+* CYRET_SUCCESS - Completed successfully\r
+* CYRET_TIMEOUT - Timeout occurred without detecting a low value on XERR.\r
+*\r
+* Side Effects and Restrictions:\r
+* If wait is enabled (non-zero wait). Uses the Fast Timewheel to time the wait.\r
+* Any other use of the Fast Timewheel (FTW) will be stopped during the period\r
+* of this function and then restored.\r
+*\r
+* Uses the 100KHz ILO. If not enabled, this function will enable the 100KHz\r
+* ILO for the period of this function. No changes to the setup of the ILO,\r
+* Fast Timewheel, Central Timewheel or Once Per Second interrupt may be made\r
+* by interrupt routines during the period of this function.\r
+*\r
+* The current operation of the ILO, Central Timewheel and Once Per Second\r
+* interrupt are maintained during the operation of this function provided the\r
+* reading of the Power Manager Interrupt Status Register is only done using the\r
+* CyPmReadStatus() function.\r
+*\r
+*******************************************************************************/\r
+cystatus CyXTAL_Start(uint8 wait) \r
+{\r
+ cystatus status = CYRET_SUCCESS;\r
+\r
+ #if(CY_PSOC5A)\r
+ volatile uint8 timeout = (wait < CY_CLK_XMHZ_MIN_TIMEOUT) ? CY_CLK_XMHZ_MIN_TIMEOUT : wait;\r
+ #else\r
+ volatile uint8 timeout = wait;\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+ volatile uint8 count;\r
+ uint8 iloEnableState;\r
+ uint8 pmTwCfg0Tmp;\r
+ uint8 pmTwCfg2Tmp;\r
+\r
+\r
+ /* Enables the MHz crystal oscillator circuit */\r
+ CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE;\r
+\r
+\r
+ if(wait > 0u)\r
+ {\r
+ /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */\r
+ iloEnableState = SLOWCLK_ILO_CR0;\r
+ pmTwCfg0Tmp = CY_PM_TW_CFG0_REG;\r
+ pmTwCfg2Tmp = CY_PM_TW_CFG2_REG;\r
+\r
+ /* Set 250 us interval */\r
+ CyPmFtwSetInterval(CY_CLK_XMHZ_FTW_INTERVAL);\r
+ status = CYRET_TIMEOUT;\r
+\r
+\r
+ for( ; timeout > 0u; timeout--)\r
+ {\r
+ #if(!CY_PSOC5A)\r
+\r
+ /* Read XERR bit to clear it */\r
+ (void) CY_CLK_XMHZ_CSR_REG;\r
+\r
+ #endif /* (!CY_PSOC5A) */\r
+\r
+\r
+ /* Wait for a millisecond - 4 x 250 us */\r
+ for(count = 4u; count > 0u; count--)\r
+ {\r
+ while(!(CY_PM_FTW_INT == CyPmReadStatus(CY_PM_FTW_INT)))\r
+ {\r
+ /* Wait for the FTW interrupt event */\r
+ }\r
+ }\r
+\r
+\r
+ #if(!CY_PSOC5A)\r
+\r
+ /*******************************************************************\r
+ * High output indicates oscillator failure.\r
+ * Only can be used after start-up interval (1 ms) is completed.\r
+ *******************************************************************/\r
+ if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR))\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ break;\r
+ }\r
+\r
+ #endif /* (!CY_PSOC5A) */\r
+ }\r
+\r
+\r
+ /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */\r
+ if(0u == (iloEnableState & ILO_CONTROL_100KHZ_ON))\r
+ {\r
+ CyILO_Stop100K();\r
+ }\r
+ CY_PM_TW_CFG0_REG = pmTwCfg0Tmp;\r
+ CY_PM_TW_CFG2_REG = pmTwCfg2Tmp;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyXTAL_Stop\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disables the megahertz crystal oscillator.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyXTAL_Stop(void) \r
+{\r
+ /* Disable the the oscillator. */\r
+ FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE));\r
+}\r
+\r
+\r
+#if(!CY_PSOC5A)\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyXTAL_EnableErrStatus\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Enables the generation of the XERR status bit for the megahertz crystal.\r
+ * This function is not available for PSoC5.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CyXTAL_EnableErrStatus(void) \r
+ {\r
+ /* If oscillator has insufficient amplitude, XERR bit will be high. */\r
+ CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XFB));\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyXTAL_DisableErrStatus\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Disables the generation of the XERR status bit for the megahertz crystal.\r
+ * This function is not available for PSoC5.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CyXTAL_DisableErrStatus(void) \r
+ {\r
+ /* If oscillator has insufficient amplitude, XERR bit will be high. */\r
+ CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XFB;\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyXTAL_ReadStatus\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Reads the XERR status bit for the megahertz crystal. This status bit is a\r
+ * sticky clear on read value. This function is not available for PSoC5.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * Status\r
+ * 0: No error\r
+ * 1: Error\r
+ *\r
+ *******************************************************************************/\r
+ uint8 CyXTAL_ReadStatus(void) \r
+ {\r
+ /***************************************************************************\r
+ * High output indicates oscillator failure. Only use this after start-up\r
+ * interval is completed. This can be used for status and failure recovery.\r
+ ***************************************************************************/\r
+ return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyXTAL_EnableFaultRecovery\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Enables the fault recovery circuit which will switch to the IMO in the case\r
+ * of a fault in the megahertz crystal circuit. The crystal must be up and\r
+ * running with the XERR bit at 0, before calling this function to prevent\r
+ * immediate fault switchover. This function is not available for PSoC5.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CyXTAL_EnableFaultRecovery(void) \r
+ {\r
+ CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XPROT;\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyXTAL_DisableFaultRecovery\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Disables the fault recovery circuit which will switch to the IMO in the case\r
+ * of a fault in the megahertz crystal circuit. This function is not available\r
+ * for PSoC5.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CyXTAL_DisableFaultRecovery(void) \r
+ {\r
+ CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XPROT));\r
+ }\r
+\r
+#endif /* (!CY_PSOC5A) */\r
+\r
+/*******************************************************************************\r
+* Function Name: CyXTAL_SetStartup\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the startup settings for the crystal. Logic model outputs a frequency\r
+* (setting + 4) MHz when enabled.\r
+*\r
+* This is artificial as the actual frequency is determined by an attached\r
+* external crystal.\r
+*\r
+* Parameters:\r
+* setting: Valid range [0-31].\r
+* Value is dependent on the frequency and quality of the crystal being used.\r
+* Refer to the device TRM and datasheet for more information.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyXTAL_SetStartup(uint8 setting) \r
+{\r
+ CY_CLK_XMHZ_CFG0_REG = (CY_CLK_XMHZ_CFG0_REG & ((uint8)(~CY_CLK_XMHZ_CFG0_XCFG_MASK))) |\r
+ (setting & CY_CLK_XMHZ_CFG0_XCFG_MASK);\r
+}\r
+\r
+\r
+#if(CY_PSOC3 || CY_PSOC5LP)\r
+ /*******************************************************************************\r
+ * Function Name: CyXTAL_SetFbVoltage\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Sets the feedback reference voltage to use for the crystal circuit.\r
+ * This function is only available for PSoC3 and PSoC 5LP.\r
+ *\r
+ * Parameters:\r
+ * setting: Valid range [0-15].\r
+ * Refer to the device TRM and datasheet for more information.\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CyXTAL_SetFbVoltage(uint8 setting) \r
+ {\r
+ CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_FB_MASK))) |\r
+ (setting & CY_CLK_XMHZ_CFG1_VREF_FB_MASK));\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyXTAL_SetWdVoltage\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Sets the reference voltage used by the watchdog to detect a failure in the\r
+ * crystal circuit. This function is only available for PSoC3 and PSoC 5LP.\r
+ *\r
+ * Parameters:\r
+ * setting: Valid range [0-7].\r
+ * Refer to the device TRM and datasheet for more information.\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CyXTAL_SetWdVoltage(uint8 setting) \r
+ {\r
+ CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_WD_MASK))) |\r
+ (((uint8)(setting << 4u)) & CY_CLK_XMHZ_CFG1_VREF_WD_MASK));\r
+ }\r
+\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyHalt\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Halts the CPU.\r
+*\r
+* Parameters:\r
+* uint8 reason: Value to be used during debugging.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyHalt(uint8 reason) CYREENTRANT\r
+{\r
+ if(0u != reason)\r
+ {\r
+ /* To remove unreferenced local variable warning */\r
+ }\r
+\r
+ #if defined (__ARMCC_VERSION)\r
+ __breakpoint(0x0);\r
+ #elif defined(__GNUC__)\r
+ __asm(" bkpt 1");\r
+ #elif defined(__C51__)\r
+ CYDEV_HALT_CPU;\r
+ #endif /* (__ARMCC_VERSION) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CySoftwareReset\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Forces a software reset of the device.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CySoftwareReset(void) \r
+{\r
+ /* Perform software reset */\r
+ *RESET_CR2 = 0x1u;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDelay\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Blocks for milliseconds.\r
+*\r
+* Note:\r
+* CyDelay has been implemented with the instruction cache assumed enabled. When\r
+* instruction cache is disabled on PSoC5, CyDelay will be two times larger. For\r
+* example, with instruction cache disabled CyDelay(100) would result in about\r
+* 200 ms delay instead of 100 ms.\r
+*\r
+* Parameters:\r
+* milliseconds: number of milliseconds to delay.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyDelay(uint32 milliseconds) CYREENTRANT\r
+{\r
+ while (milliseconds > 32768u)\r
+ {\r
+ /***********************************************************************\r
+ * This loop prevents overflow.At 100MHz, milliseconds * delay_freq_khz\r
+ * overflows at about 42 seconds.\r
+ ***********************************************************************/\r
+ CyDelayCycles(cydelay_32k_ms);\r
+ milliseconds = ((uint32)(milliseconds - 32768u));\r
+ }\r
+\r
+ CyDelayCycles(milliseconds * cydelay_freq_khz);\r
+}\r
+\r
+\r
+#if(!CY_PSOC3)\r
+\r
+ /* For PSoC3 devices function is defined in CyBootAsmKeil.a51 file */\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyDelayUs\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Blocks for microseconds.\r
+ *\r
+ * Note:\r
+ * CyDelay has been implemented with the instruction cache assumed enabled.\r
+ * When instruction cache is disabled on PSoC5, CyDelayUs will be two times\r
+ * larger. Ex: With instruction cache disabled CyDelayUs(100) would result\r
+ * in about 200us delay instead of 100us.\r
+ *\r
+ * Parameters:\r
+ * uint16 microseconds: number of microseconds to delay.\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Side Effects:\r
+ * CyDelayUS has been implemented with the instruction cache assumed enabled.\r
+ * When instruction cache is disabled on PSoC 5, CyDelayUs will be two times\r
+ * larger. For example, with instruction cache disabled CyDelayUs(100) would\r
+ * result in about 200 us delay instead of 100 us.\r
+ *\r
+ * If the bus clock frequency is a small non-integer number, the actual delay\r
+ * can be up to twice as long as the nominal value. The actual delay cannot be\r
+ * shorter than the nominal one.\r
+ *******************************************************************************/\r
+ void CyDelayUs(uint16 microseconds) CYREENTRANT\r
+ {\r
+ CyDelayCycles((uint32)microseconds * cydelay_freq_mhz);\r
+ }\r
+\r
+#endif /* (!CY_PSOC3) */\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDelayFreq\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets clock frequency for CyDelay.\r
+*\r
+* Parameters:\r
+* freq: Frequency of bus clock in Hertz.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyDelayFreq(uint32 freq) CYREENTRANT\r
+{\r
+ if (freq != 0u)\r
+ {\r
+ cydelay_freq_hz = freq;\r
+ }\r
+ else\r
+ {\r
+ cydelay_freq_hz = BCLK__BUS_CLK__HZ;\r
+ }\r
+\r
+ cydelay_freq_mhz = (uint8)((cydelay_freq_hz + 999999u) / 1000000u);\r
+ cydelay_freq_khz = (cydelay_freq_hz + 999u) / 1000u;\r
+ cydelay_32k_ms = 32768u * cydelay_freq_khz;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyWdtStart\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enables the watchdog timer.\r
+*\r
+* The timer is configured for the specified count interval, the central\r
+* timewheel is cleared, the setting for low power mode is configured and the\r
+* watchdog timer is enabled.\r
+*\r
+* Once enabled the watchdog cannot be disabled. The watchdog counts each time\r
+* the Central Time Wheel (CTW) reaches the period specified. The watchdog must\r
+* be cleared using the CyWdtClear() function before three ticks of the watchdog\r
+* timer occur. The CTW is free running, so this will occur after between 2 and\r
+* 3 timer periods elapse.\r
+*\r
+* PSoC5: The watchdog timer should not be used during sleep modes. Since the\r
+* WDT cannot be disabled after it is enabled, the WDT timeout period can be\r
+* set to be greater than the sleep wakeup period, then feed the dog on each\r
+* wakeup from Sleep.\r
+*\r
+* Parameters:\r
+* ticks: One of the four available timer periods. Once WDT enabled, the\r
+ interval cannot be changed.\r
+* CYWDT_2_TICKS - 4 - 6 ms\r
+* CYWDT_16_TICKS - 32 - 48 ms\r
+* CYWDT_128_TICKS - 256 - 384 ms\r
+* CYWDT_1024_TICKS - 2.048 - 3.072 s\r
+*\r
+* lpMode: Low power mode configuration. This parameter is ignored for PSoC 5.\r
+* The WDT always acts as if CYWDT_LPMODE_NOCHANGE is passed.\r
+*\r
+* CYWDT_LPMODE_NOCHANGE - No Change\r
+* CYWDT_LPMODE_MAXINTER - Switch to longest timer mode during low power\r
+* mode\r
+* CYWDT_LPMODE_DISABLED - Disable WDT during low power mode\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Side Effects:\r
+* PSoC5: The ILO 1 KHz must be enabled for proper WDT operation. Stopping the\r
+* ILO 1 kHz could break the active WDT functionality.\r
+*\r
+*******************************************************************************/\r
+void CyWdtStart(uint8 ticks, uint8 lpMode) \r
+{\r
+ #if(CY_PSOC5A)\r
+ CyILO_Start1K();\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+ /* Set WDT interval */\r
+ CY_WDT_CFG_REG = (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_INTERVAL_MASK))) | (ticks & CY_WDT_CFG_INTERVAL_MASK);\r
+\r
+ /* Reset CTW to ensure that first watchdog period is full */\r
+ CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET;\r
+ CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET));\r
+\r
+ #if(!CY_PSOC5A)\r
+\r
+ /* Setting the low power mode */\r
+ CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) |\r
+ (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK)));\r
+ #else\r
+\r
+ if(0u != lpMode)\r
+ {\r
+ /* To remove unreferenced local variable warning */\r
+ }\r
+\r
+ #endif /* (!CY_PSOC5A) */\r
+\r
+ /* Enables the watchdog reset */\r
+ CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyWdtClear\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Clears (feeds) the watchdog timer.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyWdtClear(void) \r
+{\r
+ #if(CY_PSOC5A)\r
+\r
+ /* PSoC5 ES1 watchdog time clear requires workaround */\r
+ uint8 wdtCfg = CY_WDT_CFG_REG;\r
+ CY_WDT_CR_REG = CY_WDT_CR_FEED;\r
+ CY_WDT_CFG_REG = CY_WDT_CFG_CLEAR_ALL;\r
+ CY_WDT_CFG_REG = wdtCfg;\r
+\r
+ #else\r
+\r
+ CY_WDT_CR_REG = CY_WDT_CR_FEED;\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+}\r
+\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyVdLvDigitEnable\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enables the digital low voltage monitors to generate interrupt on Vddd\r
+* archives specified threshold and optionally resets device.\r
+*\r
+* Parameters:\r
+* reset: Option to reset device at a specified Vddd threshold:\r
+* 0 - Device is not reset.\r
+* 1 - Device is reset.\r
+* This option is applicable for PSoC 3/PSoC 5LP devices only.\r
+*\r
+* threshold: Sets the trip level for the voltage monitor.\r
+* Values from 1.70 V to 5.45 V(for PSoC 3/PSoC 5LP) and from 2.45 V to 5.45 V\r
+* (for PSoC 5TM) are accepted with the approximately 250 mV interval.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyVdLvDigitEnable(uint8 reset, uint8 threshold) \r
+{\r
+ *CY_INT_CLEAR_PTR = 0x01u;\r
+\r
+ #if(!CY_PSOC5A)\r
+ CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));\r
+ #endif /*(!CY_PSOC5A)*/\r
+\r
+ CY_VD_LVI_TRIP_REG = (threshold & CY_VD_LVI_TRIP_LVID_MASK) |\r
+ (CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK)));\r
+ CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN;\r
+\r
+ /* Timeout to eliminate glitches on the LVI/HVI when enabling */\r
+ CyDelayUs(1u);\r
+\r
+ (void)CY_VD_PERSISTENT_STATUS_REG;\r
+\r
+ #if(!CY_PSOC5A)\r
+ if(0u != reset)\r
+ {\r
+ CY_VD_PRES_CONTROL_REG |= CY_VD_PRESD_EN;\r
+ }\r
+ else\r
+ {\r
+ CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));\r
+ }\r
+ #else\r
+\r
+ if(0u != reset)\r
+ {\r
+ /* To remove unreferenced local variable warning */\r
+ }\r
+\r
+ #endif /*(!CY_PSOC5A)*/\r
+\r
+ *CY_INT_CLR_PEND_PTR = 0x01u;\r
+ *CY_INT_ENABLE_PTR = 0x01u;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyVdLvAnalogEnable\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enables the analog low voltage monitors to generate interrupt on Vdda\r
+* archives specified threshold and optionally resets device.\r
+*\r
+* Parameters:\r
+* reset: Option to reset device at a specified Vdda threshold:\r
+* 0 - Device is not reset.\r
+* 1 - Device is reset.\r
+* This option is applicable for PSoC 3/PSoC 5LP devices only.\r
+*\r
+* threshold: Sets the trip level for the voltage monitor.\r
+* Values from 1.70 V to 5.45 V(for PSoC 3/PSoC 5LP) and from 2.45 V to 5.45 V\r
+* (for PSoC 5TM) are accepted with the approximately 250 mV interval.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) \r
+{\r
+ *CY_INT_CLEAR_PTR = 0x01u;\r
+\r
+ #if(!CY_PSOC5A)\r
+ CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
+ #endif /*(!CY_PSOC5A)*/\r
+\r
+ CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu);\r
+ CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN;\r
+\r
+ /* Timeout to eliminate glitches on the LVI/HVI when enabling */\r
+ CyDelayUs(1u);\r
+\r
+ (void)CY_VD_PERSISTENT_STATUS_REG;\r
+\r
+ #if(!CY_PSOC5A)\r
+ if(0u != reset)\r
+ {\r
+ CY_VD_PRES_CONTROL_REG |= CY_VD_PRESA_EN;\r
+ }\r
+ else\r
+ {\r
+ CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
+ }\r
+ #else\r
+\r
+ if(0u != reset)\r
+ {\r
+ /* To remove unreferenced local variable warning */\r
+ }\r
+\r
+ #endif /*(!CY_PSOC5A)*/\r
+\r
+ *CY_INT_CLR_PEND_PTR = 0x01u;\r
+ *CY_INT_ENABLE_PTR = 0x01u;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyVdLvDigitDisable\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disables the digital low voltage monitor (interrupt and device reset are\r
+* disabled).\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyVdLvDigitDisable(void) \r
+{\r
+ CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVID_EN));\r
+\r
+ #if(!CY_PSOC5A)\r
+ CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN));\r
+ #endif /*(!CY_PSOC5A)*/\r
+\r
+ while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u))\r
+ {\r
+\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyVdLvAnalogDisable\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disables the analog low voltage monitor\r
+* (interrupt and device reset are disabled).\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyVdLvAnalogDisable(void) \r
+{\r
+ CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVIA_EN));\r
+\r
+ #if(!CY_PSOC5A)\r
+ CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
+ #endif /*(!CY_PSOC5A)*/\r
+\r
+ while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u))\r
+ {\r
+\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyVdHvAnalogEnable\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enables the analog high voltage monitors to generate interrupt on\r
+* Vdda archives 5.75 V threshold and optionally resets device.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyVdHvAnalogEnable(void) \r
+{\r
+ *CY_INT_CLEAR_PTR = 0x01u;\r
+\r
+ #if(!CY_PSOC5A)\r
+ CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN));\r
+ #endif /*(!CY_PSOC5A)*/\r
+\r
+ CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_HVIA_EN;\r
+\r
+ /* Timeout to eliminate glitches on the LVI/HVI when enabling */\r
+ CyDelayUs(1u);\r
+\r
+ (void) CY_VD_PERSISTENT_STATUS_REG;\r
+\r
+ *CY_INT_CLR_PEND_PTR = 0x01u;\r
+ *CY_INT_ENABLE_PTR = 0x01u;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyVdHvAnalogDisable\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disables the analog low voltage monitor\r
+* (interrupt and device reset are disabled).\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyVdHvAnalogDisable(void) \r
+{\r
+ CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_HVIA_EN));\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyVdStickyStatus\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Manages the Reset and Voltage Detection Status Register 0.\r
+* This register has the interrupt status for the HVIA, LVID and LVIA.\r
+* This hardware register clears on read.\r
+*\r
+* Parameters:\r
+* mask: Bits in the shadow register to clear.\r
+* Value Define Bit To Clear\r
+* 0x01 CY_VD_LVID LVID\r
+* 0x02 CY_VD_LVIA LVIA\r
+* 0x04 CY_VD_HVIA HVIA\r
+*\r
+* Return:\r
+* Status. Same enumerated bit values as used for the mask parameter.\r
+*\r
+*******************************************************************************/\r
+uint8 CyVdStickyStatus(uint8 mask) \r
+{\r
+ uint8 status;\r
+\r
+ status = CY_VD_PERSISTENT_STATUS_REG;\r
+ CY_VD_PERSISTENT_STATUS_REG &= ((uint8)(~mask));\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyVdRealTimeStatus\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Returns the real time voltage detection status.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* Status. Same enumerated bit values as used for the mask parameter.\r
+*\r
+*******************************************************************************/\r
+uint8 CyVdRealTimeStatus(void) \r
+{\r
+ uint8 interruptState;\r
+ uint8 vdFlagsState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+ vdFlagsState = CY_VD_RT_STATUS_REG;\r
+ CyExitCriticalSection(interruptState);\r
+\r
+ return(vdFlagsState);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyDisableInts\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disables the interrupt enable for each interrupt.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* 32 bit mask of previously enabled interrupts.\r
+*\r
+*******************************************************************************/\r
+uint32 CyDisableInts(void) \r
+{\r
+ uint32 intState;\r
+ uint8 interruptState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ #if(CY_PSOC3)\r
+\r
+ /* Get the current interrupt state. */\r
+ intState = ((uint32) CY_GET_REG8(CY_INT_CLR_EN0_PTR));\r
+ intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN1_PTR)) << 8u));\r
+ intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN2_PTR)) << 16u));\r
+ intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN3_PTR)) << 24u));\r
+\r
+\r
+ /* Disable all of the interrupts. */\r
+ CY_SET_REG8(CY_INT_CLR_EN0_PTR, 0xFFu);\r
+ CY_SET_REG8(CY_INT_CLR_EN1_PTR, 0xFFu);\r
+ CY_SET_REG8(CY_INT_CLR_EN2_PTR, 0xFFu);\r
+ CY_SET_REG8(CY_INT_CLR_EN3_PTR, 0xFFu);\r
+\r
+ #else\r
+\r
+ /* Get the current interrupt state. */\r
+ intState = CY_GET_REG32(CY_INT_CLEAR_PTR);\r
+\r
+ /* Disable all of the interrupts. */\r
+ CY_SET_REG32(CY_INT_CLEAR_PTR, 0xFFFFFFFFu);\r
+\r
+ #endif /* (CY_PSOC3) */\r
+\r
+ CyExitCriticalSection(interruptState);\r
+\r
+ return (intState);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyEnableInts\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enables interrupts to a given state.\r
+*\r
+* Parameters:\r
+* uint32 mask: 32 bit mask of interrupts to enable.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyEnableInts(uint32 mask) \r
+{\r
+\r
+ uint8 interruptState;\r
+\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ #if(CY_PSOC3)\r
+\r
+ /* Set interrupts as enabled. */\r
+ CY_SET_REG8(CY_INT_SET_EN3_PTR, ((uint8) (mask >> 24u)));\r
+ CY_SET_REG8(CY_INT_SET_EN2_PTR, ((uint8) (mask >> 16u)));\r
+ CY_SET_REG8(CY_INT_SET_EN1_PTR, ((uint8) (mask >> 8u )));\r
+ CY_SET_REG8(CY_INT_SET_EN0_PTR, ((uint8) (mask )));\r
+\r
+ #else\r
+\r
+ CY_SET_REG32(CY_INT_ENABLE_PTR, mask);\r
+\r
+ #endif /* (CY_PSOC3) */\r
+\r
+ CyExitCriticalSection(interruptState);\r
+\r
+}\r
+\r
+#if(CY_PSOC5)\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyFlushCache\r
+ ********************************************************************************\r
+ * Summary:\r
+ * Flushes the PSoC 5/5LP cache by invalidating all entries.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CyFlushCache(void)\r
+ {\r
+ uint8 interruptState;\r
+\r
+ /* Save current global interrupt enable and disable it */\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ /* Fill instruction prefectch unit to insure data integrity */\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+\r
+ /* All entries in the cache are invalidated on the next clock cycle. */\r
+ CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH;\r
+\r
+\r
+ /***********************************************************************\r
+ * The prefetch unit could/would be filled with the instructions that\r
+ * succeed the flush. Since a flush is desired then theoretically those\r
+ * instructions might be considered stale/invalid.\r
+ ***********************************************************************/\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+\r
+ /* Restore global interrupt enable state */\r
+ CyExitCriticalSection(interruptState);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyIntSetSysVector\r
+ ********************************************************************************\r
+ * Summary:\r
+ * Sets the interrupt vector of the specified system interrupt number. System\r
+ * interrupts are present only for the ARM platform. These interrupts are for\r
+ * SysTick, PendSV and others.\r
+ *\r
+ * Parameters:\r
+ * number: Interrupt number, valid range [0-15].\r
+ address: Pointer to an interrupt service routine.\r
+ *\r
+ * Return:\r
+ * The old ISR vector at this location.\r
+ *\r
+ *******************************************************************************/\r
+ cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address)\r
+ {\r
+ cyisraddress oldIsr;\r
+ cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE;\r
+\r
+ CYASSERT(number <= CY_INT_SYS_NUMBER_MAX);\r
+\r
+ /* Save old Interrupt service routine. */\r
+ oldIsr = ramVectorTable[number & CY_INT_SYS_NUMBER_MASK];\r
+\r
+ /* Set new Interrupt service routine. */\r
+ ramVectorTable[number & CY_INT_SYS_NUMBER_MASK] = address;\r
+\r
+ return (oldIsr);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyIntGetSysVector\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Gets the interrupt vector of the specified system interrupt number. System\r
+ * interrupts are present only for the ARM platform. These interrupts are for\r
+ * SysTick, PendSV and others.\r
+ *\r
+ * Parameters:\r
+ * number: The interrupt number, valid range [0-15].\r
+ *\r
+ * Return:\r
+ * Address of the ISR in the interrupt vector table.\r
+ *\r
+ *******************************************************************************/\r
+ cyisraddress CyIntGetSysVector(uint8 number)\r
+ {\r
+ cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE;\r
+ CYASSERT(number <= CY_INT_SYS_NUMBER_MAX);\r
+\r
+ return ramVectorTable[number & CY_INT_SYS_NUMBER_MASK];\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyIntSetVector\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Sets the interrupt vector of the specified interrupt number.\r
+ *\r
+ * Parameters:\r
+ * number: Valid range [0-31]. Interrupt number\r
+ * address: Pointer to an interrupt service routine\r
+ *\r
+ * Return:\r
+ * Previous interrupt vector value.\r
+ *\r
+ *******************************************************************************/\r
+ cyisraddress CyIntSetVector(uint8 number, cyisraddress address)\r
+ {\r
+ cyisraddress oldIsr;\r
+ cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE;\r
+\r
+ CYASSERT(number <= CY_INT_NUMBER_MAX);\r
+\r
+ /* Save old Interrupt service routine. */\r
+ oldIsr = ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)];\r
+\r
+ /* Set new Interrupt service routine. */\r
+ ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)] = address;\r
+\r
+ return (oldIsr);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyIntGetVector\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Gets the interrupt vector of the specified interrupt number.\r
+ *\r
+ * Parameters:\r
+ * number: Valid range [0-31]. Interrupt number\r
+ *\r
+ * Return:\r
+ * Address of the ISR in the interrupt vector table.\r
+ *\r
+ *******************************************************************************/\r
+ cyisraddress CyIntGetVector(uint8 number)\r
+ {\r
+ cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE;\r
+ CYASSERT(number <= CY_INT_NUMBER_MAX);\r
+\r
+ return (ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)]);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyIntSetPriority\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Sets the Priority of the Interrupt.\r
+ *\r
+ * Parameters:\r
+ * priority: Priority of the interrupt. 0 - 7, 0 being the highest.\r
+ * number: The number of the interrupt, 0 - 31.\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CyIntSetPriority(uint8 number, uint8 priority)\r
+ {\r
+ CYASSERT(priority <= CY_INT_PRIORITY_MAX);\r
+ CYASSERT(number <= CY_INT_NUMBER_MAX);\r
+ CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] = (priority & CY_INT_PRIORITY_MASK)<< 5;\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyIntGetPriority\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Gets the Priority of the Interrupt.\r
+ *\r
+ * Parameters:\r
+ * number: The number of the interrupt, 0 - 31.\r
+ *\r
+ * Return:\r
+ * Priority of the interrupt. 0 - 7, 0 being the highest.\r
+ *\r
+ *******************************************************************************/\r
+ uint8 CyIntGetPriority(uint8 number)\r
+ {\r
+ uint8 priority;\r
+\r
+ CYASSERT(number <= CY_INT_NUMBER_MAX);\r
+\r
+ priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5;\r
+\r
+ return (priority);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyIntGetState\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Gets the enable state of the specified interrupt number.\r
+ *\r
+ * Parameters:\r
+ * number: Valid range [0-31]. Interrupt number.\r
+ *\r
+ * Return:\r
+ * Enable status: 1 if enabled, 0 if disabled\r
+ *\r
+ *******************************************************************************/\r
+ uint8 CyIntGetState(uint8 number)\r
+ {\r
+ reg32 * stateReg;\r
+\r
+ CYASSERT(number <= CY_INT_NUMBER_MAX);\r
+\r
+ /* Get a pointer to the Interrupt enable register. */\r
+ stateReg = CY_INT_ENABLE_PTR;\r
+\r
+ /* Get the state of the interrupt. */\r
+ return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u));\r
+ }\r
+\r
+\r
+#else /* PSoC3 */\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyIntSetVector\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Sets the interrupt vector of the specified interrupt number.\r
+ *\r
+ * Parameters:\r
+ * number: Valid range [0-31]. Interrupt number\r
+ * address: Pointer to an interrupt service routine\r
+ *\r
+ * Return:\r
+ * Previous interrupt vector value.\r
+ *\r
+ *******************************************************************************/\r
+ cyisraddress CyIntSetVector(uint8 number, cyisraddress address) \r
+ {\r
+ cyisraddress oldIsr;\r
+\r
+ CYASSERT(number <= CY_INT_NUMBER_MAX);\r
+\r
+ /* Save old Interrupt service routine. */\r
+ oldIsr = (cyisraddress) \\r
+ CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK]);\r
+\r
+ /* Set new Interrupt service routine. */\r
+ CY_SET_REG16(&CY_INT_VECT_TABLE[number], (uint16) address);\r
+\r
+ return (oldIsr);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyIntGetVector\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Gets the interrupt vector of the specified interrupt number.\r
+ *\r
+ * Parameters:\r
+ * number: Valid range [0-31]. Interrupt number\r
+ *\r
+ * Return:\r
+ * Address of the ISR in the interrupt vector table.\r
+ *\r
+ *******************************************************************************/\r
+ cyisraddress CyIntGetVector(uint8 number) \r
+ {\r
+ CYASSERT(number <= CY_INT_NUMBER_MAX);\r
+\r
+ return ((cyisraddress) \\r
+ CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK]));\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyIntSetPriority\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Sets the Priority of the Interrupt.\r
+ *\r
+ * Parameters:\r
+ * priority: Priority of the interrupt. 0 - 7, 0 being the highest.\r
+ * number: The number of the interrupt, 0 - 31.\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CyIntSetPriority(uint8 number, uint8 priority) \r
+ {\r
+ CYASSERT(priority <= CY_INT_PRIORITY_MAX);\r
+\r
+ CYASSERT(number <= CY_INT_NUMBER_MAX);\r
+\r
+ CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] =\r
+ (priority & CY_INT_PRIORITY_MASK) << 5;\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyIntGetPriority\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Gets the Priority of the Interrupt.\r
+ *\r
+ * Parameters:\r
+ * number: The number of the interrupt, 0 - 31.\r
+ *\r
+ * Return:\r
+ * Priority of the interrupt. 0 - 7, 0 being the highest.\r
+ *\r
+ *******************************************************************************/\r
+ uint8 CyIntGetPriority(uint8 number) \r
+ {\r
+ uint8 priority;\r
+\r
+ CYASSERT(number <= CY_INT_NUMBER_MAX);\r
+\r
+ priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5;\r
+\r
+ return (priority);\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyIntGetState\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Gets the enable state of the specified interrupt number.\r
+ *\r
+ * Parameters:\r
+ * number: Valid range [0-31]. Interrupt number.\r
+ *\r
+ * Return:\r
+ * Enable status: 1 if enabled, 0 if disabled\r
+ *\r
+ *******************************************************************************/\r
+ uint8 CyIntGetState(uint8 number) \r
+ {\r
+ reg8 * stateReg;\r
+\r
+ CYASSERT(number <= CY_INT_NUMBER_MAX);\r
+\r
+ /* Get a pointer to the Interrupt enable register. */\r
+ stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u);\r
+\r
+ /* Get the state of the interrupt. */\r
+ return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u)));\r
+ }\r
+\r
+\r
+#endif /* (CY_PSOC5) */\r
+\r
+\r
+#if(!CY_PSOC5A)\r
+\r
+ #if(CYDEV_VARIABLE_VDDA == 1)\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CySetScPumps\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * If 1 is passed as a parameter:\r
+ * - if any of the SC blocks are used - enable pumps for the SC blocks and\r
+ * start boost clock.\r
+ * - For the each enabled SC block set boost clock index and enable boost clock.\r
+ *\r
+ * If non-1 value is passed as a parameter:\r
+ * - If all SC blocks are not used - disable pumps for the SC blocks and\r
+ * stop boost clock.\r
+ * - For the each enabled SC block clear boost clock index and disable boost\r
+ * clock.\r
+ *\r
+ * The global variable CyScPumpEnabled is updated to be equal to passed\r
+ * parameter.\r
+ *\r
+ * Parameters:\r
+ * uint8 enable: Enable/disable SC pumps and boost clock for enabled SC block.\r
+ * 1 - Enable\r
+ * 0 - Disable\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ void CySetScPumps(uint8 enable) \r
+ {\r
+\r
+ if(1u == enable)\r
+ {\r
+ /* The SC pumps should be enabled */\r
+ CyScPumpEnabled = 1u;\r
+\r
+\r
+ /* Enable pumps if any of SC blocks are used */\r
+ if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAPS_MASK))\r
+ {\r
+\r
+ CY_LIB_SC_MISC_REG |= CY_LIB_SC_MISC_PUMP_FORCE;\r
+\r
+ CyScBoostClk_Start();\r
+ }\r
+\r
+\r
+ /* Set positive pump for each enabled SC block: set clock index and enable it */\r
+ if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP0_EN))\r
+ {\r
+ CY_LIB_SC0_BST_REG = (CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;\r
+ CY_LIB_SC0_BST_REG |= CY_LIB_SC_BST_CLK_EN;\r
+ }\r
+\r
+ if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP1_EN))\r
+ {\r
+ CY_LIB_SC1_BST_REG = (CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;\r
+ CY_LIB_SC1_BST_REG |= CY_LIB_SC_BST_CLK_EN;\r
+ }\r
+\r
+ if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP2_EN))\r
+ {\r
+ CY_LIB_SC2_BST_REG = (CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;\r
+ CY_LIB_SC2_BST_REG |= CY_LIB_SC_BST_CLK_EN;\r
+ }\r
+\r
+ if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP3_EN))\r
+ {\r
+ CY_LIB_SC3_BST_REG = (CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX;\r
+ CY_LIB_SC3_BST_REG |= CY_LIB_SC_BST_CLK_EN;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* The SC pumps should be disabled */\r
+ CyScPumpEnabled = 0u;\r
+\r
+ /* Disable pumps for all SC blocks and stop boost clock */\r
+ CY_LIB_SC_MISC_REG &= ((uint8)(~CY_LIB_SC_MISC_PUMP_FORCE));\r
+ CyScBoostClk_Stop();\r
+\r
+ /* Disable boost clock and clear clock index for each SC block */\r
+ CY_LIB_SC0_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));\r
+ CY_LIB_SC0_BST_REG = CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;\r
+\r
+ CY_LIB_SC1_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));\r
+ CY_LIB_SC1_BST_REG = CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;\r
+\r
+ CY_LIB_SC2_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));\r
+ CY_LIB_SC2_BST_REG = CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;\r
+\r
+ CY_LIB_SC3_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN));\r
+ CY_LIB_SC3_BST_REG = CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK;\r
+ }\r
+ }\r
+\r
+ #endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
+\r
+#endif /* (!CY_PSOC5A) */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: CyLib.h\r
+* Version 3.40\r
+*\r
+* Description:\r
+* Provides the function definitions for the system, clocking, interrupts and\r
+* watchdog timer API.\r
+*\r
+* Note:\r
+* Documentation of the API's in this file is located in the System Reference\r
+* Guide provided with PSoC Creator.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_BOOT_CYLIB_H)\r
+#define CY_BOOT_CYLIB_H\r
+\r
+#include <string.h>\r
+#include <limits.h>\r
+#include <ctype.h>\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+#include "cydevice_trm.h"\r
+#include "cyPm.h"\r
+\r
+#if(CY_PSOC3)\r
+ #include <PSoC3_8051.h>\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
+#if(!CY_PSOC5A)\r
+\r
+ #if(CYDEV_VARIABLE_VDDA == 1)\r
+\r
+ #include "CyScBoostClk.h"\r
+\r
+ #endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
+\r
+#endif /* (!CY_PSOC5A) */\r
+\r
+\r
+/* Global variable with preserved reset status */\r
+extern uint8 CYXDATA CyResetStatus;\r
+\r
+\r
+#if(!CY_PSOC5A)\r
+\r
+ /* Variable Vdda */\r
+ #if(CYDEV_VARIABLE_VDDA == 1)\r
+\r
+ extern uint8 CyScPumpEnabled;\r
+\r
+ #endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
+\r
+#endif /* (!CY_PSOC5A) */\r
+\r
+\r
+/* Do not use these definitions directly in your application */\r
+extern uint32 cydelay_freq_hz;\r
+extern uint32 cydelay_freq_khz;\r
+extern uint8 cydelay_freq_mhz;\r
+extern uint32 cydelay_32k_ms;\r
+\r
+\r
+/***************************************\r
+* Function Prototypes\r
+***************************************/\r
+cystatus CyPLL_OUT_Start(uint8 wait) ;\r
+void CyPLL_OUT_Stop(void) ;\r
+void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) ;\r
+void CyPLL_OUT_SetSource(uint8 source) ;\r
+\r
+void CyIMO_Start(uint8 wait) ;\r
+void CyIMO_Stop(void) ;\r
+void CyIMO_SetFreq(uint8 freq) ;\r
+void CyIMO_SetSource(uint8 source) ;\r
+void CyIMO_EnableDoubler(void) ;\r
+void CyIMO_DisableDoubler(void) ;\r
+\r
+void CyMasterClk_SetSource(uint8 source) ;\r
+void CyMasterClk_SetDivider(uint8 divider) ;\r
+void CyBusClk_SetDivider(uint16 divider) ;\r
+\r
+#if(CY_PSOC3)\r
+ void CyCpuClk_SetDivider(uint8 divider) ;\r
+#endif /* (CY_PSOC3) */\r
+\r
+void CyUsbClk_SetSource(uint8 source) ;\r
+\r
+void CyILO_Start1K(void) ;\r
+void CyILO_Stop1K(void) ;\r
+void CyILO_Start100K(void) ;\r
+void CyILO_Stop100K(void) ;\r
+void CyILO_Enable33K(void) ;\r
+void CyILO_Disable33K(void) ;\r
+void CyILO_SetSource(uint8 source) ;\r
+uint8 CyILO_SetPowerMode(uint8 mode) ;\r
+\r
+uint8 CyXTAL_32KHZ_ReadStatus(void) ;\r
+uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) ;\r
+void CyXTAL_32KHZ_Start(void) ;\r
+void CyXTAL_32KHZ_Stop(void) ;\r
+\r
+cystatus CyXTAL_Start(uint8 wait) ;\r
+void CyXTAL_Stop(void) ;\r
+void CyXTAL_SetStartup(uint8 setting) ;\r
+#if(!CY_PSOC5A)\r
+ void CyXTAL_EnableErrStatus(void) ;\r
+ void CyXTAL_DisableErrStatus(void) ;\r
+ uint8 CyXTAL_ReadStatus(void) ;\r
+ void CyXTAL_EnableFaultRecovery(void) ;\r
+ void CyXTAL_DisableFaultRecovery(void) ;\r
+#endif /* (!CY_PSOC5A) */\r
+\r
+#if(CY_PSOC3 || CY_PSOC5LP)\r
+ void CyXTAL_SetFbVoltage(uint8 setting) ;\r
+ void CyXTAL_SetWdVoltage(uint8 setting) ;\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+void CyWdtStart(uint8 ticks, uint8 lpMode) ;\r
+void CyWdtClear(void) ;\r
+\r
+/* System Function Prototypes */\r
+void CyDelay(uint32 milliseconds) CYREENTRANT;\r
+void CyDelayUs(uint16 microseconds);\r
+void CyDelayFreq(uint32 freq) CYREENTRANT;\r
+void CyDelayCycles(uint32 cycles);\r
+\r
+void CySoftwareReset(void) ;\r
+\r
+uint8 CyEnterCriticalSection(void);\r
+void CyExitCriticalSection(uint8 savedIntrStatus);\r
+void CyHalt(uint8 reason) CYREENTRANT;\r
+\r
+\r
+/* Interrupt Function Prototypes */\r
+#if(CY_PSOC5)\r
+ cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) ;\r
+ cyisraddress CyIntGetSysVector(uint8 number) ;\r
+#endif /* (CY_PSOC5) */\r
+\r
+cyisraddress CyIntSetVector(uint8 number, cyisraddress address) ;\r
+cyisraddress CyIntGetVector(uint8 number) ;\r
+\r
+void CyIntSetPriority(uint8 number, uint8 priority) ;\r
+uint8 CyIntGetPriority(uint8 number) ;\r
+\r
+uint8 CyIntGetState(uint8 number) ;\r
+\r
+uint32 CyDisableInts(void) ;\r
+void CyEnableInts(uint32 mask) ;\r
+\r
+\r
+#if(CY_PSOC5)\r
+ void CyFlushCache(void);\r
+#endif /* (CY_PSOC5) */\r
+\r
+\r
+/* Voltage Detection Function Prototypes */\r
+void CyVdLvDigitEnable(uint8 reset, uint8 threshold) ;\r
+void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) ;\r
+void CyVdLvDigitDisable(void) ;\r
+void CyVdLvAnalogDisable(void) ;\r
+void CyVdHvAnalogEnable(void) ;\r
+void CyVdHvAnalogDisable(void) ;\r
+uint8 CyVdStickyStatus(uint8 mask) ;\r
+uint8 CyVdRealTimeStatus(void) ;\r
+\r
+#if(!CY_PSOC5A)\r
+\r
+ void CySetScPumps(uint8 enable) ;\r
+\r
+#endif /* (!CY_PSOC5A) */\r
+\r
+\r
+/***************************************\r
+* API Constants\r
+***************************************/\r
+\r
+\r
+/*******************************************************************************\r
+* PLL API Constants\r
+*******************************************************************************/\r
+#define CY_CLK_PLL_ENABLE (0x01u)\r
+#define CY_CLK_PLL_LOCK_STATUS (0x01u)\r
+\r
+#define CY_CLK_PLL_FTW_INTERVAL (24u)\r
+\r
+#define CY_CLK_PLL_MAX_Q_VALUE (16u)\r
+#define CY_CLK_PLL_MIN_Q_VALUE (1u)\r
+#define CY_CLK_PLL_MIN_P_VALUE (8u)\r
+#define CY_CLK_PLL_MIN_CUR_VALUE (1u)\r
+#define CY_CLK_PLL_MAX_CUR_VALUE (7u)\r
+\r
+#define CY_CLK_PLL_CURRENT_POSITION (4u)\r
+#define CY_CLK_PLL_CURRENT_MASK (0x8Fu)\r
+\r
+\r
+/*******************************************************************************\r
+* External 32kHz Crystal Oscillator API Constants\r
+*******************************************************************************/\r
+#define CY_XTAL32K_ANA_STAT (0x20u)\r
+\r
+\r
+#define CY_CLK_XTAL32_CR_LPM (0x02u)\r
+#define CY_CLK_XTAL32_CR_EN (0x01u)\r
+#if(CY_PSOC3)\r
+ #define CY_CLK_XTAL32_CR_PDBEN (0x04u)\r
+#endif /* (CY_PSOC3) */\r
+\r
+#define CY_CLK_XTAL32_TR_MASK (0x07u)\r
+#define CY_CLK_XTAL32_TR_STARTUP (0x03u)\r
+#define CY_CLK_XTAL32_TR_HIGH_POWER (0x06u)\r
+#define CY_CLK_XTAL32_TR_LOW_POWER (0x01u)\r
+#define CY_CLK_XTAL32_TR_POWERDOWN (0x00u)\r
+\r
+#define CY_CLK_XTAL32_TST_DEFAULT (0xF3u)\r
+\r
+#define CY_CLK_XTAL32_CFG_LP_DEFAULT (0x04u)\r
+#define CY_CLK_XTAL32_CFG_LP_LOWPOWER (0x08u)\r
+#define CY_CLK_XTAL32_CFG_LP_MASK (0x0Cu)\r
+\r
+#define CY_CLK_XTAL32_CFG_LP_ALLOW (0x80u)\r
+\r
+\r
+/*******************************************************************************\r
+* External MHz Crystal Oscillator API Constants\r
+*******************************************************************************/\r
+#define CY_CLK_XMHZ_FTW_INTERVAL (24u)\r
+#define CY_CLK_XMHZ_MIN_TIMEOUT (130u)\r
+\r
+#define CY_CLK_XMHZ_CSR_ENABLE (0x01u)\r
+#define CY_CLK_XMHZ_CSR_XERR (0x80u)\r
+#define CY_CLK_XMHZ_CSR_XFB (0x04u)\r
+#define CY_CLK_XMHZ_CSR_XPROT (0x40u)\r
+\r
+#define CY_CLK_XMHZ_CFG0_XCFG_MASK (0x1Fu)\r
+#define CY_CLK_XMHZ_CFG1_VREF_FB_MASK (0x0Fu)\r
+#define CY_CLK_XMHZ_CFG1_VREF_WD_MASK (0x70u)\r
+\r
+\r
+/*******************************************************************************\r
+* Watchdog Timer API Constants\r
+*******************************************************************************/\r
+#define CYWDT_2_TICKS (0x0u) /* 4 - 6 ms */\r
+#define CYWDT_16_TICKS (0x1u) /* 32 - 48 ms */\r
+#define CYWDT_128_TICKS (0x2u) /* 256 - 384 ms */\r
+#define CYWDT_1024_TICKS (0x3u) /* 2048 - 3072 ms */\r
+\r
+#define CYWDT_LPMODE_NOCHANGE (0x00u)\r
+#define CYWDT_LPMODE_MAXINTER (0x01u)\r
+#define CYWDT_LPMODE_DISABLED (0x03u)\r
+\r
+#define CY_WDT_CFG_INTERVAL_MASK (0x03u)\r
+#define CY_WDT_CFG_CTW_RESET (0x80u)\r
+#define CY_WDT_CFG_LPMODE_SHIFT (5u)\r
+#define CY_WDT_CFG_LPMODE_MASK (0x60u)\r
+#define CY_WDT_CFG_WDR_EN (0x10u)\r
+#define CY_WDT_CFG_CLEAR_ALL (0x00u)\r
+#define CY_WDT_CR_FEED (0x01u)\r
+\r
+\r
+/*******************************************************************************\r
+* Voltage Detection API Constants\r
+*******************************************************************************/\r
+\r
+#define CY_VD_LVID_EN (0x01u)\r
+#define CY_VD_LVIA_EN (0x02u)\r
+#define CY_VD_HVIA_EN (0x04u)\r
+\r
+#define CY_VD_PRESD_EN (0x40u)\r
+#define CY_VD_PRESA_EN (0x80u)\r
+\r
+#define CY_VD_LVID (0x01u)\r
+#define CY_VD_LVIA (0x02u)\r
+#define CY_VD_HVIA (0x04u)\r
+\r
+#define CY_VD_LVI_TRIP_LVID_MASK (0x0Fu)\r
+\r
+\r
+/*******************************************************************************\r
+* Variable VDDA\r
+*******************************************************************************/\r
+#if(!CY_PSOC5A)\r
+\r
+ #if(CYDEV_VARIABLE_VDDA == 1)\r
+\r
+ /* Active Power Mode Configuration Register 9 */\r
+ #define CY_LIB_ACT_CFG9_SWCAP0_EN (0x01u)\r
+ #define CY_LIB_ACT_CFG9_SWCAP1_EN (0x02u)\r
+ #define CY_LIB_ACT_CFG9_SWCAP2_EN (0x04u)\r
+ #define CY_LIB_ACT_CFG9_SWCAP3_EN (0x08u)\r
+ #define CY_LIB_ACT_CFG9_SWCAPS_MASK (0x0Fu)\r
+\r
+ /* Switched Cap Miscellaneous Control Register */\r
+ #define CY_LIB_SC_MISC_PUMP_FORCE (0x20u)\r
+\r
+ /* Switched Capacitor 0 Boost Clock Selection Register */\r
+ #define CY_LIB_SC_BST_CLK_EN (0x08u)\r
+ #define CY_LIB_SC_BST_CLK_INDEX_MASK (0xF8u)\r
+\r
+ #endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
+\r
+#endif /* (!CY_PSOC5A) */\r
+\r
+\r
+/*******************************************************************************\r
+* Clock Distribution Constants\r
+*******************************************************************************/\r
+#define CY_LIB_CLKDIST_AMASK_MASK (0xF0u)\r
+#define CY_LIB_CLKDIST_DMASK_MASK (0x00u)\r
+#define CY_LIB_CLKDIST_LD_LOAD (0x01u)\r
+#define CY_LIB_CLKDIST_BCFG2_MASK (0x80u) /* Enable shadow loads */\r
+#define CY_LIB_CLKDIST_MASTERCLK_DIV (7u)\r
+#define CY_LIB_CLKDIST_BCFG2_SSS (0x40u) /* Sync source is same frequency */\r
+#define CY_LIB_CLKDIST_MSTR1_SRC_MASK (0xFCu)\r
+#define CY_LIB_FASTCLK_IMO_DOUBLER (0x10u)\r
+#define CY_LIB_FASTCLK_IMO_IMO (0x20u)\r
+#define CY_LIB_CLKDIST_CR_IMO2X (0x40u)\r
+#define CY_LIB_FASTCLK_IMO_CR_RANGE_MASK (0xF8u)\r
+\r
+#define CY_LIB_CLKDIST_CR_PLL_SCR_MASK (0xFCu)\r
+\r
+#define ILO_CONTROL_PD_MODE (0x10u)\r
+\r
+#define CY_ILO_SOURCE_100K (0u)\r
+#define CY_ILO_SOURCE_33K (1u)\r
+#define CY_ILO_SOURCE_1K (2u)\r
+\r
+#define CY_ILO_FAST_START (0u)\r
+#define CY_ILO_SLOW_START (1u)\r
+\r
+#define CY_ILO_SOURCE_BITS_CLEAR (0xF3u)\r
+#define CY_ILO_SOURCE_1K_SET (0x08u)\r
+#define CY_ILO_SOURCE_33K_SET (0x04u)\r
+#define CY_ILO_SOURCE_100K_SET (0x00u)\r
+\r
+\r
+#define CY_MASTER_SOURCE_IMO (0u)\r
+#define CY_MASTER_SOURCE_PLL (1u)\r
+#define CY_MASTER_SOURCE_XTAL (2u)\r
+#define CY_MASTER_SOURCE_DSI (3u)\r
+\r
+#define CY_IMO_SOURCE_IMO (0u)\r
+#define CY_IMO_SOURCE_XTAL (1u)\r
+#define CY_IMO_SOURCE_DSI (2u)\r
+#define IMO_PM_ENABLE (0x10u) /* Enable IMO clock source. */\r
+#define FASTCLK_IMO_USBCLK_ON_SET (0x40u)\r
+\r
+#define CLOCK_IMO_3MHZ_VALUE (0x03u)\r
+#define CLOCK_IMO_6MHZ_VALUE (0x01u)\r
+#define CLOCK_IMO_12MHZ_VALUE (0x00u)\r
+#define CLOCK_IMO_24MHZ_VALUE (0x02u)\r
+#define CLOCK_IMO_48MHZ_VALUE (0x04u)\r
+#define CLOCK_IMO_62MHZ_VALUE (0x05u)\r
+#define CLOCK_IMO_74MHZ_VALUE (0x06u)\r
+\r
+/* CyIMO_SetFreq() */\r
+#define CY_IMO_FREQ_3MHZ (0u)\r
+#define CY_IMO_FREQ_6MHZ (1u)\r
+#define CY_IMO_FREQ_12MHZ (2u)\r
+#define CY_IMO_FREQ_24MHZ (3u)\r
+#define CY_IMO_FREQ_48MHZ (4u)\r
+#if(!CY_PSOC5A)\r
+ #define CY_IMO_FREQ_62MHZ (5u)\r
+#endif /* (!CY_PSOC5A) */\r
+#define CY_IMO_FREQ_USB (8u)\r
+\r
+\r
+#define SFR_USER_CPUCLK_DIV_MASK (0x0Fu)\r
+#define CLKDIST_DIV_POSITION (4u)\r
+#define CLKDIST_MSTR1_DIV_CLEAR (0x0Fu)\r
+#define CLOCK_USB_ENABLE (0x02u)\r
+#define CLOCK_IMO_OUT_X2 (0x10u)\r
+#define CLOCK_IMO_OUT_X1 ((uint8)(~CLOCK_IMO_OUT_X2))\r
+#define CY_PLL_SOURCE_IMO (0u)\r
+#define CY_PLL_SOURCE_XTAL (1u)\r
+#define CY_PLL_SOURCE_DSI (2u)\r
+\r
+#define CLOCK_IMO2X_ECO ((uint8)(~CLOCK_IMO2X_DSI))\r
+\r
+#define ILO_CONTROL_PD_POSITION (4u)\r
+#define ILO_CONTROL_1KHZ_ON (0x02u)\r
+#define ILO_CONTROL_100KHZ_ON (0x04u)\r
+#define ILO_CONTROL_33KHZ_ON (0x20u)\r
+\r
+#define USB_CLKDIST_CONFIG_MASK (0x03u)\r
+#define USB_CLK_IMO2X (0x00u)\r
+#define USB_CLK_IMO (0x01u)\r
+#define USB_CLK_PLL (0x02u)\r
+#define USB_CLK_DSI (0x03u)\r
+#define USB_CLK_DIV2_ON (0x04u)\r
+#define USB_CLK_STOP_FLAG (0x00u)\r
+#define USB_CLK_START_FLAG (0x01u)\r
+\r
+#define FTW_CLEAR_ALL_BITS (0x00u) /* To clear all bits of PM_TW_CFG2 */\r
+#define FTW_CLEAR_FTW_BITS (0xFCu) /* To clear FTW bits of PM_TW_CFG2 */\r
+#define FTW_ENABLE (0x01u) /* To enable FTW, no interrupt */\r
+\r
+#define CY_ACT_USB_ENABLED (0x01u)\r
+#define CY_ALT_ACT_USB_ENABLED (0x01u)\r
+\r
+\r
+/***************************************\r
+* Registers\r
+***************************************/\r
+\r
+\r
+/*******************************************************************************\r
+* PLL Registers\r
+*******************************************************************************/\r
+\r
+/* PLL Configuration Register 0 */\r
+#define CY_CLK_PLL_CFG0_REG (*(reg8 *) CYREG_FASTCLK_PLL_CFG0)\r
+#define CY_CLK_PLL_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG0)\r
+\r
+/* PLL Configuration Register 1 */\r
+#define CY_CLK_PLL_CFG1_REG (*(reg8 *) CYREG_FASTCLK_PLL_CFG1)\r
+#define CY_CLK_PLL_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG1)\r
+\r
+/* PLL Status Register */\r
+#define CY_CLK_PLL_SR_REG (*(reg8 *) CYREG_FASTCLK_PLL_SR)\r
+#define CY_CLK_PLL_SR_PTR ( (reg8 *) CYREG_FASTCLK_PLL_SR)\r
+\r
+/* PLL Q-Counter Configuration Register */\r
+#define CY_CLK_PLL_Q_REG (*(reg8 *) CYREG_FASTCLK_PLL_Q)\r
+#define CY_CLK_PLL_Q_PTR ( (reg8 *) CYREG_FASTCLK_PLL_Q)\r
+\r
+/* PLL P-Counter Configuration Register */\r
+#define CY_CLK_PLL_P_REG (*(reg8 *) CYREG_FASTCLK_PLL_P)\r
+#define CY_CLK_PLL_P_PTR ( (reg8 *) CYREG_FASTCLK_PLL_P)\r
+\r
+\r
+/*******************************************************************************\r
+* External MHz Crystal Oscillator Registers\r
+*******************************************************************************/\r
+\r
+/* External MHz Crystal Oscillator Status and Control Register */\r
+#define CY_CLK_XMHZ_CSR_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CSR)\r
+#define CY_CLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR)\r
+\r
+/* External MHz Crystal Oscillator Configuration Register 0 */\r
+#define CY_CLK_XMHZ_CFG0_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG0)\r
+#define CY_CLK_XMHZ_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG0)\r
+\r
+/* External MHz Crystal Oscillator Configuration Register 1 */\r
+#define CY_CLK_XMHZ_CFG1_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG1)\r
+#define CY_CLK_XMHZ_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG1)\r
+\r
+\r
+/*******************************************************************************\r
+* External 32kHz Crystal Oscillator Registers\r
+*******************************************************************************/\r
+\r
+/* 32 kHz Watch Crystal Oscillator Trim Register */\r
+#define CY_CLK_XTAL32_TR_REG (*(reg8 *) CYREG_X32_TR)\r
+#define CY_CLK_XTAL32_TR_PTR ( (reg8 *) CYREG_X32_TR)\r
+\r
+/* External 32kHz Crystal Oscillator Test Register */\r
+#define CY_CLK_XTAL32_TST_REG (*(reg8 *) CYREG_SLOWCLK_X32_TST)\r
+#define CY_CLK_XTAL32_TST_PTR ( (reg8 *) CYREG_SLOWCLK_X32_TST)\r
+\r
+/* External 32kHz Crystal Oscillator Control Register */\r
+#define CY_CLK_XTAL32_CR_REG (*(reg8 *) CYREG_SLOWCLK_X32_CR)\r
+#define CY_CLK_XTAL32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR)\r
+\r
+/* External 32kHz Crystal Oscillator Configuration Register */\r
+#define CY_CLK_XTAL32_CFG_REG (*(reg8 *) CYREG_SLOWCLK_X32_CFG)\r
+#define CY_CLK_XTAL32_CFG_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CFG)\r
+\r
+\r
+/*******************************************************************************\r
+* Watchdog Timer Registers\r
+*******************************************************************************/\r
+\r
+/* Watchdog Timer Configuration Register */\r
+#define CY_WDT_CFG_REG (*(reg8 *) CYREG_PM_WDT_CFG)\r
+#define CY_WDT_CFG_PTR ( (reg8 *) CYREG_PM_WDT_CFG)\r
+\r
+/* Watchdog Timer Control Register */\r
+#define CY_WDT_CR_REG (*(reg8 *) CYREG_PM_WDT_CR)\r
+#define CY_WDT_CR_PTR ( (reg8 *) CYREG_PM_WDT_CR)\r
+\r
+\r
+/*******************************************************************************\r
+* LVI/HVI Registers\r
+*******************************************************************************/\r
+\r
+#define CY_VD_LVI_TRIP_REG (* (reg8 *) CYDEV_RESET_CR0)\r
+#define CY_VD_LVI_TRIP_PTR ( (reg8 *) CYDEV_RESET_CR0)\r
+\r
+#define CY_VD_LVI_HVI_CONTROL_REG (* (reg8 *) CYDEV_RESET_CR1)\r
+#define CY_VD_LVI_HVI_CONTROL_PTR ( (reg8 *) CYDEV_RESET_CR1)\r
+\r
+#define CY_VD_PRES_CONTROL_REG (* (reg8 *) CYDEV_RESET_CR3)\r
+#define CY_VD_PRES_CONTROL_PTR ( (reg8 *) CYDEV_RESET_CR3)\r
+\r
+#define CY_VD_PERSISTENT_STATUS_REG (* (reg8 *) CYDEV_RESET_SR0)\r
+#define CY_VD_PERSISTENT_STATUS_PTR ( (reg8 *) CYDEV_RESET_SR0)\r
+\r
+#define CY_VD_RT_STATUS_REG (* (reg8 *) CYDEV_RESET_SR2)\r
+#define CY_VD_RT_STATUS_PTR ( (reg8 *) CYDEV_RESET_SR2)\r
+\r
+\r
+/*******************************************************************************\r
+* Variable VDDA\r
+*******************************************************************************/\r
+#if(!CY_PSOC5A)\r
+\r
+ #if(CYDEV_VARIABLE_VDDA == 1)\r
+\r
+ /* Active Power Mode Configuration Register 9 */\r
+ #define CY_LIB_ACT_CFG9_REG (* (reg8 *) CYREG_PM_ACT_CFG9 )\r
+ #define CY_LIB_ACT_CFG9_PTR ( (reg8 *) CYREG_PM_ACT_CFG9 )\r
+\r
+ /* Switched Capacitor 0 Boost Clock Selection Register */\r
+ #define CY_LIB_SC0_BST_REG (* (reg8 *) CYREG_SC0_BST )\r
+ #define CY_LIB_SC0_BST_PTR ( (reg8 *) CYREG_SC0_BST )\r
+\r
+ /* Switched Capacitor 1 Boost Clock Selection Register */\r
+ #define CY_LIB_SC1_BST_REG (* (reg8 *) CYREG_SC1_BST )\r
+ #define CY_LIB_SC1_BST_PTR ( (reg8 *) CYREG_SC1_BST )\r
+\r
+ /* Switched Capacitor 2 Boost Clock Selection Register */\r
+ #define CY_LIB_SC2_BST_REG (* (reg8 *) CYREG_SC2_BST )\r
+ #define CY_LIB_SC2_BST_PTR ( (reg8 *) CYREG_SC2_BST )\r
+\r
+ /* Switched Capacitor 3 Boost Clock Selection Register */\r
+ #define CY_LIB_SC3_BST_REG (* (reg8 *) CYREG_SC3_BST )\r
+ #define CY_LIB_SC3_BST_PTR ( (reg8 *) CYREG_SC3_BST )\r
+\r
+ /* Switched Cap Miscellaneous Control Register */\r
+ #define CY_LIB_SC_MISC_REG (* (reg8 *) CYREG_SC_MISC )\r
+ #define CY_LIB_SC_MISC_PTR ( (reg8 *) CYREG_SC_MISC )\r
+\r
+ #endif /* (CYDEV_VARIABLE_VDDA == 1) */\r
+\r
+#endif /* (!CY_PSOC5A) */\r
+\r
+\r
+/*******************************************************************************\r
+* Clock Distribution Registers\r
+*******************************************************************************/\r
+\r
+/* Analog Clock Mask Register */\r
+#define CY_LIB_CLKDIST_AMASK_REG (* (reg8 *) CYREG_CLKDIST_AMASK )\r
+#define CY_LIB_CLKDIST_AMASK_PTR ( (reg8 *) CYREG_CLKDIST_AMASK )\r
+\r
+/* Digital Clock Mask Register */\r
+#define CY_LIB_CLKDIST_DMASK_REG (*(reg8 *) CYREG_CLKDIST_DMASK)\r
+#define CY_LIB_CLKDIST_DMASK_PTR ( (reg8 *) CYREG_CLKDIST_DMASK)\r
+\r
+/* CLK_BUS Configuration Register */\r
+#define CY_LIB_CLKDIST_BCFG2_REG (*(reg8 *) CYREG_CLKDIST_BCFG2)\r
+#define CY_LIB_CLKDIST_BCFG2_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2)\r
+\r
+/* LSB Shadow Divider Value Register */\r
+#define CY_LIB_CLKDIST_WRK_LSB_REG (*(reg8 *) CYREG_CLKDIST_WRK0)\r
+#define CY_LIB_CLKDIST_WRK_LSB_PTR ( (reg8 *) CYREG_CLKDIST_WRK0)\r
+\r
+/* MSB Shadow Divider Value Register */\r
+#define CY_LIB_CLKDIST_WRK_MSB_REG (*(reg8 *) CYREG_CLKDIST_WRK1)\r
+#define CY_LIB_CLKDIST_WRK_MSB_PTR ( (reg8 *) CYREG_CLKDIST_WRK1)\r
+\r
+/* LOAD Register */\r
+#define CY_LIB_CLKDIST_LD_REG (*(reg8 *) CYREG_CLKDIST_LD)\r
+#define CY_LIB_CLKDIST_LD_PTR ( (reg8 *) CYREG_CLKDIST_LD)\r
+\r
+/* CLK_BUS LSB Divider Value Register */\r
+#define CY_LIB_CLKDIST_BCFG_LSB_REG (*(reg8 *) CYREG_CLKDIST_BCFG0)\r
+#define CY_LIB_CLKDIST_BCFG_LSB_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0)\r
+\r
+/* CLK_BUS MSB Divider Value Register */\r
+#define CY_LIB_CLKDIST_BCFG_MSB_REG (*(reg8 *) CYREG_CLKDIST_BCFG1)\r
+#define CY_LIB_CLKDIST_BCFG_MSB_PTR ( (reg8 *) CYREG_CLKDIST_BCFG1)\r
+\r
+/* Master clock (clk_sync_d) Divider Value Register */\r
+#define CY_LIB_CLKDIST_MSTR0_REG (*(reg8 *) CYREG_CLKDIST_MSTR0)\r
+#define CY_LIB_CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0)\r
+\r
+/* Master (clk_sync_d) Configuration Register/CPU Divider Value */\r
+#define CY_LIB_CLKDIST_MSTR1_REG (*(reg8 *) CYREG_CLKDIST_MSTR1)\r
+#define CY_LIB_CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1)\r
+\r
+/* Internal Main Oscillator Control Register */\r
+#define CY_LIB_FASTCLK_IMO_CR_REG (*(reg8 *) CYREG_FASTCLK_IMO_CR)\r
+#define CY_LIB_FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR)\r
+\r
+/* Configuration Register CR */\r
+#define CY_LIB_CLKDIST_CR_REG (*(reg8 *) CYREG_CLKDIST_CR)\r
+#define CY_LIB_CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR)\r
+\r
+\r
+#define SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0)\r
+#define SLOWCLK_ILO_CR0 (*(reg8 *) CYREG_SLOWCLK_ILO_CR0)\r
+#define CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG)\r
+#define CLKDIST_UCFG (*(reg8 *) CYREG_CLKDIST_UCFG)\r
+\r
+#define PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0)\r
+#define PM_TW_CFG0 (*(reg8 *) CYREG_PM_TW_CFG0)\r
+\r
+#define PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2)\r
+#define PM_TW_CFG2 (*(reg8 *) CYREG_PM_TW_CFG2)\r
+\r
+#define CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1)\r
+#define CLKDIST_MSTR1 (*(reg8 *) CYREG_CLKDIST_MSTR1)\r
+\r
+\r
+\r
+#define SFR_USER_CPUCLK_DIV_PTR ((void far *) CYREG_SFR_USER_CPUCLK_DIV)\r
+\r
+#define CLOCK_CONTROL ( (reg8 *) CYREG_CLKDIST_CR)\r
+#define IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1)\r
+#define IMO_TR1 (*(reg8 *) CYREG_IMO_TR1)\r
+#define CY_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 )\r
+#define CY_USB_CR1 (*(reg8 *) CYREG_USB_CR1 )\r
+\r
+#define PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)\r
+#define PM_ACT_CFG0 (*(reg8 *) CYREG_PM_ACT_CFG0)\r
+#define PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0)\r
+#define PM_STBY_CFG0 (*(reg8 *) CYREG_PM_STBY_CFG0)\r
+#define PM_AVAIL_CR2_PTR ( (reg8 *) CYREG_PM_AVAIL_CR2)\r
+#define PM_AVAIL_CR2 (*(reg8 *) CYREG_PM_AVAIL_CR2)\r
+\r
+\r
+/* Active Power Mode Configuration Register 5 */\r
+#define CY_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 )\r
+#define CY_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 )\r
+\r
+/* Standby Power Mode Configuration Register 5 */\r
+#define CY_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 )\r
+#define CY_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 )\r
+\r
+\r
+#if(CY_PSOC3)\r
+ #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)\r
+ #define FLSHID_MFG_CFG_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))\r
+ #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB)\r
+ #else\r
+ #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)\r
+ #define FLSHID_MFG_CFG_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))\r
+ #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)\r
+ #define FLSHID_CUST_TABLES_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB)\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
+#define USB_CLKDIST_CONFIG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG)\r
+#define USB_CLKDIST_CONFIG (*(reg8 *) CYREG_CLKDIST_UCFG)\r
+\r
+\r
+/*******************************************************************************\r
+* Interrupt Registers\r
+*******************************************************************************/\r
+\r
+#if(CY_PSOC5)\r
+\r
+ /* Interrupt Vector Table Offset */\r
+ #define CY_INT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)\r
+\r
+ /* Interrupt Priority 0-31 */\r
+ #define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_NVIC_PRI_0)\r
+ #define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_NVIC_PRI_0)\r
+\r
+ /* Interrupt Enable Set 0-31 */\r
+ #define CY_INT_ENABLE_REG (* (reg32 *) CYREG_NVIC_SETENA0)\r
+ #define CY_INT_ENABLE_PTR ( (reg32 *) CYREG_NVIC_SETENA0)\r
+\r
+ /* Interrupt Enable Clear 0-31 */\r
+ #define CY_INT_CLEAR_REG (* (reg32 *) CYREG_NVIC_CLRENA0)\r
+ #define CY_INT_CLEAR_PTR ( (reg32 *) CYREG_NVIC_CLRENA0)\r
+\r
+ /* Interrupt Pending Set 0-31 */\r
+ #define CY_INT_SET_PEND_REG (* (reg32 *) CYREG_NVIC_SETPEND0)\r
+ #define CY_INT_SET_PEND_PTR ( (reg32 *) CYREG_NVIC_SETPEND0)\r
+\r
+ /* Interrupt Pending Clear 0-31 */\r
+ #define CY_INT_CLR_PEND_REG (* (reg32 *) CYREG_NVIC_CLRPEND0)\r
+ #define CY_INT_CLR_PEND_PTR ( (reg32 *) CYREG_NVIC_CLRPEND0)\r
+\r
+ /* Cache Control Register */\r
+ #define CY_CACHE_CONTROL_REG (* (reg16 *) CYREG_CACHE_CC_CTL )\r
+ #define CY_CACHE_CONTROL_PTR ( (reg16 *) CYREG_CACHE_CC_CTL )\r
+\r
+#elif (CY_PSOC3)\r
+\r
+ /* Interrupt Address Vector registers */\r
+ #define CY_INT_VECT_TABLE ((cyisraddress CYXDATA *) CYREG_INTC_VECT_MBASE)\r
+\r
+ /* Interrrupt Controller Priority Registers */\r
+ #define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_INTC_PRIOR0)\r
+ #define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_INTC_PRIOR0)\r
+\r
+ /* Interrrupt Controller Set Enable Registers */\r
+ #define CY_INT_ENABLE_REG (* (reg8 *) CYREG_INTC_SET_EN0)\r
+ #define CY_INT_ENABLE_PTR ( (reg8 *) CYREG_INTC_SET_EN0)\r
+\r
+ #define CY_INT_SET_EN0_REG (* (reg8 *) CYREG_INTC_SET_EN0)\r
+ #define CY_INT_SET_EN0_PTR ( (reg8 *) CYREG_INTC_SET_EN0)\r
+\r
+ #define CY_INT_SET_EN1_REG (* (reg8 *) CYREG_INTC_SET_EN1)\r
+ #define CY_INT_SET_EN1_PTR ( (reg8 *) CYREG_INTC_SET_EN1)\r
+\r
+ #define CY_INT_SET_EN2_REG (* (reg8 *) CYREG_INTC_SET_EN2)\r
+ #define CY_INT_SET_EN2_PTR ( (reg8 *) CYREG_INTC_SET_EN2)\r
+\r
+ #define CY_INT_SET_EN3_REG (* (reg8 *) CYREG_INTC_SET_EN3)\r
+ #define CY_INT_SET_EN3_PTR ( (reg8 *) CYREG_INTC_SET_EN3)\r
+\r
+ /* Interrrupt Controller Clear Enable Registers */\r
+ #define CY_INT_CLEAR_REG (* (reg8 *) CYREG_INTC_CLR_EN0)\r
+ #define CY_INT_CLEAR_PTR ( (reg8 *) CYREG_INTC_CLR_EN0)\r
+\r
+ #define CY_INT_CLR_EN0_REG (* (reg8 *) CYREG_INTC_CLR_EN0)\r
+ #define CY_INT_CLR_EN0_PTR ( (reg8 *) CYREG_INTC_CLR_EN0)\r
+\r
+ #define CY_INT_CLR_EN1_REG (* (reg8 *) CYREG_INTC_CLR_EN1)\r
+ #define CY_INT_CLR_EN1_PTR ( (reg8 *) CYREG_INTC_CLR_EN1)\r
+\r
+ #define CY_INT_CLR_EN2_REG (* (reg8 *) CYREG_INTC_CLR_EN2)\r
+ #define CY_INT_CLR_EN2_PTR ( (reg8 *) CYREG_INTC_CLR_EN2)\r
+\r
+ #define CY_INT_CLR_EN3_REG (* (reg8 *) CYREG_INTC_CLR_EN3)\r
+ #define CY_INT_CLR_EN3_PTR ( (reg8 *) CYREG_INTC_CLR_EN3)\r
+\r
+\r
+ /* Interrrupt Controller Set Pend Registers */\r
+ #define CY_INT_SET_PEND_REG (* (reg8 *) CYREG_INTC_SET_PD0)\r
+ #define CY_INT_SET_PEND_PTR ( (reg8 *) CYREG_INTC_SET_PD0)\r
+\r
+ /* Interrrupt Controller Clear Pend Registers */\r
+ #define CY_INT_CLR_PEND_REG (* (reg8 *) CYREG_INTC_CLR_PD0)\r
+ #define CY_INT_CLR_PEND_PTR ( (reg8 *) CYREG_INTC_CLR_PD0)\r
+\r
+\r
+ /* Access Interrupt Controller Registers based on interrupt number */\r
+ #define CY_INT_SET_EN_INDX_PTR(number) ((reg8 *) (CYREG_INTC_SET_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u)))\r
+ #define CY_INT_CLR_EN_INDX_PTR(number) ((reg8 *) (CYREG_INTC_CLR_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u)))\r
+ #define CY_INT_CLR_PEND_INDX_PTR(number) ((reg8 *) (CYREG_INTC_CLR_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u)))\r
+ #define CY_INT_SET_PEND_INDX_PTR(number) ((reg8 *) (CYREG_INTC_SET_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u)))\r
+\r
+#endif /* (CY_PSOC5) */\r
+\r
+\r
+/*******************************************************************************\r
+* Macro Name: CyAssert\r
+********************************************************************************\r
+* Summary:\r
+* Macro that evaluates the expression and if it is false (evaluates to 0) then\r
+* the processor is halted.\r
+*\r
+* This macro is evaluated unless NDEBUG is defined.\r
+*\r
+* If NDEBUG is defined, then no code is generated for this macro. NDEBUG is\r
+* defined by default for a Release build setting and not defined for a Debug\r
+* build setting.\r
+*\r
+* Parameters:\r
+* expr: Logical expression. Asserts if false.\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+#if !defined(NDEBUG)\r
+ #define CYASSERT(x) { \\r
+ if(!(x)) \\r
+ { \\r
+ CyHalt((uint8) 0u); \\r
+ } \\r
+ }\r
+#else\r
+ #define CYASSERT(x)\r
+#endif /* !defined(NDEBUG) */\r
+\r
+\r
+/* Reset register fields of RESET_SR0 (CyResetStatus) */\r
+#define CY_RESET_LVID (0x01u)\r
+#define CY_RESET_LVIA (0x02u)\r
+#define CY_RESET_HVIA (0x04u)\r
+#define CY_RESET_WD (0x08u)\r
+#define CY_RESET_SW (0x20u)\r
+#define CY_RESET_GPIO0 (0x40u)\r
+#define CY_RESET_GPIO1 (0x80u)\r
+\r
+\r
+/* Interrrupt Controller Configuration and Status Register */\r
+#if(CY_PSOC3)\r
+ #define INTERRUPT_CSR ((reg8 *) CYREG_INTC_CSR_EN)\r
+ #define DISABLE_IRQ_SET ((uint8)(0x01u << 1u)) /* INTC_CSR_EN */\r
+ #define INTERRUPT_DISABLE_IRQ {*INTERRUPT_CSR |= DISABLE_IRQ_SET;}\r
+ #define INTERRUPT_ENABLE_IRQ {*INTERRUPT_CSR = (uint8)(~DISABLE_IRQ_SET);}\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
+#if defined(__ARMCC_VERSION)\r
+ #define CyGlobalIntEnable {__enable_irq();}\r
+ #define CyGlobalIntDisable {__disable_irq();}\r
+#elif defined(__GNUC__)\r
+ #define CyGlobalIntEnable {__asm("CPSIE i");}\r
+ #define CyGlobalIntDisable {__asm("CPSID i");}\r
+#elif defined(__C51__)\r
+ #define CyGlobalIntEnable {\\r
+ EA = 1u; \\r
+ INTERRUPT_ENABLE_IRQ\\r
+ }\r
+\r
+ #define CyGlobalIntDisable {\\r
+ INTERRUPT_DISABLE_IRQ; \\r
+ CY_NOP; \\r
+ EA = 0u;\\r
+ }\r
+#endif /* (__ARMCC_VERSION) */\r
+\r
+\r
+#ifdef CYREG_MLOGIC_CPU_SCR_CPU_SCR\r
+ #define CYDEV_HALT_CPU CY_SET_REG8(CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x01u)\r
+#else\r
+ #define CYDEV_HALT_CPU CY_SET_REG8(CYREG_MLOGIC_CPU_SCR, 0x01u)\r
+#endif /* (CYREG_MLOGIC_CPU_SCR_CPU_SCR) */\r
+\r
+\r
+#ifdef CYREG_MLOGIC_REV_ID_REV_ID\r
+ #define CYDEV_CHIP_REV_ACTUAL (CY_GET_REG8(CYREG_MLOGIC_REV_ID_REV_ID))\r
+#else\r
+ #define CYDEV_CHIP_REV_ACTUAL (CY_GET_REG8(CYREG_MLOGIC_REV_ID))\r
+#endif /* (CYREG_MLOGIC_REV_ID_REV_ID) */\r
+\r
+#define RESET_CR2 ((reg8 *) CYREG_RESET_CR2)\r
+\r
+\r
+/*******************************************************************************\r
+* System API constants\r
+*******************************************************************************/\r
+#define CY_CACHE_CONTROL_FLUSH (0x0004u)\r
+\r
+\r
+/*******************************************************************************\r
+* Interrupt API constants\r
+*******************************************************************************/\r
+#if(CY_PSOC5)\r
+\r
+ #define CY_INT_IRQ_BASE (16u)\r
+\r
+#elif (CY_PSOC3)\r
+\r
+ #define CY_INT_IRQ_BASE (0u)\r
+\r
+#endif /* (CY_PSOC5) */\r
+\r
+/* Valid range of interrupt 0-31 */\r
+#define CY_INT_NUMBER_MAX (31u)\r
+\r
+/* Valid range of system interrupt 0-15 */\r
+#define CY_INT_SYS_NUMBER_MAX (15u)\r
+\r
+/* Valid range of system priority 0-7 */\r
+#define CY_INT_PRIORITY_MAX (7u)\r
+\r
+/* Mask to get valid range of interrupt 0-31 */\r
+#define CY_INT_NUMBER_MASK (0x1Fu)\r
+\r
+/* Mask to get valid range of system priority 0-7 */\r
+#define CY_INT_PRIORITY_MASK (0x7u)\r
+\r
+/* Mask to get valid range of system interrupt 0-15 */\r
+#define CY_INT_SYS_NUMBER_MASK (0xFu)\r
+\r
+\r
+/*******************************************************************************\r
+* Interrupt Macros\r
+*******************************************************************************/\r
+\r
+#if(CY_PSOC5)\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CyIntEnable\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Enables the specified interrupt number.\r
+ *\r
+ * Parameters:\r
+ * number: Valid range [0-31]. Interrupt number\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ #define CyIntEnable(number) CY_SET_REG32(CY_INT_ENABLE_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CyIntDisable\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Disables the specified interrupt number.\r
+ *\r
+ * Parameters:\r
+ * number: Valid range [0-31]. Interrupt number.\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ #define CyIntDisable(number) CY_SET_REG32(CY_INT_CLEAR_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CyIntSetPending\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Forces the specified interrupt number to be pending.\r
+ *\r
+ * Parameters:\r
+ * number: Valid range [0-31]. Interrupt number.\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ #define CyIntSetPending(number) CY_SET_REG32(CY_INT_SET_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CyIntClearPending\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Clears any pending interrupt for the specified interrupt number.\r
+ *\r
+ * Parameters:\r
+ * number: Valid range [0-31]. Interrupt number.\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ #define CyIntClearPending(number) CY_SET_REG32(CY_INT_CLR_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number)))))\r
+\r
+\r
+#else /* PSoC3 */\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CyIntEnable\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Enables the specified interrupt number.\r
+ *\r
+ * Parameters:\r
+ * number: Valid range [0-31]. Interrupt number\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ #define CyIntEnable(number) CY_SET_REG8(CY_INT_SET_EN_INDX_PTR((number)), \\r
+ ((uint8)(1u << (0x07u & (number)))))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CyIntDisable\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Disables the specified interrupt number.\r
+ *\r
+ * Parameters:\r
+ * number: Valid range [0-31]. Interrupt number.\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ #define CyIntDisable(number) CY_SET_REG8(CY_INT_CLR_EN_INDX_PTR((number)), \\r
+ ((uint8)(1u << (0x07u & (number)))))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CyIntSetPending\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Forces the specified interrupt number to be pending.\r
+ *\r
+ * Parameters:\r
+ * number: Valid range [0-31]. Interrupt number.\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ #define CyIntSetPending(number) CY_SET_REG8(CY_INT_SET_PEND_INDX_PTR((number)), \\r
+ ((uint8)(1u << (0x07u & (number)))))\r
+\r
+\r
+ /*******************************************************************************\r
+ * Macro Name: CyIntClearPending\r
+ ********************************************************************************\r
+ * Summary:\r
+ * Clears any pending interrupt for the specified interrupt number.\r
+ *\r
+ * Parameters:\r
+ * number: Valid range [0-31]. Interrupt number.\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ #define CyIntClearPending(number) CY_SET_REG8(CY_INT_CLR_PEND_INDX_PTR((number)), \\r
+ ((uint8)(1u << (0x07u & (number)))))\r
+\r
+#endif /* (CY_PSOC5) */\r
+\r
+\r
+/*******************************************************************************\r
+* Following code are OBSOLETE and must not be used.\r
+*******************************************************************************/\r
+#define CYGlobalIntEnable CyGlobalIntEnable\r
+#define CYGlobalIntDisable CyGlobalIntDisable\r
+\r
+#define cymemset(s,c,n) memset((s),(c),(n))\r
+#define cymemcpy(d,s,n) memcpy((d),(s),(n))\r
+\r
+\r
+/*******************************************************************************\r
+* Following code are OBSOLETE and must not be used starting from cy_boot 3.0\r
+*******************************************************************************/\r
+#define MFGCFG_X32_TR_PTR (CY_CLK_XTAL32_TR_PTR)\r
+#define MFGCFG_X32_TR (CY_CLK_XTAL32_TR_REG)\r
+#define SLOWCLK_X32_TST_PTR (CY_CLK_XTAL32_TST_PTR)\r
+#define SLOWCLK_X32_TST (CY_CLK_XTAL32_TST_REG)\r
+#define SLOWCLK_X32_CR_PTR (CY_CLK_XTAL32_CR_PTR)\r
+#define SLOWCLK_X32_CR (CY_CLK_XTAL32_CR_REG)\r
+#define SLOWCLK_X32_CFG_PTR (CY_CLK_XTAL32_CFG_PTR)\r
+#define SLOWCLK_X32_CFG (CY_CLK_XTAL32_CFG_REG)\r
+\r
+#define X32_CONTROL_ANA_STAT (CY_CLK_XTAL32_CR_ANA_STAT)\r
+#define X32_CONTROL_DIG_STAT (0x10u)\r
+#define X32_CONTROL_LPM (CY_CLK_XTAL32_CR_LPM)\r
+#define X32_CONTROL_LPM_POSITION (1u)\r
+#define X32_CONTROL_X32EN (CY_CLK_XTAL32_CR_EN)\r
+#if(CY_PSOC3 || CY_PSOC5LP)\r
+ #define X32_CONTROL_PDBEN (CY_CLK_XTAL32_CR_PDBEN)\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+#define X32_TR_DPMODE (CY_CLK_XTAL32_TR_STARTUP)\r
+#define X32_TR_CLEAR (CY_CLK_XTAL32_TR_POWERDOWN)\r
+#define X32_TR_HPMODE (CY_CLK_XTAL32_TR_HIGH_POWER)\r
+#define X32_TR_LPMODE (CY_CLK_XTAL32_TR_LOW_POWER)\r
+#define X32_TST_SETALL (CY_CLK_XTAL32_TST_DEFAULT)\r
+#define X32_CFG_LP_BITS_MASK (CY_CLK_XTAL32_CFG_LP_MASK)\r
+#define X32_CFG_LP_DEFAULT (CY_CLK_XTAL32_CFG_LP_DEFAULT)\r
+#define X32_CFG_LOWPOWERMODE (0x80u)\r
+#define X32_CFG_LP_LOWPOWER (0x8u)\r
+#define CY_X32_HIGHPOWER_MODE (0u)\r
+#define CY_X32_LOWPOWER_MODE (1u)\r
+#define CY_XTAL32K_DIG_STAT (0x10u)\r
+#define CY_XTAL32K_STAT_FIELDS (0x30u)\r
+#define CY_XTAL32K_DIG_STAT_UNSTABLE (0u)\r
+#define CY_XTAL32K_ANA_STAT_UNSTABLE (0x0u)\r
+#define CY_XTAL32K_STATUS (0x20u)\r
+\r
+#define FASTCLK_XMHZ_CSR_PTR (CY_CLK_XMHZ_CSR_PTR)\r
+#define FASTCLK_XMHZ_CSR (CY_CLK_XMHZ_CSR_REG)\r
+#define FASTCLK_XMHZ_CFG0_PTR (CY_CLK_XMHZ_CFG0_PTR)\r
+#define FASTCLK_XMHZ_CFG0 (CY_CLK_XMHZ_CFG0_REG)\r
+#define FASTCLK_XMHZ_CFG1_PTR (CY_CLK_XMHZ_CFG1_PTR)\r
+#define FASTCLK_XMHZ_CFG1 (CY_CLK_XMHZ_CFG1_REG)\r
+#define FASTCLK_XMHZ_GAINMASK (CY_CLK_XMHZ_CFG0_XCFG_MASK)\r
+#define FASTCLK_XMHZ_VREFMASK (CY_CLK_XMHZ_CFG1_VREF_FB_MASK)\r
+#define FASTCLK_XMHZ_VREF_WD_MASK (CY_CLK_XMHZ_CFG1_VREF_WD_MASK)\r
+#define XMHZ_CONTROL_ENABLE (CY_CLK_XMHZ_CSR_ENABLE)\r
+#define X32_CONTROL_XERR_MASK (CY_CLK_XMHZ_CSR_XERR)\r
+#define X32_CONTROL_XERR_DIS (CY_CLK_XMHZ_CSR_XFB)\r
+#define X32_CONTROL_XERR_POSITION (7u)\r
+#define X32_CONTROL_FAULT_RECOVER (CY_CLK_XMHZ_CSR_XPROT)\r
+\r
+#define CYWDT_CFG (CY_WDT_CFG_PTR)\r
+#define CYWDT_CR (CY_WDT_CR_PTR)\r
+\r
+#define CYWDT_TICKS_MASK (CY_WDT_CFG_INTERVAL_MASK)\r
+#define CYWDT_RESET (CY_WDT_CFG_CTW_RESET)\r
+#define CYWDT_LPMODE_SHIFT (CY_WDT_CFG_LPMODE_SHIFT)\r
+#define CYWDT_LPMODE_MASK (CY_WDT_CFG_LPMODE_MASK)\r
+#define CYWDT_ENABLE_BIT (CY_WDT_CFG_WDR_EN)\r
+\r
+#define FASTCLK_PLL_CFG0_PTR (CY_CLK_PLL_CFG0_PTR)\r
+#define FASTCLK_PLL_CFG0 (CY_CLK_PLL_CFG0_REG)\r
+#define FASTCLK_PLL_SR_PTR (CY_CLK_PLL_SR_PTR)\r
+#define FASTCLK_PLL_SR (CY_CLK_PLL_SR_REG)\r
+\r
+#define MAX_FASTCLK_PLL_Q_VALUE (CY_CLK_PLL_MAX_Q_VALUE)\r
+#define MIN_FASTCLK_PLL_Q_VALUE (CY_CLK_PLL_MIN_Q_VALUE)\r
+#define MIN_FASTCLK_PLL_P_VALUE (CY_CLK_PLL_MIN_P_VALUE)\r
+#define MIN_FASTCLK_PLL_CUR_VALUE (CY_CLK_PLL_MIN_CUR_VALUE)\r
+#define MAX_FASTCLK_PLL_CUR_VALUE (CY_CLK_PLL_MAX_CUR_VALUE)\r
+\r
+#define PLL_CONTROL_ENABLE (CY_CLK_PLL_ENABLE)\r
+#define PLL_STATUS_LOCK (CY_CLK_PLL_LOCK_STATUS)\r
+#define PLL_STATUS_ENABLED (CY_CLK_PLL_ENABLE)\r
+#define PLL_CURRENT_POSITION (CY_CLK_PLL_CURRENT_POSITION)\r
+#define PLL_VCO_GAIN_2 (2u)\r
+\r
+#define FASTCLK_PLL_Q_PTR (CY_CLK_PLL_Q_PTR)\r
+#define FASTCLK_PLL_Q (CY_CLK_PLL_Q_REG)\r
+#define FASTCLK_PLL_P_PTR (CY_CLK_PLL_P_PTR)\r
+#define FASTCLK_PLL_P (CY_CLK_PLL_P_REG)\r
+#define FASTCLK_PLL_CFG1_PTR (CY_CLK_PLL_CFG1_REG)\r
+#define FASTCLK_PLL_CFG1 (CY_CLK_PLL_CFG1_REG)\r
+\r
+#define CY_VD_PRESISTENT_STATUS_REG (CY_VD_PERSISTENT_STATUS_REG)\r
+#define CY_VD_PRESISTENT_STATUS_PTR (CY_VD_PERSISTENT_STATUS_PTR)\r
+\r
+\r
+/*******************************************************************************\r
+* Following code are OBSOLETE and must not be used starting from cy_boot 3.20\r
+*******************************************************************************/\r
+\r
+#if(CY_PSOC5)\r
+\r
+ #define CYINT_IRQ_BASE (CY_INT_IRQ_BASE)\r
+\r
+ #define CYINT_VECT_TABLE (CY_INT_VECT_TABLE)\r
+ #define CYINT_PRIORITY (CY_INT_PRIORITY_PTR)\r
+ #define CYINT_ENABLE (CY_INT_ENABLE_PTR)\r
+ #define CYINT_CLEAR (CY_INT_CLEAR_PTR)\r
+ #define CYINT_SET_PEND (CY_INT_SET_PEND_PTR)\r
+ #define CYINT_CLR_PEND (CY_INT_CLR_PEND_PTR)\r
+ #define CACHE_CC_CTL (CY_CACHE_CONTROL_PTR)\r
+\r
+#elif (CY_PSOC3)\r
+\r
+ #define CYINT_IRQ_BASE (CY_INT_IRQ_BASE)\r
+\r
+ #define CYINT_VECT_TABLE (CY_INT_VECT_TABLE)\r
+ #define CYINT_PRIORITY (CY_INT_PRIORITY_PTR)\r
+ #define CYINT_ENABLE (CY_INT_ENABLE_PTR)\r
+ #define CYINT_CLEAR (CY_INT_CLEAR_PTR)\r
+ #define CYINT_SET_PEND (CY_INT_SET_PEND_PTR)\r
+ #define CYINT_CLR_PEND (CY_INT_CLR_PEND_PTR)\r
+\r
+#endif /* (CY_PSOC5) */\r
+\r
+\r
+/*******************************************************************************\r
+* Following code are OBSOLETE and must not be used starting from cy_boot 3.30\r
+*******************************************************************************/\r
+#define BUS_AMASK_CLEAR (0xF0u)\r
+#define BUS_DMASK_CLEAR (0x00u)\r
+#define CLKDIST_LD_LOAD_SET (0x01u)\r
+#define CLKDIST_WRK0_MASK_SET (0x80u) /* Enable shadow loads */\r
+#define MASTERCLK_DIVIDER_VALUE (7u)\r
+#define CLKDIST_BCFG2_SSS_SET (0x40u) /* Sync source is same frequency */\r
+#define MASTER_CLK_SRC_CLEAR (0xFCu)\r
+#define IMO_DOUBLER_ENABLE (0x10u)\r
+#define CLOCK_IMO_IMO (0x20u)\r
+#define CLOCK_IMO2X_XTAL (0x40u)\r
+#define CLOCK_IMO_RANGE_CLEAR (0xF8u)\r
+#define CLOCK_CONTROL_DIST_MASK (0xFCu)\r
+\r
+\r
+#define CLKDIST_AMASK (*(reg8 *) CYREG_CLKDIST_AMASK)\r
+#define CLKDIST_AMASK_PTR ( (reg8 *) CYREG_CLKDIST_AMASK)\r
+#define CLKDIST_DMASK_PTR ( (reg8 *) CYREG_CLKDIST_DMASK)\r
+#define CLKDIST_DMASK (*(reg8 *) CYREG_CLKDIST_DMASK)\r
+#define CLKDIST_BCFG2_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2)\r
+#define CLKDIST_BCFG2 (*(reg8 *) CYREG_CLKDIST_BCFG2)\r
+#define CLKDIST_WRK0_PTR ( (reg8 *) CYREG_CLKDIST_WRK0)\r
+#define CLKDIST_WRK0 (*(reg8 *) CYREG_CLKDIST_WRK0)\r
+#define CLKDIST_LD_PTR ( (reg8 *) CYREG_CLKDIST_LD)\r
+#define CLKDIST_LD (*(reg8 *) CYREG_CLKDIST_LD)\r
+#define CLKDIST_BCFG0_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0)\r
+#define CLKDIST_BCFG0 (*(reg8 *) CYREG_CLKDIST_BCFG0)\r
+#define CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0)\r
+#define CLKDIST_MSTR0 (*(reg8 *) CYREG_CLKDIST_MSTR0)\r
+#define FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR)\r
+#define FASTCLK_IMO_CR (*(reg8 *) CYREG_FASTCLK_IMO_CR)\r
+#define CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR)\r
+#define CLKDIST_CR (*(reg8 *) CYREG_CLKDIST_CR)\r
+\r
+#endif /* (CY_BOOT_CYLIB_H) */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: CySpc.c\r
+* Version 3.40\r
+*\r
+* Description:\r
+* Provides an API for the System Performance Component.\r
+* The SPC functions are not meant to be called directly by the user\r
+* application.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "CySpc.h"\r
+\r
+#define CY_SPC_KEY_ONE (0xB6u)\r
+#define CY_SPC_KEY_TWO(x) ((uint8) (((uint16) 0xD3u) + ((uint16) (x))))\r
+\r
+/* Command Codes */\r
+#define CY_SPC_CMD_LD_BYTE (0x00u)\r
+#define CY_SPC_CMD_LD_MULTI_BYTE (0x01u)\r
+#define CY_SPC_CMD_LD_ROW (0x02u)\r
+#define CY_SPC_CMD_RD_BYTE (0x03u)\r
+#define CY_SPC_CMD_RD_MULTI_BYTE (0x04u)\r
+#define CY_SPC_CMD_WR_ROW (0x05u)\r
+#define CY_SPC_CMD_WR_USER_NVL (0x06u)\r
+#define CY_SPC_CMD_PRG_ROW (0x07u)\r
+#define CY_SPC_CMD_ER_SECTOR (0x08u)\r
+#define CY_SPC_CMD_ER_ALL (0x09u)\r
+#define CY_SPC_CMD_RD_HIDDEN (0x0Au)\r
+#define CY_SPC_CMD_PRG_PROTECT (0x0Bu)\r
+#define CY_SPC_CMD_CHECKSUM (0x0Cu)\r
+#define CY_SPC_CMD_DWNLD_ALGORITHM (0x0Du)\r
+#define CY_SPC_CMD_GET_TEMP (0x0Eu)\r
+#define CY_SPC_CMD_GET_ADC (0x0Fu)\r
+#define CY_SPC_CMD_RD_NVL_VOLATILE (0x10u)\r
+#define CY_SPC_CMD_SETUP_TS (0x11u)\r
+#define CY_SPC_CMD_DISABLE_TS (0x12u)\r
+#define CY_SPC_CMD_ER_ROW (0x13u)\r
+\r
+/* Enable bit in Active and Alternate Active mode templates */\r
+#define PM_SPC_PM_EN (0x08u)\r
+\r
+/* Gate calls to the SPC. */\r
+uint8 SpcLockState = CY_SPC_UNLOCKED;\r
+\r
+\r
+#if(CY_PSOC5LP)\r
+\r
+ /***************************************************************************\r
+ * The wait-state pipeline must be enabled prior to accessing the SPC\r
+ * register interface regardless of CPU frequency. The CySpcLock() saves\r
+ * current wait-state pipeline state and enables it. The CySpcUnlock()\r
+ * function, which must be called after SPC transaction, restores original\r
+ * state.\r
+ ***************************************************************************/\r
+ static uint8 spcWaitPipeBypass = 0u;\r
+\r
+#endif /* (CY_PSOC5LP) */\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CySpcStart\r
+********************************************************************************\r
+* Summary:\r
+* Starts the SPC.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CySpcStart(void) \r
+{\r
+ /* Save current global interrupt enable and disable it */\r
+ uint8 interruptState = CyEnterCriticalSection();\r
+\r
+ CY_SPC_PM_ACT_REG |= PM_SPC_PM_EN;\r
+ CY_SPC_PM_STBY_REG |= PM_SPC_PM_EN;\r
+\r
+ /* Restore global interrupt enable state */\r
+ CyExitCriticalSection(interruptState);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CySpcStop\r
+********************************************************************************\r
+* Summary:\r
+* Stops the SPC.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CySpcStop(void) \r
+{\r
+ /* Save current global interrupt enable and disable it */\r
+ uint8 interruptState = CyEnterCriticalSection();\r
+\r
+ CY_SPC_PM_ACT_REG &= ((uint8)(~PM_SPC_PM_EN));\r
+ CY_SPC_PM_STBY_REG &= ((uint8)(~PM_SPC_PM_EN));\r
+\r
+ /* Restore global interrupt enable state */\r
+ CyExitCriticalSection(interruptState);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CySpcReadData\r
+********************************************************************************\r
+* Summary:\r
+* Reads data from the SPC.\r
+*\r
+* Parameters:\r
+* uint8 buffer:\r
+* Address to store data read.\r
+*\r
+* uint8 size:\r
+* Number of bytes to read from the SPC.\r
+*\r
+* Return:\r
+* uint8:\r
+* The number of bytes read from the SPC.\r
+*\r
+*******************************************************************************/\r
+uint8 CySpcReadData(uint8 buffer[], uint8 size) \r
+{\r
+ uint8 i;\r
+\r
+ for(i = 0u; i < size; i++)\r
+ {\r
+ while(!CY_SPC_DATA_READY)\r
+ {\r
+ CyDelayUs(1u);\r
+ }\r
+ buffer[i] = CY_SPC_CPU_DATA_REG;\r
+ }\r
+\r
+ return(i);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CySpcLoadMultiByte\r
+********************************************************************************\r
+* Summary:\r
+* Loads 1 to 32 bytes of data into the row latch of a Flash/EEPROM array.\r
+*\r
+* Parameters:\r
+* uint8 array:\r
+* Id of the array.\r
+*\r
+* uint16 address:\r
+* Flash/eeprom addrress\r
+*\r
+* uint8* buffer:\r
+* Data to load to the row latch\r
+*\r
+* uint16 number:\r
+* Number bytes to load.\r
+*\r
+* Return:\r
+* CYRET_STARTED\r
+* CYRET_CANCELED\r
+* CYRET_LOCKED\r
+* CYRET_BAD_PARAM\r
+*\r
+*******************************************************************************/\r
+cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size) \r
+{\r
+ cystatus status = CYRET_STARTED;\r
+ uint8 i;\r
+\r
+ /***************************************************************************\r
+ * Check if number is correct for array. Number must be less than\r
+ * 32 for Flash or less than 16 for EEPROM.\r
+ ***************************************************************************/\r
+ if(((array < CY_SPC_LAST_FLASH_ARRAYID) && (size < 32u)) ||\r
+ ((array > CY_SPC_LAST_FLASH_ARRAYID) && (size < 16u)))\r
+ {\r
+ if(CY_SPC_IDLE)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_MULTI_BYTE);\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_MULTI_BYTE;\r
+\r
+ if(CY_SPC_BUSY)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = array;\r
+ CY_SPC_CPU_DATA_REG = 1u & HI8(address);\r
+ CY_SPC_CPU_DATA_REG = LO8(address);\r
+ CY_SPC_CPU_DATA_REG = ((uint8)(size - 1u));\r
+\r
+ for(i = 0u; i < size; i++)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = buffer[i];\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_CANCELED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_BAD_PARAM;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CySpcLoadRow\r
+********************************************************************************\r
+* Summary:\r
+* Loads a row of data into the row latch of a Flash/EEPROM array.\r
+*\r
+* Parameters:\r
+* uint8 array:\r
+* Id of the array.\r
+*\r
+* uint8* buffer:\r
+* Data to be loaded to the row latch\r
+*\r
+* uint8 size:\r
+* The number of data bytes that the SPC expects to be written. Depends on the\r
+* type of the array and, if the array is Flash, whether ECC is being enabled\r
+* or not. There are following values: flash row latch size with ECC enabled,\r
+* flash row latch size with ECC disabled and EEPROM row latch size.\r
+*\r
+* Return:\r
+* CYRET_STARTED\r
+* CYRET_CANCELED\r
+* CYRET_LOCKED\r
+*\r
+*******************************************************************************/\r
+cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size)\r
+{\r
+ cystatus status = CYRET_STARTED;\r
+ uint16 i;\r
+\r
+ /* Make sure the SPC is ready to accept command */\r
+ if(CY_SPC_IDLE)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW);\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW;\r
+\r
+ /* Make sure the command was accepted */\r
+ if(CY_SPC_BUSY)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = array;\r
+\r
+ for(i = 0u; i < size; i++)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = buffer[i];\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_CANCELED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CySpcWriteRow\r
+********************************************************************************\r
+* Summary:\r
+* Erases then programs a row in Flash/EEPROM with data in row latch.\r
+*\r
+* Parameters:\r
+* uint8 array:\r
+* Id of the array.\r
+*\r
+* uint16 address:\r
+* flash/eeprom addrress\r
+*\r
+* uint8 tempPolarity:\r
+* temperature polarity.\r
+* 1: the Temp Magnitude is interpreted as a positive value\r
+* 0: the Temp Magnitude is interpreted as a negative value\r
+*\r
+* uint8 tempMagnitude:\r
+* temperature magnitude.\r
+*\r
+* Return:\r
+* CYRET_STARTED\r
+* CYRET_CANCELED\r
+* CYRET_LOCKED\r
+*\r
+*******************************************************************************/\r
+cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\r
+{\r
+ cystatus status = CYRET_STARTED;\r
+\r
+ /* Make sure the SPC is ready to accept command */\r
+ if(CY_SPC_IDLE)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_WR_ROW);\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_CMD_WR_ROW;\r
+\r
+ /* Make sure the command was accepted */\r
+ if(CY_SPC_BUSY)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = array;\r
+ CY_SPC_CPU_DATA_REG = HI8(address);\r
+ CY_SPC_CPU_DATA_REG = LO8(address);\r
+ CY_SPC_CPU_DATA_REG = tempPolarity;\r
+ CY_SPC_CPU_DATA_REG = tempMagnitude;\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_CANCELED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CySpcEraseSector\r
+********************************************************************************\r
+* Summary:\r
+* Erases all data in the addressed sector (block of 64 rows).\r
+*\r
+* Parameters:\r
+* uint8 array:\r
+* Id of the array.\r
+*\r
+* uint8 sectorNumber:\r
+* Zero based sector number within Flash/EEPROM array\r
+*\r
+* Return:\r
+* CYRET_STARTED\r
+* CYRET_CANCELED\r
+* CYRET_LOCKED\r
+*\r
+*******************************************************************************/\r
+cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber)\r
+{\r
+ cystatus status = CYRET_STARTED;\r
+\r
+ /* Make sure the SPC is ready to accept command */\r
+ if(CY_SPC_IDLE)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_ER_SECTOR);\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_CMD_ER_SECTOR;\r
+\r
+ /* Make sure the command was accepted */\r
+ if(CY_SPC_BUSY)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = array;\r
+ CY_SPC_CPU_DATA_REG = sectorNumber;\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_CANCELED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CySpcGetTemp\r
+********************************************************************************\r
+* Summary:\r
+* Returns the internal die temperature\r
+*\r
+* Parameters:\r
+* uint8 numSamples:\r
+* Number of samples. Valid values are 1-5, resulting in 2 - 32 samples\r
+* respectively.\r
+*\r
+* uint16 timerPeriod:\r
+* Number of ADC ACLK cycles. A valid 14 bit value is accepted, higher 2 bits\r
+* of 16 bit values are ignored.\r
+*\r
+* uint8 clkDivSelect:\r
+* ADC ACLK clock divide value. Valid values are 2 - 225.\r
+*\r
+* Return:\r
+* CYRET_STARTED\r
+* CYRET_CANCELED\r
+* CYRET_LOCKED\r
+*\r
+*******************************************************************************/\r
+#if(CY_PSOC5A)\r
+cystatus CySpcGetTemp(uint8 numSamples, uint16 timerPeriod, uint8 clkDivSelect)\r
+#else\r
+cystatus CySpcGetTemp(uint8 numSamples)\r
+#endif /* (CY_PSOC5A) */\r
+{\r
+ cystatus status = CYRET_STARTED;\r
+\r
+ /* Make sure the SPC is ready to accept command */\r
+ if(CY_SPC_IDLE)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE;\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_GET_TEMP);\r
+ CY_SPC_CPU_DATA_REG = CY_SPC_CMD_GET_TEMP;\r
+\r
+ /* Make sure the command was accepted */\r
+ if(CY_SPC_BUSY)\r
+ {\r
+ CY_SPC_CPU_DATA_REG = numSamples;\r
+\r
+ #if(CY_PSOC5A)\r
+ CY_SPC_CPU_DATA_REG = HI8(timerPeriod);\r
+ CY_SPC_CPU_DATA_REG = LO8(timerPeriod);\r
+ CY_SPC_CPU_DATA_REG = clkDivSelect;\r
+ #endif /* (CY_PSOC5A) */\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_CANCELED;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ status = CYRET_LOCKED;\r
+ }\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CySpcLock\r
+********************************************************************************\r
+* Summary:\r
+* Locks the SPC so it can not be used by someone else:\r
+* - Saves wait-pipeline enable state and enable pipeline (PSoC5)\r
+*\r
+* Parameters:\r
+* Note\r
+*\r
+* Return:\r
+* CYRET_SUCCESS - if the resource was free.\r
+* CYRET_LOCKED - if the SPC is in use.\r
+*\r
+*******************************************************************************/\r
+cystatus CySpcLock(void)\r
+{\r
+ cystatus status = CYRET_LOCKED;\r
+ uint8 interruptState;\r
+\r
+ /* Enter critical section */\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ if(CY_SPC_UNLOCKED == SpcLockState)\r
+ {\r
+ SpcLockState = CY_SPC_LOCKED;\r
+ status = CYRET_SUCCESS;\r
+\r
+ #if(CY_PSOC5LP)\r
+\r
+ if(0u != (CY_SPC_CPU_WAITPIPE_REG & CY_SPC_CPU_WAITPIPE_BYPASS))\r
+ {\r
+ /* Enable pipeline registers */\r
+ CY_SPC_CPU_WAITPIPE_REG &= ((uint32)(~CY_SPC_CPU_WAITPIPE_BYPASS));\r
+\r
+ /* At least 2 NOP instructions are recommended */\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+\r
+ spcWaitPipeBypass = CY_SPC_CPU_WAITPIPE_BYPASS;\r
+ }\r
+\r
+ #endif /* (CY_PSOC5LP) */\r
+ }\r
+\r
+ /* Exit critical section */\r
+ CyExitCriticalSection(interruptState);\r
+\r
+ return(status);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CySpcUnlock\r
+********************************************************************************\r
+* Summary:\r
+* Unlocks the SPC so it can be used by someone else:\r
+* - Restores wait-pipeline enable state (PSoC5)\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CySpcUnlock(void)\r
+{\r
+ uint8 interruptState;\r
+\r
+ /* Enter critical section */\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ /* Release the SPC object */\r
+ SpcLockState = CY_SPC_UNLOCKED;\r
+\r
+ #if(CY_PSOC5LP)\r
+\r
+ if(CY_SPC_CPU_WAITPIPE_BYPASS == spcWaitPipeBypass)\r
+ {\r
+ /* Force to bypass pipeline registers */\r
+ CY_SPC_CPU_WAITPIPE_REG |= CY_SPC_CPU_WAITPIPE_BYPASS;\r
+\r
+ /* At least 2 NOP instructions are recommended */\r
+ CY_NOP;\r
+ CY_NOP;\r
+ CY_NOP;\r
+\r
+ spcWaitPipeBypass = 0u;\r
+ }\r
+\r
+ #endif /* (CY_PSOC5LP) */\r
+\r
+ /* Exit critical section */\r
+ CyExitCriticalSection(interruptState);\r
+}\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: CySpc.c\r
+* Version 3.40\r
+*\r
+* Description:\r
+* Provides definitions for the System Performance Component API.\r
+* The SPC functions are not meant to be called directly by the user\r
+* application.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_BOOT_CYSPC_H)\r
+#define CY_BOOT_CYSPC_H\r
+\r
+#include "cytypes.h"\r
+#include "CyLib.h"\r
+#include "cydevice_trm.h"\r
+\r
+\r
+/***************************************\r
+* Global Variables\r
+***************************************/\r
+extern uint8 SpcLockState;\r
+\r
+\r
+/***************************************\r
+* Function Prototypes\r
+***************************************/\r
+void CySpcStart(void);\r
+void CySpcStop(void);\r
+uint8 CySpcReadData(uint8 buffer[], uint8 size);\r
+cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size) ;\r
+cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size);\r
+cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude) ;\r
+cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber);\r
+\r
+#if(CY_PSOC5A)\r
+ cystatus CySpcGetTemp(uint8 numSamples, uint16 timerPeriod, uint8 clkDivSelect);\r
+#else\r
+ cystatus CySpcGetTemp(uint8 numSamples);\r
+#endif /* (CY_PSOC5A) */\r
+\r
+\r
+cystatus CySpcLock(void);\r
+void CySpcUnlock(void);\r
+\r
+\r
+/***************************************\r
+* API Constants\r
+***************************************/\r
+\r
+#define CY_SPC_LOCKED (0x01u)\r
+#define CY_SPC_UNLOCKED (0x00u)\r
+\r
+/*******************************************************************************\r
+* The Array ID indicates the unique ID of the SONOS array being accessed:\r
+* - 0x00-0x3E : Flash Arrays\r
+* - 0x3F : Selects all Flash arrays simultaneously\r
+* - 0x40-0x7F : Embedded EEPROM Arrays\r
+*******************************************************************************/\r
+#define CY_SPC_FIRST_FLASH_ARRAYID (0x00u)\r
+#define CY_SPC_LAST_FLASH_ARRAYID (0x3Fu)\r
+#define CY_SPC_FIRST_EE_ARRAYID (0x40u)\r
+#define CY_SPC_LAST_EE_ARRAYID (0x7Fu)\r
+\r
+\r
+#define CY_SPC_STATUS_DATA_READY_MASK (0x01u)\r
+#define CY_SPC_STATUS_IDLE_MASK (0x02u)\r
+#define CY_SPC_STATUS_CODE_MASK (0xFCu)\r
+#define CY_SPC_STATUS_CODE_SHIFT (0x02u)\r
+\r
+/* Status codes for the SPC. */\r
+#define CY_SPC_STATUS_SUCCESS (0x00u) /* Operation Successful */\r
+#define CY_SPC_STATUS_INVALID_ARRAY_ID (0x01u) /* Invalid Array ID for given command */\r
+#define CY_SPC_STATUS_INVALID_2BYTEKEY (0x02u) /* Invalid 2-byte key */\r
+#define CY_SPC_STATUS_ARRAY_ASLEEP (0x03u) /* Addressed Array is Asleep */\r
+#define CY_SPC_STATUS_EXTERN_ACCESS (0x04u) /* External Access Failure (SPC is not in external access mode) */\r
+#define CY_SPC_STATUS_INVALID_NUMBER (0x05u) /* Invalid 'N' Value for given command */\r
+#define CY_SPC_STATUS_TEST_MODE (0x06u) /* Test Mode Failure (SPC is not in test mode) */\r
+#define CY_SPC_STATUS_ALG_CSUM (0x07u) /* Smart Write Algorithm Checksum Failure */\r
+#define CY_SPC_STATUS_PARAM_CSUM (0x08u) /* Smart Write Parameter Checksum Failure */\r
+#define CY_SPC_STATUS_PROTECTION (0x09u) /* Protection Check Failure */\r
+#define CY_SPC_STATUS_ADDRESS_PARAM (0x0Au) /* Invalid Address parameter for the given command */\r
+#define CY_SPC_STATUS_COMMAND_CODE (0x0Bu) /* Invalid Command Code */\r
+#define CY_SPC_STATUS_ROW_ID (0x0Cu) /* Invalid Row ID parameter for given command */\r
+#define CY_SPC_STATUS_TADC_INPUT (0x0Du) /* Invalid input value for Get Temp & Get ADC commands */\r
+#define CY_SPC_STATUS_BUSY (0xFFu) /* SPC is busy */\r
+\r
+#if(CY_PSOC5LP)\r
+\r
+ /* Wait-state pipeline */\r
+ #define CY_SPC_CPU_WAITPIPE_BYPASS ((uint32)0x01u)\r
+\r
+#endif /* (CY_PSOC5LP) */\r
+\r
+\r
+/***************************************\r
+* Registers\r
+***************************************/\r
+\r
+/* SPC CPU Data Register */\r
+#define CY_SPC_CPU_DATA_REG (* (reg8 *) CYREG_SPC_CPU_DATA )\r
+#define CY_SPC_CPU_DATA_PTR ( (reg8 *) CYREG_SPC_CPU_DATA )\r
+\r
+/* SPC Status Register */\r
+#define CY_SPC_STATUS_REG (* (reg8 *) CYREG_SPC_SR )\r
+#define CY_SPC_STATUS_PTR ( (reg8 *) CYREG_SPC_SR )\r
+\r
+/* Active Power Mode Configuration Register 0 */\r
+#define CY_SPC_PM_ACT_REG (* (reg8 *) CYREG_PM_ACT_CFG0 )\r
+#define CY_SPC_PM_ACT_PTR ( (reg8 *) CYREG_PM_ACT_CFG0 )\r
+\r
+/* Standby Power Mode Configuration Register 0 */\r
+#define CY_SPC_PM_STBY_REG (* (reg8 *) CYREG_PM_STBY_CFG0 )\r
+#define CY_SPC_PM_STBY_PTR ( (reg8 *) CYREG_PM_STBY_CFG0 )\r
+\r
+#if(CY_PSOC5LP)\r
+\r
+ /* Wait State Pipeline */\r
+ #define CY_SPC_CPU_WAITPIPE_REG (* (reg32 *) CYREG_PANTHER_WAITPIPE )\r
+ #define CY_SPC_CPU_WAITPIPE_PTR ( (reg32 *) CYREG_PANTHER_WAITPIPE )\r
+\r
+#endif /* (CY_PSOC5LP) */\r
+\r
+\r
+/***************************************\r
+* Macros\r
+***************************************/\r
+#define CY_SPC_IDLE (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK))\r
+#define CY_SPC_BUSY (0u == (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK))\r
+#define CY_SPC_DATA_READY (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_DATA_READY_MASK))\r
+\r
+/* SPC must be in idle state in order to obtain correct status */\r
+#define CY_SPC_READ_STATUS (CY_SPC_IDLE ? \\r
+ ((uint8)(CY_SPC_STATUS_REG >> CY_SPC_STATUS_CODE_SHIFT)) : \\r
+ ((uint8) CY_SPC_STATUS_BUSY))\r
+\r
+\r
+/*******************************************************************************\r
+* Following code are OBSOLETE and must not be used starting from cy_boot 3.0\r
+*******************************************************************************/\r
+#define FIRST_FLASH_ARRAYID (CY_SPC_FIRST_FLASH_ARRAYID)\r
+#define LAST_FLASH_ARRAYID (CY_SPC_LAST_FLASH_ARRAYID)\r
+#define FIRST_EE_ARRAYID (CY_SPC_FIRST_EE_ARRAYID)\r
+#define LAST_EE_ARRAYID (CY_SPC_LAST_EE_ARRAYID)\r
+#define SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE)\r
+#define SIZEOF_FLASH_ROW (CYDEV_FLS_ROW_SIZE)\r
+#define SIZEOF_EEPROM_ROW (CYDEV_EEPROM_ROW_SIZE)\r
+\r
+\r
+#endif /* (CY_BOOT_CYSPC_H) */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: LED1.c \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file contains API to enable firmware control of a Pins component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "cytypes.h"\r
+#include "LED1.h"\r
+\r
+/* APIs are not generated for P15[7:6] on PSoC 5 */\r
+#if !(CY_PSOC5A &&\\r
+ LED1__PORT == 15 && ((LED1__MASK & 0xC0) != 0))\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: LED1_Write\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Assign a new value to the digital port's data output register. \r
+*\r
+* Parameters: \r
+* prtValue: The value to be assigned to the Digital Port. \r
+*\r
+* Return: \r
+* None\r
+* \r
+*******************************************************************************/\r
+void LED1_Write(uint8 value) \r
+{\r
+ uint8 staticBits = (LED1_DR & (uint8)(~LED1_MASK));\r
+ LED1_DR = staticBits | ((uint8)(value << LED1_SHIFT) & LED1_MASK);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: LED1_SetDriveMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Change the drive mode on the pins of the port.\r
+* \r
+* Parameters: \r
+* mode: Change the pins to this drive mode.\r
+*\r
+* Return: \r
+* None\r
+*\r
+*******************************************************************************/\r
+void LED1_SetDriveMode(uint8 mode) \r
+{\r
+ CyPins_SetPinDriveMode(LED1_0, mode);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: LED1_Read\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value on the pins of the Digital Port in right justified \r
+* form.\r
+*\r
+* Parameters: \r
+* None\r
+*\r
+* Return: \r
+* Returns the current value of the Digital Port as a right justified number\r
+* \r
+* Note:\r
+* Macro LED1_ReadPS calls this function. \r
+* \r
+*******************************************************************************/\r
+uint8 LED1_Read(void) \r
+{\r
+ return (LED1_PS & LED1_MASK) >> LED1_SHIFT;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: LED1_ReadDataReg\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value assigned to a Digital Port's data output register\r
+*\r
+* Parameters: \r
+* None \r
+*\r
+* Return: \r
+* Returns the current value assigned to the Digital Port's data output register\r
+* \r
+*******************************************************************************/\r
+uint8 LED1_ReadDataReg(void) \r
+{\r
+ return (LED1_DR & LED1_MASK) >> LED1_SHIFT;\r
+}\r
+\r
+\r
+/* If Interrupts Are Enabled for this Pins component */ \r
+#if defined(LED1_INTSTAT) \r
+\r
+ /*******************************************************************************\r
+ * Function Name: LED1_ClearInterrupt\r
+ ********************************************************************************\r
+ * Summary:\r
+ * Clears any active interrupts attached to port and returns the value of the \r
+ * interrupt status register.\r
+ *\r
+ * Parameters: \r
+ * None \r
+ *\r
+ * Return: \r
+ * Returns the value of the interrupt status register\r
+ * \r
+ *******************************************************************************/\r
+ uint8 LED1_ClearInterrupt(void) \r
+ {\r
+ return (LED1_INTSTAT & LED1_MASK) >> LED1_SHIFT;\r
+ }\r
+\r
+#endif /* If Interrupts Are Enabled for this Pins component */ \r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+ \r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: LED1.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_LED1_H) /* Pins LED1_H */\r
+#define CY_PINS_LED1_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+#include "cypins.h"\r
+#include "LED1_aliases.h"\r
+\r
+/* Check to see if required defines such as CY_PSOC5A are available */\r
+/* They are defined starting with cy_boot v3.0 */\r
+#if !defined (CY_PSOC5A)\r
+ #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5A) */\r
+\r
+/* APIs are not generated for P15[7:6] */\r
+#if !(CY_PSOC5A &&\\r
+ LED1__PORT == 15 && ((LED1__MASK & 0xC0) != 0))\r
+\r
+\r
+/***************************************\r
+* Function Prototypes \r
+***************************************/ \r
+\r
+void LED1_Write(uint8 value) ;\r
+void LED1_SetDriveMode(uint8 mode) ;\r
+uint8 LED1_ReadDataReg(void) ;\r
+uint8 LED1_Read(void) ;\r
+uint8 LED1_ClearInterrupt(void) ;\r
+\r
+\r
+/***************************************\r
+* API Constants \r
+***************************************/\r
+\r
+/* Drive Modes */\r
+#define LED1_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+#define LED1_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+#define LED1_DM_RES_UP PIN_DM_RES_UP\r
+#define LED1_DM_RES_DWN PIN_DM_RES_DWN\r
+#define LED1_DM_OD_LO PIN_DM_OD_LO\r
+#define LED1_DM_OD_HI PIN_DM_OD_HI\r
+#define LED1_DM_STRONG PIN_DM_STRONG\r
+#define LED1_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+\r
+/* Digital Port Constants */\r
+#define LED1_MASK LED1__MASK\r
+#define LED1_SHIFT LED1__SHIFT\r
+#define LED1_WIDTH 1u\r
+\r
+\r
+/***************************************\r
+* Registers \r
+***************************************/\r
+\r
+/* Main Port Registers */\r
+/* Pin State */\r
+#define LED1_PS (* (reg8 *) LED1__PS)\r
+/* Data Register */\r
+#define LED1_DR (* (reg8 *) LED1__DR)\r
+/* Port Number */\r
+#define LED1_PRT_NUM (* (reg8 *) LED1__PRT) \r
+/* Connect to Analog Globals */ \r
+#define LED1_AG (* (reg8 *) LED1__AG) \r
+/* Analog MUX bux enable */\r
+#define LED1_AMUX (* (reg8 *) LED1__AMUX) \r
+/* Bidirectional Enable */ \r
+#define LED1_BIE (* (reg8 *) LED1__BIE)\r
+/* Bit-mask for Aliased Register Access */\r
+#define LED1_BIT_MASK (* (reg8 *) LED1__BIT_MASK)\r
+/* Bypass Enable */\r
+#define LED1_BYP (* (reg8 *) LED1__BYP)\r
+/* Port wide control signals */ \r
+#define LED1_CTL (* (reg8 *) LED1__CTL)\r
+/* Drive Modes */\r
+#define LED1_DM0 (* (reg8 *) LED1__DM0) \r
+#define LED1_DM1 (* (reg8 *) LED1__DM1)\r
+#define LED1_DM2 (* (reg8 *) LED1__DM2) \r
+/* Input Buffer Disable Override */\r
+#define LED1_INP_DIS (* (reg8 *) LED1__INP_DIS)\r
+/* LCD Common or Segment Drive */\r
+#define LED1_LCD_COM_SEG (* (reg8 *) LED1__LCD_COM_SEG)\r
+/* Enable Segment LCD */\r
+#define LED1_LCD_EN (* (reg8 *) LED1__LCD_EN)\r
+/* Slew Rate Control */\r
+#define LED1_SLW (* (reg8 *) LED1__SLW)\r
+\r
+/* DSI Port Registers */\r
+/* Global DSI Select Register */\r
+#define LED1_PRTDSI__CAPS_SEL (* (reg8 *) LED1__PRTDSI__CAPS_SEL) \r
+/* Double Sync Enable */\r
+#define LED1_PRTDSI__DBL_SYNC_IN (* (reg8 *) LED1__PRTDSI__DBL_SYNC_IN) \r
+/* Output Enable Select Drive Strength */\r
+#define LED1_PRTDSI__OE_SEL0 (* (reg8 *) LED1__PRTDSI__OE_SEL0) \r
+#define LED1_PRTDSI__OE_SEL1 (* (reg8 *) LED1__PRTDSI__OE_SEL1) \r
+/* Port Pin Output Select Registers */\r
+#define LED1_PRTDSI__OUT_SEL0 (* (reg8 *) LED1__PRTDSI__OUT_SEL0) \r
+#define LED1_PRTDSI__OUT_SEL1 (* (reg8 *) LED1__PRTDSI__OUT_SEL1) \r
+/* Sync Output Enable Registers */\r
+#define LED1_PRTDSI__SYNC_OUT (* (reg8 *) LED1__PRTDSI__SYNC_OUT) \r
+\r
+\r
+#if defined(LED1__INTSTAT) /* Interrupt Registers */\r
+\r
+ #define LED1_INTSTAT (* (reg8 *) LED1__INTSTAT)\r
+ #define LED1_SNAP (* (reg8 *) LED1__SNAP)\r
+\r
+#endif /* Interrupt Registers */\r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+#endif /* CY_PINS_LED1_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: LED1.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_LED1_ALIASES_H) /* Pins LED1_ALIASES_H */\r
+#define CY_PINS_LED1_ALIASES_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+\r
+\r
+/***************************************\r
+* Constants \r
+***************************************/\r
+#define LED1_0 LED1__0__PC\r
+\r
+#endif /* End Pins LED1_ALIASES_H */\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: PARITY_EN.c \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file contains API to enable firmware control of a Pins component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "cytypes.h"\r
+#include "PARITY_EN.h"\r
+\r
+/* APIs are not generated for P15[7:6] on PSoC 5 */\r
+#if !(CY_PSOC5A &&\\r
+ PARITY_EN__PORT == 15 && ((PARITY_EN__MASK & 0xC0) != 0))\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: PARITY_EN_Write\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Assign a new value to the digital port's data output register. \r
+*\r
+* Parameters: \r
+* prtValue: The value to be assigned to the Digital Port. \r
+*\r
+* Return: \r
+* None\r
+* \r
+*******************************************************************************/\r
+void PARITY_EN_Write(uint8 value) \r
+{\r
+ uint8 staticBits = (PARITY_EN_DR & (uint8)(~PARITY_EN_MASK));\r
+ PARITY_EN_DR = staticBits | ((uint8)(value << PARITY_EN_SHIFT) & PARITY_EN_MASK);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: PARITY_EN_SetDriveMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Change the drive mode on the pins of the port.\r
+* \r
+* Parameters: \r
+* mode: Change the pins to this drive mode.\r
+*\r
+* Return: \r
+* None\r
+*\r
+*******************************************************************************/\r
+void PARITY_EN_SetDriveMode(uint8 mode) \r
+{\r
+ CyPins_SetPinDriveMode(PARITY_EN_0, mode);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: PARITY_EN_Read\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value on the pins of the Digital Port in right justified \r
+* form.\r
+*\r
+* Parameters: \r
+* None\r
+*\r
+* Return: \r
+* Returns the current value of the Digital Port as a right justified number\r
+* \r
+* Note:\r
+* Macro PARITY_EN_ReadPS calls this function. \r
+* \r
+*******************************************************************************/\r
+uint8 PARITY_EN_Read(void) \r
+{\r
+ return (PARITY_EN_PS & PARITY_EN_MASK) >> PARITY_EN_SHIFT;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: PARITY_EN_ReadDataReg\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value assigned to a Digital Port's data output register\r
+*\r
+* Parameters: \r
+* None \r
+*\r
+* Return: \r
+* Returns the current value assigned to the Digital Port's data output register\r
+* \r
+*******************************************************************************/\r
+uint8 PARITY_EN_ReadDataReg(void) \r
+{\r
+ return (PARITY_EN_DR & PARITY_EN_MASK) >> PARITY_EN_SHIFT;\r
+}\r
+\r
+\r
+/* If Interrupts Are Enabled for this Pins component */ \r
+#if defined(PARITY_EN_INTSTAT) \r
+\r
+ /*******************************************************************************\r
+ * Function Name: PARITY_EN_ClearInterrupt\r
+ ********************************************************************************\r
+ * Summary:\r
+ * Clears any active interrupts attached to port and returns the value of the \r
+ * interrupt status register.\r
+ *\r
+ * Parameters: \r
+ * None \r
+ *\r
+ * Return: \r
+ * Returns the value of the interrupt status register\r
+ * \r
+ *******************************************************************************/\r
+ uint8 PARITY_EN_ClearInterrupt(void) \r
+ {\r
+ return (PARITY_EN_INTSTAT & PARITY_EN_MASK) >> PARITY_EN_SHIFT;\r
+ }\r
+\r
+#endif /* If Interrupts Are Enabled for this Pins component */ \r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+ \r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: PARITY_EN.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_PARITY_EN_H) /* Pins PARITY_EN_H */\r
+#define CY_PINS_PARITY_EN_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+#include "cypins.h"\r
+#include "PARITY_EN_aliases.h"\r
+\r
+/* Check to see if required defines such as CY_PSOC5A are available */\r
+/* They are defined starting with cy_boot v3.0 */\r
+#if !defined (CY_PSOC5A)\r
+ #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5A) */\r
+\r
+/* APIs are not generated for P15[7:6] */\r
+#if !(CY_PSOC5A &&\\r
+ PARITY_EN__PORT == 15 && ((PARITY_EN__MASK & 0xC0) != 0))\r
+\r
+\r
+/***************************************\r
+* Function Prototypes \r
+***************************************/ \r
+\r
+void PARITY_EN_Write(uint8 value) ;\r
+void PARITY_EN_SetDriveMode(uint8 mode) ;\r
+uint8 PARITY_EN_ReadDataReg(void) ;\r
+uint8 PARITY_EN_Read(void) ;\r
+uint8 PARITY_EN_ClearInterrupt(void) ;\r
+\r
+\r
+/***************************************\r
+* API Constants \r
+***************************************/\r
+\r
+/* Drive Modes */\r
+#define PARITY_EN_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+#define PARITY_EN_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+#define PARITY_EN_DM_RES_UP PIN_DM_RES_UP\r
+#define PARITY_EN_DM_RES_DWN PIN_DM_RES_DWN\r
+#define PARITY_EN_DM_OD_LO PIN_DM_OD_LO\r
+#define PARITY_EN_DM_OD_HI PIN_DM_OD_HI\r
+#define PARITY_EN_DM_STRONG PIN_DM_STRONG\r
+#define PARITY_EN_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+\r
+/* Digital Port Constants */\r
+#define PARITY_EN_MASK PARITY_EN__MASK\r
+#define PARITY_EN_SHIFT PARITY_EN__SHIFT\r
+#define PARITY_EN_WIDTH 1u\r
+\r
+\r
+/***************************************\r
+* Registers \r
+***************************************/\r
+\r
+/* Main Port Registers */\r
+/* Pin State */\r
+#define PARITY_EN_PS (* (reg8 *) PARITY_EN__PS)\r
+/* Data Register */\r
+#define PARITY_EN_DR (* (reg8 *) PARITY_EN__DR)\r
+/* Port Number */\r
+#define PARITY_EN_PRT_NUM (* (reg8 *) PARITY_EN__PRT) \r
+/* Connect to Analog Globals */ \r
+#define PARITY_EN_AG (* (reg8 *) PARITY_EN__AG) \r
+/* Analog MUX bux enable */\r
+#define PARITY_EN_AMUX (* (reg8 *) PARITY_EN__AMUX) \r
+/* Bidirectional Enable */ \r
+#define PARITY_EN_BIE (* (reg8 *) PARITY_EN__BIE)\r
+/* Bit-mask for Aliased Register Access */\r
+#define PARITY_EN_BIT_MASK (* (reg8 *) PARITY_EN__BIT_MASK)\r
+/* Bypass Enable */\r
+#define PARITY_EN_BYP (* (reg8 *) PARITY_EN__BYP)\r
+/* Port wide control signals */ \r
+#define PARITY_EN_CTL (* (reg8 *) PARITY_EN__CTL)\r
+/* Drive Modes */\r
+#define PARITY_EN_DM0 (* (reg8 *) PARITY_EN__DM0) \r
+#define PARITY_EN_DM1 (* (reg8 *) PARITY_EN__DM1)\r
+#define PARITY_EN_DM2 (* (reg8 *) PARITY_EN__DM2) \r
+/* Input Buffer Disable Override */\r
+#define PARITY_EN_INP_DIS (* (reg8 *) PARITY_EN__INP_DIS)\r
+/* LCD Common or Segment Drive */\r
+#define PARITY_EN_LCD_COM_SEG (* (reg8 *) PARITY_EN__LCD_COM_SEG)\r
+/* Enable Segment LCD */\r
+#define PARITY_EN_LCD_EN (* (reg8 *) PARITY_EN__LCD_EN)\r
+/* Slew Rate Control */\r
+#define PARITY_EN_SLW (* (reg8 *) PARITY_EN__SLW)\r
+\r
+/* DSI Port Registers */\r
+/* Global DSI Select Register */\r
+#define PARITY_EN_PRTDSI__CAPS_SEL (* (reg8 *) PARITY_EN__PRTDSI__CAPS_SEL) \r
+/* Double Sync Enable */\r
+#define PARITY_EN_PRTDSI__DBL_SYNC_IN (* (reg8 *) PARITY_EN__PRTDSI__DBL_SYNC_IN) \r
+/* Output Enable Select Drive Strength */\r
+#define PARITY_EN_PRTDSI__OE_SEL0 (* (reg8 *) PARITY_EN__PRTDSI__OE_SEL0) \r
+#define PARITY_EN_PRTDSI__OE_SEL1 (* (reg8 *) PARITY_EN__PRTDSI__OE_SEL1) \r
+/* Port Pin Output Select Registers */\r
+#define PARITY_EN_PRTDSI__OUT_SEL0 (* (reg8 *) PARITY_EN__PRTDSI__OUT_SEL0) \r
+#define PARITY_EN_PRTDSI__OUT_SEL1 (* (reg8 *) PARITY_EN__PRTDSI__OUT_SEL1) \r
+/* Sync Output Enable Registers */\r
+#define PARITY_EN_PRTDSI__SYNC_OUT (* (reg8 *) PARITY_EN__PRTDSI__SYNC_OUT) \r
+\r
+\r
+#if defined(PARITY_EN__INTSTAT) /* Interrupt Registers */\r
+\r
+ #define PARITY_EN_INTSTAT (* (reg8 *) PARITY_EN__INTSTAT)\r
+ #define PARITY_EN_SNAP (* (reg8 *) PARITY_EN__SNAP)\r
+\r
+#endif /* Interrupt Registers */\r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+#endif /* CY_PINS_PARITY_EN_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: PARITY_EN.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_PARITY_EN_ALIASES_H) /* Pins PARITY_EN_ALIASES_H */\r
+#define CY_PINS_PARITY_EN_ALIASES_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+\r
+\r
+/***************************************\r
+* Constants \r
+***************************************/\r
+#define PARITY_EN_0 PARITY_EN__0__PC\r
+\r
+#endif /* End Pins PARITY_EN_ALIASES_H */\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_ID.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SCSI_ID_ALIASES_H) /* Pins SCSI_ID_ALIASES_H */\r
+#define CY_PINS_SCSI_ID_ALIASES_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+\r
+\r
+/***************************************\r
+* Constants \r
+***************************************/\r
+#define SCSI_ID_0 SCSI_ID__0__PC\r
+#define SCSI_ID_1 SCSI_ID__1__PC\r
+#define SCSI_ID_2 SCSI_ID__2__PC\r
+\r
+#endif /* End Pins SCSI_ID_ALIASES_H */\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_In_DBx.c \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file contains API to enable firmware control of a Pins component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "cytypes.h"\r
+#include "SCSI_In_DBx.h"\r
+\r
+/* APIs are not generated for P15[7:6] on PSoC 5 */\r
+#if !(CY_PSOC5A &&\\r
+ SCSI_In_DBx__PORT == 15 && ((SCSI_In_DBx__MASK & 0xC0) != 0))\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_In_DBx_Write\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Assign a new value to the digital port's data output register. \r
+*\r
+* Parameters: \r
+* prtValue: The value to be assigned to the Digital Port. \r
+*\r
+* Return: \r
+* None\r
+* \r
+*******************************************************************************/\r
+void SCSI_In_DBx_Write(uint8 value) \r
+{\r
+ uint8 staticBits = (SCSI_In_DBx_DR & (uint8)(~SCSI_In_DBx_MASK));\r
+ SCSI_In_DBx_DR = staticBits | ((uint8)(value << SCSI_In_DBx_SHIFT) & SCSI_In_DBx_MASK);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_In_DBx_SetDriveMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Change the drive mode on the pins of the port.\r
+* \r
+* Parameters: \r
+* mode: Change the pins to this drive mode.\r
+*\r
+* Return: \r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_In_DBx_SetDriveMode(uint8 mode) \r
+{\r
+ CyPins_SetPinDriveMode(SCSI_In_DBx_0, mode);\r
+ CyPins_SetPinDriveMode(SCSI_In_DBx_1, mode);\r
+ CyPins_SetPinDriveMode(SCSI_In_DBx_2, mode);\r
+ CyPins_SetPinDriveMode(SCSI_In_DBx_3, mode);\r
+ CyPins_SetPinDriveMode(SCSI_In_DBx_4, mode);\r
+ CyPins_SetPinDriveMode(SCSI_In_DBx_5, mode);\r
+ CyPins_SetPinDriveMode(SCSI_In_DBx_6, mode);\r
+ CyPins_SetPinDriveMode(SCSI_In_DBx_7, mode);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_In_DBx_Read\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value on the pins of the Digital Port in right justified \r
+* form.\r
+*\r
+* Parameters: \r
+* None\r
+*\r
+* Return: \r
+* Returns the current value of the Digital Port as a right justified number\r
+* \r
+* Note:\r
+* Macro SCSI_In_DBx_ReadPS calls this function. \r
+* \r
+*******************************************************************************/\r
+uint8 SCSI_In_DBx_Read(void) \r
+{\r
+ return (SCSI_In_DBx_PS & SCSI_In_DBx_MASK) >> SCSI_In_DBx_SHIFT;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_In_DBx_ReadDataReg\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value assigned to a Digital Port's data output register\r
+*\r
+* Parameters: \r
+* None \r
+*\r
+* Return: \r
+* Returns the current value assigned to the Digital Port's data output register\r
+* \r
+*******************************************************************************/\r
+uint8 SCSI_In_DBx_ReadDataReg(void) \r
+{\r
+ return (SCSI_In_DBx_DR & SCSI_In_DBx_MASK) >> SCSI_In_DBx_SHIFT;\r
+}\r
+\r
+\r
+/* If Interrupts Are Enabled for this Pins component */ \r
+#if defined(SCSI_In_DBx_INTSTAT) \r
+\r
+ /*******************************************************************************\r
+ * Function Name: SCSI_In_DBx_ClearInterrupt\r
+ ********************************************************************************\r
+ * Summary:\r
+ * Clears any active interrupts attached to port and returns the value of the \r
+ * interrupt status register.\r
+ *\r
+ * Parameters: \r
+ * None \r
+ *\r
+ * Return: \r
+ * Returns the value of the interrupt status register\r
+ * \r
+ *******************************************************************************/\r
+ uint8 SCSI_In_DBx_ClearInterrupt(void) \r
+ {\r
+ return (SCSI_In_DBx_INTSTAT & SCSI_In_DBx_MASK) >> SCSI_In_DBx_SHIFT;\r
+ }\r
+\r
+#endif /* If Interrupts Are Enabled for this Pins component */ \r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+ \r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_In_DBx.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SCSI_In_DBx_H) /* Pins SCSI_In_DBx_H */\r
+#define CY_PINS_SCSI_In_DBx_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+#include "cypins.h"\r
+#include "SCSI_In_DBx_aliases.h"\r
+\r
+/* Check to see if required defines such as CY_PSOC5A are available */\r
+/* They are defined starting with cy_boot v3.0 */\r
+#if !defined (CY_PSOC5A)\r
+ #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5A) */\r
+\r
+/* APIs are not generated for P15[7:6] */\r
+#if !(CY_PSOC5A &&\\r
+ SCSI_In_DBx__PORT == 15 && ((SCSI_In_DBx__MASK & 0xC0) != 0))\r
+\r
+\r
+/***************************************\r
+* Function Prototypes \r
+***************************************/ \r
+\r
+void SCSI_In_DBx_Write(uint8 value) ;\r
+void SCSI_In_DBx_SetDriveMode(uint8 mode) ;\r
+uint8 SCSI_In_DBx_ReadDataReg(void) ;\r
+uint8 SCSI_In_DBx_Read(void) ;\r
+uint8 SCSI_In_DBx_ClearInterrupt(void) ;\r
+\r
+\r
+/***************************************\r
+* API Constants \r
+***************************************/\r
+\r
+/* Drive Modes */\r
+#define SCSI_In_DBx_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+#define SCSI_In_DBx_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+#define SCSI_In_DBx_DM_RES_UP PIN_DM_RES_UP\r
+#define SCSI_In_DBx_DM_RES_DWN PIN_DM_RES_DWN\r
+#define SCSI_In_DBx_DM_OD_LO PIN_DM_OD_LO\r
+#define SCSI_In_DBx_DM_OD_HI PIN_DM_OD_HI\r
+#define SCSI_In_DBx_DM_STRONG PIN_DM_STRONG\r
+#define SCSI_In_DBx_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+\r
+/* Digital Port Constants */\r
+#define SCSI_In_DBx_MASK SCSI_In_DBx__MASK\r
+#define SCSI_In_DBx_SHIFT SCSI_In_DBx__SHIFT\r
+#define SCSI_In_DBx_WIDTH 8u\r
+\r
+\r
+/***************************************\r
+* Registers \r
+***************************************/\r
+\r
+/* Main Port Registers */\r
+/* Pin State */\r
+#define SCSI_In_DBx_PS (* (reg8 *) SCSI_In_DBx__PS)\r
+/* Data Register */\r
+#define SCSI_In_DBx_DR (* (reg8 *) SCSI_In_DBx__DR)\r
+/* Port Number */\r
+#define SCSI_In_DBx_PRT_NUM (* (reg8 *) SCSI_In_DBx__PRT) \r
+/* Connect to Analog Globals */ \r
+#define SCSI_In_DBx_AG (* (reg8 *) SCSI_In_DBx__AG) \r
+/* Analog MUX bux enable */\r
+#define SCSI_In_DBx_AMUX (* (reg8 *) SCSI_In_DBx__AMUX) \r
+/* Bidirectional Enable */ \r
+#define SCSI_In_DBx_BIE (* (reg8 *) SCSI_In_DBx__BIE)\r
+/* Bit-mask for Aliased Register Access */\r
+#define SCSI_In_DBx_BIT_MASK (* (reg8 *) SCSI_In_DBx__BIT_MASK)\r
+/* Bypass Enable */\r
+#define SCSI_In_DBx_BYP (* (reg8 *) SCSI_In_DBx__BYP)\r
+/* Port wide control signals */ \r
+#define SCSI_In_DBx_CTL (* (reg8 *) SCSI_In_DBx__CTL)\r
+/* Drive Modes */\r
+#define SCSI_In_DBx_DM0 (* (reg8 *) SCSI_In_DBx__DM0) \r
+#define SCSI_In_DBx_DM1 (* (reg8 *) SCSI_In_DBx__DM1)\r
+#define SCSI_In_DBx_DM2 (* (reg8 *) SCSI_In_DBx__DM2) \r
+/* Input Buffer Disable Override */\r
+#define SCSI_In_DBx_INP_DIS (* (reg8 *) SCSI_In_DBx__INP_DIS)\r
+/* LCD Common or Segment Drive */\r
+#define SCSI_In_DBx_LCD_COM_SEG (* (reg8 *) SCSI_In_DBx__LCD_COM_SEG)\r
+/* Enable Segment LCD */\r
+#define SCSI_In_DBx_LCD_EN (* (reg8 *) SCSI_In_DBx__LCD_EN)\r
+/* Slew Rate Control */\r
+#define SCSI_In_DBx_SLW (* (reg8 *) SCSI_In_DBx__SLW)\r
+\r
+/* DSI Port Registers */\r
+/* Global DSI Select Register */\r
+#define SCSI_In_DBx_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_In_DBx__PRTDSI__CAPS_SEL) \r
+/* Double Sync Enable */\r
+#define SCSI_In_DBx_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_In_DBx__PRTDSI__DBL_SYNC_IN) \r
+/* Output Enable Select Drive Strength */\r
+#define SCSI_In_DBx_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_In_DBx__PRTDSI__OE_SEL0) \r
+#define SCSI_In_DBx_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_In_DBx__PRTDSI__OE_SEL1) \r
+/* Port Pin Output Select Registers */\r
+#define SCSI_In_DBx_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_In_DBx__PRTDSI__OUT_SEL0) \r
+#define SCSI_In_DBx_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_In_DBx__PRTDSI__OUT_SEL1) \r
+/* Sync Output Enable Registers */\r
+#define SCSI_In_DBx_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_In_DBx__PRTDSI__SYNC_OUT) \r
+\r
+\r
+#if defined(SCSI_In_DBx__INTSTAT) /* Interrupt Registers */\r
+\r
+ #define SCSI_In_DBx_INTSTAT (* (reg8 *) SCSI_In_DBx__INTSTAT)\r
+ #define SCSI_In_DBx_SNAP (* (reg8 *) SCSI_In_DBx__SNAP)\r
+\r
+#endif /* Interrupt Registers */\r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+#endif /* CY_PINS_SCSI_In_DBx_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_In_DBx.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SCSI_In_DBx_ALIASES_H) /* Pins SCSI_In_DBx_ALIASES_H */\r
+#define CY_PINS_SCSI_In_DBx_ALIASES_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+\r
+\r
+/***************************************\r
+* Constants \r
+***************************************/\r
+#define SCSI_In_DBx_0 SCSI_In_DBx__0__PC\r
+#define SCSI_In_DBx_1 SCSI_In_DBx__1__PC\r
+#define SCSI_In_DBx_2 SCSI_In_DBx__2__PC\r
+#define SCSI_In_DBx_3 SCSI_In_DBx__3__PC\r
+#define SCSI_In_DBx_4 SCSI_In_DBx__4__PC\r
+#define SCSI_In_DBx_5 SCSI_In_DBx__5__PC\r
+#define SCSI_In_DBx_6 SCSI_In_DBx__6__PC\r
+#define SCSI_In_DBx_7 SCSI_In_DBx__7__PC\r
+\r
+#define SCSI_In_DBx_SCSI_Out_DB0 SCSI_In_DBx__SCSI_Out_DB0__PC\r
+#define SCSI_In_DBx_SCSI_Out_DB1 SCSI_In_DBx__SCSI_Out_DB1__PC\r
+#define SCSI_In_DBx_SCSI_Out_DB2 SCSI_In_DBx__SCSI_Out_DB2__PC\r
+#define SCSI_In_DBx_SCSI_Out_DB3 SCSI_In_DBx__SCSI_Out_DB3__PC\r
+#define SCSI_In_DBx_SCSI_Out_DB4 SCSI_In_DBx__SCSI_Out_DB4__PC\r
+#define SCSI_In_DBx_SCSI_Out_DB5 SCSI_In_DBx__SCSI_Out_DB5__PC\r
+#define SCSI_In_DBx_SCSI_Out_DB6 SCSI_In_DBx__SCSI_Out_DB6__PC\r
+#define SCSI_In_DBx_SCSI_Out_DB7 SCSI_In_DBx__SCSI_Out_DB7__PC\r
+\r
+#endif /* End Pins SCSI_In_DBx_ALIASES_H */\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_In.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SCSI_In_ALIASES_H) /* Pins SCSI_In_ALIASES_H */\r
+#define CY_PINS_SCSI_In_ALIASES_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+\r
+\r
+/***************************************\r
+* Constants \r
+***************************************/\r
+#define SCSI_In_0 SCSI_In__0__PC\r
+#define SCSI_In_1 SCSI_In__1__PC\r
+#define SCSI_In_2 SCSI_In__2__PC\r
+#define SCSI_In_3 SCSI_In__3__PC\r
+#define SCSI_In_4 SCSI_In__4__PC\r
+#define SCSI_In_5 SCSI_In__5__PC\r
+#define SCSI_In_6 SCSI_In__6__PC\r
+#define SCSI_In_7 SCSI_In__7__PC\r
+#define SCSI_In_8 SCSI_In__8__PC\r
+#define SCSI_In_9 SCSI_In__9__PC\r
+\r
+#define SCSI_In_DBP SCSI_In__DBP__PC\r
+#define SCSI_In_ATN SCSI_In__ATN__PC\r
+#define SCSI_In_BSY SCSI_In__BSY__PC\r
+#define SCSI_In_ACK SCSI_In__ACK__PC\r
+#define SCSI_In_RST SCSI_In__RST__PC\r
+#define SCSI_In_MSG SCSI_In__MSG__PC\r
+#define SCSI_In_SEL SCSI_In__SEL__PC\r
+#define SCSI_In_CD SCSI_In__CD__PC\r
+#define SCSI_In_REQ SCSI_In__REQ__PC\r
+#define SCSI_In_IO SCSI_In__IO__PC\r
+\r
+#endif /* End Pins SCSI_In_ALIASES_H */\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_Out_DBx.c \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file contains API to enable firmware control of a Pins component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "cytypes.h"\r
+#include "SCSI_Out_DBx.h"\r
+\r
+/* APIs are not generated for P15[7:6] on PSoC 5 */\r
+#if !(CY_PSOC5A &&\\r
+ SCSI_Out_DBx__PORT == 15 && ((SCSI_Out_DBx__MASK & 0xC0) != 0))\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_Out_DBx_Write\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Assign a new value to the digital port's data output register. \r
+*\r
+* Parameters: \r
+* prtValue: The value to be assigned to the Digital Port. \r
+*\r
+* Return: \r
+* None\r
+* \r
+*******************************************************************************/\r
+void SCSI_Out_DBx_Write(uint8 value) \r
+{\r
+ uint8 staticBits = (SCSI_Out_DBx_DR & (uint8)(~SCSI_Out_DBx_MASK));\r
+ SCSI_Out_DBx_DR = staticBits | ((uint8)(value << SCSI_Out_DBx_SHIFT) & SCSI_Out_DBx_MASK);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_Out_DBx_SetDriveMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Change the drive mode on the pins of the port.\r
+* \r
+* Parameters: \r
+* mode: Change the pins to this drive mode.\r
+*\r
+* Return: \r
+* None\r
+*\r
+*******************************************************************************/\r
+void SCSI_Out_DBx_SetDriveMode(uint8 mode) \r
+{\r
+ CyPins_SetPinDriveMode(SCSI_Out_DBx_0, mode);\r
+ CyPins_SetPinDriveMode(SCSI_Out_DBx_1, mode);\r
+ CyPins_SetPinDriveMode(SCSI_Out_DBx_2, mode);\r
+ CyPins_SetPinDriveMode(SCSI_Out_DBx_3, mode);\r
+ CyPins_SetPinDriveMode(SCSI_Out_DBx_4, mode);\r
+ CyPins_SetPinDriveMode(SCSI_Out_DBx_5, mode);\r
+ CyPins_SetPinDriveMode(SCSI_Out_DBx_6, mode);\r
+ CyPins_SetPinDriveMode(SCSI_Out_DBx_7, mode);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_Out_DBx_Read\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value on the pins of the Digital Port in right justified \r
+* form.\r
+*\r
+* Parameters: \r
+* None\r
+*\r
+* Return: \r
+* Returns the current value of the Digital Port as a right justified number\r
+* \r
+* Note:\r
+* Macro SCSI_Out_DBx_ReadPS calls this function. \r
+* \r
+*******************************************************************************/\r
+uint8 SCSI_Out_DBx_Read(void) \r
+{\r
+ return (SCSI_Out_DBx_PS & SCSI_Out_DBx_MASK) >> SCSI_Out_DBx_SHIFT;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SCSI_Out_DBx_ReadDataReg\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value assigned to a Digital Port's data output register\r
+*\r
+* Parameters: \r
+* None \r
+*\r
+* Return: \r
+* Returns the current value assigned to the Digital Port's data output register\r
+* \r
+*******************************************************************************/\r
+uint8 SCSI_Out_DBx_ReadDataReg(void) \r
+{\r
+ return (SCSI_Out_DBx_DR & SCSI_Out_DBx_MASK) >> SCSI_Out_DBx_SHIFT;\r
+}\r
+\r
+\r
+/* If Interrupts Are Enabled for this Pins component */ \r
+#if defined(SCSI_Out_DBx_INTSTAT) \r
+\r
+ /*******************************************************************************\r
+ * Function Name: SCSI_Out_DBx_ClearInterrupt\r
+ ********************************************************************************\r
+ * Summary:\r
+ * Clears any active interrupts attached to port and returns the value of the \r
+ * interrupt status register.\r
+ *\r
+ * Parameters: \r
+ * None \r
+ *\r
+ * Return: \r
+ * Returns the value of the interrupt status register\r
+ * \r
+ *******************************************************************************/\r
+ uint8 SCSI_Out_DBx_ClearInterrupt(void) \r
+ {\r
+ return (SCSI_Out_DBx_INTSTAT & SCSI_Out_DBx_MASK) >> SCSI_Out_DBx_SHIFT;\r
+ }\r
+\r
+#endif /* If Interrupts Are Enabled for this Pins component */ \r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+ \r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_Out_DBx.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SCSI_Out_DBx_H) /* Pins SCSI_Out_DBx_H */\r
+#define CY_PINS_SCSI_Out_DBx_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+#include "cypins.h"\r
+#include "SCSI_Out_DBx_aliases.h"\r
+\r
+/* Check to see if required defines such as CY_PSOC5A are available */\r
+/* They are defined starting with cy_boot v3.0 */\r
+#if !defined (CY_PSOC5A)\r
+ #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5A) */\r
+\r
+/* APIs are not generated for P15[7:6] */\r
+#if !(CY_PSOC5A &&\\r
+ SCSI_Out_DBx__PORT == 15 && ((SCSI_Out_DBx__MASK & 0xC0) != 0))\r
+\r
+\r
+/***************************************\r
+* Function Prototypes \r
+***************************************/ \r
+\r
+void SCSI_Out_DBx_Write(uint8 value) ;\r
+void SCSI_Out_DBx_SetDriveMode(uint8 mode) ;\r
+uint8 SCSI_Out_DBx_ReadDataReg(void) ;\r
+uint8 SCSI_Out_DBx_Read(void) ;\r
+uint8 SCSI_Out_DBx_ClearInterrupt(void) ;\r
+\r
+\r
+/***************************************\r
+* API Constants \r
+***************************************/\r
+\r
+/* Drive Modes */\r
+#define SCSI_Out_DBx_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+#define SCSI_Out_DBx_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+#define SCSI_Out_DBx_DM_RES_UP PIN_DM_RES_UP\r
+#define SCSI_Out_DBx_DM_RES_DWN PIN_DM_RES_DWN\r
+#define SCSI_Out_DBx_DM_OD_LO PIN_DM_OD_LO\r
+#define SCSI_Out_DBx_DM_OD_HI PIN_DM_OD_HI\r
+#define SCSI_Out_DBx_DM_STRONG PIN_DM_STRONG\r
+#define SCSI_Out_DBx_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+\r
+/* Digital Port Constants */\r
+#define SCSI_Out_DBx_MASK SCSI_Out_DBx__MASK\r
+#define SCSI_Out_DBx_SHIFT SCSI_Out_DBx__SHIFT\r
+#define SCSI_Out_DBx_WIDTH 8u\r
+\r
+\r
+/***************************************\r
+* Registers \r
+***************************************/\r
+\r
+/* Main Port Registers */\r
+/* Pin State */\r
+#define SCSI_Out_DBx_PS (* (reg8 *) SCSI_Out_DBx__PS)\r
+/* Data Register */\r
+#define SCSI_Out_DBx_DR (* (reg8 *) SCSI_Out_DBx__DR)\r
+/* Port Number */\r
+#define SCSI_Out_DBx_PRT_NUM (* (reg8 *) SCSI_Out_DBx__PRT) \r
+/* Connect to Analog Globals */ \r
+#define SCSI_Out_DBx_AG (* (reg8 *) SCSI_Out_DBx__AG) \r
+/* Analog MUX bux enable */\r
+#define SCSI_Out_DBx_AMUX (* (reg8 *) SCSI_Out_DBx__AMUX) \r
+/* Bidirectional Enable */ \r
+#define SCSI_Out_DBx_BIE (* (reg8 *) SCSI_Out_DBx__BIE)\r
+/* Bit-mask for Aliased Register Access */\r
+#define SCSI_Out_DBx_BIT_MASK (* (reg8 *) SCSI_Out_DBx__BIT_MASK)\r
+/* Bypass Enable */\r
+#define SCSI_Out_DBx_BYP (* (reg8 *) SCSI_Out_DBx__BYP)\r
+/* Port wide control signals */ \r
+#define SCSI_Out_DBx_CTL (* (reg8 *) SCSI_Out_DBx__CTL)\r
+/* Drive Modes */\r
+#define SCSI_Out_DBx_DM0 (* (reg8 *) SCSI_Out_DBx__DM0) \r
+#define SCSI_Out_DBx_DM1 (* (reg8 *) SCSI_Out_DBx__DM1)\r
+#define SCSI_Out_DBx_DM2 (* (reg8 *) SCSI_Out_DBx__DM2) \r
+/* Input Buffer Disable Override */\r
+#define SCSI_Out_DBx_INP_DIS (* (reg8 *) SCSI_Out_DBx__INP_DIS)\r
+/* LCD Common or Segment Drive */\r
+#define SCSI_Out_DBx_LCD_COM_SEG (* (reg8 *) SCSI_Out_DBx__LCD_COM_SEG)\r
+/* Enable Segment LCD */\r
+#define SCSI_Out_DBx_LCD_EN (* (reg8 *) SCSI_Out_DBx__LCD_EN)\r
+/* Slew Rate Control */\r
+#define SCSI_Out_DBx_SLW (* (reg8 *) SCSI_Out_DBx__SLW)\r
+\r
+/* DSI Port Registers */\r
+/* Global DSI Select Register */\r
+#define SCSI_Out_DBx_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_Out_DBx__PRTDSI__CAPS_SEL) \r
+/* Double Sync Enable */\r
+#define SCSI_Out_DBx_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_Out_DBx__PRTDSI__DBL_SYNC_IN) \r
+/* Output Enable Select Drive Strength */\r
+#define SCSI_Out_DBx_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_Out_DBx__PRTDSI__OE_SEL0) \r
+#define SCSI_Out_DBx_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_Out_DBx__PRTDSI__OE_SEL1) \r
+/* Port Pin Output Select Registers */\r
+#define SCSI_Out_DBx_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_Out_DBx__PRTDSI__OUT_SEL0) \r
+#define SCSI_Out_DBx_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_Out_DBx__PRTDSI__OUT_SEL1) \r
+/* Sync Output Enable Registers */\r
+#define SCSI_Out_DBx_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_Out_DBx__PRTDSI__SYNC_OUT) \r
+\r
+\r
+#if defined(SCSI_Out_DBx__INTSTAT) /* Interrupt Registers */\r
+\r
+ #define SCSI_Out_DBx_INTSTAT (* (reg8 *) SCSI_Out_DBx__INTSTAT)\r
+ #define SCSI_Out_DBx_SNAP (* (reg8 *) SCSI_Out_DBx__SNAP)\r
+\r
+#endif /* Interrupt Registers */\r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+#endif /* CY_PINS_SCSI_Out_DBx_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_Out_DBx.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SCSI_Out_DBx_ALIASES_H) /* Pins SCSI_Out_DBx_ALIASES_H */\r
+#define CY_PINS_SCSI_Out_DBx_ALIASES_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+\r
+\r
+/***************************************\r
+* Constants \r
+***************************************/\r
+#define SCSI_Out_DBx_0 SCSI_Out_DBx__0__PC\r
+#define SCSI_Out_DBx_1 SCSI_Out_DBx__1__PC\r
+#define SCSI_Out_DBx_2 SCSI_Out_DBx__2__PC\r
+#define SCSI_Out_DBx_3 SCSI_Out_DBx__3__PC\r
+#define SCSI_Out_DBx_4 SCSI_Out_DBx__4__PC\r
+#define SCSI_Out_DBx_5 SCSI_Out_DBx__5__PC\r
+#define SCSI_Out_DBx_6 SCSI_Out_DBx__6__PC\r
+#define SCSI_Out_DBx_7 SCSI_Out_DBx__7__PC\r
+\r
+#define SCSI_Out_DBx_SCSI_Out_DB0 SCSI_Out_DBx__SCSI_Out_DB0__PC\r
+#define SCSI_Out_DBx_SCSI_Out_DB1 SCSI_Out_DBx__SCSI_Out_DB1__PC\r
+#define SCSI_Out_DBx_SCSI_Out_DB2 SCSI_Out_DBx__SCSI_Out_DB2__PC\r
+#define SCSI_Out_DBx_SCSI_Out_DB3 SCSI_Out_DBx__SCSI_Out_DB3__PC\r
+#define SCSI_Out_DBx_SCSI_Out_DB4 SCSI_Out_DBx__SCSI_Out_DB4__PC\r
+#define SCSI_Out_DBx_SCSI_Out_DB5 SCSI_Out_DBx__SCSI_Out_DB5__PC\r
+#define SCSI_Out_DBx_SCSI_Out_DB6 SCSI_Out_DBx__SCSI_Out_DB6__PC\r
+#define SCSI_Out_DBx_SCSI_Out_DB7 SCSI_Out_DBx__SCSI_Out_DB7__PC\r
+\r
+#endif /* End Pins SCSI_Out_DBx_ALIASES_H */\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SCSI_Out.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SCSI_Out_ALIASES_H) /* Pins SCSI_Out_ALIASES_H */\r
+#define CY_PINS_SCSI_Out_ALIASES_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+\r
+\r
+/***************************************\r
+* Constants \r
+***************************************/\r
+#define SCSI_Out_0 SCSI_Out__0__PC\r
+#define SCSI_Out_1 SCSI_Out__1__PC\r
+#define SCSI_Out_2 SCSI_Out__2__PC\r
+#define SCSI_Out_3 SCSI_Out__3__PC\r
+#define SCSI_Out_4 SCSI_Out__4__PC\r
+#define SCSI_Out_5 SCSI_Out__5__PC\r
+#define SCSI_Out_6 SCSI_Out__6__PC\r
+#define SCSI_Out_7 SCSI_Out__7__PC\r
+#define SCSI_Out_8 SCSI_Out__8__PC\r
+#define SCSI_Out_9 SCSI_Out__9__PC\r
+\r
+#define SCSI_Out_DBP SCSI_Out__DBP__PC\r
+#define SCSI_Out_ATN SCSI_Out__ATN__PC\r
+#define SCSI_Out_BSY SCSI_Out__BSY__PC\r
+#define SCSI_Out_ACK SCSI_Out__ACK__PC\r
+#define SCSI_Out_RST SCSI_Out__RST__PC\r
+#define SCSI_Out_MSG SCSI_Out__MSG__PC\r
+#define SCSI_Out_SEL SCSI_Out__SEL__PC\r
+#define SCSI_Out_CD SCSI_Out__CD__PC\r
+#define SCSI_Out_REQ SCSI_Out__REQ__PC\r
+#define SCSI_Out_IO SCSI_Out__IO__PC\r
+\r
+#endif /* End Pins SCSI_Out_ALIASES_H */\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD.c\r
+* Version 2.40\r
+*\r
+* Description:\r
+* This file provides all API functionality of the SPI Master component.\r
+*\r
+* Note:\r
+* None.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "SD_PVT.h"\r
+\r
+#if(SD_TX_SOFTWARE_BUF_ENABLED)\r
+ volatile uint8 SD_txBuffer[SD_TX_BUFFER_SIZE] = {0u};\r
+ volatile uint8 SD_txBufferFull;\r
+ volatile uint8 SD_txBufferRead;\r
+ volatile uint8 SD_txBufferWrite;\r
+#endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
+\r
+#if(SD_RX_SOFTWARE_BUF_ENABLED)\r
+ volatile uint8 SD_rxBuffer[SD_RX_BUFFER_SIZE] = {0u};\r
+ volatile uint8 SD_rxBufferFull;\r
+ volatile uint8 SD_rxBufferRead;\r
+ volatile uint8 SD_rxBufferWrite;\r
+#endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
+\r
+uint8 SD_initVar = 0u;\r
+\r
+volatile uint8 SD_swStatusTx;\r
+volatile uint8 SD_swStatusRx;\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Init\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Inits/Restores default SPIM configuration provided with customizer.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Side Effects:\r
+* When this function is called it initializes all of the necessary parameters\r
+* for execution. i.e. setting the initial interrupt mask, configuring the\r
+* interrupt service routine, configuring the bit-counter parameters and\r
+* clearing the FIFO and Status Register.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void SD_Init(void) \r
+{\r
+ /* Initialize the Bit counter */\r
+ SD_COUNTER_PERIOD_REG = SD_BITCTR_INIT;\r
+\r
+ /* Init TX ISR */\r
+ #if(0u != SD_INTERNAL_TX_INT_ENABLED)\r
+ CyIntDisable (SD_TX_ISR_NUMBER);\r
+ CyIntSetPriority (SD_TX_ISR_NUMBER, SD_TX_ISR_PRIORITY);\r
+ (void) CyIntSetVector(SD_TX_ISR_NUMBER, &SD_TX_ISR);\r
+ #endif /* (0u != SD_INTERNAL_TX_INT_ENABLED) */\r
+\r
+ /* Init RX ISR */\r
+ #if(0u != SD_INTERNAL_RX_INT_ENABLED)\r
+ CyIntDisable (SD_RX_ISR_NUMBER);\r
+ CyIntSetPriority (SD_RX_ISR_NUMBER, SD_RX_ISR_PRIORITY);\r
+ (void) CyIntSetVector(SD_RX_ISR_NUMBER, &SD_RX_ISR);\r
+ #endif /* (0u != SD_INTERNAL_RX_INT_ENABLED) */\r
+\r
+ /* Clear any stray data from the RX and TX FIFO */\r
+ SD_ClearFIFO();\r
+\r
+ #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
+ SD_rxBufferFull = 0u;\r
+ SD_rxBufferRead = 0u;\r
+ SD_rxBufferWrite = 0u;\r
+ #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
+ SD_txBufferFull = 0u;\r
+ SD_txBufferRead = 0u;\r
+ SD_txBufferWrite = 0u;\r
+ #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ (void) SD_ReadTxStatus(); /* Clear Tx status and swStatusTx */\r
+ (void) SD_ReadRxStatus(); /* Clear Rx status and swStatusRx */\r
+\r
+ /* Configure TX and RX interrupt mask */\r
+ SD_TX_STATUS_MASK_REG = SD_TX_INIT_INTERRUPTS_MASK;\r
+ SD_RX_STATUS_MASK_REG = SD_RX_INIT_INTERRUPTS_MASK;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Enable\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enable SPIM component.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+*******************************************************************************/\r
+void SD_Enable(void) \r
+{\r
+ uint8 enableInterrupts;\r
+\r
+ enableInterrupts = CyEnterCriticalSection();\r
+ SD_COUNTER_CONTROL_REG |= SD_CNTR_ENABLE;\r
+ SD_TX_STATUS_ACTL_REG |= SD_INT_ENABLE;\r
+ SD_RX_STATUS_ACTL_REG |= SD_INT_ENABLE;\r
+ CyExitCriticalSection(enableInterrupts);\r
+\r
+ #if(0u != SD_INTERNAL_CLOCK)\r
+ SD_IntClock_Enable();\r
+ #endif /* (0u != SD_INTERNAL_CLOCK) */\r
+\r
+ SD_EnableTxInt();\r
+ SD_EnableRxInt();\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Start\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Initialize and Enable the SPI Master component.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global variables:\r
+* SD_initVar - used to check initial configuration, modified on\r
+* first function call.\r
+*\r
+* Theory:\r
+* Enable the clock input to enable operation.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void SD_Start(void) \r
+{\r
+ if(0u == SD_initVar)\r
+ {\r
+ SD_Init();\r
+ SD_initVar = 1u;\r
+ }\r
+\r
+ SD_Enable();\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Stop\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disable the SPI Master component.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Disable the clock input to enable operation.\r
+*\r
+*******************************************************************************/\r
+void SD_Stop(void) \r
+{\r
+ uint8 enableInterrupts;\r
+\r
+ enableInterrupts = CyEnterCriticalSection();\r
+ SD_TX_STATUS_ACTL_REG &= ((uint8) ~SD_INT_ENABLE);\r
+ SD_RX_STATUS_ACTL_REG &= ((uint8) ~SD_INT_ENABLE);\r
+ CyExitCriticalSection(enableInterrupts);\r
+\r
+ #if(0u != SD_INTERNAL_CLOCK)\r
+ SD_IntClock_Disable();\r
+ #endif /* (0u != SD_INTERNAL_CLOCK) */\r
+\r
+ SD_DisableTxInt();\r
+ SD_DisableRxInt();\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_EnableTxInt\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enable internal Tx interrupt generation.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Enable the internal Tx interrupt output -or- the interrupt component itself.\r
+*\r
+*******************************************************************************/\r
+void SD_EnableTxInt(void) \r
+{\r
+ #if(0u != SD_INTERNAL_TX_INT_ENABLED)\r
+ CyIntEnable(SD_TX_ISR_NUMBER);\r
+ #endif /* (0u != SD_INTERNAL_TX_INT_ENABLED) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_EnableRxInt\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enable internal Rx interrupt generation.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Enable the internal Rx interrupt output -or- the interrupt component itself.\r
+*\r
+*******************************************************************************/\r
+void SD_EnableRxInt(void) \r
+{\r
+ #if(0u != SD_INTERNAL_RX_INT_ENABLED)\r
+ CyIntEnable(SD_RX_ISR_NUMBER);\r
+ #endif /* (0u != SD_INTERNAL_RX_INT_ENABLED) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_DisableTxInt\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disable internal Tx interrupt generation.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Disable the internal Tx interrupt output -or- the interrupt component itself.\r
+*\r
+*******************************************************************************/\r
+void SD_DisableTxInt(void) \r
+{\r
+ #if(0u != SD_INTERNAL_TX_INT_ENABLED)\r
+ CyIntDisable(SD_TX_ISR_NUMBER);\r
+ #endif /* (0u != SD_INTERNAL_TX_INT_ENABLED) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_DisableRxInt\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disable internal Rx interrupt generation.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Disable the internal Rx interrupt output -or- the interrupt component itself.\r
+*\r
+*******************************************************************************/\r
+void SD_DisableRxInt(void) \r
+{\r
+ #if(0u != SD_INTERNAL_RX_INT_ENABLED)\r
+ CyIntDisable(SD_RX_ISR_NUMBER);\r
+ #endif /* (0u != SD_INTERNAL_RX_INT_ENABLED) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_SetTxInterruptMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Configure which status bits trigger an interrupt event.\r
+*\r
+* Parameters:\r
+* intSrc: An or'd combination of the desired status bit masks (defined in the\r
+* header file).\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Enables the output of specific status bits to the interrupt controller.\r
+*\r
+*******************************************************************************/\r
+void SD_SetTxInterruptMode(uint8 intSrc) \r
+{\r
+ SD_TX_STATUS_MASK_REG = intSrc;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_SetRxInterruptMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Configure which status bits trigger an interrupt event.\r
+*\r
+* Parameters:\r
+* intSrc: An or'd combination of the desired status bit masks (defined in the\r
+* header file).\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Enables the output of specific status bits to the interrupt controller.\r
+*\r
+*******************************************************************************/\r
+void SD_SetRxInterruptMode(uint8 intSrc) \r
+{\r
+ SD_RX_STATUS_MASK_REG = intSrc;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_ReadTxStatus\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the Tx status register for the component.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* Contents of the Tx status register.\r
+*\r
+* Global variables:\r
+* SD_swStatusTx - used to store in software status register,\r
+* modified every function call - resets to zero.\r
+*\r
+* Theory:\r
+* Allows the user and the API to read the Tx status register for error\r
+* detection and flow control.\r
+*\r
+* Side Effects:\r
+* Clear Tx status register of the component.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+uint8 SD_ReadTxStatus(void) \r
+{\r
+ uint8 tmpStatus;\r
+\r
+ #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
+ /* Disable TX interrupt to protect global veriables */\r
+ SD_DisableTxInt();\r
+\r
+ tmpStatus = SD_GET_STATUS_TX(SD_swStatusTx);\r
+ SD_swStatusTx = 0u;\r
+\r
+ SD_EnableTxInt();\r
+\r
+ #else\r
+\r
+ tmpStatus = SD_TX_STATUS_REG;\r
+\r
+ #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ return(tmpStatus);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_ReadRxStatus\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the Rx status register for the component.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* Contents of the Rx status register.\r
+*\r
+* Global variables:\r
+* SD_swStatusRx - used to store in software Rx status register,\r
+* modified every function call - resets to zero.\r
+*\r
+* Theory:\r
+* Allows the user and the API to read the Rx status register for error\r
+* detection and flow control.\r
+*\r
+* Side Effects:\r
+* Clear Rx status register of the component.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+uint8 SD_ReadRxStatus(void) \r
+{\r
+ uint8 tmpStatus;\r
+\r
+ #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
+ /* Disable RX interrupt to protect global veriables */\r
+ SD_DisableRxInt();\r
+\r
+ tmpStatus = SD_GET_STATUS_RX(SD_swStatusRx);\r
+ SD_swStatusRx = 0u;\r
+\r
+ SD_EnableRxInt();\r
+\r
+ #else\r
+\r
+ tmpStatus = SD_RX_STATUS_REG;\r
+\r
+ #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ return(tmpStatus);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_WriteTxData\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Write a byte of data to be sent across the SPI.\r
+*\r
+* Parameters:\r
+* txDataByte: The data value to send across the SPI.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global variables:\r
+* SD_txBufferWrite - used for the account of the bytes which\r
+* have been written down in the TX software buffer, modified every function\r
+* call if TX Software Buffer is used.\r
+* SD_txBufferRead - used for the account of the bytes which\r
+* have been read from the TX software buffer.\r
+* SD_txBuffer[SD_TX_BUFFER_SIZE] - used to store\r
+* data to sending, modified every function call if TX Software Buffer is used.\r
+*\r
+* Theory:\r
+* Allows the user to transmit any byte of data in a single transfer.\r
+*\r
+* Side Effects:\r
+* If this function is called again before the previous byte is finished then\r
+* the next byte will be appended to the transfer with no time between\r
+* the byte transfers. Clear Tx status register of the component.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void SD_WriteTxData(uint8 txData) \r
+{\r
+ #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
+\r
+ uint8 tempStatus;\r
+ uint8 tmpTxBufferRead;\r
+\r
+ /* Block if TX buffer is FULL: don't overwrite */\r
+ do\r
+ {\r
+ tmpTxBufferRead = SD_txBufferRead;\r
+ if(0u == tmpTxBufferRead)\r
+ {\r
+ tmpTxBufferRead = (SD_TX_BUFFER_SIZE - 1u);\r
+ }\r
+ else\r
+ {\r
+ tmpTxBufferRead--;\r
+ }\r
+\r
+ }while(tmpTxBufferRead == SD_txBufferWrite);\r
+\r
+ /* Disable TX interrupt to protect global veriables */\r
+ SD_DisableTxInt();\r
+\r
+ tempStatus = SD_GET_STATUS_TX(SD_swStatusTx);\r
+ SD_swStatusTx = tempStatus;\r
+\r
+\r
+ if((SD_txBufferRead == SD_txBufferWrite) &&\r
+ (0u != (SD_swStatusTx & SD_STS_TX_FIFO_NOT_FULL)))\r
+ {\r
+ /* Add directly to the TX FIFO */\r
+ CY_SET_REG8(SD_TXDATA_PTR, txData);\r
+ }\r
+ else\r
+ {\r
+ /* Add to the TX software buffer */\r
+ SD_txBufferWrite++;\r
+ if(SD_txBufferWrite >= SD_TX_BUFFER_SIZE)\r
+ {\r
+ SD_txBufferWrite = 0u;\r
+ }\r
+\r
+ if(SD_txBufferWrite == SD_txBufferRead)\r
+ {\r
+ SD_txBufferRead++;\r
+ if(SD_txBufferRead >= SD_TX_BUFFER_SIZE)\r
+ {\r
+ SD_txBufferRead = 0u;\r
+ }\r
+ SD_txBufferFull = 1u;\r
+ }\r
+\r
+ SD_txBuffer[SD_txBufferWrite] = txData;\r
+\r
+ SD_TX_STATUS_MASK_REG |= SD_STS_TX_FIFO_NOT_FULL;\r
+ }\r
+\r
+ SD_EnableTxInt();\r
+\r
+ #else\r
+\r
+ while(0u == (SD_TX_STATUS_REG & SD_STS_TX_FIFO_NOT_FULL))\r
+ {\r
+ ; /* Wait for room in FIFO */\r
+ }\r
+\r
+ /* Put byte in TX FIFO */\r
+ CY_SET_REG8(SD_TXDATA_PTR, txData);\r
+\r
+ #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_ReadRxData\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the next byte of data received across the SPI.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* The next byte of data read from the FIFO.\r
+*\r
+* Global variables:\r
+* SD_rxBufferWrite - used for the account of the bytes which\r
+* have been written down in the RX software buffer.\r
+* SD_rxBufferRead - used for the account of the bytes which\r
+* have been read from the RX software buffer, modified every function\r
+* call if RX Software Buffer is used.\r
+* SD_rxBuffer[SD_RX_BUFFER_SIZE] - used to store\r
+* received data.\r
+*\r
+* Theory:\r
+* Allows the user to read a byte of data received.\r
+*\r
+* Side Effects:\r
+* Will return invalid data if the FIFO is empty. The user should Call\r
+* GetRxBufferSize() and if it returns a non-zero value then it is safe to call\r
+* ReadByte() function.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+uint8 SD_ReadRxData(void) \r
+{\r
+ uint8 rxData;\r
+\r
+ #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
+\r
+ /* Disable RX interrupt to protect global veriables */\r
+ SD_DisableRxInt();\r
+\r
+ if(SD_rxBufferRead != SD_rxBufferWrite)\r
+ {\r
+ if(0u == SD_rxBufferFull)\r
+ {\r
+ SD_rxBufferRead++;\r
+ if(SD_rxBufferRead >= SD_RX_BUFFER_SIZE)\r
+ {\r
+ SD_rxBufferRead = 0u;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ SD_rxBufferFull = 0u;\r
+ }\r
+ }\r
+\r
+ rxData = SD_rxBuffer[SD_rxBufferRead];\r
+\r
+ SD_EnableRxInt();\r
+\r
+ #else\r
+\r
+ rxData = CY_GET_REG8(SD_RXDATA_PTR);\r
+\r
+ #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ return(rxData);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_GetRxBufferSize\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Returns the number of bytes/words of data currently held in the RX buffer.\r
+* If RX Software Buffer not used then function return 0 if FIFO empty or 1 if\r
+* FIFO not empty. In another case function return size of RX Software Buffer.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* Integer count of the number of bytes/words in the RX buffer.\r
+*\r
+* Global variables:\r
+* SD_rxBufferWrite - used for the account of the bytes which\r
+* have been written down in the RX software buffer.\r
+* SD_rxBufferRead - used for the account of the bytes which\r
+* have been read from the RX software buffer.\r
+*\r
+* Side Effects:\r
+* Clear status register of the component.\r
+*\r
+*******************************************************************************/\r
+uint8 SD_GetRxBufferSize(void) \r
+{\r
+ uint8 size;\r
+\r
+ #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
+\r
+ /* Disable RX interrupt to protect global veriables */\r
+ SD_DisableRxInt();\r
+\r
+ if(SD_rxBufferRead == SD_rxBufferWrite)\r
+ {\r
+ size = 0u;\r
+ }\r
+ else if(SD_rxBufferRead < SD_rxBufferWrite)\r
+ {\r
+ size = (SD_rxBufferWrite - SD_rxBufferRead);\r
+ }\r
+ else\r
+ {\r
+ size = (SD_RX_BUFFER_SIZE - SD_rxBufferRead) + SD_rxBufferWrite;\r
+ }\r
+\r
+ SD_EnableRxInt();\r
+\r
+ #else\r
+\r
+ /* We can only know if there is data in the RX FIFO */\r
+ size = (0u != (SD_RX_STATUS_REG & SD_STS_RX_FIFO_NOT_EMPTY)) ? 1u : 0u;\r
+\r
+ #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ return(size);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_GetTxBufferSize\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Returns the number of bytes/words of data currently held in the TX buffer.\r
+* If TX Software Buffer not used then function return 0 - if FIFO empty, 1 - if\r
+* FIFO not full, 4 - if FIFO full. In another case function return size of TX\r
+* Software Buffer.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* Integer count of the number of bytes/words in the TX buffer.\r
+*\r
+* Global variables:\r
+* SD_txBufferWrite - used for the account of the bytes which\r
+* have been written down in the TX software buffer.\r
+* SD_txBufferRead - used for the account of the bytes which\r
+* have been read from the TX software buffer.\r
+*\r
+* Side Effects:\r
+* Clear status register of the component.\r
+*\r
+*******************************************************************************/\r
+uint8 SD_GetTxBufferSize(void) \r
+{\r
+ uint8 size;\r
+\r
+ #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
+ /* Disable TX interrupt to protect global veriables */\r
+ SD_DisableTxInt();\r
+\r
+ if(SD_txBufferRead == SD_txBufferWrite)\r
+ {\r
+ size = 0u;\r
+ }\r
+ else if(SD_txBufferRead < SD_txBufferWrite)\r
+ {\r
+ size = (SD_txBufferWrite - SD_txBufferRead);\r
+ }\r
+ else\r
+ {\r
+ size = (SD_TX_BUFFER_SIZE - SD_txBufferRead) + SD_txBufferWrite;\r
+ }\r
+\r
+ SD_EnableTxInt();\r
+\r
+ #else\r
+\r
+ size = SD_TX_STATUS_REG;\r
+\r
+ if(0u != (size & SD_STS_TX_FIFO_EMPTY))\r
+ {\r
+ size = 0u;\r
+ }\r
+ else if(0u != (size & SD_STS_TX_FIFO_NOT_FULL))\r
+ {\r
+ size = 1u;\r
+ }\r
+ else\r
+ {\r
+ size = SD_FIFO_SIZE;\r
+ }\r
+\r
+ #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ return(size);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_ClearRxBuffer\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Clear the RX RAM buffer by setting the read and write pointers both to zero.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global variables:\r
+* SD_rxBufferWrite - used for the account of the bytes which\r
+* have been written down in the RX software buffer, modified every function\r
+* call - resets to zero.\r
+* SD_rxBufferRead - used for the account of the bytes which\r
+* have been read from the RX software buffer, modified every function call -\r
+* resets to zero.\r
+*\r
+* Theory:\r
+* Setting the pointers to zero makes the system believe there is no data to\r
+* read and writing will resume at address 0 overwriting any data that may have\r
+* remained in the RAM.\r
+*\r
+* Side Effects:\r
+* Any received data not read from the RAM buffer will be lost when overwritten.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void SD_ClearRxBuffer(void) \r
+{\r
+ /* Clear Hardware RX FIFO */\r
+ while(0u !=(SD_RX_STATUS_REG & SD_STS_RX_FIFO_NOT_EMPTY))\r
+ {\r
+ (void) CY_GET_REG8(SD_RXDATA_PTR);\r
+ }\r
+\r
+ #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
+ /* Disable RX interrupt to protect global veriables */\r
+ SD_DisableRxInt();\r
+\r
+ SD_rxBufferFull = 0u;\r
+ SD_rxBufferRead = 0u;\r
+ SD_rxBufferWrite = 0u;\r
+\r
+ SD_EnableRxInt();\r
+ #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_ClearTxBuffer\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Clear the TX RAM buffer by setting the read and write pointers both to zero.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global variables:\r
+* SD_txBufferWrite - used for the account of the bytes which\r
+* have been written down in the TX software buffer, modified every function\r
+* call - resets to zero.\r
+* SD_txBufferRead - used for the account of the bytes which\r
+* have been read from the TX software buffer, modified every function call -\r
+* resets to zero.\r
+*\r
+* Theory:\r
+* Setting the pointers to zero makes the system believe there is no data to\r
+* read and writing will resume at address 0 overwriting any data that may have\r
+* remained in the RAM.\r
+*\r
+* Side Effects:\r
+* Any data not yet transmitted from the RAM buffer will be lost when\r
+* overwritten.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void SD_ClearTxBuffer(void) \r
+{\r
+ uint8 enableInterrupts;\r
+\r
+ enableInterrupts = CyEnterCriticalSection();\r
+ /* Clear TX FIFO */\r
+ SD_AUX_CONTROL_DP0_REG |= ((uint8) SD_TX_FIFO_CLR);\r
+ SD_AUX_CONTROL_DP0_REG &= ((uint8) ~SD_TX_FIFO_CLR);\r
+\r
+ #if(SD_USE_SECOND_DATAPATH)\r
+ /* Clear TX FIFO for 2nd Datapath */\r
+ SD_AUX_CONTROL_DP1_REG |= ((uint8) SD_TX_FIFO_CLR);\r
+ SD_AUX_CONTROL_DP1_REG &= ((uint8) ~SD_TX_FIFO_CLR);\r
+ #endif /* (SD_USE_SECOND_DATAPATH) */\r
+ CyExitCriticalSection(enableInterrupts);\r
+\r
+ #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
+ /* Disable TX interrupt to protect global veriables */\r
+ SD_DisableTxInt();\r
+\r
+ SD_txBufferFull = 0u;\r
+ SD_txBufferRead = 0u;\r
+ SD_txBufferWrite = 0u;\r
+\r
+ /* Buffer is EMPTY: disable TX FIFO NOT FULL interrupt */\r
+ SD_TX_STATUS_MASK_REG &= ((uint8) ~SD_STS_TX_FIFO_NOT_FULL);\r
+\r
+ SD_EnableTxInt();\r
+ #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
+}\r
+\r
+\r
+#if(0u != SD_BIDIRECTIONAL_MODE)\r
+ /*******************************************************************************\r
+ * Function Name: SD_TxEnable\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * If the SPI master is configured to use a single bi-directional pin then this\r
+ * will set the bi-directional pin to transmit.\r
+ *\r
+ * Parameters:\r
+ * None.\r
+ *\r
+ * Return:\r
+ * None.\r
+ *\r
+ *******************************************************************************/\r
+ void SD_TxEnable(void) \r
+ {\r
+ SD_CONTROL_REG |= SD_CTRL_TX_SIGNAL_EN;\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: SD_TxDisable\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * If the SPI master is configured to use a single bi-directional pin then this\r
+ * will set the bi-directional pin to receive.\r
+ *\r
+ * Parameters:\r
+ * None.\r
+ *\r
+ * Return:\r
+ * None.\r
+ *\r
+ *******************************************************************************/\r
+ void SD_TxDisable(void) \r
+ {\r
+ SD_CONTROL_REG &= ((uint8) ~SD_CTRL_TX_SIGNAL_EN);\r
+ }\r
+\r
+#endif /* (0u != SD_BIDIRECTIONAL_MODE) */\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_PutArray\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Write available data from ROM/RAM to the TX buffer while space is available\r
+* in the TX buffer. Keep trying until all data is passed to the TX buffer.\r
+*\r
+* Parameters:\r
+* *buffer: Pointer to the location in RAM containing the data to send\r
+* byteCount: The number of bytes to move to the transmit buffer.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Side Effects:\r
+* Will stay in this routine until all data has been sent. May get locked in\r
+* this loop if data is not being initiated by the master if there is not\r
+* enough room in the TX FIFO.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void SD_PutArray(const uint8 buffer[], uint8 byteCount)\r
+ \r
+{\r
+ uint8 bufIndex;\r
+\r
+ bufIndex = 0u;\r
+\r
+ while(byteCount > 0u)\r
+ {\r
+ SD_WriteTxData(buffer[bufIndex]);\r
+ bufIndex++;\r
+ byteCount--;\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_ClearFIFO\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Clear the RX and TX FIFO's of all data for a fresh start.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Side Effects:\r
+* Clear status register of the component.\r
+*\r
+*******************************************************************************/\r
+void SD_ClearFIFO(void) \r
+{\r
+ uint8 enableInterrupts;\r
+\r
+ /* Clear Hardware RX FIFO */\r
+ while(0u !=(SD_RX_STATUS_REG & SD_STS_RX_FIFO_NOT_EMPTY))\r
+ {\r
+ (void) CY_GET_REG8(SD_RXDATA_PTR);\r
+ }\r
+\r
+ enableInterrupts = CyEnterCriticalSection();\r
+ /* Clear TX FIFO */\r
+ SD_AUX_CONTROL_DP0_REG |= ((uint8) SD_TX_FIFO_CLR);\r
+ SD_AUX_CONTROL_DP0_REG &= ((uint8) ~SD_TX_FIFO_CLR);\r
+\r
+ #if(SD_USE_SECOND_DATAPATH)\r
+ /* Clear TX FIFO for 2nd Datapath */\r
+ SD_AUX_CONTROL_DP1_REG |= ((uint8) SD_TX_FIFO_CLR);\r
+ SD_AUX_CONTROL_DP1_REG &= ((uint8) ~SD_TX_FIFO_CLR);\r
+ #endif /* (SD_USE_SECOND_DATAPATH) */\r
+ CyExitCriticalSection(enableInterrupts);\r
+}\r
+\r
+\r
+/* Following functions are for version Compatibility, they are obsolete.\r
+* Please do not use it in new projects.\r
+*/\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_EnableInt\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enable internal interrupt generation.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Enable the internal interrupt output -or- the interrupt component itself.\r
+*\r
+*******************************************************************************/\r
+void SD_EnableInt(void) \r
+{\r
+ SD_EnableRxInt();\r
+ SD_EnableTxInt();\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_DisableInt\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disable internal interrupt generation.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Disable the internal interrupt output -or- the interrupt component itself.\r
+*\r
+*******************************************************************************/\r
+void SD_DisableInt(void) \r
+{\r
+ SD_DisableTxInt();\r
+ SD_DisableRxInt();\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_SetInterruptMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Configure which status bits trigger an interrupt event.\r
+*\r
+* Parameters:\r
+* intSrc: An or'd combination of the desired status bit masks (defined in the\r
+* header file).\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Enables the output of specific status bits to the interrupt controller.\r
+*\r
+*******************************************************************************/\r
+void SD_SetInterruptMode(uint8 intSrc) \r
+{\r
+ SD_TX_STATUS_MASK_REG = (intSrc & ((uint8) ~SD_STS_SPI_IDLE));\r
+ SD_RX_STATUS_MASK_REG = intSrc;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_ReadStatus\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the status register for the component.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* Contents of the status register.\r
+*\r
+* Global variables:\r
+* SD_swStatus - used to store in software status register,\r
+* modified every function call - resets to zero.\r
+*\r
+* Theory:\r
+* Allows the user and the API to read the status register for error detection\r
+* and flow control.\r
+*\r
+* Side Effects:\r
+* Clear status register of the component.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+uint8 SD_ReadStatus(void) \r
+{\r
+ uint8 tmpStatus;\r
+\r
+ #if(SD_TX_SOFTWARE_BUF_ENABLED || SD_RX_SOFTWARE_BUF_ENABLED)\r
+\r
+ SD_DisableInt();\r
+\r
+ tmpStatus = SD_GET_STATUS_RX(SD_swStatusRx);\r
+ tmpStatus |= SD_GET_STATUS_TX(SD_swStatusTx);\r
+ tmpStatus &= ((uint8) ~SD_STS_SPI_IDLE);\r
+\r
+ SD_swStatusTx = 0u;\r
+ SD_swStatusRx = 0u;\r
+\r
+ SD_EnableInt();\r
+\r
+ #else\r
+\r
+ tmpStatus = SD_RX_STATUS_REG;\r
+ tmpStatus |= SD_TX_STATUS_REG;\r
+ tmpStatus &= ((uint8) ~SD_STS_SPI_IDLE);\r
+\r
+ #endif /* (SD_TX_SOFTWARE_BUF_ENABLED || SD_RX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ return(tmpStatus);\r
+}\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD.h\r
+* Version 2.40\r
+*\r
+* Description:\r
+* Contains the function prototypes, constants and register definition\r
+* of the SPI Master Component.\r
+*\r
+* Note:\r
+* None\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_SPIM_SD_H)\r
+#define CY_SPIM_SD_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+#include "CyLib.h"\r
+\r
+/* Check to see if required defines such as CY_PSOC5A are available */\r
+/* They are defined starting with cy_boot v3.0 */\r
+#if !defined (CY_PSOC5A)\r
+ #error Component SPI_Master_v2_40 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5A) */\r
+\r
+\r
+/***************************************\r
+* Conditional Compilation Parameters\r
+***************************************/\r
+\r
+#define SD_INTERNAL_CLOCK (0u)\r
+\r
+#if(0u != SD_INTERNAL_CLOCK)\r
+ #include "SD_IntClock.h"\r
+#endif /* (0u != SD_INTERNAL_CLOCK) */\r
+\r
+#define SD_MODE (1u)\r
+#define SD_DATA_WIDTH (8u)\r
+#define SD_MODE_USE_ZERO (1u)\r
+#define SD_BIDIRECTIONAL_MODE (0u)\r
+\r
+/* Internal interrupt handling */\r
+#define SD_TX_BUFFER_SIZE (4u)\r
+#define SD_RX_BUFFER_SIZE (4u)\r
+#define SD_INTERNAL_TX_INT_ENABLED (0u)\r
+#define SD_INTERNAL_RX_INT_ENABLED (0u)\r
+\r
+#define SD_SINGLE_REG_SIZE (8u)\r
+#define SD_USE_SECOND_DATAPATH (SD_DATA_WIDTH > SD_SINGLE_REG_SIZE)\r
+\r
+#define SD_FIFO_SIZE (4u)\r
+#define SD_TX_SOFTWARE_BUF_ENABLED ((0u != SD_INTERNAL_TX_INT_ENABLED) && \\r
+ (SD_TX_BUFFER_SIZE > SD_FIFO_SIZE))\r
+\r
+#define SD_RX_SOFTWARE_BUF_ENABLED ((0u != SD_INTERNAL_RX_INT_ENABLED) && \\r
+ (SD_RX_BUFFER_SIZE > SD_FIFO_SIZE))\r
+\r
+\r
+/***************************************\r
+* Data Struct Definition\r
+***************************************/\r
+\r
+/* Sleep Mode API Support */\r
+typedef struct\r
+{\r
+ uint8 enableState;\r
+ uint8 cntrPeriod;\r
+ #if(CY_UDB_V0)\r
+ uint8 saveSrTxIntMask;\r
+ uint8 saveSrRxIntMask;\r
+ #endif /* (CY_UDB_V0) */\r
+\r
+} SD_BACKUP_STRUCT;\r
+\r
+\r
+/***************************************\r
+* Function Prototypes\r
+***************************************/\r
+\r
+void SD_Init(void) ;\r
+void SD_Enable(void) ;\r
+void SD_Start(void) ;\r
+void SD_Stop(void) ;\r
+\r
+void SD_EnableTxInt(void) ;\r
+void SD_EnableRxInt(void) ;\r
+void SD_DisableTxInt(void) ;\r
+void SD_DisableRxInt(void) ;\r
+\r
+void SD_Sleep(void) ;\r
+void SD_Wakeup(void) ;\r
+void SD_SaveConfig(void) ;\r
+void SD_RestoreConfig(void) ;\r
+\r
+void SD_SetTxInterruptMode(uint8 intSrc) ;\r
+void SD_SetRxInterruptMode(uint8 intSrc) ;\r
+uint8 SD_ReadTxStatus(void) ;\r
+uint8 SD_ReadRxStatus(void) ;\r
+void SD_WriteTxData(uint8 txData) \\r
+ ;\r
+uint8 SD_ReadRxData(void) \\r
+ ;\r
+uint8 SD_GetRxBufferSize(void) ;\r
+uint8 SD_GetTxBufferSize(void) ;\r
+void SD_ClearRxBuffer(void) ;\r
+void SD_ClearTxBuffer(void) ;\r
+void SD_ClearFIFO(void) ;\r
+void SD_PutArray(const uint8 buffer[], uint8 byteCount) \\r
+ ;\r
+\r
+#if(0u != SD_BIDIRECTIONAL_MODE)\r
+ void SD_TxEnable(void) ;\r
+ void SD_TxDisable(void) ;\r
+#endif /* (0u != SD_BIDIRECTIONAL_MODE) */\r
+\r
+CY_ISR_PROTO(SD_TX_ISR);\r
+CY_ISR_PROTO(SD_RX_ISR);\r
+\r
+\r
+/**********************************\r
+* Variable with external linkage\r
+**********************************/\r
+\r
+extern uint8 SD_initVar;\r
+\r
+\r
+/***************************************\r
+* API Constants\r
+***************************************/\r
+\r
+#define SD_TX_ISR_NUMBER ((uint8) (SD_TxInternalInterrupt__INTC_NUMBER))\r
+#define SD_RX_ISR_NUMBER ((uint8) (SD_RxInternalInterrupt__INTC_NUMBER))\r
+\r
+#define SD_TX_ISR_PRIORITY ((uint8) (SD_TxInternalInterrupt__INTC_PRIOR_NUM))\r
+#define SD_RX_ISR_PRIORITY ((uint8) (SD_RxInternalInterrupt__INTC_PRIOR_NUM))\r
+\r
+\r
+/***************************************\r
+* Initial Parameter Constants\r
+***************************************/\r
+\r
+#define SD_INT_ON_SPI_DONE ((uint8) (0u << SD_STS_SPI_DONE_SHIFT))\r
+#define SD_INT_ON_TX_EMPTY ((uint8) (0u << SD_STS_TX_FIFO_EMPTY_SHIFT))\r
+#define SD_INT_ON_TX_NOT_FULL ((uint8) (0u << \\r
+ SD_STS_TX_FIFO_NOT_FULL_SHIFT))\r
+#define SD_INT_ON_BYTE_COMP ((uint8) (0u << SD_STS_BYTE_COMPLETE_SHIFT))\r
+#define SD_INT_ON_SPI_IDLE ((uint8) (0u << SD_STS_SPI_IDLE_SHIFT))\r
+\r
+/* Disable TX_NOT_FULL if software buffer is used */\r
+#define SD_INT_ON_TX_NOT_FULL_DEF ((SD_TX_SOFTWARE_BUF_ENABLED) ? \\r
+ (0u) : (SD_INT_ON_TX_NOT_FULL))\r
+\r
+/* TX interrupt mask */\r
+#define SD_TX_INIT_INTERRUPTS_MASK (SD_INT_ON_SPI_DONE | \\r
+ SD_INT_ON_TX_EMPTY | \\r
+ SD_INT_ON_TX_NOT_FULL_DEF | \\r
+ SD_INT_ON_BYTE_COMP | \\r
+ SD_INT_ON_SPI_IDLE)\r
+\r
+#define SD_INT_ON_RX_FULL ((uint8) (0u << \\r
+ SD_STS_RX_FIFO_FULL_SHIFT))\r
+#define SD_INT_ON_RX_NOT_EMPTY ((uint8) (0u << \\r
+ SD_STS_RX_FIFO_NOT_EMPTY_SHIFT))\r
+#define SD_INT_ON_RX_OVER ((uint8) (0u << \\r
+ SD_STS_RX_FIFO_OVERRUN_SHIFT))\r
+\r
+/* RX interrupt mask */\r
+#define SD_RX_INIT_INTERRUPTS_MASK (SD_INT_ON_RX_FULL | \\r
+ SD_INT_ON_RX_NOT_EMPTY | \\r
+ SD_INT_ON_RX_OVER)\r
+/* Nubmer of bits to receive/transmit */\r
+#define SD_BITCTR_INIT (((uint8) (SD_DATA_WIDTH << 1u)) - 1u)\r
+\r
+\r
+/***************************************\r
+* Registers\r
+***************************************/\r
+\r
+#if(CY_PSOC3 || CY_PSOC5)\r
+ #define SD_TXDATA_REG (* (reg8 *) \\r
+ SD_BSPIM_sR8_Dp_u0__F0_REG)\r
+ #define SD_TXDATA_PTR ( (reg8 *) \\r
+ SD_BSPIM_sR8_Dp_u0__F0_REG)\r
+ #define SD_RXDATA_REG (* (reg8 *) \\r
+ SD_BSPIM_sR8_Dp_u0__F1_REG)\r
+ #define SD_RXDATA_PTR ( (reg8 *) \\r
+ SD_BSPIM_sR8_Dp_u0__F1_REG)\r
+#else /* PSOC4 */\r
+ #if(SD_USE_SECOND_DATAPATH)\r
+ #define SD_TXDATA_REG (* (reg16 *) \\r
+ SD_BSPIM_sR8_Dp_u0__16BIT_F0_REG)\r
+ #define SD_TXDATA_PTR ( (reg16 *) \\r
+ SD_BSPIM_sR8_Dp_u0__16BIT_F0_REG)\r
+ #define SD_RXDATA_REG (* (reg16 *) \\r
+ SD_BSPIM_sR8_Dp_u0__16BIT_F1_REG)\r
+ #define SD_RXDATA_PTR ( (reg16 *) \\r
+ SD_BSPIM_sR8_Dp_u0__16BIT_F1_REG)\r
+ #else\r
+ #define SD_TXDATA_REG (* (reg8 *) \\r
+ SD_BSPIM_sR8_Dp_u0__F0_REG)\r
+ #define SD_TXDATA_PTR ( (reg8 *) \\r
+ SD_BSPIM_sR8_Dp_u0__F0_REG)\r
+ #define SD_RXDATA_REG (* (reg8 *) \\r
+ SD_BSPIM_sR8_Dp_u0__F1_REG)\r
+ #define SD_RXDATA_PTR ( (reg8 *) \\r
+ SD_BSPIM_sR8_Dp_u0__F1_REG)\r
+ #endif /* (SD_USE_SECOND_DATAPATH) */\r
+#endif /* (CY_PSOC3 || CY_PSOC5) */\r
+\r
+#define SD_AUX_CONTROL_DP0_REG (* (reg8 *) \\r
+ SD_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)\r
+#define SD_AUX_CONTROL_DP0_PTR ( (reg8 *) \\r
+ SD_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)\r
+\r
+#if(SD_USE_SECOND_DATAPATH)\r
+ #define SD_AUX_CONTROL_DP1_REG (* (reg8 *) \\r
+ SD_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)\r
+ #define SD_AUX_CONTROL_DP1_PTR ( (reg8 *) \\r
+ SD_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)\r
+#endif /* (SD_USE_SECOND_DATAPATH) */\r
+\r
+#define SD_COUNTER_PERIOD_REG (* (reg8 *) SD_BSPIM_BitCounter__PERIOD_REG)\r
+#define SD_COUNTER_PERIOD_PTR ( (reg8 *) SD_BSPIM_BitCounter__PERIOD_REG)\r
+#define SD_COUNTER_CONTROL_REG (* (reg8 *) SD_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)\r
+#define SD_COUNTER_CONTROL_PTR ( (reg8 *) SD_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)\r
+\r
+#define SD_TX_STATUS_REG (* (reg8 *) SD_BSPIM_TxStsReg__STATUS_REG)\r
+#define SD_TX_STATUS_PTR ( (reg8 *) SD_BSPIM_TxStsReg__STATUS_REG)\r
+#define SD_RX_STATUS_REG (* (reg8 *) SD_BSPIM_RxStsReg__STATUS_REG)\r
+#define SD_RX_STATUS_PTR ( (reg8 *) SD_BSPIM_RxStsReg__STATUS_REG)\r
+\r
+#define SD_CONTROL_REG (* (reg8 *) \\r
+ SD_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)\r
+#define SD_CONTROL_PTR ( (reg8 *) \\r
+ SD_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)\r
+\r
+#define SD_TX_STATUS_MASK_REG (* (reg8 *) SD_BSPIM_TxStsReg__MASK_REG)\r
+#define SD_TX_STATUS_MASK_PTR ( (reg8 *) SD_BSPIM_TxStsReg__MASK_REG)\r
+#define SD_RX_STATUS_MASK_REG (* (reg8 *) SD_BSPIM_RxStsReg__MASK_REG)\r
+#define SD_RX_STATUS_MASK_PTR ( (reg8 *) SD_BSPIM_RxStsReg__MASK_REG)\r
+\r
+#define SD_TX_STATUS_ACTL_REG (* (reg8 *) SD_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)\r
+#define SD_TX_STATUS_ACTL_PTR ( (reg8 *) SD_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)\r
+#define SD_RX_STATUS_ACTL_REG (* (reg8 *) SD_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)\r
+#define SD_RX_STATUS_ACTL_PTR ( (reg8 *) SD_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)\r
+\r
+#if(SD_USE_SECOND_DATAPATH)\r
+ #define SD_AUX_CONTROLDP1 (SD_AUX_CONTROL_DP1_REG)\r
+#endif /* (SD_USE_SECOND_DATAPATH) */\r
+\r
+\r
+/***************************************\r
+* Register Constants\r
+***************************************/\r
+\r
+/* Status Register Definitions */\r
+#define SD_STS_SPI_DONE_SHIFT (0x00u)\r
+#define SD_STS_TX_FIFO_EMPTY_SHIFT (0x01u)\r
+#define SD_STS_TX_FIFO_NOT_FULL_SHIFT (0x02u)\r
+#define SD_STS_BYTE_COMPLETE_SHIFT (0x03u)\r
+#define SD_STS_SPI_IDLE_SHIFT (0x04u)\r
+#define SD_STS_RX_FIFO_FULL_SHIFT (0x04u)\r
+#define SD_STS_RX_FIFO_NOT_EMPTY_SHIFT (0x05u)\r
+#define SD_STS_RX_FIFO_OVERRUN_SHIFT (0x06u)\r
+\r
+#define SD_STS_SPI_DONE ((uint8) (0x01u << SD_STS_SPI_DONE_SHIFT))\r
+#define SD_STS_TX_FIFO_EMPTY ((uint8) (0x01u << SD_STS_TX_FIFO_EMPTY_SHIFT))\r
+#define SD_STS_TX_FIFO_NOT_FULL ((uint8) (0x01u << SD_STS_TX_FIFO_NOT_FULL_SHIFT))\r
+#define SD_STS_BYTE_COMPLETE ((uint8) (0x01u << SD_STS_BYTE_COMPLETE_SHIFT))\r
+#define SD_STS_SPI_IDLE ((uint8) (0x01u << SD_STS_SPI_IDLE_SHIFT))\r
+#define SD_STS_RX_FIFO_FULL ((uint8) (0x01u << SD_STS_RX_FIFO_FULL_SHIFT))\r
+#define SD_STS_RX_FIFO_NOT_EMPTY ((uint8) (0x01u << SD_STS_RX_FIFO_NOT_EMPTY_SHIFT))\r
+#define SD_STS_RX_FIFO_OVERRUN ((uint8) (0x01u << SD_STS_RX_FIFO_OVERRUN_SHIFT))\r
+\r
+/* TX and RX masks for clear on read bits */\r
+#define SD_TX_STS_CLR_ON_RD_BYTES_MASK (0x09u)\r
+#define SD_RX_STS_CLR_ON_RD_BYTES_MASK (0x40u)\r
+\r
+/* StatusI Register Interrupt Enable Control Bits */\r
+/* As defined by the Register map for the AUX Control Register */\r
+#define SD_INT_ENABLE (0x10u) /* Enable interrupt from statusi */\r
+#define SD_TX_FIFO_CLR (0x01u) /* F0 - TX FIFO */\r
+#define SD_RX_FIFO_CLR (0x02u) /* F1 - RX FIFO */\r
+#define SD_FIFO_CLR (SD_TX_FIFO_CLR | SD_RX_FIFO_CLR)\r
+\r
+/* Bit Counter (7-bit) Control Register Bit Definitions */\r
+/* As defined by the Register map for the AUX Control Register */\r
+#define SD_CNTR_ENABLE (0x20u) /* Enable CNT7 */\r
+\r
+/* Bi-Directional mode control bit */\r
+#define SD_CTRL_TX_SIGNAL_EN (0x01u)\r
+\r
+/* Datapath Auxillary Control Register definitions */\r
+#define SD_AUX_CTRL_FIFO0_CLR (0x01u)\r
+#define SD_AUX_CTRL_FIFO1_CLR (0x02u)\r
+#define SD_AUX_CTRL_FIFO0_LVL (0x04u)\r
+#define SD_AUX_CTRL_FIFO1_LVL (0x08u)\r
+#define SD_STATUS_ACTL_INT_EN_MASK (0x10u)\r
+\r
+/* Component disabled */\r
+#define SD_DISABLED (0u)\r
+\r
+\r
+/***************************************\r
+* Macros\r
+***************************************/\r
+\r
+/* Returns true if componentn enabled */\r
+#define SD_IS_ENABLED (0u != (SD_TX_STATUS_ACTL_REG & SD_INT_ENABLE))\r
+\r
+/* Retuns TX status register */\r
+#define SD_GET_STATUS_TX(swTxSts) ( (uint8)(SD_TX_STATUS_REG | \\r
+ ((swTxSts) & SD_TX_STS_CLR_ON_RD_BYTES_MASK)) )\r
+/* Retuns RX status register */\r
+#define SD_GET_STATUS_RX(swRxSts) ( (uint8)(SD_RX_STATUS_REG | \\r
+ ((swRxSts) & SD_RX_STS_CLR_ON_RD_BYTES_MASK)) )\r
+\r
+\r
+/***************************************\r
+* Obsolete definitions\r
+***************************************/\r
+\r
+/* Following definitions are for version compatibility.\r
+* They are obsolete in SPIM v2_30.\r
+* Please do not use it in new projects\r
+*/\r
+\r
+#define SD_WriteByte SD_WriteTxData\r
+#define SD_ReadByte SD_ReadRxData\r
+void SD_SetInterruptMode(uint8 intSrc) ;\r
+uint8 SD_ReadStatus(void) ;\r
+void SD_EnableInt(void) ;\r
+void SD_DisableInt(void) ;\r
+\r
+/* Obsolete register names. Not to be used in new designs */\r
+#define SD_TXDATA (SD_TXDATA_REG)\r
+#define SD_RXDATA (SD_RXDATA_REG)\r
+#define SD_AUX_CONTROLDP0 (SD_AUX_CONTROL_DP0_REG)\r
+#define SD_TXBUFFERREAD (SD_txBufferRead)\r
+#define SD_TXBUFFERWRITE (SD_txBufferWrite)\r
+#define SD_RXBUFFERREAD (SD_rxBufferRead)\r
+#define SD_RXBUFFERWRITE (SD_rxBufferWrite)\r
+\r
+#define SD_COUNTER_PERIOD (SD_COUNTER_PERIOD_REG)\r
+#define SD_COUNTER_CONTROL (SD_COUNTER_CONTROL_REG)\r
+#define SD_STATUS (SD_TX_STATUS_REG)\r
+#define SD_CONTROL (SD_CONTROL_REG)\r
+#define SD_STATUS_MASK (SD_TX_STATUS_MASK_REG)\r
+#define SD_STATUS_ACTL (SD_TX_STATUS_ACTL_REG)\r
+\r
+#define SD_INIT_INTERRUPTS_MASK (SD_INT_ON_SPI_DONE | \\r
+ SD_INT_ON_TX_EMPTY | \\r
+ SD_INT_ON_TX_NOT_FULL_DEF | \\r
+ SD_INT_ON_RX_FULL | \\r
+ SD_INT_ON_RX_NOT_EMPTY | \\r
+ SD_INT_ON_RX_OVER | \\r
+ SD_INT_ON_BYTE_COMP)\r
+ \r
+/* Following definitions are for version Compatibility.\r
+* They are obsolete in SPIM v2_40.\r
+* Please do not use it in new projects\r
+*/\r
+\r
+#define SD_DataWidth (SD_DATA_WIDTH)\r
+#define SD_InternalClockUsed (SD_INTERNAL_CLOCK)\r
+#define SD_InternalTxInterruptEnabled (SD_INTERNAL_TX_INT_ENABLED)\r
+#define SD_InternalRxInterruptEnabled (SD_INTERNAL_RX_INT_ENABLED)\r
+#define SD_ModeUseZero (SD_MODE_USE_ZERO)\r
+#define SD_BidirectionalMode (SD_BIDIRECTIONAL_MODE)\r
+#define SD_Mode (SD_MODE)\r
+#define SD_DATAWIDHT (SD_DATA_WIDTH)\r
+#define SD_InternalInterruptEnabled (0u)\r
+\r
+#define SD_TXBUFFERSIZE (SD_TX_BUFFER_SIZE)\r
+#define SD_RXBUFFERSIZE (SD_RX_BUFFER_SIZE)\r
+\r
+#define SD_TXBUFFER SD_txBuffer\r
+#define SD_RXBUFFER SD_rxBuffer\r
+\r
+#endif /* (CY_SPIM_SD_H) */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SDCard.c\r
+* Version 2.40\r
+*\r
+* Description:\r
+* This file provides all API functionality of the SPI Master component.\r
+*\r
+* Note:\r
+* None.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "SDCard_PVT.h"\r
+\r
+#if(SDCard_TX_SOFTWARE_BUF_ENABLED)\r
+ volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] = {0u};\r
+ volatile uint8 SDCard_txBufferFull;\r
+ volatile uint8 SDCard_txBufferRead;\r
+ volatile uint8 SDCard_txBufferWrite;\r
+#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */\r
+\r
+#if(SDCard_RX_SOFTWARE_BUF_ENABLED)\r
+ volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] = {0u};\r
+ volatile uint8 SDCard_rxBufferFull;\r
+ volatile uint8 SDCard_rxBufferRead;\r
+ volatile uint8 SDCard_rxBufferWrite;\r
+#endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */\r
+\r
+uint8 SDCard_initVar = 0u;\r
+\r
+volatile uint8 SDCard_swStatusTx;\r
+volatile uint8 SDCard_swStatusRx;\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_Init\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Inits/Restores default SPIM configuration provided with customizer.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Side Effects:\r
+* When this function is called it initializes all of the necessary parameters\r
+* for execution. i.e. setting the initial interrupt mask, configuring the\r
+* interrupt service routine, configuring the bit-counter parameters and\r
+* clearing the FIFO and Status Register.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void SDCard_Init(void) \r
+{\r
+ /* Initialize the Bit counter */\r
+ SDCard_COUNTER_PERIOD_REG = SDCard_BITCTR_INIT;\r
+\r
+ /* Init TX ISR */\r
+ #if(0u != SDCard_INTERNAL_TX_INT_ENABLED)\r
+ CyIntDisable (SDCard_TX_ISR_NUMBER);\r
+ CyIntSetPriority (SDCard_TX_ISR_NUMBER, SDCard_TX_ISR_PRIORITY);\r
+ (void) CyIntSetVector(SDCard_TX_ISR_NUMBER, &SDCard_TX_ISR);\r
+ #endif /* (0u != SDCard_INTERNAL_TX_INT_ENABLED) */\r
+\r
+ /* Init RX ISR */\r
+ #if(0u != SDCard_INTERNAL_RX_INT_ENABLED)\r
+ CyIntDisable (SDCard_RX_ISR_NUMBER);\r
+ CyIntSetPriority (SDCard_RX_ISR_NUMBER, SDCard_RX_ISR_PRIORITY);\r
+ (void) CyIntSetVector(SDCard_RX_ISR_NUMBER, &SDCard_RX_ISR);\r
+ #endif /* (0u != SDCard_INTERNAL_RX_INT_ENABLED) */\r
+\r
+ /* Clear any stray data from the RX and TX FIFO */\r
+ SDCard_ClearFIFO();\r
+\r
+ #if(SDCard_RX_SOFTWARE_BUF_ENABLED)\r
+ SDCard_rxBufferFull = 0u;\r
+ SDCard_rxBufferRead = 0u;\r
+ SDCard_rxBufferWrite = 0u;\r
+ #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ #if(SDCard_TX_SOFTWARE_BUF_ENABLED)\r
+ SDCard_txBufferFull = 0u;\r
+ SDCard_txBufferRead = 0u;\r
+ SDCard_txBufferWrite = 0u;\r
+ #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ (void) SDCard_ReadTxStatus(); /* Clear Tx status and swStatusTx */\r
+ (void) SDCard_ReadRxStatus(); /* Clear Rx status and swStatusRx */\r
+\r
+ /* Configure TX and RX interrupt mask */\r
+ SDCard_TX_STATUS_MASK_REG = SDCard_TX_INIT_INTERRUPTS_MASK;\r
+ SDCard_RX_STATUS_MASK_REG = SDCard_RX_INIT_INTERRUPTS_MASK;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_Enable\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enable SPIM component.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+*******************************************************************************/\r
+void SDCard_Enable(void) \r
+{\r
+ uint8 enableInterrupts;\r
+\r
+ enableInterrupts = CyEnterCriticalSection();\r
+ SDCard_COUNTER_CONTROL_REG |= SDCard_CNTR_ENABLE;\r
+ SDCard_TX_STATUS_ACTL_REG |= SDCard_INT_ENABLE;\r
+ SDCard_RX_STATUS_ACTL_REG |= SDCard_INT_ENABLE;\r
+ CyExitCriticalSection(enableInterrupts);\r
+\r
+ #if(0u != SDCard_INTERNAL_CLOCK)\r
+ SDCard_IntClock_Enable();\r
+ #endif /* (0u != SDCard_INTERNAL_CLOCK) */\r
+\r
+ SDCard_EnableTxInt();\r
+ SDCard_EnableRxInt();\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_Start\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Initialize and Enable the SPI Master component.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global variables:\r
+* SDCard_initVar - used to check initial configuration, modified on\r
+* first function call.\r
+*\r
+* Theory:\r
+* Enable the clock input to enable operation.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void SDCard_Start(void) \r
+{\r
+ if(0u == SDCard_initVar)\r
+ {\r
+ SDCard_Init();\r
+ SDCard_initVar = 1u;\r
+ }\r
+\r
+ SDCard_Enable();\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_Stop\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disable the SPI Master component.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Disable the clock input to enable operation.\r
+*\r
+*******************************************************************************/\r
+void SDCard_Stop(void) \r
+{\r
+ uint8 enableInterrupts;\r
+\r
+ enableInterrupts = CyEnterCriticalSection();\r
+ SDCard_TX_STATUS_ACTL_REG &= ((uint8) ~SDCard_INT_ENABLE);\r
+ SDCard_RX_STATUS_ACTL_REG &= ((uint8) ~SDCard_INT_ENABLE);\r
+ CyExitCriticalSection(enableInterrupts);\r
+\r
+ #if(0u != SDCard_INTERNAL_CLOCK)\r
+ SDCard_IntClock_Disable();\r
+ #endif /* (0u != SDCard_INTERNAL_CLOCK) */\r
+\r
+ SDCard_DisableTxInt();\r
+ SDCard_DisableRxInt();\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_EnableTxInt\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enable internal Tx interrupt generation.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Enable the internal Tx interrupt output -or- the interrupt component itself.\r
+*\r
+*******************************************************************************/\r
+void SDCard_EnableTxInt(void) \r
+{\r
+ #if(0u != SDCard_INTERNAL_TX_INT_ENABLED)\r
+ CyIntEnable(SDCard_TX_ISR_NUMBER);\r
+ #endif /* (0u != SDCard_INTERNAL_TX_INT_ENABLED) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_EnableRxInt\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enable internal Rx interrupt generation.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Enable the internal Rx interrupt output -or- the interrupt component itself.\r
+*\r
+*******************************************************************************/\r
+void SDCard_EnableRxInt(void) \r
+{\r
+ #if(0u != SDCard_INTERNAL_RX_INT_ENABLED)\r
+ CyIntEnable(SDCard_RX_ISR_NUMBER);\r
+ #endif /* (0u != SDCard_INTERNAL_RX_INT_ENABLED) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_DisableTxInt\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disable internal Tx interrupt generation.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Disable the internal Tx interrupt output -or- the interrupt component itself.\r
+*\r
+*******************************************************************************/\r
+void SDCard_DisableTxInt(void) \r
+{\r
+ #if(0u != SDCard_INTERNAL_TX_INT_ENABLED)\r
+ CyIntDisable(SDCard_TX_ISR_NUMBER);\r
+ #endif /* (0u != SDCard_INTERNAL_TX_INT_ENABLED) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_DisableRxInt\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disable internal Rx interrupt generation.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Disable the internal Rx interrupt output -or- the interrupt component itself.\r
+*\r
+*******************************************************************************/\r
+void SDCard_DisableRxInt(void) \r
+{\r
+ #if(0u != SDCard_INTERNAL_RX_INT_ENABLED)\r
+ CyIntDisable(SDCard_RX_ISR_NUMBER);\r
+ #endif /* (0u != SDCard_INTERNAL_RX_INT_ENABLED) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_SetTxInterruptMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Configure which status bits trigger an interrupt event.\r
+*\r
+* Parameters:\r
+* intSrc: An or'd combination of the desired status bit masks (defined in the\r
+* header file).\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Enables the output of specific status bits to the interrupt controller.\r
+*\r
+*******************************************************************************/\r
+void SDCard_SetTxInterruptMode(uint8 intSrc) \r
+{\r
+ SDCard_TX_STATUS_MASK_REG = intSrc;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_SetRxInterruptMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Configure which status bits trigger an interrupt event.\r
+*\r
+* Parameters:\r
+* intSrc: An or'd combination of the desired status bit masks (defined in the\r
+* header file).\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Enables the output of specific status bits to the interrupt controller.\r
+*\r
+*******************************************************************************/\r
+void SDCard_SetRxInterruptMode(uint8 intSrc) \r
+{\r
+ SDCard_RX_STATUS_MASK_REG = intSrc;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_ReadTxStatus\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the Tx status register for the component.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* Contents of the Tx status register.\r
+*\r
+* Global variables:\r
+* SDCard_swStatusTx - used to store in software status register,\r
+* modified every function call - resets to zero.\r
+*\r
+* Theory:\r
+* Allows the user and the API to read the Tx status register for error\r
+* detection and flow control.\r
+*\r
+* Side Effects:\r
+* Clear Tx status register of the component.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+uint8 SDCard_ReadTxStatus(void) \r
+{\r
+ uint8 tmpStatus;\r
+\r
+ #if(SDCard_TX_SOFTWARE_BUF_ENABLED)\r
+ /* Disable TX interrupt to protect global veriables */\r
+ SDCard_DisableTxInt();\r
+\r
+ tmpStatus = SDCard_GET_STATUS_TX(SDCard_swStatusTx);\r
+ SDCard_swStatusTx = 0u;\r
+\r
+ SDCard_EnableTxInt();\r
+\r
+ #else\r
+\r
+ tmpStatus = SDCard_TX_STATUS_REG;\r
+\r
+ #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ return(tmpStatus);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_ReadRxStatus\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the Rx status register for the component.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* Contents of the Rx status register.\r
+*\r
+* Global variables:\r
+* SDCard_swStatusRx - used to store in software Rx status register,\r
+* modified every function call - resets to zero.\r
+*\r
+* Theory:\r
+* Allows the user and the API to read the Rx status register for error\r
+* detection and flow control.\r
+*\r
+* Side Effects:\r
+* Clear Rx status register of the component.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+uint8 SDCard_ReadRxStatus(void) \r
+{\r
+ uint8 tmpStatus;\r
+\r
+ #if(SDCard_RX_SOFTWARE_BUF_ENABLED)\r
+ /* Disable RX interrupt to protect global veriables */\r
+ SDCard_DisableRxInt();\r
+\r
+ tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx);\r
+ SDCard_swStatusRx = 0u;\r
+\r
+ SDCard_EnableRxInt();\r
+\r
+ #else\r
+\r
+ tmpStatus = SDCard_RX_STATUS_REG;\r
+\r
+ #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ return(tmpStatus);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_WriteTxData\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Write a byte of data to be sent across the SPI.\r
+*\r
+* Parameters:\r
+* txDataByte: The data value to send across the SPI.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global variables:\r
+* SDCard_txBufferWrite - used for the account of the bytes which\r
+* have been written down in the TX software buffer, modified every function\r
+* call if TX Software Buffer is used.\r
+* SDCard_txBufferRead - used for the account of the bytes which\r
+* have been read from the TX software buffer.\r
+* SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] - used to store\r
+* data to sending, modified every function call if TX Software Buffer is used.\r
+*\r
+* Theory:\r
+* Allows the user to transmit any byte of data in a single transfer.\r
+*\r
+* Side Effects:\r
+* If this function is called again before the previous byte is finished then\r
+* the next byte will be appended to the transfer with no time between\r
+* the byte transfers. Clear Tx status register of the component.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void SDCard_WriteTxData(uint8 txData) \r
+{\r
+ #if(SDCard_TX_SOFTWARE_BUF_ENABLED)\r
+\r
+ uint8 tempStatus;\r
+ uint8 tmpTxBufferRead;\r
+\r
+ /* Block if TX buffer is FULL: don't overwrite */\r
+ do\r
+ {\r
+ tmpTxBufferRead = SDCard_txBufferRead;\r
+ if(0u == tmpTxBufferRead)\r
+ {\r
+ tmpTxBufferRead = (SDCard_TX_BUFFER_SIZE - 1u);\r
+ }\r
+ else\r
+ {\r
+ tmpTxBufferRead--;\r
+ }\r
+\r
+ }while(tmpTxBufferRead == SDCard_txBufferWrite);\r
+\r
+ /* Disable TX interrupt to protect global veriables */\r
+ SDCard_DisableTxInt();\r
+\r
+ tempStatus = SDCard_GET_STATUS_TX(SDCard_swStatusTx);\r
+ SDCard_swStatusTx = tempStatus;\r
+\r
+\r
+ if((SDCard_txBufferRead == SDCard_txBufferWrite) &&\r
+ (0u != (SDCard_swStatusTx & SDCard_STS_TX_FIFO_NOT_FULL)))\r
+ {\r
+ /* Add directly to the TX FIFO */\r
+ CY_SET_REG8(SDCard_TXDATA_PTR, txData);\r
+ }\r
+ else\r
+ {\r
+ /* Add to the TX software buffer */\r
+ SDCard_txBufferWrite++;\r
+ if(SDCard_txBufferWrite >= SDCard_TX_BUFFER_SIZE)\r
+ {\r
+ SDCard_txBufferWrite = 0u;\r
+ }\r
+\r
+ if(SDCard_txBufferWrite == SDCard_txBufferRead)\r
+ {\r
+ SDCard_txBufferRead++;\r
+ if(SDCard_txBufferRead >= SDCard_TX_BUFFER_SIZE)\r
+ {\r
+ SDCard_txBufferRead = 0u;\r
+ }\r
+ SDCard_txBufferFull = 1u;\r
+ }\r
+\r
+ SDCard_txBuffer[SDCard_txBufferWrite] = txData;\r
+\r
+ SDCard_TX_STATUS_MASK_REG |= SDCard_STS_TX_FIFO_NOT_FULL;\r
+ }\r
+\r
+ SDCard_EnableTxInt();\r
+\r
+ #else\r
+\r
+ while(0u == (SDCard_TX_STATUS_REG & SDCard_STS_TX_FIFO_NOT_FULL))\r
+ {\r
+ ; /* Wait for room in FIFO */\r
+ }\r
+\r
+ /* Put byte in TX FIFO */\r
+ CY_SET_REG8(SDCard_TXDATA_PTR, txData);\r
+\r
+ #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_ReadRxData\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the next byte of data received across the SPI.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* The next byte of data read from the FIFO.\r
+*\r
+* Global variables:\r
+* SDCard_rxBufferWrite - used for the account of the bytes which\r
+* have been written down in the RX software buffer.\r
+* SDCard_rxBufferRead - used for the account of the bytes which\r
+* have been read from the RX software buffer, modified every function\r
+* call if RX Software Buffer is used.\r
+* SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] - used to store\r
+* received data.\r
+*\r
+* Theory:\r
+* Allows the user to read a byte of data received.\r
+*\r
+* Side Effects:\r
+* Will return invalid data if the FIFO is empty. The user should Call\r
+* GetRxBufferSize() and if it returns a non-zero value then it is safe to call\r
+* ReadByte() function.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+uint8 SDCard_ReadRxData(void) \r
+{\r
+ uint8 rxData;\r
+\r
+ #if(SDCard_RX_SOFTWARE_BUF_ENABLED)\r
+\r
+ /* Disable RX interrupt to protect global veriables */\r
+ SDCard_DisableRxInt();\r
+\r
+ if(SDCard_rxBufferRead != SDCard_rxBufferWrite)\r
+ {\r
+ if(0u == SDCard_rxBufferFull)\r
+ {\r
+ SDCard_rxBufferRead++;\r
+ if(SDCard_rxBufferRead >= SDCard_RX_BUFFER_SIZE)\r
+ {\r
+ SDCard_rxBufferRead = 0u;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ SDCard_rxBufferFull = 0u;\r
+ }\r
+ }\r
+\r
+ rxData = SDCard_rxBuffer[SDCard_rxBufferRead];\r
+\r
+ SDCard_EnableRxInt();\r
+\r
+ #else\r
+\r
+ rxData = CY_GET_REG8(SDCard_RXDATA_PTR);\r
+\r
+ #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ return(rxData);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_GetRxBufferSize\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Returns the number of bytes/words of data currently held in the RX buffer.\r
+* If RX Software Buffer not used then function return 0 if FIFO empty or 1 if\r
+* FIFO not empty. In another case function return size of RX Software Buffer.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* Integer count of the number of bytes/words in the RX buffer.\r
+*\r
+* Global variables:\r
+* SDCard_rxBufferWrite - used for the account of the bytes which\r
+* have been written down in the RX software buffer.\r
+* SDCard_rxBufferRead - used for the account of the bytes which\r
+* have been read from the RX software buffer.\r
+*\r
+* Side Effects:\r
+* Clear status register of the component.\r
+*\r
+*******************************************************************************/\r
+uint8 SDCard_GetRxBufferSize(void) \r
+{\r
+ uint8 size;\r
+\r
+ #if(SDCard_RX_SOFTWARE_BUF_ENABLED)\r
+\r
+ /* Disable RX interrupt to protect global veriables */\r
+ SDCard_DisableRxInt();\r
+\r
+ if(SDCard_rxBufferRead == SDCard_rxBufferWrite)\r
+ {\r
+ size = 0u;\r
+ }\r
+ else if(SDCard_rxBufferRead < SDCard_rxBufferWrite)\r
+ {\r
+ size = (SDCard_rxBufferWrite - SDCard_rxBufferRead);\r
+ }\r
+ else\r
+ {\r
+ size = (SDCard_RX_BUFFER_SIZE - SDCard_rxBufferRead) + SDCard_rxBufferWrite;\r
+ }\r
+\r
+ SDCard_EnableRxInt();\r
+\r
+ #else\r
+\r
+ /* We can only know if there is data in the RX FIFO */\r
+ size = (0u != (SDCard_RX_STATUS_REG & SDCard_STS_RX_FIFO_NOT_EMPTY)) ? 1u : 0u;\r
+\r
+ #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ return(size);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_GetTxBufferSize\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Returns the number of bytes/words of data currently held in the TX buffer.\r
+* If TX Software Buffer not used then function return 0 - if FIFO empty, 1 - if\r
+* FIFO not full, 4 - if FIFO full. In another case function return size of TX\r
+* Software Buffer.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* Integer count of the number of bytes/words in the TX buffer.\r
+*\r
+* Global variables:\r
+* SDCard_txBufferWrite - used for the account of the bytes which\r
+* have been written down in the TX software buffer.\r
+* SDCard_txBufferRead - used for the account of the bytes which\r
+* have been read from the TX software buffer.\r
+*\r
+* Side Effects:\r
+* Clear status register of the component.\r
+*\r
+*******************************************************************************/\r
+uint8 SDCard_GetTxBufferSize(void) \r
+{\r
+ uint8 size;\r
+\r
+ #if(SDCard_TX_SOFTWARE_BUF_ENABLED)\r
+ /* Disable TX interrupt to protect global veriables */\r
+ SDCard_DisableTxInt();\r
+\r
+ if(SDCard_txBufferRead == SDCard_txBufferWrite)\r
+ {\r
+ size = 0u;\r
+ }\r
+ else if(SDCard_txBufferRead < SDCard_txBufferWrite)\r
+ {\r
+ size = (SDCard_txBufferWrite - SDCard_txBufferRead);\r
+ }\r
+ else\r
+ {\r
+ size = (SDCard_TX_BUFFER_SIZE - SDCard_txBufferRead) + SDCard_txBufferWrite;\r
+ }\r
+\r
+ SDCard_EnableTxInt();\r
+\r
+ #else\r
+\r
+ size = SDCard_TX_STATUS_REG;\r
+\r
+ if(0u != (size & SDCard_STS_TX_FIFO_EMPTY))\r
+ {\r
+ size = 0u;\r
+ }\r
+ else if(0u != (size & SDCard_STS_TX_FIFO_NOT_FULL))\r
+ {\r
+ size = 1u;\r
+ }\r
+ else\r
+ {\r
+ size = SDCard_FIFO_SIZE;\r
+ }\r
+\r
+ #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ return(size);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_ClearRxBuffer\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Clear the RX RAM buffer by setting the read and write pointers both to zero.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global variables:\r
+* SDCard_rxBufferWrite - used for the account of the bytes which\r
+* have been written down in the RX software buffer, modified every function\r
+* call - resets to zero.\r
+* SDCard_rxBufferRead - used for the account of the bytes which\r
+* have been read from the RX software buffer, modified every function call -\r
+* resets to zero.\r
+*\r
+* Theory:\r
+* Setting the pointers to zero makes the system believe there is no data to\r
+* read and writing will resume at address 0 overwriting any data that may have\r
+* remained in the RAM.\r
+*\r
+* Side Effects:\r
+* Any received data not read from the RAM buffer will be lost when overwritten.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void SDCard_ClearRxBuffer(void) \r
+{\r
+ /* Clear Hardware RX FIFO */\r
+ while(0u !=(SDCard_RX_STATUS_REG & SDCard_STS_RX_FIFO_NOT_EMPTY))\r
+ {\r
+ (void) CY_GET_REG8(SDCard_RXDATA_PTR);\r
+ }\r
+\r
+ #if(SDCard_RX_SOFTWARE_BUF_ENABLED)\r
+ /* Disable RX interrupt to protect global veriables */\r
+ SDCard_DisableRxInt();\r
+\r
+ SDCard_rxBufferFull = 0u;\r
+ SDCard_rxBufferRead = 0u;\r
+ SDCard_rxBufferWrite = 0u;\r
+\r
+ SDCard_EnableRxInt();\r
+ #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_ClearTxBuffer\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Clear the TX RAM buffer by setting the read and write pointers both to zero.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global variables:\r
+* SDCard_txBufferWrite - used for the account of the bytes which\r
+* have been written down in the TX software buffer, modified every function\r
+* call - resets to zero.\r
+* SDCard_txBufferRead - used for the account of the bytes which\r
+* have been read from the TX software buffer, modified every function call -\r
+* resets to zero.\r
+*\r
+* Theory:\r
+* Setting the pointers to zero makes the system believe there is no data to\r
+* read and writing will resume at address 0 overwriting any data that may have\r
+* remained in the RAM.\r
+*\r
+* Side Effects:\r
+* Any data not yet transmitted from the RAM buffer will be lost when\r
+* overwritten.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void SDCard_ClearTxBuffer(void) \r
+{\r
+ uint8 enableInterrupts;\r
+\r
+ enableInterrupts = CyEnterCriticalSection();\r
+ /* Clear TX FIFO */\r
+ SDCard_AUX_CONTROL_DP0_REG |= ((uint8) SDCard_TX_FIFO_CLR);\r
+ SDCard_AUX_CONTROL_DP0_REG &= ((uint8) ~SDCard_TX_FIFO_CLR);\r
+\r
+ #if(SDCard_USE_SECOND_DATAPATH)\r
+ /* Clear TX FIFO for 2nd Datapath */\r
+ SDCard_AUX_CONTROL_DP1_REG |= ((uint8) SDCard_TX_FIFO_CLR);\r
+ SDCard_AUX_CONTROL_DP1_REG &= ((uint8) ~SDCard_TX_FIFO_CLR);\r
+ #endif /* (SDCard_USE_SECOND_DATAPATH) */\r
+ CyExitCriticalSection(enableInterrupts);\r
+\r
+ #if(SDCard_TX_SOFTWARE_BUF_ENABLED)\r
+ /* Disable TX interrupt to protect global veriables */\r
+ SDCard_DisableTxInt();\r
+\r
+ SDCard_txBufferFull = 0u;\r
+ SDCard_txBufferRead = 0u;\r
+ SDCard_txBufferWrite = 0u;\r
+\r
+ /* Buffer is EMPTY: disable TX FIFO NOT FULL interrupt */\r
+ SDCard_TX_STATUS_MASK_REG &= ((uint8) ~SDCard_STS_TX_FIFO_NOT_FULL);\r
+\r
+ SDCard_EnableTxInt();\r
+ #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */\r
+}\r
+\r
+\r
+#if(0u != SDCard_BIDIRECTIONAL_MODE)\r
+ /*******************************************************************************\r
+ * Function Name: SDCard_TxEnable\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * If the SPI master is configured to use a single bi-directional pin then this\r
+ * will set the bi-directional pin to transmit.\r
+ *\r
+ * Parameters:\r
+ * None.\r
+ *\r
+ * Return:\r
+ * None.\r
+ *\r
+ *******************************************************************************/\r
+ void SDCard_TxEnable(void) \r
+ {\r
+ SDCard_CONTROL_REG |= SDCard_CTRL_TX_SIGNAL_EN;\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: SDCard_TxDisable\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * If the SPI master is configured to use a single bi-directional pin then this\r
+ * will set the bi-directional pin to receive.\r
+ *\r
+ * Parameters:\r
+ * None.\r
+ *\r
+ * Return:\r
+ * None.\r
+ *\r
+ *******************************************************************************/\r
+ void SDCard_TxDisable(void) \r
+ {\r
+ SDCard_CONTROL_REG &= ((uint8) ~SDCard_CTRL_TX_SIGNAL_EN);\r
+ }\r
+\r
+#endif /* (0u != SDCard_BIDIRECTIONAL_MODE) */\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_PutArray\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Write available data from ROM/RAM to the TX buffer while space is available\r
+* in the TX buffer. Keep trying until all data is passed to the TX buffer.\r
+*\r
+* Parameters:\r
+* *buffer: Pointer to the location in RAM containing the data to send\r
+* byteCount: The number of bytes to move to the transmit buffer.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Side Effects:\r
+* Will stay in this routine until all data has been sent. May get locked in\r
+* this loop if data is not being initiated by the master if there is not\r
+* enough room in the TX FIFO.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void SDCard_PutArray(const uint8 buffer[], uint8 byteCount)\r
+ \r
+{\r
+ uint8 bufIndex;\r
+\r
+ bufIndex = 0u;\r
+\r
+ while(byteCount > 0u)\r
+ {\r
+ SDCard_WriteTxData(buffer[bufIndex]);\r
+ bufIndex++;\r
+ byteCount--;\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_ClearFIFO\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Clear the RX and TX FIFO's of all data for a fresh start.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Side Effects:\r
+* Clear status register of the component.\r
+*\r
+*******************************************************************************/\r
+void SDCard_ClearFIFO(void) \r
+{\r
+ uint8 enableInterrupts;\r
+\r
+ /* Clear Hardware RX FIFO */\r
+ while(0u !=(SDCard_RX_STATUS_REG & SDCard_STS_RX_FIFO_NOT_EMPTY))\r
+ {\r
+ (void) CY_GET_REG8(SDCard_RXDATA_PTR);\r
+ }\r
+\r
+ enableInterrupts = CyEnterCriticalSection();\r
+ /* Clear TX FIFO */\r
+ SDCard_AUX_CONTROL_DP0_REG |= ((uint8) SDCard_TX_FIFO_CLR);\r
+ SDCard_AUX_CONTROL_DP0_REG &= ((uint8) ~SDCard_TX_FIFO_CLR);\r
+\r
+ #if(SDCard_USE_SECOND_DATAPATH)\r
+ /* Clear TX FIFO for 2nd Datapath */\r
+ SDCard_AUX_CONTROL_DP1_REG |= ((uint8) SDCard_TX_FIFO_CLR);\r
+ SDCard_AUX_CONTROL_DP1_REG &= ((uint8) ~SDCard_TX_FIFO_CLR);\r
+ #endif /* (SDCard_USE_SECOND_DATAPATH) */\r
+ CyExitCriticalSection(enableInterrupts);\r
+}\r
+\r
+\r
+/* Following functions are for version Compatibility, they are obsolete.\r
+* Please do not use it in new projects.\r
+*/\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_EnableInt\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enable internal interrupt generation.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Enable the internal interrupt output -or- the interrupt component itself.\r
+*\r
+*******************************************************************************/\r
+void SDCard_EnableInt(void) \r
+{\r
+ SDCard_EnableRxInt();\r
+ SDCard_EnableTxInt();\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_DisableInt\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Disable internal interrupt generation.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Disable the internal interrupt output -or- the interrupt component itself.\r
+*\r
+*******************************************************************************/\r
+void SDCard_DisableInt(void) \r
+{\r
+ SDCard_DisableTxInt();\r
+ SDCard_DisableRxInt();\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_SetInterruptMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Configure which status bits trigger an interrupt event.\r
+*\r
+* Parameters:\r
+* intSrc: An or'd combination of the desired status bit masks (defined in the\r
+* header file).\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Theory:\r
+* Enables the output of specific status bits to the interrupt controller.\r
+*\r
+*******************************************************************************/\r
+void SDCard_SetInterruptMode(uint8 intSrc) \r
+{\r
+ SDCard_TX_STATUS_MASK_REG = (intSrc & ((uint8) ~SDCard_STS_SPI_IDLE));\r
+ SDCard_RX_STATUS_MASK_REG = intSrc;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_ReadStatus\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the status register for the component.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* Contents of the status register.\r
+*\r
+* Global variables:\r
+* SDCard_swStatus - used to store in software status register,\r
+* modified every function call - resets to zero.\r
+*\r
+* Theory:\r
+* Allows the user and the API to read the status register for error detection\r
+* and flow control.\r
+*\r
+* Side Effects:\r
+* Clear status register of the component.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+uint8 SDCard_ReadStatus(void) \r
+{\r
+ uint8 tmpStatus;\r
+\r
+ #if(SDCard_TX_SOFTWARE_BUF_ENABLED || SDCard_RX_SOFTWARE_BUF_ENABLED)\r
+\r
+ SDCard_DisableInt();\r
+\r
+ tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx);\r
+ tmpStatus |= SDCard_GET_STATUS_TX(SDCard_swStatusTx);\r
+ tmpStatus &= ((uint8) ~SDCard_STS_SPI_IDLE);\r
+\r
+ SDCard_swStatusTx = 0u;\r
+ SDCard_swStatusRx = 0u;\r
+\r
+ SDCard_EnableInt();\r
+\r
+ #else\r
+\r
+ tmpStatus = SDCard_RX_STATUS_REG;\r
+ tmpStatus |= SDCard_TX_STATUS_REG;\r
+ tmpStatus &= ((uint8) ~SDCard_STS_SPI_IDLE);\r
+\r
+ #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED || SDCard_RX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ return(tmpStatus);\r
+}\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SDCard.h\r
+* Version 2.40\r
+*\r
+* Description:\r
+* Contains the function prototypes, constants and register definition\r
+* of the SPI Master Component.\r
+*\r
+* Note:\r
+* None\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_SPIM_SDCard_H)\r
+#define CY_SPIM_SDCard_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+#include "CyLib.h"\r
+\r
+/* Check to see if required defines such as CY_PSOC5A are available */\r
+/* They are defined starting with cy_boot v3.0 */\r
+#if !defined (CY_PSOC5A)\r
+ #error Component SPI_Master_v2_40 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5A) */\r
+\r
+\r
+/***************************************\r
+* Conditional Compilation Parameters\r
+***************************************/\r
+\r
+#define SDCard_INTERNAL_CLOCK (0u)\r
+\r
+#if(0u != SDCard_INTERNAL_CLOCK)\r
+ #include "SDCard_IntClock.h"\r
+#endif /* (0u != SDCard_INTERNAL_CLOCK) */\r
+\r
+#define SDCard_MODE (1u)\r
+#define SDCard_DATA_WIDTH (8u)\r
+#define SDCard_MODE_USE_ZERO (1u)\r
+#define SDCard_BIDIRECTIONAL_MODE (0u)\r
+\r
+/* Internal interrupt handling */\r
+#define SDCard_TX_BUFFER_SIZE (4u)\r
+#define SDCard_RX_BUFFER_SIZE (4u)\r
+#define SDCard_INTERNAL_TX_INT_ENABLED (1u)\r
+#define SDCard_INTERNAL_RX_INT_ENABLED (1u)\r
+\r
+#define SDCard_SINGLE_REG_SIZE (8u)\r
+#define SDCard_USE_SECOND_DATAPATH (SDCard_DATA_WIDTH > SDCard_SINGLE_REG_SIZE)\r
+\r
+#define SDCard_FIFO_SIZE (4u)\r
+#define SDCard_TX_SOFTWARE_BUF_ENABLED ((0u != SDCard_INTERNAL_TX_INT_ENABLED) && \\r
+ (SDCard_TX_BUFFER_SIZE > SDCard_FIFO_SIZE))\r
+\r
+#define SDCard_RX_SOFTWARE_BUF_ENABLED ((0u != SDCard_INTERNAL_RX_INT_ENABLED) && \\r
+ (SDCard_RX_BUFFER_SIZE > SDCard_FIFO_SIZE))\r
+\r
+\r
+/***************************************\r
+* Data Struct Definition\r
+***************************************/\r
+\r
+/* Sleep Mode API Support */\r
+typedef struct\r
+{\r
+ uint8 enableState;\r
+ uint8 cntrPeriod;\r
+ #if(CY_UDB_V0)\r
+ uint8 saveSrTxIntMask;\r
+ uint8 saveSrRxIntMask;\r
+ #endif /* (CY_UDB_V0) */\r
+\r
+} SDCard_BACKUP_STRUCT;\r
+\r
+\r
+/***************************************\r
+* Function Prototypes\r
+***************************************/\r
+\r
+void SDCard_Init(void) ;\r
+void SDCard_Enable(void) ;\r
+void SDCard_Start(void) ;\r
+void SDCard_Stop(void) ;\r
+\r
+void SDCard_EnableTxInt(void) ;\r
+void SDCard_EnableRxInt(void) ;\r
+void SDCard_DisableTxInt(void) ;\r
+void SDCard_DisableRxInt(void) ;\r
+\r
+void SDCard_Sleep(void) ;\r
+void SDCard_Wakeup(void) ;\r
+void SDCard_SaveConfig(void) ;\r
+void SDCard_RestoreConfig(void) ;\r
+\r
+void SDCard_SetTxInterruptMode(uint8 intSrc) ;\r
+void SDCard_SetRxInterruptMode(uint8 intSrc) ;\r
+uint8 SDCard_ReadTxStatus(void) ;\r
+uint8 SDCard_ReadRxStatus(void) ;\r
+void SDCard_WriteTxData(uint8 txData) \\r
+ ;\r
+uint8 SDCard_ReadRxData(void) \\r
+ ;\r
+uint8 SDCard_GetRxBufferSize(void) ;\r
+uint8 SDCard_GetTxBufferSize(void) ;\r
+void SDCard_ClearRxBuffer(void) ;\r
+void SDCard_ClearTxBuffer(void) ;\r
+void SDCard_ClearFIFO(void) ;\r
+void SDCard_PutArray(const uint8 buffer[], uint8 byteCount) \\r
+ ;\r
+\r
+#if(0u != SDCard_BIDIRECTIONAL_MODE)\r
+ void SDCard_TxEnable(void) ;\r
+ void SDCard_TxDisable(void) ;\r
+#endif /* (0u != SDCard_BIDIRECTIONAL_MODE) */\r
+\r
+CY_ISR_PROTO(SDCard_TX_ISR);\r
+CY_ISR_PROTO(SDCard_RX_ISR);\r
+\r
+\r
+/**********************************\r
+* Variable with external linkage\r
+**********************************/\r
+\r
+extern uint8 SDCard_initVar;\r
+\r
+\r
+/***************************************\r
+* API Constants\r
+***************************************/\r
+\r
+#define SDCard_TX_ISR_NUMBER ((uint8) (SDCard_TxInternalInterrupt__INTC_NUMBER))\r
+#define SDCard_RX_ISR_NUMBER ((uint8) (SDCard_RxInternalInterrupt__INTC_NUMBER))\r
+\r
+#define SDCard_TX_ISR_PRIORITY ((uint8) (SDCard_TxInternalInterrupt__INTC_PRIOR_NUM))\r
+#define SDCard_RX_ISR_PRIORITY ((uint8) (SDCard_RxInternalInterrupt__INTC_PRIOR_NUM))\r
+\r
+\r
+/***************************************\r
+* Initial Parameter Constants\r
+***************************************/\r
+\r
+#define SDCard_INT_ON_SPI_DONE ((uint8) (0u << SDCard_STS_SPI_DONE_SHIFT))\r
+#define SDCard_INT_ON_TX_EMPTY ((uint8) (0u << SDCard_STS_TX_FIFO_EMPTY_SHIFT))\r
+#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (0u << \\r
+ SDCard_STS_TX_FIFO_NOT_FULL_SHIFT))\r
+#define SDCard_INT_ON_BYTE_COMP ((uint8) (0u << SDCard_STS_BYTE_COMPLETE_SHIFT))\r
+#define SDCard_INT_ON_SPI_IDLE ((uint8) (0u << SDCard_STS_SPI_IDLE_SHIFT))\r
+\r
+/* Disable TX_NOT_FULL if software buffer is used */\r
+#define SDCard_INT_ON_TX_NOT_FULL_DEF ((SDCard_TX_SOFTWARE_BUF_ENABLED) ? \\r
+ (0u) : (SDCard_INT_ON_TX_NOT_FULL))\r
+\r
+/* TX interrupt mask */\r
+#define SDCard_TX_INIT_INTERRUPTS_MASK (SDCard_INT_ON_SPI_DONE | \\r
+ SDCard_INT_ON_TX_EMPTY | \\r
+ SDCard_INT_ON_TX_NOT_FULL_DEF | \\r
+ SDCard_INT_ON_BYTE_COMP | \\r
+ SDCard_INT_ON_SPI_IDLE)\r
+\r
+#define SDCard_INT_ON_RX_FULL ((uint8) (0u << \\r
+ SDCard_STS_RX_FIFO_FULL_SHIFT))\r
+#define SDCard_INT_ON_RX_NOT_EMPTY ((uint8) (0u << \\r
+ SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT))\r
+#define SDCard_INT_ON_RX_OVER ((uint8) (0u << \\r
+ SDCard_STS_RX_FIFO_OVERRUN_SHIFT))\r
+\r
+/* RX interrupt mask */\r
+#define SDCard_RX_INIT_INTERRUPTS_MASK (SDCard_INT_ON_RX_FULL | \\r
+ SDCard_INT_ON_RX_NOT_EMPTY | \\r
+ SDCard_INT_ON_RX_OVER)\r
+/* Nubmer of bits to receive/transmit */\r
+#define SDCard_BITCTR_INIT (((uint8) (SDCard_DATA_WIDTH << 1u)) - 1u)\r
+\r
+\r
+/***************************************\r
+* Registers\r
+***************************************/\r
+\r
+#if(CY_PSOC3 || CY_PSOC5)\r
+ #define SDCard_TXDATA_REG (* (reg8 *) \\r
+ SDCard_BSPIM_sR8_Dp_u0__F0_REG)\r
+ #define SDCard_TXDATA_PTR ( (reg8 *) \\r
+ SDCard_BSPIM_sR8_Dp_u0__F0_REG)\r
+ #define SDCard_RXDATA_REG (* (reg8 *) \\r
+ SDCard_BSPIM_sR8_Dp_u0__F1_REG)\r
+ #define SDCard_RXDATA_PTR ( (reg8 *) \\r
+ SDCard_BSPIM_sR8_Dp_u0__F1_REG)\r
+#else /* PSOC4 */\r
+ #if(SDCard_USE_SECOND_DATAPATH)\r
+ #define SDCard_TXDATA_REG (* (reg16 *) \\r
+ SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG)\r
+ #define SDCard_TXDATA_PTR ( (reg16 *) \\r
+ SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG)\r
+ #define SDCard_RXDATA_REG (* (reg16 *) \\r
+ SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG)\r
+ #define SDCard_RXDATA_PTR ( (reg16 *) \\r
+ SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG)\r
+ #else\r
+ #define SDCard_TXDATA_REG (* (reg8 *) \\r
+ SDCard_BSPIM_sR8_Dp_u0__F0_REG)\r
+ #define SDCard_TXDATA_PTR ( (reg8 *) \\r
+ SDCard_BSPIM_sR8_Dp_u0__F0_REG)\r
+ #define SDCard_RXDATA_REG (* (reg8 *) \\r
+ SDCard_BSPIM_sR8_Dp_u0__F1_REG)\r
+ #define SDCard_RXDATA_PTR ( (reg8 *) \\r
+ SDCard_BSPIM_sR8_Dp_u0__F1_REG)\r
+ #endif /* (SDCard_USE_SECOND_DATAPATH) */\r
+#endif /* (CY_PSOC3 || CY_PSOC5) */\r
+\r
+#define SDCard_AUX_CONTROL_DP0_REG (* (reg8 *) \\r
+ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)\r
+#define SDCard_AUX_CONTROL_DP0_PTR ( (reg8 *) \\r
+ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG)\r
+\r
+#if(SDCard_USE_SECOND_DATAPATH)\r
+ #define SDCard_AUX_CONTROL_DP1_REG (* (reg8 *) \\r
+ SDCard_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)\r
+ #define SDCard_AUX_CONTROL_DP1_PTR ( (reg8 *) \\r
+ SDCard_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG)\r
+#endif /* (SDCard_USE_SECOND_DATAPATH) */\r
+\r
+#define SDCard_COUNTER_PERIOD_REG (* (reg8 *) SDCard_BSPIM_BitCounter__PERIOD_REG)\r
+#define SDCard_COUNTER_PERIOD_PTR ( (reg8 *) SDCard_BSPIM_BitCounter__PERIOD_REG)\r
+#define SDCard_COUNTER_CONTROL_REG (* (reg8 *) SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)\r
+#define SDCard_COUNTER_CONTROL_PTR ( (reg8 *) SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG)\r
+\r
+#define SDCard_TX_STATUS_REG (* (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_REG)\r
+#define SDCard_TX_STATUS_PTR ( (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_REG)\r
+#define SDCard_RX_STATUS_REG (* (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_REG)\r
+#define SDCard_RX_STATUS_PTR ( (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_REG)\r
+\r
+#define SDCard_CONTROL_REG (* (reg8 *) \\r
+ SDCard_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)\r
+#define SDCard_CONTROL_PTR ( (reg8 *) \\r
+ SDCard_BSPIM_BidirMode_SyncCtl_CtrlReg__CONTROL_REG)\r
+\r
+#define SDCard_TX_STATUS_MASK_REG (* (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG)\r
+#define SDCard_TX_STATUS_MASK_PTR ( (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG)\r
+#define SDCard_RX_STATUS_MASK_REG (* (reg8 *) SDCard_BSPIM_RxStsReg__MASK_REG)\r
+#define SDCard_RX_STATUS_MASK_PTR ( (reg8 *) SDCard_BSPIM_RxStsReg__MASK_REG)\r
+\r
+#define SDCard_TX_STATUS_ACTL_REG (* (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)\r
+#define SDCard_TX_STATUS_ACTL_PTR ( (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG)\r
+#define SDCard_RX_STATUS_ACTL_REG (* (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)\r
+#define SDCard_RX_STATUS_ACTL_PTR ( (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG)\r
+\r
+#if(SDCard_USE_SECOND_DATAPATH)\r
+ #define SDCard_AUX_CONTROLDP1 (SDCard_AUX_CONTROL_DP1_REG)\r
+#endif /* (SDCard_USE_SECOND_DATAPATH) */\r
+\r
+\r
+/***************************************\r
+* Register Constants\r
+***************************************/\r
+\r
+/* Status Register Definitions */\r
+#define SDCard_STS_SPI_DONE_SHIFT (0x00u)\r
+#define SDCard_STS_TX_FIFO_EMPTY_SHIFT (0x01u)\r
+#define SDCard_STS_TX_FIFO_NOT_FULL_SHIFT (0x02u)\r
+#define SDCard_STS_BYTE_COMPLETE_SHIFT (0x03u)\r
+#define SDCard_STS_SPI_IDLE_SHIFT (0x04u)\r
+#define SDCard_STS_RX_FIFO_FULL_SHIFT (0x04u)\r
+#define SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT (0x05u)\r
+#define SDCard_STS_RX_FIFO_OVERRUN_SHIFT (0x06u)\r
+\r
+#define SDCard_STS_SPI_DONE ((uint8) (0x01u << SDCard_STS_SPI_DONE_SHIFT))\r
+#define SDCard_STS_TX_FIFO_EMPTY ((uint8) (0x01u << SDCard_STS_TX_FIFO_EMPTY_SHIFT))\r
+#define SDCard_STS_TX_FIFO_NOT_FULL ((uint8) (0x01u << SDCard_STS_TX_FIFO_NOT_FULL_SHIFT))\r
+#define SDCard_STS_BYTE_COMPLETE ((uint8) (0x01u << SDCard_STS_BYTE_COMPLETE_SHIFT))\r
+#define SDCard_STS_SPI_IDLE ((uint8) (0x01u << SDCard_STS_SPI_IDLE_SHIFT))\r
+#define SDCard_STS_RX_FIFO_FULL ((uint8) (0x01u << SDCard_STS_RX_FIFO_FULL_SHIFT))\r
+#define SDCard_STS_RX_FIFO_NOT_EMPTY ((uint8) (0x01u << SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT))\r
+#define SDCard_STS_RX_FIFO_OVERRUN ((uint8) (0x01u << SDCard_STS_RX_FIFO_OVERRUN_SHIFT))\r
+\r
+/* TX and RX masks for clear on read bits */\r
+#define SDCard_TX_STS_CLR_ON_RD_BYTES_MASK (0x09u)\r
+#define SDCard_RX_STS_CLR_ON_RD_BYTES_MASK (0x40u)\r
+\r
+/* StatusI Register Interrupt Enable Control Bits */\r
+/* As defined by the Register map for the AUX Control Register */\r
+#define SDCard_INT_ENABLE (0x10u) /* Enable interrupt from statusi */\r
+#define SDCard_TX_FIFO_CLR (0x01u) /* F0 - TX FIFO */\r
+#define SDCard_RX_FIFO_CLR (0x02u) /* F1 - RX FIFO */\r
+#define SDCard_FIFO_CLR (SDCard_TX_FIFO_CLR | SDCard_RX_FIFO_CLR)\r
+\r
+/* Bit Counter (7-bit) Control Register Bit Definitions */\r
+/* As defined by the Register map for the AUX Control Register */\r
+#define SDCard_CNTR_ENABLE (0x20u) /* Enable CNT7 */\r
+\r
+/* Bi-Directional mode control bit */\r
+#define SDCard_CTRL_TX_SIGNAL_EN (0x01u)\r
+\r
+/* Datapath Auxillary Control Register definitions */\r
+#define SDCard_AUX_CTRL_FIFO0_CLR (0x01u)\r
+#define SDCard_AUX_CTRL_FIFO1_CLR (0x02u)\r
+#define SDCard_AUX_CTRL_FIFO0_LVL (0x04u)\r
+#define SDCard_AUX_CTRL_FIFO1_LVL (0x08u)\r
+#define SDCard_STATUS_ACTL_INT_EN_MASK (0x10u)\r
+\r
+/* Component disabled */\r
+#define SDCard_DISABLED (0u)\r
+\r
+\r
+/***************************************\r
+* Macros\r
+***************************************/\r
+\r
+/* Returns true if componentn enabled */\r
+#define SDCard_IS_ENABLED (0u != (SDCard_TX_STATUS_ACTL_REG & SDCard_INT_ENABLE))\r
+\r
+/* Retuns TX status register */\r
+#define SDCard_GET_STATUS_TX(swTxSts) ( (uint8)(SDCard_TX_STATUS_REG | \\r
+ ((swTxSts) & SDCard_TX_STS_CLR_ON_RD_BYTES_MASK)) )\r
+/* Retuns RX status register */\r
+#define SDCard_GET_STATUS_RX(swRxSts) ( (uint8)(SDCard_RX_STATUS_REG | \\r
+ ((swRxSts) & SDCard_RX_STS_CLR_ON_RD_BYTES_MASK)) )\r
+\r
+\r
+/***************************************\r
+* Obsolete definitions\r
+***************************************/\r
+\r
+/* Following definitions are for version compatibility.\r
+* They are obsolete in SPIM v2_30.\r
+* Please do not use it in new projects\r
+*/\r
+\r
+#define SDCard_WriteByte SDCard_WriteTxData\r
+#define SDCard_ReadByte SDCard_ReadRxData\r
+void SDCard_SetInterruptMode(uint8 intSrc) ;\r
+uint8 SDCard_ReadStatus(void) ;\r
+void SDCard_EnableInt(void) ;\r
+void SDCard_DisableInt(void) ;\r
+\r
+/* Obsolete register names. Not to be used in new designs */\r
+#define SDCard_TXDATA (SDCard_TXDATA_REG)\r
+#define SDCard_RXDATA (SDCard_RXDATA_REG)\r
+#define SDCard_AUX_CONTROLDP0 (SDCard_AUX_CONTROL_DP0_REG)\r
+#define SDCard_TXBUFFERREAD (SDCard_txBufferRead)\r
+#define SDCard_TXBUFFERWRITE (SDCard_txBufferWrite)\r
+#define SDCard_RXBUFFERREAD (SDCard_rxBufferRead)\r
+#define SDCard_RXBUFFERWRITE (SDCard_rxBufferWrite)\r
+\r
+#define SDCard_COUNTER_PERIOD (SDCard_COUNTER_PERIOD_REG)\r
+#define SDCard_COUNTER_CONTROL (SDCard_COUNTER_CONTROL_REG)\r
+#define SDCard_STATUS (SDCard_TX_STATUS_REG)\r
+#define SDCard_CONTROL (SDCard_CONTROL_REG)\r
+#define SDCard_STATUS_MASK (SDCard_TX_STATUS_MASK_REG)\r
+#define SDCard_STATUS_ACTL (SDCard_TX_STATUS_ACTL_REG)\r
+\r
+#define SDCard_INIT_INTERRUPTS_MASK (SDCard_INT_ON_SPI_DONE | \\r
+ SDCard_INT_ON_TX_EMPTY | \\r
+ SDCard_INT_ON_TX_NOT_FULL_DEF | \\r
+ SDCard_INT_ON_RX_FULL | \\r
+ SDCard_INT_ON_RX_NOT_EMPTY | \\r
+ SDCard_INT_ON_RX_OVER | \\r
+ SDCard_INT_ON_BYTE_COMP)\r
+ \r
+/* Following definitions are for version Compatibility.\r
+* They are obsolete in SPIM v2_40.\r
+* Please do not use it in new projects\r
+*/\r
+\r
+#define SDCard_DataWidth (SDCard_DATA_WIDTH)\r
+#define SDCard_InternalClockUsed (SDCard_INTERNAL_CLOCK)\r
+#define SDCard_InternalTxInterruptEnabled (SDCard_INTERNAL_TX_INT_ENABLED)\r
+#define SDCard_InternalRxInterruptEnabled (SDCard_INTERNAL_RX_INT_ENABLED)\r
+#define SDCard_ModeUseZero (SDCard_MODE_USE_ZERO)\r
+#define SDCard_BidirectionalMode (SDCard_BIDIRECTIONAL_MODE)\r
+#define SDCard_Mode (SDCard_MODE)\r
+#define SDCard_DATAWIDHT (SDCard_DATA_WIDTH)\r
+#define SDCard_InternalInterruptEnabled (0u)\r
+\r
+#define SDCard_TXBUFFERSIZE (SDCard_TX_BUFFER_SIZE)\r
+#define SDCard_RXBUFFERSIZE (SDCard_RX_BUFFER_SIZE)\r
+\r
+#define SDCard_TXBUFFER SDCard_txBuffer\r
+#define SDCard_RXBUFFER SDCard_rxBuffer\r
+\r
+#endif /* (CY_SPIM_SDCard_H) */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SDCard_INT.c\r
+* Version 2.40\r
+*\r
+* Description:\r
+* This file provides all Interrupt Service Routine (ISR) for the SPI Master\r
+* component.\r
+*\r
+* Note:\r
+* None.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "SDCard_PVT.h"\r
+\r
+/* User code required at start of ISR */\r
+/* `#START SDCard_ISR_START_DEF` */\r
+\r
+/* `#END` */\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_TX_ISR\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Interrupt Service Routine for TX portion of the SPI Master.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global variables:\r
+* SDCard_txBufferWrite - used for the account of the bytes which\r
+* have been written down in the TX software buffer.\r
+* SDCard_txBufferRead - used for the account of the bytes which\r
+* have been read from the TX software buffer, modified when exist data to\r
+* sending and FIFO Not Full.\r
+* SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] - used to store\r
+* data to sending.\r
+* All described above Global variables are used when Software Buffer is used.\r
+*\r
+*******************************************************************************/\r
+CY_ISR(SDCard_TX_ISR)\r
+{\r
+ #if(SDCard_TX_SOFTWARE_BUF_ENABLED)\r
+ uint8 tmpStatus;\r
+ #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ /* User code required at start of ISR */\r
+ /* `#START SDCard_TX_ISR_START` */\r
+\r
+ /* `#END` */\r
+\r
+ #if(SDCard_TX_SOFTWARE_BUF_ENABLED)\r
+ /* Check if TX data buffer is not empty and there is space in TX FIFO */\r
+ while(SDCard_txBufferRead != SDCard_txBufferWrite)\r
+ {\r
+ tmpStatus = SDCard_GET_STATUS_TX(SDCard_swStatusTx);\r
+ SDCard_swStatusTx = tmpStatus;\r
+\r
+ if(0u != (SDCard_swStatusTx & SDCard_STS_TX_FIFO_NOT_FULL))\r
+ {\r
+ if(0u == SDCard_txBufferFull)\r
+ {\r
+ SDCard_txBufferRead++;\r
+\r
+ if(SDCard_txBufferRead >= SDCard_TX_BUFFER_SIZE)\r
+ {\r
+ SDCard_txBufferRead = 0u;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ SDCard_txBufferFull = 0u;\r
+ }\r
+\r
+ /* Move data from the Buffer to the FIFO */\r
+ CY_SET_REG8(SDCard_TXDATA_PTR,\r
+ SDCard_txBuffer[SDCard_txBufferRead]);\r
+ }\r
+ else\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ if(SDCard_txBufferRead == SDCard_txBufferWrite)\r
+ {\r
+ /* TX Buffer is EMPTY: disable interrupt on TX NOT FULL */\r
+ SDCard_TX_STATUS_MASK_REG &= ((uint8) ~SDCard_STS_TX_FIFO_NOT_FULL);\r
+ }\r
+\r
+ #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ /* User code required at end of ISR (Optional) */\r
+ /* `#START SDCard_TX_ISR_END` */\r
+\r
+ /* `#END` */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_RX_ISR\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Interrupt Service Routine for RX portion of the SPI Master.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global variables:\r
+* SDCard_rxBufferWrite - used for the account of the bytes which\r
+* have been written down in the RX software buffer modified when FIFO contains\r
+* new data.\r
+* SDCard_rxBufferRead - used for the account of the bytes which\r
+* have been read from the RX software buffer, modified when overflow occurred.\r
+* SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] - used to store\r
+* received data, modified when FIFO contains new data.\r
+* All described above Global variables are used when Software Buffer is used.\r
+*\r
+*******************************************************************************/\r
+CY_ISR(SDCard_RX_ISR)\r
+{\r
+ #if(SDCard_RX_SOFTWARE_BUF_ENABLED)\r
+ uint8 tmpStatus;\r
+ uint8 rxData;\r
+ #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ /* User code required at start of ISR */\r
+ /* `#START SDCard_RX_ISR_START` */\r
+\r
+ /* `#END` */\r
+\r
+ #if(SDCard_RX_SOFTWARE_BUF_ENABLED)\r
+\r
+ tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx);\r
+ SDCard_swStatusRx = tmpStatus;\r
+\r
+ /* Check if RX data FIFO has some data to be moved into the RX Buffer */\r
+ while(0u != (SDCard_swStatusRx & SDCard_STS_RX_FIFO_NOT_EMPTY))\r
+ {\r
+ rxData = CY_GET_REG8(SDCard_RXDATA_PTR);\r
+\r
+ /* Set next pointer. */\r
+ SDCard_rxBufferWrite++;\r
+ if(SDCard_rxBufferWrite >= SDCard_RX_BUFFER_SIZE)\r
+ {\r
+ SDCard_rxBufferWrite = 0u;\r
+ }\r
+\r
+ if(SDCard_rxBufferWrite == SDCard_rxBufferRead)\r
+ {\r
+ SDCard_rxBufferRead++;\r
+ if(SDCard_rxBufferRead >= SDCard_RX_BUFFER_SIZE)\r
+ {\r
+ SDCard_rxBufferRead = 0u;\r
+ }\r
+\r
+ SDCard_rxBufferFull = 1u;\r
+ }\r
+\r
+ /* Move data from the FIFO to the Buffer */\r
+ SDCard_rxBuffer[SDCard_rxBufferWrite] = rxData;\r
+\r
+ tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx);\r
+ SDCard_swStatusRx = tmpStatus;\r
+ }\r
+\r
+ #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ /* User code required at end of ISR (Optional) */\r
+ /* `#START SDCard_RX_ISR_END` */\r
+\r
+ /* `#END` */\r
+}\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SDCard_PM.c\r
+* Version 2.40\r
+*\r
+* Description:\r
+* This file contains the setup, control and status commands to support\r
+* component operations in low power mode.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "SDCard_PVT.h"\r
+\r
+static SDCard_BACKUP_STRUCT SDCard_backup =\r
+{\r
+ SDCard_DISABLED,\r
+ SDCard_BITCTR_INIT,\r
+ #if(CY_UDB_V0)\r
+ SDCard_TX_INIT_INTERRUPTS_MASK,\r
+ SDCard_RX_INIT_INTERRUPTS_MASK\r
+ #endif /* CY_UDB_V0 */\r
+};\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_SaveConfig\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Saves SPIM configuration.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global Variables:\r
+* SDCard_backup - modified when non-retention registers are saved.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void SDCard_SaveConfig(void) \r
+{\r
+ /* Store Status Mask registers */\r
+ #if(CY_UDB_V0)\r
+ SDCard_backup.cntrPeriod = SDCard_COUNTER_PERIOD_REG;\r
+ SDCard_backup.saveSrTxIntMask = SDCard_TX_STATUS_MASK_REG;\r
+ SDCard_backup.saveSrRxIntMask = SDCard_RX_STATUS_MASK_REG;\r
+ #endif /* (CY_UDB_V0) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_RestoreConfig\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Restores SPIM configuration.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global Variables:\r
+* SDCard_backup - used when non-retention registers are restored.\r
+*\r
+* Side Effects:\r
+* If this API is called without first calling SaveConfig then in the following\r
+* registers will be default values from Customizer:\r
+* SDCard_STATUS_MASK_REG and SDCard_COUNTER_PERIOD_REG.\r
+*\r
+*******************************************************************************/\r
+void SDCard_RestoreConfig(void) \r
+{\r
+ /* Restore the data, saved by SaveConfig() function */\r
+ #if(CY_UDB_V0)\r
+ SDCard_COUNTER_PERIOD_REG = SDCard_backup.cntrPeriod;\r
+ SDCard_TX_STATUS_MASK_REG = ((uint8) SDCard_backup.saveSrTxIntMask);\r
+ SDCard_RX_STATUS_MASK_REG = ((uint8) SDCard_backup.saveSrRxIntMask);\r
+ #endif /* (CY_UDB_V0) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_Sleep\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Prepare SPIM Component goes to sleep.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global Variables:\r
+* SDCard_backup - modified when non-retention registers are saved.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void SDCard_Sleep(void) \r
+{\r
+ /* Save components enable state */\r
+ SDCard_backup.enableState = ((uint8) SDCard_IS_ENABLED);\r
+\r
+ SDCard_Stop();\r
+ SDCard_SaveConfig();\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SDCard_Wakeup\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Prepare SPIM Component to wake up.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global Variables:\r
+* SDCard_backup - used when non-retention registers are restored.\r
+* SDCard_txBufferWrite - modified every function call - resets to\r
+* zero.\r
+* SDCard_txBufferRead - modified every function call - resets to\r
+* zero.\r
+* SDCard_rxBufferWrite - modified every function call - resets to\r
+* zero.\r
+* SDCard_rxBufferRead - modified every function call - resets to\r
+* zero.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void SDCard_Wakeup(void) \r
+{\r
+ SDCard_RestoreConfig();\r
+\r
+ #if(SDCard_RX_SOFTWARE_BUF_ENABLED)\r
+ SDCard_rxBufferFull = 0u;\r
+ SDCard_rxBufferRead = 0u;\r
+ SDCard_rxBufferWrite = 0u;\r
+ #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ #if(SDCard_TX_SOFTWARE_BUF_ENABLED)\r
+ SDCard_txBufferFull = 0u;\r
+ SDCard_txBufferRead = 0u;\r
+ SDCard_txBufferWrite = 0u;\r
+ #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ /* Clear any data from the RX and TX FIFO */\r
+ SDCard_ClearFIFO();\r
+\r
+ /* Restore components block enable state */\r
+ if(0u != SDCard_backup.enableState)\r
+ {\r
+ SDCard_Enable();\r
+ }\r
+}\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: .h\r
+* Version 2.40\r
+*\r
+* Description:\r
+* This private header file contains internal definitions for the SPIM\r
+* component. Do not use these definitions directly in your application.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_SPIM_PVT_SDCard_H)\r
+#define CY_SPIM_PVT_SDCard_H\r
+\r
+#include "SDCard.h"\r
+\r
+\r
+/**********************************\r
+* Functions with external linkage\r
+**********************************/\r
+\r
+\r
+/**********************************\r
+* Variables with external linkage\r
+**********************************/\r
+\r
+extern volatile uint8 SDCard_swStatusTx;\r
+extern volatile uint8 SDCard_swStatusRx;\r
+\r
+#if(SDCard_TX_SOFTWARE_BUF_ENABLED)\r
+ extern volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE];\r
+ extern volatile uint8 SDCard_txBufferRead;\r
+ extern volatile uint8 SDCard_txBufferWrite;\r
+ extern volatile uint8 SDCard_txBufferFull;\r
+#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */\r
+\r
+#if(SDCard_RX_SOFTWARE_BUF_ENABLED)\r
+ extern volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE];\r
+ extern volatile uint8 SDCard_rxBufferRead;\r
+ extern volatile uint8 SDCard_rxBufferWrite;\r
+ extern volatile uint8 SDCard_rxBufferFull;\r
+#endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */\r
+\r
+#endif /* CY_SPIM_PVT_SDCard_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_CD.c \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file contains API to enable firmware control of a Pins component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "cytypes.h"\r
+#include "SD_CD.h"\r
+\r
+/* APIs are not generated for P15[7:6] on PSoC 5 */\r
+#if !(CY_PSOC5A &&\\r
+ SD_CD__PORT == 15 && ((SD_CD__MASK & 0xC0) != 0))\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_CD_Write\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Assign a new value to the digital port's data output register. \r
+*\r
+* Parameters: \r
+* prtValue: The value to be assigned to the Digital Port. \r
+*\r
+* Return: \r
+* None\r
+* \r
+*******************************************************************************/\r
+void SD_CD_Write(uint8 value) \r
+{\r
+ uint8 staticBits = (SD_CD_DR & (uint8)(~SD_CD_MASK));\r
+ SD_CD_DR = staticBits | ((uint8)(value << SD_CD_SHIFT) & SD_CD_MASK);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_CD_SetDriveMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Change the drive mode on the pins of the port.\r
+* \r
+* Parameters: \r
+* mode: Change the pins to this drive mode.\r
+*\r
+* Return: \r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_CD_SetDriveMode(uint8 mode) \r
+{\r
+ CyPins_SetPinDriveMode(SD_CD_0, mode);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_CD_Read\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value on the pins of the Digital Port in right justified \r
+* form.\r
+*\r
+* Parameters: \r
+* None\r
+*\r
+* Return: \r
+* Returns the current value of the Digital Port as a right justified number\r
+* \r
+* Note:\r
+* Macro SD_CD_ReadPS calls this function. \r
+* \r
+*******************************************************************************/\r
+uint8 SD_CD_Read(void) \r
+{\r
+ return (SD_CD_PS & SD_CD_MASK) >> SD_CD_SHIFT;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_CD_ReadDataReg\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value assigned to a Digital Port's data output register\r
+*\r
+* Parameters: \r
+* None \r
+*\r
+* Return: \r
+* Returns the current value assigned to the Digital Port's data output register\r
+* \r
+*******************************************************************************/\r
+uint8 SD_CD_ReadDataReg(void) \r
+{\r
+ return (SD_CD_DR & SD_CD_MASK) >> SD_CD_SHIFT;\r
+}\r
+\r
+\r
+/* If Interrupts Are Enabled for this Pins component */ \r
+#if defined(SD_CD_INTSTAT) \r
+\r
+ /*******************************************************************************\r
+ * Function Name: SD_CD_ClearInterrupt\r
+ ********************************************************************************\r
+ * Summary:\r
+ * Clears any active interrupts attached to port and returns the value of the \r
+ * interrupt status register.\r
+ *\r
+ * Parameters: \r
+ * None \r
+ *\r
+ * Return: \r
+ * Returns the value of the interrupt status register\r
+ * \r
+ *******************************************************************************/\r
+ uint8 SD_CD_ClearInterrupt(void) \r
+ {\r
+ return (SD_CD_INTSTAT & SD_CD_MASK) >> SD_CD_SHIFT;\r
+ }\r
+\r
+#endif /* If Interrupts Are Enabled for this Pins component */ \r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+ \r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_CD.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SD_CD_H) /* Pins SD_CD_H */\r
+#define CY_PINS_SD_CD_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+#include "cypins.h"\r
+#include "SD_CD_aliases.h"\r
+\r
+/* Check to see if required defines such as CY_PSOC5A are available */\r
+/* They are defined starting with cy_boot v3.0 */\r
+#if !defined (CY_PSOC5A)\r
+ #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5A) */\r
+\r
+/* APIs are not generated for P15[7:6] */\r
+#if !(CY_PSOC5A &&\\r
+ SD_CD__PORT == 15 && ((SD_CD__MASK & 0xC0) != 0))\r
+\r
+\r
+/***************************************\r
+* Function Prototypes \r
+***************************************/ \r
+\r
+void SD_CD_Write(uint8 value) ;\r
+void SD_CD_SetDriveMode(uint8 mode) ;\r
+uint8 SD_CD_ReadDataReg(void) ;\r
+uint8 SD_CD_Read(void) ;\r
+uint8 SD_CD_ClearInterrupt(void) ;\r
+\r
+\r
+/***************************************\r
+* API Constants \r
+***************************************/\r
+\r
+/* Drive Modes */\r
+#define SD_CD_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+#define SD_CD_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+#define SD_CD_DM_RES_UP PIN_DM_RES_UP\r
+#define SD_CD_DM_RES_DWN PIN_DM_RES_DWN\r
+#define SD_CD_DM_OD_LO PIN_DM_OD_LO\r
+#define SD_CD_DM_OD_HI PIN_DM_OD_HI\r
+#define SD_CD_DM_STRONG PIN_DM_STRONG\r
+#define SD_CD_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+\r
+/* Digital Port Constants */\r
+#define SD_CD_MASK SD_CD__MASK\r
+#define SD_CD_SHIFT SD_CD__SHIFT\r
+#define SD_CD_WIDTH 1u\r
+\r
+\r
+/***************************************\r
+* Registers \r
+***************************************/\r
+\r
+/* Main Port Registers */\r
+/* Pin State */\r
+#define SD_CD_PS (* (reg8 *) SD_CD__PS)\r
+/* Data Register */\r
+#define SD_CD_DR (* (reg8 *) SD_CD__DR)\r
+/* Port Number */\r
+#define SD_CD_PRT_NUM (* (reg8 *) SD_CD__PRT) \r
+/* Connect to Analog Globals */ \r
+#define SD_CD_AG (* (reg8 *) SD_CD__AG) \r
+/* Analog MUX bux enable */\r
+#define SD_CD_AMUX (* (reg8 *) SD_CD__AMUX) \r
+/* Bidirectional Enable */ \r
+#define SD_CD_BIE (* (reg8 *) SD_CD__BIE)\r
+/* Bit-mask for Aliased Register Access */\r
+#define SD_CD_BIT_MASK (* (reg8 *) SD_CD__BIT_MASK)\r
+/* Bypass Enable */\r
+#define SD_CD_BYP (* (reg8 *) SD_CD__BYP)\r
+/* Port wide control signals */ \r
+#define SD_CD_CTL (* (reg8 *) SD_CD__CTL)\r
+/* Drive Modes */\r
+#define SD_CD_DM0 (* (reg8 *) SD_CD__DM0) \r
+#define SD_CD_DM1 (* (reg8 *) SD_CD__DM1)\r
+#define SD_CD_DM2 (* (reg8 *) SD_CD__DM2) \r
+/* Input Buffer Disable Override */\r
+#define SD_CD_INP_DIS (* (reg8 *) SD_CD__INP_DIS)\r
+/* LCD Common or Segment Drive */\r
+#define SD_CD_LCD_COM_SEG (* (reg8 *) SD_CD__LCD_COM_SEG)\r
+/* Enable Segment LCD */\r
+#define SD_CD_LCD_EN (* (reg8 *) SD_CD__LCD_EN)\r
+/* Slew Rate Control */\r
+#define SD_CD_SLW (* (reg8 *) SD_CD__SLW)\r
+\r
+/* DSI Port Registers */\r
+/* Global DSI Select Register */\r
+#define SD_CD_PRTDSI__CAPS_SEL (* (reg8 *) SD_CD__PRTDSI__CAPS_SEL) \r
+/* Double Sync Enable */\r
+#define SD_CD_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_CD__PRTDSI__DBL_SYNC_IN) \r
+/* Output Enable Select Drive Strength */\r
+#define SD_CD_PRTDSI__OE_SEL0 (* (reg8 *) SD_CD__PRTDSI__OE_SEL0) \r
+#define SD_CD_PRTDSI__OE_SEL1 (* (reg8 *) SD_CD__PRTDSI__OE_SEL1) \r
+/* Port Pin Output Select Registers */\r
+#define SD_CD_PRTDSI__OUT_SEL0 (* (reg8 *) SD_CD__PRTDSI__OUT_SEL0) \r
+#define SD_CD_PRTDSI__OUT_SEL1 (* (reg8 *) SD_CD__PRTDSI__OUT_SEL1) \r
+/* Sync Output Enable Registers */\r
+#define SD_CD_PRTDSI__SYNC_OUT (* (reg8 *) SD_CD__PRTDSI__SYNC_OUT) \r
+\r
+\r
+#if defined(SD_CD__INTSTAT) /* Interrupt Registers */\r
+\r
+ #define SD_CD_INTSTAT (* (reg8 *) SD_CD__INTSTAT)\r
+ #define SD_CD_SNAP (* (reg8 *) SD_CD__SNAP)\r
+\r
+#endif /* Interrupt Registers */\r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+#endif /* CY_PINS_SD_CD_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_CD.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SD_CD_ALIASES_H) /* Pins SD_CD_ALIASES_H */\r
+#define CY_PINS_SD_CD_ALIASES_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+\r
+\r
+/***************************************\r
+* Constants \r
+***************************************/\r
+#define SD_CD_0 SD_CD__0__PC\r
+\r
+#endif /* End Pins SD_CD_ALIASES_H */\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_CS.c \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file contains API to enable firmware control of a Pins component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "cytypes.h"\r
+#include "SD_CS.h"\r
+\r
+/* APIs are not generated for P15[7:6] on PSoC 5 */\r
+#if !(CY_PSOC5A &&\\r
+ SD_CS__PORT == 15 && ((SD_CS__MASK & 0xC0) != 0))\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_CS_Write\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Assign a new value to the digital port's data output register. \r
+*\r
+* Parameters: \r
+* prtValue: The value to be assigned to the Digital Port. \r
+*\r
+* Return: \r
+* None\r
+* \r
+*******************************************************************************/\r
+void SD_CS_Write(uint8 value) \r
+{\r
+ uint8 staticBits = (SD_CS_DR & (uint8)(~SD_CS_MASK));\r
+ SD_CS_DR = staticBits | ((uint8)(value << SD_CS_SHIFT) & SD_CS_MASK);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_CS_SetDriveMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Change the drive mode on the pins of the port.\r
+* \r
+* Parameters: \r
+* mode: Change the pins to this drive mode.\r
+*\r
+* Return: \r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_CS_SetDriveMode(uint8 mode) \r
+{\r
+ CyPins_SetPinDriveMode(SD_CS_0, mode);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_CS_Read\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value on the pins of the Digital Port in right justified \r
+* form.\r
+*\r
+* Parameters: \r
+* None\r
+*\r
+* Return: \r
+* Returns the current value of the Digital Port as a right justified number\r
+* \r
+* Note:\r
+* Macro SD_CS_ReadPS calls this function. \r
+* \r
+*******************************************************************************/\r
+uint8 SD_CS_Read(void) \r
+{\r
+ return (SD_CS_PS & SD_CS_MASK) >> SD_CS_SHIFT;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_CS_ReadDataReg\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value assigned to a Digital Port's data output register\r
+*\r
+* Parameters: \r
+* None \r
+*\r
+* Return: \r
+* Returns the current value assigned to the Digital Port's data output register\r
+* \r
+*******************************************************************************/\r
+uint8 SD_CS_ReadDataReg(void) \r
+{\r
+ return (SD_CS_DR & SD_CS_MASK) >> SD_CS_SHIFT;\r
+}\r
+\r
+\r
+/* If Interrupts Are Enabled for this Pins component */ \r
+#if defined(SD_CS_INTSTAT) \r
+\r
+ /*******************************************************************************\r
+ * Function Name: SD_CS_ClearInterrupt\r
+ ********************************************************************************\r
+ * Summary:\r
+ * Clears any active interrupts attached to port and returns the value of the \r
+ * interrupt status register.\r
+ *\r
+ * Parameters: \r
+ * None \r
+ *\r
+ * Return: \r
+ * Returns the value of the interrupt status register\r
+ * \r
+ *******************************************************************************/\r
+ uint8 SD_CS_ClearInterrupt(void) \r
+ {\r
+ return (SD_CS_INTSTAT & SD_CS_MASK) >> SD_CS_SHIFT;\r
+ }\r
+\r
+#endif /* If Interrupts Are Enabled for this Pins component */ \r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+ \r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_CS.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SD_CS_H) /* Pins SD_CS_H */\r
+#define CY_PINS_SD_CS_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+#include "cypins.h"\r
+#include "SD_CS_aliases.h"\r
+\r
+/* Check to see if required defines such as CY_PSOC5A are available */\r
+/* They are defined starting with cy_boot v3.0 */\r
+#if !defined (CY_PSOC5A)\r
+ #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5A) */\r
+\r
+/* APIs are not generated for P15[7:6] */\r
+#if !(CY_PSOC5A &&\\r
+ SD_CS__PORT == 15 && ((SD_CS__MASK & 0xC0) != 0))\r
+\r
+\r
+/***************************************\r
+* Function Prototypes \r
+***************************************/ \r
+\r
+void SD_CS_Write(uint8 value) ;\r
+void SD_CS_SetDriveMode(uint8 mode) ;\r
+uint8 SD_CS_ReadDataReg(void) ;\r
+uint8 SD_CS_Read(void) ;\r
+uint8 SD_CS_ClearInterrupt(void) ;\r
+\r
+\r
+/***************************************\r
+* API Constants \r
+***************************************/\r
+\r
+/* Drive Modes */\r
+#define SD_CS_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+#define SD_CS_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+#define SD_CS_DM_RES_UP PIN_DM_RES_UP\r
+#define SD_CS_DM_RES_DWN PIN_DM_RES_DWN\r
+#define SD_CS_DM_OD_LO PIN_DM_OD_LO\r
+#define SD_CS_DM_OD_HI PIN_DM_OD_HI\r
+#define SD_CS_DM_STRONG PIN_DM_STRONG\r
+#define SD_CS_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+\r
+/* Digital Port Constants */\r
+#define SD_CS_MASK SD_CS__MASK\r
+#define SD_CS_SHIFT SD_CS__SHIFT\r
+#define SD_CS_WIDTH 1u\r
+\r
+\r
+/***************************************\r
+* Registers \r
+***************************************/\r
+\r
+/* Main Port Registers */\r
+/* Pin State */\r
+#define SD_CS_PS (* (reg8 *) SD_CS__PS)\r
+/* Data Register */\r
+#define SD_CS_DR (* (reg8 *) SD_CS__DR)\r
+/* Port Number */\r
+#define SD_CS_PRT_NUM (* (reg8 *) SD_CS__PRT) \r
+/* Connect to Analog Globals */ \r
+#define SD_CS_AG (* (reg8 *) SD_CS__AG) \r
+/* Analog MUX bux enable */\r
+#define SD_CS_AMUX (* (reg8 *) SD_CS__AMUX) \r
+/* Bidirectional Enable */ \r
+#define SD_CS_BIE (* (reg8 *) SD_CS__BIE)\r
+/* Bit-mask for Aliased Register Access */\r
+#define SD_CS_BIT_MASK (* (reg8 *) SD_CS__BIT_MASK)\r
+/* Bypass Enable */\r
+#define SD_CS_BYP (* (reg8 *) SD_CS__BYP)\r
+/* Port wide control signals */ \r
+#define SD_CS_CTL (* (reg8 *) SD_CS__CTL)\r
+/* Drive Modes */\r
+#define SD_CS_DM0 (* (reg8 *) SD_CS__DM0) \r
+#define SD_CS_DM1 (* (reg8 *) SD_CS__DM1)\r
+#define SD_CS_DM2 (* (reg8 *) SD_CS__DM2) \r
+/* Input Buffer Disable Override */\r
+#define SD_CS_INP_DIS (* (reg8 *) SD_CS__INP_DIS)\r
+/* LCD Common or Segment Drive */\r
+#define SD_CS_LCD_COM_SEG (* (reg8 *) SD_CS__LCD_COM_SEG)\r
+/* Enable Segment LCD */\r
+#define SD_CS_LCD_EN (* (reg8 *) SD_CS__LCD_EN)\r
+/* Slew Rate Control */\r
+#define SD_CS_SLW (* (reg8 *) SD_CS__SLW)\r
+\r
+/* DSI Port Registers */\r
+/* Global DSI Select Register */\r
+#define SD_CS_PRTDSI__CAPS_SEL (* (reg8 *) SD_CS__PRTDSI__CAPS_SEL) \r
+/* Double Sync Enable */\r
+#define SD_CS_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_CS__PRTDSI__DBL_SYNC_IN) \r
+/* Output Enable Select Drive Strength */\r
+#define SD_CS_PRTDSI__OE_SEL0 (* (reg8 *) SD_CS__PRTDSI__OE_SEL0) \r
+#define SD_CS_PRTDSI__OE_SEL1 (* (reg8 *) SD_CS__PRTDSI__OE_SEL1) \r
+/* Port Pin Output Select Registers */\r
+#define SD_CS_PRTDSI__OUT_SEL0 (* (reg8 *) SD_CS__PRTDSI__OUT_SEL0) \r
+#define SD_CS_PRTDSI__OUT_SEL1 (* (reg8 *) SD_CS__PRTDSI__OUT_SEL1) \r
+/* Sync Output Enable Registers */\r
+#define SD_CS_PRTDSI__SYNC_OUT (* (reg8 *) SD_CS__PRTDSI__SYNC_OUT) \r
+\r
+\r
+#if defined(SD_CS__INTSTAT) /* Interrupt Registers */\r
+\r
+ #define SD_CS_INTSTAT (* (reg8 *) SD_CS__INTSTAT)\r
+ #define SD_CS_SNAP (* (reg8 *) SD_CS__SNAP)\r
+\r
+#endif /* Interrupt Registers */\r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+#endif /* CY_PINS_SD_CS_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_CS.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SD_CS_ALIASES_H) /* Pins SD_CS_ALIASES_H */\r
+#define CY_PINS_SD_CS_ALIASES_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+\r
+\r
+/***************************************\r
+* Constants \r
+***************************************/\r
+#define SD_CS_0 SD_CS__0__PC\r
+\r
+#endif /* End Pins SD_CS_ALIASES_H */\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_Clk_Ctl.c \r
+* Version 1.70\r
+*\r
+* Description:\r
+* This file contains API to enable firmware control of a Control Register.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "SD_Clk_Ctl.h"\r
+\r
+#if !defined(SD_Clk_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Clk_Ctl_Write\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Write a byte to the Control Register.\r
+*\r
+* Parameters:\r
+* control: The value to be assigned to the Control Register.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+*******************************************************************************/\r
+void SD_Clk_Ctl_Write(uint8 control) \r
+{\r
+ SD_Clk_Ctl_Control = control;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Clk_Ctl_Read\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Reads the current value assigned to the Control Register.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* Returns the current value in the Control Register.\r
+*\r
+*******************************************************************************/\r
+uint8 SD_Clk_Ctl_Read(void) \r
+{\r
+ return SD_Clk_Ctl_Control;\r
+}\r
+\r
+#endif /* End check for removal by optimization */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_Clk_Ctl.h \r
+* Version 1.70\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_CONTROL_REG_SD_Clk_Ctl_H) /* CY_CONTROL_REG_SD_Clk_Ctl_H */\r
+#define CY_CONTROL_REG_SD_Clk_Ctl_H\r
+\r
+#include "cytypes.h"\r
+\r
+\r
+/***************************************\r
+* Function Prototypes \r
+***************************************/\r
+\r
+void SD_Clk_Ctl_Write(uint8 control) ;\r
+uint8 SD_Clk_Ctl_Read(void) ;\r
+\r
+\r
+/***************************************\r
+* Registers \r
+***************************************/\r
+\r
+/* Control Register */\r
+#define SD_Clk_Ctl_Control (* (reg8 *) SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG )\r
+#define SD_Clk_Ctl_Control_PTR ( (reg8 *) SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG )\r
+\r
+#endif /* End CY_CONTROL_REG_SD_Clk_Ctl_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_DAT1.c \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file contains API to enable firmware control of a Pins component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "cytypes.h"\r
+#include "SD_DAT1.h"\r
+\r
+/* APIs are not generated for P15[7:6] on PSoC 5 */\r
+#if !(CY_PSOC5A &&\\r
+ SD_DAT1__PORT == 15 && ((SD_DAT1__MASK & 0xC0) != 0))\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_DAT1_Write\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Assign a new value to the digital port's data output register. \r
+*\r
+* Parameters: \r
+* prtValue: The value to be assigned to the Digital Port. \r
+*\r
+* Return: \r
+* None\r
+* \r
+*******************************************************************************/\r
+void SD_DAT1_Write(uint8 value) \r
+{\r
+ uint8 staticBits = (SD_DAT1_DR & (uint8)(~SD_DAT1_MASK));\r
+ SD_DAT1_DR = staticBits | ((uint8)(value << SD_DAT1_SHIFT) & SD_DAT1_MASK);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_DAT1_SetDriveMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Change the drive mode on the pins of the port.\r
+* \r
+* Parameters: \r
+* mode: Change the pins to this drive mode.\r
+*\r
+* Return: \r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_DAT1_SetDriveMode(uint8 mode) \r
+{\r
+ CyPins_SetPinDriveMode(SD_DAT1_0, mode);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_DAT1_Read\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value on the pins of the Digital Port in right justified \r
+* form.\r
+*\r
+* Parameters: \r
+* None\r
+*\r
+* Return: \r
+* Returns the current value of the Digital Port as a right justified number\r
+* \r
+* Note:\r
+* Macro SD_DAT1_ReadPS calls this function. \r
+* \r
+*******************************************************************************/\r
+uint8 SD_DAT1_Read(void) \r
+{\r
+ return (SD_DAT1_PS & SD_DAT1_MASK) >> SD_DAT1_SHIFT;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_DAT1_ReadDataReg\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value assigned to a Digital Port's data output register\r
+*\r
+* Parameters: \r
+* None \r
+*\r
+* Return: \r
+* Returns the current value assigned to the Digital Port's data output register\r
+* \r
+*******************************************************************************/\r
+uint8 SD_DAT1_ReadDataReg(void) \r
+{\r
+ return (SD_DAT1_DR & SD_DAT1_MASK) >> SD_DAT1_SHIFT;\r
+}\r
+\r
+\r
+/* If Interrupts Are Enabled for this Pins component */ \r
+#if defined(SD_DAT1_INTSTAT) \r
+\r
+ /*******************************************************************************\r
+ * Function Name: SD_DAT1_ClearInterrupt\r
+ ********************************************************************************\r
+ * Summary:\r
+ * Clears any active interrupts attached to port and returns the value of the \r
+ * interrupt status register.\r
+ *\r
+ * Parameters: \r
+ * None \r
+ *\r
+ * Return: \r
+ * Returns the value of the interrupt status register\r
+ * \r
+ *******************************************************************************/\r
+ uint8 SD_DAT1_ClearInterrupt(void) \r
+ {\r
+ return (SD_DAT1_INTSTAT & SD_DAT1_MASK) >> SD_DAT1_SHIFT;\r
+ }\r
+\r
+#endif /* If Interrupts Are Enabled for this Pins component */ \r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+ \r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_DAT1.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SD_DAT1_H) /* Pins SD_DAT1_H */\r
+#define CY_PINS_SD_DAT1_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+#include "cypins.h"\r
+#include "SD_DAT1_aliases.h"\r
+\r
+/* Check to see if required defines such as CY_PSOC5A are available */\r
+/* They are defined starting with cy_boot v3.0 */\r
+#if !defined (CY_PSOC5A)\r
+ #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5A) */\r
+\r
+/* APIs are not generated for P15[7:6] */\r
+#if !(CY_PSOC5A &&\\r
+ SD_DAT1__PORT == 15 && ((SD_DAT1__MASK & 0xC0) != 0))\r
+\r
+\r
+/***************************************\r
+* Function Prototypes \r
+***************************************/ \r
+\r
+void SD_DAT1_Write(uint8 value) ;\r
+void SD_DAT1_SetDriveMode(uint8 mode) ;\r
+uint8 SD_DAT1_ReadDataReg(void) ;\r
+uint8 SD_DAT1_Read(void) ;\r
+uint8 SD_DAT1_ClearInterrupt(void) ;\r
+\r
+\r
+/***************************************\r
+* API Constants \r
+***************************************/\r
+\r
+/* Drive Modes */\r
+#define SD_DAT1_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+#define SD_DAT1_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+#define SD_DAT1_DM_RES_UP PIN_DM_RES_UP\r
+#define SD_DAT1_DM_RES_DWN PIN_DM_RES_DWN\r
+#define SD_DAT1_DM_OD_LO PIN_DM_OD_LO\r
+#define SD_DAT1_DM_OD_HI PIN_DM_OD_HI\r
+#define SD_DAT1_DM_STRONG PIN_DM_STRONG\r
+#define SD_DAT1_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+\r
+/* Digital Port Constants */\r
+#define SD_DAT1_MASK SD_DAT1__MASK\r
+#define SD_DAT1_SHIFT SD_DAT1__SHIFT\r
+#define SD_DAT1_WIDTH 1u\r
+\r
+\r
+/***************************************\r
+* Registers \r
+***************************************/\r
+\r
+/* Main Port Registers */\r
+/* Pin State */\r
+#define SD_DAT1_PS (* (reg8 *) SD_DAT1__PS)\r
+/* Data Register */\r
+#define SD_DAT1_DR (* (reg8 *) SD_DAT1__DR)\r
+/* Port Number */\r
+#define SD_DAT1_PRT_NUM (* (reg8 *) SD_DAT1__PRT) \r
+/* Connect to Analog Globals */ \r
+#define SD_DAT1_AG (* (reg8 *) SD_DAT1__AG) \r
+/* Analog MUX bux enable */\r
+#define SD_DAT1_AMUX (* (reg8 *) SD_DAT1__AMUX) \r
+/* Bidirectional Enable */ \r
+#define SD_DAT1_BIE (* (reg8 *) SD_DAT1__BIE)\r
+/* Bit-mask for Aliased Register Access */\r
+#define SD_DAT1_BIT_MASK (* (reg8 *) SD_DAT1__BIT_MASK)\r
+/* Bypass Enable */\r
+#define SD_DAT1_BYP (* (reg8 *) SD_DAT1__BYP)\r
+/* Port wide control signals */ \r
+#define SD_DAT1_CTL (* (reg8 *) SD_DAT1__CTL)\r
+/* Drive Modes */\r
+#define SD_DAT1_DM0 (* (reg8 *) SD_DAT1__DM0) \r
+#define SD_DAT1_DM1 (* (reg8 *) SD_DAT1__DM1)\r
+#define SD_DAT1_DM2 (* (reg8 *) SD_DAT1__DM2) \r
+/* Input Buffer Disable Override */\r
+#define SD_DAT1_INP_DIS (* (reg8 *) SD_DAT1__INP_DIS)\r
+/* LCD Common or Segment Drive */\r
+#define SD_DAT1_LCD_COM_SEG (* (reg8 *) SD_DAT1__LCD_COM_SEG)\r
+/* Enable Segment LCD */\r
+#define SD_DAT1_LCD_EN (* (reg8 *) SD_DAT1__LCD_EN)\r
+/* Slew Rate Control */\r
+#define SD_DAT1_SLW (* (reg8 *) SD_DAT1__SLW)\r
+\r
+/* DSI Port Registers */\r
+/* Global DSI Select Register */\r
+#define SD_DAT1_PRTDSI__CAPS_SEL (* (reg8 *) SD_DAT1__PRTDSI__CAPS_SEL) \r
+/* Double Sync Enable */\r
+#define SD_DAT1_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_DAT1__PRTDSI__DBL_SYNC_IN) \r
+/* Output Enable Select Drive Strength */\r
+#define SD_DAT1_PRTDSI__OE_SEL0 (* (reg8 *) SD_DAT1__PRTDSI__OE_SEL0) \r
+#define SD_DAT1_PRTDSI__OE_SEL1 (* (reg8 *) SD_DAT1__PRTDSI__OE_SEL1) \r
+/* Port Pin Output Select Registers */\r
+#define SD_DAT1_PRTDSI__OUT_SEL0 (* (reg8 *) SD_DAT1__PRTDSI__OUT_SEL0) \r
+#define SD_DAT1_PRTDSI__OUT_SEL1 (* (reg8 *) SD_DAT1__PRTDSI__OUT_SEL1) \r
+/* Sync Output Enable Registers */\r
+#define SD_DAT1_PRTDSI__SYNC_OUT (* (reg8 *) SD_DAT1__PRTDSI__SYNC_OUT) \r
+\r
+\r
+#if defined(SD_DAT1__INTSTAT) /* Interrupt Registers */\r
+\r
+ #define SD_DAT1_INTSTAT (* (reg8 *) SD_DAT1__INTSTAT)\r
+ #define SD_DAT1_SNAP (* (reg8 *) SD_DAT1__SNAP)\r
+\r
+#endif /* Interrupt Registers */\r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+#endif /* CY_PINS_SD_DAT1_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_DAT1.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SD_DAT1_ALIASES_H) /* Pins SD_DAT1_ALIASES_H */\r
+#define CY_PINS_SD_DAT1_ALIASES_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+\r
+\r
+/***************************************\r
+* Constants \r
+***************************************/\r
+#define SD_DAT1_0 SD_DAT1__0__PC\r
+\r
+#endif /* End Pins SD_DAT1_ALIASES_H */\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_DAT2.c \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file contains API to enable firmware control of a Pins component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "cytypes.h"\r
+#include "SD_DAT2.h"\r
+\r
+/* APIs are not generated for P15[7:6] on PSoC 5 */\r
+#if !(CY_PSOC5A &&\\r
+ SD_DAT2__PORT == 15 && ((SD_DAT2__MASK & 0xC0) != 0))\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_DAT2_Write\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Assign a new value to the digital port's data output register. \r
+*\r
+* Parameters: \r
+* prtValue: The value to be assigned to the Digital Port. \r
+*\r
+* Return: \r
+* None\r
+* \r
+*******************************************************************************/\r
+void SD_DAT2_Write(uint8 value) \r
+{\r
+ uint8 staticBits = (SD_DAT2_DR & (uint8)(~SD_DAT2_MASK));\r
+ SD_DAT2_DR = staticBits | ((uint8)(value << SD_DAT2_SHIFT) & SD_DAT2_MASK);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_DAT2_SetDriveMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Change the drive mode on the pins of the port.\r
+* \r
+* Parameters: \r
+* mode: Change the pins to this drive mode.\r
+*\r
+* Return: \r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_DAT2_SetDriveMode(uint8 mode) \r
+{\r
+ CyPins_SetPinDriveMode(SD_DAT2_0, mode);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_DAT2_Read\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value on the pins of the Digital Port in right justified \r
+* form.\r
+*\r
+* Parameters: \r
+* None\r
+*\r
+* Return: \r
+* Returns the current value of the Digital Port as a right justified number\r
+* \r
+* Note:\r
+* Macro SD_DAT2_ReadPS calls this function. \r
+* \r
+*******************************************************************************/\r
+uint8 SD_DAT2_Read(void) \r
+{\r
+ return (SD_DAT2_PS & SD_DAT2_MASK) >> SD_DAT2_SHIFT;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_DAT2_ReadDataReg\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value assigned to a Digital Port's data output register\r
+*\r
+* Parameters: \r
+* None \r
+*\r
+* Return: \r
+* Returns the current value assigned to the Digital Port's data output register\r
+* \r
+*******************************************************************************/\r
+uint8 SD_DAT2_ReadDataReg(void) \r
+{\r
+ return (SD_DAT2_DR & SD_DAT2_MASK) >> SD_DAT2_SHIFT;\r
+}\r
+\r
+\r
+/* If Interrupts Are Enabled for this Pins component */ \r
+#if defined(SD_DAT2_INTSTAT) \r
+\r
+ /*******************************************************************************\r
+ * Function Name: SD_DAT2_ClearInterrupt\r
+ ********************************************************************************\r
+ * Summary:\r
+ * Clears any active interrupts attached to port and returns the value of the \r
+ * interrupt status register.\r
+ *\r
+ * Parameters: \r
+ * None \r
+ *\r
+ * Return: \r
+ * Returns the value of the interrupt status register\r
+ * \r
+ *******************************************************************************/\r
+ uint8 SD_DAT2_ClearInterrupt(void) \r
+ {\r
+ return (SD_DAT2_INTSTAT & SD_DAT2_MASK) >> SD_DAT2_SHIFT;\r
+ }\r
+\r
+#endif /* If Interrupts Are Enabled for this Pins component */ \r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+ \r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_DAT2.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SD_DAT2_H) /* Pins SD_DAT2_H */\r
+#define CY_PINS_SD_DAT2_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+#include "cypins.h"\r
+#include "SD_DAT2_aliases.h"\r
+\r
+/* Check to see if required defines such as CY_PSOC5A are available */\r
+/* They are defined starting with cy_boot v3.0 */\r
+#if !defined (CY_PSOC5A)\r
+ #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5A) */\r
+\r
+/* APIs are not generated for P15[7:6] */\r
+#if !(CY_PSOC5A &&\\r
+ SD_DAT2__PORT == 15 && ((SD_DAT2__MASK & 0xC0) != 0))\r
+\r
+\r
+/***************************************\r
+* Function Prototypes \r
+***************************************/ \r
+\r
+void SD_DAT2_Write(uint8 value) ;\r
+void SD_DAT2_SetDriveMode(uint8 mode) ;\r
+uint8 SD_DAT2_ReadDataReg(void) ;\r
+uint8 SD_DAT2_Read(void) ;\r
+uint8 SD_DAT2_ClearInterrupt(void) ;\r
+\r
+\r
+/***************************************\r
+* API Constants \r
+***************************************/\r
+\r
+/* Drive Modes */\r
+#define SD_DAT2_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+#define SD_DAT2_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+#define SD_DAT2_DM_RES_UP PIN_DM_RES_UP\r
+#define SD_DAT2_DM_RES_DWN PIN_DM_RES_DWN\r
+#define SD_DAT2_DM_OD_LO PIN_DM_OD_LO\r
+#define SD_DAT2_DM_OD_HI PIN_DM_OD_HI\r
+#define SD_DAT2_DM_STRONG PIN_DM_STRONG\r
+#define SD_DAT2_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+\r
+/* Digital Port Constants */\r
+#define SD_DAT2_MASK SD_DAT2__MASK\r
+#define SD_DAT2_SHIFT SD_DAT2__SHIFT\r
+#define SD_DAT2_WIDTH 1u\r
+\r
+\r
+/***************************************\r
+* Registers \r
+***************************************/\r
+\r
+/* Main Port Registers */\r
+/* Pin State */\r
+#define SD_DAT2_PS (* (reg8 *) SD_DAT2__PS)\r
+/* Data Register */\r
+#define SD_DAT2_DR (* (reg8 *) SD_DAT2__DR)\r
+/* Port Number */\r
+#define SD_DAT2_PRT_NUM (* (reg8 *) SD_DAT2__PRT) \r
+/* Connect to Analog Globals */ \r
+#define SD_DAT2_AG (* (reg8 *) SD_DAT2__AG) \r
+/* Analog MUX bux enable */\r
+#define SD_DAT2_AMUX (* (reg8 *) SD_DAT2__AMUX) \r
+/* Bidirectional Enable */ \r
+#define SD_DAT2_BIE (* (reg8 *) SD_DAT2__BIE)\r
+/* Bit-mask for Aliased Register Access */\r
+#define SD_DAT2_BIT_MASK (* (reg8 *) SD_DAT2__BIT_MASK)\r
+/* Bypass Enable */\r
+#define SD_DAT2_BYP (* (reg8 *) SD_DAT2__BYP)\r
+/* Port wide control signals */ \r
+#define SD_DAT2_CTL (* (reg8 *) SD_DAT2__CTL)\r
+/* Drive Modes */\r
+#define SD_DAT2_DM0 (* (reg8 *) SD_DAT2__DM0) \r
+#define SD_DAT2_DM1 (* (reg8 *) SD_DAT2__DM1)\r
+#define SD_DAT2_DM2 (* (reg8 *) SD_DAT2__DM2) \r
+/* Input Buffer Disable Override */\r
+#define SD_DAT2_INP_DIS (* (reg8 *) SD_DAT2__INP_DIS)\r
+/* LCD Common or Segment Drive */\r
+#define SD_DAT2_LCD_COM_SEG (* (reg8 *) SD_DAT2__LCD_COM_SEG)\r
+/* Enable Segment LCD */\r
+#define SD_DAT2_LCD_EN (* (reg8 *) SD_DAT2__LCD_EN)\r
+/* Slew Rate Control */\r
+#define SD_DAT2_SLW (* (reg8 *) SD_DAT2__SLW)\r
+\r
+/* DSI Port Registers */\r
+/* Global DSI Select Register */\r
+#define SD_DAT2_PRTDSI__CAPS_SEL (* (reg8 *) SD_DAT2__PRTDSI__CAPS_SEL) \r
+/* Double Sync Enable */\r
+#define SD_DAT2_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_DAT2__PRTDSI__DBL_SYNC_IN) \r
+/* Output Enable Select Drive Strength */\r
+#define SD_DAT2_PRTDSI__OE_SEL0 (* (reg8 *) SD_DAT2__PRTDSI__OE_SEL0) \r
+#define SD_DAT2_PRTDSI__OE_SEL1 (* (reg8 *) SD_DAT2__PRTDSI__OE_SEL1) \r
+/* Port Pin Output Select Registers */\r
+#define SD_DAT2_PRTDSI__OUT_SEL0 (* (reg8 *) SD_DAT2__PRTDSI__OUT_SEL0) \r
+#define SD_DAT2_PRTDSI__OUT_SEL1 (* (reg8 *) SD_DAT2__PRTDSI__OUT_SEL1) \r
+/* Sync Output Enable Registers */\r
+#define SD_DAT2_PRTDSI__SYNC_OUT (* (reg8 *) SD_DAT2__PRTDSI__SYNC_OUT) \r
+\r
+\r
+#if defined(SD_DAT2__INTSTAT) /* Interrupt Registers */\r
+\r
+ #define SD_DAT2_INTSTAT (* (reg8 *) SD_DAT2__INTSTAT)\r
+ #define SD_DAT2_SNAP (* (reg8 *) SD_DAT2__SNAP)\r
+\r
+#endif /* Interrupt Registers */\r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+#endif /* CY_PINS_SD_DAT2_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_DAT2.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SD_DAT2_ALIASES_H) /* Pins SD_DAT2_ALIASES_H */\r
+#define CY_PINS_SD_DAT2_ALIASES_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+\r
+\r
+/***************************************\r
+* Constants \r
+***************************************/\r
+#define SD_DAT2_0 SD_DAT2__0__PC\r
+\r
+#endif /* End Pins SD_DAT2_ALIASES_H */\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_Data_Clk.c\r
+* Version 2.0\r
+*\r
+* Description:\r
+* This file provides the source code to the API for the clock component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include <cydevice_trm.h>\r
+#include "SD_Data_Clk.h"\r
+\r
+/* Clock Distribution registers. */\r
+#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD)\r
+#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2)\r
+#define BCFG2_MASK (0x80u)\r
+#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK)\r
+#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK)\r
+\r
+#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP)\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Data_Clk_Start\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Starts the clock. Note that on startup, clocks may be already running if the\r
+* "Start on Reset" option is enabled in the DWR.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_Data_Clk_Start(void) \r
+{\r
+ /* Set the bit to enable the clock. */\r
+ SD_Data_Clk_CLKEN |= SD_Data_Clk_CLKEN_MASK;\r
+ SD_Data_Clk_CLKSTBY |= SD_Data_Clk_CLKSTBY_MASK;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Data_Clk_Stop\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Stops the clock and returns immediately. This API does not require the\r
+* source clock to be running but may return before the hardware is actually\r
+* disabled. If the settings of the clock are changed after calling this\r
+* function, the clock may glitch when it is started. To avoid the clock\r
+* glitch, use the StopBlock function.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_Data_Clk_Stop(void) \r
+{\r
+ /* Clear the bit to disable the clock. */\r
+ SD_Data_Clk_CLKEN &= (uint8)(~SD_Data_Clk_CLKEN_MASK);\r
+ SD_Data_Clk_CLKSTBY &= (uint8)(~SD_Data_Clk_CLKSTBY_MASK);\r
+}\r
+\r
+\r
+#if(CY_PSOC3 || CY_PSOC5LP)\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Data_Clk_StopBlock\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Stops the clock and waits for the hardware to actually be disabled before\r
+* returning. This ensures that the clock is never truncated (high part of the\r
+* cycle will terminate before the clock is disabled and the API returns).\r
+* Note that the source clock must be running or this API will never return as\r
+* a stopped clock cannot be disabled.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_Data_Clk_StopBlock(void) \r
+{\r
+ if ((SD_Data_Clk_CLKEN & SD_Data_Clk_CLKEN_MASK) != 0u)\r
+ {\r
+#if HAS_CLKDIST_LD_DISABLE\r
+ uint16 oldDivider;\r
+\r
+ CLK_DIST_LD = 0u;\r
+\r
+ /* Clear all the mask bits except ours. */\r
+#if defined(SD_Data_Clk__CFG3)\r
+ CLK_DIST_AMASK = SD_Data_Clk_CLKEN_MASK;\r
+ CLK_DIST_DMASK = 0x00u;\r
+#else\r
+ CLK_DIST_DMASK = SD_Data_Clk_CLKEN_MASK;\r
+ CLK_DIST_AMASK = 0x00u;\r
+#endif /* SD_Data_Clk__CFG3 */\r
+\r
+ /* Clear mask of bus clock. */\r
+ CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);\r
+\r
+ oldDivider = CY_GET_REG16(SD_Data_Clk_DIV_PTR);\r
+ CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);\r
+ CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;\r
+\r
+ /* Wait for clock to be disabled */\r
+ while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
+#endif /* HAS_CLKDIST_LD_DISABLE */\r
+\r
+ /* Clear the bit to disable the clock. */\r
+ SD_Data_Clk_CLKEN &= (uint8)(~SD_Data_Clk_CLKEN_MASK);\r
+ SD_Data_Clk_CLKSTBY &= (uint8)(~SD_Data_Clk_CLKSTBY_MASK);\r
+\r
+#if HAS_CLKDIST_LD_DISABLE\r
+ /* Clear the disable bit */\r
+ CLK_DIST_LD = 0x00u;\r
+ CY_SET_REG16(SD_Data_Clk_DIV_PTR, oldDivider);\r
+#endif /* HAS_CLKDIST_LD_DISABLE */\r
+ }\r
+}\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Data_Clk_StandbyPower\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets whether the clock is active in standby mode.\r
+*\r
+* Parameters:\r
+* state: 0 to disable clock during standby, nonzero to enable.\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_Data_Clk_StandbyPower(uint8 state) \r
+{\r
+ if(state == 0u)\r
+ {\r
+ SD_Data_Clk_CLKSTBY &= (uint8)(~SD_Data_Clk_CLKSTBY_MASK);\r
+ }\r
+ else\r
+ {\r
+ SD_Data_Clk_CLKSTBY |= SD_Data_Clk_CLKSTBY_MASK;\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Data_Clk_SetDividerRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Modifies the clock divider and, thus, the frequency. When the clock divider\r
+* register is set to zero or changed from zero, the clock will be temporarily\r
+* disabled in order to change the SSS mode bit. If the clock is enabled when\r
+* SetDividerRegister is called, then the source clock must be running.\r
+*\r
+* Parameters:\r
+* clkDivider: Divider register value (0-65,535). This value is NOT the\r
+* divider; the clock hardware divides by clkDivider plus one. For example,\r
+* to divide the clock by 2, this parameter should be set to 1.\r
+* restart: If nonzero, restarts the clock divider: the current clock cycle\r
+* will be truncated and the new divide value will take effect immediately. If\r
+* zero, the new divide value will take effect at the end of the current clock\r
+* cycle.\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_Data_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart)\r
+ \r
+{\r
+ uint8 enabled;\r
+\r
+ uint8 currSrc = SD_Data_Clk_GetSourceRegister();\r
+ uint16 oldDivider = SD_Data_Clk_GetDividerRegister();\r
+\r
+ if (clkDivider != oldDivider)\r
+ {\r
+ enabled = SD_Data_Clk_CLKEN & SD_Data_Clk_CLKEN_MASK;\r
+\r
+ if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))\r
+ {\r
+ /* Moving to/from SSS requires correct ordering to prevent halting the clock */\r
+ if (oldDivider == 0u)\r
+ {\r
+ /* Moving away from SSS, set the divider first so when SSS is cleared we */\r
+ /* don't halt the clock. Using the shadow load isn't required as the */\r
+ /* divider is ignored while SSS is set. */\r
+ CY_SET_REG16(SD_Data_Clk_DIV_PTR, clkDivider);\r
+ SD_Data_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS);\r
+ }\r
+ else\r
+ {\r
+ /* Moving to SSS, set SSS which then ignores the divider and we can set */\r
+ /* it without bothering with the shadow load. */\r
+ SD_Data_Clk_MOD_SRC |= CYCLK_SSS;\r
+ CY_SET_REG16(SD_Data_Clk_DIV_PTR, clkDivider);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ \r
+ if (enabled != 0u)\r
+ {\r
+ CLK_DIST_LD = 0x00u;\r
+\r
+ /* Clear all the mask bits except ours. */\r
+#if defined(SD_Data_Clk__CFG3)\r
+ CLK_DIST_AMASK = SD_Data_Clk_CLKEN_MASK;\r
+ CLK_DIST_DMASK = 0x00u;\r
+#else\r
+ CLK_DIST_DMASK = SD_Data_Clk_CLKEN_MASK;\r
+ CLK_DIST_AMASK = 0x00u;\r
+#endif /* SD_Data_Clk__CFG3 */\r
+ /* Clear mask of bus clock. */\r
+ CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);\r
+\r
+ /* If clock is currently enabled, disable it if async or going from N-to-1*/\r
+ if (((SD_Data_Clk_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))\r
+ {\r
+#if HAS_CLKDIST_LD_DISABLE\r
+ CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);\r
+ CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;\r
+\r
+ /* Wait for clock to be disabled */\r
+ while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
+#endif /* HAS_CLKDIST_LD_DISABLE */\r
+\r
+ SD_Data_Clk_CLKEN &= (uint8)(~SD_Data_Clk_CLKEN_MASK);\r
+\r
+#if HAS_CLKDIST_LD_DISABLE\r
+ /* Clear the disable bit */\r
+ CLK_DIST_LD = 0x00u;\r
+#endif /* HAS_CLKDIST_LD_DISABLE */\r
+ }\r
+ }\r
+\r
+ /* Load divide value. */\r
+ if ((SD_Data_Clk_CLKEN & SD_Data_Clk_CLKEN_MASK) != 0u)\r
+ {\r
+ /* If the clock is still enabled, use the shadow registers */\r
+ CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);\r
+\r
+ CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));\r
+ while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
+ }\r
+ else\r
+ {\r
+ /* If the clock is disabled, set the divider directly */\r
+ CY_SET_REG16(SD_Data_Clk_DIV_PTR, clkDivider);\r
+ SD_Data_Clk_CLKEN |= enabled;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Data_Clk_GetDividerRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Gets the clock divider register value.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* Divide value of the clock minus 1. For example, if the clock is set to\r
+* divide by 2, the return value will be 1.\r
+*\r
+*******************************************************************************/\r
+uint16 SD_Data_Clk_GetDividerRegister(void) \r
+{\r
+ return CY_GET_REG16(SD_Data_Clk_DIV_PTR);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Data_Clk_SetModeRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets flags that control the operating mode of the clock. This function only\r
+* changes flags from 0 to 1; flags that are already 1 will remain unchanged.\r
+* To clear flags, use the ClearModeRegister function. The clock must be\r
+* disabled before changing the mode.\r
+*\r
+* Parameters:\r
+* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,\r
+* clkMode should be a set of the following optional bits or'ed together.\r
+* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will\r
+* occur when the divider count reaches half of the divide\r
+* value.\r
+* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock\r
+* is asserted for approximately half of its period. When\r
+* disabled, the output clock is asserted for one period of the\r
+* source clock.\r
+* - CYCLK_SYNC Enable output synchronization to master clock. This should\r
+* be enabled for all synchronous clocks.\r
+* See the Technical Reference Manual for details about setting the mode of\r
+* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_Data_Clk_SetModeRegister(uint8 modeBitMask) \r
+{\r
+ SD_Data_Clk_MOD_SRC |= modeBitMask & (uint8)SD_Data_Clk_MODE_MASK;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Data_Clk_ClearModeRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Clears flags that control the operating mode of the clock. This function\r
+* only changes flags from 1 to 0; flags that are already 0 will remain\r
+* unchanged. To set flags, use the SetModeRegister function. The clock must be\r
+* disabled before changing the mode.\r
+*\r
+* Parameters:\r
+* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,\r
+* clkMode should be a set of the following optional bits or'ed together.\r
+* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will\r
+* occur when the divider count reaches half of the divide\r
+* value.\r
+* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock\r
+* is asserted for approximately half of its period. When\r
+* disabled, the output clock is asserted for one period of the\r
+* source clock.\r
+* - CYCLK_SYNC Enable output synchronization to master clock. This should\r
+* be enabled for all synchronous clocks.\r
+* See the Technical Reference Manual for details about setting the mode of\r
+* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_Data_Clk_ClearModeRegister(uint8 modeBitMask) \r
+{\r
+ SD_Data_Clk_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SD_Data_Clk_MODE_MASK));\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Data_Clk_GetModeRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Gets the clock mode register value.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* Bit mask representing the enabled mode bits. See the SetModeRegister and\r
+* ClearModeRegister descriptions for details about the mode bits.\r
+*\r
+*******************************************************************************/\r
+uint8 SD_Data_Clk_GetModeRegister(void) \r
+{\r
+ return SD_Data_Clk_MOD_SRC & (uint8)(SD_Data_Clk_MODE_MASK);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Data_Clk_SetSourceRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the input source of the clock. The clock must be disabled before\r
+* changing the source. The old and new clock sources must be running.\r
+*\r
+* Parameters:\r
+* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the\r
+* following input sources:\r
+* - CYCLK_SRC_SEL_SYNC_DIG\r
+* - CYCLK_SRC_SEL_IMO\r
+* - CYCLK_SRC_SEL_XTALM\r
+* - CYCLK_SRC_SEL_ILO\r
+* - CYCLK_SRC_SEL_PLL\r
+* - CYCLK_SRC_SEL_XTALK\r
+* - CYCLK_SRC_SEL_DSI_G\r
+* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A\r
+* See the Technical Reference Manual for details on clock sources.\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_Data_Clk_SetSourceRegister(uint8 clkSource) \r
+{\r
+ uint16 currDiv = SD_Data_Clk_GetDividerRegister();\r
+ uint8 oldSrc = SD_Data_Clk_GetSourceRegister();\r
+\r
+ if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && \r
+ (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))\r
+ {\r
+ /* Switching to Master and divider is 1, set SSS, which will output master, */\r
+ /* then set the source so we are consistent. */\r
+ SD_Data_Clk_MOD_SRC |= CYCLK_SSS;\r
+ SD_Data_Clk_MOD_SRC =\r
+ (SD_Data_Clk_MOD_SRC & (uint8)(~SD_Data_Clk_SRC_SEL_MSK)) | clkSource;\r
+ }\r
+ else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && \r
+ (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))\r
+ {\r
+ /* Switching from Master to not and divider is 1, set source, so we don't */\r
+ /* lock when we clear SSS. */\r
+ SD_Data_Clk_MOD_SRC =\r
+ (SD_Data_Clk_MOD_SRC & (uint8)(~SD_Data_Clk_SRC_SEL_MSK)) | clkSource;\r
+ SD_Data_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS);\r
+ }\r
+ else\r
+ {\r
+ SD_Data_Clk_MOD_SRC =\r
+ (SD_Data_Clk_MOD_SRC & (uint8)(~SD_Data_Clk_SRC_SEL_MSK)) | clkSource;\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Data_Clk_GetSourceRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Gets the input source of the clock.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* The input source of the clock. See SetSourceRegister for details.\r
+*\r
+*******************************************************************************/\r
+uint8 SD_Data_Clk_GetSourceRegister(void) \r
+{\r
+ return SD_Data_Clk_MOD_SRC & SD_Data_Clk_SRC_SEL_MSK;\r
+}\r
+\r
+\r
+#if defined(SD_Data_Clk__CFG3)\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Data_Clk_SetPhaseRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the phase delay of the analog clock. This function is only available\r
+* for analog clocks. The clock must be disabled before changing the phase\r
+* delay to avoid glitches.\r
+*\r
+* Parameters:\r
+* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.\r
+* clkPhase must be from 1 to 11 inclusive. Other values, including 0,\r
+* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 \r
+* produces a 10ns delay.\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_Data_Clk_SetPhaseRegister(uint8 clkPhase) \r
+{\r
+ SD_Data_Clk_PHASE = clkPhase & SD_Data_Clk_PHASE_MASK;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Data_Clk_GetPhase\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Gets the phase delay of the analog clock. This function is only available\r
+* for analog clocks.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* Phase of the analog clock. See SetPhaseRegister for details.\r
+*\r
+*******************************************************************************/\r
+uint8 SD_Data_Clk_GetPhaseRegister(void) \r
+{\r
+ return SD_Data_Clk_PHASE & SD_Data_Clk_PHASE_MASK;\r
+}\r
+\r
+#endif /* SD_Data_Clk__CFG3 */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_Data_Clk.h\r
+* Version 2.0\r
+*\r
+* Description:\r
+* Provides the function and constant definitions for the clock component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_CLOCK_SD_Data_Clk_H)\r
+#define CY_CLOCK_SD_Data_Clk_H\r
+\r
+#include <cytypes.h>\r
+#include <cyfitter.h>\r
+\r
+\r
+/***************************************\r
+* Conditional Compilation Parameters\r
+***************************************/\r
+\r
+/* Check to see if required defines such as CY_PSOC5LP are available */\r
+/* They are defined starting with cy_boot v3.0 */\r
+#if !defined (CY_PSOC5LP)\r
+ #error Component cy_clock_v2_0 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5LP) */\r
+\r
+\r
+/***************************************\r
+* Function Prototypes\r
+***************************************/\r
+\r
+void SD_Data_Clk_Start(void) ;\r
+void SD_Data_Clk_Stop(void) ;\r
+\r
+#if(CY_PSOC3 || CY_PSOC5LP)\r
+void SD_Data_Clk_StopBlock(void) ;\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+void SD_Data_Clk_StandbyPower(uint8 state) ;\r
+void SD_Data_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) \r
+ ;\r
+uint16 SD_Data_Clk_GetDividerRegister(void) ;\r
+void SD_Data_Clk_SetModeRegister(uint8 modeBitMask) ;\r
+void SD_Data_Clk_ClearModeRegister(uint8 modeBitMask) ;\r
+uint8 SD_Data_Clk_GetModeRegister(void) ;\r
+void SD_Data_Clk_SetSourceRegister(uint8 clkSource) ;\r
+uint8 SD_Data_Clk_GetSourceRegister(void) ;\r
+#if defined(SD_Data_Clk__CFG3)\r
+void SD_Data_Clk_SetPhaseRegister(uint8 clkPhase) ;\r
+uint8 SD_Data_Clk_GetPhaseRegister(void) ;\r
+#endif /* defined(SD_Data_Clk__CFG3) */\r
+\r
+#define SD_Data_Clk_Enable() SD_Data_Clk_Start()\r
+#define SD_Data_Clk_Disable() SD_Data_Clk_Stop()\r
+#define SD_Data_Clk_SetDivider(clkDivider) SD_Data_Clk_SetDividerRegister(clkDivider, 1)\r
+#define SD_Data_Clk_SetDividerValue(clkDivider) SD_Data_Clk_SetDividerRegister((clkDivider) - 1, 1)\r
+#define SD_Data_Clk_SetMode(clkMode) SD_Data_Clk_SetModeRegister(clkMode)\r
+#define SD_Data_Clk_SetSource(clkSource) SD_Data_Clk_SetSourceRegister(clkSource)\r
+#if defined(SD_Data_Clk__CFG3)\r
+#define SD_Data_Clk_SetPhase(clkPhase) SD_Data_Clk_SetPhaseRegister(clkPhase)\r
+#define SD_Data_Clk_SetPhaseValue(clkPhase) SD_Data_Clk_SetPhaseRegister((clkPhase) + 1)\r
+#endif /* defined(SD_Data_Clk__CFG3) */\r
+\r
+\r
+/***************************************\r
+* Registers\r
+***************************************/\r
+\r
+/* Register to enable or disable the clock */\r
+#define SD_Data_Clk_CLKEN (* (reg8 *) SD_Data_Clk__PM_ACT_CFG)\r
+#define SD_Data_Clk_CLKEN_PTR ((reg8 *) SD_Data_Clk__PM_ACT_CFG)\r
+\r
+/* Register to enable or disable the clock */\r
+#define SD_Data_Clk_CLKSTBY (* (reg8 *) SD_Data_Clk__PM_STBY_CFG)\r
+#define SD_Data_Clk_CLKSTBY_PTR ((reg8 *) SD_Data_Clk__PM_STBY_CFG)\r
+\r
+/* Clock LSB divider configuration register. */\r
+#define SD_Data_Clk_DIV_LSB (* (reg8 *) SD_Data_Clk__CFG0)\r
+#define SD_Data_Clk_DIV_LSB_PTR ((reg8 *) SD_Data_Clk__CFG0)\r
+#define SD_Data_Clk_DIV_PTR ((reg16 *) SD_Data_Clk__CFG0)\r
+\r
+/* Clock MSB divider configuration register. */\r
+#define SD_Data_Clk_DIV_MSB (* (reg8 *) SD_Data_Clk__CFG1)\r
+#define SD_Data_Clk_DIV_MSB_PTR ((reg8 *) SD_Data_Clk__CFG1)\r
+\r
+/* Mode and source configuration register */\r
+#define SD_Data_Clk_MOD_SRC (* (reg8 *) SD_Data_Clk__CFG2)\r
+#define SD_Data_Clk_MOD_SRC_PTR ((reg8 *) SD_Data_Clk__CFG2)\r
+\r
+#if defined(SD_Data_Clk__CFG3)\r
+/* Analog clock phase configuration register */\r
+#define SD_Data_Clk_PHASE (* (reg8 *) SD_Data_Clk__CFG3)\r
+#define SD_Data_Clk_PHASE_PTR ((reg8 *) SD_Data_Clk__CFG3)\r
+#endif /* defined(SD_Data_Clk__CFG3) */\r
+\r
+\r
+/**************************************\r
+* Register Constants\r
+**************************************/\r
+\r
+/* Power manager register masks */\r
+#define SD_Data_Clk_CLKEN_MASK SD_Data_Clk__PM_ACT_MSK\r
+#define SD_Data_Clk_CLKSTBY_MASK SD_Data_Clk__PM_STBY_MSK\r
+\r
+/* CFG2 field masks */\r
+#define SD_Data_Clk_SRC_SEL_MSK SD_Data_Clk__CFG2_SRC_SEL_MASK\r
+#define SD_Data_Clk_MODE_MASK (~(SD_Data_Clk_SRC_SEL_MSK))\r
+\r
+#if defined(SD_Data_Clk__CFG3)\r
+/* CFG3 phase mask */\r
+#define SD_Data_Clk_PHASE_MASK SD_Data_Clk__CFG3_PHASE_DLY_MASK\r
+#endif /* defined(SD_Data_Clk__CFG3) */\r
+\r
+#endif /* CY_CLOCK_SD_Data_Clk_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_INT.c\r
+* Version 2.40\r
+*\r
+* Description:\r
+* This file provides all Interrupt Service Routine (ISR) for the SPI Master\r
+* component.\r
+*\r
+* Note:\r
+* None.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "SD_PVT.h"\r
+\r
+/* User code required at start of ISR */\r
+/* `#START SD_ISR_START_DEF` */\r
+\r
+/* `#END` */\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_TX_ISR\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Interrupt Service Routine for TX portion of the SPI Master.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global variables:\r
+* SD_txBufferWrite - used for the account of the bytes which\r
+* have been written down in the TX software buffer.\r
+* SD_txBufferRead - used for the account of the bytes which\r
+* have been read from the TX software buffer, modified when exist data to\r
+* sending and FIFO Not Full.\r
+* SD_txBuffer[SD_TX_BUFFER_SIZE] - used to store\r
+* data to sending.\r
+* All described above Global variables are used when Software Buffer is used.\r
+*\r
+*******************************************************************************/\r
+CY_ISR(SD_TX_ISR)\r
+{\r
+ #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
+ uint8 tmpStatus;\r
+ #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ /* User code required at start of ISR */\r
+ /* `#START SD_TX_ISR_START` */\r
+\r
+ /* `#END` */\r
+\r
+ #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
+ /* Check if TX data buffer is not empty and there is space in TX FIFO */\r
+ while(SD_txBufferRead != SD_txBufferWrite)\r
+ {\r
+ tmpStatus = SD_GET_STATUS_TX(SD_swStatusTx);\r
+ SD_swStatusTx = tmpStatus;\r
+\r
+ if(0u != (SD_swStatusTx & SD_STS_TX_FIFO_NOT_FULL))\r
+ {\r
+ if(0u == SD_txBufferFull)\r
+ {\r
+ SD_txBufferRead++;\r
+\r
+ if(SD_txBufferRead >= SD_TX_BUFFER_SIZE)\r
+ {\r
+ SD_txBufferRead = 0u;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ SD_txBufferFull = 0u;\r
+ }\r
+\r
+ /* Move data from the Buffer to the FIFO */\r
+ CY_SET_REG8(SD_TXDATA_PTR,\r
+ SD_txBuffer[SD_txBufferRead]);\r
+ }\r
+ else\r
+ {\r
+ break;\r
+ }\r
+ }\r
+\r
+ if(SD_txBufferRead == SD_txBufferWrite)\r
+ {\r
+ /* TX Buffer is EMPTY: disable interrupt on TX NOT FULL */\r
+ SD_TX_STATUS_MASK_REG &= ((uint8) ~SD_STS_TX_FIFO_NOT_FULL);\r
+ }\r
+\r
+ #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ /* User code required at end of ISR (Optional) */\r
+ /* `#START SD_TX_ISR_END` */\r
+\r
+ /* `#END` */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_RX_ISR\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Interrupt Service Routine for RX portion of the SPI Master.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global variables:\r
+* SD_rxBufferWrite - used for the account of the bytes which\r
+* have been written down in the RX software buffer modified when FIFO contains\r
+* new data.\r
+* SD_rxBufferRead - used for the account of the bytes which\r
+* have been read from the RX software buffer, modified when overflow occurred.\r
+* SD_rxBuffer[SD_RX_BUFFER_SIZE] - used to store\r
+* received data, modified when FIFO contains new data.\r
+* All described above Global variables are used when Software Buffer is used.\r
+*\r
+*******************************************************************************/\r
+CY_ISR(SD_RX_ISR)\r
+{\r
+ #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
+ uint8 tmpStatus;\r
+ uint8 rxData;\r
+ #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ /* User code required at start of ISR */\r
+ /* `#START SD_RX_ISR_START` */\r
+\r
+ /* `#END` */\r
+\r
+ #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
+\r
+ tmpStatus = SD_GET_STATUS_RX(SD_swStatusRx);\r
+ SD_swStatusRx = tmpStatus;\r
+\r
+ /* Check if RX data FIFO has some data to be moved into the RX Buffer */\r
+ while(0u != (SD_swStatusRx & SD_STS_RX_FIFO_NOT_EMPTY))\r
+ {\r
+ rxData = CY_GET_REG8(SD_RXDATA_PTR);\r
+\r
+ /* Set next pointer. */\r
+ SD_rxBufferWrite++;\r
+ if(SD_rxBufferWrite >= SD_RX_BUFFER_SIZE)\r
+ {\r
+ SD_rxBufferWrite = 0u;\r
+ }\r
+\r
+ if(SD_rxBufferWrite == SD_rxBufferRead)\r
+ {\r
+ SD_rxBufferRead++;\r
+ if(SD_rxBufferRead >= SD_RX_BUFFER_SIZE)\r
+ {\r
+ SD_rxBufferRead = 0u;\r
+ }\r
+\r
+ SD_rxBufferFull = 1u;\r
+ }\r
+\r
+ /* Move data from the FIFO to the Buffer */\r
+ SD_rxBuffer[SD_rxBufferWrite] = rxData;\r
+\r
+ tmpStatus = SD_GET_STATUS_RX(SD_swStatusRx);\r
+ SD_swStatusRx = tmpStatus;\r
+ }\r
+\r
+ #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ /* User code required at end of ISR (Optional) */\r
+ /* `#START SD_RX_ISR_END` */\r
+\r
+ /* `#END` */\r
+}\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_Init_Clk.c\r
+* Version 2.0\r
+*\r
+* Description:\r
+* This file provides the source code to the API for the clock component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include <cydevice_trm.h>\r
+#include "SD_Init_Clk.h"\r
+\r
+/* Clock Distribution registers. */\r
+#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD)\r
+#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2)\r
+#define BCFG2_MASK (0x80u)\r
+#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK)\r
+#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK)\r
+\r
+#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP)\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Init_Clk_Start\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Starts the clock. Note that on startup, clocks may be already running if the\r
+* "Start on Reset" option is enabled in the DWR.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_Init_Clk_Start(void) \r
+{\r
+ /* Set the bit to enable the clock. */\r
+ SD_Init_Clk_CLKEN |= SD_Init_Clk_CLKEN_MASK;\r
+ SD_Init_Clk_CLKSTBY |= SD_Init_Clk_CLKSTBY_MASK;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Init_Clk_Stop\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Stops the clock and returns immediately. This API does not require the\r
+* source clock to be running but may return before the hardware is actually\r
+* disabled. If the settings of the clock are changed after calling this\r
+* function, the clock may glitch when it is started. To avoid the clock\r
+* glitch, use the StopBlock function.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_Init_Clk_Stop(void) \r
+{\r
+ /* Clear the bit to disable the clock. */\r
+ SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK);\r
+ SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK);\r
+}\r
+\r
+\r
+#if(CY_PSOC3 || CY_PSOC5LP)\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Init_Clk_StopBlock\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Stops the clock and waits for the hardware to actually be disabled before\r
+* returning. This ensures that the clock is never truncated (high part of the\r
+* cycle will terminate before the clock is disabled and the API returns).\r
+* Note that the source clock must be running or this API will never return as\r
+* a stopped clock cannot be disabled.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_Init_Clk_StopBlock(void) \r
+{\r
+ if ((SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK) != 0u)\r
+ {\r
+#if HAS_CLKDIST_LD_DISABLE\r
+ uint16 oldDivider;\r
+\r
+ CLK_DIST_LD = 0u;\r
+\r
+ /* Clear all the mask bits except ours. */\r
+#if defined(SD_Init_Clk__CFG3)\r
+ CLK_DIST_AMASK = SD_Init_Clk_CLKEN_MASK;\r
+ CLK_DIST_DMASK = 0x00u;\r
+#else\r
+ CLK_DIST_DMASK = SD_Init_Clk_CLKEN_MASK;\r
+ CLK_DIST_AMASK = 0x00u;\r
+#endif /* SD_Init_Clk__CFG3 */\r
+\r
+ /* Clear mask of bus clock. */\r
+ CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);\r
+\r
+ oldDivider = CY_GET_REG16(SD_Init_Clk_DIV_PTR);\r
+ CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);\r
+ CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;\r
+\r
+ /* Wait for clock to be disabled */\r
+ while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
+#endif /* HAS_CLKDIST_LD_DISABLE */\r
+\r
+ /* Clear the bit to disable the clock. */\r
+ SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK);\r
+ SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK);\r
+\r
+#if HAS_CLKDIST_LD_DISABLE\r
+ /* Clear the disable bit */\r
+ CLK_DIST_LD = 0x00u;\r
+ CY_SET_REG16(SD_Init_Clk_DIV_PTR, oldDivider);\r
+#endif /* HAS_CLKDIST_LD_DISABLE */\r
+ }\r
+}\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Init_Clk_StandbyPower\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets whether the clock is active in standby mode.\r
+*\r
+* Parameters:\r
+* state: 0 to disable clock during standby, nonzero to enable.\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_Init_Clk_StandbyPower(uint8 state) \r
+{\r
+ if(state == 0u)\r
+ {\r
+ SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK);\r
+ }\r
+ else\r
+ {\r
+ SD_Init_Clk_CLKSTBY |= SD_Init_Clk_CLKSTBY_MASK;\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Init_Clk_SetDividerRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Modifies the clock divider and, thus, the frequency. When the clock divider\r
+* register is set to zero or changed from zero, the clock will be temporarily\r
+* disabled in order to change the SSS mode bit. If the clock is enabled when\r
+* SetDividerRegister is called, then the source clock must be running.\r
+*\r
+* Parameters:\r
+* clkDivider: Divider register value (0-65,535). This value is NOT the\r
+* divider; the clock hardware divides by clkDivider plus one. For example,\r
+* to divide the clock by 2, this parameter should be set to 1.\r
+* restart: If nonzero, restarts the clock divider: the current clock cycle\r
+* will be truncated and the new divide value will take effect immediately. If\r
+* zero, the new divide value will take effect at the end of the current clock\r
+* cycle.\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_Init_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart)\r
+ \r
+{\r
+ uint8 enabled;\r
+\r
+ uint8 currSrc = SD_Init_Clk_GetSourceRegister();\r
+ uint16 oldDivider = SD_Init_Clk_GetDividerRegister();\r
+\r
+ if (clkDivider != oldDivider)\r
+ {\r
+ enabled = SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK;\r
+\r
+ if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))\r
+ {\r
+ /* Moving to/from SSS requires correct ordering to prevent halting the clock */\r
+ if (oldDivider == 0u)\r
+ {\r
+ /* Moving away from SSS, set the divider first so when SSS is cleared we */\r
+ /* don't halt the clock. Using the shadow load isn't required as the */\r
+ /* divider is ignored while SSS is set. */\r
+ CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider);\r
+ SD_Init_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS);\r
+ }\r
+ else\r
+ {\r
+ /* Moving to SSS, set SSS which then ignores the divider and we can set */\r
+ /* it without bothering with the shadow load. */\r
+ SD_Init_Clk_MOD_SRC |= CYCLK_SSS;\r
+ CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ \r
+ if (enabled != 0u)\r
+ {\r
+ CLK_DIST_LD = 0x00u;\r
+\r
+ /* Clear all the mask bits except ours. */\r
+#if defined(SD_Init_Clk__CFG3)\r
+ CLK_DIST_AMASK = SD_Init_Clk_CLKEN_MASK;\r
+ CLK_DIST_DMASK = 0x00u;\r
+#else\r
+ CLK_DIST_DMASK = SD_Init_Clk_CLKEN_MASK;\r
+ CLK_DIST_AMASK = 0x00u;\r
+#endif /* SD_Init_Clk__CFG3 */\r
+ /* Clear mask of bus clock. */\r
+ CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);\r
+\r
+ /* If clock is currently enabled, disable it if async or going from N-to-1*/\r
+ if (((SD_Init_Clk_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))\r
+ {\r
+#if HAS_CLKDIST_LD_DISABLE\r
+ CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);\r
+ CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;\r
+\r
+ /* Wait for clock to be disabled */\r
+ while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
+#endif /* HAS_CLKDIST_LD_DISABLE */\r
+\r
+ SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK);\r
+\r
+#if HAS_CLKDIST_LD_DISABLE\r
+ /* Clear the disable bit */\r
+ CLK_DIST_LD = 0x00u;\r
+#endif /* HAS_CLKDIST_LD_DISABLE */\r
+ }\r
+ }\r
+\r
+ /* Load divide value. */\r
+ if ((SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK) != 0u)\r
+ {\r
+ /* If the clock is still enabled, use the shadow registers */\r
+ CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);\r
+\r
+ CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));\r
+ while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
+ }\r
+ else\r
+ {\r
+ /* If the clock is disabled, set the divider directly */\r
+ CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider);\r
+ SD_Init_Clk_CLKEN |= enabled;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Init_Clk_GetDividerRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Gets the clock divider register value.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* Divide value of the clock minus 1. For example, if the clock is set to\r
+* divide by 2, the return value will be 1.\r
+*\r
+*******************************************************************************/\r
+uint16 SD_Init_Clk_GetDividerRegister(void) \r
+{\r
+ return CY_GET_REG16(SD_Init_Clk_DIV_PTR);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Init_Clk_SetModeRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets flags that control the operating mode of the clock. This function only\r
+* changes flags from 0 to 1; flags that are already 1 will remain unchanged.\r
+* To clear flags, use the ClearModeRegister function. The clock must be\r
+* disabled before changing the mode.\r
+*\r
+* Parameters:\r
+* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,\r
+* clkMode should be a set of the following optional bits or'ed together.\r
+* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will\r
+* occur when the divider count reaches half of the divide\r
+* value.\r
+* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock\r
+* is asserted for approximately half of its period. When\r
+* disabled, the output clock is asserted for one period of the\r
+* source clock.\r
+* - CYCLK_SYNC Enable output synchronization to master clock. This should\r
+* be enabled for all synchronous clocks.\r
+* See the Technical Reference Manual for details about setting the mode of\r
+* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_Init_Clk_SetModeRegister(uint8 modeBitMask) \r
+{\r
+ SD_Init_Clk_MOD_SRC |= modeBitMask & (uint8)SD_Init_Clk_MODE_MASK;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Init_Clk_ClearModeRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Clears flags that control the operating mode of the clock. This function\r
+* only changes flags from 1 to 0; flags that are already 0 will remain\r
+* unchanged. To set flags, use the SetModeRegister function. The clock must be\r
+* disabled before changing the mode.\r
+*\r
+* Parameters:\r
+* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,\r
+* clkMode should be a set of the following optional bits or'ed together.\r
+* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will\r
+* occur when the divider count reaches half of the divide\r
+* value.\r
+* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock\r
+* is asserted for approximately half of its period. When\r
+* disabled, the output clock is asserted for one period of the\r
+* source clock.\r
+* - CYCLK_SYNC Enable output synchronization to master clock. This should\r
+* be enabled for all synchronous clocks.\r
+* See the Technical Reference Manual for details about setting the mode of\r
+* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_Init_Clk_ClearModeRegister(uint8 modeBitMask) \r
+{\r
+ SD_Init_Clk_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SD_Init_Clk_MODE_MASK));\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Init_Clk_GetModeRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Gets the clock mode register value.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* Bit mask representing the enabled mode bits. See the SetModeRegister and\r
+* ClearModeRegister descriptions for details about the mode bits.\r
+*\r
+*******************************************************************************/\r
+uint8 SD_Init_Clk_GetModeRegister(void) \r
+{\r
+ return SD_Init_Clk_MOD_SRC & (uint8)(SD_Init_Clk_MODE_MASK);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Init_Clk_SetSourceRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the input source of the clock. The clock must be disabled before\r
+* changing the source. The old and new clock sources must be running.\r
+*\r
+* Parameters:\r
+* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the\r
+* following input sources:\r
+* - CYCLK_SRC_SEL_SYNC_DIG\r
+* - CYCLK_SRC_SEL_IMO\r
+* - CYCLK_SRC_SEL_XTALM\r
+* - CYCLK_SRC_SEL_ILO\r
+* - CYCLK_SRC_SEL_PLL\r
+* - CYCLK_SRC_SEL_XTALK\r
+* - CYCLK_SRC_SEL_DSI_G\r
+* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A\r
+* See the Technical Reference Manual for details on clock sources.\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_Init_Clk_SetSourceRegister(uint8 clkSource) \r
+{\r
+ uint16 currDiv = SD_Init_Clk_GetDividerRegister();\r
+ uint8 oldSrc = SD_Init_Clk_GetSourceRegister();\r
+\r
+ if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && \r
+ (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))\r
+ {\r
+ /* Switching to Master and divider is 1, set SSS, which will output master, */\r
+ /* then set the source so we are consistent. */\r
+ SD_Init_Clk_MOD_SRC |= CYCLK_SSS;\r
+ SD_Init_Clk_MOD_SRC =\r
+ (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource;\r
+ }\r
+ else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && \r
+ (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))\r
+ {\r
+ /* Switching from Master to not and divider is 1, set source, so we don't */\r
+ /* lock when we clear SSS. */\r
+ SD_Init_Clk_MOD_SRC =\r
+ (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource;\r
+ SD_Init_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS);\r
+ }\r
+ else\r
+ {\r
+ SD_Init_Clk_MOD_SRC =\r
+ (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource;\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Init_Clk_GetSourceRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Gets the input source of the clock.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* The input source of the clock. See SetSourceRegister for details.\r
+*\r
+*******************************************************************************/\r
+uint8 SD_Init_Clk_GetSourceRegister(void) \r
+{\r
+ return SD_Init_Clk_MOD_SRC & SD_Init_Clk_SRC_SEL_MSK;\r
+}\r
+\r
+\r
+#if defined(SD_Init_Clk__CFG3)\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Init_Clk_SetPhaseRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the phase delay of the analog clock. This function is only available\r
+* for analog clocks. The clock must be disabled before changing the phase\r
+* delay to avoid glitches.\r
+*\r
+* Parameters:\r
+* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.\r
+* clkPhase must be from 1 to 11 inclusive. Other values, including 0,\r
+* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 \r
+* produces a 10ns delay.\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_Init_Clk_SetPhaseRegister(uint8 clkPhase) \r
+{\r
+ SD_Init_Clk_PHASE = clkPhase & SD_Init_Clk_PHASE_MASK;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Init_Clk_GetPhase\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Gets the phase delay of the analog clock. This function is only available\r
+* for analog clocks.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* Phase of the analog clock. See SetPhaseRegister for details.\r
+*\r
+*******************************************************************************/\r
+uint8 SD_Init_Clk_GetPhaseRegister(void) \r
+{\r
+ return SD_Init_Clk_PHASE & SD_Init_Clk_PHASE_MASK;\r
+}\r
+\r
+#endif /* SD_Init_Clk__CFG3 */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_Init_Clk.h\r
+* Version 2.0\r
+*\r
+* Description:\r
+* Provides the function and constant definitions for the clock component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_CLOCK_SD_Init_Clk_H)\r
+#define CY_CLOCK_SD_Init_Clk_H\r
+\r
+#include <cytypes.h>\r
+#include <cyfitter.h>\r
+\r
+\r
+/***************************************\r
+* Conditional Compilation Parameters\r
+***************************************/\r
+\r
+/* Check to see if required defines such as CY_PSOC5LP are available */\r
+/* They are defined starting with cy_boot v3.0 */\r
+#if !defined (CY_PSOC5LP)\r
+ #error Component cy_clock_v2_0 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5LP) */\r
+\r
+\r
+/***************************************\r
+* Function Prototypes\r
+***************************************/\r
+\r
+void SD_Init_Clk_Start(void) ;\r
+void SD_Init_Clk_Stop(void) ;\r
+\r
+#if(CY_PSOC3 || CY_PSOC5LP)\r
+void SD_Init_Clk_StopBlock(void) ;\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+void SD_Init_Clk_StandbyPower(uint8 state) ;\r
+void SD_Init_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) \r
+ ;\r
+uint16 SD_Init_Clk_GetDividerRegister(void) ;\r
+void SD_Init_Clk_SetModeRegister(uint8 modeBitMask) ;\r
+void SD_Init_Clk_ClearModeRegister(uint8 modeBitMask) ;\r
+uint8 SD_Init_Clk_GetModeRegister(void) ;\r
+void SD_Init_Clk_SetSourceRegister(uint8 clkSource) ;\r
+uint8 SD_Init_Clk_GetSourceRegister(void) ;\r
+#if defined(SD_Init_Clk__CFG3)\r
+void SD_Init_Clk_SetPhaseRegister(uint8 clkPhase) ;\r
+uint8 SD_Init_Clk_GetPhaseRegister(void) ;\r
+#endif /* defined(SD_Init_Clk__CFG3) */\r
+\r
+#define SD_Init_Clk_Enable() SD_Init_Clk_Start()\r
+#define SD_Init_Clk_Disable() SD_Init_Clk_Stop()\r
+#define SD_Init_Clk_SetDivider(clkDivider) SD_Init_Clk_SetDividerRegister(clkDivider, 1)\r
+#define SD_Init_Clk_SetDividerValue(clkDivider) SD_Init_Clk_SetDividerRegister((clkDivider) - 1, 1)\r
+#define SD_Init_Clk_SetMode(clkMode) SD_Init_Clk_SetModeRegister(clkMode)\r
+#define SD_Init_Clk_SetSource(clkSource) SD_Init_Clk_SetSourceRegister(clkSource)\r
+#if defined(SD_Init_Clk__CFG3)\r
+#define SD_Init_Clk_SetPhase(clkPhase) SD_Init_Clk_SetPhaseRegister(clkPhase)\r
+#define SD_Init_Clk_SetPhaseValue(clkPhase) SD_Init_Clk_SetPhaseRegister((clkPhase) + 1)\r
+#endif /* defined(SD_Init_Clk__CFG3) */\r
+\r
+\r
+/***************************************\r
+* Registers\r
+***************************************/\r
+\r
+/* Register to enable or disable the clock */\r
+#define SD_Init_Clk_CLKEN (* (reg8 *) SD_Init_Clk__PM_ACT_CFG)\r
+#define SD_Init_Clk_CLKEN_PTR ((reg8 *) SD_Init_Clk__PM_ACT_CFG)\r
+\r
+/* Register to enable or disable the clock */\r
+#define SD_Init_Clk_CLKSTBY (* (reg8 *) SD_Init_Clk__PM_STBY_CFG)\r
+#define SD_Init_Clk_CLKSTBY_PTR ((reg8 *) SD_Init_Clk__PM_STBY_CFG)\r
+\r
+/* Clock LSB divider configuration register. */\r
+#define SD_Init_Clk_DIV_LSB (* (reg8 *) SD_Init_Clk__CFG0)\r
+#define SD_Init_Clk_DIV_LSB_PTR ((reg8 *) SD_Init_Clk__CFG0)\r
+#define SD_Init_Clk_DIV_PTR ((reg16 *) SD_Init_Clk__CFG0)\r
+\r
+/* Clock MSB divider configuration register. */\r
+#define SD_Init_Clk_DIV_MSB (* (reg8 *) SD_Init_Clk__CFG1)\r
+#define SD_Init_Clk_DIV_MSB_PTR ((reg8 *) SD_Init_Clk__CFG1)\r
+\r
+/* Mode and source configuration register */\r
+#define SD_Init_Clk_MOD_SRC (* (reg8 *) SD_Init_Clk__CFG2)\r
+#define SD_Init_Clk_MOD_SRC_PTR ((reg8 *) SD_Init_Clk__CFG2)\r
+\r
+#if defined(SD_Init_Clk__CFG3)\r
+/* Analog clock phase configuration register */\r
+#define SD_Init_Clk_PHASE (* (reg8 *) SD_Init_Clk__CFG3)\r
+#define SD_Init_Clk_PHASE_PTR ((reg8 *) SD_Init_Clk__CFG3)\r
+#endif /* defined(SD_Init_Clk__CFG3) */\r
+\r
+\r
+/**************************************\r
+* Register Constants\r
+**************************************/\r
+\r
+/* Power manager register masks */\r
+#define SD_Init_Clk_CLKEN_MASK SD_Init_Clk__PM_ACT_MSK\r
+#define SD_Init_Clk_CLKSTBY_MASK SD_Init_Clk__PM_STBY_MSK\r
+\r
+/* CFG2 field masks */\r
+#define SD_Init_Clk_SRC_SEL_MSK SD_Init_Clk__CFG2_SRC_SEL_MASK\r
+#define SD_Init_Clk_MODE_MASK (~(SD_Init_Clk_SRC_SEL_MSK))\r
+\r
+#if defined(SD_Init_Clk__CFG3)\r
+/* CFG3 phase mask */\r
+#define SD_Init_Clk_PHASE_MASK SD_Init_Clk__CFG3_PHASE_DLY_MASK\r
+#endif /* defined(SD_Init_Clk__CFG3) */\r
+\r
+#endif /* CY_CLOCK_SD_Init_Clk_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_IntClock.c\r
+* Version 2.0\r
+*\r
+* Description:\r
+* This file provides the source code to the API for the clock component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include <cydevice_trm.h>\r
+#include "SD_IntClock.h"\r
+\r
+/* Clock Distribution registers. */\r
+#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD)\r
+#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2)\r
+#define BCFG2_MASK (0x80u)\r
+#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK)\r
+#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK)\r
+\r
+#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP)\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_IntClock_Start\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Starts the clock. Note that on startup, clocks may be already running if the\r
+* "Start on Reset" option is enabled in the DWR.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_IntClock_Start(void) \r
+{\r
+ /* Set the bit to enable the clock. */\r
+ SD_IntClock_CLKEN |= SD_IntClock_CLKEN_MASK;\r
+ SD_IntClock_CLKSTBY |= SD_IntClock_CLKSTBY_MASK;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_IntClock_Stop\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Stops the clock and returns immediately. This API does not require the\r
+* source clock to be running but may return before the hardware is actually\r
+* disabled. If the settings of the clock are changed after calling this\r
+* function, the clock may glitch when it is started. To avoid the clock\r
+* glitch, use the StopBlock function.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_IntClock_Stop(void) \r
+{\r
+ /* Clear the bit to disable the clock. */\r
+ SD_IntClock_CLKEN &= (uint8)(~SD_IntClock_CLKEN_MASK);\r
+ SD_IntClock_CLKSTBY &= (uint8)(~SD_IntClock_CLKSTBY_MASK);\r
+}\r
+\r
+\r
+#if(CY_PSOC3 || CY_PSOC5LP)\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_IntClock_StopBlock\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Stops the clock and waits for the hardware to actually be disabled before\r
+* returning. This ensures that the clock is never truncated (high part of the\r
+* cycle will terminate before the clock is disabled and the API returns).\r
+* Note that the source clock must be running or this API will never return as\r
+* a stopped clock cannot be disabled.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_IntClock_StopBlock(void) \r
+{\r
+ if ((SD_IntClock_CLKEN & SD_IntClock_CLKEN_MASK) != 0u)\r
+ {\r
+#if HAS_CLKDIST_LD_DISABLE\r
+ uint16 oldDivider;\r
+\r
+ CLK_DIST_LD = 0u;\r
+\r
+ /* Clear all the mask bits except ours. */\r
+#if defined(SD_IntClock__CFG3)\r
+ CLK_DIST_AMASK = SD_IntClock_CLKEN_MASK;\r
+ CLK_DIST_DMASK = 0x00u;\r
+#else\r
+ CLK_DIST_DMASK = SD_IntClock_CLKEN_MASK;\r
+ CLK_DIST_AMASK = 0x00u;\r
+#endif /* SD_IntClock__CFG3 */\r
+\r
+ /* Clear mask of bus clock. */\r
+ CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);\r
+\r
+ oldDivider = CY_GET_REG16(SD_IntClock_DIV_PTR);\r
+ CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);\r
+ CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;\r
+\r
+ /* Wait for clock to be disabled */\r
+ while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
+#endif /* HAS_CLKDIST_LD_DISABLE */\r
+\r
+ /* Clear the bit to disable the clock. */\r
+ SD_IntClock_CLKEN &= (uint8)(~SD_IntClock_CLKEN_MASK);\r
+ SD_IntClock_CLKSTBY &= (uint8)(~SD_IntClock_CLKSTBY_MASK);\r
+\r
+#if HAS_CLKDIST_LD_DISABLE\r
+ /* Clear the disable bit */\r
+ CLK_DIST_LD = 0x00u;\r
+ CY_SET_REG16(SD_IntClock_DIV_PTR, oldDivider);\r
+#endif /* HAS_CLKDIST_LD_DISABLE */\r
+ }\r
+}\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_IntClock_StandbyPower\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets whether the clock is active in standby mode.\r
+*\r
+* Parameters:\r
+* state: 0 to disable clock during standby, nonzero to enable.\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_IntClock_StandbyPower(uint8 state) \r
+{\r
+ if(state == 0u)\r
+ {\r
+ SD_IntClock_CLKSTBY &= (uint8)(~SD_IntClock_CLKSTBY_MASK);\r
+ }\r
+ else\r
+ {\r
+ SD_IntClock_CLKSTBY |= SD_IntClock_CLKSTBY_MASK;\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_IntClock_SetDividerRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Modifies the clock divider and, thus, the frequency. When the clock divider\r
+* register is set to zero or changed from zero, the clock will be temporarily\r
+* disabled in order to change the SSS mode bit. If the clock is enabled when\r
+* SetDividerRegister is called, then the source clock must be running.\r
+*\r
+* Parameters:\r
+* clkDivider: Divider register value (0-65,535). This value is NOT the\r
+* divider; the clock hardware divides by clkDivider plus one. For example,\r
+* to divide the clock by 2, this parameter should be set to 1.\r
+* restart: If nonzero, restarts the clock divider: the current clock cycle\r
+* will be truncated and the new divide value will take effect immediately. If\r
+* zero, the new divide value will take effect at the end of the current clock\r
+* cycle.\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_IntClock_SetDividerRegister(uint16 clkDivider, uint8 restart)\r
+ \r
+{\r
+ uint8 enabled;\r
+\r
+ uint8 currSrc = SD_IntClock_GetSourceRegister();\r
+ uint16 oldDivider = SD_IntClock_GetDividerRegister();\r
+\r
+ if (clkDivider != oldDivider)\r
+ {\r
+ enabled = SD_IntClock_CLKEN & SD_IntClock_CLKEN_MASK;\r
+\r
+ if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))\r
+ {\r
+ /* Moving to/from SSS requires correct ordering to prevent halting the clock */\r
+ if (oldDivider == 0u)\r
+ {\r
+ /* Moving away from SSS, set the divider first so when SSS is cleared we */\r
+ /* don't halt the clock. Using the shadow load isn't required as the */\r
+ /* divider is ignored while SSS is set. */\r
+ CY_SET_REG16(SD_IntClock_DIV_PTR, clkDivider);\r
+ SD_IntClock_MOD_SRC &= (uint8)(~CYCLK_SSS);\r
+ }\r
+ else\r
+ {\r
+ /* Moving to SSS, set SSS which then ignores the divider and we can set */\r
+ /* it without bothering with the shadow load. */\r
+ SD_IntClock_MOD_SRC |= CYCLK_SSS;\r
+ CY_SET_REG16(SD_IntClock_DIV_PTR, clkDivider);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ \r
+ if (enabled != 0u)\r
+ {\r
+ CLK_DIST_LD = 0x00u;\r
+\r
+ /* Clear all the mask bits except ours. */\r
+#if defined(SD_IntClock__CFG3)\r
+ CLK_DIST_AMASK = SD_IntClock_CLKEN_MASK;\r
+ CLK_DIST_DMASK = 0x00u;\r
+#else\r
+ CLK_DIST_DMASK = SD_IntClock_CLKEN_MASK;\r
+ CLK_DIST_AMASK = 0x00u;\r
+#endif /* SD_IntClock__CFG3 */\r
+ /* Clear mask of bus clock. */\r
+ CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);\r
+\r
+ /* If clock is currently enabled, disable it if async or going from N-to-1*/\r
+ if (((SD_IntClock_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))\r
+ {\r
+#if HAS_CLKDIST_LD_DISABLE\r
+ CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);\r
+ CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;\r
+\r
+ /* Wait for clock to be disabled */\r
+ while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
+#endif /* HAS_CLKDIST_LD_DISABLE */\r
+\r
+ SD_IntClock_CLKEN &= (uint8)(~SD_IntClock_CLKEN_MASK);\r
+\r
+#if HAS_CLKDIST_LD_DISABLE\r
+ /* Clear the disable bit */\r
+ CLK_DIST_LD = 0x00u;\r
+#endif /* HAS_CLKDIST_LD_DISABLE */\r
+ }\r
+ }\r
+\r
+ /* Load divide value. */\r
+ if ((SD_IntClock_CLKEN & SD_IntClock_CLKEN_MASK) != 0u)\r
+ {\r
+ /* If the clock is still enabled, use the shadow registers */\r
+ CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);\r
+\r
+ CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));\r
+ while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }\r
+ }\r
+ else\r
+ {\r
+ /* If the clock is disabled, set the divider directly */\r
+ CY_SET_REG16(SD_IntClock_DIV_PTR, clkDivider);\r
+ SD_IntClock_CLKEN |= enabled;\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_IntClock_GetDividerRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Gets the clock divider register value.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* Divide value of the clock minus 1. For example, if the clock is set to\r
+* divide by 2, the return value will be 1.\r
+*\r
+*******************************************************************************/\r
+uint16 SD_IntClock_GetDividerRegister(void) \r
+{\r
+ return CY_GET_REG16(SD_IntClock_DIV_PTR);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_IntClock_SetModeRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets flags that control the operating mode of the clock. This function only\r
+* changes flags from 0 to 1; flags that are already 1 will remain unchanged.\r
+* To clear flags, use the ClearModeRegister function. The clock must be\r
+* disabled before changing the mode.\r
+*\r
+* Parameters:\r
+* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,\r
+* clkMode should be a set of the following optional bits or'ed together.\r
+* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will\r
+* occur when the divider count reaches half of the divide\r
+* value.\r
+* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock\r
+* is asserted for approximately half of its period. When\r
+* disabled, the output clock is asserted for one period of the\r
+* source clock.\r
+* - CYCLK_SYNC Enable output synchronization to master clock. This should\r
+* be enabled for all synchronous clocks.\r
+* See the Technical Reference Manual for details about setting the mode of\r
+* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_IntClock_SetModeRegister(uint8 modeBitMask) \r
+{\r
+ SD_IntClock_MOD_SRC |= modeBitMask & (uint8)SD_IntClock_MODE_MASK;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_IntClock_ClearModeRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Clears flags that control the operating mode of the clock. This function\r
+* only changes flags from 1 to 0; flags that are already 0 will remain\r
+* unchanged. To set flags, use the SetModeRegister function. The clock must be\r
+* disabled before changing the mode.\r
+*\r
+* Parameters:\r
+* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,\r
+* clkMode should be a set of the following optional bits or'ed together.\r
+* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will\r
+* occur when the divider count reaches half of the divide\r
+* value.\r
+* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock\r
+* is asserted for approximately half of its period. When\r
+* disabled, the output clock is asserted for one period of the\r
+* source clock.\r
+* - CYCLK_SYNC Enable output synchronization to master clock. This should\r
+* be enabled for all synchronous clocks.\r
+* See the Technical Reference Manual for details about setting the mode of\r
+* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_IntClock_ClearModeRegister(uint8 modeBitMask) \r
+{\r
+ SD_IntClock_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SD_IntClock_MODE_MASK));\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_IntClock_GetModeRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Gets the clock mode register value.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* Bit mask representing the enabled mode bits. See the SetModeRegister and\r
+* ClearModeRegister descriptions for details about the mode bits.\r
+*\r
+*******************************************************************************/\r
+uint8 SD_IntClock_GetModeRegister(void) \r
+{\r
+ return SD_IntClock_MOD_SRC & (uint8)(SD_IntClock_MODE_MASK);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_IntClock_SetSourceRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the input source of the clock. The clock must be disabled before\r
+* changing the source. The old and new clock sources must be running.\r
+*\r
+* Parameters:\r
+* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the\r
+* following input sources:\r
+* - CYCLK_SRC_SEL_SYNC_DIG\r
+* - CYCLK_SRC_SEL_IMO\r
+* - CYCLK_SRC_SEL_XTALM\r
+* - CYCLK_SRC_SEL_ILO\r
+* - CYCLK_SRC_SEL_PLL\r
+* - CYCLK_SRC_SEL_XTALK\r
+* - CYCLK_SRC_SEL_DSI_G\r
+* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A\r
+* See the Technical Reference Manual for details on clock sources.\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_IntClock_SetSourceRegister(uint8 clkSource) \r
+{\r
+ uint16 currDiv = SD_IntClock_GetDividerRegister();\r
+ uint8 oldSrc = SD_IntClock_GetSourceRegister();\r
+\r
+ if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && \r
+ (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))\r
+ {\r
+ /* Switching to Master and divider is 1, set SSS, which will output master, */\r
+ /* then set the source so we are consistent. */\r
+ SD_IntClock_MOD_SRC |= CYCLK_SSS;\r
+ SD_IntClock_MOD_SRC =\r
+ (SD_IntClock_MOD_SRC & (uint8)(~SD_IntClock_SRC_SEL_MSK)) | clkSource;\r
+ }\r
+ else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && \r
+ (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))\r
+ {\r
+ /* Switching from Master to not and divider is 1, set source, so we don't */\r
+ /* lock when we clear SSS. */\r
+ SD_IntClock_MOD_SRC =\r
+ (SD_IntClock_MOD_SRC & (uint8)(~SD_IntClock_SRC_SEL_MSK)) | clkSource;\r
+ SD_IntClock_MOD_SRC &= (uint8)(~CYCLK_SSS);\r
+ }\r
+ else\r
+ {\r
+ SD_IntClock_MOD_SRC =\r
+ (SD_IntClock_MOD_SRC & (uint8)(~SD_IntClock_SRC_SEL_MSK)) | clkSource;\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_IntClock_GetSourceRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Gets the input source of the clock.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* The input source of the clock. See SetSourceRegister for details.\r
+*\r
+*******************************************************************************/\r
+uint8 SD_IntClock_GetSourceRegister(void) \r
+{\r
+ return SD_IntClock_MOD_SRC & SD_IntClock_SRC_SEL_MSK;\r
+}\r
+\r
+\r
+#if defined(SD_IntClock__CFG3)\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_IntClock_SetPhaseRegister\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the phase delay of the analog clock. This function is only available\r
+* for analog clocks. The clock must be disabled before changing the phase\r
+* delay to avoid glitches.\r
+*\r
+* Parameters:\r
+* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.\r
+* clkPhase must be from 1 to 11 inclusive. Other values, including 0,\r
+* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 \r
+* produces a 10ns delay.\r
+*\r
+* Returns:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_IntClock_SetPhaseRegister(uint8 clkPhase) \r
+{\r
+ SD_IntClock_PHASE = clkPhase & SD_IntClock_PHASE_MASK;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_IntClock_GetPhase\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Gets the phase delay of the analog clock. This function is only available\r
+* for analog clocks.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Returns:\r
+* Phase of the analog clock. See SetPhaseRegister for details.\r
+*\r
+*******************************************************************************/\r
+uint8 SD_IntClock_GetPhaseRegister(void) \r
+{\r
+ return SD_IntClock_PHASE & SD_IntClock_PHASE_MASK;\r
+}\r
+\r
+#endif /* SD_IntClock__CFG3 */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_IntClock.h\r
+* Version 2.0\r
+*\r
+* Description:\r
+* Provides the function and constant definitions for the clock component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_CLOCK_SD_IntClock_H)\r
+#define CY_CLOCK_SD_IntClock_H\r
+\r
+#include <cytypes.h>\r
+#include <cyfitter.h>\r
+\r
+\r
+/***************************************\r
+* Conditional Compilation Parameters\r
+***************************************/\r
+\r
+/* Check to see if required defines such as CY_PSOC5LP are available */\r
+/* They are defined starting with cy_boot v3.0 */\r
+#if !defined (CY_PSOC5LP)\r
+ #error Component cy_clock_v2_0 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5LP) */\r
+\r
+\r
+/***************************************\r
+* Function Prototypes\r
+***************************************/\r
+\r
+void SD_IntClock_Start(void) ;\r
+void SD_IntClock_Stop(void) ;\r
+\r
+#if(CY_PSOC3 || CY_PSOC5LP)\r
+void SD_IntClock_StopBlock(void) ;\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+void SD_IntClock_StandbyPower(uint8 state) ;\r
+void SD_IntClock_SetDividerRegister(uint16 clkDivider, uint8 restart) \r
+ ;\r
+uint16 SD_IntClock_GetDividerRegister(void) ;\r
+void SD_IntClock_SetModeRegister(uint8 modeBitMask) ;\r
+void SD_IntClock_ClearModeRegister(uint8 modeBitMask) ;\r
+uint8 SD_IntClock_GetModeRegister(void) ;\r
+void SD_IntClock_SetSourceRegister(uint8 clkSource) ;\r
+uint8 SD_IntClock_GetSourceRegister(void) ;\r
+#if defined(SD_IntClock__CFG3)\r
+void SD_IntClock_SetPhaseRegister(uint8 clkPhase) ;\r
+uint8 SD_IntClock_GetPhaseRegister(void) ;\r
+#endif /* defined(SD_IntClock__CFG3) */\r
+\r
+#define SD_IntClock_Enable() SD_IntClock_Start()\r
+#define SD_IntClock_Disable() SD_IntClock_Stop()\r
+#define SD_IntClock_SetDivider(clkDivider) SD_IntClock_SetDividerRegister(clkDivider, 1)\r
+#define SD_IntClock_SetDividerValue(clkDivider) SD_IntClock_SetDividerRegister((clkDivider) - 1, 1)\r
+#define SD_IntClock_SetMode(clkMode) SD_IntClock_SetModeRegister(clkMode)\r
+#define SD_IntClock_SetSource(clkSource) SD_IntClock_SetSourceRegister(clkSource)\r
+#if defined(SD_IntClock__CFG3)\r
+#define SD_IntClock_SetPhase(clkPhase) SD_IntClock_SetPhaseRegister(clkPhase)\r
+#define SD_IntClock_SetPhaseValue(clkPhase) SD_IntClock_SetPhaseRegister((clkPhase) + 1)\r
+#endif /* defined(SD_IntClock__CFG3) */\r
+\r
+\r
+/***************************************\r
+* Registers\r
+***************************************/\r
+\r
+/* Register to enable or disable the clock */\r
+#define SD_IntClock_CLKEN (* (reg8 *) SD_IntClock__PM_ACT_CFG)\r
+#define SD_IntClock_CLKEN_PTR ((reg8 *) SD_IntClock__PM_ACT_CFG)\r
+\r
+/* Register to enable or disable the clock */\r
+#define SD_IntClock_CLKSTBY (* (reg8 *) SD_IntClock__PM_STBY_CFG)\r
+#define SD_IntClock_CLKSTBY_PTR ((reg8 *) SD_IntClock__PM_STBY_CFG)\r
+\r
+/* Clock LSB divider configuration register. */\r
+#define SD_IntClock_DIV_LSB (* (reg8 *) SD_IntClock__CFG0)\r
+#define SD_IntClock_DIV_LSB_PTR ((reg8 *) SD_IntClock__CFG0)\r
+#define SD_IntClock_DIV_PTR ((reg16 *) SD_IntClock__CFG0)\r
+\r
+/* Clock MSB divider configuration register. */\r
+#define SD_IntClock_DIV_MSB (* (reg8 *) SD_IntClock__CFG1)\r
+#define SD_IntClock_DIV_MSB_PTR ((reg8 *) SD_IntClock__CFG1)\r
+\r
+/* Mode and source configuration register */\r
+#define SD_IntClock_MOD_SRC (* (reg8 *) SD_IntClock__CFG2)\r
+#define SD_IntClock_MOD_SRC_PTR ((reg8 *) SD_IntClock__CFG2)\r
+\r
+#if defined(SD_IntClock__CFG3)\r
+/* Analog clock phase configuration register */\r
+#define SD_IntClock_PHASE (* (reg8 *) SD_IntClock__CFG3)\r
+#define SD_IntClock_PHASE_PTR ((reg8 *) SD_IntClock__CFG3)\r
+#endif /* defined(SD_IntClock__CFG3) */\r
+\r
+\r
+/**************************************\r
+* Register Constants\r
+**************************************/\r
+\r
+/* Power manager register masks */\r
+#define SD_IntClock_CLKEN_MASK SD_IntClock__PM_ACT_MSK\r
+#define SD_IntClock_CLKSTBY_MASK SD_IntClock__PM_STBY_MSK\r
+\r
+/* CFG2 field masks */\r
+#define SD_IntClock_SRC_SEL_MSK SD_IntClock__CFG2_SRC_SEL_MASK\r
+#define SD_IntClock_MODE_MASK (~(SD_IntClock_SRC_SEL_MSK))\r
+\r
+#if defined(SD_IntClock__CFG3)\r
+/* CFG3 phase mask */\r
+#define SD_IntClock_PHASE_MASK SD_IntClock__CFG3_PHASE_DLY_MASK\r
+#endif /* defined(SD_IntClock__CFG3) */\r
+\r
+#endif /* CY_CLOCK_SD_IntClock_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_MISO.c \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file contains API to enable firmware control of a Pins component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "cytypes.h"\r
+#include "SD_MISO.h"\r
+\r
+/* APIs are not generated for P15[7:6] on PSoC 5 */\r
+#if !(CY_PSOC5A &&\\r
+ SD_MISO__PORT == 15 && ((SD_MISO__MASK & 0xC0) != 0))\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_MISO_Write\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Assign a new value to the digital port's data output register. \r
+*\r
+* Parameters: \r
+* prtValue: The value to be assigned to the Digital Port. \r
+*\r
+* Return: \r
+* None\r
+* \r
+*******************************************************************************/\r
+void SD_MISO_Write(uint8 value) \r
+{\r
+ uint8 staticBits = (SD_MISO_DR & (uint8)(~SD_MISO_MASK));\r
+ SD_MISO_DR = staticBits | ((uint8)(value << SD_MISO_SHIFT) & SD_MISO_MASK);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_MISO_SetDriveMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Change the drive mode on the pins of the port.\r
+* \r
+* Parameters: \r
+* mode: Change the pins to this drive mode.\r
+*\r
+* Return: \r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_MISO_SetDriveMode(uint8 mode) \r
+{\r
+ CyPins_SetPinDriveMode(SD_MISO_0, mode);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_MISO_Read\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value on the pins of the Digital Port in right justified \r
+* form.\r
+*\r
+* Parameters: \r
+* None\r
+*\r
+* Return: \r
+* Returns the current value of the Digital Port as a right justified number\r
+* \r
+* Note:\r
+* Macro SD_MISO_ReadPS calls this function. \r
+* \r
+*******************************************************************************/\r
+uint8 SD_MISO_Read(void) \r
+{\r
+ return (SD_MISO_PS & SD_MISO_MASK) >> SD_MISO_SHIFT;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_MISO_ReadDataReg\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value assigned to a Digital Port's data output register\r
+*\r
+* Parameters: \r
+* None \r
+*\r
+* Return: \r
+* Returns the current value assigned to the Digital Port's data output register\r
+* \r
+*******************************************************************************/\r
+uint8 SD_MISO_ReadDataReg(void) \r
+{\r
+ return (SD_MISO_DR & SD_MISO_MASK) >> SD_MISO_SHIFT;\r
+}\r
+\r
+\r
+/* If Interrupts Are Enabled for this Pins component */ \r
+#if defined(SD_MISO_INTSTAT) \r
+\r
+ /*******************************************************************************\r
+ * Function Name: SD_MISO_ClearInterrupt\r
+ ********************************************************************************\r
+ * Summary:\r
+ * Clears any active interrupts attached to port and returns the value of the \r
+ * interrupt status register.\r
+ *\r
+ * Parameters: \r
+ * None \r
+ *\r
+ * Return: \r
+ * Returns the value of the interrupt status register\r
+ * \r
+ *******************************************************************************/\r
+ uint8 SD_MISO_ClearInterrupt(void) \r
+ {\r
+ return (SD_MISO_INTSTAT & SD_MISO_MASK) >> SD_MISO_SHIFT;\r
+ }\r
+\r
+#endif /* If Interrupts Are Enabled for this Pins component */ \r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+ \r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_MISO.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SD_MISO_H) /* Pins SD_MISO_H */\r
+#define CY_PINS_SD_MISO_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+#include "cypins.h"\r
+#include "SD_MISO_aliases.h"\r
+\r
+/* Check to see if required defines such as CY_PSOC5A are available */\r
+/* They are defined starting with cy_boot v3.0 */\r
+#if !defined (CY_PSOC5A)\r
+ #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5A) */\r
+\r
+/* APIs are not generated for P15[7:6] */\r
+#if !(CY_PSOC5A &&\\r
+ SD_MISO__PORT == 15 && ((SD_MISO__MASK & 0xC0) != 0))\r
+\r
+\r
+/***************************************\r
+* Function Prototypes \r
+***************************************/ \r
+\r
+void SD_MISO_Write(uint8 value) ;\r
+void SD_MISO_SetDriveMode(uint8 mode) ;\r
+uint8 SD_MISO_ReadDataReg(void) ;\r
+uint8 SD_MISO_Read(void) ;\r
+uint8 SD_MISO_ClearInterrupt(void) ;\r
+\r
+\r
+/***************************************\r
+* API Constants \r
+***************************************/\r
+\r
+/* Drive Modes */\r
+#define SD_MISO_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+#define SD_MISO_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+#define SD_MISO_DM_RES_UP PIN_DM_RES_UP\r
+#define SD_MISO_DM_RES_DWN PIN_DM_RES_DWN\r
+#define SD_MISO_DM_OD_LO PIN_DM_OD_LO\r
+#define SD_MISO_DM_OD_HI PIN_DM_OD_HI\r
+#define SD_MISO_DM_STRONG PIN_DM_STRONG\r
+#define SD_MISO_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+\r
+/* Digital Port Constants */\r
+#define SD_MISO_MASK SD_MISO__MASK\r
+#define SD_MISO_SHIFT SD_MISO__SHIFT\r
+#define SD_MISO_WIDTH 1u\r
+\r
+\r
+/***************************************\r
+* Registers \r
+***************************************/\r
+\r
+/* Main Port Registers */\r
+/* Pin State */\r
+#define SD_MISO_PS (* (reg8 *) SD_MISO__PS)\r
+/* Data Register */\r
+#define SD_MISO_DR (* (reg8 *) SD_MISO__DR)\r
+/* Port Number */\r
+#define SD_MISO_PRT_NUM (* (reg8 *) SD_MISO__PRT) \r
+/* Connect to Analog Globals */ \r
+#define SD_MISO_AG (* (reg8 *) SD_MISO__AG) \r
+/* Analog MUX bux enable */\r
+#define SD_MISO_AMUX (* (reg8 *) SD_MISO__AMUX) \r
+/* Bidirectional Enable */ \r
+#define SD_MISO_BIE (* (reg8 *) SD_MISO__BIE)\r
+/* Bit-mask for Aliased Register Access */\r
+#define SD_MISO_BIT_MASK (* (reg8 *) SD_MISO__BIT_MASK)\r
+/* Bypass Enable */\r
+#define SD_MISO_BYP (* (reg8 *) SD_MISO__BYP)\r
+/* Port wide control signals */ \r
+#define SD_MISO_CTL (* (reg8 *) SD_MISO__CTL)\r
+/* Drive Modes */\r
+#define SD_MISO_DM0 (* (reg8 *) SD_MISO__DM0) \r
+#define SD_MISO_DM1 (* (reg8 *) SD_MISO__DM1)\r
+#define SD_MISO_DM2 (* (reg8 *) SD_MISO__DM2) \r
+/* Input Buffer Disable Override */\r
+#define SD_MISO_INP_DIS (* (reg8 *) SD_MISO__INP_DIS)\r
+/* LCD Common or Segment Drive */\r
+#define SD_MISO_LCD_COM_SEG (* (reg8 *) SD_MISO__LCD_COM_SEG)\r
+/* Enable Segment LCD */\r
+#define SD_MISO_LCD_EN (* (reg8 *) SD_MISO__LCD_EN)\r
+/* Slew Rate Control */\r
+#define SD_MISO_SLW (* (reg8 *) SD_MISO__SLW)\r
+\r
+/* DSI Port Registers */\r
+/* Global DSI Select Register */\r
+#define SD_MISO_PRTDSI__CAPS_SEL (* (reg8 *) SD_MISO__PRTDSI__CAPS_SEL) \r
+/* Double Sync Enable */\r
+#define SD_MISO_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_MISO__PRTDSI__DBL_SYNC_IN) \r
+/* Output Enable Select Drive Strength */\r
+#define SD_MISO_PRTDSI__OE_SEL0 (* (reg8 *) SD_MISO__PRTDSI__OE_SEL0) \r
+#define SD_MISO_PRTDSI__OE_SEL1 (* (reg8 *) SD_MISO__PRTDSI__OE_SEL1) \r
+/* Port Pin Output Select Registers */\r
+#define SD_MISO_PRTDSI__OUT_SEL0 (* (reg8 *) SD_MISO__PRTDSI__OUT_SEL0) \r
+#define SD_MISO_PRTDSI__OUT_SEL1 (* (reg8 *) SD_MISO__PRTDSI__OUT_SEL1) \r
+/* Sync Output Enable Registers */\r
+#define SD_MISO_PRTDSI__SYNC_OUT (* (reg8 *) SD_MISO__PRTDSI__SYNC_OUT) \r
+\r
+\r
+#if defined(SD_MISO__INTSTAT) /* Interrupt Registers */\r
+\r
+ #define SD_MISO_INTSTAT (* (reg8 *) SD_MISO__INTSTAT)\r
+ #define SD_MISO_SNAP (* (reg8 *) SD_MISO__SNAP)\r
+\r
+#endif /* Interrupt Registers */\r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+#endif /* CY_PINS_SD_MISO_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_MISO.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SD_MISO_ALIASES_H) /* Pins SD_MISO_ALIASES_H */\r
+#define CY_PINS_SD_MISO_ALIASES_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+\r
+\r
+/***************************************\r
+* Constants \r
+***************************************/\r
+#define SD_MISO_0 SD_MISO__0__PC\r
+\r
+#endif /* End Pins SD_MISO_ALIASES_H */\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_MOSI.c \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file contains API to enable firmware control of a Pins component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "cytypes.h"\r
+#include "SD_MOSI.h"\r
+\r
+/* APIs are not generated for P15[7:6] on PSoC 5 */\r
+#if !(CY_PSOC5A &&\\r
+ SD_MOSI__PORT == 15 && ((SD_MOSI__MASK & 0xC0) != 0))\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_MOSI_Write\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Assign a new value to the digital port's data output register. \r
+*\r
+* Parameters: \r
+* prtValue: The value to be assigned to the Digital Port. \r
+*\r
+* Return: \r
+* None\r
+* \r
+*******************************************************************************/\r
+void SD_MOSI_Write(uint8 value) \r
+{\r
+ uint8 staticBits = (SD_MOSI_DR & (uint8)(~SD_MOSI_MASK));\r
+ SD_MOSI_DR = staticBits | ((uint8)(value << SD_MOSI_SHIFT) & SD_MOSI_MASK);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_MOSI_SetDriveMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Change the drive mode on the pins of the port.\r
+* \r
+* Parameters: \r
+* mode: Change the pins to this drive mode.\r
+*\r
+* Return: \r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_MOSI_SetDriveMode(uint8 mode) \r
+{\r
+ CyPins_SetPinDriveMode(SD_MOSI_0, mode);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_MOSI_Read\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value on the pins of the Digital Port in right justified \r
+* form.\r
+*\r
+* Parameters: \r
+* None\r
+*\r
+* Return: \r
+* Returns the current value of the Digital Port as a right justified number\r
+* \r
+* Note:\r
+* Macro SD_MOSI_ReadPS calls this function. \r
+* \r
+*******************************************************************************/\r
+uint8 SD_MOSI_Read(void) \r
+{\r
+ return (SD_MOSI_PS & SD_MOSI_MASK) >> SD_MOSI_SHIFT;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_MOSI_ReadDataReg\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value assigned to a Digital Port's data output register\r
+*\r
+* Parameters: \r
+* None \r
+*\r
+* Return: \r
+* Returns the current value assigned to the Digital Port's data output register\r
+* \r
+*******************************************************************************/\r
+uint8 SD_MOSI_ReadDataReg(void) \r
+{\r
+ return (SD_MOSI_DR & SD_MOSI_MASK) >> SD_MOSI_SHIFT;\r
+}\r
+\r
+\r
+/* If Interrupts Are Enabled for this Pins component */ \r
+#if defined(SD_MOSI_INTSTAT) \r
+\r
+ /*******************************************************************************\r
+ * Function Name: SD_MOSI_ClearInterrupt\r
+ ********************************************************************************\r
+ * Summary:\r
+ * Clears any active interrupts attached to port and returns the value of the \r
+ * interrupt status register.\r
+ *\r
+ * Parameters: \r
+ * None \r
+ *\r
+ * Return: \r
+ * Returns the value of the interrupt status register\r
+ * \r
+ *******************************************************************************/\r
+ uint8 SD_MOSI_ClearInterrupt(void) \r
+ {\r
+ return (SD_MOSI_INTSTAT & SD_MOSI_MASK) >> SD_MOSI_SHIFT;\r
+ }\r
+\r
+#endif /* If Interrupts Are Enabled for this Pins component */ \r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+ \r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_MOSI.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SD_MOSI_H) /* Pins SD_MOSI_H */\r
+#define CY_PINS_SD_MOSI_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+#include "cypins.h"\r
+#include "SD_MOSI_aliases.h"\r
+\r
+/* Check to see if required defines such as CY_PSOC5A are available */\r
+/* They are defined starting with cy_boot v3.0 */\r
+#if !defined (CY_PSOC5A)\r
+ #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5A) */\r
+\r
+/* APIs are not generated for P15[7:6] */\r
+#if !(CY_PSOC5A &&\\r
+ SD_MOSI__PORT == 15 && ((SD_MOSI__MASK & 0xC0) != 0))\r
+\r
+\r
+/***************************************\r
+* Function Prototypes \r
+***************************************/ \r
+\r
+void SD_MOSI_Write(uint8 value) ;\r
+void SD_MOSI_SetDriveMode(uint8 mode) ;\r
+uint8 SD_MOSI_ReadDataReg(void) ;\r
+uint8 SD_MOSI_Read(void) ;\r
+uint8 SD_MOSI_ClearInterrupt(void) ;\r
+\r
+\r
+/***************************************\r
+* API Constants \r
+***************************************/\r
+\r
+/* Drive Modes */\r
+#define SD_MOSI_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+#define SD_MOSI_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+#define SD_MOSI_DM_RES_UP PIN_DM_RES_UP\r
+#define SD_MOSI_DM_RES_DWN PIN_DM_RES_DWN\r
+#define SD_MOSI_DM_OD_LO PIN_DM_OD_LO\r
+#define SD_MOSI_DM_OD_HI PIN_DM_OD_HI\r
+#define SD_MOSI_DM_STRONG PIN_DM_STRONG\r
+#define SD_MOSI_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+\r
+/* Digital Port Constants */\r
+#define SD_MOSI_MASK SD_MOSI__MASK\r
+#define SD_MOSI_SHIFT SD_MOSI__SHIFT\r
+#define SD_MOSI_WIDTH 1u\r
+\r
+\r
+/***************************************\r
+* Registers \r
+***************************************/\r
+\r
+/* Main Port Registers */\r
+/* Pin State */\r
+#define SD_MOSI_PS (* (reg8 *) SD_MOSI__PS)\r
+/* Data Register */\r
+#define SD_MOSI_DR (* (reg8 *) SD_MOSI__DR)\r
+/* Port Number */\r
+#define SD_MOSI_PRT_NUM (* (reg8 *) SD_MOSI__PRT) \r
+/* Connect to Analog Globals */ \r
+#define SD_MOSI_AG (* (reg8 *) SD_MOSI__AG) \r
+/* Analog MUX bux enable */\r
+#define SD_MOSI_AMUX (* (reg8 *) SD_MOSI__AMUX) \r
+/* Bidirectional Enable */ \r
+#define SD_MOSI_BIE (* (reg8 *) SD_MOSI__BIE)\r
+/* Bit-mask for Aliased Register Access */\r
+#define SD_MOSI_BIT_MASK (* (reg8 *) SD_MOSI__BIT_MASK)\r
+/* Bypass Enable */\r
+#define SD_MOSI_BYP (* (reg8 *) SD_MOSI__BYP)\r
+/* Port wide control signals */ \r
+#define SD_MOSI_CTL (* (reg8 *) SD_MOSI__CTL)\r
+/* Drive Modes */\r
+#define SD_MOSI_DM0 (* (reg8 *) SD_MOSI__DM0) \r
+#define SD_MOSI_DM1 (* (reg8 *) SD_MOSI__DM1)\r
+#define SD_MOSI_DM2 (* (reg8 *) SD_MOSI__DM2) \r
+/* Input Buffer Disable Override */\r
+#define SD_MOSI_INP_DIS (* (reg8 *) SD_MOSI__INP_DIS)\r
+/* LCD Common or Segment Drive */\r
+#define SD_MOSI_LCD_COM_SEG (* (reg8 *) SD_MOSI__LCD_COM_SEG)\r
+/* Enable Segment LCD */\r
+#define SD_MOSI_LCD_EN (* (reg8 *) SD_MOSI__LCD_EN)\r
+/* Slew Rate Control */\r
+#define SD_MOSI_SLW (* (reg8 *) SD_MOSI__SLW)\r
+\r
+/* DSI Port Registers */\r
+/* Global DSI Select Register */\r
+#define SD_MOSI_PRTDSI__CAPS_SEL (* (reg8 *) SD_MOSI__PRTDSI__CAPS_SEL) \r
+/* Double Sync Enable */\r
+#define SD_MOSI_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_MOSI__PRTDSI__DBL_SYNC_IN) \r
+/* Output Enable Select Drive Strength */\r
+#define SD_MOSI_PRTDSI__OE_SEL0 (* (reg8 *) SD_MOSI__PRTDSI__OE_SEL0) \r
+#define SD_MOSI_PRTDSI__OE_SEL1 (* (reg8 *) SD_MOSI__PRTDSI__OE_SEL1) \r
+/* Port Pin Output Select Registers */\r
+#define SD_MOSI_PRTDSI__OUT_SEL0 (* (reg8 *) SD_MOSI__PRTDSI__OUT_SEL0) \r
+#define SD_MOSI_PRTDSI__OUT_SEL1 (* (reg8 *) SD_MOSI__PRTDSI__OUT_SEL1) \r
+/* Sync Output Enable Registers */\r
+#define SD_MOSI_PRTDSI__SYNC_OUT (* (reg8 *) SD_MOSI__PRTDSI__SYNC_OUT) \r
+\r
+\r
+#if defined(SD_MOSI__INTSTAT) /* Interrupt Registers */\r
+\r
+ #define SD_MOSI_INTSTAT (* (reg8 *) SD_MOSI__INTSTAT)\r
+ #define SD_MOSI_SNAP (* (reg8 *) SD_MOSI__SNAP)\r
+\r
+#endif /* Interrupt Registers */\r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+#endif /* CY_PINS_SD_MOSI_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_MOSI.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SD_MOSI_ALIASES_H) /* Pins SD_MOSI_ALIASES_H */\r
+#define CY_PINS_SD_MOSI_ALIASES_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+\r
+\r
+/***************************************\r
+* Constants \r
+***************************************/\r
+#define SD_MOSI_0 SD_MOSI__0__PC\r
+\r
+#endif /* End Pins SD_MOSI_ALIASES_H */\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_PM.c\r
+* Version 2.40\r
+*\r
+* Description:\r
+* This file contains the setup, control and status commands to support\r
+* component operations in low power mode.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "SD_PVT.h"\r
+\r
+static SD_BACKUP_STRUCT SD_backup =\r
+{\r
+ SD_DISABLED,\r
+ SD_BITCTR_INIT,\r
+ #if(CY_UDB_V0)\r
+ SD_TX_INIT_INTERRUPTS_MASK,\r
+ SD_RX_INIT_INTERRUPTS_MASK\r
+ #endif /* CY_UDB_V0 */\r
+};\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_SaveConfig\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Saves SPIM configuration.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global Variables:\r
+* SD_backup - modified when non-retention registers are saved.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void SD_SaveConfig(void) \r
+{\r
+ /* Store Status Mask registers */\r
+ #if(CY_UDB_V0)\r
+ SD_backup.cntrPeriod = SD_COUNTER_PERIOD_REG;\r
+ SD_backup.saveSrTxIntMask = SD_TX_STATUS_MASK_REG;\r
+ SD_backup.saveSrRxIntMask = SD_RX_STATUS_MASK_REG;\r
+ #endif /* (CY_UDB_V0) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_RestoreConfig\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Restores SPIM configuration.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global Variables:\r
+* SD_backup - used when non-retention registers are restored.\r
+*\r
+* Side Effects:\r
+* If this API is called without first calling SaveConfig then in the following\r
+* registers will be default values from Customizer:\r
+* SD_STATUS_MASK_REG and SD_COUNTER_PERIOD_REG.\r
+*\r
+*******************************************************************************/\r
+void SD_RestoreConfig(void) \r
+{\r
+ /* Restore the data, saved by SaveConfig() function */\r
+ #if(CY_UDB_V0)\r
+ SD_COUNTER_PERIOD_REG = SD_backup.cntrPeriod;\r
+ SD_TX_STATUS_MASK_REG = ((uint8) SD_backup.saveSrTxIntMask);\r
+ SD_RX_STATUS_MASK_REG = ((uint8) SD_backup.saveSrRxIntMask);\r
+ #endif /* (CY_UDB_V0) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Sleep\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Prepare SPIM Component goes to sleep.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global Variables:\r
+* SD_backup - modified when non-retention registers are saved.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void SD_Sleep(void) \r
+{\r
+ /* Save components enable state */\r
+ SD_backup.enableState = ((uint8) SD_IS_ENABLED);\r
+\r
+ SD_Stop();\r
+ SD_SaveConfig();\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_Wakeup\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Prepare SPIM Component to wake up.\r
+*\r
+* Parameters:\r
+* None.\r
+*\r
+* Return:\r
+* None.\r
+*\r
+* Global Variables:\r
+* SD_backup - used when non-retention registers are restored.\r
+* SD_txBufferWrite - modified every function call - resets to\r
+* zero.\r
+* SD_txBufferRead - modified every function call - resets to\r
+* zero.\r
+* SD_rxBufferWrite - modified every function call - resets to\r
+* zero.\r
+* SD_rxBufferRead - modified every function call - resets to\r
+* zero.\r
+*\r
+* Reentrant:\r
+* No.\r
+*\r
+*******************************************************************************/\r
+void SD_Wakeup(void) \r
+{\r
+ SD_RestoreConfig();\r
+\r
+ #if(SD_RX_SOFTWARE_BUF_ENABLED)\r
+ SD_rxBufferFull = 0u;\r
+ SD_rxBufferRead = 0u;\r
+ SD_rxBufferWrite = 0u;\r
+ #endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ #if(SD_TX_SOFTWARE_BUF_ENABLED)\r
+ SD_txBufferFull = 0u;\r
+ SD_txBufferRead = 0u;\r
+ SD_txBufferWrite = 0u;\r
+ #endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
+\r
+ /* Clear any data from the RX and TX FIFO */\r
+ SD_ClearFIFO();\r
+\r
+ /* Restore components block enable state */\r
+ if(0u != SD_backup.enableState)\r
+ {\r
+ SD_Enable();\r
+ }\r
+}\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: .h\r
+* Version 2.40\r
+*\r
+* Description:\r
+* This private header file contains internal definitions for the SPIM\r
+* component. Do not use these definitions directly in your application.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_SPIM_PVT_SD_H)\r
+#define CY_SPIM_PVT_SD_H\r
+\r
+#include "SD.h"\r
+\r
+\r
+/**********************************\r
+* Functions with external linkage\r
+**********************************/\r
+\r
+\r
+/**********************************\r
+* Variables with external linkage\r
+**********************************/\r
+\r
+extern volatile uint8 SD_swStatusTx;\r
+extern volatile uint8 SD_swStatusRx;\r
+\r
+#if(SD_TX_SOFTWARE_BUF_ENABLED)\r
+ extern volatile uint8 SD_txBuffer[SD_TX_BUFFER_SIZE];\r
+ extern volatile uint8 SD_txBufferRead;\r
+ extern volatile uint8 SD_txBufferWrite;\r
+ extern volatile uint8 SD_txBufferFull;\r
+#endif /* (SD_TX_SOFTWARE_BUF_ENABLED) */\r
+\r
+#if(SD_RX_SOFTWARE_BUF_ENABLED)\r
+ extern volatile uint8 SD_rxBuffer[SD_RX_BUFFER_SIZE];\r
+ extern volatile uint8 SD_rxBufferRead;\r
+ extern volatile uint8 SD_rxBufferWrite;\r
+ extern volatile uint8 SD_rxBufferFull;\r
+#endif /* (SD_RX_SOFTWARE_BUF_ENABLED) */\r
+\r
+#endif /* CY_SPIM_PVT_SD_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_SCK.c \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file contains API to enable firmware control of a Pins component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "cytypes.h"\r
+#include "SD_SCK.h"\r
+\r
+/* APIs are not generated for P15[7:6] on PSoC 5 */\r
+#if !(CY_PSOC5A &&\\r
+ SD_SCK__PORT == 15 && ((SD_SCK__MASK & 0xC0) != 0))\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_SCK_Write\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Assign a new value to the digital port's data output register. \r
+*\r
+* Parameters: \r
+* prtValue: The value to be assigned to the Digital Port. \r
+*\r
+* Return: \r
+* None\r
+* \r
+*******************************************************************************/\r
+void SD_SCK_Write(uint8 value) \r
+{\r
+ uint8 staticBits = (SD_SCK_DR & (uint8)(~SD_SCK_MASK));\r
+ SD_SCK_DR = staticBits | ((uint8)(value << SD_SCK_SHIFT) & SD_SCK_MASK);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_SCK_SetDriveMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Change the drive mode on the pins of the port.\r
+* \r
+* Parameters: \r
+* mode: Change the pins to this drive mode.\r
+*\r
+* Return: \r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_SCK_SetDriveMode(uint8 mode) \r
+{\r
+ CyPins_SetPinDriveMode(SD_SCK_0, mode);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_SCK_Read\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value on the pins of the Digital Port in right justified \r
+* form.\r
+*\r
+* Parameters: \r
+* None\r
+*\r
+* Return: \r
+* Returns the current value of the Digital Port as a right justified number\r
+* \r
+* Note:\r
+* Macro SD_SCK_ReadPS calls this function. \r
+* \r
+*******************************************************************************/\r
+uint8 SD_SCK_Read(void) \r
+{\r
+ return (SD_SCK_PS & SD_SCK_MASK) >> SD_SCK_SHIFT;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_SCK_ReadDataReg\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value assigned to a Digital Port's data output register\r
+*\r
+* Parameters: \r
+* None \r
+*\r
+* Return: \r
+* Returns the current value assigned to the Digital Port's data output register\r
+* \r
+*******************************************************************************/\r
+uint8 SD_SCK_ReadDataReg(void) \r
+{\r
+ return (SD_SCK_DR & SD_SCK_MASK) >> SD_SCK_SHIFT;\r
+}\r
+\r
+\r
+/* If Interrupts Are Enabled for this Pins component */ \r
+#if defined(SD_SCK_INTSTAT) \r
+\r
+ /*******************************************************************************\r
+ * Function Name: SD_SCK_ClearInterrupt\r
+ ********************************************************************************\r
+ * Summary:\r
+ * Clears any active interrupts attached to port and returns the value of the \r
+ * interrupt status register.\r
+ *\r
+ * Parameters: \r
+ * None \r
+ *\r
+ * Return: \r
+ * Returns the value of the interrupt status register\r
+ * \r
+ *******************************************************************************/\r
+ uint8 SD_SCK_ClearInterrupt(void) \r
+ {\r
+ return (SD_SCK_INTSTAT & SD_SCK_MASK) >> SD_SCK_SHIFT;\r
+ }\r
+\r
+#endif /* If Interrupts Are Enabled for this Pins component */ \r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+ \r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_SCK.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SD_SCK_H) /* Pins SD_SCK_H */\r
+#define CY_PINS_SD_SCK_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+#include "cypins.h"\r
+#include "SD_SCK_aliases.h"\r
+\r
+/* Check to see if required defines such as CY_PSOC5A are available */\r
+/* They are defined starting with cy_boot v3.0 */\r
+#if !defined (CY_PSOC5A)\r
+ #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5A) */\r
+\r
+/* APIs are not generated for P15[7:6] */\r
+#if !(CY_PSOC5A &&\\r
+ SD_SCK__PORT == 15 && ((SD_SCK__MASK & 0xC0) != 0))\r
+\r
+\r
+/***************************************\r
+* Function Prototypes \r
+***************************************/ \r
+\r
+void SD_SCK_Write(uint8 value) ;\r
+void SD_SCK_SetDriveMode(uint8 mode) ;\r
+uint8 SD_SCK_ReadDataReg(void) ;\r
+uint8 SD_SCK_Read(void) ;\r
+uint8 SD_SCK_ClearInterrupt(void) ;\r
+\r
+\r
+/***************************************\r
+* API Constants \r
+***************************************/\r
+\r
+/* Drive Modes */\r
+#define SD_SCK_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+#define SD_SCK_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+#define SD_SCK_DM_RES_UP PIN_DM_RES_UP\r
+#define SD_SCK_DM_RES_DWN PIN_DM_RES_DWN\r
+#define SD_SCK_DM_OD_LO PIN_DM_OD_LO\r
+#define SD_SCK_DM_OD_HI PIN_DM_OD_HI\r
+#define SD_SCK_DM_STRONG PIN_DM_STRONG\r
+#define SD_SCK_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+\r
+/* Digital Port Constants */\r
+#define SD_SCK_MASK SD_SCK__MASK\r
+#define SD_SCK_SHIFT SD_SCK__SHIFT\r
+#define SD_SCK_WIDTH 1u\r
+\r
+\r
+/***************************************\r
+* Registers \r
+***************************************/\r
+\r
+/* Main Port Registers */\r
+/* Pin State */\r
+#define SD_SCK_PS (* (reg8 *) SD_SCK__PS)\r
+/* Data Register */\r
+#define SD_SCK_DR (* (reg8 *) SD_SCK__DR)\r
+/* Port Number */\r
+#define SD_SCK_PRT_NUM (* (reg8 *) SD_SCK__PRT) \r
+/* Connect to Analog Globals */ \r
+#define SD_SCK_AG (* (reg8 *) SD_SCK__AG) \r
+/* Analog MUX bux enable */\r
+#define SD_SCK_AMUX (* (reg8 *) SD_SCK__AMUX) \r
+/* Bidirectional Enable */ \r
+#define SD_SCK_BIE (* (reg8 *) SD_SCK__BIE)\r
+/* Bit-mask for Aliased Register Access */\r
+#define SD_SCK_BIT_MASK (* (reg8 *) SD_SCK__BIT_MASK)\r
+/* Bypass Enable */\r
+#define SD_SCK_BYP (* (reg8 *) SD_SCK__BYP)\r
+/* Port wide control signals */ \r
+#define SD_SCK_CTL (* (reg8 *) SD_SCK__CTL)\r
+/* Drive Modes */\r
+#define SD_SCK_DM0 (* (reg8 *) SD_SCK__DM0) \r
+#define SD_SCK_DM1 (* (reg8 *) SD_SCK__DM1)\r
+#define SD_SCK_DM2 (* (reg8 *) SD_SCK__DM2) \r
+/* Input Buffer Disable Override */\r
+#define SD_SCK_INP_DIS (* (reg8 *) SD_SCK__INP_DIS)\r
+/* LCD Common or Segment Drive */\r
+#define SD_SCK_LCD_COM_SEG (* (reg8 *) SD_SCK__LCD_COM_SEG)\r
+/* Enable Segment LCD */\r
+#define SD_SCK_LCD_EN (* (reg8 *) SD_SCK__LCD_EN)\r
+/* Slew Rate Control */\r
+#define SD_SCK_SLW (* (reg8 *) SD_SCK__SLW)\r
+\r
+/* DSI Port Registers */\r
+/* Global DSI Select Register */\r
+#define SD_SCK_PRTDSI__CAPS_SEL (* (reg8 *) SD_SCK__PRTDSI__CAPS_SEL) \r
+/* Double Sync Enable */\r
+#define SD_SCK_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_SCK__PRTDSI__DBL_SYNC_IN) \r
+/* Output Enable Select Drive Strength */\r
+#define SD_SCK_PRTDSI__OE_SEL0 (* (reg8 *) SD_SCK__PRTDSI__OE_SEL0) \r
+#define SD_SCK_PRTDSI__OE_SEL1 (* (reg8 *) SD_SCK__PRTDSI__OE_SEL1) \r
+/* Port Pin Output Select Registers */\r
+#define SD_SCK_PRTDSI__OUT_SEL0 (* (reg8 *) SD_SCK__PRTDSI__OUT_SEL0) \r
+#define SD_SCK_PRTDSI__OUT_SEL1 (* (reg8 *) SD_SCK__PRTDSI__OUT_SEL1) \r
+/* Sync Output Enable Registers */\r
+#define SD_SCK_PRTDSI__SYNC_OUT (* (reg8 *) SD_SCK__PRTDSI__SYNC_OUT) \r
+\r
+\r
+#if defined(SD_SCK__INTSTAT) /* Interrupt Registers */\r
+\r
+ #define SD_SCK_INTSTAT (* (reg8 *) SD_SCK__INTSTAT)\r
+ #define SD_SCK_SNAP (* (reg8 *) SD_SCK__SNAP)\r
+\r
+#endif /* Interrupt Registers */\r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+#endif /* CY_PINS_SD_SCK_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_SCK.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SD_SCK_ALIASES_H) /* Pins SD_SCK_ALIASES_H */\r
+#define CY_PINS_SD_SCK_ALIASES_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+\r
+\r
+/***************************************\r
+* Constants \r
+***************************************/\r
+#define SD_SCK_0 SD_SCK__0__PC\r
+\r
+#endif /* End Pins SD_SCK_ALIASES_H */\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_WP.c \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file contains API to enable firmware control of a Pins component.\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "cytypes.h"\r
+#include "SD_WP.h"\r
+\r
+/* APIs are not generated for P15[7:6] on PSoC 5 */\r
+#if !(CY_PSOC5A &&\\r
+ SD_WP__PORT == 15 && ((SD_WP__MASK & 0xC0) != 0))\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_WP_Write\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Assign a new value to the digital port's data output register. \r
+*\r
+* Parameters: \r
+* prtValue: The value to be assigned to the Digital Port. \r
+*\r
+* Return: \r
+* None\r
+* \r
+*******************************************************************************/\r
+void SD_WP_Write(uint8 value) \r
+{\r
+ uint8 staticBits = (SD_WP_DR & (uint8)(~SD_WP_MASK));\r
+ SD_WP_DR = staticBits | ((uint8)(value << SD_WP_SHIFT) & SD_WP_MASK);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_WP_SetDriveMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Change the drive mode on the pins of the port.\r
+* \r
+* Parameters: \r
+* mode: Change the pins to this drive mode.\r
+*\r
+* Return: \r
+* None\r
+*\r
+*******************************************************************************/\r
+void SD_WP_SetDriveMode(uint8 mode) \r
+{\r
+ CyPins_SetPinDriveMode(SD_WP_0, mode);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_WP_Read\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value on the pins of the Digital Port in right justified \r
+* form.\r
+*\r
+* Parameters: \r
+* None\r
+*\r
+* Return: \r
+* Returns the current value of the Digital Port as a right justified number\r
+* \r
+* Note:\r
+* Macro SD_WP_ReadPS calls this function. \r
+* \r
+*******************************************************************************/\r
+uint8 SD_WP_Read(void) \r
+{\r
+ return (SD_WP_PS & SD_WP_MASK) >> SD_WP_SHIFT;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SD_WP_ReadDataReg\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Read the current value assigned to a Digital Port's data output register\r
+*\r
+* Parameters: \r
+* None \r
+*\r
+* Return: \r
+* Returns the current value assigned to the Digital Port's data output register\r
+* \r
+*******************************************************************************/\r
+uint8 SD_WP_ReadDataReg(void) \r
+{\r
+ return (SD_WP_DR & SD_WP_MASK) >> SD_WP_SHIFT;\r
+}\r
+\r
+\r
+/* If Interrupts Are Enabled for this Pins component */ \r
+#if defined(SD_WP_INTSTAT) \r
+\r
+ /*******************************************************************************\r
+ * Function Name: SD_WP_ClearInterrupt\r
+ ********************************************************************************\r
+ * Summary:\r
+ * Clears any active interrupts attached to port and returns the value of the \r
+ * interrupt status register.\r
+ *\r
+ * Parameters: \r
+ * None \r
+ *\r
+ * Return: \r
+ * Returns the value of the interrupt status register\r
+ * \r
+ *******************************************************************************/\r
+ uint8 SD_WP_ClearInterrupt(void) \r
+ {\r
+ return (SD_WP_INTSTAT & SD_WP_MASK) >> SD_WP_SHIFT;\r
+ }\r
+\r
+#endif /* If Interrupts Are Enabled for this Pins component */ \r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+ \r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_WP.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SD_WP_H) /* Pins SD_WP_H */\r
+#define CY_PINS_SD_WP_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+#include "cypins.h"\r
+#include "SD_WP_aliases.h"\r
+\r
+/* Check to see if required defines such as CY_PSOC5A are available */\r
+/* They are defined starting with cy_boot v3.0 */\r
+#if !defined (CY_PSOC5A)\r
+ #error Component cy_pins_v1_90 requires cy_boot v3.0 or later\r
+#endif /* (CY_PSOC5A) */\r
+\r
+/* APIs are not generated for P15[7:6] */\r
+#if !(CY_PSOC5A &&\\r
+ SD_WP__PORT == 15 && ((SD_WP__MASK & 0xC0) != 0))\r
+\r
+\r
+/***************************************\r
+* Function Prototypes \r
+***************************************/ \r
+\r
+void SD_WP_Write(uint8 value) ;\r
+void SD_WP_SetDriveMode(uint8 mode) ;\r
+uint8 SD_WP_ReadDataReg(void) ;\r
+uint8 SD_WP_Read(void) ;\r
+uint8 SD_WP_ClearInterrupt(void) ;\r
+\r
+\r
+/***************************************\r
+* API Constants \r
+***************************************/\r
+\r
+/* Drive Modes */\r
+#define SD_WP_DM_ALG_HIZ PIN_DM_ALG_HIZ\r
+#define SD_WP_DM_DIG_HIZ PIN_DM_DIG_HIZ\r
+#define SD_WP_DM_RES_UP PIN_DM_RES_UP\r
+#define SD_WP_DM_RES_DWN PIN_DM_RES_DWN\r
+#define SD_WP_DM_OD_LO PIN_DM_OD_LO\r
+#define SD_WP_DM_OD_HI PIN_DM_OD_HI\r
+#define SD_WP_DM_STRONG PIN_DM_STRONG\r
+#define SD_WP_DM_RES_UPDWN PIN_DM_RES_UPDWN\r
+\r
+/* Digital Port Constants */\r
+#define SD_WP_MASK SD_WP__MASK\r
+#define SD_WP_SHIFT SD_WP__SHIFT\r
+#define SD_WP_WIDTH 1u\r
+\r
+\r
+/***************************************\r
+* Registers \r
+***************************************/\r
+\r
+/* Main Port Registers */\r
+/* Pin State */\r
+#define SD_WP_PS (* (reg8 *) SD_WP__PS)\r
+/* Data Register */\r
+#define SD_WP_DR (* (reg8 *) SD_WP__DR)\r
+/* Port Number */\r
+#define SD_WP_PRT_NUM (* (reg8 *) SD_WP__PRT) \r
+/* Connect to Analog Globals */ \r
+#define SD_WP_AG (* (reg8 *) SD_WP__AG) \r
+/* Analog MUX bux enable */\r
+#define SD_WP_AMUX (* (reg8 *) SD_WP__AMUX) \r
+/* Bidirectional Enable */ \r
+#define SD_WP_BIE (* (reg8 *) SD_WP__BIE)\r
+/* Bit-mask for Aliased Register Access */\r
+#define SD_WP_BIT_MASK (* (reg8 *) SD_WP__BIT_MASK)\r
+/* Bypass Enable */\r
+#define SD_WP_BYP (* (reg8 *) SD_WP__BYP)\r
+/* Port wide control signals */ \r
+#define SD_WP_CTL (* (reg8 *) SD_WP__CTL)\r
+/* Drive Modes */\r
+#define SD_WP_DM0 (* (reg8 *) SD_WP__DM0) \r
+#define SD_WP_DM1 (* (reg8 *) SD_WP__DM1)\r
+#define SD_WP_DM2 (* (reg8 *) SD_WP__DM2) \r
+/* Input Buffer Disable Override */\r
+#define SD_WP_INP_DIS (* (reg8 *) SD_WP__INP_DIS)\r
+/* LCD Common or Segment Drive */\r
+#define SD_WP_LCD_COM_SEG (* (reg8 *) SD_WP__LCD_COM_SEG)\r
+/* Enable Segment LCD */\r
+#define SD_WP_LCD_EN (* (reg8 *) SD_WP__LCD_EN)\r
+/* Slew Rate Control */\r
+#define SD_WP_SLW (* (reg8 *) SD_WP__SLW)\r
+\r
+/* DSI Port Registers */\r
+/* Global DSI Select Register */\r
+#define SD_WP_PRTDSI__CAPS_SEL (* (reg8 *) SD_WP__PRTDSI__CAPS_SEL) \r
+/* Double Sync Enable */\r
+#define SD_WP_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_WP__PRTDSI__DBL_SYNC_IN) \r
+/* Output Enable Select Drive Strength */\r
+#define SD_WP_PRTDSI__OE_SEL0 (* (reg8 *) SD_WP__PRTDSI__OE_SEL0) \r
+#define SD_WP_PRTDSI__OE_SEL1 (* (reg8 *) SD_WP__PRTDSI__OE_SEL1) \r
+/* Port Pin Output Select Registers */\r
+#define SD_WP_PRTDSI__OUT_SEL0 (* (reg8 *) SD_WP__PRTDSI__OUT_SEL0) \r
+#define SD_WP_PRTDSI__OUT_SEL1 (* (reg8 *) SD_WP__PRTDSI__OUT_SEL1) \r
+/* Sync Output Enable Registers */\r
+#define SD_WP_PRTDSI__SYNC_OUT (* (reg8 *) SD_WP__PRTDSI__SYNC_OUT) \r
+\r
+\r
+#if defined(SD_WP__INTSTAT) /* Interrupt Registers */\r
+\r
+ #define SD_WP_INTSTAT (* (reg8 *) SD_WP__INTSTAT)\r
+ #define SD_WP_SNAP (* (reg8 *) SD_WP__SNAP)\r
+\r
+#endif /* Interrupt Registers */\r
+\r
+#endif /* CY_PSOC5A... */\r
+\r
+#endif /* CY_PINS_SD_WP_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: SD_WP.h \r
+* Version 1.90\r
+*\r
+* Description:\r
+* This file containts Control Register function prototypes and register defines\r
+*\r
+* Note:\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_PINS_SD_WP_ALIASES_H) /* Pins SD_WP_ALIASES_H */\r
+#define CY_PINS_SD_WP_ALIASES_H\r
+\r
+#include "cytypes.h"\r
+#include "cyfitter.h"\r
+\r
+\r
+\r
+/***************************************\r
+* Constants \r
+***************************************/\r
+#define SD_WP_0 SD_WP__0__PC\r
+\r
+#endif /* End Pins SD_WP_ALIASES_H */\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/* Linker script for ARM M-profile Simulator\r
+ *\r
+ * Version: Sourcery G++ Lite 2010q1-188\r
+ * Support: https://support.codesourcery.com/GNUToolchain/\r
+ *\r
+ * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc.\r
+ *\r
+ * The authors hereby grant permission to use, copy, modify, distribute,\r
+ * and license this software and its documentation for any purpose, provided\r
+ * that existing copyright notices are retained in all copies and that this\r
+ * notice is included verbatim in any distributions. No written agreement,\r
+ * license, or royalty fee is required for any of the authorized uses.\r
+ * Modifications to this software may be copyrighted by their authors\r
+ * and need not follow the licensing terms described here, provided that\r
+ * the new terms are clearly indicated on the first page of each file where\r
+ * they apply.\r
+ */\r
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")\r
+ENTRY(__cs3_reset)\r
+SEARCH_DIR(.)\r
+GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3micro)\r
+\r
+MEMORY\r
+{\r
+ rom (rx) : ORIGIN = 0, LENGTH = (262144 - 0)\r
+ ram (rwx) : ORIGIN = 0x20000000 - (65536 / 2), LENGTH = (65536 - 0x4000 - 0x1000)\r
+}\r
+\r
+/* These force the linker to search for particular symbols from\r
+ * the start of the link process and thus ensure the user's\r
+ * overrides are picked up\r
+ */\r
+EXTERN(__cs3_reset Reset)\r
+EXTERN(__cs3_start_asm __cs3_start_asm_generic_m)\r
+/* Bring in the interrupt routines & vector */\r
+INCLUDE micro-names.inc\r
+EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)\r
+\r
+/* Provide fall-back values */\r
+PROVIDE(__cs3_heap_start = _end);\r
+PROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) / 20);\r
+PROVIDE(__cs3_stack = 0x20000000 + (65536 / 2));\r
+PROVIDE(__cs3_heap_end = __cs3_stack - 0x4000);\r
+\r
+\r
+SECTIONS\r
+{\r
+\r
+ .text :\r
+ {\r
+ CREATE_OBJECT_SYMBOLS\r
+ PROVIDE(__cs3_interrupt_vector = RomVectors);\r
+ *(.romvectors)\r
+ *(.cs3.interrupt_vector)\r
+ /* Make sure we pulled in an interrupt vector. */\r
+ ASSERT (. != __cs3_interrupt_vector, "No interrupt vector");\r
+\r
+ PROVIDE(__cs3_reset = Reset);\r
+ *(.cs3.reset)\r
+ /* Make sure we pulled in some reset code. */\r
+ ASSERT (. != __cs3_reset, "No reset code");\r
+\r
+ /* Place the DMA initialization before text to ensure it gets placed in first 64K of flash */\r
+ *(.dma_init)\r
+ ASSERT(0 + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash");\r
+ \r
+ *(.text.cs3.init)\r
+ *(.text .text.* .gnu.linkonce.t.*)\r
+ *(.plt)\r
+ *(.gnu.warning)\r
+ *(.glue_7t) *(.glue_7) *(.vfp11_veneer)\r
+ \r
+ KEEP(*(.bootloader)) /* necessary for bootloader's, but doesn't impact non-bootloaders */\r
+\r
+ *(.ARM.extab* .gnu.linkonce.armextab.*)\r
+ *(.gcc_except_table)\r
+ } >rom\r
+ .eh_frame_hdr : ALIGN (4)\r
+ {\r
+ KEEP (*(.eh_frame_hdr))\r
+ } >rom\r
+ .eh_frame : ALIGN (4)\r
+ {\r
+ KEEP (*(.eh_frame))\r
+ } >rom\r
+ /* .ARM.exidx is sorted, so has to go in its own output section. */\r
+ PROVIDE_HIDDEN (__exidx_start = .);\r
+ .ARM.exidx :\r
+ {\r
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)\r
+ } >rom\r
+ __exidx_end = .;\r
+ .rodata : ALIGN (4)\r
+ {\r
+ *(.rodata .rodata.* .gnu.linkonce.r.*)\r
+\r
+ . = ALIGN(4);\r
+ KEEP(*(.init))\r
+\r
+ . = ALIGN(4);\r
+ __preinit_array_start = .;\r
+ KEEP (*(.preinit_array))\r
+ __preinit_array_end = .;\r
+\r
+ . = ALIGN(4);\r
+ __init_array_start = .;\r
+ KEEP (*(SORT(.init_array.*)))\r
+ KEEP (*(.init_array))\r
+ __init_array_end = .;\r
+\r
+ . = ALIGN(4);\r
+ KEEP(*(.fini))\r
+\r
+ . = ALIGN(4);\r
+ __fini_array_start = .;\r
+ KEEP (*(.fini_array))\r
+ KEEP (*(SORT(.fini_array.*)))\r
+ __fini_array_end = .;\r
+\r
+ . = ALIGN(0x4);\r
+ KEEP (*crtbegin.o(.ctors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))\r
+ KEEP (*(SORT(.ctors.*)))\r
+ KEEP (*crtend.o(.ctors))\r
+\r
+ . = ALIGN(0x4);\r
+ KEEP (*crtbegin.o(.dtors))\r
+ KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))\r
+ KEEP (*(SORT(.dtors.*)))\r
+ KEEP (*crtend.o(.dtors))\r
+\r
+ . = ALIGN(4);\r
+ __cs3_regions = .;\r
+ LONG (0)\r
+ LONG (__cs3_region_init_ram)\r
+ LONG (__cs3_region_start_data)\r
+ LONG (__cs3_region_init_size_ram)\r
+ LONG (__cs3_region_zero_size_ram)\r
+ __cs3_regions_end = .;\r
+\r
+ . = ALIGN (8);\r
+ _etext = .;\r
+ } >rom\r
+\r
+ .ramvectors (NOLOAD) : ALIGN(8)\r
+ {\r
+ __cs3_region_start_ram = .;\r
+ *(.cs3.region-head.ram)\r
+ ASSERT (. == __cs3_region_start_ram, ".cs3.region-head.ram not permitted");\r
+ KEEP(*(.ramvectors))\r
+ }\r
+\r
+ .noinit (NOLOAD) : ALIGN(8)\r
+ {\r
+ KEEP(*(.noinit))\r
+ }\r
+\r
+ .data : ALIGN(8)\r
+ {\r
+ __cs3_region_start_data = .;\r
+\r
+ KEEP(*(.jcr))\r
+ *(.got.plt) *(.got)\r
+ *(.shdata)\r
+ *(.data .data.* .gnu.linkonce.d.*)\r
+ . = ALIGN (8);\r
+ *(.ram)\r
+ _edata = .;\r
+ } >ram AT>rom\r
+ .bss : ALIGN(8)\r
+ {\r
+ *(.shbss)\r
+ *(.bss .bss.* .gnu.linkonce.b.*)\r
+ *(COMMON)\r
+ . = ALIGN (8);\r
+ *(.ram.b)\r
+ _end = .;\r
+ __end = .;\r
+ } >ram AT>rom\r
+ \r
+ __cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);\r
+ __cs3_region_size_ram = LENGTH(ram);\r
+ __cs3_region_init_ram = LOADADDR (.data);\r
+ __cs3_region_init_size_ram = _edata - ADDR (.data);\r
+ __cs3_region_zero_size_ram = _end - _edata;\r
+\r
+\r
+ .stab 0 (NOLOAD) : { *(.stab) }\r
+ .stabstr 0 (NOLOAD) : { *(.stabstr) }\r
+ /* DWARF debug sections.\r
+ * Symbols in the DWARF debugging sections are relative to the beginning\r
+ * of the section so we begin them at 0.\r
+ */\r
+ /* DWARF 1 */\r
+ .debug 0 : { *(.debug) }\r
+ .line 0 : { *(.line) }\r
+ /* GNU DWARF 1 extensions */\r
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }\r
+ .debug_sfnames 0 : { *(.debug_sfnames) }\r
+ /* DWARF 1.1 and DWARF 2 */\r
+ .debug_aranges 0 : { *(.debug_aranges) }\r
+ .debug_pubnames 0 : { *(.debug_pubnames) }\r
+ /* DWARF 2 */\r
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }\r
+ .debug_abbrev 0 : { *(.debug_abbrev) }\r
+ .debug_line 0 : { *(.debug_line) }\r
+ .debug_frame 0 : { *(.debug_frame) }\r
+ .debug_str 0 : { *(.debug_str) }\r
+ .debug_loc 0 : { *(.debug_loc) }\r
+ .debug_macinfo 0 : { *(.debug_macinfo) }\r
+ /* DWARF 2.1 */\r
+ .debug_ranges 0 : { *(.debug_ranges) }\r
+ /* SGI/MIPS DWARF 2 extensions */\r
+ .debug_weaknames 0 : { *(.debug_weaknames) }\r
+ .debug_funcnames 0 : { *(.debug_funcnames) }\r
+ .debug_typenames 0 : { *(.debug_typenames) }\r
+ .debug_varnames 0 : { *(.debug_varnames) }\r
+\r
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }\r
+ .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }\r
+ /DISCARD/ : { *(.note.GNU-stack) }\r
+}\r
+\r
--- /dev/null
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+:2002E00000D0FF067FD2800400D60000C0000100C0040400C002080000219F8E000F00F0DE\r
+:20030000000FFF01002200080000404063024000050EFDBC3DFFFFFF2200F008040000005B\r
+:2003200000000228040B0B0B909900010000C00040011011C00100114001400100000000CE\r
+:2003400000000000000000000000000000FFFF00000000000800300008000000000000005F\r
+:200360000000000010000000FF000000000000010200F10E0E000C000000000000FCFC005A\r
+:2003800000000000F0000FF00000000000010000F00F0F000000000100000000000000005E\r
+:00000001FF\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.c\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File\r
+ * @version V1.30\r
+ * @date 30. October 2009\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#include <stdint.h>\r
+\r
+/* define compiler specific symbols */\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+__ASM uint32_t __get_PSP(void)\r
+{\r
+ mrs r0, psp\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+__ASM void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ msr psp, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+__ASM uint32_t __get_MSP(void)\r
+{\r
+ mrs r0, msp\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+__ASM void __set_MSP(uint32_t mainStackPointer)\r
+{\r
+ msr msp, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+__ASM uint32_t __REV16(uint16_t value)\r
+{\r
+ rev16 r0, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+__ASM int32_t __REVSH(int16_t value)\r
+{\r
+ revsh r0, r0\r
+ bx lr\r
+}\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+__ASM void __CLREX(void)\r
+{\r
+ clrex\r
+}\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+__ASM uint32_t __get_BASEPRI(void)\r
+{\r
+ mrs r0, basepri\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+__ASM void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ msr basepri, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+__ASM uint32_t __get_PRIMASK(void)\r
+{\r
+ mrs r0, primask\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+__ASM void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ msr primask, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+__ASM uint32_t __get_FAULTMASK(void)\r
+{\r
+ mrs r0, faultmask\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+__ASM void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ msr faultmask, r0\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+__ASM uint32_t __get_CONTROL(void)\r
+{\r
+ mrs r0, control\r
+ bx lr\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+__ASM void __set_CONTROL(uint32_t control)\r
+{\r
+ msr control, r0\r
+ bx lr\r
+}\r
+\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+#pragma diag_suppress=Pe940\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+uint32_t __get_PSP(void)\r
+{\r
+ __ASM("mrs r0, psp");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM("msr psp, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+uint32_t __get_MSP(void)\r
+{\r
+ __ASM("mrs r0, msp");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM("msr msp, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+uint32_t __REV16(uint16_t value)\r
+{\r
+ __ASM("rev16 r0, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+uint32_t __RBIT(uint32_t value)\r
+{\r
+ __ASM("rbit r0, r0");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit values)\r
+ */\r
+uint8_t __LDREXB(uint8_t *addr)\r
+{\r
+ __ASM("ldrexb r0, [r0]");\r
+ __ASM("bx lr"); \r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+uint16_t __LDREXH(uint16_t *addr)\r
+{\r
+ __ASM("ldrexh r0, [r0]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+uint32_t __LDREXW(uint32_t *addr)\r
+{\r
+ __ASM("ldrex r0, [r0]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
+{\r
+ __ASM("strexb r0, r0, [r1]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
+{\r
+ __ASM("strexh r0, r0, [r1]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
+{\r
+ __ASM("strex r0, r0, [r1]");\r
+ __ASM("bx lr");\r
+}\r
+\r
+#pragma diag_default=Pe940\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+uint32_t __get_PSP(void) __attribute__( ( naked ) );\r
+uint32_t __get_PSP(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, psp\n\t" \r
+ "MOV r0, %0 \n\t"\r
+ "BX lr \n\t" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );\r
+void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n\t"\r
+ "BX lr \n\t" : : "r" (topOfProcStack) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+uint32_t __get_MSP(void) __attribute__( ( naked ) );\r
+uint32_t __get_MSP(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, msp\n\t" \r
+ "MOV r0, %0 \n\t"\r
+ "BX lr \n\t" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );\r
+void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n\t"\r
+ "BX lr \n\t" : : "r" (topOfMainStack) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+* \r
+* @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result=0;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) );\r
+}\r
+\r
+\r
+/**\r
+ * @brief Reverse byte order in integer value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+uint32_t __REV(uint32_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+uint32_t __REV16(uint16_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+int32_t __REVSH(int16_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit value\r
+ */\r
+uint8_t __LDREXB(uint8_t *addr)\r
+{\r
+ uint8_t result=0;\r
+ \r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+uint16_t __LDREXH(uint16_t *addr)\r
+{\r
+ uint16_t result=0;\r
+ \r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+uint32_t __LDREXW(uint32_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+uint32_t __STREXB(uint8_t value, uint8_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+uint32_t __STREXH(uint16_t value, uint16_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+uint32_t __STREXW(uint32_t value, uint32_t *addr)\r
+{\r
+ uint32_t result=0;\r
+ \r
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm3.h\r
+ * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File\r
+ * @version V1.30\r
+ * @date 30. October 2009\r
+ *\r
+ * @note\r
+ * Copyright (C) 2009 ARM Limited. All rights reserved.\r
+ *\r
+ * @par\r
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M \r
+ * processor based microcontrollers. This file can be freely distributed \r
+ * within development tools that are supporting such ARM based processors. \r
+ *\r
+ * @par\r
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED\r
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\r
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\r
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\r
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.\r
+ *\r
+ ******************************************************************************/\r
+\r
+#ifndef __CM3_CORE_H__\r
+#define __CM3_CORE_H__\r
+\r
+/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration\r
+ *\r
+ * List of Lint messages which will be suppressed and not shown:\r
+ * - Error 10: \n\r
+ * register uint32_t __regBasePri __asm("basepri"); \n\r
+ * Error 10: Expecting ';'\r
+ * .\r
+ * - Error 530: \n\r
+ * return(__regBasePri); \n\r
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized\r
+ * . \r
+ * - Error 550: \n\r
+ * __regBasePri = (basePri & 0x1ff); \n\r
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed\r
+ * .\r
+ * - Error 754: \n\r
+ * uint32_t RESERVED0[24]; \n\r
+ * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 750: \n\r
+ * #define __CM3_CORE_H__ \n\r
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 528: \n\r
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n\r
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced\r
+ * .\r
+ * - Error 751: \n\r
+ * } InterruptType_Type; \n\r
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced\r
+ * .\r
+ * Note: To re-enable a Message, insert a space before 'lint' *\r
+ *\r
+ */\r
+\r
+/*lint -save */\r
+/*lint -e10 */\r
+/*lint -e530 */\r
+/*lint -e550 */\r
+/*lint -e754 */\r
+/*lint -e750 */\r
+/*lint -e528 */\r
+/*lint -e751 */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions\r
+ This file defines all structures and symbols for CMSIS core:\r
+ - CMSIS version number\r
+ - Cortex-M core registers and bitfields\r
+ - Cortex-M core peripheral base address\r
+ @{\r
+ */\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x03) /*!< Cortex core */\r
+\r
+#include <stdint.h> /* Include standard types */\r
+\r
+#if defined (__ICCARM__)\r
+ #include <intrinsics.h> /* IAR Intrinsics */\r
+#endif\r
+\r
+\r
+#ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3 /*!< standard definition for NVIC Priority Bits */\r
+#endif\r
+\r
+\r
+\r
+\r
+/**\r
+ * IO definitions\r
+ *\r
+ * define access restrictions to peripheral registers\r
+ */\r
+\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< defines 'write only' permissions */\r
+#define __IO volatile /*!< defines 'read / write' permissions */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ ******************************************************************************/\r
+/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register\r
+ @{\r
+*/\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC\r
+ memory mapped structure for Nested Vectored Interrupt Controller (NVIC)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24]; \r
+ __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24]; \r
+ __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24]; \r
+ __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24]; \r
+ __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56]; \r
+ __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644]; \r
+ __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */\r
+} NVIC_Type; \r
+/*@}*/ /* end of group CMSIS_CM3_NVIC */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB\r
+ memory mapped structure for System Control Block (SCB)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */\r
+ __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */\r
+ __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */\r
+ __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */\r
+ __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */\r
+ __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */\r
+ __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */\r
+ __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */\r
+ __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */\r
+ __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */\r
+ __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */\r
+ __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */\r
+ __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */\r
+ __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */\r
+ __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */\r
+ __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */\r
+ __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */\r
+ __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */\r
+} SCB_Type; \r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */\r
+#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */\r
+\r
+#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+ \r
+#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Registers Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Registers Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SCB */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick\r
+ memory mapped structure for SysTick\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */\r
+ __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */\r
+ __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */\r
+ __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_SysTick */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM\r
+ memory mapped structure for Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __O union \r
+ {\r
+ __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */\r
+ __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */\r
+ __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */\r
+ } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864]; \r
+ __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15]; \r
+ __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15]; \r
+ __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */\r
+ uint32_t RESERVED3[29]; \r
+ __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */\r
+ __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */\r
+ __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43]; \r
+ __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */\r
+ __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */\r
+ uint32_t RESERVED5[6]; \r
+ __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */\r
+ __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */\r
+ __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */\r
+ __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */\r
+ __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */\r
+ __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */\r
+ __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */\r
+ __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */\r
+ __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */\r
+ __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */\r
+ __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */\r
+ __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */\r
+} ITM_Type; \r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_ITM */\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type\r
+ memory mapped structure for Interrupt Type\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0;\r
+ __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */\r
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))\r
+ __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */\r
+#else\r
+ uint32_t RESERVED1;\r
+#endif\r
+} InterruptType_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */\r
+#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */\r
+#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */\r
+\r
+#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */\r
+#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */\r
+\r
+#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */\r
+#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_InterruptType */\r
+\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU\r
+ memory mapped structure for Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */\r
+ __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */\r
+ __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */\r
+ __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */\r
+ __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */\r
+ __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */\r
+ __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */\r
+ __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */\r
+ __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type; \r
+\r
+/* MPU Type Register */\r
+#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register */\r
+#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register */\r
+#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register */\r
+#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */\r
+#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */\r
+#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */\r
+#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */\r
+#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */\r
+\r
+#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */\r
+#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */\r
+\r
+#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */\r
+#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_MPU */\r
+#endif\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug\r
+ memory mapped structure for Core Debug Register\r
+ @{\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */\r
+ __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */\r
+ __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */\r
+ __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+/*@}*/ /* end of group CMSIS_CM3_CoreDebug */\r
+\r
+\r
+/* Memory mapping of Cortex-M3 Hardware */\r
+#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000) /*!< ITM Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */\r
+\r
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */\r
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_register */\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ ******************************************************************************/\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+\r
+#endif\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+\r
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/\r
+/* ARM armcc specific functions */\r
+\r
+#define __enable_fault_irq __enable_fiq\r
+#define __disable_fault_irq __disable_fiq\r
+\r
+#define __NOP __nop\r
+#define __WFI __wfi\r
+#define __WFE __wfe\r
+#define __SEV __sev\r
+#define __ISB() __isb(0)\r
+#define __DSB() __dsb(0)\r
+#define __DMB() __dmb(0)\r
+#define __REV __rev\r
+#define __RBIT __rbit\r
+#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))\r
+#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))\r
+#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))\r
+#define __STREXB(value, ptr) __strex(value, ptr)\r
+#define __STREXH(value, ptr) __strex(value, ptr)\r
+#define __STREXW(value, ptr) __strex(value, ptr)\r
+\r
+\r
+/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */\r
+/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */\r
+/* intrinsic void __enable_irq(); */\r
+/* intrinsic void __disable_irq(); */\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+\r
+#if (__ARMCC_VERSION < 400000)\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+extern void __CLREX(void);\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+#else /* (__ARMCC_VERSION >= 400000) */\r
+\r
+/**\r
+ * @brief Remove the exclusive lock created by ldrex\r
+ *\r
+ * Removes the exclusive lock which is created by ldrex.\r
+ */\r
+#define __CLREX __clrex\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+static __INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ return(__regBasePri);\r
+}\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+static __INLINE void __set_BASEPRI(uint32_t basePri)\r
+{\r
+ register uint32_t __regBasePri __ASM("basepri");\r
+ __regBasePri = (basePri & 0xff);\r
+}\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+static __INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ return(__regPriMask);\r
+}\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+static __INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ register uint32_t __regPriMask __ASM("primask");\r
+ __regPriMask = (priMask);\r
+}\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+static __INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ return(__regFaultMask);\r
+}\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ register uint32_t __regFaultMask __ASM("faultmask");\r
+ __regFaultMask = (faultMask & 1);\r
+}\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+ * \r
+ * @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+static __INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ return(__regControl);\r
+}\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+static __INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ register uint32_t __regControl __ASM("control");\r
+ __regControl = control;\r
+}\r
+\r
+#endif /* __ARMCC_VERSION */ \r
+\r
+\r
+\r
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/\r
+/* IAR iccarm specific functions */\r
+\r
+#define __enable_irq __enable_interrupt /*!< global Interrupt enable */\r
+#define __disable_irq __disable_interrupt /*!< global Interrupt disable */\r
+\r
+static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }\r
+\r
+#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */ \r
+static __INLINE void __WFI() { __ASM ("wfi"); }\r
+static __INLINE void __WFE() { __ASM ("wfe"); }\r
+static __INLINE void __SEV() { __ASM ("sev"); }\r
+static __INLINE void __CLREX() { __ASM ("clrex"); }\r
+\r
+/* intrinsic void __ISB(void) */\r
+/* intrinsic void __DSB(void) */\r
+/* intrinsic void __DMB(void) */\r
+/* intrinsic void __set_PRIMASK(); */\r
+/* intrinsic void __get_PRIMASK(); */\r
+/* intrinsic void __set_FAULTMASK(); */\r
+/* intrinsic void __get_FAULTMASK(); */\r
+/* intrinsic uint32_t __REV(uint32_t value); */\r
+/* intrinsic uint32_t __REVSH(uint32_t value); */\r
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */\r
+/* intrinsic unsigned long __LDREX(unsigned long *); */\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit values)\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+\r
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/\r
+/* GNU gcc specific functions */\r
+\r
+static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }\r
+static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }\r
+\r
+static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }\r
+static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }\r
+\r
+static __INLINE void __NOP() { __ASM volatile ("nop"); }\r
+static __INLINE void __WFI() { __ASM volatile ("wfi"); }\r
+static __INLINE void __WFE() { __ASM volatile ("wfe"); }\r
+static __INLINE void __SEV() { __ASM volatile ("sev"); }\r
+static __INLINE void __ISB() { __ASM volatile ("isb"); }\r
+static __INLINE void __DSB() { __ASM volatile ("dsb"); }\r
+static __INLINE void __DMB() { __ASM volatile ("dmb"); }\r
+static __INLINE void __CLREX() { __ASM volatile ("clrex"); }\r
+\r
+\r
+/**\r
+ * @brief Return the Process Stack Pointer\r
+ *\r
+ * @return ProcessStackPointer\r
+ *\r
+ * Return the actual process stack pointer\r
+ */\r
+extern uint32_t __get_PSP(void);\r
+\r
+/**\r
+ * @brief Set the Process Stack Pointer\r
+ *\r
+ * @param topOfProcStack Process Stack Pointer\r
+ *\r
+ * Assign the value ProcessStackPointer to the MSP \r
+ * (process stack pointer) Cortex processor register\r
+ */\r
+extern void __set_PSP(uint32_t topOfProcStack);\r
+\r
+/**\r
+ * @brief Return the Main Stack Pointer\r
+ *\r
+ * @return Main Stack Pointer\r
+ *\r
+ * Return the current value of the MSP (main stack pointer)\r
+ * Cortex processor register\r
+ */\r
+extern uint32_t __get_MSP(void);\r
+\r
+/**\r
+ * @brief Set the Main Stack Pointer\r
+ *\r
+ * @param topOfMainStack Main Stack Pointer\r
+ *\r
+ * Assign the value mainStackPointer to the MSP \r
+ * (main stack pointer) Cortex processor register\r
+ */\r
+extern void __set_MSP(uint32_t topOfMainStack);\r
+\r
+/**\r
+ * @brief Return the Base Priority value\r
+ *\r
+ * @return BasePriority\r
+ *\r
+ * Return the content of the base priority register\r
+ */\r
+extern uint32_t __get_BASEPRI(void);\r
+\r
+/**\r
+ * @brief Set the Base Priority value\r
+ *\r
+ * @param basePri BasePriority\r
+ *\r
+ * Set the base priority register\r
+ */\r
+extern void __set_BASEPRI(uint32_t basePri);\r
+\r
+/**\r
+ * @brief Return the Priority Mask value\r
+ *\r
+ * @return PriMask\r
+ *\r
+ * Return state of the priority mask bit from the priority mask register\r
+ */\r
+extern uint32_t __get_PRIMASK(void);\r
+\r
+/**\r
+ * @brief Set the Priority Mask value\r
+ *\r
+ * @param priMask PriMask\r
+ *\r
+ * Set the priority mask bit in the priority mask register\r
+ */\r
+extern void __set_PRIMASK(uint32_t priMask);\r
+\r
+/**\r
+ * @brief Return the Fault Mask value\r
+ *\r
+ * @return FaultMask\r
+ *\r
+ * Return the content of the fault mask register\r
+ */\r
+extern uint32_t __get_FAULTMASK(void);\r
+\r
+/**\r
+ * @brief Set the Fault Mask value\r
+ *\r
+ * @param faultMask faultMask value\r
+ *\r
+ * Set the fault mask register\r
+ */\r
+extern void __set_FAULTMASK(uint32_t faultMask);\r
+\r
+/**\r
+ * @brief Return the Control Register value\r
+* \r
+* @return Control value\r
+ *\r
+ * Return the content of the control register\r
+ */\r
+extern uint32_t __get_CONTROL(void);\r
+\r
+/**\r
+ * @brief Set the Control Register value\r
+ *\r
+ * @param control Control value\r
+ *\r
+ * Set the control register\r
+ */\r
+extern void __set_CONTROL(uint32_t control);\r
+\r
+/**\r
+ * @brief Reverse byte order in integer value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in integer value\r
+ */\r
+extern uint32_t __REV(uint32_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in unsigned short value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in unsigned short value\r
+ */\r
+extern uint32_t __REV16(uint16_t value);\r
+\r
+/**\r
+ * @brief Reverse byte order in signed short value with sign extension to integer\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse byte order in signed short value with sign extension to integer\r
+ */\r
+extern int32_t __REVSH(int16_t value);\r
+\r
+/**\r
+ * @brief Reverse bit order of value\r
+ *\r
+ * @param value value to reverse\r
+ * @return reversed value\r
+ *\r
+ * Reverse bit order of value\r
+ */\r
+extern uint32_t __RBIT(uint32_t value);\r
+\r
+/**\r
+ * @brief LDR Exclusive (8 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 8 bit value\r
+ */\r
+extern uint8_t __LDREXB(uint8_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (16 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 16 bit values\r
+ */\r
+extern uint16_t __LDREXH(uint16_t *addr);\r
+\r
+/**\r
+ * @brief LDR Exclusive (32 bit)\r
+ *\r
+ * @param *addr address pointer\r
+ * @return value of (*address)\r
+ *\r
+ * Exclusive LDR command for 32 bit values\r
+ */\r
+extern uint32_t __LDREXW(uint32_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (8 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 8 bit values\r
+ */\r
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (16 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 16 bit values\r
+ */\r
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);\r
+\r
+/**\r
+ * @brief STR Exclusive (32 bit)\r
+ *\r
+ * @param value value to store\r
+ * @param *addr address pointer\r
+ * @return successful / failed\r
+ *\r
+ * Exclusive STR command for 32 bit values\r
+ */\r
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);\r
+\r
+\r
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/\r
+/* TASKING carm specific functions */\r
+\r
+/*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all instrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+#endif\r
+\r
+\r
+/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface\r
+ Core Function Interface containing:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Reset Functions\r
+*/\r
+/*@{*/\r
+\r
+/* ########################## NVIC functions #################################### */\r
+\r
+/**\r
+ * @brief Set the Priority Grouping in NVIC Interrupt Controller\r
+ *\r
+ * @param PriorityGroup is priority grouping field\r
+ *\r
+ * Set the priority grouping field using the required unlock sequence.\r
+ * The parameter priority_grouping is assigned to the field \r
+ * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ */\r
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ \r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ (0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
+ (PriorityGroupTmp << 8)); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+/**\r
+ * @brief Get the Priority Grouping from NVIC Interrupt Controller\r
+ *\r
+ * @return priority grouping field \r
+ *\r
+ * Get the priority grouping from NVIC Interrupt Controller.\r
+ * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */\r
+}\r
+\r
+/**\r
+ * @brief Enable Interrupt in NVIC Interrupt Controller\r
+ *\r
+ * @param IRQn The positive number of the external interrupt to enable\r
+ *\r
+ * Enable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Disable the interrupt line for external interrupt specified\r
+ * \r
+ * @param IRQn The positive number of the external interrupt to disable\r
+ * \r
+ * Disable a device specific interupt in the NVIC interrupt controller.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Read the interrupt pending bit for a device specific interrupt source\r
+ * \r
+ * @param IRQn The number of the device specifc interrupt\r
+ * @return 1 = interrupt pending, 0 = interrupt not pending\r
+ *\r
+ * Read the pending register in NVIC and return 1 if its status is pending, \r
+ * otherwise it returns 0\r
+ */\r
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */\r
+}\r
+\r
+/**\r
+ * @brief Set the pending bit for an external interrupt\r
+ * \r
+ * @param IRQn The number of the interrupt for set pending\r
+ *\r
+ * Set the pending bit for the specified interrupt.\r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */\r
+}\r
+\r
+/**\r
+ * @brief Clear the pending bit for an external interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for clear pending\r
+ *\r
+ * Clear the pending bit for the specified interrupt. \r
+ * The interrupt number cannot be a negative value.\r
+ */\r
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */\r
+}\r
+\r
+/**\r
+ * @brief Read the active bit for an external interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for read active bit\r
+ * @return 1 = interrupt active, 0 = interrupt not active\r
+ *\r
+ * Read the active register in NVIC and returns 1 if its status is active, \r
+ * otherwise it returns 0.\r
+ */\r
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */\r
+}\r
+\r
+/**\r
+ * @brief Set the priority for an interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for set priority\r
+ * @param priority The priority to set\r
+ *\r
+ * Set the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if(IRQn < 0) {\r
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */\r
+ else {\r
+ NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */\r
+}\r
+\r
+/**\r
+ * @brief Read the priority for an interrupt\r
+ *\r
+ * @param IRQn The number of the interrupt for get priority\r
+ * @return The priority for the interrupt\r
+ *\r
+ * Read the priority for the specified interrupt. The interrupt \r
+ * number can be positive to specify an external (device specific) \r
+ * interrupt, or negative to specify an internal (core) interrupt.\r
+ *\r
+ * The returned priority value is automatically aligned to the implemented\r
+ * priority bits of the microcontroller.\r
+ *\r
+ * Note: The priority cannot be set for every core interrupt.\r
+ */\r
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if(IRQn < 0) {\r
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */\r
+ else {\r
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */\r
+}\r
+\r
+\r
+/**\r
+ * @brief Encode the priority for an interrupt\r
+ *\r
+ * @param PriorityGroup The used priority group\r
+ * @param PreemptPriority The preemptive priority value (starting from 0)\r
+ * @param SubPriority The sub priority value (starting from 0)\r
+ * @return The encoded priority for the interrupt\r
+ *\r
+ * Encode the priority for an interrupt with the given priority group,\r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The returned priority value can be used for NVIC_SetPriority(...) function\r
+ */\r
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ return (\r
+ ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |\r
+ ((SubPriority & ((1 << (SubPriorityBits )) - 1)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ * @brief Decode the priority of an interrupt\r
+ *\r
+ * @param Priority The priority for the interrupt\r
+ * @param PriorityGroup The used priority group\r
+ * @param pPreemptPriority The preemptive priority value (starting from 0)\r
+ * @param pSubPriority The sub priority value (starting from 0)\r
+ *\r
+ * Decode an interrupt priority value with the given priority group to \r
+ * preemptive priority value and sub priority value.\r
+ * In case of a conflict between priority grouping and available\r
+ * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.\r
+ *\r
+ * The priority value can be retrieved with NVIC_GetPriority(...) function\r
+ */\r
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;\r
+ SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;\r
+ \r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);\r
+ *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);\r
+}\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+\r
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)\r
+\r
+/**\r
+ * @brief Initialize and start the SysTick counter and its interrupt.\r
+ *\r
+ * @param ticks number of ticks between two interrupts\r
+ * @return 1 = failed, 0 = successful\r
+ *\r
+ * Initialise the system tick timer and its interrupt and start the\r
+ * system tick timer / counter in free running mode to generate \r
+ * periodical interrupts.\r
+ */\r
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{ \r
+ if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */\r
+ \r
+ SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */\r
+ SysTick->VAL = 0; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | \r
+ SysTick_CTRL_TICKINT_Msk | \r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+/* ################################## Reset function ############################################ */\r
+\r
+/**\r
+ * @brief Initiate a system reset request.\r
+ *\r
+ * Initiate a system reset request to reset the MCU\r
+ */\r
+static __INLINE void NVIC_SystemReset(void)\r
+{\r
+ SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | \r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | \r
+ SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */ \r
+ while(1); /* wait until reset */\r
+}\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+\r
+/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface\r
+ Core Debug Interface containing:\r
+ - Core Debug Receive / Transmit Functions\r
+ - Core Debug Defines\r
+ - Core Debug Variables\r
+*/\r
+/*@{*/\r
+\r
+extern volatile int ITM_RxBuffer; /*!< variable to receive characters */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */\r
+\r
+\r
+/**\r
+ * @brief Outputs a character via the ITM channel 0\r
+ *\r
+ * @param ch character to output\r
+ * @return character to output\r
+ *\r
+ * The function outputs a character via the ITM channel 0. \r
+ * The function returns when no debugger is connected that has booked the output. \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */\r
+ (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */\r
+ (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0].u32 == 0);\r
+ ITM->PORT[0].u8 = (uint8_t) ch;\r
+ } \r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ * @brief Inputs a character via variable ITM_RxBuffer\r
+ *\r
+ * @return received character, -1 = no character received\r
+ *\r
+ * The function inputs a character via variable ITM_RxBuffer. \r
+ * The function returns when no debugger is connected that has booked the output. \r
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted. \r
+ */\r
+static __INLINE int ITM_ReceiveChar (void) {\r
+ int ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+ \r
+ return (ch); \r
+}\r
+\r
+\r
+/**\r
+ * @brief Check if a character via variable ITM_RxBuffer is available\r
+ *\r
+ * @return 1 = character available, 0 = no character available\r
+ *\r
+ * The function checks variable ITM_RxBuffer whether a character is available or not. \r
+ * The function returns '1' if a character is available and '0' if no character is available. \r
+ */\r
+static __INLINE int ITM_CheckChar (void) {\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {\r
+ return (0); /* no character available */\r
+ } else {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_CM3_core_definitions */\r
+\r
+#endif /* __CM3_CORE_H__ */\r
+\r
+/*lint -restore */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: core_cm3_psoc5.h\r
+* Version 3.40\r
+*\r
+* Description:\r
+* Provides important type information for the PSoC5. This includes types\r
+* necessary for core_cm3.h.\r
+*\r
+* Note:\r
+* Documentation of the API's in this file is located in the\r
+* System Reference Guide provided with PSoC Creator.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+********************************************************************************/\r
+\r
+\r
+#if !defined(__CORE_CM3_PSOC5_H__)\r
+#define __CORE_CM3_PSOC5_H__\r
+\r
+/** Interrupt Number Definition */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */\r
+ SysTick_IRQn = -1 /*!< 15 Cortex-M3 System Tick Interrupt */\r
+/****** PSoC5 Peripheral Interrupt Numbers *******************************************************/\r
+ /* Not relevant. All peripheral interrupts are defined by the user */\r
+} IRQn_Type;\r
+\r
+#include <core_cm3.h>\r
+\r
+#endif /* __CORE_CM3_PSOC5_H__ */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: cyPm.c\r
+* Version 3.40\r
+*\r
+* Description:\r
+* Provides an API for the power management.\r
+*\r
+* Note:\r
+* Documentation of the API's in this file is located in the\r
+* System Reference Guide provided with PSoC Creator.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "cyPm.h"\r
+\r
+\r
+/*******************************************************************\r
+* Place your includes, defines and code here. Do not use merge\r
+* region below unless any component datasheet suggest to do so.\r
+*******************************************************************/\r
+/* `#START CY_PM_HEADER_INCLUDE` */\r
+\r
+/* `#END` */\r
+\r
+\r
+static CY_PM_BACKUP_STRUCT cyPmBackup;\r
+static CY_PM_CLOCK_BACKUP_STRUCT cyPmClockBackup;\r
+\r
+/* Convertion table between register's values and frequency in MHz */\r
+static const uint8 CYCODE cyPmImoFreqReg2Mhz[7u] = {12u, 6u, 24u, 3u, 48u, 62u, 74u};\r
+\r
+/* Function Prototypes */\r
+static void CyPmHibSaveSet(void);\r
+static void CyPmHibRestore(void) ;\r
+\r
+static void CyPmSlpSaveSet(void) ;\r
+static void CyPmSlpRestore(void) ;\r
+\r
+static void CyPmHibSlpSaveSet(void) ;\r
+static void CyPmHibSlpRestore(void) ;\r
+\r
+static void CyPmHviLviSaveDisable(void) ;\r
+static void CyPmHviLviRestore(void) ;\r
+\r
+#if(CY_PSOC5A)\r
+\r
+ /***************************************************************************\r
+ * The PICU interupt event is not allowed to act as wakeup source for PSoC 5.\r
+ * To prevent accidental wakeup all the PICU interrupts are disabled before\r
+ * Sleep and Hibernate low power modes entry. In case of Sleep mode registers\r
+ * values must be restored on wakeup, but in case of Hibernate low power mode\r
+ * there is no sense in saving/restoring registers values as the only wakeup\r
+ * source for this mode is external reset (XRES). For more information refer\r
+ * to the PSoC 5 device TRM.\r
+ ***************************************************************************/\r
+\r
+ static void CyPmSavePicuInterrupts(void);\r
+ static void CyPmDisablePicuInterrupts(void) ;\r
+ static void CyPmRestorePicuInterrupts(void) ;\r
+\r
+#endif /* (CY_PSOC5A) */\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPmSaveClocks\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* This function is called in preparation for entering sleep or hibernate low\r
+* power modes. Saves all state of the clocking system that does not persist\r
+* during sleep/hibernate or that needs to be altered in preparation for\r
+* sleep/hibernate. Shutdowns all the digital and analog clock dividers for the\r
+* active power mode configuration.\r
+*\r
+* Switches the master clock over to the IMO and shuts down the PLL and MHz\r
+* Crystal. The IMO frequency is set to either 12 MHz or 48 MHz to match the\r
+* Design-Wide Resources System Editor "Enable Fast IMO During Startup" setting.\r
+* The ILO and 32 KHz oscillators are not impacted. The current Flash wait state\r
+* setting is saved and the Flash wait state setting is set for the current IMO\r
+* speed.\r
+*\r
+* Note If the Master Clock source is routed through the DSI inputs, then it\r
+* must be set manually to another source before using the\r
+* CyPmSaveClocks()/CyPmRestoreClocks() functions.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Side Effects:\r
+* All peripheral clocks are going to be off after this API method call.\r
+*\r
+*******************************************************************************/\r
+void CyPmSaveClocks(void) \r
+{\r
+ /* Digital and analog clocks - save enable state and disable them all */\r
+ cyPmClockBackup.enClkA = CY_PM_ACT_CFG1_REG & CY_PM_ACT_EN_CLK_A_MASK;\r
+ cyPmClockBackup.enClkD = CY_PM_ACT_CFG2_REG;\r
+ CY_PM_ACT_CFG1_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_A_MASK));\r
+ CY_PM_ACT_CFG2_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_D_MASK));\r
+\r
+ /* Save current flash wait cycles and set the maximum value */\r
+ cyPmClockBackup.flashWaitCycles = CY_PM_CACHE_CR_CYCLES_MASK & CY_PM_CACHE_CR_REG;\r
+ CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES);\r
+\r
+ /* IMO - save current IMO MHz OSC frequency and USB mode is on bit */\r
+ cyPmClockBackup.imoFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK;\r
+ cyPmClockBackup.imoUsbClk = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_USB;\r
+\r
+ /* IMO doubler - save enable state */\r
+ if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON))\r
+ {\r
+ /* IMO doubler enabled - save and disable */\r
+ cyPmClockBackup.imo2x = CY_PM_ENABLED;\r
+ }\r
+ else\r
+ {\r
+ /* IMO doubler disabled */\r
+ cyPmClockBackup.imo2x = CY_PM_DISABLED;\r
+ }\r
+\r
+ /* IMO - set appropriate frequency for LPM */\r
+ CyIMO_SetFreq(CY_PM_IMO_FREQ_LPM);\r
+\r
+ /* IMO - save enable state and enable without wait to settle */\r
+ if(0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG))\r
+ {\r
+ /* IMO - save enabled state */\r
+ cyPmClockBackup.imoEnable = CY_PM_ENABLED;\r
+ }\r
+ else\r
+ {\r
+ /* IMO - save disabled state */\r
+ cyPmClockBackup.imoEnable = CY_PM_DISABLED;\r
+\r
+ /* IMO - enable */\r
+ CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE);\r
+ }\r
+\r
+ /* IMO - save the current IMOCLK source and set to IMO if not yet */\r
+ if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_XCLKEN))\r
+ {\r
+ /* DSI or XTAL CLK */\r
+ cyPmClockBackup.imoClkSrc =\r
+ (0u == (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO2X_SRC)) ? CY_IMO_SOURCE_DSI : CY_IMO_SOURCE_XTAL;\r
+\r
+ /* IMO - set IMOCLK source to MHz OSC */\r
+ CyIMO_SetSource(CY_IMO_SOURCE_IMO);\r
+ }\r
+ else\r
+ {\r
+ /* IMO */\r
+ cyPmClockBackup.imoClkSrc = CY_IMO_SOURCE_IMO;\r
+ }\r
+\r
+ /* Save clk_imo source */\r
+ cyPmClockBackup.clkImoSrc = CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK;\r
+\r
+ /* If IMOCLK2X or SPC OSC is source for clk_imo, set it to IMOCLK */\r
+ if(CY_PM_CLKDIST_IMO_OUT_IMO != cyPmClockBackup.clkImoSrc)\r
+ {\r
+ /* Set IMOCLK to source for clk_imo */\r
+ CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) |\r
+ CY_PM_CLKDIST_IMO_OUT_IMO;\r
+ } /* Need to change nothing if IMOCLK is source clk_imo */\r
+\r
+ /* IMO doubler - disable it (saved above) */\r
+ if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON))\r
+ {\r
+ CyIMO_DisableDoubler();\r
+ }\r
+\r
+ /* Master clock - save divider and set it to divide-by-one (if no yet) */\r
+ cyPmClockBackup.clkSyncDiv = CY_PM_CLKDIST_MSTR0_REG;\r
+ if(CY_PM_DIV_BY_ONE != cyPmClockBackup.clkSyncDiv)\r
+ {\r
+ CyMasterClk_SetDivider(CY_PM_DIV_BY_ONE);\r
+ } /* Need to change nothing if master clock divider is 1 */\r
+\r
+ /* Master clock - save current source */\r
+ cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK;\r
+\r
+ /* Master clock source - set it to IMO if not yet. */\r
+ if(CY_MASTER_SOURCE_IMO != cyPmClockBackup.masterClkSrc)\r
+ {\r
+ CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO);\r
+ } /* Need to change nothing if master clock source is IMO */\r
+\r
+ /* Bus clock - save divider and set it, if needed, to divide-by-one */\r
+ cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u) | CY_PM_CLK_BUS_LSB_DIV_REG;\r
+ if(CY_PM_BUS_CLK_DIV_BY_ONE != cyPmClockBackup.clkBusDiv)\r
+ {\r
+ CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE);\r
+ } /* Do nothing if saved and actual values are equal */\r
+\r
+ /* Set number of wait cycles for the flash according CPU frequency in MHz */\r
+ CyFlash_SetWaitCycles((uint8)CY_PM_GET_CPU_FREQ_MHZ);\r
+\r
+ /* PLL - check enable state, disable if needed */\r
+ if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE))\r
+ {\r
+ /* PLL is enabled - save state and disable */\r
+ cyPmClockBackup.pllEnableState = CY_PM_ENABLED;\r
+ CyPLL_OUT_Stop();\r
+ }\r
+ else\r
+ {\r
+ /* PLL is disabled - save state */\r
+ cyPmClockBackup.pllEnableState = CY_PM_DISABLED;\r
+ }\r
+\r
+ /* MHz ECO - check enable state and disable if needed */\r
+ if(0u != (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_ENABLE))\r
+ {\r
+ /* MHz ECO is enabled - save state and disable */\r
+ cyPmClockBackup.xmhzEnableState = CY_PM_ENABLED;\r
+ CyXTAL_Stop();\r
+ }\r
+ else\r
+ {\r
+ /* MHz ECO is disabled - save state */\r
+ cyPmClockBackup.xmhzEnableState = CY_PM_DISABLED;\r
+ }\r
+\r
+\r
+ /***************************************************************************\r
+ * Save enable state of delay between the system bus clock and each of the\r
+ * 4 individual analog clocks. This bit non-retention and it's value should\r
+ * be restored on wakeup.\r
+ ***************************************************************************/\r
+ if(0u != (CY_PM_CLKDIST_DELAY_REG & CY_PM_CLKDIST_DELAY_EN))\r
+ {\r
+ cyPmClockBackup.clkDistDelay = CY_PM_ENABLED;\r
+ }\r
+ else\r
+ {\r
+ cyPmClockBackup.clkDistDelay = CY_PM_DISABLED;\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPmRestoreClocks\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Restores any state that was preserved by the last call to CyPmSaveClocks().\r
+* The Flash wait state setting is also restored.\r
+*\r
+* Note If the Master Clock source is routed through the DSI inputs, then it\r
+* must be set manually to another source before using the\r
+* CyPmSaveClocks()/CyPmRestoreClocks() functions.\r
+*\r
+* PSoC 3 and PSoC 5LP:\r
+* The merge region could be used to process state when the megahertz crystal is\r
+* not ready after the hold-off timeout.\r
+*\r
+* PSoC 5:\r
+* The 130 ms is given for the megahertz crystal to stabilize. It's readiness is\r
+* not verified after the hold-off timeout.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyPmRestoreClocks(void) \r
+{\r
+ #if (!CY_PSOC5A)\r
+\r
+ cystatus status = CYRET_TIMEOUT;\r
+ uint16 i;\r
+\r
+ #endif /* (!CY_PSOC5A) */\r
+\r
+\r
+ /* Convertion table between CyIMO_SetFreq() parameters and register's value */\r
+ const uint8 CYCODE cyPmImoFreqMhz2Reg[7u] = {\r
+ CY_IMO_FREQ_12MHZ, CY_IMO_FREQ_6MHZ, CY_IMO_FREQ_24MHZ, CY_IMO_FREQ_3MHZ,\r
+ CY_IMO_FREQ_48MHZ, 5u, 6u};\r
+\r
+ /* Restore enable state of delay between the system bus clock and ACLKs. */\r
+ if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay)\r
+ {\r
+ /* Delay for both the bandgap and the delay line to settle out */\r
+ CyDelayCycles((uint32)(CY_PM_CLK_DELAY_BANDGAP_SETTLE_US + CY_PM_CLK_DELAY_BIAS_SETTLE_US) *\r
+ CY_PM_GET_CPU_FREQ_MHZ);\r
+\r
+ CY_PM_CLKDIST_DELAY_REG |= CY_PM_CLKDIST_DELAY_EN;\r
+ }\r
+\r
+ /* MHz ECO restore state */\r
+ if(CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState)\r
+ {\r
+ /***********************************************************************\r
+ * Enabling XMHZ XTAL. The actual CyXTAL_Start() with non zero wait\r
+ * period uses FTW for period measurement. This could cause a problem\r
+ * if CTW/FTW is used as a wake up time in the low power modes APIs.\r
+ * So, the XTAL wait procedure is implemented with a software delay.\r
+ ***********************************************************************/\r
+\r
+ /* Enable XMHZ XTAL with no wait */\r
+ (void) CyXTAL_Start(CY_PM_XTAL_MHZ_NO_WAIT);\r
+\r
+ #if(CY_PSOC5A)\r
+\r
+ /* Make a 130 milliseconds delay */\r
+ CyDelayCycles((uint32)CY_PM_WAIT_200_US * CY_PM_GET_CPU_FREQ_MHZ * CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US);\r
+\r
+ #else\r
+\r
+ /* Read XERR bit to clear it */\r
+ (void) CY_PM_FASTCLK_XMHZ_CSR_REG;\r
+\r
+ /* Wait */\r
+ for(i = CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US; i > 0u; i--)\r
+ {\r
+ /* Make a 200 microseconds delay */\r
+ CyDelayCycles((uint32)CY_PM_WAIT_200_US * CY_PM_GET_CPU_FREQ_MHZ);\r
+\r
+ /* High output indicates oscillator failure */\r
+ if(0u == (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_XERR))\r
+ {\r
+ status = CYRET_SUCCESS;\r
+ break;\r
+ }\r
+ }\r
+\r
+ if(CYRET_TIMEOUT == status)\r
+ {\r
+ /*******************************************************************\r
+ * Process the situation when megahertz crystal is not ready.\r
+ * Time to stabialize value is crystal specific.\r
+ *******************************************************************/\r
+\r
+ /* `#START_MHZ_ECO_TIMEOUT` */\r
+\r
+ /* `#END` */\r
+ }\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+ } /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */\r
+\r
+\r
+ /* Temprorary set the maximum flash wait cycles */\r
+ CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES);\r
+\r
+ /* The XTAL and DSI clocks are ready to be source for Master clock. */\r
+ if((CY_PM_MASTER_CLK_SRC_XTAL == cyPmClockBackup.masterClkSrc) ||\r
+ (CY_PM_MASTER_CLK_SRC_DSI == cyPmClockBackup.masterClkSrc))\r
+ {\r
+ /* Restore Master clock's divider */\r
+ if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv)\r
+ {\r
+ /* Restore Master clock divider */\r
+ CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv);\r
+ }\r
+\r
+ /* Restore Master clock source */\r
+ CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc);\r
+ }\r
+\r
+ /* IMO - restore IMO frequency */\r
+ if((0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) &&\r
+ (CY_IMO_FREQ_24MHZ == cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq]))\r
+ {\r
+ /* Restore IMO frequency (24 MHz) and trim it for USB */\r
+ CyIMO_SetFreq(CY_IMO_FREQ_USB);\r
+ }\r
+ else\r
+ {\r
+ /* Restore IMO frequency */\r
+ CyIMO_SetFreq(cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq]);\r
+\r
+ if(0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB))\r
+ {\r
+ CY_PM_FASTCLK_IMO_CR_REG |= CY_PM_FASTCLK_IMO_CR_USB;\r
+ }\r
+ else\r
+ {\r
+ CY_PM_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_PM_FASTCLK_IMO_CR_USB));\r
+ }\r
+ }\r
+\r
+ /* IMO - restore enable state if needed */\r
+ if((CY_PM_ENABLED == cyPmClockBackup.imoEnable) &&\r
+ (0u == (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)))\r
+ {\r
+ /* IMO - restore enabled state */\r
+ CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE);\r
+ }\r
+\r
+ /* IMO - restore disable state if needed */\r
+ if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) &&\r
+ (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)))\r
+ {\r
+ CyIMO_Stop();\r
+ }\r
+\r
+ /* IMO - restore IMOCLK source */\r
+ CyIMO_SetSource(cyPmClockBackup.imoClkSrc);\r
+\r
+ /* Restore IMO doubler enable state (turned off by CyPmSaveClocks()) */\r
+ if(CY_PM_ENABLED == cyPmClockBackup.imo2x)\r
+ {\r
+ CyIMO_EnableDoubler();\r
+ }\r
+\r
+ /* IMO - restore clk_imo source, if needed */\r
+ if(cyPmClockBackup.clkImoSrc != (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK))\r
+ {\r
+ CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) |\r
+ cyPmClockBackup.clkImoSrc;\r
+ }\r
+\r
+ /* PLL restore state */\r
+ if(CY_PM_ENABLED == cyPmClockBackup.pllEnableState)\r
+ {\r
+ /***********************************************************************\r
+ * Enable PLL. The actual CyPLL_OUT_Start() without wait period uses FTW\r
+ * for period measurement. This could cause a problem if CTW/FTW is used\r
+ * as a wakeup time in the low power modes APIs. To omit this issue PLL\r
+ * wait procedure is implemented with a software delay.\r
+ ***********************************************************************/\r
+\r
+ /* Enable PLL */\r
+ (void) CyPLL_OUT_Start(CY_PM_PLL_OUT_NO_WAIT);\r
+\r
+ /* Make a 250 us delay */\r
+ CyDelayCycles((uint32)CY_PM_WAIT_250_US * CY_PM_GET_CPU_FREQ_MHZ);\r
+ } /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */\r
+\r
+\r
+ /* PLL and IMO is ready to be source for Master clock */\r
+ if((CY_PM_MASTER_CLK_SRC_IMO == cyPmClockBackup.masterClkSrc) ||\r
+ (CY_PM_MASTER_CLK_SRC_PLL == cyPmClockBackup.masterClkSrc))\r
+ {\r
+ /* Restore Master clock divider */\r
+ if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv)\r
+ {\r
+ CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv);\r
+ }\r
+\r
+ /* Restore Master clock source */\r
+ CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc);\r
+ }\r
+\r
+ /* Bus clock - restore divider, if needed */\r
+ if(cyPmClockBackup.clkBusDiv != ((uint16)((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u) | CY_PM_CLK_BUS_LSB_DIV_REG))\r
+ {\r
+ CyBusClk_SetDivider(cyPmClockBackup.clkBusDiv);\r
+ }\r
+\r
+ /* Restore flash wait cycles */\r
+ CY_PM_CACHE_CR_REG = ((CY_PM_CACHE_CR_REG & ((uint8)(~CY_PM_CACHE_CR_CYCLES_MASK))) |\r
+ cyPmClockBackup.flashWaitCycles);\r
+\r
+ /* Digital and analog clocks - restore state */\r
+ CY_PM_ACT_CFG1_REG = cyPmClockBackup.enClkA;\r
+ CY_PM_ACT_CFG2_REG = cyPmClockBackup.enClkD;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPmAltAct\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Puts the part into the Alternate Active (Standby) state. The Alternate Active\r
+* state can allow for any of the capabilities of the device to be active, but\r
+* the operation of this function is dependent on the CPU being disabled during\r
+* the Alternate Active state. The configuration code and the component APIs\r
+* will configure the template for the Alternate Active state to be the same as\r
+* the Active state with the exception that the CPU will be disabled during\r
+* Alternate Active.\r
+*\r
+* Note Before calling this function, you must manually configure the power mode\r
+* of the source clocks for the timer that is used as the wakeup timer.\r
+*\r
+* PSoC 3:\r
+* Before switching to Alternate Active, if a wakeupTime other than NONE is\r
+* specified, then the appropriate timer state is configured as specified with\r
+* the interrupt for that timer disabled. The wakeup source will be the\r
+* combination of the values specified in the wakeupSource and any timer\r
+* specified in the wakeupTime argument. Once the wakeup condition is\r
+* satisfied, then all saved state is restored and the function returns in the\r
+* Active state.\r
+*\r
+* Note that if the wakeupTime is made with a different value, the period before\r
+* the wakeup occurs can be significantly shorter than the specified time. If\r
+* the next call is made with the same wakeupTime value, then the wakeup will\r
+* occur the specified period after the previous wakeup occurred.\r
+*\r
+* If a wakeupTime other than NONE is specified, then upon exit the state of the\r
+* specified timer will be left as specified by wakeupTime with the timer\r
+* enabled and the interrupt disabled. If the CTW, FTW or One PPS is already\r
+* configured for wakeup, for example with the SleepTimer or RTC components,\r
+* then specify NONE for the wakeupTime and include the appropriate source for\r
+* wakeupSource.\r
+*\r
+* PSoC 5:\r
+* This function is used to both enter the Alternate Active mode and halt the\r
+* processor. For PSoC 3 these two actions must be paired together. With\r
+* PSoC 5 the processor can be halted independently with the __WFI() function\r
+* from the CMSIS library that is included in Creator. This function should be\r
+* used instead when the action required is just to halt the processor until an\r
+* enabled interrupt occurs.\r
+*\r
+* Neither of the parameters to the CyPmAltAct() function are used. The\r
+* parameters must be set to 0 (PM_ALT_ACT_TIME_NONE and PM_ALT_ACT_SRC_NONE).\r
+* The wake up time configuration can be done by a separate component: the CTW\r
+* wakeup interval should be configured with the Sleep Timer component and one\r
+* second interval should be configured with the RTC component.\r
+*\r
+* Upon function execution the device will be switched from Active to Alternate\r
+* Active mode and the CPU will be halted. When an enabled interrupt occurs the\r
+* device will be switched to Active mode and the CPU will be started. Note that\r
+* if a wakeup event occurs and the associated interrupt is not enabled, then\r
+* the device will switch to Active mode with the CPU still halted. The CPU will\r
+* remain halted until an enabled interrupt occurs.\r
+*\r
+* PSoC 5LP:\r
+* This function is used to both enter the Alternate Active mode and halt the\r
+* processor. For PSoC 3 these two actions must be paired together. With PSoC\r
+* 5LP the processor can be halted independently with the __WFI() function from\r
+* the CMSIS library that is included in Creator. This function should be used\r
+* instead when the action required is just to halt the processor until an\r
+* enabled interrupt occurs.\r
+*\r
+* The wakeupTime parameter is not used for this device. It must be set to zero\r
+* (PM_ALT_ACT_TIME_NONE). The wake up time configuration can be done by a\r
+* separate component: the CTW wakeup interval should be configured with the\r
+* Sleep Timer component and one second interval should be configured with the\r
+* RTC component.\r
+*\r
+* The wakeup behavior depends on wakeupSource parameter in the following\r
+* manner: upon function execution the device will be switched from Active to\r
+* Alternate Active mode and then the CPU will be halted. When an enabled wakeup\r
+* event occurs the device will return to Active mode. Similarly when an\r
+* enabled interrupt occurs the CPU will be started. These two actions will\r
+* occur together provided that the event that occurs is an enabled wakeup\r
+* source and also generates an interrupt. If just the wakeup event occurs then\r
+* the device will be in Active mode, but the CPU will remain halted waiting for\r
+* an interrupt. If an interrupt occurs from something other than a wakeup\r
+* source, then the CPU will restart with the device in Alternate Active mode\r
+* until a wakeup event occurs.\r
+*\r
+* For example, if CyPmAltAct(PM_ALT_ACT_TIME_NONE, PM_ALT_ACT_SRC_PICU) is\r
+* called and PICU interrupt occurs, the CPU will be started and device will be\r
+* switched into Active mode. And if CyPmAltAct(PM_ALT_ACT_TIME_NONE,\r
+* PM_ALT_ACT_SRC_NONE) is called and PICU interrupt occurs, the CPU will be\r
+* started while device remains in Alternate Active mode.\r
+*\r
+* Parameters:\r
+* wakeupTime: Specifies a timer wakeup source and the frequency of that\r
+* source. For PSoC 5 and PSoC 5LP this parameter is ignored.\r
+*\r
+* Define Time\r
+* PM_ALT_ACT_TIME_NONE None\r
+* PM_ALT_ACT_TIME_ONE_PPS One PPS: 1 second\r
+* PM_ALT_ACT_TIME_CTW_2MS CTW: 2 ms\r
+* PM_ALT_ACT_TIME_CTW_4MS CTW: 4 ms\r
+* PM_ALT_ACT_TIME_CTW_8MS CTW: 8 ms\r
+* PM_ALT_ACT_TIME_CTW_16MS CTW: 16 ms\r
+* PM_ALT_ACT_TIME_CTW_32MS CTW: 32 ms\r
+* PM_ALT_ACT_TIME_CTW_64MS CTW: 64 ms\r
+* PM_ALT_ACT_TIME_CTW_128MS CTW: 128 ms\r
+* PM_ALT_ACT_TIME_CTW_256MS CTW: 256 ms\r
+* PM_ALT_ACT_TIME_CTW_512MS CTW: 512 ms\r
+* PM_ALT_ACT_TIME_CTW_1024MS CTW: 1024 ms\r
+* PM_ALT_ACT_TIME_CTW_2048MS CTW: 2048 ms\r
+* PM_ALT_ACT_TIME_CTW_4096MS CTW: 4096 ms\r
+* PM_ALT_ACT_TIME_FTW(1-256)* FTW: 10us to 2.56 ms\r
+*\r
+* *Note: PM_ALT_ACT_TIME_FTW() is a macro that takes an argument that\r
+* specifies how many increments of 10 us to delay.\r
+ For PSoC 3 silicon the valid range of values is 1 to 256.\r
+*\r
+* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if\r
+* a wakeupTime has been specified the associated timer will be\r
+* included as a wakeup source. For PSoC 5 this parameter is\r
+* ignored.\r
+*\r
+* Define Source\r
+* PM_ALT_ACT_SRC_NONE None\r
+* PM_ALT_ACT_SRC_COMPARATOR0 Comparator 0\r
+* PM_ALT_ACT_SRC_COMPARATOR1 Comparator 1\r
+* PM_ALT_ACT_SRC_COMPARATOR2 Comparator 2\r
+* PM_ALT_ACT_SRC_COMPARATOR3 Comparator 3\r
+* PM_ALT_ACT_SRC_INTERRUPT Interrupt\r
+* PM_ALT_ACT_SRC_PICU PICU\r
+* PM_ALT_ACT_SRC_I2C I2C\r
+* PM_ALT_ACT_SRC_BOOSTCONVERTER Boost Converter\r
+* PM_ALT_ACT_SRC_FTW Fast Timewheel*\r
+* PM_ALT_ACT_SRC_VD High and Low Voltage Detection (HVI, LVI)*\r
+* PM_ALT_ACT_SRC_CTW Central Timewheel**\r
+* PM_ALT_ACT_SRC_ONE_PPS One PPS**\r
+* PM_ALT_ACT_SRC_LCD LCD\r
+*\r
+* *Note : FTW and HVI/LVI wakeup signals are in the same mask bit.\r
+* **Note: CTW and One PPS wakeup signals are in the same mask bit.\r
+*\r
+* When specifying a Comparator as the wakeupSource an instance specific define\r
+* should be used that will track with the specific comparator that the instance\r
+* is placed into. As an example, for a Comparator instance named MyComp the\r
+* value to OR into the mask is: MyComp_ctComp__CMP_MASK.\r
+*\r
+* When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus()\r
+* function must be called upon wakeup with corresponding parameter. Please\r
+* refer to the CyPmReadStatus() API in the System Reference Guide for more\r
+* information.\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Reentrant:\r
+* No\r
+*\r
+* Side Effects:\r
+* If a wakeupTime other than NONE is specified, then upon exit the state of the\r
+* specified timer will be left as specified by wakeupTime with the timer\r
+* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is\r
+* used as wakeup time) or ILO 100 KHz (if FTW timer is used as wakeup time)\r
+* will be left started.\r
+*\r
+*******************************************************************************/\r
+void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) \r
+{\r
+ #if(CY_PSOC5)\r
+\r
+ /* Arguments expected to be 0 */\r
+ CYASSERT(PM_ALT_ACT_TIME_NONE == wakeupTime);\r
+\r
+ #if(CY_PSOC5A)\r
+\r
+ /* The wakeupSource argument expected to be 0 */\r
+ CYASSERT(PM_ALT_ACT_SRC_NONE == wakeupSource);\r
+\r
+ if(0u != wakeupSource)\r
+ {\r
+ /* To remove unreferenced local variable warning */\r
+ }\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+ if(0u != wakeupTime)\r
+ {\r
+ /* To remove unreferenced local variable warning */\r
+ }\r
+\r
+ #endif /* (CY_PSOC5) */\r
+\r
+\r
+ #if(CY_PSOC3)\r
+\r
+ /* FTW - save current and set new configuration */\r
+ if((wakeupTime >= PM_ALT_ACT_TIME_FTW(1u)) && (wakeupTime <= PM_ALT_ACT_TIME_FTW(256u)))\r
+ {\r
+ CyPmFtwSetInterval(PM_ALT_ACT_FTW_INTERVAL(wakeupTime));\r
+\r
+ /* Include associated timer to the wakeupSource */\r
+ wakeupSource |= PM_ALT_ACT_SRC_FTW;\r
+ }\r
+\r
+ /* CTW - save current and set new configuration */\r
+ if((wakeupTime >= PM_ALT_ACT_TIME_CTW_2MS) && (wakeupTime <= PM_ALT_ACT_TIME_CTW_4096MS))\r
+ {\r
+ /* Save current CTW configuration and set new one */\r
+ CyPmCtwSetInterval((uint8)(wakeupTime - 1u));\r
+\r
+ /* Include associated timer to the wakeupSource */\r
+ wakeupSource |= PM_ALT_ACT_SRC_CTW;\r
+ }\r
+\r
+ /* 1PPS - save current and set new configuration */\r
+ if(PM_ALT_ACT_TIME_ONE_PPS == wakeupTime)\r
+ {\r
+ /* Save current 1PPS configuration and set new one */\r
+ CyPmOppsSet();\r
+\r
+ /* Include associated timer to the wakeupSource */\r
+ wakeupSource |= PM_ALT_ACT_SRC_ONE_PPS;\r
+ }\r
+\r
+ #endif /* (CY_PSOC3) */\r
+\r
+\r
+ #if(CY_PSOC3 || CY_PSOC5LP)\r
+\r
+ /* Save and set new wake up configuration */\r
+\r
+ /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */\r
+ cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG;\r
+ CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u);\r
+\r
+ /* Comparators */\r
+ cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG;\r
+ CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK);\r
+\r
+ /* LCD */\r
+ cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG;\r
+ CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u));\r
+\r
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+\r
+ /* Switch to the Alternate Active mode */\r
+ CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_ALT_ACT);\r
+\r
+ /* Recommended readback. */\r
+ (void) CY_PM_MODE_CSR_REG;\r
+\r
+ /* Two recommended NOPs to get into the mode. */\r
+ CY_NOP;\r
+ CY_NOP;\r
+\r
+ /* Execute WFI instruction (for ARM-based devices only) */\r
+ CY_PM_WFI;\r
+\r
+ /* Point of return from Alternate Active Mode */\r
+\r
+ #if(CY_PSOC3 || CY_PSOC5LP)\r
+\r
+ /* Restore wake up configuration */\r
+ CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0;\r
+ CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1;\r
+ CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2;\r
+\r
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPmSleep\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Puts the part into the Sleep state.\r
+*\r
+* Note Before calling this function, you must manually configure the power\r
+* mode of the source clocks for the timer that is used as wakeup timer.\r
+*\r
+* Note Before calling this function, you must prepare clock tree configuration\r
+* for the low power mode by calling CyPmSaveClocks(). And restore clock\r
+* configuration after CyPmSleep() execution by calling CyPmRestoreClocks(). See\r
+* Power Management section, Clock Configuration subsection of the System\r
+* Reference Guide for more information.\r
+*\r
+* PSoC 3:\r
+* Before switching to Sleep, if a wakeupTime other than NONE is specified,\r
+* then the appropriate timer state is configured as specified with the\r
+* interrupt for that timer disabled. The wakeup source will be the combination\r
+* of the values specified in the wakeupSource and any timer specified in the\r
+* wakeupTime argument. Once the wakeup condition is satisfied, then all saved\r
+* state is restored and the function returns in the Active state.\r
+*\r
+* Note that if the wakeupTime is made with a different value, the period before\r
+* the wakeup occurs can be significantly shorter than the specified time. If\r
+* the next call is made with the same wakeupTime value, then the wakeup will\r
+* occur the specified period after the previous wakeup occurred.\r
+*\r
+* If a wakeupTime other than NONE is specified, then upon exit the state of the\r
+* specified timer will be left as specified by wakeupTime with the timer\r
+* enabled and the interrupt disabled. If the CTW or One PPS is already\r
+* configured for wakeup, for example with the SleepTimer or RTC components,\r
+* then specify NONE for the wakeupTime and include the appropriate source for\r
+* wakeupSource.\r
+*\r
+* PSoC 5:\r
+* Neither parameter to this function is used for PSoC 5. The parameters must be\r
+* set to 0 (PM_SLEEP_TIME_NONE and PM_SLEEP_SRC_NONE). The device will go\r
+* into Sleep mode until it is woken by an interrupt from the Central Time Wheel\r
+* (CTW). The CTW must already be configured to generate an interrupt. It is\r
+* configured using the SleepTimer component. Only the CTW can be used to wake\r
+* the device from sleep mode. The other wakeup sources, Once per second or\r
+* Port Interrupt Controller (PICU), cannot be used reliably with PSoC 5. This\r
+* function automatically disables these interrupt sources and then restores\r
+* them after the devices is woken by the CTW.\r
+*\r
+* The duration of sleep needs to be controlled so that the device doesn't wake\r
+* up too soon after going to sleep or remain asleep for too long. Reliable\r
+* sleep times of between 1 ms and 128 ms can be supported. This requirement is\r
+* satisfied with CTW settings of 4, 8, 16, 32, 64, 128 or 256 ms. To control\r
+* the sleep time the CTW is reset automatically just before putting the device\r
+* to sleep. The resulting wakeup time is half the duration programmed into the\r
+* CTW with an uncertainty of 1 ms due to the arrival time of the first ILO\r
+* clock edge. For example, the setting of 4 ms will result in a sleep time\r
+* between 1 ms and 2 ms.\r
+*\r
+* PSoC 5LP:\r
+* The wakeupTime parameter is not used and the only NONE can be specified.\r
+* The wakeup time must be configured with the component, SleepTimer for CTW\r
+* intervals and RTC for 1PPS interval. The component must be configured to\r
+* generate an interrrupt.\r
+*\r
+* Parameters:\r
+* wakeupTime: Specifies a timer wakeup source and the frequency of that\r
+* source. For PSoC 5 and PSoC 5LP, this parameter is ignored.\r
+*\r
+* Define Time\r
+* PM_SLEEP_TIME_NONE None\r
+* PM_SLEEP_TIME_ONE_PPS One PPS: 1 second\r
+* PM_SLEEP_TIME_CTW_2MS CTW: 2 ms\r
+* PM_SLEEP_TIME_CTW_4MS CTW: 4 ms\r
+* PM_SLEEP_TIME_CTW_8MS CTW: 8 ms\r
+* PM_SLEEP_TIME_CTW_16MS CTW: 16 ms\r
+* PM_SLEEP_TIME_CTW_32MS CTW: 32 ms\r
+* PM_SLEEP_TIME_CTW_64MS CTW: 64 ms\r
+* PM_SLEEP_TIME_CTW_128MS CTW: 128 ms\r
+* PM_SLEEP_TIME_CTW_256MS CTW: 256 ms\r
+* PM_SLEEP_TIME_CTW_512MS CTW: 512 ms\r
+* PM_SLEEP_TIME_CTW_1024MS CTW: 1024 ms\r
+* PM_SLEEP_TIME_CTW_2048MS CTW: 2048 ms\r
+* PM_SLEEP_TIME_CTW_4096MS CTW: 4096 ms\r
+*\r
+* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if\r
+* a wakeupTime has been specified the associated timer will be\r
+* included as a wakeup source. For PSoC 5 this parameter is\r
+* ignored.\r
+*\r
+* Define Source\r
+* PM_SLEEP_SRC_NONE None\r
+* PM_SLEEP_SRC_COMPARATOR0 Comparator 0\r
+* PM_SLEEP_SRC_COMPARATOR1 Comparator 1\r
+* PM_SLEEP_SRC_COMPARATOR2 Comparator 2\r
+* PM_SLEEP_SRC_COMPARATOR3 Comparator 3\r
+* PM_SLEEP_SRC_PICU PICU\r
+* PM_SLEEP_SRC_I2C I2C\r
+* PM_SLEEP_SRC_BOOSTCONVERTER Boost Converter\r
+* PM_SLEEP_SRC_VD High and Low Voltage Detection (HVI, LVI)\r
+* PM_SLEEP_SRC_CTW Central Timewheel*\r
+* PM_SLEEP_SRC_ONE_PPS One PPS*\r
+* PM_SLEEP_SRC_LCD LCD\r
+*\r
+* *Note: CTW and One PPS wakeup signals are in the same mask bit.\r
+* For PSoC 5, these are in a different bit (value 1024).\r
+*\r
+* When specifying a Comparator as the wakeupSource an instance specific define\r
+* should be used that will track with the specific comparator that the instance\r
+* is placed into. As an example for a Comparator instance named MyComp the\r
+* value to OR into the mask is: MyComp_ctComp__CMP_MASK.\r
+*\r
+* When CTW or One PPS is used as a wakeup source, the CyPmReadStatus()\r
+* function must be called upon wakeup with corresponding parameter. Please\r
+* refer to the CyPmReadStatus() API in the System Reference Guide for more\r
+* information.\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Reentrant:\r
+* No\r
+*\r
+* Side Effects and Restrictions:\r
+* For PSoC 5 silicon the wakeup source is not selectable. In this case the\r
+* wakeupSource argument is ignored and any of the available wakeup sources will\r
+* wake the device.\r
+*\r
+* If a wakeupTime other than NONE is specified, then upon exit the state of the\r
+* specified timer will be left as specified by wakeupTime with the timer\r
+* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is\r
+* used as wake up time) will be left started.\r
+*\r
+* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to\r
+* measure Hibernate/Sleep regulator settling time after a reset. The holdoff\r
+* delay is measured using rising edges of the 1 kHz ILO.\r
+*\r
+* For PSoC 3 silicon hardware buzz should be disabled before entering a sleep\r
+* power mode. It is disabled by PSoC Creator during startup.\r
+* If a Low Voltage Interrupt (LVI), High Voltage Interrupt (HVI) or Brown Out\r
+* detect (power supply supervising capabilities) are required in a design\r
+* during sleep, use the Central Time Wheel (CTW) to periodically wake the\r
+* device, perform software buzz, and refresh the supervisory services. If LVI,\r
+* HVI, or Brown Out is not required, then use of the CTW is not required.\r
+* Refer to the device errata for more information.\r
+*\r
+*******************************************************************************/\r
+void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) \r
+{\r
+ uint8 interruptState;\r
+\r
+ /* Save current global interrupt enable and disable it */\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+\r
+ #if(CY_PSOC3 || CY_PSOC5LP)\r
+\r
+ /***********************************************************************\r
+ * The Hibernate/Sleep regulator has a settling time after a reset.\r
+ * During this time, the system ignores requests to enter Sleep and\r
+ * Hibernate modes. The holdoff delay is measured using rising edges of\r
+ * the 1 kHz ILO.\r
+ ***********************************************************************/\r
+ if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q))\r
+ {\r
+ /* Disable hold off - no action on restore */\r
+ CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK;\r
+ }\r
+ else\r
+ {\r
+ /* Abort, device is not ready for low power mode entry */\r
+\r
+ /* Restore global interrupt enable state */\r
+ CyExitCriticalSection(interruptState);\r
+\r
+ return;\r
+ }\r
+\r
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+\r
+ #if(CY_PSOC3)\r
+\r
+ /* Silicon Revision ID is below TO6 */\r
+ if(CYDEV_CHIP_REV_ACTUAL < 5u)\r
+ {\r
+ /* Hardware buzz expected to be disabled in Sleep mode */\r
+ CYASSERT(0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ));\r
+\r
+ /* LVI/HVI requires hardware buzz to be enabled */\r
+ if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN |\r
+ CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN)))\r
+ {\r
+ CYASSERT(0u != 0u);\r
+ }\r
+ }\r
+\r
+ #endif /* (CY_PSOC3) */\r
+\r
+\r
+ /*******************************************************************************\r
+ * For ARM-based devices, an interrupt is required for the CPU to wake up. The\r
+ * Power Management implementation assumes that wakeup time is configured with a\r
+ * separate component (component-based wakeup time configuration) for an\r
+ * interrupt to be issued on terminal count. For more information, refer to the\r
+ * Wakeup Time Configuration section of System Reference Guide.\r
+ *******************************************************************************/\r
+ #if(CY_PSOC5)\r
+\r
+ /* Arguments expected to be 0 */\r
+ CYASSERT(PM_SLEEP_TIME_NONE == wakeupTime);\r
+\r
+ #if(CY_PSOC5A)\r
+\r
+ /* The wakeupSource argument expected to be 0 */\r
+ CYASSERT(PM_SLEEP_SRC_NONE == wakeupSource);\r
+\r
+ if(0u != wakeupSource)\r
+ {\r
+ /* To remove unreferenced local variable warning */\r
+ }\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+ if(0u != wakeupTime)\r
+ {\r
+ /* To remove unreferenced local variable warning */\r
+ }\r
+\r
+ #endif /* (CY_PSOC5) */\r
+\r
+\r
+ /* Prepare hardware for Sleep mode */\r
+ CyPmSlpSaveSet();\r
+\r
+\r
+ #if(CY_PSOC3)\r
+\r
+ /* CTW - save current and set new configuration */\r
+ if((wakeupTime >= PM_SLEEP_TIME_CTW_2MS) && (wakeupTime <= PM_SLEEP_TIME_CTW_4096MS))\r
+ {\r
+ /* Save current and set new configuration of the CTW */\r
+ CyPmCtwSetInterval((uint8)(wakeupTime - 1u));\r
+\r
+ /* Include associated timer to the wakeupSource */\r
+ wakeupSource |= PM_SLEEP_SRC_CTW;\r
+ }\r
+\r
+ /* 1PPS - save current and set new configuration */\r
+ if(PM_SLEEP_TIME_ONE_PPS == wakeupTime)\r
+ {\r
+ /* Save current and set new configuration of the 1PPS */\r
+ CyPmOppsSet();\r
+\r
+ /* Include associated timer to the wakeupSource */\r
+ wakeupSource |= PM_SLEEP_SRC_ONE_PPS;\r
+ }\r
+\r
+ #endif /* (CY_PSOC3) */\r
+\r
+\r
+ #if(!CY_PSOC5A)\r
+\r
+ /* Save and set new wake up configuration */\r
+\r
+ /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */\r
+ cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG;\r
+ CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u);\r
+\r
+ /* Comparators */\r
+ cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG;\r
+ CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK);\r
+\r
+ /* LCD */\r
+ cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG;\r
+ CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u));\r
+\r
+ #endif /* (!CY_PSOC5A) */\r
+\r
+\r
+ /*******************************************************************\r
+ * Do not use merge region below unless any component datasheet\r
+ * suggest to do so.\r
+ *******************************************************************/\r
+ /* `#START CY_PM_JUST_BEFORE_SLEEP` */\r
+\r
+ /* `#END` */\r
+\r
+\r
+ /* Last moment IMO frequency change */\r
+ if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK))\r
+ {\r
+ /* IMO frequency is 12 MHz */\r
+ cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED;\r
+ }\r
+ else\r
+ {\r
+ /* IMO frequency is not 12 MHz */\r
+ cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED;\r
+\r
+ /* Save IMO frequency */\r
+ cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK;\r
+\r
+ /* Set IMO frequency to 12 MHz */\r
+ CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK));\r
+ }\r
+\r
+ /* Switch to the Sleep mode */\r
+ CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_SLEEP);\r
+\r
+ /* Recommended readback. */\r
+ (void) CY_PM_MODE_CSR_REG;\r
+\r
+ /* Two recommended NOPs to get into the mode. */\r
+ CY_NOP;\r
+ CY_NOP;\r
+\r
+ /* Execute WFI instruction (for ARM-based devices only) */\r
+ CY_PM_WFI;\r
+\r
+ /* Point of return from Sleep Mode */\r
+\r
+ /* Restore last moment IMO frequency change */\r
+ if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz)\r
+ {\r
+ CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ_MASK))) |\r
+ cyPmBackup.imoActFreq;\r
+ }\r
+\r
+\r
+ /*******************************************************************\r
+ * Do not use merge region below unless any component datasheet\r
+ * suggest to do so.\r
+ *******************************************************************/\r
+ /* `#START CY_PM_JUST_AFTER_WAKEUP_FROM_SLEEP` */\r
+\r
+ /* `#END` */\r
+\r
+\r
+ /* Restore hardware configuration */\r
+ CyPmSlpRestore();\r
+\r
+\r
+ #if(!CY_PSOC5A)\r
+\r
+ /* Restore current wake up configuration */\r
+ CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0;\r
+ CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1;\r
+ CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2;\r
+\r
+ #endif /* (!CY_PSOC5A) */\r
+\r
+ /* Restore global interrupt enable state */\r
+ CyExitCriticalSection(interruptState);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPmHibernate\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Puts the part into the Hibernate state.\r
+*\r
+* PSoC 3 and PSoC 5LP:\r
+* Before switching to Hibernate, the current status of the PICU wakeup source\r
+* bit is saved and then set. This configures the device to wake up from the\r
+* PICU. Make sure you have at least one pin configured to generate a PICU\r
+* interrupt. For pin Px.y, the register "PICU_INTTYPE_PICUx_INTTYPEy" controls\r
+* the PICU behavior. In the TRM, this register is "PICU[0..15]_INTTYPE[0..7]."\r
+* In the Pins component datasheet, this register is referred to as the IRQ\r
+* option. Once the wakeup occurs, the PICU wakeup source bit is restored and\r
+* the PSoC returns to the Active state.\r
+*\r
+* PSoC 5:\r
+* The only method supported for waking up from the Hibernate state is a\r
+* hardware reset of the device. The PICU wakeup source cannot be used\r
+* reliably, so the PICU interrupt sources are automatically disabled by this\r
+* function before putting the device into the Hibernate state.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Reentrant:\r
+* No\r
+*\r
+* Side Effects:\r
+* Applications must wait 20 us before re-entering hibernate or sleep after\r
+* waking up from hibernate. The 20 us allows the sleep regulator time to\r
+* stabilize before the next hibernate / sleep event occurs. The 20 us\r
+* requirement begins when the device wakes up. There is no hardware check that\r
+* this requirement is met. The specified delay should be done on ISR entry.\r
+*\r
+* After wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is\r
+* instance name of the Pins component) function must be called to clear the\r
+* latched pin events to allow proper Hibernate mode entry andd to enable\r
+* detection of future events.\r
+*\r
+* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to\r
+* measure Hibernate/Sleep regulator settling time after a reset. The holdoff\r
+* delay is measured using rising edges of the 1 kHz ILO.\r
+*\r
+*******************************************************************************/\r
+void CyPmHibernate(void) \r
+{\r
+ uint8 interruptState;\r
+\r
+ /* Save current global interrupt enable and disable it */\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ #if(CY_PSOC3 || CY_PSOC5LP)\r
+\r
+ /***********************************************************************\r
+ * The Hibernate/Sleep regulator has a settling time after a reset.\r
+ * During this time, the system ignores requests to enter Sleep and\r
+ * Hibernate modes. The holdoff delay is measured using rising edges of\r
+ * the 1 kHz ILO.\r
+ ***********************************************************************/\r
+ if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q))\r
+ {\r
+ /* Disable hold off - no action on restore */\r
+ CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK;\r
+ }\r
+ else\r
+ {\r
+ /* Abort, device is not ready for low power mode entry */\r
+\r
+ /* Restore global interrupt enable state */\r
+ CyExitCriticalSection(interruptState);\r
+\r
+ return;\r
+ }\r
+\r
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+ /* Prepare device for proper Hibernate mode entry */\r
+ CyPmHibSaveSet();\r
+\r
+\r
+ #if(!CY_PSOC5A)\r
+\r
+ /* Save and enable only wakeup on PICU */\r
+ cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG;\r
+ CY_PM_WAKEUP_CFG0_REG = CY_PM_WAKEUP_PICU;\r
+\r
+ cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG;\r
+ CY_PM_WAKEUP_CFG1_REG = 0x00u;\r
+\r
+ cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG;\r
+ CY_PM_WAKEUP_CFG2_REG = 0x00u;\r
+\r
+ #endif /* (!CY_PSOC5A) */\r
+\r
+\r
+ /* Last moment IMO frequency change */\r
+ if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK))\r
+ {\r
+ /* IMO frequency is 12 MHz */\r
+ cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED;\r
+ }\r
+ else\r
+ {\r
+ /* IMO frequency is not 12 MHz */\r
+ cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED;\r
+\r
+ /* Save IMO frequency */\r
+ cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK;\r
+\r
+ /* Set IMO frequency to 12 MHz */\r
+ CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK));\r
+ }\r
+\r
+\r
+ /* Switch to Hibernate Mode */\r
+ CY_PM_MODE_CSR_REG = (CY_PM_MODE_CSR_REG & ((uint8) (~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_HIBERNATE;\r
+\r
+ /* Recommended readback. */\r
+ (void) CY_PM_MODE_CSR_REG;\r
+\r
+ /* Two recommended NOPs to get into the mode. */\r
+ CY_NOP;\r
+ CY_NOP;\r
+\r
+ /* Execute WFI instruction (for ARM-based devices only) */\r
+ CY_PM_WFI;\r
+\r
+ /* Point of return from Hibernate mode */\r
+\r
+\r
+ /* Restore last moment IMO frequency change */\r
+ if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz)\r
+ {\r
+ CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ_MASK))) |\r
+ cyPmBackup.imoActFreq;\r
+ }\r
+\r
+\r
+ /* Restore device for proper Hibernate mode exit*/\r
+ CyPmHibRestore();\r
+\r
+\r
+ #if(!CY_PSOC5A)\r
+\r
+ /* Restore current wake up configuration */\r
+ CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0;\r
+ CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1;\r
+ CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2;\r
+\r
+ #endif /* (!CY_PSOC5A) */\r
+\r
+ /* Restore global interrupt enable state */\r
+ CyExitCriticalSection(interruptState);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPmReadStatus\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Manages the Power Manager Interrupt Status Register. This register has the\r
+* interrupt status for the one pulse per second, central timewheel and fast\r
+* timewheel timers. This hardware register clears on read. To allow for only\r
+* clearing the bits of interest and preserving the other bits, this function\r
+* uses a shadow register that retains the state. This function reads the\r
+* status register and ORs that value with the shadow register. That is the\r
+* value that is returned. Then the bits in the mask that are set are cleared\r
+* from this value and written back to the shadow register.\r
+*\r
+* Note You must call this function within 1 ms (1 clock cycle of the ILO)\r
+* after a CTW event has occurred.\r
+*\r
+* Parameters:\r
+* mask: Bits in the shadow register to clear.\r
+*\r
+* Define Source\r
+* CY_PM_FTW_INT Fast Timewheel\r
+* CY_PM_CTW_INT Central Timewheel\r
+* CY_PM_ONEPPS_INT One Pulse Per Second\r
+*\r
+* Return:\r
+* Status. Same bits values as the mask parameter.\r
+*\r
+*******************************************************************************/\r
+uint8 CyPmReadStatus(uint8 mask) \r
+{\r
+ static uint8 interruptStatus;\r
+ uint8 interruptState;\r
+ uint8 tmpStatus;\r
+\r
+ /* Enter critical section */\r
+ interruptState = CyEnterCriticalSection();\r
+\r
+ /* Save value of the register, copy it and clear desired bit */\r
+ interruptStatus |= CY_PM_INT_SR_REG;\r
+ tmpStatus = interruptStatus;\r
+ interruptStatus &= ((uint8)(~mask));\r
+\r
+ /* Exit critical section */\r
+ CyExitCriticalSection(interruptState);\r
+\r
+ return(tmpStatus);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPmHibSaveSet\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Prepare device for proper Hibernate low power mode entry:\r
+* - Disables I2C backup regulator\r
+* - Save state of I2C backup regulator (PSoC 5)\r
+* - Saves ILO power down mode state and enable it (all but PSoC 5)\r
+* - Saves state of 1 kHz and 100 kHz ILO and disable them (all but PSoC 5)\r
+* - Disables sleep regulator and shorts vccd to vpwrsleep (all but PSoC 5)\r
+* - Save LVI/HVI configuration and disable them - CyPmHviLviSaveDisable()\r
+* - CyPmHibSlpSaveSet() function is called\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Reentrant:\r
+* No\r
+*\r
+*******************************************************************************/\r
+static void CyPmHibSaveSet(void) \r
+{\r
+ /* I2C backup reg must be off when the sleep regulator is unavailable */\r
+ if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP))\r
+ {\r
+ /***********************************************************************\r
+ * If I2C backup regulator is enabled, all the fixed-function registers\r
+ * store their values while device is in low power mode, otherwise their\r
+ * configuration is lost. The I2C API makes a decision to restore or not\r
+ * to restore I2C registers based on this. If this regulator will be\r
+ * disabled and then enabled, I2C API will suppose that I2C block\r
+ * registers preserved their values, while this is not true. So, the\r
+ * backup regulator is disabled. And its value is restored only for\r
+ * and PSoC 5 devices. The I2C sleep APIs is responsible for restoration.\r
+ ***********************************************************************/\r
+\r
+ #if(CY_PSOC5A)\r
+\r
+ cyPmBackup.i2cRegBackup = CY_PM_ENABLED;\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+ /* Disable I2C backup register */\r
+ CY_PM_PWRSYS_CR1_REG &= ((uint8)(~CY_PM_PWRSYS_CR1_I2CREG_BACKUP));\r
+ }\r
+ else\r
+ {\r
+ #if(CY_PSOC5A)\r
+\r
+ /* Save disabled state of the I2C backup regulator */\r
+ cyPmBackup.i2cRegBackup = CY_PM_DISABLED;\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+ }\r
+\r
+\r
+ #if(!CY_PSOC5A)\r
+\r
+ /* Save current ILO power mode and ensure low power mode */\r
+ cyPmBackup.iloPowerMode = CyILO_SetPowerMode(CY_PM_POWERDOWN_MODE);\r
+\r
+ /* Save current 1kHz ILO enable state. Disabled automatically. */\r
+ cyPmBackup.ilo1kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_1K)) ?\r
+ CY_PM_DISABLED : CY_PM_ENABLED;\r
+\r
+ /* Save current 100kHz ILO enable state. Disabled automatically. */\r
+ cyPmBackup.ilo100kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_100K)) ?\r
+ CY_PM_DISABLED : CY_PM_ENABLED;\r
+\r
+\r
+ /* Disable the sleep regulator and shorts vccd to vpwrsleep */\r
+ if(0u == (CY_PM_PWRSYS_SLP_TR_REG & CY_PM_PWRSYS_SLP_TR_BYPASS))\r
+ {\r
+ /* Save current bypass state */\r
+ cyPmBackup.slpTrBypass = CY_PM_DISABLED;\r
+ CY_PM_PWRSYS_SLP_TR_REG |= CY_PM_PWRSYS_SLP_TR_BYPASS;\r
+ }\r
+ else\r
+ {\r
+ cyPmBackup.slpTrBypass = CY_PM_ENABLED;\r
+ }\r
+\r
+ /* LPCOMPs are always enabled (even when BOTH ext_vccd=1 and ext_vcca=1)*/\r
+\r
+ #endif /* (!CY_PSOC5A) */\r
+\r
+\r
+ /* Device is PSoC 5 and the revision is ES1 or earlier. */\r
+ #if(CY_PSOC5A)\r
+\r
+ /* Disable all the PICU interrupts */\r
+ CyPmDisablePicuInterrupts();\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+\r
+ /***************************************************************************\r
+ * LVI/HVI must be disabled in Hibernate\r
+ ***************************************************************************/\r
+\r
+ /* Save LVI/HVI configuration and disable them */\r
+ CyPmHviLviSaveDisable();\r
+\r
+\r
+ /* Make the same preparations for Hibernate and Sleep modes */\r
+ CyPmHibSlpSaveSet();\r
+\r
+\r
+ /***************************************************************************\r
+ * Save and set power mode wakeup trim registers\r
+ ***************************************************************************/\r
+ #if(CY_PSOC3 || CY_PSOC5LP)\r
+\r
+ cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG;\r
+ cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG;\r
+\r
+ CY_PM_PWRSYS_WAKE_TR0_REG = CY_PM_PWRSYS_WAKE_TR0;\r
+ CY_PM_PWRSYS_WAKE_TR1_REG = CY_PM_PWRSYS_WAKE_TR1;\r
+\r
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPmHibRestore\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Restore device for proper Hibernate mode exit:\r
+* - Restore LVI/HVI configuration - call CyPmHviLviRestore()\r
+* - CyPmHibSlpSaveRestore() function is called\r
+* - Restores state of I2C backup regulator (PSoC 5)\r
+* - Restores ILO power down mode state and enable it (all but PSoC 5)\r
+* - Restores state of 1 kHz and 100 kHz ILO and disable them (all but PSoC 5)\r
+* - Restores sleep regulator settings (all but PSoC 5)\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+static void CyPmHibRestore(void) \r
+{\r
+ /* Restore LVI/HVI configuration */\r
+ CyPmHviLviRestore();\r
+\r
+ /* Restore the same configuration for Hibernate and Sleep modes */\r
+ CyPmHibSlpRestore();\r
+\r
+ #if(CY_PSOC5A)\r
+\r
+ /* Restore I2C backup regulator configuration */\r
+ if(CY_PM_ENABLED == cyPmBackup.i2cRegBackup)\r
+ {\r
+ /* Enable I2C backup regulator state */\r
+ CY_PM_PWRSYS_CR1_REG |= CY_PM_PWRSYS_CR1_I2CREG_BACKUP;\r
+ }\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+\r
+ #if(!CY_PSOC5A)\r
+\r
+ /* Restore 1kHz ILO enable state */\r
+ if(CY_PM_ENABLED == cyPmBackup.ilo1kEnable)\r
+ {\r
+ /* Enable 1kHz ILO */\r
+ CyILO_Start1K();\r
+ }\r
+\r
+ /* Restore 100kHz ILO enable state */\r
+ if(CY_PM_ENABLED == cyPmBackup.ilo100kEnable)\r
+ {\r
+ /* Enable 100kHz ILO */\r
+ CyILO_Start100K();\r
+ }\r
+\r
+ /* Restore ILO power mode */\r
+ (void) CyILO_SetPowerMode(cyPmBackup.iloPowerMode);\r
+\r
+\r
+ if(CY_PM_DISABLED == cyPmBackup.slpTrBypass)\r
+ {\r
+ /* Enable the sleep regulator */\r
+ CY_PM_PWRSYS_SLP_TR_REG &= ((uint8)(~CY_PM_PWRSYS_SLP_TR_BYPASS));\r
+ }\r
+\r
+ #endif /* (!CY_PSOC5A) */\r
+\r
+\r
+ /***************************************************************************\r
+ * Restore power mode wakeup trim registers\r
+ ***************************************************************************/\r
+ #if(CY_PSOC3 || CY_PSOC5LP)\r
+\r
+ CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0;\r
+ CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1;\r
+\r
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPmCtwSetInterval\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Performs CTW configuration:\r
+* - Disables CTW interrupt\r
+* - Enables 1 kHz ILO\r
+* - Sets new CTW interval\r
+*\r
+* Parameters:\r
+* ctwInterval: the CTW interval to be set.\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Side Effects:\r
+* Enables ILO 1 KHz clock and leaves it enabled.\r
+*\r
+*******************************************************************************/\r
+void CyPmCtwSetInterval(uint8 ctwInterval) \r
+{\r
+ /* Disable CTW interrupt enable */\r
+ CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_IE));\r
+\r
+ /* Enable 1kHz ILO (required for CTW operation) */\r
+ CyILO_Start1K();\r
+\r
+ /* Interval could be set only while CTW is disabled */\r
+ if(0u != (CY_PM_TW_CFG2_REG & CY_PM_CTW_EN))\r
+ {\r
+ /* Set CTW interval if needed */\r
+ if(CY_PM_TW_CFG1_REG != ctwInterval)\r
+ {\r
+ /* Disable the CTW, set new CTW interval and enable it again */\r
+ CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_EN));\r
+ CY_PM_TW_CFG1_REG = ctwInterval;\r
+ CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN;\r
+ } /* Required interval is already set */\r
+ }\r
+ else\r
+ {\r
+ /* Set CTW interval if needed */\r
+ if(CY_PM_TW_CFG1_REG != ctwInterval)\r
+ {\r
+ /* Set the new CTW interval. Could be changed if CTW is disabled */\r
+ CY_PM_TW_CFG1_REG = ctwInterval;\r
+ } /* Required interval is already set */\r
+\r
+ /* Enable the CTW */\r
+ CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN;\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPmOppsSet\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Performs 1PPS configuration:\r
+* - Starts 32 KHz XTAL\r
+* - Disables 1PPS interupts\r
+* - Enables 1PPS\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+void CyPmOppsSet(void) \r
+{\r
+ /* Enable 32kHz XTAL if needed */\r
+ if(0u == (CY_PM_SLOWCLK_X32_CR_REG & CY_PM_X32_CR_X32EN))\r
+ {\r
+ /* Enable 32kHz XTAL */\r
+ CyXTAL_32KHZ_Start();\r
+ }\r
+\r
+ /* Disable 1PPS interrupt enable */\r
+ CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_1PPS_IE));\r
+\r
+ /* Enable 1PPS operation */\r
+ CY_PM_TW_CFG2_REG |= CY_PM_1PPS_EN;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPmFtwSetInterval\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Performs FTW configuration:\r
+* - Disables FTW interrupt\r
+* - Enables 100 kHz ILO\r
+* - Sets new FTW interval.\r
+*\r
+* Parameters:\r
+* ftwInterval - FTW counter interval.\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Side Effects:\r
+* Enables ILO 100 KHz clock and leaves it enabled.\r
+*\r
+*******************************************************************************/\r
+void CyPmFtwSetInterval(uint8 ftwInterval) \r
+{\r
+ /* Disable FTW interrupt enable */\r
+ CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_IE));\r
+\r
+ /* Enable 100kHz ILO */\r
+ CyILO_Start100K();\r
+\r
+ /* Iterval could be set only while FTW is disabled */\r
+ if(0u != (CY_PM_TW_CFG2_REG & CY_PM_FTW_EN))\r
+ {\r
+ /* Disable FTW, set new FTW interval if needed and enable it again */\r
+ if(CY_PM_TW_CFG0_REG != ftwInterval)\r
+ {\r
+ /* Disable the CTW, set new CTW interval and enable it again */\r
+ CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_EN));\r
+ CY_PM_TW_CFG0_REG = ftwInterval;\r
+ CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN;\r
+ } /* Required interval is already set */\r
+ }\r
+ else\r
+ {\r
+ /* Set new FTW counter interval if needed. FTW is disabled. */\r
+ if(CY_PM_TW_CFG0_REG != ftwInterval)\r
+ {\r
+ /* Set the new CTW interval. Could be changed if CTW is disabled */\r
+ CY_PM_TW_CFG0_REG = ftwInterval;\r
+ } /* Required interval is already set */\r
+\r
+ /* Enable the FTW */\r
+ CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN;\r
+ }\r
+}\r
+\r
+\r
+#if(CY_PSOC5A)\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyPmSavePicuInterrupts\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Saves PICU interrupt type registers to the backup structure.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Reentrant:\r
+ * No\r
+ *\r
+ *******************************************************************************/\r
+ static void CyPmSavePicuInterrupts(void) \r
+ {\r
+ /* Save all the PICU interrupt type */\r
+ (void) memcpy((void *) &cyPmBackup.picuIntType[0u],\r
+ (void *) CY_PM_PICU_0_6_INT_BASE,\r
+ CY_PM_PICU_0_6_INT_SIZE);\r
+\r
+ (void) memcpy((void *) &cyPmBackup.picuIntType[CY_PM_PICU_0_6_INT_SIZE],\r
+ (void *) CY_PM_PICU_12_INT_BASE,\r
+ CY_PM_PICU_12_INT_SIZE);\r
+\r
+ (void) memcpy((void *) &cyPmBackup.picuIntType[CY_PM_PICU_0_6_INT_SIZE + CY_PM_PICU_12_INT_SIZE],\r
+ (void *) CY_PM_PICU_15_INT_BASE,\r
+ CY_PM_PICU_15_INT_SIZE);\r
+\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyPmDisablePicuInterrupts\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Disableds PICU interrupts.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ static void CyPmDisablePicuInterrupts(void) \r
+ {\r
+ /* Disable all the PICU interrupts */\r
+ (void) memset((void *) CY_PM_PICU_0_6_INT_BASE, 0, CY_PM_PICU_0_6_INT_SIZE);\r
+ (void) memset((void *) CY_PM_PICU_12_INT_BASE, 0, CY_PM_PICU_12_INT_SIZE );\r
+ (void) memset((void *) CY_PM_PICU_15_INT_BASE, 0, CY_PM_PICU_15_INT_SIZE );\r
+ }\r
+\r
+\r
+ /*******************************************************************************\r
+ * Function Name: CyPmRestorePicuInterrupts\r
+ ********************************************************************************\r
+ *\r
+ * Summary:\r
+ * Restores PICU interrupt type registers from the backup structure.\r
+ *\r
+ * Parameters:\r
+ * None\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ *******************************************************************************/\r
+ static void CyPmRestorePicuInterrupts(void) \r
+ {\r
+ /* Save all the PICU interrupt type */\r
+ (void) memcpy((void *) CY_PM_PICU_0_6_INT_BASE,\r
+ (void *) &cyPmBackup.picuIntType[0u],\r
+ CY_PM_PICU_0_6_INT_SIZE);\r
+\r
+ (void) memcpy((void *) CY_PM_PICU_12_INT_BASE,\r
+ (void *) &cyPmBackup.picuIntType[CY_PM_PICU_0_6_INT_SIZE],\r
+ CY_PM_PICU_12_INT_SIZE);\r
+\r
+ (void) memcpy((void *) CY_PM_PICU_15_INT_BASE,\r
+ (void *) &cyPmBackup.picuIntType[CY_PM_PICU_0_6_INT_SIZE + CY_PM_PICU_12_INT_SIZE],\r
+ CY_PM_PICU_15_INT_SIZE);\r
+\r
+ }\r
+\r
+#endif /* (CY_PSOC5A) */\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPmSlpSaveSet\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Prepare device for proper Sleep low power mode entry:\r
+* - Prepare CTW for Sleep mode entry (PSoC 5)\r
+* * Save timewheels configuration\r
+* * Disable FTW and 1PPS (enable and interrupt)\r
+* * Reset CTW\r
+* * Save and disable PICU interrupts\r
+* * Save and disable PRES-A and PRES-D\r
+* - Save and disable LVI/HVI configuration (PSoC 5)\r
+* - Save and set to max buzz interval (PSoC 5)\r
+* - CyPmHibSlpSaveSet() function is called\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Reentrant:\r
+* No\r
+*\r
+*******************************************************************************/\r
+static void CyPmSlpSaveSet(void) \r
+{\r
+ #if(CY_PSOC5A)\r
+\r
+ /* Preserve the Timewheel Configuration Register 2 */\r
+ cyPmBackup.pmTwCfg2 = CY_PM_TW_CFG2_REG;\r
+\r
+ /* Clear the enable and interrupt enables for the FTW and ONEPPS */\r
+ CY_PM_TW_CFG2_REG &= ((uint8)(~(CY_PM_FTW_IE | CY_PM_FTW_EN | CY_PM_1PPS_EN | CY_PM_1PPS_IE)));\r
+\r
+ /* Reset free-running CTW counter to 0 and held it there */\r
+ CY_PM_WDT_CFG_REG |= CY_PM_WDT_CFG_CTW_RESET;\r
+\r
+ /* Exit CTW counter reset state */\r
+ CY_PM_WDT_CFG_REG &= ((uint8)(~CY_PM_WDT_CFG_CTW_RESET));\r
+\r
+ /* Save and disable PICU interrupts */\r
+ CyPmSavePicuInterrupts();\r
+ CyPmDisablePicuInterrupts();\r
+\r
+ /* Save and disable PRES-A and PRES-D */\r
+ cyPmBackup.pres1 = CY_PM_RESET_CR1_REG & CY_PM_RESET_CR1_DIS_PRES1;\r
+ cyPmBackup.pres2 = CY_PM_RESET_CR3_REG & CY_PM_RESET_CR3_DIS_PRES2;\r
+ CY_PM_RESET_CR1_REG &= ((uint8)(~CY_PM_RESET_CR1_DIS_PRES1));\r
+ CY_PM_RESET_CR3_REG &= ((uint8)(~CY_PM_RESET_CR3_DIS_PRES2));\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+\r
+ #if(CY_PSOC5A)\r
+\r
+ /***************************************************************************\r
+ * LVI/HVI must be disabled as it doesn't work during buzzing.\r
+ *\r
+ * Using hardware buzz in conjunction with other device wakeup sources\r
+ * can cause the device to lockup, halting further code execution. The\r
+ * hardware buzz provides power supply supervising capability in sleep.\r
+ * It is enabled by default and there is no way to disable it. So the buzz\r
+ * interval is set to maximum (512 ms). The CTW must be configured to wake up\r
+ * at a rate less than hardware buzz interval.\r
+ ***************************************************************************/\r
+\r
+ /* Save and disable LVI/HVI */\r
+ CyPmHviLviSaveDisable();\r
+\r
+ /* Save buzz trim value */\r
+ cyPmBackup.buzzSleepTrim = CY_PM_PWRSYS_BUZZ_TR_REG & ((uint8)(~CY_PM_PWRSYS_BUZZ_TR_MASK));\r
+\r
+ /* Set buzz interval to maximum */\r
+ CY_PM_PWRSYS_BUZZ_TR_REG = CY_PM_PWRSYS_BUZZ_TR_512_TICKS |\r
+ (CY_PM_PWRSYS_BUZZ_TR_REG & CY_PM_PWRSYS_BUZZ_TR_MASK);\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+\r
+ /* Apply configuration that are same for Sleep and Hibernate */\r
+ CyPmHibSlpSaveSet();\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPmSlpRestore\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Restore device for proper Sleep mode exit:\r
+* - Restore timewheel configuration (PSoC 5)\r
+* - Restore PRES-A and PRES-D (PSoC 5)\r
+* - Restore PICU interrupts (PSoC 5)\r
+* - Restore buzz sleep trim value (PSoC 5)\r
+* - Call to CyPmHibSlpSaveRestore()\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+static void CyPmSlpRestore(void) \r
+{\r
+ #if(CY_PSOC5A)\r
+\r
+ /* Restore the Timewheel Configuration Register 2 */\r
+ CY_PM_TW_CFG2_REG = cyPmBackup.pmTwCfg2;\r
+\r
+ /* Restore PICU interrupts */\r
+ CyPmRestorePicuInterrupts();\r
+\r
+ /* Restore PRES-A and PRES-D (assumed they were disabled) */\r
+ CY_PM_RESET_CR1_REG |= cyPmBackup.pres1;\r
+ CY_PM_RESET_CR3_REG |= cyPmBackup.pres2;\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+\r
+ #if(CY_PSOC5A)\r
+\r
+ /* Restore LVI/HVI configuration */\r
+ CyPmHviLviRestore();\r
+\r
+ /* Restore buzz sleep trim value */\r
+ CY_PM_PWRSYS_BUZZ_TR_REG = cyPmBackup.buzzSleepTrim |\r
+ (CY_PM_PWRSYS_BUZZ_TR_REG & CY_PM_PWRSYS_BUZZ_TR_MASK);\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+\r
+ /* Restore configuration that are same for Sleep and Hibernate */\r
+ CyPmHibSlpRestore();\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPmHibSlpSaveSet\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* This API is used for preparing device for Sleep and Hibernate low power\r
+* modes entry:\r
+* - Saves COMP, VIDAC, DSM and SAR routing connections (PSoC 5)\r
+* - Saves SC/CT routing connections (PSoC 3/5/5LP)\r
+* - Disables Serial Wire Viewer (SWV) (PSoC 3)\r
+* - Save boost reference selection and set it to internal\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Reentrant:\r
+* No\r
+*\r
+*******************************************************************************/\r
+static void CyPmHibSlpSaveSet(void) \r
+{\r
+ #if(CY_PSOC5A)\r
+\r
+ /* Save CMP routing registers */\r
+ cyPmBackup.cmpData[0u] = CY_GET_REG8(CYREG_CMP0_SW0);\r
+ cyPmBackup.cmpData[1u] = CY_GET_REG8(CYREG_CMP0_SW2);\r
+ cyPmBackup.cmpData[2u] = CY_GET_REG8(CYREG_CMP0_SW3);\r
+ cyPmBackup.cmpData[3u] = CY_GET_REG8(CYREG_CMP0_SW4);\r
+ cyPmBackup.cmpData[4u] = CY_GET_REG8(CYREG_CMP0_SW6);\r
+\r
+ cyPmBackup.cmpData[5u] = CY_GET_REG8(CYREG_CMP1_SW0);\r
+ cyPmBackup.cmpData[6u] = CY_GET_REG8(CYREG_CMP1_SW2);\r
+ cyPmBackup.cmpData[7u] = CY_GET_REG8(CYREG_CMP1_SW3);\r
+ cyPmBackup.cmpData[8u] = CY_GET_REG8(CYREG_CMP1_SW4);\r
+ cyPmBackup.cmpData[9u] = CY_GET_REG8(CYREG_CMP1_SW6);\r
+\r
+ cyPmBackup.cmpData[10u] = CY_GET_REG8(CYREG_CMP2_SW0);\r
+ cyPmBackup.cmpData[11u] = CY_GET_REG8(CYREG_CMP2_SW2);\r
+ cyPmBackup.cmpData[12u] = CY_GET_REG8(CYREG_CMP2_SW3);\r
+ cyPmBackup.cmpData[13u] = CY_GET_REG8(CYREG_CMP2_SW4);\r
+ cyPmBackup.cmpData[14u] = CY_GET_REG8(CYREG_CMP2_SW6);\r
+\r
+ cyPmBackup.cmpData[15u] = CY_GET_REG8(CYREG_CMP3_SW0);\r
+ cyPmBackup.cmpData[16u] = CY_GET_REG8(CYREG_CMP3_SW2);\r
+ cyPmBackup.cmpData[17u] = CY_GET_REG8(CYREG_CMP3_SW3);\r
+ cyPmBackup.cmpData[18u] = CY_GET_REG8(CYREG_CMP3_SW4);\r
+ cyPmBackup.cmpData[19u] = CY_GET_REG8(CYREG_CMP3_SW6);\r
+\r
+\r
+ /* Clear CMP routing registers */\r
+ CY_SET_REG8(CYREG_CMP0_SW0 , 0u);\r
+ CY_SET_REG8(CYREG_CMP0_SW2 , 0u);\r
+ CY_SET_REG8(CYREG_CMP0_SW3 , 0u);\r
+ CY_SET_REG8(CYREG_CMP0_SW4 , 0u);\r
+ CY_SET_REG8(CYREG_CMP0_SW6 , 0u);\r
+\r
+ CY_SET_REG8(CYREG_CMP1_SW0 , 0u);\r
+ CY_SET_REG8(CYREG_CMP1_SW2 , 0u);\r
+ CY_SET_REG8(CYREG_CMP1_SW3 , 0u);\r
+ CY_SET_REG8(CYREG_CMP1_SW4 , 0u);\r
+ CY_SET_REG8(CYREG_CMP1_SW6 , 0u);\r
+\r
+ CY_SET_REG8(CYREG_CMP2_SW0 , 0u);\r
+ CY_SET_REG8(CYREG_CMP2_SW2 , 0u);\r
+ CY_SET_REG8(CYREG_CMP2_SW3 , 0u);\r
+ CY_SET_REG8(CYREG_CMP2_SW4 , 0u);\r
+ CY_SET_REG8(CYREG_CMP2_SW6 , 0u);\r
+\r
+ CY_SET_REG8(CYREG_CMP3_SW0 , 0u);\r
+ CY_SET_REG8(CYREG_CMP3_SW2 , 0u);\r
+ CY_SET_REG8(CYREG_CMP3_SW3 , 0u);\r
+ CY_SET_REG8(CYREG_CMP3_SW4 , 0u);\r
+ CY_SET_REG8(CYREG_CMP3_SW6 , 0u);\r
+\r
+\r
+ /* Save DAC routing registers */\r
+ cyPmBackup.dacData[0u] = CY_GET_REG8(CYREG_DAC0_SW0);\r
+ cyPmBackup.dacData[1u] = CY_GET_REG8(CYREG_DAC0_SW2);\r
+ cyPmBackup.dacData[2u] = CY_GET_REG8(CYREG_DAC0_SW3);\r
+ cyPmBackup.dacData[3u] = CY_GET_REG8(CYREG_DAC0_SW4);\r
+\r
+ cyPmBackup.dacData[4u] = CY_GET_REG8(CYREG_DAC1_SW0);\r
+ cyPmBackup.dacData[5u] = CY_GET_REG8(CYREG_DAC1_SW2);\r
+ cyPmBackup.dacData[6u] = CY_GET_REG8(CYREG_DAC1_SW3);\r
+ cyPmBackup.dacData[7u] = CY_GET_REG8(CYREG_DAC1_SW4);\r
+\r
+ cyPmBackup.dacData[8u] = CY_GET_REG8(CYREG_DAC2_SW0);\r
+ cyPmBackup.dacData[9u] = CY_GET_REG8(CYREG_DAC2_SW2);\r
+ cyPmBackup.dacData[10u] = CY_GET_REG8(CYREG_DAC2_SW3);\r
+ cyPmBackup.dacData[11u] = CY_GET_REG8(CYREG_DAC2_SW4);\r
+\r
+ cyPmBackup.dacData[12u] = CY_GET_REG8(CYREG_DAC3_SW0);\r
+ cyPmBackup.dacData[13u] = CY_GET_REG8(CYREG_DAC3_SW2);\r
+ cyPmBackup.dacData[14u] = CY_GET_REG8(CYREG_DAC3_SW3);\r
+ cyPmBackup.dacData[15u] = CY_GET_REG8(CYREG_DAC3_SW4);\r
+\r
+ /* Clear DAC routing registers */\r
+ CY_SET_REG8(CYREG_DAC0_SW0 , 0u);\r
+ CY_SET_REG8(CYREG_DAC0_SW2 , 0u);\r
+ CY_SET_REG8(CYREG_DAC0_SW3 , 0u);\r
+ CY_SET_REG8(CYREG_DAC0_SW4 , 0u);\r
+\r
+ CY_SET_REG8(CYREG_DAC1_SW0 , 0u);\r
+ CY_SET_REG8(CYREG_DAC1_SW2 , 0u);\r
+ CY_SET_REG8(CYREG_DAC1_SW3 , 0u);\r
+ CY_SET_REG8(CYREG_DAC1_SW4 , 0u);\r
+\r
+ CY_SET_REG8(CYREG_DAC2_SW0 , 0u);\r
+ CY_SET_REG8(CYREG_DAC2_SW2 , 0u);\r
+ CY_SET_REG8(CYREG_DAC2_SW3 , 0u);\r
+ CY_SET_REG8(CYREG_DAC2_SW4 , 0u);\r
+\r
+ CY_SET_REG8(CYREG_DAC3_SW0 , 0u);\r
+ CY_SET_REG8(CYREG_DAC3_SW2 , 0u);\r
+ CY_SET_REG8(CYREG_DAC3_SW3 , 0u);\r
+ CY_SET_REG8(CYREG_DAC3_SW4 , 0u);\r
+\r
+\r
+ /* Save DSM routing registers */\r
+ cyPmBackup.dsmData[0u] = CY_GET_REG8(CYREG_DSM0_SW0);\r
+ cyPmBackup.dsmData[1u] = CY_GET_REG8(CYREG_DSM0_SW2);\r
+ cyPmBackup.dsmData[2u] = CY_GET_REG8(CYREG_DSM0_SW3);\r
+ cyPmBackup.dsmData[3u] = CY_GET_REG8(CYREG_DSM0_SW4);\r
+ cyPmBackup.dsmData[4u] = CY_GET_REG8(CYREG_DSM0_SW6);\r
+\r
+ /* Clear DSM routing registers */\r
+ CY_SET_REG8(CYREG_DSM0_SW0 , 0u);\r
+ CY_SET_REG8(CYREG_DSM0_SW2 , 0u);\r
+ CY_SET_REG8(CYREG_DSM0_SW3 , 0u);\r
+ CY_SET_REG8(CYREG_DSM0_SW4 , 0u);\r
+ CY_SET_REG8(CYREG_DSM0_SW6 , 0u);\r
+\r
+\r
+ /* Save SAR routing registers */\r
+ cyPmBackup.sarData[0u] = CY_GET_REG8(CYREG_SAR0_SW0);\r
+ cyPmBackup.sarData[1u] = CY_GET_REG8(CYREG_SAR0_SW2);\r
+ cyPmBackup.sarData[2u] = CY_GET_REG8(CYREG_SAR0_SW3);\r
+ cyPmBackup.sarData[3u] = CY_GET_REG8(CYREG_SAR0_SW4);\r
+ cyPmBackup.sarData[4u] = CY_GET_REG8(CYREG_SAR0_SW6);\r
+\r
+ cyPmBackup.sarData[5u] = CY_GET_REG8(CYREG_SAR1_SW0);\r
+ cyPmBackup.sarData[6u] = CY_GET_REG8(CYREG_SAR1_SW2);\r
+ cyPmBackup.sarData[7u] = CY_GET_REG8(CYREG_SAR1_SW3);\r
+ cyPmBackup.sarData[8u] = CY_GET_REG8(CYREG_SAR1_SW4);\r
+ cyPmBackup.sarData[9u] = CY_GET_REG8(CYREG_SAR1_SW6);\r
+\r
+\r
+ /* Clear SAR routing registers */\r
+ CY_SET_REG8(CYREG_SAR0_SW0 , 0u);\r
+ CY_SET_REG8(CYREG_SAR0_SW2 , 0u);\r
+ CY_SET_REG8(CYREG_SAR0_SW3 , 0u);\r
+ CY_SET_REG8(CYREG_SAR0_SW4 , 0u);\r
+ CY_SET_REG8(CYREG_SAR0_SW6 , 0u);\r
+\r
+ CY_SET_REG8(CYREG_SAR1_SW0 , 0u);\r
+ CY_SET_REG8(CYREG_SAR1_SW2 , 0u);\r
+ CY_SET_REG8(CYREG_SAR1_SW3 , 0u);\r
+ CY_SET_REG8(CYREG_SAR1_SW4 , 0u);\r
+ CY_SET_REG8(CYREG_SAR1_SW6 , 0u);\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+\r
+ #if(CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP)\r
+\r
+ /* Save SC/CT routing registers */\r
+ cyPmBackup.scctData[0u] = CY_GET_REG8(CYREG_SC0_SW0 );\r
+ cyPmBackup.scctData[1u] = CY_GET_REG8(CYREG_SC0_SW2 );\r
+ cyPmBackup.scctData[2u] = CY_GET_REG8(CYREG_SC0_SW3 );\r
+ cyPmBackup.scctData[3u] = CY_GET_REG8(CYREG_SC0_SW4 );\r
+ cyPmBackup.scctData[4u] = CY_GET_REG8(CYREG_SC0_SW6 );\r
+ cyPmBackup.scctData[5u] = CY_GET_REG8(CYREG_SC0_SW8 );\r
+ cyPmBackup.scctData[6u] = CY_GET_REG8(CYREG_SC0_SW10);\r
+\r
+ cyPmBackup.scctData[7u] = CY_GET_REG8(CYREG_SC1_SW0 );\r
+ cyPmBackup.scctData[8u] = CY_GET_REG8(CYREG_SC1_SW2 );\r
+ cyPmBackup.scctData[9u] = CY_GET_REG8(CYREG_SC1_SW3 );\r
+ cyPmBackup.scctData[10u] = CY_GET_REG8(CYREG_SC1_SW4 );\r
+ cyPmBackup.scctData[11u] = CY_GET_REG8(CYREG_SC1_SW6 );\r
+ cyPmBackup.scctData[12u] = CY_GET_REG8(CYREG_SC1_SW8 );\r
+ cyPmBackup.scctData[13u] = CY_GET_REG8(CYREG_SC1_SW10);\r
+\r
+ cyPmBackup.scctData[14u] = CY_GET_REG8(CYREG_SC2_SW0 );\r
+ cyPmBackup.scctData[15u] = CY_GET_REG8(CYREG_SC2_SW2 );\r
+ cyPmBackup.scctData[16u] = CY_GET_REG8(CYREG_SC2_SW3 );\r
+ cyPmBackup.scctData[17u] = CY_GET_REG8(CYREG_SC2_SW4 );\r
+ cyPmBackup.scctData[18u] = CY_GET_REG8(CYREG_SC2_SW6 );\r
+ cyPmBackup.scctData[19u] = CY_GET_REG8(CYREG_SC2_SW8 );\r
+ cyPmBackup.scctData[20u] = CY_GET_REG8(CYREG_SC2_SW10);\r
+\r
+ cyPmBackup.scctData[21u] = CY_GET_REG8(CYREG_SC3_SW0 );\r
+ cyPmBackup.scctData[22u] = CY_GET_REG8(CYREG_SC3_SW2 );\r
+ cyPmBackup.scctData[23u] = CY_GET_REG8(CYREG_SC3_SW3 );\r
+ cyPmBackup.scctData[24u] = CY_GET_REG8(CYREG_SC3_SW4 );\r
+ cyPmBackup.scctData[25u] = CY_GET_REG8(CYREG_SC3_SW6 );\r
+ cyPmBackup.scctData[26u] = CY_GET_REG8(CYREG_SC3_SW8 );\r
+ cyPmBackup.scctData[27u] = CY_GET_REG8(CYREG_SC3_SW10);\r
+\r
+ CY_SET_REG8(CYREG_SC0_SW0 , 0u);\r
+ CY_SET_REG8(CYREG_SC0_SW2 , 0u);\r
+ CY_SET_REG8(CYREG_SC0_SW3 , 0u);\r
+ CY_SET_REG8(CYREG_SC0_SW4 , 0u);\r
+ CY_SET_REG8(CYREG_SC0_SW6 , 0u);\r
+ CY_SET_REG8(CYREG_SC0_SW8 , 0u);\r
+ CY_SET_REG8(CYREG_SC0_SW10, 0u);\r
+\r
+ CY_SET_REG8(CYREG_SC1_SW0 , 0u);\r
+ CY_SET_REG8(CYREG_SC1_SW2 , 0u);\r
+ CY_SET_REG8(CYREG_SC1_SW3 , 0u);\r
+ CY_SET_REG8(CYREG_SC1_SW4 , 0u);\r
+ CY_SET_REG8(CYREG_SC1_SW6 , 0u);\r
+ CY_SET_REG8(CYREG_SC1_SW8 , 0u);\r
+ CY_SET_REG8(CYREG_SC1_SW10, 0u);\r
+\r
+ CY_SET_REG8(CYREG_SC2_SW0 , 0u);\r
+ CY_SET_REG8(CYREG_SC2_SW2 , 0u);\r
+ CY_SET_REG8(CYREG_SC2_SW3 , 0u);\r
+ CY_SET_REG8(CYREG_SC2_SW4 , 0u);\r
+ CY_SET_REG8(CYREG_SC2_SW6 , 0u);\r
+ CY_SET_REG8(CYREG_SC2_SW8 , 0u);\r
+ CY_SET_REG8(CYREG_SC2_SW10, 0u);\r
+\r
+ CY_SET_REG8(CYREG_SC3_SW0 , 0u);\r
+ CY_SET_REG8(CYREG_SC3_SW2 , 0u);\r
+ CY_SET_REG8(CYREG_SC3_SW3 , 0u);\r
+ CY_SET_REG8(CYREG_SC3_SW4 , 0u);\r
+ CY_SET_REG8(CYREG_SC3_SW6 , 0u);\r
+ CY_SET_REG8(CYREG_SC3_SW8 , 0u);\r
+ CY_SET_REG8(CYREG_SC3_SW10, 0u);\r
+\r
+ #endif /* (CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP) */\r
+\r
+\r
+ #if(CY_PSOC3)\r
+\r
+ /* Serial Wire Viewer (SWV) workaround */\r
+\r
+ /* Disable SWV before entering low power mode */\r
+ if(0u != (CY_PM_MLOGIC_DBG_REG & CY_PM_MLOGIC_DBG_SWV_CLK_EN))\r
+ {\r
+ /* Save SWV clock enabled state */\r
+ cyPmBackup.swvClkEnabled = CY_PM_ENABLED;\r
+\r
+ /* Save current ports drive mode settings */\r
+ cyPmBackup.prt1Dm = CY_PM_PRT1_PC3_REG & ((uint8)(~CY_PM_PRT1_PC3_DM_MASK));\r
+\r
+ /* Set drive mode to strong output */\r
+ CY_PM_PRT1_PC3_REG = (CY_PM_PRT1_PC3_REG & CY_PM_PRT1_PC3_DM_MASK) |\r
+ CY_PM_PRT1_PC3_DM_STRONG;\r
+\r
+ /* Disable SWV clocks */\r
+ CY_PM_MLOGIC_DBG_REG &= ((uint8)(~CY_PM_MLOGIC_DBG_SWV_CLK_EN));\r
+ }\r
+ else\r
+ {\r
+ /* Save SWV clock disabled state */\r
+ cyPmBackup.swvClkEnabled = CY_PM_DISABLED;\r
+ }\r
+\r
+ #endif /* (CY_PSOC3) */\r
+\r
+\r
+ /***************************************************************************\r
+ * Save boost reference and set it to boost's internal by clearing the bit.\r
+ * External (chip bandgap) reference is not available in Sleep and Hibernate.\r
+ ***************************************************************************/\r
+ if(0u != (CY_PM_BOOST_CR2_REG & CY_PM_BOOST_CR2_EREFSEL_EXT))\r
+ {\r
+ cyPmBackup.boostRefExt = CY_PM_ENABLED;\r
+ CY_PM_BOOST_CR2_REG &= ((uint8)(~CY_PM_BOOST_CR2_EREFSEL_EXT));\r
+ }\r
+ else\r
+ {\r
+ cyPmBackup.boostRefExt = CY_PM_DISABLED;\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPmHibSlpRestore\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* This API is used for restoring device configurations after wakeup from Sleep\r
+* and Hibernate low power modes:\r
+* - Restores COMP, VIDAC, DSM and SAR routing connections (PSoC 5)\r
+* - Restores SC/CT routing connections (PSoC 3/5/5LP)\r
+* - Restores enable state of Serial Wire Viewer (SWV) (PSoC 3)\r
+* - Restores initial buzz rate (PSoC 5)\r
+* - Restore boost reference selection\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+static void CyPmHibSlpRestore(void) \r
+{\r
+ #if(CY_PSOC5A)\r
+\r
+ /* Restore COMP routing registers */\r
+ CY_SET_REG8(CYREG_CMP0_SW0 , cyPmBackup.cmpData[0u] );\r
+ CY_SET_REG8(CYREG_CMP0_SW2 , cyPmBackup.cmpData[1u] );\r
+ CY_SET_REG8(CYREG_CMP0_SW3 , cyPmBackup.cmpData[2u] );\r
+ CY_SET_REG8(CYREG_CMP0_SW4 , cyPmBackup.cmpData[3u] );\r
+ CY_SET_REG8(CYREG_CMP0_SW6 , cyPmBackup.cmpData[4u] );\r
+\r
+ CY_SET_REG8(CYREG_CMP1_SW0 , cyPmBackup.cmpData[5u] );\r
+ CY_SET_REG8(CYREG_CMP1_SW2 , cyPmBackup.cmpData[6u] );\r
+ CY_SET_REG8(CYREG_CMP1_SW3 , cyPmBackup.cmpData[7u] );\r
+ CY_SET_REG8(CYREG_CMP1_SW4 , cyPmBackup.cmpData[8u] );\r
+ CY_SET_REG8(CYREG_CMP1_SW6 , cyPmBackup.cmpData[9u] );\r
+\r
+ CY_SET_REG8(CYREG_CMP2_SW0 , cyPmBackup.cmpData[10u]);\r
+ CY_SET_REG8(CYREG_CMP2_SW2 , cyPmBackup.cmpData[11u]);\r
+ CY_SET_REG8(CYREG_CMP2_SW3 , cyPmBackup.cmpData[12u]);\r
+ CY_SET_REG8(CYREG_CMP2_SW4 , cyPmBackup.cmpData[13u]);\r
+ CY_SET_REG8(CYREG_CMP2_SW6 , cyPmBackup.cmpData[14u]);\r
+\r
+ CY_SET_REG8(CYREG_CMP3_SW0 , cyPmBackup.cmpData[15u]);\r
+ CY_SET_REG8(CYREG_CMP3_SW2 , cyPmBackup.cmpData[16u]);\r
+ CY_SET_REG8(CYREG_CMP3_SW3 , cyPmBackup.cmpData[17u]);\r
+ CY_SET_REG8(CYREG_CMP3_SW4 , cyPmBackup.cmpData[18u]);\r
+ CY_SET_REG8(CYREG_CMP3_SW6 , cyPmBackup.cmpData[19u]);\r
+\r
+ /* Restore DAC routing registers */\r
+ CY_SET_REG8(CYREG_DAC0_SW0 , cyPmBackup.dacData[0u] );\r
+ CY_SET_REG8(CYREG_DAC0_SW2 , cyPmBackup.dacData[1u] );\r
+ CY_SET_REG8(CYREG_DAC0_SW3 , cyPmBackup.dacData[2u] );\r
+ CY_SET_REG8(CYREG_DAC0_SW4 , cyPmBackup.dacData[3u] );\r
+\r
+ CY_SET_REG8(CYREG_DAC1_SW0 , cyPmBackup.dacData[4u] );\r
+ CY_SET_REG8(CYREG_DAC1_SW2 , cyPmBackup.dacData[5u] );\r
+ CY_SET_REG8(CYREG_DAC1_SW3 , cyPmBackup.dacData[6u] );\r
+ CY_SET_REG8(CYREG_DAC1_SW4 , cyPmBackup.dacData[7u] );\r
+\r
+ CY_SET_REG8(CYREG_DAC2_SW0 , cyPmBackup.dacData[8u] );\r
+ CY_SET_REG8(CYREG_DAC2_SW2 , cyPmBackup.dacData[9u] );\r
+ CY_SET_REG8(CYREG_DAC2_SW3 , cyPmBackup.dacData[10u]);\r
+ CY_SET_REG8(CYREG_DAC2_SW4 , cyPmBackup.dacData[11u]);\r
+\r
+ CY_SET_REG8(CYREG_DAC3_SW0 , cyPmBackup.dacData[12u]);\r
+ CY_SET_REG8(CYREG_DAC3_SW2 , cyPmBackup.dacData[13u]);\r
+ CY_SET_REG8(CYREG_DAC3_SW3 , cyPmBackup.dacData[14u]);\r
+ CY_SET_REG8(CYREG_DAC3_SW4 , cyPmBackup.dacData[15u]);\r
+\r
+\r
+ /* Restore DSM routing registers */\r
+ CY_SET_REG8(CYREG_DSM0_SW0 , cyPmBackup.dsmData[0u]);\r
+ CY_SET_REG8(CYREG_DSM0_SW2 , cyPmBackup.dsmData[1u]);\r
+ CY_SET_REG8(CYREG_DSM0_SW3 , cyPmBackup.dsmData[2u]);\r
+ CY_SET_REG8(CYREG_DSM0_SW4 , cyPmBackup.dsmData[3u]);\r
+ CY_SET_REG8(CYREG_DSM0_SW6 , cyPmBackup.dsmData[4u]);\r
+\r
+\r
+ /* Restore SAR routing registers */\r
+ CY_SET_REG8(CYREG_SAR0_SW0 , cyPmBackup.sarData[0u]);\r
+ CY_SET_REG8(CYREG_SAR0_SW2 , cyPmBackup.sarData[1u]);\r
+ CY_SET_REG8(CYREG_SAR0_SW3 , cyPmBackup.sarData[2u]);\r
+ CY_SET_REG8(CYREG_SAR0_SW4 , cyPmBackup.sarData[3u]);\r
+ CY_SET_REG8(CYREG_SAR0_SW6 , cyPmBackup.sarData[4u]);\r
+\r
+ CY_SET_REG8(CYREG_SAR1_SW0 , cyPmBackup.sarData[5u]);\r
+ CY_SET_REG8(CYREG_SAR1_SW2 , cyPmBackup.sarData[6u]);\r
+ CY_SET_REG8(CYREG_SAR1_SW3 , cyPmBackup.sarData[7u]);\r
+ CY_SET_REG8(CYREG_SAR1_SW4 , cyPmBackup.sarData[8u]);\r
+ CY_SET_REG8(CYREG_SAR1_SW6 , cyPmBackup.sarData[9u]);\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+ #if(CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP)\r
+\r
+ /* Restore SC/CT routing registers */\r
+ CY_SET_REG8(CYREG_SC0_SW0 , cyPmBackup.scctData[0u] );\r
+ CY_SET_REG8(CYREG_SC0_SW2 , cyPmBackup.scctData[1u] );\r
+ CY_SET_REG8(CYREG_SC0_SW3 , cyPmBackup.scctData[2u] );\r
+ CY_SET_REG8(CYREG_SC0_SW4 , cyPmBackup.scctData[3u] );\r
+ CY_SET_REG8(CYREG_SC0_SW6 , cyPmBackup.scctData[4u] );\r
+ CY_SET_REG8(CYREG_SC0_SW8 , cyPmBackup.scctData[5u] );\r
+ CY_SET_REG8(CYREG_SC0_SW10, cyPmBackup.scctData[6u] );\r
+\r
+ CY_SET_REG8(CYREG_SC1_SW0 , cyPmBackup.scctData[7u] );\r
+ CY_SET_REG8(CYREG_SC1_SW2 , cyPmBackup.scctData[8u] );\r
+ CY_SET_REG8(CYREG_SC1_SW3 , cyPmBackup.scctData[9u] );\r
+ CY_SET_REG8(CYREG_SC1_SW4 , cyPmBackup.scctData[10u]);\r
+ CY_SET_REG8(CYREG_SC1_SW6 , cyPmBackup.scctData[11u]);\r
+ CY_SET_REG8(CYREG_SC1_SW8 , cyPmBackup.scctData[12u]);\r
+ CY_SET_REG8(CYREG_SC1_SW10, cyPmBackup.scctData[13u]);\r
+\r
+ CY_SET_REG8(CYREG_SC2_SW0 , cyPmBackup.scctData[14u]);\r
+ CY_SET_REG8(CYREG_SC2_SW2 , cyPmBackup.scctData[15u]);\r
+ CY_SET_REG8(CYREG_SC2_SW3 , cyPmBackup.scctData[16u]);\r
+ CY_SET_REG8(CYREG_SC2_SW4 , cyPmBackup.scctData[17u]);\r
+ CY_SET_REG8(CYREG_SC2_SW6 , cyPmBackup.scctData[18u]);\r
+ CY_SET_REG8(CYREG_SC2_SW8 , cyPmBackup.scctData[19u]);\r
+ CY_SET_REG8(CYREG_SC2_SW10, cyPmBackup.scctData[20u]);\r
+\r
+ CY_SET_REG8(CYREG_SC3_SW0 , cyPmBackup.scctData[21u]);\r
+ CY_SET_REG8(CYREG_SC3_SW2 , cyPmBackup.scctData[22u]);\r
+ CY_SET_REG8(CYREG_SC3_SW3 , cyPmBackup.scctData[23u]);\r
+ CY_SET_REG8(CYREG_SC3_SW4 , cyPmBackup.scctData[24u]);\r
+ CY_SET_REG8(CYREG_SC3_SW6 , cyPmBackup.scctData[25u]);\r
+ CY_SET_REG8(CYREG_SC3_SW8 , cyPmBackup.scctData[26u]);\r
+ CY_SET_REG8(CYREG_SC3_SW10, cyPmBackup.scctData[27u]);\r
+\r
+ #endif /* (CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP) */\r
+\r
+\r
+ #if(CY_PSOC3)\r
+\r
+ /* Serial Wire Viewer (SWV) workaround */\r
+ if(CY_PM_ENABLED == cyPmBackup.swvClkEnabled)\r
+ {\r
+ /* Restore ports drive mode */\r
+ CY_PM_PRT1_PC3_REG = (CY_PM_PRT1_PC3_REG & CY_PM_PRT1_PC3_DM_MASK) |\r
+ cyPmBackup.prt1Dm;\r
+\r
+ /* Enable SWV clocks */\r
+ CY_PM_MLOGIC_DBG_REG |= CY_PM_MLOGIC_DBG_SWV_CLK_EN;\r
+ }\r
+\r
+ #endif /* (CY_PSOC3) */\r
+\r
+\r
+ #if(CY_PSOC5A)\r
+\r
+ /* Restore buzz sleep trim value */\r
+ CY_PM_PWRSYS_BUZZ_TR_REG = cyPmBackup.buzzSleepTrim | \\r
+ (CY_PM_PWRSYS_BUZZ_TR_REG & CY_PM_PWRSYS_BUZZ_TR_MASK);\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+\r
+ /* Restore boost reference */\r
+ if(CY_PM_ENABLED == cyPmBackup.boostRefExt)\r
+ {\r
+ CY_PM_BOOST_CR2_REG |= CY_PM_BOOST_CR2_EREFSEL_EXT;\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPmHviLviSaveDisable\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Saves analog and digital LVI and HVI configuration and disables them.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Reentrant:\r
+* No\r
+*\r
+*******************************************************************************/\r
+static void CyPmHviLviSaveDisable(void) \r
+{\r
+ if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_LVID_EN))\r
+ {\r
+ cyPmBackup.lvidEn = CY_PM_ENABLED;\r
+ cyPmBackup.lvidTrip = CY_VD_LVI_TRIP_REG & CY_VD_LVI_TRIP_LVID_MASK;\r
+\r
+ /* Save state of reset device at a specified Vddd threshold */\r
+ #if(CY_PSOC5A)\r
+\r
+ /* Not applicable PSoC 5 */\r
+ cyPmBackup.lvidRst = CY_PM_DISABLED;\r
+\r
+ #else\r
+\r
+ cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \\r
+ CY_PM_DISABLED : CY_PM_ENABLED;\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+ CyVdLvDigitDisable();\r
+ }\r
+ else\r
+ {\r
+ cyPmBackup.lvidEn = CY_PM_DISABLED;\r
+ }\r
+\r
+ if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_LVIA_EN))\r
+ {\r
+ cyPmBackup.lviaEn = CY_PM_ENABLED;\r
+ cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u;\r
+\r
+ /* Save state of reset device at a specified Vdda threshold */\r
+ #if(CY_PSOC5A)\r
+\r
+ /* Not applicable PSoC 5 */\r
+ cyPmBackup.lviaRst = CY_PM_DISABLED;\r
+\r
+ #else\r
+\r
+ cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \\r
+ CY_PM_DISABLED : CY_PM_ENABLED;\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+ CyVdLvAnalogDisable();\r
+ }\r
+ else\r
+ {\r
+ cyPmBackup.lviaEn = CY_PM_DISABLED;\r
+ }\r
+\r
+ if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_HVIA_EN))\r
+ {\r
+ cyPmBackup.hviaEn = CY_PM_ENABLED;\r
+ CyVdHvAnalogDisable();\r
+ }\r
+ else\r
+ {\r
+ cyPmBackup.hviaEn = CY_PM_DISABLED;\r
+ }\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: CyPmHviLviRestore\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Restores analog and digital LVI and HVI configuration.\r
+*\r
+* Parameters:\r
+* None\r
+*\r
+* Return:\r
+* None\r
+*\r
+* Reentrant:\r
+* No\r
+*\r
+*******************************************************************************/\r
+static void CyPmHviLviRestore(void) \r
+{\r
+ /* Restore LVI/HVI configuration */\r
+ if(CY_PM_ENABLED == cyPmBackup.lvidEn)\r
+ {\r
+ CyVdLvDigitEnable(cyPmBackup.lvidRst, cyPmBackup.lvidTrip);\r
+ }\r
+\r
+ if(CY_PM_ENABLED == cyPmBackup.lviaEn)\r
+ {\r
+ CyVdLvAnalogEnable(cyPmBackup.lviaRst, cyPmBackup.lviaTrip);\r
+ }\r
+\r
+ if(CY_PM_ENABLED == cyPmBackup.hviaEn)\r
+ {\r
+ CyVdHvAnalogEnable();\r
+ }\r
+}\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: cyPm.h\r
+* Version 3.40\r
+*\r
+* Description:\r
+* Provides the function definitions for the power management API.\r
+*\r
+* Note:\r
+* Documentation of the API's in this file is located in the\r
+* System Reference Guide provided with PSoC Creator.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_BOOT_CYPM_H)\r
+#define CY_BOOT_CYPM_H\r
+\r
+#include "cytypes.h" /* Register access API */\r
+#include "cydevice_trm.h" /* Registers addresses */\r
+#include "cyfitter.h" /* Comparators placement */\r
+#include "CyLib.h" /* Clock API */\r
+#include "CyFlash.h" /* Flash API - CyFlash_SetWaitCycles() */\r
+\r
+\r
+/***************************************\r
+* Function Prototypes\r
+***************************************/\r
+void CyPmSaveClocks(void) ;\r
+void CyPmRestoreClocks(void) ;\r
+void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) ;\r
+void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) ;\r
+void CyPmHibernate(void) ;\r
+\r
+uint8 CyPmReadStatus(uint8 mask) ;\r
+\r
+/* Internal APIs and are not meant to be called directly by the user */\r
+void CyPmCtwSetInterval(uint8 ctwInterval) ;\r
+void CyPmFtwSetInterval(uint8 ftwInterval) ;\r
+void CyPmOppsSet(void) ;\r
+\r
+\r
+/***************************************\r
+* API Constants\r
+***************************************/\r
+\r
+#define PM_SLEEP_SRC_NONE (0x0000u)\r
+#define PM_SLEEP_TIME_NONE (0x00u)\r
+#define PM_ALT_ACT_SRC_NONE (0x0000u)\r
+#define PM_ALT_ACT_TIME_NONE (0x0000u)\r
+\r
+#if(CY_PSOC3)\r
+\r
+ /* Wake up time for the Sleep mode */\r
+ #define PM_SLEEP_TIME_ONE_PPS (0x01u)\r
+ #define PM_SLEEP_TIME_CTW_2MS (0x02u)\r
+ #define PM_SLEEP_TIME_CTW_4MS (0x03u)\r
+ #define PM_SLEEP_TIME_CTW_8MS (0x04u)\r
+ #define PM_SLEEP_TIME_CTW_16MS (0x05u)\r
+ #define PM_SLEEP_TIME_CTW_32MS (0x06u)\r
+ #define PM_SLEEP_TIME_CTW_64MS (0x07u)\r
+ #define PM_SLEEP_TIME_CTW_128MS (0x08u)\r
+ #define PM_SLEEP_TIME_CTW_256MS (0x09u)\r
+ #define PM_SLEEP_TIME_CTW_512MS (0x0Au)\r
+ #define PM_SLEEP_TIME_CTW_1024MS (0x0Bu)\r
+ #define PM_SLEEP_TIME_CTW_2048MS (0x0Cu)\r
+ #define PM_SLEEP_TIME_CTW_4096MS (0x0Du)\r
+\r
+ /* Difference between parameter's value and register's one */\r
+ #define CY_PM_FTW_INTERVAL_SHIFT (0x000Eu)\r
+\r
+ /* Wake up time for the Alternate Active mode */\r
+ #define PM_ALT_ACT_TIME_ONE_PPS (0x0001u)\r
+ #define PM_ALT_ACT_TIME_CTW_2MS (0x0002u)\r
+ #define PM_ALT_ACT_TIME_CTW_4MS (0x0003u)\r
+ #define PM_ALT_ACT_TIME_CTW_8MS (0x0004u)\r
+ #define PM_ALT_ACT_TIME_CTW_16MS (0x0005u)\r
+ #define PM_ALT_ACT_TIME_CTW_32MS (0x0006u)\r
+ #define PM_ALT_ACT_TIME_CTW_64MS (0x0007u)\r
+ #define PM_ALT_ACT_TIME_CTW_128MS (0x0008u)\r
+ #define PM_ALT_ACT_TIME_CTW_256MS (0x0009u)\r
+ #define PM_ALT_ACT_TIME_CTW_512MS (0x000Au)\r
+ #define PM_ALT_ACT_TIME_CTW_1024MS (0x000Bu)\r
+ #define PM_ALT_ACT_TIME_CTW_2048MS (0x000Cu)\r
+ #define PM_ALT_ACT_TIME_CTW_4096MS (0x000Du)\r
+ #define PM_ALT_ACT_TIME_FTW(x) ((x) + CY_PM_FTW_INTERVAL_SHIFT)\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
+#if(CY_PSOC3 || CY_PSOC5LP)\r
+\r
+ /* Wake up sources for the Sleep mode */\r
+ #define PM_SLEEP_SRC_COMPARATOR0 (0x0001u)\r
+ #define PM_SLEEP_SRC_COMPARATOR1 (0x0002u)\r
+ #define PM_SLEEP_SRC_COMPARATOR2 (0x0004u)\r
+ #define PM_SLEEP_SRC_COMPARATOR3 (0x0008u)\r
+ #define PM_SLEEP_SRC_PICU (0x0040u)\r
+ #define PM_SLEEP_SRC_I2C (0x0080u)\r
+ #define PM_SLEEP_SRC_BOOSTCONVERTER (0x0200u)\r
+ #define PM_SLEEP_SRC_VD (0x0400u)\r
+ #define PM_SLEEP_SRC_CTW (0x0800u)\r
+ #define PM_SLEEP_SRC_ONE_PPS (0x0800u)\r
+ #define PM_SLEEP_SRC_LCD (0x1000u)\r
+\r
+ /* Wake up sources for the Alternate Active mode */\r
+ #define PM_ALT_ACT_SRC_COMPARATOR0 (0x0001u)\r
+ #define PM_ALT_ACT_SRC_COMPARATOR1 (0x0002u)\r
+ #define PM_ALT_ACT_SRC_COMPARATOR2 (0x0004u)\r
+ #define PM_ALT_ACT_SRC_COMPARATOR3 (0x0008u)\r
+ #define PM_ALT_ACT_SRC_INTERRUPT (0x0010u)\r
+ #define PM_ALT_ACT_SRC_PICU (0x0040u)\r
+ #define PM_ALT_ACT_SRC_I2C (0x0080u)\r
+ #define PM_ALT_ACT_SRC_BOOSTCONVERTER (0x0200u)\r
+ #define PM_ALT_ACT_SRC_FTW (0x0400u)\r
+ #define PM_ALT_ACT_SRC_VD (0x0400u)\r
+ #define PM_ALT_ACT_SRC_CTW (0x0800u)\r
+ #define PM_ALT_ACT_SRC_ONE_PPS (0x0800u)\r
+ #define PM_ALT_ACT_SRC_LCD (0x1000u)\r
+\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+\r
+#define CY_PM_WAKEUP_PICU (0x04u)\r
+#define CY_PM_IMO_NO_WAIT_TO_SETTLE (0x00u)\r
+#define CY_PM_POWERDOWN_MODE (0x01u)\r
+#define CY_PM_HIGHPOWER_MODE (0x00u) /* Deprecated */\r
+#define CY_PM_ENABLED (0x01u)\r
+#define CY_PM_DISABLED (0x00u)\r
+\r
+/* No wait for PLL to stabilize, used in CyPLL_OUT_Start() */\r
+#define CY_PM_PLL_OUT_NO_WAIT (0u)\r
+\r
+/* No wait for MHZ XTAL to stabilize, used in CyXTAL_Start() */\r
+#define CY_PM_XTAL_MHZ_NO_WAIT (0u)\r
+\r
+#define CY_PM_WAIT_200_US (200u)\r
+#define CY_PM_WAIT_250_US (250u)\r
+#define CY_PM_WAIT_20_US (20u)\r
+\r
+#define CY_PM_FREQ_3MHZ (3u)\r
+#define CY_PM_FREQ_12MHZ (12u)\r
+#define CY_PM_FREQ_48MHZ (48u)\r
+\r
+\r
+#if(CY_PSOC5A)\r
+ #define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (650u)\r
+#else\r
+ #define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (5u)\r
+#endif /* (CY_PSOC5A) */\r
+\r
+\r
+/* Delay line bandgap current settling time starting from a wakeup event */\r
+#define CY_PM_CLK_DELAY_BANDGAP_SETTLE_US (50u)\r
+\r
+/* Delay line internal bias settling */\r
+#define CY_PM_CLK_DELAY_BIAS_SETTLE_US (25u)\r
+\r
+\r
+/* Max flash wait cycles for each device */\r
+#if(CY_PSOC3)\r
+ #define CY_PM_MAX_FLASH_WAIT_CYCLES (45u)\r
+#endif /* (CY_PSOC3) */\r
+\r
+#if(CY_PSOC5A)\r
+ #define CY_PM_MAX_FLASH_WAIT_CYCLES (55u)\r
+#endif /* (CY_PSOC5A) */\r
+\r
+#if(CY_PSOC5LP)\r
+ #define CY_PM_MAX_FLASH_WAIT_CYCLES (55u)\r
+#endif /* (CY_PSOC5LP) */\r
+\r
+\r
+/*******************************************************************************\r
+* This marco is used to obtain the CPU frequency in MHz. It should be only used\r
+* when the clock distribution system is prepared for the low power mode entry.\r
+* This macro is silicon dependent as PSoC 5 devices have no CPU clock divider\r
+* and PSoC 3 devices have different placement of the CPU clock divider register\r
+* bitfield.\r
+*******************************************************************************/\r
+#if(CY_PSOC3)\r
+ #define CY_PM_GET_CPU_FREQ_MHZ ((uint32)(cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) / \\r
+ ((uint8)(((CY_PM_CLKDIST_MSTR1_REG & CY_PM_CLKDIST_CPU_DIV_MASK) >> 4u) + 1u)))\r
+#endif /* (CY_PSOC3) */\r
+\r
+#if(CY_PSOC5)\r
+\r
+ /* The CPU clock is directly derived from bus clock */\r
+ #define CY_PM_GET_CPU_FREQ_MHZ (cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK])\r
+\r
+#endif /* (CY_PSOC5) */\r
+\r
+\r
+/*******************************************************************************\r
+* The low power mode entry is different for PSoC 3 and PSoC 5 devices. The low\r
+* power modes in PSoC 5 devices are invoked by Wait-For-Interrupt (WFI)\r
+* instruction. The ARM compilers has __wfi() instristic that inserts a WFI\r
+* instruction into the instruction stream generated by the compiler. The GCC\r
+* compiler has to execute assembly language instruction.\r
+*******************************************************************************/\r
+#if(CY_PSOC5)\r
+\r
+ #if defined(__ARMCC_VERSION) /* Instristic for Keil compilers */\r
+ #define CY_PM_WFI __wfi()\r
+ #else /* ASM for GCC */\r
+ #define CY_PM_WFI asm volatile ("WFI \n")\r
+ #endif /* (__ARMCC_VERSION) */\r
+\r
+#else\r
+\r
+ #define CY_PM_WFI CY_NOP\r
+\r
+#endif /* (CY_PSOC5) */\r
+\r
+\r
+/*******************************************************************************\r
+* Macro for the wakeupTime argument of the CyPmAltAct() function. The FTW should\r
+* be programmed manually for non PSoC 3 devices.\r
+*******************************************************************************/\r
+#if(CY_PSOC3)\r
+\r
+ #define PM_ALT_ACT_FTW_INTERVAL(x) ((uint8)((x) - CY_PM_FTW_INTERVAL_SHIFT))\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
+/*******************************************************************************\r
+* This macro defines the IMO frequency that will be set by CyPmSaveClocks()\r
+* function based on Enable Fast IMO during Startup option from the DWR file.\r
+* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering\r
+* low power mode and restore IMO back to the value set by CyPmSaveClocks()\r
+* immediately on wakeup.\r
+*******************************************************************************/\r
+\r
+/* Enable Fast IMO during Startup - enabled */\r
+#if(1u == CYDEV_CONFIGURATION_IMOENABLED)\r
+\r
+ /* IMO will be configured to 48 MHz */\r
+ #define CY_PM_IMO_FREQ_LPM (CY_IMO_FREQ_48MHZ)\r
+\r
+#else\r
+\r
+ /* IMO will be configured to 12 MHz */\r
+ #define CY_PM_IMO_FREQ_LPM (CY_IMO_FREQ_12MHZ)\r
+\r
+#endif /* (1u == CYDEV_CONFIGURATION_IMOENABLED) */\r
+\r
+\r
+typedef struct cyPmClockBackupStruct\r
+{\r
+ /* CyPmSaveClocks()/CyPmRestoreClocks() */\r
+ uint8 enClkA; /* Analog clocks enable */\r
+ uint8 enClkD; /* Digital clocks enable */\r
+ uint8 masterClkSrc; /* The Master clock source */\r
+ uint8 imoFreq; /* IMO frequency (reg's value) */\r
+ uint8 imoUsbClk; /* IMO USB CLK (reg's value) */\r
+ uint8 flashWaitCycles; /* Flash wait cycles */\r
+ uint8 imoEnable; /* IMO enable in Active mode */\r
+ uint8 imoClkSrc; /* The IMO output */\r
+ uint8 clkImoSrc;\r
+ uint8 imo2x; /* IMO doubler enable state */\r
+ uint8 clkSyncDiv; /* Master clk divider */\r
+ uint16 clkBusDiv; /* The clk_bus divider */\r
+ uint8 pllEnableState; /* PLL enable state */\r
+ uint8 xmhzEnableState; /* XM HZ enable state */\r
+ uint8 clkDistDelay; /* Delay for clk_bus and ACLKs */\r
+\r
+} CY_PM_CLOCK_BACKUP_STRUCT;\r
+\r
+\r
+typedef struct cyPmBackupStruct\r
+{\r
+ #if(!CY_PSOC5A)\r
+\r
+ uint8 iloPowerMode; /* ILO power mode */\r
+ uint8 ilo1kEnable; /* ILO 1K enable state */\r
+ uint8 ilo100kEnable; /* ILO 100K enable state */\r
+\r
+ uint8 slpTrBypass; /* Sleep Trim Bypass */\r
+\r
+ #endif /* (!CY_PSOC5A) */\r
+\r
+\r
+ #if(CY_PSOC5A)\r
+\r
+ /* State of the I2C regulator backup */\r
+ uint8 i2cRegBackup;\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+\r
+ #if(CY_PSOC5A)\r
+ uint8 buzzSleepTrim;\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+\r
+ #if(CY_PSOC3)\r
+\r
+ uint8 swvClkEnabled; /* SWV clock enable state */\r
+ uint8 prt1Dm; /* Ports drive mode configuration */\r
+\r
+ #endif /* (CY_PSOC3) */\r
+\r
+ #if(CY_PSOC3 || CY_PSOC5LP)\r
+\r
+ uint8 wakeupCfg0; /* Wake up configuration 0 */\r
+ uint8 wakeupCfg1; /* Wake up configuration 1 */\r
+ uint8 wakeupCfg2; /* Wake up configuration 2 */\r
+\r
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+\r
+ #if(CY_PSOC3 || CY_PSOC5LP)\r
+\r
+ uint8 wakeupTrim0;\r
+ uint8 wakeupTrim1;\r
+\r
+ #endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+\r
+ #if(CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP)\r
+\r
+ uint8 scctData[28u]; /* SC/CT routing registers */\r
+\r
+ #endif /* (CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP) */\r
+\r
+ #if(CY_PSOC5A)\r
+\r
+ uint8 cmpData[20u];\r
+ uint8 dacData[16u];\r
+ uint8 dsmData[5u];\r
+ uint8 sarData[10u];\r
+\r
+ uint8 pmTwCfg2;\r
+ uint8 picuIntType[72u];\r
+\r
+ uint8 pres1;\r
+ uint8 pres2;\r
+\r
+ #endif /* (CY_PSOC5A) */\r
+\r
+\r
+ /* CyPmHviLviSaveDisable()/CyPmHviLviRestore() */\r
+ uint8 lvidEn;\r
+ uint8 lvidTrip;\r
+ uint8 lviaEn;\r
+ uint8 lviaTrip;\r
+ uint8 hviaEn;\r
+ uint8 lvidRst;\r
+ uint8 lviaRst;\r
+\r
+ uint8 imoActFreq; /* Last moment IMO change */\r
+ uint8 imoActFreq12Mhz; /* 12 MHz or not */\r
+\r
+ uint8 boostRefExt; /* Boost reference selection */\r
+\r
+} CY_PM_BACKUP_STRUCT;\r
+\r
+\r
+/***************************************\r
+* Registers\r
+***************************************/\r
+\r
+/* Power Mode Wakeup Trim Register 1 */\r
+#define CY_PM_PWRSYS_WAKE_TR1_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR1 )\r
+#define CY_PM_PWRSYS_WAKE_TR1_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR1 )\r
+\r
+/* Master clock Divider Value Register */\r
+#define CY_PM_CLKDIST_MSTR0_REG (* (reg8 *) CYREG_CLKDIST_MSTR0 )\r
+#define CY_PM_CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0 )\r
+\r
+/* Master Clock Configuration Register/CPU Divider Value */\r
+#define CY_PM_CLKDIST_MSTR1_REG (* (reg8 *) CYREG_CLKDIST_MSTR1 )\r
+#define CY_PM_CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1 )\r
+\r
+/* Clock distribution configuration Register */\r
+#define CY_PM_CLKDIST_CR_REG (* (reg8 *) CYREG_CLKDIST_CR )\r
+#define CY_PM_CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR )\r
+\r
+/* CLK_BUS LSB Divider Value Register */\r
+#define CY_PM_CLK_BUS_LSB_DIV_REG (* (reg8 *) CYREG_CLKDIST_BCFG0 )\r
+#define CY_PM_CLK_BUS_LSB_DIV_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0 )\r
+\r
+/* CLK_BUS MSB Divider Value Register */\r
+#define CY_PM_CLK_BUS_MSB_DIV_REG (* (reg8 *) CYREG_CLKDIST_BCFG1 )\r
+#define CY_PM_CLK_BUS_MSB_DIV_PTR ( (reg8 *) CYREG_CLKDIST_BCFG1 )\r
+\r
+/* CLK_BUS Configuration Register */\r
+#define CLK_BUS_CFG_REG (* (reg8 *) CYREG_CLKDIST_BCFG2 )\r
+#define CLK_BUS_CFG_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2 )\r
+\r
+/* Power Mode Control/Status Register */\r
+#define CY_PM_MODE_CSR_REG (* (reg8 *) CYREG_PM_MODE_CSR )\r
+#define CY_PM_MODE_CSR_PTR ( (reg8 *) CYREG_PM_MODE_CSR )\r
+\r
+/* Power System Control Register 1 */\r
+#define CY_PM_PWRSYS_CR1_REG (* (reg8 *) CYREG_PWRSYS_CR1 )\r
+#define CY_PM_PWRSYS_CR1_PTR ( (reg8 *) CYREG_PWRSYS_CR1 )\r
+\r
+/* Power System Control Register 0 */\r
+#define CY_PM_PWRSYS_CR0_REG (* (reg8 *) CYREG_PWRSYS_CR0 )\r
+#define CY_PM_PWRSYS_CR0_PTR ( (reg8 *) CYREG_PWRSYS_CR0 )\r
+\r
+/* Internal Low-speed Oscillator Control Register 0 */\r
+#define CY_PM_SLOWCLK_ILO_CR0_REG (* (reg8 *) CYREG_SLOWCLK_ILO_CR0 )\r
+#define CY_PM_SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0 )\r
+\r
+/* External 32kHz Crystal Oscillator Control Register */\r
+#define CY_PM_SLOWCLK_X32_CR_REG (* (reg8 *) CYREG_SLOWCLK_X32_CR )\r
+#define CY_PM_SLOWCLK_X32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR )\r
+\r
+#if(CY_PSOC3)\r
+\r
+ /* MLOGIC Debug Register */\r
+ #define CY_PM_MLOGIC_DBG_REG (* (reg8 *) CYREG_MLOGIC_DEBUG )\r
+ #define CY_PM_MLOGIC_DBG_PTR ( (reg8 *) CYREG_MLOGIC_DEBUG )\r
+\r
+ /* Port Pin Configuration Register */\r
+ #define CY_PM_PRT1_PC3_REG (* (reg8 *) CYREG_PRT1_PC3 )\r
+ #define CY_PM_PRT1_PC3_PTR ( (reg8 *) CYREG_PRT1_PC3 )\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
+#if(!CY_PSOC5A)\r
+\r
+ /* Sleep Regulator Trim Register */\r
+ #define CY_PM_PWRSYS_SLP_TR_REG (* (reg8 *) CYREG_PWRSYS_SLP_TR )\r
+ #define CY_PM_PWRSYS_SLP_TR_PTR ( (reg8 *) CYREG_PWRSYS_SLP_TR )\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+/* Reset System Control Register */\r
+#define CY_PM_RESET_CR1_REG (* (reg8 *) CYREG_RESET_CR1 )\r
+#define CY_PM_RESET_CR1_PTR ( (reg8 *) CYREG_RESET_CR1 )\r
+\r
+#if(CY_PSOC5A)\r
+\r
+ /* LVD/POR Test Mode Control Register */\r
+ #define CY_PM_RESET_CR3_REG (* (reg8 *) CYREG_RESET_CR3 )\r
+ #define CY_PM_RESET_CR3_PTR ( (reg8 *) CYREG_RESET_CR3 )\r
+\r
+#endif /* (CY_PSOC5A) */\r
+\r
+/* Power Mode Wakeup Trim Register 0 */\r
+#define CY_PM_PWRSYS_WAKE_TR0_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR0 )\r
+#define CY_PM_PWRSYS_WAKE_TR0_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR0 )\r
+\r
+#if(CY_PSOC3)\r
+\r
+ /* Power Mode Wakeup Trim Register 2 */\r
+ #define CY_PM_PWRSYS_WAKE_TR2_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR2 )\r
+ #define CY_PM_PWRSYS_WAKE_TR2_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR2 )\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+#if(CY_PSOC5A)\r
+\r
+ /* Power Mode Buzz Trim Register */\r
+ #define CY_PM_PWRSYS_BUZZ_TR_REG (* (reg8 *) CYREG_PWRSYS_BUZZ_TR )\r
+ #define CY_PM_PWRSYS_BUZZ_TR_PTR ( (reg8 *) CYREG_PWRSYS_BUZZ_TR )\r
+\r
+#endif /* (CY_PSOC5A) */\r
+\r
+/* Power Manager Interrupt Status Register */\r
+#define CY_PM_INT_SR_REG (* (reg8 *) CYREG_PM_INT_SR )\r
+#define CY_PM_INT_SR_PTR ( (reg8 *) CYREG_PM_INT_SR )\r
+\r
+/* Active Power Mode Configuration Register 0 */\r
+#define CY_PM_ACT_CFG0_REG (* (reg8 *) CYREG_PM_ACT_CFG0 )\r
+#define CY_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0 )\r
+\r
+/* Active Power Mode Configuration Register 1 */\r
+#define CY_PM_ACT_CFG1_REG (* (reg8 *) CYREG_PM_ACT_CFG1 )\r
+#define CY_PM_ACT_CFG1_PTR ( (reg8 *) CYREG_PM_ACT_CFG1 )\r
+\r
+/* Active Power Mode Configuration Register 2 */\r
+#define CY_PM_ACT_CFG2_REG (* (reg8 *) CYREG_PM_ACT_CFG2 )\r
+#define CY_PM_ACT_CFG2_PTR ( (reg8 *) CYREG_PM_ACT_CFG2 )\r
+\r
+/* Boost Control 1 */\r
+#define CY_PM_BOOST_CR1_REG (* (reg8 *) CYREG_BOOST_CR1 )\r
+#define CY_PM_BOOST_CR1_PTR ( (reg8 *) CYREG_BOOST_CR1 )\r
+\r
+/* Timewheel Configuration Register 0 */\r
+#define CY_PM_TW_CFG0_REG (* (reg8 *) CYREG_PM_TW_CFG0 )\r
+#define CY_PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0 )\r
+\r
+/* Timewheel Configuration Register 1 */\r
+#define CY_PM_TW_CFG1_REG (* (reg8 *) CYREG_PM_TW_CFG1 )\r
+#define CY_PM_TW_CFG1_PTR ( (reg8 *) CYREG_PM_TW_CFG1 )\r
+\r
+/* Timewheel Configuration Register 2 */\r
+#define CY_PM_TW_CFG2_REG (* (reg8 *) CYREG_PM_TW_CFG2 )\r
+#define CY_PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2 )\r
+\r
+/* PLL Status Register */\r
+#define CY_PM_FASTCLK_PLL_SR_REG (*(reg8 *) CYREG_FASTCLK_PLL_SR )\r
+#define CY_PM_FASTCLK_PLL_SR_PTR ( (reg8 *) CYREG_FASTCLK_PLL_SR )\r
+\r
+/* Internal Main Oscillator Control Register */\r
+#define CY_PM_FASTCLK_IMO_CR_REG (* (reg8 *) CYREG_FASTCLK_IMO_CR )\r
+#define CY_PM_FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR )\r
+\r
+/* PLL Configuration Register */\r
+#define CY_PM_FASTCLK_PLL_CFG0_REG (* (reg8 *) CYREG_FASTCLK_PLL_CFG0 )\r
+#define CY_PM_FASTCLK_PLL_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG0 )\r
+\r
+/* External 4-33 MHz Crystal Oscillator Status and Control Register */\r
+#define CY_PM_FASTCLK_XMHZ_CSR_REG (* (reg8 *) CYREG_FASTCLK_XMHZ_CSR )\r
+#define CY_PM_FASTCLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR )\r
+\r
+/* Delay block Configuration Register */\r
+#define CY_PM_CLKDIST_DELAY_REG (* (reg8 *) CYREG_CLKDIST_DLY1 )\r
+#define CY_PM_CLKDIST_DELAY_PTR ( (reg8 *) CYREG_CLKDIST_DLY1 )\r
+\r
+\r
+#if(CY_PSOC3)\r
+\r
+ /* Cache Control Register */\r
+ #define CY_PM_CACHE_CR_REG (* (reg8 *) CYREG_CACHE_CR )\r
+ #define CY_PM_CACHE_CR_PTR ( (reg8 *) CYREG_CACHE_CR )\r
+\r
+#else /* Device is PSoC 5 */\r
+\r
+ /* Cache Control Register */\r
+ #define CY_PM_CACHE_CR_REG (* (reg8 *) CYREG_CACHE_CC_CTL )\r
+ #define CY_PM_CACHE_CR_PTR ( (reg8 *) CYREG_CACHE_CC_CTL )\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
+#if(CY_PSOC3 || CY_PSOC5LP)\r
+\r
+ /* Power Mode Wakeup Mask Configuration Register 0 */\r
+ #define CY_PM_WAKEUP_CFG0_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG0 )\r
+ #define CY_PM_WAKEUP_CFG0_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG0 )\r
+\r
+ /* Power Mode Wakeup Mask Configuration Register 1 */\r
+ #define CY_PM_WAKEUP_CFG1_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG1 )\r
+ #define CY_PM_WAKEUP_CFG1_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG1 )\r
+\r
+ /* Power Mode Wakeup Mask Configuration Register 2 */\r
+ #define CY_PM_WAKEUP_CFG2_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG2 )\r
+ #define CY_PM_WAKEUP_CFG2_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG2 )\r
+\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+\r
+#if(CY_PSOC5A)\r
+\r
+ /* Watchdog Timer Configuration Register */\r
+ #define CY_PM_WDT_CFG_REG (* (reg8 *) CYREG_PM_WDT_CFG )\r
+ #define CY_PM_WDT_CFG_PTR ( (reg8 *) CYREG_PM_WDT_CFG )\r
+\r
+#endif /* (CY_PSOC5A) */\r
+\r
+\r
+/* Boost Control 2 */\r
+#define CY_PM_BOOST_CR2_REG (* (reg8 *) CYREG_BOOST_CR2 )\r
+#define CY_PM_BOOST_CR2_PTR ( (reg8 *) CYREG_BOOST_CR2 )\r
+\r
+\r
+/***************************************\r
+* Register Constants\r
+***************************************/\r
+\r
+/* Internal Main Oscillator Control Register */\r
+\r
+#define CY_PM_FASTCLK_IMO_CR_FREQ_MASK (0x07u) /* IMO frequency mask */\r
+#define CY_PM_FASTCLK_IMO_CR_FREQ_12MHZ (0x00u) /* IMO frequency 12 MHz */\r
+#define CY_PM_FASTCLK_IMO_CR_F2XON (0x10u) /* IMO doubler enable */\r
+#define CY_PM_FASTCLK_IMO_CR_USB (0x40u) /* IMO is in USB mode */\r
+\r
+#define CY_PM_MASTER_CLK_SRC_IMO (0u)\r
+#define CY_PM_MASTER_CLK_SRC_PLL (1u)\r
+#define CY_PM_MASTER_CLK_SRC_XTAL (2u)\r
+#define CY_PM_MASTER_CLK_SRC_DSI (3u)\r
+#define CY_PM_MASTER_CLK_SRC_MASK (3u)\r
+\r
+#define CY_PM_PLL_CFG0_ENABLE (0x01u) /* PLL enable */\r
+#define CY_PM_PLL_STATUS_LOCK (0x01u) /* PLL Lock Status */\r
+#define CY_PM_XMHZ_CSR_ENABLE (0x01u) /* Enable X MHz OSC */\r
+#define CY_PM_XMHZ_CSR_XERR (0x80u) /* High indicates failure */\r
+#define CY_PM_BOOST_ENABLE (0x08u) /* Boost enable */\r
+#define CY_PM_ILO_CR0_EN_1K (0x02u) /* Enable 1kHz ILO */\r
+#define CY_PM_ILO_CR0_EN_100K (0x04u) /* Enable 100kHz ILO */\r
+#define CY_PM_ILO_CR0_PD_MODE (0x10u) /* Power down mode for ILO*/\r
+#define CY_PM_X32_CR_X32EN (0x01u) /* Enable 32kHz OSC */\r
+\r
+#define CY_PM_CTW_IE (0x08u) /* CTW interrupt enable */\r
+#define CY_PM_CTW_EN (0x04u) /* CTW enable */\r
+#define CY_PM_FTW_IE (0x02u) /* FTW interrupt enable */\r
+#define CY_PM_FTW_EN (0x01u) /* FTW enable */\r
+#define CY_PM_1PPS_EN (0x10u) /* 1PPS enable */\r
+#define CY_PM_1PPS_IE (0x20u) /* 1PPS interrupt enable */\r
+\r
+\r
+#define CY_PM_ACT_EN_CLK_A_MASK (0x0Fu)\r
+#define CY_PM_ACT_EN_CLK_D_MASK (0xFFu)\r
+\r
+#define CY_PM_DIV_BY_ONE (0x00u)\r
+\r
+/* Internal Main Oscillator Control Register */\r
+#define CY_PM_FASTCLK_IMO_CR_XCLKEN (0x20u)\r
+\r
+/* Clock distribution configuration Register */\r
+#define CY_PM_CLKDIST_IMO_OUT_MASK (0x30u)\r
+#define CY_PM_CLKDIST_IMO_OUT_IMO (0x00u)\r
+#define CY_PM_CLKDIST_IMO2X_SRC (0x40u)\r
+\r
+/* Waiting for the hibernate/sleep regulator to stabilize */\r
+#define CY_PM_MODE_CSR_PWRUP_PULSE_Q (0x08u)\r
+\r
+#define CY_PM_MODE_CSR_ACTIVE (0x00u) /* Active power mode */\r
+#define CY_PM_MODE_CSR_ALT_ACT (0x01u) /* Alternate Active power */\r
+#define CY_PM_MODE_CSR_SLEEP (0x03u) /* Sleep power mode */\r
+#define CY_PM_MODE_CSR_HIBERNATE (0x04u) /* Hibernate power mode */\r
+#define CY_PM_MODE_CSR_MASK (0x07u)\r
+\r
+/* I2C regulator backup enable */\r
+#define CY_PM_PWRSYS_CR1_I2CREG_BACKUP (0x04u)\r
+\r
+/* When set, prepares the system to disable the LDO-A */\r
+#define CY_PM_PWRSYS_CR1_LDOA_ISO (0x01u)\r
+\r
+/* When set, disables the analog LDO regulator */\r
+#define CY_PM_PWRSYS_CR1_LDOA_DIS (0x02u)\r
+\r
+#define CY_PM_PWRSYS_WAKE_TR2_VCCD_CLK_DET (0x04u)\r
+\r
+#define CY_PM_FTW_INT (0x01u) /* FTW event has occured */\r
+#define CY_PM_CTW_INT (0x02u) /* CTW event has occured */\r
+#define CY_PM_ONEPPS_INT (0x04u) /* 1PPS event has occured */\r
+\r
+/* Active Power Mode Configuration Register 0 */\r
+#define CY_PM_ACT_CFG0_IMO (0x10u) /* IMO enable in Active */\r
+\r
+/* Cache Control Register (same mask for all device revisions) */\r
+#define CY_PM_CACHE_CR_CYCLES_MASK (0xC0u)\r
+\r
+/* Bus Clock divider to divide-by-one */\r
+#define CY_PM_BUS_CLK_DIV_BY_ONE (0x00u)\r
+\r
+/* HVI/LVI feature on the external analog and digital supply mask */\r
+#define CY_PM_RESET_CR1_HVI_LVI_EN_MASK (0x07u)\r
+\r
+/* The high-voltage-interrupt feature on the external analog supply */\r
+#define CY_PM_RESET_CR1_HVIA_EN (0x04u)\r
+\r
+/* The low-voltage-interrupt feature on the external analog supply */\r
+#define CY_PM_RESET_CR1_LVIA_EN (0x02u)\r
+\r
+/* The low-voltage-interrupt feature on the external digital supply */\r
+#define CY_PM_RESET_CR1_LVID_EN (0x01u)\r
+\r
+#if(CY_PSOC5A)\r
+\r
+ /* Partly disables PRES-A and PRES-D circuits */\r
+ #define CY_PM_RESET_CR1_DIS_PRES1 (0x10u)\r
+\r
+ /* Partly disables PRES-A and PRES-D circuits */\r
+ #define CY_PM_RESET_CR3_DIS_PRES2 (0x08u)\r
+\r
+#endif /* (CY_PSOC5A) */\r
+\r
+/* Allows the system to program delays on clk_sync_d */\r
+#define CY_PM_CLKDIST_DELAY_EN (0x04u)\r
+\r
+\r
+#if(CY_PSOC3 || CY_PSOC5LP)\r
+\r
+ #define CY_PM_WAKEUP_SRC_CMPS_MASK (0x000Fu)\r
+\r
+ /* Holdoff mask sleep trim */\r
+ #define CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK (0x1Fu)\r
+\r
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */\r
+\r
+\r
+#if(CY_PSOC3)\r
+\r
+ /* CPU clock divider mask */\r
+ #define CY_PM_CLKDIST_CPU_DIV_MASK (0xF0u)\r
+\r
+ /* Serial Wire View (SWV) clock enable */\r
+ #define CY_PM_MLOGIC_DBG_SWV_CLK_EN (0x04u)\r
+\r
+ /* Port drive mode */\r
+ #define CY_PM_PRT1_PC3_DM_MASK (0xf1u)\r
+\r
+ /* Mode 6, stong pull-up, strong pull-down */\r
+ #define CY_PM_PRT1_PC3_DM_STRONG (0x0Cu)\r
+\r
+ /* When set, enables buzz wakeups */\r
+ #define CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ (0x01u)\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
+#if(!CY_PSOC5A)\r
+\r
+ /* Disable the sleep regulator and shorts vccd to vpwrsleep */\r
+ #define CY_PM_PWRSYS_SLP_TR_BYPASS (0x10u)\r
+\r
+#endif /* (!CY_PSOC5A) */\r
+\r
+\r
+#if(CY_PSOC5A)\r
+\r
+ #define CY_PM_PWRSYS_BUZZ_TR_512_TICKS (0x08u)\r
+ #define CY_PM_PWRSYS_BUZZ_TR_MASK (0xF0u)\r
+\r
+#endif /* (CY_PSOC5A) */\r
+\r
+\r
+#if(CY_PSOC5A)\r
+\r
+ /* Watchdog Timer Configuration Register */\r
+ #define CY_PM_WDT_CFG_CTW_RESET (0x80u)\r
+\r
+ /***************************************************************************\r
+ * The PICU interrupt type registers are divided into three sections where\r
+ * the registers addresses are consecutive.\r
+ ***************************************************************************/\r
+ #define CY_PM_PICU_0_6_INT_BASE (CYDEV_PICU_INTTYPE_PICU0_BASE )\r
+ #define CY_PM_PICU_12_INT_BASE (CYDEV_PICU_INTTYPE_PICU12_BASE)\r
+ #define CY_PM_PICU_15_INT_BASE (CYDEV_PICU_INTTYPE_PICU15_BASE)\r
+\r
+ #define CY_PM_PICU_0_6_INT_SIZE (CYDEV_PICU_INTTYPE_PICU0_SIZE + CYDEV_PICU_INTTYPE_PICU1_SIZE + \\r
+ CYDEV_PICU_INTTYPE_PICU2_SIZE + CYDEV_PICU_INTTYPE_PICU3_SIZE + \\r
+ CYDEV_PICU_INTTYPE_PICU4_SIZE + CYDEV_PICU_INTTYPE_PICU5_SIZE + \\r
+ CYDEV_PICU_INTTYPE_PICU6_SIZE)\r
+ #define CY_PM_PICU_12_INT_SIZE (CYDEV_PICU_INTTYPE_PICU12_SIZE)\r
+ #define CY_PM_PICU_15_INT_SIZE (CYDEV_PICU_INTTYPE_PICU15_SIZE)\r
+\r
+#endif /* (CY_PSOC5A) */\r
+\r
+/* Boost Control 2: Select external precision reference */\r
+#define CY_PM_BOOST_CR2_EREFSEL_EXT (0x08u)\r
+\r
+\r
+\r
+#if(CY_PSOC3)\r
+\r
+ #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu)\r
+ #define CY_PM_PWRSYS_WAKE_TR1 (0x90u)\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
+#if(CY_PSOC5LP)\r
+\r
+ #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu)\r
+ #define CY_PM_PWRSYS_WAKE_TR1 (0xB0u)\r
+\r
+#endif /* (CY_PSOC5LP) */\r
+\r
+\r
+/*******************************************************************************\r
+* Following code are OBSOLETE and must not be used starting from cy_boot 3.30\r
+*******************************************************************************/\r
+#if(CY_PSOC3)\r
+\r
+ /* Was removed as redundant */\r
+ #define CY_PM_FTW_INTERVAL_MASK (0xFFu)\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+/* Was removed as redundant */\r
+#define CY_PM_CTW_INTERVAL_MASK (0x0Fu)\r
+\r
+#endif /* (CY_BOOT_CYPM_H) */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* FILENAME: cydevice.h\r
+* OBSOLETE: Do not use this file. Use the _trm version instead.\r
+* PSoC Creator 2.2 Component Pack 6\r
+*\r
+* DESCRIPTION:\r
+* This file provides all of the address values for the entire PSoC device.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+********************************************************************************/\r
+\r
+#if !defined(CYDEVICE_H)\r
+#define CYDEVICE_H\r
+#define CYDEV_FLASH_BASE 0x00000000u\r
+#define CYDEV_FLASH_SIZE 0x00040000u\r
+#define CYDEV_FLASH_DATA_MBASE 0x00000000u\r
+#define CYDEV_FLASH_DATA_MSIZE 0x00040000u\r
+#define CYDEV_SRAM_BASE 0x1fff8000u\r
+#define CYDEV_SRAM_SIZE 0x00010000u\r
+#define CYDEV_SRAM_CODE64K_MBASE 0x1fff8000u\r
+#define CYDEV_SRAM_CODE64K_MSIZE 0x00004000u\r
+#define CYDEV_SRAM_CODE32K_MBASE 0x1fffc000u\r
+#define CYDEV_SRAM_CODE32K_MSIZE 0x00002000u\r
+#define CYDEV_SRAM_CODE16K_MBASE 0x1fffe000u\r
+#define CYDEV_SRAM_CODE16K_MSIZE 0x00001000u\r
+#define CYDEV_SRAM_CODE_MBASE 0x1fff8000u\r
+#define CYDEV_SRAM_CODE_MSIZE 0x00008000u\r
+#define CYDEV_SRAM_DATA_MBASE 0x20000000u\r
+#define CYDEV_SRAM_DATA_MSIZE 0x00008000u\r
+#define CYDEV_SRAM_DATA16K_MBASE 0x20001000u\r
+#define CYDEV_SRAM_DATA16K_MSIZE 0x00001000u\r
+#define CYDEV_SRAM_DATA32K_MBASE 0x20002000u\r
+#define CYDEV_SRAM_DATA32K_MSIZE 0x00002000u\r
+#define CYDEV_SRAM_DATA64K_MBASE 0x20004000u\r
+#define CYDEV_SRAM_DATA64K_MSIZE 0x00004000u\r
+#define CYDEV_DMA_BASE 0x20008000u\r
+#define CYDEV_DMA_SIZE 0x00008000u\r
+#define CYDEV_DMA_SRAM64K_MBASE 0x20008000u\r
+#define CYDEV_DMA_SRAM64K_MSIZE 0x00004000u\r
+#define CYDEV_DMA_SRAM32K_MBASE 0x2000c000u\r
+#define CYDEV_DMA_SRAM32K_MSIZE 0x00002000u\r
+#define CYDEV_DMA_SRAM16K_MBASE 0x2000e000u\r
+#define CYDEV_DMA_SRAM16K_MSIZE 0x00001000u\r
+#define CYDEV_DMA_SRAM_MBASE 0x2000f000u\r
+#define CYDEV_DMA_SRAM_MSIZE 0x00001000u\r
+#define CYDEV_CLKDIST_BASE 0x40004000u\r
+#define CYDEV_CLKDIST_SIZE 0x00000110u\r
+#define CYDEV_CLKDIST_CR 0x40004000u\r
+#define CYDEV_CLKDIST_LD 0x40004001u\r
+#define CYDEV_CLKDIST_WRK0 0x40004002u\r
+#define CYDEV_CLKDIST_WRK1 0x40004003u\r
+#define CYDEV_CLKDIST_MSTR0 0x40004004u\r
+#define CYDEV_CLKDIST_MSTR1 0x40004005u\r
+#define CYDEV_CLKDIST_BCFG0 0x40004006u\r
+#define CYDEV_CLKDIST_BCFG1 0x40004007u\r
+#define CYDEV_CLKDIST_BCFG2 0x40004008u\r
+#define CYDEV_CLKDIST_UCFG 0x40004009u\r
+#define CYDEV_CLKDIST_DLY0 0x4000400au\r
+#define CYDEV_CLKDIST_DLY1 0x4000400bu\r
+#define CYDEV_CLKDIST_DMASK 0x40004010u\r
+#define CYDEV_CLKDIST_AMASK 0x40004014u\r
+#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080u\r
+#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003u\r
+#define CYDEV_CLKDIST_DCFG0_CFG0 0x40004080u\r
+#define CYDEV_CLKDIST_DCFG0_CFG1 0x40004081u\r
+#define CYDEV_CLKDIST_DCFG0_CFG2 0x40004082u\r
+#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084u\r
+#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003u\r
+#define CYDEV_CLKDIST_DCFG1_CFG0 0x40004084u\r
+#define CYDEV_CLKDIST_DCFG1_CFG1 0x40004085u\r
+#define CYDEV_CLKDIST_DCFG1_CFG2 0x40004086u\r
+#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088u\r
+#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003u\r
+#define CYDEV_CLKDIST_DCFG2_CFG0 0x40004088u\r
+#define CYDEV_CLKDIST_DCFG2_CFG1 0x40004089u\r
+#define CYDEV_CLKDIST_DCFG2_CFG2 0x4000408au\r
+#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408cu\r
+#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003u\r
+#define CYDEV_CLKDIST_DCFG3_CFG0 0x4000408cu\r
+#define CYDEV_CLKDIST_DCFG3_CFG1 0x4000408du\r
+#define CYDEV_CLKDIST_DCFG3_CFG2 0x4000408eu\r
+#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090u\r
+#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003u\r
+#define CYDEV_CLKDIST_DCFG4_CFG0 0x40004090u\r
+#define CYDEV_CLKDIST_DCFG4_CFG1 0x40004091u\r
+#define CYDEV_CLKDIST_DCFG4_CFG2 0x40004092u\r
+#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094u\r
+#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003u\r
+#define CYDEV_CLKDIST_DCFG5_CFG0 0x40004094u\r
+#define CYDEV_CLKDIST_DCFG5_CFG1 0x40004095u\r
+#define CYDEV_CLKDIST_DCFG5_CFG2 0x40004096u\r
+#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098u\r
+#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003u\r
+#define CYDEV_CLKDIST_DCFG6_CFG0 0x40004098u\r
+#define CYDEV_CLKDIST_DCFG6_CFG1 0x40004099u\r
+#define CYDEV_CLKDIST_DCFG6_CFG2 0x4000409au\r
+#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409cu\r
+#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003u\r
+#define CYDEV_CLKDIST_DCFG7_CFG0 0x4000409cu\r
+#define CYDEV_CLKDIST_DCFG7_CFG1 0x4000409du\r
+#define CYDEV_CLKDIST_DCFG7_CFG2 0x4000409eu\r
+#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100u\r
+#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004u\r
+#define CYDEV_CLKDIST_ACFG0_CFG0 0x40004100u\r
+#define CYDEV_CLKDIST_ACFG0_CFG1 0x40004101u\r
+#define CYDEV_CLKDIST_ACFG0_CFG2 0x40004102u\r
+#define CYDEV_CLKDIST_ACFG0_CFG3 0x40004103u\r
+#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104u\r
+#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004u\r
+#define CYDEV_CLKDIST_ACFG1_CFG0 0x40004104u\r
+#define CYDEV_CLKDIST_ACFG1_CFG1 0x40004105u\r
+#define CYDEV_CLKDIST_ACFG1_CFG2 0x40004106u\r
+#define CYDEV_CLKDIST_ACFG1_CFG3 0x40004107u\r
+#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108u\r
+#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004u\r
+#define CYDEV_CLKDIST_ACFG2_CFG0 0x40004108u\r
+#define CYDEV_CLKDIST_ACFG2_CFG1 0x40004109u\r
+#define CYDEV_CLKDIST_ACFG2_CFG2 0x4000410au\r
+#define CYDEV_CLKDIST_ACFG2_CFG3 0x4000410bu\r
+#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410cu\r
+#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004u\r
+#define CYDEV_CLKDIST_ACFG3_CFG0 0x4000410cu\r
+#define CYDEV_CLKDIST_ACFG3_CFG1 0x4000410du\r
+#define CYDEV_CLKDIST_ACFG3_CFG2 0x4000410eu\r
+#define CYDEV_CLKDIST_ACFG3_CFG3 0x4000410fu\r
+#define CYDEV_FASTCLK_BASE 0x40004200u\r
+#define CYDEV_FASTCLK_SIZE 0x00000026u\r
+#define CYDEV_FASTCLK_IMO_BASE 0x40004200u\r
+#define CYDEV_FASTCLK_IMO_SIZE 0x00000001u\r
+#define CYDEV_FASTCLK_IMO_CR 0x40004200u\r
+#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210u\r
+#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004u\r
+#define CYDEV_FASTCLK_XMHZ_CSR 0x40004210u\r
+#define CYDEV_FASTCLK_XMHZ_CFG0 0x40004212u\r
+#define CYDEV_FASTCLK_XMHZ_CFG1 0x40004213u\r
+#define CYDEV_FASTCLK_PLL_BASE 0x40004220u\r
+#define CYDEV_FASTCLK_PLL_SIZE 0x00000006u\r
+#define CYDEV_FASTCLK_PLL_CFG0 0x40004220u\r
+#define CYDEV_FASTCLK_PLL_CFG1 0x40004221u\r
+#define CYDEV_FASTCLK_PLL_P 0x40004222u\r
+#define CYDEV_FASTCLK_PLL_Q 0x40004223u\r
+#define CYDEV_FASTCLK_PLL_SR 0x40004225u\r
+#define CYDEV_SLOWCLK_BASE 0x40004300u\r
+#define CYDEV_SLOWCLK_SIZE 0x0000000bu\r
+#define CYDEV_SLOWCLK_ILO_BASE 0x40004300u\r
+#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002u\r
+#define CYDEV_SLOWCLK_ILO_CR0 0x40004300u\r
+#define CYDEV_SLOWCLK_ILO_CR1 0x40004301u\r
+#define CYDEV_SLOWCLK_X32_BASE 0x40004308u\r
+#define CYDEV_SLOWCLK_X32_SIZE 0x00000003u\r
+#define CYDEV_SLOWCLK_X32_CR 0x40004308u\r
+#define CYDEV_SLOWCLK_X32_CFG 0x40004309u\r
+#define CYDEV_SLOWCLK_X32_TST 0x4000430au\r
+#define CYDEV_BOOST_BASE 0x40004320u\r
+#define CYDEV_BOOST_SIZE 0x00000007u\r
+#define CYDEV_BOOST_CR0 0x40004320u\r
+#define CYDEV_BOOST_CR1 0x40004321u\r
+#define CYDEV_BOOST_CR2 0x40004322u\r
+#define CYDEV_BOOST_CR3 0x40004323u\r
+#define CYDEV_BOOST_SR 0x40004324u\r
+#define CYDEV_BOOST_CR4 0x40004325u\r
+#define CYDEV_BOOST_SR2 0x40004326u\r
+#define CYDEV_PWRSYS_BASE 0x40004330u\r
+#define CYDEV_PWRSYS_SIZE 0x00000002u\r
+#define CYDEV_PWRSYS_CR0 0x40004330u\r
+#define CYDEV_PWRSYS_CR1 0x40004331u\r
+#define CYDEV_PM_BASE 0x40004380u\r
+#define CYDEV_PM_SIZE 0x00000057u\r
+#define CYDEV_PM_TW_CFG0 0x40004380u\r
+#define CYDEV_PM_TW_CFG1 0x40004381u\r
+#define CYDEV_PM_TW_CFG2 0x40004382u\r
+#define CYDEV_PM_WDT_CFG 0x40004383u\r
+#define CYDEV_PM_WDT_CR 0x40004384u\r
+#define CYDEV_PM_INT_SR 0x40004390u\r
+#define CYDEV_PM_MODE_CFG0 0x40004391u\r
+#define CYDEV_PM_MODE_CFG1 0x40004392u\r
+#define CYDEV_PM_MODE_CSR 0x40004393u\r
+#define CYDEV_PM_USB_CR0 0x40004394u\r
+#define CYDEV_PM_WAKEUP_CFG0 0x40004398u\r
+#define CYDEV_PM_WAKEUP_CFG1 0x40004399u\r
+#define CYDEV_PM_WAKEUP_CFG2 0x4000439au\r
+#define CYDEV_PM_ACT_BASE 0x400043a0u\r
+#define CYDEV_PM_ACT_SIZE 0x0000000eu\r
+#define CYDEV_PM_ACT_CFG0 0x400043a0u\r
+#define CYDEV_PM_ACT_CFG1 0x400043a1u\r
+#define CYDEV_PM_ACT_CFG2 0x400043a2u\r
+#define CYDEV_PM_ACT_CFG3 0x400043a3u\r
+#define CYDEV_PM_ACT_CFG4 0x400043a4u\r
+#define CYDEV_PM_ACT_CFG5 0x400043a5u\r
+#define CYDEV_PM_ACT_CFG6 0x400043a6u\r
+#define CYDEV_PM_ACT_CFG7 0x400043a7u\r
+#define CYDEV_PM_ACT_CFG8 0x400043a8u\r
+#define CYDEV_PM_ACT_CFG9 0x400043a9u\r
+#define CYDEV_PM_ACT_CFG10 0x400043aau\r
+#define CYDEV_PM_ACT_CFG11 0x400043abu\r
+#define CYDEV_PM_ACT_CFG12 0x400043acu\r
+#define CYDEV_PM_ACT_CFG13 0x400043adu\r
+#define CYDEV_PM_STBY_BASE 0x400043b0u\r
+#define CYDEV_PM_STBY_SIZE 0x0000000eu\r
+#define CYDEV_PM_STBY_CFG0 0x400043b0u\r
+#define CYDEV_PM_STBY_CFG1 0x400043b1u\r
+#define CYDEV_PM_STBY_CFG2 0x400043b2u\r
+#define CYDEV_PM_STBY_CFG3 0x400043b3u\r
+#define CYDEV_PM_STBY_CFG4 0x400043b4u\r
+#define CYDEV_PM_STBY_CFG5 0x400043b5u\r
+#define CYDEV_PM_STBY_CFG6 0x400043b6u\r
+#define CYDEV_PM_STBY_CFG7 0x400043b7u\r
+#define CYDEV_PM_STBY_CFG8 0x400043b8u\r
+#define CYDEV_PM_STBY_CFG9 0x400043b9u\r
+#define CYDEV_PM_STBY_CFG10 0x400043bau\r
+#define CYDEV_PM_STBY_CFG11 0x400043bbu\r
+#define CYDEV_PM_STBY_CFG12 0x400043bcu\r
+#define CYDEV_PM_STBY_CFG13 0x400043bdu\r
+#define CYDEV_PM_AVAIL_BASE 0x400043c0u\r
+#define CYDEV_PM_AVAIL_SIZE 0x00000017u\r
+#define CYDEV_PM_AVAIL_CR0 0x400043c0u\r
+#define CYDEV_PM_AVAIL_CR1 0x400043c1u\r
+#define CYDEV_PM_AVAIL_CR2 0x400043c2u\r
+#define CYDEV_PM_AVAIL_CR3 0x400043c3u\r
+#define CYDEV_PM_AVAIL_CR4 0x400043c4u\r
+#define CYDEV_PM_AVAIL_CR5 0x400043c5u\r
+#define CYDEV_PM_AVAIL_CR6 0x400043c6u\r
+#define CYDEV_PM_AVAIL_SR0 0x400043d0u\r
+#define CYDEV_PM_AVAIL_SR1 0x400043d1u\r
+#define CYDEV_PM_AVAIL_SR2 0x400043d2u\r
+#define CYDEV_PM_AVAIL_SR3 0x400043d3u\r
+#define CYDEV_PM_AVAIL_SR4 0x400043d4u\r
+#define CYDEV_PM_AVAIL_SR5 0x400043d5u\r
+#define CYDEV_PM_AVAIL_SR6 0x400043d6u\r
+#define CYDEV_PICU_BASE 0x40004500u\r
+#define CYDEV_PICU_SIZE 0x000000b0u\r
+#define CYDEV_PICU_INTTYPE_BASE 0x40004500u\r
+#define CYDEV_PICU_INTTYPE_SIZE 0x00000080u\r
+#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500u\r
+#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008u\r
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 0x40004500u\r
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 0x40004501u\r
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 0x40004502u\r
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 0x40004503u\r
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 0x40004504u\r
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 0x40004505u\r
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 0x40004506u\r
+#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 0x40004507u\r
+#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508u\r
+#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008u\r
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 0x40004508u\r
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 0x40004509u\r
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 0x4000450au\r
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 0x4000450bu\r
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 0x4000450cu\r
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 0x4000450du\r
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 0x4000450eu\r
+#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 0x4000450fu\r
+#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510u\r
+#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008u\r
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 0x40004510u\r
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 0x40004511u\r
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 0x40004512u\r
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 0x40004513u\r
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 0x40004514u\r
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 0x40004515u\r
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 0x40004516u\r
+#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 0x40004517u\r
+#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518u\r
+#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008u\r
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 0x40004518u\r
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 0x40004519u\r
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 0x4000451au\r
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 0x4000451bu\r
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 0x4000451cu\r
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 0x4000451du\r
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 0x4000451eu\r
+#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 0x4000451fu\r
+#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520u\r
+#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008u\r
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 0x40004520u\r
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 0x40004521u\r
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 0x40004522u\r
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 0x40004523u\r
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 0x40004524u\r
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 0x40004525u\r
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 0x40004526u\r
+#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 0x40004527u\r
+#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528u\r
+#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008u\r
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 0x40004528u\r
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 0x40004529u\r
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 0x4000452au\r
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 0x4000452bu\r
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 0x4000452cu\r
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 0x4000452du\r
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 0x4000452eu\r
+#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 0x4000452fu\r
+#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530u\r
+#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008u\r
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 0x40004530u\r
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 0x40004531u\r
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 0x40004532u\r
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 0x40004533u\r
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 0x40004534u\r
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 0x40004535u\r
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 0x40004536u\r
+#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 0x40004537u\r
+#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560u\r
+#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008u\r
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 0x40004560u\r
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 0x40004561u\r
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 0x40004562u\r
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 0x40004563u\r
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 0x40004564u\r
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 0x40004565u\r
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 0x40004566u\r
+#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 0x40004567u\r
+#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578u\r
+#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008u\r
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 0x40004578u\r
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 0x40004579u\r
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 0x4000457au\r
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 0x4000457bu\r
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 0x4000457cu\r
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 0x4000457du\r
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 0x4000457eu\r
+#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 0x4000457fu\r
+#define CYDEV_PICU_STAT_BASE 0x40004580u\r
+#define CYDEV_PICU_STAT_SIZE 0x00000010u\r
+#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580u\r
+#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001u\r
+#define CYDEV_PICU_STAT_PICU0_INTSTAT 0x40004580u\r
+#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581u\r
+#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001u\r
+#define CYDEV_PICU_STAT_PICU1_INTSTAT 0x40004581u\r
+#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582u\r
+#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001u\r
+#define CYDEV_PICU_STAT_PICU2_INTSTAT 0x40004582u\r
+#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583u\r
+#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001u\r
+#define CYDEV_PICU_STAT_PICU3_INTSTAT 0x40004583u\r
+#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584u\r
+#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001u\r
+#define CYDEV_PICU_STAT_PICU4_INTSTAT 0x40004584u\r
+#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585u\r
+#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001u\r
+#define CYDEV_PICU_STAT_PICU5_INTSTAT 0x40004585u\r
+#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586u\r
+#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001u\r
+#define CYDEV_PICU_STAT_PICU6_INTSTAT 0x40004586u\r
+#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458cu\r
+#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001u\r
+#define CYDEV_PICU_STAT_PICU12_INTSTAT 0x4000458cu\r
+#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458fu\r
+#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001u\r
+#define CYDEV_PICU_STAT_PICU15_INTSTAT 0x4000458fu\r
+#define CYDEV_PICU_SNAP_BASE 0x40004590u\r
+#define CYDEV_PICU_SNAP_SIZE 0x00000010u\r
+#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590u\r
+#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001u\r
+#define CYDEV_PICU_SNAP_PICU0_SNAP 0x40004590u\r
+#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591u\r
+#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001u\r
+#define CYDEV_PICU_SNAP_PICU1_SNAP 0x40004591u\r
+#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592u\r
+#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001u\r
+#define CYDEV_PICU_SNAP_PICU2_SNAP 0x40004592u\r
+#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593u\r
+#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001u\r
+#define CYDEV_PICU_SNAP_PICU3_SNAP 0x40004593u\r
+#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594u\r
+#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001u\r
+#define CYDEV_PICU_SNAP_PICU4_SNAP 0x40004594u\r
+#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595u\r
+#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001u\r
+#define CYDEV_PICU_SNAP_PICU5_SNAP 0x40004595u\r
+#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596u\r
+#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001u\r
+#define CYDEV_PICU_SNAP_PICU6_SNAP 0x40004596u\r
+#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459cu\r
+#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001u\r
+#define CYDEV_PICU_SNAP_PICU12_SNAP 0x4000459cu\r
+#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459fu\r
+#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001u\r
+#define CYDEV_PICU_SNAP_PICU_15_SNAP_15 0x4000459fu\r
+#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0u\r
+#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010u\r
+#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0u\r
+#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001u\r
+#define CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR 0x400045a0u\r
+#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1u\r
+#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001u\r
+#define CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR 0x400045a1u\r
+#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2u\r
+#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001u\r
+#define CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR 0x400045a2u\r
+#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3u\r
+#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001u\r
+#define CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR 0x400045a3u\r
+#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4u\r
+#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001u\r
+#define CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR 0x400045a4u\r
+#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5u\r
+#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001u\r
+#define CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR 0x400045a5u\r
+#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6u\r
+#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001u\r
+#define CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR 0x400045a6u\r
+#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045acu\r
+#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001u\r
+#define CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR 0x400045acu\r
+#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045afu\r
+#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001u\r
+#define CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR 0x400045afu\r
+#define CYDEV_MFGCFG_BASE 0x40004600u\r
+#define CYDEV_MFGCFG_SIZE 0x000000edu\r
+#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600u\r
+#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038u\r
+#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608u\r
+#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001u\r
+#define CYDEV_MFGCFG_ANAIF_DAC0_TR 0x40004608u\r
+#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609u\r
+#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001u\r
+#define CYDEV_MFGCFG_ANAIF_DAC1_TR 0x40004609u\r
+#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460au\r
+#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001u\r
+#define CYDEV_MFGCFG_ANAIF_DAC2_TR 0x4000460au\r
+#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460bu\r
+#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001u\r
+#define CYDEV_MFGCFG_ANAIF_DAC3_TR 0x4000460bu\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610u\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001u\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 0x40004610u\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611u\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001u\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 0x40004611u\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612u\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001u\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 0x40004612u\r
+#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614u\r
+#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001u\r
+#define CYDEV_MFGCFG_ANAIF_SAR0_TR0 0x40004614u\r
+#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616u\r
+#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001u\r
+#define CYDEV_MFGCFG_ANAIF_SAR1_TR0 0x40004616u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 0x40004620u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 0x40004621u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 0x40004622u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 0x40004623u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 0x40004624u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 0x40004625u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 0x40004626u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 0x40004627u\r
+#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630u\r
+#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002u\r
+#define CYDEV_MFGCFG_ANAIF_CMP0_TR0 0x40004630u\r
+#define CYDEV_MFGCFG_ANAIF_CMP0_TR1 0x40004631u\r
+#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632u\r
+#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002u\r
+#define CYDEV_MFGCFG_ANAIF_CMP1_TR0 0x40004632u\r
+#define CYDEV_MFGCFG_ANAIF_CMP1_TR1 0x40004633u\r
+#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634u\r
+#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002u\r
+#define CYDEV_MFGCFG_ANAIF_CMP2_TR0 0x40004634u\r
+#define CYDEV_MFGCFG_ANAIF_CMP2_TR1 0x40004635u\r
+#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636u\r
+#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002u\r
+#define CYDEV_MFGCFG_ANAIF_CMP3_TR0 0x40004636u\r
+#define CYDEV_MFGCFG_ANAIF_CMP3_TR1 0x40004637u\r
+#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680u\r
+#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000bu\r
+#define CYDEV_MFGCFG_PWRSYS_HIB_TR0 0x40004680u\r
+#define CYDEV_MFGCFG_PWRSYS_HIB_TR1 0x40004681u\r
+#define CYDEV_MFGCFG_PWRSYS_I2C_TR 0x40004682u\r
+#define CYDEV_MFGCFG_PWRSYS_SLP_TR 0x40004683u\r
+#define CYDEV_MFGCFG_PWRSYS_BUZZ_TR 0x40004684u\r
+#define CYDEV_MFGCFG_PWRSYS_WAKE_TR0 0x40004685u\r
+#define CYDEV_MFGCFG_PWRSYS_WAKE_TR1 0x40004686u\r
+#define CYDEV_MFGCFG_PWRSYS_BREF_TR 0x40004687u\r
+#define CYDEV_MFGCFG_PWRSYS_BG_TR 0x40004688u\r
+#define CYDEV_MFGCFG_PWRSYS_WAKE_TR2 0x40004689u\r
+#define CYDEV_MFGCFG_PWRSYS_WAKE_TR3 0x4000468au\r
+#define CYDEV_MFGCFG_ILO_BASE 0x40004690u\r
+#define CYDEV_MFGCFG_ILO_SIZE 0x00000002u\r
+#define CYDEV_MFGCFG_ILO_TR0 0x40004690u\r
+#define CYDEV_MFGCFG_ILO_TR1 0x40004691u\r
+#define CYDEV_MFGCFG_X32_BASE 0x40004698u\r
+#define CYDEV_MFGCFG_X32_SIZE 0x00000001u\r
+#define CYDEV_MFGCFG_X32_TR 0x40004698u\r
+#define CYDEV_MFGCFG_IMO_BASE 0x400046a0u\r
+#define CYDEV_MFGCFG_IMO_SIZE 0x00000005u\r
+#define CYDEV_MFGCFG_IMO_TR0 0x400046a0u\r
+#define CYDEV_MFGCFG_IMO_TR1 0x400046a1u\r
+#define CYDEV_MFGCFG_IMO_GAIN 0x400046a2u\r
+#define CYDEV_MFGCFG_IMO_C36M 0x400046a3u\r
+#define CYDEV_MFGCFG_IMO_TR2 0x400046a4u\r
+#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8u\r
+#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001u\r
+#define CYDEV_MFGCFG_XMHZ_TR 0x400046a8u\r
+#define CYDEV_MFGCFG_DLY 0x400046c0u\r
+#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0u\r
+#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000du\r
+#define CYDEV_MFGCFG_MLOGIC_DMPSTR 0x400046e2u\r
+#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4u\r
+#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002u\r
+#define CYDEV_MFGCFG_MLOGIC_SEG_CR 0x400046e4u\r
+#define CYDEV_MFGCFG_MLOGIC_SEG_CFG0 0x400046e5u\r
+#define CYDEV_MFGCFG_MLOGIC_DEBUG 0x400046e8u\r
+#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046eau\r
+#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001u\r
+#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR 0x400046eau\r
+#define CYDEV_MFGCFG_MLOGIC_REV_ID 0x400046ecu\r
+#define CYDEV_RESET_BASE 0x400046f0u\r
+#define CYDEV_RESET_SIZE 0x0000000fu\r
+#define CYDEV_RESET_IPOR_CR0 0x400046f0u\r
+#define CYDEV_RESET_IPOR_CR1 0x400046f1u\r
+#define CYDEV_RESET_IPOR_CR2 0x400046f2u\r
+#define CYDEV_RESET_IPOR_CR3 0x400046f3u\r
+#define CYDEV_RESET_CR0 0x400046f4u\r
+#define CYDEV_RESET_CR1 0x400046f5u\r
+#define CYDEV_RESET_CR2 0x400046f6u\r
+#define CYDEV_RESET_CR3 0x400046f7u\r
+#define CYDEV_RESET_CR4 0x400046f8u\r
+#define CYDEV_RESET_CR5 0x400046f9u\r
+#define CYDEV_RESET_SR0 0x400046fau\r
+#define CYDEV_RESET_SR1 0x400046fbu\r
+#define CYDEV_RESET_SR2 0x400046fcu\r
+#define CYDEV_RESET_SR3 0x400046fdu\r
+#define CYDEV_RESET_TR 0x400046feu\r
+#define CYDEV_SPC_BASE 0x40004700u\r
+#define CYDEV_SPC_SIZE 0x00000100u\r
+#define CYDEV_SPC_FM_EE_CR 0x40004700u\r
+#define CYDEV_SPC_FM_EE_WAKE_CNT 0x40004701u\r
+#define CYDEV_SPC_EE_SCR 0x40004702u\r
+#define CYDEV_SPC_EE_ERR 0x40004703u\r
+#define CYDEV_SPC_CPU_DATA 0x40004720u\r
+#define CYDEV_SPC_DMA_DATA 0x40004721u\r
+#define CYDEV_SPC_SR 0x40004722u\r
+#define CYDEV_SPC_CR 0x40004723u\r
+#define CYDEV_SPC_DMM_MAP_BASE 0x40004780u\r
+#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080u\r
+#define CYDEV_SPC_DMM_MAP_SRAM_MBASE 0x40004780u\r
+#define CYDEV_SPC_DMM_MAP_SRAM_MSIZE 0x00000080u\r
+#define CYDEV_CACHE_BASE 0x40004800u\r
+#define CYDEV_CACHE_SIZE 0x0000009cu\r
+#define CYDEV_CACHE_CC_CTL 0x40004800u\r
+#define CYDEV_CACHE_ECC_CORR 0x40004880u\r
+#define CYDEV_CACHE_ECC_ERR 0x40004888u\r
+#define CYDEV_CACHE_FLASH_ERR 0x40004890u\r
+#define CYDEV_CACHE_HITMISS 0x40004898u\r
+#define CYDEV_I2C_BASE 0x40004900u\r
+#define CYDEV_I2C_SIZE 0x000000e1u\r
+#define CYDEV_I2C_XCFG 0x400049c8u\r
+#define CYDEV_I2C_ADR 0x400049cau\r
+#define CYDEV_I2C_CFG 0x400049d6u\r
+#define CYDEV_I2C_CSR 0x400049d7u\r
+#define CYDEV_I2C_D 0x400049d8u\r
+#define CYDEV_I2C_MCSR 0x400049d9u\r
+#define CYDEV_I2C_CLK_DIV1 0x400049dbu\r
+#define CYDEV_I2C_CLK_DIV2 0x400049dcu\r
+#define CYDEV_I2C_TMOUT_CSR 0x400049ddu\r
+#define CYDEV_I2C_TMOUT_SR 0x400049deu\r
+#define CYDEV_I2C_TMOUT_CFG0 0x400049dfu\r
+#define CYDEV_I2C_TMOUT_CFG1 0x400049e0u\r
+#define CYDEV_DEC_BASE 0x40004e00u\r
+#define CYDEV_DEC_SIZE 0x00000015u\r
+#define CYDEV_DEC_CR 0x40004e00u\r
+#define CYDEV_DEC_SR 0x40004e01u\r
+#define CYDEV_DEC_SHIFT1 0x40004e02u\r
+#define CYDEV_DEC_SHIFT2 0x40004e03u\r
+#define CYDEV_DEC_DR2 0x40004e04u\r
+#define CYDEV_DEC_DR2H 0x40004e05u\r
+#define CYDEV_DEC_DR1 0x40004e06u\r
+#define CYDEV_DEC_OCOR 0x40004e08u\r
+#define CYDEV_DEC_OCORM 0x40004e09u\r
+#define CYDEV_DEC_OCORH 0x40004e0au\r
+#define CYDEV_DEC_GCOR 0x40004e0cu\r
+#define CYDEV_DEC_GCORH 0x40004e0du\r
+#define CYDEV_DEC_GVAL 0x40004e0eu\r
+#define CYDEV_DEC_OUTSAMP 0x40004e10u\r
+#define CYDEV_DEC_OUTSAMPM 0x40004e11u\r
+#define CYDEV_DEC_OUTSAMPH 0x40004e12u\r
+#define CYDEV_DEC_OUTSAMPS 0x40004e13u\r
+#define CYDEV_DEC_COHER 0x40004e14u\r
+#define CYDEV_TMR0_BASE 0x40004f00u\r
+#define CYDEV_TMR0_SIZE 0x0000000cu\r
+#define CYDEV_TMR0_CFG0 0x40004f00u\r
+#define CYDEV_TMR0_CFG1 0x40004f01u\r
+#define CYDEV_TMR0_CFG2 0x40004f02u\r
+#define CYDEV_TMR0_SR0 0x40004f03u\r
+#define CYDEV_TMR0_PER0 0x40004f04u\r
+#define CYDEV_TMR0_PER1 0x40004f05u\r
+#define CYDEV_TMR0_CNT_CMP0 0x40004f06u\r
+#define CYDEV_TMR0_CNT_CMP1 0x40004f07u\r
+#define CYDEV_TMR0_CAP0 0x40004f08u\r
+#define CYDEV_TMR0_CAP1 0x40004f09u\r
+#define CYDEV_TMR0_RT0 0x40004f0au\r
+#define CYDEV_TMR0_RT1 0x40004f0bu\r
+#define CYDEV_TMR1_BASE 0x40004f0cu\r
+#define CYDEV_TMR1_SIZE 0x0000000cu\r
+#define CYDEV_TMR1_CFG0 0x40004f0cu\r
+#define CYDEV_TMR1_CFG1 0x40004f0du\r
+#define CYDEV_TMR1_CFG2 0x40004f0eu\r
+#define CYDEV_TMR1_SR0 0x40004f0fu\r
+#define CYDEV_TMR1_PER0 0x40004f10u\r
+#define CYDEV_TMR1_PER1 0x40004f11u\r
+#define CYDEV_TMR1_CNT_CMP0 0x40004f12u\r
+#define CYDEV_TMR1_CNT_CMP1 0x40004f13u\r
+#define CYDEV_TMR1_CAP0 0x40004f14u\r
+#define CYDEV_TMR1_CAP1 0x40004f15u\r
+#define CYDEV_TMR1_RT0 0x40004f16u\r
+#define CYDEV_TMR1_RT1 0x40004f17u\r
+#define CYDEV_TMR2_BASE 0x40004f18u\r
+#define CYDEV_TMR2_SIZE 0x0000000cu\r
+#define CYDEV_TMR2_CFG0 0x40004f18u\r
+#define CYDEV_TMR2_CFG1 0x40004f19u\r
+#define CYDEV_TMR2_CFG2 0x40004f1au\r
+#define CYDEV_TMR2_SR0 0x40004f1bu\r
+#define CYDEV_TMR2_PER0 0x40004f1cu\r
+#define CYDEV_TMR2_PER1 0x40004f1du\r
+#define CYDEV_TMR2_CNT_CMP0 0x40004f1eu\r
+#define CYDEV_TMR2_CNT_CMP1 0x40004f1fu\r
+#define CYDEV_TMR2_CAP0 0x40004f20u\r
+#define CYDEV_TMR2_CAP1 0x40004f21u\r
+#define CYDEV_TMR2_RT0 0x40004f22u\r
+#define CYDEV_TMR2_RT1 0x40004f23u\r
+#define CYDEV_TMR3_BASE 0x40004f24u\r
+#define CYDEV_TMR3_SIZE 0x0000000cu\r
+#define CYDEV_TMR3_CFG0 0x40004f24u\r
+#define CYDEV_TMR3_CFG1 0x40004f25u\r
+#define CYDEV_TMR3_CFG2 0x40004f26u\r
+#define CYDEV_TMR3_SR0 0x40004f27u\r
+#define CYDEV_TMR3_PER0 0x40004f28u\r
+#define CYDEV_TMR3_PER1 0x40004f29u\r
+#define CYDEV_TMR3_CNT_CMP0 0x40004f2au\r
+#define CYDEV_TMR3_CNT_CMP1 0x40004f2bu\r
+#define CYDEV_TMR3_CAP0 0x40004f2cu\r
+#define CYDEV_TMR3_CAP1 0x40004f2du\r
+#define CYDEV_TMR3_RT0 0x40004f2eu\r
+#define CYDEV_TMR3_RT1 0x40004f2fu\r
+#define CYDEV_IO_BASE 0x40005000u\r
+#define CYDEV_IO_SIZE 0x00000200u\r
+#define CYDEV_IO_PC_BASE 0x40005000u\r
+#define CYDEV_IO_PC_SIZE 0x00000080u\r
+#define CYDEV_IO_PC_PRT0_BASE 0x40005000u\r
+#define CYDEV_IO_PC_PRT0_SIZE 0x00000008u\r
+#define CYDEV_IO_PC_PRT0_PC0 0x40005000u\r
+#define CYDEV_IO_PC_PRT0_PC1 0x40005001u\r
+#define CYDEV_IO_PC_PRT0_PC2 0x40005002u\r
+#define CYDEV_IO_PC_PRT0_PC3 0x40005003u\r
+#define CYDEV_IO_PC_PRT0_PC4 0x40005004u\r
+#define CYDEV_IO_PC_PRT0_PC5 0x40005005u\r
+#define CYDEV_IO_PC_PRT0_PC6 0x40005006u\r
+#define CYDEV_IO_PC_PRT0_PC7 0x40005007u\r
+#define CYDEV_IO_PC_PRT1_BASE 0x40005008u\r
+#define CYDEV_IO_PC_PRT1_SIZE 0x00000008u\r
+#define CYDEV_IO_PC_PRT1_PC0 0x40005008u\r
+#define CYDEV_IO_PC_PRT1_PC1 0x40005009u\r
+#define CYDEV_IO_PC_PRT1_PC2 0x4000500au\r
+#define CYDEV_IO_PC_PRT1_PC3 0x4000500bu\r
+#define CYDEV_IO_PC_PRT1_PC4 0x4000500cu\r
+#define CYDEV_IO_PC_PRT1_PC5 0x4000500du\r
+#define CYDEV_IO_PC_PRT1_PC6 0x4000500eu\r
+#define CYDEV_IO_PC_PRT1_PC7 0x4000500fu\r
+#define CYDEV_IO_PC_PRT2_BASE 0x40005010u\r
+#define CYDEV_IO_PC_PRT2_SIZE 0x00000008u\r
+#define CYDEV_IO_PC_PRT2_PC0 0x40005010u\r
+#define CYDEV_IO_PC_PRT2_PC1 0x40005011u\r
+#define CYDEV_IO_PC_PRT2_PC2 0x40005012u\r
+#define CYDEV_IO_PC_PRT2_PC3 0x40005013u\r
+#define CYDEV_IO_PC_PRT2_PC4 0x40005014u\r
+#define CYDEV_IO_PC_PRT2_PC5 0x40005015u\r
+#define CYDEV_IO_PC_PRT2_PC6 0x40005016u\r
+#define CYDEV_IO_PC_PRT2_PC7 0x40005017u\r
+#define CYDEV_IO_PC_PRT3_BASE 0x40005018u\r
+#define CYDEV_IO_PC_PRT3_SIZE 0x00000008u\r
+#define CYDEV_IO_PC_PRT3_PC0 0x40005018u\r
+#define CYDEV_IO_PC_PRT3_PC1 0x40005019u\r
+#define CYDEV_IO_PC_PRT3_PC2 0x4000501au\r
+#define CYDEV_IO_PC_PRT3_PC3 0x4000501bu\r
+#define CYDEV_IO_PC_PRT3_PC4 0x4000501cu\r
+#define CYDEV_IO_PC_PRT3_PC5 0x4000501du\r
+#define CYDEV_IO_PC_PRT3_PC6 0x4000501eu\r
+#define CYDEV_IO_PC_PRT3_PC7 0x4000501fu\r
+#define CYDEV_IO_PC_PRT4_BASE 0x40005020u\r
+#define CYDEV_IO_PC_PRT4_SIZE 0x00000008u\r
+#define CYDEV_IO_PC_PRT4_PC0 0x40005020u\r
+#define CYDEV_IO_PC_PRT4_PC1 0x40005021u\r
+#define CYDEV_IO_PC_PRT4_PC2 0x40005022u\r
+#define CYDEV_IO_PC_PRT4_PC3 0x40005023u\r
+#define CYDEV_IO_PC_PRT4_PC4 0x40005024u\r
+#define CYDEV_IO_PC_PRT4_PC5 0x40005025u\r
+#define CYDEV_IO_PC_PRT4_PC6 0x40005026u\r
+#define CYDEV_IO_PC_PRT4_PC7 0x40005027u\r
+#define CYDEV_IO_PC_PRT5_BASE 0x40005028u\r
+#define CYDEV_IO_PC_PRT5_SIZE 0x00000008u\r
+#define CYDEV_IO_PC_PRT5_PC0 0x40005028u\r
+#define CYDEV_IO_PC_PRT5_PC1 0x40005029u\r
+#define CYDEV_IO_PC_PRT5_PC2 0x4000502au\r
+#define CYDEV_IO_PC_PRT5_PC3 0x4000502bu\r
+#define CYDEV_IO_PC_PRT5_PC4 0x4000502cu\r
+#define CYDEV_IO_PC_PRT5_PC5 0x4000502du\r
+#define CYDEV_IO_PC_PRT5_PC6 0x4000502eu\r
+#define CYDEV_IO_PC_PRT5_PC7 0x4000502fu\r
+#define CYDEV_IO_PC_PRT6_BASE 0x40005030u\r
+#define CYDEV_IO_PC_PRT6_SIZE 0x00000008u\r
+#define CYDEV_IO_PC_PRT6_PC0 0x40005030u\r
+#define CYDEV_IO_PC_PRT6_PC1 0x40005031u\r
+#define CYDEV_IO_PC_PRT6_PC2 0x40005032u\r
+#define CYDEV_IO_PC_PRT6_PC3 0x40005033u\r
+#define CYDEV_IO_PC_PRT6_PC4 0x40005034u\r
+#define CYDEV_IO_PC_PRT6_PC5 0x40005035u\r
+#define CYDEV_IO_PC_PRT6_PC6 0x40005036u\r
+#define CYDEV_IO_PC_PRT6_PC7 0x40005037u\r
+#define CYDEV_IO_PC_PRT12_BASE 0x40005060u\r
+#define CYDEV_IO_PC_PRT12_SIZE 0x00000008u\r
+#define CYDEV_IO_PC_PRT12_PC0 0x40005060u\r
+#define CYDEV_IO_PC_PRT12_PC1 0x40005061u\r
+#define CYDEV_IO_PC_PRT12_PC2 0x40005062u\r
+#define CYDEV_IO_PC_PRT12_PC3 0x40005063u\r
+#define CYDEV_IO_PC_PRT12_PC4 0x40005064u\r
+#define CYDEV_IO_PC_PRT12_PC5 0x40005065u\r
+#define CYDEV_IO_PC_PRT12_PC6 0x40005066u\r
+#define CYDEV_IO_PC_PRT12_PC7 0x40005067u\r
+#define CYDEV_IO_PC_PRT15_BASE 0x40005078u\r
+#define CYDEV_IO_PC_PRT15_SIZE 0x00000006u\r
+#define CYDEV_IO_PC_PRT15_PC0 0x40005078u\r
+#define CYDEV_IO_PC_PRT15_PC1 0x40005079u\r
+#define CYDEV_IO_PC_PRT15_PC2 0x4000507au\r
+#define CYDEV_IO_PC_PRT15_PC3 0x4000507bu\r
+#define CYDEV_IO_PC_PRT15_PC4 0x4000507cu\r
+#define CYDEV_IO_PC_PRT15_PC5 0x4000507du\r
+#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507eu\r
+#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002u\r
+#define CYDEV_IO_PC_PRT15_7_6_PC0 0x4000507eu\r
+#define CYDEV_IO_PC_PRT15_7_6_PC1 0x4000507fu\r
+#define CYDEV_IO_DR_BASE 0x40005080u\r
+#define CYDEV_IO_DR_SIZE 0x00000010u\r
+#define CYDEV_IO_DR_PRT0_BASE 0x40005080u\r
+#define CYDEV_IO_DR_PRT0_SIZE 0x00000001u\r
+#define CYDEV_IO_DR_PRT0_DR_ALIAS 0x40005080u\r
+#define CYDEV_IO_DR_PRT1_BASE 0x40005081u\r
+#define CYDEV_IO_DR_PRT1_SIZE 0x00000001u\r
+#define CYDEV_IO_DR_PRT1_DR_ALIAS 0x40005081u\r
+#define CYDEV_IO_DR_PRT2_BASE 0x40005082u\r
+#define CYDEV_IO_DR_PRT2_SIZE 0x00000001u\r
+#define CYDEV_IO_DR_PRT2_DR_ALIAS 0x40005082u\r
+#define CYDEV_IO_DR_PRT3_BASE 0x40005083u\r
+#define CYDEV_IO_DR_PRT3_SIZE 0x00000001u\r
+#define CYDEV_IO_DR_PRT3_DR_ALIAS 0x40005083u\r
+#define CYDEV_IO_DR_PRT4_BASE 0x40005084u\r
+#define CYDEV_IO_DR_PRT4_SIZE 0x00000001u\r
+#define CYDEV_IO_DR_PRT4_DR_ALIAS 0x40005084u\r
+#define CYDEV_IO_DR_PRT5_BASE 0x40005085u\r
+#define CYDEV_IO_DR_PRT5_SIZE 0x00000001u\r
+#define CYDEV_IO_DR_PRT5_DR_ALIAS 0x40005085u\r
+#define CYDEV_IO_DR_PRT6_BASE 0x40005086u\r
+#define CYDEV_IO_DR_PRT6_SIZE 0x00000001u\r
+#define CYDEV_IO_DR_PRT6_DR_ALIAS 0x40005086u\r
+#define CYDEV_IO_DR_PRT12_BASE 0x4000508cu\r
+#define CYDEV_IO_DR_PRT12_SIZE 0x00000001u\r
+#define CYDEV_IO_DR_PRT12_DR_ALIAS 0x4000508cu\r
+#define CYDEV_IO_DR_PRT15_BASE 0x4000508fu\r
+#define CYDEV_IO_DR_PRT15_SIZE 0x00000001u\r
+#define CYDEV_IO_DR_PRT15_DR_15_ALIAS 0x4000508fu\r
+#define CYDEV_IO_PS_BASE 0x40005090u\r
+#define CYDEV_IO_PS_SIZE 0x00000010u\r
+#define CYDEV_IO_PS_PRT0_BASE 0x40005090u\r
+#define CYDEV_IO_PS_PRT0_SIZE 0x00000001u\r
+#define CYDEV_IO_PS_PRT0_PS_ALIAS 0x40005090u\r
+#define CYDEV_IO_PS_PRT1_BASE 0x40005091u\r
+#define CYDEV_IO_PS_PRT1_SIZE 0x00000001u\r
+#define CYDEV_IO_PS_PRT1_PS_ALIAS 0x40005091u\r
+#define CYDEV_IO_PS_PRT2_BASE 0x40005092u\r
+#define CYDEV_IO_PS_PRT2_SIZE 0x00000001u\r
+#define CYDEV_IO_PS_PRT2_PS_ALIAS 0x40005092u\r
+#define CYDEV_IO_PS_PRT3_BASE 0x40005093u\r
+#define CYDEV_IO_PS_PRT3_SIZE 0x00000001u\r
+#define CYDEV_IO_PS_PRT3_PS_ALIAS 0x40005093u\r
+#define CYDEV_IO_PS_PRT4_BASE 0x40005094u\r
+#define CYDEV_IO_PS_PRT4_SIZE 0x00000001u\r
+#define CYDEV_IO_PS_PRT4_PS_ALIAS 0x40005094u\r
+#define CYDEV_IO_PS_PRT5_BASE 0x40005095u\r
+#define CYDEV_IO_PS_PRT5_SIZE 0x00000001u\r
+#define CYDEV_IO_PS_PRT5_PS_ALIAS 0x40005095u\r
+#define CYDEV_IO_PS_PRT6_BASE 0x40005096u\r
+#define CYDEV_IO_PS_PRT6_SIZE 0x00000001u\r
+#define CYDEV_IO_PS_PRT6_PS_ALIAS 0x40005096u\r
+#define CYDEV_IO_PS_PRT12_BASE 0x4000509cu\r
+#define CYDEV_IO_PS_PRT12_SIZE 0x00000001u\r
+#define CYDEV_IO_PS_PRT12_PS_ALIAS 0x4000509cu\r
+#define CYDEV_IO_PS_PRT15_BASE 0x4000509fu\r
+#define CYDEV_IO_PS_PRT15_SIZE 0x00000001u\r
+#define CYDEV_IO_PS_PRT15_PS15_ALIAS 0x4000509fu\r
+#define CYDEV_IO_PRT_BASE 0x40005100u\r
+#define CYDEV_IO_PRT_SIZE 0x00000100u\r
+#define CYDEV_IO_PRT_PRT0_BASE 0x40005100u\r
+#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010u\r
+#define CYDEV_IO_PRT_PRT0_DR 0x40005100u\r
+#define CYDEV_IO_PRT_PRT0_PS 0x40005101u\r
+#define CYDEV_IO_PRT_PRT0_DM0 0x40005102u\r
+#define CYDEV_IO_PRT_PRT0_DM1 0x40005103u\r
+#define CYDEV_IO_PRT_PRT0_DM2 0x40005104u\r
+#define CYDEV_IO_PRT_PRT0_SLW 0x40005105u\r
+#define CYDEV_IO_PRT_PRT0_BYP 0x40005106u\r
+#define CYDEV_IO_PRT_PRT0_BIE 0x40005107u\r
+#define CYDEV_IO_PRT_PRT0_INP_DIS 0x40005108u\r
+#define CYDEV_IO_PRT_PRT0_CTL 0x40005109u\r
+#define CYDEV_IO_PRT_PRT0_PRT 0x4000510au\r
+#define CYDEV_IO_PRT_PRT0_BIT_MASK 0x4000510bu\r
+#define CYDEV_IO_PRT_PRT0_AMUX 0x4000510cu\r
+#define CYDEV_IO_PRT_PRT0_AG 0x4000510du\r
+#define CYDEV_IO_PRT_PRT0_LCD_COM_SEG 0x4000510eu\r
+#define CYDEV_IO_PRT_PRT0_LCD_EN 0x4000510fu\r
+#define CYDEV_IO_PRT_PRT1_BASE 0x40005110u\r
+#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010u\r
+#define CYDEV_IO_PRT_PRT1_DR 0x40005110u\r
+#define CYDEV_IO_PRT_PRT1_PS 0x40005111u\r
+#define CYDEV_IO_PRT_PRT1_DM0 0x40005112u\r
+#define CYDEV_IO_PRT_PRT1_DM1 0x40005113u\r
+#define CYDEV_IO_PRT_PRT1_DM2 0x40005114u\r
+#define CYDEV_IO_PRT_PRT1_SLW 0x40005115u\r
+#define CYDEV_IO_PRT_PRT1_BYP 0x40005116u\r
+#define CYDEV_IO_PRT_PRT1_BIE 0x40005117u\r
+#define CYDEV_IO_PRT_PRT1_INP_DIS 0x40005118u\r
+#define CYDEV_IO_PRT_PRT1_CTL 0x40005119u\r
+#define CYDEV_IO_PRT_PRT1_PRT 0x4000511au\r
+#define CYDEV_IO_PRT_PRT1_BIT_MASK 0x4000511bu\r
+#define CYDEV_IO_PRT_PRT1_AMUX 0x4000511cu\r
+#define CYDEV_IO_PRT_PRT1_AG 0x4000511du\r
+#define CYDEV_IO_PRT_PRT1_LCD_COM_SEG 0x4000511eu\r
+#define CYDEV_IO_PRT_PRT1_LCD_EN 0x4000511fu\r
+#define CYDEV_IO_PRT_PRT2_BASE 0x40005120u\r
+#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010u\r
+#define CYDEV_IO_PRT_PRT2_DR 0x40005120u\r
+#define CYDEV_IO_PRT_PRT2_PS 0x40005121u\r
+#define CYDEV_IO_PRT_PRT2_DM0 0x40005122u\r
+#define CYDEV_IO_PRT_PRT2_DM1 0x40005123u\r
+#define CYDEV_IO_PRT_PRT2_DM2 0x40005124u\r
+#define CYDEV_IO_PRT_PRT2_SLW 0x40005125u\r
+#define CYDEV_IO_PRT_PRT2_BYP 0x40005126u\r
+#define CYDEV_IO_PRT_PRT2_BIE 0x40005127u\r
+#define CYDEV_IO_PRT_PRT2_INP_DIS 0x40005128u\r
+#define CYDEV_IO_PRT_PRT2_CTL 0x40005129u\r
+#define CYDEV_IO_PRT_PRT2_PRT 0x4000512au\r
+#define CYDEV_IO_PRT_PRT2_BIT_MASK 0x4000512bu\r
+#define CYDEV_IO_PRT_PRT2_AMUX 0x4000512cu\r
+#define CYDEV_IO_PRT_PRT2_AG 0x4000512du\r
+#define CYDEV_IO_PRT_PRT2_LCD_COM_SEG 0x4000512eu\r
+#define CYDEV_IO_PRT_PRT2_LCD_EN 0x4000512fu\r
+#define CYDEV_IO_PRT_PRT3_BASE 0x40005130u\r
+#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010u\r
+#define CYDEV_IO_PRT_PRT3_DR 0x40005130u\r
+#define CYDEV_IO_PRT_PRT3_PS 0x40005131u\r
+#define CYDEV_IO_PRT_PRT3_DM0 0x40005132u\r
+#define CYDEV_IO_PRT_PRT3_DM1 0x40005133u\r
+#define CYDEV_IO_PRT_PRT3_DM2 0x40005134u\r
+#define CYDEV_IO_PRT_PRT3_SLW 0x40005135u\r
+#define CYDEV_IO_PRT_PRT3_BYP 0x40005136u\r
+#define CYDEV_IO_PRT_PRT3_BIE 0x40005137u\r
+#define CYDEV_IO_PRT_PRT3_INP_DIS 0x40005138u\r
+#define CYDEV_IO_PRT_PRT3_CTL 0x40005139u\r
+#define CYDEV_IO_PRT_PRT3_PRT 0x4000513au\r
+#define CYDEV_IO_PRT_PRT3_BIT_MASK 0x4000513bu\r
+#define CYDEV_IO_PRT_PRT3_AMUX 0x4000513cu\r
+#define CYDEV_IO_PRT_PRT3_AG 0x4000513du\r
+#define CYDEV_IO_PRT_PRT3_LCD_COM_SEG 0x4000513eu\r
+#define CYDEV_IO_PRT_PRT3_LCD_EN 0x4000513fu\r
+#define CYDEV_IO_PRT_PRT4_BASE 0x40005140u\r
+#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010u\r
+#define CYDEV_IO_PRT_PRT4_DR 0x40005140u\r
+#define CYDEV_IO_PRT_PRT4_PS 0x40005141u\r
+#define CYDEV_IO_PRT_PRT4_DM0 0x40005142u\r
+#define CYDEV_IO_PRT_PRT4_DM1 0x40005143u\r
+#define CYDEV_IO_PRT_PRT4_DM2 0x40005144u\r
+#define CYDEV_IO_PRT_PRT4_SLW 0x40005145u\r
+#define CYDEV_IO_PRT_PRT4_BYP 0x40005146u\r
+#define CYDEV_IO_PRT_PRT4_BIE 0x40005147u\r
+#define CYDEV_IO_PRT_PRT4_INP_DIS 0x40005148u\r
+#define CYDEV_IO_PRT_PRT4_CTL 0x40005149u\r
+#define CYDEV_IO_PRT_PRT4_PRT 0x4000514au\r
+#define CYDEV_IO_PRT_PRT4_BIT_MASK 0x4000514bu\r
+#define CYDEV_IO_PRT_PRT4_AMUX 0x4000514cu\r
+#define CYDEV_IO_PRT_PRT4_AG 0x4000514du\r
+#define CYDEV_IO_PRT_PRT4_LCD_COM_SEG 0x4000514eu\r
+#define CYDEV_IO_PRT_PRT4_LCD_EN 0x4000514fu\r
+#define CYDEV_IO_PRT_PRT5_BASE 0x40005150u\r
+#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010u\r
+#define CYDEV_IO_PRT_PRT5_DR 0x40005150u\r
+#define CYDEV_IO_PRT_PRT5_PS 0x40005151u\r
+#define CYDEV_IO_PRT_PRT5_DM0 0x40005152u\r
+#define CYDEV_IO_PRT_PRT5_DM1 0x40005153u\r
+#define CYDEV_IO_PRT_PRT5_DM2 0x40005154u\r
+#define CYDEV_IO_PRT_PRT5_SLW 0x40005155u\r
+#define CYDEV_IO_PRT_PRT5_BYP 0x40005156u\r
+#define CYDEV_IO_PRT_PRT5_BIE 0x40005157u\r
+#define CYDEV_IO_PRT_PRT5_INP_DIS 0x40005158u\r
+#define CYDEV_IO_PRT_PRT5_CTL 0x40005159u\r
+#define CYDEV_IO_PRT_PRT5_PRT 0x4000515au\r
+#define CYDEV_IO_PRT_PRT5_BIT_MASK 0x4000515bu\r
+#define CYDEV_IO_PRT_PRT5_AMUX 0x4000515cu\r
+#define CYDEV_IO_PRT_PRT5_AG 0x4000515du\r
+#define CYDEV_IO_PRT_PRT5_LCD_COM_SEG 0x4000515eu\r
+#define CYDEV_IO_PRT_PRT5_LCD_EN 0x4000515fu\r
+#define CYDEV_IO_PRT_PRT6_BASE 0x40005160u\r
+#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010u\r
+#define CYDEV_IO_PRT_PRT6_DR 0x40005160u\r
+#define CYDEV_IO_PRT_PRT6_PS 0x40005161u\r
+#define CYDEV_IO_PRT_PRT6_DM0 0x40005162u\r
+#define CYDEV_IO_PRT_PRT6_DM1 0x40005163u\r
+#define CYDEV_IO_PRT_PRT6_DM2 0x40005164u\r
+#define CYDEV_IO_PRT_PRT6_SLW 0x40005165u\r
+#define CYDEV_IO_PRT_PRT6_BYP 0x40005166u\r
+#define CYDEV_IO_PRT_PRT6_BIE 0x40005167u\r
+#define CYDEV_IO_PRT_PRT6_INP_DIS 0x40005168u\r
+#define CYDEV_IO_PRT_PRT6_CTL 0x40005169u\r
+#define CYDEV_IO_PRT_PRT6_PRT 0x4000516au\r
+#define CYDEV_IO_PRT_PRT6_BIT_MASK 0x4000516bu\r
+#define CYDEV_IO_PRT_PRT6_AMUX 0x4000516cu\r
+#define CYDEV_IO_PRT_PRT6_AG 0x4000516du\r
+#define CYDEV_IO_PRT_PRT6_LCD_COM_SEG 0x4000516eu\r
+#define CYDEV_IO_PRT_PRT6_LCD_EN 0x4000516fu\r
+#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0u\r
+#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010u\r
+#define CYDEV_IO_PRT_PRT12_DR 0x400051c0u\r
+#define CYDEV_IO_PRT_PRT12_PS 0x400051c1u\r
+#define CYDEV_IO_PRT_PRT12_DM0 0x400051c2u\r
+#define CYDEV_IO_PRT_PRT12_DM1 0x400051c3u\r
+#define CYDEV_IO_PRT_PRT12_DM2 0x400051c4u\r
+#define CYDEV_IO_PRT_PRT12_SLW 0x400051c5u\r
+#define CYDEV_IO_PRT_PRT12_BYP 0x400051c6u\r
+#define CYDEV_IO_PRT_PRT12_BIE 0x400051c7u\r
+#define CYDEV_IO_PRT_PRT12_INP_DIS 0x400051c8u\r
+#define CYDEV_IO_PRT_PRT12_SIO_HYST_EN 0x400051c9u\r
+#define CYDEV_IO_PRT_PRT12_PRT 0x400051cau\r
+#define CYDEV_IO_PRT_PRT12_BIT_MASK 0x400051cbu\r
+#define CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ 0x400051ccu\r
+#define CYDEV_IO_PRT_PRT12_AG 0x400051cdu\r
+#define CYDEV_IO_PRT_PRT12_SIO_CFG 0x400051ceu\r
+#define CYDEV_IO_PRT_PRT12_SIO_DIFF 0x400051cfu\r
+#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0u\r
+#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010u\r
+#define CYDEV_IO_PRT_PRT15_DR 0x400051f0u\r
+#define CYDEV_IO_PRT_PRT15_PS 0x400051f1u\r
+#define CYDEV_IO_PRT_PRT15_DM0 0x400051f2u\r
+#define CYDEV_IO_PRT_PRT15_DM1 0x400051f3u\r
+#define CYDEV_IO_PRT_PRT15_DM2 0x400051f4u\r
+#define CYDEV_IO_PRT_PRT15_SLW 0x400051f5u\r
+#define CYDEV_IO_PRT_PRT15_BYP 0x400051f6u\r
+#define CYDEV_IO_PRT_PRT15_BIE 0x400051f7u\r
+#define CYDEV_IO_PRT_PRT15_INP_DIS 0x400051f8u\r
+#define CYDEV_IO_PRT_PRT15_CTL 0x400051f9u\r
+#define CYDEV_IO_PRT_PRT15_PRT 0x400051fau\r
+#define CYDEV_IO_PRT_PRT15_BIT_MASK 0x400051fbu\r
+#define CYDEV_IO_PRT_PRT15_AMUX 0x400051fcu\r
+#define CYDEV_IO_PRT_PRT15_AG 0x400051fdu\r
+#define CYDEV_IO_PRT_PRT15_LCD_COM_SEG 0x400051feu\r
+#define CYDEV_IO_PRT_PRT15_LCD_EN 0x400051ffu\r
+#define CYDEV_PRTDSI_BASE 0x40005200u\r
+#define CYDEV_PRTDSI_SIZE 0x0000007fu\r
+#define CYDEV_PRTDSI_PRT0_BASE 0x40005200u\r
+#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007u\r
+#define CYDEV_PRTDSI_PRT0_OUT_SEL0 0x40005200u\r
+#define CYDEV_PRTDSI_PRT0_OUT_SEL1 0x40005201u\r
+#define CYDEV_PRTDSI_PRT0_OE_SEL0 0x40005202u\r
+#define CYDEV_PRTDSI_PRT0_OE_SEL1 0x40005203u\r
+#define CYDEV_PRTDSI_PRT0_DBL_SYNC_IN 0x40005204u\r
+#define CYDEV_PRTDSI_PRT0_SYNC_OUT 0x40005205u\r
+#define CYDEV_PRTDSI_PRT0_CAPS_SEL 0x40005206u\r
+#define CYDEV_PRTDSI_PRT1_BASE 0x40005208u\r
+#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007u\r
+#define CYDEV_PRTDSI_PRT1_OUT_SEL0 0x40005208u\r
+#define CYDEV_PRTDSI_PRT1_OUT_SEL1 0x40005209u\r
+#define CYDEV_PRTDSI_PRT1_OE_SEL0 0x4000520au\r
+#define CYDEV_PRTDSI_PRT1_OE_SEL1 0x4000520bu\r
+#define CYDEV_PRTDSI_PRT1_DBL_SYNC_IN 0x4000520cu\r
+#define CYDEV_PRTDSI_PRT1_SYNC_OUT 0x4000520du\r
+#define CYDEV_PRTDSI_PRT1_CAPS_SEL 0x4000520eu\r
+#define CYDEV_PRTDSI_PRT2_BASE 0x40005210u\r
+#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007u\r
+#define CYDEV_PRTDSI_PRT2_OUT_SEL0 0x40005210u\r
+#define CYDEV_PRTDSI_PRT2_OUT_SEL1 0x40005211u\r
+#define CYDEV_PRTDSI_PRT2_OE_SEL0 0x40005212u\r
+#define CYDEV_PRTDSI_PRT2_OE_SEL1 0x40005213u\r
+#define CYDEV_PRTDSI_PRT2_DBL_SYNC_IN 0x40005214u\r
+#define CYDEV_PRTDSI_PRT2_SYNC_OUT 0x40005215u\r
+#define CYDEV_PRTDSI_PRT2_CAPS_SEL 0x40005216u\r
+#define CYDEV_PRTDSI_PRT3_BASE 0x40005218u\r
+#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007u\r
+#define CYDEV_PRTDSI_PRT3_OUT_SEL0 0x40005218u\r
+#define CYDEV_PRTDSI_PRT3_OUT_SEL1 0x40005219u\r
+#define CYDEV_PRTDSI_PRT3_OE_SEL0 0x4000521au\r
+#define CYDEV_PRTDSI_PRT3_OE_SEL1 0x4000521bu\r
+#define CYDEV_PRTDSI_PRT3_DBL_SYNC_IN 0x4000521cu\r
+#define CYDEV_PRTDSI_PRT3_SYNC_OUT 0x4000521du\r
+#define CYDEV_PRTDSI_PRT3_CAPS_SEL 0x4000521eu\r
+#define CYDEV_PRTDSI_PRT4_BASE 0x40005220u\r
+#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007u\r
+#define CYDEV_PRTDSI_PRT4_OUT_SEL0 0x40005220u\r
+#define CYDEV_PRTDSI_PRT4_OUT_SEL1 0x40005221u\r
+#define CYDEV_PRTDSI_PRT4_OE_SEL0 0x40005222u\r
+#define CYDEV_PRTDSI_PRT4_OE_SEL1 0x40005223u\r
+#define CYDEV_PRTDSI_PRT4_DBL_SYNC_IN 0x40005224u\r
+#define CYDEV_PRTDSI_PRT4_SYNC_OUT 0x40005225u\r
+#define CYDEV_PRTDSI_PRT4_CAPS_SEL 0x40005226u\r
+#define CYDEV_PRTDSI_PRT5_BASE 0x40005228u\r
+#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007u\r
+#define CYDEV_PRTDSI_PRT5_OUT_SEL0 0x40005228u\r
+#define CYDEV_PRTDSI_PRT5_OUT_SEL1 0x40005229u\r
+#define CYDEV_PRTDSI_PRT5_OE_SEL0 0x4000522au\r
+#define CYDEV_PRTDSI_PRT5_OE_SEL1 0x4000522bu\r
+#define CYDEV_PRTDSI_PRT5_DBL_SYNC_IN 0x4000522cu\r
+#define CYDEV_PRTDSI_PRT5_SYNC_OUT 0x4000522du\r
+#define CYDEV_PRTDSI_PRT5_CAPS_SEL 0x4000522eu\r
+#define CYDEV_PRTDSI_PRT6_BASE 0x40005230u\r
+#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007u\r
+#define CYDEV_PRTDSI_PRT6_OUT_SEL0 0x40005230u\r
+#define CYDEV_PRTDSI_PRT6_OUT_SEL1 0x40005231u\r
+#define CYDEV_PRTDSI_PRT6_OE_SEL0 0x40005232u\r
+#define CYDEV_PRTDSI_PRT6_OE_SEL1 0x40005233u\r
+#define CYDEV_PRTDSI_PRT6_DBL_SYNC_IN 0x40005234u\r
+#define CYDEV_PRTDSI_PRT6_SYNC_OUT 0x40005235u\r
+#define CYDEV_PRTDSI_PRT6_CAPS_SEL 0x40005236u\r
+#define CYDEV_PRTDSI_PRT12_BASE 0x40005260u\r
+#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006u\r
+#define CYDEV_PRTDSI_PRT12_OUT_SEL0 0x40005260u\r
+#define CYDEV_PRTDSI_PRT12_OUT_SEL1 0x40005261u\r
+#define CYDEV_PRTDSI_PRT12_OE_SEL0 0x40005262u\r
+#define CYDEV_PRTDSI_PRT12_OE_SEL1 0x40005263u\r
+#define CYDEV_PRTDSI_PRT12_DBL_SYNC_IN 0x40005264u\r
+#define CYDEV_PRTDSI_PRT12_SYNC_OUT 0x40005265u\r
+#define CYDEV_PRTDSI_PRT15_BASE 0x40005278u\r
+#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007u\r
+#define CYDEV_PRTDSI_PRT15_OUT_SEL0 0x40005278u\r
+#define CYDEV_PRTDSI_PRT15_OUT_SEL1 0x40005279u\r
+#define CYDEV_PRTDSI_PRT15_OE_SEL0 0x4000527au\r
+#define CYDEV_PRTDSI_PRT15_OE_SEL1 0x4000527bu\r
+#define CYDEV_PRTDSI_PRT15_DBL_SYNC_IN 0x4000527cu\r
+#define CYDEV_PRTDSI_PRT15_SYNC_OUT 0x4000527du\r
+#define CYDEV_PRTDSI_PRT15_CAPS_SEL 0x4000527eu\r
+#define CYDEV_EMIF_BASE 0x40005400u\r
+#define CYDEV_EMIF_SIZE 0x00000007u\r
+#define CYDEV_EMIF_NO_UDB 0x40005400u\r
+#define CYDEV_EMIF_RP_WAIT_STATES 0x40005401u\r
+#define CYDEV_EMIF_MEM_DWN 0x40005402u\r
+#define CYDEV_EMIF_MEMCLK_DIV 0x40005403u\r
+#define CYDEV_EMIF_CLOCK_EN 0x40005404u\r
+#define CYDEV_EMIF_EM_TYPE 0x40005405u\r
+#define CYDEV_EMIF_WP_WAIT_STATES 0x40005406u\r
+#define CYDEV_ANAIF_BASE 0x40005800u\r
+#define CYDEV_ANAIF_SIZE 0x000003a9u\r
+#define CYDEV_ANAIF_CFG_BASE 0x40005800u\r
+#define CYDEV_ANAIF_CFG_SIZE 0x0000010fu\r
+#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800u\r
+#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003u\r
+#define CYDEV_ANAIF_CFG_SC0_CR0 0x40005800u\r
+#define CYDEV_ANAIF_CFG_SC0_CR1 0x40005801u\r
+#define CYDEV_ANAIF_CFG_SC0_CR2 0x40005802u\r
+#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804u\r
+#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003u\r
+#define CYDEV_ANAIF_CFG_SC1_CR0 0x40005804u\r
+#define CYDEV_ANAIF_CFG_SC1_CR1 0x40005805u\r
+#define CYDEV_ANAIF_CFG_SC1_CR2 0x40005806u\r
+#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808u\r
+#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003u\r
+#define CYDEV_ANAIF_CFG_SC2_CR0 0x40005808u\r
+#define CYDEV_ANAIF_CFG_SC2_CR1 0x40005809u\r
+#define CYDEV_ANAIF_CFG_SC2_CR2 0x4000580au\r
+#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580cu\r
+#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003u\r
+#define CYDEV_ANAIF_CFG_SC3_CR0 0x4000580cu\r
+#define CYDEV_ANAIF_CFG_SC3_CR1 0x4000580du\r
+#define CYDEV_ANAIF_CFG_SC3_CR2 0x4000580eu\r
+#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820u\r
+#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003u\r
+#define CYDEV_ANAIF_CFG_DAC0_CR0 0x40005820u\r
+#define CYDEV_ANAIF_CFG_DAC0_CR1 0x40005821u\r
+#define CYDEV_ANAIF_CFG_DAC0_TST 0x40005822u\r
+#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824u\r
+#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003u\r
+#define CYDEV_ANAIF_CFG_DAC1_CR0 0x40005824u\r
+#define CYDEV_ANAIF_CFG_DAC1_CR1 0x40005825u\r
+#define CYDEV_ANAIF_CFG_DAC1_TST 0x40005826u\r
+#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828u\r
+#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003u\r
+#define CYDEV_ANAIF_CFG_DAC2_CR0 0x40005828u\r
+#define CYDEV_ANAIF_CFG_DAC2_CR1 0x40005829u\r
+#define CYDEV_ANAIF_CFG_DAC2_TST 0x4000582au\r
+#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582cu\r
+#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003u\r
+#define CYDEV_ANAIF_CFG_DAC3_CR0 0x4000582cu\r
+#define CYDEV_ANAIF_CFG_DAC3_CR1 0x4000582du\r
+#define CYDEV_ANAIF_CFG_DAC3_TST 0x4000582eu\r
+#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840u\r
+#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001u\r
+#define CYDEV_ANAIF_CFG_CMP0_CR 0x40005840u\r
+#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841u\r
+#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001u\r
+#define CYDEV_ANAIF_CFG_CMP1_CR 0x40005841u\r
+#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842u\r
+#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001u\r
+#define CYDEV_ANAIF_CFG_CMP2_CR 0x40005842u\r
+#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843u\r
+#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001u\r
+#define CYDEV_ANAIF_CFG_CMP3_CR 0x40005843u\r
+#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848u\r
+#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_CFG_LUT0_CR 0x40005848u\r
+#define CYDEV_ANAIF_CFG_LUT0_MX 0x40005849u\r
+#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584au\r
+#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_CFG_LUT1_CR 0x4000584au\r
+#define CYDEV_ANAIF_CFG_LUT1_MX 0x4000584bu\r
+#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584cu\r
+#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_CFG_LUT2_CR 0x4000584cu\r
+#define CYDEV_ANAIF_CFG_LUT2_MX 0x4000584du\r
+#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584eu\r
+#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_CFG_LUT3_CR 0x4000584eu\r
+#define CYDEV_ANAIF_CFG_LUT3_MX 0x4000584fu\r
+#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858u\r
+#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_CFG_OPAMP0_CR 0x40005858u\r
+#define CYDEV_ANAIF_CFG_OPAMP0_RSVD 0x40005859u\r
+#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585au\r
+#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_CFG_OPAMP1_CR 0x4000585au\r
+#define CYDEV_ANAIF_CFG_OPAMP1_RSVD 0x4000585bu\r
+#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585cu\r
+#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_CFG_OPAMP2_CR 0x4000585cu\r
+#define CYDEV_ANAIF_CFG_OPAMP2_RSVD 0x4000585du\r
+#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585eu\r
+#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_CFG_OPAMP3_CR 0x4000585eu\r
+#define CYDEV_ANAIF_CFG_OPAMP3_RSVD 0x4000585fu\r
+#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868u\r
+#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_CFG_LCDDAC_CR0 0x40005868u\r
+#define CYDEV_ANAIF_CFG_LCDDAC_CR1 0x40005869u\r
+#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586au\r
+#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001u\r
+#define CYDEV_ANAIF_CFG_LCDDRV_CR 0x4000586au\r
+#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586bu\r
+#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001u\r
+#define CYDEV_ANAIF_CFG_LCDTMR_CFG 0x4000586bu\r
+#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586cu\r
+#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004u\r
+#define CYDEV_ANAIF_CFG_BG_CR0 0x4000586cu\r
+#define CYDEV_ANAIF_CFG_BG_RSVD 0x4000586du\r
+#define CYDEV_ANAIF_CFG_BG_DFT0 0x4000586eu\r
+#define CYDEV_ANAIF_CFG_BG_DFT1 0x4000586fu\r
+#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870u\r
+#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_CFG_CAPSL_CFG0 0x40005870u\r
+#define CYDEV_ANAIF_CFG_CAPSL_CFG1 0x40005871u\r
+#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872u\r
+#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_CFG_CAPSR_CFG0 0x40005872u\r
+#define CYDEV_ANAIF_CFG_CAPSR_CFG1 0x40005873u\r
+#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876u\r
+#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_CFG_PUMP_CR0 0x40005876u\r
+#define CYDEV_ANAIF_CFG_PUMP_CR1 0x40005877u\r
+#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878u\r
+#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_CFG_LPF0_CR0 0x40005878u\r
+#define CYDEV_ANAIF_CFG_LPF0_RSVD 0x40005879u\r
+#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587au\r
+#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_CFG_LPF1_CR0 0x4000587au\r
+#define CYDEV_ANAIF_CFG_LPF1_RSVD 0x4000587bu\r
+#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587cu\r
+#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001u\r
+#define CYDEV_ANAIF_CFG_MISC_CR0 0x4000587cu\r
+#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880u\r
+#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020u\r
+#define CYDEV_ANAIF_CFG_DSM0_CR0 0x40005880u\r
+#define CYDEV_ANAIF_CFG_DSM0_CR1 0x40005881u\r
+#define CYDEV_ANAIF_CFG_DSM0_CR2 0x40005882u\r
+#define CYDEV_ANAIF_CFG_DSM0_CR3 0x40005883u\r
+#define CYDEV_ANAIF_CFG_DSM0_CR4 0x40005884u\r
+#define CYDEV_ANAIF_CFG_DSM0_CR5 0x40005885u\r
+#define CYDEV_ANAIF_CFG_DSM0_CR6 0x40005886u\r
+#define CYDEV_ANAIF_CFG_DSM0_CR7 0x40005887u\r
+#define CYDEV_ANAIF_CFG_DSM0_CR8 0x40005888u\r
+#define CYDEV_ANAIF_CFG_DSM0_CR9 0x40005889u\r
+#define CYDEV_ANAIF_CFG_DSM0_CR10 0x4000588au\r
+#define CYDEV_ANAIF_CFG_DSM0_CR11 0x4000588bu\r
+#define CYDEV_ANAIF_CFG_DSM0_CR12 0x4000588cu\r
+#define CYDEV_ANAIF_CFG_DSM0_CR13 0x4000588du\r
+#define CYDEV_ANAIF_CFG_DSM0_CR14 0x4000588eu\r
+#define CYDEV_ANAIF_CFG_DSM0_CR15 0x4000588fu\r
+#define CYDEV_ANAIF_CFG_DSM0_CR16 0x40005890u\r
+#define CYDEV_ANAIF_CFG_DSM0_CR17 0x40005891u\r
+#define CYDEV_ANAIF_CFG_DSM0_REF0 0x40005892u\r
+#define CYDEV_ANAIF_CFG_DSM0_REF1 0x40005893u\r
+#define CYDEV_ANAIF_CFG_DSM0_REF2 0x40005894u\r
+#define CYDEV_ANAIF_CFG_DSM0_REF3 0x40005895u\r
+#define CYDEV_ANAIF_CFG_DSM0_DEM0 0x40005896u\r
+#define CYDEV_ANAIF_CFG_DSM0_DEM1 0x40005897u\r
+#define CYDEV_ANAIF_CFG_DSM0_TST0 0x40005898u\r
+#define CYDEV_ANAIF_CFG_DSM0_TST1 0x40005899u\r
+#define CYDEV_ANAIF_CFG_DSM0_BUF0 0x4000589au\r
+#define CYDEV_ANAIF_CFG_DSM0_BUF1 0x4000589bu\r
+#define CYDEV_ANAIF_CFG_DSM0_BUF2 0x4000589cu\r
+#define CYDEV_ANAIF_CFG_DSM0_BUF3 0x4000589du\r
+#define CYDEV_ANAIF_CFG_DSM0_MISC 0x4000589eu\r
+#define CYDEV_ANAIF_CFG_DSM0_RSVD1 0x4000589fu\r
+#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900u\r
+#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007u\r
+#define CYDEV_ANAIF_CFG_SAR0_CSR0 0x40005900u\r
+#define CYDEV_ANAIF_CFG_SAR0_CSR1 0x40005901u\r
+#define CYDEV_ANAIF_CFG_SAR0_CSR2 0x40005902u\r
+#define CYDEV_ANAIF_CFG_SAR0_CSR3 0x40005903u\r
+#define CYDEV_ANAIF_CFG_SAR0_CSR4 0x40005904u\r
+#define CYDEV_ANAIF_CFG_SAR0_CSR5 0x40005905u\r
+#define CYDEV_ANAIF_CFG_SAR0_CSR6 0x40005906u\r
+#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908u\r
+#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007u\r
+#define CYDEV_ANAIF_CFG_SAR1_CSR0 0x40005908u\r
+#define CYDEV_ANAIF_CFG_SAR1_CSR1 0x40005909u\r
+#define CYDEV_ANAIF_CFG_SAR1_CSR2 0x4000590au\r
+#define CYDEV_ANAIF_CFG_SAR1_CSR3 0x4000590bu\r
+#define CYDEV_ANAIF_CFG_SAR1_CSR4 0x4000590cu\r
+#define CYDEV_ANAIF_CFG_SAR1_CSR5 0x4000590du\r
+#define CYDEV_ANAIF_CFG_SAR1_CSR6 0x4000590eu\r
+#define CYDEV_ANAIF_RT_BASE 0x40005a00u\r
+#define CYDEV_ANAIF_RT_SIZE 0x00000162u\r
+#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00u\r
+#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000du\r
+#define CYDEV_ANAIF_RT_SC0_SW0 0x40005a00u\r
+#define CYDEV_ANAIF_RT_SC0_SW2 0x40005a02u\r
+#define CYDEV_ANAIF_RT_SC0_SW3 0x40005a03u\r
+#define CYDEV_ANAIF_RT_SC0_SW4 0x40005a04u\r
+#define CYDEV_ANAIF_RT_SC0_SW6 0x40005a06u\r
+#define CYDEV_ANAIF_RT_SC0_SW7 0x40005a07u\r
+#define CYDEV_ANAIF_RT_SC0_SW8 0x40005a08u\r
+#define CYDEV_ANAIF_RT_SC0_SW10 0x40005a0au\r
+#define CYDEV_ANAIF_RT_SC0_CLK 0x40005a0bu\r
+#define CYDEV_ANAIF_RT_SC0_BST 0x40005a0cu\r
+#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10u\r
+#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000du\r
+#define CYDEV_ANAIF_RT_SC1_SW0 0x40005a10u\r
+#define CYDEV_ANAIF_RT_SC1_SW2 0x40005a12u\r
+#define CYDEV_ANAIF_RT_SC1_SW3 0x40005a13u\r
+#define CYDEV_ANAIF_RT_SC1_SW4 0x40005a14u\r
+#define CYDEV_ANAIF_RT_SC1_SW6 0x40005a16u\r
+#define CYDEV_ANAIF_RT_SC1_SW7 0x40005a17u\r
+#define CYDEV_ANAIF_RT_SC1_SW8 0x40005a18u\r
+#define CYDEV_ANAIF_RT_SC1_SW10 0x40005a1au\r
+#define CYDEV_ANAIF_RT_SC1_CLK 0x40005a1bu\r
+#define CYDEV_ANAIF_RT_SC1_BST 0x40005a1cu\r
+#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20u\r
+#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000du\r
+#define CYDEV_ANAIF_RT_SC2_SW0 0x40005a20u\r
+#define CYDEV_ANAIF_RT_SC2_SW2 0x40005a22u\r
+#define CYDEV_ANAIF_RT_SC2_SW3 0x40005a23u\r
+#define CYDEV_ANAIF_RT_SC2_SW4 0x40005a24u\r
+#define CYDEV_ANAIF_RT_SC2_SW6 0x40005a26u\r
+#define CYDEV_ANAIF_RT_SC2_SW7 0x40005a27u\r
+#define CYDEV_ANAIF_RT_SC2_SW8 0x40005a28u\r
+#define CYDEV_ANAIF_RT_SC2_SW10 0x40005a2au\r
+#define CYDEV_ANAIF_RT_SC2_CLK 0x40005a2bu\r
+#define CYDEV_ANAIF_RT_SC2_BST 0x40005a2cu\r
+#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30u\r
+#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000du\r
+#define CYDEV_ANAIF_RT_SC3_SW0 0x40005a30u\r
+#define CYDEV_ANAIF_RT_SC3_SW2 0x40005a32u\r
+#define CYDEV_ANAIF_RT_SC3_SW3 0x40005a33u\r
+#define CYDEV_ANAIF_RT_SC3_SW4 0x40005a34u\r
+#define CYDEV_ANAIF_RT_SC3_SW6 0x40005a36u\r
+#define CYDEV_ANAIF_RT_SC3_SW7 0x40005a37u\r
+#define CYDEV_ANAIF_RT_SC3_SW8 0x40005a38u\r
+#define CYDEV_ANAIF_RT_SC3_SW10 0x40005a3au\r
+#define CYDEV_ANAIF_RT_SC3_CLK 0x40005a3bu\r
+#define CYDEV_ANAIF_RT_SC3_BST 0x40005a3cu\r
+#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80u\r
+#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008u\r
+#define CYDEV_ANAIF_RT_DAC0_SW0 0x40005a80u\r
+#define CYDEV_ANAIF_RT_DAC0_SW2 0x40005a82u\r
+#define CYDEV_ANAIF_RT_DAC0_SW3 0x40005a83u\r
+#define CYDEV_ANAIF_RT_DAC0_SW4 0x40005a84u\r
+#define CYDEV_ANAIF_RT_DAC0_STROBE 0x40005a87u\r
+#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88u\r
+#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008u\r
+#define CYDEV_ANAIF_RT_DAC1_SW0 0x40005a88u\r
+#define CYDEV_ANAIF_RT_DAC1_SW2 0x40005a8au\r
+#define CYDEV_ANAIF_RT_DAC1_SW3 0x40005a8bu\r
+#define CYDEV_ANAIF_RT_DAC1_SW4 0x40005a8cu\r
+#define CYDEV_ANAIF_RT_DAC1_STROBE 0x40005a8fu\r
+#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90u\r
+#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008u\r
+#define CYDEV_ANAIF_RT_DAC2_SW0 0x40005a90u\r
+#define CYDEV_ANAIF_RT_DAC2_SW2 0x40005a92u\r
+#define CYDEV_ANAIF_RT_DAC2_SW3 0x40005a93u\r
+#define CYDEV_ANAIF_RT_DAC2_SW4 0x40005a94u\r
+#define CYDEV_ANAIF_RT_DAC2_STROBE 0x40005a97u\r
+#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98u\r
+#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008u\r
+#define CYDEV_ANAIF_RT_DAC3_SW0 0x40005a98u\r
+#define CYDEV_ANAIF_RT_DAC3_SW2 0x40005a9au\r
+#define CYDEV_ANAIF_RT_DAC3_SW3 0x40005a9bu\r
+#define CYDEV_ANAIF_RT_DAC3_SW4 0x40005a9cu\r
+#define CYDEV_ANAIF_RT_DAC3_STROBE 0x40005a9fu\r
+#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0u\r
+#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008u\r
+#define CYDEV_ANAIF_RT_CMP0_SW0 0x40005ac0u\r
+#define CYDEV_ANAIF_RT_CMP0_SW2 0x40005ac2u\r
+#define CYDEV_ANAIF_RT_CMP0_SW3 0x40005ac3u\r
+#define CYDEV_ANAIF_RT_CMP0_SW4 0x40005ac4u\r
+#define CYDEV_ANAIF_RT_CMP0_SW6 0x40005ac6u\r
+#define CYDEV_ANAIF_RT_CMP0_CLK 0x40005ac7u\r
+#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8u\r
+#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008u\r
+#define CYDEV_ANAIF_RT_CMP1_SW0 0x40005ac8u\r
+#define CYDEV_ANAIF_RT_CMP1_SW2 0x40005acau\r
+#define CYDEV_ANAIF_RT_CMP1_SW3 0x40005acbu\r
+#define CYDEV_ANAIF_RT_CMP1_SW4 0x40005accu\r
+#define CYDEV_ANAIF_RT_CMP1_SW6 0x40005aceu\r
+#define CYDEV_ANAIF_RT_CMP1_CLK 0x40005acfu\r
+#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0u\r
+#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008u\r
+#define CYDEV_ANAIF_RT_CMP2_SW0 0x40005ad0u\r
+#define CYDEV_ANAIF_RT_CMP2_SW2 0x40005ad2u\r
+#define CYDEV_ANAIF_RT_CMP2_SW3 0x40005ad3u\r
+#define CYDEV_ANAIF_RT_CMP2_SW4 0x40005ad4u\r
+#define CYDEV_ANAIF_RT_CMP2_SW6 0x40005ad6u\r
+#define CYDEV_ANAIF_RT_CMP2_CLK 0x40005ad7u\r
+#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8u\r
+#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008u\r
+#define CYDEV_ANAIF_RT_CMP3_SW0 0x40005ad8u\r
+#define CYDEV_ANAIF_RT_CMP3_SW2 0x40005adau\r
+#define CYDEV_ANAIF_RT_CMP3_SW3 0x40005adbu\r
+#define CYDEV_ANAIF_RT_CMP3_SW4 0x40005adcu\r
+#define CYDEV_ANAIF_RT_CMP3_SW6 0x40005adeu\r
+#define CYDEV_ANAIF_RT_CMP3_CLK 0x40005adfu\r
+#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00u\r
+#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008u\r
+#define CYDEV_ANAIF_RT_DSM0_SW0 0x40005b00u\r
+#define CYDEV_ANAIF_RT_DSM0_SW2 0x40005b02u\r
+#define CYDEV_ANAIF_RT_DSM0_SW3 0x40005b03u\r
+#define CYDEV_ANAIF_RT_DSM0_SW4 0x40005b04u\r
+#define CYDEV_ANAIF_RT_DSM0_SW6 0x40005b06u\r
+#define CYDEV_ANAIF_RT_DSM0_CLK 0x40005b07u\r
+#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20u\r
+#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008u\r
+#define CYDEV_ANAIF_RT_SAR0_SW0 0x40005b20u\r
+#define CYDEV_ANAIF_RT_SAR0_SW2 0x40005b22u\r
+#define CYDEV_ANAIF_RT_SAR0_SW3 0x40005b23u\r
+#define CYDEV_ANAIF_RT_SAR0_SW4 0x40005b24u\r
+#define CYDEV_ANAIF_RT_SAR0_SW6 0x40005b26u\r
+#define CYDEV_ANAIF_RT_SAR0_CLK 0x40005b27u\r
+#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28u\r
+#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008u\r
+#define CYDEV_ANAIF_RT_SAR1_SW0 0x40005b28u\r
+#define CYDEV_ANAIF_RT_SAR1_SW2 0x40005b2au\r
+#define CYDEV_ANAIF_RT_SAR1_SW3 0x40005b2bu\r
+#define CYDEV_ANAIF_RT_SAR1_SW4 0x40005b2cu\r
+#define CYDEV_ANAIF_RT_SAR1_SW6 0x40005b2eu\r
+#define CYDEV_ANAIF_RT_SAR1_CLK 0x40005b2fu\r
+#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40u\r
+#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_RT_OPAMP0_MX 0x40005b40u\r
+#define CYDEV_ANAIF_RT_OPAMP0_SW 0x40005b41u\r
+#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42u\r
+#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_RT_OPAMP1_MX 0x40005b42u\r
+#define CYDEV_ANAIF_RT_OPAMP1_SW 0x40005b43u\r
+#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44u\r
+#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_RT_OPAMP2_MX 0x40005b44u\r
+#define CYDEV_ANAIF_RT_OPAMP2_SW 0x40005b45u\r
+#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46u\r
+#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_RT_OPAMP3_MX 0x40005b46u\r
+#define CYDEV_ANAIF_RT_OPAMP3_SW 0x40005b47u\r
+#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50u\r
+#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005u\r
+#define CYDEV_ANAIF_RT_LCDDAC_SW0 0x40005b50u\r
+#define CYDEV_ANAIF_RT_LCDDAC_SW1 0x40005b51u\r
+#define CYDEV_ANAIF_RT_LCDDAC_SW2 0x40005b52u\r
+#define CYDEV_ANAIF_RT_LCDDAC_SW3 0x40005b53u\r
+#define CYDEV_ANAIF_RT_LCDDAC_SW4 0x40005b54u\r
+#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56u\r
+#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001u\r
+#define CYDEV_ANAIF_RT_SC_MISC 0x40005b56u\r
+#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58u\r
+#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004u\r
+#define CYDEV_ANAIF_RT_BUS_SW0 0x40005b58u\r
+#define CYDEV_ANAIF_RT_BUS_SW2 0x40005b5au\r
+#define CYDEV_ANAIF_RT_BUS_SW3 0x40005b5bu\r
+#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5cu\r
+#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006u\r
+#define CYDEV_ANAIF_RT_DFT_CR0 0x40005b5cu\r
+#define CYDEV_ANAIF_RT_DFT_CR1 0x40005b5du\r
+#define CYDEV_ANAIF_RT_DFT_CR2 0x40005b5eu\r
+#define CYDEV_ANAIF_RT_DFT_CR3 0x40005b5fu\r
+#define CYDEV_ANAIF_RT_DFT_CR4 0x40005b60u\r
+#define CYDEV_ANAIF_RT_DFT_CR5 0x40005b61u\r
+#define CYDEV_ANAIF_WRK_BASE 0x40005b80u\r
+#define CYDEV_ANAIF_WRK_SIZE 0x00000029u\r
+#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80u\r
+#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001u\r
+#define CYDEV_ANAIF_WRK_DAC0_D 0x40005b80u\r
+#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81u\r
+#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001u\r
+#define CYDEV_ANAIF_WRK_DAC1_D 0x40005b81u\r
+#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82u\r
+#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001u\r
+#define CYDEV_ANAIF_WRK_DAC2_D 0x40005b82u\r
+#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83u\r
+#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001u\r
+#define CYDEV_ANAIF_WRK_DAC3_D 0x40005b83u\r
+#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88u\r
+#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_WRK_DSM0_OUT0 0x40005b88u\r
+#define CYDEV_ANAIF_WRK_DSM0_OUT1 0x40005b89u\r
+#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90u\r
+#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005u\r
+#define CYDEV_ANAIF_WRK_LUT_SR 0x40005b90u\r
+#define CYDEV_ANAIF_WRK_LUT_WRK1 0x40005b91u\r
+#define CYDEV_ANAIF_WRK_LUT_MSK 0x40005b92u\r
+#define CYDEV_ANAIF_WRK_LUT_CLK 0x40005b93u\r
+#define CYDEV_ANAIF_WRK_LUT_CPTR 0x40005b94u\r
+#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96u\r
+#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_WRK_CMP_WRK 0x40005b96u\r
+#define CYDEV_ANAIF_WRK_CMP_TST 0x40005b97u\r
+#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98u\r
+#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005u\r
+#define CYDEV_ANAIF_WRK_SC_SR 0x40005b98u\r
+#define CYDEV_ANAIF_WRK_SC_WRK1 0x40005b99u\r
+#define CYDEV_ANAIF_WRK_SC_MSK 0x40005b9au\r
+#define CYDEV_ANAIF_WRK_SC_CMPINV 0x40005b9bu\r
+#define CYDEV_ANAIF_WRK_SC_CPTR 0x40005b9cu\r
+#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0u\r
+#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_WRK_SAR0_WRK0 0x40005ba0u\r
+#define CYDEV_ANAIF_WRK_SAR0_WRK1 0x40005ba1u\r
+#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2u\r
+#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002u\r
+#define CYDEV_ANAIF_WRK_SAR1_WRK0 0x40005ba2u\r
+#define CYDEV_ANAIF_WRK_SAR1_WRK1 0x40005ba3u\r
+#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8u\r
+#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001u\r
+#define CYDEV_ANAIF_WRK_SARS_SOF 0x40005ba8u\r
+#define CYDEV_USB_BASE 0x40006000u\r
+#define CYDEV_USB_SIZE 0x00000300u\r
+#define CYDEV_USB_EP0_DR0 0x40006000u\r
+#define CYDEV_USB_EP0_DR1 0x40006001u\r
+#define CYDEV_USB_EP0_DR2 0x40006002u\r
+#define CYDEV_USB_EP0_DR3 0x40006003u\r
+#define CYDEV_USB_EP0_DR4 0x40006004u\r
+#define CYDEV_USB_EP0_DR5 0x40006005u\r
+#define CYDEV_USB_EP0_DR6 0x40006006u\r
+#define CYDEV_USB_EP0_DR7 0x40006007u\r
+#define CYDEV_USB_CR0 0x40006008u\r
+#define CYDEV_USB_CR1 0x40006009u\r
+#define CYDEV_USB_SIE_EP_INT_EN 0x4000600au\r
+#define CYDEV_USB_SIE_EP_INT_SR 0x4000600bu\r
+#define CYDEV_USB_SIE_EP1_BASE 0x4000600cu\r
+#define CYDEV_USB_SIE_EP1_SIZE 0x00000003u\r
+#define CYDEV_USB_SIE_EP1_CNT0 0x4000600cu\r
+#define CYDEV_USB_SIE_EP1_CNT1 0x4000600du\r
+#define CYDEV_USB_SIE_EP1_CR0 0x4000600eu\r
+#define CYDEV_USB_USBIO_CR0 0x40006010u\r
+#define CYDEV_USB_USBIO_CR1 0x40006012u\r
+#define CYDEV_USB_DYN_RECONFIG 0x40006014u\r
+#define CYDEV_USB_SOF0 0x40006018u\r
+#define CYDEV_USB_SOF1 0x40006019u\r
+#define CYDEV_USB_SIE_EP2_BASE 0x4000601cu\r
+#define CYDEV_USB_SIE_EP2_SIZE 0x00000003u\r
+#define CYDEV_USB_SIE_EP2_CNT0 0x4000601cu\r
+#define CYDEV_USB_SIE_EP2_CNT1 0x4000601du\r
+#define CYDEV_USB_SIE_EP2_CR0 0x4000601eu\r
+#define CYDEV_USB_EP0_CR 0x40006028u\r
+#define CYDEV_USB_EP0_CNT 0x40006029u\r
+#define CYDEV_USB_SIE_EP3_BASE 0x4000602cu\r
+#define CYDEV_USB_SIE_EP3_SIZE 0x00000003u\r
+#define CYDEV_USB_SIE_EP3_CNT0 0x4000602cu\r
+#define CYDEV_USB_SIE_EP3_CNT1 0x4000602du\r
+#define CYDEV_USB_SIE_EP3_CR0 0x4000602eu\r
+#define CYDEV_USB_SIE_EP4_BASE 0x4000603cu\r
+#define CYDEV_USB_SIE_EP4_SIZE 0x00000003u\r
+#define CYDEV_USB_SIE_EP4_CNT0 0x4000603cu\r
+#define CYDEV_USB_SIE_EP4_CNT1 0x4000603du\r
+#define CYDEV_USB_SIE_EP4_CR0 0x4000603eu\r
+#define CYDEV_USB_SIE_EP5_BASE 0x4000604cu\r
+#define CYDEV_USB_SIE_EP5_SIZE 0x00000003u\r
+#define CYDEV_USB_SIE_EP5_CNT0 0x4000604cu\r
+#define CYDEV_USB_SIE_EP5_CNT1 0x4000604du\r
+#define CYDEV_USB_SIE_EP5_CR0 0x4000604eu\r
+#define CYDEV_USB_SIE_EP6_BASE 0x4000605cu\r
+#define CYDEV_USB_SIE_EP6_SIZE 0x00000003u\r
+#define CYDEV_USB_SIE_EP6_CNT0 0x4000605cu\r
+#define CYDEV_USB_SIE_EP6_CNT1 0x4000605du\r
+#define CYDEV_USB_SIE_EP6_CR0 0x4000605eu\r
+#define CYDEV_USB_SIE_EP7_BASE 0x4000606cu\r
+#define CYDEV_USB_SIE_EP7_SIZE 0x00000003u\r
+#define CYDEV_USB_SIE_EP7_CNT0 0x4000606cu\r
+#define CYDEV_USB_SIE_EP7_CNT1 0x4000606du\r
+#define CYDEV_USB_SIE_EP7_CR0 0x4000606eu\r
+#define CYDEV_USB_SIE_EP8_BASE 0x4000607cu\r
+#define CYDEV_USB_SIE_EP8_SIZE 0x00000003u\r
+#define CYDEV_USB_SIE_EP8_CNT0 0x4000607cu\r
+#define CYDEV_USB_SIE_EP8_CNT1 0x4000607du\r
+#define CYDEV_USB_SIE_EP8_CR0 0x4000607eu\r
+#define CYDEV_USB_ARB_EP1_BASE 0x40006080u\r
+#define CYDEV_USB_ARB_EP1_SIZE 0x00000003u\r
+#define CYDEV_USB_ARB_EP1_CFG 0x40006080u\r
+#define CYDEV_USB_ARB_EP1_INT_EN 0x40006081u\r
+#define CYDEV_USB_ARB_EP1_SR 0x40006082u\r
+#define CYDEV_USB_ARB_RW1_BASE 0x40006084u\r
+#define CYDEV_USB_ARB_RW1_SIZE 0x00000005u\r
+#define CYDEV_USB_ARB_RW1_WA 0x40006084u\r
+#define CYDEV_USB_ARB_RW1_WA_MSB 0x40006085u\r
+#define CYDEV_USB_ARB_RW1_RA 0x40006086u\r
+#define CYDEV_USB_ARB_RW1_RA_MSB 0x40006087u\r
+#define CYDEV_USB_ARB_RW1_DR 0x40006088u\r
+#define CYDEV_USB_BUF_SIZE 0x4000608cu\r
+#define CYDEV_USB_EP_ACTIVE 0x4000608eu\r
+#define CYDEV_USB_EP_TYPE 0x4000608fu\r
+#define CYDEV_USB_ARB_EP2_BASE 0x40006090u\r
+#define CYDEV_USB_ARB_EP2_SIZE 0x00000003u\r
+#define CYDEV_USB_ARB_EP2_CFG 0x40006090u\r
+#define CYDEV_USB_ARB_EP2_INT_EN 0x40006091u\r
+#define CYDEV_USB_ARB_EP2_SR 0x40006092u\r
+#define CYDEV_USB_ARB_RW2_BASE 0x40006094u\r
+#define CYDEV_USB_ARB_RW2_SIZE 0x00000005u\r
+#define CYDEV_USB_ARB_RW2_WA 0x40006094u\r
+#define CYDEV_USB_ARB_RW2_WA_MSB 0x40006095u\r
+#define CYDEV_USB_ARB_RW2_RA 0x40006096u\r
+#define CYDEV_USB_ARB_RW2_RA_MSB 0x40006097u\r
+#define CYDEV_USB_ARB_RW2_DR 0x40006098u\r
+#define CYDEV_USB_ARB_CFG 0x4000609cu\r
+#define CYDEV_USB_USB_CLK_EN 0x4000609du\r
+#define CYDEV_USB_ARB_INT_EN 0x4000609eu\r
+#define CYDEV_USB_ARB_INT_SR 0x4000609fu\r
+#define CYDEV_USB_ARB_EP3_BASE 0x400060a0u\r
+#define CYDEV_USB_ARB_EP3_SIZE 0x00000003u\r
+#define CYDEV_USB_ARB_EP3_CFG 0x400060a0u\r
+#define CYDEV_USB_ARB_EP3_INT_EN 0x400060a1u\r
+#define CYDEV_USB_ARB_EP3_SR 0x400060a2u\r
+#define CYDEV_USB_ARB_RW3_BASE 0x400060a4u\r
+#define CYDEV_USB_ARB_RW3_SIZE 0x00000005u\r
+#define CYDEV_USB_ARB_RW3_WA 0x400060a4u\r
+#define CYDEV_USB_ARB_RW3_WA_MSB 0x400060a5u\r
+#define CYDEV_USB_ARB_RW3_RA 0x400060a6u\r
+#define CYDEV_USB_ARB_RW3_RA_MSB 0x400060a7u\r
+#define CYDEV_USB_ARB_RW3_DR 0x400060a8u\r
+#define CYDEV_USB_CWA 0x400060acu\r
+#define CYDEV_USB_CWA_MSB 0x400060adu\r
+#define CYDEV_USB_ARB_EP4_BASE 0x400060b0u\r
+#define CYDEV_USB_ARB_EP4_SIZE 0x00000003u\r
+#define CYDEV_USB_ARB_EP4_CFG 0x400060b0u\r
+#define CYDEV_USB_ARB_EP4_INT_EN 0x400060b1u\r
+#define CYDEV_USB_ARB_EP4_SR 0x400060b2u\r
+#define CYDEV_USB_ARB_RW4_BASE 0x400060b4u\r
+#define CYDEV_USB_ARB_RW4_SIZE 0x00000005u\r
+#define CYDEV_USB_ARB_RW4_WA 0x400060b4u\r
+#define CYDEV_USB_ARB_RW4_WA_MSB 0x400060b5u\r
+#define CYDEV_USB_ARB_RW4_RA 0x400060b6u\r
+#define CYDEV_USB_ARB_RW4_RA_MSB 0x400060b7u\r
+#define CYDEV_USB_ARB_RW4_DR 0x400060b8u\r
+#define CYDEV_USB_DMA_THRES 0x400060bcu\r
+#define CYDEV_USB_DMA_THRES_MSB 0x400060bdu\r
+#define CYDEV_USB_ARB_EP5_BASE 0x400060c0u\r
+#define CYDEV_USB_ARB_EP5_SIZE 0x00000003u\r
+#define CYDEV_USB_ARB_EP5_CFG 0x400060c0u\r
+#define CYDEV_USB_ARB_EP5_INT_EN 0x400060c1u\r
+#define CYDEV_USB_ARB_EP5_SR 0x400060c2u\r
+#define CYDEV_USB_ARB_RW5_BASE 0x400060c4u\r
+#define CYDEV_USB_ARB_RW5_SIZE 0x00000005u\r
+#define CYDEV_USB_ARB_RW5_WA 0x400060c4u\r
+#define CYDEV_USB_ARB_RW5_WA_MSB 0x400060c5u\r
+#define CYDEV_USB_ARB_RW5_RA 0x400060c6u\r
+#define CYDEV_USB_ARB_RW5_RA_MSB 0x400060c7u\r
+#define CYDEV_USB_ARB_RW5_DR 0x400060c8u\r
+#define CYDEV_USB_BUS_RST_CNT 0x400060ccu\r
+#define CYDEV_USB_ARB_EP6_BASE 0x400060d0u\r
+#define CYDEV_USB_ARB_EP6_SIZE 0x00000003u\r
+#define CYDEV_USB_ARB_EP6_CFG 0x400060d0u\r
+#define CYDEV_USB_ARB_EP6_INT_EN 0x400060d1u\r
+#define CYDEV_USB_ARB_EP6_SR 0x400060d2u\r
+#define CYDEV_USB_ARB_RW6_BASE 0x400060d4u\r
+#define CYDEV_USB_ARB_RW6_SIZE 0x00000005u\r
+#define CYDEV_USB_ARB_RW6_WA 0x400060d4u\r
+#define CYDEV_USB_ARB_RW6_WA_MSB 0x400060d5u\r
+#define CYDEV_USB_ARB_RW6_RA 0x400060d6u\r
+#define CYDEV_USB_ARB_RW6_RA_MSB 0x400060d7u\r
+#define CYDEV_USB_ARB_RW6_DR 0x400060d8u\r
+#define CYDEV_USB_ARB_EP7_BASE 0x400060e0u\r
+#define CYDEV_USB_ARB_EP7_SIZE 0x00000003u\r
+#define CYDEV_USB_ARB_EP7_CFG 0x400060e0u\r
+#define CYDEV_USB_ARB_EP7_INT_EN 0x400060e1u\r
+#define CYDEV_USB_ARB_EP7_SR 0x400060e2u\r
+#define CYDEV_USB_ARB_RW7_BASE 0x400060e4u\r
+#define CYDEV_USB_ARB_RW7_SIZE 0x00000005u\r
+#define CYDEV_USB_ARB_RW7_WA 0x400060e4u\r
+#define CYDEV_USB_ARB_RW7_WA_MSB 0x400060e5u\r
+#define CYDEV_USB_ARB_RW7_RA 0x400060e6u\r
+#define CYDEV_USB_ARB_RW7_RA_MSB 0x400060e7u\r
+#define CYDEV_USB_ARB_RW7_DR 0x400060e8u\r
+#define CYDEV_USB_ARB_EP8_BASE 0x400060f0u\r
+#define CYDEV_USB_ARB_EP8_SIZE 0x00000003u\r
+#define CYDEV_USB_ARB_EP8_CFG 0x400060f0u\r
+#define CYDEV_USB_ARB_EP8_INT_EN 0x400060f1u\r
+#define CYDEV_USB_ARB_EP8_SR 0x400060f2u\r
+#define CYDEV_USB_ARB_RW8_BASE 0x400060f4u\r
+#define CYDEV_USB_ARB_RW8_SIZE 0x00000005u\r
+#define CYDEV_USB_ARB_RW8_WA 0x400060f4u\r
+#define CYDEV_USB_ARB_RW8_WA_MSB 0x400060f5u\r
+#define CYDEV_USB_ARB_RW8_RA 0x400060f6u\r
+#define CYDEV_USB_ARB_RW8_RA_MSB 0x400060f7u\r
+#define CYDEV_USB_ARB_RW8_DR 0x400060f8u\r
+#define CYDEV_USB_MEM_BASE 0x40006100u\r
+#define CYDEV_USB_MEM_SIZE 0x00000200u\r
+#define CYDEV_USB_MEM_DATA_MBASE 0x40006100u\r
+#define CYDEV_USB_MEM_DATA_MSIZE 0x00000200u\r
+#define CYDEV_UWRK_BASE 0x40006400u\r
+#define CYDEV_UWRK_SIZE 0x00000b60u\r
+#define CYDEV_UWRK_UWRK8_BASE 0x40006400u\r
+#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0u\r
+#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400u\r
+#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_A0 0x40006400u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_A0 0x40006401u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_A0 0x40006402u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_A0 0x40006403u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_A0 0x40006404u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_A0 0x40006405u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_A0 0x40006406u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_A0 0x40006407u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_A0 0x40006408u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_A0 0x40006409u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_A0 0x4000640au\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_A0 0x4000640bu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_A0 0x4000640cu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_A0 0x4000640du\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_A0 0x4000640eu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_A0 0x4000640fu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_A1 0x40006410u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_A1 0x40006411u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_A1 0x40006412u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_A1 0x40006413u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_A1 0x40006414u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_A1 0x40006415u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_A1 0x40006416u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_A1 0x40006417u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_A1 0x40006418u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_A1 0x40006419u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_A1 0x4000641au\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_A1 0x4000641bu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_A1 0x4000641cu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_A1 0x4000641du\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_A1 0x4000641eu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_A1 0x4000641fu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_D0 0x40006420u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_D0 0x40006421u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_D0 0x40006422u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_D0 0x40006423u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_D0 0x40006424u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_D0 0x40006425u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_D0 0x40006426u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_D0 0x40006427u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_D0 0x40006428u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_D0 0x40006429u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_D0 0x4000642au\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_D0 0x4000642bu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_D0 0x4000642cu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_D0 0x4000642du\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_D0 0x4000642eu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_D0 0x4000642fu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_D1 0x40006430u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_D1 0x40006431u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_D1 0x40006432u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_D1 0x40006433u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_D1 0x40006434u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_D1 0x40006435u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_D1 0x40006436u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_D1 0x40006437u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_D1 0x40006438u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_D1 0x40006439u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_D1 0x4000643au\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_D1 0x4000643bu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_D1 0x4000643cu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_D1 0x4000643du\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_D1 0x4000643eu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_D1 0x4000643fu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_F0 0x40006440u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_F0 0x40006441u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_F0 0x40006442u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_F0 0x40006443u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_F0 0x40006444u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_F0 0x40006445u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_F0 0x40006446u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_F0 0x40006447u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_F0 0x40006448u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_F0 0x40006449u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_F0 0x4000644au\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_F0 0x4000644bu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_F0 0x4000644cu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_F0 0x4000644du\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_F0 0x4000644eu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_F0 0x4000644fu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_F1 0x40006450u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_F1 0x40006451u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_F1 0x40006452u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_F1 0x40006453u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_F1 0x40006454u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_F1 0x40006455u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_F1 0x40006456u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_F1 0x40006457u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_F1 0x40006458u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_F1 0x40006459u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_F1 0x4000645au\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_F1 0x4000645bu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_F1 0x4000645cu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_F1 0x4000645du\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_F1 0x4000645eu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_F1 0x4000645fu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_ST 0x40006460u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_ST 0x40006461u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_ST 0x40006462u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_ST 0x40006463u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_ST 0x40006464u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_ST 0x40006465u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_ST 0x40006466u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_ST 0x40006467u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_ST 0x40006468u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_ST 0x40006469u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_ST 0x4000646au\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_ST 0x4000646bu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_ST 0x4000646cu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_ST 0x4000646du\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_ST 0x4000646eu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_ST 0x4000646fu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_CTL 0x40006470u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_CTL 0x40006471u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_CTL 0x40006472u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_CTL 0x40006473u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_CTL 0x40006474u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_CTL 0x40006475u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_CTL 0x40006476u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_CTL 0x40006477u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_CTL 0x40006478u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_CTL 0x40006479u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_CTL 0x4000647au\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_CTL 0x4000647bu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_CTL 0x4000647cu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_CTL 0x4000647du\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_CTL 0x4000647eu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_CTL 0x4000647fu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_MSK 0x40006480u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_MSK 0x40006481u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_MSK 0x40006482u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_MSK 0x40006483u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_MSK 0x40006484u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_MSK 0x40006485u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_MSK 0x40006486u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_MSK 0x40006487u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_MSK 0x40006488u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_MSK 0x40006489u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_MSK 0x4000648au\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_MSK 0x4000648bu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_MSK 0x4000648cu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_MSK 0x4000648du\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_MSK 0x4000648eu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_MSK 0x4000648fu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_ACTL 0x40006490u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_ACTL 0x40006491u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_ACTL 0x40006492u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_ACTL 0x40006493u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_ACTL 0x40006494u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_ACTL 0x40006495u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_ACTL 0x40006496u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_ACTL 0x40006497u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_ACTL 0x40006498u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_ACTL 0x40006499u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_ACTL 0x4000649au\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_ACTL 0x4000649bu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_ACTL 0x4000649cu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_ACTL 0x4000649du\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_ACTL 0x4000649eu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_ACTL 0x4000649fu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB00_MC 0x400064a0u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB01_MC 0x400064a1u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB02_MC 0x400064a2u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB03_MC 0x400064a3u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB04_MC 0x400064a4u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB05_MC 0x400064a5u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB06_MC 0x400064a6u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB07_MC 0x400064a7u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB08_MC 0x400064a8u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB09_MC 0x400064a9u\r
+#define CYDEV_UWRK_UWRK8_B0_UDB10_MC 0x400064aau\r
+#define CYDEV_UWRK_UWRK8_B0_UDB11_MC 0x400064abu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB12_MC 0x400064acu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB13_MC 0x400064adu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB14_MC 0x400064aeu\r
+#define CYDEV_UWRK_UWRK8_B0_UDB15_MC 0x400064afu\r
+#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500u\r
+#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_A0 0x40006504u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_A0 0x40006505u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_A0 0x40006506u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_A0 0x40006507u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_A0 0x40006508u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_A0 0x40006509u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_A0 0x4000650au\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_A0 0x4000650bu\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_A1 0x40006514u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_A1 0x40006515u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_A1 0x40006516u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_A1 0x40006517u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_A1 0x40006518u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_A1 0x40006519u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_A1 0x4000651au\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_A1 0x4000651bu\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_D0 0x40006524u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_D0 0x40006525u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_D0 0x40006526u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_D0 0x40006527u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_D0 0x40006528u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_D0 0x40006529u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_D0 0x4000652au\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_D0 0x4000652bu\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_D1 0x40006534u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_D1 0x40006535u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_D1 0x40006536u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_D1 0x40006537u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_D1 0x40006538u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_D1 0x40006539u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_D1 0x4000653au\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_D1 0x4000653bu\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_F0 0x40006544u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_F0 0x40006545u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_F0 0x40006546u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_F0 0x40006547u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_F0 0x40006548u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_F0 0x40006549u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_F0 0x4000654au\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_F0 0x4000654bu\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_F1 0x40006554u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_F1 0x40006555u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_F1 0x40006556u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_F1 0x40006557u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_F1 0x40006558u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_F1 0x40006559u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_F1 0x4000655au\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_F1 0x4000655bu\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_ST 0x40006564u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_ST 0x40006565u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_ST 0x40006566u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_ST 0x40006567u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_ST 0x40006568u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_ST 0x40006569u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_ST 0x4000656au\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_ST 0x4000656bu\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_CTL 0x40006574u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_CTL 0x40006575u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_CTL 0x40006576u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_CTL 0x40006577u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_CTL 0x40006578u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_CTL 0x40006579u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_CTL 0x4000657au\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_CTL 0x4000657bu\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_MSK 0x40006584u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_MSK 0x40006585u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_MSK 0x40006586u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_MSK 0x40006587u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_MSK 0x40006588u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_MSK 0x40006589u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_MSK 0x4000658au\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_MSK 0x4000658bu\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_ACTL 0x40006594u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_ACTL 0x40006595u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_ACTL 0x40006596u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_ACTL 0x40006597u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_ACTL 0x40006598u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_ACTL 0x40006599u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_ACTL 0x4000659au\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_ACTL 0x4000659bu\r
+#define CYDEV_UWRK_UWRK8_B1_UDB04_MC 0x400065a4u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB05_MC 0x400065a5u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB06_MC 0x400065a6u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB07_MC 0x400065a7u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB08_MC 0x400065a8u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB09_MC 0x400065a9u\r
+#define CYDEV_UWRK_UWRK8_B1_UDB10_MC 0x400065aau\r
+#define CYDEV_UWRK_UWRK8_B1_UDB11_MC 0x400065abu\r
+#define CYDEV_UWRK_UWRK16_BASE 0x40006800u\r
+#define CYDEV_UWRK_UWRK16_SIZE 0x00000760u\r
+#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800u\r
+#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 0x40006800u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 0x40006802u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 0x40006804u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 0x40006806u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 0x40006808u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 0x4000680au\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 0x4000680cu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 0x4000680eu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 0x40006810u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 0x40006812u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 0x40006814u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 0x40006816u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 0x40006818u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 0x4000681au\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 0x4000681cu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 0x4000681eu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 0x40006840u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 0x40006842u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 0x40006844u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 0x40006846u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 0x40006848u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 0x4000684au\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 0x4000684cu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 0x4000684eu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 0x40006850u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 0x40006852u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 0x40006854u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 0x40006856u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 0x40006858u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 0x4000685au\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 0x4000685cu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 0x4000685eu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 0x40006880u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 0x40006882u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 0x40006884u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 0x40006886u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 0x40006888u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 0x4000688au\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 0x4000688cu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 0x4000688eu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 0x40006890u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 0x40006892u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 0x40006894u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 0x40006896u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 0x40006898u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 0x4000689au\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 0x4000689cu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 0x4000689eu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL 0x400068c0u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL 0x400068c2u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL 0x400068c4u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL 0x400068c6u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL 0x400068c8u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL 0x400068cau\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL 0x400068ccu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL 0x400068ceu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL 0x400068d0u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL 0x400068d2u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL 0x400068d4u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL 0x400068d6u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL 0x400068d8u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL 0x400068dau\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL 0x400068dcu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL 0x400068deu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL 0x40006900u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL 0x40006902u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL 0x40006904u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL 0x40006906u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL 0x40006908u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL 0x4000690au\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL 0x4000690cu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL 0x4000690eu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL 0x40006910u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL 0x40006912u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL 0x40006914u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL 0x40006916u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL 0x40006918u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL 0x4000691au\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL 0x4000691cu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL 0x4000691eu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 0x40006940u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 0x40006942u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 0x40006944u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 0x40006946u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 0x40006948u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 0x4000694au\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 0x4000694cu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 0x4000694eu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 0x40006950u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 0x40006952u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 0x40006954u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 0x40006956u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 0x40006958u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 0x4000695au\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 0x4000695cu\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 0x4000695eu\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 0x40006a08u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 0x40006a0au\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 0x40006a0cu\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 0x40006a0eu\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 0x40006a10u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 0x40006a12u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 0x40006a14u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 0x40006a16u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 0x40006a48u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 0x40006a4au\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 0x40006a4cu\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 0x40006a4eu\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 0x40006a50u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 0x40006a52u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 0x40006a54u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 0x40006a56u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 0x40006a88u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 0x40006a8au\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 0x40006a8cu\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 0x40006a8eu\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 0x40006a90u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 0x40006a92u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 0x40006a94u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 0x40006a96u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL 0x40006ac8u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL 0x40006acau\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL 0x40006accu\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL 0x40006aceu\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL 0x40006ad0u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL 0x40006ad2u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL 0x40006ad4u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL 0x40006ad6u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL 0x40006b08u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL 0x40006b0au\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL 0x40006b0cu\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL 0x40006b0eu\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL 0x40006b10u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL 0x40006b12u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL 0x40006b14u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL 0x40006b16u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 0x40006b48u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 0x40006b4au\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 0x40006b4cu\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 0x40006b4eu\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 0x40006b50u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 0x40006b52u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 0x40006b54u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 0x40006b56u\r
+#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800u\r
+#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 0x40006800u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 0x40006802u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 0x40006804u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 0x40006806u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 0x40006808u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 0x4000680au\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 0x4000680cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 0x4000680eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 0x40006810u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 0x40006812u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 0x40006814u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 0x40006816u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 0x40006818u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 0x4000681au\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 0x4000681cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 0x40006820u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 0x40006822u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 0x40006824u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 0x40006826u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 0x40006828u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 0x4000682au\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 0x4000682cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 0x4000682eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 0x40006830u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 0x40006832u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 0x40006834u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 0x40006836u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 0x40006838u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 0x4000683au\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 0x4000683cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 0x40006840u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 0x40006842u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 0x40006844u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 0x40006846u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 0x40006848u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 0x4000684au\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 0x4000684cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 0x4000684eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 0x40006850u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 0x40006852u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 0x40006854u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 0x40006856u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 0x40006858u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 0x4000685au\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 0x4000685cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 0x40006860u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 0x40006862u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 0x40006864u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 0x40006866u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 0x40006868u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 0x4000686au\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 0x4000686cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 0x4000686eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 0x40006870u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 0x40006872u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 0x40006874u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 0x40006876u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 0x40006878u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 0x4000687au\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 0x4000687cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 0x40006880u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 0x40006882u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 0x40006884u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 0x40006886u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 0x40006888u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 0x4000688au\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 0x4000688cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 0x4000688eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 0x40006890u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 0x40006892u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 0x40006894u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 0x40006896u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 0x40006898u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 0x4000689au\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 0x4000689cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 0x400068a0u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 0x400068a2u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 0x400068a4u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 0x400068a6u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 0x400068a8u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 0x400068aau\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 0x400068acu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 0x400068aeu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 0x400068b0u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 0x400068b2u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 0x400068b4u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 0x400068b6u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 0x400068b8u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 0x400068bau\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 0x400068bcu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST 0x400068c0u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST 0x400068c2u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST 0x400068c4u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST 0x400068c6u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST 0x400068c8u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST 0x400068cau\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST 0x400068ccu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST 0x400068ceu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST 0x400068d0u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST 0x400068d2u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST 0x400068d4u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST 0x400068d6u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST 0x400068d8u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST 0x400068dau\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST 0x400068dcu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL 0x400068e0u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL 0x400068e2u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL 0x400068e4u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL 0x400068e6u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL 0x400068e8u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL 0x400068eau\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL 0x400068ecu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL 0x400068eeu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL 0x400068f0u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL 0x400068f2u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL 0x400068f4u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL 0x400068f6u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL 0x400068f8u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL 0x400068fau\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL 0x400068fcu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK 0x40006900u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK 0x40006902u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK 0x40006904u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK 0x40006906u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK 0x40006908u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK 0x4000690au\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK 0x4000690cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK 0x4000690eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK 0x40006910u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK 0x40006912u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK 0x40006914u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK 0x40006916u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK 0x40006918u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK 0x4000691au\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK 0x4000691cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL 0x40006920u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL 0x40006922u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL 0x40006924u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL 0x40006926u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL 0x40006928u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL 0x4000692au\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL 0x4000692cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL 0x4000692eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL 0x40006930u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL 0x40006932u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL 0x40006934u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL 0x40006936u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL 0x40006938u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL 0x4000693au\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL 0x4000693cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC 0x40006940u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC 0x40006942u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC 0x40006944u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC 0x40006946u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC 0x40006948u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC 0x4000694au\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC 0x4000694cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC 0x4000694eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC 0x40006950u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC 0x40006952u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC 0x40006954u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC 0x40006956u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC 0x40006958u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC 0x4000695au\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC 0x4000695cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 0x40006a08u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 0x40006a0au\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 0x40006a0cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 0x40006a0eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 0x40006a10u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 0x40006a12u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 0x40006a14u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 0x40006a16u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 0x40006a28u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 0x40006a2au\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 0x40006a2cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 0x40006a2eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 0x40006a30u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 0x40006a32u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 0x40006a34u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 0x40006a36u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 0x40006a48u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 0x40006a4au\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 0x40006a4cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 0x40006a4eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 0x40006a50u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 0x40006a52u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 0x40006a54u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 0x40006a56u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 0x40006a68u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 0x40006a6au\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 0x40006a6cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 0x40006a6eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 0x40006a70u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 0x40006a72u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 0x40006a74u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 0x40006a76u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 0x40006a88u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 0x40006a8au\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 0x40006a8cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 0x40006a8eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 0x40006a90u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 0x40006a92u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 0x40006a94u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 0x40006a96u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 0x40006aa8u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 0x40006aaau\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 0x40006aacu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 0x40006aaeu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 0x40006ab0u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 0x40006ab2u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 0x40006ab4u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 0x40006ab6u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST 0x40006ac8u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST 0x40006acau\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST 0x40006accu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST 0x40006aceu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST 0x40006ad0u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST 0x40006ad2u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST 0x40006ad4u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST 0x40006ad6u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL 0x40006ae8u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL 0x40006aeau\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL 0x40006aecu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL 0x40006aeeu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL 0x40006af0u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL 0x40006af2u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL 0x40006af4u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL 0x40006af6u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK 0x40006b08u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK 0x40006b0au\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK 0x40006b0cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK 0x40006b0eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK 0x40006b10u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK 0x40006b12u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK 0x40006b14u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK 0x40006b16u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL 0x40006b28u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL 0x40006b2au\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL 0x40006b2cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL 0x40006b2eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL 0x40006b30u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL 0x40006b32u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL 0x40006b34u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL 0x40006b36u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC 0x40006b48u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC 0x40006b4au\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC 0x40006b4cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC 0x40006b4eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC 0x40006b50u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC 0x40006b52u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC 0x40006b54u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC 0x40006b56u\r
+#define CYDEV_PHUB_BASE 0x40007000u\r
+#define CYDEV_PHUB_SIZE 0x00000c00u\r
+#define CYDEV_PHUB_CFG 0x40007000u\r
+#define CYDEV_PHUB_ERR 0x40007004u\r
+#define CYDEV_PHUB_ERR_ADR 0x40007008u\r
+#define CYDEV_PHUB_CH0_BASE 0x40007010u\r
+#define CYDEV_PHUB_CH0_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH0_BASIC_CFG 0x40007010u\r
+#define CYDEV_PHUB_CH0_ACTION 0x40007014u\r
+#define CYDEV_PHUB_CH0_BASIC_STATUS 0x40007018u\r
+#define CYDEV_PHUB_CH1_BASE 0x40007020u\r
+#define CYDEV_PHUB_CH1_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH1_BASIC_CFG 0x40007020u\r
+#define CYDEV_PHUB_CH1_ACTION 0x40007024u\r
+#define CYDEV_PHUB_CH1_BASIC_STATUS 0x40007028u\r
+#define CYDEV_PHUB_CH2_BASE 0x40007030u\r
+#define CYDEV_PHUB_CH2_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH2_BASIC_CFG 0x40007030u\r
+#define CYDEV_PHUB_CH2_ACTION 0x40007034u\r
+#define CYDEV_PHUB_CH2_BASIC_STATUS 0x40007038u\r
+#define CYDEV_PHUB_CH3_BASE 0x40007040u\r
+#define CYDEV_PHUB_CH3_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH3_BASIC_CFG 0x40007040u\r
+#define CYDEV_PHUB_CH3_ACTION 0x40007044u\r
+#define CYDEV_PHUB_CH3_BASIC_STATUS 0x40007048u\r
+#define CYDEV_PHUB_CH4_BASE 0x40007050u\r
+#define CYDEV_PHUB_CH4_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH4_BASIC_CFG 0x40007050u\r
+#define CYDEV_PHUB_CH4_ACTION 0x40007054u\r
+#define CYDEV_PHUB_CH4_BASIC_STATUS 0x40007058u\r
+#define CYDEV_PHUB_CH5_BASE 0x40007060u\r
+#define CYDEV_PHUB_CH5_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH5_BASIC_CFG 0x40007060u\r
+#define CYDEV_PHUB_CH5_ACTION 0x40007064u\r
+#define CYDEV_PHUB_CH5_BASIC_STATUS 0x40007068u\r
+#define CYDEV_PHUB_CH6_BASE 0x40007070u\r
+#define CYDEV_PHUB_CH6_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH6_BASIC_CFG 0x40007070u\r
+#define CYDEV_PHUB_CH6_ACTION 0x40007074u\r
+#define CYDEV_PHUB_CH6_BASIC_STATUS 0x40007078u\r
+#define CYDEV_PHUB_CH7_BASE 0x40007080u\r
+#define CYDEV_PHUB_CH7_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH7_BASIC_CFG 0x40007080u\r
+#define CYDEV_PHUB_CH7_ACTION 0x40007084u\r
+#define CYDEV_PHUB_CH7_BASIC_STATUS 0x40007088u\r
+#define CYDEV_PHUB_CH8_BASE 0x40007090u\r
+#define CYDEV_PHUB_CH8_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH8_BASIC_CFG 0x40007090u\r
+#define CYDEV_PHUB_CH8_ACTION 0x40007094u\r
+#define CYDEV_PHUB_CH8_BASIC_STATUS 0x40007098u\r
+#define CYDEV_PHUB_CH9_BASE 0x400070a0u\r
+#define CYDEV_PHUB_CH9_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH9_BASIC_CFG 0x400070a0u\r
+#define CYDEV_PHUB_CH9_ACTION 0x400070a4u\r
+#define CYDEV_PHUB_CH9_BASIC_STATUS 0x400070a8u\r
+#define CYDEV_PHUB_CH10_BASE 0x400070b0u\r
+#define CYDEV_PHUB_CH10_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH10_BASIC_CFG 0x400070b0u\r
+#define CYDEV_PHUB_CH10_ACTION 0x400070b4u\r
+#define CYDEV_PHUB_CH10_BASIC_STATUS 0x400070b8u\r
+#define CYDEV_PHUB_CH11_BASE 0x400070c0u\r
+#define CYDEV_PHUB_CH11_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH11_BASIC_CFG 0x400070c0u\r
+#define CYDEV_PHUB_CH11_ACTION 0x400070c4u\r
+#define CYDEV_PHUB_CH11_BASIC_STATUS 0x400070c8u\r
+#define CYDEV_PHUB_CH12_BASE 0x400070d0u\r
+#define CYDEV_PHUB_CH12_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH12_BASIC_CFG 0x400070d0u\r
+#define CYDEV_PHUB_CH12_ACTION 0x400070d4u\r
+#define CYDEV_PHUB_CH12_BASIC_STATUS 0x400070d8u\r
+#define CYDEV_PHUB_CH13_BASE 0x400070e0u\r
+#define CYDEV_PHUB_CH13_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH13_BASIC_CFG 0x400070e0u\r
+#define CYDEV_PHUB_CH13_ACTION 0x400070e4u\r
+#define CYDEV_PHUB_CH13_BASIC_STATUS 0x400070e8u\r
+#define CYDEV_PHUB_CH14_BASE 0x400070f0u\r
+#define CYDEV_PHUB_CH14_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH14_BASIC_CFG 0x400070f0u\r
+#define CYDEV_PHUB_CH14_ACTION 0x400070f4u\r
+#define CYDEV_PHUB_CH14_BASIC_STATUS 0x400070f8u\r
+#define CYDEV_PHUB_CH15_BASE 0x40007100u\r
+#define CYDEV_PHUB_CH15_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH15_BASIC_CFG 0x40007100u\r
+#define CYDEV_PHUB_CH15_ACTION 0x40007104u\r
+#define CYDEV_PHUB_CH15_BASIC_STATUS 0x40007108u\r
+#define CYDEV_PHUB_CH16_BASE 0x40007110u\r
+#define CYDEV_PHUB_CH16_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH16_BASIC_CFG 0x40007110u\r
+#define CYDEV_PHUB_CH16_ACTION 0x40007114u\r
+#define CYDEV_PHUB_CH16_BASIC_STATUS 0x40007118u\r
+#define CYDEV_PHUB_CH17_BASE 0x40007120u\r
+#define CYDEV_PHUB_CH17_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH17_BASIC_CFG 0x40007120u\r
+#define CYDEV_PHUB_CH17_ACTION 0x40007124u\r
+#define CYDEV_PHUB_CH17_BASIC_STATUS 0x40007128u\r
+#define CYDEV_PHUB_CH18_BASE 0x40007130u\r
+#define CYDEV_PHUB_CH18_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH18_BASIC_CFG 0x40007130u\r
+#define CYDEV_PHUB_CH18_ACTION 0x40007134u\r
+#define CYDEV_PHUB_CH18_BASIC_STATUS 0x40007138u\r
+#define CYDEV_PHUB_CH19_BASE 0x40007140u\r
+#define CYDEV_PHUB_CH19_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH19_BASIC_CFG 0x40007140u\r
+#define CYDEV_PHUB_CH19_ACTION 0x40007144u\r
+#define CYDEV_PHUB_CH19_BASIC_STATUS 0x40007148u\r
+#define CYDEV_PHUB_CH20_BASE 0x40007150u\r
+#define CYDEV_PHUB_CH20_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH20_BASIC_CFG 0x40007150u\r
+#define CYDEV_PHUB_CH20_ACTION 0x40007154u\r
+#define CYDEV_PHUB_CH20_BASIC_STATUS 0x40007158u\r
+#define CYDEV_PHUB_CH21_BASE 0x40007160u\r
+#define CYDEV_PHUB_CH21_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH21_BASIC_CFG 0x40007160u\r
+#define CYDEV_PHUB_CH21_ACTION 0x40007164u\r
+#define CYDEV_PHUB_CH21_BASIC_STATUS 0x40007168u\r
+#define CYDEV_PHUB_CH22_BASE 0x40007170u\r
+#define CYDEV_PHUB_CH22_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH22_BASIC_CFG 0x40007170u\r
+#define CYDEV_PHUB_CH22_ACTION 0x40007174u\r
+#define CYDEV_PHUB_CH22_BASIC_STATUS 0x40007178u\r
+#define CYDEV_PHUB_CH23_BASE 0x40007180u\r
+#define CYDEV_PHUB_CH23_SIZE 0x0000000cu\r
+#define CYDEV_PHUB_CH23_BASIC_CFG 0x40007180u\r
+#define CYDEV_PHUB_CH23_ACTION 0x40007184u\r
+#define CYDEV_PHUB_CH23_BASIC_STATUS 0x40007188u\r
+#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600u\r
+#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM0_CFG0 0x40007600u\r
+#define CYDEV_PHUB_CFGMEM0_CFG1 0x40007604u\r
+#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608u\r
+#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM1_CFG0 0x40007608u\r
+#define CYDEV_PHUB_CFGMEM1_CFG1 0x4000760cu\r
+#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610u\r
+#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM2_CFG0 0x40007610u\r
+#define CYDEV_PHUB_CFGMEM2_CFG1 0x40007614u\r
+#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618u\r
+#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM3_CFG0 0x40007618u\r
+#define CYDEV_PHUB_CFGMEM3_CFG1 0x4000761cu\r
+#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620u\r
+#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM4_CFG0 0x40007620u\r
+#define CYDEV_PHUB_CFGMEM4_CFG1 0x40007624u\r
+#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628u\r
+#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM5_CFG0 0x40007628u\r
+#define CYDEV_PHUB_CFGMEM5_CFG1 0x4000762cu\r
+#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630u\r
+#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM6_CFG0 0x40007630u\r
+#define CYDEV_PHUB_CFGMEM6_CFG1 0x40007634u\r
+#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638u\r
+#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM7_CFG0 0x40007638u\r
+#define CYDEV_PHUB_CFGMEM7_CFG1 0x4000763cu\r
+#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640u\r
+#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM8_CFG0 0x40007640u\r
+#define CYDEV_PHUB_CFGMEM8_CFG1 0x40007644u\r
+#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648u\r
+#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM9_CFG0 0x40007648u\r
+#define CYDEV_PHUB_CFGMEM9_CFG1 0x4000764cu\r
+#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650u\r
+#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM10_CFG0 0x40007650u\r
+#define CYDEV_PHUB_CFGMEM10_CFG1 0x40007654u\r
+#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658u\r
+#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM11_CFG0 0x40007658u\r
+#define CYDEV_PHUB_CFGMEM11_CFG1 0x4000765cu\r
+#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660u\r
+#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM12_CFG0 0x40007660u\r
+#define CYDEV_PHUB_CFGMEM12_CFG1 0x40007664u\r
+#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668u\r
+#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM13_CFG0 0x40007668u\r
+#define CYDEV_PHUB_CFGMEM13_CFG1 0x4000766cu\r
+#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670u\r
+#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM14_CFG0 0x40007670u\r
+#define CYDEV_PHUB_CFGMEM14_CFG1 0x40007674u\r
+#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678u\r
+#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM15_CFG0 0x40007678u\r
+#define CYDEV_PHUB_CFGMEM15_CFG1 0x4000767cu\r
+#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680u\r
+#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM16_CFG0 0x40007680u\r
+#define CYDEV_PHUB_CFGMEM16_CFG1 0x40007684u\r
+#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688u\r
+#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM17_CFG0 0x40007688u\r
+#define CYDEV_PHUB_CFGMEM17_CFG1 0x4000768cu\r
+#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690u\r
+#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM18_CFG0 0x40007690u\r
+#define CYDEV_PHUB_CFGMEM18_CFG1 0x40007694u\r
+#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698u\r
+#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM19_CFG0 0x40007698u\r
+#define CYDEV_PHUB_CFGMEM19_CFG1 0x4000769cu\r
+#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0u\r
+#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM20_CFG0 0x400076a0u\r
+#define CYDEV_PHUB_CFGMEM20_CFG1 0x400076a4u\r
+#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8u\r
+#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM21_CFG0 0x400076a8u\r
+#define CYDEV_PHUB_CFGMEM21_CFG1 0x400076acu\r
+#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0u\r
+#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM22_CFG0 0x400076b0u\r
+#define CYDEV_PHUB_CFGMEM22_CFG1 0x400076b4u\r
+#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8u\r
+#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008u\r
+#define CYDEV_PHUB_CFGMEM23_CFG0 0x400076b8u\r
+#define CYDEV_PHUB_CFGMEM23_CFG1 0x400076bcu\r
+#define CYDEV_PHUB_TDMEM0_BASE 0x40007800u\r
+#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM0_ORIG_TD0 0x40007800u\r
+#define CYDEV_PHUB_TDMEM0_ORIG_TD1 0x40007804u\r
+#define CYDEV_PHUB_TDMEM1_BASE 0x40007808u\r
+#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM1_ORIG_TD0 0x40007808u\r
+#define CYDEV_PHUB_TDMEM1_ORIG_TD1 0x4000780cu\r
+#define CYDEV_PHUB_TDMEM2_BASE 0x40007810u\r
+#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM2_ORIG_TD0 0x40007810u\r
+#define CYDEV_PHUB_TDMEM2_ORIG_TD1 0x40007814u\r
+#define CYDEV_PHUB_TDMEM3_BASE 0x40007818u\r
+#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM3_ORIG_TD0 0x40007818u\r
+#define CYDEV_PHUB_TDMEM3_ORIG_TD1 0x4000781cu\r
+#define CYDEV_PHUB_TDMEM4_BASE 0x40007820u\r
+#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM4_ORIG_TD0 0x40007820u\r
+#define CYDEV_PHUB_TDMEM4_ORIG_TD1 0x40007824u\r
+#define CYDEV_PHUB_TDMEM5_BASE 0x40007828u\r
+#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM5_ORIG_TD0 0x40007828u\r
+#define CYDEV_PHUB_TDMEM5_ORIG_TD1 0x4000782cu\r
+#define CYDEV_PHUB_TDMEM6_BASE 0x40007830u\r
+#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM6_ORIG_TD0 0x40007830u\r
+#define CYDEV_PHUB_TDMEM6_ORIG_TD1 0x40007834u\r
+#define CYDEV_PHUB_TDMEM7_BASE 0x40007838u\r
+#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM7_ORIG_TD0 0x40007838u\r
+#define CYDEV_PHUB_TDMEM7_ORIG_TD1 0x4000783cu\r
+#define CYDEV_PHUB_TDMEM8_BASE 0x40007840u\r
+#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM8_ORIG_TD0 0x40007840u\r
+#define CYDEV_PHUB_TDMEM8_ORIG_TD1 0x40007844u\r
+#define CYDEV_PHUB_TDMEM9_BASE 0x40007848u\r
+#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM9_ORIG_TD0 0x40007848u\r
+#define CYDEV_PHUB_TDMEM9_ORIG_TD1 0x4000784cu\r
+#define CYDEV_PHUB_TDMEM10_BASE 0x40007850u\r
+#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM10_ORIG_TD0 0x40007850u\r
+#define CYDEV_PHUB_TDMEM10_ORIG_TD1 0x40007854u\r
+#define CYDEV_PHUB_TDMEM11_BASE 0x40007858u\r
+#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM11_ORIG_TD0 0x40007858u\r
+#define CYDEV_PHUB_TDMEM11_ORIG_TD1 0x4000785cu\r
+#define CYDEV_PHUB_TDMEM12_BASE 0x40007860u\r
+#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM12_ORIG_TD0 0x40007860u\r
+#define CYDEV_PHUB_TDMEM12_ORIG_TD1 0x40007864u\r
+#define CYDEV_PHUB_TDMEM13_BASE 0x40007868u\r
+#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM13_ORIG_TD0 0x40007868u\r
+#define CYDEV_PHUB_TDMEM13_ORIG_TD1 0x4000786cu\r
+#define CYDEV_PHUB_TDMEM14_BASE 0x40007870u\r
+#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM14_ORIG_TD0 0x40007870u\r
+#define CYDEV_PHUB_TDMEM14_ORIG_TD1 0x40007874u\r
+#define CYDEV_PHUB_TDMEM15_BASE 0x40007878u\r
+#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM15_ORIG_TD0 0x40007878u\r
+#define CYDEV_PHUB_TDMEM15_ORIG_TD1 0x4000787cu\r
+#define CYDEV_PHUB_TDMEM16_BASE 0x40007880u\r
+#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM16_ORIG_TD0 0x40007880u\r
+#define CYDEV_PHUB_TDMEM16_ORIG_TD1 0x40007884u\r
+#define CYDEV_PHUB_TDMEM17_BASE 0x40007888u\r
+#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM17_ORIG_TD0 0x40007888u\r
+#define CYDEV_PHUB_TDMEM17_ORIG_TD1 0x4000788cu\r
+#define CYDEV_PHUB_TDMEM18_BASE 0x40007890u\r
+#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM18_ORIG_TD0 0x40007890u\r
+#define CYDEV_PHUB_TDMEM18_ORIG_TD1 0x40007894u\r
+#define CYDEV_PHUB_TDMEM19_BASE 0x40007898u\r
+#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM19_ORIG_TD0 0x40007898u\r
+#define CYDEV_PHUB_TDMEM19_ORIG_TD1 0x4000789cu\r
+#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0u\r
+#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM20_ORIG_TD0 0x400078a0u\r
+#define CYDEV_PHUB_TDMEM20_ORIG_TD1 0x400078a4u\r
+#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8u\r
+#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM21_ORIG_TD0 0x400078a8u\r
+#define CYDEV_PHUB_TDMEM21_ORIG_TD1 0x400078acu\r
+#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0u\r
+#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM22_ORIG_TD0 0x400078b0u\r
+#define CYDEV_PHUB_TDMEM22_ORIG_TD1 0x400078b4u\r
+#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8u\r
+#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM23_ORIG_TD0 0x400078b8u\r
+#define CYDEV_PHUB_TDMEM23_ORIG_TD1 0x400078bcu\r
+#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0u\r
+#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM24_ORIG_TD0 0x400078c0u\r
+#define CYDEV_PHUB_TDMEM24_ORIG_TD1 0x400078c4u\r
+#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8u\r
+#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM25_ORIG_TD0 0x400078c8u\r
+#define CYDEV_PHUB_TDMEM25_ORIG_TD1 0x400078ccu\r
+#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0u\r
+#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM26_ORIG_TD0 0x400078d0u\r
+#define CYDEV_PHUB_TDMEM26_ORIG_TD1 0x400078d4u\r
+#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8u\r
+#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM27_ORIG_TD0 0x400078d8u\r
+#define CYDEV_PHUB_TDMEM27_ORIG_TD1 0x400078dcu\r
+#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0u\r
+#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM28_ORIG_TD0 0x400078e0u\r
+#define CYDEV_PHUB_TDMEM28_ORIG_TD1 0x400078e4u\r
+#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8u\r
+#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM29_ORIG_TD0 0x400078e8u\r
+#define CYDEV_PHUB_TDMEM29_ORIG_TD1 0x400078ecu\r
+#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0u\r
+#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM30_ORIG_TD0 0x400078f0u\r
+#define CYDEV_PHUB_TDMEM30_ORIG_TD1 0x400078f4u\r
+#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8u\r
+#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM31_ORIG_TD0 0x400078f8u\r
+#define CYDEV_PHUB_TDMEM31_ORIG_TD1 0x400078fcu\r
+#define CYDEV_PHUB_TDMEM32_BASE 0x40007900u\r
+#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM32_ORIG_TD0 0x40007900u\r
+#define CYDEV_PHUB_TDMEM32_ORIG_TD1 0x40007904u\r
+#define CYDEV_PHUB_TDMEM33_BASE 0x40007908u\r
+#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM33_ORIG_TD0 0x40007908u\r
+#define CYDEV_PHUB_TDMEM33_ORIG_TD1 0x4000790cu\r
+#define CYDEV_PHUB_TDMEM34_BASE 0x40007910u\r
+#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM34_ORIG_TD0 0x40007910u\r
+#define CYDEV_PHUB_TDMEM34_ORIG_TD1 0x40007914u\r
+#define CYDEV_PHUB_TDMEM35_BASE 0x40007918u\r
+#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM35_ORIG_TD0 0x40007918u\r
+#define CYDEV_PHUB_TDMEM35_ORIG_TD1 0x4000791cu\r
+#define CYDEV_PHUB_TDMEM36_BASE 0x40007920u\r
+#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM36_ORIG_TD0 0x40007920u\r
+#define CYDEV_PHUB_TDMEM36_ORIG_TD1 0x40007924u\r
+#define CYDEV_PHUB_TDMEM37_BASE 0x40007928u\r
+#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM37_ORIG_TD0 0x40007928u\r
+#define CYDEV_PHUB_TDMEM37_ORIG_TD1 0x4000792cu\r
+#define CYDEV_PHUB_TDMEM38_BASE 0x40007930u\r
+#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM38_ORIG_TD0 0x40007930u\r
+#define CYDEV_PHUB_TDMEM38_ORIG_TD1 0x40007934u\r
+#define CYDEV_PHUB_TDMEM39_BASE 0x40007938u\r
+#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM39_ORIG_TD0 0x40007938u\r
+#define CYDEV_PHUB_TDMEM39_ORIG_TD1 0x4000793cu\r
+#define CYDEV_PHUB_TDMEM40_BASE 0x40007940u\r
+#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM40_ORIG_TD0 0x40007940u\r
+#define CYDEV_PHUB_TDMEM40_ORIG_TD1 0x40007944u\r
+#define CYDEV_PHUB_TDMEM41_BASE 0x40007948u\r
+#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM41_ORIG_TD0 0x40007948u\r
+#define CYDEV_PHUB_TDMEM41_ORIG_TD1 0x4000794cu\r
+#define CYDEV_PHUB_TDMEM42_BASE 0x40007950u\r
+#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM42_ORIG_TD0 0x40007950u\r
+#define CYDEV_PHUB_TDMEM42_ORIG_TD1 0x40007954u\r
+#define CYDEV_PHUB_TDMEM43_BASE 0x40007958u\r
+#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM43_ORIG_TD0 0x40007958u\r
+#define CYDEV_PHUB_TDMEM43_ORIG_TD1 0x4000795cu\r
+#define CYDEV_PHUB_TDMEM44_BASE 0x40007960u\r
+#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM44_ORIG_TD0 0x40007960u\r
+#define CYDEV_PHUB_TDMEM44_ORIG_TD1 0x40007964u\r
+#define CYDEV_PHUB_TDMEM45_BASE 0x40007968u\r
+#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM45_ORIG_TD0 0x40007968u\r
+#define CYDEV_PHUB_TDMEM45_ORIG_TD1 0x4000796cu\r
+#define CYDEV_PHUB_TDMEM46_BASE 0x40007970u\r
+#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM46_ORIG_TD0 0x40007970u\r
+#define CYDEV_PHUB_TDMEM46_ORIG_TD1 0x40007974u\r
+#define CYDEV_PHUB_TDMEM47_BASE 0x40007978u\r
+#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM47_ORIG_TD0 0x40007978u\r
+#define CYDEV_PHUB_TDMEM47_ORIG_TD1 0x4000797cu\r
+#define CYDEV_PHUB_TDMEM48_BASE 0x40007980u\r
+#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM48_ORIG_TD0 0x40007980u\r
+#define CYDEV_PHUB_TDMEM48_ORIG_TD1 0x40007984u\r
+#define CYDEV_PHUB_TDMEM49_BASE 0x40007988u\r
+#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM49_ORIG_TD0 0x40007988u\r
+#define CYDEV_PHUB_TDMEM49_ORIG_TD1 0x4000798cu\r
+#define CYDEV_PHUB_TDMEM50_BASE 0x40007990u\r
+#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM50_ORIG_TD0 0x40007990u\r
+#define CYDEV_PHUB_TDMEM50_ORIG_TD1 0x40007994u\r
+#define CYDEV_PHUB_TDMEM51_BASE 0x40007998u\r
+#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM51_ORIG_TD0 0x40007998u\r
+#define CYDEV_PHUB_TDMEM51_ORIG_TD1 0x4000799cu\r
+#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0u\r
+#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM52_ORIG_TD0 0x400079a0u\r
+#define CYDEV_PHUB_TDMEM52_ORIG_TD1 0x400079a4u\r
+#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8u\r
+#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM53_ORIG_TD0 0x400079a8u\r
+#define CYDEV_PHUB_TDMEM53_ORIG_TD1 0x400079acu\r
+#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0u\r
+#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM54_ORIG_TD0 0x400079b0u\r
+#define CYDEV_PHUB_TDMEM54_ORIG_TD1 0x400079b4u\r
+#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8u\r
+#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM55_ORIG_TD0 0x400079b8u\r
+#define CYDEV_PHUB_TDMEM55_ORIG_TD1 0x400079bcu\r
+#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0u\r
+#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM56_ORIG_TD0 0x400079c0u\r
+#define CYDEV_PHUB_TDMEM56_ORIG_TD1 0x400079c4u\r
+#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8u\r
+#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM57_ORIG_TD0 0x400079c8u\r
+#define CYDEV_PHUB_TDMEM57_ORIG_TD1 0x400079ccu\r
+#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0u\r
+#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM58_ORIG_TD0 0x400079d0u\r
+#define CYDEV_PHUB_TDMEM58_ORIG_TD1 0x400079d4u\r
+#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8u\r
+#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM59_ORIG_TD0 0x400079d8u\r
+#define CYDEV_PHUB_TDMEM59_ORIG_TD1 0x400079dcu\r
+#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0u\r
+#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM60_ORIG_TD0 0x400079e0u\r
+#define CYDEV_PHUB_TDMEM60_ORIG_TD1 0x400079e4u\r
+#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8u\r
+#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM61_ORIG_TD0 0x400079e8u\r
+#define CYDEV_PHUB_TDMEM61_ORIG_TD1 0x400079ecu\r
+#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0u\r
+#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM62_ORIG_TD0 0x400079f0u\r
+#define CYDEV_PHUB_TDMEM62_ORIG_TD1 0x400079f4u\r
+#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8u\r
+#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM63_ORIG_TD0 0x400079f8u\r
+#define CYDEV_PHUB_TDMEM63_ORIG_TD1 0x400079fcu\r
+#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00u\r
+#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM64_ORIG_TD0 0x40007a00u\r
+#define CYDEV_PHUB_TDMEM64_ORIG_TD1 0x40007a04u\r
+#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08u\r
+#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM65_ORIG_TD0 0x40007a08u\r
+#define CYDEV_PHUB_TDMEM65_ORIG_TD1 0x40007a0cu\r
+#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10u\r
+#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM66_ORIG_TD0 0x40007a10u\r
+#define CYDEV_PHUB_TDMEM66_ORIG_TD1 0x40007a14u\r
+#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18u\r
+#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM67_ORIG_TD0 0x40007a18u\r
+#define CYDEV_PHUB_TDMEM67_ORIG_TD1 0x40007a1cu\r
+#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20u\r
+#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM68_ORIG_TD0 0x40007a20u\r
+#define CYDEV_PHUB_TDMEM68_ORIG_TD1 0x40007a24u\r
+#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28u\r
+#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM69_ORIG_TD0 0x40007a28u\r
+#define CYDEV_PHUB_TDMEM69_ORIG_TD1 0x40007a2cu\r
+#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30u\r
+#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM70_ORIG_TD0 0x40007a30u\r
+#define CYDEV_PHUB_TDMEM70_ORIG_TD1 0x40007a34u\r
+#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38u\r
+#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM71_ORIG_TD0 0x40007a38u\r
+#define CYDEV_PHUB_TDMEM71_ORIG_TD1 0x40007a3cu\r
+#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40u\r
+#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM72_ORIG_TD0 0x40007a40u\r
+#define CYDEV_PHUB_TDMEM72_ORIG_TD1 0x40007a44u\r
+#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48u\r
+#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM73_ORIG_TD0 0x40007a48u\r
+#define CYDEV_PHUB_TDMEM73_ORIG_TD1 0x40007a4cu\r
+#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50u\r
+#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM74_ORIG_TD0 0x40007a50u\r
+#define CYDEV_PHUB_TDMEM74_ORIG_TD1 0x40007a54u\r
+#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58u\r
+#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM75_ORIG_TD0 0x40007a58u\r
+#define CYDEV_PHUB_TDMEM75_ORIG_TD1 0x40007a5cu\r
+#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60u\r
+#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM76_ORIG_TD0 0x40007a60u\r
+#define CYDEV_PHUB_TDMEM76_ORIG_TD1 0x40007a64u\r
+#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68u\r
+#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM77_ORIG_TD0 0x40007a68u\r
+#define CYDEV_PHUB_TDMEM77_ORIG_TD1 0x40007a6cu\r
+#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70u\r
+#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM78_ORIG_TD0 0x40007a70u\r
+#define CYDEV_PHUB_TDMEM78_ORIG_TD1 0x40007a74u\r
+#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78u\r
+#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM79_ORIG_TD0 0x40007a78u\r
+#define CYDEV_PHUB_TDMEM79_ORIG_TD1 0x40007a7cu\r
+#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80u\r
+#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM80_ORIG_TD0 0x40007a80u\r
+#define CYDEV_PHUB_TDMEM80_ORIG_TD1 0x40007a84u\r
+#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88u\r
+#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM81_ORIG_TD0 0x40007a88u\r
+#define CYDEV_PHUB_TDMEM81_ORIG_TD1 0x40007a8cu\r
+#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90u\r
+#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM82_ORIG_TD0 0x40007a90u\r
+#define CYDEV_PHUB_TDMEM82_ORIG_TD1 0x40007a94u\r
+#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98u\r
+#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM83_ORIG_TD0 0x40007a98u\r
+#define CYDEV_PHUB_TDMEM83_ORIG_TD1 0x40007a9cu\r
+#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0u\r
+#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM84_ORIG_TD0 0x40007aa0u\r
+#define CYDEV_PHUB_TDMEM84_ORIG_TD1 0x40007aa4u\r
+#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8u\r
+#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM85_ORIG_TD0 0x40007aa8u\r
+#define CYDEV_PHUB_TDMEM85_ORIG_TD1 0x40007aacu\r
+#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0u\r
+#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM86_ORIG_TD0 0x40007ab0u\r
+#define CYDEV_PHUB_TDMEM86_ORIG_TD1 0x40007ab4u\r
+#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8u\r
+#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM87_ORIG_TD0 0x40007ab8u\r
+#define CYDEV_PHUB_TDMEM87_ORIG_TD1 0x40007abcu\r
+#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0u\r
+#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM88_ORIG_TD0 0x40007ac0u\r
+#define CYDEV_PHUB_TDMEM88_ORIG_TD1 0x40007ac4u\r
+#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8u\r
+#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM89_ORIG_TD0 0x40007ac8u\r
+#define CYDEV_PHUB_TDMEM89_ORIG_TD1 0x40007accu\r
+#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0u\r
+#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM90_ORIG_TD0 0x40007ad0u\r
+#define CYDEV_PHUB_TDMEM90_ORIG_TD1 0x40007ad4u\r
+#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8u\r
+#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM91_ORIG_TD0 0x40007ad8u\r
+#define CYDEV_PHUB_TDMEM91_ORIG_TD1 0x40007adcu\r
+#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0u\r
+#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM92_ORIG_TD0 0x40007ae0u\r
+#define CYDEV_PHUB_TDMEM92_ORIG_TD1 0x40007ae4u\r
+#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8u\r
+#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM93_ORIG_TD0 0x40007ae8u\r
+#define CYDEV_PHUB_TDMEM93_ORIG_TD1 0x40007aecu\r
+#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0u\r
+#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM94_ORIG_TD0 0x40007af0u\r
+#define CYDEV_PHUB_TDMEM94_ORIG_TD1 0x40007af4u\r
+#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8u\r
+#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM95_ORIG_TD0 0x40007af8u\r
+#define CYDEV_PHUB_TDMEM95_ORIG_TD1 0x40007afcu\r
+#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00u\r
+#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM96_ORIG_TD0 0x40007b00u\r
+#define CYDEV_PHUB_TDMEM96_ORIG_TD1 0x40007b04u\r
+#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08u\r
+#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM97_ORIG_TD0 0x40007b08u\r
+#define CYDEV_PHUB_TDMEM97_ORIG_TD1 0x40007b0cu\r
+#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10u\r
+#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM98_ORIG_TD0 0x40007b10u\r
+#define CYDEV_PHUB_TDMEM98_ORIG_TD1 0x40007b14u\r
+#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18u\r
+#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM99_ORIG_TD0 0x40007b18u\r
+#define CYDEV_PHUB_TDMEM99_ORIG_TD1 0x40007b1cu\r
+#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20u\r
+#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM100_ORIG_TD0 0x40007b20u\r
+#define CYDEV_PHUB_TDMEM100_ORIG_TD1 0x40007b24u\r
+#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28u\r
+#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM101_ORIG_TD0 0x40007b28u\r
+#define CYDEV_PHUB_TDMEM101_ORIG_TD1 0x40007b2cu\r
+#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30u\r
+#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM102_ORIG_TD0 0x40007b30u\r
+#define CYDEV_PHUB_TDMEM102_ORIG_TD1 0x40007b34u\r
+#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38u\r
+#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM103_ORIG_TD0 0x40007b38u\r
+#define CYDEV_PHUB_TDMEM103_ORIG_TD1 0x40007b3cu\r
+#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40u\r
+#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM104_ORIG_TD0 0x40007b40u\r
+#define CYDEV_PHUB_TDMEM104_ORIG_TD1 0x40007b44u\r
+#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48u\r
+#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM105_ORIG_TD0 0x40007b48u\r
+#define CYDEV_PHUB_TDMEM105_ORIG_TD1 0x40007b4cu\r
+#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50u\r
+#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM106_ORIG_TD0 0x40007b50u\r
+#define CYDEV_PHUB_TDMEM106_ORIG_TD1 0x40007b54u\r
+#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58u\r
+#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM107_ORIG_TD0 0x40007b58u\r
+#define CYDEV_PHUB_TDMEM107_ORIG_TD1 0x40007b5cu\r
+#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60u\r
+#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM108_ORIG_TD0 0x40007b60u\r
+#define CYDEV_PHUB_TDMEM108_ORIG_TD1 0x40007b64u\r
+#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68u\r
+#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM109_ORIG_TD0 0x40007b68u\r
+#define CYDEV_PHUB_TDMEM109_ORIG_TD1 0x40007b6cu\r
+#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70u\r
+#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM110_ORIG_TD0 0x40007b70u\r
+#define CYDEV_PHUB_TDMEM110_ORIG_TD1 0x40007b74u\r
+#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78u\r
+#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM111_ORIG_TD0 0x40007b78u\r
+#define CYDEV_PHUB_TDMEM111_ORIG_TD1 0x40007b7cu\r
+#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80u\r
+#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM112_ORIG_TD0 0x40007b80u\r
+#define CYDEV_PHUB_TDMEM112_ORIG_TD1 0x40007b84u\r
+#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88u\r
+#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM113_ORIG_TD0 0x40007b88u\r
+#define CYDEV_PHUB_TDMEM113_ORIG_TD1 0x40007b8cu\r
+#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90u\r
+#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM114_ORIG_TD0 0x40007b90u\r
+#define CYDEV_PHUB_TDMEM114_ORIG_TD1 0x40007b94u\r
+#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98u\r
+#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM115_ORIG_TD0 0x40007b98u\r
+#define CYDEV_PHUB_TDMEM115_ORIG_TD1 0x40007b9cu\r
+#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0u\r
+#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM116_ORIG_TD0 0x40007ba0u\r
+#define CYDEV_PHUB_TDMEM116_ORIG_TD1 0x40007ba4u\r
+#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8u\r
+#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM117_ORIG_TD0 0x40007ba8u\r
+#define CYDEV_PHUB_TDMEM117_ORIG_TD1 0x40007bacu\r
+#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0u\r
+#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM118_ORIG_TD0 0x40007bb0u\r
+#define CYDEV_PHUB_TDMEM118_ORIG_TD1 0x40007bb4u\r
+#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8u\r
+#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM119_ORIG_TD0 0x40007bb8u\r
+#define CYDEV_PHUB_TDMEM119_ORIG_TD1 0x40007bbcu\r
+#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0u\r
+#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM120_ORIG_TD0 0x40007bc0u\r
+#define CYDEV_PHUB_TDMEM120_ORIG_TD1 0x40007bc4u\r
+#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8u\r
+#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM121_ORIG_TD0 0x40007bc8u\r
+#define CYDEV_PHUB_TDMEM121_ORIG_TD1 0x40007bccu\r
+#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0u\r
+#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM122_ORIG_TD0 0x40007bd0u\r
+#define CYDEV_PHUB_TDMEM122_ORIG_TD1 0x40007bd4u\r
+#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8u\r
+#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM123_ORIG_TD0 0x40007bd8u\r
+#define CYDEV_PHUB_TDMEM123_ORIG_TD1 0x40007bdcu\r
+#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0u\r
+#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM124_ORIG_TD0 0x40007be0u\r
+#define CYDEV_PHUB_TDMEM124_ORIG_TD1 0x40007be4u\r
+#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8u\r
+#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM125_ORIG_TD0 0x40007be8u\r
+#define CYDEV_PHUB_TDMEM125_ORIG_TD1 0x40007becu\r
+#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0u\r
+#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM126_ORIG_TD0 0x40007bf0u\r
+#define CYDEV_PHUB_TDMEM126_ORIG_TD1 0x40007bf4u\r
+#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8u\r
+#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008u\r
+#define CYDEV_PHUB_TDMEM127_ORIG_TD0 0x40007bf8u\r
+#define CYDEV_PHUB_TDMEM127_ORIG_TD1 0x40007bfcu\r
+#define CYDEV_EE_BASE 0x40008000u\r
+#define CYDEV_EE_SIZE 0x00000800u\r
+#define CYDEV_EE_DATA_MBASE 0x40008000u\r
+#define CYDEV_EE_DATA_MSIZE 0x00000800u\r
+#define CYDEV_CAN0_BASE 0x4000a000u\r
+#define CYDEV_CAN0_SIZE 0x000002a0u\r
+#define CYDEV_CAN0_CSR_BASE 0x4000a000u\r
+#define CYDEV_CAN0_CSR_SIZE 0x00000018u\r
+#define CYDEV_CAN0_CSR_INT_SR 0x4000a000u\r
+#define CYDEV_CAN0_CSR_INT_EN 0x4000a004u\r
+#define CYDEV_CAN0_CSR_BUF_SR 0x4000a008u\r
+#define CYDEV_CAN0_CSR_ERR_SR 0x4000a00cu\r
+#define CYDEV_CAN0_CSR_CMD 0x4000a010u\r
+#define CYDEV_CAN0_CSR_CFG 0x4000a014u\r
+#define CYDEV_CAN0_TX0_BASE 0x4000a020u\r
+#define CYDEV_CAN0_TX0_SIZE 0x00000010u\r
+#define CYDEV_CAN0_TX0_CMD 0x4000a020u\r
+#define CYDEV_CAN0_TX0_ID 0x4000a024u\r
+#define CYDEV_CAN0_TX0_DH 0x4000a028u\r
+#define CYDEV_CAN0_TX0_DL 0x4000a02cu\r
+#define CYDEV_CAN0_TX1_BASE 0x4000a030u\r
+#define CYDEV_CAN0_TX1_SIZE 0x00000010u\r
+#define CYDEV_CAN0_TX1_CMD 0x4000a030u\r
+#define CYDEV_CAN0_TX1_ID 0x4000a034u\r
+#define CYDEV_CAN0_TX1_DH 0x4000a038u\r
+#define CYDEV_CAN0_TX1_DL 0x4000a03cu\r
+#define CYDEV_CAN0_TX2_BASE 0x4000a040u\r
+#define CYDEV_CAN0_TX2_SIZE 0x00000010u\r
+#define CYDEV_CAN0_TX2_CMD 0x4000a040u\r
+#define CYDEV_CAN0_TX2_ID 0x4000a044u\r
+#define CYDEV_CAN0_TX2_DH 0x4000a048u\r
+#define CYDEV_CAN0_TX2_DL 0x4000a04cu\r
+#define CYDEV_CAN0_TX3_BASE 0x4000a050u\r
+#define CYDEV_CAN0_TX3_SIZE 0x00000010u\r
+#define CYDEV_CAN0_TX3_CMD 0x4000a050u\r
+#define CYDEV_CAN0_TX3_ID 0x4000a054u\r
+#define CYDEV_CAN0_TX3_DH 0x4000a058u\r
+#define CYDEV_CAN0_TX3_DL 0x4000a05cu\r
+#define CYDEV_CAN0_TX4_BASE 0x4000a060u\r
+#define CYDEV_CAN0_TX4_SIZE 0x00000010u\r
+#define CYDEV_CAN0_TX4_CMD 0x4000a060u\r
+#define CYDEV_CAN0_TX4_ID 0x4000a064u\r
+#define CYDEV_CAN0_TX4_DH 0x4000a068u\r
+#define CYDEV_CAN0_TX4_DL 0x4000a06cu\r
+#define CYDEV_CAN0_TX5_BASE 0x4000a070u\r
+#define CYDEV_CAN0_TX5_SIZE 0x00000010u\r
+#define CYDEV_CAN0_TX5_CMD 0x4000a070u\r
+#define CYDEV_CAN0_TX5_ID 0x4000a074u\r
+#define CYDEV_CAN0_TX5_DH 0x4000a078u\r
+#define CYDEV_CAN0_TX5_DL 0x4000a07cu\r
+#define CYDEV_CAN0_TX6_BASE 0x4000a080u\r
+#define CYDEV_CAN0_TX6_SIZE 0x00000010u\r
+#define CYDEV_CAN0_TX6_CMD 0x4000a080u\r
+#define CYDEV_CAN0_TX6_ID 0x4000a084u\r
+#define CYDEV_CAN0_TX6_DH 0x4000a088u\r
+#define CYDEV_CAN0_TX6_DL 0x4000a08cu\r
+#define CYDEV_CAN0_TX7_BASE 0x4000a090u\r
+#define CYDEV_CAN0_TX7_SIZE 0x00000010u\r
+#define CYDEV_CAN0_TX7_CMD 0x4000a090u\r
+#define CYDEV_CAN0_TX7_ID 0x4000a094u\r
+#define CYDEV_CAN0_TX7_DH 0x4000a098u\r
+#define CYDEV_CAN0_TX7_DL 0x4000a09cu\r
+#define CYDEV_CAN0_RX0_BASE 0x4000a0a0u\r
+#define CYDEV_CAN0_RX0_SIZE 0x00000020u\r
+#define CYDEV_CAN0_RX0_CMD 0x4000a0a0u\r
+#define CYDEV_CAN0_RX0_ID 0x4000a0a4u\r
+#define CYDEV_CAN0_RX0_DH 0x4000a0a8u\r
+#define CYDEV_CAN0_RX0_DL 0x4000a0acu\r
+#define CYDEV_CAN0_RX0_AMR 0x4000a0b0u\r
+#define CYDEV_CAN0_RX0_ACR 0x4000a0b4u\r
+#define CYDEV_CAN0_RX0_AMRD 0x4000a0b8u\r
+#define CYDEV_CAN0_RX0_ACRD 0x4000a0bcu\r
+#define CYDEV_CAN0_RX1_BASE 0x4000a0c0u\r
+#define CYDEV_CAN0_RX1_SIZE 0x00000020u\r
+#define CYDEV_CAN0_RX1_CMD 0x4000a0c0u\r
+#define CYDEV_CAN0_RX1_ID 0x4000a0c4u\r
+#define CYDEV_CAN0_RX1_DH 0x4000a0c8u\r
+#define CYDEV_CAN0_RX1_DL 0x4000a0ccu\r
+#define CYDEV_CAN0_RX1_AMR 0x4000a0d0u\r
+#define CYDEV_CAN0_RX1_ACR 0x4000a0d4u\r
+#define CYDEV_CAN0_RX1_AMRD 0x4000a0d8u\r
+#define CYDEV_CAN0_RX1_ACRD 0x4000a0dcu\r
+#define CYDEV_CAN0_RX2_BASE 0x4000a0e0u\r
+#define CYDEV_CAN0_RX2_SIZE 0x00000020u\r
+#define CYDEV_CAN0_RX2_CMD 0x4000a0e0u\r
+#define CYDEV_CAN0_RX2_ID 0x4000a0e4u\r
+#define CYDEV_CAN0_RX2_DH 0x4000a0e8u\r
+#define CYDEV_CAN0_RX2_DL 0x4000a0ecu\r
+#define CYDEV_CAN0_RX2_AMR 0x4000a0f0u\r
+#define CYDEV_CAN0_RX2_ACR 0x4000a0f4u\r
+#define CYDEV_CAN0_RX2_AMRD 0x4000a0f8u\r
+#define CYDEV_CAN0_RX2_ACRD 0x4000a0fcu\r
+#define CYDEV_CAN0_RX3_BASE 0x4000a100u\r
+#define CYDEV_CAN0_RX3_SIZE 0x00000020u\r
+#define CYDEV_CAN0_RX3_CMD 0x4000a100u\r
+#define CYDEV_CAN0_RX3_ID 0x4000a104u\r
+#define CYDEV_CAN0_RX3_DH 0x4000a108u\r
+#define CYDEV_CAN0_RX3_DL 0x4000a10cu\r
+#define CYDEV_CAN0_RX3_AMR 0x4000a110u\r
+#define CYDEV_CAN0_RX3_ACR 0x4000a114u\r
+#define CYDEV_CAN0_RX3_AMRD 0x4000a118u\r
+#define CYDEV_CAN0_RX3_ACRD 0x4000a11cu\r
+#define CYDEV_CAN0_RX4_BASE 0x4000a120u\r
+#define CYDEV_CAN0_RX4_SIZE 0x00000020u\r
+#define CYDEV_CAN0_RX4_CMD 0x4000a120u\r
+#define CYDEV_CAN0_RX4_ID 0x4000a124u\r
+#define CYDEV_CAN0_RX4_DH 0x4000a128u\r
+#define CYDEV_CAN0_RX4_DL 0x4000a12cu\r
+#define CYDEV_CAN0_RX4_AMR 0x4000a130u\r
+#define CYDEV_CAN0_RX4_ACR 0x4000a134u\r
+#define CYDEV_CAN0_RX4_AMRD 0x4000a138u\r
+#define CYDEV_CAN0_RX4_ACRD 0x4000a13cu\r
+#define CYDEV_CAN0_RX5_BASE 0x4000a140u\r
+#define CYDEV_CAN0_RX5_SIZE 0x00000020u\r
+#define CYDEV_CAN0_RX5_CMD 0x4000a140u\r
+#define CYDEV_CAN0_RX5_ID 0x4000a144u\r
+#define CYDEV_CAN0_RX5_DH 0x4000a148u\r
+#define CYDEV_CAN0_RX5_DL 0x4000a14cu\r
+#define CYDEV_CAN0_RX5_AMR 0x4000a150u\r
+#define CYDEV_CAN0_RX5_ACR 0x4000a154u\r
+#define CYDEV_CAN0_RX5_AMRD 0x4000a158u\r
+#define CYDEV_CAN0_RX5_ACRD 0x4000a15cu\r
+#define CYDEV_CAN0_RX6_BASE 0x4000a160u\r
+#define CYDEV_CAN0_RX6_SIZE 0x00000020u\r
+#define CYDEV_CAN0_RX6_CMD 0x4000a160u\r
+#define CYDEV_CAN0_RX6_ID 0x4000a164u\r
+#define CYDEV_CAN0_RX6_DH 0x4000a168u\r
+#define CYDEV_CAN0_RX6_DL 0x4000a16cu\r
+#define CYDEV_CAN0_RX6_AMR 0x4000a170u\r
+#define CYDEV_CAN0_RX6_ACR 0x4000a174u\r
+#define CYDEV_CAN0_RX6_AMRD 0x4000a178u\r
+#define CYDEV_CAN0_RX6_ACRD 0x4000a17cu\r
+#define CYDEV_CAN0_RX7_BASE 0x4000a180u\r
+#define CYDEV_CAN0_RX7_SIZE 0x00000020u\r
+#define CYDEV_CAN0_RX7_CMD 0x4000a180u\r
+#define CYDEV_CAN0_RX7_ID 0x4000a184u\r
+#define CYDEV_CAN0_RX7_DH 0x4000a188u\r
+#define CYDEV_CAN0_RX7_DL 0x4000a18cu\r
+#define CYDEV_CAN0_RX7_AMR 0x4000a190u\r
+#define CYDEV_CAN0_RX7_ACR 0x4000a194u\r
+#define CYDEV_CAN0_RX7_AMRD 0x4000a198u\r
+#define CYDEV_CAN0_RX7_ACRD 0x4000a19cu\r
+#define CYDEV_CAN0_RX8_BASE 0x4000a1a0u\r
+#define CYDEV_CAN0_RX8_SIZE 0x00000020u\r
+#define CYDEV_CAN0_RX8_CMD 0x4000a1a0u\r
+#define CYDEV_CAN0_RX8_ID 0x4000a1a4u\r
+#define CYDEV_CAN0_RX8_DH 0x4000a1a8u\r
+#define CYDEV_CAN0_RX8_DL 0x4000a1acu\r
+#define CYDEV_CAN0_RX8_AMR 0x4000a1b0u\r
+#define CYDEV_CAN0_RX8_ACR 0x4000a1b4u\r
+#define CYDEV_CAN0_RX8_AMRD 0x4000a1b8u\r
+#define CYDEV_CAN0_RX8_ACRD 0x4000a1bcu\r
+#define CYDEV_CAN0_RX9_BASE 0x4000a1c0u\r
+#define CYDEV_CAN0_RX9_SIZE 0x00000020u\r
+#define CYDEV_CAN0_RX9_CMD 0x4000a1c0u\r
+#define CYDEV_CAN0_RX9_ID 0x4000a1c4u\r
+#define CYDEV_CAN0_RX9_DH 0x4000a1c8u\r
+#define CYDEV_CAN0_RX9_DL 0x4000a1ccu\r
+#define CYDEV_CAN0_RX9_AMR 0x4000a1d0u\r
+#define CYDEV_CAN0_RX9_ACR 0x4000a1d4u\r
+#define CYDEV_CAN0_RX9_AMRD 0x4000a1d8u\r
+#define CYDEV_CAN0_RX9_ACRD 0x4000a1dcu\r
+#define CYDEV_CAN0_RX10_BASE 0x4000a1e0u\r
+#define CYDEV_CAN0_RX10_SIZE 0x00000020u\r
+#define CYDEV_CAN0_RX10_CMD 0x4000a1e0u\r
+#define CYDEV_CAN0_RX10_ID 0x4000a1e4u\r
+#define CYDEV_CAN0_RX10_DH 0x4000a1e8u\r
+#define CYDEV_CAN0_RX10_DL 0x4000a1ecu\r
+#define CYDEV_CAN0_RX10_AMR 0x4000a1f0u\r
+#define CYDEV_CAN0_RX10_ACR 0x4000a1f4u\r
+#define CYDEV_CAN0_RX10_AMRD 0x4000a1f8u\r
+#define CYDEV_CAN0_RX10_ACRD 0x4000a1fcu\r
+#define CYDEV_CAN0_RX11_BASE 0x4000a200u\r
+#define CYDEV_CAN0_RX11_SIZE 0x00000020u\r
+#define CYDEV_CAN0_RX11_CMD 0x4000a200u\r
+#define CYDEV_CAN0_RX11_ID 0x4000a204u\r
+#define CYDEV_CAN0_RX11_DH 0x4000a208u\r
+#define CYDEV_CAN0_RX11_DL 0x4000a20cu\r
+#define CYDEV_CAN0_RX11_AMR 0x4000a210u\r
+#define CYDEV_CAN0_RX11_ACR 0x4000a214u\r
+#define CYDEV_CAN0_RX11_AMRD 0x4000a218u\r
+#define CYDEV_CAN0_RX11_ACRD 0x4000a21cu\r
+#define CYDEV_CAN0_RX12_BASE 0x4000a220u\r
+#define CYDEV_CAN0_RX12_SIZE 0x00000020u\r
+#define CYDEV_CAN0_RX12_CMD 0x4000a220u\r
+#define CYDEV_CAN0_RX12_ID 0x4000a224u\r
+#define CYDEV_CAN0_RX12_DH 0x4000a228u\r
+#define CYDEV_CAN0_RX12_DL 0x4000a22cu\r
+#define CYDEV_CAN0_RX12_AMR 0x4000a230u\r
+#define CYDEV_CAN0_RX12_ACR 0x4000a234u\r
+#define CYDEV_CAN0_RX12_AMRD 0x4000a238u\r
+#define CYDEV_CAN0_RX12_ACRD 0x4000a23cu\r
+#define CYDEV_CAN0_RX13_BASE 0x4000a240u\r
+#define CYDEV_CAN0_RX13_SIZE 0x00000020u\r
+#define CYDEV_CAN0_RX13_CMD 0x4000a240u\r
+#define CYDEV_CAN0_RX13_ID 0x4000a244u\r
+#define CYDEV_CAN0_RX13_DH 0x4000a248u\r
+#define CYDEV_CAN0_RX13_DL 0x4000a24cu\r
+#define CYDEV_CAN0_RX13_AMR 0x4000a250u\r
+#define CYDEV_CAN0_RX13_ACR 0x4000a254u\r
+#define CYDEV_CAN0_RX13_AMRD 0x4000a258u\r
+#define CYDEV_CAN0_RX13_ACRD 0x4000a25cu\r
+#define CYDEV_CAN0_RX14_BASE 0x4000a260u\r
+#define CYDEV_CAN0_RX14_SIZE 0x00000020u\r
+#define CYDEV_CAN0_RX14_CMD 0x4000a260u\r
+#define CYDEV_CAN0_RX14_ID 0x4000a264u\r
+#define CYDEV_CAN0_RX14_DH 0x4000a268u\r
+#define CYDEV_CAN0_RX14_DL 0x4000a26cu\r
+#define CYDEV_CAN0_RX14_AMR 0x4000a270u\r
+#define CYDEV_CAN0_RX14_ACR 0x4000a274u\r
+#define CYDEV_CAN0_RX14_AMRD 0x4000a278u\r
+#define CYDEV_CAN0_RX14_ACRD 0x4000a27cu\r
+#define CYDEV_CAN0_RX15_BASE 0x4000a280u\r
+#define CYDEV_CAN0_RX15_SIZE 0x00000020u\r
+#define CYDEV_CAN0_RX15_CMD 0x4000a280u\r
+#define CYDEV_CAN0_RX15_ID 0x4000a284u\r
+#define CYDEV_CAN0_RX15_DH 0x4000a288u\r
+#define CYDEV_CAN0_RX15_DL 0x4000a28cu\r
+#define CYDEV_CAN0_RX15_AMR 0x4000a290u\r
+#define CYDEV_CAN0_RX15_ACR 0x4000a294u\r
+#define CYDEV_CAN0_RX15_AMRD 0x4000a298u\r
+#define CYDEV_CAN0_RX15_ACRD 0x4000a29cu\r
+#define CYDEV_DFB0_BASE 0x4000c000u\r
+#define CYDEV_DFB0_SIZE 0x000007b5u\r
+#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000u\r
+#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200u\r
+#define CYDEV_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000u\r
+#define CYDEV_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200u\r
+#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200u\r
+#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200u\r
+#define CYDEV_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200u\r
+#define CYDEV_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200u\r
+#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400u\r
+#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100u\r
+#define CYDEV_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400u\r
+#define CYDEV_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100u\r
+#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500u\r
+#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100u\r
+#define CYDEV_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500u\r
+#define CYDEV_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100u\r
+#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600u\r
+#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100u\r
+#define CYDEV_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600u\r
+#define CYDEV_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100u\r
+#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700u\r
+#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040u\r
+#define CYDEV_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700u\r
+#define CYDEV_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040u\r
+#define CYDEV_DFB0_CR 0x4000c780u\r
+#define CYDEV_DFB0_SR 0x4000c784u\r
+#define CYDEV_DFB0_RAM_EN 0x4000c788u\r
+#define CYDEV_DFB0_RAM_DIR 0x4000c78cu\r
+#define CYDEV_DFB0_SEMA 0x4000c790u\r
+#define CYDEV_DFB0_DSI_CTRL 0x4000c794u\r
+#define CYDEV_DFB0_INT_CTRL 0x4000c798u\r
+#define CYDEV_DFB0_DMA_CTRL 0x4000c79cu\r
+#define CYDEV_DFB0_STAGEA 0x4000c7a0u\r
+#define CYDEV_DFB0_STAGEAM 0x4000c7a1u\r
+#define CYDEV_DFB0_STAGEAH 0x4000c7a2u\r
+#define CYDEV_DFB0_STAGEB 0x4000c7a4u\r
+#define CYDEV_DFB0_STAGEBM 0x4000c7a5u\r
+#define CYDEV_DFB0_STAGEBH 0x4000c7a6u\r
+#define CYDEV_DFB0_HOLDA 0x4000c7a8u\r
+#define CYDEV_DFB0_HOLDAM 0x4000c7a9u\r
+#define CYDEV_DFB0_HOLDAH 0x4000c7aau\r
+#define CYDEV_DFB0_HOLDAS 0x4000c7abu\r
+#define CYDEV_DFB0_HOLDB 0x4000c7acu\r
+#define CYDEV_DFB0_HOLDBM 0x4000c7adu\r
+#define CYDEV_DFB0_HOLDBH 0x4000c7aeu\r
+#define CYDEV_DFB0_HOLDBS 0x4000c7afu\r
+#define CYDEV_DFB0_COHER 0x4000c7b0u\r
+#define CYDEV_DFB0_DALIGN 0x4000c7b4u\r
+#define CYDEV_UCFG_BASE 0x40010000u\r
+#define CYDEV_UCFG_SIZE 0x00005040u\r
+#define CYDEV_UCFG_B0_BASE 0x40010000u\r
+#define CYDEV_UCFG_B0_SIZE 0x00000fefu\r
+#define CYDEV_UCFG_B0_P0_BASE 0x40010000u\r
+#define CYDEV_UCFG_B0_P0_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000u\r
+#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT0 0x40010000u\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT1 0x40010004u\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT2 0x40010008u\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT3 0x4001000cu\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT4 0x40010010u\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT5 0x40010014u\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT6 0x40010018u\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT7 0x4001001cu\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT8 0x40010020u\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT9 0x40010024u\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT10 0x40010028u\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_IT11 0x4001002cu\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_ORT0 0x40010030u\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_ORT1 0x40010032u\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_ORT2 0x40010034u\r
+#define CYDEV_UCFG_B0_P0_U0_PLD_ORT3 0x40010036u\r
+#define CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038u\r
+#define CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB 0x4001003au\r
+#define CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003cu\r
+#define CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS 0x4001003eu\r
+#define CYDEV_UCFG_B0_P0_U0_CFG0 0x40010040u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG1 0x40010041u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG2 0x40010042u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG3 0x40010043u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG4 0x40010044u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG5 0x40010045u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG6 0x40010046u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG7 0x40010047u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG8 0x40010048u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG9 0x40010049u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG10 0x4001004au\r
+#define CYDEV_UCFG_B0_P0_U0_CFG11 0x4001004bu\r
+#define CYDEV_UCFG_B0_P0_U0_CFG12 0x4001004cu\r
+#define CYDEV_UCFG_B0_P0_U0_CFG13 0x4001004du\r
+#define CYDEV_UCFG_B0_P0_U0_CFG14 0x4001004eu\r
+#define CYDEV_UCFG_B0_P0_U0_CFG15 0x4001004fu\r
+#define CYDEV_UCFG_B0_P0_U0_CFG16 0x40010050u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG17 0x40010051u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG18 0x40010052u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG19 0x40010053u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG20 0x40010054u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG21 0x40010055u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG22 0x40010056u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG23 0x40010057u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG24 0x40010058u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG25 0x40010059u\r
+#define CYDEV_UCFG_B0_P0_U0_CFG26 0x4001005au\r
+#define CYDEV_UCFG_B0_P0_U0_CFG27 0x4001005bu\r
+#define CYDEV_UCFG_B0_P0_U0_CFG28 0x4001005cu\r
+#define CYDEV_UCFG_B0_P0_U0_CFG29 0x4001005du\r
+#define CYDEV_UCFG_B0_P0_U0_CFG30 0x4001005eu\r
+#define CYDEV_UCFG_B0_P0_U0_CFG31 0x4001005fu\r
+#define CYDEV_UCFG_B0_P0_U0_DCFG0 0x40010060u\r
+#define CYDEV_UCFG_B0_P0_U0_DCFG1 0x40010062u\r
+#define CYDEV_UCFG_B0_P0_U0_DCFG2 0x40010064u\r
+#define CYDEV_UCFG_B0_P0_U0_DCFG3 0x40010066u\r
+#define CYDEV_UCFG_B0_P0_U0_DCFG4 0x40010068u\r
+#define CYDEV_UCFG_B0_P0_U0_DCFG5 0x4001006au\r
+#define CYDEV_UCFG_B0_P0_U0_DCFG6 0x4001006cu\r
+#define CYDEV_UCFG_B0_P0_U0_DCFG7 0x4001006eu\r
+#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080u\r
+#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT0 0x40010080u\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT1 0x40010084u\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT2 0x40010088u\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT3 0x4001008cu\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT4 0x40010090u\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT5 0x40010094u\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT6 0x40010098u\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT7 0x4001009cu\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT8 0x400100a0u\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT9 0x400100a4u\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT10 0x400100a8u\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_IT11 0x400100acu\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_ORT0 0x400100b0u\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_ORT1 0x400100b2u\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_ORT2 0x400100b4u\r
+#define CYDEV_UCFG_B0_P0_U1_PLD_ORT3 0x400100b6u\r
+#define CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8u\r
+#define CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB 0x400100bau\r
+#define CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bcu\r
+#define CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS 0x400100beu\r
+#define CYDEV_UCFG_B0_P0_U1_CFG0 0x400100c0u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG1 0x400100c1u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG2 0x400100c2u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG3 0x400100c3u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG4 0x400100c4u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG5 0x400100c5u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG6 0x400100c6u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG7 0x400100c7u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG8 0x400100c8u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG9 0x400100c9u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG10 0x400100cau\r
+#define CYDEV_UCFG_B0_P0_U1_CFG11 0x400100cbu\r
+#define CYDEV_UCFG_B0_P0_U1_CFG12 0x400100ccu\r
+#define CYDEV_UCFG_B0_P0_U1_CFG13 0x400100cdu\r
+#define CYDEV_UCFG_B0_P0_U1_CFG14 0x400100ceu\r
+#define CYDEV_UCFG_B0_P0_U1_CFG15 0x400100cfu\r
+#define CYDEV_UCFG_B0_P0_U1_CFG16 0x400100d0u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG17 0x400100d1u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG18 0x400100d2u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG19 0x400100d3u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG20 0x400100d4u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG21 0x400100d5u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG22 0x400100d6u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG23 0x400100d7u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG24 0x400100d8u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG25 0x400100d9u\r
+#define CYDEV_UCFG_B0_P0_U1_CFG26 0x400100dau\r
+#define CYDEV_UCFG_B0_P0_U1_CFG27 0x400100dbu\r
+#define CYDEV_UCFG_B0_P0_U1_CFG28 0x400100dcu\r
+#define CYDEV_UCFG_B0_P0_U1_CFG29 0x400100ddu\r
+#define CYDEV_UCFG_B0_P0_U1_CFG30 0x400100deu\r
+#define CYDEV_UCFG_B0_P0_U1_CFG31 0x400100dfu\r
+#define CYDEV_UCFG_B0_P0_U1_DCFG0 0x400100e0u\r
+#define CYDEV_UCFG_B0_P0_U1_DCFG1 0x400100e2u\r
+#define CYDEV_UCFG_B0_P0_U1_DCFG2 0x400100e4u\r
+#define CYDEV_UCFG_B0_P0_U1_DCFG3 0x400100e6u\r
+#define CYDEV_UCFG_B0_P0_U1_DCFG4 0x400100e8u\r
+#define CYDEV_UCFG_B0_P0_U1_DCFG5 0x400100eau\r
+#define CYDEV_UCFG_B0_P0_U1_DCFG6 0x400100ecu\r
+#define CYDEV_UCFG_B0_P0_U1_DCFG7 0x400100eeu\r
+#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100u\r
+#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B0_P1_BASE 0x40010200u\r
+#define CYDEV_UCFG_B0_P1_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200u\r
+#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT0 0x40010200u\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT1 0x40010204u\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT2 0x40010208u\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT3 0x4001020cu\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT4 0x40010210u\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT5 0x40010214u\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT6 0x40010218u\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT7 0x4001021cu\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT8 0x40010220u\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT9 0x40010224u\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT10 0x40010228u\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_IT11 0x4001022cu\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_ORT0 0x40010230u\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_ORT1 0x40010232u\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_ORT2 0x40010234u\r
+#define CYDEV_UCFG_B0_P1_U0_PLD_ORT3 0x40010236u\r
+#define CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238u\r
+#define CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB 0x4001023au\r
+#define CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023cu\r
+#define CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS 0x4001023eu\r
+#define CYDEV_UCFG_B0_P1_U0_CFG0 0x40010240u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG1 0x40010241u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG2 0x40010242u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG3 0x40010243u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG4 0x40010244u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG5 0x40010245u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG6 0x40010246u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG7 0x40010247u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG8 0x40010248u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG9 0x40010249u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG10 0x4001024au\r
+#define CYDEV_UCFG_B0_P1_U0_CFG11 0x4001024bu\r
+#define CYDEV_UCFG_B0_P1_U0_CFG12 0x4001024cu\r
+#define CYDEV_UCFG_B0_P1_U0_CFG13 0x4001024du\r
+#define CYDEV_UCFG_B0_P1_U0_CFG14 0x4001024eu\r
+#define CYDEV_UCFG_B0_P1_U0_CFG15 0x4001024fu\r
+#define CYDEV_UCFG_B0_P1_U0_CFG16 0x40010250u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG17 0x40010251u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG18 0x40010252u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG19 0x40010253u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG20 0x40010254u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG21 0x40010255u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG22 0x40010256u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG23 0x40010257u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG24 0x40010258u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG25 0x40010259u\r
+#define CYDEV_UCFG_B0_P1_U0_CFG26 0x4001025au\r
+#define CYDEV_UCFG_B0_P1_U0_CFG27 0x4001025bu\r
+#define CYDEV_UCFG_B0_P1_U0_CFG28 0x4001025cu\r
+#define CYDEV_UCFG_B0_P1_U0_CFG29 0x4001025du\r
+#define CYDEV_UCFG_B0_P1_U0_CFG30 0x4001025eu\r
+#define CYDEV_UCFG_B0_P1_U0_CFG31 0x4001025fu\r
+#define CYDEV_UCFG_B0_P1_U0_DCFG0 0x40010260u\r
+#define CYDEV_UCFG_B0_P1_U0_DCFG1 0x40010262u\r
+#define CYDEV_UCFG_B0_P1_U0_DCFG2 0x40010264u\r
+#define CYDEV_UCFG_B0_P1_U0_DCFG3 0x40010266u\r
+#define CYDEV_UCFG_B0_P1_U0_DCFG4 0x40010268u\r
+#define CYDEV_UCFG_B0_P1_U0_DCFG5 0x4001026au\r
+#define CYDEV_UCFG_B0_P1_U0_DCFG6 0x4001026cu\r
+#define CYDEV_UCFG_B0_P1_U0_DCFG7 0x4001026eu\r
+#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280u\r
+#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT0 0x40010280u\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT1 0x40010284u\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT2 0x40010288u\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT3 0x4001028cu\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT4 0x40010290u\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT5 0x40010294u\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT6 0x40010298u\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT7 0x4001029cu\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT8 0x400102a0u\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT9 0x400102a4u\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT10 0x400102a8u\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_IT11 0x400102acu\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_ORT0 0x400102b0u\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_ORT1 0x400102b2u\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_ORT2 0x400102b4u\r
+#define CYDEV_UCFG_B0_P1_U1_PLD_ORT3 0x400102b6u\r
+#define CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8u\r
+#define CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB 0x400102bau\r
+#define CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bcu\r
+#define CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS 0x400102beu\r
+#define CYDEV_UCFG_B0_P1_U1_CFG0 0x400102c0u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG1 0x400102c1u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG2 0x400102c2u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG3 0x400102c3u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG4 0x400102c4u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG5 0x400102c5u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG6 0x400102c6u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG7 0x400102c7u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG8 0x400102c8u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG9 0x400102c9u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG10 0x400102cau\r
+#define CYDEV_UCFG_B0_P1_U1_CFG11 0x400102cbu\r
+#define CYDEV_UCFG_B0_P1_U1_CFG12 0x400102ccu\r
+#define CYDEV_UCFG_B0_P1_U1_CFG13 0x400102cdu\r
+#define CYDEV_UCFG_B0_P1_U1_CFG14 0x400102ceu\r
+#define CYDEV_UCFG_B0_P1_U1_CFG15 0x400102cfu\r
+#define CYDEV_UCFG_B0_P1_U1_CFG16 0x400102d0u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG17 0x400102d1u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG18 0x400102d2u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG19 0x400102d3u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG20 0x400102d4u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG21 0x400102d5u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG22 0x400102d6u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG23 0x400102d7u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG24 0x400102d8u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG25 0x400102d9u\r
+#define CYDEV_UCFG_B0_P1_U1_CFG26 0x400102dau\r
+#define CYDEV_UCFG_B0_P1_U1_CFG27 0x400102dbu\r
+#define CYDEV_UCFG_B0_P1_U1_CFG28 0x400102dcu\r
+#define CYDEV_UCFG_B0_P1_U1_CFG29 0x400102ddu\r
+#define CYDEV_UCFG_B0_P1_U1_CFG30 0x400102deu\r
+#define CYDEV_UCFG_B0_P1_U1_CFG31 0x400102dfu\r
+#define CYDEV_UCFG_B0_P1_U1_DCFG0 0x400102e0u\r
+#define CYDEV_UCFG_B0_P1_U1_DCFG1 0x400102e2u\r
+#define CYDEV_UCFG_B0_P1_U1_DCFG2 0x400102e4u\r
+#define CYDEV_UCFG_B0_P1_U1_DCFG3 0x400102e6u\r
+#define CYDEV_UCFG_B0_P1_U1_DCFG4 0x400102e8u\r
+#define CYDEV_UCFG_B0_P1_U1_DCFG5 0x400102eau\r
+#define CYDEV_UCFG_B0_P1_U1_DCFG6 0x400102ecu\r
+#define CYDEV_UCFG_B0_P1_U1_DCFG7 0x400102eeu\r
+#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300u\r
+#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B0_P2_BASE 0x40010400u\r
+#define CYDEV_UCFG_B0_P2_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400u\r
+#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT0 0x40010400u\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT1 0x40010404u\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT2 0x40010408u\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT3 0x4001040cu\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT4 0x40010410u\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT5 0x40010414u\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT6 0x40010418u\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT7 0x4001041cu\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT8 0x40010420u\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT9 0x40010424u\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT10 0x40010428u\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_IT11 0x4001042cu\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_ORT0 0x40010430u\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_ORT1 0x40010432u\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_ORT2 0x40010434u\r
+#define CYDEV_UCFG_B0_P2_U0_PLD_ORT3 0x40010436u\r
+#define CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438u\r
+#define CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB 0x4001043au\r
+#define CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043cu\r
+#define CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS 0x4001043eu\r
+#define CYDEV_UCFG_B0_P2_U0_CFG0 0x40010440u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG1 0x40010441u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG2 0x40010442u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG3 0x40010443u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG4 0x40010444u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG5 0x40010445u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG6 0x40010446u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG7 0x40010447u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG8 0x40010448u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG9 0x40010449u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG10 0x4001044au\r
+#define CYDEV_UCFG_B0_P2_U0_CFG11 0x4001044bu\r
+#define CYDEV_UCFG_B0_P2_U0_CFG12 0x4001044cu\r
+#define CYDEV_UCFG_B0_P2_U0_CFG13 0x4001044du\r
+#define CYDEV_UCFG_B0_P2_U0_CFG14 0x4001044eu\r
+#define CYDEV_UCFG_B0_P2_U0_CFG15 0x4001044fu\r
+#define CYDEV_UCFG_B0_P2_U0_CFG16 0x40010450u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG17 0x40010451u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG18 0x40010452u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG19 0x40010453u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG20 0x40010454u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG21 0x40010455u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG22 0x40010456u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG23 0x40010457u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG24 0x40010458u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG25 0x40010459u\r
+#define CYDEV_UCFG_B0_P2_U0_CFG26 0x4001045au\r
+#define CYDEV_UCFG_B0_P2_U0_CFG27 0x4001045bu\r
+#define CYDEV_UCFG_B0_P2_U0_CFG28 0x4001045cu\r
+#define CYDEV_UCFG_B0_P2_U0_CFG29 0x4001045du\r
+#define CYDEV_UCFG_B0_P2_U0_CFG30 0x4001045eu\r
+#define CYDEV_UCFG_B0_P2_U0_CFG31 0x4001045fu\r
+#define CYDEV_UCFG_B0_P2_U0_DCFG0 0x40010460u\r
+#define CYDEV_UCFG_B0_P2_U0_DCFG1 0x40010462u\r
+#define CYDEV_UCFG_B0_P2_U0_DCFG2 0x40010464u\r
+#define CYDEV_UCFG_B0_P2_U0_DCFG3 0x40010466u\r
+#define CYDEV_UCFG_B0_P2_U0_DCFG4 0x40010468u\r
+#define CYDEV_UCFG_B0_P2_U0_DCFG5 0x4001046au\r
+#define CYDEV_UCFG_B0_P2_U0_DCFG6 0x4001046cu\r
+#define CYDEV_UCFG_B0_P2_U0_DCFG7 0x4001046eu\r
+#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480u\r
+#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT0 0x40010480u\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT1 0x40010484u\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT2 0x40010488u\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT3 0x4001048cu\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT4 0x40010490u\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT5 0x40010494u\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT6 0x40010498u\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT7 0x4001049cu\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT8 0x400104a0u\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT9 0x400104a4u\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT10 0x400104a8u\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_IT11 0x400104acu\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_ORT0 0x400104b0u\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_ORT1 0x400104b2u\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_ORT2 0x400104b4u\r
+#define CYDEV_UCFG_B0_P2_U1_PLD_ORT3 0x400104b6u\r
+#define CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8u\r
+#define CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB 0x400104bau\r
+#define CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bcu\r
+#define CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS 0x400104beu\r
+#define CYDEV_UCFG_B0_P2_U1_CFG0 0x400104c0u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG1 0x400104c1u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG2 0x400104c2u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG3 0x400104c3u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG4 0x400104c4u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG5 0x400104c5u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG6 0x400104c6u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG7 0x400104c7u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG8 0x400104c8u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG9 0x400104c9u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG10 0x400104cau\r
+#define CYDEV_UCFG_B0_P2_U1_CFG11 0x400104cbu\r
+#define CYDEV_UCFG_B0_P2_U1_CFG12 0x400104ccu\r
+#define CYDEV_UCFG_B0_P2_U1_CFG13 0x400104cdu\r
+#define CYDEV_UCFG_B0_P2_U1_CFG14 0x400104ceu\r
+#define CYDEV_UCFG_B0_P2_U1_CFG15 0x400104cfu\r
+#define CYDEV_UCFG_B0_P2_U1_CFG16 0x400104d0u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG17 0x400104d1u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG18 0x400104d2u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG19 0x400104d3u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG20 0x400104d4u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG21 0x400104d5u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG22 0x400104d6u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG23 0x400104d7u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG24 0x400104d8u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG25 0x400104d9u\r
+#define CYDEV_UCFG_B0_P2_U1_CFG26 0x400104dau\r
+#define CYDEV_UCFG_B0_P2_U1_CFG27 0x400104dbu\r
+#define CYDEV_UCFG_B0_P2_U1_CFG28 0x400104dcu\r
+#define CYDEV_UCFG_B0_P2_U1_CFG29 0x400104ddu\r
+#define CYDEV_UCFG_B0_P2_U1_CFG30 0x400104deu\r
+#define CYDEV_UCFG_B0_P2_U1_CFG31 0x400104dfu\r
+#define CYDEV_UCFG_B0_P2_U1_DCFG0 0x400104e0u\r
+#define CYDEV_UCFG_B0_P2_U1_DCFG1 0x400104e2u\r
+#define CYDEV_UCFG_B0_P2_U1_DCFG2 0x400104e4u\r
+#define CYDEV_UCFG_B0_P2_U1_DCFG3 0x400104e6u\r
+#define CYDEV_UCFG_B0_P2_U1_DCFG4 0x400104e8u\r
+#define CYDEV_UCFG_B0_P2_U1_DCFG5 0x400104eau\r
+#define CYDEV_UCFG_B0_P2_U1_DCFG6 0x400104ecu\r
+#define CYDEV_UCFG_B0_P2_U1_DCFG7 0x400104eeu\r
+#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500u\r
+#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B0_P3_BASE 0x40010600u\r
+#define CYDEV_UCFG_B0_P3_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600u\r
+#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT0 0x40010600u\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT1 0x40010604u\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT2 0x40010608u\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT3 0x4001060cu\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT4 0x40010610u\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT5 0x40010614u\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT6 0x40010618u\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT7 0x4001061cu\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT8 0x40010620u\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT9 0x40010624u\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT10 0x40010628u\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_IT11 0x4001062cu\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_ORT0 0x40010630u\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_ORT1 0x40010632u\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_ORT2 0x40010634u\r
+#define CYDEV_UCFG_B0_P3_U0_PLD_ORT3 0x40010636u\r
+#define CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638u\r
+#define CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB 0x4001063au\r
+#define CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063cu\r
+#define CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS 0x4001063eu\r
+#define CYDEV_UCFG_B0_P3_U0_CFG0 0x40010640u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG1 0x40010641u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG2 0x40010642u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG3 0x40010643u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG4 0x40010644u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG5 0x40010645u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG6 0x40010646u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG7 0x40010647u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG8 0x40010648u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG9 0x40010649u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG10 0x4001064au\r
+#define CYDEV_UCFG_B0_P3_U0_CFG11 0x4001064bu\r
+#define CYDEV_UCFG_B0_P3_U0_CFG12 0x4001064cu\r
+#define CYDEV_UCFG_B0_P3_U0_CFG13 0x4001064du\r
+#define CYDEV_UCFG_B0_P3_U0_CFG14 0x4001064eu\r
+#define CYDEV_UCFG_B0_P3_U0_CFG15 0x4001064fu\r
+#define CYDEV_UCFG_B0_P3_U0_CFG16 0x40010650u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG17 0x40010651u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG18 0x40010652u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG19 0x40010653u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG20 0x40010654u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG21 0x40010655u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG22 0x40010656u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG23 0x40010657u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG24 0x40010658u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG25 0x40010659u\r
+#define CYDEV_UCFG_B0_P3_U0_CFG26 0x4001065au\r
+#define CYDEV_UCFG_B0_P3_U0_CFG27 0x4001065bu\r
+#define CYDEV_UCFG_B0_P3_U0_CFG28 0x4001065cu\r
+#define CYDEV_UCFG_B0_P3_U0_CFG29 0x4001065du\r
+#define CYDEV_UCFG_B0_P3_U0_CFG30 0x4001065eu\r
+#define CYDEV_UCFG_B0_P3_U0_CFG31 0x4001065fu\r
+#define CYDEV_UCFG_B0_P3_U0_DCFG0 0x40010660u\r
+#define CYDEV_UCFG_B0_P3_U0_DCFG1 0x40010662u\r
+#define CYDEV_UCFG_B0_P3_U0_DCFG2 0x40010664u\r
+#define CYDEV_UCFG_B0_P3_U0_DCFG3 0x40010666u\r
+#define CYDEV_UCFG_B0_P3_U0_DCFG4 0x40010668u\r
+#define CYDEV_UCFG_B0_P3_U0_DCFG5 0x4001066au\r
+#define CYDEV_UCFG_B0_P3_U0_DCFG6 0x4001066cu\r
+#define CYDEV_UCFG_B0_P3_U0_DCFG7 0x4001066eu\r
+#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680u\r
+#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT0 0x40010680u\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT1 0x40010684u\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT2 0x40010688u\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT3 0x4001068cu\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT4 0x40010690u\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT5 0x40010694u\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT6 0x40010698u\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT7 0x4001069cu\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT8 0x400106a0u\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT9 0x400106a4u\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT10 0x400106a8u\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_IT11 0x400106acu\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_ORT0 0x400106b0u\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_ORT1 0x400106b2u\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_ORT2 0x400106b4u\r
+#define CYDEV_UCFG_B0_P3_U1_PLD_ORT3 0x400106b6u\r
+#define CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8u\r
+#define CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB 0x400106bau\r
+#define CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bcu\r
+#define CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS 0x400106beu\r
+#define CYDEV_UCFG_B0_P3_U1_CFG0 0x400106c0u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG1 0x400106c1u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG2 0x400106c2u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG3 0x400106c3u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG4 0x400106c4u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG5 0x400106c5u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG6 0x400106c6u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG7 0x400106c7u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG8 0x400106c8u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG9 0x400106c9u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG10 0x400106cau\r
+#define CYDEV_UCFG_B0_P3_U1_CFG11 0x400106cbu\r
+#define CYDEV_UCFG_B0_P3_U1_CFG12 0x400106ccu\r
+#define CYDEV_UCFG_B0_P3_U1_CFG13 0x400106cdu\r
+#define CYDEV_UCFG_B0_P3_U1_CFG14 0x400106ceu\r
+#define CYDEV_UCFG_B0_P3_U1_CFG15 0x400106cfu\r
+#define CYDEV_UCFG_B0_P3_U1_CFG16 0x400106d0u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG17 0x400106d1u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG18 0x400106d2u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG19 0x400106d3u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG20 0x400106d4u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG21 0x400106d5u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG22 0x400106d6u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG23 0x400106d7u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG24 0x400106d8u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG25 0x400106d9u\r
+#define CYDEV_UCFG_B0_P3_U1_CFG26 0x400106dau\r
+#define CYDEV_UCFG_B0_P3_U1_CFG27 0x400106dbu\r
+#define CYDEV_UCFG_B0_P3_U1_CFG28 0x400106dcu\r
+#define CYDEV_UCFG_B0_P3_U1_CFG29 0x400106ddu\r
+#define CYDEV_UCFG_B0_P3_U1_CFG30 0x400106deu\r
+#define CYDEV_UCFG_B0_P3_U1_CFG31 0x400106dfu\r
+#define CYDEV_UCFG_B0_P3_U1_DCFG0 0x400106e0u\r
+#define CYDEV_UCFG_B0_P3_U1_DCFG1 0x400106e2u\r
+#define CYDEV_UCFG_B0_P3_U1_DCFG2 0x400106e4u\r
+#define CYDEV_UCFG_B0_P3_U1_DCFG3 0x400106e6u\r
+#define CYDEV_UCFG_B0_P3_U1_DCFG4 0x400106e8u\r
+#define CYDEV_UCFG_B0_P3_U1_DCFG5 0x400106eau\r
+#define CYDEV_UCFG_B0_P3_U1_DCFG6 0x400106ecu\r
+#define CYDEV_UCFG_B0_P3_U1_DCFG7 0x400106eeu\r
+#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700u\r
+#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B0_P4_BASE 0x40010800u\r
+#define CYDEV_UCFG_B0_P4_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800u\r
+#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT0 0x40010800u\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT1 0x40010804u\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT2 0x40010808u\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT3 0x4001080cu\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT4 0x40010810u\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT5 0x40010814u\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT6 0x40010818u\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT7 0x4001081cu\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT8 0x40010820u\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT9 0x40010824u\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT10 0x40010828u\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_IT11 0x4001082cu\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_ORT0 0x40010830u\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_ORT1 0x40010832u\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_ORT2 0x40010834u\r
+#define CYDEV_UCFG_B0_P4_U0_PLD_ORT3 0x40010836u\r
+#define CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838u\r
+#define CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB 0x4001083au\r
+#define CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083cu\r
+#define CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS 0x4001083eu\r
+#define CYDEV_UCFG_B0_P4_U0_CFG0 0x40010840u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG1 0x40010841u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG2 0x40010842u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG3 0x40010843u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG4 0x40010844u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG5 0x40010845u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG6 0x40010846u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG7 0x40010847u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG8 0x40010848u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG9 0x40010849u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG10 0x4001084au\r
+#define CYDEV_UCFG_B0_P4_U0_CFG11 0x4001084bu\r
+#define CYDEV_UCFG_B0_P4_U0_CFG12 0x4001084cu\r
+#define CYDEV_UCFG_B0_P4_U0_CFG13 0x4001084du\r
+#define CYDEV_UCFG_B0_P4_U0_CFG14 0x4001084eu\r
+#define CYDEV_UCFG_B0_P4_U0_CFG15 0x4001084fu\r
+#define CYDEV_UCFG_B0_P4_U0_CFG16 0x40010850u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG17 0x40010851u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG18 0x40010852u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG19 0x40010853u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG20 0x40010854u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG21 0x40010855u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG22 0x40010856u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG23 0x40010857u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG24 0x40010858u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG25 0x40010859u\r
+#define CYDEV_UCFG_B0_P4_U0_CFG26 0x4001085au\r
+#define CYDEV_UCFG_B0_P4_U0_CFG27 0x4001085bu\r
+#define CYDEV_UCFG_B0_P4_U0_CFG28 0x4001085cu\r
+#define CYDEV_UCFG_B0_P4_U0_CFG29 0x4001085du\r
+#define CYDEV_UCFG_B0_P4_U0_CFG30 0x4001085eu\r
+#define CYDEV_UCFG_B0_P4_U0_CFG31 0x4001085fu\r
+#define CYDEV_UCFG_B0_P4_U0_DCFG0 0x40010860u\r
+#define CYDEV_UCFG_B0_P4_U0_DCFG1 0x40010862u\r
+#define CYDEV_UCFG_B0_P4_U0_DCFG2 0x40010864u\r
+#define CYDEV_UCFG_B0_P4_U0_DCFG3 0x40010866u\r
+#define CYDEV_UCFG_B0_P4_U0_DCFG4 0x40010868u\r
+#define CYDEV_UCFG_B0_P4_U0_DCFG5 0x4001086au\r
+#define CYDEV_UCFG_B0_P4_U0_DCFG6 0x4001086cu\r
+#define CYDEV_UCFG_B0_P4_U0_DCFG7 0x4001086eu\r
+#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880u\r
+#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT0 0x40010880u\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT1 0x40010884u\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT2 0x40010888u\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT3 0x4001088cu\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT4 0x40010890u\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT5 0x40010894u\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT6 0x40010898u\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT7 0x4001089cu\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT8 0x400108a0u\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT9 0x400108a4u\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT10 0x400108a8u\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_IT11 0x400108acu\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_ORT0 0x400108b0u\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_ORT1 0x400108b2u\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_ORT2 0x400108b4u\r
+#define CYDEV_UCFG_B0_P4_U1_PLD_ORT3 0x400108b6u\r
+#define CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8u\r
+#define CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB 0x400108bau\r
+#define CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bcu\r
+#define CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS 0x400108beu\r
+#define CYDEV_UCFG_B0_P4_U1_CFG0 0x400108c0u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG1 0x400108c1u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG2 0x400108c2u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG3 0x400108c3u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG4 0x400108c4u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG5 0x400108c5u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG6 0x400108c6u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG7 0x400108c7u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG8 0x400108c8u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG9 0x400108c9u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG10 0x400108cau\r
+#define CYDEV_UCFG_B0_P4_U1_CFG11 0x400108cbu\r
+#define CYDEV_UCFG_B0_P4_U1_CFG12 0x400108ccu\r
+#define CYDEV_UCFG_B0_P4_U1_CFG13 0x400108cdu\r
+#define CYDEV_UCFG_B0_P4_U1_CFG14 0x400108ceu\r
+#define CYDEV_UCFG_B0_P4_U1_CFG15 0x400108cfu\r
+#define CYDEV_UCFG_B0_P4_U1_CFG16 0x400108d0u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG17 0x400108d1u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG18 0x400108d2u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG19 0x400108d3u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG20 0x400108d4u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG21 0x400108d5u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG22 0x400108d6u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG23 0x400108d7u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG24 0x400108d8u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG25 0x400108d9u\r
+#define CYDEV_UCFG_B0_P4_U1_CFG26 0x400108dau\r
+#define CYDEV_UCFG_B0_P4_U1_CFG27 0x400108dbu\r
+#define CYDEV_UCFG_B0_P4_U1_CFG28 0x400108dcu\r
+#define CYDEV_UCFG_B0_P4_U1_CFG29 0x400108ddu\r
+#define CYDEV_UCFG_B0_P4_U1_CFG30 0x400108deu\r
+#define CYDEV_UCFG_B0_P4_U1_CFG31 0x400108dfu\r
+#define CYDEV_UCFG_B0_P4_U1_DCFG0 0x400108e0u\r
+#define CYDEV_UCFG_B0_P4_U1_DCFG1 0x400108e2u\r
+#define CYDEV_UCFG_B0_P4_U1_DCFG2 0x400108e4u\r
+#define CYDEV_UCFG_B0_P4_U1_DCFG3 0x400108e6u\r
+#define CYDEV_UCFG_B0_P4_U1_DCFG4 0x400108e8u\r
+#define CYDEV_UCFG_B0_P4_U1_DCFG5 0x400108eau\r
+#define CYDEV_UCFG_B0_P4_U1_DCFG6 0x400108ecu\r
+#define CYDEV_UCFG_B0_P4_U1_DCFG7 0x400108eeu\r
+#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900u\r
+#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B0_P5_BASE 0x40010a00u\r
+#define CYDEV_UCFG_B0_P5_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00u\r
+#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT0 0x40010a00u\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT1 0x40010a04u\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT2 0x40010a08u\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT3 0x40010a0cu\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT4 0x40010a10u\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT5 0x40010a14u\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT6 0x40010a18u\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT7 0x40010a1cu\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT8 0x40010a20u\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT9 0x40010a24u\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT10 0x40010a28u\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_IT11 0x40010a2cu\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_ORT0 0x40010a30u\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_ORT1 0x40010a32u\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_ORT2 0x40010a34u\r
+#define CYDEV_UCFG_B0_P5_U0_PLD_ORT3 0x40010a36u\r
+#define CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38u\r
+#define CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB 0x40010a3au\r
+#define CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3cu\r
+#define CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3eu\r
+#define CYDEV_UCFG_B0_P5_U0_CFG0 0x40010a40u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG1 0x40010a41u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG2 0x40010a42u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG3 0x40010a43u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG4 0x40010a44u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG5 0x40010a45u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG6 0x40010a46u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG7 0x40010a47u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG8 0x40010a48u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG9 0x40010a49u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG10 0x40010a4au\r
+#define CYDEV_UCFG_B0_P5_U0_CFG11 0x40010a4bu\r
+#define CYDEV_UCFG_B0_P5_U0_CFG12 0x40010a4cu\r
+#define CYDEV_UCFG_B0_P5_U0_CFG13 0x40010a4du\r
+#define CYDEV_UCFG_B0_P5_U0_CFG14 0x40010a4eu\r
+#define CYDEV_UCFG_B0_P5_U0_CFG15 0x40010a4fu\r
+#define CYDEV_UCFG_B0_P5_U0_CFG16 0x40010a50u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG17 0x40010a51u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG18 0x40010a52u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG19 0x40010a53u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG20 0x40010a54u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG21 0x40010a55u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG22 0x40010a56u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG23 0x40010a57u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG24 0x40010a58u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG25 0x40010a59u\r
+#define CYDEV_UCFG_B0_P5_U0_CFG26 0x40010a5au\r
+#define CYDEV_UCFG_B0_P5_U0_CFG27 0x40010a5bu\r
+#define CYDEV_UCFG_B0_P5_U0_CFG28 0x40010a5cu\r
+#define CYDEV_UCFG_B0_P5_U0_CFG29 0x40010a5du\r
+#define CYDEV_UCFG_B0_P5_U0_CFG30 0x40010a5eu\r
+#define CYDEV_UCFG_B0_P5_U0_CFG31 0x40010a5fu\r
+#define CYDEV_UCFG_B0_P5_U0_DCFG0 0x40010a60u\r
+#define CYDEV_UCFG_B0_P5_U0_DCFG1 0x40010a62u\r
+#define CYDEV_UCFG_B0_P5_U0_DCFG2 0x40010a64u\r
+#define CYDEV_UCFG_B0_P5_U0_DCFG3 0x40010a66u\r
+#define CYDEV_UCFG_B0_P5_U0_DCFG4 0x40010a68u\r
+#define CYDEV_UCFG_B0_P5_U0_DCFG5 0x40010a6au\r
+#define CYDEV_UCFG_B0_P5_U0_DCFG6 0x40010a6cu\r
+#define CYDEV_UCFG_B0_P5_U0_DCFG7 0x40010a6eu\r
+#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80u\r
+#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT0 0x40010a80u\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT1 0x40010a84u\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT2 0x40010a88u\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT3 0x40010a8cu\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT4 0x40010a90u\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT5 0x40010a94u\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT6 0x40010a98u\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT7 0x40010a9cu\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT8 0x40010aa0u\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT9 0x40010aa4u\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT10 0x40010aa8u\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_IT11 0x40010aacu\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_ORT0 0x40010ab0u\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_ORT1 0x40010ab2u\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_ORT2 0x40010ab4u\r
+#define CYDEV_UCFG_B0_P5_U1_PLD_ORT3 0x40010ab6u\r
+#define CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8u\r
+#define CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB 0x40010abau\r
+#define CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abcu\r
+#define CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS 0x40010abeu\r
+#define CYDEV_UCFG_B0_P5_U1_CFG0 0x40010ac0u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG1 0x40010ac1u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG2 0x40010ac2u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG3 0x40010ac3u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG4 0x40010ac4u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG5 0x40010ac5u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG6 0x40010ac6u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG7 0x40010ac7u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG8 0x40010ac8u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG9 0x40010ac9u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG10 0x40010acau\r
+#define CYDEV_UCFG_B0_P5_U1_CFG11 0x40010acbu\r
+#define CYDEV_UCFG_B0_P5_U1_CFG12 0x40010accu\r
+#define CYDEV_UCFG_B0_P5_U1_CFG13 0x40010acdu\r
+#define CYDEV_UCFG_B0_P5_U1_CFG14 0x40010aceu\r
+#define CYDEV_UCFG_B0_P5_U1_CFG15 0x40010acfu\r
+#define CYDEV_UCFG_B0_P5_U1_CFG16 0x40010ad0u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG17 0x40010ad1u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG18 0x40010ad2u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG19 0x40010ad3u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG20 0x40010ad4u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG21 0x40010ad5u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG22 0x40010ad6u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG23 0x40010ad7u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG24 0x40010ad8u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG25 0x40010ad9u\r
+#define CYDEV_UCFG_B0_P5_U1_CFG26 0x40010adau\r
+#define CYDEV_UCFG_B0_P5_U1_CFG27 0x40010adbu\r
+#define CYDEV_UCFG_B0_P5_U1_CFG28 0x40010adcu\r
+#define CYDEV_UCFG_B0_P5_U1_CFG29 0x40010addu\r
+#define CYDEV_UCFG_B0_P5_U1_CFG30 0x40010adeu\r
+#define CYDEV_UCFG_B0_P5_U1_CFG31 0x40010adfu\r
+#define CYDEV_UCFG_B0_P5_U1_DCFG0 0x40010ae0u\r
+#define CYDEV_UCFG_B0_P5_U1_DCFG1 0x40010ae2u\r
+#define CYDEV_UCFG_B0_P5_U1_DCFG2 0x40010ae4u\r
+#define CYDEV_UCFG_B0_P5_U1_DCFG3 0x40010ae6u\r
+#define CYDEV_UCFG_B0_P5_U1_DCFG4 0x40010ae8u\r
+#define CYDEV_UCFG_B0_P5_U1_DCFG5 0x40010aeau\r
+#define CYDEV_UCFG_B0_P5_U1_DCFG6 0x40010aecu\r
+#define CYDEV_UCFG_B0_P5_U1_DCFG7 0x40010aeeu\r
+#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00u\r
+#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B0_P6_BASE 0x40010c00u\r
+#define CYDEV_UCFG_B0_P6_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00u\r
+#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT0 0x40010c00u\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT1 0x40010c04u\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT2 0x40010c08u\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT3 0x40010c0cu\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT4 0x40010c10u\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT5 0x40010c14u\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT6 0x40010c18u\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT7 0x40010c1cu\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT8 0x40010c20u\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT9 0x40010c24u\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT10 0x40010c28u\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_IT11 0x40010c2cu\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_ORT0 0x40010c30u\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_ORT1 0x40010c32u\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_ORT2 0x40010c34u\r
+#define CYDEV_UCFG_B0_P6_U0_PLD_ORT3 0x40010c36u\r
+#define CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38u\r
+#define CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB 0x40010c3au\r
+#define CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3cu\r
+#define CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3eu\r
+#define CYDEV_UCFG_B0_P6_U0_CFG0 0x40010c40u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG1 0x40010c41u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG2 0x40010c42u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG3 0x40010c43u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG4 0x40010c44u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG5 0x40010c45u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG6 0x40010c46u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG7 0x40010c47u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG8 0x40010c48u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG9 0x40010c49u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG10 0x40010c4au\r
+#define CYDEV_UCFG_B0_P6_U0_CFG11 0x40010c4bu\r
+#define CYDEV_UCFG_B0_P6_U0_CFG12 0x40010c4cu\r
+#define CYDEV_UCFG_B0_P6_U0_CFG13 0x40010c4du\r
+#define CYDEV_UCFG_B0_P6_U0_CFG14 0x40010c4eu\r
+#define CYDEV_UCFG_B0_P6_U0_CFG15 0x40010c4fu\r
+#define CYDEV_UCFG_B0_P6_U0_CFG16 0x40010c50u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG17 0x40010c51u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG18 0x40010c52u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG19 0x40010c53u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG20 0x40010c54u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG21 0x40010c55u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG22 0x40010c56u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG23 0x40010c57u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG24 0x40010c58u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG25 0x40010c59u\r
+#define CYDEV_UCFG_B0_P6_U0_CFG26 0x40010c5au\r
+#define CYDEV_UCFG_B0_P6_U0_CFG27 0x40010c5bu\r
+#define CYDEV_UCFG_B0_P6_U0_CFG28 0x40010c5cu\r
+#define CYDEV_UCFG_B0_P6_U0_CFG29 0x40010c5du\r
+#define CYDEV_UCFG_B0_P6_U0_CFG30 0x40010c5eu\r
+#define CYDEV_UCFG_B0_P6_U0_CFG31 0x40010c5fu\r
+#define CYDEV_UCFG_B0_P6_U0_DCFG0 0x40010c60u\r
+#define CYDEV_UCFG_B0_P6_U0_DCFG1 0x40010c62u\r
+#define CYDEV_UCFG_B0_P6_U0_DCFG2 0x40010c64u\r
+#define CYDEV_UCFG_B0_P6_U0_DCFG3 0x40010c66u\r
+#define CYDEV_UCFG_B0_P6_U0_DCFG4 0x40010c68u\r
+#define CYDEV_UCFG_B0_P6_U0_DCFG5 0x40010c6au\r
+#define CYDEV_UCFG_B0_P6_U0_DCFG6 0x40010c6cu\r
+#define CYDEV_UCFG_B0_P6_U0_DCFG7 0x40010c6eu\r
+#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80u\r
+#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT0 0x40010c80u\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT1 0x40010c84u\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT2 0x40010c88u\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT3 0x40010c8cu\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT4 0x40010c90u\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT5 0x40010c94u\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT6 0x40010c98u\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT7 0x40010c9cu\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT8 0x40010ca0u\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT9 0x40010ca4u\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT10 0x40010ca8u\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_IT11 0x40010cacu\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_ORT0 0x40010cb0u\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_ORT1 0x40010cb2u\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_ORT2 0x40010cb4u\r
+#define CYDEV_UCFG_B0_P6_U1_PLD_ORT3 0x40010cb6u\r
+#define CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8u\r
+#define CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB 0x40010cbau\r
+#define CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbcu\r
+#define CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbeu\r
+#define CYDEV_UCFG_B0_P6_U1_CFG0 0x40010cc0u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG1 0x40010cc1u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG2 0x40010cc2u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG3 0x40010cc3u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG4 0x40010cc4u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG5 0x40010cc5u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG6 0x40010cc6u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG7 0x40010cc7u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG8 0x40010cc8u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG9 0x40010cc9u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG10 0x40010ccau\r
+#define CYDEV_UCFG_B0_P6_U1_CFG11 0x40010ccbu\r
+#define CYDEV_UCFG_B0_P6_U1_CFG12 0x40010cccu\r
+#define CYDEV_UCFG_B0_P6_U1_CFG13 0x40010ccdu\r
+#define CYDEV_UCFG_B0_P6_U1_CFG14 0x40010cceu\r
+#define CYDEV_UCFG_B0_P6_U1_CFG15 0x40010ccfu\r
+#define CYDEV_UCFG_B0_P6_U1_CFG16 0x40010cd0u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG17 0x40010cd1u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG18 0x40010cd2u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG19 0x40010cd3u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG20 0x40010cd4u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG21 0x40010cd5u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG22 0x40010cd6u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG23 0x40010cd7u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG24 0x40010cd8u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG25 0x40010cd9u\r
+#define CYDEV_UCFG_B0_P6_U1_CFG26 0x40010cdau\r
+#define CYDEV_UCFG_B0_P6_U1_CFG27 0x40010cdbu\r
+#define CYDEV_UCFG_B0_P6_U1_CFG28 0x40010cdcu\r
+#define CYDEV_UCFG_B0_P6_U1_CFG29 0x40010cddu\r
+#define CYDEV_UCFG_B0_P6_U1_CFG30 0x40010cdeu\r
+#define CYDEV_UCFG_B0_P6_U1_CFG31 0x40010cdfu\r
+#define CYDEV_UCFG_B0_P6_U1_DCFG0 0x40010ce0u\r
+#define CYDEV_UCFG_B0_P6_U1_DCFG1 0x40010ce2u\r
+#define CYDEV_UCFG_B0_P6_U1_DCFG2 0x40010ce4u\r
+#define CYDEV_UCFG_B0_P6_U1_DCFG3 0x40010ce6u\r
+#define CYDEV_UCFG_B0_P6_U1_DCFG4 0x40010ce8u\r
+#define CYDEV_UCFG_B0_P6_U1_DCFG5 0x40010ceau\r
+#define CYDEV_UCFG_B0_P6_U1_DCFG6 0x40010cecu\r
+#define CYDEV_UCFG_B0_P6_U1_DCFG7 0x40010ceeu\r
+#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00u\r
+#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B0_P7_BASE 0x40010e00u\r
+#define CYDEV_UCFG_B0_P7_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00u\r
+#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT0 0x40010e00u\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT1 0x40010e04u\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT2 0x40010e08u\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT3 0x40010e0cu\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT4 0x40010e10u\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT5 0x40010e14u\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT6 0x40010e18u\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT7 0x40010e1cu\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT8 0x40010e20u\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT9 0x40010e24u\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT10 0x40010e28u\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_IT11 0x40010e2cu\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_ORT0 0x40010e30u\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_ORT1 0x40010e32u\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_ORT2 0x40010e34u\r
+#define CYDEV_UCFG_B0_P7_U0_PLD_ORT3 0x40010e36u\r
+#define CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38u\r
+#define CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB 0x40010e3au\r
+#define CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3cu\r
+#define CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3eu\r
+#define CYDEV_UCFG_B0_P7_U0_CFG0 0x40010e40u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG1 0x40010e41u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG2 0x40010e42u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG3 0x40010e43u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG4 0x40010e44u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG5 0x40010e45u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG6 0x40010e46u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG7 0x40010e47u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG8 0x40010e48u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG9 0x40010e49u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG10 0x40010e4au\r
+#define CYDEV_UCFG_B0_P7_U0_CFG11 0x40010e4bu\r
+#define CYDEV_UCFG_B0_P7_U0_CFG12 0x40010e4cu\r
+#define CYDEV_UCFG_B0_P7_U0_CFG13 0x40010e4du\r
+#define CYDEV_UCFG_B0_P7_U0_CFG14 0x40010e4eu\r
+#define CYDEV_UCFG_B0_P7_U0_CFG15 0x40010e4fu\r
+#define CYDEV_UCFG_B0_P7_U0_CFG16 0x40010e50u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG17 0x40010e51u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG18 0x40010e52u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG19 0x40010e53u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG20 0x40010e54u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG21 0x40010e55u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG22 0x40010e56u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG23 0x40010e57u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG24 0x40010e58u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG25 0x40010e59u\r
+#define CYDEV_UCFG_B0_P7_U0_CFG26 0x40010e5au\r
+#define CYDEV_UCFG_B0_P7_U0_CFG27 0x40010e5bu\r
+#define CYDEV_UCFG_B0_P7_U0_CFG28 0x40010e5cu\r
+#define CYDEV_UCFG_B0_P7_U0_CFG29 0x40010e5du\r
+#define CYDEV_UCFG_B0_P7_U0_CFG30 0x40010e5eu\r
+#define CYDEV_UCFG_B0_P7_U0_CFG31 0x40010e5fu\r
+#define CYDEV_UCFG_B0_P7_U0_DCFG0 0x40010e60u\r
+#define CYDEV_UCFG_B0_P7_U0_DCFG1 0x40010e62u\r
+#define CYDEV_UCFG_B0_P7_U0_DCFG2 0x40010e64u\r
+#define CYDEV_UCFG_B0_P7_U0_DCFG3 0x40010e66u\r
+#define CYDEV_UCFG_B0_P7_U0_DCFG4 0x40010e68u\r
+#define CYDEV_UCFG_B0_P7_U0_DCFG5 0x40010e6au\r
+#define CYDEV_UCFG_B0_P7_U0_DCFG6 0x40010e6cu\r
+#define CYDEV_UCFG_B0_P7_U0_DCFG7 0x40010e6eu\r
+#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80u\r
+#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT0 0x40010e80u\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT1 0x40010e84u\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT2 0x40010e88u\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT3 0x40010e8cu\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT4 0x40010e90u\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT5 0x40010e94u\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT6 0x40010e98u\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT7 0x40010e9cu\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT8 0x40010ea0u\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT9 0x40010ea4u\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT10 0x40010ea8u\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_IT11 0x40010eacu\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_ORT0 0x40010eb0u\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_ORT1 0x40010eb2u\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_ORT2 0x40010eb4u\r
+#define CYDEV_UCFG_B0_P7_U1_PLD_ORT3 0x40010eb6u\r
+#define CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8u\r
+#define CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB 0x40010ebau\r
+#define CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebcu\r
+#define CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebeu\r
+#define CYDEV_UCFG_B0_P7_U1_CFG0 0x40010ec0u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG1 0x40010ec1u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG2 0x40010ec2u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG3 0x40010ec3u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG4 0x40010ec4u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG5 0x40010ec5u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG6 0x40010ec6u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG7 0x40010ec7u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG8 0x40010ec8u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG9 0x40010ec9u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG10 0x40010ecau\r
+#define CYDEV_UCFG_B0_P7_U1_CFG11 0x40010ecbu\r
+#define CYDEV_UCFG_B0_P7_U1_CFG12 0x40010eccu\r
+#define CYDEV_UCFG_B0_P7_U1_CFG13 0x40010ecdu\r
+#define CYDEV_UCFG_B0_P7_U1_CFG14 0x40010eceu\r
+#define CYDEV_UCFG_B0_P7_U1_CFG15 0x40010ecfu\r
+#define CYDEV_UCFG_B0_P7_U1_CFG16 0x40010ed0u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG17 0x40010ed1u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG18 0x40010ed2u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG19 0x40010ed3u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG20 0x40010ed4u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG21 0x40010ed5u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG22 0x40010ed6u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG23 0x40010ed7u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG24 0x40010ed8u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG25 0x40010ed9u\r
+#define CYDEV_UCFG_B0_P7_U1_CFG26 0x40010edau\r
+#define CYDEV_UCFG_B0_P7_U1_CFG27 0x40010edbu\r
+#define CYDEV_UCFG_B0_P7_U1_CFG28 0x40010edcu\r
+#define CYDEV_UCFG_B0_P7_U1_CFG29 0x40010eddu\r
+#define CYDEV_UCFG_B0_P7_U1_CFG30 0x40010edeu\r
+#define CYDEV_UCFG_B0_P7_U1_CFG31 0x40010edfu\r
+#define CYDEV_UCFG_B0_P7_U1_DCFG0 0x40010ee0u\r
+#define CYDEV_UCFG_B0_P7_U1_DCFG1 0x40010ee2u\r
+#define CYDEV_UCFG_B0_P7_U1_DCFG2 0x40010ee4u\r
+#define CYDEV_UCFG_B0_P7_U1_DCFG3 0x40010ee6u\r
+#define CYDEV_UCFG_B0_P7_U1_DCFG4 0x40010ee8u\r
+#define CYDEV_UCFG_B0_P7_U1_DCFG5 0x40010eeau\r
+#define CYDEV_UCFG_B0_P7_U1_DCFG6 0x40010eecu\r
+#define CYDEV_UCFG_B0_P7_U1_DCFG7 0x40010eeeu\r
+#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00u\r
+#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B1_BASE 0x40011000u\r
+#define CYDEV_UCFG_B1_SIZE 0x00000fefu\r
+#define CYDEV_UCFG_B1_P2_BASE 0x40011400u\r
+#define CYDEV_UCFG_B1_P2_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400u\r
+#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT0 0x40011400u\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT1 0x40011404u\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT2 0x40011408u\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT3 0x4001140cu\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT4 0x40011410u\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT5 0x40011414u\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT6 0x40011418u\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT7 0x4001141cu\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT8 0x40011420u\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT9 0x40011424u\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT10 0x40011428u\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_IT11 0x4001142cu\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_ORT0 0x40011430u\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_ORT1 0x40011432u\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_ORT2 0x40011434u\r
+#define CYDEV_UCFG_B1_P2_U0_PLD_ORT3 0x40011436u\r
+#define CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438u\r
+#define CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB 0x4001143au\r
+#define CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143cu\r
+#define CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS 0x4001143eu\r
+#define CYDEV_UCFG_B1_P2_U0_CFG0 0x40011440u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG1 0x40011441u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG2 0x40011442u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG3 0x40011443u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG4 0x40011444u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG5 0x40011445u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG6 0x40011446u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG7 0x40011447u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG8 0x40011448u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG9 0x40011449u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG10 0x4001144au\r
+#define CYDEV_UCFG_B1_P2_U0_CFG11 0x4001144bu\r
+#define CYDEV_UCFG_B1_P2_U0_CFG12 0x4001144cu\r
+#define CYDEV_UCFG_B1_P2_U0_CFG13 0x4001144du\r
+#define CYDEV_UCFG_B1_P2_U0_CFG14 0x4001144eu\r
+#define CYDEV_UCFG_B1_P2_U0_CFG15 0x4001144fu\r
+#define CYDEV_UCFG_B1_P2_U0_CFG16 0x40011450u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG17 0x40011451u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG18 0x40011452u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG19 0x40011453u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG20 0x40011454u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG21 0x40011455u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG22 0x40011456u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG23 0x40011457u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG24 0x40011458u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG25 0x40011459u\r
+#define CYDEV_UCFG_B1_P2_U0_CFG26 0x4001145au\r
+#define CYDEV_UCFG_B1_P2_U0_CFG27 0x4001145bu\r
+#define CYDEV_UCFG_B1_P2_U0_CFG28 0x4001145cu\r
+#define CYDEV_UCFG_B1_P2_U0_CFG29 0x4001145du\r
+#define CYDEV_UCFG_B1_P2_U0_CFG30 0x4001145eu\r
+#define CYDEV_UCFG_B1_P2_U0_CFG31 0x4001145fu\r
+#define CYDEV_UCFG_B1_P2_U0_DCFG0 0x40011460u\r
+#define CYDEV_UCFG_B1_P2_U0_DCFG1 0x40011462u\r
+#define CYDEV_UCFG_B1_P2_U0_DCFG2 0x40011464u\r
+#define CYDEV_UCFG_B1_P2_U0_DCFG3 0x40011466u\r
+#define CYDEV_UCFG_B1_P2_U0_DCFG4 0x40011468u\r
+#define CYDEV_UCFG_B1_P2_U0_DCFG5 0x4001146au\r
+#define CYDEV_UCFG_B1_P2_U0_DCFG6 0x4001146cu\r
+#define CYDEV_UCFG_B1_P2_U0_DCFG7 0x4001146eu\r
+#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480u\r
+#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT0 0x40011480u\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT1 0x40011484u\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT2 0x40011488u\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT3 0x4001148cu\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT4 0x40011490u\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT5 0x40011494u\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT6 0x40011498u\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT7 0x4001149cu\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT8 0x400114a0u\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT9 0x400114a4u\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT10 0x400114a8u\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_IT11 0x400114acu\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_ORT0 0x400114b0u\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_ORT1 0x400114b2u\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_ORT2 0x400114b4u\r
+#define CYDEV_UCFG_B1_P2_U1_PLD_ORT3 0x400114b6u\r
+#define CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8u\r
+#define CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB 0x400114bau\r
+#define CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bcu\r
+#define CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS 0x400114beu\r
+#define CYDEV_UCFG_B1_P2_U1_CFG0 0x400114c0u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG1 0x400114c1u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG2 0x400114c2u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG3 0x400114c3u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG4 0x400114c4u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG5 0x400114c5u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG6 0x400114c6u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG7 0x400114c7u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG8 0x400114c8u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG9 0x400114c9u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG10 0x400114cau\r
+#define CYDEV_UCFG_B1_P2_U1_CFG11 0x400114cbu\r
+#define CYDEV_UCFG_B1_P2_U1_CFG12 0x400114ccu\r
+#define CYDEV_UCFG_B1_P2_U1_CFG13 0x400114cdu\r
+#define CYDEV_UCFG_B1_P2_U1_CFG14 0x400114ceu\r
+#define CYDEV_UCFG_B1_P2_U1_CFG15 0x400114cfu\r
+#define CYDEV_UCFG_B1_P2_U1_CFG16 0x400114d0u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG17 0x400114d1u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG18 0x400114d2u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG19 0x400114d3u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG20 0x400114d4u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG21 0x400114d5u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG22 0x400114d6u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG23 0x400114d7u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG24 0x400114d8u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG25 0x400114d9u\r
+#define CYDEV_UCFG_B1_P2_U1_CFG26 0x400114dau\r
+#define CYDEV_UCFG_B1_P2_U1_CFG27 0x400114dbu\r
+#define CYDEV_UCFG_B1_P2_U1_CFG28 0x400114dcu\r
+#define CYDEV_UCFG_B1_P2_U1_CFG29 0x400114ddu\r
+#define CYDEV_UCFG_B1_P2_U1_CFG30 0x400114deu\r
+#define CYDEV_UCFG_B1_P2_U1_CFG31 0x400114dfu\r
+#define CYDEV_UCFG_B1_P2_U1_DCFG0 0x400114e0u\r
+#define CYDEV_UCFG_B1_P2_U1_DCFG1 0x400114e2u\r
+#define CYDEV_UCFG_B1_P2_U1_DCFG2 0x400114e4u\r
+#define CYDEV_UCFG_B1_P2_U1_DCFG3 0x400114e6u\r
+#define CYDEV_UCFG_B1_P2_U1_DCFG4 0x400114e8u\r
+#define CYDEV_UCFG_B1_P2_U1_DCFG5 0x400114eau\r
+#define CYDEV_UCFG_B1_P2_U1_DCFG6 0x400114ecu\r
+#define CYDEV_UCFG_B1_P2_U1_DCFG7 0x400114eeu\r
+#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500u\r
+#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B1_P3_BASE 0x40011600u\r
+#define CYDEV_UCFG_B1_P3_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600u\r
+#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT0 0x40011600u\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT1 0x40011604u\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT2 0x40011608u\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT3 0x4001160cu\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT4 0x40011610u\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT5 0x40011614u\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT6 0x40011618u\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT7 0x4001161cu\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT8 0x40011620u\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT9 0x40011624u\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT10 0x40011628u\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_IT11 0x4001162cu\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_ORT0 0x40011630u\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_ORT1 0x40011632u\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_ORT2 0x40011634u\r
+#define CYDEV_UCFG_B1_P3_U0_PLD_ORT3 0x40011636u\r
+#define CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638u\r
+#define CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB 0x4001163au\r
+#define CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163cu\r
+#define CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS 0x4001163eu\r
+#define CYDEV_UCFG_B1_P3_U0_CFG0 0x40011640u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG1 0x40011641u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG2 0x40011642u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG3 0x40011643u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG4 0x40011644u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG5 0x40011645u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG6 0x40011646u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG7 0x40011647u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG8 0x40011648u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG9 0x40011649u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG10 0x4001164au\r
+#define CYDEV_UCFG_B1_P3_U0_CFG11 0x4001164bu\r
+#define CYDEV_UCFG_B1_P3_U0_CFG12 0x4001164cu\r
+#define CYDEV_UCFG_B1_P3_U0_CFG13 0x4001164du\r
+#define CYDEV_UCFG_B1_P3_U0_CFG14 0x4001164eu\r
+#define CYDEV_UCFG_B1_P3_U0_CFG15 0x4001164fu\r
+#define CYDEV_UCFG_B1_P3_U0_CFG16 0x40011650u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG17 0x40011651u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG18 0x40011652u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG19 0x40011653u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG20 0x40011654u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG21 0x40011655u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG22 0x40011656u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG23 0x40011657u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG24 0x40011658u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG25 0x40011659u\r
+#define CYDEV_UCFG_B1_P3_U0_CFG26 0x4001165au\r
+#define CYDEV_UCFG_B1_P3_U0_CFG27 0x4001165bu\r
+#define CYDEV_UCFG_B1_P3_U0_CFG28 0x4001165cu\r
+#define CYDEV_UCFG_B1_P3_U0_CFG29 0x4001165du\r
+#define CYDEV_UCFG_B1_P3_U0_CFG30 0x4001165eu\r
+#define CYDEV_UCFG_B1_P3_U0_CFG31 0x4001165fu\r
+#define CYDEV_UCFG_B1_P3_U0_DCFG0 0x40011660u\r
+#define CYDEV_UCFG_B1_P3_U0_DCFG1 0x40011662u\r
+#define CYDEV_UCFG_B1_P3_U0_DCFG2 0x40011664u\r
+#define CYDEV_UCFG_B1_P3_U0_DCFG3 0x40011666u\r
+#define CYDEV_UCFG_B1_P3_U0_DCFG4 0x40011668u\r
+#define CYDEV_UCFG_B1_P3_U0_DCFG5 0x4001166au\r
+#define CYDEV_UCFG_B1_P3_U0_DCFG6 0x4001166cu\r
+#define CYDEV_UCFG_B1_P3_U0_DCFG7 0x4001166eu\r
+#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680u\r
+#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT0 0x40011680u\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT1 0x40011684u\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT2 0x40011688u\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT3 0x4001168cu\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT4 0x40011690u\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT5 0x40011694u\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT6 0x40011698u\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT7 0x4001169cu\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT8 0x400116a0u\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT9 0x400116a4u\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT10 0x400116a8u\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_IT11 0x400116acu\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_ORT0 0x400116b0u\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_ORT1 0x400116b2u\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_ORT2 0x400116b4u\r
+#define CYDEV_UCFG_B1_P3_U1_PLD_ORT3 0x400116b6u\r
+#define CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8u\r
+#define CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB 0x400116bau\r
+#define CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bcu\r
+#define CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS 0x400116beu\r
+#define CYDEV_UCFG_B1_P3_U1_CFG0 0x400116c0u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG1 0x400116c1u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG2 0x400116c2u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG3 0x400116c3u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG4 0x400116c4u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG5 0x400116c5u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG6 0x400116c6u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG7 0x400116c7u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG8 0x400116c8u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG9 0x400116c9u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG10 0x400116cau\r
+#define CYDEV_UCFG_B1_P3_U1_CFG11 0x400116cbu\r
+#define CYDEV_UCFG_B1_P3_U1_CFG12 0x400116ccu\r
+#define CYDEV_UCFG_B1_P3_U1_CFG13 0x400116cdu\r
+#define CYDEV_UCFG_B1_P3_U1_CFG14 0x400116ceu\r
+#define CYDEV_UCFG_B1_P3_U1_CFG15 0x400116cfu\r
+#define CYDEV_UCFG_B1_P3_U1_CFG16 0x400116d0u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG17 0x400116d1u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG18 0x400116d2u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG19 0x400116d3u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG20 0x400116d4u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG21 0x400116d5u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG22 0x400116d6u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG23 0x400116d7u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG24 0x400116d8u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG25 0x400116d9u\r
+#define CYDEV_UCFG_B1_P3_U1_CFG26 0x400116dau\r
+#define CYDEV_UCFG_B1_P3_U1_CFG27 0x400116dbu\r
+#define CYDEV_UCFG_B1_P3_U1_CFG28 0x400116dcu\r
+#define CYDEV_UCFG_B1_P3_U1_CFG29 0x400116ddu\r
+#define CYDEV_UCFG_B1_P3_U1_CFG30 0x400116deu\r
+#define CYDEV_UCFG_B1_P3_U1_CFG31 0x400116dfu\r
+#define CYDEV_UCFG_B1_P3_U1_DCFG0 0x400116e0u\r
+#define CYDEV_UCFG_B1_P3_U1_DCFG1 0x400116e2u\r
+#define CYDEV_UCFG_B1_P3_U1_DCFG2 0x400116e4u\r
+#define CYDEV_UCFG_B1_P3_U1_DCFG3 0x400116e6u\r
+#define CYDEV_UCFG_B1_P3_U1_DCFG4 0x400116e8u\r
+#define CYDEV_UCFG_B1_P3_U1_DCFG5 0x400116eau\r
+#define CYDEV_UCFG_B1_P3_U1_DCFG6 0x400116ecu\r
+#define CYDEV_UCFG_B1_P3_U1_DCFG7 0x400116eeu\r
+#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700u\r
+#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B1_P4_BASE 0x40011800u\r
+#define CYDEV_UCFG_B1_P4_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800u\r
+#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT0 0x40011800u\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT1 0x40011804u\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT2 0x40011808u\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT3 0x4001180cu\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT4 0x40011810u\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT5 0x40011814u\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT6 0x40011818u\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT7 0x4001181cu\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT8 0x40011820u\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT9 0x40011824u\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT10 0x40011828u\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_IT11 0x4001182cu\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_ORT0 0x40011830u\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_ORT1 0x40011832u\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_ORT2 0x40011834u\r
+#define CYDEV_UCFG_B1_P4_U0_PLD_ORT3 0x40011836u\r
+#define CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838u\r
+#define CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB 0x4001183au\r
+#define CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183cu\r
+#define CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS 0x4001183eu\r
+#define CYDEV_UCFG_B1_P4_U0_CFG0 0x40011840u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG1 0x40011841u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG2 0x40011842u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG3 0x40011843u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG4 0x40011844u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG5 0x40011845u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG6 0x40011846u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG7 0x40011847u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG8 0x40011848u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG9 0x40011849u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG10 0x4001184au\r
+#define CYDEV_UCFG_B1_P4_U0_CFG11 0x4001184bu\r
+#define CYDEV_UCFG_B1_P4_U0_CFG12 0x4001184cu\r
+#define CYDEV_UCFG_B1_P4_U0_CFG13 0x4001184du\r
+#define CYDEV_UCFG_B1_P4_U0_CFG14 0x4001184eu\r
+#define CYDEV_UCFG_B1_P4_U0_CFG15 0x4001184fu\r
+#define CYDEV_UCFG_B1_P4_U0_CFG16 0x40011850u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG17 0x40011851u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG18 0x40011852u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG19 0x40011853u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG20 0x40011854u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG21 0x40011855u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG22 0x40011856u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG23 0x40011857u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG24 0x40011858u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG25 0x40011859u\r
+#define CYDEV_UCFG_B1_P4_U0_CFG26 0x4001185au\r
+#define CYDEV_UCFG_B1_P4_U0_CFG27 0x4001185bu\r
+#define CYDEV_UCFG_B1_P4_U0_CFG28 0x4001185cu\r
+#define CYDEV_UCFG_B1_P4_U0_CFG29 0x4001185du\r
+#define CYDEV_UCFG_B1_P4_U0_CFG30 0x4001185eu\r
+#define CYDEV_UCFG_B1_P4_U0_CFG31 0x4001185fu\r
+#define CYDEV_UCFG_B1_P4_U0_DCFG0 0x40011860u\r
+#define CYDEV_UCFG_B1_P4_U0_DCFG1 0x40011862u\r
+#define CYDEV_UCFG_B1_P4_U0_DCFG2 0x40011864u\r
+#define CYDEV_UCFG_B1_P4_U0_DCFG3 0x40011866u\r
+#define CYDEV_UCFG_B1_P4_U0_DCFG4 0x40011868u\r
+#define CYDEV_UCFG_B1_P4_U0_DCFG5 0x4001186au\r
+#define CYDEV_UCFG_B1_P4_U0_DCFG6 0x4001186cu\r
+#define CYDEV_UCFG_B1_P4_U0_DCFG7 0x4001186eu\r
+#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880u\r
+#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT0 0x40011880u\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT1 0x40011884u\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT2 0x40011888u\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT3 0x4001188cu\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT4 0x40011890u\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT5 0x40011894u\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT6 0x40011898u\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT7 0x4001189cu\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT8 0x400118a0u\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT9 0x400118a4u\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT10 0x400118a8u\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_IT11 0x400118acu\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_ORT0 0x400118b0u\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_ORT1 0x400118b2u\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_ORT2 0x400118b4u\r
+#define CYDEV_UCFG_B1_P4_U1_PLD_ORT3 0x400118b6u\r
+#define CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8u\r
+#define CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB 0x400118bau\r
+#define CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bcu\r
+#define CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS 0x400118beu\r
+#define CYDEV_UCFG_B1_P4_U1_CFG0 0x400118c0u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG1 0x400118c1u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG2 0x400118c2u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG3 0x400118c3u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG4 0x400118c4u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG5 0x400118c5u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG6 0x400118c6u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG7 0x400118c7u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG8 0x400118c8u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG9 0x400118c9u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG10 0x400118cau\r
+#define CYDEV_UCFG_B1_P4_U1_CFG11 0x400118cbu\r
+#define CYDEV_UCFG_B1_P4_U1_CFG12 0x400118ccu\r
+#define CYDEV_UCFG_B1_P4_U1_CFG13 0x400118cdu\r
+#define CYDEV_UCFG_B1_P4_U1_CFG14 0x400118ceu\r
+#define CYDEV_UCFG_B1_P4_U1_CFG15 0x400118cfu\r
+#define CYDEV_UCFG_B1_P4_U1_CFG16 0x400118d0u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG17 0x400118d1u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG18 0x400118d2u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG19 0x400118d3u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG20 0x400118d4u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG21 0x400118d5u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG22 0x400118d6u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG23 0x400118d7u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG24 0x400118d8u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG25 0x400118d9u\r
+#define CYDEV_UCFG_B1_P4_U1_CFG26 0x400118dau\r
+#define CYDEV_UCFG_B1_P4_U1_CFG27 0x400118dbu\r
+#define CYDEV_UCFG_B1_P4_U1_CFG28 0x400118dcu\r
+#define CYDEV_UCFG_B1_P4_U1_CFG29 0x400118ddu\r
+#define CYDEV_UCFG_B1_P4_U1_CFG30 0x400118deu\r
+#define CYDEV_UCFG_B1_P4_U1_CFG31 0x400118dfu\r
+#define CYDEV_UCFG_B1_P4_U1_DCFG0 0x400118e0u\r
+#define CYDEV_UCFG_B1_P4_U1_DCFG1 0x400118e2u\r
+#define CYDEV_UCFG_B1_P4_U1_DCFG2 0x400118e4u\r
+#define CYDEV_UCFG_B1_P4_U1_DCFG3 0x400118e6u\r
+#define CYDEV_UCFG_B1_P4_U1_DCFG4 0x400118e8u\r
+#define CYDEV_UCFG_B1_P4_U1_DCFG5 0x400118eau\r
+#define CYDEV_UCFG_B1_P4_U1_DCFG6 0x400118ecu\r
+#define CYDEV_UCFG_B1_P4_U1_DCFG7 0x400118eeu\r
+#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900u\r
+#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B1_P5_BASE 0x40011a00u\r
+#define CYDEV_UCFG_B1_P5_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00u\r
+#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT0 0x40011a00u\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT1 0x40011a04u\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT2 0x40011a08u\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT3 0x40011a0cu\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT4 0x40011a10u\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT5 0x40011a14u\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT6 0x40011a18u\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT7 0x40011a1cu\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT8 0x40011a20u\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT9 0x40011a24u\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT10 0x40011a28u\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_IT11 0x40011a2cu\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_ORT0 0x40011a30u\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_ORT1 0x40011a32u\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_ORT2 0x40011a34u\r
+#define CYDEV_UCFG_B1_P5_U0_PLD_ORT3 0x40011a36u\r
+#define CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38u\r
+#define CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB 0x40011a3au\r
+#define CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3cu\r
+#define CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3eu\r
+#define CYDEV_UCFG_B1_P5_U0_CFG0 0x40011a40u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG1 0x40011a41u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG2 0x40011a42u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG3 0x40011a43u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG4 0x40011a44u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG5 0x40011a45u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG6 0x40011a46u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG7 0x40011a47u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG8 0x40011a48u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG9 0x40011a49u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG10 0x40011a4au\r
+#define CYDEV_UCFG_B1_P5_U0_CFG11 0x40011a4bu\r
+#define CYDEV_UCFG_B1_P5_U0_CFG12 0x40011a4cu\r
+#define CYDEV_UCFG_B1_P5_U0_CFG13 0x40011a4du\r
+#define CYDEV_UCFG_B1_P5_U0_CFG14 0x40011a4eu\r
+#define CYDEV_UCFG_B1_P5_U0_CFG15 0x40011a4fu\r
+#define CYDEV_UCFG_B1_P5_U0_CFG16 0x40011a50u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG17 0x40011a51u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG18 0x40011a52u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG19 0x40011a53u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG20 0x40011a54u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG21 0x40011a55u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG22 0x40011a56u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG23 0x40011a57u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG24 0x40011a58u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG25 0x40011a59u\r
+#define CYDEV_UCFG_B1_P5_U0_CFG26 0x40011a5au\r
+#define CYDEV_UCFG_B1_P5_U0_CFG27 0x40011a5bu\r
+#define CYDEV_UCFG_B1_P5_U0_CFG28 0x40011a5cu\r
+#define CYDEV_UCFG_B1_P5_U0_CFG29 0x40011a5du\r
+#define CYDEV_UCFG_B1_P5_U0_CFG30 0x40011a5eu\r
+#define CYDEV_UCFG_B1_P5_U0_CFG31 0x40011a5fu\r
+#define CYDEV_UCFG_B1_P5_U0_DCFG0 0x40011a60u\r
+#define CYDEV_UCFG_B1_P5_U0_DCFG1 0x40011a62u\r
+#define CYDEV_UCFG_B1_P5_U0_DCFG2 0x40011a64u\r
+#define CYDEV_UCFG_B1_P5_U0_DCFG3 0x40011a66u\r
+#define CYDEV_UCFG_B1_P5_U0_DCFG4 0x40011a68u\r
+#define CYDEV_UCFG_B1_P5_U0_DCFG5 0x40011a6au\r
+#define CYDEV_UCFG_B1_P5_U0_DCFG6 0x40011a6cu\r
+#define CYDEV_UCFG_B1_P5_U0_DCFG7 0x40011a6eu\r
+#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80u\r
+#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070u\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT0 0x40011a80u\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT1 0x40011a84u\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT2 0x40011a88u\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT3 0x40011a8cu\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT4 0x40011a90u\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT5 0x40011a94u\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT6 0x40011a98u\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT7 0x40011a9cu\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT8 0x40011aa0u\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT9 0x40011aa4u\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT10 0x40011aa8u\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_IT11 0x40011aacu\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_ORT0 0x40011ab0u\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_ORT1 0x40011ab2u\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_ORT2 0x40011ab4u\r
+#define CYDEV_UCFG_B1_P5_U1_PLD_ORT3 0x40011ab6u\r
+#define CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8u\r
+#define CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB 0x40011abau\r
+#define CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abcu\r
+#define CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS 0x40011abeu\r
+#define CYDEV_UCFG_B1_P5_U1_CFG0 0x40011ac0u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG1 0x40011ac1u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG2 0x40011ac2u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG3 0x40011ac3u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG4 0x40011ac4u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG5 0x40011ac5u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG6 0x40011ac6u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG7 0x40011ac7u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG8 0x40011ac8u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG9 0x40011ac9u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG10 0x40011acau\r
+#define CYDEV_UCFG_B1_P5_U1_CFG11 0x40011acbu\r
+#define CYDEV_UCFG_B1_P5_U1_CFG12 0x40011accu\r
+#define CYDEV_UCFG_B1_P5_U1_CFG13 0x40011acdu\r
+#define CYDEV_UCFG_B1_P5_U1_CFG14 0x40011aceu\r
+#define CYDEV_UCFG_B1_P5_U1_CFG15 0x40011acfu\r
+#define CYDEV_UCFG_B1_P5_U1_CFG16 0x40011ad0u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG17 0x40011ad1u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG18 0x40011ad2u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG19 0x40011ad3u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG20 0x40011ad4u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG21 0x40011ad5u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG22 0x40011ad6u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG23 0x40011ad7u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG24 0x40011ad8u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG25 0x40011ad9u\r
+#define CYDEV_UCFG_B1_P5_U1_CFG26 0x40011adau\r
+#define CYDEV_UCFG_B1_P5_U1_CFG27 0x40011adbu\r
+#define CYDEV_UCFG_B1_P5_U1_CFG28 0x40011adcu\r
+#define CYDEV_UCFG_B1_P5_U1_CFG29 0x40011addu\r
+#define CYDEV_UCFG_B1_P5_U1_CFG30 0x40011adeu\r
+#define CYDEV_UCFG_B1_P5_U1_CFG31 0x40011adfu\r
+#define CYDEV_UCFG_B1_P5_U1_DCFG0 0x40011ae0u\r
+#define CYDEV_UCFG_B1_P5_U1_DCFG1 0x40011ae2u\r
+#define CYDEV_UCFG_B1_P5_U1_DCFG2 0x40011ae4u\r
+#define CYDEV_UCFG_B1_P5_U1_DCFG3 0x40011ae6u\r
+#define CYDEV_UCFG_B1_P5_U1_DCFG4 0x40011ae8u\r
+#define CYDEV_UCFG_B1_P5_U1_DCFG5 0x40011aeau\r
+#define CYDEV_UCFG_B1_P5_U1_DCFG6 0x40011aecu\r
+#define CYDEV_UCFG_B1_P5_U1_DCFG7 0x40011aeeu\r
+#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00u\r
+#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI0_BASE 0x40014000u\r
+#define CYDEV_UCFG_DSI0_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI1_BASE 0x40014100u\r
+#define CYDEV_UCFG_DSI1_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI2_BASE 0x40014200u\r
+#define CYDEV_UCFG_DSI2_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI3_BASE 0x40014300u\r
+#define CYDEV_UCFG_DSI3_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI4_BASE 0x40014400u\r
+#define CYDEV_UCFG_DSI4_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI5_BASE 0x40014500u\r
+#define CYDEV_UCFG_DSI5_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI6_BASE 0x40014600u\r
+#define CYDEV_UCFG_DSI6_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI7_BASE 0x40014700u\r
+#define CYDEV_UCFG_DSI7_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI8_BASE 0x40014800u\r
+#define CYDEV_UCFG_DSI8_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI9_BASE 0x40014900u\r
+#define CYDEV_UCFG_DSI9_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI12_BASE 0x40014c00u\r
+#define CYDEV_UCFG_DSI12_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI13_BASE 0x40014d00u\r
+#define CYDEV_UCFG_DSI13_SIZE 0x000000efu\r
+#define CYDEV_UCFG_BCTL0_BASE 0x40015000u\r
+#define CYDEV_UCFG_BCTL0_SIZE 0x00000010u\r
+#define CYDEV_UCFG_BCTL0_MDCLK_EN 0x40015000u\r
+#define CYDEV_UCFG_BCTL0_MBCLK_EN 0x40015001u\r
+#define CYDEV_UCFG_BCTL0_WAIT_CFG 0x40015002u\r
+#define CYDEV_UCFG_BCTL0_BANK_CTL 0x40015003u\r
+#define CYDEV_UCFG_BCTL0_UDB_TEST_3 0x40015007u\r
+#define CYDEV_UCFG_BCTL0_DCLK_EN0 0x40015008u\r
+#define CYDEV_UCFG_BCTL0_BCLK_EN0 0x40015009u\r
+#define CYDEV_UCFG_BCTL0_DCLK_EN1 0x4001500au\r
+#define CYDEV_UCFG_BCTL0_BCLK_EN1 0x4001500bu\r
+#define CYDEV_UCFG_BCTL0_DCLK_EN2 0x4001500cu\r
+#define CYDEV_UCFG_BCTL0_BCLK_EN2 0x4001500du\r
+#define CYDEV_UCFG_BCTL0_DCLK_EN3 0x4001500eu\r
+#define CYDEV_UCFG_BCTL0_BCLK_EN3 0x4001500fu\r
+#define CYDEV_UCFG_BCTL1_BASE 0x40015010u\r
+#define CYDEV_UCFG_BCTL1_SIZE 0x00000010u\r
+#define CYDEV_UCFG_BCTL1_MDCLK_EN 0x40015010u\r
+#define CYDEV_UCFG_BCTL1_MBCLK_EN 0x40015011u\r
+#define CYDEV_UCFG_BCTL1_WAIT_CFG 0x40015012u\r
+#define CYDEV_UCFG_BCTL1_BANK_CTL 0x40015013u\r
+#define CYDEV_UCFG_BCTL1_UDB_TEST_3 0x40015017u\r
+#define CYDEV_UCFG_BCTL1_DCLK_EN0 0x40015018u\r
+#define CYDEV_UCFG_BCTL1_BCLK_EN0 0x40015019u\r
+#define CYDEV_UCFG_BCTL1_DCLK_EN1 0x4001501au\r
+#define CYDEV_UCFG_BCTL1_BCLK_EN1 0x4001501bu\r
+#define CYDEV_UCFG_BCTL1_DCLK_EN2 0x4001501cu\r
+#define CYDEV_UCFG_BCTL1_BCLK_EN2 0x4001501du\r
+#define CYDEV_UCFG_BCTL1_DCLK_EN3 0x4001501eu\r
+#define CYDEV_UCFG_BCTL1_BCLK_EN3 0x4001501fu\r
+#define CYDEV_IDMUX_BASE 0x40015100u\r
+#define CYDEV_IDMUX_SIZE 0x00000016u\r
+#define CYDEV_IDMUX_IRQ_CTL0 0x40015100u\r
+#define CYDEV_IDMUX_IRQ_CTL1 0x40015101u\r
+#define CYDEV_IDMUX_IRQ_CTL2 0x40015102u\r
+#define CYDEV_IDMUX_IRQ_CTL3 0x40015103u\r
+#define CYDEV_IDMUX_IRQ_CTL4 0x40015104u\r
+#define CYDEV_IDMUX_IRQ_CTL5 0x40015105u\r
+#define CYDEV_IDMUX_IRQ_CTL6 0x40015106u\r
+#define CYDEV_IDMUX_IRQ_CTL7 0x40015107u\r
+#define CYDEV_IDMUX_DRQ_CTL0 0x40015110u\r
+#define CYDEV_IDMUX_DRQ_CTL1 0x40015111u\r
+#define CYDEV_IDMUX_DRQ_CTL2 0x40015112u\r
+#define CYDEV_IDMUX_DRQ_CTL3 0x40015113u\r
+#define CYDEV_IDMUX_DRQ_CTL4 0x40015114u\r
+#define CYDEV_IDMUX_DRQ_CTL5 0x40015115u\r
+#define CYDEV_CACHERAM_BASE 0x40030000u\r
+#define CYDEV_CACHERAM_SIZE 0x00000400u\r
+#define CYDEV_CACHERAM_DATA_MBASE 0x40030000u\r
+#define CYDEV_CACHERAM_DATA_MSIZE 0x00000400u\r
+#define CYDEV_SFR_BASE 0x40050100u\r
+#define CYDEV_SFR_SIZE 0x000000fbu\r
+#define CYDEV_SFR_GPIO0 0x40050180u\r
+#define CYDEV_SFR_GPIRD0 0x40050189u\r
+#define CYDEV_SFR_GPIO0_SEL 0x4005018au\r
+#define CYDEV_SFR_GPIO1 0x40050190u\r
+#define CYDEV_SFR_GPIRD1 0x40050191u\r
+#define CYDEV_SFR_GPIO2 0x40050198u\r
+#define CYDEV_SFR_GPIRD2 0x40050199u\r
+#define CYDEV_SFR_GPIO2_SEL 0x4005019au\r
+#define CYDEV_SFR_GPIO1_SEL 0x400501a2u\r
+#define CYDEV_SFR_GPIO3 0x400501b0u\r
+#define CYDEV_SFR_GPIRD3 0x400501b1u\r
+#define CYDEV_SFR_GPIO3_SEL 0x400501b2u\r
+#define CYDEV_SFR_GPIO4 0x400501c0u\r
+#define CYDEV_SFR_GPIRD4 0x400501c1u\r
+#define CYDEV_SFR_GPIO4_SEL 0x400501c2u\r
+#define CYDEV_SFR_GPIO5 0x400501c8u\r
+#define CYDEV_SFR_GPIRD5 0x400501c9u\r
+#define CYDEV_SFR_GPIO5_SEL 0x400501cau\r
+#define CYDEV_SFR_GPIO6 0x400501d8u\r
+#define CYDEV_SFR_GPIRD6 0x400501d9u\r
+#define CYDEV_SFR_GPIO6_SEL 0x400501dau\r
+#define CYDEV_SFR_GPIO12 0x400501e8u\r
+#define CYDEV_SFR_GPIRD12 0x400501e9u\r
+#define CYDEV_SFR_GPIO12_SEL 0x400501f2u\r
+#define CYDEV_SFR_GPIO15 0x400501f8u\r
+#define CYDEV_SFR_GPIRD15 0x400501f9u\r
+#define CYDEV_SFR_GPIO15_SEL 0x400501fau\r
+#define CYDEV_P3BA_BASE 0x40050300u\r
+#define CYDEV_P3BA_SIZE 0x0000002bu\r
+#define CYDEV_P3BA_Y_START 0x40050300u\r
+#define CYDEV_P3BA_YROLL 0x40050301u\r
+#define CYDEV_P3BA_YCFG 0x40050302u\r
+#define CYDEV_P3BA_X_START1 0x40050303u\r
+#define CYDEV_P3BA_X_START2 0x40050304u\r
+#define CYDEV_P3BA_XROLL1 0x40050305u\r
+#define CYDEV_P3BA_XROLL2 0x40050306u\r
+#define CYDEV_P3BA_XINC 0x40050307u\r
+#define CYDEV_P3BA_XCFG 0x40050308u\r
+#define CYDEV_P3BA_OFFSETADDR1 0x40050309u\r
+#define CYDEV_P3BA_OFFSETADDR2 0x4005030au\r
+#define CYDEV_P3BA_OFFSETADDR3 0x4005030bu\r
+#define CYDEV_P3BA_ABSADDR1 0x4005030cu\r
+#define CYDEV_P3BA_ABSADDR2 0x4005030du\r
+#define CYDEV_P3BA_ABSADDR3 0x4005030eu\r
+#define CYDEV_P3BA_ABSADDR4 0x4005030fu\r
+#define CYDEV_P3BA_DATCFG1 0x40050310u\r
+#define CYDEV_P3BA_DATCFG2 0x40050311u\r
+#define CYDEV_P3BA_CMP_RSLT1 0x40050314u\r
+#define CYDEV_P3BA_CMP_RSLT2 0x40050315u\r
+#define CYDEV_P3BA_CMP_RSLT3 0x40050316u\r
+#define CYDEV_P3BA_CMP_RSLT4 0x40050317u\r
+#define CYDEV_P3BA_DATA_REG1 0x40050318u\r
+#define CYDEV_P3BA_DATA_REG2 0x40050319u\r
+#define CYDEV_P3BA_DATA_REG3 0x4005031au\r
+#define CYDEV_P3BA_DATA_REG4 0x4005031bu\r
+#define CYDEV_P3BA_EXP_DATA1 0x4005031cu\r
+#define CYDEV_P3BA_EXP_DATA2 0x4005031du\r
+#define CYDEV_P3BA_EXP_DATA3 0x4005031eu\r
+#define CYDEV_P3BA_EXP_DATA4 0x4005031fu\r
+#define CYDEV_P3BA_MSTR_HRDATA1 0x40050320u\r
+#define CYDEV_P3BA_MSTR_HRDATA2 0x40050321u\r
+#define CYDEV_P3BA_MSTR_HRDATA3 0x40050322u\r
+#define CYDEV_P3BA_MSTR_HRDATA4 0x40050323u\r
+#define CYDEV_P3BA_BIST_EN 0x40050324u\r
+#define CYDEV_P3BA_PHUB_MASTER_SSR 0x40050325u\r
+#define CYDEV_P3BA_SEQCFG1 0x40050326u\r
+#define CYDEV_P3BA_SEQCFG2 0x40050327u\r
+#define CYDEV_P3BA_Y_CURR 0x40050328u\r
+#define CYDEV_P3BA_X_CURR1 0x40050329u\r
+#define CYDEV_P3BA_X_CURR2 0x4005032au\r
+#define CYDEV_PANTHER_BASE 0x40080000u\r
+#define CYDEV_PANTHER_SIZE 0x00000020u\r
+#define CYDEV_PANTHER_STCALIB_CFG 0x40080000u\r
+#define CYDEV_PANTHER_WAITPIPE 0x40080004u\r
+#define CYDEV_PANTHER_TRACE_CFG 0x40080008u\r
+#define CYDEV_PANTHER_DBG_CFG 0x4008000cu\r
+#define CYDEV_PANTHER_CM3_LCKRST_STAT 0x40080018u\r
+#define CYDEV_PANTHER_DEVICE_ID 0x4008001cu\r
+#define CYDEV_FLSECC_BASE 0x48000000u\r
+#define CYDEV_FLSECC_SIZE 0x00008000u\r
+#define CYDEV_FLSECC_DATA_MBASE 0x48000000u\r
+#define CYDEV_FLSECC_DATA_MSIZE 0x00008000u\r
+#define CYDEV_FLSHID_BASE 0x49000000u\r
+#define CYDEV_FLSHID_SIZE 0x00000200u\r
+#define CYDEV_FLSHID_RSVD_MBASE 0x49000000u\r
+#define CYDEV_FLSHID_RSVD_MSIZE 0x00000080u\r
+#define CYDEV_FLSHID_CUST_MDATA_MBASE 0x49000080u\r
+#define CYDEV_FLSHID_CUST_MDATA_MSIZE 0x00000080u\r
+#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100u\r
+#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040u\r
+#define CYDEV_FLSHID_CUST_TABLES_Y_LOC 0x49000100u\r
+#define CYDEV_FLSHID_CUST_TABLES_X_LOC 0x49000101u\r
+#define CYDEV_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102u\r
+#define CYDEV_FLSHID_CUST_TABLES_LOT_LSB 0x49000103u\r
+#define CYDEV_FLSHID_CUST_TABLES_LOT_MSB 0x49000104u\r
+#define CYDEV_FLSHID_CUST_TABLES_WRK_WK 0x49000105u\r
+#define CYDEV_FLSHID_CUST_TABLES_FAB_YR 0x49000106u\r
+#define CYDEV_FLSHID_CUST_TABLES_MINOR 0x49000107u\r
+#define CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108u\r
+#define CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109u\r
+#define CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010au\r
+#define CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010bu\r
+#define CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010cu\r
+#define CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010du\r
+#define CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010eu\r
+#define CYDEV_FLSHID_CUST_TABLES_IMO_USB 0x4900010fu\r
+#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110u\r
+#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111u\r
+#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112u\r
+#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113u\r
+#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114u\r
+#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115u\r
+#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116u\r
+#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117u\r
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M1 0x49000118u\r
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M2 0x49000119u\r
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M3 0x4900011au\r
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M4 0x4900011bu\r
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M5 0x4900011cu\r
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M6 0x4900011du\r
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M7 0x4900011eu\r
+#define CYDEV_FLSHID_CUST_TABLES_DEC_M8 0x4900011fu\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M1 0x49000120u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M2 0x49000121u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M3 0x49000122u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M4 0x49000123u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M5 0x49000124u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M6 0x49000125u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M7 0x49000126u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC0_M8 0x49000127u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M1 0x49000128u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M2 0x49000129u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M3 0x4900012au\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M4 0x4900012bu\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M5 0x4900012cu\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M6 0x4900012du\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M7 0x4900012eu\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC2_M8 0x4900012fu\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M1 0x49000130u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M2 0x49000131u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M3 0x49000132u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M4 0x49000133u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M5 0x49000134u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M6 0x49000135u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M7 0x49000136u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC1_M8 0x49000137u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M1 0x49000138u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M2 0x49000139u\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M3 0x4900013au\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M4 0x4900013bu\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M5 0x4900013cu\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M6 0x4900013du\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M7 0x4900013eu\r
+#define CYDEV_FLSHID_CUST_TABLES_DAC3_M8 0x4900013fu\r
+#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180u\r
+#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080u\r
+#define CYDEV_FLSHID_MFG_CFG_IMO_TR1 0x49000188u\r
+#define CYDEV_FLSHID_MFG_CFG_CMP0_TR0 0x490001acu\r
+#define CYDEV_FLSHID_MFG_CFG_CMP1_TR0 0x490001aeu\r
+#define CYDEV_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0u\r
+#define CYDEV_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2u\r
+#define CYDEV_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4u\r
+#define CYDEV_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6u\r
+#define CYDEV_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8u\r
+#define CYDEV_FLSHID_MFG_CFG_CMP3_TR1 0x490001bau\r
+#define CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ceu\r
+#define CYDEV_EXTMEM_BASE 0x60000000u\r
+#define CYDEV_EXTMEM_SIZE 0x00800000u\r
+#define CYDEV_EXTMEM_DATA_MBASE 0x60000000u\r
+#define CYDEV_EXTMEM_DATA_MSIZE 0x00800000u\r
+#define CYDEV_ITM_BASE 0xe0000000u\r
+#define CYDEV_ITM_SIZE 0x00001000u\r
+#define CYDEV_ITM_TRACE_EN 0xe0000e00u\r
+#define CYDEV_ITM_TRACE_PRIVILEGE 0xe0000e40u\r
+#define CYDEV_ITM_TRACE_CTRL 0xe0000e80u\r
+#define CYDEV_ITM_LOCK_ACCESS 0xe0000fb0u\r
+#define CYDEV_ITM_LOCK_STATUS 0xe0000fb4u\r
+#define CYDEV_ITM_PID4 0xe0000fd0u\r
+#define CYDEV_ITM_PID5 0xe0000fd4u\r
+#define CYDEV_ITM_PID6 0xe0000fd8u\r
+#define CYDEV_ITM_PID7 0xe0000fdcu\r
+#define CYDEV_ITM_PID0 0xe0000fe0u\r
+#define CYDEV_ITM_PID1 0xe0000fe4u\r
+#define CYDEV_ITM_PID2 0xe0000fe8u\r
+#define CYDEV_ITM_PID3 0xe0000fecu\r
+#define CYDEV_ITM_CID0 0xe0000ff0u\r
+#define CYDEV_ITM_CID1 0xe0000ff4u\r
+#define CYDEV_ITM_CID2 0xe0000ff8u\r
+#define CYDEV_ITM_CID3 0xe0000ffcu\r
+#define CYDEV_DWT_BASE 0xe0001000u\r
+#define CYDEV_DWT_SIZE 0x0000005cu\r
+#define CYDEV_DWT_CTRL 0xe0001000u\r
+#define CYDEV_DWT_CYCLE_COUNT 0xe0001004u\r
+#define CYDEV_DWT_CPI_COUNT 0xe0001008u\r
+#define CYDEV_DWT_EXC_OVHD_COUNT 0xe000100cu\r
+#define CYDEV_DWT_SLEEP_COUNT 0xe0001010u\r
+#define CYDEV_DWT_LSU_COUNT 0xe0001014u\r
+#define CYDEV_DWT_FOLD_COUNT 0xe0001018u\r
+#define CYDEV_DWT_PC_SAMPLE 0xe000101cu\r
+#define CYDEV_DWT_COMP_0 0xe0001020u\r
+#define CYDEV_DWT_MASK_0 0xe0001024u\r
+#define CYDEV_DWT_FUNCTION_0 0xe0001028u\r
+#define CYDEV_DWT_COMP_1 0xe0001030u\r
+#define CYDEV_DWT_MASK_1 0xe0001034u\r
+#define CYDEV_DWT_FUNCTION_1 0xe0001038u\r
+#define CYDEV_DWT_COMP_2 0xe0001040u\r
+#define CYDEV_DWT_MASK_2 0xe0001044u\r
+#define CYDEV_DWT_FUNCTION_2 0xe0001048u\r
+#define CYDEV_DWT_COMP_3 0xe0001050u\r
+#define CYDEV_DWT_MASK_3 0xe0001054u\r
+#define CYDEV_DWT_FUNCTION_3 0xe0001058u\r
+#define CYDEV_FPB_BASE 0xe0002000u\r
+#define CYDEV_FPB_SIZE 0x00001000u\r
+#define CYDEV_FPB_CTRL 0xe0002000u\r
+#define CYDEV_FPB_REMAP 0xe0002004u\r
+#define CYDEV_FPB_FP_COMP_0 0xe0002008u\r
+#define CYDEV_FPB_FP_COMP_1 0xe000200cu\r
+#define CYDEV_FPB_FP_COMP_2 0xe0002010u\r
+#define CYDEV_FPB_FP_COMP_3 0xe0002014u\r
+#define CYDEV_FPB_FP_COMP_4 0xe0002018u\r
+#define CYDEV_FPB_FP_COMP_5 0xe000201cu\r
+#define CYDEV_FPB_FP_COMP_6 0xe0002020u\r
+#define CYDEV_FPB_FP_COMP_7 0xe0002024u\r
+#define CYDEV_FPB_PID4 0xe0002fd0u\r
+#define CYDEV_FPB_PID5 0xe0002fd4u\r
+#define CYDEV_FPB_PID6 0xe0002fd8u\r
+#define CYDEV_FPB_PID7 0xe0002fdcu\r
+#define CYDEV_FPB_PID0 0xe0002fe0u\r
+#define CYDEV_FPB_PID1 0xe0002fe4u\r
+#define CYDEV_FPB_PID2 0xe0002fe8u\r
+#define CYDEV_FPB_PID3 0xe0002fecu\r
+#define CYDEV_FPB_CID0 0xe0002ff0u\r
+#define CYDEV_FPB_CID1 0xe0002ff4u\r
+#define CYDEV_FPB_CID2 0xe0002ff8u\r
+#define CYDEV_FPB_CID3 0xe0002ffcu\r
+#define CYDEV_NVIC_BASE 0xe000e000u\r
+#define CYDEV_NVIC_SIZE 0x00000d3cu\r
+#define CYDEV_NVIC_INT_CTL_TYPE 0xe000e004u\r
+#define CYDEV_NVIC_SYSTICK_CTL 0xe000e010u\r
+#define CYDEV_NVIC_SYSTICK_RELOAD 0xe000e014u\r
+#define CYDEV_NVIC_SYSTICK_CURRENT 0xe000e018u\r
+#define CYDEV_NVIC_SYSTICK_CAL 0xe000e01cu\r
+#define CYDEV_NVIC_SETENA0 0xe000e100u\r
+#define CYDEV_NVIC_CLRENA0 0xe000e180u\r
+#define CYDEV_NVIC_SETPEND0 0xe000e200u\r
+#define CYDEV_NVIC_CLRPEND0 0xe000e280u\r
+#define CYDEV_NVIC_ACTIVE0 0xe000e300u\r
+#define CYDEV_NVIC_PRI_0 0xe000e400u\r
+#define CYDEV_NVIC_PRI_1 0xe000e401u\r
+#define CYDEV_NVIC_PRI_2 0xe000e402u\r
+#define CYDEV_NVIC_PRI_3 0xe000e403u\r
+#define CYDEV_NVIC_PRI_4 0xe000e404u\r
+#define CYDEV_NVIC_PRI_5 0xe000e405u\r
+#define CYDEV_NVIC_PRI_6 0xe000e406u\r
+#define CYDEV_NVIC_PRI_7 0xe000e407u\r
+#define CYDEV_NVIC_PRI_8 0xe000e408u\r
+#define CYDEV_NVIC_PRI_9 0xe000e409u\r
+#define CYDEV_NVIC_PRI_10 0xe000e40au\r
+#define CYDEV_NVIC_PRI_11 0xe000e40bu\r
+#define CYDEV_NVIC_PRI_12 0xe000e40cu\r
+#define CYDEV_NVIC_PRI_13 0xe000e40du\r
+#define CYDEV_NVIC_PRI_14 0xe000e40eu\r
+#define CYDEV_NVIC_PRI_15 0xe000e40fu\r
+#define CYDEV_NVIC_PRI_16 0xe000e410u\r
+#define CYDEV_NVIC_PRI_17 0xe000e411u\r
+#define CYDEV_NVIC_PRI_18 0xe000e412u\r
+#define CYDEV_NVIC_PRI_19 0xe000e413u\r
+#define CYDEV_NVIC_PRI_20 0xe000e414u\r
+#define CYDEV_NVIC_PRI_21 0xe000e415u\r
+#define CYDEV_NVIC_PRI_22 0xe000e416u\r
+#define CYDEV_NVIC_PRI_23 0xe000e417u\r
+#define CYDEV_NVIC_PRI_24 0xe000e418u\r
+#define CYDEV_NVIC_PRI_25 0xe000e419u\r
+#define CYDEV_NVIC_PRI_26 0xe000e41au\r
+#define CYDEV_NVIC_PRI_27 0xe000e41bu\r
+#define CYDEV_NVIC_PRI_28 0xe000e41cu\r
+#define CYDEV_NVIC_PRI_29 0xe000e41du\r
+#define CYDEV_NVIC_PRI_30 0xe000e41eu\r
+#define CYDEV_NVIC_PRI_31 0xe000e41fu\r
+#define CYDEV_NVIC_CPUID_BASE 0xe000ed00u\r
+#define CYDEV_NVIC_INTR_CTRL_STATE 0xe000ed04u\r
+#define CYDEV_NVIC_VECT_OFFSET 0xe000ed08u\r
+#define CYDEV_NVIC_APPLN_INTR 0xe000ed0cu\r
+#define CYDEV_NVIC_SYSTEM_CONTROL 0xe000ed10u\r
+#define CYDEV_NVIC_CFG_CONTROL 0xe000ed14u\r
+#define CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18u\r
+#define CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1cu\r
+#define CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20u\r
+#define CYDEV_NVIC_SYS_HANDLER_CSR 0xe000ed24u\r
+#define CYDEV_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28u\r
+#define CYDEV_NVIC_BUS_FAULT_STATUS 0xe000ed29u\r
+#define CYDEV_NVIC_USAGE_FAULT_STATUS 0xe000ed2au\r
+#define CYDEV_NVIC_HARD_FAULT_STATUS 0xe000ed2cu\r
+#define CYDEV_NVIC_DEBUG_FAULT_STATUS 0xe000ed30u\r
+#define CYDEV_NVIC_MEMMAN_FAULT_ADD 0xe000ed34u\r
+#define CYDEV_NVIC_BUS_FAULT_ADD 0xe000ed38u\r
+#define CYDEV_CORE_DBG_BASE 0xe000edf0u\r
+#define CYDEV_CORE_DBG_SIZE 0x00000010u\r
+#define CYDEV_CORE_DBG_DBG_HLT_CS 0xe000edf0u\r
+#define CYDEV_CORE_DBG_DBG_REG_SEL 0xe000edf4u\r
+#define CYDEV_CORE_DBG_DBG_REG_DATA 0xe000edf8u\r
+#define CYDEV_CORE_DBG_EXC_MON_CTL 0xe000edfcu\r
+#define CYDEV_TPIU_BASE 0xe0040000u\r
+#define CYDEV_TPIU_SIZE 0x00001000u\r
+#define CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000u\r
+#define CYDEV_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004u\r
+#define CYDEV_TPIU_ASYNC_CLK_PRESCALER 0xe0040010u\r
+#define CYDEV_TPIU_PROTOCOL 0xe00400f0u\r
+#define CYDEV_TPIU_FORM_FLUSH_STAT 0xe0040300u\r
+#define CYDEV_TPIU_FORM_FLUSH_CTRL 0xe0040304u\r
+#define CYDEV_TPIU_TRIGGER 0xe0040ee8u\r
+#define CYDEV_TPIU_ITETMDATA 0xe0040eecu\r
+#define CYDEV_TPIU_ITATBCTR2 0xe0040ef0u\r
+#define CYDEV_TPIU_ITATBCTR0 0xe0040ef8u\r
+#define CYDEV_TPIU_ITITMDATA 0xe0040efcu\r
+#define CYDEV_TPIU_ITCTRL 0xe0040f00u\r
+#define CYDEV_TPIU_DEVID 0xe0040fc8u\r
+#define CYDEV_TPIU_DEVTYPE 0xe0040fccu\r
+#define CYDEV_TPIU_PID4 0xe0040fd0u\r
+#define CYDEV_TPIU_PID5 0xe0040fd4u\r
+#define CYDEV_TPIU_PID6 0xe0040fd8u\r
+#define CYDEV_TPIU_PID7 0xe0040fdcu\r
+#define CYDEV_TPIU_PID0 0xe0040fe0u\r
+#define CYDEV_TPIU_PID1 0xe0040fe4u\r
+#define CYDEV_TPIU_PID2 0xe0040fe8u\r
+#define CYDEV_TPIU_PID3 0xe0040fecu\r
+#define CYDEV_TPIU_CID0 0xe0040ff0u\r
+#define CYDEV_TPIU_CID1 0xe0040ff4u\r
+#define CYDEV_TPIU_CID2 0xe0040ff8u\r
+#define CYDEV_TPIU_CID3 0xe0040ffcu\r
+#define CYDEV_ETM_BASE 0xe0041000u\r
+#define CYDEV_ETM_SIZE 0x00001000u\r
+#define CYDEV_ETM_CTL 0xe0041000u\r
+#define CYDEV_ETM_CFG_CODE 0xe0041004u\r
+#define CYDEV_ETM_TRIG_EVENT 0xe0041008u\r
+#define CYDEV_ETM_STATUS 0xe0041010u\r
+#define CYDEV_ETM_SYS_CFG 0xe0041014u\r
+#define CYDEV_ETM_TRACE_ENB_EVENT 0xe0041020u\r
+#define CYDEV_ETM_TRACE_EN_CTRL1 0xe0041024u\r
+#define CYDEV_ETM_FIFOFULL_LEVEL 0xe004102cu\r
+#define CYDEV_ETM_SYNC_FREQ 0xe00411e0u\r
+#define CYDEV_ETM_ETM_ID 0xe00411e4u\r
+#define CYDEV_ETM_CFG_CODE_EXT 0xe00411e8u\r
+#define CYDEV_ETM_TR_SS_EMBICE_CTRL 0xe00411f0u\r
+#define CYDEV_ETM_CS_TRACE_ID 0xe0041200u\r
+#define CYDEV_ETM_OS_LOCK_ACCESS 0xe0041300u\r
+#define CYDEV_ETM_OS_LOCK_STATUS 0xe0041304u\r
+#define CYDEV_ETM_PDSR 0xe0041314u\r
+#define CYDEV_ETM_ITMISCIN 0xe0041ee0u\r
+#define CYDEV_ETM_ITTRIGOUT 0xe0041ee8u\r
+#define CYDEV_ETM_ITATBCTR2 0xe0041ef0u\r
+#define CYDEV_ETM_ITATBCTR0 0xe0041ef8u\r
+#define CYDEV_ETM_INT_MODE_CTRL 0xe0041f00u\r
+#define CYDEV_ETM_CLM_TAG_SET 0xe0041fa0u\r
+#define CYDEV_ETM_CLM_TAG_CLR 0xe0041fa4u\r
+#define CYDEV_ETM_LOCK_ACCESS 0xe0041fb0u\r
+#define CYDEV_ETM_LOCK_STATUS 0xe0041fb4u\r
+#define CYDEV_ETM_AUTH_STATUS 0xe0041fb8u\r
+#define CYDEV_ETM_DEV_TYPE 0xe0041fccu\r
+#define CYDEV_ETM_PID4 0xe0041fd0u\r
+#define CYDEV_ETM_PID5 0xe0041fd4u\r
+#define CYDEV_ETM_PID6 0xe0041fd8u\r
+#define CYDEV_ETM_PID7 0xe0041fdcu\r
+#define CYDEV_ETM_PID0 0xe0041fe0u\r
+#define CYDEV_ETM_PID1 0xe0041fe4u\r
+#define CYDEV_ETM_PID2 0xe0041fe8u\r
+#define CYDEV_ETM_PID3 0xe0041fecu\r
+#define CYDEV_ETM_CID0 0xe0041ff0u\r
+#define CYDEV_ETM_CID1 0xe0041ff4u\r
+#define CYDEV_ETM_CID2 0xe0041ff8u\r
+#define CYDEV_ETM_CID3 0xe0041ffcu\r
+#define CYDEV_ROM_TABLE_BASE 0xe00ff000u\r
+#define CYDEV_ROM_TABLE_SIZE 0x00001000u\r
+#define CYDEV_ROM_TABLE_NVIC 0xe00ff000u\r
+#define CYDEV_ROM_TABLE_DWT 0xe00ff004u\r
+#define CYDEV_ROM_TABLE_FPB 0xe00ff008u\r
+#define CYDEV_ROM_TABLE_ITM 0xe00ff00cu\r
+#define CYDEV_ROM_TABLE_TPIU 0xe00ff010u\r
+#define CYDEV_ROM_TABLE_ETM 0xe00ff014u\r
+#define CYDEV_ROM_TABLE_END 0xe00ff018u\r
+#define CYDEV_ROM_TABLE_MEMTYPE 0xe00fffccu\r
+#define CYDEV_ROM_TABLE_PID4 0xe00fffd0u\r
+#define CYDEV_ROM_TABLE_PID5 0xe00fffd4u\r
+#define CYDEV_ROM_TABLE_PID6 0xe00fffd8u\r
+#define CYDEV_ROM_TABLE_PID7 0xe00fffdcu\r
+#define CYDEV_ROM_TABLE_PID0 0xe00fffe0u\r
+#define CYDEV_ROM_TABLE_PID1 0xe00fffe4u\r
+#define CYDEV_ROM_TABLE_PID2 0xe00fffe8u\r
+#define CYDEV_ROM_TABLE_PID3 0xe00fffecu\r
+#define CYDEV_ROM_TABLE_CID0 0xe00ffff0u\r
+#define CYDEV_ROM_TABLE_CID1 0xe00ffff4u\r
+#define CYDEV_ROM_TABLE_CID2 0xe00ffff8u\r
+#define CYDEV_ROM_TABLE_CID3 0xe00ffffcu\r
+#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE\r
+#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE\r
+#define CYDEV_FLS_SECTOR_SIZE 0x00010000u\r
+#define CYDEV_FLS_ROW_SIZE 0x00000100u\r
+#define CYDEV_ECC_SECTOR_SIZE 0x00002000u\r
+#define CYDEV_ECC_ROW_SIZE 0x00000020u\r
+#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u\r
+#define CYDEV_EEPROM_ROW_SIZE 0x00000010u\r
+#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE\r
+#define CYCLK_LD_DISABLE 0x00000004u\r
+#define CYCLK_LD_SYNC_EN 0x00000002u\r
+#define CYCLK_LD_LOAD 0x00000001u\r
+#define CYCLK_PIPE 0x00000080u\r
+#define CYCLK_SSS 0x00000040u\r
+#define CYCLK_EARLY 0x00000020u\r
+#define CYCLK_DUTY 0x00000010u\r
+#define CYCLK_SYNC 0x00000008u\r
+#define CYCLK_SRC_SEL_CLK_SYNC_D 0\r
+#define CYCLK_SRC_SEL_SYNC_DIG 0\r
+#define CYCLK_SRC_SEL_IMO 1\r
+#define CYCLK_SRC_SEL_XTAL_MHZ 2\r
+#define CYCLK_SRC_SEL_XTALM 2\r
+#define CYCLK_SRC_SEL_ILO 3\r
+#define CYCLK_SRC_SEL_PLL 4\r
+#define CYCLK_SRC_SEL_XTAL_KHZ 5\r
+#define CYCLK_SRC_SEL_XTALK 5\r
+#define CYCLK_SRC_SEL_DSI_G 6\r
+#define CYCLK_SRC_SEL_DSI_D 7\r
+#define CYCLK_SRC_SEL_CLK_SYNC_A 0\r
+#define CYCLK_SRC_SEL_DSI_A 7\r
+#endif /* CYDEVICE_H */\r
--- /dev/null
+/*******************************************************************************\r
+* FILENAME: cydevice_trm.h\r
+* \r
+* PSoC Creator 2.2 Component Pack 6\r
+*\r
+* DESCRIPTION:\r
+* This file provides all of the address values for the entire PSoC device.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+********************************************************************************/\r
+\r
+#if !defined(CYDEVICE_TRM_H)\r
+#define CYDEVICE_TRM_H\r
+#define CYDEV_FLASH_BASE 0x00000000u\r
+#define CYDEV_FLASH_SIZE 0x00040000u\r
+#define CYREG_FLASH_DATA_MBASE 0x00000000u\r
+#define CYREG_FLASH_DATA_MSIZE 0x00040000u\r
+#define CYDEV_SRAM_BASE 0x1fff8000u\r
+#define CYDEV_SRAM_SIZE 0x00010000u\r
+#define CYREG_SRAM_CODE64K_MBASE 0x1fff8000u\r
+#define CYREG_SRAM_CODE64K_MSIZE 0x00004000u\r
+#define CYREG_SRAM_CODE32K_MBASE 0x1fffc000u\r
+#define CYREG_SRAM_CODE32K_MSIZE 0x00002000u\r
+#define CYREG_SRAM_CODE16K_MBASE 0x1fffe000u\r
+#define CYREG_SRAM_CODE16K_MSIZE 0x00001000u\r
+#define CYREG_SRAM_CODE_MBASE 0x1fff8000u\r
+#define CYREG_SRAM_CODE_MSIZE 0x00008000u\r
+#define CYREG_SRAM_DATA_MBASE 0x20000000u\r
+#define CYREG_SRAM_DATA_MSIZE 0x00008000u\r
+#define CYREG_SRAM_DATA16K_MBASE 0x20001000u\r
+#define CYREG_SRAM_DATA16K_MSIZE 0x00001000u\r
+#define CYREG_SRAM_DATA32K_MBASE 0x20002000u\r
+#define CYREG_SRAM_DATA32K_MSIZE 0x00002000u\r
+#define CYREG_SRAM_DATA64K_MBASE 0x20004000u\r
+#define CYREG_SRAM_DATA64K_MSIZE 0x00004000u\r
+#define CYDEV_DMA_BASE 0x20008000u\r
+#define CYDEV_DMA_SIZE 0x00008000u\r
+#define CYREG_DMA_SRAM64K_MBASE 0x20008000u\r
+#define CYREG_DMA_SRAM64K_MSIZE 0x00004000u\r
+#define CYREG_DMA_SRAM32K_MBASE 0x2000c000u\r
+#define CYREG_DMA_SRAM32K_MSIZE 0x00002000u\r
+#define CYREG_DMA_SRAM16K_MBASE 0x2000e000u\r
+#define CYREG_DMA_SRAM16K_MSIZE 0x00001000u\r
+#define CYREG_DMA_SRAM_MBASE 0x2000f000u\r
+#define CYREG_DMA_SRAM_MSIZE 0x00001000u\r
+#define CYDEV_CLKDIST_BASE 0x40004000u\r
+#define CYDEV_CLKDIST_SIZE 0x00000110u\r
+#define CYREG_CLKDIST_CR 0x40004000u\r
+#define CYREG_CLKDIST_LD 0x40004001u\r
+#define CYREG_CLKDIST_WRK0 0x40004002u\r
+#define CYREG_CLKDIST_WRK1 0x40004003u\r
+#define CYREG_CLKDIST_MSTR0 0x40004004u\r
+#define CYREG_CLKDIST_MSTR1 0x40004005u\r
+#define CYREG_CLKDIST_BCFG0 0x40004006u\r
+#define CYREG_CLKDIST_BCFG1 0x40004007u\r
+#define CYREG_CLKDIST_BCFG2 0x40004008u\r
+#define CYREG_CLKDIST_UCFG 0x40004009u\r
+#define CYREG_CLKDIST_DLY0 0x4000400au\r
+#define CYREG_CLKDIST_DLY1 0x4000400bu\r
+#define CYREG_CLKDIST_DMASK 0x40004010u\r
+#define CYREG_CLKDIST_AMASK 0x40004014u\r
+#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080u\r
+#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003u\r
+#define CYREG_CLKDIST_DCFG0_CFG0 0x40004080u\r
+#define CYREG_CLKDIST_DCFG0_CFG1 0x40004081u\r
+#define CYREG_CLKDIST_DCFG0_CFG2 0x40004082u\r
+#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084u\r
+#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003u\r
+#define CYREG_CLKDIST_DCFG1_CFG0 0x40004084u\r
+#define CYREG_CLKDIST_DCFG1_CFG1 0x40004085u\r
+#define CYREG_CLKDIST_DCFG1_CFG2 0x40004086u\r
+#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088u\r
+#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003u\r
+#define CYREG_CLKDIST_DCFG2_CFG0 0x40004088u\r
+#define CYREG_CLKDIST_DCFG2_CFG1 0x40004089u\r
+#define CYREG_CLKDIST_DCFG2_CFG2 0x4000408au\r
+#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408cu\r
+#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003u\r
+#define CYREG_CLKDIST_DCFG3_CFG0 0x4000408cu\r
+#define CYREG_CLKDIST_DCFG3_CFG1 0x4000408du\r
+#define CYREG_CLKDIST_DCFG3_CFG2 0x4000408eu\r
+#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090u\r
+#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003u\r
+#define CYREG_CLKDIST_DCFG4_CFG0 0x40004090u\r
+#define CYREG_CLKDIST_DCFG4_CFG1 0x40004091u\r
+#define CYREG_CLKDIST_DCFG4_CFG2 0x40004092u\r
+#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094u\r
+#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003u\r
+#define CYREG_CLKDIST_DCFG5_CFG0 0x40004094u\r
+#define CYREG_CLKDIST_DCFG5_CFG1 0x40004095u\r
+#define CYREG_CLKDIST_DCFG5_CFG2 0x40004096u\r
+#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098u\r
+#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003u\r
+#define CYREG_CLKDIST_DCFG6_CFG0 0x40004098u\r
+#define CYREG_CLKDIST_DCFG6_CFG1 0x40004099u\r
+#define CYREG_CLKDIST_DCFG6_CFG2 0x4000409au\r
+#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409cu\r
+#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003u\r
+#define CYREG_CLKDIST_DCFG7_CFG0 0x4000409cu\r
+#define CYREG_CLKDIST_DCFG7_CFG1 0x4000409du\r
+#define CYREG_CLKDIST_DCFG7_CFG2 0x4000409eu\r
+#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100u\r
+#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004u\r
+#define CYREG_CLKDIST_ACFG0_CFG0 0x40004100u\r
+#define CYREG_CLKDIST_ACFG0_CFG1 0x40004101u\r
+#define CYREG_CLKDIST_ACFG0_CFG2 0x40004102u\r
+#define CYREG_CLKDIST_ACFG0_CFG3 0x40004103u\r
+#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104u\r
+#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004u\r
+#define CYREG_CLKDIST_ACFG1_CFG0 0x40004104u\r
+#define CYREG_CLKDIST_ACFG1_CFG1 0x40004105u\r
+#define CYREG_CLKDIST_ACFG1_CFG2 0x40004106u\r
+#define CYREG_CLKDIST_ACFG1_CFG3 0x40004107u\r
+#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108u\r
+#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004u\r
+#define CYREG_CLKDIST_ACFG2_CFG0 0x40004108u\r
+#define CYREG_CLKDIST_ACFG2_CFG1 0x40004109u\r
+#define CYREG_CLKDIST_ACFG2_CFG2 0x4000410au\r
+#define CYREG_CLKDIST_ACFG2_CFG3 0x4000410bu\r
+#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410cu\r
+#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004u\r
+#define CYREG_CLKDIST_ACFG3_CFG0 0x4000410cu\r
+#define CYREG_CLKDIST_ACFG3_CFG1 0x4000410du\r
+#define CYREG_CLKDIST_ACFG3_CFG2 0x4000410eu\r
+#define CYREG_CLKDIST_ACFG3_CFG3 0x4000410fu\r
+#define CYDEV_FASTCLK_BASE 0x40004200u\r
+#define CYDEV_FASTCLK_SIZE 0x00000026u\r
+#define CYDEV_FASTCLK_IMO_BASE 0x40004200u\r
+#define CYDEV_FASTCLK_IMO_SIZE 0x00000001u\r
+#define CYREG_FASTCLK_IMO_CR 0x40004200u\r
+#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210u\r
+#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004u\r
+#define CYREG_FASTCLK_XMHZ_CSR 0x40004210u\r
+#define CYREG_FASTCLK_XMHZ_CFG0 0x40004212u\r
+#define CYREG_FASTCLK_XMHZ_CFG1 0x40004213u\r
+#define CYDEV_FASTCLK_PLL_BASE 0x40004220u\r
+#define CYDEV_FASTCLK_PLL_SIZE 0x00000006u\r
+#define CYREG_FASTCLK_PLL_CFG0 0x40004220u\r
+#define CYREG_FASTCLK_PLL_CFG1 0x40004221u\r
+#define CYREG_FASTCLK_PLL_P 0x40004222u\r
+#define CYREG_FASTCLK_PLL_Q 0x40004223u\r
+#define CYREG_FASTCLK_PLL_SR 0x40004225u\r
+#define CYDEV_SLOWCLK_BASE 0x40004300u\r
+#define CYDEV_SLOWCLK_SIZE 0x0000000bu\r
+#define CYDEV_SLOWCLK_ILO_BASE 0x40004300u\r
+#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002u\r
+#define CYREG_SLOWCLK_ILO_CR0 0x40004300u\r
+#define CYREG_SLOWCLK_ILO_CR1 0x40004301u\r
+#define CYDEV_SLOWCLK_X32_BASE 0x40004308u\r
+#define CYDEV_SLOWCLK_X32_SIZE 0x00000003u\r
+#define CYREG_SLOWCLK_X32_CR 0x40004308u\r
+#define CYREG_SLOWCLK_X32_CFG 0x40004309u\r
+#define CYREG_SLOWCLK_X32_TST 0x4000430au\r
+#define CYDEV_BOOST_BASE 0x40004320u\r
+#define CYDEV_BOOST_SIZE 0x00000007u\r
+#define CYREG_BOOST_CR0 0x40004320u\r
+#define CYREG_BOOST_CR1 0x40004321u\r
+#define CYREG_BOOST_CR2 0x40004322u\r
+#define CYREG_BOOST_CR3 0x40004323u\r
+#define CYREG_BOOST_SR 0x40004324u\r
+#define CYREG_BOOST_CR4 0x40004325u\r
+#define CYREG_BOOST_SR2 0x40004326u\r
+#define CYDEV_PWRSYS_BASE 0x40004330u\r
+#define CYDEV_PWRSYS_SIZE 0x00000002u\r
+#define CYREG_PWRSYS_CR0 0x40004330u\r
+#define CYREG_PWRSYS_CR1 0x40004331u\r
+#define CYDEV_PM_BASE 0x40004380u\r
+#define CYDEV_PM_SIZE 0x00000057u\r
+#define CYREG_PM_TW_CFG0 0x40004380u\r
+#define CYREG_PM_TW_CFG1 0x40004381u\r
+#define CYREG_PM_TW_CFG2 0x40004382u\r
+#define CYREG_PM_WDT_CFG 0x40004383u\r
+#define CYREG_PM_WDT_CR 0x40004384u\r
+#define CYREG_PM_INT_SR 0x40004390u\r
+#define CYREG_PM_MODE_CFG0 0x40004391u\r
+#define CYREG_PM_MODE_CFG1 0x40004392u\r
+#define CYREG_PM_MODE_CSR 0x40004393u\r
+#define CYREG_PM_USB_CR0 0x40004394u\r
+#define CYREG_PM_WAKEUP_CFG0 0x40004398u\r
+#define CYREG_PM_WAKEUP_CFG1 0x40004399u\r
+#define CYREG_PM_WAKEUP_CFG2 0x4000439au\r
+#define CYDEV_PM_ACT_BASE 0x400043a0u\r
+#define CYDEV_PM_ACT_SIZE 0x0000000eu\r
+#define CYREG_PM_ACT_CFG0 0x400043a0u\r
+#define CYREG_PM_ACT_CFG1 0x400043a1u\r
+#define CYREG_PM_ACT_CFG2 0x400043a2u\r
+#define CYREG_PM_ACT_CFG3 0x400043a3u\r
+#define CYREG_PM_ACT_CFG4 0x400043a4u\r
+#define CYREG_PM_ACT_CFG5 0x400043a5u\r
+#define CYREG_PM_ACT_CFG6 0x400043a6u\r
+#define CYREG_PM_ACT_CFG7 0x400043a7u\r
+#define CYREG_PM_ACT_CFG8 0x400043a8u\r
+#define CYREG_PM_ACT_CFG9 0x400043a9u\r
+#define CYREG_PM_ACT_CFG10 0x400043aau\r
+#define CYREG_PM_ACT_CFG11 0x400043abu\r
+#define CYREG_PM_ACT_CFG12 0x400043acu\r
+#define CYREG_PM_ACT_CFG13 0x400043adu\r
+#define CYDEV_PM_STBY_BASE 0x400043b0u\r
+#define CYDEV_PM_STBY_SIZE 0x0000000eu\r
+#define CYREG_PM_STBY_CFG0 0x400043b0u\r
+#define CYREG_PM_STBY_CFG1 0x400043b1u\r
+#define CYREG_PM_STBY_CFG2 0x400043b2u\r
+#define CYREG_PM_STBY_CFG3 0x400043b3u\r
+#define CYREG_PM_STBY_CFG4 0x400043b4u\r
+#define CYREG_PM_STBY_CFG5 0x400043b5u\r
+#define CYREG_PM_STBY_CFG6 0x400043b6u\r
+#define CYREG_PM_STBY_CFG7 0x400043b7u\r
+#define CYREG_PM_STBY_CFG8 0x400043b8u\r
+#define CYREG_PM_STBY_CFG9 0x400043b9u\r
+#define CYREG_PM_STBY_CFG10 0x400043bau\r
+#define CYREG_PM_STBY_CFG11 0x400043bbu\r
+#define CYREG_PM_STBY_CFG12 0x400043bcu\r
+#define CYREG_PM_STBY_CFG13 0x400043bdu\r
+#define CYDEV_PM_AVAIL_BASE 0x400043c0u\r
+#define CYDEV_PM_AVAIL_SIZE 0x00000017u\r
+#define CYREG_PM_AVAIL_CR0 0x400043c0u\r
+#define CYREG_PM_AVAIL_CR1 0x400043c1u\r
+#define CYREG_PM_AVAIL_CR2 0x400043c2u\r
+#define CYREG_PM_AVAIL_CR3 0x400043c3u\r
+#define CYREG_PM_AVAIL_CR4 0x400043c4u\r
+#define CYREG_PM_AVAIL_CR5 0x400043c5u\r
+#define CYREG_PM_AVAIL_CR6 0x400043c6u\r
+#define CYREG_PM_AVAIL_SR0 0x400043d0u\r
+#define CYREG_PM_AVAIL_SR1 0x400043d1u\r
+#define CYREG_PM_AVAIL_SR2 0x400043d2u\r
+#define CYREG_PM_AVAIL_SR3 0x400043d3u\r
+#define CYREG_PM_AVAIL_SR4 0x400043d4u\r
+#define CYREG_PM_AVAIL_SR5 0x400043d5u\r
+#define CYREG_PM_AVAIL_SR6 0x400043d6u\r
+#define CYDEV_PICU_BASE 0x40004500u\r
+#define CYDEV_PICU_SIZE 0x000000b0u\r
+#define CYDEV_PICU_INTTYPE_BASE 0x40004500u\r
+#define CYDEV_PICU_INTTYPE_SIZE 0x00000080u\r
+#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500u\r
+#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008u\r
+#define CYREG_PICU0_INTTYPE0 0x40004500u\r
+#define CYREG_PICU0_INTTYPE1 0x40004501u\r
+#define CYREG_PICU0_INTTYPE2 0x40004502u\r
+#define CYREG_PICU0_INTTYPE3 0x40004503u\r
+#define CYREG_PICU0_INTTYPE4 0x40004504u\r
+#define CYREG_PICU0_INTTYPE5 0x40004505u\r
+#define CYREG_PICU0_INTTYPE6 0x40004506u\r
+#define CYREG_PICU0_INTTYPE7 0x40004507u\r
+#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508u\r
+#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008u\r
+#define CYREG_PICU1_INTTYPE0 0x40004508u\r
+#define CYREG_PICU1_INTTYPE1 0x40004509u\r
+#define CYREG_PICU1_INTTYPE2 0x4000450au\r
+#define CYREG_PICU1_INTTYPE3 0x4000450bu\r
+#define CYREG_PICU1_INTTYPE4 0x4000450cu\r
+#define CYREG_PICU1_INTTYPE5 0x4000450du\r
+#define CYREG_PICU1_INTTYPE6 0x4000450eu\r
+#define CYREG_PICU1_INTTYPE7 0x4000450fu\r
+#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510u\r
+#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008u\r
+#define CYREG_PICU2_INTTYPE0 0x40004510u\r
+#define CYREG_PICU2_INTTYPE1 0x40004511u\r
+#define CYREG_PICU2_INTTYPE2 0x40004512u\r
+#define CYREG_PICU2_INTTYPE3 0x40004513u\r
+#define CYREG_PICU2_INTTYPE4 0x40004514u\r
+#define CYREG_PICU2_INTTYPE5 0x40004515u\r
+#define CYREG_PICU2_INTTYPE6 0x40004516u\r
+#define CYREG_PICU2_INTTYPE7 0x40004517u\r
+#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518u\r
+#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008u\r
+#define CYREG_PICU3_INTTYPE0 0x40004518u\r
+#define CYREG_PICU3_INTTYPE1 0x40004519u\r
+#define CYREG_PICU3_INTTYPE2 0x4000451au\r
+#define CYREG_PICU3_INTTYPE3 0x4000451bu\r
+#define CYREG_PICU3_INTTYPE4 0x4000451cu\r
+#define CYREG_PICU3_INTTYPE5 0x4000451du\r
+#define CYREG_PICU3_INTTYPE6 0x4000451eu\r
+#define CYREG_PICU3_INTTYPE7 0x4000451fu\r
+#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520u\r
+#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008u\r
+#define CYREG_PICU4_INTTYPE0 0x40004520u\r
+#define CYREG_PICU4_INTTYPE1 0x40004521u\r
+#define CYREG_PICU4_INTTYPE2 0x40004522u\r
+#define CYREG_PICU4_INTTYPE3 0x40004523u\r
+#define CYREG_PICU4_INTTYPE4 0x40004524u\r
+#define CYREG_PICU4_INTTYPE5 0x40004525u\r
+#define CYREG_PICU4_INTTYPE6 0x40004526u\r
+#define CYREG_PICU4_INTTYPE7 0x40004527u\r
+#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528u\r
+#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008u\r
+#define CYREG_PICU5_INTTYPE0 0x40004528u\r
+#define CYREG_PICU5_INTTYPE1 0x40004529u\r
+#define CYREG_PICU5_INTTYPE2 0x4000452au\r
+#define CYREG_PICU5_INTTYPE3 0x4000452bu\r
+#define CYREG_PICU5_INTTYPE4 0x4000452cu\r
+#define CYREG_PICU5_INTTYPE5 0x4000452du\r
+#define CYREG_PICU5_INTTYPE6 0x4000452eu\r
+#define CYREG_PICU5_INTTYPE7 0x4000452fu\r
+#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530u\r
+#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008u\r
+#define CYREG_PICU6_INTTYPE0 0x40004530u\r
+#define CYREG_PICU6_INTTYPE1 0x40004531u\r
+#define CYREG_PICU6_INTTYPE2 0x40004532u\r
+#define CYREG_PICU6_INTTYPE3 0x40004533u\r
+#define CYREG_PICU6_INTTYPE4 0x40004534u\r
+#define CYREG_PICU6_INTTYPE5 0x40004535u\r
+#define CYREG_PICU6_INTTYPE6 0x40004536u\r
+#define CYREG_PICU6_INTTYPE7 0x40004537u\r
+#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560u\r
+#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008u\r
+#define CYREG_PICU12_INTTYPE0 0x40004560u\r
+#define CYREG_PICU12_INTTYPE1 0x40004561u\r
+#define CYREG_PICU12_INTTYPE2 0x40004562u\r
+#define CYREG_PICU12_INTTYPE3 0x40004563u\r
+#define CYREG_PICU12_INTTYPE4 0x40004564u\r
+#define CYREG_PICU12_INTTYPE5 0x40004565u\r
+#define CYREG_PICU12_INTTYPE6 0x40004566u\r
+#define CYREG_PICU12_INTTYPE7 0x40004567u\r
+#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578u\r
+#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008u\r
+#define CYREG_PICU15_INTTYPE0 0x40004578u\r
+#define CYREG_PICU15_INTTYPE1 0x40004579u\r
+#define CYREG_PICU15_INTTYPE2 0x4000457au\r
+#define CYREG_PICU15_INTTYPE3 0x4000457bu\r
+#define CYREG_PICU15_INTTYPE4 0x4000457cu\r
+#define CYREG_PICU15_INTTYPE5 0x4000457du\r
+#define CYREG_PICU15_INTTYPE6 0x4000457eu\r
+#define CYREG_PICU15_INTTYPE7 0x4000457fu\r
+#define CYDEV_PICU_STAT_BASE 0x40004580u\r
+#define CYDEV_PICU_STAT_SIZE 0x00000010u\r
+#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580u\r
+#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001u\r
+#define CYREG_PICU0_INTSTAT 0x40004580u\r
+#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581u\r
+#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001u\r
+#define CYREG_PICU1_INTSTAT 0x40004581u\r
+#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582u\r
+#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001u\r
+#define CYREG_PICU2_INTSTAT 0x40004582u\r
+#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583u\r
+#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001u\r
+#define CYREG_PICU3_INTSTAT 0x40004583u\r
+#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584u\r
+#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001u\r
+#define CYREG_PICU4_INTSTAT 0x40004584u\r
+#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585u\r
+#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001u\r
+#define CYREG_PICU5_INTSTAT 0x40004585u\r
+#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586u\r
+#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001u\r
+#define CYREG_PICU6_INTSTAT 0x40004586u\r
+#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458cu\r
+#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001u\r
+#define CYREG_PICU12_INTSTAT 0x4000458cu\r
+#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458fu\r
+#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001u\r
+#define CYREG_PICU15_INTSTAT 0x4000458fu\r
+#define CYDEV_PICU_SNAP_BASE 0x40004590u\r
+#define CYDEV_PICU_SNAP_SIZE 0x00000010u\r
+#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590u\r
+#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001u\r
+#define CYREG_PICU0_SNAP 0x40004590u\r
+#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591u\r
+#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001u\r
+#define CYREG_PICU1_SNAP 0x40004591u\r
+#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592u\r
+#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001u\r
+#define CYREG_PICU2_SNAP 0x40004592u\r
+#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593u\r
+#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001u\r
+#define CYREG_PICU3_SNAP 0x40004593u\r
+#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594u\r
+#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001u\r
+#define CYREG_PICU4_SNAP 0x40004594u\r
+#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595u\r
+#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001u\r
+#define CYREG_PICU5_SNAP 0x40004595u\r
+#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596u\r
+#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001u\r
+#define CYREG_PICU6_SNAP 0x40004596u\r
+#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459cu\r
+#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001u\r
+#define CYREG_PICU12_SNAP 0x4000459cu\r
+#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459fu\r
+#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001u\r
+#define CYREG_PICU_15_SNAP_15 0x4000459fu\r
+#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0u\r
+#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010u\r
+#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0u\r
+#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001u\r
+#define CYREG_PICU0_DISABLE_COR 0x400045a0u\r
+#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1u\r
+#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001u\r
+#define CYREG_PICU1_DISABLE_COR 0x400045a1u\r
+#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2u\r
+#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001u\r
+#define CYREG_PICU2_DISABLE_COR 0x400045a2u\r
+#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3u\r
+#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001u\r
+#define CYREG_PICU3_DISABLE_COR 0x400045a3u\r
+#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4u\r
+#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001u\r
+#define CYREG_PICU4_DISABLE_COR 0x400045a4u\r
+#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5u\r
+#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001u\r
+#define CYREG_PICU5_DISABLE_COR 0x400045a5u\r
+#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6u\r
+#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001u\r
+#define CYREG_PICU6_DISABLE_COR 0x400045a6u\r
+#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045acu\r
+#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001u\r
+#define CYREG_PICU12_DISABLE_COR 0x400045acu\r
+#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045afu\r
+#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001u\r
+#define CYREG_PICU15_DISABLE_COR 0x400045afu\r
+#define CYDEV_MFGCFG_BASE 0x40004600u\r
+#define CYDEV_MFGCFG_SIZE 0x000000edu\r
+#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600u\r
+#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038u\r
+#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608u\r
+#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001u\r
+#define CYREG_DAC0_TR 0x40004608u\r
+#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609u\r
+#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001u\r
+#define CYREG_DAC1_TR 0x40004609u\r
+#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460au\r
+#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001u\r
+#define CYREG_DAC2_TR 0x4000460au\r
+#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460bu\r
+#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001u\r
+#define CYREG_DAC3_TR 0x4000460bu\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610u\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001u\r
+#define CYREG_NPUMP_DSM_TR0 0x40004610u\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611u\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001u\r
+#define CYREG_NPUMP_SC_TR0 0x40004611u\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612u\r
+#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001u\r
+#define CYREG_NPUMP_OPAMP_TR0 0x40004612u\r
+#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614u\r
+#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001u\r
+#define CYREG_SAR0_TR0 0x40004614u\r
+#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616u\r
+#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001u\r
+#define CYREG_SAR1_TR0 0x40004616u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002u\r
+#define CYREG_OPAMP0_TR0 0x40004620u\r
+#define CYREG_OPAMP0_TR1 0x40004621u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002u\r
+#define CYREG_OPAMP1_TR0 0x40004622u\r
+#define CYREG_OPAMP1_TR1 0x40004623u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002u\r
+#define CYREG_OPAMP2_TR0 0x40004624u\r
+#define CYREG_OPAMP2_TR1 0x40004625u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626u\r
+#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002u\r
+#define CYREG_OPAMP3_TR0 0x40004626u\r
+#define CYREG_OPAMP3_TR1 0x40004627u\r
+#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630u\r
+#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002u\r
+#define CYREG_CMP0_TR0 0x40004630u\r
+#define CYREG_CMP0_TR1 0x40004631u\r
+#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632u\r
+#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002u\r
+#define CYREG_CMP1_TR0 0x40004632u\r
+#define CYREG_CMP1_TR1 0x40004633u\r
+#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634u\r
+#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002u\r
+#define CYREG_CMP2_TR0 0x40004634u\r
+#define CYREG_CMP2_TR1 0x40004635u\r
+#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636u\r
+#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002u\r
+#define CYREG_CMP3_TR0 0x40004636u\r
+#define CYREG_CMP3_TR1 0x40004637u\r
+#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680u\r
+#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000bu\r
+#define CYREG_PWRSYS_HIB_TR0 0x40004680u\r
+#define CYREG_PWRSYS_HIB_TR1 0x40004681u\r
+#define CYREG_PWRSYS_I2C_TR 0x40004682u\r
+#define CYREG_PWRSYS_SLP_TR 0x40004683u\r
+#define CYREG_PWRSYS_BUZZ_TR 0x40004684u\r
+#define CYREG_PWRSYS_WAKE_TR0 0x40004685u\r
+#define CYREG_PWRSYS_WAKE_TR1 0x40004686u\r
+#define CYREG_PWRSYS_BREF_TR 0x40004687u\r
+#define CYREG_PWRSYS_BG_TR 0x40004688u\r
+#define CYREG_PWRSYS_WAKE_TR2 0x40004689u\r
+#define CYREG_PWRSYS_WAKE_TR3 0x4000468au\r
+#define CYDEV_MFGCFG_ILO_BASE 0x40004690u\r
+#define CYDEV_MFGCFG_ILO_SIZE 0x00000002u\r
+#define CYREG_ILO_TR0 0x40004690u\r
+#define CYREG_ILO_TR1 0x40004691u\r
+#define CYDEV_MFGCFG_X32_BASE 0x40004698u\r
+#define CYDEV_MFGCFG_X32_SIZE 0x00000001u\r
+#define CYREG_X32_TR 0x40004698u\r
+#define CYDEV_MFGCFG_IMO_BASE 0x400046a0u\r
+#define CYDEV_MFGCFG_IMO_SIZE 0x00000005u\r
+#define CYREG_IMO_TR0 0x400046a0u\r
+#define CYREG_IMO_TR1 0x400046a1u\r
+#define CYREG_IMO_GAIN 0x400046a2u\r
+#define CYREG_IMO_C36M 0x400046a3u\r
+#define CYREG_IMO_TR2 0x400046a4u\r
+#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8u\r
+#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001u\r
+#define CYREG_XMHZ_TR 0x400046a8u\r
+#define CYREG_MFGCFG_DLY 0x400046c0u\r
+#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0u\r
+#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000du\r
+#define CYREG_MLOGIC_DMPSTR 0x400046e2u\r
+#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4u\r
+#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002u\r
+#define CYREG_MLOGIC_SEG_CR 0x400046e4u\r
+#define CYREG_MLOGIC_SEG_CFG0 0x400046e5u\r
+#define CYREG_MLOGIC_DEBUG 0x400046e8u\r
+#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046eau\r
+#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001u\r
+#define CYREG_MLOGIC_CPU_SCR_CPU_SCR 0x400046eau\r
+#define CYREG_MLOGIC_REV_ID 0x400046ecu\r
+#define CYDEV_RESET_BASE 0x400046f0u\r
+#define CYDEV_RESET_SIZE 0x0000000fu\r
+#define CYREG_RESET_IPOR_CR0 0x400046f0u\r
+#define CYREG_RESET_IPOR_CR1 0x400046f1u\r
+#define CYREG_RESET_IPOR_CR2 0x400046f2u\r
+#define CYREG_RESET_IPOR_CR3 0x400046f3u\r
+#define CYREG_RESET_CR0 0x400046f4u\r
+#define CYREG_RESET_CR1 0x400046f5u\r
+#define CYREG_RESET_CR2 0x400046f6u\r
+#define CYREG_RESET_CR3 0x400046f7u\r
+#define CYREG_RESET_CR4 0x400046f8u\r
+#define CYREG_RESET_CR5 0x400046f9u\r
+#define CYREG_RESET_SR0 0x400046fau\r
+#define CYREG_RESET_SR1 0x400046fbu\r
+#define CYREG_RESET_SR2 0x400046fcu\r
+#define CYREG_RESET_SR3 0x400046fdu\r
+#define CYREG_RESET_TR 0x400046feu\r
+#define CYDEV_SPC_BASE 0x40004700u\r
+#define CYDEV_SPC_SIZE 0x00000100u\r
+#define CYREG_SPC_FM_EE_CR 0x40004700u\r
+#define CYREG_SPC_FM_EE_WAKE_CNT 0x40004701u\r
+#define CYREG_SPC_EE_SCR 0x40004702u\r
+#define CYREG_SPC_EE_ERR 0x40004703u\r
+#define CYREG_SPC_CPU_DATA 0x40004720u\r
+#define CYREG_SPC_DMA_DATA 0x40004721u\r
+#define CYREG_SPC_SR 0x40004722u\r
+#define CYREG_SPC_CR 0x40004723u\r
+#define CYDEV_SPC_DMM_MAP_BASE 0x40004780u\r
+#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080u\r
+#define CYREG_SPC_DMM_MAP_SRAM_MBASE 0x40004780u\r
+#define CYREG_SPC_DMM_MAP_SRAM_MSIZE 0x00000080u\r
+#define CYDEV_CACHE_BASE 0x40004800u\r
+#define CYDEV_CACHE_SIZE 0x0000009cu\r
+#define CYREG_CACHE_CC_CTL 0x40004800u\r
+#define CYREG_CACHE_ECC_CORR 0x40004880u\r
+#define CYREG_CACHE_ECC_ERR 0x40004888u\r
+#define CYREG_CACHE_FLASH_ERR 0x40004890u\r
+#define CYREG_CACHE_HITMISS 0x40004898u\r
+#define CYDEV_I2C_BASE 0x40004900u\r
+#define CYDEV_I2C_SIZE 0x000000e1u\r
+#define CYREG_I2C_XCFG 0x400049c8u\r
+#define CYREG_I2C_ADR 0x400049cau\r
+#define CYREG_I2C_CFG 0x400049d6u\r
+#define CYREG_I2C_CSR 0x400049d7u\r
+#define CYREG_I2C_D 0x400049d8u\r
+#define CYREG_I2C_MCSR 0x400049d9u\r
+#define CYREG_I2C_CLK_DIV1 0x400049dbu\r
+#define CYREG_I2C_CLK_DIV2 0x400049dcu\r
+#define CYREG_I2C_TMOUT_CSR 0x400049ddu\r
+#define CYREG_I2C_TMOUT_SR 0x400049deu\r
+#define CYREG_I2C_TMOUT_CFG0 0x400049dfu\r
+#define CYREG_I2C_TMOUT_CFG1 0x400049e0u\r
+#define CYDEV_DEC_BASE 0x40004e00u\r
+#define CYDEV_DEC_SIZE 0x00000015u\r
+#define CYREG_DEC_CR 0x40004e00u\r
+#define CYREG_DEC_SR 0x40004e01u\r
+#define CYREG_DEC_SHIFT1 0x40004e02u\r
+#define CYREG_DEC_SHIFT2 0x40004e03u\r
+#define CYREG_DEC_DR2 0x40004e04u\r
+#define CYREG_DEC_DR2H 0x40004e05u\r
+#define CYREG_DEC_DR1 0x40004e06u\r
+#define CYREG_DEC_OCOR 0x40004e08u\r
+#define CYREG_DEC_OCORM 0x40004e09u\r
+#define CYREG_DEC_OCORH 0x40004e0au\r
+#define CYREG_DEC_GCOR 0x40004e0cu\r
+#define CYREG_DEC_GCORH 0x40004e0du\r
+#define CYREG_DEC_GVAL 0x40004e0eu\r
+#define CYREG_DEC_OUTSAMP 0x40004e10u\r
+#define CYREG_DEC_OUTSAMPM 0x40004e11u\r
+#define CYREG_DEC_OUTSAMPH 0x40004e12u\r
+#define CYREG_DEC_OUTSAMPS 0x40004e13u\r
+#define CYREG_DEC_COHER 0x40004e14u\r
+#define CYDEV_TMR0_BASE 0x40004f00u\r
+#define CYDEV_TMR0_SIZE 0x0000000cu\r
+#define CYREG_TMR0_CFG0 0x40004f00u\r
+#define CYREG_TMR0_CFG1 0x40004f01u\r
+#define CYREG_TMR0_CFG2 0x40004f02u\r
+#define CYREG_TMR0_SR0 0x40004f03u\r
+#define CYREG_TMR0_PER0 0x40004f04u\r
+#define CYREG_TMR0_PER1 0x40004f05u\r
+#define CYREG_TMR0_CNT_CMP0 0x40004f06u\r
+#define CYREG_TMR0_CNT_CMP1 0x40004f07u\r
+#define CYREG_TMR0_CAP0 0x40004f08u\r
+#define CYREG_TMR0_CAP1 0x40004f09u\r
+#define CYREG_TMR0_RT0 0x40004f0au\r
+#define CYREG_TMR0_RT1 0x40004f0bu\r
+#define CYDEV_TMR1_BASE 0x40004f0cu\r
+#define CYDEV_TMR1_SIZE 0x0000000cu\r
+#define CYREG_TMR1_CFG0 0x40004f0cu\r
+#define CYREG_TMR1_CFG1 0x40004f0du\r
+#define CYREG_TMR1_CFG2 0x40004f0eu\r
+#define CYREG_TMR1_SR0 0x40004f0fu\r
+#define CYREG_TMR1_PER0 0x40004f10u\r
+#define CYREG_TMR1_PER1 0x40004f11u\r
+#define CYREG_TMR1_CNT_CMP0 0x40004f12u\r
+#define CYREG_TMR1_CNT_CMP1 0x40004f13u\r
+#define CYREG_TMR1_CAP0 0x40004f14u\r
+#define CYREG_TMR1_CAP1 0x40004f15u\r
+#define CYREG_TMR1_RT0 0x40004f16u\r
+#define CYREG_TMR1_RT1 0x40004f17u\r
+#define CYDEV_TMR2_BASE 0x40004f18u\r
+#define CYDEV_TMR2_SIZE 0x0000000cu\r
+#define CYREG_TMR2_CFG0 0x40004f18u\r
+#define CYREG_TMR2_CFG1 0x40004f19u\r
+#define CYREG_TMR2_CFG2 0x40004f1au\r
+#define CYREG_TMR2_SR0 0x40004f1bu\r
+#define CYREG_TMR2_PER0 0x40004f1cu\r
+#define CYREG_TMR2_PER1 0x40004f1du\r
+#define CYREG_TMR2_CNT_CMP0 0x40004f1eu\r
+#define CYREG_TMR2_CNT_CMP1 0x40004f1fu\r
+#define CYREG_TMR2_CAP0 0x40004f20u\r
+#define CYREG_TMR2_CAP1 0x40004f21u\r
+#define CYREG_TMR2_RT0 0x40004f22u\r
+#define CYREG_TMR2_RT1 0x40004f23u\r
+#define CYDEV_TMR3_BASE 0x40004f24u\r
+#define CYDEV_TMR3_SIZE 0x0000000cu\r
+#define CYREG_TMR3_CFG0 0x40004f24u\r
+#define CYREG_TMR3_CFG1 0x40004f25u\r
+#define CYREG_TMR3_CFG2 0x40004f26u\r
+#define CYREG_TMR3_SR0 0x40004f27u\r
+#define CYREG_TMR3_PER0 0x40004f28u\r
+#define CYREG_TMR3_PER1 0x40004f29u\r
+#define CYREG_TMR3_CNT_CMP0 0x40004f2au\r
+#define CYREG_TMR3_CNT_CMP1 0x40004f2bu\r
+#define CYREG_TMR3_CAP0 0x40004f2cu\r
+#define CYREG_TMR3_CAP1 0x40004f2du\r
+#define CYREG_TMR3_RT0 0x40004f2eu\r
+#define CYREG_TMR3_RT1 0x40004f2fu\r
+#define CYDEV_IO_BASE 0x40005000u\r
+#define CYDEV_IO_SIZE 0x00000200u\r
+#define CYDEV_IO_PC_BASE 0x40005000u\r
+#define CYDEV_IO_PC_SIZE 0x00000080u\r
+#define CYDEV_IO_PC_PRT0_BASE 0x40005000u\r
+#define CYDEV_IO_PC_PRT0_SIZE 0x00000008u\r
+#define CYREG_PRT0_PC0 0x40005000u\r
+#define CYREG_PRT0_PC1 0x40005001u\r
+#define CYREG_PRT0_PC2 0x40005002u\r
+#define CYREG_PRT0_PC3 0x40005003u\r
+#define CYREG_PRT0_PC4 0x40005004u\r
+#define CYREG_PRT0_PC5 0x40005005u\r
+#define CYREG_PRT0_PC6 0x40005006u\r
+#define CYREG_PRT0_PC7 0x40005007u\r
+#define CYDEV_IO_PC_PRT1_BASE 0x40005008u\r
+#define CYDEV_IO_PC_PRT1_SIZE 0x00000008u\r
+#define CYREG_PRT1_PC0 0x40005008u\r
+#define CYREG_PRT1_PC1 0x40005009u\r
+#define CYREG_PRT1_PC2 0x4000500au\r
+#define CYREG_PRT1_PC3 0x4000500bu\r
+#define CYREG_PRT1_PC4 0x4000500cu\r
+#define CYREG_PRT1_PC5 0x4000500du\r
+#define CYREG_PRT1_PC6 0x4000500eu\r
+#define CYREG_PRT1_PC7 0x4000500fu\r
+#define CYDEV_IO_PC_PRT2_BASE 0x40005010u\r
+#define CYDEV_IO_PC_PRT2_SIZE 0x00000008u\r
+#define CYREG_PRT2_PC0 0x40005010u\r
+#define CYREG_PRT2_PC1 0x40005011u\r
+#define CYREG_PRT2_PC2 0x40005012u\r
+#define CYREG_PRT2_PC3 0x40005013u\r
+#define CYREG_PRT2_PC4 0x40005014u\r
+#define CYREG_PRT2_PC5 0x40005015u\r
+#define CYREG_PRT2_PC6 0x40005016u\r
+#define CYREG_PRT2_PC7 0x40005017u\r
+#define CYDEV_IO_PC_PRT3_BASE 0x40005018u\r
+#define CYDEV_IO_PC_PRT3_SIZE 0x00000008u\r
+#define CYREG_PRT3_PC0 0x40005018u\r
+#define CYREG_PRT3_PC1 0x40005019u\r
+#define CYREG_PRT3_PC2 0x4000501au\r
+#define CYREG_PRT3_PC3 0x4000501bu\r
+#define CYREG_PRT3_PC4 0x4000501cu\r
+#define CYREG_PRT3_PC5 0x4000501du\r
+#define CYREG_PRT3_PC6 0x4000501eu\r
+#define CYREG_PRT3_PC7 0x4000501fu\r
+#define CYDEV_IO_PC_PRT4_BASE 0x40005020u\r
+#define CYDEV_IO_PC_PRT4_SIZE 0x00000008u\r
+#define CYREG_PRT4_PC0 0x40005020u\r
+#define CYREG_PRT4_PC1 0x40005021u\r
+#define CYREG_PRT4_PC2 0x40005022u\r
+#define CYREG_PRT4_PC3 0x40005023u\r
+#define CYREG_PRT4_PC4 0x40005024u\r
+#define CYREG_PRT4_PC5 0x40005025u\r
+#define CYREG_PRT4_PC6 0x40005026u\r
+#define CYREG_PRT4_PC7 0x40005027u\r
+#define CYDEV_IO_PC_PRT5_BASE 0x40005028u\r
+#define CYDEV_IO_PC_PRT5_SIZE 0x00000008u\r
+#define CYREG_PRT5_PC0 0x40005028u\r
+#define CYREG_PRT5_PC1 0x40005029u\r
+#define CYREG_PRT5_PC2 0x4000502au\r
+#define CYREG_PRT5_PC3 0x4000502bu\r
+#define CYREG_PRT5_PC4 0x4000502cu\r
+#define CYREG_PRT5_PC5 0x4000502du\r
+#define CYREG_PRT5_PC6 0x4000502eu\r
+#define CYREG_PRT5_PC7 0x4000502fu\r
+#define CYDEV_IO_PC_PRT6_BASE 0x40005030u\r
+#define CYDEV_IO_PC_PRT6_SIZE 0x00000008u\r
+#define CYREG_PRT6_PC0 0x40005030u\r
+#define CYREG_PRT6_PC1 0x40005031u\r
+#define CYREG_PRT6_PC2 0x40005032u\r
+#define CYREG_PRT6_PC3 0x40005033u\r
+#define CYREG_PRT6_PC4 0x40005034u\r
+#define CYREG_PRT6_PC5 0x40005035u\r
+#define CYREG_PRT6_PC6 0x40005036u\r
+#define CYREG_PRT6_PC7 0x40005037u\r
+#define CYDEV_IO_PC_PRT12_BASE 0x40005060u\r
+#define CYDEV_IO_PC_PRT12_SIZE 0x00000008u\r
+#define CYREG_PRT12_PC0 0x40005060u\r
+#define CYREG_PRT12_PC1 0x40005061u\r
+#define CYREG_PRT12_PC2 0x40005062u\r
+#define CYREG_PRT12_PC3 0x40005063u\r
+#define CYREG_PRT12_PC4 0x40005064u\r
+#define CYREG_PRT12_PC5 0x40005065u\r
+#define CYREG_PRT12_PC6 0x40005066u\r
+#define CYREG_PRT12_PC7 0x40005067u\r
+#define CYDEV_IO_PC_PRT15_BASE 0x40005078u\r
+#define CYDEV_IO_PC_PRT15_SIZE 0x00000006u\r
+#define CYREG_IO_PC_PRT15_PC0 0x40005078u\r
+#define CYREG_IO_PC_PRT15_PC1 0x40005079u\r
+#define CYREG_IO_PC_PRT15_PC2 0x4000507au\r
+#define CYREG_IO_PC_PRT15_PC3 0x4000507bu\r
+#define CYREG_IO_PC_PRT15_PC4 0x4000507cu\r
+#define CYREG_IO_PC_PRT15_PC5 0x4000507du\r
+#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507eu\r
+#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002u\r
+#define CYREG_IO_PC_PRT15_7_6_PC0 0x4000507eu\r
+#define CYREG_IO_PC_PRT15_7_6_PC1 0x4000507fu\r
+#define CYDEV_IO_DR_BASE 0x40005080u\r
+#define CYDEV_IO_DR_SIZE 0x00000010u\r
+#define CYDEV_IO_DR_PRT0_BASE 0x40005080u\r
+#define CYDEV_IO_DR_PRT0_SIZE 0x00000001u\r
+#define CYREG_PRT0_DR_ALIAS 0x40005080u\r
+#define CYDEV_IO_DR_PRT1_BASE 0x40005081u\r
+#define CYDEV_IO_DR_PRT1_SIZE 0x00000001u\r
+#define CYREG_PRT1_DR_ALIAS 0x40005081u\r
+#define CYDEV_IO_DR_PRT2_BASE 0x40005082u\r
+#define CYDEV_IO_DR_PRT2_SIZE 0x00000001u\r
+#define CYREG_PRT2_DR_ALIAS 0x40005082u\r
+#define CYDEV_IO_DR_PRT3_BASE 0x40005083u\r
+#define CYDEV_IO_DR_PRT3_SIZE 0x00000001u\r
+#define CYREG_PRT3_DR_ALIAS 0x40005083u\r
+#define CYDEV_IO_DR_PRT4_BASE 0x40005084u\r
+#define CYDEV_IO_DR_PRT4_SIZE 0x00000001u\r
+#define CYREG_PRT4_DR_ALIAS 0x40005084u\r
+#define CYDEV_IO_DR_PRT5_BASE 0x40005085u\r
+#define CYDEV_IO_DR_PRT5_SIZE 0x00000001u\r
+#define CYREG_PRT5_DR_ALIAS 0x40005085u\r
+#define CYDEV_IO_DR_PRT6_BASE 0x40005086u\r
+#define CYDEV_IO_DR_PRT6_SIZE 0x00000001u\r
+#define CYREG_PRT6_DR_ALIAS 0x40005086u\r
+#define CYDEV_IO_DR_PRT12_BASE 0x4000508cu\r
+#define CYDEV_IO_DR_PRT12_SIZE 0x00000001u\r
+#define CYREG_PRT12_DR_ALIAS 0x4000508cu\r
+#define CYDEV_IO_DR_PRT15_BASE 0x4000508fu\r
+#define CYDEV_IO_DR_PRT15_SIZE 0x00000001u\r
+#define CYREG_PRT15_DR_15_ALIAS 0x4000508fu\r
+#define CYDEV_IO_PS_BASE 0x40005090u\r
+#define CYDEV_IO_PS_SIZE 0x00000010u\r
+#define CYDEV_IO_PS_PRT0_BASE 0x40005090u\r
+#define CYDEV_IO_PS_PRT0_SIZE 0x00000001u\r
+#define CYREG_PRT0_PS_ALIAS 0x40005090u\r
+#define CYDEV_IO_PS_PRT1_BASE 0x40005091u\r
+#define CYDEV_IO_PS_PRT1_SIZE 0x00000001u\r
+#define CYREG_PRT1_PS_ALIAS 0x40005091u\r
+#define CYDEV_IO_PS_PRT2_BASE 0x40005092u\r
+#define CYDEV_IO_PS_PRT2_SIZE 0x00000001u\r
+#define CYREG_PRT2_PS_ALIAS 0x40005092u\r
+#define CYDEV_IO_PS_PRT3_BASE 0x40005093u\r
+#define CYDEV_IO_PS_PRT3_SIZE 0x00000001u\r
+#define CYREG_PRT3_PS_ALIAS 0x40005093u\r
+#define CYDEV_IO_PS_PRT4_BASE 0x40005094u\r
+#define CYDEV_IO_PS_PRT4_SIZE 0x00000001u\r
+#define CYREG_PRT4_PS_ALIAS 0x40005094u\r
+#define CYDEV_IO_PS_PRT5_BASE 0x40005095u\r
+#define CYDEV_IO_PS_PRT5_SIZE 0x00000001u\r
+#define CYREG_PRT5_PS_ALIAS 0x40005095u\r
+#define CYDEV_IO_PS_PRT6_BASE 0x40005096u\r
+#define CYDEV_IO_PS_PRT6_SIZE 0x00000001u\r
+#define CYREG_PRT6_PS_ALIAS 0x40005096u\r
+#define CYDEV_IO_PS_PRT12_BASE 0x4000509cu\r
+#define CYDEV_IO_PS_PRT12_SIZE 0x00000001u\r
+#define CYREG_PRT12_PS_ALIAS 0x4000509cu\r
+#define CYDEV_IO_PS_PRT15_BASE 0x4000509fu\r
+#define CYDEV_IO_PS_PRT15_SIZE 0x00000001u\r
+#define CYREG_PRT15_PS15_ALIAS 0x4000509fu\r
+#define CYDEV_IO_PRT_BASE 0x40005100u\r
+#define CYDEV_IO_PRT_SIZE 0x00000100u\r
+#define CYDEV_IO_PRT_PRT0_BASE 0x40005100u\r
+#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010u\r
+#define CYREG_PRT0_DR 0x40005100u\r
+#define CYREG_PRT0_PS 0x40005101u\r
+#define CYREG_PRT0_DM0 0x40005102u\r
+#define CYREG_PRT0_DM1 0x40005103u\r
+#define CYREG_PRT0_DM2 0x40005104u\r
+#define CYREG_PRT0_SLW 0x40005105u\r
+#define CYREG_PRT0_BYP 0x40005106u\r
+#define CYREG_PRT0_BIE 0x40005107u\r
+#define CYREG_PRT0_INP_DIS 0x40005108u\r
+#define CYREG_PRT0_CTL 0x40005109u\r
+#define CYREG_PRT0_PRT 0x4000510au\r
+#define CYREG_PRT0_BIT_MASK 0x4000510bu\r
+#define CYREG_PRT0_AMUX 0x4000510cu\r
+#define CYREG_PRT0_AG 0x4000510du\r
+#define CYREG_PRT0_LCD_COM_SEG 0x4000510eu\r
+#define CYREG_PRT0_LCD_EN 0x4000510fu\r
+#define CYDEV_IO_PRT_PRT1_BASE 0x40005110u\r
+#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010u\r
+#define CYREG_PRT1_DR 0x40005110u\r
+#define CYREG_PRT1_PS 0x40005111u\r
+#define CYREG_PRT1_DM0 0x40005112u\r
+#define CYREG_PRT1_DM1 0x40005113u\r
+#define CYREG_PRT1_DM2 0x40005114u\r
+#define CYREG_PRT1_SLW 0x40005115u\r
+#define CYREG_PRT1_BYP 0x40005116u\r
+#define CYREG_PRT1_BIE 0x40005117u\r
+#define CYREG_PRT1_INP_DIS 0x40005118u\r
+#define CYREG_PRT1_CTL 0x40005119u\r
+#define CYREG_PRT1_PRT 0x4000511au\r
+#define CYREG_PRT1_BIT_MASK 0x4000511bu\r
+#define CYREG_PRT1_AMUX 0x4000511cu\r
+#define CYREG_PRT1_AG 0x4000511du\r
+#define CYREG_PRT1_LCD_COM_SEG 0x4000511eu\r
+#define CYREG_PRT1_LCD_EN 0x4000511fu\r
+#define CYDEV_IO_PRT_PRT2_BASE 0x40005120u\r
+#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010u\r
+#define CYREG_PRT2_DR 0x40005120u\r
+#define CYREG_PRT2_PS 0x40005121u\r
+#define CYREG_PRT2_DM0 0x40005122u\r
+#define CYREG_PRT2_DM1 0x40005123u\r
+#define CYREG_PRT2_DM2 0x40005124u\r
+#define CYREG_PRT2_SLW 0x40005125u\r
+#define CYREG_PRT2_BYP 0x40005126u\r
+#define CYREG_PRT2_BIE 0x40005127u\r
+#define CYREG_PRT2_INP_DIS 0x40005128u\r
+#define CYREG_PRT2_CTL 0x40005129u\r
+#define CYREG_PRT2_PRT 0x4000512au\r
+#define CYREG_PRT2_BIT_MASK 0x4000512bu\r
+#define CYREG_PRT2_AMUX 0x4000512cu\r
+#define CYREG_PRT2_AG 0x4000512du\r
+#define CYREG_PRT2_LCD_COM_SEG 0x4000512eu\r
+#define CYREG_PRT2_LCD_EN 0x4000512fu\r
+#define CYDEV_IO_PRT_PRT3_BASE 0x40005130u\r
+#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010u\r
+#define CYREG_PRT3_DR 0x40005130u\r
+#define CYREG_PRT3_PS 0x40005131u\r
+#define CYREG_PRT3_DM0 0x40005132u\r
+#define CYREG_PRT3_DM1 0x40005133u\r
+#define CYREG_PRT3_DM2 0x40005134u\r
+#define CYREG_PRT3_SLW 0x40005135u\r
+#define CYREG_PRT3_BYP 0x40005136u\r
+#define CYREG_PRT3_BIE 0x40005137u\r
+#define CYREG_PRT3_INP_DIS 0x40005138u\r
+#define CYREG_PRT3_CTL 0x40005139u\r
+#define CYREG_PRT3_PRT 0x4000513au\r
+#define CYREG_PRT3_BIT_MASK 0x4000513bu\r
+#define CYREG_PRT3_AMUX 0x4000513cu\r
+#define CYREG_PRT3_AG 0x4000513du\r
+#define CYREG_PRT3_LCD_COM_SEG 0x4000513eu\r
+#define CYREG_PRT3_LCD_EN 0x4000513fu\r
+#define CYDEV_IO_PRT_PRT4_BASE 0x40005140u\r
+#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010u\r
+#define CYREG_PRT4_DR 0x40005140u\r
+#define CYREG_PRT4_PS 0x40005141u\r
+#define CYREG_PRT4_DM0 0x40005142u\r
+#define CYREG_PRT4_DM1 0x40005143u\r
+#define CYREG_PRT4_DM2 0x40005144u\r
+#define CYREG_PRT4_SLW 0x40005145u\r
+#define CYREG_PRT4_BYP 0x40005146u\r
+#define CYREG_PRT4_BIE 0x40005147u\r
+#define CYREG_PRT4_INP_DIS 0x40005148u\r
+#define CYREG_PRT4_CTL 0x40005149u\r
+#define CYREG_PRT4_PRT 0x4000514au\r
+#define CYREG_PRT4_BIT_MASK 0x4000514bu\r
+#define CYREG_PRT4_AMUX 0x4000514cu\r
+#define CYREG_PRT4_AG 0x4000514du\r
+#define CYREG_PRT4_LCD_COM_SEG 0x4000514eu\r
+#define CYREG_PRT4_LCD_EN 0x4000514fu\r
+#define CYDEV_IO_PRT_PRT5_BASE 0x40005150u\r
+#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010u\r
+#define CYREG_PRT5_DR 0x40005150u\r
+#define CYREG_PRT5_PS 0x40005151u\r
+#define CYREG_PRT5_DM0 0x40005152u\r
+#define CYREG_PRT5_DM1 0x40005153u\r
+#define CYREG_PRT5_DM2 0x40005154u\r
+#define CYREG_PRT5_SLW 0x40005155u\r
+#define CYREG_PRT5_BYP 0x40005156u\r
+#define CYREG_PRT5_BIE 0x40005157u\r
+#define CYREG_PRT5_INP_DIS 0x40005158u\r
+#define CYREG_PRT5_CTL 0x40005159u\r
+#define CYREG_PRT5_PRT 0x4000515au\r
+#define CYREG_PRT5_BIT_MASK 0x4000515bu\r
+#define CYREG_PRT5_AMUX 0x4000515cu\r
+#define CYREG_PRT5_AG 0x4000515du\r
+#define CYREG_PRT5_LCD_COM_SEG 0x4000515eu\r
+#define CYREG_PRT5_LCD_EN 0x4000515fu\r
+#define CYDEV_IO_PRT_PRT6_BASE 0x40005160u\r
+#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010u\r
+#define CYREG_PRT6_DR 0x40005160u\r
+#define CYREG_PRT6_PS 0x40005161u\r
+#define CYREG_PRT6_DM0 0x40005162u\r
+#define CYREG_PRT6_DM1 0x40005163u\r
+#define CYREG_PRT6_DM2 0x40005164u\r
+#define CYREG_PRT6_SLW 0x40005165u\r
+#define CYREG_PRT6_BYP 0x40005166u\r
+#define CYREG_PRT6_BIE 0x40005167u\r
+#define CYREG_PRT6_INP_DIS 0x40005168u\r
+#define CYREG_PRT6_CTL 0x40005169u\r
+#define CYREG_PRT6_PRT 0x4000516au\r
+#define CYREG_PRT6_BIT_MASK 0x4000516bu\r
+#define CYREG_PRT6_AMUX 0x4000516cu\r
+#define CYREG_PRT6_AG 0x4000516du\r
+#define CYREG_PRT6_LCD_COM_SEG 0x4000516eu\r
+#define CYREG_PRT6_LCD_EN 0x4000516fu\r
+#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0u\r
+#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010u\r
+#define CYREG_PRT12_DR 0x400051c0u\r
+#define CYREG_PRT12_PS 0x400051c1u\r
+#define CYREG_PRT12_DM0 0x400051c2u\r
+#define CYREG_PRT12_DM1 0x400051c3u\r
+#define CYREG_PRT12_DM2 0x400051c4u\r
+#define CYREG_PRT12_SLW 0x400051c5u\r
+#define CYREG_PRT12_BYP 0x400051c6u\r
+#define CYREG_PRT12_BIE 0x400051c7u\r
+#define CYREG_PRT12_INP_DIS 0x400051c8u\r
+#define CYREG_PRT12_SIO_HYST_EN 0x400051c9u\r
+#define CYREG_PRT12_PRT 0x400051cau\r
+#define CYREG_PRT12_BIT_MASK 0x400051cbu\r
+#define CYREG_PRT12_SIO_REG_HIFREQ 0x400051ccu\r
+#define CYREG_PRT12_AG 0x400051cdu\r
+#define CYREG_PRT12_SIO_CFG 0x400051ceu\r
+#define CYREG_PRT12_SIO_DIFF 0x400051cfu\r
+#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0u\r
+#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010u\r
+#define CYREG_PRT15_DR 0x400051f0u\r
+#define CYREG_PRT15_PS 0x400051f1u\r
+#define CYREG_PRT15_DM0 0x400051f2u\r
+#define CYREG_PRT15_DM1 0x400051f3u\r
+#define CYREG_PRT15_DM2 0x400051f4u\r
+#define CYREG_PRT15_SLW 0x400051f5u\r
+#define CYREG_PRT15_BYP 0x400051f6u\r
+#define CYREG_PRT15_BIE 0x400051f7u\r
+#define CYREG_PRT15_INP_DIS 0x400051f8u\r
+#define CYREG_PRT15_CTL 0x400051f9u\r
+#define CYREG_PRT15_PRT 0x400051fau\r
+#define CYREG_PRT15_BIT_MASK 0x400051fbu\r
+#define CYREG_PRT15_AMUX 0x400051fcu\r
+#define CYREG_PRT15_AG 0x400051fdu\r
+#define CYREG_PRT15_LCD_COM_SEG 0x400051feu\r
+#define CYREG_PRT15_LCD_EN 0x400051ffu\r
+#define CYDEV_PRTDSI_BASE 0x40005200u\r
+#define CYDEV_PRTDSI_SIZE 0x0000007fu\r
+#define CYDEV_PRTDSI_PRT0_BASE 0x40005200u\r
+#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007u\r
+#define CYREG_PRT0_OUT_SEL0 0x40005200u\r
+#define CYREG_PRT0_OUT_SEL1 0x40005201u\r
+#define CYREG_PRT0_OE_SEL0 0x40005202u\r
+#define CYREG_PRT0_OE_SEL1 0x40005203u\r
+#define CYREG_PRT0_DBL_SYNC_IN 0x40005204u\r
+#define CYREG_PRT0_SYNC_OUT 0x40005205u\r
+#define CYREG_PRT0_CAPS_SEL 0x40005206u\r
+#define CYDEV_PRTDSI_PRT1_BASE 0x40005208u\r
+#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007u\r
+#define CYREG_PRT1_OUT_SEL0 0x40005208u\r
+#define CYREG_PRT1_OUT_SEL1 0x40005209u\r
+#define CYREG_PRT1_OE_SEL0 0x4000520au\r
+#define CYREG_PRT1_OE_SEL1 0x4000520bu\r
+#define CYREG_PRT1_DBL_SYNC_IN 0x4000520cu\r
+#define CYREG_PRT1_SYNC_OUT 0x4000520du\r
+#define CYREG_PRT1_CAPS_SEL 0x4000520eu\r
+#define CYDEV_PRTDSI_PRT2_BASE 0x40005210u\r
+#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007u\r
+#define CYREG_PRT2_OUT_SEL0 0x40005210u\r
+#define CYREG_PRT2_OUT_SEL1 0x40005211u\r
+#define CYREG_PRT2_OE_SEL0 0x40005212u\r
+#define CYREG_PRT2_OE_SEL1 0x40005213u\r
+#define CYREG_PRT2_DBL_SYNC_IN 0x40005214u\r
+#define CYREG_PRT2_SYNC_OUT 0x40005215u\r
+#define CYREG_PRT2_CAPS_SEL 0x40005216u\r
+#define CYDEV_PRTDSI_PRT3_BASE 0x40005218u\r
+#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007u\r
+#define CYREG_PRT3_OUT_SEL0 0x40005218u\r
+#define CYREG_PRT3_OUT_SEL1 0x40005219u\r
+#define CYREG_PRT3_OE_SEL0 0x4000521au\r
+#define CYREG_PRT3_OE_SEL1 0x4000521bu\r
+#define CYREG_PRT3_DBL_SYNC_IN 0x4000521cu\r
+#define CYREG_PRT3_SYNC_OUT 0x4000521du\r
+#define CYREG_PRT3_CAPS_SEL 0x4000521eu\r
+#define CYDEV_PRTDSI_PRT4_BASE 0x40005220u\r
+#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007u\r
+#define CYREG_PRT4_OUT_SEL0 0x40005220u\r
+#define CYREG_PRT4_OUT_SEL1 0x40005221u\r
+#define CYREG_PRT4_OE_SEL0 0x40005222u\r
+#define CYREG_PRT4_OE_SEL1 0x40005223u\r
+#define CYREG_PRT4_DBL_SYNC_IN 0x40005224u\r
+#define CYREG_PRT4_SYNC_OUT 0x40005225u\r
+#define CYREG_PRT4_CAPS_SEL 0x40005226u\r
+#define CYDEV_PRTDSI_PRT5_BASE 0x40005228u\r
+#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007u\r
+#define CYREG_PRT5_OUT_SEL0 0x40005228u\r
+#define CYREG_PRT5_OUT_SEL1 0x40005229u\r
+#define CYREG_PRT5_OE_SEL0 0x4000522au\r
+#define CYREG_PRT5_OE_SEL1 0x4000522bu\r
+#define CYREG_PRT5_DBL_SYNC_IN 0x4000522cu\r
+#define CYREG_PRT5_SYNC_OUT 0x4000522du\r
+#define CYREG_PRT5_CAPS_SEL 0x4000522eu\r
+#define CYDEV_PRTDSI_PRT6_BASE 0x40005230u\r
+#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007u\r
+#define CYREG_PRT6_OUT_SEL0 0x40005230u\r
+#define CYREG_PRT6_OUT_SEL1 0x40005231u\r
+#define CYREG_PRT6_OE_SEL0 0x40005232u\r
+#define CYREG_PRT6_OE_SEL1 0x40005233u\r
+#define CYREG_PRT6_DBL_SYNC_IN 0x40005234u\r
+#define CYREG_PRT6_SYNC_OUT 0x40005235u\r
+#define CYREG_PRT6_CAPS_SEL 0x40005236u\r
+#define CYDEV_PRTDSI_PRT12_BASE 0x40005260u\r
+#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006u\r
+#define CYREG_PRT12_OUT_SEL0 0x40005260u\r
+#define CYREG_PRT12_OUT_SEL1 0x40005261u\r
+#define CYREG_PRT12_OE_SEL0 0x40005262u\r
+#define CYREG_PRT12_OE_SEL1 0x40005263u\r
+#define CYREG_PRT12_DBL_SYNC_IN 0x40005264u\r
+#define CYREG_PRT12_SYNC_OUT 0x40005265u\r
+#define CYDEV_PRTDSI_PRT15_BASE 0x40005278u\r
+#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007u\r
+#define CYREG_PRT15_OUT_SEL0 0x40005278u\r
+#define CYREG_PRT15_OUT_SEL1 0x40005279u\r
+#define CYREG_PRT15_OE_SEL0 0x4000527au\r
+#define CYREG_PRT15_OE_SEL1 0x4000527bu\r
+#define CYREG_PRT15_DBL_SYNC_IN 0x4000527cu\r
+#define CYREG_PRT15_SYNC_OUT 0x4000527du\r
+#define CYREG_PRT15_CAPS_SEL 0x4000527eu\r
+#define CYDEV_EMIF_BASE 0x40005400u\r
+#define CYDEV_EMIF_SIZE 0x00000007u\r
+#define CYREG_EMIF_NO_UDB 0x40005400u\r
+#define CYREG_EMIF_RP_WAIT_STATES 0x40005401u\r
+#define CYREG_EMIF_MEM_DWN 0x40005402u\r
+#define CYREG_EMIF_MEMCLK_DIV 0x40005403u\r
+#define CYREG_EMIF_CLOCK_EN 0x40005404u\r
+#define CYREG_EMIF_EM_TYPE 0x40005405u\r
+#define CYREG_EMIF_WP_WAIT_STATES 0x40005406u\r
+#define CYDEV_ANAIF_BASE 0x40005800u\r
+#define CYDEV_ANAIF_SIZE 0x000003a9u\r
+#define CYDEV_ANAIF_CFG_BASE 0x40005800u\r
+#define CYDEV_ANAIF_CFG_SIZE 0x0000010fu\r
+#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800u\r
+#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003u\r
+#define CYREG_SC0_CR0 0x40005800u\r
+#define CYREG_SC0_CR1 0x40005801u\r
+#define CYREG_SC0_CR2 0x40005802u\r
+#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804u\r
+#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003u\r
+#define CYREG_SC1_CR0 0x40005804u\r
+#define CYREG_SC1_CR1 0x40005805u\r
+#define CYREG_SC1_CR2 0x40005806u\r
+#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808u\r
+#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003u\r
+#define CYREG_SC2_CR0 0x40005808u\r
+#define CYREG_SC2_CR1 0x40005809u\r
+#define CYREG_SC2_CR2 0x4000580au\r
+#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580cu\r
+#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003u\r
+#define CYREG_SC3_CR0 0x4000580cu\r
+#define CYREG_SC3_CR1 0x4000580du\r
+#define CYREG_SC3_CR2 0x4000580eu\r
+#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820u\r
+#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003u\r
+#define CYREG_DAC0_CR0 0x40005820u\r
+#define CYREG_DAC0_CR1 0x40005821u\r
+#define CYREG_DAC0_TST 0x40005822u\r
+#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824u\r
+#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003u\r
+#define CYREG_DAC1_CR0 0x40005824u\r
+#define CYREG_DAC1_CR1 0x40005825u\r
+#define CYREG_DAC1_TST 0x40005826u\r
+#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828u\r
+#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003u\r
+#define CYREG_DAC2_CR0 0x40005828u\r
+#define CYREG_DAC2_CR1 0x40005829u\r
+#define CYREG_DAC2_TST 0x4000582au\r
+#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582cu\r
+#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003u\r
+#define CYREG_DAC3_CR0 0x4000582cu\r
+#define CYREG_DAC3_CR1 0x4000582du\r
+#define CYREG_DAC3_TST 0x4000582eu\r
+#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840u\r
+#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001u\r
+#define CYREG_CMP0_CR 0x40005840u\r
+#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841u\r
+#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001u\r
+#define CYREG_CMP1_CR 0x40005841u\r
+#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842u\r
+#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001u\r
+#define CYREG_CMP2_CR 0x40005842u\r
+#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843u\r
+#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001u\r
+#define CYREG_CMP3_CR 0x40005843u\r
+#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848u\r
+#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002u\r
+#define CYREG_LUT0_CR 0x40005848u\r
+#define CYREG_LUT0_MX 0x40005849u\r
+#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584au\r
+#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002u\r
+#define CYREG_LUT1_CR 0x4000584au\r
+#define CYREG_LUT1_MX 0x4000584bu\r
+#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584cu\r
+#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002u\r
+#define CYREG_LUT2_CR 0x4000584cu\r
+#define CYREG_LUT2_MX 0x4000584du\r
+#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584eu\r
+#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002u\r
+#define CYREG_LUT3_CR 0x4000584eu\r
+#define CYREG_LUT3_MX 0x4000584fu\r
+#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858u\r
+#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002u\r
+#define CYREG_OPAMP0_CR 0x40005858u\r
+#define CYREG_OPAMP0_RSVD 0x40005859u\r
+#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585au\r
+#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002u\r
+#define CYREG_OPAMP1_CR 0x4000585au\r
+#define CYREG_OPAMP1_RSVD 0x4000585bu\r
+#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585cu\r
+#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002u\r
+#define CYREG_OPAMP2_CR 0x4000585cu\r
+#define CYREG_OPAMP2_RSVD 0x4000585du\r
+#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585eu\r
+#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002u\r
+#define CYREG_OPAMP3_CR 0x4000585eu\r
+#define CYREG_OPAMP3_RSVD 0x4000585fu\r
+#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868u\r
+#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002u\r
+#define CYREG_LCDDAC_CR0 0x40005868u\r
+#define CYREG_LCDDAC_CR1 0x40005869u\r
+#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586au\r
+#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001u\r
+#define CYREG_LCDDRV_CR 0x4000586au\r
+#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586bu\r
+#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001u\r
+#define CYREG_LCDTMR_CFG 0x4000586bu\r
+#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586cu\r
+#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004u\r
+#define CYREG_BG_CR0 0x4000586cu\r
+#define CYREG_BG_RSVD 0x4000586du\r
+#define CYREG_BG_DFT0 0x4000586eu\r
+#define CYREG_BG_DFT1 0x4000586fu\r
+#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870u\r
+#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002u\r
+#define CYREG_CAPSL_CFG0 0x40005870u\r
+#define CYREG_CAPSL_CFG1 0x40005871u\r
+#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872u\r
+#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002u\r
+#define CYREG_CAPSR_CFG0 0x40005872u\r
+#define CYREG_CAPSR_CFG1 0x40005873u\r
+#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876u\r
+#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002u\r
+#define CYREG_PUMP_CR0 0x40005876u\r
+#define CYREG_PUMP_CR1 0x40005877u\r
+#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878u\r
+#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002u\r
+#define CYREG_LPF0_CR0 0x40005878u\r
+#define CYREG_LPF0_RSVD 0x40005879u\r
+#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587au\r
+#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002u\r
+#define CYREG_LPF1_CR0 0x4000587au\r
+#define CYREG_LPF1_RSVD 0x4000587bu\r
+#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587cu\r
+#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001u\r
+#define CYREG_ANAIF_CFG_MISC_CR0 0x4000587cu\r
+#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880u\r
+#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020u\r
+#define CYREG_DSM0_CR0 0x40005880u\r
+#define CYREG_DSM0_CR1 0x40005881u\r
+#define CYREG_DSM0_CR2 0x40005882u\r
+#define CYREG_DSM0_CR3 0x40005883u\r
+#define CYREG_DSM0_CR4 0x40005884u\r
+#define CYREG_DSM0_CR5 0x40005885u\r
+#define CYREG_DSM0_CR6 0x40005886u\r
+#define CYREG_DSM0_CR7 0x40005887u\r
+#define CYREG_DSM0_CR8 0x40005888u\r
+#define CYREG_DSM0_CR9 0x40005889u\r
+#define CYREG_DSM0_CR10 0x4000588au\r
+#define CYREG_DSM0_CR11 0x4000588bu\r
+#define CYREG_DSM0_CR12 0x4000588cu\r
+#define CYREG_DSM0_CR13 0x4000588du\r
+#define CYREG_DSM0_CR14 0x4000588eu\r
+#define CYREG_DSM0_CR15 0x4000588fu\r
+#define CYREG_DSM0_CR16 0x40005890u\r
+#define CYREG_DSM0_CR17 0x40005891u\r
+#define CYREG_DSM0_REF0 0x40005892u\r
+#define CYREG_DSM0_REF1 0x40005893u\r
+#define CYREG_DSM0_REF2 0x40005894u\r
+#define CYREG_DSM0_REF3 0x40005895u\r
+#define CYREG_DSM0_DEM0 0x40005896u\r
+#define CYREG_DSM0_DEM1 0x40005897u\r
+#define CYREG_DSM0_TST0 0x40005898u\r
+#define CYREG_DSM0_TST1 0x40005899u\r
+#define CYREG_DSM0_BUF0 0x4000589au\r
+#define CYREG_DSM0_BUF1 0x4000589bu\r
+#define CYREG_DSM0_BUF2 0x4000589cu\r
+#define CYREG_DSM0_BUF3 0x4000589du\r
+#define CYREG_DSM0_MISC 0x4000589eu\r
+#define CYREG_DSM0_RSVD1 0x4000589fu\r
+#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900u\r
+#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007u\r
+#define CYREG_SAR0_CSR0 0x40005900u\r
+#define CYREG_SAR0_CSR1 0x40005901u\r
+#define CYREG_SAR0_CSR2 0x40005902u\r
+#define CYREG_SAR0_CSR3 0x40005903u\r
+#define CYREG_SAR0_CSR4 0x40005904u\r
+#define CYREG_SAR0_CSR5 0x40005905u\r
+#define CYREG_SAR0_CSR6 0x40005906u\r
+#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908u\r
+#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007u\r
+#define CYREG_SAR1_CSR0 0x40005908u\r
+#define CYREG_SAR1_CSR1 0x40005909u\r
+#define CYREG_SAR1_CSR2 0x4000590au\r
+#define CYREG_SAR1_CSR3 0x4000590bu\r
+#define CYREG_SAR1_CSR4 0x4000590cu\r
+#define CYREG_SAR1_CSR5 0x4000590du\r
+#define CYREG_SAR1_CSR6 0x4000590eu\r
+#define CYDEV_ANAIF_RT_BASE 0x40005a00u\r
+#define CYDEV_ANAIF_RT_SIZE 0x00000162u\r
+#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00u\r
+#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000du\r
+#define CYREG_SC0_SW0 0x40005a00u\r
+#define CYREG_SC0_SW2 0x40005a02u\r
+#define CYREG_SC0_SW3 0x40005a03u\r
+#define CYREG_SC0_SW4 0x40005a04u\r
+#define CYREG_SC0_SW6 0x40005a06u\r
+#define CYREG_SC0_SW7 0x40005a07u\r
+#define CYREG_SC0_SW8 0x40005a08u\r
+#define CYREG_SC0_SW10 0x40005a0au\r
+#define CYREG_SC0_CLK 0x40005a0bu\r
+#define CYREG_SC0_BST 0x40005a0cu\r
+#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10u\r
+#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000du\r
+#define CYREG_SC1_SW0 0x40005a10u\r
+#define CYREG_SC1_SW2 0x40005a12u\r
+#define CYREG_SC1_SW3 0x40005a13u\r
+#define CYREG_SC1_SW4 0x40005a14u\r
+#define CYREG_SC1_SW6 0x40005a16u\r
+#define CYREG_SC1_SW7 0x40005a17u\r
+#define CYREG_SC1_SW8 0x40005a18u\r
+#define CYREG_SC1_SW10 0x40005a1au\r
+#define CYREG_SC1_CLK 0x40005a1bu\r
+#define CYREG_SC1_BST 0x40005a1cu\r
+#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20u\r
+#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000du\r
+#define CYREG_SC2_SW0 0x40005a20u\r
+#define CYREG_SC2_SW2 0x40005a22u\r
+#define CYREG_SC2_SW3 0x40005a23u\r
+#define CYREG_SC2_SW4 0x40005a24u\r
+#define CYREG_SC2_SW6 0x40005a26u\r
+#define CYREG_SC2_SW7 0x40005a27u\r
+#define CYREG_SC2_SW8 0x40005a28u\r
+#define CYREG_SC2_SW10 0x40005a2au\r
+#define CYREG_SC2_CLK 0x40005a2bu\r
+#define CYREG_SC2_BST 0x40005a2cu\r
+#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30u\r
+#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000du\r
+#define CYREG_SC3_SW0 0x40005a30u\r
+#define CYREG_SC3_SW2 0x40005a32u\r
+#define CYREG_SC3_SW3 0x40005a33u\r
+#define CYREG_SC3_SW4 0x40005a34u\r
+#define CYREG_SC3_SW6 0x40005a36u\r
+#define CYREG_SC3_SW7 0x40005a37u\r
+#define CYREG_SC3_SW8 0x40005a38u\r
+#define CYREG_SC3_SW10 0x40005a3au\r
+#define CYREG_SC3_CLK 0x40005a3bu\r
+#define CYREG_SC3_BST 0x40005a3cu\r
+#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80u\r
+#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008u\r
+#define CYREG_DAC0_SW0 0x40005a80u\r
+#define CYREG_DAC0_SW2 0x40005a82u\r
+#define CYREG_DAC0_SW3 0x40005a83u\r
+#define CYREG_DAC0_SW4 0x40005a84u\r
+#define CYREG_DAC0_STROBE 0x40005a87u\r
+#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88u\r
+#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008u\r
+#define CYREG_DAC1_SW0 0x40005a88u\r
+#define CYREG_DAC1_SW2 0x40005a8au\r
+#define CYREG_DAC1_SW3 0x40005a8bu\r
+#define CYREG_DAC1_SW4 0x40005a8cu\r
+#define CYREG_DAC1_STROBE 0x40005a8fu\r
+#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90u\r
+#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008u\r
+#define CYREG_DAC2_SW0 0x40005a90u\r
+#define CYREG_DAC2_SW2 0x40005a92u\r
+#define CYREG_DAC2_SW3 0x40005a93u\r
+#define CYREG_DAC2_SW4 0x40005a94u\r
+#define CYREG_DAC2_STROBE 0x40005a97u\r
+#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98u\r
+#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008u\r
+#define CYREG_DAC3_SW0 0x40005a98u\r
+#define CYREG_DAC3_SW2 0x40005a9au\r
+#define CYREG_DAC3_SW3 0x40005a9bu\r
+#define CYREG_DAC3_SW4 0x40005a9cu\r
+#define CYREG_DAC3_STROBE 0x40005a9fu\r
+#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0u\r
+#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008u\r
+#define CYREG_CMP0_SW0 0x40005ac0u\r
+#define CYREG_CMP0_SW2 0x40005ac2u\r
+#define CYREG_CMP0_SW3 0x40005ac3u\r
+#define CYREG_CMP0_SW4 0x40005ac4u\r
+#define CYREG_CMP0_SW6 0x40005ac6u\r
+#define CYREG_CMP0_CLK 0x40005ac7u\r
+#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8u\r
+#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008u\r
+#define CYREG_CMP1_SW0 0x40005ac8u\r
+#define CYREG_CMP1_SW2 0x40005acau\r
+#define CYREG_CMP1_SW3 0x40005acbu\r
+#define CYREG_CMP1_SW4 0x40005accu\r
+#define CYREG_CMP1_SW6 0x40005aceu\r
+#define CYREG_CMP1_CLK 0x40005acfu\r
+#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0u\r
+#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008u\r
+#define CYREG_CMP2_SW0 0x40005ad0u\r
+#define CYREG_CMP2_SW2 0x40005ad2u\r
+#define CYREG_CMP2_SW3 0x40005ad3u\r
+#define CYREG_CMP2_SW4 0x40005ad4u\r
+#define CYREG_CMP2_SW6 0x40005ad6u\r
+#define CYREG_CMP2_CLK 0x40005ad7u\r
+#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8u\r
+#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008u\r
+#define CYREG_CMP3_SW0 0x40005ad8u\r
+#define CYREG_CMP3_SW2 0x40005adau\r
+#define CYREG_CMP3_SW3 0x40005adbu\r
+#define CYREG_CMP3_SW4 0x40005adcu\r
+#define CYREG_CMP3_SW6 0x40005adeu\r
+#define CYREG_CMP3_CLK 0x40005adfu\r
+#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00u\r
+#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008u\r
+#define CYREG_DSM0_SW0 0x40005b00u\r
+#define CYREG_DSM0_SW2 0x40005b02u\r
+#define CYREG_DSM0_SW3 0x40005b03u\r
+#define CYREG_DSM0_SW4 0x40005b04u\r
+#define CYREG_DSM0_SW6 0x40005b06u\r
+#define CYREG_DSM0_CLK 0x40005b07u\r
+#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20u\r
+#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008u\r
+#define CYREG_SAR0_SW0 0x40005b20u\r
+#define CYREG_SAR0_SW2 0x40005b22u\r
+#define CYREG_SAR0_SW3 0x40005b23u\r
+#define CYREG_SAR0_SW4 0x40005b24u\r
+#define CYREG_SAR0_SW6 0x40005b26u\r
+#define CYREG_SAR0_CLK 0x40005b27u\r
+#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28u\r
+#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008u\r
+#define CYREG_SAR1_SW0 0x40005b28u\r
+#define CYREG_SAR1_SW2 0x40005b2au\r
+#define CYREG_SAR1_SW3 0x40005b2bu\r
+#define CYREG_SAR1_SW4 0x40005b2cu\r
+#define CYREG_SAR1_SW6 0x40005b2eu\r
+#define CYREG_SAR1_CLK 0x40005b2fu\r
+#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40u\r
+#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002u\r
+#define CYREG_OPAMP0_MX 0x40005b40u\r
+#define CYREG_OPAMP0_SW 0x40005b41u\r
+#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42u\r
+#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002u\r
+#define CYREG_OPAMP1_MX 0x40005b42u\r
+#define CYREG_OPAMP1_SW 0x40005b43u\r
+#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44u\r
+#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002u\r
+#define CYREG_OPAMP2_MX 0x40005b44u\r
+#define CYREG_OPAMP2_SW 0x40005b45u\r
+#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46u\r
+#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002u\r
+#define CYREG_OPAMP3_MX 0x40005b46u\r
+#define CYREG_OPAMP3_SW 0x40005b47u\r
+#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50u\r
+#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005u\r
+#define CYREG_LCDDAC_SW0 0x40005b50u\r
+#define CYREG_LCDDAC_SW1 0x40005b51u\r
+#define CYREG_LCDDAC_SW2 0x40005b52u\r
+#define CYREG_LCDDAC_SW3 0x40005b53u\r
+#define CYREG_LCDDAC_SW4 0x40005b54u\r
+#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56u\r
+#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001u\r
+#define CYREG_SC_MISC 0x40005b56u\r
+#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58u\r
+#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004u\r
+#define CYREG_BUS_SW0 0x40005b58u\r
+#define CYREG_BUS_SW2 0x40005b5au\r
+#define CYREG_BUS_SW3 0x40005b5bu\r
+#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5cu\r
+#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006u\r
+#define CYREG_DFT_CR0 0x40005b5cu\r
+#define CYREG_DFT_CR1 0x40005b5du\r
+#define CYREG_DFT_CR2 0x40005b5eu\r
+#define CYREG_DFT_CR3 0x40005b5fu\r
+#define CYREG_DFT_CR4 0x40005b60u\r
+#define CYREG_DFT_CR5 0x40005b61u\r
+#define CYDEV_ANAIF_WRK_BASE 0x40005b80u\r
+#define CYDEV_ANAIF_WRK_SIZE 0x00000029u\r
+#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80u\r
+#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001u\r
+#define CYREG_DAC0_D 0x40005b80u\r
+#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81u\r
+#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001u\r
+#define CYREG_DAC1_D 0x40005b81u\r
+#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82u\r
+#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001u\r
+#define CYREG_DAC2_D 0x40005b82u\r
+#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83u\r
+#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001u\r
+#define CYREG_DAC3_D 0x40005b83u\r
+#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88u\r
+#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002u\r
+#define CYREG_DSM0_OUT0 0x40005b88u\r
+#define CYREG_DSM0_OUT1 0x40005b89u\r
+#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90u\r
+#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005u\r
+#define CYREG_LUT_SR 0x40005b90u\r
+#define CYREG_LUT_WRK1 0x40005b91u\r
+#define CYREG_LUT_MSK 0x40005b92u\r
+#define CYREG_LUT_CLK 0x40005b93u\r
+#define CYREG_LUT_CPTR 0x40005b94u\r
+#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96u\r
+#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002u\r
+#define CYREG_CMP_WRK 0x40005b96u\r
+#define CYREG_CMP_TST 0x40005b97u\r
+#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98u\r
+#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005u\r
+#define CYREG_SC_SR 0x40005b98u\r
+#define CYREG_SC_WRK1 0x40005b99u\r
+#define CYREG_SC_MSK 0x40005b9au\r
+#define CYREG_SC_CMPINV 0x40005b9bu\r
+#define CYREG_SC_CPTR 0x40005b9cu\r
+#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0u\r
+#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002u\r
+#define CYREG_SAR0_WRK0 0x40005ba0u\r
+#define CYREG_SAR0_WRK1 0x40005ba1u\r
+#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2u\r
+#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002u\r
+#define CYREG_SAR1_WRK0 0x40005ba2u\r
+#define CYREG_SAR1_WRK1 0x40005ba3u\r
+#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8u\r
+#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001u\r
+#define CYREG_ANAIF_WRK_SARS_SOF 0x40005ba8u\r
+#define CYDEV_USB_BASE 0x40006000u\r
+#define CYDEV_USB_SIZE 0x00000300u\r
+#define CYREG_USB_EP0_DR0 0x40006000u\r
+#define CYREG_USB_EP0_DR1 0x40006001u\r
+#define CYREG_USB_EP0_DR2 0x40006002u\r
+#define CYREG_USB_EP0_DR3 0x40006003u\r
+#define CYREG_USB_EP0_DR4 0x40006004u\r
+#define CYREG_USB_EP0_DR5 0x40006005u\r
+#define CYREG_USB_EP0_DR6 0x40006006u\r
+#define CYREG_USB_EP0_DR7 0x40006007u\r
+#define CYREG_USB_CR0 0x40006008u\r
+#define CYREG_USB_CR1 0x40006009u\r
+#define CYREG_USB_SIE_EP_INT_EN 0x4000600au\r
+#define CYREG_USB_SIE_EP_INT_SR 0x4000600bu\r
+#define CYDEV_USB_SIE_EP1_BASE 0x4000600cu\r
+#define CYDEV_USB_SIE_EP1_SIZE 0x00000003u\r
+#define CYREG_USB_SIE_EP1_CNT0 0x4000600cu\r
+#define CYREG_USB_SIE_EP1_CNT1 0x4000600du\r
+#define CYREG_USB_SIE_EP1_CR0 0x4000600eu\r
+#define CYREG_USB_USBIO_CR0 0x40006010u\r
+#define CYREG_USB_USBIO_CR1 0x40006012u\r
+#define CYREG_USB_DYN_RECONFIG 0x40006014u\r
+#define CYREG_USB_SOF0 0x40006018u\r
+#define CYREG_USB_SOF1 0x40006019u\r
+#define CYDEV_USB_SIE_EP2_BASE 0x4000601cu\r
+#define CYDEV_USB_SIE_EP2_SIZE 0x00000003u\r
+#define CYREG_USB_SIE_EP2_CNT0 0x4000601cu\r
+#define CYREG_USB_SIE_EP2_CNT1 0x4000601du\r
+#define CYREG_USB_SIE_EP2_CR0 0x4000601eu\r
+#define CYREG_USB_EP0_CR 0x40006028u\r
+#define CYREG_USB_EP0_CNT 0x40006029u\r
+#define CYDEV_USB_SIE_EP3_BASE 0x4000602cu\r
+#define CYDEV_USB_SIE_EP3_SIZE 0x00000003u\r
+#define CYREG_USB_SIE_EP3_CNT0 0x4000602cu\r
+#define CYREG_USB_SIE_EP3_CNT1 0x4000602du\r
+#define CYREG_USB_SIE_EP3_CR0 0x4000602eu\r
+#define CYDEV_USB_SIE_EP4_BASE 0x4000603cu\r
+#define CYDEV_USB_SIE_EP4_SIZE 0x00000003u\r
+#define CYREG_USB_SIE_EP4_CNT0 0x4000603cu\r
+#define CYREG_USB_SIE_EP4_CNT1 0x4000603du\r
+#define CYREG_USB_SIE_EP4_CR0 0x4000603eu\r
+#define CYDEV_USB_SIE_EP5_BASE 0x4000604cu\r
+#define CYDEV_USB_SIE_EP5_SIZE 0x00000003u\r
+#define CYREG_USB_SIE_EP5_CNT0 0x4000604cu\r
+#define CYREG_USB_SIE_EP5_CNT1 0x4000604du\r
+#define CYREG_USB_SIE_EP5_CR0 0x4000604eu\r
+#define CYDEV_USB_SIE_EP6_BASE 0x4000605cu\r
+#define CYDEV_USB_SIE_EP6_SIZE 0x00000003u\r
+#define CYREG_USB_SIE_EP6_CNT0 0x4000605cu\r
+#define CYREG_USB_SIE_EP6_CNT1 0x4000605du\r
+#define CYREG_USB_SIE_EP6_CR0 0x4000605eu\r
+#define CYDEV_USB_SIE_EP7_BASE 0x4000606cu\r
+#define CYDEV_USB_SIE_EP7_SIZE 0x00000003u\r
+#define CYREG_USB_SIE_EP7_CNT0 0x4000606cu\r
+#define CYREG_USB_SIE_EP7_CNT1 0x4000606du\r
+#define CYREG_USB_SIE_EP7_CR0 0x4000606eu\r
+#define CYDEV_USB_SIE_EP8_BASE 0x4000607cu\r
+#define CYDEV_USB_SIE_EP8_SIZE 0x00000003u\r
+#define CYREG_USB_SIE_EP8_CNT0 0x4000607cu\r
+#define CYREG_USB_SIE_EP8_CNT1 0x4000607du\r
+#define CYREG_USB_SIE_EP8_CR0 0x4000607eu\r
+#define CYDEV_USB_ARB_EP1_BASE 0x40006080u\r
+#define CYDEV_USB_ARB_EP1_SIZE 0x00000003u\r
+#define CYREG_USB_ARB_EP1_CFG 0x40006080u\r
+#define CYREG_USB_ARB_EP1_INT_EN 0x40006081u\r
+#define CYREG_USB_ARB_EP1_SR 0x40006082u\r
+#define CYDEV_USB_ARB_RW1_BASE 0x40006084u\r
+#define CYDEV_USB_ARB_RW1_SIZE 0x00000005u\r
+#define CYREG_USB_ARB_RW1_WA 0x40006084u\r
+#define CYREG_USB_ARB_RW1_WA_MSB 0x40006085u\r
+#define CYREG_USB_ARB_RW1_RA 0x40006086u\r
+#define CYREG_USB_ARB_RW1_RA_MSB 0x40006087u\r
+#define CYREG_USB_ARB_RW1_DR 0x40006088u\r
+#define CYREG_USB_BUF_SIZE 0x4000608cu\r
+#define CYREG_USB_EP_ACTIVE 0x4000608eu\r
+#define CYREG_USB_EP_TYPE 0x4000608fu\r
+#define CYDEV_USB_ARB_EP2_BASE 0x40006090u\r
+#define CYDEV_USB_ARB_EP2_SIZE 0x00000003u\r
+#define CYREG_USB_ARB_EP2_CFG 0x40006090u\r
+#define CYREG_USB_ARB_EP2_INT_EN 0x40006091u\r
+#define CYREG_USB_ARB_EP2_SR 0x40006092u\r
+#define CYDEV_USB_ARB_RW2_BASE 0x40006094u\r
+#define CYDEV_USB_ARB_RW2_SIZE 0x00000005u\r
+#define CYREG_USB_ARB_RW2_WA 0x40006094u\r
+#define CYREG_USB_ARB_RW2_WA_MSB 0x40006095u\r
+#define CYREG_USB_ARB_RW2_RA 0x40006096u\r
+#define CYREG_USB_ARB_RW2_RA_MSB 0x40006097u\r
+#define CYREG_USB_ARB_RW2_DR 0x40006098u\r
+#define CYREG_USB_ARB_CFG 0x4000609cu\r
+#define CYREG_USB_USB_CLK_EN 0x4000609du\r
+#define CYREG_USB_ARB_INT_EN 0x4000609eu\r
+#define CYREG_USB_ARB_INT_SR 0x4000609fu\r
+#define CYDEV_USB_ARB_EP3_BASE 0x400060a0u\r
+#define CYDEV_USB_ARB_EP3_SIZE 0x00000003u\r
+#define CYREG_USB_ARB_EP3_CFG 0x400060a0u\r
+#define CYREG_USB_ARB_EP3_INT_EN 0x400060a1u\r
+#define CYREG_USB_ARB_EP3_SR 0x400060a2u\r
+#define CYDEV_USB_ARB_RW3_BASE 0x400060a4u\r
+#define CYDEV_USB_ARB_RW3_SIZE 0x00000005u\r
+#define CYREG_USB_ARB_RW3_WA 0x400060a4u\r
+#define CYREG_USB_ARB_RW3_WA_MSB 0x400060a5u\r
+#define CYREG_USB_ARB_RW3_RA 0x400060a6u\r
+#define CYREG_USB_ARB_RW3_RA_MSB 0x400060a7u\r
+#define CYREG_USB_ARB_RW3_DR 0x400060a8u\r
+#define CYREG_USB_CWA 0x400060acu\r
+#define CYREG_USB_CWA_MSB 0x400060adu\r
+#define CYDEV_USB_ARB_EP4_BASE 0x400060b0u\r
+#define CYDEV_USB_ARB_EP4_SIZE 0x00000003u\r
+#define CYREG_USB_ARB_EP4_CFG 0x400060b0u\r
+#define CYREG_USB_ARB_EP4_INT_EN 0x400060b1u\r
+#define CYREG_USB_ARB_EP4_SR 0x400060b2u\r
+#define CYDEV_USB_ARB_RW4_BASE 0x400060b4u\r
+#define CYDEV_USB_ARB_RW4_SIZE 0x00000005u\r
+#define CYREG_USB_ARB_RW4_WA 0x400060b4u\r
+#define CYREG_USB_ARB_RW4_WA_MSB 0x400060b5u\r
+#define CYREG_USB_ARB_RW4_RA 0x400060b6u\r
+#define CYREG_USB_ARB_RW4_RA_MSB 0x400060b7u\r
+#define CYREG_USB_ARB_RW4_DR 0x400060b8u\r
+#define CYREG_USB_DMA_THRES 0x400060bcu\r
+#define CYREG_USB_DMA_THRES_MSB 0x400060bdu\r
+#define CYDEV_USB_ARB_EP5_BASE 0x400060c0u\r
+#define CYDEV_USB_ARB_EP5_SIZE 0x00000003u\r
+#define CYREG_USB_ARB_EP5_CFG 0x400060c0u\r
+#define CYREG_USB_ARB_EP5_INT_EN 0x400060c1u\r
+#define CYREG_USB_ARB_EP5_SR 0x400060c2u\r
+#define CYDEV_USB_ARB_RW5_BASE 0x400060c4u\r
+#define CYDEV_USB_ARB_RW5_SIZE 0x00000005u\r
+#define CYREG_USB_ARB_RW5_WA 0x400060c4u\r
+#define CYREG_USB_ARB_RW5_WA_MSB 0x400060c5u\r
+#define CYREG_USB_ARB_RW5_RA 0x400060c6u\r
+#define CYREG_USB_ARB_RW5_RA_MSB 0x400060c7u\r
+#define CYREG_USB_ARB_RW5_DR 0x400060c8u\r
+#define CYREG_USB_BUS_RST_CNT 0x400060ccu\r
+#define CYDEV_USB_ARB_EP6_BASE 0x400060d0u\r
+#define CYDEV_USB_ARB_EP6_SIZE 0x00000003u\r
+#define CYREG_USB_ARB_EP6_CFG 0x400060d0u\r
+#define CYREG_USB_ARB_EP6_INT_EN 0x400060d1u\r
+#define CYREG_USB_ARB_EP6_SR 0x400060d2u\r
+#define CYDEV_USB_ARB_RW6_BASE 0x400060d4u\r
+#define CYDEV_USB_ARB_RW6_SIZE 0x00000005u\r
+#define CYREG_USB_ARB_RW6_WA 0x400060d4u\r
+#define CYREG_USB_ARB_RW6_WA_MSB 0x400060d5u\r
+#define CYREG_USB_ARB_RW6_RA 0x400060d6u\r
+#define CYREG_USB_ARB_RW6_RA_MSB 0x400060d7u\r
+#define CYREG_USB_ARB_RW6_DR 0x400060d8u\r
+#define CYDEV_USB_ARB_EP7_BASE 0x400060e0u\r
+#define CYDEV_USB_ARB_EP7_SIZE 0x00000003u\r
+#define CYREG_USB_ARB_EP7_CFG 0x400060e0u\r
+#define CYREG_USB_ARB_EP7_INT_EN 0x400060e1u\r
+#define CYREG_USB_ARB_EP7_SR 0x400060e2u\r
+#define CYDEV_USB_ARB_RW7_BASE 0x400060e4u\r
+#define CYDEV_USB_ARB_RW7_SIZE 0x00000005u\r
+#define CYREG_USB_ARB_RW7_WA 0x400060e4u\r
+#define CYREG_USB_ARB_RW7_WA_MSB 0x400060e5u\r
+#define CYREG_USB_ARB_RW7_RA 0x400060e6u\r
+#define CYREG_USB_ARB_RW7_RA_MSB 0x400060e7u\r
+#define CYREG_USB_ARB_RW7_DR 0x400060e8u\r
+#define CYDEV_USB_ARB_EP8_BASE 0x400060f0u\r
+#define CYDEV_USB_ARB_EP8_SIZE 0x00000003u\r
+#define CYREG_USB_ARB_EP8_CFG 0x400060f0u\r
+#define CYREG_USB_ARB_EP8_INT_EN 0x400060f1u\r
+#define CYREG_USB_ARB_EP8_SR 0x400060f2u\r
+#define CYDEV_USB_ARB_RW8_BASE 0x400060f4u\r
+#define CYDEV_USB_ARB_RW8_SIZE 0x00000005u\r
+#define CYREG_USB_ARB_RW8_WA 0x400060f4u\r
+#define CYREG_USB_ARB_RW8_WA_MSB 0x400060f5u\r
+#define CYREG_USB_ARB_RW8_RA 0x400060f6u\r
+#define CYREG_USB_ARB_RW8_RA_MSB 0x400060f7u\r
+#define CYREG_USB_ARB_RW8_DR 0x400060f8u\r
+#define CYDEV_USB_MEM_BASE 0x40006100u\r
+#define CYDEV_USB_MEM_SIZE 0x00000200u\r
+#define CYREG_USB_MEM_DATA_MBASE 0x40006100u\r
+#define CYREG_USB_MEM_DATA_MSIZE 0x00000200u\r
+#define CYDEV_UWRK_BASE 0x40006400u\r
+#define CYDEV_UWRK_SIZE 0x00000b60u\r
+#define CYDEV_UWRK_UWRK8_BASE 0x40006400u\r
+#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0u\r
+#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400u\r
+#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0u\r
+#define CYREG_B0_UDB00_A0 0x40006400u\r
+#define CYREG_B0_UDB01_A0 0x40006401u\r
+#define CYREG_B0_UDB02_A0 0x40006402u\r
+#define CYREG_B0_UDB03_A0 0x40006403u\r
+#define CYREG_B0_UDB04_A0 0x40006404u\r
+#define CYREG_B0_UDB05_A0 0x40006405u\r
+#define CYREG_B0_UDB06_A0 0x40006406u\r
+#define CYREG_B0_UDB07_A0 0x40006407u\r
+#define CYREG_B0_UDB08_A0 0x40006408u\r
+#define CYREG_B0_UDB09_A0 0x40006409u\r
+#define CYREG_B0_UDB10_A0 0x4000640au\r
+#define CYREG_B0_UDB11_A0 0x4000640bu\r
+#define CYREG_B0_UDB12_A0 0x4000640cu\r
+#define CYREG_B0_UDB13_A0 0x4000640du\r
+#define CYREG_B0_UDB14_A0 0x4000640eu\r
+#define CYREG_B0_UDB15_A0 0x4000640fu\r
+#define CYREG_B0_UDB00_A1 0x40006410u\r
+#define CYREG_B0_UDB01_A1 0x40006411u\r
+#define CYREG_B0_UDB02_A1 0x40006412u\r
+#define CYREG_B0_UDB03_A1 0x40006413u\r
+#define CYREG_B0_UDB04_A1 0x40006414u\r
+#define CYREG_B0_UDB05_A1 0x40006415u\r
+#define CYREG_B0_UDB06_A1 0x40006416u\r
+#define CYREG_B0_UDB07_A1 0x40006417u\r
+#define CYREG_B0_UDB08_A1 0x40006418u\r
+#define CYREG_B0_UDB09_A1 0x40006419u\r
+#define CYREG_B0_UDB10_A1 0x4000641au\r
+#define CYREG_B0_UDB11_A1 0x4000641bu\r
+#define CYREG_B0_UDB12_A1 0x4000641cu\r
+#define CYREG_B0_UDB13_A1 0x4000641du\r
+#define CYREG_B0_UDB14_A1 0x4000641eu\r
+#define CYREG_B0_UDB15_A1 0x4000641fu\r
+#define CYREG_B0_UDB00_D0 0x40006420u\r
+#define CYREG_B0_UDB01_D0 0x40006421u\r
+#define CYREG_B0_UDB02_D0 0x40006422u\r
+#define CYREG_B0_UDB03_D0 0x40006423u\r
+#define CYREG_B0_UDB04_D0 0x40006424u\r
+#define CYREG_B0_UDB05_D0 0x40006425u\r
+#define CYREG_B0_UDB06_D0 0x40006426u\r
+#define CYREG_B0_UDB07_D0 0x40006427u\r
+#define CYREG_B0_UDB08_D0 0x40006428u\r
+#define CYREG_B0_UDB09_D0 0x40006429u\r
+#define CYREG_B0_UDB10_D0 0x4000642au\r
+#define CYREG_B0_UDB11_D0 0x4000642bu\r
+#define CYREG_B0_UDB12_D0 0x4000642cu\r
+#define CYREG_B0_UDB13_D0 0x4000642du\r
+#define CYREG_B0_UDB14_D0 0x4000642eu\r
+#define CYREG_B0_UDB15_D0 0x4000642fu\r
+#define CYREG_B0_UDB00_D1 0x40006430u\r
+#define CYREG_B0_UDB01_D1 0x40006431u\r
+#define CYREG_B0_UDB02_D1 0x40006432u\r
+#define CYREG_B0_UDB03_D1 0x40006433u\r
+#define CYREG_B0_UDB04_D1 0x40006434u\r
+#define CYREG_B0_UDB05_D1 0x40006435u\r
+#define CYREG_B0_UDB06_D1 0x40006436u\r
+#define CYREG_B0_UDB07_D1 0x40006437u\r
+#define CYREG_B0_UDB08_D1 0x40006438u\r
+#define CYREG_B0_UDB09_D1 0x40006439u\r
+#define CYREG_B0_UDB10_D1 0x4000643au\r
+#define CYREG_B0_UDB11_D1 0x4000643bu\r
+#define CYREG_B0_UDB12_D1 0x4000643cu\r
+#define CYREG_B0_UDB13_D1 0x4000643du\r
+#define CYREG_B0_UDB14_D1 0x4000643eu\r
+#define CYREG_B0_UDB15_D1 0x4000643fu\r
+#define CYREG_B0_UDB00_F0 0x40006440u\r
+#define CYREG_B0_UDB01_F0 0x40006441u\r
+#define CYREG_B0_UDB02_F0 0x40006442u\r
+#define CYREG_B0_UDB03_F0 0x40006443u\r
+#define CYREG_B0_UDB04_F0 0x40006444u\r
+#define CYREG_B0_UDB05_F0 0x40006445u\r
+#define CYREG_B0_UDB06_F0 0x40006446u\r
+#define CYREG_B0_UDB07_F0 0x40006447u\r
+#define CYREG_B0_UDB08_F0 0x40006448u\r
+#define CYREG_B0_UDB09_F0 0x40006449u\r
+#define CYREG_B0_UDB10_F0 0x4000644au\r
+#define CYREG_B0_UDB11_F0 0x4000644bu\r
+#define CYREG_B0_UDB12_F0 0x4000644cu\r
+#define CYREG_B0_UDB13_F0 0x4000644du\r
+#define CYREG_B0_UDB14_F0 0x4000644eu\r
+#define CYREG_B0_UDB15_F0 0x4000644fu\r
+#define CYREG_B0_UDB00_F1 0x40006450u\r
+#define CYREG_B0_UDB01_F1 0x40006451u\r
+#define CYREG_B0_UDB02_F1 0x40006452u\r
+#define CYREG_B0_UDB03_F1 0x40006453u\r
+#define CYREG_B0_UDB04_F1 0x40006454u\r
+#define CYREG_B0_UDB05_F1 0x40006455u\r
+#define CYREG_B0_UDB06_F1 0x40006456u\r
+#define CYREG_B0_UDB07_F1 0x40006457u\r
+#define CYREG_B0_UDB08_F1 0x40006458u\r
+#define CYREG_B0_UDB09_F1 0x40006459u\r
+#define CYREG_B0_UDB10_F1 0x4000645au\r
+#define CYREG_B0_UDB11_F1 0x4000645bu\r
+#define CYREG_B0_UDB12_F1 0x4000645cu\r
+#define CYREG_B0_UDB13_F1 0x4000645du\r
+#define CYREG_B0_UDB14_F1 0x4000645eu\r
+#define CYREG_B0_UDB15_F1 0x4000645fu\r
+#define CYREG_B0_UDB00_ST 0x40006460u\r
+#define CYREG_B0_UDB01_ST 0x40006461u\r
+#define CYREG_B0_UDB02_ST 0x40006462u\r
+#define CYREG_B0_UDB03_ST 0x40006463u\r
+#define CYREG_B0_UDB04_ST 0x40006464u\r
+#define CYREG_B0_UDB05_ST 0x40006465u\r
+#define CYREG_B0_UDB06_ST 0x40006466u\r
+#define CYREG_B0_UDB07_ST 0x40006467u\r
+#define CYREG_B0_UDB08_ST 0x40006468u\r
+#define CYREG_B0_UDB09_ST 0x40006469u\r
+#define CYREG_B0_UDB10_ST 0x4000646au\r
+#define CYREG_B0_UDB11_ST 0x4000646bu\r
+#define CYREG_B0_UDB12_ST 0x4000646cu\r
+#define CYREG_B0_UDB13_ST 0x4000646du\r
+#define CYREG_B0_UDB14_ST 0x4000646eu\r
+#define CYREG_B0_UDB15_ST 0x4000646fu\r
+#define CYREG_B0_UDB00_CTL 0x40006470u\r
+#define CYREG_B0_UDB01_CTL 0x40006471u\r
+#define CYREG_B0_UDB02_CTL 0x40006472u\r
+#define CYREG_B0_UDB03_CTL 0x40006473u\r
+#define CYREG_B0_UDB04_CTL 0x40006474u\r
+#define CYREG_B0_UDB05_CTL 0x40006475u\r
+#define CYREG_B0_UDB06_CTL 0x40006476u\r
+#define CYREG_B0_UDB07_CTL 0x40006477u\r
+#define CYREG_B0_UDB08_CTL 0x40006478u\r
+#define CYREG_B0_UDB09_CTL 0x40006479u\r
+#define CYREG_B0_UDB10_CTL 0x4000647au\r
+#define CYREG_B0_UDB11_CTL 0x4000647bu\r
+#define CYREG_B0_UDB12_CTL 0x4000647cu\r
+#define CYREG_B0_UDB13_CTL 0x4000647du\r
+#define CYREG_B0_UDB14_CTL 0x4000647eu\r
+#define CYREG_B0_UDB15_CTL 0x4000647fu\r
+#define CYREG_B0_UDB00_MSK 0x40006480u\r
+#define CYREG_B0_UDB01_MSK 0x40006481u\r
+#define CYREG_B0_UDB02_MSK 0x40006482u\r
+#define CYREG_B0_UDB03_MSK 0x40006483u\r
+#define CYREG_B0_UDB04_MSK 0x40006484u\r
+#define CYREG_B0_UDB05_MSK 0x40006485u\r
+#define CYREG_B0_UDB06_MSK 0x40006486u\r
+#define CYREG_B0_UDB07_MSK 0x40006487u\r
+#define CYREG_B0_UDB08_MSK 0x40006488u\r
+#define CYREG_B0_UDB09_MSK 0x40006489u\r
+#define CYREG_B0_UDB10_MSK 0x4000648au\r
+#define CYREG_B0_UDB11_MSK 0x4000648bu\r
+#define CYREG_B0_UDB12_MSK 0x4000648cu\r
+#define CYREG_B0_UDB13_MSK 0x4000648du\r
+#define CYREG_B0_UDB14_MSK 0x4000648eu\r
+#define CYREG_B0_UDB15_MSK 0x4000648fu\r
+#define CYREG_B0_UDB00_ACTL 0x40006490u\r
+#define CYREG_B0_UDB01_ACTL 0x40006491u\r
+#define CYREG_B0_UDB02_ACTL 0x40006492u\r
+#define CYREG_B0_UDB03_ACTL 0x40006493u\r
+#define CYREG_B0_UDB04_ACTL 0x40006494u\r
+#define CYREG_B0_UDB05_ACTL 0x40006495u\r
+#define CYREG_B0_UDB06_ACTL 0x40006496u\r
+#define CYREG_B0_UDB07_ACTL 0x40006497u\r
+#define CYREG_B0_UDB08_ACTL 0x40006498u\r
+#define CYREG_B0_UDB09_ACTL 0x40006499u\r
+#define CYREG_B0_UDB10_ACTL 0x4000649au\r
+#define CYREG_B0_UDB11_ACTL 0x4000649bu\r
+#define CYREG_B0_UDB12_ACTL 0x4000649cu\r
+#define CYREG_B0_UDB13_ACTL 0x4000649du\r
+#define CYREG_B0_UDB14_ACTL 0x4000649eu\r
+#define CYREG_B0_UDB15_ACTL 0x4000649fu\r
+#define CYREG_B0_UDB00_MC 0x400064a0u\r
+#define CYREG_B0_UDB01_MC 0x400064a1u\r
+#define CYREG_B0_UDB02_MC 0x400064a2u\r
+#define CYREG_B0_UDB03_MC 0x400064a3u\r
+#define CYREG_B0_UDB04_MC 0x400064a4u\r
+#define CYREG_B0_UDB05_MC 0x400064a5u\r
+#define CYREG_B0_UDB06_MC 0x400064a6u\r
+#define CYREG_B0_UDB07_MC 0x400064a7u\r
+#define CYREG_B0_UDB08_MC 0x400064a8u\r
+#define CYREG_B0_UDB09_MC 0x400064a9u\r
+#define CYREG_B0_UDB10_MC 0x400064aau\r
+#define CYREG_B0_UDB11_MC 0x400064abu\r
+#define CYREG_B0_UDB12_MC 0x400064acu\r
+#define CYREG_B0_UDB13_MC 0x400064adu\r
+#define CYREG_B0_UDB14_MC 0x400064aeu\r
+#define CYREG_B0_UDB15_MC 0x400064afu\r
+#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500u\r
+#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0u\r
+#define CYREG_B1_UDB04_A0 0x40006504u\r
+#define CYREG_B1_UDB05_A0 0x40006505u\r
+#define CYREG_B1_UDB06_A0 0x40006506u\r
+#define CYREG_B1_UDB07_A0 0x40006507u\r
+#define CYREG_B1_UDB08_A0 0x40006508u\r
+#define CYREG_B1_UDB09_A0 0x40006509u\r
+#define CYREG_B1_UDB10_A0 0x4000650au\r
+#define CYREG_B1_UDB11_A0 0x4000650bu\r
+#define CYREG_B1_UDB04_A1 0x40006514u\r
+#define CYREG_B1_UDB05_A1 0x40006515u\r
+#define CYREG_B1_UDB06_A1 0x40006516u\r
+#define CYREG_B1_UDB07_A1 0x40006517u\r
+#define CYREG_B1_UDB08_A1 0x40006518u\r
+#define CYREG_B1_UDB09_A1 0x40006519u\r
+#define CYREG_B1_UDB10_A1 0x4000651au\r
+#define CYREG_B1_UDB11_A1 0x4000651bu\r
+#define CYREG_B1_UDB04_D0 0x40006524u\r
+#define CYREG_B1_UDB05_D0 0x40006525u\r
+#define CYREG_B1_UDB06_D0 0x40006526u\r
+#define CYREG_B1_UDB07_D0 0x40006527u\r
+#define CYREG_B1_UDB08_D0 0x40006528u\r
+#define CYREG_B1_UDB09_D0 0x40006529u\r
+#define CYREG_B1_UDB10_D0 0x4000652au\r
+#define CYREG_B1_UDB11_D0 0x4000652bu\r
+#define CYREG_B1_UDB04_D1 0x40006534u\r
+#define CYREG_B1_UDB05_D1 0x40006535u\r
+#define CYREG_B1_UDB06_D1 0x40006536u\r
+#define CYREG_B1_UDB07_D1 0x40006537u\r
+#define CYREG_B1_UDB08_D1 0x40006538u\r
+#define CYREG_B1_UDB09_D1 0x40006539u\r
+#define CYREG_B1_UDB10_D1 0x4000653au\r
+#define CYREG_B1_UDB11_D1 0x4000653bu\r
+#define CYREG_B1_UDB04_F0 0x40006544u\r
+#define CYREG_B1_UDB05_F0 0x40006545u\r
+#define CYREG_B1_UDB06_F0 0x40006546u\r
+#define CYREG_B1_UDB07_F0 0x40006547u\r
+#define CYREG_B1_UDB08_F0 0x40006548u\r
+#define CYREG_B1_UDB09_F0 0x40006549u\r
+#define CYREG_B1_UDB10_F0 0x4000654au\r
+#define CYREG_B1_UDB11_F0 0x4000654bu\r
+#define CYREG_B1_UDB04_F1 0x40006554u\r
+#define CYREG_B1_UDB05_F1 0x40006555u\r
+#define CYREG_B1_UDB06_F1 0x40006556u\r
+#define CYREG_B1_UDB07_F1 0x40006557u\r
+#define CYREG_B1_UDB08_F1 0x40006558u\r
+#define CYREG_B1_UDB09_F1 0x40006559u\r
+#define CYREG_B1_UDB10_F1 0x4000655au\r
+#define CYREG_B1_UDB11_F1 0x4000655bu\r
+#define CYREG_B1_UDB04_ST 0x40006564u\r
+#define CYREG_B1_UDB05_ST 0x40006565u\r
+#define CYREG_B1_UDB06_ST 0x40006566u\r
+#define CYREG_B1_UDB07_ST 0x40006567u\r
+#define CYREG_B1_UDB08_ST 0x40006568u\r
+#define CYREG_B1_UDB09_ST 0x40006569u\r
+#define CYREG_B1_UDB10_ST 0x4000656au\r
+#define CYREG_B1_UDB11_ST 0x4000656bu\r
+#define CYREG_B1_UDB04_CTL 0x40006574u\r
+#define CYREG_B1_UDB05_CTL 0x40006575u\r
+#define CYREG_B1_UDB06_CTL 0x40006576u\r
+#define CYREG_B1_UDB07_CTL 0x40006577u\r
+#define CYREG_B1_UDB08_CTL 0x40006578u\r
+#define CYREG_B1_UDB09_CTL 0x40006579u\r
+#define CYREG_B1_UDB10_CTL 0x4000657au\r
+#define CYREG_B1_UDB11_CTL 0x4000657bu\r
+#define CYREG_B1_UDB04_MSK 0x40006584u\r
+#define CYREG_B1_UDB05_MSK 0x40006585u\r
+#define CYREG_B1_UDB06_MSK 0x40006586u\r
+#define CYREG_B1_UDB07_MSK 0x40006587u\r
+#define CYREG_B1_UDB08_MSK 0x40006588u\r
+#define CYREG_B1_UDB09_MSK 0x40006589u\r
+#define CYREG_B1_UDB10_MSK 0x4000658au\r
+#define CYREG_B1_UDB11_MSK 0x4000658bu\r
+#define CYREG_B1_UDB04_ACTL 0x40006594u\r
+#define CYREG_B1_UDB05_ACTL 0x40006595u\r
+#define CYREG_B1_UDB06_ACTL 0x40006596u\r
+#define CYREG_B1_UDB07_ACTL 0x40006597u\r
+#define CYREG_B1_UDB08_ACTL 0x40006598u\r
+#define CYREG_B1_UDB09_ACTL 0x40006599u\r
+#define CYREG_B1_UDB10_ACTL 0x4000659au\r
+#define CYREG_B1_UDB11_ACTL 0x4000659bu\r
+#define CYREG_B1_UDB04_MC 0x400065a4u\r
+#define CYREG_B1_UDB05_MC 0x400065a5u\r
+#define CYREG_B1_UDB06_MC 0x400065a6u\r
+#define CYREG_B1_UDB07_MC 0x400065a7u\r
+#define CYREG_B1_UDB08_MC 0x400065a8u\r
+#define CYREG_B1_UDB09_MC 0x400065a9u\r
+#define CYREG_B1_UDB10_MC 0x400065aau\r
+#define CYREG_B1_UDB11_MC 0x400065abu\r
+#define CYDEV_UWRK_UWRK16_BASE 0x40006800u\r
+#define CYDEV_UWRK_UWRK16_SIZE 0x00000760u\r
+#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800u\r
+#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800u\r
+#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160u\r
+#define CYREG_B0_UDB00_A0_A1 0x40006800u\r
+#define CYREG_B0_UDB01_A0_A1 0x40006802u\r
+#define CYREG_B0_UDB02_A0_A1 0x40006804u\r
+#define CYREG_B0_UDB03_A0_A1 0x40006806u\r
+#define CYREG_B0_UDB04_A0_A1 0x40006808u\r
+#define CYREG_B0_UDB05_A0_A1 0x4000680au\r
+#define CYREG_B0_UDB06_A0_A1 0x4000680cu\r
+#define CYREG_B0_UDB07_A0_A1 0x4000680eu\r
+#define CYREG_B0_UDB08_A0_A1 0x40006810u\r
+#define CYREG_B0_UDB09_A0_A1 0x40006812u\r
+#define CYREG_B0_UDB10_A0_A1 0x40006814u\r
+#define CYREG_B0_UDB11_A0_A1 0x40006816u\r
+#define CYREG_B0_UDB12_A0_A1 0x40006818u\r
+#define CYREG_B0_UDB13_A0_A1 0x4000681au\r
+#define CYREG_B0_UDB14_A0_A1 0x4000681cu\r
+#define CYREG_B0_UDB15_A0_A1 0x4000681eu\r
+#define CYREG_B0_UDB00_D0_D1 0x40006840u\r
+#define CYREG_B0_UDB01_D0_D1 0x40006842u\r
+#define CYREG_B0_UDB02_D0_D1 0x40006844u\r
+#define CYREG_B0_UDB03_D0_D1 0x40006846u\r
+#define CYREG_B0_UDB04_D0_D1 0x40006848u\r
+#define CYREG_B0_UDB05_D0_D1 0x4000684au\r
+#define CYREG_B0_UDB06_D0_D1 0x4000684cu\r
+#define CYREG_B0_UDB07_D0_D1 0x4000684eu\r
+#define CYREG_B0_UDB08_D0_D1 0x40006850u\r
+#define CYREG_B0_UDB09_D0_D1 0x40006852u\r
+#define CYREG_B0_UDB10_D0_D1 0x40006854u\r
+#define CYREG_B0_UDB11_D0_D1 0x40006856u\r
+#define CYREG_B0_UDB12_D0_D1 0x40006858u\r
+#define CYREG_B0_UDB13_D0_D1 0x4000685au\r
+#define CYREG_B0_UDB14_D0_D1 0x4000685cu\r
+#define CYREG_B0_UDB15_D0_D1 0x4000685eu\r
+#define CYREG_B0_UDB00_F0_F1 0x40006880u\r
+#define CYREG_B0_UDB01_F0_F1 0x40006882u\r
+#define CYREG_B0_UDB02_F0_F1 0x40006884u\r
+#define CYREG_B0_UDB03_F0_F1 0x40006886u\r
+#define CYREG_B0_UDB04_F0_F1 0x40006888u\r
+#define CYREG_B0_UDB05_F0_F1 0x4000688au\r
+#define CYREG_B0_UDB06_F0_F1 0x4000688cu\r
+#define CYREG_B0_UDB07_F0_F1 0x4000688eu\r
+#define CYREG_B0_UDB08_F0_F1 0x40006890u\r
+#define CYREG_B0_UDB09_F0_F1 0x40006892u\r
+#define CYREG_B0_UDB10_F0_F1 0x40006894u\r
+#define CYREG_B0_UDB11_F0_F1 0x40006896u\r
+#define CYREG_B0_UDB12_F0_F1 0x40006898u\r
+#define CYREG_B0_UDB13_F0_F1 0x4000689au\r
+#define CYREG_B0_UDB14_F0_F1 0x4000689cu\r
+#define CYREG_B0_UDB15_F0_F1 0x4000689eu\r
+#define CYREG_B0_UDB00_ST_CTL 0x400068c0u\r
+#define CYREG_B0_UDB01_ST_CTL 0x400068c2u\r
+#define CYREG_B0_UDB02_ST_CTL 0x400068c4u\r
+#define CYREG_B0_UDB03_ST_CTL 0x400068c6u\r
+#define CYREG_B0_UDB04_ST_CTL 0x400068c8u\r
+#define CYREG_B0_UDB05_ST_CTL 0x400068cau\r
+#define CYREG_B0_UDB06_ST_CTL 0x400068ccu\r
+#define CYREG_B0_UDB07_ST_CTL 0x400068ceu\r
+#define CYREG_B0_UDB08_ST_CTL 0x400068d0u\r
+#define CYREG_B0_UDB09_ST_CTL 0x400068d2u\r
+#define CYREG_B0_UDB10_ST_CTL 0x400068d4u\r
+#define CYREG_B0_UDB11_ST_CTL 0x400068d6u\r
+#define CYREG_B0_UDB12_ST_CTL 0x400068d8u\r
+#define CYREG_B0_UDB13_ST_CTL 0x400068dau\r
+#define CYREG_B0_UDB14_ST_CTL 0x400068dcu\r
+#define CYREG_B0_UDB15_ST_CTL 0x400068deu\r
+#define CYREG_B0_UDB00_MSK_ACTL 0x40006900u\r
+#define CYREG_B0_UDB01_MSK_ACTL 0x40006902u\r
+#define CYREG_B0_UDB02_MSK_ACTL 0x40006904u\r
+#define CYREG_B0_UDB03_MSK_ACTL 0x40006906u\r
+#define CYREG_B0_UDB04_MSK_ACTL 0x40006908u\r
+#define CYREG_B0_UDB05_MSK_ACTL 0x4000690au\r
+#define CYREG_B0_UDB06_MSK_ACTL 0x4000690cu\r
+#define CYREG_B0_UDB07_MSK_ACTL 0x4000690eu\r
+#define CYREG_B0_UDB08_MSK_ACTL 0x40006910u\r
+#define CYREG_B0_UDB09_MSK_ACTL 0x40006912u\r
+#define CYREG_B0_UDB10_MSK_ACTL 0x40006914u\r
+#define CYREG_B0_UDB11_MSK_ACTL 0x40006916u\r
+#define CYREG_B0_UDB12_MSK_ACTL 0x40006918u\r
+#define CYREG_B0_UDB13_MSK_ACTL 0x4000691au\r
+#define CYREG_B0_UDB14_MSK_ACTL 0x4000691cu\r
+#define CYREG_B0_UDB15_MSK_ACTL 0x4000691eu\r
+#define CYREG_B0_UDB00_MC_00 0x40006940u\r
+#define CYREG_B0_UDB01_MC_00 0x40006942u\r
+#define CYREG_B0_UDB02_MC_00 0x40006944u\r
+#define CYREG_B0_UDB03_MC_00 0x40006946u\r
+#define CYREG_B0_UDB04_MC_00 0x40006948u\r
+#define CYREG_B0_UDB05_MC_00 0x4000694au\r
+#define CYREG_B0_UDB06_MC_00 0x4000694cu\r
+#define CYREG_B0_UDB07_MC_00 0x4000694eu\r
+#define CYREG_B0_UDB08_MC_00 0x40006950u\r
+#define CYREG_B0_UDB09_MC_00 0x40006952u\r
+#define CYREG_B0_UDB10_MC_00 0x40006954u\r
+#define CYREG_B0_UDB11_MC_00 0x40006956u\r
+#define CYREG_B0_UDB12_MC_00 0x40006958u\r
+#define CYREG_B0_UDB13_MC_00 0x4000695au\r
+#define CYREG_B0_UDB14_MC_00 0x4000695cu\r
+#define CYREG_B0_UDB15_MC_00 0x4000695eu\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00u\r
+#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160u\r
+#define CYREG_B1_UDB04_A0_A1 0x40006a08u\r
+#define CYREG_B1_UDB05_A0_A1 0x40006a0au\r
+#define CYREG_B1_UDB06_A0_A1 0x40006a0cu\r
+#define CYREG_B1_UDB07_A0_A1 0x40006a0eu\r
+#define CYREG_B1_UDB08_A0_A1 0x40006a10u\r
+#define CYREG_B1_UDB09_A0_A1 0x40006a12u\r
+#define CYREG_B1_UDB10_A0_A1 0x40006a14u\r
+#define CYREG_B1_UDB11_A0_A1 0x40006a16u\r
+#define CYREG_B1_UDB04_D0_D1 0x40006a48u\r
+#define CYREG_B1_UDB05_D0_D1 0x40006a4au\r
+#define CYREG_B1_UDB06_D0_D1 0x40006a4cu\r
+#define CYREG_B1_UDB07_D0_D1 0x40006a4eu\r
+#define CYREG_B1_UDB08_D0_D1 0x40006a50u\r
+#define CYREG_B1_UDB09_D0_D1 0x40006a52u\r
+#define CYREG_B1_UDB10_D0_D1 0x40006a54u\r
+#define CYREG_B1_UDB11_D0_D1 0x40006a56u\r
+#define CYREG_B1_UDB04_F0_F1 0x40006a88u\r
+#define CYREG_B1_UDB05_F0_F1 0x40006a8au\r
+#define CYREG_B1_UDB06_F0_F1 0x40006a8cu\r
+#define CYREG_B1_UDB07_F0_F1 0x40006a8eu\r
+#define CYREG_B1_UDB08_F0_F1 0x40006a90u\r
+#define CYREG_B1_UDB09_F0_F1 0x40006a92u\r
+#define CYREG_B1_UDB10_F0_F1 0x40006a94u\r
+#define CYREG_B1_UDB11_F0_F1 0x40006a96u\r
+#define CYREG_B1_UDB04_ST_CTL 0x40006ac8u\r
+#define CYREG_B1_UDB05_ST_CTL 0x40006acau\r
+#define CYREG_B1_UDB06_ST_CTL 0x40006accu\r
+#define CYREG_B1_UDB07_ST_CTL 0x40006aceu\r
+#define CYREG_B1_UDB08_ST_CTL 0x40006ad0u\r
+#define CYREG_B1_UDB09_ST_CTL 0x40006ad2u\r
+#define CYREG_B1_UDB10_ST_CTL 0x40006ad4u\r
+#define CYREG_B1_UDB11_ST_CTL 0x40006ad6u\r
+#define CYREG_B1_UDB04_MSK_ACTL 0x40006b08u\r
+#define CYREG_B1_UDB05_MSK_ACTL 0x40006b0au\r
+#define CYREG_B1_UDB06_MSK_ACTL 0x40006b0cu\r
+#define CYREG_B1_UDB07_MSK_ACTL 0x40006b0eu\r
+#define CYREG_B1_UDB08_MSK_ACTL 0x40006b10u\r
+#define CYREG_B1_UDB09_MSK_ACTL 0x40006b12u\r
+#define CYREG_B1_UDB10_MSK_ACTL 0x40006b14u\r
+#define CYREG_B1_UDB11_MSK_ACTL 0x40006b16u\r
+#define CYREG_B1_UDB04_MC_00 0x40006b48u\r
+#define CYREG_B1_UDB05_MC_00 0x40006b4au\r
+#define CYREG_B1_UDB06_MC_00 0x40006b4cu\r
+#define CYREG_B1_UDB07_MC_00 0x40006b4eu\r
+#define CYREG_B1_UDB08_MC_00 0x40006b50u\r
+#define CYREG_B1_UDB09_MC_00 0x40006b52u\r
+#define CYREG_B1_UDB10_MC_00 0x40006b54u\r
+#define CYREG_B1_UDB11_MC_00 0x40006b56u\r
+#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800u\r
+#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075eu\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800u\r
+#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015eu\r
+#define CYREG_B0_UDB00_01_A0 0x40006800u\r
+#define CYREG_B0_UDB01_02_A0 0x40006802u\r
+#define CYREG_B0_UDB02_03_A0 0x40006804u\r
+#define CYREG_B0_UDB03_04_A0 0x40006806u\r
+#define CYREG_B0_UDB04_05_A0 0x40006808u\r
+#define CYREG_B0_UDB05_06_A0 0x4000680au\r
+#define CYREG_B0_UDB06_07_A0 0x4000680cu\r
+#define CYREG_B0_UDB07_08_A0 0x4000680eu\r
+#define CYREG_B0_UDB08_09_A0 0x40006810u\r
+#define CYREG_B0_UDB09_10_A0 0x40006812u\r
+#define CYREG_B0_UDB10_11_A0 0x40006814u\r
+#define CYREG_B0_UDB11_12_A0 0x40006816u\r
+#define CYREG_B0_UDB12_13_A0 0x40006818u\r
+#define CYREG_B0_UDB13_14_A0 0x4000681au\r
+#define CYREG_B0_UDB14_15_A0 0x4000681cu\r
+#define CYREG_B0_UDB00_01_A1 0x40006820u\r
+#define CYREG_B0_UDB01_02_A1 0x40006822u\r
+#define CYREG_B0_UDB02_03_A1 0x40006824u\r
+#define CYREG_B0_UDB03_04_A1 0x40006826u\r
+#define CYREG_B0_UDB04_05_A1 0x40006828u\r
+#define CYREG_B0_UDB05_06_A1 0x4000682au\r
+#define CYREG_B0_UDB06_07_A1 0x4000682cu\r
+#define CYREG_B0_UDB07_08_A1 0x4000682eu\r
+#define CYREG_B0_UDB08_09_A1 0x40006830u\r
+#define CYREG_B0_UDB09_10_A1 0x40006832u\r
+#define CYREG_B0_UDB10_11_A1 0x40006834u\r
+#define CYREG_B0_UDB11_12_A1 0x40006836u\r
+#define CYREG_B0_UDB12_13_A1 0x40006838u\r
+#define CYREG_B0_UDB13_14_A1 0x4000683au\r
+#define CYREG_B0_UDB14_15_A1 0x4000683cu\r
+#define CYREG_B0_UDB00_01_D0 0x40006840u\r
+#define CYREG_B0_UDB01_02_D0 0x40006842u\r
+#define CYREG_B0_UDB02_03_D0 0x40006844u\r
+#define CYREG_B0_UDB03_04_D0 0x40006846u\r
+#define CYREG_B0_UDB04_05_D0 0x40006848u\r
+#define CYREG_B0_UDB05_06_D0 0x4000684au\r
+#define CYREG_B0_UDB06_07_D0 0x4000684cu\r
+#define CYREG_B0_UDB07_08_D0 0x4000684eu\r
+#define CYREG_B0_UDB08_09_D0 0x40006850u\r
+#define CYREG_B0_UDB09_10_D0 0x40006852u\r
+#define CYREG_B0_UDB10_11_D0 0x40006854u\r
+#define CYREG_B0_UDB11_12_D0 0x40006856u\r
+#define CYREG_B0_UDB12_13_D0 0x40006858u\r
+#define CYREG_B0_UDB13_14_D0 0x4000685au\r
+#define CYREG_B0_UDB14_15_D0 0x4000685cu\r
+#define CYREG_B0_UDB00_01_D1 0x40006860u\r
+#define CYREG_B0_UDB01_02_D1 0x40006862u\r
+#define CYREG_B0_UDB02_03_D1 0x40006864u\r
+#define CYREG_B0_UDB03_04_D1 0x40006866u\r
+#define CYREG_B0_UDB04_05_D1 0x40006868u\r
+#define CYREG_B0_UDB05_06_D1 0x4000686au\r
+#define CYREG_B0_UDB06_07_D1 0x4000686cu\r
+#define CYREG_B0_UDB07_08_D1 0x4000686eu\r
+#define CYREG_B0_UDB08_09_D1 0x40006870u\r
+#define CYREG_B0_UDB09_10_D1 0x40006872u\r
+#define CYREG_B0_UDB10_11_D1 0x40006874u\r
+#define CYREG_B0_UDB11_12_D1 0x40006876u\r
+#define CYREG_B0_UDB12_13_D1 0x40006878u\r
+#define CYREG_B0_UDB13_14_D1 0x4000687au\r
+#define CYREG_B0_UDB14_15_D1 0x4000687cu\r
+#define CYREG_B0_UDB00_01_F0 0x40006880u\r
+#define CYREG_B0_UDB01_02_F0 0x40006882u\r
+#define CYREG_B0_UDB02_03_F0 0x40006884u\r
+#define CYREG_B0_UDB03_04_F0 0x40006886u\r
+#define CYREG_B0_UDB04_05_F0 0x40006888u\r
+#define CYREG_B0_UDB05_06_F0 0x4000688au\r
+#define CYREG_B0_UDB06_07_F0 0x4000688cu\r
+#define CYREG_B0_UDB07_08_F0 0x4000688eu\r
+#define CYREG_B0_UDB08_09_F0 0x40006890u\r
+#define CYREG_B0_UDB09_10_F0 0x40006892u\r
+#define CYREG_B0_UDB10_11_F0 0x40006894u\r
+#define CYREG_B0_UDB11_12_F0 0x40006896u\r
+#define CYREG_B0_UDB12_13_F0 0x40006898u\r
+#define CYREG_B0_UDB13_14_F0 0x4000689au\r
+#define CYREG_B0_UDB14_15_F0 0x4000689cu\r
+#define CYREG_B0_UDB00_01_F1 0x400068a0u\r
+#define CYREG_B0_UDB01_02_F1 0x400068a2u\r
+#define CYREG_B0_UDB02_03_F1 0x400068a4u\r
+#define CYREG_B0_UDB03_04_F1 0x400068a6u\r
+#define CYREG_B0_UDB04_05_F1 0x400068a8u\r
+#define CYREG_B0_UDB05_06_F1 0x400068aau\r
+#define CYREG_B0_UDB06_07_F1 0x400068acu\r
+#define CYREG_B0_UDB07_08_F1 0x400068aeu\r
+#define CYREG_B0_UDB08_09_F1 0x400068b0u\r
+#define CYREG_B0_UDB09_10_F1 0x400068b2u\r
+#define CYREG_B0_UDB10_11_F1 0x400068b4u\r
+#define CYREG_B0_UDB11_12_F1 0x400068b6u\r
+#define CYREG_B0_UDB12_13_F1 0x400068b8u\r
+#define CYREG_B0_UDB13_14_F1 0x400068bau\r
+#define CYREG_B0_UDB14_15_F1 0x400068bcu\r
+#define CYREG_B0_UDB00_01_ST 0x400068c0u\r
+#define CYREG_B0_UDB01_02_ST 0x400068c2u\r
+#define CYREG_B0_UDB02_03_ST 0x400068c4u\r
+#define CYREG_B0_UDB03_04_ST 0x400068c6u\r
+#define CYREG_B0_UDB04_05_ST 0x400068c8u\r
+#define CYREG_B0_UDB05_06_ST 0x400068cau\r
+#define CYREG_B0_UDB06_07_ST 0x400068ccu\r
+#define CYREG_B0_UDB07_08_ST 0x400068ceu\r
+#define CYREG_B0_UDB08_09_ST 0x400068d0u\r
+#define CYREG_B0_UDB09_10_ST 0x400068d2u\r
+#define CYREG_B0_UDB10_11_ST 0x400068d4u\r
+#define CYREG_B0_UDB11_12_ST 0x400068d6u\r
+#define CYREG_B0_UDB12_13_ST 0x400068d8u\r
+#define CYREG_B0_UDB13_14_ST 0x400068dau\r
+#define CYREG_B0_UDB14_15_ST 0x400068dcu\r
+#define CYREG_B0_UDB00_01_CTL 0x400068e0u\r
+#define CYREG_B0_UDB01_02_CTL 0x400068e2u\r
+#define CYREG_B0_UDB02_03_CTL 0x400068e4u\r
+#define CYREG_B0_UDB03_04_CTL 0x400068e6u\r
+#define CYREG_B0_UDB04_05_CTL 0x400068e8u\r
+#define CYREG_B0_UDB05_06_CTL 0x400068eau\r
+#define CYREG_B0_UDB06_07_CTL 0x400068ecu\r
+#define CYREG_B0_UDB07_08_CTL 0x400068eeu\r
+#define CYREG_B0_UDB08_09_CTL 0x400068f0u\r
+#define CYREG_B0_UDB09_10_CTL 0x400068f2u\r
+#define CYREG_B0_UDB10_11_CTL 0x400068f4u\r
+#define CYREG_B0_UDB11_12_CTL 0x400068f6u\r
+#define CYREG_B0_UDB12_13_CTL 0x400068f8u\r
+#define CYREG_B0_UDB13_14_CTL 0x400068fau\r
+#define CYREG_B0_UDB14_15_CTL 0x400068fcu\r
+#define CYREG_B0_UDB00_01_MSK 0x40006900u\r
+#define CYREG_B0_UDB01_02_MSK 0x40006902u\r
+#define CYREG_B0_UDB02_03_MSK 0x40006904u\r
+#define CYREG_B0_UDB03_04_MSK 0x40006906u\r
+#define CYREG_B0_UDB04_05_MSK 0x40006908u\r
+#define CYREG_B0_UDB05_06_MSK 0x4000690au\r
+#define CYREG_B0_UDB06_07_MSK 0x4000690cu\r
+#define CYREG_B0_UDB07_08_MSK 0x4000690eu\r
+#define CYREG_B0_UDB08_09_MSK 0x40006910u\r
+#define CYREG_B0_UDB09_10_MSK 0x40006912u\r
+#define CYREG_B0_UDB10_11_MSK 0x40006914u\r
+#define CYREG_B0_UDB11_12_MSK 0x40006916u\r
+#define CYREG_B0_UDB12_13_MSK 0x40006918u\r
+#define CYREG_B0_UDB13_14_MSK 0x4000691au\r
+#define CYREG_B0_UDB14_15_MSK 0x4000691cu\r
+#define CYREG_B0_UDB00_01_ACTL 0x40006920u\r
+#define CYREG_B0_UDB01_02_ACTL 0x40006922u\r
+#define CYREG_B0_UDB02_03_ACTL 0x40006924u\r
+#define CYREG_B0_UDB03_04_ACTL 0x40006926u\r
+#define CYREG_B0_UDB04_05_ACTL 0x40006928u\r
+#define CYREG_B0_UDB05_06_ACTL 0x4000692au\r
+#define CYREG_B0_UDB06_07_ACTL 0x4000692cu\r
+#define CYREG_B0_UDB07_08_ACTL 0x4000692eu\r
+#define CYREG_B0_UDB08_09_ACTL 0x40006930u\r
+#define CYREG_B0_UDB09_10_ACTL 0x40006932u\r
+#define CYREG_B0_UDB10_11_ACTL 0x40006934u\r
+#define CYREG_B0_UDB11_12_ACTL 0x40006936u\r
+#define CYREG_B0_UDB12_13_ACTL 0x40006938u\r
+#define CYREG_B0_UDB13_14_ACTL 0x4000693au\r
+#define CYREG_B0_UDB14_15_ACTL 0x4000693cu\r
+#define CYREG_B0_UDB00_01_MC 0x40006940u\r
+#define CYREG_B0_UDB01_02_MC 0x40006942u\r
+#define CYREG_B0_UDB02_03_MC 0x40006944u\r
+#define CYREG_B0_UDB03_04_MC 0x40006946u\r
+#define CYREG_B0_UDB04_05_MC 0x40006948u\r
+#define CYREG_B0_UDB05_06_MC 0x4000694au\r
+#define CYREG_B0_UDB06_07_MC 0x4000694cu\r
+#define CYREG_B0_UDB07_08_MC 0x4000694eu\r
+#define CYREG_B0_UDB08_09_MC 0x40006950u\r
+#define CYREG_B0_UDB09_10_MC 0x40006952u\r
+#define CYREG_B0_UDB10_11_MC 0x40006954u\r
+#define CYREG_B0_UDB11_12_MC 0x40006956u\r
+#define CYREG_B0_UDB12_13_MC 0x40006958u\r
+#define CYREG_B0_UDB13_14_MC 0x4000695au\r
+#define CYREG_B0_UDB14_15_MC 0x4000695cu\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00u\r
+#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015eu\r
+#define CYREG_B1_UDB04_05_A0 0x40006a08u\r
+#define CYREG_B1_UDB05_06_A0 0x40006a0au\r
+#define CYREG_B1_UDB06_07_A0 0x40006a0cu\r
+#define CYREG_B1_UDB07_08_A0 0x40006a0eu\r
+#define CYREG_B1_UDB08_09_A0 0x40006a10u\r
+#define CYREG_B1_UDB09_10_A0 0x40006a12u\r
+#define CYREG_B1_UDB10_11_A0 0x40006a14u\r
+#define CYREG_B1_UDB11_12_A0 0x40006a16u\r
+#define CYREG_B1_UDB04_05_A1 0x40006a28u\r
+#define CYREG_B1_UDB05_06_A1 0x40006a2au\r
+#define CYREG_B1_UDB06_07_A1 0x40006a2cu\r
+#define CYREG_B1_UDB07_08_A1 0x40006a2eu\r
+#define CYREG_B1_UDB08_09_A1 0x40006a30u\r
+#define CYREG_B1_UDB09_10_A1 0x40006a32u\r
+#define CYREG_B1_UDB10_11_A1 0x40006a34u\r
+#define CYREG_B1_UDB11_12_A1 0x40006a36u\r
+#define CYREG_B1_UDB04_05_D0 0x40006a48u\r
+#define CYREG_B1_UDB05_06_D0 0x40006a4au\r
+#define CYREG_B1_UDB06_07_D0 0x40006a4cu\r
+#define CYREG_B1_UDB07_08_D0 0x40006a4eu\r
+#define CYREG_B1_UDB08_09_D0 0x40006a50u\r
+#define CYREG_B1_UDB09_10_D0 0x40006a52u\r
+#define CYREG_B1_UDB10_11_D0 0x40006a54u\r
+#define CYREG_B1_UDB11_12_D0 0x40006a56u\r
+#define CYREG_B1_UDB04_05_D1 0x40006a68u\r
+#define CYREG_B1_UDB05_06_D1 0x40006a6au\r
+#define CYREG_B1_UDB06_07_D1 0x40006a6cu\r
+#define CYREG_B1_UDB07_08_D1 0x40006a6eu\r
+#define CYREG_B1_UDB08_09_D1 0x40006a70u\r
+#define CYREG_B1_UDB09_10_D1 0x40006a72u\r
+#define CYREG_B1_UDB10_11_D1 0x40006a74u\r
+#define CYREG_B1_UDB11_12_D1 0x40006a76u\r
+#define CYREG_B1_UDB04_05_F0 0x40006a88u\r
+#define CYREG_B1_UDB05_06_F0 0x40006a8au\r
+#define CYREG_B1_UDB06_07_F0 0x40006a8cu\r
+#define CYREG_B1_UDB07_08_F0 0x40006a8eu\r
+#define CYREG_B1_UDB08_09_F0 0x40006a90u\r
+#define CYREG_B1_UDB09_10_F0 0x40006a92u\r
+#define CYREG_B1_UDB10_11_F0 0x40006a94u\r
+#define CYREG_B1_UDB11_12_F0 0x40006a96u\r
+#define CYREG_B1_UDB04_05_F1 0x40006aa8u\r
+#define CYREG_B1_UDB05_06_F1 0x40006aaau\r
+#define CYREG_B1_UDB06_07_F1 0x40006aacu\r
+#define CYREG_B1_UDB07_08_F1 0x40006aaeu\r
+#define CYREG_B1_UDB08_09_F1 0x40006ab0u\r
+#define CYREG_B1_UDB09_10_F1 0x40006ab2u\r
+#define CYREG_B1_UDB10_11_F1 0x40006ab4u\r
+#define CYREG_B1_UDB11_12_F1 0x40006ab6u\r
+#define CYREG_B1_UDB04_05_ST 0x40006ac8u\r
+#define CYREG_B1_UDB05_06_ST 0x40006acau\r
+#define CYREG_B1_UDB06_07_ST 0x40006accu\r
+#define CYREG_B1_UDB07_08_ST 0x40006aceu\r
+#define CYREG_B1_UDB08_09_ST 0x40006ad0u\r
+#define CYREG_B1_UDB09_10_ST 0x40006ad2u\r
+#define CYREG_B1_UDB10_11_ST 0x40006ad4u\r
+#define CYREG_B1_UDB11_12_ST 0x40006ad6u\r
+#define CYREG_B1_UDB04_05_CTL 0x40006ae8u\r
+#define CYREG_B1_UDB05_06_CTL 0x40006aeau\r
+#define CYREG_B1_UDB06_07_CTL 0x40006aecu\r
+#define CYREG_B1_UDB07_08_CTL 0x40006aeeu\r
+#define CYREG_B1_UDB08_09_CTL 0x40006af0u\r
+#define CYREG_B1_UDB09_10_CTL 0x40006af2u\r
+#define CYREG_B1_UDB10_11_CTL 0x40006af4u\r
+#define CYREG_B1_UDB11_12_CTL 0x40006af6u\r
+#define CYREG_B1_UDB04_05_MSK 0x40006b08u\r
+#define CYREG_B1_UDB05_06_MSK 0x40006b0au\r
+#define CYREG_B1_UDB06_07_MSK 0x40006b0cu\r
+#define CYREG_B1_UDB07_08_MSK 0x40006b0eu\r
+#define CYREG_B1_UDB08_09_MSK 0x40006b10u\r
+#define CYREG_B1_UDB09_10_MSK 0x40006b12u\r
+#define CYREG_B1_UDB10_11_MSK 0x40006b14u\r
+#define CYREG_B1_UDB11_12_MSK 0x40006b16u\r
+#define CYREG_B1_UDB04_05_ACTL 0x40006b28u\r
+#define CYREG_B1_UDB05_06_ACTL 0x40006b2au\r
+#define CYREG_B1_UDB06_07_ACTL 0x40006b2cu\r
+#define CYREG_B1_UDB07_08_ACTL 0x40006b2eu\r
+#define CYREG_B1_UDB08_09_ACTL 0x40006b30u\r
+#define CYREG_B1_UDB09_10_ACTL 0x40006b32u\r
+#define CYREG_B1_UDB10_11_ACTL 0x40006b34u\r
+#define CYREG_B1_UDB11_12_ACTL 0x40006b36u\r
+#define CYREG_B1_UDB04_05_MC 0x40006b48u\r
+#define CYREG_B1_UDB05_06_MC 0x40006b4au\r
+#define CYREG_B1_UDB06_07_MC 0x40006b4cu\r
+#define CYREG_B1_UDB07_08_MC 0x40006b4eu\r
+#define CYREG_B1_UDB08_09_MC 0x40006b50u\r
+#define CYREG_B1_UDB09_10_MC 0x40006b52u\r
+#define CYREG_B1_UDB10_11_MC 0x40006b54u\r
+#define CYREG_B1_UDB11_12_MC 0x40006b56u\r
+#define CYDEV_PHUB_BASE 0x40007000u\r
+#define CYDEV_PHUB_SIZE 0x00000c00u\r
+#define CYREG_PHUB_CFG 0x40007000u\r
+#define CYREG_PHUB_ERR 0x40007004u\r
+#define CYREG_PHUB_ERR_ADR 0x40007008u\r
+#define CYDEV_PHUB_CH0_BASE 0x40007010u\r
+#define CYDEV_PHUB_CH0_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH0_BASIC_CFG 0x40007010u\r
+#define CYREG_PHUB_CH0_ACTION 0x40007014u\r
+#define CYREG_PHUB_CH0_BASIC_STATUS 0x40007018u\r
+#define CYDEV_PHUB_CH1_BASE 0x40007020u\r
+#define CYDEV_PHUB_CH1_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH1_BASIC_CFG 0x40007020u\r
+#define CYREG_PHUB_CH1_ACTION 0x40007024u\r
+#define CYREG_PHUB_CH1_BASIC_STATUS 0x40007028u\r
+#define CYDEV_PHUB_CH2_BASE 0x40007030u\r
+#define CYDEV_PHUB_CH2_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH2_BASIC_CFG 0x40007030u\r
+#define CYREG_PHUB_CH2_ACTION 0x40007034u\r
+#define CYREG_PHUB_CH2_BASIC_STATUS 0x40007038u\r
+#define CYDEV_PHUB_CH3_BASE 0x40007040u\r
+#define CYDEV_PHUB_CH3_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH3_BASIC_CFG 0x40007040u\r
+#define CYREG_PHUB_CH3_ACTION 0x40007044u\r
+#define CYREG_PHUB_CH3_BASIC_STATUS 0x40007048u\r
+#define CYDEV_PHUB_CH4_BASE 0x40007050u\r
+#define CYDEV_PHUB_CH4_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH4_BASIC_CFG 0x40007050u\r
+#define CYREG_PHUB_CH4_ACTION 0x40007054u\r
+#define CYREG_PHUB_CH4_BASIC_STATUS 0x40007058u\r
+#define CYDEV_PHUB_CH5_BASE 0x40007060u\r
+#define CYDEV_PHUB_CH5_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH5_BASIC_CFG 0x40007060u\r
+#define CYREG_PHUB_CH5_ACTION 0x40007064u\r
+#define CYREG_PHUB_CH5_BASIC_STATUS 0x40007068u\r
+#define CYDEV_PHUB_CH6_BASE 0x40007070u\r
+#define CYDEV_PHUB_CH6_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH6_BASIC_CFG 0x40007070u\r
+#define CYREG_PHUB_CH6_ACTION 0x40007074u\r
+#define CYREG_PHUB_CH6_BASIC_STATUS 0x40007078u\r
+#define CYDEV_PHUB_CH7_BASE 0x40007080u\r
+#define CYDEV_PHUB_CH7_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH7_BASIC_CFG 0x40007080u\r
+#define CYREG_PHUB_CH7_ACTION 0x40007084u\r
+#define CYREG_PHUB_CH7_BASIC_STATUS 0x40007088u\r
+#define CYDEV_PHUB_CH8_BASE 0x40007090u\r
+#define CYDEV_PHUB_CH8_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH8_BASIC_CFG 0x40007090u\r
+#define CYREG_PHUB_CH8_ACTION 0x40007094u\r
+#define CYREG_PHUB_CH8_BASIC_STATUS 0x40007098u\r
+#define CYDEV_PHUB_CH9_BASE 0x400070a0u\r
+#define CYDEV_PHUB_CH9_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH9_BASIC_CFG 0x400070a0u\r
+#define CYREG_PHUB_CH9_ACTION 0x400070a4u\r
+#define CYREG_PHUB_CH9_BASIC_STATUS 0x400070a8u\r
+#define CYDEV_PHUB_CH10_BASE 0x400070b0u\r
+#define CYDEV_PHUB_CH10_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH10_BASIC_CFG 0x400070b0u\r
+#define CYREG_PHUB_CH10_ACTION 0x400070b4u\r
+#define CYREG_PHUB_CH10_BASIC_STATUS 0x400070b8u\r
+#define CYDEV_PHUB_CH11_BASE 0x400070c0u\r
+#define CYDEV_PHUB_CH11_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH11_BASIC_CFG 0x400070c0u\r
+#define CYREG_PHUB_CH11_ACTION 0x400070c4u\r
+#define CYREG_PHUB_CH11_BASIC_STATUS 0x400070c8u\r
+#define CYDEV_PHUB_CH12_BASE 0x400070d0u\r
+#define CYDEV_PHUB_CH12_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH12_BASIC_CFG 0x400070d0u\r
+#define CYREG_PHUB_CH12_ACTION 0x400070d4u\r
+#define CYREG_PHUB_CH12_BASIC_STATUS 0x400070d8u\r
+#define CYDEV_PHUB_CH13_BASE 0x400070e0u\r
+#define CYDEV_PHUB_CH13_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH13_BASIC_CFG 0x400070e0u\r
+#define CYREG_PHUB_CH13_ACTION 0x400070e4u\r
+#define CYREG_PHUB_CH13_BASIC_STATUS 0x400070e8u\r
+#define CYDEV_PHUB_CH14_BASE 0x400070f0u\r
+#define CYDEV_PHUB_CH14_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH14_BASIC_CFG 0x400070f0u\r
+#define CYREG_PHUB_CH14_ACTION 0x400070f4u\r
+#define CYREG_PHUB_CH14_BASIC_STATUS 0x400070f8u\r
+#define CYDEV_PHUB_CH15_BASE 0x40007100u\r
+#define CYDEV_PHUB_CH15_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH15_BASIC_CFG 0x40007100u\r
+#define CYREG_PHUB_CH15_ACTION 0x40007104u\r
+#define CYREG_PHUB_CH15_BASIC_STATUS 0x40007108u\r
+#define CYDEV_PHUB_CH16_BASE 0x40007110u\r
+#define CYDEV_PHUB_CH16_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH16_BASIC_CFG 0x40007110u\r
+#define CYREG_PHUB_CH16_ACTION 0x40007114u\r
+#define CYREG_PHUB_CH16_BASIC_STATUS 0x40007118u\r
+#define CYDEV_PHUB_CH17_BASE 0x40007120u\r
+#define CYDEV_PHUB_CH17_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH17_BASIC_CFG 0x40007120u\r
+#define CYREG_PHUB_CH17_ACTION 0x40007124u\r
+#define CYREG_PHUB_CH17_BASIC_STATUS 0x40007128u\r
+#define CYDEV_PHUB_CH18_BASE 0x40007130u\r
+#define CYDEV_PHUB_CH18_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH18_BASIC_CFG 0x40007130u\r
+#define CYREG_PHUB_CH18_ACTION 0x40007134u\r
+#define CYREG_PHUB_CH18_BASIC_STATUS 0x40007138u\r
+#define CYDEV_PHUB_CH19_BASE 0x40007140u\r
+#define CYDEV_PHUB_CH19_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH19_BASIC_CFG 0x40007140u\r
+#define CYREG_PHUB_CH19_ACTION 0x40007144u\r
+#define CYREG_PHUB_CH19_BASIC_STATUS 0x40007148u\r
+#define CYDEV_PHUB_CH20_BASE 0x40007150u\r
+#define CYDEV_PHUB_CH20_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH20_BASIC_CFG 0x40007150u\r
+#define CYREG_PHUB_CH20_ACTION 0x40007154u\r
+#define CYREG_PHUB_CH20_BASIC_STATUS 0x40007158u\r
+#define CYDEV_PHUB_CH21_BASE 0x40007160u\r
+#define CYDEV_PHUB_CH21_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH21_BASIC_CFG 0x40007160u\r
+#define CYREG_PHUB_CH21_ACTION 0x40007164u\r
+#define CYREG_PHUB_CH21_BASIC_STATUS 0x40007168u\r
+#define CYDEV_PHUB_CH22_BASE 0x40007170u\r
+#define CYDEV_PHUB_CH22_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH22_BASIC_CFG 0x40007170u\r
+#define CYREG_PHUB_CH22_ACTION 0x40007174u\r
+#define CYREG_PHUB_CH22_BASIC_STATUS 0x40007178u\r
+#define CYDEV_PHUB_CH23_BASE 0x40007180u\r
+#define CYDEV_PHUB_CH23_SIZE 0x0000000cu\r
+#define CYREG_PHUB_CH23_BASIC_CFG 0x40007180u\r
+#define CYREG_PHUB_CH23_ACTION 0x40007184u\r
+#define CYREG_PHUB_CH23_BASIC_STATUS 0x40007188u\r
+#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600u\r
+#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM0_CFG0 0x40007600u\r
+#define CYREG_PHUB_CFGMEM0_CFG1 0x40007604u\r
+#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608u\r
+#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM1_CFG0 0x40007608u\r
+#define CYREG_PHUB_CFGMEM1_CFG1 0x4000760cu\r
+#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610u\r
+#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM2_CFG0 0x40007610u\r
+#define CYREG_PHUB_CFGMEM2_CFG1 0x40007614u\r
+#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618u\r
+#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM3_CFG0 0x40007618u\r
+#define CYREG_PHUB_CFGMEM3_CFG1 0x4000761cu\r
+#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620u\r
+#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM4_CFG0 0x40007620u\r
+#define CYREG_PHUB_CFGMEM4_CFG1 0x40007624u\r
+#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628u\r
+#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM5_CFG0 0x40007628u\r
+#define CYREG_PHUB_CFGMEM5_CFG1 0x4000762cu\r
+#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630u\r
+#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM6_CFG0 0x40007630u\r
+#define CYREG_PHUB_CFGMEM6_CFG1 0x40007634u\r
+#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638u\r
+#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM7_CFG0 0x40007638u\r
+#define CYREG_PHUB_CFGMEM7_CFG1 0x4000763cu\r
+#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640u\r
+#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM8_CFG0 0x40007640u\r
+#define CYREG_PHUB_CFGMEM8_CFG1 0x40007644u\r
+#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648u\r
+#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM9_CFG0 0x40007648u\r
+#define CYREG_PHUB_CFGMEM9_CFG1 0x4000764cu\r
+#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650u\r
+#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM10_CFG0 0x40007650u\r
+#define CYREG_PHUB_CFGMEM10_CFG1 0x40007654u\r
+#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658u\r
+#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM11_CFG0 0x40007658u\r
+#define CYREG_PHUB_CFGMEM11_CFG1 0x4000765cu\r
+#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660u\r
+#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM12_CFG0 0x40007660u\r
+#define CYREG_PHUB_CFGMEM12_CFG1 0x40007664u\r
+#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668u\r
+#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM13_CFG0 0x40007668u\r
+#define CYREG_PHUB_CFGMEM13_CFG1 0x4000766cu\r
+#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670u\r
+#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM14_CFG0 0x40007670u\r
+#define CYREG_PHUB_CFGMEM14_CFG1 0x40007674u\r
+#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678u\r
+#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM15_CFG0 0x40007678u\r
+#define CYREG_PHUB_CFGMEM15_CFG1 0x4000767cu\r
+#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680u\r
+#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM16_CFG0 0x40007680u\r
+#define CYREG_PHUB_CFGMEM16_CFG1 0x40007684u\r
+#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688u\r
+#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM17_CFG0 0x40007688u\r
+#define CYREG_PHUB_CFGMEM17_CFG1 0x4000768cu\r
+#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690u\r
+#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM18_CFG0 0x40007690u\r
+#define CYREG_PHUB_CFGMEM18_CFG1 0x40007694u\r
+#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698u\r
+#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM19_CFG0 0x40007698u\r
+#define CYREG_PHUB_CFGMEM19_CFG1 0x4000769cu\r
+#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0u\r
+#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM20_CFG0 0x400076a0u\r
+#define CYREG_PHUB_CFGMEM20_CFG1 0x400076a4u\r
+#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8u\r
+#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM21_CFG0 0x400076a8u\r
+#define CYREG_PHUB_CFGMEM21_CFG1 0x400076acu\r
+#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0u\r
+#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM22_CFG0 0x400076b0u\r
+#define CYREG_PHUB_CFGMEM22_CFG1 0x400076b4u\r
+#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8u\r
+#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008u\r
+#define CYREG_PHUB_CFGMEM23_CFG0 0x400076b8u\r
+#define CYREG_PHUB_CFGMEM23_CFG1 0x400076bcu\r
+#define CYDEV_PHUB_TDMEM0_BASE 0x40007800u\r
+#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM0_ORIG_TD0 0x40007800u\r
+#define CYREG_PHUB_TDMEM0_ORIG_TD1 0x40007804u\r
+#define CYDEV_PHUB_TDMEM1_BASE 0x40007808u\r
+#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM1_ORIG_TD0 0x40007808u\r
+#define CYREG_PHUB_TDMEM1_ORIG_TD1 0x4000780cu\r
+#define CYDEV_PHUB_TDMEM2_BASE 0x40007810u\r
+#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM2_ORIG_TD0 0x40007810u\r
+#define CYREG_PHUB_TDMEM2_ORIG_TD1 0x40007814u\r
+#define CYDEV_PHUB_TDMEM3_BASE 0x40007818u\r
+#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM3_ORIG_TD0 0x40007818u\r
+#define CYREG_PHUB_TDMEM3_ORIG_TD1 0x4000781cu\r
+#define CYDEV_PHUB_TDMEM4_BASE 0x40007820u\r
+#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM4_ORIG_TD0 0x40007820u\r
+#define CYREG_PHUB_TDMEM4_ORIG_TD1 0x40007824u\r
+#define CYDEV_PHUB_TDMEM5_BASE 0x40007828u\r
+#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM5_ORIG_TD0 0x40007828u\r
+#define CYREG_PHUB_TDMEM5_ORIG_TD1 0x4000782cu\r
+#define CYDEV_PHUB_TDMEM6_BASE 0x40007830u\r
+#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM6_ORIG_TD0 0x40007830u\r
+#define CYREG_PHUB_TDMEM6_ORIG_TD1 0x40007834u\r
+#define CYDEV_PHUB_TDMEM7_BASE 0x40007838u\r
+#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM7_ORIG_TD0 0x40007838u\r
+#define CYREG_PHUB_TDMEM7_ORIG_TD1 0x4000783cu\r
+#define CYDEV_PHUB_TDMEM8_BASE 0x40007840u\r
+#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM8_ORIG_TD0 0x40007840u\r
+#define CYREG_PHUB_TDMEM8_ORIG_TD1 0x40007844u\r
+#define CYDEV_PHUB_TDMEM9_BASE 0x40007848u\r
+#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM9_ORIG_TD0 0x40007848u\r
+#define CYREG_PHUB_TDMEM9_ORIG_TD1 0x4000784cu\r
+#define CYDEV_PHUB_TDMEM10_BASE 0x40007850u\r
+#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM10_ORIG_TD0 0x40007850u\r
+#define CYREG_PHUB_TDMEM10_ORIG_TD1 0x40007854u\r
+#define CYDEV_PHUB_TDMEM11_BASE 0x40007858u\r
+#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM11_ORIG_TD0 0x40007858u\r
+#define CYREG_PHUB_TDMEM11_ORIG_TD1 0x4000785cu\r
+#define CYDEV_PHUB_TDMEM12_BASE 0x40007860u\r
+#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM12_ORIG_TD0 0x40007860u\r
+#define CYREG_PHUB_TDMEM12_ORIG_TD1 0x40007864u\r
+#define CYDEV_PHUB_TDMEM13_BASE 0x40007868u\r
+#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM13_ORIG_TD0 0x40007868u\r
+#define CYREG_PHUB_TDMEM13_ORIG_TD1 0x4000786cu\r
+#define CYDEV_PHUB_TDMEM14_BASE 0x40007870u\r
+#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM14_ORIG_TD0 0x40007870u\r
+#define CYREG_PHUB_TDMEM14_ORIG_TD1 0x40007874u\r
+#define CYDEV_PHUB_TDMEM15_BASE 0x40007878u\r
+#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM15_ORIG_TD0 0x40007878u\r
+#define CYREG_PHUB_TDMEM15_ORIG_TD1 0x4000787cu\r
+#define CYDEV_PHUB_TDMEM16_BASE 0x40007880u\r
+#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM16_ORIG_TD0 0x40007880u\r
+#define CYREG_PHUB_TDMEM16_ORIG_TD1 0x40007884u\r
+#define CYDEV_PHUB_TDMEM17_BASE 0x40007888u\r
+#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM17_ORIG_TD0 0x40007888u\r
+#define CYREG_PHUB_TDMEM17_ORIG_TD1 0x4000788cu\r
+#define CYDEV_PHUB_TDMEM18_BASE 0x40007890u\r
+#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM18_ORIG_TD0 0x40007890u\r
+#define CYREG_PHUB_TDMEM18_ORIG_TD1 0x40007894u\r
+#define CYDEV_PHUB_TDMEM19_BASE 0x40007898u\r
+#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM19_ORIG_TD0 0x40007898u\r
+#define CYREG_PHUB_TDMEM19_ORIG_TD1 0x4000789cu\r
+#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0u\r
+#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM20_ORIG_TD0 0x400078a0u\r
+#define CYREG_PHUB_TDMEM20_ORIG_TD1 0x400078a4u\r
+#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8u\r
+#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM21_ORIG_TD0 0x400078a8u\r
+#define CYREG_PHUB_TDMEM21_ORIG_TD1 0x400078acu\r
+#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0u\r
+#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM22_ORIG_TD0 0x400078b0u\r
+#define CYREG_PHUB_TDMEM22_ORIG_TD1 0x400078b4u\r
+#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8u\r
+#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM23_ORIG_TD0 0x400078b8u\r
+#define CYREG_PHUB_TDMEM23_ORIG_TD1 0x400078bcu\r
+#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0u\r
+#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM24_ORIG_TD0 0x400078c0u\r
+#define CYREG_PHUB_TDMEM24_ORIG_TD1 0x400078c4u\r
+#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8u\r
+#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM25_ORIG_TD0 0x400078c8u\r
+#define CYREG_PHUB_TDMEM25_ORIG_TD1 0x400078ccu\r
+#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0u\r
+#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM26_ORIG_TD0 0x400078d0u\r
+#define CYREG_PHUB_TDMEM26_ORIG_TD1 0x400078d4u\r
+#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8u\r
+#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM27_ORIG_TD0 0x400078d8u\r
+#define CYREG_PHUB_TDMEM27_ORIG_TD1 0x400078dcu\r
+#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0u\r
+#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM28_ORIG_TD0 0x400078e0u\r
+#define CYREG_PHUB_TDMEM28_ORIG_TD1 0x400078e4u\r
+#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8u\r
+#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM29_ORIG_TD0 0x400078e8u\r
+#define CYREG_PHUB_TDMEM29_ORIG_TD1 0x400078ecu\r
+#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0u\r
+#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM30_ORIG_TD0 0x400078f0u\r
+#define CYREG_PHUB_TDMEM30_ORIG_TD1 0x400078f4u\r
+#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8u\r
+#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM31_ORIG_TD0 0x400078f8u\r
+#define CYREG_PHUB_TDMEM31_ORIG_TD1 0x400078fcu\r
+#define CYDEV_PHUB_TDMEM32_BASE 0x40007900u\r
+#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM32_ORIG_TD0 0x40007900u\r
+#define CYREG_PHUB_TDMEM32_ORIG_TD1 0x40007904u\r
+#define CYDEV_PHUB_TDMEM33_BASE 0x40007908u\r
+#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM33_ORIG_TD0 0x40007908u\r
+#define CYREG_PHUB_TDMEM33_ORIG_TD1 0x4000790cu\r
+#define CYDEV_PHUB_TDMEM34_BASE 0x40007910u\r
+#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM34_ORIG_TD0 0x40007910u\r
+#define CYREG_PHUB_TDMEM34_ORIG_TD1 0x40007914u\r
+#define CYDEV_PHUB_TDMEM35_BASE 0x40007918u\r
+#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM35_ORIG_TD0 0x40007918u\r
+#define CYREG_PHUB_TDMEM35_ORIG_TD1 0x4000791cu\r
+#define CYDEV_PHUB_TDMEM36_BASE 0x40007920u\r
+#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM36_ORIG_TD0 0x40007920u\r
+#define CYREG_PHUB_TDMEM36_ORIG_TD1 0x40007924u\r
+#define CYDEV_PHUB_TDMEM37_BASE 0x40007928u\r
+#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM37_ORIG_TD0 0x40007928u\r
+#define CYREG_PHUB_TDMEM37_ORIG_TD1 0x4000792cu\r
+#define CYDEV_PHUB_TDMEM38_BASE 0x40007930u\r
+#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM38_ORIG_TD0 0x40007930u\r
+#define CYREG_PHUB_TDMEM38_ORIG_TD1 0x40007934u\r
+#define CYDEV_PHUB_TDMEM39_BASE 0x40007938u\r
+#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM39_ORIG_TD0 0x40007938u\r
+#define CYREG_PHUB_TDMEM39_ORIG_TD1 0x4000793cu\r
+#define CYDEV_PHUB_TDMEM40_BASE 0x40007940u\r
+#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM40_ORIG_TD0 0x40007940u\r
+#define CYREG_PHUB_TDMEM40_ORIG_TD1 0x40007944u\r
+#define CYDEV_PHUB_TDMEM41_BASE 0x40007948u\r
+#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM41_ORIG_TD0 0x40007948u\r
+#define CYREG_PHUB_TDMEM41_ORIG_TD1 0x4000794cu\r
+#define CYDEV_PHUB_TDMEM42_BASE 0x40007950u\r
+#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM42_ORIG_TD0 0x40007950u\r
+#define CYREG_PHUB_TDMEM42_ORIG_TD1 0x40007954u\r
+#define CYDEV_PHUB_TDMEM43_BASE 0x40007958u\r
+#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM43_ORIG_TD0 0x40007958u\r
+#define CYREG_PHUB_TDMEM43_ORIG_TD1 0x4000795cu\r
+#define CYDEV_PHUB_TDMEM44_BASE 0x40007960u\r
+#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM44_ORIG_TD0 0x40007960u\r
+#define CYREG_PHUB_TDMEM44_ORIG_TD1 0x40007964u\r
+#define CYDEV_PHUB_TDMEM45_BASE 0x40007968u\r
+#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM45_ORIG_TD0 0x40007968u\r
+#define CYREG_PHUB_TDMEM45_ORIG_TD1 0x4000796cu\r
+#define CYDEV_PHUB_TDMEM46_BASE 0x40007970u\r
+#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM46_ORIG_TD0 0x40007970u\r
+#define CYREG_PHUB_TDMEM46_ORIG_TD1 0x40007974u\r
+#define CYDEV_PHUB_TDMEM47_BASE 0x40007978u\r
+#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM47_ORIG_TD0 0x40007978u\r
+#define CYREG_PHUB_TDMEM47_ORIG_TD1 0x4000797cu\r
+#define CYDEV_PHUB_TDMEM48_BASE 0x40007980u\r
+#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM48_ORIG_TD0 0x40007980u\r
+#define CYREG_PHUB_TDMEM48_ORIG_TD1 0x40007984u\r
+#define CYDEV_PHUB_TDMEM49_BASE 0x40007988u\r
+#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM49_ORIG_TD0 0x40007988u\r
+#define CYREG_PHUB_TDMEM49_ORIG_TD1 0x4000798cu\r
+#define CYDEV_PHUB_TDMEM50_BASE 0x40007990u\r
+#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM50_ORIG_TD0 0x40007990u\r
+#define CYREG_PHUB_TDMEM50_ORIG_TD1 0x40007994u\r
+#define CYDEV_PHUB_TDMEM51_BASE 0x40007998u\r
+#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM51_ORIG_TD0 0x40007998u\r
+#define CYREG_PHUB_TDMEM51_ORIG_TD1 0x4000799cu\r
+#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0u\r
+#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM52_ORIG_TD0 0x400079a0u\r
+#define CYREG_PHUB_TDMEM52_ORIG_TD1 0x400079a4u\r
+#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8u\r
+#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM53_ORIG_TD0 0x400079a8u\r
+#define CYREG_PHUB_TDMEM53_ORIG_TD1 0x400079acu\r
+#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0u\r
+#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM54_ORIG_TD0 0x400079b0u\r
+#define CYREG_PHUB_TDMEM54_ORIG_TD1 0x400079b4u\r
+#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8u\r
+#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM55_ORIG_TD0 0x400079b8u\r
+#define CYREG_PHUB_TDMEM55_ORIG_TD1 0x400079bcu\r
+#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0u\r
+#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM56_ORIG_TD0 0x400079c0u\r
+#define CYREG_PHUB_TDMEM56_ORIG_TD1 0x400079c4u\r
+#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8u\r
+#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM57_ORIG_TD0 0x400079c8u\r
+#define CYREG_PHUB_TDMEM57_ORIG_TD1 0x400079ccu\r
+#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0u\r
+#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM58_ORIG_TD0 0x400079d0u\r
+#define CYREG_PHUB_TDMEM58_ORIG_TD1 0x400079d4u\r
+#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8u\r
+#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM59_ORIG_TD0 0x400079d8u\r
+#define CYREG_PHUB_TDMEM59_ORIG_TD1 0x400079dcu\r
+#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0u\r
+#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM60_ORIG_TD0 0x400079e0u\r
+#define CYREG_PHUB_TDMEM60_ORIG_TD1 0x400079e4u\r
+#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8u\r
+#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM61_ORIG_TD0 0x400079e8u\r
+#define CYREG_PHUB_TDMEM61_ORIG_TD1 0x400079ecu\r
+#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0u\r
+#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM62_ORIG_TD0 0x400079f0u\r
+#define CYREG_PHUB_TDMEM62_ORIG_TD1 0x400079f4u\r
+#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8u\r
+#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM63_ORIG_TD0 0x400079f8u\r
+#define CYREG_PHUB_TDMEM63_ORIG_TD1 0x400079fcu\r
+#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00u\r
+#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM64_ORIG_TD0 0x40007a00u\r
+#define CYREG_PHUB_TDMEM64_ORIG_TD1 0x40007a04u\r
+#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08u\r
+#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM65_ORIG_TD0 0x40007a08u\r
+#define CYREG_PHUB_TDMEM65_ORIG_TD1 0x40007a0cu\r
+#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10u\r
+#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM66_ORIG_TD0 0x40007a10u\r
+#define CYREG_PHUB_TDMEM66_ORIG_TD1 0x40007a14u\r
+#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18u\r
+#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM67_ORIG_TD0 0x40007a18u\r
+#define CYREG_PHUB_TDMEM67_ORIG_TD1 0x40007a1cu\r
+#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20u\r
+#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM68_ORIG_TD0 0x40007a20u\r
+#define CYREG_PHUB_TDMEM68_ORIG_TD1 0x40007a24u\r
+#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28u\r
+#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM69_ORIG_TD0 0x40007a28u\r
+#define CYREG_PHUB_TDMEM69_ORIG_TD1 0x40007a2cu\r
+#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30u\r
+#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM70_ORIG_TD0 0x40007a30u\r
+#define CYREG_PHUB_TDMEM70_ORIG_TD1 0x40007a34u\r
+#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38u\r
+#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM71_ORIG_TD0 0x40007a38u\r
+#define CYREG_PHUB_TDMEM71_ORIG_TD1 0x40007a3cu\r
+#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40u\r
+#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM72_ORIG_TD0 0x40007a40u\r
+#define CYREG_PHUB_TDMEM72_ORIG_TD1 0x40007a44u\r
+#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48u\r
+#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM73_ORIG_TD0 0x40007a48u\r
+#define CYREG_PHUB_TDMEM73_ORIG_TD1 0x40007a4cu\r
+#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50u\r
+#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM74_ORIG_TD0 0x40007a50u\r
+#define CYREG_PHUB_TDMEM74_ORIG_TD1 0x40007a54u\r
+#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58u\r
+#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM75_ORIG_TD0 0x40007a58u\r
+#define CYREG_PHUB_TDMEM75_ORIG_TD1 0x40007a5cu\r
+#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60u\r
+#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM76_ORIG_TD0 0x40007a60u\r
+#define CYREG_PHUB_TDMEM76_ORIG_TD1 0x40007a64u\r
+#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68u\r
+#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM77_ORIG_TD0 0x40007a68u\r
+#define CYREG_PHUB_TDMEM77_ORIG_TD1 0x40007a6cu\r
+#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70u\r
+#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM78_ORIG_TD0 0x40007a70u\r
+#define CYREG_PHUB_TDMEM78_ORIG_TD1 0x40007a74u\r
+#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78u\r
+#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM79_ORIG_TD0 0x40007a78u\r
+#define CYREG_PHUB_TDMEM79_ORIG_TD1 0x40007a7cu\r
+#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80u\r
+#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM80_ORIG_TD0 0x40007a80u\r
+#define CYREG_PHUB_TDMEM80_ORIG_TD1 0x40007a84u\r
+#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88u\r
+#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM81_ORIG_TD0 0x40007a88u\r
+#define CYREG_PHUB_TDMEM81_ORIG_TD1 0x40007a8cu\r
+#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90u\r
+#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM82_ORIG_TD0 0x40007a90u\r
+#define CYREG_PHUB_TDMEM82_ORIG_TD1 0x40007a94u\r
+#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98u\r
+#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM83_ORIG_TD0 0x40007a98u\r
+#define CYREG_PHUB_TDMEM83_ORIG_TD1 0x40007a9cu\r
+#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0u\r
+#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM84_ORIG_TD0 0x40007aa0u\r
+#define CYREG_PHUB_TDMEM84_ORIG_TD1 0x40007aa4u\r
+#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8u\r
+#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM85_ORIG_TD0 0x40007aa8u\r
+#define CYREG_PHUB_TDMEM85_ORIG_TD1 0x40007aacu\r
+#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0u\r
+#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM86_ORIG_TD0 0x40007ab0u\r
+#define CYREG_PHUB_TDMEM86_ORIG_TD1 0x40007ab4u\r
+#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8u\r
+#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM87_ORIG_TD0 0x40007ab8u\r
+#define CYREG_PHUB_TDMEM87_ORIG_TD1 0x40007abcu\r
+#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0u\r
+#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM88_ORIG_TD0 0x40007ac0u\r
+#define CYREG_PHUB_TDMEM88_ORIG_TD1 0x40007ac4u\r
+#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8u\r
+#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM89_ORIG_TD0 0x40007ac8u\r
+#define CYREG_PHUB_TDMEM89_ORIG_TD1 0x40007accu\r
+#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0u\r
+#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM90_ORIG_TD0 0x40007ad0u\r
+#define CYREG_PHUB_TDMEM90_ORIG_TD1 0x40007ad4u\r
+#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8u\r
+#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM91_ORIG_TD0 0x40007ad8u\r
+#define CYREG_PHUB_TDMEM91_ORIG_TD1 0x40007adcu\r
+#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0u\r
+#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM92_ORIG_TD0 0x40007ae0u\r
+#define CYREG_PHUB_TDMEM92_ORIG_TD1 0x40007ae4u\r
+#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8u\r
+#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM93_ORIG_TD0 0x40007ae8u\r
+#define CYREG_PHUB_TDMEM93_ORIG_TD1 0x40007aecu\r
+#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0u\r
+#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM94_ORIG_TD0 0x40007af0u\r
+#define CYREG_PHUB_TDMEM94_ORIG_TD1 0x40007af4u\r
+#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8u\r
+#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM95_ORIG_TD0 0x40007af8u\r
+#define CYREG_PHUB_TDMEM95_ORIG_TD1 0x40007afcu\r
+#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00u\r
+#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM96_ORIG_TD0 0x40007b00u\r
+#define CYREG_PHUB_TDMEM96_ORIG_TD1 0x40007b04u\r
+#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08u\r
+#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM97_ORIG_TD0 0x40007b08u\r
+#define CYREG_PHUB_TDMEM97_ORIG_TD1 0x40007b0cu\r
+#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10u\r
+#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM98_ORIG_TD0 0x40007b10u\r
+#define CYREG_PHUB_TDMEM98_ORIG_TD1 0x40007b14u\r
+#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18u\r
+#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM99_ORIG_TD0 0x40007b18u\r
+#define CYREG_PHUB_TDMEM99_ORIG_TD1 0x40007b1cu\r
+#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20u\r
+#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM100_ORIG_TD0 0x40007b20u\r
+#define CYREG_PHUB_TDMEM100_ORIG_TD1 0x40007b24u\r
+#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28u\r
+#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM101_ORIG_TD0 0x40007b28u\r
+#define CYREG_PHUB_TDMEM101_ORIG_TD1 0x40007b2cu\r
+#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30u\r
+#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM102_ORIG_TD0 0x40007b30u\r
+#define CYREG_PHUB_TDMEM102_ORIG_TD1 0x40007b34u\r
+#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38u\r
+#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM103_ORIG_TD0 0x40007b38u\r
+#define CYREG_PHUB_TDMEM103_ORIG_TD1 0x40007b3cu\r
+#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40u\r
+#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM104_ORIG_TD0 0x40007b40u\r
+#define CYREG_PHUB_TDMEM104_ORIG_TD1 0x40007b44u\r
+#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48u\r
+#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM105_ORIG_TD0 0x40007b48u\r
+#define CYREG_PHUB_TDMEM105_ORIG_TD1 0x40007b4cu\r
+#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50u\r
+#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM106_ORIG_TD0 0x40007b50u\r
+#define CYREG_PHUB_TDMEM106_ORIG_TD1 0x40007b54u\r
+#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58u\r
+#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM107_ORIG_TD0 0x40007b58u\r
+#define CYREG_PHUB_TDMEM107_ORIG_TD1 0x40007b5cu\r
+#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60u\r
+#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM108_ORIG_TD0 0x40007b60u\r
+#define CYREG_PHUB_TDMEM108_ORIG_TD1 0x40007b64u\r
+#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68u\r
+#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM109_ORIG_TD0 0x40007b68u\r
+#define CYREG_PHUB_TDMEM109_ORIG_TD1 0x40007b6cu\r
+#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70u\r
+#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM110_ORIG_TD0 0x40007b70u\r
+#define CYREG_PHUB_TDMEM110_ORIG_TD1 0x40007b74u\r
+#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78u\r
+#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM111_ORIG_TD0 0x40007b78u\r
+#define CYREG_PHUB_TDMEM111_ORIG_TD1 0x40007b7cu\r
+#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80u\r
+#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM112_ORIG_TD0 0x40007b80u\r
+#define CYREG_PHUB_TDMEM112_ORIG_TD1 0x40007b84u\r
+#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88u\r
+#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM113_ORIG_TD0 0x40007b88u\r
+#define CYREG_PHUB_TDMEM113_ORIG_TD1 0x40007b8cu\r
+#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90u\r
+#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM114_ORIG_TD0 0x40007b90u\r
+#define CYREG_PHUB_TDMEM114_ORIG_TD1 0x40007b94u\r
+#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98u\r
+#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM115_ORIG_TD0 0x40007b98u\r
+#define CYREG_PHUB_TDMEM115_ORIG_TD1 0x40007b9cu\r
+#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0u\r
+#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM116_ORIG_TD0 0x40007ba0u\r
+#define CYREG_PHUB_TDMEM116_ORIG_TD1 0x40007ba4u\r
+#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8u\r
+#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM117_ORIG_TD0 0x40007ba8u\r
+#define CYREG_PHUB_TDMEM117_ORIG_TD1 0x40007bacu\r
+#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0u\r
+#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM118_ORIG_TD0 0x40007bb0u\r
+#define CYREG_PHUB_TDMEM118_ORIG_TD1 0x40007bb4u\r
+#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8u\r
+#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM119_ORIG_TD0 0x40007bb8u\r
+#define CYREG_PHUB_TDMEM119_ORIG_TD1 0x40007bbcu\r
+#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0u\r
+#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM120_ORIG_TD0 0x40007bc0u\r
+#define CYREG_PHUB_TDMEM120_ORIG_TD1 0x40007bc4u\r
+#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8u\r
+#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM121_ORIG_TD0 0x40007bc8u\r
+#define CYREG_PHUB_TDMEM121_ORIG_TD1 0x40007bccu\r
+#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0u\r
+#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM122_ORIG_TD0 0x40007bd0u\r
+#define CYREG_PHUB_TDMEM122_ORIG_TD1 0x40007bd4u\r
+#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8u\r
+#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM123_ORIG_TD0 0x40007bd8u\r
+#define CYREG_PHUB_TDMEM123_ORIG_TD1 0x40007bdcu\r
+#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0u\r
+#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM124_ORIG_TD0 0x40007be0u\r
+#define CYREG_PHUB_TDMEM124_ORIG_TD1 0x40007be4u\r
+#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8u\r
+#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM125_ORIG_TD0 0x40007be8u\r
+#define CYREG_PHUB_TDMEM125_ORIG_TD1 0x40007becu\r
+#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0u\r
+#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM126_ORIG_TD0 0x40007bf0u\r
+#define CYREG_PHUB_TDMEM126_ORIG_TD1 0x40007bf4u\r
+#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8u\r
+#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008u\r
+#define CYREG_PHUB_TDMEM127_ORIG_TD0 0x40007bf8u\r
+#define CYREG_PHUB_TDMEM127_ORIG_TD1 0x40007bfcu\r
+#define CYDEV_EE_BASE 0x40008000u\r
+#define CYDEV_EE_SIZE 0x00000800u\r
+#define CYREG_EE_DATA_MBASE 0x40008000u\r
+#define CYREG_EE_DATA_MSIZE 0x00000800u\r
+#define CYDEV_CAN0_BASE 0x4000a000u\r
+#define CYDEV_CAN0_SIZE 0x000002a0u\r
+#define CYDEV_CAN0_CSR_BASE 0x4000a000u\r
+#define CYDEV_CAN0_CSR_SIZE 0x00000018u\r
+#define CYREG_CAN0_CSR_INT_SR 0x4000a000u\r
+#define CYREG_CAN0_CSR_INT_EN 0x4000a004u\r
+#define CYREG_CAN0_CSR_BUF_SR 0x4000a008u\r
+#define CYREG_CAN0_CSR_ERR_SR 0x4000a00cu\r
+#define CYREG_CAN0_CSR_CMD 0x4000a010u\r
+#define CYREG_CAN0_CSR_CFG 0x4000a014u\r
+#define CYDEV_CAN0_TX0_BASE 0x4000a020u\r
+#define CYDEV_CAN0_TX0_SIZE 0x00000010u\r
+#define CYREG_CAN0_TX0_CMD 0x4000a020u\r
+#define CYREG_CAN0_TX0_ID 0x4000a024u\r
+#define CYREG_CAN0_TX0_DH 0x4000a028u\r
+#define CYREG_CAN0_TX0_DL 0x4000a02cu\r
+#define CYDEV_CAN0_TX1_BASE 0x4000a030u\r
+#define CYDEV_CAN0_TX1_SIZE 0x00000010u\r
+#define CYREG_CAN0_TX1_CMD 0x4000a030u\r
+#define CYREG_CAN0_TX1_ID 0x4000a034u\r
+#define CYREG_CAN0_TX1_DH 0x4000a038u\r
+#define CYREG_CAN0_TX1_DL 0x4000a03cu\r
+#define CYDEV_CAN0_TX2_BASE 0x4000a040u\r
+#define CYDEV_CAN0_TX2_SIZE 0x00000010u\r
+#define CYREG_CAN0_TX2_CMD 0x4000a040u\r
+#define CYREG_CAN0_TX2_ID 0x4000a044u\r
+#define CYREG_CAN0_TX2_DH 0x4000a048u\r
+#define CYREG_CAN0_TX2_DL 0x4000a04cu\r
+#define CYDEV_CAN0_TX3_BASE 0x4000a050u\r
+#define CYDEV_CAN0_TX3_SIZE 0x00000010u\r
+#define CYREG_CAN0_TX3_CMD 0x4000a050u\r
+#define CYREG_CAN0_TX3_ID 0x4000a054u\r
+#define CYREG_CAN0_TX3_DH 0x4000a058u\r
+#define CYREG_CAN0_TX3_DL 0x4000a05cu\r
+#define CYDEV_CAN0_TX4_BASE 0x4000a060u\r
+#define CYDEV_CAN0_TX4_SIZE 0x00000010u\r
+#define CYREG_CAN0_TX4_CMD 0x4000a060u\r
+#define CYREG_CAN0_TX4_ID 0x4000a064u\r
+#define CYREG_CAN0_TX4_DH 0x4000a068u\r
+#define CYREG_CAN0_TX4_DL 0x4000a06cu\r
+#define CYDEV_CAN0_TX5_BASE 0x4000a070u\r
+#define CYDEV_CAN0_TX5_SIZE 0x00000010u\r
+#define CYREG_CAN0_TX5_CMD 0x4000a070u\r
+#define CYREG_CAN0_TX5_ID 0x4000a074u\r
+#define CYREG_CAN0_TX5_DH 0x4000a078u\r
+#define CYREG_CAN0_TX5_DL 0x4000a07cu\r
+#define CYDEV_CAN0_TX6_BASE 0x4000a080u\r
+#define CYDEV_CAN0_TX6_SIZE 0x00000010u\r
+#define CYREG_CAN0_TX6_CMD 0x4000a080u\r
+#define CYREG_CAN0_TX6_ID 0x4000a084u\r
+#define CYREG_CAN0_TX6_DH 0x4000a088u\r
+#define CYREG_CAN0_TX6_DL 0x4000a08cu\r
+#define CYDEV_CAN0_TX7_BASE 0x4000a090u\r
+#define CYDEV_CAN0_TX7_SIZE 0x00000010u\r
+#define CYREG_CAN0_TX7_CMD 0x4000a090u\r
+#define CYREG_CAN0_TX7_ID 0x4000a094u\r
+#define CYREG_CAN0_TX7_DH 0x4000a098u\r
+#define CYREG_CAN0_TX7_DL 0x4000a09cu\r
+#define CYDEV_CAN0_RX0_BASE 0x4000a0a0u\r
+#define CYDEV_CAN0_RX0_SIZE 0x00000020u\r
+#define CYREG_CAN0_RX0_CMD 0x4000a0a0u\r
+#define CYREG_CAN0_RX0_ID 0x4000a0a4u\r
+#define CYREG_CAN0_RX0_DH 0x4000a0a8u\r
+#define CYREG_CAN0_RX0_DL 0x4000a0acu\r
+#define CYREG_CAN0_RX0_AMR 0x4000a0b0u\r
+#define CYREG_CAN0_RX0_ACR 0x4000a0b4u\r
+#define CYREG_CAN0_RX0_AMRD 0x4000a0b8u\r
+#define CYREG_CAN0_RX0_ACRD 0x4000a0bcu\r
+#define CYDEV_CAN0_RX1_BASE 0x4000a0c0u\r
+#define CYDEV_CAN0_RX1_SIZE 0x00000020u\r
+#define CYREG_CAN0_RX1_CMD 0x4000a0c0u\r
+#define CYREG_CAN0_RX1_ID 0x4000a0c4u\r
+#define CYREG_CAN0_RX1_DH 0x4000a0c8u\r
+#define CYREG_CAN0_RX1_DL 0x4000a0ccu\r
+#define CYREG_CAN0_RX1_AMR 0x4000a0d0u\r
+#define CYREG_CAN0_RX1_ACR 0x4000a0d4u\r
+#define CYREG_CAN0_RX1_AMRD 0x4000a0d8u\r
+#define CYREG_CAN0_RX1_ACRD 0x4000a0dcu\r
+#define CYDEV_CAN0_RX2_BASE 0x4000a0e0u\r
+#define CYDEV_CAN0_RX2_SIZE 0x00000020u\r
+#define CYREG_CAN0_RX2_CMD 0x4000a0e0u\r
+#define CYREG_CAN0_RX2_ID 0x4000a0e4u\r
+#define CYREG_CAN0_RX2_DH 0x4000a0e8u\r
+#define CYREG_CAN0_RX2_DL 0x4000a0ecu\r
+#define CYREG_CAN0_RX2_AMR 0x4000a0f0u\r
+#define CYREG_CAN0_RX2_ACR 0x4000a0f4u\r
+#define CYREG_CAN0_RX2_AMRD 0x4000a0f8u\r
+#define CYREG_CAN0_RX2_ACRD 0x4000a0fcu\r
+#define CYDEV_CAN0_RX3_BASE 0x4000a100u\r
+#define CYDEV_CAN0_RX3_SIZE 0x00000020u\r
+#define CYREG_CAN0_RX3_CMD 0x4000a100u\r
+#define CYREG_CAN0_RX3_ID 0x4000a104u\r
+#define CYREG_CAN0_RX3_DH 0x4000a108u\r
+#define CYREG_CAN0_RX3_DL 0x4000a10cu\r
+#define CYREG_CAN0_RX3_AMR 0x4000a110u\r
+#define CYREG_CAN0_RX3_ACR 0x4000a114u\r
+#define CYREG_CAN0_RX3_AMRD 0x4000a118u\r
+#define CYREG_CAN0_RX3_ACRD 0x4000a11cu\r
+#define CYDEV_CAN0_RX4_BASE 0x4000a120u\r
+#define CYDEV_CAN0_RX4_SIZE 0x00000020u\r
+#define CYREG_CAN0_RX4_CMD 0x4000a120u\r
+#define CYREG_CAN0_RX4_ID 0x4000a124u\r
+#define CYREG_CAN0_RX4_DH 0x4000a128u\r
+#define CYREG_CAN0_RX4_DL 0x4000a12cu\r
+#define CYREG_CAN0_RX4_AMR 0x4000a130u\r
+#define CYREG_CAN0_RX4_ACR 0x4000a134u\r
+#define CYREG_CAN0_RX4_AMRD 0x4000a138u\r
+#define CYREG_CAN0_RX4_ACRD 0x4000a13cu\r
+#define CYDEV_CAN0_RX5_BASE 0x4000a140u\r
+#define CYDEV_CAN0_RX5_SIZE 0x00000020u\r
+#define CYREG_CAN0_RX5_CMD 0x4000a140u\r
+#define CYREG_CAN0_RX5_ID 0x4000a144u\r
+#define CYREG_CAN0_RX5_DH 0x4000a148u\r
+#define CYREG_CAN0_RX5_DL 0x4000a14cu\r
+#define CYREG_CAN0_RX5_AMR 0x4000a150u\r
+#define CYREG_CAN0_RX5_ACR 0x4000a154u\r
+#define CYREG_CAN0_RX5_AMRD 0x4000a158u\r
+#define CYREG_CAN0_RX5_ACRD 0x4000a15cu\r
+#define CYDEV_CAN0_RX6_BASE 0x4000a160u\r
+#define CYDEV_CAN0_RX6_SIZE 0x00000020u\r
+#define CYREG_CAN0_RX6_CMD 0x4000a160u\r
+#define CYREG_CAN0_RX6_ID 0x4000a164u\r
+#define CYREG_CAN0_RX6_DH 0x4000a168u\r
+#define CYREG_CAN0_RX6_DL 0x4000a16cu\r
+#define CYREG_CAN0_RX6_AMR 0x4000a170u\r
+#define CYREG_CAN0_RX6_ACR 0x4000a174u\r
+#define CYREG_CAN0_RX6_AMRD 0x4000a178u\r
+#define CYREG_CAN0_RX6_ACRD 0x4000a17cu\r
+#define CYDEV_CAN0_RX7_BASE 0x4000a180u\r
+#define CYDEV_CAN0_RX7_SIZE 0x00000020u\r
+#define CYREG_CAN0_RX7_CMD 0x4000a180u\r
+#define CYREG_CAN0_RX7_ID 0x4000a184u\r
+#define CYREG_CAN0_RX7_DH 0x4000a188u\r
+#define CYREG_CAN0_RX7_DL 0x4000a18cu\r
+#define CYREG_CAN0_RX7_AMR 0x4000a190u\r
+#define CYREG_CAN0_RX7_ACR 0x4000a194u\r
+#define CYREG_CAN0_RX7_AMRD 0x4000a198u\r
+#define CYREG_CAN0_RX7_ACRD 0x4000a19cu\r
+#define CYDEV_CAN0_RX8_BASE 0x4000a1a0u\r
+#define CYDEV_CAN0_RX8_SIZE 0x00000020u\r
+#define CYREG_CAN0_RX8_CMD 0x4000a1a0u\r
+#define CYREG_CAN0_RX8_ID 0x4000a1a4u\r
+#define CYREG_CAN0_RX8_DH 0x4000a1a8u\r
+#define CYREG_CAN0_RX8_DL 0x4000a1acu\r
+#define CYREG_CAN0_RX8_AMR 0x4000a1b0u\r
+#define CYREG_CAN0_RX8_ACR 0x4000a1b4u\r
+#define CYREG_CAN0_RX8_AMRD 0x4000a1b8u\r
+#define CYREG_CAN0_RX8_ACRD 0x4000a1bcu\r
+#define CYDEV_CAN0_RX9_BASE 0x4000a1c0u\r
+#define CYDEV_CAN0_RX9_SIZE 0x00000020u\r
+#define CYREG_CAN0_RX9_CMD 0x4000a1c0u\r
+#define CYREG_CAN0_RX9_ID 0x4000a1c4u\r
+#define CYREG_CAN0_RX9_DH 0x4000a1c8u\r
+#define CYREG_CAN0_RX9_DL 0x4000a1ccu\r
+#define CYREG_CAN0_RX9_AMR 0x4000a1d0u\r
+#define CYREG_CAN0_RX9_ACR 0x4000a1d4u\r
+#define CYREG_CAN0_RX9_AMRD 0x4000a1d8u\r
+#define CYREG_CAN0_RX9_ACRD 0x4000a1dcu\r
+#define CYDEV_CAN0_RX10_BASE 0x4000a1e0u\r
+#define CYDEV_CAN0_RX10_SIZE 0x00000020u\r
+#define CYREG_CAN0_RX10_CMD 0x4000a1e0u\r
+#define CYREG_CAN0_RX10_ID 0x4000a1e4u\r
+#define CYREG_CAN0_RX10_DH 0x4000a1e8u\r
+#define CYREG_CAN0_RX10_DL 0x4000a1ecu\r
+#define CYREG_CAN0_RX10_AMR 0x4000a1f0u\r
+#define CYREG_CAN0_RX10_ACR 0x4000a1f4u\r
+#define CYREG_CAN0_RX10_AMRD 0x4000a1f8u\r
+#define CYREG_CAN0_RX10_ACRD 0x4000a1fcu\r
+#define CYDEV_CAN0_RX11_BASE 0x4000a200u\r
+#define CYDEV_CAN0_RX11_SIZE 0x00000020u\r
+#define CYREG_CAN0_RX11_CMD 0x4000a200u\r
+#define CYREG_CAN0_RX11_ID 0x4000a204u\r
+#define CYREG_CAN0_RX11_DH 0x4000a208u\r
+#define CYREG_CAN0_RX11_DL 0x4000a20cu\r
+#define CYREG_CAN0_RX11_AMR 0x4000a210u\r
+#define CYREG_CAN0_RX11_ACR 0x4000a214u\r
+#define CYREG_CAN0_RX11_AMRD 0x4000a218u\r
+#define CYREG_CAN0_RX11_ACRD 0x4000a21cu\r
+#define CYDEV_CAN0_RX12_BASE 0x4000a220u\r
+#define CYDEV_CAN0_RX12_SIZE 0x00000020u\r
+#define CYREG_CAN0_RX12_CMD 0x4000a220u\r
+#define CYREG_CAN0_RX12_ID 0x4000a224u\r
+#define CYREG_CAN0_RX12_DH 0x4000a228u\r
+#define CYREG_CAN0_RX12_DL 0x4000a22cu\r
+#define CYREG_CAN0_RX12_AMR 0x4000a230u\r
+#define CYREG_CAN0_RX12_ACR 0x4000a234u\r
+#define CYREG_CAN0_RX12_AMRD 0x4000a238u\r
+#define CYREG_CAN0_RX12_ACRD 0x4000a23cu\r
+#define CYDEV_CAN0_RX13_BASE 0x4000a240u\r
+#define CYDEV_CAN0_RX13_SIZE 0x00000020u\r
+#define CYREG_CAN0_RX13_CMD 0x4000a240u\r
+#define CYREG_CAN0_RX13_ID 0x4000a244u\r
+#define CYREG_CAN0_RX13_DH 0x4000a248u\r
+#define CYREG_CAN0_RX13_DL 0x4000a24cu\r
+#define CYREG_CAN0_RX13_AMR 0x4000a250u\r
+#define CYREG_CAN0_RX13_ACR 0x4000a254u\r
+#define CYREG_CAN0_RX13_AMRD 0x4000a258u\r
+#define CYREG_CAN0_RX13_ACRD 0x4000a25cu\r
+#define CYDEV_CAN0_RX14_BASE 0x4000a260u\r
+#define CYDEV_CAN0_RX14_SIZE 0x00000020u\r
+#define CYREG_CAN0_RX14_CMD 0x4000a260u\r
+#define CYREG_CAN0_RX14_ID 0x4000a264u\r
+#define CYREG_CAN0_RX14_DH 0x4000a268u\r
+#define CYREG_CAN0_RX14_DL 0x4000a26cu\r
+#define CYREG_CAN0_RX14_AMR 0x4000a270u\r
+#define CYREG_CAN0_RX14_ACR 0x4000a274u\r
+#define CYREG_CAN0_RX14_AMRD 0x4000a278u\r
+#define CYREG_CAN0_RX14_ACRD 0x4000a27cu\r
+#define CYDEV_CAN0_RX15_BASE 0x4000a280u\r
+#define CYDEV_CAN0_RX15_SIZE 0x00000020u\r
+#define CYREG_CAN0_RX15_CMD 0x4000a280u\r
+#define CYREG_CAN0_RX15_ID 0x4000a284u\r
+#define CYREG_CAN0_RX15_DH 0x4000a288u\r
+#define CYREG_CAN0_RX15_DL 0x4000a28cu\r
+#define CYREG_CAN0_RX15_AMR 0x4000a290u\r
+#define CYREG_CAN0_RX15_ACR 0x4000a294u\r
+#define CYREG_CAN0_RX15_AMRD 0x4000a298u\r
+#define CYREG_CAN0_RX15_ACRD 0x4000a29cu\r
+#define CYDEV_DFB0_BASE 0x4000c000u\r
+#define CYDEV_DFB0_SIZE 0x000007b5u\r
+#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000u\r
+#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200u\r
+#define CYREG_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000u\r
+#define CYREG_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200u\r
+#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200u\r
+#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200u\r
+#define CYREG_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200u\r
+#define CYREG_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200u\r
+#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400u\r
+#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100u\r
+#define CYREG_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400u\r
+#define CYREG_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100u\r
+#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500u\r
+#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100u\r
+#define CYREG_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500u\r
+#define CYREG_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100u\r
+#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600u\r
+#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100u\r
+#define CYREG_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600u\r
+#define CYREG_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100u\r
+#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700u\r
+#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040u\r
+#define CYREG_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700u\r
+#define CYREG_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040u\r
+#define CYREG_DFB0_CR 0x4000c780u\r
+#define CYREG_DFB0_SR 0x4000c784u\r
+#define CYREG_DFB0_RAM_EN 0x4000c788u\r
+#define CYREG_DFB0_RAM_DIR 0x4000c78cu\r
+#define CYREG_DFB0_SEMA 0x4000c790u\r
+#define CYREG_DFB0_DSI_CTRL 0x4000c794u\r
+#define CYREG_DFB0_INT_CTRL 0x4000c798u\r
+#define CYREG_DFB0_DMA_CTRL 0x4000c79cu\r
+#define CYREG_DFB0_STAGEA 0x4000c7a0u\r
+#define CYREG_DFB0_STAGEAM 0x4000c7a1u\r
+#define CYREG_DFB0_STAGEAH 0x4000c7a2u\r
+#define CYREG_DFB0_STAGEB 0x4000c7a4u\r
+#define CYREG_DFB0_STAGEBM 0x4000c7a5u\r
+#define CYREG_DFB0_STAGEBH 0x4000c7a6u\r
+#define CYREG_DFB0_HOLDA 0x4000c7a8u\r
+#define CYREG_DFB0_HOLDAM 0x4000c7a9u\r
+#define CYREG_DFB0_HOLDAH 0x4000c7aau\r
+#define CYREG_DFB0_HOLDAS 0x4000c7abu\r
+#define CYREG_DFB0_HOLDB 0x4000c7acu\r
+#define CYREG_DFB0_HOLDBM 0x4000c7adu\r
+#define CYREG_DFB0_HOLDBH 0x4000c7aeu\r
+#define CYREG_DFB0_HOLDBS 0x4000c7afu\r
+#define CYREG_DFB0_COHER 0x4000c7b0u\r
+#define CYREG_DFB0_DALIGN 0x4000c7b4u\r
+#define CYDEV_UCFG_BASE 0x40010000u\r
+#define CYDEV_UCFG_SIZE 0x00005040u\r
+#define CYDEV_UCFG_B0_BASE 0x40010000u\r
+#define CYDEV_UCFG_B0_SIZE 0x00000fefu\r
+#define CYDEV_UCFG_B0_P0_BASE 0x40010000u\r
+#define CYDEV_UCFG_B0_P0_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000u\r
+#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070u\r
+#define CYREG_B0_P0_U0_PLD_IT0 0x40010000u\r
+#define CYREG_B0_P0_U0_PLD_IT1 0x40010004u\r
+#define CYREG_B0_P0_U0_PLD_IT2 0x40010008u\r
+#define CYREG_B0_P0_U0_PLD_IT3 0x4001000cu\r
+#define CYREG_B0_P0_U0_PLD_IT4 0x40010010u\r
+#define CYREG_B0_P0_U0_PLD_IT5 0x40010014u\r
+#define CYREG_B0_P0_U0_PLD_IT6 0x40010018u\r
+#define CYREG_B0_P0_U0_PLD_IT7 0x4001001cu\r
+#define CYREG_B0_P0_U0_PLD_IT8 0x40010020u\r
+#define CYREG_B0_P0_U0_PLD_IT9 0x40010024u\r
+#define CYREG_B0_P0_U0_PLD_IT10 0x40010028u\r
+#define CYREG_B0_P0_U0_PLD_IT11 0x4001002cu\r
+#define CYREG_B0_P0_U0_PLD_ORT0 0x40010030u\r
+#define CYREG_B0_P0_U0_PLD_ORT1 0x40010032u\r
+#define CYREG_B0_P0_U0_PLD_ORT2 0x40010034u\r
+#define CYREG_B0_P0_U0_PLD_ORT3 0x40010036u\r
+#define CYREG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038u\r
+#define CYREG_B0_P0_U0_MC_CFG_XORFB 0x4001003au\r
+#define CYREG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003cu\r
+#define CYREG_B0_P0_U0_MC_CFG_BYPASS 0x4001003eu\r
+#define CYREG_B0_P0_U0_CFG0 0x40010040u\r
+#define CYREG_B0_P0_U0_CFG1 0x40010041u\r
+#define CYREG_B0_P0_U0_CFG2 0x40010042u\r
+#define CYREG_B0_P0_U0_CFG3 0x40010043u\r
+#define CYREG_B0_P0_U0_CFG4 0x40010044u\r
+#define CYREG_B0_P0_U0_CFG5 0x40010045u\r
+#define CYREG_B0_P0_U0_CFG6 0x40010046u\r
+#define CYREG_B0_P0_U0_CFG7 0x40010047u\r
+#define CYREG_B0_P0_U0_CFG8 0x40010048u\r
+#define CYREG_B0_P0_U0_CFG9 0x40010049u\r
+#define CYREG_B0_P0_U0_CFG10 0x4001004au\r
+#define CYREG_B0_P0_U0_CFG11 0x4001004bu\r
+#define CYREG_B0_P0_U0_CFG12 0x4001004cu\r
+#define CYREG_B0_P0_U0_CFG13 0x4001004du\r
+#define CYREG_B0_P0_U0_CFG14 0x4001004eu\r
+#define CYREG_B0_P0_U0_CFG15 0x4001004fu\r
+#define CYREG_B0_P0_U0_CFG16 0x40010050u\r
+#define CYREG_B0_P0_U0_CFG17 0x40010051u\r
+#define CYREG_B0_P0_U0_CFG18 0x40010052u\r
+#define CYREG_B0_P0_U0_CFG19 0x40010053u\r
+#define CYREG_B0_P0_U0_CFG20 0x40010054u\r
+#define CYREG_B0_P0_U0_CFG21 0x40010055u\r
+#define CYREG_B0_P0_U0_CFG22 0x40010056u\r
+#define CYREG_B0_P0_U0_CFG23 0x40010057u\r
+#define CYREG_B0_P0_U0_CFG24 0x40010058u\r
+#define CYREG_B0_P0_U0_CFG25 0x40010059u\r
+#define CYREG_B0_P0_U0_CFG26 0x4001005au\r
+#define CYREG_B0_P0_U0_CFG27 0x4001005bu\r
+#define CYREG_B0_P0_U0_CFG28 0x4001005cu\r
+#define CYREG_B0_P0_U0_CFG29 0x4001005du\r
+#define CYREG_B0_P0_U0_CFG30 0x4001005eu\r
+#define CYREG_B0_P0_U0_CFG31 0x4001005fu\r
+#define CYREG_B0_P0_U0_DCFG0 0x40010060u\r
+#define CYREG_B0_P0_U0_DCFG1 0x40010062u\r
+#define CYREG_B0_P0_U0_DCFG2 0x40010064u\r
+#define CYREG_B0_P0_U0_DCFG3 0x40010066u\r
+#define CYREG_B0_P0_U0_DCFG4 0x40010068u\r
+#define CYREG_B0_P0_U0_DCFG5 0x4001006au\r
+#define CYREG_B0_P0_U0_DCFG6 0x4001006cu\r
+#define CYREG_B0_P0_U0_DCFG7 0x4001006eu\r
+#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080u\r
+#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070u\r
+#define CYREG_B0_P0_U1_PLD_IT0 0x40010080u\r
+#define CYREG_B0_P0_U1_PLD_IT1 0x40010084u\r
+#define CYREG_B0_P0_U1_PLD_IT2 0x40010088u\r
+#define CYREG_B0_P0_U1_PLD_IT3 0x4001008cu\r
+#define CYREG_B0_P0_U1_PLD_IT4 0x40010090u\r
+#define CYREG_B0_P0_U1_PLD_IT5 0x40010094u\r
+#define CYREG_B0_P0_U1_PLD_IT6 0x40010098u\r
+#define CYREG_B0_P0_U1_PLD_IT7 0x4001009cu\r
+#define CYREG_B0_P0_U1_PLD_IT8 0x400100a0u\r
+#define CYREG_B0_P0_U1_PLD_IT9 0x400100a4u\r
+#define CYREG_B0_P0_U1_PLD_IT10 0x400100a8u\r
+#define CYREG_B0_P0_U1_PLD_IT11 0x400100acu\r
+#define CYREG_B0_P0_U1_PLD_ORT0 0x400100b0u\r
+#define CYREG_B0_P0_U1_PLD_ORT1 0x400100b2u\r
+#define CYREG_B0_P0_U1_PLD_ORT2 0x400100b4u\r
+#define CYREG_B0_P0_U1_PLD_ORT3 0x400100b6u\r
+#define CYREG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8u\r
+#define CYREG_B0_P0_U1_MC_CFG_XORFB 0x400100bau\r
+#define CYREG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bcu\r
+#define CYREG_B0_P0_U1_MC_CFG_BYPASS 0x400100beu\r
+#define CYREG_B0_P0_U1_CFG0 0x400100c0u\r
+#define CYREG_B0_P0_U1_CFG1 0x400100c1u\r
+#define CYREG_B0_P0_U1_CFG2 0x400100c2u\r
+#define CYREG_B0_P0_U1_CFG3 0x400100c3u\r
+#define CYREG_B0_P0_U1_CFG4 0x400100c4u\r
+#define CYREG_B0_P0_U1_CFG5 0x400100c5u\r
+#define CYREG_B0_P0_U1_CFG6 0x400100c6u\r
+#define CYREG_B0_P0_U1_CFG7 0x400100c7u\r
+#define CYREG_B0_P0_U1_CFG8 0x400100c8u\r
+#define CYREG_B0_P0_U1_CFG9 0x400100c9u\r
+#define CYREG_B0_P0_U1_CFG10 0x400100cau\r
+#define CYREG_B0_P0_U1_CFG11 0x400100cbu\r
+#define CYREG_B0_P0_U1_CFG12 0x400100ccu\r
+#define CYREG_B0_P0_U1_CFG13 0x400100cdu\r
+#define CYREG_B0_P0_U1_CFG14 0x400100ceu\r
+#define CYREG_B0_P0_U1_CFG15 0x400100cfu\r
+#define CYREG_B0_P0_U1_CFG16 0x400100d0u\r
+#define CYREG_B0_P0_U1_CFG17 0x400100d1u\r
+#define CYREG_B0_P0_U1_CFG18 0x400100d2u\r
+#define CYREG_B0_P0_U1_CFG19 0x400100d3u\r
+#define CYREG_B0_P0_U1_CFG20 0x400100d4u\r
+#define CYREG_B0_P0_U1_CFG21 0x400100d5u\r
+#define CYREG_B0_P0_U1_CFG22 0x400100d6u\r
+#define CYREG_B0_P0_U1_CFG23 0x400100d7u\r
+#define CYREG_B0_P0_U1_CFG24 0x400100d8u\r
+#define CYREG_B0_P0_U1_CFG25 0x400100d9u\r
+#define CYREG_B0_P0_U1_CFG26 0x400100dau\r
+#define CYREG_B0_P0_U1_CFG27 0x400100dbu\r
+#define CYREG_B0_P0_U1_CFG28 0x400100dcu\r
+#define CYREG_B0_P0_U1_CFG29 0x400100ddu\r
+#define CYREG_B0_P0_U1_CFG30 0x400100deu\r
+#define CYREG_B0_P0_U1_CFG31 0x400100dfu\r
+#define CYREG_B0_P0_U1_DCFG0 0x400100e0u\r
+#define CYREG_B0_P0_U1_DCFG1 0x400100e2u\r
+#define CYREG_B0_P0_U1_DCFG2 0x400100e4u\r
+#define CYREG_B0_P0_U1_DCFG3 0x400100e6u\r
+#define CYREG_B0_P0_U1_DCFG4 0x400100e8u\r
+#define CYREG_B0_P0_U1_DCFG5 0x400100eau\r
+#define CYREG_B0_P0_U1_DCFG6 0x400100ecu\r
+#define CYREG_B0_P0_U1_DCFG7 0x400100eeu\r
+#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100u\r
+#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B0_P1_BASE 0x40010200u\r
+#define CYDEV_UCFG_B0_P1_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200u\r
+#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070u\r
+#define CYREG_B0_P1_U0_PLD_IT0 0x40010200u\r
+#define CYREG_B0_P1_U0_PLD_IT1 0x40010204u\r
+#define CYREG_B0_P1_U0_PLD_IT2 0x40010208u\r
+#define CYREG_B0_P1_U0_PLD_IT3 0x4001020cu\r
+#define CYREG_B0_P1_U0_PLD_IT4 0x40010210u\r
+#define CYREG_B0_P1_U0_PLD_IT5 0x40010214u\r
+#define CYREG_B0_P1_U0_PLD_IT6 0x40010218u\r
+#define CYREG_B0_P1_U0_PLD_IT7 0x4001021cu\r
+#define CYREG_B0_P1_U0_PLD_IT8 0x40010220u\r
+#define CYREG_B0_P1_U0_PLD_IT9 0x40010224u\r
+#define CYREG_B0_P1_U0_PLD_IT10 0x40010228u\r
+#define CYREG_B0_P1_U0_PLD_IT11 0x4001022cu\r
+#define CYREG_B0_P1_U0_PLD_ORT0 0x40010230u\r
+#define CYREG_B0_P1_U0_PLD_ORT1 0x40010232u\r
+#define CYREG_B0_P1_U0_PLD_ORT2 0x40010234u\r
+#define CYREG_B0_P1_U0_PLD_ORT3 0x40010236u\r
+#define CYREG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238u\r
+#define CYREG_B0_P1_U0_MC_CFG_XORFB 0x4001023au\r
+#define CYREG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023cu\r
+#define CYREG_B0_P1_U0_MC_CFG_BYPASS 0x4001023eu\r
+#define CYREG_B0_P1_U0_CFG0 0x40010240u\r
+#define CYREG_B0_P1_U0_CFG1 0x40010241u\r
+#define CYREG_B0_P1_U0_CFG2 0x40010242u\r
+#define CYREG_B0_P1_U0_CFG3 0x40010243u\r
+#define CYREG_B0_P1_U0_CFG4 0x40010244u\r
+#define CYREG_B0_P1_U0_CFG5 0x40010245u\r
+#define CYREG_B0_P1_U0_CFG6 0x40010246u\r
+#define CYREG_B0_P1_U0_CFG7 0x40010247u\r
+#define CYREG_B0_P1_U0_CFG8 0x40010248u\r
+#define CYREG_B0_P1_U0_CFG9 0x40010249u\r
+#define CYREG_B0_P1_U0_CFG10 0x4001024au\r
+#define CYREG_B0_P1_U0_CFG11 0x4001024bu\r
+#define CYREG_B0_P1_U0_CFG12 0x4001024cu\r
+#define CYREG_B0_P1_U0_CFG13 0x4001024du\r
+#define CYREG_B0_P1_U0_CFG14 0x4001024eu\r
+#define CYREG_B0_P1_U0_CFG15 0x4001024fu\r
+#define CYREG_B0_P1_U0_CFG16 0x40010250u\r
+#define CYREG_B0_P1_U0_CFG17 0x40010251u\r
+#define CYREG_B0_P1_U0_CFG18 0x40010252u\r
+#define CYREG_B0_P1_U0_CFG19 0x40010253u\r
+#define CYREG_B0_P1_U0_CFG20 0x40010254u\r
+#define CYREG_B0_P1_U0_CFG21 0x40010255u\r
+#define CYREG_B0_P1_U0_CFG22 0x40010256u\r
+#define CYREG_B0_P1_U0_CFG23 0x40010257u\r
+#define CYREG_B0_P1_U0_CFG24 0x40010258u\r
+#define CYREG_B0_P1_U0_CFG25 0x40010259u\r
+#define CYREG_B0_P1_U0_CFG26 0x4001025au\r
+#define CYREG_B0_P1_U0_CFG27 0x4001025bu\r
+#define CYREG_B0_P1_U0_CFG28 0x4001025cu\r
+#define CYREG_B0_P1_U0_CFG29 0x4001025du\r
+#define CYREG_B0_P1_U0_CFG30 0x4001025eu\r
+#define CYREG_B0_P1_U0_CFG31 0x4001025fu\r
+#define CYREG_B0_P1_U0_DCFG0 0x40010260u\r
+#define CYREG_B0_P1_U0_DCFG1 0x40010262u\r
+#define CYREG_B0_P1_U0_DCFG2 0x40010264u\r
+#define CYREG_B0_P1_U0_DCFG3 0x40010266u\r
+#define CYREG_B0_P1_U0_DCFG4 0x40010268u\r
+#define CYREG_B0_P1_U0_DCFG5 0x4001026au\r
+#define CYREG_B0_P1_U0_DCFG6 0x4001026cu\r
+#define CYREG_B0_P1_U0_DCFG7 0x4001026eu\r
+#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280u\r
+#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070u\r
+#define CYREG_B0_P1_U1_PLD_IT0 0x40010280u\r
+#define CYREG_B0_P1_U1_PLD_IT1 0x40010284u\r
+#define CYREG_B0_P1_U1_PLD_IT2 0x40010288u\r
+#define CYREG_B0_P1_U1_PLD_IT3 0x4001028cu\r
+#define CYREG_B0_P1_U1_PLD_IT4 0x40010290u\r
+#define CYREG_B0_P1_U1_PLD_IT5 0x40010294u\r
+#define CYREG_B0_P1_U1_PLD_IT6 0x40010298u\r
+#define CYREG_B0_P1_U1_PLD_IT7 0x4001029cu\r
+#define CYREG_B0_P1_U1_PLD_IT8 0x400102a0u\r
+#define CYREG_B0_P1_U1_PLD_IT9 0x400102a4u\r
+#define CYREG_B0_P1_U1_PLD_IT10 0x400102a8u\r
+#define CYREG_B0_P1_U1_PLD_IT11 0x400102acu\r
+#define CYREG_B0_P1_U1_PLD_ORT0 0x400102b0u\r
+#define CYREG_B0_P1_U1_PLD_ORT1 0x400102b2u\r
+#define CYREG_B0_P1_U1_PLD_ORT2 0x400102b4u\r
+#define CYREG_B0_P1_U1_PLD_ORT3 0x400102b6u\r
+#define CYREG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8u\r
+#define CYREG_B0_P1_U1_MC_CFG_XORFB 0x400102bau\r
+#define CYREG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bcu\r
+#define CYREG_B0_P1_U1_MC_CFG_BYPASS 0x400102beu\r
+#define CYREG_B0_P1_U1_CFG0 0x400102c0u\r
+#define CYREG_B0_P1_U1_CFG1 0x400102c1u\r
+#define CYREG_B0_P1_U1_CFG2 0x400102c2u\r
+#define CYREG_B0_P1_U1_CFG3 0x400102c3u\r
+#define CYREG_B0_P1_U1_CFG4 0x400102c4u\r
+#define CYREG_B0_P1_U1_CFG5 0x400102c5u\r
+#define CYREG_B0_P1_U1_CFG6 0x400102c6u\r
+#define CYREG_B0_P1_U1_CFG7 0x400102c7u\r
+#define CYREG_B0_P1_U1_CFG8 0x400102c8u\r
+#define CYREG_B0_P1_U1_CFG9 0x400102c9u\r
+#define CYREG_B0_P1_U1_CFG10 0x400102cau\r
+#define CYREG_B0_P1_U1_CFG11 0x400102cbu\r
+#define CYREG_B0_P1_U1_CFG12 0x400102ccu\r
+#define CYREG_B0_P1_U1_CFG13 0x400102cdu\r
+#define CYREG_B0_P1_U1_CFG14 0x400102ceu\r
+#define CYREG_B0_P1_U1_CFG15 0x400102cfu\r
+#define CYREG_B0_P1_U1_CFG16 0x400102d0u\r
+#define CYREG_B0_P1_U1_CFG17 0x400102d1u\r
+#define CYREG_B0_P1_U1_CFG18 0x400102d2u\r
+#define CYREG_B0_P1_U1_CFG19 0x400102d3u\r
+#define CYREG_B0_P1_U1_CFG20 0x400102d4u\r
+#define CYREG_B0_P1_U1_CFG21 0x400102d5u\r
+#define CYREG_B0_P1_U1_CFG22 0x400102d6u\r
+#define CYREG_B0_P1_U1_CFG23 0x400102d7u\r
+#define CYREG_B0_P1_U1_CFG24 0x400102d8u\r
+#define CYREG_B0_P1_U1_CFG25 0x400102d9u\r
+#define CYREG_B0_P1_U1_CFG26 0x400102dau\r
+#define CYREG_B0_P1_U1_CFG27 0x400102dbu\r
+#define CYREG_B0_P1_U1_CFG28 0x400102dcu\r
+#define CYREG_B0_P1_U1_CFG29 0x400102ddu\r
+#define CYREG_B0_P1_U1_CFG30 0x400102deu\r
+#define CYREG_B0_P1_U1_CFG31 0x400102dfu\r
+#define CYREG_B0_P1_U1_DCFG0 0x400102e0u\r
+#define CYREG_B0_P1_U1_DCFG1 0x400102e2u\r
+#define CYREG_B0_P1_U1_DCFG2 0x400102e4u\r
+#define CYREG_B0_P1_U1_DCFG3 0x400102e6u\r
+#define CYREG_B0_P1_U1_DCFG4 0x400102e8u\r
+#define CYREG_B0_P1_U1_DCFG5 0x400102eau\r
+#define CYREG_B0_P1_U1_DCFG6 0x400102ecu\r
+#define CYREG_B0_P1_U1_DCFG7 0x400102eeu\r
+#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300u\r
+#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B0_P2_BASE 0x40010400u\r
+#define CYDEV_UCFG_B0_P2_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400u\r
+#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070u\r
+#define CYREG_B0_P2_U0_PLD_IT0 0x40010400u\r
+#define CYREG_B0_P2_U0_PLD_IT1 0x40010404u\r
+#define CYREG_B0_P2_U0_PLD_IT2 0x40010408u\r
+#define CYREG_B0_P2_U0_PLD_IT3 0x4001040cu\r
+#define CYREG_B0_P2_U0_PLD_IT4 0x40010410u\r
+#define CYREG_B0_P2_U0_PLD_IT5 0x40010414u\r
+#define CYREG_B0_P2_U0_PLD_IT6 0x40010418u\r
+#define CYREG_B0_P2_U0_PLD_IT7 0x4001041cu\r
+#define CYREG_B0_P2_U0_PLD_IT8 0x40010420u\r
+#define CYREG_B0_P2_U0_PLD_IT9 0x40010424u\r
+#define CYREG_B0_P2_U0_PLD_IT10 0x40010428u\r
+#define CYREG_B0_P2_U0_PLD_IT11 0x4001042cu\r
+#define CYREG_B0_P2_U0_PLD_ORT0 0x40010430u\r
+#define CYREG_B0_P2_U0_PLD_ORT1 0x40010432u\r
+#define CYREG_B0_P2_U0_PLD_ORT2 0x40010434u\r
+#define CYREG_B0_P2_U0_PLD_ORT3 0x40010436u\r
+#define CYREG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438u\r
+#define CYREG_B0_P2_U0_MC_CFG_XORFB 0x4001043au\r
+#define CYREG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043cu\r
+#define CYREG_B0_P2_U0_MC_CFG_BYPASS 0x4001043eu\r
+#define CYREG_B0_P2_U0_CFG0 0x40010440u\r
+#define CYREG_B0_P2_U0_CFG1 0x40010441u\r
+#define CYREG_B0_P2_U0_CFG2 0x40010442u\r
+#define CYREG_B0_P2_U0_CFG3 0x40010443u\r
+#define CYREG_B0_P2_U0_CFG4 0x40010444u\r
+#define CYREG_B0_P2_U0_CFG5 0x40010445u\r
+#define CYREG_B0_P2_U0_CFG6 0x40010446u\r
+#define CYREG_B0_P2_U0_CFG7 0x40010447u\r
+#define CYREG_B0_P2_U0_CFG8 0x40010448u\r
+#define CYREG_B0_P2_U0_CFG9 0x40010449u\r
+#define CYREG_B0_P2_U0_CFG10 0x4001044au\r
+#define CYREG_B0_P2_U0_CFG11 0x4001044bu\r
+#define CYREG_B0_P2_U0_CFG12 0x4001044cu\r
+#define CYREG_B0_P2_U0_CFG13 0x4001044du\r
+#define CYREG_B0_P2_U0_CFG14 0x4001044eu\r
+#define CYREG_B0_P2_U0_CFG15 0x4001044fu\r
+#define CYREG_B0_P2_U0_CFG16 0x40010450u\r
+#define CYREG_B0_P2_U0_CFG17 0x40010451u\r
+#define CYREG_B0_P2_U0_CFG18 0x40010452u\r
+#define CYREG_B0_P2_U0_CFG19 0x40010453u\r
+#define CYREG_B0_P2_U0_CFG20 0x40010454u\r
+#define CYREG_B0_P2_U0_CFG21 0x40010455u\r
+#define CYREG_B0_P2_U0_CFG22 0x40010456u\r
+#define CYREG_B0_P2_U0_CFG23 0x40010457u\r
+#define CYREG_B0_P2_U0_CFG24 0x40010458u\r
+#define CYREG_B0_P2_U0_CFG25 0x40010459u\r
+#define CYREG_B0_P2_U0_CFG26 0x4001045au\r
+#define CYREG_B0_P2_U0_CFG27 0x4001045bu\r
+#define CYREG_B0_P2_U0_CFG28 0x4001045cu\r
+#define CYREG_B0_P2_U0_CFG29 0x4001045du\r
+#define CYREG_B0_P2_U0_CFG30 0x4001045eu\r
+#define CYREG_B0_P2_U0_CFG31 0x4001045fu\r
+#define CYREG_B0_P2_U0_DCFG0 0x40010460u\r
+#define CYREG_B0_P2_U0_DCFG1 0x40010462u\r
+#define CYREG_B0_P2_U0_DCFG2 0x40010464u\r
+#define CYREG_B0_P2_U0_DCFG3 0x40010466u\r
+#define CYREG_B0_P2_U0_DCFG4 0x40010468u\r
+#define CYREG_B0_P2_U0_DCFG5 0x4001046au\r
+#define CYREG_B0_P2_U0_DCFG6 0x4001046cu\r
+#define CYREG_B0_P2_U0_DCFG7 0x4001046eu\r
+#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480u\r
+#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070u\r
+#define CYREG_B0_P2_U1_PLD_IT0 0x40010480u\r
+#define CYREG_B0_P2_U1_PLD_IT1 0x40010484u\r
+#define CYREG_B0_P2_U1_PLD_IT2 0x40010488u\r
+#define CYREG_B0_P2_U1_PLD_IT3 0x4001048cu\r
+#define CYREG_B0_P2_U1_PLD_IT4 0x40010490u\r
+#define CYREG_B0_P2_U1_PLD_IT5 0x40010494u\r
+#define CYREG_B0_P2_U1_PLD_IT6 0x40010498u\r
+#define CYREG_B0_P2_U1_PLD_IT7 0x4001049cu\r
+#define CYREG_B0_P2_U1_PLD_IT8 0x400104a0u\r
+#define CYREG_B0_P2_U1_PLD_IT9 0x400104a4u\r
+#define CYREG_B0_P2_U1_PLD_IT10 0x400104a8u\r
+#define CYREG_B0_P2_U1_PLD_IT11 0x400104acu\r
+#define CYREG_B0_P2_U1_PLD_ORT0 0x400104b0u\r
+#define CYREG_B0_P2_U1_PLD_ORT1 0x400104b2u\r
+#define CYREG_B0_P2_U1_PLD_ORT2 0x400104b4u\r
+#define CYREG_B0_P2_U1_PLD_ORT3 0x400104b6u\r
+#define CYREG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8u\r
+#define CYREG_B0_P2_U1_MC_CFG_XORFB 0x400104bau\r
+#define CYREG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bcu\r
+#define CYREG_B0_P2_U1_MC_CFG_BYPASS 0x400104beu\r
+#define CYREG_B0_P2_U1_CFG0 0x400104c0u\r
+#define CYREG_B0_P2_U1_CFG1 0x400104c1u\r
+#define CYREG_B0_P2_U1_CFG2 0x400104c2u\r
+#define CYREG_B0_P2_U1_CFG3 0x400104c3u\r
+#define CYREG_B0_P2_U1_CFG4 0x400104c4u\r
+#define CYREG_B0_P2_U1_CFG5 0x400104c5u\r
+#define CYREG_B0_P2_U1_CFG6 0x400104c6u\r
+#define CYREG_B0_P2_U1_CFG7 0x400104c7u\r
+#define CYREG_B0_P2_U1_CFG8 0x400104c8u\r
+#define CYREG_B0_P2_U1_CFG9 0x400104c9u\r
+#define CYREG_B0_P2_U1_CFG10 0x400104cau\r
+#define CYREG_B0_P2_U1_CFG11 0x400104cbu\r
+#define CYREG_B0_P2_U1_CFG12 0x400104ccu\r
+#define CYREG_B0_P2_U1_CFG13 0x400104cdu\r
+#define CYREG_B0_P2_U1_CFG14 0x400104ceu\r
+#define CYREG_B0_P2_U1_CFG15 0x400104cfu\r
+#define CYREG_B0_P2_U1_CFG16 0x400104d0u\r
+#define CYREG_B0_P2_U1_CFG17 0x400104d1u\r
+#define CYREG_B0_P2_U1_CFG18 0x400104d2u\r
+#define CYREG_B0_P2_U1_CFG19 0x400104d3u\r
+#define CYREG_B0_P2_U1_CFG20 0x400104d4u\r
+#define CYREG_B0_P2_U1_CFG21 0x400104d5u\r
+#define CYREG_B0_P2_U1_CFG22 0x400104d6u\r
+#define CYREG_B0_P2_U1_CFG23 0x400104d7u\r
+#define CYREG_B0_P2_U1_CFG24 0x400104d8u\r
+#define CYREG_B0_P2_U1_CFG25 0x400104d9u\r
+#define CYREG_B0_P2_U1_CFG26 0x400104dau\r
+#define CYREG_B0_P2_U1_CFG27 0x400104dbu\r
+#define CYREG_B0_P2_U1_CFG28 0x400104dcu\r
+#define CYREG_B0_P2_U1_CFG29 0x400104ddu\r
+#define CYREG_B0_P2_U1_CFG30 0x400104deu\r
+#define CYREG_B0_P2_U1_CFG31 0x400104dfu\r
+#define CYREG_B0_P2_U1_DCFG0 0x400104e0u\r
+#define CYREG_B0_P2_U1_DCFG1 0x400104e2u\r
+#define CYREG_B0_P2_U1_DCFG2 0x400104e4u\r
+#define CYREG_B0_P2_U1_DCFG3 0x400104e6u\r
+#define CYREG_B0_P2_U1_DCFG4 0x400104e8u\r
+#define CYREG_B0_P2_U1_DCFG5 0x400104eau\r
+#define CYREG_B0_P2_U1_DCFG6 0x400104ecu\r
+#define CYREG_B0_P2_U1_DCFG7 0x400104eeu\r
+#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500u\r
+#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B0_P3_BASE 0x40010600u\r
+#define CYDEV_UCFG_B0_P3_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600u\r
+#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070u\r
+#define CYREG_B0_P3_U0_PLD_IT0 0x40010600u\r
+#define CYREG_B0_P3_U0_PLD_IT1 0x40010604u\r
+#define CYREG_B0_P3_U0_PLD_IT2 0x40010608u\r
+#define CYREG_B0_P3_U0_PLD_IT3 0x4001060cu\r
+#define CYREG_B0_P3_U0_PLD_IT4 0x40010610u\r
+#define CYREG_B0_P3_U0_PLD_IT5 0x40010614u\r
+#define CYREG_B0_P3_U0_PLD_IT6 0x40010618u\r
+#define CYREG_B0_P3_U0_PLD_IT7 0x4001061cu\r
+#define CYREG_B0_P3_U0_PLD_IT8 0x40010620u\r
+#define CYREG_B0_P3_U0_PLD_IT9 0x40010624u\r
+#define CYREG_B0_P3_U0_PLD_IT10 0x40010628u\r
+#define CYREG_B0_P3_U0_PLD_IT11 0x4001062cu\r
+#define CYREG_B0_P3_U0_PLD_ORT0 0x40010630u\r
+#define CYREG_B0_P3_U0_PLD_ORT1 0x40010632u\r
+#define CYREG_B0_P3_U0_PLD_ORT2 0x40010634u\r
+#define CYREG_B0_P3_U0_PLD_ORT3 0x40010636u\r
+#define CYREG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638u\r
+#define CYREG_B0_P3_U0_MC_CFG_XORFB 0x4001063au\r
+#define CYREG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063cu\r
+#define CYREG_B0_P3_U0_MC_CFG_BYPASS 0x4001063eu\r
+#define CYREG_B0_P3_U0_CFG0 0x40010640u\r
+#define CYREG_B0_P3_U0_CFG1 0x40010641u\r
+#define CYREG_B0_P3_U0_CFG2 0x40010642u\r
+#define CYREG_B0_P3_U0_CFG3 0x40010643u\r
+#define CYREG_B0_P3_U0_CFG4 0x40010644u\r
+#define CYREG_B0_P3_U0_CFG5 0x40010645u\r
+#define CYREG_B0_P3_U0_CFG6 0x40010646u\r
+#define CYREG_B0_P3_U0_CFG7 0x40010647u\r
+#define CYREG_B0_P3_U0_CFG8 0x40010648u\r
+#define CYREG_B0_P3_U0_CFG9 0x40010649u\r
+#define CYREG_B0_P3_U0_CFG10 0x4001064au\r
+#define CYREG_B0_P3_U0_CFG11 0x4001064bu\r
+#define CYREG_B0_P3_U0_CFG12 0x4001064cu\r
+#define CYREG_B0_P3_U0_CFG13 0x4001064du\r
+#define CYREG_B0_P3_U0_CFG14 0x4001064eu\r
+#define CYREG_B0_P3_U0_CFG15 0x4001064fu\r
+#define CYREG_B0_P3_U0_CFG16 0x40010650u\r
+#define CYREG_B0_P3_U0_CFG17 0x40010651u\r
+#define CYREG_B0_P3_U0_CFG18 0x40010652u\r
+#define CYREG_B0_P3_U0_CFG19 0x40010653u\r
+#define CYREG_B0_P3_U0_CFG20 0x40010654u\r
+#define CYREG_B0_P3_U0_CFG21 0x40010655u\r
+#define CYREG_B0_P3_U0_CFG22 0x40010656u\r
+#define CYREG_B0_P3_U0_CFG23 0x40010657u\r
+#define CYREG_B0_P3_U0_CFG24 0x40010658u\r
+#define CYREG_B0_P3_U0_CFG25 0x40010659u\r
+#define CYREG_B0_P3_U0_CFG26 0x4001065au\r
+#define CYREG_B0_P3_U0_CFG27 0x4001065bu\r
+#define CYREG_B0_P3_U0_CFG28 0x4001065cu\r
+#define CYREG_B0_P3_U0_CFG29 0x4001065du\r
+#define CYREG_B0_P3_U0_CFG30 0x4001065eu\r
+#define CYREG_B0_P3_U0_CFG31 0x4001065fu\r
+#define CYREG_B0_P3_U0_DCFG0 0x40010660u\r
+#define CYREG_B0_P3_U0_DCFG1 0x40010662u\r
+#define CYREG_B0_P3_U0_DCFG2 0x40010664u\r
+#define CYREG_B0_P3_U0_DCFG3 0x40010666u\r
+#define CYREG_B0_P3_U0_DCFG4 0x40010668u\r
+#define CYREG_B0_P3_U0_DCFG5 0x4001066au\r
+#define CYREG_B0_P3_U0_DCFG6 0x4001066cu\r
+#define CYREG_B0_P3_U0_DCFG7 0x4001066eu\r
+#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680u\r
+#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070u\r
+#define CYREG_B0_P3_U1_PLD_IT0 0x40010680u\r
+#define CYREG_B0_P3_U1_PLD_IT1 0x40010684u\r
+#define CYREG_B0_P3_U1_PLD_IT2 0x40010688u\r
+#define CYREG_B0_P3_U1_PLD_IT3 0x4001068cu\r
+#define CYREG_B0_P3_U1_PLD_IT4 0x40010690u\r
+#define CYREG_B0_P3_U1_PLD_IT5 0x40010694u\r
+#define CYREG_B0_P3_U1_PLD_IT6 0x40010698u\r
+#define CYREG_B0_P3_U1_PLD_IT7 0x4001069cu\r
+#define CYREG_B0_P3_U1_PLD_IT8 0x400106a0u\r
+#define CYREG_B0_P3_U1_PLD_IT9 0x400106a4u\r
+#define CYREG_B0_P3_U1_PLD_IT10 0x400106a8u\r
+#define CYREG_B0_P3_U1_PLD_IT11 0x400106acu\r
+#define CYREG_B0_P3_U1_PLD_ORT0 0x400106b0u\r
+#define CYREG_B0_P3_U1_PLD_ORT1 0x400106b2u\r
+#define CYREG_B0_P3_U1_PLD_ORT2 0x400106b4u\r
+#define CYREG_B0_P3_U1_PLD_ORT3 0x400106b6u\r
+#define CYREG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8u\r
+#define CYREG_B0_P3_U1_MC_CFG_XORFB 0x400106bau\r
+#define CYREG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bcu\r
+#define CYREG_B0_P3_U1_MC_CFG_BYPASS 0x400106beu\r
+#define CYREG_B0_P3_U1_CFG0 0x400106c0u\r
+#define CYREG_B0_P3_U1_CFG1 0x400106c1u\r
+#define CYREG_B0_P3_U1_CFG2 0x400106c2u\r
+#define CYREG_B0_P3_U1_CFG3 0x400106c3u\r
+#define CYREG_B0_P3_U1_CFG4 0x400106c4u\r
+#define CYREG_B0_P3_U1_CFG5 0x400106c5u\r
+#define CYREG_B0_P3_U1_CFG6 0x400106c6u\r
+#define CYREG_B0_P3_U1_CFG7 0x400106c7u\r
+#define CYREG_B0_P3_U1_CFG8 0x400106c8u\r
+#define CYREG_B0_P3_U1_CFG9 0x400106c9u\r
+#define CYREG_B0_P3_U1_CFG10 0x400106cau\r
+#define CYREG_B0_P3_U1_CFG11 0x400106cbu\r
+#define CYREG_B0_P3_U1_CFG12 0x400106ccu\r
+#define CYREG_B0_P3_U1_CFG13 0x400106cdu\r
+#define CYREG_B0_P3_U1_CFG14 0x400106ceu\r
+#define CYREG_B0_P3_U1_CFG15 0x400106cfu\r
+#define CYREG_B0_P3_U1_CFG16 0x400106d0u\r
+#define CYREG_B0_P3_U1_CFG17 0x400106d1u\r
+#define CYREG_B0_P3_U1_CFG18 0x400106d2u\r
+#define CYREG_B0_P3_U1_CFG19 0x400106d3u\r
+#define CYREG_B0_P3_U1_CFG20 0x400106d4u\r
+#define CYREG_B0_P3_U1_CFG21 0x400106d5u\r
+#define CYREG_B0_P3_U1_CFG22 0x400106d6u\r
+#define CYREG_B0_P3_U1_CFG23 0x400106d7u\r
+#define CYREG_B0_P3_U1_CFG24 0x400106d8u\r
+#define CYREG_B0_P3_U1_CFG25 0x400106d9u\r
+#define CYREG_B0_P3_U1_CFG26 0x400106dau\r
+#define CYREG_B0_P3_U1_CFG27 0x400106dbu\r
+#define CYREG_B0_P3_U1_CFG28 0x400106dcu\r
+#define CYREG_B0_P3_U1_CFG29 0x400106ddu\r
+#define CYREG_B0_P3_U1_CFG30 0x400106deu\r
+#define CYREG_B0_P3_U1_CFG31 0x400106dfu\r
+#define CYREG_B0_P3_U1_DCFG0 0x400106e0u\r
+#define CYREG_B0_P3_U1_DCFG1 0x400106e2u\r
+#define CYREG_B0_P3_U1_DCFG2 0x400106e4u\r
+#define CYREG_B0_P3_U1_DCFG3 0x400106e6u\r
+#define CYREG_B0_P3_U1_DCFG4 0x400106e8u\r
+#define CYREG_B0_P3_U1_DCFG5 0x400106eau\r
+#define CYREG_B0_P3_U1_DCFG6 0x400106ecu\r
+#define CYREG_B0_P3_U1_DCFG7 0x400106eeu\r
+#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700u\r
+#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B0_P4_BASE 0x40010800u\r
+#define CYDEV_UCFG_B0_P4_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800u\r
+#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070u\r
+#define CYREG_B0_P4_U0_PLD_IT0 0x40010800u\r
+#define CYREG_B0_P4_U0_PLD_IT1 0x40010804u\r
+#define CYREG_B0_P4_U0_PLD_IT2 0x40010808u\r
+#define CYREG_B0_P4_U0_PLD_IT3 0x4001080cu\r
+#define CYREG_B0_P4_U0_PLD_IT4 0x40010810u\r
+#define CYREG_B0_P4_U0_PLD_IT5 0x40010814u\r
+#define CYREG_B0_P4_U0_PLD_IT6 0x40010818u\r
+#define CYREG_B0_P4_U0_PLD_IT7 0x4001081cu\r
+#define CYREG_B0_P4_U0_PLD_IT8 0x40010820u\r
+#define CYREG_B0_P4_U0_PLD_IT9 0x40010824u\r
+#define CYREG_B0_P4_U0_PLD_IT10 0x40010828u\r
+#define CYREG_B0_P4_U0_PLD_IT11 0x4001082cu\r
+#define CYREG_B0_P4_U0_PLD_ORT0 0x40010830u\r
+#define CYREG_B0_P4_U0_PLD_ORT1 0x40010832u\r
+#define CYREG_B0_P4_U0_PLD_ORT2 0x40010834u\r
+#define CYREG_B0_P4_U0_PLD_ORT3 0x40010836u\r
+#define CYREG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838u\r
+#define CYREG_B0_P4_U0_MC_CFG_XORFB 0x4001083au\r
+#define CYREG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083cu\r
+#define CYREG_B0_P4_U0_MC_CFG_BYPASS 0x4001083eu\r
+#define CYREG_B0_P4_U0_CFG0 0x40010840u\r
+#define CYREG_B0_P4_U0_CFG1 0x40010841u\r
+#define CYREG_B0_P4_U0_CFG2 0x40010842u\r
+#define CYREG_B0_P4_U0_CFG3 0x40010843u\r
+#define CYREG_B0_P4_U0_CFG4 0x40010844u\r
+#define CYREG_B0_P4_U0_CFG5 0x40010845u\r
+#define CYREG_B0_P4_U0_CFG6 0x40010846u\r
+#define CYREG_B0_P4_U0_CFG7 0x40010847u\r
+#define CYREG_B0_P4_U0_CFG8 0x40010848u\r
+#define CYREG_B0_P4_U0_CFG9 0x40010849u\r
+#define CYREG_B0_P4_U0_CFG10 0x4001084au\r
+#define CYREG_B0_P4_U0_CFG11 0x4001084bu\r
+#define CYREG_B0_P4_U0_CFG12 0x4001084cu\r
+#define CYREG_B0_P4_U0_CFG13 0x4001084du\r
+#define CYREG_B0_P4_U0_CFG14 0x4001084eu\r
+#define CYREG_B0_P4_U0_CFG15 0x4001084fu\r
+#define CYREG_B0_P4_U0_CFG16 0x40010850u\r
+#define CYREG_B0_P4_U0_CFG17 0x40010851u\r
+#define CYREG_B0_P4_U0_CFG18 0x40010852u\r
+#define CYREG_B0_P4_U0_CFG19 0x40010853u\r
+#define CYREG_B0_P4_U0_CFG20 0x40010854u\r
+#define CYREG_B0_P4_U0_CFG21 0x40010855u\r
+#define CYREG_B0_P4_U0_CFG22 0x40010856u\r
+#define CYREG_B0_P4_U0_CFG23 0x40010857u\r
+#define CYREG_B0_P4_U0_CFG24 0x40010858u\r
+#define CYREG_B0_P4_U0_CFG25 0x40010859u\r
+#define CYREG_B0_P4_U0_CFG26 0x4001085au\r
+#define CYREG_B0_P4_U0_CFG27 0x4001085bu\r
+#define CYREG_B0_P4_U0_CFG28 0x4001085cu\r
+#define CYREG_B0_P4_U0_CFG29 0x4001085du\r
+#define CYREG_B0_P4_U0_CFG30 0x4001085eu\r
+#define CYREG_B0_P4_U0_CFG31 0x4001085fu\r
+#define CYREG_B0_P4_U0_DCFG0 0x40010860u\r
+#define CYREG_B0_P4_U0_DCFG1 0x40010862u\r
+#define CYREG_B0_P4_U0_DCFG2 0x40010864u\r
+#define CYREG_B0_P4_U0_DCFG3 0x40010866u\r
+#define CYREG_B0_P4_U0_DCFG4 0x40010868u\r
+#define CYREG_B0_P4_U0_DCFG5 0x4001086au\r
+#define CYREG_B0_P4_U0_DCFG6 0x4001086cu\r
+#define CYREG_B0_P4_U0_DCFG7 0x4001086eu\r
+#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880u\r
+#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070u\r
+#define CYREG_B0_P4_U1_PLD_IT0 0x40010880u\r
+#define CYREG_B0_P4_U1_PLD_IT1 0x40010884u\r
+#define CYREG_B0_P4_U1_PLD_IT2 0x40010888u\r
+#define CYREG_B0_P4_U1_PLD_IT3 0x4001088cu\r
+#define CYREG_B0_P4_U1_PLD_IT4 0x40010890u\r
+#define CYREG_B0_P4_U1_PLD_IT5 0x40010894u\r
+#define CYREG_B0_P4_U1_PLD_IT6 0x40010898u\r
+#define CYREG_B0_P4_U1_PLD_IT7 0x4001089cu\r
+#define CYREG_B0_P4_U1_PLD_IT8 0x400108a0u\r
+#define CYREG_B0_P4_U1_PLD_IT9 0x400108a4u\r
+#define CYREG_B0_P4_U1_PLD_IT10 0x400108a8u\r
+#define CYREG_B0_P4_U1_PLD_IT11 0x400108acu\r
+#define CYREG_B0_P4_U1_PLD_ORT0 0x400108b0u\r
+#define CYREG_B0_P4_U1_PLD_ORT1 0x400108b2u\r
+#define CYREG_B0_P4_U1_PLD_ORT2 0x400108b4u\r
+#define CYREG_B0_P4_U1_PLD_ORT3 0x400108b6u\r
+#define CYREG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8u\r
+#define CYREG_B0_P4_U1_MC_CFG_XORFB 0x400108bau\r
+#define CYREG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bcu\r
+#define CYREG_B0_P4_U1_MC_CFG_BYPASS 0x400108beu\r
+#define CYREG_B0_P4_U1_CFG0 0x400108c0u\r
+#define CYREG_B0_P4_U1_CFG1 0x400108c1u\r
+#define CYREG_B0_P4_U1_CFG2 0x400108c2u\r
+#define CYREG_B0_P4_U1_CFG3 0x400108c3u\r
+#define CYREG_B0_P4_U1_CFG4 0x400108c4u\r
+#define CYREG_B0_P4_U1_CFG5 0x400108c5u\r
+#define CYREG_B0_P4_U1_CFG6 0x400108c6u\r
+#define CYREG_B0_P4_U1_CFG7 0x400108c7u\r
+#define CYREG_B0_P4_U1_CFG8 0x400108c8u\r
+#define CYREG_B0_P4_U1_CFG9 0x400108c9u\r
+#define CYREG_B0_P4_U1_CFG10 0x400108cau\r
+#define CYREG_B0_P4_U1_CFG11 0x400108cbu\r
+#define CYREG_B0_P4_U1_CFG12 0x400108ccu\r
+#define CYREG_B0_P4_U1_CFG13 0x400108cdu\r
+#define CYREG_B0_P4_U1_CFG14 0x400108ceu\r
+#define CYREG_B0_P4_U1_CFG15 0x400108cfu\r
+#define CYREG_B0_P4_U1_CFG16 0x400108d0u\r
+#define CYREG_B0_P4_U1_CFG17 0x400108d1u\r
+#define CYREG_B0_P4_U1_CFG18 0x400108d2u\r
+#define CYREG_B0_P4_U1_CFG19 0x400108d3u\r
+#define CYREG_B0_P4_U1_CFG20 0x400108d4u\r
+#define CYREG_B0_P4_U1_CFG21 0x400108d5u\r
+#define CYREG_B0_P4_U1_CFG22 0x400108d6u\r
+#define CYREG_B0_P4_U1_CFG23 0x400108d7u\r
+#define CYREG_B0_P4_U1_CFG24 0x400108d8u\r
+#define CYREG_B0_P4_U1_CFG25 0x400108d9u\r
+#define CYREG_B0_P4_U1_CFG26 0x400108dau\r
+#define CYREG_B0_P4_U1_CFG27 0x400108dbu\r
+#define CYREG_B0_P4_U1_CFG28 0x400108dcu\r
+#define CYREG_B0_P4_U1_CFG29 0x400108ddu\r
+#define CYREG_B0_P4_U1_CFG30 0x400108deu\r
+#define CYREG_B0_P4_U1_CFG31 0x400108dfu\r
+#define CYREG_B0_P4_U1_DCFG0 0x400108e0u\r
+#define CYREG_B0_P4_U1_DCFG1 0x400108e2u\r
+#define CYREG_B0_P4_U1_DCFG2 0x400108e4u\r
+#define CYREG_B0_P4_U1_DCFG3 0x400108e6u\r
+#define CYREG_B0_P4_U1_DCFG4 0x400108e8u\r
+#define CYREG_B0_P4_U1_DCFG5 0x400108eau\r
+#define CYREG_B0_P4_U1_DCFG6 0x400108ecu\r
+#define CYREG_B0_P4_U1_DCFG7 0x400108eeu\r
+#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900u\r
+#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B0_P5_BASE 0x40010a00u\r
+#define CYDEV_UCFG_B0_P5_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00u\r
+#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070u\r
+#define CYREG_B0_P5_U0_PLD_IT0 0x40010a00u\r
+#define CYREG_B0_P5_U0_PLD_IT1 0x40010a04u\r
+#define CYREG_B0_P5_U0_PLD_IT2 0x40010a08u\r
+#define CYREG_B0_P5_U0_PLD_IT3 0x40010a0cu\r
+#define CYREG_B0_P5_U0_PLD_IT4 0x40010a10u\r
+#define CYREG_B0_P5_U0_PLD_IT5 0x40010a14u\r
+#define CYREG_B0_P5_U0_PLD_IT6 0x40010a18u\r
+#define CYREG_B0_P5_U0_PLD_IT7 0x40010a1cu\r
+#define CYREG_B0_P5_U0_PLD_IT8 0x40010a20u\r
+#define CYREG_B0_P5_U0_PLD_IT9 0x40010a24u\r
+#define CYREG_B0_P5_U0_PLD_IT10 0x40010a28u\r
+#define CYREG_B0_P5_U0_PLD_IT11 0x40010a2cu\r
+#define CYREG_B0_P5_U0_PLD_ORT0 0x40010a30u\r
+#define CYREG_B0_P5_U0_PLD_ORT1 0x40010a32u\r
+#define CYREG_B0_P5_U0_PLD_ORT2 0x40010a34u\r
+#define CYREG_B0_P5_U0_PLD_ORT3 0x40010a36u\r
+#define CYREG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38u\r
+#define CYREG_B0_P5_U0_MC_CFG_XORFB 0x40010a3au\r
+#define CYREG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3cu\r
+#define CYREG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3eu\r
+#define CYREG_B0_P5_U0_CFG0 0x40010a40u\r
+#define CYREG_B0_P5_U0_CFG1 0x40010a41u\r
+#define CYREG_B0_P5_U0_CFG2 0x40010a42u\r
+#define CYREG_B0_P5_U0_CFG3 0x40010a43u\r
+#define CYREG_B0_P5_U0_CFG4 0x40010a44u\r
+#define CYREG_B0_P5_U0_CFG5 0x40010a45u\r
+#define CYREG_B0_P5_U0_CFG6 0x40010a46u\r
+#define CYREG_B0_P5_U0_CFG7 0x40010a47u\r
+#define CYREG_B0_P5_U0_CFG8 0x40010a48u\r
+#define CYREG_B0_P5_U0_CFG9 0x40010a49u\r
+#define CYREG_B0_P5_U0_CFG10 0x40010a4au\r
+#define CYREG_B0_P5_U0_CFG11 0x40010a4bu\r
+#define CYREG_B0_P5_U0_CFG12 0x40010a4cu\r
+#define CYREG_B0_P5_U0_CFG13 0x40010a4du\r
+#define CYREG_B0_P5_U0_CFG14 0x40010a4eu\r
+#define CYREG_B0_P5_U0_CFG15 0x40010a4fu\r
+#define CYREG_B0_P5_U0_CFG16 0x40010a50u\r
+#define CYREG_B0_P5_U0_CFG17 0x40010a51u\r
+#define CYREG_B0_P5_U0_CFG18 0x40010a52u\r
+#define CYREG_B0_P5_U0_CFG19 0x40010a53u\r
+#define CYREG_B0_P5_U0_CFG20 0x40010a54u\r
+#define CYREG_B0_P5_U0_CFG21 0x40010a55u\r
+#define CYREG_B0_P5_U0_CFG22 0x40010a56u\r
+#define CYREG_B0_P5_U0_CFG23 0x40010a57u\r
+#define CYREG_B0_P5_U0_CFG24 0x40010a58u\r
+#define CYREG_B0_P5_U0_CFG25 0x40010a59u\r
+#define CYREG_B0_P5_U0_CFG26 0x40010a5au\r
+#define CYREG_B0_P5_U0_CFG27 0x40010a5bu\r
+#define CYREG_B0_P5_U0_CFG28 0x40010a5cu\r
+#define CYREG_B0_P5_U0_CFG29 0x40010a5du\r
+#define CYREG_B0_P5_U0_CFG30 0x40010a5eu\r
+#define CYREG_B0_P5_U0_CFG31 0x40010a5fu\r
+#define CYREG_B0_P5_U0_DCFG0 0x40010a60u\r
+#define CYREG_B0_P5_U0_DCFG1 0x40010a62u\r
+#define CYREG_B0_P5_U0_DCFG2 0x40010a64u\r
+#define CYREG_B0_P5_U0_DCFG3 0x40010a66u\r
+#define CYREG_B0_P5_U0_DCFG4 0x40010a68u\r
+#define CYREG_B0_P5_U0_DCFG5 0x40010a6au\r
+#define CYREG_B0_P5_U0_DCFG6 0x40010a6cu\r
+#define CYREG_B0_P5_U0_DCFG7 0x40010a6eu\r
+#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80u\r
+#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070u\r
+#define CYREG_B0_P5_U1_PLD_IT0 0x40010a80u\r
+#define CYREG_B0_P5_U1_PLD_IT1 0x40010a84u\r
+#define CYREG_B0_P5_U1_PLD_IT2 0x40010a88u\r
+#define CYREG_B0_P5_U1_PLD_IT3 0x40010a8cu\r
+#define CYREG_B0_P5_U1_PLD_IT4 0x40010a90u\r
+#define CYREG_B0_P5_U1_PLD_IT5 0x40010a94u\r
+#define CYREG_B0_P5_U1_PLD_IT6 0x40010a98u\r
+#define CYREG_B0_P5_U1_PLD_IT7 0x40010a9cu\r
+#define CYREG_B0_P5_U1_PLD_IT8 0x40010aa0u\r
+#define CYREG_B0_P5_U1_PLD_IT9 0x40010aa4u\r
+#define CYREG_B0_P5_U1_PLD_IT10 0x40010aa8u\r
+#define CYREG_B0_P5_U1_PLD_IT11 0x40010aacu\r
+#define CYREG_B0_P5_U1_PLD_ORT0 0x40010ab0u\r
+#define CYREG_B0_P5_U1_PLD_ORT1 0x40010ab2u\r
+#define CYREG_B0_P5_U1_PLD_ORT2 0x40010ab4u\r
+#define CYREG_B0_P5_U1_PLD_ORT3 0x40010ab6u\r
+#define CYREG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8u\r
+#define CYREG_B0_P5_U1_MC_CFG_XORFB 0x40010abau\r
+#define CYREG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abcu\r
+#define CYREG_B0_P5_U1_MC_CFG_BYPASS 0x40010abeu\r
+#define CYREG_B0_P5_U1_CFG0 0x40010ac0u\r
+#define CYREG_B0_P5_U1_CFG1 0x40010ac1u\r
+#define CYREG_B0_P5_U1_CFG2 0x40010ac2u\r
+#define CYREG_B0_P5_U1_CFG3 0x40010ac3u\r
+#define CYREG_B0_P5_U1_CFG4 0x40010ac4u\r
+#define CYREG_B0_P5_U1_CFG5 0x40010ac5u\r
+#define CYREG_B0_P5_U1_CFG6 0x40010ac6u\r
+#define CYREG_B0_P5_U1_CFG7 0x40010ac7u\r
+#define CYREG_B0_P5_U1_CFG8 0x40010ac8u\r
+#define CYREG_B0_P5_U1_CFG9 0x40010ac9u\r
+#define CYREG_B0_P5_U1_CFG10 0x40010acau\r
+#define CYREG_B0_P5_U1_CFG11 0x40010acbu\r
+#define CYREG_B0_P5_U1_CFG12 0x40010accu\r
+#define CYREG_B0_P5_U1_CFG13 0x40010acdu\r
+#define CYREG_B0_P5_U1_CFG14 0x40010aceu\r
+#define CYREG_B0_P5_U1_CFG15 0x40010acfu\r
+#define CYREG_B0_P5_U1_CFG16 0x40010ad0u\r
+#define CYREG_B0_P5_U1_CFG17 0x40010ad1u\r
+#define CYREG_B0_P5_U1_CFG18 0x40010ad2u\r
+#define CYREG_B0_P5_U1_CFG19 0x40010ad3u\r
+#define CYREG_B0_P5_U1_CFG20 0x40010ad4u\r
+#define CYREG_B0_P5_U1_CFG21 0x40010ad5u\r
+#define CYREG_B0_P5_U1_CFG22 0x40010ad6u\r
+#define CYREG_B0_P5_U1_CFG23 0x40010ad7u\r
+#define CYREG_B0_P5_U1_CFG24 0x40010ad8u\r
+#define CYREG_B0_P5_U1_CFG25 0x40010ad9u\r
+#define CYREG_B0_P5_U1_CFG26 0x40010adau\r
+#define CYREG_B0_P5_U1_CFG27 0x40010adbu\r
+#define CYREG_B0_P5_U1_CFG28 0x40010adcu\r
+#define CYREG_B0_P5_U1_CFG29 0x40010addu\r
+#define CYREG_B0_P5_U1_CFG30 0x40010adeu\r
+#define CYREG_B0_P5_U1_CFG31 0x40010adfu\r
+#define CYREG_B0_P5_U1_DCFG0 0x40010ae0u\r
+#define CYREG_B0_P5_U1_DCFG1 0x40010ae2u\r
+#define CYREG_B0_P5_U1_DCFG2 0x40010ae4u\r
+#define CYREG_B0_P5_U1_DCFG3 0x40010ae6u\r
+#define CYREG_B0_P5_U1_DCFG4 0x40010ae8u\r
+#define CYREG_B0_P5_U1_DCFG5 0x40010aeau\r
+#define CYREG_B0_P5_U1_DCFG6 0x40010aecu\r
+#define CYREG_B0_P5_U1_DCFG7 0x40010aeeu\r
+#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00u\r
+#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B0_P6_BASE 0x40010c00u\r
+#define CYDEV_UCFG_B0_P6_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00u\r
+#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070u\r
+#define CYREG_B0_P6_U0_PLD_IT0 0x40010c00u\r
+#define CYREG_B0_P6_U0_PLD_IT1 0x40010c04u\r
+#define CYREG_B0_P6_U0_PLD_IT2 0x40010c08u\r
+#define CYREG_B0_P6_U0_PLD_IT3 0x40010c0cu\r
+#define CYREG_B0_P6_U0_PLD_IT4 0x40010c10u\r
+#define CYREG_B0_P6_U0_PLD_IT5 0x40010c14u\r
+#define CYREG_B0_P6_U0_PLD_IT6 0x40010c18u\r
+#define CYREG_B0_P6_U0_PLD_IT7 0x40010c1cu\r
+#define CYREG_B0_P6_U0_PLD_IT8 0x40010c20u\r
+#define CYREG_B0_P6_U0_PLD_IT9 0x40010c24u\r
+#define CYREG_B0_P6_U0_PLD_IT10 0x40010c28u\r
+#define CYREG_B0_P6_U0_PLD_IT11 0x40010c2cu\r
+#define CYREG_B0_P6_U0_PLD_ORT0 0x40010c30u\r
+#define CYREG_B0_P6_U0_PLD_ORT1 0x40010c32u\r
+#define CYREG_B0_P6_U0_PLD_ORT2 0x40010c34u\r
+#define CYREG_B0_P6_U0_PLD_ORT3 0x40010c36u\r
+#define CYREG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38u\r
+#define CYREG_B0_P6_U0_MC_CFG_XORFB 0x40010c3au\r
+#define CYREG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3cu\r
+#define CYREG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3eu\r
+#define CYREG_B0_P6_U0_CFG0 0x40010c40u\r
+#define CYREG_B0_P6_U0_CFG1 0x40010c41u\r
+#define CYREG_B0_P6_U0_CFG2 0x40010c42u\r
+#define CYREG_B0_P6_U0_CFG3 0x40010c43u\r
+#define CYREG_B0_P6_U0_CFG4 0x40010c44u\r
+#define CYREG_B0_P6_U0_CFG5 0x40010c45u\r
+#define CYREG_B0_P6_U0_CFG6 0x40010c46u\r
+#define CYREG_B0_P6_U0_CFG7 0x40010c47u\r
+#define CYREG_B0_P6_U0_CFG8 0x40010c48u\r
+#define CYREG_B0_P6_U0_CFG9 0x40010c49u\r
+#define CYREG_B0_P6_U0_CFG10 0x40010c4au\r
+#define CYREG_B0_P6_U0_CFG11 0x40010c4bu\r
+#define CYREG_B0_P6_U0_CFG12 0x40010c4cu\r
+#define CYREG_B0_P6_U0_CFG13 0x40010c4du\r
+#define CYREG_B0_P6_U0_CFG14 0x40010c4eu\r
+#define CYREG_B0_P6_U0_CFG15 0x40010c4fu\r
+#define CYREG_B0_P6_U0_CFG16 0x40010c50u\r
+#define CYREG_B0_P6_U0_CFG17 0x40010c51u\r
+#define CYREG_B0_P6_U0_CFG18 0x40010c52u\r
+#define CYREG_B0_P6_U0_CFG19 0x40010c53u\r
+#define CYREG_B0_P6_U0_CFG20 0x40010c54u\r
+#define CYREG_B0_P6_U0_CFG21 0x40010c55u\r
+#define CYREG_B0_P6_U0_CFG22 0x40010c56u\r
+#define CYREG_B0_P6_U0_CFG23 0x40010c57u\r
+#define CYREG_B0_P6_U0_CFG24 0x40010c58u\r
+#define CYREG_B0_P6_U0_CFG25 0x40010c59u\r
+#define CYREG_B0_P6_U0_CFG26 0x40010c5au\r
+#define CYREG_B0_P6_U0_CFG27 0x40010c5bu\r
+#define CYREG_B0_P6_U0_CFG28 0x40010c5cu\r
+#define CYREG_B0_P6_U0_CFG29 0x40010c5du\r
+#define CYREG_B0_P6_U0_CFG30 0x40010c5eu\r
+#define CYREG_B0_P6_U0_CFG31 0x40010c5fu\r
+#define CYREG_B0_P6_U0_DCFG0 0x40010c60u\r
+#define CYREG_B0_P6_U0_DCFG1 0x40010c62u\r
+#define CYREG_B0_P6_U0_DCFG2 0x40010c64u\r
+#define CYREG_B0_P6_U0_DCFG3 0x40010c66u\r
+#define CYREG_B0_P6_U0_DCFG4 0x40010c68u\r
+#define CYREG_B0_P6_U0_DCFG5 0x40010c6au\r
+#define CYREG_B0_P6_U0_DCFG6 0x40010c6cu\r
+#define CYREG_B0_P6_U0_DCFG7 0x40010c6eu\r
+#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80u\r
+#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070u\r
+#define CYREG_B0_P6_U1_PLD_IT0 0x40010c80u\r
+#define CYREG_B0_P6_U1_PLD_IT1 0x40010c84u\r
+#define CYREG_B0_P6_U1_PLD_IT2 0x40010c88u\r
+#define CYREG_B0_P6_U1_PLD_IT3 0x40010c8cu\r
+#define CYREG_B0_P6_U1_PLD_IT4 0x40010c90u\r
+#define CYREG_B0_P6_U1_PLD_IT5 0x40010c94u\r
+#define CYREG_B0_P6_U1_PLD_IT6 0x40010c98u\r
+#define CYREG_B0_P6_U1_PLD_IT7 0x40010c9cu\r
+#define CYREG_B0_P6_U1_PLD_IT8 0x40010ca0u\r
+#define CYREG_B0_P6_U1_PLD_IT9 0x40010ca4u\r
+#define CYREG_B0_P6_U1_PLD_IT10 0x40010ca8u\r
+#define CYREG_B0_P6_U1_PLD_IT11 0x40010cacu\r
+#define CYREG_B0_P6_U1_PLD_ORT0 0x40010cb0u\r
+#define CYREG_B0_P6_U1_PLD_ORT1 0x40010cb2u\r
+#define CYREG_B0_P6_U1_PLD_ORT2 0x40010cb4u\r
+#define CYREG_B0_P6_U1_PLD_ORT3 0x40010cb6u\r
+#define CYREG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8u\r
+#define CYREG_B0_P6_U1_MC_CFG_XORFB 0x40010cbau\r
+#define CYREG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbcu\r
+#define CYREG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbeu\r
+#define CYREG_B0_P6_U1_CFG0 0x40010cc0u\r
+#define CYREG_B0_P6_U1_CFG1 0x40010cc1u\r
+#define CYREG_B0_P6_U1_CFG2 0x40010cc2u\r
+#define CYREG_B0_P6_U1_CFG3 0x40010cc3u\r
+#define CYREG_B0_P6_U1_CFG4 0x40010cc4u\r
+#define CYREG_B0_P6_U1_CFG5 0x40010cc5u\r
+#define CYREG_B0_P6_U1_CFG6 0x40010cc6u\r
+#define CYREG_B0_P6_U1_CFG7 0x40010cc7u\r
+#define CYREG_B0_P6_U1_CFG8 0x40010cc8u\r
+#define CYREG_B0_P6_U1_CFG9 0x40010cc9u\r
+#define CYREG_B0_P6_U1_CFG10 0x40010ccau\r
+#define CYREG_B0_P6_U1_CFG11 0x40010ccbu\r
+#define CYREG_B0_P6_U1_CFG12 0x40010cccu\r
+#define CYREG_B0_P6_U1_CFG13 0x40010ccdu\r
+#define CYREG_B0_P6_U1_CFG14 0x40010cceu\r
+#define CYREG_B0_P6_U1_CFG15 0x40010ccfu\r
+#define CYREG_B0_P6_U1_CFG16 0x40010cd0u\r
+#define CYREG_B0_P6_U1_CFG17 0x40010cd1u\r
+#define CYREG_B0_P6_U1_CFG18 0x40010cd2u\r
+#define CYREG_B0_P6_U1_CFG19 0x40010cd3u\r
+#define CYREG_B0_P6_U1_CFG20 0x40010cd4u\r
+#define CYREG_B0_P6_U1_CFG21 0x40010cd5u\r
+#define CYREG_B0_P6_U1_CFG22 0x40010cd6u\r
+#define CYREG_B0_P6_U1_CFG23 0x40010cd7u\r
+#define CYREG_B0_P6_U1_CFG24 0x40010cd8u\r
+#define CYREG_B0_P6_U1_CFG25 0x40010cd9u\r
+#define CYREG_B0_P6_U1_CFG26 0x40010cdau\r
+#define CYREG_B0_P6_U1_CFG27 0x40010cdbu\r
+#define CYREG_B0_P6_U1_CFG28 0x40010cdcu\r
+#define CYREG_B0_P6_U1_CFG29 0x40010cddu\r
+#define CYREG_B0_P6_U1_CFG30 0x40010cdeu\r
+#define CYREG_B0_P6_U1_CFG31 0x40010cdfu\r
+#define CYREG_B0_P6_U1_DCFG0 0x40010ce0u\r
+#define CYREG_B0_P6_U1_DCFG1 0x40010ce2u\r
+#define CYREG_B0_P6_U1_DCFG2 0x40010ce4u\r
+#define CYREG_B0_P6_U1_DCFG3 0x40010ce6u\r
+#define CYREG_B0_P6_U1_DCFG4 0x40010ce8u\r
+#define CYREG_B0_P6_U1_DCFG5 0x40010ceau\r
+#define CYREG_B0_P6_U1_DCFG6 0x40010cecu\r
+#define CYREG_B0_P6_U1_DCFG7 0x40010ceeu\r
+#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00u\r
+#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B0_P7_BASE 0x40010e00u\r
+#define CYDEV_UCFG_B0_P7_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00u\r
+#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070u\r
+#define CYREG_B0_P7_U0_PLD_IT0 0x40010e00u\r
+#define CYREG_B0_P7_U0_PLD_IT1 0x40010e04u\r
+#define CYREG_B0_P7_U0_PLD_IT2 0x40010e08u\r
+#define CYREG_B0_P7_U0_PLD_IT3 0x40010e0cu\r
+#define CYREG_B0_P7_U0_PLD_IT4 0x40010e10u\r
+#define CYREG_B0_P7_U0_PLD_IT5 0x40010e14u\r
+#define CYREG_B0_P7_U0_PLD_IT6 0x40010e18u\r
+#define CYREG_B0_P7_U0_PLD_IT7 0x40010e1cu\r
+#define CYREG_B0_P7_U0_PLD_IT8 0x40010e20u\r
+#define CYREG_B0_P7_U0_PLD_IT9 0x40010e24u\r
+#define CYREG_B0_P7_U0_PLD_IT10 0x40010e28u\r
+#define CYREG_B0_P7_U0_PLD_IT11 0x40010e2cu\r
+#define CYREG_B0_P7_U0_PLD_ORT0 0x40010e30u\r
+#define CYREG_B0_P7_U0_PLD_ORT1 0x40010e32u\r
+#define CYREG_B0_P7_U0_PLD_ORT2 0x40010e34u\r
+#define CYREG_B0_P7_U0_PLD_ORT3 0x40010e36u\r
+#define CYREG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38u\r
+#define CYREG_B0_P7_U0_MC_CFG_XORFB 0x40010e3au\r
+#define CYREG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3cu\r
+#define CYREG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3eu\r
+#define CYREG_B0_P7_U0_CFG0 0x40010e40u\r
+#define CYREG_B0_P7_U0_CFG1 0x40010e41u\r
+#define CYREG_B0_P7_U0_CFG2 0x40010e42u\r
+#define CYREG_B0_P7_U0_CFG3 0x40010e43u\r
+#define CYREG_B0_P7_U0_CFG4 0x40010e44u\r
+#define CYREG_B0_P7_U0_CFG5 0x40010e45u\r
+#define CYREG_B0_P7_U0_CFG6 0x40010e46u\r
+#define CYREG_B0_P7_U0_CFG7 0x40010e47u\r
+#define CYREG_B0_P7_U0_CFG8 0x40010e48u\r
+#define CYREG_B0_P7_U0_CFG9 0x40010e49u\r
+#define CYREG_B0_P7_U0_CFG10 0x40010e4au\r
+#define CYREG_B0_P7_U0_CFG11 0x40010e4bu\r
+#define CYREG_B0_P7_U0_CFG12 0x40010e4cu\r
+#define CYREG_B0_P7_U0_CFG13 0x40010e4du\r
+#define CYREG_B0_P7_U0_CFG14 0x40010e4eu\r
+#define CYREG_B0_P7_U0_CFG15 0x40010e4fu\r
+#define CYREG_B0_P7_U0_CFG16 0x40010e50u\r
+#define CYREG_B0_P7_U0_CFG17 0x40010e51u\r
+#define CYREG_B0_P7_U0_CFG18 0x40010e52u\r
+#define CYREG_B0_P7_U0_CFG19 0x40010e53u\r
+#define CYREG_B0_P7_U0_CFG20 0x40010e54u\r
+#define CYREG_B0_P7_U0_CFG21 0x40010e55u\r
+#define CYREG_B0_P7_U0_CFG22 0x40010e56u\r
+#define CYREG_B0_P7_U0_CFG23 0x40010e57u\r
+#define CYREG_B0_P7_U0_CFG24 0x40010e58u\r
+#define CYREG_B0_P7_U0_CFG25 0x40010e59u\r
+#define CYREG_B0_P7_U0_CFG26 0x40010e5au\r
+#define CYREG_B0_P7_U0_CFG27 0x40010e5bu\r
+#define CYREG_B0_P7_U0_CFG28 0x40010e5cu\r
+#define CYREG_B0_P7_U0_CFG29 0x40010e5du\r
+#define CYREG_B0_P7_U0_CFG30 0x40010e5eu\r
+#define CYREG_B0_P7_U0_CFG31 0x40010e5fu\r
+#define CYREG_B0_P7_U0_DCFG0 0x40010e60u\r
+#define CYREG_B0_P7_U0_DCFG1 0x40010e62u\r
+#define CYREG_B0_P7_U0_DCFG2 0x40010e64u\r
+#define CYREG_B0_P7_U0_DCFG3 0x40010e66u\r
+#define CYREG_B0_P7_U0_DCFG4 0x40010e68u\r
+#define CYREG_B0_P7_U0_DCFG5 0x40010e6au\r
+#define CYREG_B0_P7_U0_DCFG6 0x40010e6cu\r
+#define CYREG_B0_P7_U0_DCFG7 0x40010e6eu\r
+#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80u\r
+#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070u\r
+#define CYREG_B0_P7_U1_PLD_IT0 0x40010e80u\r
+#define CYREG_B0_P7_U1_PLD_IT1 0x40010e84u\r
+#define CYREG_B0_P7_U1_PLD_IT2 0x40010e88u\r
+#define CYREG_B0_P7_U1_PLD_IT3 0x40010e8cu\r
+#define CYREG_B0_P7_U1_PLD_IT4 0x40010e90u\r
+#define CYREG_B0_P7_U1_PLD_IT5 0x40010e94u\r
+#define CYREG_B0_P7_U1_PLD_IT6 0x40010e98u\r
+#define CYREG_B0_P7_U1_PLD_IT7 0x40010e9cu\r
+#define CYREG_B0_P7_U1_PLD_IT8 0x40010ea0u\r
+#define CYREG_B0_P7_U1_PLD_IT9 0x40010ea4u\r
+#define CYREG_B0_P7_U1_PLD_IT10 0x40010ea8u\r
+#define CYREG_B0_P7_U1_PLD_IT11 0x40010eacu\r
+#define CYREG_B0_P7_U1_PLD_ORT0 0x40010eb0u\r
+#define CYREG_B0_P7_U1_PLD_ORT1 0x40010eb2u\r
+#define CYREG_B0_P7_U1_PLD_ORT2 0x40010eb4u\r
+#define CYREG_B0_P7_U1_PLD_ORT3 0x40010eb6u\r
+#define CYREG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8u\r
+#define CYREG_B0_P7_U1_MC_CFG_XORFB 0x40010ebau\r
+#define CYREG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebcu\r
+#define CYREG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebeu\r
+#define CYREG_B0_P7_U1_CFG0 0x40010ec0u\r
+#define CYREG_B0_P7_U1_CFG1 0x40010ec1u\r
+#define CYREG_B0_P7_U1_CFG2 0x40010ec2u\r
+#define CYREG_B0_P7_U1_CFG3 0x40010ec3u\r
+#define CYREG_B0_P7_U1_CFG4 0x40010ec4u\r
+#define CYREG_B0_P7_U1_CFG5 0x40010ec5u\r
+#define CYREG_B0_P7_U1_CFG6 0x40010ec6u\r
+#define CYREG_B0_P7_U1_CFG7 0x40010ec7u\r
+#define CYREG_B0_P7_U1_CFG8 0x40010ec8u\r
+#define CYREG_B0_P7_U1_CFG9 0x40010ec9u\r
+#define CYREG_B0_P7_U1_CFG10 0x40010ecau\r
+#define CYREG_B0_P7_U1_CFG11 0x40010ecbu\r
+#define CYREG_B0_P7_U1_CFG12 0x40010eccu\r
+#define CYREG_B0_P7_U1_CFG13 0x40010ecdu\r
+#define CYREG_B0_P7_U1_CFG14 0x40010eceu\r
+#define CYREG_B0_P7_U1_CFG15 0x40010ecfu\r
+#define CYREG_B0_P7_U1_CFG16 0x40010ed0u\r
+#define CYREG_B0_P7_U1_CFG17 0x40010ed1u\r
+#define CYREG_B0_P7_U1_CFG18 0x40010ed2u\r
+#define CYREG_B0_P7_U1_CFG19 0x40010ed3u\r
+#define CYREG_B0_P7_U1_CFG20 0x40010ed4u\r
+#define CYREG_B0_P7_U1_CFG21 0x40010ed5u\r
+#define CYREG_B0_P7_U1_CFG22 0x40010ed6u\r
+#define CYREG_B0_P7_U1_CFG23 0x40010ed7u\r
+#define CYREG_B0_P7_U1_CFG24 0x40010ed8u\r
+#define CYREG_B0_P7_U1_CFG25 0x40010ed9u\r
+#define CYREG_B0_P7_U1_CFG26 0x40010edau\r
+#define CYREG_B0_P7_U1_CFG27 0x40010edbu\r
+#define CYREG_B0_P7_U1_CFG28 0x40010edcu\r
+#define CYREG_B0_P7_U1_CFG29 0x40010eddu\r
+#define CYREG_B0_P7_U1_CFG30 0x40010edeu\r
+#define CYREG_B0_P7_U1_CFG31 0x40010edfu\r
+#define CYREG_B0_P7_U1_DCFG0 0x40010ee0u\r
+#define CYREG_B0_P7_U1_DCFG1 0x40010ee2u\r
+#define CYREG_B0_P7_U1_DCFG2 0x40010ee4u\r
+#define CYREG_B0_P7_U1_DCFG3 0x40010ee6u\r
+#define CYREG_B0_P7_U1_DCFG4 0x40010ee8u\r
+#define CYREG_B0_P7_U1_DCFG5 0x40010eeau\r
+#define CYREG_B0_P7_U1_DCFG6 0x40010eecu\r
+#define CYREG_B0_P7_U1_DCFG7 0x40010eeeu\r
+#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00u\r
+#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B1_BASE 0x40011000u\r
+#define CYDEV_UCFG_B1_SIZE 0x00000fefu\r
+#define CYDEV_UCFG_B1_P2_BASE 0x40011400u\r
+#define CYDEV_UCFG_B1_P2_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400u\r
+#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070u\r
+#define CYREG_B1_P2_U0_PLD_IT0 0x40011400u\r
+#define CYREG_B1_P2_U0_PLD_IT1 0x40011404u\r
+#define CYREG_B1_P2_U0_PLD_IT2 0x40011408u\r
+#define CYREG_B1_P2_U0_PLD_IT3 0x4001140cu\r
+#define CYREG_B1_P2_U0_PLD_IT4 0x40011410u\r
+#define CYREG_B1_P2_U0_PLD_IT5 0x40011414u\r
+#define CYREG_B1_P2_U0_PLD_IT6 0x40011418u\r
+#define CYREG_B1_P2_U0_PLD_IT7 0x4001141cu\r
+#define CYREG_B1_P2_U0_PLD_IT8 0x40011420u\r
+#define CYREG_B1_P2_U0_PLD_IT9 0x40011424u\r
+#define CYREG_B1_P2_U0_PLD_IT10 0x40011428u\r
+#define CYREG_B1_P2_U0_PLD_IT11 0x4001142cu\r
+#define CYREG_B1_P2_U0_PLD_ORT0 0x40011430u\r
+#define CYREG_B1_P2_U0_PLD_ORT1 0x40011432u\r
+#define CYREG_B1_P2_U0_PLD_ORT2 0x40011434u\r
+#define CYREG_B1_P2_U0_PLD_ORT3 0x40011436u\r
+#define CYREG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438u\r
+#define CYREG_B1_P2_U0_MC_CFG_XORFB 0x4001143au\r
+#define CYREG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143cu\r
+#define CYREG_B1_P2_U0_MC_CFG_BYPASS 0x4001143eu\r
+#define CYREG_B1_P2_U0_CFG0 0x40011440u\r
+#define CYREG_B1_P2_U0_CFG1 0x40011441u\r
+#define CYREG_B1_P2_U0_CFG2 0x40011442u\r
+#define CYREG_B1_P2_U0_CFG3 0x40011443u\r
+#define CYREG_B1_P2_U0_CFG4 0x40011444u\r
+#define CYREG_B1_P2_U0_CFG5 0x40011445u\r
+#define CYREG_B1_P2_U0_CFG6 0x40011446u\r
+#define CYREG_B1_P2_U0_CFG7 0x40011447u\r
+#define CYREG_B1_P2_U0_CFG8 0x40011448u\r
+#define CYREG_B1_P2_U0_CFG9 0x40011449u\r
+#define CYREG_B1_P2_U0_CFG10 0x4001144au\r
+#define CYREG_B1_P2_U0_CFG11 0x4001144bu\r
+#define CYREG_B1_P2_U0_CFG12 0x4001144cu\r
+#define CYREG_B1_P2_U0_CFG13 0x4001144du\r
+#define CYREG_B1_P2_U0_CFG14 0x4001144eu\r
+#define CYREG_B1_P2_U0_CFG15 0x4001144fu\r
+#define CYREG_B1_P2_U0_CFG16 0x40011450u\r
+#define CYREG_B1_P2_U0_CFG17 0x40011451u\r
+#define CYREG_B1_P2_U0_CFG18 0x40011452u\r
+#define CYREG_B1_P2_U0_CFG19 0x40011453u\r
+#define CYREG_B1_P2_U0_CFG20 0x40011454u\r
+#define CYREG_B1_P2_U0_CFG21 0x40011455u\r
+#define CYREG_B1_P2_U0_CFG22 0x40011456u\r
+#define CYREG_B1_P2_U0_CFG23 0x40011457u\r
+#define CYREG_B1_P2_U0_CFG24 0x40011458u\r
+#define CYREG_B1_P2_U0_CFG25 0x40011459u\r
+#define CYREG_B1_P2_U0_CFG26 0x4001145au\r
+#define CYREG_B1_P2_U0_CFG27 0x4001145bu\r
+#define CYREG_B1_P2_U0_CFG28 0x4001145cu\r
+#define CYREG_B1_P2_U0_CFG29 0x4001145du\r
+#define CYREG_B1_P2_U0_CFG30 0x4001145eu\r
+#define CYREG_B1_P2_U0_CFG31 0x4001145fu\r
+#define CYREG_B1_P2_U0_DCFG0 0x40011460u\r
+#define CYREG_B1_P2_U0_DCFG1 0x40011462u\r
+#define CYREG_B1_P2_U0_DCFG2 0x40011464u\r
+#define CYREG_B1_P2_U0_DCFG3 0x40011466u\r
+#define CYREG_B1_P2_U0_DCFG4 0x40011468u\r
+#define CYREG_B1_P2_U0_DCFG5 0x4001146au\r
+#define CYREG_B1_P2_U0_DCFG6 0x4001146cu\r
+#define CYREG_B1_P2_U0_DCFG7 0x4001146eu\r
+#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480u\r
+#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070u\r
+#define CYREG_B1_P2_U1_PLD_IT0 0x40011480u\r
+#define CYREG_B1_P2_U1_PLD_IT1 0x40011484u\r
+#define CYREG_B1_P2_U1_PLD_IT2 0x40011488u\r
+#define CYREG_B1_P2_U1_PLD_IT3 0x4001148cu\r
+#define CYREG_B1_P2_U1_PLD_IT4 0x40011490u\r
+#define CYREG_B1_P2_U1_PLD_IT5 0x40011494u\r
+#define CYREG_B1_P2_U1_PLD_IT6 0x40011498u\r
+#define CYREG_B1_P2_U1_PLD_IT7 0x4001149cu\r
+#define CYREG_B1_P2_U1_PLD_IT8 0x400114a0u\r
+#define CYREG_B1_P2_U1_PLD_IT9 0x400114a4u\r
+#define CYREG_B1_P2_U1_PLD_IT10 0x400114a8u\r
+#define CYREG_B1_P2_U1_PLD_IT11 0x400114acu\r
+#define CYREG_B1_P2_U1_PLD_ORT0 0x400114b0u\r
+#define CYREG_B1_P2_U1_PLD_ORT1 0x400114b2u\r
+#define CYREG_B1_P2_U1_PLD_ORT2 0x400114b4u\r
+#define CYREG_B1_P2_U1_PLD_ORT3 0x400114b6u\r
+#define CYREG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8u\r
+#define CYREG_B1_P2_U1_MC_CFG_XORFB 0x400114bau\r
+#define CYREG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bcu\r
+#define CYREG_B1_P2_U1_MC_CFG_BYPASS 0x400114beu\r
+#define CYREG_B1_P2_U1_CFG0 0x400114c0u\r
+#define CYREG_B1_P2_U1_CFG1 0x400114c1u\r
+#define CYREG_B1_P2_U1_CFG2 0x400114c2u\r
+#define CYREG_B1_P2_U1_CFG3 0x400114c3u\r
+#define CYREG_B1_P2_U1_CFG4 0x400114c4u\r
+#define CYREG_B1_P2_U1_CFG5 0x400114c5u\r
+#define CYREG_B1_P2_U1_CFG6 0x400114c6u\r
+#define CYREG_B1_P2_U1_CFG7 0x400114c7u\r
+#define CYREG_B1_P2_U1_CFG8 0x400114c8u\r
+#define CYREG_B1_P2_U1_CFG9 0x400114c9u\r
+#define CYREG_B1_P2_U1_CFG10 0x400114cau\r
+#define CYREG_B1_P2_U1_CFG11 0x400114cbu\r
+#define CYREG_B1_P2_U1_CFG12 0x400114ccu\r
+#define CYREG_B1_P2_U1_CFG13 0x400114cdu\r
+#define CYREG_B1_P2_U1_CFG14 0x400114ceu\r
+#define CYREG_B1_P2_U1_CFG15 0x400114cfu\r
+#define CYREG_B1_P2_U1_CFG16 0x400114d0u\r
+#define CYREG_B1_P2_U1_CFG17 0x400114d1u\r
+#define CYREG_B1_P2_U1_CFG18 0x400114d2u\r
+#define CYREG_B1_P2_U1_CFG19 0x400114d3u\r
+#define CYREG_B1_P2_U1_CFG20 0x400114d4u\r
+#define CYREG_B1_P2_U1_CFG21 0x400114d5u\r
+#define CYREG_B1_P2_U1_CFG22 0x400114d6u\r
+#define CYREG_B1_P2_U1_CFG23 0x400114d7u\r
+#define CYREG_B1_P2_U1_CFG24 0x400114d8u\r
+#define CYREG_B1_P2_U1_CFG25 0x400114d9u\r
+#define CYREG_B1_P2_U1_CFG26 0x400114dau\r
+#define CYREG_B1_P2_U1_CFG27 0x400114dbu\r
+#define CYREG_B1_P2_U1_CFG28 0x400114dcu\r
+#define CYREG_B1_P2_U1_CFG29 0x400114ddu\r
+#define CYREG_B1_P2_U1_CFG30 0x400114deu\r
+#define CYREG_B1_P2_U1_CFG31 0x400114dfu\r
+#define CYREG_B1_P2_U1_DCFG0 0x400114e0u\r
+#define CYREG_B1_P2_U1_DCFG1 0x400114e2u\r
+#define CYREG_B1_P2_U1_DCFG2 0x400114e4u\r
+#define CYREG_B1_P2_U1_DCFG3 0x400114e6u\r
+#define CYREG_B1_P2_U1_DCFG4 0x400114e8u\r
+#define CYREG_B1_P2_U1_DCFG5 0x400114eau\r
+#define CYREG_B1_P2_U1_DCFG6 0x400114ecu\r
+#define CYREG_B1_P2_U1_DCFG7 0x400114eeu\r
+#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500u\r
+#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B1_P3_BASE 0x40011600u\r
+#define CYDEV_UCFG_B1_P3_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600u\r
+#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070u\r
+#define CYREG_B1_P3_U0_PLD_IT0 0x40011600u\r
+#define CYREG_B1_P3_U0_PLD_IT1 0x40011604u\r
+#define CYREG_B1_P3_U0_PLD_IT2 0x40011608u\r
+#define CYREG_B1_P3_U0_PLD_IT3 0x4001160cu\r
+#define CYREG_B1_P3_U0_PLD_IT4 0x40011610u\r
+#define CYREG_B1_P3_U0_PLD_IT5 0x40011614u\r
+#define CYREG_B1_P3_U0_PLD_IT6 0x40011618u\r
+#define CYREG_B1_P3_U0_PLD_IT7 0x4001161cu\r
+#define CYREG_B1_P3_U0_PLD_IT8 0x40011620u\r
+#define CYREG_B1_P3_U0_PLD_IT9 0x40011624u\r
+#define CYREG_B1_P3_U0_PLD_IT10 0x40011628u\r
+#define CYREG_B1_P3_U0_PLD_IT11 0x4001162cu\r
+#define CYREG_B1_P3_U0_PLD_ORT0 0x40011630u\r
+#define CYREG_B1_P3_U0_PLD_ORT1 0x40011632u\r
+#define CYREG_B1_P3_U0_PLD_ORT2 0x40011634u\r
+#define CYREG_B1_P3_U0_PLD_ORT3 0x40011636u\r
+#define CYREG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638u\r
+#define CYREG_B1_P3_U0_MC_CFG_XORFB 0x4001163au\r
+#define CYREG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163cu\r
+#define CYREG_B1_P3_U0_MC_CFG_BYPASS 0x4001163eu\r
+#define CYREG_B1_P3_U0_CFG0 0x40011640u\r
+#define CYREG_B1_P3_U0_CFG1 0x40011641u\r
+#define CYREG_B1_P3_U0_CFG2 0x40011642u\r
+#define CYREG_B1_P3_U0_CFG3 0x40011643u\r
+#define CYREG_B1_P3_U0_CFG4 0x40011644u\r
+#define CYREG_B1_P3_U0_CFG5 0x40011645u\r
+#define CYREG_B1_P3_U0_CFG6 0x40011646u\r
+#define CYREG_B1_P3_U0_CFG7 0x40011647u\r
+#define CYREG_B1_P3_U0_CFG8 0x40011648u\r
+#define CYREG_B1_P3_U0_CFG9 0x40011649u\r
+#define CYREG_B1_P3_U0_CFG10 0x4001164au\r
+#define CYREG_B1_P3_U0_CFG11 0x4001164bu\r
+#define CYREG_B1_P3_U0_CFG12 0x4001164cu\r
+#define CYREG_B1_P3_U0_CFG13 0x4001164du\r
+#define CYREG_B1_P3_U0_CFG14 0x4001164eu\r
+#define CYREG_B1_P3_U0_CFG15 0x4001164fu\r
+#define CYREG_B1_P3_U0_CFG16 0x40011650u\r
+#define CYREG_B1_P3_U0_CFG17 0x40011651u\r
+#define CYREG_B1_P3_U0_CFG18 0x40011652u\r
+#define CYREG_B1_P3_U0_CFG19 0x40011653u\r
+#define CYREG_B1_P3_U0_CFG20 0x40011654u\r
+#define CYREG_B1_P3_U0_CFG21 0x40011655u\r
+#define CYREG_B1_P3_U0_CFG22 0x40011656u\r
+#define CYREG_B1_P3_U0_CFG23 0x40011657u\r
+#define CYREG_B1_P3_U0_CFG24 0x40011658u\r
+#define CYREG_B1_P3_U0_CFG25 0x40011659u\r
+#define CYREG_B1_P3_U0_CFG26 0x4001165au\r
+#define CYREG_B1_P3_U0_CFG27 0x4001165bu\r
+#define CYREG_B1_P3_U0_CFG28 0x4001165cu\r
+#define CYREG_B1_P3_U0_CFG29 0x4001165du\r
+#define CYREG_B1_P3_U0_CFG30 0x4001165eu\r
+#define CYREG_B1_P3_U0_CFG31 0x4001165fu\r
+#define CYREG_B1_P3_U0_DCFG0 0x40011660u\r
+#define CYREG_B1_P3_U0_DCFG1 0x40011662u\r
+#define CYREG_B1_P3_U0_DCFG2 0x40011664u\r
+#define CYREG_B1_P3_U0_DCFG3 0x40011666u\r
+#define CYREG_B1_P3_U0_DCFG4 0x40011668u\r
+#define CYREG_B1_P3_U0_DCFG5 0x4001166au\r
+#define CYREG_B1_P3_U0_DCFG6 0x4001166cu\r
+#define CYREG_B1_P3_U0_DCFG7 0x4001166eu\r
+#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680u\r
+#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070u\r
+#define CYREG_B1_P3_U1_PLD_IT0 0x40011680u\r
+#define CYREG_B1_P3_U1_PLD_IT1 0x40011684u\r
+#define CYREG_B1_P3_U1_PLD_IT2 0x40011688u\r
+#define CYREG_B1_P3_U1_PLD_IT3 0x4001168cu\r
+#define CYREG_B1_P3_U1_PLD_IT4 0x40011690u\r
+#define CYREG_B1_P3_U1_PLD_IT5 0x40011694u\r
+#define CYREG_B1_P3_U1_PLD_IT6 0x40011698u\r
+#define CYREG_B1_P3_U1_PLD_IT7 0x4001169cu\r
+#define CYREG_B1_P3_U1_PLD_IT8 0x400116a0u\r
+#define CYREG_B1_P3_U1_PLD_IT9 0x400116a4u\r
+#define CYREG_B1_P3_U1_PLD_IT10 0x400116a8u\r
+#define CYREG_B1_P3_U1_PLD_IT11 0x400116acu\r
+#define CYREG_B1_P3_U1_PLD_ORT0 0x400116b0u\r
+#define CYREG_B1_P3_U1_PLD_ORT1 0x400116b2u\r
+#define CYREG_B1_P3_U1_PLD_ORT2 0x400116b4u\r
+#define CYREG_B1_P3_U1_PLD_ORT3 0x400116b6u\r
+#define CYREG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8u\r
+#define CYREG_B1_P3_U1_MC_CFG_XORFB 0x400116bau\r
+#define CYREG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bcu\r
+#define CYREG_B1_P3_U1_MC_CFG_BYPASS 0x400116beu\r
+#define CYREG_B1_P3_U1_CFG0 0x400116c0u\r
+#define CYREG_B1_P3_U1_CFG1 0x400116c1u\r
+#define CYREG_B1_P3_U1_CFG2 0x400116c2u\r
+#define CYREG_B1_P3_U1_CFG3 0x400116c3u\r
+#define CYREG_B1_P3_U1_CFG4 0x400116c4u\r
+#define CYREG_B1_P3_U1_CFG5 0x400116c5u\r
+#define CYREG_B1_P3_U1_CFG6 0x400116c6u\r
+#define CYREG_B1_P3_U1_CFG7 0x400116c7u\r
+#define CYREG_B1_P3_U1_CFG8 0x400116c8u\r
+#define CYREG_B1_P3_U1_CFG9 0x400116c9u\r
+#define CYREG_B1_P3_U1_CFG10 0x400116cau\r
+#define CYREG_B1_P3_U1_CFG11 0x400116cbu\r
+#define CYREG_B1_P3_U1_CFG12 0x400116ccu\r
+#define CYREG_B1_P3_U1_CFG13 0x400116cdu\r
+#define CYREG_B1_P3_U1_CFG14 0x400116ceu\r
+#define CYREG_B1_P3_U1_CFG15 0x400116cfu\r
+#define CYREG_B1_P3_U1_CFG16 0x400116d0u\r
+#define CYREG_B1_P3_U1_CFG17 0x400116d1u\r
+#define CYREG_B1_P3_U1_CFG18 0x400116d2u\r
+#define CYREG_B1_P3_U1_CFG19 0x400116d3u\r
+#define CYREG_B1_P3_U1_CFG20 0x400116d4u\r
+#define CYREG_B1_P3_U1_CFG21 0x400116d5u\r
+#define CYREG_B1_P3_U1_CFG22 0x400116d6u\r
+#define CYREG_B1_P3_U1_CFG23 0x400116d7u\r
+#define CYREG_B1_P3_U1_CFG24 0x400116d8u\r
+#define CYREG_B1_P3_U1_CFG25 0x400116d9u\r
+#define CYREG_B1_P3_U1_CFG26 0x400116dau\r
+#define CYREG_B1_P3_U1_CFG27 0x400116dbu\r
+#define CYREG_B1_P3_U1_CFG28 0x400116dcu\r
+#define CYREG_B1_P3_U1_CFG29 0x400116ddu\r
+#define CYREG_B1_P3_U1_CFG30 0x400116deu\r
+#define CYREG_B1_P3_U1_CFG31 0x400116dfu\r
+#define CYREG_B1_P3_U1_DCFG0 0x400116e0u\r
+#define CYREG_B1_P3_U1_DCFG1 0x400116e2u\r
+#define CYREG_B1_P3_U1_DCFG2 0x400116e4u\r
+#define CYREG_B1_P3_U1_DCFG3 0x400116e6u\r
+#define CYREG_B1_P3_U1_DCFG4 0x400116e8u\r
+#define CYREG_B1_P3_U1_DCFG5 0x400116eau\r
+#define CYREG_B1_P3_U1_DCFG6 0x400116ecu\r
+#define CYREG_B1_P3_U1_DCFG7 0x400116eeu\r
+#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700u\r
+#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B1_P4_BASE 0x40011800u\r
+#define CYDEV_UCFG_B1_P4_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800u\r
+#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070u\r
+#define CYREG_B1_P4_U0_PLD_IT0 0x40011800u\r
+#define CYREG_B1_P4_U0_PLD_IT1 0x40011804u\r
+#define CYREG_B1_P4_U0_PLD_IT2 0x40011808u\r
+#define CYREG_B1_P4_U0_PLD_IT3 0x4001180cu\r
+#define CYREG_B1_P4_U0_PLD_IT4 0x40011810u\r
+#define CYREG_B1_P4_U0_PLD_IT5 0x40011814u\r
+#define CYREG_B1_P4_U0_PLD_IT6 0x40011818u\r
+#define CYREG_B1_P4_U0_PLD_IT7 0x4001181cu\r
+#define CYREG_B1_P4_U0_PLD_IT8 0x40011820u\r
+#define CYREG_B1_P4_U0_PLD_IT9 0x40011824u\r
+#define CYREG_B1_P4_U0_PLD_IT10 0x40011828u\r
+#define CYREG_B1_P4_U0_PLD_IT11 0x4001182cu\r
+#define CYREG_B1_P4_U0_PLD_ORT0 0x40011830u\r
+#define CYREG_B1_P4_U0_PLD_ORT1 0x40011832u\r
+#define CYREG_B1_P4_U0_PLD_ORT2 0x40011834u\r
+#define CYREG_B1_P4_U0_PLD_ORT3 0x40011836u\r
+#define CYREG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838u\r
+#define CYREG_B1_P4_U0_MC_CFG_XORFB 0x4001183au\r
+#define CYREG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183cu\r
+#define CYREG_B1_P4_U0_MC_CFG_BYPASS 0x4001183eu\r
+#define CYREG_B1_P4_U0_CFG0 0x40011840u\r
+#define CYREG_B1_P4_U0_CFG1 0x40011841u\r
+#define CYREG_B1_P4_U0_CFG2 0x40011842u\r
+#define CYREG_B1_P4_U0_CFG3 0x40011843u\r
+#define CYREG_B1_P4_U0_CFG4 0x40011844u\r
+#define CYREG_B1_P4_U0_CFG5 0x40011845u\r
+#define CYREG_B1_P4_U0_CFG6 0x40011846u\r
+#define CYREG_B1_P4_U0_CFG7 0x40011847u\r
+#define CYREG_B1_P4_U0_CFG8 0x40011848u\r
+#define CYREG_B1_P4_U0_CFG9 0x40011849u\r
+#define CYREG_B1_P4_U0_CFG10 0x4001184au\r
+#define CYREG_B1_P4_U0_CFG11 0x4001184bu\r
+#define CYREG_B1_P4_U0_CFG12 0x4001184cu\r
+#define CYREG_B1_P4_U0_CFG13 0x4001184du\r
+#define CYREG_B1_P4_U0_CFG14 0x4001184eu\r
+#define CYREG_B1_P4_U0_CFG15 0x4001184fu\r
+#define CYREG_B1_P4_U0_CFG16 0x40011850u\r
+#define CYREG_B1_P4_U0_CFG17 0x40011851u\r
+#define CYREG_B1_P4_U0_CFG18 0x40011852u\r
+#define CYREG_B1_P4_U0_CFG19 0x40011853u\r
+#define CYREG_B1_P4_U0_CFG20 0x40011854u\r
+#define CYREG_B1_P4_U0_CFG21 0x40011855u\r
+#define CYREG_B1_P4_U0_CFG22 0x40011856u\r
+#define CYREG_B1_P4_U0_CFG23 0x40011857u\r
+#define CYREG_B1_P4_U0_CFG24 0x40011858u\r
+#define CYREG_B1_P4_U0_CFG25 0x40011859u\r
+#define CYREG_B1_P4_U0_CFG26 0x4001185au\r
+#define CYREG_B1_P4_U0_CFG27 0x4001185bu\r
+#define CYREG_B1_P4_U0_CFG28 0x4001185cu\r
+#define CYREG_B1_P4_U0_CFG29 0x4001185du\r
+#define CYREG_B1_P4_U0_CFG30 0x4001185eu\r
+#define CYREG_B1_P4_U0_CFG31 0x4001185fu\r
+#define CYREG_B1_P4_U0_DCFG0 0x40011860u\r
+#define CYREG_B1_P4_U0_DCFG1 0x40011862u\r
+#define CYREG_B1_P4_U0_DCFG2 0x40011864u\r
+#define CYREG_B1_P4_U0_DCFG3 0x40011866u\r
+#define CYREG_B1_P4_U0_DCFG4 0x40011868u\r
+#define CYREG_B1_P4_U0_DCFG5 0x4001186au\r
+#define CYREG_B1_P4_U0_DCFG6 0x4001186cu\r
+#define CYREG_B1_P4_U0_DCFG7 0x4001186eu\r
+#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880u\r
+#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070u\r
+#define CYREG_B1_P4_U1_PLD_IT0 0x40011880u\r
+#define CYREG_B1_P4_U1_PLD_IT1 0x40011884u\r
+#define CYREG_B1_P4_U1_PLD_IT2 0x40011888u\r
+#define CYREG_B1_P4_U1_PLD_IT3 0x4001188cu\r
+#define CYREG_B1_P4_U1_PLD_IT4 0x40011890u\r
+#define CYREG_B1_P4_U1_PLD_IT5 0x40011894u\r
+#define CYREG_B1_P4_U1_PLD_IT6 0x40011898u\r
+#define CYREG_B1_P4_U1_PLD_IT7 0x4001189cu\r
+#define CYREG_B1_P4_U1_PLD_IT8 0x400118a0u\r
+#define CYREG_B1_P4_U1_PLD_IT9 0x400118a4u\r
+#define CYREG_B1_P4_U1_PLD_IT10 0x400118a8u\r
+#define CYREG_B1_P4_U1_PLD_IT11 0x400118acu\r
+#define CYREG_B1_P4_U1_PLD_ORT0 0x400118b0u\r
+#define CYREG_B1_P4_U1_PLD_ORT1 0x400118b2u\r
+#define CYREG_B1_P4_U1_PLD_ORT2 0x400118b4u\r
+#define CYREG_B1_P4_U1_PLD_ORT3 0x400118b6u\r
+#define CYREG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8u\r
+#define CYREG_B1_P4_U1_MC_CFG_XORFB 0x400118bau\r
+#define CYREG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bcu\r
+#define CYREG_B1_P4_U1_MC_CFG_BYPASS 0x400118beu\r
+#define CYREG_B1_P4_U1_CFG0 0x400118c0u\r
+#define CYREG_B1_P4_U1_CFG1 0x400118c1u\r
+#define CYREG_B1_P4_U1_CFG2 0x400118c2u\r
+#define CYREG_B1_P4_U1_CFG3 0x400118c3u\r
+#define CYREG_B1_P4_U1_CFG4 0x400118c4u\r
+#define CYREG_B1_P4_U1_CFG5 0x400118c5u\r
+#define CYREG_B1_P4_U1_CFG6 0x400118c6u\r
+#define CYREG_B1_P4_U1_CFG7 0x400118c7u\r
+#define CYREG_B1_P4_U1_CFG8 0x400118c8u\r
+#define CYREG_B1_P4_U1_CFG9 0x400118c9u\r
+#define CYREG_B1_P4_U1_CFG10 0x400118cau\r
+#define CYREG_B1_P4_U1_CFG11 0x400118cbu\r
+#define CYREG_B1_P4_U1_CFG12 0x400118ccu\r
+#define CYREG_B1_P4_U1_CFG13 0x400118cdu\r
+#define CYREG_B1_P4_U1_CFG14 0x400118ceu\r
+#define CYREG_B1_P4_U1_CFG15 0x400118cfu\r
+#define CYREG_B1_P4_U1_CFG16 0x400118d0u\r
+#define CYREG_B1_P4_U1_CFG17 0x400118d1u\r
+#define CYREG_B1_P4_U1_CFG18 0x400118d2u\r
+#define CYREG_B1_P4_U1_CFG19 0x400118d3u\r
+#define CYREG_B1_P4_U1_CFG20 0x400118d4u\r
+#define CYREG_B1_P4_U1_CFG21 0x400118d5u\r
+#define CYREG_B1_P4_U1_CFG22 0x400118d6u\r
+#define CYREG_B1_P4_U1_CFG23 0x400118d7u\r
+#define CYREG_B1_P4_U1_CFG24 0x400118d8u\r
+#define CYREG_B1_P4_U1_CFG25 0x400118d9u\r
+#define CYREG_B1_P4_U1_CFG26 0x400118dau\r
+#define CYREG_B1_P4_U1_CFG27 0x400118dbu\r
+#define CYREG_B1_P4_U1_CFG28 0x400118dcu\r
+#define CYREG_B1_P4_U1_CFG29 0x400118ddu\r
+#define CYREG_B1_P4_U1_CFG30 0x400118deu\r
+#define CYREG_B1_P4_U1_CFG31 0x400118dfu\r
+#define CYREG_B1_P4_U1_DCFG0 0x400118e0u\r
+#define CYREG_B1_P4_U1_DCFG1 0x400118e2u\r
+#define CYREG_B1_P4_U1_DCFG2 0x400118e4u\r
+#define CYREG_B1_P4_U1_DCFG3 0x400118e6u\r
+#define CYREG_B1_P4_U1_DCFG4 0x400118e8u\r
+#define CYREG_B1_P4_U1_DCFG5 0x400118eau\r
+#define CYREG_B1_P4_U1_DCFG6 0x400118ecu\r
+#define CYREG_B1_P4_U1_DCFG7 0x400118eeu\r
+#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900u\r
+#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_B1_P5_BASE 0x40011a00u\r
+#define CYDEV_UCFG_B1_P5_SIZE 0x000001efu\r
+#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00u\r
+#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070u\r
+#define CYREG_B1_P5_U0_PLD_IT0 0x40011a00u\r
+#define CYREG_B1_P5_U0_PLD_IT1 0x40011a04u\r
+#define CYREG_B1_P5_U0_PLD_IT2 0x40011a08u\r
+#define CYREG_B1_P5_U0_PLD_IT3 0x40011a0cu\r
+#define CYREG_B1_P5_U0_PLD_IT4 0x40011a10u\r
+#define CYREG_B1_P5_U0_PLD_IT5 0x40011a14u\r
+#define CYREG_B1_P5_U0_PLD_IT6 0x40011a18u\r
+#define CYREG_B1_P5_U0_PLD_IT7 0x40011a1cu\r
+#define CYREG_B1_P5_U0_PLD_IT8 0x40011a20u\r
+#define CYREG_B1_P5_U0_PLD_IT9 0x40011a24u\r
+#define CYREG_B1_P5_U0_PLD_IT10 0x40011a28u\r
+#define CYREG_B1_P5_U0_PLD_IT11 0x40011a2cu\r
+#define CYREG_B1_P5_U0_PLD_ORT0 0x40011a30u\r
+#define CYREG_B1_P5_U0_PLD_ORT1 0x40011a32u\r
+#define CYREG_B1_P5_U0_PLD_ORT2 0x40011a34u\r
+#define CYREG_B1_P5_U0_PLD_ORT3 0x40011a36u\r
+#define CYREG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38u\r
+#define CYREG_B1_P5_U0_MC_CFG_XORFB 0x40011a3au\r
+#define CYREG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3cu\r
+#define CYREG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3eu\r
+#define CYREG_B1_P5_U0_CFG0 0x40011a40u\r
+#define CYREG_B1_P5_U0_CFG1 0x40011a41u\r
+#define CYREG_B1_P5_U0_CFG2 0x40011a42u\r
+#define CYREG_B1_P5_U0_CFG3 0x40011a43u\r
+#define CYREG_B1_P5_U0_CFG4 0x40011a44u\r
+#define CYREG_B1_P5_U0_CFG5 0x40011a45u\r
+#define CYREG_B1_P5_U0_CFG6 0x40011a46u\r
+#define CYREG_B1_P5_U0_CFG7 0x40011a47u\r
+#define CYREG_B1_P5_U0_CFG8 0x40011a48u\r
+#define CYREG_B1_P5_U0_CFG9 0x40011a49u\r
+#define CYREG_B1_P5_U0_CFG10 0x40011a4au\r
+#define CYREG_B1_P5_U0_CFG11 0x40011a4bu\r
+#define CYREG_B1_P5_U0_CFG12 0x40011a4cu\r
+#define CYREG_B1_P5_U0_CFG13 0x40011a4du\r
+#define CYREG_B1_P5_U0_CFG14 0x40011a4eu\r
+#define CYREG_B1_P5_U0_CFG15 0x40011a4fu\r
+#define CYREG_B1_P5_U0_CFG16 0x40011a50u\r
+#define CYREG_B1_P5_U0_CFG17 0x40011a51u\r
+#define CYREG_B1_P5_U0_CFG18 0x40011a52u\r
+#define CYREG_B1_P5_U0_CFG19 0x40011a53u\r
+#define CYREG_B1_P5_U0_CFG20 0x40011a54u\r
+#define CYREG_B1_P5_U0_CFG21 0x40011a55u\r
+#define CYREG_B1_P5_U0_CFG22 0x40011a56u\r
+#define CYREG_B1_P5_U0_CFG23 0x40011a57u\r
+#define CYREG_B1_P5_U0_CFG24 0x40011a58u\r
+#define CYREG_B1_P5_U0_CFG25 0x40011a59u\r
+#define CYREG_B1_P5_U0_CFG26 0x40011a5au\r
+#define CYREG_B1_P5_U0_CFG27 0x40011a5bu\r
+#define CYREG_B1_P5_U0_CFG28 0x40011a5cu\r
+#define CYREG_B1_P5_U0_CFG29 0x40011a5du\r
+#define CYREG_B1_P5_U0_CFG30 0x40011a5eu\r
+#define CYREG_B1_P5_U0_CFG31 0x40011a5fu\r
+#define CYREG_B1_P5_U0_DCFG0 0x40011a60u\r
+#define CYREG_B1_P5_U0_DCFG1 0x40011a62u\r
+#define CYREG_B1_P5_U0_DCFG2 0x40011a64u\r
+#define CYREG_B1_P5_U0_DCFG3 0x40011a66u\r
+#define CYREG_B1_P5_U0_DCFG4 0x40011a68u\r
+#define CYREG_B1_P5_U0_DCFG5 0x40011a6au\r
+#define CYREG_B1_P5_U0_DCFG6 0x40011a6cu\r
+#define CYREG_B1_P5_U0_DCFG7 0x40011a6eu\r
+#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80u\r
+#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070u\r
+#define CYREG_B1_P5_U1_PLD_IT0 0x40011a80u\r
+#define CYREG_B1_P5_U1_PLD_IT1 0x40011a84u\r
+#define CYREG_B1_P5_U1_PLD_IT2 0x40011a88u\r
+#define CYREG_B1_P5_U1_PLD_IT3 0x40011a8cu\r
+#define CYREG_B1_P5_U1_PLD_IT4 0x40011a90u\r
+#define CYREG_B1_P5_U1_PLD_IT5 0x40011a94u\r
+#define CYREG_B1_P5_U1_PLD_IT6 0x40011a98u\r
+#define CYREG_B1_P5_U1_PLD_IT7 0x40011a9cu\r
+#define CYREG_B1_P5_U1_PLD_IT8 0x40011aa0u\r
+#define CYREG_B1_P5_U1_PLD_IT9 0x40011aa4u\r
+#define CYREG_B1_P5_U1_PLD_IT10 0x40011aa8u\r
+#define CYREG_B1_P5_U1_PLD_IT11 0x40011aacu\r
+#define CYREG_B1_P5_U1_PLD_ORT0 0x40011ab0u\r
+#define CYREG_B1_P5_U1_PLD_ORT1 0x40011ab2u\r
+#define CYREG_B1_P5_U1_PLD_ORT2 0x40011ab4u\r
+#define CYREG_B1_P5_U1_PLD_ORT3 0x40011ab6u\r
+#define CYREG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8u\r
+#define CYREG_B1_P5_U1_MC_CFG_XORFB 0x40011abau\r
+#define CYREG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abcu\r
+#define CYREG_B1_P5_U1_MC_CFG_BYPASS 0x40011abeu\r
+#define CYREG_B1_P5_U1_CFG0 0x40011ac0u\r
+#define CYREG_B1_P5_U1_CFG1 0x40011ac1u\r
+#define CYREG_B1_P5_U1_CFG2 0x40011ac2u\r
+#define CYREG_B1_P5_U1_CFG3 0x40011ac3u\r
+#define CYREG_B1_P5_U1_CFG4 0x40011ac4u\r
+#define CYREG_B1_P5_U1_CFG5 0x40011ac5u\r
+#define CYREG_B1_P5_U1_CFG6 0x40011ac6u\r
+#define CYREG_B1_P5_U1_CFG7 0x40011ac7u\r
+#define CYREG_B1_P5_U1_CFG8 0x40011ac8u\r
+#define CYREG_B1_P5_U1_CFG9 0x40011ac9u\r
+#define CYREG_B1_P5_U1_CFG10 0x40011acau\r
+#define CYREG_B1_P5_U1_CFG11 0x40011acbu\r
+#define CYREG_B1_P5_U1_CFG12 0x40011accu\r
+#define CYREG_B1_P5_U1_CFG13 0x40011acdu\r
+#define CYREG_B1_P5_U1_CFG14 0x40011aceu\r
+#define CYREG_B1_P5_U1_CFG15 0x40011acfu\r
+#define CYREG_B1_P5_U1_CFG16 0x40011ad0u\r
+#define CYREG_B1_P5_U1_CFG17 0x40011ad1u\r
+#define CYREG_B1_P5_U1_CFG18 0x40011ad2u\r
+#define CYREG_B1_P5_U1_CFG19 0x40011ad3u\r
+#define CYREG_B1_P5_U1_CFG20 0x40011ad4u\r
+#define CYREG_B1_P5_U1_CFG21 0x40011ad5u\r
+#define CYREG_B1_P5_U1_CFG22 0x40011ad6u\r
+#define CYREG_B1_P5_U1_CFG23 0x40011ad7u\r
+#define CYREG_B1_P5_U1_CFG24 0x40011ad8u\r
+#define CYREG_B1_P5_U1_CFG25 0x40011ad9u\r
+#define CYREG_B1_P5_U1_CFG26 0x40011adau\r
+#define CYREG_B1_P5_U1_CFG27 0x40011adbu\r
+#define CYREG_B1_P5_U1_CFG28 0x40011adcu\r
+#define CYREG_B1_P5_U1_CFG29 0x40011addu\r
+#define CYREG_B1_P5_U1_CFG30 0x40011adeu\r
+#define CYREG_B1_P5_U1_CFG31 0x40011adfu\r
+#define CYREG_B1_P5_U1_DCFG0 0x40011ae0u\r
+#define CYREG_B1_P5_U1_DCFG1 0x40011ae2u\r
+#define CYREG_B1_P5_U1_DCFG2 0x40011ae4u\r
+#define CYREG_B1_P5_U1_DCFG3 0x40011ae6u\r
+#define CYREG_B1_P5_U1_DCFG4 0x40011ae8u\r
+#define CYREG_B1_P5_U1_DCFG5 0x40011aeau\r
+#define CYREG_B1_P5_U1_DCFG6 0x40011aecu\r
+#define CYREG_B1_P5_U1_DCFG7 0x40011aeeu\r
+#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00u\r
+#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI0_BASE 0x40014000u\r
+#define CYDEV_UCFG_DSI0_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI1_BASE 0x40014100u\r
+#define CYDEV_UCFG_DSI1_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI2_BASE 0x40014200u\r
+#define CYDEV_UCFG_DSI2_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI3_BASE 0x40014300u\r
+#define CYDEV_UCFG_DSI3_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI4_BASE 0x40014400u\r
+#define CYDEV_UCFG_DSI4_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI5_BASE 0x40014500u\r
+#define CYDEV_UCFG_DSI5_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI6_BASE 0x40014600u\r
+#define CYDEV_UCFG_DSI6_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI7_BASE 0x40014700u\r
+#define CYDEV_UCFG_DSI7_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI8_BASE 0x40014800u\r
+#define CYDEV_UCFG_DSI8_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI9_BASE 0x40014900u\r
+#define CYDEV_UCFG_DSI9_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI12_BASE 0x40014c00u\r
+#define CYDEV_UCFG_DSI12_SIZE 0x000000efu\r
+#define CYDEV_UCFG_DSI13_BASE 0x40014d00u\r
+#define CYDEV_UCFG_DSI13_SIZE 0x000000efu\r
+#define CYDEV_UCFG_BCTL0_BASE 0x40015000u\r
+#define CYDEV_UCFG_BCTL0_SIZE 0x00000010u\r
+#define CYREG_BCTL0_MDCLK_EN 0x40015000u\r
+#define CYREG_BCTL0_MBCLK_EN 0x40015001u\r
+#define CYREG_BCTL0_WAIT_CFG 0x40015002u\r
+#define CYREG_BCTL0_BANK_CTL 0x40015003u\r
+#define CYREG_BCTL0_UDB_TEST_3 0x40015007u\r
+#define CYREG_BCTL0_DCLK_EN0 0x40015008u\r
+#define CYREG_BCTL0_BCLK_EN0 0x40015009u\r
+#define CYREG_BCTL0_DCLK_EN1 0x4001500au\r
+#define CYREG_BCTL0_BCLK_EN1 0x4001500bu\r
+#define CYREG_BCTL0_DCLK_EN2 0x4001500cu\r
+#define CYREG_BCTL0_BCLK_EN2 0x4001500du\r
+#define CYREG_BCTL0_DCLK_EN3 0x4001500eu\r
+#define CYREG_BCTL0_BCLK_EN3 0x4001500fu\r
+#define CYDEV_UCFG_BCTL1_BASE 0x40015010u\r
+#define CYDEV_UCFG_BCTL1_SIZE 0x00000010u\r
+#define CYREG_BCTL1_MDCLK_EN 0x40015010u\r
+#define CYREG_BCTL1_MBCLK_EN 0x40015011u\r
+#define CYREG_BCTL1_WAIT_CFG 0x40015012u\r
+#define CYREG_BCTL1_BANK_CTL 0x40015013u\r
+#define CYREG_BCTL1_UDB_TEST_3 0x40015017u\r
+#define CYREG_BCTL1_DCLK_EN0 0x40015018u\r
+#define CYREG_BCTL1_BCLK_EN0 0x40015019u\r
+#define CYREG_BCTL1_DCLK_EN1 0x4001501au\r
+#define CYREG_BCTL1_BCLK_EN1 0x4001501bu\r
+#define CYREG_BCTL1_DCLK_EN2 0x4001501cu\r
+#define CYREG_BCTL1_BCLK_EN2 0x4001501du\r
+#define CYREG_BCTL1_DCLK_EN3 0x4001501eu\r
+#define CYREG_BCTL1_BCLK_EN3 0x4001501fu\r
+#define CYDEV_IDMUX_BASE 0x40015100u\r
+#define CYDEV_IDMUX_SIZE 0x00000016u\r
+#define CYREG_IDMUX_IRQ_CTL0 0x40015100u\r
+#define CYREG_IDMUX_IRQ_CTL1 0x40015101u\r
+#define CYREG_IDMUX_IRQ_CTL2 0x40015102u\r
+#define CYREG_IDMUX_IRQ_CTL3 0x40015103u\r
+#define CYREG_IDMUX_IRQ_CTL4 0x40015104u\r
+#define CYREG_IDMUX_IRQ_CTL5 0x40015105u\r
+#define CYREG_IDMUX_IRQ_CTL6 0x40015106u\r
+#define CYREG_IDMUX_IRQ_CTL7 0x40015107u\r
+#define CYREG_IDMUX_DRQ_CTL0 0x40015110u\r
+#define CYREG_IDMUX_DRQ_CTL1 0x40015111u\r
+#define CYREG_IDMUX_DRQ_CTL2 0x40015112u\r
+#define CYREG_IDMUX_DRQ_CTL3 0x40015113u\r
+#define CYREG_IDMUX_DRQ_CTL4 0x40015114u\r
+#define CYREG_IDMUX_DRQ_CTL5 0x40015115u\r
+#define CYDEV_CACHERAM_BASE 0x40030000u\r
+#define CYDEV_CACHERAM_SIZE 0x00000400u\r
+#define CYREG_CACHERAM_DATA_MBASE 0x40030000u\r
+#define CYREG_CACHERAM_DATA_MSIZE 0x00000400u\r
+#define CYDEV_SFR_BASE 0x40050100u\r
+#define CYDEV_SFR_SIZE 0x000000fbu\r
+#define CYREG_SFR_GPIO0 0x40050180u\r
+#define CYREG_SFR_GPIRD0 0x40050189u\r
+#define CYREG_SFR_GPIO0_SEL 0x4005018au\r
+#define CYREG_SFR_GPIO1 0x40050190u\r
+#define CYREG_SFR_GPIRD1 0x40050191u\r
+#define CYREG_SFR_GPIO2 0x40050198u\r
+#define CYREG_SFR_GPIRD2 0x40050199u\r
+#define CYREG_SFR_GPIO2_SEL 0x4005019au\r
+#define CYREG_SFR_GPIO1_SEL 0x400501a2u\r
+#define CYREG_SFR_GPIO3 0x400501b0u\r
+#define CYREG_SFR_GPIRD3 0x400501b1u\r
+#define CYREG_SFR_GPIO3_SEL 0x400501b2u\r
+#define CYREG_SFR_GPIO4 0x400501c0u\r
+#define CYREG_SFR_GPIRD4 0x400501c1u\r
+#define CYREG_SFR_GPIO4_SEL 0x400501c2u\r
+#define CYREG_SFR_GPIO5 0x400501c8u\r
+#define CYREG_SFR_GPIRD5 0x400501c9u\r
+#define CYREG_SFR_GPIO5_SEL 0x400501cau\r
+#define CYREG_SFR_GPIO6 0x400501d8u\r
+#define CYREG_SFR_GPIRD6 0x400501d9u\r
+#define CYREG_SFR_GPIO6_SEL 0x400501dau\r
+#define CYREG_SFR_GPIO12 0x400501e8u\r
+#define CYREG_SFR_GPIRD12 0x400501e9u\r
+#define CYREG_SFR_GPIO12_SEL 0x400501f2u\r
+#define CYREG_SFR_GPIO15 0x400501f8u\r
+#define CYREG_SFR_GPIRD15 0x400501f9u\r
+#define CYREG_SFR_GPIO15_SEL 0x400501fau\r
+#define CYDEV_P3BA_BASE 0x40050300u\r
+#define CYDEV_P3BA_SIZE 0x0000002bu\r
+#define CYREG_P3BA_Y_START 0x40050300u\r
+#define CYREG_P3BA_YROLL 0x40050301u\r
+#define CYREG_P3BA_YCFG 0x40050302u\r
+#define CYREG_P3BA_X_START1 0x40050303u\r
+#define CYREG_P3BA_X_START2 0x40050304u\r
+#define CYREG_P3BA_XROLL1 0x40050305u\r
+#define CYREG_P3BA_XROLL2 0x40050306u\r
+#define CYREG_P3BA_XINC 0x40050307u\r
+#define CYREG_P3BA_XCFG 0x40050308u\r
+#define CYREG_P3BA_OFFSETADDR1 0x40050309u\r
+#define CYREG_P3BA_OFFSETADDR2 0x4005030au\r
+#define CYREG_P3BA_OFFSETADDR3 0x4005030bu\r
+#define CYREG_P3BA_ABSADDR1 0x4005030cu\r
+#define CYREG_P3BA_ABSADDR2 0x4005030du\r
+#define CYREG_P3BA_ABSADDR3 0x4005030eu\r
+#define CYREG_P3BA_ABSADDR4 0x4005030fu\r
+#define CYREG_P3BA_DATCFG1 0x40050310u\r
+#define CYREG_P3BA_DATCFG2 0x40050311u\r
+#define CYREG_P3BA_CMP_RSLT1 0x40050314u\r
+#define CYREG_P3BA_CMP_RSLT2 0x40050315u\r
+#define CYREG_P3BA_CMP_RSLT3 0x40050316u\r
+#define CYREG_P3BA_CMP_RSLT4 0x40050317u\r
+#define CYREG_P3BA_DATA_REG1 0x40050318u\r
+#define CYREG_P3BA_DATA_REG2 0x40050319u\r
+#define CYREG_P3BA_DATA_REG3 0x4005031au\r
+#define CYREG_P3BA_DATA_REG4 0x4005031bu\r
+#define CYREG_P3BA_EXP_DATA1 0x4005031cu\r
+#define CYREG_P3BA_EXP_DATA2 0x4005031du\r
+#define CYREG_P3BA_EXP_DATA3 0x4005031eu\r
+#define CYREG_P3BA_EXP_DATA4 0x4005031fu\r
+#define CYREG_P3BA_MSTR_HRDATA1 0x40050320u\r
+#define CYREG_P3BA_MSTR_HRDATA2 0x40050321u\r
+#define CYREG_P3BA_MSTR_HRDATA3 0x40050322u\r
+#define CYREG_P3BA_MSTR_HRDATA4 0x40050323u\r
+#define CYREG_P3BA_BIST_EN 0x40050324u\r
+#define CYREG_P3BA_PHUB_MASTER_SSR 0x40050325u\r
+#define CYREG_P3BA_SEQCFG1 0x40050326u\r
+#define CYREG_P3BA_SEQCFG2 0x40050327u\r
+#define CYREG_P3BA_Y_CURR 0x40050328u\r
+#define CYREG_P3BA_X_CURR1 0x40050329u\r
+#define CYREG_P3BA_X_CURR2 0x4005032au\r
+#define CYDEV_PANTHER_BASE 0x40080000u\r
+#define CYDEV_PANTHER_SIZE 0x00000020u\r
+#define CYREG_PANTHER_STCALIB_CFG 0x40080000u\r
+#define CYREG_PANTHER_WAITPIPE 0x40080004u\r
+#define CYREG_PANTHER_TRACE_CFG 0x40080008u\r
+#define CYREG_PANTHER_DBG_CFG 0x4008000cu\r
+#define CYREG_PANTHER_CM3_LCKRST_STAT 0x40080018u\r
+#define CYREG_PANTHER_DEVICE_ID 0x4008001cu\r
+#define CYDEV_FLSECC_BASE 0x48000000u\r
+#define CYDEV_FLSECC_SIZE 0x00008000u\r
+#define CYREG_FLSECC_DATA_MBASE 0x48000000u\r
+#define CYREG_FLSECC_DATA_MSIZE 0x00008000u\r
+#define CYDEV_FLSHID_BASE 0x49000000u\r
+#define CYDEV_FLSHID_SIZE 0x00000200u\r
+#define CYREG_FLSHID_RSVD_MBASE 0x49000000u\r
+#define CYREG_FLSHID_RSVD_MSIZE 0x00000080u\r
+#define CYREG_FLSHID_CUST_MDATA_MBASE 0x49000080u\r
+#define CYREG_FLSHID_CUST_MDATA_MSIZE 0x00000080u\r
+#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100u\r
+#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040u\r
+#define CYREG_FLSHID_CUST_TABLES_Y_LOC 0x49000100u\r
+#define CYREG_FLSHID_CUST_TABLES_X_LOC 0x49000101u\r
+#define CYREG_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102u\r
+#define CYREG_FLSHID_CUST_TABLES_LOT_LSB 0x49000103u\r
+#define CYREG_FLSHID_CUST_TABLES_LOT_MSB 0x49000104u\r
+#define CYREG_FLSHID_CUST_TABLES_WRK_WK 0x49000105u\r
+#define CYREG_FLSHID_CUST_TABLES_FAB_YR 0x49000106u\r
+#define CYREG_FLSHID_CUST_TABLES_MINOR 0x49000107u\r
+#define CYREG_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108u\r
+#define CYREG_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109u\r
+#define CYREG_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010au\r
+#define CYREG_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010bu\r
+#define CYREG_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010cu\r
+#define CYREG_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010du\r
+#define CYREG_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010eu\r
+#define CYREG_FLSHID_CUST_TABLES_IMO_USB 0x4900010fu\r
+#define CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110u\r
+#define CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111u\r
+#define CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112u\r
+#define CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113u\r
+#define CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114u\r
+#define CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115u\r
+#define CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116u\r
+#define CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117u\r
+#define CYREG_FLSHID_CUST_TABLES_DEC_M1 0x49000118u\r
+#define CYREG_FLSHID_CUST_TABLES_DEC_M2 0x49000119u\r
+#define CYREG_FLSHID_CUST_TABLES_DEC_M3 0x4900011au\r
+#define CYREG_FLSHID_CUST_TABLES_DEC_M4 0x4900011bu\r
+#define CYREG_FLSHID_CUST_TABLES_DEC_M5 0x4900011cu\r
+#define CYREG_FLSHID_CUST_TABLES_DEC_M6 0x4900011du\r
+#define CYREG_FLSHID_CUST_TABLES_DEC_M7 0x4900011eu\r
+#define CYREG_FLSHID_CUST_TABLES_DEC_M8 0x4900011fu\r
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M1 0x49000120u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M2 0x49000121u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M3 0x49000122u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M4 0x49000123u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M5 0x49000124u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M6 0x49000125u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M7 0x49000126u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC0_M8 0x49000127u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M1 0x49000128u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M2 0x49000129u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M3 0x4900012au\r
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M4 0x4900012bu\r
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M5 0x4900012cu\r
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M6 0x4900012du\r
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M7 0x4900012eu\r
+#define CYREG_FLSHID_CUST_TABLES_DAC2_M8 0x4900012fu\r
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M1 0x49000130u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M2 0x49000131u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M3 0x49000132u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M4 0x49000133u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M5 0x49000134u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M6 0x49000135u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M7 0x49000136u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC1_M8 0x49000137u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M1 0x49000138u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M2 0x49000139u\r
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M3 0x4900013au\r
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M4 0x4900013bu\r
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M5 0x4900013cu\r
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M6 0x4900013du\r
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M7 0x4900013eu\r
+#define CYREG_FLSHID_CUST_TABLES_DAC3_M8 0x4900013fu\r
+#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180u\r
+#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080u\r
+#define CYREG_FLSHID_MFG_CFG_IMO_TR1 0x49000188u\r
+#define CYREG_FLSHID_MFG_CFG_CMP0_TR0 0x490001acu\r
+#define CYREG_FLSHID_MFG_CFG_CMP1_TR0 0x490001aeu\r
+#define CYREG_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0u\r
+#define CYREG_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2u\r
+#define CYREG_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4u\r
+#define CYREG_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6u\r
+#define CYREG_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8u\r
+#define CYREG_FLSHID_MFG_CFG_CMP3_TR1 0x490001bau\r
+#define CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ceu\r
+#define CYDEV_EXTMEM_BASE 0x60000000u\r
+#define CYDEV_EXTMEM_SIZE 0x00800000u\r
+#define CYREG_EXTMEM_DATA_MBASE 0x60000000u\r
+#define CYREG_EXTMEM_DATA_MSIZE 0x00800000u\r
+#define CYDEV_ITM_BASE 0xe0000000u\r
+#define CYDEV_ITM_SIZE 0x00001000u\r
+#define CYREG_ITM_TRACE_EN 0xe0000e00u\r
+#define CYREG_ITM_TRACE_PRIVILEGE 0xe0000e40u\r
+#define CYREG_ITM_TRACE_CTRL 0xe0000e80u\r
+#define CYREG_ITM_LOCK_ACCESS 0xe0000fb0u\r
+#define CYREG_ITM_LOCK_STATUS 0xe0000fb4u\r
+#define CYREG_ITM_PID4 0xe0000fd0u\r
+#define CYREG_ITM_PID5 0xe0000fd4u\r
+#define CYREG_ITM_PID6 0xe0000fd8u\r
+#define CYREG_ITM_PID7 0xe0000fdcu\r
+#define CYREG_ITM_PID0 0xe0000fe0u\r
+#define CYREG_ITM_PID1 0xe0000fe4u\r
+#define CYREG_ITM_PID2 0xe0000fe8u\r
+#define CYREG_ITM_PID3 0xe0000fecu\r
+#define CYREG_ITM_CID0 0xe0000ff0u\r
+#define CYREG_ITM_CID1 0xe0000ff4u\r
+#define CYREG_ITM_CID2 0xe0000ff8u\r
+#define CYREG_ITM_CID3 0xe0000ffcu\r
+#define CYDEV_DWT_BASE 0xe0001000u\r
+#define CYDEV_DWT_SIZE 0x0000005cu\r
+#define CYREG_DWT_CTRL 0xe0001000u\r
+#define CYREG_DWT_CYCLE_COUNT 0xe0001004u\r
+#define CYREG_DWT_CPI_COUNT 0xe0001008u\r
+#define CYREG_DWT_EXC_OVHD_COUNT 0xe000100cu\r
+#define CYREG_DWT_SLEEP_COUNT 0xe0001010u\r
+#define CYREG_DWT_LSU_COUNT 0xe0001014u\r
+#define CYREG_DWT_FOLD_COUNT 0xe0001018u\r
+#define CYREG_DWT_PC_SAMPLE 0xe000101cu\r
+#define CYREG_DWT_COMP_0 0xe0001020u\r
+#define CYREG_DWT_MASK_0 0xe0001024u\r
+#define CYREG_DWT_FUNCTION_0 0xe0001028u\r
+#define CYREG_DWT_COMP_1 0xe0001030u\r
+#define CYREG_DWT_MASK_1 0xe0001034u\r
+#define CYREG_DWT_FUNCTION_1 0xe0001038u\r
+#define CYREG_DWT_COMP_2 0xe0001040u\r
+#define CYREG_DWT_MASK_2 0xe0001044u\r
+#define CYREG_DWT_FUNCTION_2 0xe0001048u\r
+#define CYREG_DWT_COMP_3 0xe0001050u\r
+#define CYREG_DWT_MASK_3 0xe0001054u\r
+#define CYREG_DWT_FUNCTION_3 0xe0001058u\r
+#define CYDEV_FPB_BASE 0xe0002000u\r
+#define CYDEV_FPB_SIZE 0x00001000u\r
+#define CYREG_FPB_CTRL 0xe0002000u\r
+#define CYREG_FPB_REMAP 0xe0002004u\r
+#define CYREG_FPB_FP_COMP_0 0xe0002008u\r
+#define CYREG_FPB_FP_COMP_1 0xe000200cu\r
+#define CYREG_FPB_FP_COMP_2 0xe0002010u\r
+#define CYREG_FPB_FP_COMP_3 0xe0002014u\r
+#define CYREG_FPB_FP_COMP_4 0xe0002018u\r
+#define CYREG_FPB_FP_COMP_5 0xe000201cu\r
+#define CYREG_FPB_FP_COMP_6 0xe0002020u\r
+#define CYREG_FPB_FP_COMP_7 0xe0002024u\r
+#define CYREG_FPB_PID4 0xe0002fd0u\r
+#define CYREG_FPB_PID5 0xe0002fd4u\r
+#define CYREG_FPB_PID6 0xe0002fd8u\r
+#define CYREG_FPB_PID7 0xe0002fdcu\r
+#define CYREG_FPB_PID0 0xe0002fe0u\r
+#define CYREG_FPB_PID1 0xe0002fe4u\r
+#define CYREG_FPB_PID2 0xe0002fe8u\r
+#define CYREG_FPB_PID3 0xe0002fecu\r
+#define CYREG_FPB_CID0 0xe0002ff0u\r
+#define CYREG_FPB_CID1 0xe0002ff4u\r
+#define CYREG_FPB_CID2 0xe0002ff8u\r
+#define CYREG_FPB_CID3 0xe0002ffcu\r
+#define CYDEV_NVIC_BASE 0xe000e000u\r
+#define CYDEV_NVIC_SIZE 0x00000d3cu\r
+#define CYREG_NVIC_INT_CTL_TYPE 0xe000e004u\r
+#define CYREG_NVIC_SYSTICK_CTL 0xe000e010u\r
+#define CYREG_NVIC_SYSTICK_RELOAD 0xe000e014u\r
+#define CYREG_NVIC_SYSTICK_CURRENT 0xe000e018u\r
+#define CYREG_NVIC_SYSTICK_CAL 0xe000e01cu\r
+#define CYREG_NVIC_SETENA0 0xe000e100u\r
+#define CYREG_NVIC_CLRENA0 0xe000e180u\r
+#define CYREG_NVIC_SETPEND0 0xe000e200u\r
+#define CYREG_NVIC_CLRPEND0 0xe000e280u\r
+#define CYREG_NVIC_ACTIVE0 0xe000e300u\r
+#define CYREG_NVIC_PRI_0 0xe000e400u\r
+#define CYREG_NVIC_PRI_1 0xe000e401u\r
+#define CYREG_NVIC_PRI_2 0xe000e402u\r
+#define CYREG_NVIC_PRI_3 0xe000e403u\r
+#define CYREG_NVIC_PRI_4 0xe000e404u\r
+#define CYREG_NVIC_PRI_5 0xe000e405u\r
+#define CYREG_NVIC_PRI_6 0xe000e406u\r
+#define CYREG_NVIC_PRI_7 0xe000e407u\r
+#define CYREG_NVIC_PRI_8 0xe000e408u\r
+#define CYREG_NVIC_PRI_9 0xe000e409u\r
+#define CYREG_NVIC_PRI_10 0xe000e40au\r
+#define CYREG_NVIC_PRI_11 0xe000e40bu\r
+#define CYREG_NVIC_PRI_12 0xe000e40cu\r
+#define CYREG_NVIC_PRI_13 0xe000e40du\r
+#define CYREG_NVIC_PRI_14 0xe000e40eu\r
+#define CYREG_NVIC_PRI_15 0xe000e40fu\r
+#define CYREG_NVIC_PRI_16 0xe000e410u\r
+#define CYREG_NVIC_PRI_17 0xe000e411u\r
+#define CYREG_NVIC_PRI_18 0xe000e412u\r
+#define CYREG_NVIC_PRI_19 0xe000e413u\r
+#define CYREG_NVIC_PRI_20 0xe000e414u\r
+#define CYREG_NVIC_PRI_21 0xe000e415u\r
+#define CYREG_NVIC_PRI_22 0xe000e416u\r
+#define CYREG_NVIC_PRI_23 0xe000e417u\r
+#define CYREG_NVIC_PRI_24 0xe000e418u\r
+#define CYREG_NVIC_PRI_25 0xe000e419u\r
+#define CYREG_NVIC_PRI_26 0xe000e41au\r
+#define CYREG_NVIC_PRI_27 0xe000e41bu\r
+#define CYREG_NVIC_PRI_28 0xe000e41cu\r
+#define CYREG_NVIC_PRI_29 0xe000e41du\r
+#define CYREG_NVIC_PRI_30 0xe000e41eu\r
+#define CYREG_NVIC_PRI_31 0xe000e41fu\r
+#define CYREG_NVIC_CPUID_BASE 0xe000ed00u\r
+#define CYREG_NVIC_INTR_CTRL_STATE 0xe000ed04u\r
+#define CYREG_NVIC_VECT_OFFSET 0xe000ed08u\r
+#define CYREG_NVIC_APPLN_INTR 0xe000ed0cu\r
+#define CYREG_NVIC_SYSTEM_CONTROL 0xe000ed10u\r
+#define CYREG_NVIC_CFG_CONTROL 0xe000ed14u\r
+#define CYREG_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18u\r
+#define CYREG_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1cu\r
+#define CYREG_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20u\r
+#define CYREG_NVIC_SYS_HANDLER_CSR 0xe000ed24u\r
+#define CYREG_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28u\r
+#define CYREG_NVIC_BUS_FAULT_STATUS 0xe000ed29u\r
+#define CYREG_NVIC_USAGE_FAULT_STATUS 0xe000ed2au\r
+#define CYREG_NVIC_HARD_FAULT_STATUS 0xe000ed2cu\r
+#define CYREG_NVIC_DEBUG_FAULT_STATUS 0xe000ed30u\r
+#define CYREG_NVIC_MEMMAN_FAULT_ADD 0xe000ed34u\r
+#define CYREG_NVIC_BUS_FAULT_ADD 0xe000ed38u\r
+#define CYDEV_CORE_DBG_BASE 0xe000edf0u\r
+#define CYDEV_CORE_DBG_SIZE 0x00000010u\r
+#define CYREG_CORE_DBG_DBG_HLT_CS 0xe000edf0u\r
+#define CYREG_CORE_DBG_DBG_REG_SEL 0xe000edf4u\r
+#define CYREG_CORE_DBG_DBG_REG_DATA 0xe000edf8u\r
+#define CYREG_CORE_DBG_EXC_MON_CTL 0xe000edfcu\r
+#define CYDEV_TPIU_BASE 0xe0040000u\r
+#define CYDEV_TPIU_SIZE 0x00001000u\r
+#define CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000u\r
+#define CYREG_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004u\r
+#define CYREG_TPIU_ASYNC_CLK_PRESCALER 0xe0040010u\r
+#define CYREG_TPIU_PROTOCOL 0xe00400f0u\r
+#define CYREG_TPIU_FORM_FLUSH_STAT 0xe0040300u\r
+#define CYREG_TPIU_FORM_FLUSH_CTRL 0xe0040304u\r
+#define CYREG_TPIU_TRIGGER 0xe0040ee8u\r
+#define CYREG_TPIU_ITETMDATA 0xe0040eecu\r
+#define CYREG_TPIU_ITATBCTR2 0xe0040ef0u\r
+#define CYREG_TPIU_ITATBCTR0 0xe0040ef8u\r
+#define CYREG_TPIU_ITITMDATA 0xe0040efcu\r
+#define CYREG_TPIU_ITCTRL 0xe0040f00u\r
+#define CYREG_TPIU_DEVID 0xe0040fc8u\r
+#define CYREG_TPIU_DEVTYPE 0xe0040fccu\r
+#define CYREG_TPIU_PID4 0xe0040fd0u\r
+#define CYREG_TPIU_PID5 0xe0040fd4u\r
+#define CYREG_TPIU_PID6 0xe0040fd8u\r
+#define CYREG_TPIU_PID7 0xe0040fdcu\r
+#define CYREG_TPIU_PID0 0xe0040fe0u\r
+#define CYREG_TPIU_PID1 0xe0040fe4u\r
+#define CYREG_TPIU_PID2 0xe0040fe8u\r
+#define CYREG_TPIU_PID3 0xe0040fecu\r
+#define CYREG_TPIU_CID0 0xe0040ff0u\r
+#define CYREG_TPIU_CID1 0xe0040ff4u\r
+#define CYREG_TPIU_CID2 0xe0040ff8u\r
+#define CYREG_TPIU_CID3 0xe0040ffcu\r
+#define CYDEV_ETM_BASE 0xe0041000u\r
+#define CYDEV_ETM_SIZE 0x00001000u\r
+#define CYREG_ETM_CTL 0xe0041000u\r
+#define CYREG_ETM_CFG_CODE 0xe0041004u\r
+#define CYREG_ETM_TRIG_EVENT 0xe0041008u\r
+#define CYREG_ETM_STATUS 0xe0041010u\r
+#define CYREG_ETM_SYS_CFG 0xe0041014u\r
+#define CYREG_ETM_TRACE_ENB_EVENT 0xe0041020u\r
+#define CYREG_ETM_TRACE_EN_CTRL1 0xe0041024u\r
+#define CYREG_ETM_FIFOFULL_LEVEL 0xe004102cu\r
+#define CYREG_ETM_SYNC_FREQ 0xe00411e0u\r
+#define CYREG_ETM_ETM_ID 0xe00411e4u\r
+#define CYREG_ETM_CFG_CODE_EXT 0xe00411e8u\r
+#define CYREG_ETM_TR_SS_EMBICE_CTRL 0xe00411f0u\r
+#define CYREG_ETM_CS_TRACE_ID 0xe0041200u\r
+#define CYREG_ETM_OS_LOCK_ACCESS 0xe0041300u\r
+#define CYREG_ETM_OS_LOCK_STATUS 0xe0041304u\r
+#define CYREG_ETM_PDSR 0xe0041314u\r
+#define CYREG_ETM_ITMISCIN 0xe0041ee0u\r
+#define CYREG_ETM_ITTRIGOUT 0xe0041ee8u\r
+#define CYREG_ETM_ITATBCTR2 0xe0041ef0u\r
+#define CYREG_ETM_ITATBCTR0 0xe0041ef8u\r
+#define CYREG_ETM_INT_MODE_CTRL 0xe0041f00u\r
+#define CYREG_ETM_CLM_TAG_SET 0xe0041fa0u\r
+#define CYREG_ETM_CLM_TAG_CLR 0xe0041fa4u\r
+#define CYREG_ETM_LOCK_ACCESS 0xe0041fb0u\r
+#define CYREG_ETM_LOCK_STATUS 0xe0041fb4u\r
+#define CYREG_ETM_AUTH_STATUS 0xe0041fb8u\r
+#define CYREG_ETM_DEV_TYPE 0xe0041fccu\r
+#define CYREG_ETM_PID4 0xe0041fd0u\r
+#define CYREG_ETM_PID5 0xe0041fd4u\r
+#define CYREG_ETM_PID6 0xe0041fd8u\r
+#define CYREG_ETM_PID7 0xe0041fdcu\r
+#define CYREG_ETM_PID0 0xe0041fe0u\r
+#define CYREG_ETM_PID1 0xe0041fe4u\r
+#define CYREG_ETM_PID2 0xe0041fe8u\r
+#define CYREG_ETM_PID3 0xe0041fecu\r
+#define CYREG_ETM_CID0 0xe0041ff0u\r
+#define CYREG_ETM_CID1 0xe0041ff4u\r
+#define CYREG_ETM_CID2 0xe0041ff8u\r
+#define CYREG_ETM_CID3 0xe0041ffcu\r
+#define CYDEV_ROM_TABLE_BASE 0xe00ff000u\r
+#define CYDEV_ROM_TABLE_SIZE 0x00001000u\r
+#define CYREG_ROM_TABLE_NVIC 0xe00ff000u\r
+#define CYREG_ROM_TABLE_DWT 0xe00ff004u\r
+#define CYREG_ROM_TABLE_FPB 0xe00ff008u\r
+#define CYREG_ROM_TABLE_ITM 0xe00ff00cu\r
+#define CYREG_ROM_TABLE_TPIU 0xe00ff010u\r
+#define CYREG_ROM_TABLE_ETM 0xe00ff014u\r
+#define CYREG_ROM_TABLE_END 0xe00ff018u\r
+#define CYREG_ROM_TABLE_MEMTYPE 0xe00fffccu\r
+#define CYREG_ROM_TABLE_PID4 0xe00fffd0u\r
+#define CYREG_ROM_TABLE_PID5 0xe00fffd4u\r
+#define CYREG_ROM_TABLE_PID6 0xe00fffd8u\r
+#define CYREG_ROM_TABLE_PID7 0xe00fffdcu\r
+#define CYREG_ROM_TABLE_PID0 0xe00fffe0u\r
+#define CYREG_ROM_TABLE_PID1 0xe00fffe4u\r
+#define CYREG_ROM_TABLE_PID2 0xe00fffe8u\r
+#define CYREG_ROM_TABLE_PID3 0xe00fffecu\r
+#define CYREG_ROM_TABLE_CID0 0xe00ffff0u\r
+#define CYREG_ROM_TABLE_CID1 0xe00ffff4u\r
+#define CYREG_ROM_TABLE_CID2 0xe00ffff8u\r
+#define CYREG_ROM_TABLE_CID3 0xe00ffffcu\r
+#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE\r
+#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE\r
+#define CYDEV_FLS_SECTOR_SIZE 0x00010000u\r
+#define CYDEV_FLS_ROW_SIZE 0x00000100u\r
+#define CYDEV_ECC_SECTOR_SIZE 0x00002000u\r
+#define CYDEV_ECC_ROW_SIZE 0x00000020u\r
+#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u\r
+#define CYDEV_EEPROM_ROW_SIZE 0x00000010u\r
+#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE\r
+#define CYCLK_LD_DISABLE 0x00000004u\r
+#define CYCLK_LD_SYNC_EN 0x00000002u\r
+#define CYCLK_LD_LOAD 0x00000001u\r
+#define CYCLK_PIPE 0x00000080u\r
+#define CYCLK_SSS 0x00000040u\r
+#define CYCLK_EARLY 0x00000020u\r
+#define CYCLK_DUTY 0x00000010u\r
+#define CYCLK_SYNC 0x00000008u\r
+#define CYCLK_SRC_SEL_CLK_SYNC_D 0\r
+#define CYCLK_SRC_SEL_SYNC_DIG 0\r
+#define CYCLK_SRC_SEL_IMO 1\r
+#define CYCLK_SRC_SEL_XTAL_MHZ 2\r
+#define CYCLK_SRC_SEL_XTALM 2\r
+#define CYCLK_SRC_SEL_ILO 3\r
+#define CYCLK_SRC_SEL_PLL 4\r
+#define CYCLK_SRC_SEL_XTAL_KHZ 5\r
+#define CYCLK_SRC_SEL_XTALK 5\r
+#define CYCLK_SRC_SEL_DSI_G 6\r
+#define CYCLK_SRC_SEL_DSI_D 7\r
+#define CYCLK_SRC_SEL_CLK_SYNC_A 0\r
+#define CYCLK_SRC_SEL_DSI_A 7\r
+#endif /* CYDEVICE_TRM_H */\r
--- /dev/null
+/*******************************************************************************\r
+* FILENAME: cydevicegnu.inc\r
+* OBSOLETE: Do not use this file. Use the _trm version instead.\r
+* PSoC Creator 2.2 Component Pack 6\r
+*\r
+* DESCRIPTION:\r
+* This file provides all of the address values for the entire PSoC device.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+********************************************************************************/\r
+\r
+.set CYDEV_FLASH_BASE, 0x00000000\r
+.set CYDEV_FLASH_SIZE, 0x00040000\r
+.set CYDEV_FLASH_DATA_MBASE, 0x00000000\r
+.set CYDEV_FLASH_DATA_MSIZE, 0x00040000\r
+.set CYDEV_SRAM_BASE, 0x1fff8000\r
+.set CYDEV_SRAM_SIZE, 0x00010000\r
+.set CYDEV_SRAM_CODE64K_MBASE, 0x1fff8000\r
+.set CYDEV_SRAM_CODE64K_MSIZE, 0x00004000\r
+.set CYDEV_SRAM_CODE32K_MBASE, 0x1fffc000\r
+.set CYDEV_SRAM_CODE32K_MSIZE, 0x00002000\r
+.set CYDEV_SRAM_CODE16K_MBASE, 0x1fffe000\r
+.set CYDEV_SRAM_CODE16K_MSIZE, 0x00001000\r
+.set CYDEV_SRAM_CODE_MBASE, 0x1fff8000\r
+.set CYDEV_SRAM_CODE_MSIZE, 0x00008000\r
+.set CYDEV_SRAM_DATA_MBASE, 0x20000000\r
+.set CYDEV_SRAM_DATA_MSIZE, 0x00008000\r
+.set CYDEV_SRAM_DATA16K_MBASE, 0x20001000\r
+.set CYDEV_SRAM_DATA16K_MSIZE, 0x00001000\r
+.set CYDEV_SRAM_DATA32K_MBASE, 0x20002000\r
+.set CYDEV_SRAM_DATA32K_MSIZE, 0x00002000\r
+.set CYDEV_SRAM_DATA64K_MBASE, 0x20004000\r
+.set CYDEV_SRAM_DATA64K_MSIZE, 0x00004000\r
+.set CYDEV_DMA_BASE, 0x20008000\r
+.set CYDEV_DMA_SIZE, 0x00008000\r
+.set CYDEV_DMA_SRAM64K_MBASE, 0x20008000\r
+.set CYDEV_DMA_SRAM64K_MSIZE, 0x00004000\r
+.set CYDEV_DMA_SRAM32K_MBASE, 0x2000c000\r
+.set CYDEV_DMA_SRAM32K_MSIZE, 0x00002000\r
+.set CYDEV_DMA_SRAM16K_MBASE, 0x2000e000\r
+.set CYDEV_DMA_SRAM16K_MSIZE, 0x00001000\r
+.set CYDEV_DMA_SRAM_MBASE, 0x2000f000\r
+.set CYDEV_DMA_SRAM_MSIZE, 0x00001000\r
+.set CYDEV_CLKDIST_BASE, 0x40004000\r
+.set CYDEV_CLKDIST_SIZE, 0x00000110\r
+.set CYDEV_CLKDIST_CR, 0x40004000\r
+.set CYDEV_CLKDIST_LD, 0x40004001\r
+.set CYDEV_CLKDIST_WRK0, 0x40004002\r
+.set CYDEV_CLKDIST_WRK1, 0x40004003\r
+.set CYDEV_CLKDIST_MSTR0, 0x40004004\r
+.set CYDEV_CLKDIST_MSTR1, 0x40004005\r
+.set CYDEV_CLKDIST_BCFG0, 0x40004006\r
+.set CYDEV_CLKDIST_BCFG1, 0x40004007\r
+.set CYDEV_CLKDIST_BCFG2, 0x40004008\r
+.set CYDEV_CLKDIST_UCFG, 0x40004009\r
+.set CYDEV_CLKDIST_DLY0, 0x4000400a\r
+.set CYDEV_CLKDIST_DLY1, 0x4000400b\r
+.set CYDEV_CLKDIST_DMASK, 0x40004010\r
+.set CYDEV_CLKDIST_AMASK, 0x40004014\r
+.set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080\r
+.set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003\r
+.set CYDEV_CLKDIST_DCFG0_CFG0, 0x40004080\r
+.set CYDEV_CLKDIST_DCFG0_CFG1, 0x40004081\r
+.set CYDEV_CLKDIST_DCFG0_CFG2, 0x40004082\r
+.set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084\r
+.set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003\r
+.set CYDEV_CLKDIST_DCFG1_CFG0, 0x40004084\r
+.set CYDEV_CLKDIST_DCFG1_CFG1, 0x40004085\r
+.set CYDEV_CLKDIST_DCFG1_CFG2, 0x40004086\r
+.set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088\r
+.set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003\r
+.set CYDEV_CLKDIST_DCFG2_CFG0, 0x40004088\r
+.set CYDEV_CLKDIST_DCFG2_CFG1, 0x40004089\r
+.set CYDEV_CLKDIST_DCFG2_CFG2, 0x4000408a\r
+.set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c\r
+.set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003\r
+.set CYDEV_CLKDIST_DCFG3_CFG0, 0x4000408c\r
+.set CYDEV_CLKDIST_DCFG3_CFG1, 0x4000408d\r
+.set CYDEV_CLKDIST_DCFG3_CFG2, 0x4000408e\r
+.set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090\r
+.set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003\r
+.set CYDEV_CLKDIST_DCFG4_CFG0, 0x40004090\r
+.set CYDEV_CLKDIST_DCFG4_CFG1, 0x40004091\r
+.set CYDEV_CLKDIST_DCFG4_CFG2, 0x40004092\r
+.set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094\r
+.set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003\r
+.set CYDEV_CLKDIST_DCFG5_CFG0, 0x40004094\r
+.set CYDEV_CLKDIST_DCFG5_CFG1, 0x40004095\r
+.set CYDEV_CLKDIST_DCFG5_CFG2, 0x40004096\r
+.set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098\r
+.set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003\r
+.set CYDEV_CLKDIST_DCFG6_CFG0, 0x40004098\r
+.set CYDEV_CLKDIST_DCFG6_CFG1, 0x40004099\r
+.set CYDEV_CLKDIST_DCFG6_CFG2, 0x4000409a\r
+.set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c\r
+.set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003\r
+.set CYDEV_CLKDIST_DCFG7_CFG0, 0x4000409c\r
+.set CYDEV_CLKDIST_DCFG7_CFG1, 0x4000409d\r
+.set CYDEV_CLKDIST_DCFG7_CFG2, 0x4000409e\r
+.set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100\r
+.set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004\r
+.set CYDEV_CLKDIST_ACFG0_CFG0, 0x40004100\r
+.set CYDEV_CLKDIST_ACFG0_CFG1, 0x40004101\r
+.set CYDEV_CLKDIST_ACFG0_CFG2, 0x40004102\r
+.set CYDEV_CLKDIST_ACFG0_CFG3, 0x40004103\r
+.set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104\r
+.set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004\r
+.set CYDEV_CLKDIST_ACFG1_CFG0, 0x40004104\r
+.set CYDEV_CLKDIST_ACFG1_CFG1, 0x40004105\r
+.set CYDEV_CLKDIST_ACFG1_CFG2, 0x40004106\r
+.set CYDEV_CLKDIST_ACFG1_CFG3, 0x40004107\r
+.set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108\r
+.set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004\r
+.set CYDEV_CLKDIST_ACFG2_CFG0, 0x40004108\r
+.set CYDEV_CLKDIST_ACFG2_CFG1, 0x40004109\r
+.set CYDEV_CLKDIST_ACFG2_CFG2, 0x4000410a\r
+.set CYDEV_CLKDIST_ACFG2_CFG3, 0x4000410b\r
+.set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c\r
+.set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004\r
+.set CYDEV_CLKDIST_ACFG3_CFG0, 0x4000410c\r
+.set CYDEV_CLKDIST_ACFG3_CFG1, 0x4000410d\r
+.set CYDEV_CLKDIST_ACFG3_CFG2, 0x4000410e\r
+.set CYDEV_CLKDIST_ACFG3_CFG3, 0x4000410f\r
+.set CYDEV_FASTCLK_BASE, 0x40004200\r
+.set CYDEV_FASTCLK_SIZE, 0x00000026\r
+.set CYDEV_FASTCLK_IMO_BASE, 0x40004200\r
+.set CYDEV_FASTCLK_IMO_SIZE, 0x00000001\r
+.set CYDEV_FASTCLK_IMO_CR, 0x40004200\r
+.set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210\r
+.set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004\r
+.set CYDEV_FASTCLK_XMHZ_CSR, 0x40004210\r
+.set CYDEV_FASTCLK_XMHZ_CFG0, 0x40004212\r
+.set CYDEV_FASTCLK_XMHZ_CFG1, 0x40004213\r
+.set CYDEV_FASTCLK_PLL_BASE, 0x40004220\r
+.set CYDEV_FASTCLK_PLL_SIZE, 0x00000006\r
+.set CYDEV_FASTCLK_PLL_CFG0, 0x40004220\r
+.set CYDEV_FASTCLK_PLL_CFG1, 0x40004221\r
+.set CYDEV_FASTCLK_PLL_P, 0x40004222\r
+.set CYDEV_FASTCLK_PLL_Q, 0x40004223\r
+.set CYDEV_FASTCLK_PLL_SR, 0x40004225\r
+.set CYDEV_SLOWCLK_BASE, 0x40004300\r
+.set CYDEV_SLOWCLK_SIZE, 0x0000000b\r
+.set CYDEV_SLOWCLK_ILO_BASE, 0x40004300\r
+.set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002\r
+.set CYDEV_SLOWCLK_ILO_CR0, 0x40004300\r
+.set CYDEV_SLOWCLK_ILO_CR1, 0x40004301\r
+.set CYDEV_SLOWCLK_X32_BASE, 0x40004308\r
+.set CYDEV_SLOWCLK_X32_SIZE, 0x00000003\r
+.set CYDEV_SLOWCLK_X32_CR, 0x40004308\r
+.set CYDEV_SLOWCLK_X32_CFG, 0x40004309\r
+.set CYDEV_SLOWCLK_X32_TST, 0x4000430a\r
+.set CYDEV_BOOST_BASE, 0x40004320\r
+.set CYDEV_BOOST_SIZE, 0x00000007\r
+.set CYDEV_BOOST_CR0, 0x40004320\r
+.set CYDEV_BOOST_CR1, 0x40004321\r
+.set CYDEV_BOOST_CR2, 0x40004322\r
+.set CYDEV_BOOST_CR3, 0x40004323\r
+.set CYDEV_BOOST_SR, 0x40004324\r
+.set CYDEV_BOOST_CR4, 0x40004325\r
+.set CYDEV_BOOST_SR2, 0x40004326\r
+.set CYDEV_PWRSYS_BASE, 0x40004330\r
+.set CYDEV_PWRSYS_SIZE, 0x00000002\r
+.set CYDEV_PWRSYS_CR0, 0x40004330\r
+.set CYDEV_PWRSYS_CR1, 0x40004331\r
+.set CYDEV_PM_BASE, 0x40004380\r
+.set CYDEV_PM_SIZE, 0x00000057\r
+.set CYDEV_PM_TW_CFG0, 0x40004380\r
+.set CYDEV_PM_TW_CFG1, 0x40004381\r
+.set CYDEV_PM_TW_CFG2, 0x40004382\r
+.set CYDEV_PM_WDT_CFG, 0x40004383\r
+.set CYDEV_PM_WDT_CR, 0x40004384\r
+.set CYDEV_PM_INT_SR, 0x40004390\r
+.set CYDEV_PM_MODE_CFG0, 0x40004391\r
+.set CYDEV_PM_MODE_CFG1, 0x40004392\r
+.set CYDEV_PM_MODE_CSR, 0x40004393\r
+.set CYDEV_PM_USB_CR0, 0x40004394\r
+.set CYDEV_PM_WAKEUP_CFG0, 0x40004398\r
+.set CYDEV_PM_WAKEUP_CFG1, 0x40004399\r
+.set CYDEV_PM_WAKEUP_CFG2, 0x4000439a\r
+.set CYDEV_PM_ACT_BASE, 0x400043a0\r
+.set CYDEV_PM_ACT_SIZE, 0x0000000e\r
+.set CYDEV_PM_ACT_CFG0, 0x400043a0\r
+.set CYDEV_PM_ACT_CFG1, 0x400043a1\r
+.set CYDEV_PM_ACT_CFG2, 0x400043a2\r
+.set CYDEV_PM_ACT_CFG3, 0x400043a3\r
+.set CYDEV_PM_ACT_CFG4, 0x400043a4\r
+.set CYDEV_PM_ACT_CFG5, 0x400043a5\r
+.set CYDEV_PM_ACT_CFG6, 0x400043a6\r
+.set CYDEV_PM_ACT_CFG7, 0x400043a7\r
+.set CYDEV_PM_ACT_CFG8, 0x400043a8\r
+.set CYDEV_PM_ACT_CFG9, 0x400043a9\r
+.set CYDEV_PM_ACT_CFG10, 0x400043aa\r
+.set CYDEV_PM_ACT_CFG11, 0x400043ab\r
+.set CYDEV_PM_ACT_CFG12, 0x400043ac\r
+.set CYDEV_PM_ACT_CFG13, 0x400043ad\r
+.set CYDEV_PM_STBY_BASE, 0x400043b0\r
+.set CYDEV_PM_STBY_SIZE, 0x0000000e\r
+.set CYDEV_PM_STBY_CFG0, 0x400043b0\r
+.set CYDEV_PM_STBY_CFG1, 0x400043b1\r
+.set CYDEV_PM_STBY_CFG2, 0x400043b2\r
+.set CYDEV_PM_STBY_CFG3, 0x400043b3\r
+.set CYDEV_PM_STBY_CFG4, 0x400043b4\r
+.set CYDEV_PM_STBY_CFG5, 0x400043b5\r
+.set CYDEV_PM_STBY_CFG6, 0x400043b6\r
+.set CYDEV_PM_STBY_CFG7, 0x400043b7\r
+.set CYDEV_PM_STBY_CFG8, 0x400043b8\r
+.set CYDEV_PM_STBY_CFG9, 0x400043b9\r
+.set CYDEV_PM_STBY_CFG10, 0x400043ba\r
+.set CYDEV_PM_STBY_CFG11, 0x400043bb\r
+.set CYDEV_PM_STBY_CFG12, 0x400043bc\r
+.set CYDEV_PM_STBY_CFG13, 0x400043bd\r
+.set CYDEV_PM_AVAIL_BASE, 0x400043c0\r
+.set CYDEV_PM_AVAIL_SIZE, 0x00000017\r
+.set CYDEV_PM_AVAIL_CR0, 0x400043c0\r
+.set CYDEV_PM_AVAIL_CR1, 0x400043c1\r
+.set CYDEV_PM_AVAIL_CR2, 0x400043c2\r
+.set CYDEV_PM_AVAIL_CR3, 0x400043c3\r
+.set CYDEV_PM_AVAIL_CR4, 0x400043c4\r
+.set CYDEV_PM_AVAIL_CR5, 0x400043c5\r
+.set CYDEV_PM_AVAIL_CR6, 0x400043c6\r
+.set CYDEV_PM_AVAIL_SR0, 0x400043d0\r
+.set CYDEV_PM_AVAIL_SR1, 0x400043d1\r
+.set CYDEV_PM_AVAIL_SR2, 0x400043d2\r
+.set CYDEV_PM_AVAIL_SR3, 0x400043d3\r
+.set CYDEV_PM_AVAIL_SR4, 0x400043d4\r
+.set CYDEV_PM_AVAIL_SR5, 0x400043d5\r
+.set CYDEV_PM_AVAIL_SR6, 0x400043d6\r
+.set CYDEV_PICU_BASE, 0x40004500\r
+.set CYDEV_PICU_SIZE, 0x000000b0\r
+.set CYDEV_PICU_INTTYPE_BASE, 0x40004500\r
+.set CYDEV_PICU_INTTYPE_SIZE, 0x00000080\r
+.set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500\r
+.set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008\r
+.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE0, 0x40004500\r
+.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE1, 0x40004501\r
+.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE2, 0x40004502\r
+.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE3, 0x40004503\r
+.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE4, 0x40004504\r
+.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE5, 0x40004505\r
+.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE6, 0x40004506\r
+.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE7, 0x40004507\r
+.set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508\r
+.set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008\r
+.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE0, 0x40004508\r
+.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE1, 0x40004509\r
+.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE2, 0x4000450a\r
+.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE3, 0x4000450b\r
+.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE4, 0x4000450c\r
+.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE5, 0x4000450d\r
+.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE6, 0x4000450e\r
+.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE7, 0x4000450f\r
+.set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510\r
+.set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008\r
+.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE0, 0x40004510\r
+.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE1, 0x40004511\r
+.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE2, 0x40004512\r
+.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE3, 0x40004513\r
+.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE4, 0x40004514\r
+.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE5, 0x40004515\r
+.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE6, 0x40004516\r
+.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE7, 0x40004517\r
+.set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518\r
+.set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008\r
+.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE0, 0x40004518\r
+.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE1, 0x40004519\r
+.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE2, 0x4000451a\r
+.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE3, 0x4000451b\r
+.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE4, 0x4000451c\r
+.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE5, 0x4000451d\r
+.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE6, 0x4000451e\r
+.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE7, 0x4000451f\r
+.set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520\r
+.set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008\r
+.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE0, 0x40004520\r
+.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE1, 0x40004521\r
+.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE2, 0x40004522\r
+.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE3, 0x40004523\r
+.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE4, 0x40004524\r
+.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE5, 0x40004525\r
+.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE6, 0x40004526\r
+.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE7, 0x40004527\r
+.set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528\r
+.set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008\r
+.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE0, 0x40004528\r
+.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE1, 0x40004529\r
+.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE2, 0x4000452a\r
+.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE3, 0x4000452b\r
+.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE4, 0x4000452c\r
+.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE5, 0x4000452d\r
+.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE6, 0x4000452e\r
+.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE7, 0x4000452f\r
+.set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530\r
+.set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008\r
+.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE0, 0x40004530\r
+.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE1, 0x40004531\r
+.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE2, 0x40004532\r
+.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE3, 0x40004533\r
+.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE4, 0x40004534\r
+.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE5, 0x40004535\r
+.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE6, 0x40004536\r
+.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE7, 0x40004537\r
+.set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560\r
+.set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008\r
+.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE0, 0x40004560\r
+.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE1, 0x40004561\r
+.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE2, 0x40004562\r
+.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE3, 0x40004563\r
+.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE4, 0x40004564\r
+.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE5, 0x40004565\r
+.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE6, 0x40004566\r
+.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE7, 0x40004567\r
+.set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578\r
+.set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008\r
+.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE0, 0x40004578\r
+.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE1, 0x40004579\r
+.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE2, 0x4000457a\r
+.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE3, 0x4000457b\r
+.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE4, 0x4000457c\r
+.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE5, 0x4000457d\r
+.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE6, 0x4000457e\r
+.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE7, 0x4000457f\r
+.set CYDEV_PICU_STAT_BASE, 0x40004580\r
+.set CYDEV_PICU_STAT_SIZE, 0x00000010\r
+.set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580\r
+.set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001\r
+.set CYDEV_PICU_STAT_PICU0_INTSTAT, 0x40004580\r
+.set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581\r
+.set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001\r
+.set CYDEV_PICU_STAT_PICU1_INTSTAT, 0x40004581\r
+.set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582\r
+.set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001\r
+.set CYDEV_PICU_STAT_PICU2_INTSTAT, 0x40004582\r
+.set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583\r
+.set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001\r
+.set CYDEV_PICU_STAT_PICU3_INTSTAT, 0x40004583\r
+.set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584\r
+.set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001\r
+.set CYDEV_PICU_STAT_PICU4_INTSTAT, 0x40004584\r
+.set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585\r
+.set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001\r
+.set CYDEV_PICU_STAT_PICU5_INTSTAT, 0x40004585\r
+.set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586\r
+.set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001\r
+.set CYDEV_PICU_STAT_PICU6_INTSTAT, 0x40004586\r
+.set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c\r
+.set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001\r
+.set CYDEV_PICU_STAT_PICU12_INTSTAT, 0x4000458c\r
+.set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f\r
+.set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001\r
+.set CYDEV_PICU_STAT_PICU15_INTSTAT, 0x4000458f\r
+.set CYDEV_PICU_SNAP_BASE, 0x40004590\r
+.set CYDEV_PICU_SNAP_SIZE, 0x00000010\r
+.set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590\r
+.set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001\r
+.set CYDEV_PICU_SNAP_PICU0_SNAP, 0x40004590\r
+.set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591\r
+.set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001\r
+.set CYDEV_PICU_SNAP_PICU1_SNAP, 0x40004591\r
+.set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592\r
+.set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001\r
+.set CYDEV_PICU_SNAP_PICU2_SNAP, 0x40004592\r
+.set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593\r
+.set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001\r
+.set CYDEV_PICU_SNAP_PICU3_SNAP, 0x40004593\r
+.set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594\r
+.set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001\r
+.set CYDEV_PICU_SNAP_PICU4_SNAP, 0x40004594\r
+.set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595\r
+.set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001\r
+.set CYDEV_PICU_SNAP_PICU5_SNAP, 0x40004595\r
+.set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596\r
+.set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001\r
+.set CYDEV_PICU_SNAP_PICU6_SNAP, 0x40004596\r
+.set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c\r
+.set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001\r
+.set CYDEV_PICU_SNAP_PICU12_SNAP, 0x4000459c\r
+.set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f\r
+.set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001\r
+.set CYDEV_PICU_SNAP_PICU_15_SNAP_15, 0x4000459f\r
+.set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0\r
+.set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010\r
+.set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0\r
+.set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001\r
+.set CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR, 0x400045a0\r
+.set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1\r
+.set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001\r
+.set CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR, 0x400045a1\r
+.set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2\r
+.set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001\r
+.set CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR, 0x400045a2\r
+.set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3\r
+.set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001\r
+.set CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR, 0x400045a3\r
+.set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4\r
+.set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001\r
+.set CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR, 0x400045a4\r
+.set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5\r
+.set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001\r
+.set CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR, 0x400045a5\r
+.set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6\r
+.set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001\r
+.set CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR, 0x400045a6\r
+.set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac\r
+.set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001\r
+.set CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR, 0x400045ac\r
+.set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af\r
+.set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001\r
+.set CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR, 0x400045af\r
+.set CYDEV_MFGCFG_BASE, 0x40004600\r
+.set CYDEV_MFGCFG_SIZE, 0x000000ed\r
+.set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600\r
+.set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038\r
+.set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608\r
+.set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001\r
+.set CYDEV_MFGCFG_ANAIF_DAC0_TR, 0x40004608\r
+.set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609\r
+.set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001\r
+.set CYDEV_MFGCFG_ANAIF_DAC1_TR, 0x40004609\r
+.set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a\r
+.set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001\r
+.set CYDEV_MFGCFG_ANAIF_DAC2_TR, 0x4000460a\r
+.set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b\r
+.set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001\r
+.set CYDEV_MFGCFG_ANAIF_DAC3_TR, 0x4000460b\r
+.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610\r
+.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001\r
+.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0, 0x40004610\r
+.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611\r
+.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001\r
+.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0, 0x40004611\r
+.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612\r
+.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001\r
+.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0, 0x40004612\r
+.set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614\r
+.set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001\r
+.set CYDEV_MFGCFG_ANAIF_SAR0_TR0, 0x40004614\r
+.set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616\r
+.set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001\r
+.set CYDEV_MFGCFG_ANAIF_SAR1_TR0, 0x40004616\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP0_TR0, 0x40004620\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP0_TR1, 0x40004621\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP1_TR0, 0x40004622\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP1_TR1, 0x40004623\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP2_TR0, 0x40004624\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP2_TR1, 0x40004625\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP3_TR0, 0x40004626\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP3_TR1, 0x40004627\r
+.set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630\r
+.set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002\r
+.set CYDEV_MFGCFG_ANAIF_CMP0_TR0, 0x40004630\r
+.set CYDEV_MFGCFG_ANAIF_CMP0_TR1, 0x40004631\r
+.set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632\r
+.set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002\r
+.set CYDEV_MFGCFG_ANAIF_CMP1_TR0, 0x40004632\r
+.set CYDEV_MFGCFG_ANAIF_CMP1_TR1, 0x40004633\r
+.set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634\r
+.set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002\r
+.set CYDEV_MFGCFG_ANAIF_CMP2_TR0, 0x40004634\r
+.set CYDEV_MFGCFG_ANAIF_CMP2_TR1, 0x40004635\r
+.set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636\r
+.set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002\r
+.set CYDEV_MFGCFG_ANAIF_CMP3_TR0, 0x40004636\r
+.set CYDEV_MFGCFG_ANAIF_CMP3_TR1, 0x40004637\r
+.set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680\r
+.set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b\r
+.set CYDEV_MFGCFG_PWRSYS_HIB_TR0, 0x40004680\r
+.set CYDEV_MFGCFG_PWRSYS_HIB_TR1, 0x40004681\r
+.set CYDEV_MFGCFG_PWRSYS_I2C_TR, 0x40004682\r
+.set CYDEV_MFGCFG_PWRSYS_SLP_TR, 0x40004683\r
+.set CYDEV_MFGCFG_PWRSYS_BUZZ_TR, 0x40004684\r
+.set CYDEV_MFGCFG_PWRSYS_WAKE_TR0, 0x40004685\r
+.set CYDEV_MFGCFG_PWRSYS_WAKE_TR1, 0x40004686\r
+.set CYDEV_MFGCFG_PWRSYS_BREF_TR, 0x40004687\r
+.set CYDEV_MFGCFG_PWRSYS_BG_TR, 0x40004688\r
+.set CYDEV_MFGCFG_PWRSYS_WAKE_TR2, 0x40004689\r
+.set CYDEV_MFGCFG_PWRSYS_WAKE_TR3, 0x4000468a\r
+.set CYDEV_MFGCFG_ILO_BASE, 0x40004690\r
+.set CYDEV_MFGCFG_ILO_SIZE, 0x00000002\r
+.set CYDEV_MFGCFG_ILO_TR0, 0x40004690\r
+.set CYDEV_MFGCFG_ILO_TR1, 0x40004691\r
+.set CYDEV_MFGCFG_X32_BASE, 0x40004698\r
+.set CYDEV_MFGCFG_X32_SIZE, 0x00000001\r
+.set CYDEV_MFGCFG_X32_TR, 0x40004698\r
+.set CYDEV_MFGCFG_IMO_BASE, 0x400046a0\r
+.set CYDEV_MFGCFG_IMO_SIZE, 0x00000005\r
+.set CYDEV_MFGCFG_IMO_TR0, 0x400046a0\r
+.set CYDEV_MFGCFG_IMO_TR1, 0x400046a1\r
+.set CYDEV_MFGCFG_IMO_GAIN, 0x400046a2\r
+.set CYDEV_MFGCFG_IMO_C36M, 0x400046a3\r
+.set CYDEV_MFGCFG_IMO_TR2, 0x400046a4\r
+.set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8\r
+.set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001\r
+.set CYDEV_MFGCFG_XMHZ_TR, 0x400046a8\r
+.set CYDEV_MFGCFG_DLY, 0x400046c0\r
+.set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0\r
+.set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d\r
+.set CYDEV_MFGCFG_MLOGIC_DMPSTR, 0x400046e2\r
+.set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4\r
+.set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002\r
+.set CYDEV_MFGCFG_MLOGIC_SEG_CR, 0x400046e4\r
+.set CYDEV_MFGCFG_MLOGIC_SEG_CFG0, 0x400046e5\r
+.set CYDEV_MFGCFG_MLOGIC_DEBUG, 0x400046e8\r
+.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea\r
+.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001\r
+.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea\r
+.set CYDEV_MFGCFG_MLOGIC_REV_ID, 0x400046ec\r
+.set CYDEV_RESET_BASE, 0x400046f0\r
+.set CYDEV_RESET_SIZE, 0x0000000f\r
+.set CYDEV_RESET_IPOR_CR0, 0x400046f0\r
+.set CYDEV_RESET_IPOR_CR1, 0x400046f1\r
+.set CYDEV_RESET_IPOR_CR2, 0x400046f2\r
+.set CYDEV_RESET_IPOR_CR3, 0x400046f3\r
+.set CYDEV_RESET_CR0, 0x400046f4\r
+.set CYDEV_RESET_CR1, 0x400046f5\r
+.set CYDEV_RESET_CR2, 0x400046f6\r
+.set CYDEV_RESET_CR3, 0x400046f7\r
+.set CYDEV_RESET_CR4, 0x400046f8\r
+.set CYDEV_RESET_CR5, 0x400046f9\r
+.set CYDEV_RESET_SR0, 0x400046fa\r
+.set CYDEV_RESET_SR1, 0x400046fb\r
+.set CYDEV_RESET_SR2, 0x400046fc\r
+.set CYDEV_RESET_SR3, 0x400046fd\r
+.set CYDEV_RESET_TR, 0x400046fe\r
+.set CYDEV_SPC_BASE, 0x40004700\r
+.set CYDEV_SPC_SIZE, 0x00000100\r
+.set CYDEV_SPC_FM_EE_CR, 0x40004700\r
+.set CYDEV_SPC_FM_EE_WAKE_CNT, 0x40004701\r
+.set CYDEV_SPC_EE_SCR, 0x40004702\r
+.set CYDEV_SPC_EE_ERR, 0x40004703\r
+.set CYDEV_SPC_CPU_DATA, 0x40004720\r
+.set CYDEV_SPC_DMA_DATA, 0x40004721\r
+.set CYDEV_SPC_SR, 0x40004722\r
+.set CYDEV_SPC_CR, 0x40004723\r
+.set CYDEV_SPC_DMM_MAP_BASE, 0x40004780\r
+.set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080\r
+.set CYDEV_SPC_DMM_MAP_SRAM_MBASE, 0x40004780\r
+.set CYDEV_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080\r
+.set CYDEV_CACHE_BASE, 0x40004800\r
+.set CYDEV_CACHE_SIZE, 0x0000009c\r
+.set CYDEV_CACHE_CC_CTL, 0x40004800\r
+.set CYDEV_CACHE_ECC_CORR, 0x40004880\r
+.set CYDEV_CACHE_ECC_ERR, 0x40004888\r
+.set CYDEV_CACHE_FLASH_ERR, 0x40004890\r
+.set CYDEV_CACHE_HITMISS, 0x40004898\r
+.set CYDEV_I2C_BASE, 0x40004900\r
+.set CYDEV_I2C_SIZE, 0x000000e1\r
+.set CYDEV_I2C_XCFG, 0x400049c8\r
+.set CYDEV_I2C_ADR, 0x400049ca\r
+.set CYDEV_I2C_CFG, 0x400049d6\r
+.set CYDEV_I2C_CSR, 0x400049d7\r
+.set CYDEV_I2C_D, 0x400049d8\r
+.set CYDEV_I2C_MCSR, 0x400049d9\r
+.set CYDEV_I2C_CLK_DIV1, 0x400049db\r
+.set CYDEV_I2C_CLK_DIV2, 0x400049dc\r
+.set CYDEV_I2C_TMOUT_CSR, 0x400049dd\r
+.set CYDEV_I2C_TMOUT_SR, 0x400049de\r
+.set CYDEV_I2C_TMOUT_CFG0, 0x400049df\r
+.set CYDEV_I2C_TMOUT_CFG1, 0x400049e0\r
+.set CYDEV_DEC_BASE, 0x40004e00\r
+.set CYDEV_DEC_SIZE, 0x00000015\r
+.set CYDEV_DEC_CR, 0x40004e00\r
+.set CYDEV_DEC_SR, 0x40004e01\r
+.set CYDEV_DEC_SHIFT1, 0x40004e02\r
+.set CYDEV_DEC_SHIFT2, 0x40004e03\r
+.set CYDEV_DEC_DR2, 0x40004e04\r
+.set CYDEV_DEC_DR2H, 0x40004e05\r
+.set CYDEV_DEC_DR1, 0x40004e06\r
+.set CYDEV_DEC_OCOR, 0x40004e08\r
+.set CYDEV_DEC_OCORM, 0x40004e09\r
+.set CYDEV_DEC_OCORH, 0x40004e0a\r
+.set CYDEV_DEC_GCOR, 0x40004e0c\r
+.set CYDEV_DEC_GCORH, 0x40004e0d\r
+.set CYDEV_DEC_GVAL, 0x40004e0e\r
+.set CYDEV_DEC_OUTSAMP, 0x40004e10\r
+.set CYDEV_DEC_OUTSAMPM, 0x40004e11\r
+.set CYDEV_DEC_OUTSAMPH, 0x40004e12\r
+.set CYDEV_DEC_OUTSAMPS, 0x40004e13\r
+.set CYDEV_DEC_COHER, 0x40004e14\r
+.set CYDEV_TMR0_BASE, 0x40004f00\r
+.set CYDEV_TMR0_SIZE, 0x0000000c\r
+.set CYDEV_TMR0_CFG0, 0x40004f00\r
+.set CYDEV_TMR0_CFG1, 0x40004f01\r
+.set CYDEV_TMR0_CFG2, 0x40004f02\r
+.set CYDEV_TMR0_SR0, 0x40004f03\r
+.set CYDEV_TMR0_PER0, 0x40004f04\r
+.set CYDEV_TMR0_PER1, 0x40004f05\r
+.set CYDEV_TMR0_CNT_CMP0, 0x40004f06\r
+.set CYDEV_TMR0_CNT_CMP1, 0x40004f07\r
+.set CYDEV_TMR0_CAP0, 0x40004f08\r
+.set CYDEV_TMR0_CAP1, 0x40004f09\r
+.set CYDEV_TMR0_RT0, 0x40004f0a\r
+.set CYDEV_TMR0_RT1, 0x40004f0b\r
+.set CYDEV_TMR1_BASE, 0x40004f0c\r
+.set CYDEV_TMR1_SIZE, 0x0000000c\r
+.set CYDEV_TMR1_CFG0, 0x40004f0c\r
+.set CYDEV_TMR1_CFG1, 0x40004f0d\r
+.set CYDEV_TMR1_CFG2, 0x40004f0e\r
+.set CYDEV_TMR1_SR0, 0x40004f0f\r
+.set CYDEV_TMR1_PER0, 0x40004f10\r
+.set CYDEV_TMR1_PER1, 0x40004f11\r
+.set CYDEV_TMR1_CNT_CMP0, 0x40004f12\r
+.set CYDEV_TMR1_CNT_CMP1, 0x40004f13\r
+.set CYDEV_TMR1_CAP0, 0x40004f14\r
+.set CYDEV_TMR1_CAP1, 0x40004f15\r
+.set CYDEV_TMR1_RT0, 0x40004f16\r
+.set CYDEV_TMR1_RT1, 0x40004f17\r
+.set CYDEV_TMR2_BASE, 0x40004f18\r
+.set CYDEV_TMR2_SIZE, 0x0000000c\r
+.set CYDEV_TMR2_CFG0, 0x40004f18\r
+.set CYDEV_TMR2_CFG1, 0x40004f19\r
+.set CYDEV_TMR2_CFG2, 0x40004f1a\r
+.set CYDEV_TMR2_SR0, 0x40004f1b\r
+.set CYDEV_TMR2_PER0, 0x40004f1c\r
+.set CYDEV_TMR2_PER1, 0x40004f1d\r
+.set CYDEV_TMR2_CNT_CMP0, 0x40004f1e\r
+.set CYDEV_TMR2_CNT_CMP1, 0x40004f1f\r
+.set CYDEV_TMR2_CAP0, 0x40004f20\r
+.set CYDEV_TMR2_CAP1, 0x40004f21\r
+.set CYDEV_TMR2_RT0, 0x40004f22\r
+.set CYDEV_TMR2_RT1, 0x40004f23\r
+.set CYDEV_TMR3_BASE, 0x40004f24\r
+.set CYDEV_TMR3_SIZE, 0x0000000c\r
+.set CYDEV_TMR3_CFG0, 0x40004f24\r
+.set CYDEV_TMR3_CFG1, 0x40004f25\r
+.set CYDEV_TMR3_CFG2, 0x40004f26\r
+.set CYDEV_TMR3_SR0, 0x40004f27\r
+.set CYDEV_TMR3_PER0, 0x40004f28\r
+.set CYDEV_TMR3_PER1, 0x40004f29\r
+.set CYDEV_TMR3_CNT_CMP0, 0x40004f2a\r
+.set CYDEV_TMR3_CNT_CMP1, 0x40004f2b\r
+.set CYDEV_TMR3_CAP0, 0x40004f2c\r
+.set CYDEV_TMR3_CAP1, 0x40004f2d\r
+.set CYDEV_TMR3_RT0, 0x40004f2e\r
+.set CYDEV_TMR3_RT1, 0x40004f2f\r
+.set CYDEV_IO_BASE, 0x40005000\r
+.set CYDEV_IO_SIZE, 0x00000200\r
+.set CYDEV_IO_PC_BASE, 0x40005000\r
+.set CYDEV_IO_PC_SIZE, 0x00000080\r
+.set CYDEV_IO_PC_PRT0_BASE, 0x40005000\r
+.set CYDEV_IO_PC_PRT0_SIZE, 0x00000008\r
+.set CYDEV_IO_PC_PRT0_PC0, 0x40005000\r
+.set CYDEV_IO_PC_PRT0_PC1, 0x40005001\r
+.set CYDEV_IO_PC_PRT0_PC2, 0x40005002\r
+.set CYDEV_IO_PC_PRT0_PC3, 0x40005003\r
+.set CYDEV_IO_PC_PRT0_PC4, 0x40005004\r
+.set CYDEV_IO_PC_PRT0_PC5, 0x40005005\r
+.set CYDEV_IO_PC_PRT0_PC6, 0x40005006\r
+.set CYDEV_IO_PC_PRT0_PC7, 0x40005007\r
+.set CYDEV_IO_PC_PRT1_BASE, 0x40005008\r
+.set CYDEV_IO_PC_PRT1_SIZE, 0x00000008\r
+.set CYDEV_IO_PC_PRT1_PC0, 0x40005008\r
+.set CYDEV_IO_PC_PRT1_PC1, 0x40005009\r
+.set CYDEV_IO_PC_PRT1_PC2, 0x4000500a\r
+.set CYDEV_IO_PC_PRT1_PC3, 0x4000500b\r
+.set CYDEV_IO_PC_PRT1_PC4, 0x4000500c\r
+.set CYDEV_IO_PC_PRT1_PC5, 0x4000500d\r
+.set CYDEV_IO_PC_PRT1_PC6, 0x4000500e\r
+.set CYDEV_IO_PC_PRT1_PC7, 0x4000500f\r
+.set CYDEV_IO_PC_PRT2_BASE, 0x40005010\r
+.set CYDEV_IO_PC_PRT2_SIZE, 0x00000008\r
+.set CYDEV_IO_PC_PRT2_PC0, 0x40005010\r
+.set CYDEV_IO_PC_PRT2_PC1, 0x40005011\r
+.set CYDEV_IO_PC_PRT2_PC2, 0x40005012\r
+.set CYDEV_IO_PC_PRT2_PC3, 0x40005013\r
+.set CYDEV_IO_PC_PRT2_PC4, 0x40005014\r
+.set CYDEV_IO_PC_PRT2_PC5, 0x40005015\r
+.set CYDEV_IO_PC_PRT2_PC6, 0x40005016\r
+.set CYDEV_IO_PC_PRT2_PC7, 0x40005017\r
+.set CYDEV_IO_PC_PRT3_BASE, 0x40005018\r
+.set CYDEV_IO_PC_PRT3_SIZE, 0x00000008\r
+.set CYDEV_IO_PC_PRT3_PC0, 0x40005018\r
+.set CYDEV_IO_PC_PRT3_PC1, 0x40005019\r
+.set CYDEV_IO_PC_PRT3_PC2, 0x4000501a\r
+.set CYDEV_IO_PC_PRT3_PC3, 0x4000501b\r
+.set CYDEV_IO_PC_PRT3_PC4, 0x4000501c\r
+.set CYDEV_IO_PC_PRT3_PC5, 0x4000501d\r
+.set CYDEV_IO_PC_PRT3_PC6, 0x4000501e\r
+.set CYDEV_IO_PC_PRT3_PC7, 0x4000501f\r
+.set CYDEV_IO_PC_PRT4_BASE, 0x40005020\r
+.set CYDEV_IO_PC_PRT4_SIZE, 0x00000008\r
+.set CYDEV_IO_PC_PRT4_PC0, 0x40005020\r
+.set CYDEV_IO_PC_PRT4_PC1, 0x40005021\r
+.set CYDEV_IO_PC_PRT4_PC2, 0x40005022\r
+.set CYDEV_IO_PC_PRT4_PC3, 0x40005023\r
+.set CYDEV_IO_PC_PRT4_PC4, 0x40005024\r
+.set CYDEV_IO_PC_PRT4_PC5, 0x40005025\r
+.set CYDEV_IO_PC_PRT4_PC6, 0x40005026\r
+.set CYDEV_IO_PC_PRT4_PC7, 0x40005027\r
+.set CYDEV_IO_PC_PRT5_BASE, 0x40005028\r
+.set CYDEV_IO_PC_PRT5_SIZE, 0x00000008\r
+.set CYDEV_IO_PC_PRT5_PC0, 0x40005028\r
+.set CYDEV_IO_PC_PRT5_PC1, 0x40005029\r
+.set CYDEV_IO_PC_PRT5_PC2, 0x4000502a\r
+.set CYDEV_IO_PC_PRT5_PC3, 0x4000502b\r
+.set CYDEV_IO_PC_PRT5_PC4, 0x4000502c\r
+.set CYDEV_IO_PC_PRT5_PC5, 0x4000502d\r
+.set CYDEV_IO_PC_PRT5_PC6, 0x4000502e\r
+.set CYDEV_IO_PC_PRT5_PC7, 0x4000502f\r
+.set CYDEV_IO_PC_PRT6_BASE, 0x40005030\r
+.set CYDEV_IO_PC_PRT6_SIZE, 0x00000008\r
+.set CYDEV_IO_PC_PRT6_PC0, 0x40005030\r
+.set CYDEV_IO_PC_PRT6_PC1, 0x40005031\r
+.set CYDEV_IO_PC_PRT6_PC2, 0x40005032\r
+.set CYDEV_IO_PC_PRT6_PC3, 0x40005033\r
+.set CYDEV_IO_PC_PRT6_PC4, 0x40005034\r
+.set CYDEV_IO_PC_PRT6_PC5, 0x40005035\r
+.set CYDEV_IO_PC_PRT6_PC6, 0x40005036\r
+.set CYDEV_IO_PC_PRT6_PC7, 0x40005037\r
+.set CYDEV_IO_PC_PRT12_BASE, 0x40005060\r
+.set CYDEV_IO_PC_PRT12_SIZE, 0x00000008\r
+.set CYDEV_IO_PC_PRT12_PC0, 0x40005060\r
+.set CYDEV_IO_PC_PRT12_PC1, 0x40005061\r
+.set CYDEV_IO_PC_PRT12_PC2, 0x40005062\r
+.set CYDEV_IO_PC_PRT12_PC3, 0x40005063\r
+.set CYDEV_IO_PC_PRT12_PC4, 0x40005064\r
+.set CYDEV_IO_PC_PRT12_PC5, 0x40005065\r
+.set CYDEV_IO_PC_PRT12_PC6, 0x40005066\r
+.set CYDEV_IO_PC_PRT12_PC7, 0x40005067\r
+.set CYDEV_IO_PC_PRT15_BASE, 0x40005078\r
+.set CYDEV_IO_PC_PRT15_SIZE, 0x00000006\r
+.set CYDEV_IO_PC_PRT15_PC0, 0x40005078\r
+.set CYDEV_IO_PC_PRT15_PC1, 0x40005079\r
+.set CYDEV_IO_PC_PRT15_PC2, 0x4000507a\r
+.set CYDEV_IO_PC_PRT15_PC3, 0x4000507b\r
+.set CYDEV_IO_PC_PRT15_PC4, 0x4000507c\r
+.set CYDEV_IO_PC_PRT15_PC5, 0x4000507d\r
+.set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e\r
+.set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002\r
+.set CYDEV_IO_PC_PRT15_7_6_PC0, 0x4000507e\r
+.set CYDEV_IO_PC_PRT15_7_6_PC1, 0x4000507f\r
+.set CYDEV_IO_DR_BASE, 0x40005080\r
+.set CYDEV_IO_DR_SIZE, 0x00000010\r
+.set CYDEV_IO_DR_PRT0_BASE, 0x40005080\r
+.set CYDEV_IO_DR_PRT0_SIZE, 0x00000001\r
+.set CYDEV_IO_DR_PRT0_DR_ALIAS, 0x40005080\r
+.set CYDEV_IO_DR_PRT1_BASE, 0x40005081\r
+.set CYDEV_IO_DR_PRT1_SIZE, 0x00000001\r
+.set CYDEV_IO_DR_PRT1_DR_ALIAS, 0x40005081\r
+.set CYDEV_IO_DR_PRT2_BASE, 0x40005082\r
+.set CYDEV_IO_DR_PRT2_SIZE, 0x00000001\r
+.set CYDEV_IO_DR_PRT2_DR_ALIAS, 0x40005082\r
+.set CYDEV_IO_DR_PRT3_BASE, 0x40005083\r
+.set CYDEV_IO_DR_PRT3_SIZE, 0x00000001\r
+.set CYDEV_IO_DR_PRT3_DR_ALIAS, 0x40005083\r
+.set CYDEV_IO_DR_PRT4_BASE, 0x40005084\r
+.set CYDEV_IO_DR_PRT4_SIZE, 0x00000001\r
+.set CYDEV_IO_DR_PRT4_DR_ALIAS, 0x40005084\r
+.set CYDEV_IO_DR_PRT5_BASE, 0x40005085\r
+.set CYDEV_IO_DR_PRT5_SIZE, 0x00000001\r
+.set CYDEV_IO_DR_PRT5_DR_ALIAS, 0x40005085\r
+.set CYDEV_IO_DR_PRT6_BASE, 0x40005086\r
+.set CYDEV_IO_DR_PRT6_SIZE, 0x00000001\r
+.set CYDEV_IO_DR_PRT6_DR_ALIAS, 0x40005086\r
+.set CYDEV_IO_DR_PRT12_BASE, 0x4000508c\r
+.set CYDEV_IO_DR_PRT12_SIZE, 0x00000001\r
+.set CYDEV_IO_DR_PRT12_DR_ALIAS, 0x4000508c\r
+.set CYDEV_IO_DR_PRT15_BASE, 0x4000508f\r
+.set CYDEV_IO_DR_PRT15_SIZE, 0x00000001\r
+.set CYDEV_IO_DR_PRT15_DR_15_ALIAS, 0x4000508f\r
+.set CYDEV_IO_PS_BASE, 0x40005090\r
+.set CYDEV_IO_PS_SIZE, 0x00000010\r
+.set CYDEV_IO_PS_PRT0_BASE, 0x40005090\r
+.set CYDEV_IO_PS_PRT0_SIZE, 0x00000001\r
+.set CYDEV_IO_PS_PRT0_PS_ALIAS, 0x40005090\r
+.set CYDEV_IO_PS_PRT1_BASE, 0x40005091\r
+.set CYDEV_IO_PS_PRT1_SIZE, 0x00000001\r
+.set CYDEV_IO_PS_PRT1_PS_ALIAS, 0x40005091\r
+.set CYDEV_IO_PS_PRT2_BASE, 0x40005092\r
+.set CYDEV_IO_PS_PRT2_SIZE, 0x00000001\r
+.set CYDEV_IO_PS_PRT2_PS_ALIAS, 0x40005092\r
+.set CYDEV_IO_PS_PRT3_BASE, 0x40005093\r
+.set CYDEV_IO_PS_PRT3_SIZE, 0x00000001\r
+.set CYDEV_IO_PS_PRT3_PS_ALIAS, 0x40005093\r
+.set CYDEV_IO_PS_PRT4_BASE, 0x40005094\r
+.set CYDEV_IO_PS_PRT4_SIZE, 0x00000001\r
+.set CYDEV_IO_PS_PRT4_PS_ALIAS, 0x40005094\r
+.set CYDEV_IO_PS_PRT5_BASE, 0x40005095\r
+.set CYDEV_IO_PS_PRT5_SIZE, 0x00000001\r
+.set CYDEV_IO_PS_PRT5_PS_ALIAS, 0x40005095\r
+.set CYDEV_IO_PS_PRT6_BASE, 0x40005096\r
+.set CYDEV_IO_PS_PRT6_SIZE, 0x00000001\r
+.set CYDEV_IO_PS_PRT6_PS_ALIAS, 0x40005096\r
+.set CYDEV_IO_PS_PRT12_BASE, 0x4000509c\r
+.set CYDEV_IO_PS_PRT12_SIZE, 0x00000001\r
+.set CYDEV_IO_PS_PRT12_PS_ALIAS, 0x4000509c\r
+.set CYDEV_IO_PS_PRT15_BASE, 0x4000509f\r
+.set CYDEV_IO_PS_PRT15_SIZE, 0x00000001\r
+.set CYDEV_IO_PS_PRT15_PS15_ALIAS, 0x4000509f\r
+.set CYDEV_IO_PRT_BASE, 0x40005100\r
+.set CYDEV_IO_PRT_SIZE, 0x00000100\r
+.set CYDEV_IO_PRT_PRT0_BASE, 0x40005100\r
+.set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010\r
+.set CYDEV_IO_PRT_PRT0_DR, 0x40005100\r
+.set CYDEV_IO_PRT_PRT0_PS, 0x40005101\r
+.set CYDEV_IO_PRT_PRT0_DM0, 0x40005102\r
+.set CYDEV_IO_PRT_PRT0_DM1, 0x40005103\r
+.set CYDEV_IO_PRT_PRT0_DM2, 0x40005104\r
+.set CYDEV_IO_PRT_PRT0_SLW, 0x40005105\r
+.set CYDEV_IO_PRT_PRT0_BYP, 0x40005106\r
+.set CYDEV_IO_PRT_PRT0_BIE, 0x40005107\r
+.set CYDEV_IO_PRT_PRT0_INP_DIS, 0x40005108\r
+.set CYDEV_IO_PRT_PRT0_CTL, 0x40005109\r
+.set CYDEV_IO_PRT_PRT0_PRT, 0x4000510a\r
+.set CYDEV_IO_PRT_PRT0_BIT_MASK, 0x4000510b\r
+.set CYDEV_IO_PRT_PRT0_AMUX, 0x4000510c\r
+.set CYDEV_IO_PRT_PRT0_AG, 0x4000510d\r
+.set CYDEV_IO_PRT_PRT0_LCD_COM_SEG, 0x4000510e\r
+.set CYDEV_IO_PRT_PRT0_LCD_EN, 0x4000510f\r
+.set CYDEV_IO_PRT_PRT1_BASE, 0x40005110\r
+.set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010\r
+.set CYDEV_IO_PRT_PRT1_DR, 0x40005110\r
+.set CYDEV_IO_PRT_PRT1_PS, 0x40005111\r
+.set CYDEV_IO_PRT_PRT1_DM0, 0x40005112\r
+.set CYDEV_IO_PRT_PRT1_DM1, 0x40005113\r
+.set CYDEV_IO_PRT_PRT1_DM2, 0x40005114\r
+.set CYDEV_IO_PRT_PRT1_SLW, 0x40005115\r
+.set CYDEV_IO_PRT_PRT1_BYP, 0x40005116\r
+.set CYDEV_IO_PRT_PRT1_BIE, 0x40005117\r
+.set CYDEV_IO_PRT_PRT1_INP_DIS, 0x40005118\r
+.set CYDEV_IO_PRT_PRT1_CTL, 0x40005119\r
+.set CYDEV_IO_PRT_PRT1_PRT, 0x4000511a\r
+.set CYDEV_IO_PRT_PRT1_BIT_MASK, 0x4000511b\r
+.set CYDEV_IO_PRT_PRT1_AMUX, 0x4000511c\r
+.set CYDEV_IO_PRT_PRT1_AG, 0x4000511d\r
+.set CYDEV_IO_PRT_PRT1_LCD_COM_SEG, 0x4000511e\r
+.set CYDEV_IO_PRT_PRT1_LCD_EN, 0x4000511f\r
+.set CYDEV_IO_PRT_PRT2_BASE, 0x40005120\r
+.set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010\r
+.set CYDEV_IO_PRT_PRT2_DR, 0x40005120\r
+.set CYDEV_IO_PRT_PRT2_PS, 0x40005121\r
+.set CYDEV_IO_PRT_PRT2_DM0, 0x40005122\r
+.set CYDEV_IO_PRT_PRT2_DM1, 0x40005123\r
+.set CYDEV_IO_PRT_PRT2_DM2, 0x40005124\r
+.set CYDEV_IO_PRT_PRT2_SLW, 0x40005125\r
+.set CYDEV_IO_PRT_PRT2_BYP, 0x40005126\r
+.set CYDEV_IO_PRT_PRT2_BIE, 0x40005127\r
+.set CYDEV_IO_PRT_PRT2_INP_DIS, 0x40005128\r
+.set CYDEV_IO_PRT_PRT2_CTL, 0x40005129\r
+.set CYDEV_IO_PRT_PRT2_PRT, 0x4000512a\r
+.set CYDEV_IO_PRT_PRT2_BIT_MASK, 0x4000512b\r
+.set CYDEV_IO_PRT_PRT2_AMUX, 0x4000512c\r
+.set CYDEV_IO_PRT_PRT2_AG, 0x4000512d\r
+.set CYDEV_IO_PRT_PRT2_LCD_COM_SEG, 0x4000512e\r
+.set CYDEV_IO_PRT_PRT2_LCD_EN, 0x4000512f\r
+.set CYDEV_IO_PRT_PRT3_BASE, 0x40005130\r
+.set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010\r
+.set CYDEV_IO_PRT_PRT3_DR, 0x40005130\r
+.set CYDEV_IO_PRT_PRT3_PS, 0x40005131\r
+.set CYDEV_IO_PRT_PRT3_DM0, 0x40005132\r
+.set CYDEV_IO_PRT_PRT3_DM1, 0x40005133\r
+.set CYDEV_IO_PRT_PRT3_DM2, 0x40005134\r
+.set CYDEV_IO_PRT_PRT3_SLW, 0x40005135\r
+.set CYDEV_IO_PRT_PRT3_BYP, 0x40005136\r
+.set CYDEV_IO_PRT_PRT3_BIE, 0x40005137\r
+.set CYDEV_IO_PRT_PRT3_INP_DIS, 0x40005138\r
+.set CYDEV_IO_PRT_PRT3_CTL, 0x40005139\r
+.set CYDEV_IO_PRT_PRT3_PRT, 0x4000513a\r
+.set CYDEV_IO_PRT_PRT3_BIT_MASK, 0x4000513b\r
+.set CYDEV_IO_PRT_PRT3_AMUX, 0x4000513c\r
+.set CYDEV_IO_PRT_PRT3_AG, 0x4000513d\r
+.set CYDEV_IO_PRT_PRT3_LCD_COM_SEG, 0x4000513e\r
+.set CYDEV_IO_PRT_PRT3_LCD_EN, 0x4000513f\r
+.set CYDEV_IO_PRT_PRT4_BASE, 0x40005140\r
+.set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010\r
+.set CYDEV_IO_PRT_PRT4_DR, 0x40005140\r
+.set CYDEV_IO_PRT_PRT4_PS, 0x40005141\r
+.set CYDEV_IO_PRT_PRT4_DM0, 0x40005142\r
+.set CYDEV_IO_PRT_PRT4_DM1, 0x40005143\r
+.set CYDEV_IO_PRT_PRT4_DM2, 0x40005144\r
+.set CYDEV_IO_PRT_PRT4_SLW, 0x40005145\r
+.set CYDEV_IO_PRT_PRT4_BYP, 0x40005146\r
+.set CYDEV_IO_PRT_PRT4_BIE, 0x40005147\r
+.set CYDEV_IO_PRT_PRT4_INP_DIS, 0x40005148\r
+.set CYDEV_IO_PRT_PRT4_CTL, 0x40005149\r
+.set CYDEV_IO_PRT_PRT4_PRT, 0x4000514a\r
+.set CYDEV_IO_PRT_PRT4_BIT_MASK, 0x4000514b\r
+.set CYDEV_IO_PRT_PRT4_AMUX, 0x4000514c\r
+.set CYDEV_IO_PRT_PRT4_AG, 0x4000514d\r
+.set CYDEV_IO_PRT_PRT4_LCD_COM_SEG, 0x4000514e\r
+.set CYDEV_IO_PRT_PRT4_LCD_EN, 0x4000514f\r
+.set CYDEV_IO_PRT_PRT5_BASE, 0x40005150\r
+.set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010\r
+.set CYDEV_IO_PRT_PRT5_DR, 0x40005150\r
+.set CYDEV_IO_PRT_PRT5_PS, 0x40005151\r
+.set CYDEV_IO_PRT_PRT5_DM0, 0x40005152\r
+.set CYDEV_IO_PRT_PRT5_DM1, 0x40005153\r
+.set CYDEV_IO_PRT_PRT5_DM2, 0x40005154\r
+.set CYDEV_IO_PRT_PRT5_SLW, 0x40005155\r
+.set CYDEV_IO_PRT_PRT5_BYP, 0x40005156\r
+.set CYDEV_IO_PRT_PRT5_BIE, 0x40005157\r
+.set CYDEV_IO_PRT_PRT5_INP_DIS, 0x40005158\r
+.set CYDEV_IO_PRT_PRT5_CTL, 0x40005159\r
+.set CYDEV_IO_PRT_PRT5_PRT, 0x4000515a\r
+.set CYDEV_IO_PRT_PRT5_BIT_MASK, 0x4000515b\r
+.set CYDEV_IO_PRT_PRT5_AMUX, 0x4000515c\r
+.set CYDEV_IO_PRT_PRT5_AG, 0x4000515d\r
+.set CYDEV_IO_PRT_PRT5_LCD_COM_SEG, 0x4000515e\r
+.set CYDEV_IO_PRT_PRT5_LCD_EN, 0x4000515f\r
+.set CYDEV_IO_PRT_PRT6_BASE, 0x40005160\r
+.set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010\r
+.set CYDEV_IO_PRT_PRT6_DR, 0x40005160\r
+.set CYDEV_IO_PRT_PRT6_PS, 0x40005161\r
+.set CYDEV_IO_PRT_PRT6_DM0, 0x40005162\r
+.set CYDEV_IO_PRT_PRT6_DM1, 0x40005163\r
+.set CYDEV_IO_PRT_PRT6_DM2, 0x40005164\r
+.set CYDEV_IO_PRT_PRT6_SLW, 0x40005165\r
+.set CYDEV_IO_PRT_PRT6_BYP, 0x40005166\r
+.set CYDEV_IO_PRT_PRT6_BIE, 0x40005167\r
+.set CYDEV_IO_PRT_PRT6_INP_DIS, 0x40005168\r
+.set CYDEV_IO_PRT_PRT6_CTL, 0x40005169\r
+.set CYDEV_IO_PRT_PRT6_PRT, 0x4000516a\r
+.set CYDEV_IO_PRT_PRT6_BIT_MASK, 0x4000516b\r
+.set CYDEV_IO_PRT_PRT6_AMUX, 0x4000516c\r
+.set CYDEV_IO_PRT_PRT6_AG, 0x4000516d\r
+.set CYDEV_IO_PRT_PRT6_LCD_COM_SEG, 0x4000516e\r
+.set CYDEV_IO_PRT_PRT6_LCD_EN, 0x4000516f\r
+.set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0\r
+.set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010\r
+.set CYDEV_IO_PRT_PRT12_DR, 0x400051c0\r
+.set CYDEV_IO_PRT_PRT12_PS, 0x400051c1\r
+.set CYDEV_IO_PRT_PRT12_DM0, 0x400051c2\r
+.set CYDEV_IO_PRT_PRT12_DM1, 0x400051c3\r
+.set CYDEV_IO_PRT_PRT12_DM2, 0x400051c4\r
+.set CYDEV_IO_PRT_PRT12_SLW, 0x400051c5\r
+.set CYDEV_IO_PRT_PRT12_BYP, 0x400051c6\r
+.set CYDEV_IO_PRT_PRT12_BIE, 0x400051c7\r
+.set CYDEV_IO_PRT_PRT12_INP_DIS, 0x400051c8\r
+.set CYDEV_IO_PRT_PRT12_SIO_HYST_EN, 0x400051c9\r
+.set CYDEV_IO_PRT_PRT12_PRT, 0x400051ca\r
+.set CYDEV_IO_PRT_PRT12_BIT_MASK, 0x400051cb\r
+.set CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ, 0x400051cc\r
+.set CYDEV_IO_PRT_PRT12_AG, 0x400051cd\r
+.set CYDEV_IO_PRT_PRT12_SIO_CFG, 0x400051ce\r
+.set CYDEV_IO_PRT_PRT12_SIO_DIFF, 0x400051cf\r
+.set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0\r
+.set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010\r
+.set CYDEV_IO_PRT_PRT15_DR, 0x400051f0\r
+.set CYDEV_IO_PRT_PRT15_PS, 0x400051f1\r
+.set CYDEV_IO_PRT_PRT15_DM0, 0x400051f2\r
+.set CYDEV_IO_PRT_PRT15_DM1, 0x400051f3\r
+.set CYDEV_IO_PRT_PRT15_DM2, 0x400051f4\r
+.set CYDEV_IO_PRT_PRT15_SLW, 0x400051f5\r
+.set CYDEV_IO_PRT_PRT15_BYP, 0x400051f6\r
+.set CYDEV_IO_PRT_PRT15_BIE, 0x400051f7\r
+.set CYDEV_IO_PRT_PRT15_INP_DIS, 0x400051f8\r
+.set CYDEV_IO_PRT_PRT15_CTL, 0x400051f9\r
+.set CYDEV_IO_PRT_PRT15_PRT, 0x400051fa\r
+.set CYDEV_IO_PRT_PRT15_BIT_MASK, 0x400051fb\r
+.set CYDEV_IO_PRT_PRT15_AMUX, 0x400051fc\r
+.set CYDEV_IO_PRT_PRT15_AG, 0x400051fd\r
+.set CYDEV_IO_PRT_PRT15_LCD_COM_SEG, 0x400051fe\r
+.set CYDEV_IO_PRT_PRT15_LCD_EN, 0x400051ff\r
+.set CYDEV_PRTDSI_BASE, 0x40005200\r
+.set CYDEV_PRTDSI_SIZE, 0x0000007f\r
+.set CYDEV_PRTDSI_PRT0_BASE, 0x40005200\r
+.set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007\r
+.set CYDEV_PRTDSI_PRT0_OUT_SEL0, 0x40005200\r
+.set CYDEV_PRTDSI_PRT0_OUT_SEL1, 0x40005201\r
+.set CYDEV_PRTDSI_PRT0_OE_SEL0, 0x40005202\r
+.set CYDEV_PRTDSI_PRT0_OE_SEL1, 0x40005203\r
+.set CYDEV_PRTDSI_PRT0_DBL_SYNC_IN, 0x40005204\r
+.set CYDEV_PRTDSI_PRT0_SYNC_OUT, 0x40005205\r
+.set CYDEV_PRTDSI_PRT0_CAPS_SEL, 0x40005206\r
+.set CYDEV_PRTDSI_PRT1_BASE, 0x40005208\r
+.set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007\r
+.set CYDEV_PRTDSI_PRT1_OUT_SEL0, 0x40005208\r
+.set CYDEV_PRTDSI_PRT1_OUT_SEL1, 0x40005209\r
+.set CYDEV_PRTDSI_PRT1_OE_SEL0, 0x4000520a\r
+.set CYDEV_PRTDSI_PRT1_OE_SEL1, 0x4000520b\r
+.set CYDEV_PRTDSI_PRT1_DBL_SYNC_IN, 0x4000520c\r
+.set CYDEV_PRTDSI_PRT1_SYNC_OUT, 0x4000520d\r
+.set CYDEV_PRTDSI_PRT1_CAPS_SEL, 0x4000520e\r
+.set CYDEV_PRTDSI_PRT2_BASE, 0x40005210\r
+.set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007\r
+.set CYDEV_PRTDSI_PRT2_OUT_SEL0, 0x40005210\r
+.set CYDEV_PRTDSI_PRT2_OUT_SEL1, 0x40005211\r
+.set CYDEV_PRTDSI_PRT2_OE_SEL0, 0x40005212\r
+.set CYDEV_PRTDSI_PRT2_OE_SEL1, 0x40005213\r
+.set CYDEV_PRTDSI_PRT2_DBL_SYNC_IN, 0x40005214\r
+.set CYDEV_PRTDSI_PRT2_SYNC_OUT, 0x40005215\r
+.set CYDEV_PRTDSI_PRT2_CAPS_SEL, 0x40005216\r
+.set CYDEV_PRTDSI_PRT3_BASE, 0x40005218\r
+.set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007\r
+.set CYDEV_PRTDSI_PRT3_OUT_SEL0, 0x40005218\r
+.set CYDEV_PRTDSI_PRT3_OUT_SEL1, 0x40005219\r
+.set CYDEV_PRTDSI_PRT3_OE_SEL0, 0x4000521a\r
+.set CYDEV_PRTDSI_PRT3_OE_SEL1, 0x4000521b\r
+.set CYDEV_PRTDSI_PRT3_DBL_SYNC_IN, 0x4000521c\r
+.set CYDEV_PRTDSI_PRT3_SYNC_OUT, 0x4000521d\r
+.set CYDEV_PRTDSI_PRT3_CAPS_SEL, 0x4000521e\r
+.set CYDEV_PRTDSI_PRT4_BASE, 0x40005220\r
+.set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007\r
+.set CYDEV_PRTDSI_PRT4_OUT_SEL0, 0x40005220\r
+.set CYDEV_PRTDSI_PRT4_OUT_SEL1, 0x40005221\r
+.set CYDEV_PRTDSI_PRT4_OE_SEL0, 0x40005222\r
+.set CYDEV_PRTDSI_PRT4_OE_SEL1, 0x40005223\r
+.set CYDEV_PRTDSI_PRT4_DBL_SYNC_IN, 0x40005224\r
+.set CYDEV_PRTDSI_PRT4_SYNC_OUT, 0x40005225\r
+.set CYDEV_PRTDSI_PRT4_CAPS_SEL, 0x40005226\r
+.set CYDEV_PRTDSI_PRT5_BASE, 0x40005228\r
+.set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007\r
+.set CYDEV_PRTDSI_PRT5_OUT_SEL0, 0x40005228\r
+.set CYDEV_PRTDSI_PRT5_OUT_SEL1, 0x40005229\r
+.set CYDEV_PRTDSI_PRT5_OE_SEL0, 0x4000522a\r
+.set CYDEV_PRTDSI_PRT5_OE_SEL1, 0x4000522b\r
+.set CYDEV_PRTDSI_PRT5_DBL_SYNC_IN, 0x4000522c\r
+.set CYDEV_PRTDSI_PRT5_SYNC_OUT, 0x4000522d\r
+.set CYDEV_PRTDSI_PRT5_CAPS_SEL, 0x4000522e\r
+.set CYDEV_PRTDSI_PRT6_BASE, 0x40005230\r
+.set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007\r
+.set CYDEV_PRTDSI_PRT6_OUT_SEL0, 0x40005230\r
+.set CYDEV_PRTDSI_PRT6_OUT_SEL1, 0x40005231\r
+.set CYDEV_PRTDSI_PRT6_OE_SEL0, 0x40005232\r
+.set CYDEV_PRTDSI_PRT6_OE_SEL1, 0x40005233\r
+.set CYDEV_PRTDSI_PRT6_DBL_SYNC_IN, 0x40005234\r
+.set CYDEV_PRTDSI_PRT6_SYNC_OUT, 0x40005235\r
+.set CYDEV_PRTDSI_PRT6_CAPS_SEL, 0x40005236\r
+.set CYDEV_PRTDSI_PRT12_BASE, 0x40005260\r
+.set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006\r
+.set CYDEV_PRTDSI_PRT12_OUT_SEL0, 0x40005260\r
+.set CYDEV_PRTDSI_PRT12_OUT_SEL1, 0x40005261\r
+.set CYDEV_PRTDSI_PRT12_OE_SEL0, 0x40005262\r
+.set CYDEV_PRTDSI_PRT12_OE_SEL1, 0x40005263\r
+.set CYDEV_PRTDSI_PRT12_DBL_SYNC_IN, 0x40005264\r
+.set CYDEV_PRTDSI_PRT12_SYNC_OUT, 0x40005265\r
+.set CYDEV_PRTDSI_PRT15_BASE, 0x40005278\r
+.set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007\r
+.set CYDEV_PRTDSI_PRT15_OUT_SEL0, 0x40005278\r
+.set CYDEV_PRTDSI_PRT15_OUT_SEL1, 0x40005279\r
+.set CYDEV_PRTDSI_PRT15_OE_SEL0, 0x4000527a\r
+.set CYDEV_PRTDSI_PRT15_OE_SEL1, 0x4000527b\r
+.set CYDEV_PRTDSI_PRT15_DBL_SYNC_IN, 0x4000527c\r
+.set CYDEV_PRTDSI_PRT15_SYNC_OUT, 0x4000527d\r
+.set CYDEV_PRTDSI_PRT15_CAPS_SEL, 0x4000527e\r
+.set CYDEV_EMIF_BASE, 0x40005400\r
+.set CYDEV_EMIF_SIZE, 0x00000007\r
+.set CYDEV_EMIF_NO_UDB, 0x40005400\r
+.set CYDEV_EMIF_RP_WAIT_STATES, 0x40005401\r
+.set CYDEV_EMIF_MEM_DWN, 0x40005402\r
+.set CYDEV_EMIF_MEMCLK_DIV, 0x40005403\r
+.set CYDEV_EMIF_CLOCK_EN, 0x40005404\r
+.set CYDEV_EMIF_EM_TYPE, 0x40005405\r
+.set CYDEV_EMIF_WP_WAIT_STATES, 0x40005406\r
+.set CYDEV_ANAIF_BASE, 0x40005800\r
+.set CYDEV_ANAIF_SIZE, 0x000003a9\r
+.set CYDEV_ANAIF_CFG_BASE, 0x40005800\r
+.set CYDEV_ANAIF_CFG_SIZE, 0x0000010f\r
+.set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800\r
+.set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003\r
+.set CYDEV_ANAIF_CFG_SC0_CR0, 0x40005800\r
+.set CYDEV_ANAIF_CFG_SC0_CR1, 0x40005801\r
+.set CYDEV_ANAIF_CFG_SC0_CR2, 0x40005802\r
+.set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804\r
+.set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003\r
+.set CYDEV_ANAIF_CFG_SC1_CR0, 0x40005804\r
+.set CYDEV_ANAIF_CFG_SC1_CR1, 0x40005805\r
+.set CYDEV_ANAIF_CFG_SC1_CR2, 0x40005806\r
+.set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808\r
+.set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003\r
+.set CYDEV_ANAIF_CFG_SC2_CR0, 0x40005808\r
+.set CYDEV_ANAIF_CFG_SC2_CR1, 0x40005809\r
+.set CYDEV_ANAIF_CFG_SC2_CR2, 0x4000580a\r
+.set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c\r
+.set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003\r
+.set CYDEV_ANAIF_CFG_SC3_CR0, 0x4000580c\r
+.set CYDEV_ANAIF_CFG_SC3_CR1, 0x4000580d\r
+.set CYDEV_ANAIF_CFG_SC3_CR2, 0x4000580e\r
+.set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820\r
+.set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003\r
+.set CYDEV_ANAIF_CFG_DAC0_CR0, 0x40005820\r
+.set CYDEV_ANAIF_CFG_DAC0_CR1, 0x40005821\r
+.set CYDEV_ANAIF_CFG_DAC0_TST, 0x40005822\r
+.set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824\r
+.set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003\r
+.set CYDEV_ANAIF_CFG_DAC1_CR0, 0x40005824\r
+.set CYDEV_ANAIF_CFG_DAC1_CR1, 0x40005825\r
+.set CYDEV_ANAIF_CFG_DAC1_TST, 0x40005826\r
+.set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828\r
+.set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003\r
+.set CYDEV_ANAIF_CFG_DAC2_CR0, 0x40005828\r
+.set CYDEV_ANAIF_CFG_DAC2_CR1, 0x40005829\r
+.set CYDEV_ANAIF_CFG_DAC2_TST, 0x4000582a\r
+.set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c\r
+.set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003\r
+.set CYDEV_ANAIF_CFG_DAC3_CR0, 0x4000582c\r
+.set CYDEV_ANAIF_CFG_DAC3_CR1, 0x4000582d\r
+.set CYDEV_ANAIF_CFG_DAC3_TST, 0x4000582e\r
+.set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840\r
+.set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001\r
+.set CYDEV_ANAIF_CFG_CMP0_CR, 0x40005840\r
+.set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841\r
+.set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001\r
+.set CYDEV_ANAIF_CFG_CMP1_CR, 0x40005841\r
+.set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842\r
+.set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001\r
+.set CYDEV_ANAIF_CFG_CMP2_CR, 0x40005842\r
+.set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843\r
+.set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001\r
+.set CYDEV_ANAIF_CFG_CMP3_CR, 0x40005843\r
+.set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848\r
+.set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_CFG_LUT0_CR, 0x40005848\r
+.set CYDEV_ANAIF_CFG_LUT0_MX, 0x40005849\r
+.set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a\r
+.set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_CFG_LUT1_CR, 0x4000584a\r
+.set CYDEV_ANAIF_CFG_LUT1_MX, 0x4000584b\r
+.set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c\r
+.set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_CFG_LUT2_CR, 0x4000584c\r
+.set CYDEV_ANAIF_CFG_LUT2_MX, 0x4000584d\r
+.set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e\r
+.set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_CFG_LUT3_CR, 0x4000584e\r
+.set CYDEV_ANAIF_CFG_LUT3_MX, 0x4000584f\r
+.set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858\r
+.set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_CFG_OPAMP0_CR, 0x40005858\r
+.set CYDEV_ANAIF_CFG_OPAMP0_RSVD, 0x40005859\r
+.set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a\r
+.set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_CFG_OPAMP1_CR, 0x4000585a\r
+.set CYDEV_ANAIF_CFG_OPAMP1_RSVD, 0x4000585b\r
+.set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c\r
+.set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_CFG_OPAMP2_CR, 0x4000585c\r
+.set CYDEV_ANAIF_CFG_OPAMP2_RSVD, 0x4000585d\r
+.set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e\r
+.set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_CFG_OPAMP3_CR, 0x4000585e\r
+.set CYDEV_ANAIF_CFG_OPAMP3_RSVD, 0x4000585f\r
+.set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868\r
+.set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_CFG_LCDDAC_CR0, 0x40005868\r
+.set CYDEV_ANAIF_CFG_LCDDAC_CR1, 0x40005869\r
+.set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a\r
+.set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001\r
+.set CYDEV_ANAIF_CFG_LCDDRV_CR, 0x4000586a\r
+.set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b\r
+.set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001\r
+.set CYDEV_ANAIF_CFG_LCDTMR_CFG, 0x4000586b\r
+.set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c\r
+.set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004\r
+.set CYDEV_ANAIF_CFG_BG_CR0, 0x4000586c\r
+.set CYDEV_ANAIF_CFG_BG_RSVD, 0x4000586d\r
+.set CYDEV_ANAIF_CFG_BG_DFT0, 0x4000586e\r
+.set CYDEV_ANAIF_CFG_BG_DFT1, 0x4000586f\r
+.set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870\r
+.set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_CFG_CAPSL_CFG0, 0x40005870\r
+.set CYDEV_ANAIF_CFG_CAPSL_CFG1, 0x40005871\r
+.set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872\r
+.set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_CFG_CAPSR_CFG0, 0x40005872\r
+.set CYDEV_ANAIF_CFG_CAPSR_CFG1, 0x40005873\r
+.set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876\r
+.set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_CFG_PUMP_CR0, 0x40005876\r
+.set CYDEV_ANAIF_CFG_PUMP_CR1, 0x40005877\r
+.set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878\r
+.set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_CFG_LPF0_CR0, 0x40005878\r
+.set CYDEV_ANAIF_CFG_LPF0_RSVD, 0x40005879\r
+.set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a\r
+.set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_CFG_LPF1_CR0, 0x4000587a\r
+.set CYDEV_ANAIF_CFG_LPF1_RSVD, 0x4000587b\r
+.set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c\r
+.set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001\r
+.set CYDEV_ANAIF_CFG_MISC_CR0, 0x4000587c\r
+.set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880\r
+.set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020\r
+.set CYDEV_ANAIF_CFG_DSM0_CR0, 0x40005880\r
+.set CYDEV_ANAIF_CFG_DSM0_CR1, 0x40005881\r
+.set CYDEV_ANAIF_CFG_DSM0_CR2, 0x40005882\r
+.set CYDEV_ANAIF_CFG_DSM0_CR3, 0x40005883\r
+.set CYDEV_ANAIF_CFG_DSM0_CR4, 0x40005884\r
+.set CYDEV_ANAIF_CFG_DSM0_CR5, 0x40005885\r
+.set CYDEV_ANAIF_CFG_DSM0_CR6, 0x40005886\r
+.set CYDEV_ANAIF_CFG_DSM0_CR7, 0x40005887\r
+.set CYDEV_ANAIF_CFG_DSM0_CR8, 0x40005888\r
+.set CYDEV_ANAIF_CFG_DSM0_CR9, 0x40005889\r
+.set CYDEV_ANAIF_CFG_DSM0_CR10, 0x4000588a\r
+.set CYDEV_ANAIF_CFG_DSM0_CR11, 0x4000588b\r
+.set CYDEV_ANAIF_CFG_DSM0_CR12, 0x4000588c\r
+.set CYDEV_ANAIF_CFG_DSM0_CR13, 0x4000588d\r
+.set CYDEV_ANAIF_CFG_DSM0_CR14, 0x4000588e\r
+.set CYDEV_ANAIF_CFG_DSM0_CR15, 0x4000588f\r
+.set CYDEV_ANAIF_CFG_DSM0_CR16, 0x40005890\r
+.set CYDEV_ANAIF_CFG_DSM0_CR17, 0x40005891\r
+.set CYDEV_ANAIF_CFG_DSM0_REF0, 0x40005892\r
+.set CYDEV_ANAIF_CFG_DSM0_REF1, 0x40005893\r
+.set CYDEV_ANAIF_CFG_DSM0_REF2, 0x40005894\r
+.set CYDEV_ANAIF_CFG_DSM0_REF3, 0x40005895\r
+.set CYDEV_ANAIF_CFG_DSM0_DEM0, 0x40005896\r
+.set CYDEV_ANAIF_CFG_DSM0_DEM1, 0x40005897\r
+.set CYDEV_ANAIF_CFG_DSM0_TST0, 0x40005898\r
+.set CYDEV_ANAIF_CFG_DSM0_TST1, 0x40005899\r
+.set CYDEV_ANAIF_CFG_DSM0_BUF0, 0x4000589a\r
+.set CYDEV_ANAIF_CFG_DSM0_BUF1, 0x4000589b\r
+.set CYDEV_ANAIF_CFG_DSM0_BUF2, 0x4000589c\r
+.set CYDEV_ANAIF_CFG_DSM0_BUF3, 0x4000589d\r
+.set CYDEV_ANAIF_CFG_DSM0_MISC, 0x4000589e\r
+.set CYDEV_ANAIF_CFG_DSM0_RSVD1, 0x4000589f\r
+.set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900\r
+.set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007\r
+.set CYDEV_ANAIF_CFG_SAR0_CSR0, 0x40005900\r
+.set CYDEV_ANAIF_CFG_SAR0_CSR1, 0x40005901\r
+.set CYDEV_ANAIF_CFG_SAR0_CSR2, 0x40005902\r
+.set CYDEV_ANAIF_CFG_SAR0_CSR3, 0x40005903\r
+.set CYDEV_ANAIF_CFG_SAR0_CSR4, 0x40005904\r
+.set CYDEV_ANAIF_CFG_SAR0_CSR5, 0x40005905\r
+.set CYDEV_ANAIF_CFG_SAR0_CSR6, 0x40005906\r
+.set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908\r
+.set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007\r
+.set CYDEV_ANAIF_CFG_SAR1_CSR0, 0x40005908\r
+.set CYDEV_ANAIF_CFG_SAR1_CSR1, 0x40005909\r
+.set CYDEV_ANAIF_CFG_SAR1_CSR2, 0x4000590a\r
+.set CYDEV_ANAIF_CFG_SAR1_CSR3, 0x4000590b\r
+.set CYDEV_ANAIF_CFG_SAR1_CSR4, 0x4000590c\r
+.set CYDEV_ANAIF_CFG_SAR1_CSR5, 0x4000590d\r
+.set CYDEV_ANAIF_CFG_SAR1_CSR6, 0x4000590e\r
+.set CYDEV_ANAIF_RT_BASE, 0x40005a00\r
+.set CYDEV_ANAIF_RT_SIZE, 0x00000162\r
+.set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00\r
+.set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d\r
+.set CYDEV_ANAIF_RT_SC0_SW0, 0x40005a00\r
+.set CYDEV_ANAIF_RT_SC0_SW2, 0x40005a02\r
+.set CYDEV_ANAIF_RT_SC0_SW3, 0x40005a03\r
+.set CYDEV_ANAIF_RT_SC0_SW4, 0x40005a04\r
+.set CYDEV_ANAIF_RT_SC0_SW6, 0x40005a06\r
+.set CYDEV_ANAIF_RT_SC0_SW7, 0x40005a07\r
+.set CYDEV_ANAIF_RT_SC0_SW8, 0x40005a08\r
+.set CYDEV_ANAIF_RT_SC0_SW10, 0x40005a0a\r
+.set CYDEV_ANAIF_RT_SC0_CLK, 0x40005a0b\r
+.set CYDEV_ANAIF_RT_SC0_BST, 0x40005a0c\r
+.set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10\r
+.set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d\r
+.set CYDEV_ANAIF_RT_SC1_SW0, 0x40005a10\r
+.set CYDEV_ANAIF_RT_SC1_SW2, 0x40005a12\r
+.set CYDEV_ANAIF_RT_SC1_SW3, 0x40005a13\r
+.set CYDEV_ANAIF_RT_SC1_SW4, 0x40005a14\r
+.set CYDEV_ANAIF_RT_SC1_SW6, 0x40005a16\r
+.set CYDEV_ANAIF_RT_SC1_SW7, 0x40005a17\r
+.set CYDEV_ANAIF_RT_SC1_SW8, 0x40005a18\r
+.set CYDEV_ANAIF_RT_SC1_SW10, 0x40005a1a\r
+.set CYDEV_ANAIF_RT_SC1_CLK, 0x40005a1b\r
+.set CYDEV_ANAIF_RT_SC1_BST, 0x40005a1c\r
+.set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20\r
+.set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d\r
+.set CYDEV_ANAIF_RT_SC2_SW0, 0x40005a20\r
+.set CYDEV_ANAIF_RT_SC2_SW2, 0x40005a22\r
+.set CYDEV_ANAIF_RT_SC2_SW3, 0x40005a23\r
+.set CYDEV_ANAIF_RT_SC2_SW4, 0x40005a24\r
+.set CYDEV_ANAIF_RT_SC2_SW6, 0x40005a26\r
+.set CYDEV_ANAIF_RT_SC2_SW7, 0x40005a27\r
+.set CYDEV_ANAIF_RT_SC2_SW8, 0x40005a28\r
+.set CYDEV_ANAIF_RT_SC2_SW10, 0x40005a2a\r
+.set CYDEV_ANAIF_RT_SC2_CLK, 0x40005a2b\r
+.set CYDEV_ANAIF_RT_SC2_BST, 0x40005a2c\r
+.set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30\r
+.set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d\r
+.set CYDEV_ANAIF_RT_SC3_SW0, 0x40005a30\r
+.set CYDEV_ANAIF_RT_SC3_SW2, 0x40005a32\r
+.set CYDEV_ANAIF_RT_SC3_SW3, 0x40005a33\r
+.set CYDEV_ANAIF_RT_SC3_SW4, 0x40005a34\r
+.set CYDEV_ANAIF_RT_SC3_SW6, 0x40005a36\r
+.set CYDEV_ANAIF_RT_SC3_SW7, 0x40005a37\r
+.set CYDEV_ANAIF_RT_SC3_SW8, 0x40005a38\r
+.set CYDEV_ANAIF_RT_SC3_SW10, 0x40005a3a\r
+.set CYDEV_ANAIF_RT_SC3_CLK, 0x40005a3b\r
+.set CYDEV_ANAIF_RT_SC3_BST, 0x40005a3c\r
+.set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80\r
+.set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008\r
+.set CYDEV_ANAIF_RT_DAC0_SW0, 0x40005a80\r
+.set CYDEV_ANAIF_RT_DAC0_SW2, 0x40005a82\r
+.set CYDEV_ANAIF_RT_DAC0_SW3, 0x40005a83\r
+.set CYDEV_ANAIF_RT_DAC0_SW4, 0x40005a84\r
+.set CYDEV_ANAIF_RT_DAC0_STROBE, 0x40005a87\r
+.set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88\r
+.set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008\r
+.set CYDEV_ANAIF_RT_DAC1_SW0, 0x40005a88\r
+.set CYDEV_ANAIF_RT_DAC1_SW2, 0x40005a8a\r
+.set CYDEV_ANAIF_RT_DAC1_SW3, 0x40005a8b\r
+.set CYDEV_ANAIF_RT_DAC1_SW4, 0x40005a8c\r
+.set CYDEV_ANAIF_RT_DAC1_STROBE, 0x40005a8f\r
+.set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90\r
+.set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008\r
+.set CYDEV_ANAIF_RT_DAC2_SW0, 0x40005a90\r
+.set CYDEV_ANAIF_RT_DAC2_SW2, 0x40005a92\r
+.set CYDEV_ANAIF_RT_DAC2_SW3, 0x40005a93\r
+.set CYDEV_ANAIF_RT_DAC2_SW4, 0x40005a94\r
+.set CYDEV_ANAIF_RT_DAC2_STROBE, 0x40005a97\r
+.set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98\r
+.set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008\r
+.set CYDEV_ANAIF_RT_DAC3_SW0, 0x40005a98\r
+.set CYDEV_ANAIF_RT_DAC3_SW2, 0x40005a9a\r
+.set CYDEV_ANAIF_RT_DAC3_SW3, 0x40005a9b\r
+.set CYDEV_ANAIF_RT_DAC3_SW4, 0x40005a9c\r
+.set CYDEV_ANAIF_RT_DAC3_STROBE, 0x40005a9f\r
+.set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0\r
+.set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008\r
+.set CYDEV_ANAIF_RT_CMP0_SW0, 0x40005ac0\r
+.set CYDEV_ANAIF_RT_CMP0_SW2, 0x40005ac2\r
+.set CYDEV_ANAIF_RT_CMP0_SW3, 0x40005ac3\r
+.set CYDEV_ANAIF_RT_CMP0_SW4, 0x40005ac4\r
+.set CYDEV_ANAIF_RT_CMP0_SW6, 0x40005ac6\r
+.set CYDEV_ANAIF_RT_CMP0_CLK, 0x40005ac7\r
+.set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8\r
+.set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008\r
+.set CYDEV_ANAIF_RT_CMP1_SW0, 0x40005ac8\r
+.set CYDEV_ANAIF_RT_CMP1_SW2, 0x40005aca\r
+.set CYDEV_ANAIF_RT_CMP1_SW3, 0x40005acb\r
+.set CYDEV_ANAIF_RT_CMP1_SW4, 0x40005acc\r
+.set CYDEV_ANAIF_RT_CMP1_SW6, 0x40005ace\r
+.set CYDEV_ANAIF_RT_CMP1_CLK, 0x40005acf\r
+.set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0\r
+.set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008\r
+.set CYDEV_ANAIF_RT_CMP2_SW0, 0x40005ad0\r
+.set CYDEV_ANAIF_RT_CMP2_SW2, 0x40005ad2\r
+.set CYDEV_ANAIF_RT_CMP2_SW3, 0x40005ad3\r
+.set CYDEV_ANAIF_RT_CMP2_SW4, 0x40005ad4\r
+.set CYDEV_ANAIF_RT_CMP2_SW6, 0x40005ad6\r
+.set CYDEV_ANAIF_RT_CMP2_CLK, 0x40005ad7\r
+.set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8\r
+.set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008\r
+.set CYDEV_ANAIF_RT_CMP3_SW0, 0x40005ad8\r
+.set CYDEV_ANAIF_RT_CMP3_SW2, 0x40005ada\r
+.set CYDEV_ANAIF_RT_CMP3_SW3, 0x40005adb\r
+.set CYDEV_ANAIF_RT_CMP3_SW4, 0x40005adc\r
+.set CYDEV_ANAIF_RT_CMP3_SW6, 0x40005ade\r
+.set CYDEV_ANAIF_RT_CMP3_CLK, 0x40005adf\r
+.set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00\r
+.set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008\r
+.set CYDEV_ANAIF_RT_DSM0_SW0, 0x40005b00\r
+.set CYDEV_ANAIF_RT_DSM0_SW2, 0x40005b02\r
+.set CYDEV_ANAIF_RT_DSM0_SW3, 0x40005b03\r
+.set CYDEV_ANAIF_RT_DSM0_SW4, 0x40005b04\r
+.set CYDEV_ANAIF_RT_DSM0_SW6, 0x40005b06\r
+.set CYDEV_ANAIF_RT_DSM0_CLK, 0x40005b07\r
+.set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20\r
+.set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008\r
+.set CYDEV_ANAIF_RT_SAR0_SW0, 0x40005b20\r
+.set CYDEV_ANAIF_RT_SAR0_SW2, 0x40005b22\r
+.set CYDEV_ANAIF_RT_SAR0_SW3, 0x40005b23\r
+.set CYDEV_ANAIF_RT_SAR0_SW4, 0x40005b24\r
+.set CYDEV_ANAIF_RT_SAR0_SW6, 0x40005b26\r
+.set CYDEV_ANAIF_RT_SAR0_CLK, 0x40005b27\r
+.set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28\r
+.set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008\r
+.set CYDEV_ANAIF_RT_SAR1_SW0, 0x40005b28\r
+.set CYDEV_ANAIF_RT_SAR1_SW2, 0x40005b2a\r
+.set CYDEV_ANAIF_RT_SAR1_SW3, 0x40005b2b\r
+.set CYDEV_ANAIF_RT_SAR1_SW4, 0x40005b2c\r
+.set CYDEV_ANAIF_RT_SAR1_SW6, 0x40005b2e\r
+.set CYDEV_ANAIF_RT_SAR1_CLK, 0x40005b2f\r
+.set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40\r
+.set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_RT_OPAMP0_MX, 0x40005b40\r
+.set CYDEV_ANAIF_RT_OPAMP0_SW, 0x40005b41\r
+.set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42\r
+.set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_RT_OPAMP1_MX, 0x40005b42\r
+.set CYDEV_ANAIF_RT_OPAMP1_SW, 0x40005b43\r
+.set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44\r
+.set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_RT_OPAMP2_MX, 0x40005b44\r
+.set CYDEV_ANAIF_RT_OPAMP2_SW, 0x40005b45\r
+.set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46\r
+.set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_RT_OPAMP3_MX, 0x40005b46\r
+.set CYDEV_ANAIF_RT_OPAMP3_SW, 0x40005b47\r
+.set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50\r
+.set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005\r
+.set CYDEV_ANAIF_RT_LCDDAC_SW0, 0x40005b50\r
+.set CYDEV_ANAIF_RT_LCDDAC_SW1, 0x40005b51\r
+.set CYDEV_ANAIF_RT_LCDDAC_SW2, 0x40005b52\r
+.set CYDEV_ANAIF_RT_LCDDAC_SW3, 0x40005b53\r
+.set CYDEV_ANAIF_RT_LCDDAC_SW4, 0x40005b54\r
+.set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56\r
+.set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001\r
+.set CYDEV_ANAIF_RT_SC_MISC, 0x40005b56\r
+.set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58\r
+.set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004\r
+.set CYDEV_ANAIF_RT_BUS_SW0, 0x40005b58\r
+.set CYDEV_ANAIF_RT_BUS_SW2, 0x40005b5a\r
+.set CYDEV_ANAIF_RT_BUS_SW3, 0x40005b5b\r
+.set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c\r
+.set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006\r
+.set CYDEV_ANAIF_RT_DFT_CR0, 0x40005b5c\r
+.set CYDEV_ANAIF_RT_DFT_CR1, 0x40005b5d\r
+.set CYDEV_ANAIF_RT_DFT_CR2, 0x40005b5e\r
+.set CYDEV_ANAIF_RT_DFT_CR3, 0x40005b5f\r
+.set CYDEV_ANAIF_RT_DFT_CR4, 0x40005b60\r
+.set CYDEV_ANAIF_RT_DFT_CR5, 0x40005b61\r
+.set CYDEV_ANAIF_WRK_BASE, 0x40005b80\r
+.set CYDEV_ANAIF_WRK_SIZE, 0x00000029\r
+.set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80\r
+.set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001\r
+.set CYDEV_ANAIF_WRK_DAC0_D, 0x40005b80\r
+.set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81\r
+.set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001\r
+.set CYDEV_ANAIF_WRK_DAC1_D, 0x40005b81\r
+.set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82\r
+.set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001\r
+.set CYDEV_ANAIF_WRK_DAC2_D, 0x40005b82\r
+.set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83\r
+.set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001\r
+.set CYDEV_ANAIF_WRK_DAC3_D, 0x40005b83\r
+.set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88\r
+.set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_WRK_DSM0_OUT0, 0x40005b88\r
+.set CYDEV_ANAIF_WRK_DSM0_OUT1, 0x40005b89\r
+.set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90\r
+.set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005\r
+.set CYDEV_ANAIF_WRK_LUT_SR, 0x40005b90\r
+.set CYDEV_ANAIF_WRK_LUT_WRK1, 0x40005b91\r
+.set CYDEV_ANAIF_WRK_LUT_MSK, 0x40005b92\r
+.set CYDEV_ANAIF_WRK_LUT_CLK, 0x40005b93\r
+.set CYDEV_ANAIF_WRK_LUT_CPTR, 0x40005b94\r
+.set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96\r
+.set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_WRK_CMP_WRK, 0x40005b96\r
+.set CYDEV_ANAIF_WRK_CMP_TST, 0x40005b97\r
+.set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98\r
+.set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005\r
+.set CYDEV_ANAIF_WRK_SC_SR, 0x40005b98\r
+.set CYDEV_ANAIF_WRK_SC_WRK1, 0x40005b99\r
+.set CYDEV_ANAIF_WRK_SC_MSK, 0x40005b9a\r
+.set CYDEV_ANAIF_WRK_SC_CMPINV, 0x40005b9b\r
+.set CYDEV_ANAIF_WRK_SC_CPTR, 0x40005b9c\r
+.set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0\r
+.set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_WRK_SAR0_WRK0, 0x40005ba0\r
+.set CYDEV_ANAIF_WRK_SAR0_WRK1, 0x40005ba1\r
+.set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2\r
+.set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002\r
+.set CYDEV_ANAIF_WRK_SAR1_WRK0, 0x40005ba2\r
+.set CYDEV_ANAIF_WRK_SAR1_WRK1, 0x40005ba3\r
+.set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8\r
+.set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001\r
+.set CYDEV_ANAIF_WRK_SARS_SOF, 0x40005ba8\r
+.set CYDEV_USB_BASE, 0x40006000\r
+.set CYDEV_USB_SIZE, 0x00000300\r
+.set CYDEV_USB_EP0_DR0, 0x40006000\r
+.set CYDEV_USB_EP0_DR1, 0x40006001\r
+.set CYDEV_USB_EP0_DR2, 0x40006002\r
+.set CYDEV_USB_EP0_DR3, 0x40006003\r
+.set CYDEV_USB_EP0_DR4, 0x40006004\r
+.set CYDEV_USB_EP0_DR5, 0x40006005\r
+.set CYDEV_USB_EP0_DR6, 0x40006006\r
+.set CYDEV_USB_EP0_DR7, 0x40006007\r
+.set CYDEV_USB_CR0, 0x40006008\r
+.set CYDEV_USB_CR1, 0x40006009\r
+.set CYDEV_USB_SIE_EP_INT_EN, 0x4000600a\r
+.set CYDEV_USB_SIE_EP_INT_SR, 0x4000600b\r
+.set CYDEV_USB_SIE_EP1_BASE, 0x4000600c\r
+.set CYDEV_USB_SIE_EP1_SIZE, 0x00000003\r
+.set CYDEV_USB_SIE_EP1_CNT0, 0x4000600c\r
+.set CYDEV_USB_SIE_EP1_CNT1, 0x4000600d\r
+.set CYDEV_USB_SIE_EP1_CR0, 0x4000600e\r
+.set CYDEV_USB_USBIO_CR0, 0x40006010\r
+.set CYDEV_USB_USBIO_CR1, 0x40006012\r
+.set CYDEV_USB_DYN_RECONFIG, 0x40006014\r
+.set CYDEV_USB_SOF0, 0x40006018\r
+.set CYDEV_USB_SOF1, 0x40006019\r
+.set CYDEV_USB_SIE_EP2_BASE, 0x4000601c\r
+.set CYDEV_USB_SIE_EP2_SIZE, 0x00000003\r
+.set CYDEV_USB_SIE_EP2_CNT0, 0x4000601c\r
+.set CYDEV_USB_SIE_EP2_CNT1, 0x4000601d\r
+.set CYDEV_USB_SIE_EP2_CR0, 0x4000601e\r
+.set CYDEV_USB_EP0_CR, 0x40006028\r
+.set CYDEV_USB_EP0_CNT, 0x40006029\r
+.set CYDEV_USB_SIE_EP3_BASE, 0x4000602c\r
+.set CYDEV_USB_SIE_EP3_SIZE, 0x00000003\r
+.set CYDEV_USB_SIE_EP3_CNT0, 0x4000602c\r
+.set CYDEV_USB_SIE_EP3_CNT1, 0x4000602d\r
+.set CYDEV_USB_SIE_EP3_CR0, 0x4000602e\r
+.set CYDEV_USB_SIE_EP4_BASE, 0x4000603c\r
+.set CYDEV_USB_SIE_EP4_SIZE, 0x00000003\r
+.set CYDEV_USB_SIE_EP4_CNT0, 0x4000603c\r
+.set CYDEV_USB_SIE_EP4_CNT1, 0x4000603d\r
+.set CYDEV_USB_SIE_EP4_CR0, 0x4000603e\r
+.set CYDEV_USB_SIE_EP5_BASE, 0x4000604c\r
+.set CYDEV_USB_SIE_EP5_SIZE, 0x00000003\r
+.set CYDEV_USB_SIE_EP5_CNT0, 0x4000604c\r
+.set CYDEV_USB_SIE_EP5_CNT1, 0x4000604d\r
+.set CYDEV_USB_SIE_EP5_CR0, 0x4000604e\r
+.set CYDEV_USB_SIE_EP6_BASE, 0x4000605c\r
+.set CYDEV_USB_SIE_EP6_SIZE, 0x00000003\r
+.set CYDEV_USB_SIE_EP6_CNT0, 0x4000605c\r
+.set CYDEV_USB_SIE_EP6_CNT1, 0x4000605d\r
+.set CYDEV_USB_SIE_EP6_CR0, 0x4000605e\r
+.set CYDEV_USB_SIE_EP7_BASE, 0x4000606c\r
+.set CYDEV_USB_SIE_EP7_SIZE, 0x00000003\r
+.set CYDEV_USB_SIE_EP7_CNT0, 0x4000606c\r
+.set CYDEV_USB_SIE_EP7_CNT1, 0x4000606d\r
+.set CYDEV_USB_SIE_EP7_CR0, 0x4000606e\r
+.set CYDEV_USB_SIE_EP8_BASE, 0x4000607c\r
+.set CYDEV_USB_SIE_EP8_SIZE, 0x00000003\r
+.set CYDEV_USB_SIE_EP8_CNT0, 0x4000607c\r
+.set CYDEV_USB_SIE_EP8_CNT1, 0x4000607d\r
+.set CYDEV_USB_SIE_EP8_CR0, 0x4000607e\r
+.set CYDEV_USB_ARB_EP1_BASE, 0x40006080\r
+.set CYDEV_USB_ARB_EP1_SIZE, 0x00000003\r
+.set CYDEV_USB_ARB_EP1_CFG, 0x40006080\r
+.set CYDEV_USB_ARB_EP1_INT_EN, 0x40006081\r
+.set CYDEV_USB_ARB_EP1_SR, 0x40006082\r
+.set CYDEV_USB_ARB_RW1_BASE, 0x40006084\r
+.set CYDEV_USB_ARB_RW1_SIZE, 0x00000005\r
+.set CYDEV_USB_ARB_RW1_WA, 0x40006084\r
+.set CYDEV_USB_ARB_RW1_WA_MSB, 0x40006085\r
+.set CYDEV_USB_ARB_RW1_RA, 0x40006086\r
+.set CYDEV_USB_ARB_RW1_RA_MSB, 0x40006087\r
+.set CYDEV_USB_ARB_RW1_DR, 0x40006088\r
+.set CYDEV_USB_BUF_SIZE, 0x4000608c\r
+.set CYDEV_USB_EP_ACTIVE, 0x4000608e\r
+.set CYDEV_USB_EP_TYPE, 0x4000608f\r
+.set CYDEV_USB_ARB_EP2_BASE, 0x40006090\r
+.set CYDEV_USB_ARB_EP2_SIZE, 0x00000003\r
+.set CYDEV_USB_ARB_EP2_CFG, 0x40006090\r
+.set CYDEV_USB_ARB_EP2_INT_EN, 0x40006091\r
+.set CYDEV_USB_ARB_EP2_SR, 0x40006092\r
+.set CYDEV_USB_ARB_RW2_BASE, 0x40006094\r
+.set CYDEV_USB_ARB_RW2_SIZE, 0x00000005\r
+.set CYDEV_USB_ARB_RW2_WA, 0x40006094\r
+.set CYDEV_USB_ARB_RW2_WA_MSB, 0x40006095\r
+.set CYDEV_USB_ARB_RW2_RA, 0x40006096\r
+.set CYDEV_USB_ARB_RW2_RA_MSB, 0x40006097\r
+.set CYDEV_USB_ARB_RW2_DR, 0x40006098\r
+.set CYDEV_USB_ARB_CFG, 0x4000609c\r
+.set CYDEV_USB_USB_CLK_EN, 0x4000609d\r
+.set CYDEV_USB_ARB_INT_EN, 0x4000609e\r
+.set CYDEV_USB_ARB_INT_SR, 0x4000609f\r
+.set CYDEV_USB_ARB_EP3_BASE, 0x400060a0\r
+.set CYDEV_USB_ARB_EP3_SIZE, 0x00000003\r
+.set CYDEV_USB_ARB_EP3_CFG, 0x400060a0\r
+.set CYDEV_USB_ARB_EP3_INT_EN, 0x400060a1\r
+.set CYDEV_USB_ARB_EP3_SR, 0x400060a2\r
+.set CYDEV_USB_ARB_RW3_BASE, 0x400060a4\r
+.set CYDEV_USB_ARB_RW3_SIZE, 0x00000005\r
+.set CYDEV_USB_ARB_RW3_WA, 0x400060a4\r
+.set CYDEV_USB_ARB_RW3_WA_MSB, 0x400060a5\r
+.set CYDEV_USB_ARB_RW3_RA, 0x400060a6\r
+.set CYDEV_USB_ARB_RW3_RA_MSB, 0x400060a7\r
+.set CYDEV_USB_ARB_RW3_DR, 0x400060a8\r
+.set CYDEV_USB_CWA, 0x400060ac\r
+.set CYDEV_USB_CWA_MSB, 0x400060ad\r
+.set CYDEV_USB_ARB_EP4_BASE, 0x400060b0\r
+.set CYDEV_USB_ARB_EP4_SIZE, 0x00000003\r
+.set CYDEV_USB_ARB_EP4_CFG, 0x400060b0\r
+.set CYDEV_USB_ARB_EP4_INT_EN, 0x400060b1\r
+.set CYDEV_USB_ARB_EP4_SR, 0x400060b2\r
+.set CYDEV_USB_ARB_RW4_BASE, 0x400060b4\r
+.set CYDEV_USB_ARB_RW4_SIZE, 0x00000005\r
+.set CYDEV_USB_ARB_RW4_WA, 0x400060b4\r
+.set CYDEV_USB_ARB_RW4_WA_MSB, 0x400060b5\r
+.set CYDEV_USB_ARB_RW4_RA, 0x400060b6\r
+.set CYDEV_USB_ARB_RW4_RA_MSB, 0x400060b7\r
+.set CYDEV_USB_ARB_RW4_DR, 0x400060b8\r
+.set CYDEV_USB_DMA_THRES, 0x400060bc\r
+.set CYDEV_USB_DMA_THRES_MSB, 0x400060bd\r
+.set CYDEV_USB_ARB_EP5_BASE, 0x400060c0\r
+.set CYDEV_USB_ARB_EP5_SIZE, 0x00000003\r
+.set CYDEV_USB_ARB_EP5_CFG, 0x400060c0\r
+.set CYDEV_USB_ARB_EP5_INT_EN, 0x400060c1\r
+.set CYDEV_USB_ARB_EP5_SR, 0x400060c2\r
+.set CYDEV_USB_ARB_RW5_BASE, 0x400060c4\r
+.set CYDEV_USB_ARB_RW5_SIZE, 0x00000005\r
+.set CYDEV_USB_ARB_RW5_WA, 0x400060c4\r
+.set CYDEV_USB_ARB_RW5_WA_MSB, 0x400060c5\r
+.set CYDEV_USB_ARB_RW5_RA, 0x400060c6\r
+.set CYDEV_USB_ARB_RW5_RA_MSB, 0x400060c7\r
+.set CYDEV_USB_ARB_RW5_DR, 0x400060c8\r
+.set CYDEV_USB_BUS_RST_CNT, 0x400060cc\r
+.set CYDEV_USB_ARB_EP6_BASE, 0x400060d0\r
+.set CYDEV_USB_ARB_EP6_SIZE, 0x00000003\r
+.set CYDEV_USB_ARB_EP6_CFG, 0x400060d0\r
+.set CYDEV_USB_ARB_EP6_INT_EN, 0x400060d1\r
+.set CYDEV_USB_ARB_EP6_SR, 0x400060d2\r
+.set CYDEV_USB_ARB_RW6_BASE, 0x400060d4\r
+.set CYDEV_USB_ARB_RW6_SIZE, 0x00000005\r
+.set CYDEV_USB_ARB_RW6_WA, 0x400060d4\r
+.set CYDEV_USB_ARB_RW6_WA_MSB, 0x400060d5\r
+.set CYDEV_USB_ARB_RW6_RA, 0x400060d6\r
+.set CYDEV_USB_ARB_RW6_RA_MSB, 0x400060d7\r
+.set CYDEV_USB_ARB_RW6_DR, 0x400060d8\r
+.set CYDEV_USB_ARB_EP7_BASE, 0x400060e0\r
+.set CYDEV_USB_ARB_EP7_SIZE, 0x00000003\r
+.set CYDEV_USB_ARB_EP7_CFG, 0x400060e0\r
+.set CYDEV_USB_ARB_EP7_INT_EN, 0x400060e1\r
+.set CYDEV_USB_ARB_EP7_SR, 0x400060e2\r
+.set CYDEV_USB_ARB_RW7_BASE, 0x400060e4\r
+.set CYDEV_USB_ARB_RW7_SIZE, 0x00000005\r
+.set CYDEV_USB_ARB_RW7_WA, 0x400060e4\r
+.set CYDEV_USB_ARB_RW7_WA_MSB, 0x400060e5\r
+.set CYDEV_USB_ARB_RW7_RA, 0x400060e6\r
+.set CYDEV_USB_ARB_RW7_RA_MSB, 0x400060e7\r
+.set CYDEV_USB_ARB_RW7_DR, 0x400060e8\r
+.set CYDEV_USB_ARB_EP8_BASE, 0x400060f0\r
+.set CYDEV_USB_ARB_EP8_SIZE, 0x00000003\r
+.set CYDEV_USB_ARB_EP8_CFG, 0x400060f0\r
+.set CYDEV_USB_ARB_EP8_INT_EN, 0x400060f1\r
+.set CYDEV_USB_ARB_EP8_SR, 0x400060f2\r
+.set CYDEV_USB_ARB_RW8_BASE, 0x400060f4\r
+.set CYDEV_USB_ARB_RW8_SIZE, 0x00000005\r
+.set CYDEV_USB_ARB_RW8_WA, 0x400060f4\r
+.set CYDEV_USB_ARB_RW8_WA_MSB, 0x400060f5\r
+.set CYDEV_USB_ARB_RW8_RA, 0x400060f6\r
+.set CYDEV_USB_ARB_RW8_RA_MSB, 0x400060f7\r
+.set CYDEV_USB_ARB_RW8_DR, 0x400060f8\r
+.set CYDEV_USB_MEM_BASE, 0x40006100\r
+.set CYDEV_USB_MEM_SIZE, 0x00000200\r
+.set CYDEV_USB_MEM_DATA_MBASE, 0x40006100\r
+.set CYDEV_USB_MEM_DATA_MSIZE, 0x00000200\r
+.set CYDEV_UWRK_BASE, 0x40006400\r
+.set CYDEV_UWRK_SIZE, 0x00000b60\r
+.set CYDEV_UWRK_UWRK8_BASE, 0x40006400\r
+.set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0\r
+.set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400\r
+.set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0\r
+.set CYDEV_UWRK_UWRK8_B0_UDB00_A0, 0x40006400\r
+.set CYDEV_UWRK_UWRK8_B0_UDB01_A0, 0x40006401\r
+.set CYDEV_UWRK_UWRK8_B0_UDB02_A0, 0x40006402\r
+.set CYDEV_UWRK_UWRK8_B0_UDB03_A0, 0x40006403\r
+.set CYDEV_UWRK_UWRK8_B0_UDB04_A0, 0x40006404\r
+.set CYDEV_UWRK_UWRK8_B0_UDB05_A0, 0x40006405\r
+.set CYDEV_UWRK_UWRK8_B0_UDB06_A0, 0x40006406\r
+.set CYDEV_UWRK_UWRK8_B0_UDB07_A0, 0x40006407\r
+.set CYDEV_UWRK_UWRK8_B0_UDB08_A0, 0x40006408\r
+.set CYDEV_UWRK_UWRK8_B0_UDB09_A0, 0x40006409\r
+.set CYDEV_UWRK_UWRK8_B0_UDB10_A0, 0x4000640a\r
+.set CYDEV_UWRK_UWRK8_B0_UDB11_A0, 0x4000640b\r
+.set CYDEV_UWRK_UWRK8_B0_UDB12_A0, 0x4000640c\r
+.set CYDEV_UWRK_UWRK8_B0_UDB13_A0, 0x4000640d\r
+.set CYDEV_UWRK_UWRK8_B0_UDB14_A0, 0x4000640e\r
+.set CYDEV_UWRK_UWRK8_B0_UDB15_A0, 0x4000640f\r
+.set CYDEV_UWRK_UWRK8_B0_UDB00_A1, 0x40006410\r
+.set CYDEV_UWRK_UWRK8_B0_UDB01_A1, 0x40006411\r
+.set CYDEV_UWRK_UWRK8_B0_UDB02_A1, 0x40006412\r
+.set CYDEV_UWRK_UWRK8_B0_UDB03_A1, 0x40006413\r
+.set CYDEV_UWRK_UWRK8_B0_UDB04_A1, 0x40006414\r
+.set CYDEV_UWRK_UWRK8_B0_UDB05_A1, 0x40006415\r
+.set CYDEV_UWRK_UWRK8_B0_UDB06_A1, 0x40006416\r
+.set CYDEV_UWRK_UWRK8_B0_UDB07_A1, 0x40006417\r
+.set CYDEV_UWRK_UWRK8_B0_UDB08_A1, 0x40006418\r
+.set CYDEV_UWRK_UWRK8_B0_UDB09_A1, 0x40006419\r
+.set CYDEV_UWRK_UWRK8_B0_UDB10_A1, 0x4000641a\r
+.set CYDEV_UWRK_UWRK8_B0_UDB11_A1, 0x4000641b\r
+.set CYDEV_UWRK_UWRK8_B0_UDB12_A1, 0x4000641c\r
+.set CYDEV_UWRK_UWRK8_B0_UDB13_A1, 0x4000641d\r
+.set CYDEV_UWRK_UWRK8_B0_UDB14_A1, 0x4000641e\r
+.set CYDEV_UWRK_UWRK8_B0_UDB15_A1, 0x4000641f\r
+.set CYDEV_UWRK_UWRK8_B0_UDB00_D0, 0x40006420\r
+.set CYDEV_UWRK_UWRK8_B0_UDB01_D0, 0x40006421\r
+.set CYDEV_UWRK_UWRK8_B0_UDB02_D0, 0x40006422\r
+.set CYDEV_UWRK_UWRK8_B0_UDB03_D0, 0x40006423\r
+.set CYDEV_UWRK_UWRK8_B0_UDB04_D0, 0x40006424\r
+.set CYDEV_UWRK_UWRK8_B0_UDB05_D0, 0x40006425\r
+.set CYDEV_UWRK_UWRK8_B0_UDB06_D0, 0x40006426\r
+.set CYDEV_UWRK_UWRK8_B0_UDB07_D0, 0x40006427\r
+.set CYDEV_UWRK_UWRK8_B0_UDB08_D0, 0x40006428\r
+.set CYDEV_UWRK_UWRK8_B0_UDB09_D0, 0x40006429\r
+.set CYDEV_UWRK_UWRK8_B0_UDB10_D0, 0x4000642a\r
+.set CYDEV_UWRK_UWRK8_B0_UDB11_D0, 0x4000642b\r
+.set CYDEV_UWRK_UWRK8_B0_UDB12_D0, 0x4000642c\r
+.set CYDEV_UWRK_UWRK8_B0_UDB13_D0, 0x4000642d\r
+.set CYDEV_UWRK_UWRK8_B0_UDB14_D0, 0x4000642e\r
+.set CYDEV_UWRK_UWRK8_B0_UDB15_D0, 0x4000642f\r
+.set CYDEV_UWRK_UWRK8_B0_UDB00_D1, 0x40006430\r
+.set CYDEV_UWRK_UWRK8_B0_UDB01_D1, 0x40006431\r
+.set CYDEV_UWRK_UWRK8_B0_UDB02_D1, 0x40006432\r
+.set CYDEV_UWRK_UWRK8_B0_UDB03_D1, 0x40006433\r
+.set CYDEV_UWRK_UWRK8_B0_UDB04_D1, 0x40006434\r
+.set CYDEV_UWRK_UWRK8_B0_UDB05_D1, 0x40006435\r
+.set CYDEV_UWRK_UWRK8_B0_UDB06_D1, 0x40006436\r
+.set CYDEV_UWRK_UWRK8_B0_UDB07_D1, 0x40006437\r
+.set CYDEV_UWRK_UWRK8_B0_UDB08_D1, 0x40006438\r
+.set CYDEV_UWRK_UWRK8_B0_UDB09_D1, 0x40006439\r
+.set CYDEV_UWRK_UWRK8_B0_UDB10_D1, 0x4000643a\r
+.set CYDEV_UWRK_UWRK8_B0_UDB11_D1, 0x4000643b\r
+.set CYDEV_UWRK_UWRK8_B0_UDB12_D1, 0x4000643c\r
+.set CYDEV_UWRK_UWRK8_B0_UDB13_D1, 0x4000643d\r
+.set CYDEV_UWRK_UWRK8_B0_UDB14_D1, 0x4000643e\r
+.set CYDEV_UWRK_UWRK8_B0_UDB15_D1, 0x4000643f\r
+.set CYDEV_UWRK_UWRK8_B0_UDB00_F0, 0x40006440\r
+.set CYDEV_UWRK_UWRK8_B0_UDB01_F0, 0x40006441\r
+.set CYDEV_UWRK_UWRK8_B0_UDB02_F0, 0x40006442\r
+.set CYDEV_UWRK_UWRK8_B0_UDB03_F0, 0x40006443\r
+.set CYDEV_UWRK_UWRK8_B0_UDB04_F0, 0x40006444\r
+.set CYDEV_UWRK_UWRK8_B0_UDB05_F0, 0x40006445\r
+.set CYDEV_UWRK_UWRK8_B0_UDB06_F0, 0x40006446\r
+.set CYDEV_UWRK_UWRK8_B0_UDB07_F0, 0x40006447\r
+.set CYDEV_UWRK_UWRK8_B0_UDB08_F0, 0x40006448\r
+.set CYDEV_UWRK_UWRK8_B0_UDB09_F0, 0x40006449\r
+.set CYDEV_UWRK_UWRK8_B0_UDB10_F0, 0x4000644a\r
+.set CYDEV_UWRK_UWRK8_B0_UDB11_F0, 0x4000644b\r
+.set CYDEV_UWRK_UWRK8_B0_UDB12_F0, 0x4000644c\r
+.set CYDEV_UWRK_UWRK8_B0_UDB13_F0, 0x4000644d\r
+.set CYDEV_UWRK_UWRK8_B0_UDB14_F0, 0x4000644e\r
+.set CYDEV_UWRK_UWRK8_B0_UDB15_F0, 0x4000644f\r
+.set CYDEV_UWRK_UWRK8_B0_UDB00_F1, 0x40006450\r
+.set CYDEV_UWRK_UWRK8_B0_UDB01_F1, 0x40006451\r
+.set CYDEV_UWRK_UWRK8_B0_UDB02_F1, 0x40006452\r
+.set CYDEV_UWRK_UWRK8_B0_UDB03_F1, 0x40006453\r
+.set CYDEV_UWRK_UWRK8_B0_UDB04_F1, 0x40006454\r
+.set CYDEV_UWRK_UWRK8_B0_UDB05_F1, 0x40006455\r
+.set CYDEV_UWRK_UWRK8_B0_UDB06_F1, 0x40006456\r
+.set CYDEV_UWRK_UWRK8_B0_UDB07_F1, 0x40006457\r
+.set CYDEV_UWRK_UWRK8_B0_UDB08_F1, 0x40006458\r
+.set CYDEV_UWRK_UWRK8_B0_UDB09_F1, 0x40006459\r
+.set CYDEV_UWRK_UWRK8_B0_UDB10_F1, 0x4000645a\r
+.set CYDEV_UWRK_UWRK8_B0_UDB11_F1, 0x4000645b\r
+.set CYDEV_UWRK_UWRK8_B0_UDB12_F1, 0x4000645c\r
+.set CYDEV_UWRK_UWRK8_B0_UDB13_F1, 0x4000645d\r
+.set CYDEV_UWRK_UWRK8_B0_UDB14_F1, 0x4000645e\r
+.set CYDEV_UWRK_UWRK8_B0_UDB15_F1, 0x4000645f\r
+.set CYDEV_UWRK_UWRK8_B0_UDB00_ST, 0x40006460\r
+.set CYDEV_UWRK_UWRK8_B0_UDB01_ST, 0x40006461\r
+.set CYDEV_UWRK_UWRK8_B0_UDB02_ST, 0x40006462\r
+.set CYDEV_UWRK_UWRK8_B0_UDB03_ST, 0x40006463\r
+.set CYDEV_UWRK_UWRK8_B0_UDB04_ST, 0x40006464\r
+.set CYDEV_UWRK_UWRK8_B0_UDB05_ST, 0x40006465\r
+.set CYDEV_UWRK_UWRK8_B0_UDB06_ST, 0x40006466\r
+.set CYDEV_UWRK_UWRK8_B0_UDB07_ST, 0x40006467\r
+.set CYDEV_UWRK_UWRK8_B0_UDB08_ST, 0x40006468\r
+.set CYDEV_UWRK_UWRK8_B0_UDB09_ST, 0x40006469\r
+.set CYDEV_UWRK_UWRK8_B0_UDB10_ST, 0x4000646a\r
+.set CYDEV_UWRK_UWRK8_B0_UDB11_ST, 0x4000646b\r
+.set CYDEV_UWRK_UWRK8_B0_UDB12_ST, 0x4000646c\r
+.set CYDEV_UWRK_UWRK8_B0_UDB13_ST, 0x4000646d\r
+.set CYDEV_UWRK_UWRK8_B0_UDB14_ST, 0x4000646e\r
+.set CYDEV_UWRK_UWRK8_B0_UDB15_ST, 0x4000646f\r
+.set CYDEV_UWRK_UWRK8_B0_UDB00_CTL, 0x40006470\r
+.set CYDEV_UWRK_UWRK8_B0_UDB01_CTL, 0x40006471\r
+.set CYDEV_UWRK_UWRK8_B0_UDB02_CTL, 0x40006472\r
+.set CYDEV_UWRK_UWRK8_B0_UDB03_CTL, 0x40006473\r
+.set CYDEV_UWRK_UWRK8_B0_UDB04_CTL, 0x40006474\r
+.set CYDEV_UWRK_UWRK8_B0_UDB05_CTL, 0x40006475\r
+.set CYDEV_UWRK_UWRK8_B0_UDB06_CTL, 0x40006476\r
+.set CYDEV_UWRK_UWRK8_B0_UDB07_CTL, 0x40006477\r
+.set CYDEV_UWRK_UWRK8_B0_UDB08_CTL, 0x40006478\r
+.set CYDEV_UWRK_UWRK8_B0_UDB09_CTL, 0x40006479\r
+.set CYDEV_UWRK_UWRK8_B0_UDB10_CTL, 0x4000647a\r
+.set CYDEV_UWRK_UWRK8_B0_UDB11_CTL, 0x4000647b\r
+.set CYDEV_UWRK_UWRK8_B0_UDB12_CTL, 0x4000647c\r
+.set CYDEV_UWRK_UWRK8_B0_UDB13_CTL, 0x4000647d\r
+.set CYDEV_UWRK_UWRK8_B0_UDB14_CTL, 0x4000647e\r
+.set CYDEV_UWRK_UWRK8_B0_UDB15_CTL, 0x4000647f\r
+.set CYDEV_UWRK_UWRK8_B0_UDB00_MSK, 0x40006480\r
+.set CYDEV_UWRK_UWRK8_B0_UDB01_MSK, 0x40006481\r
+.set CYDEV_UWRK_UWRK8_B0_UDB02_MSK, 0x40006482\r
+.set CYDEV_UWRK_UWRK8_B0_UDB03_MSK, 0x40006483\r
+.set CYDEV_UWRK_UWRK8_B0_UDB04_MSK, 0x40006484\r
+.set CYDEV_UWRK_UWRK8_B0_UDB05_MSK, 0x40006485\r
+.set CYDEV_UWRK_UWRK8_B0_UDB06_MSK, 0x40006486\r
+.set CYDEV_UWRK_UWRK8_B0_UDB07_MSK, 0x40006487\r
+.set CYDEV_UWRK_UWRK8_B0_UDB08_MSK, 0x40006488\r
+.set CYDEV_UWRK_UWRK8_B0_UDB09_MSK, 0x40006489\r
+.set CYDEV_UWRK_UWRK8_B0_UDB10_MSK, 0x4000648a\r
+.set CYDEV_UWRK_UWRK8_B0_UDB11_MSK, 0x4000648b\r
+.set CYDEV_UWRK_UWRK8_B0_UDB12_MSK, 0x4000648c\r
+.set CYDEV_UWRK_UWRK8_B0_UDB13_MSK, 0x4000648d\r
+.set CYDEV_UWRK_UWRK8_B0_UDB14_MSK, 0x4000648e\r
+.set CYDEV_UWRK_UWRK8_B0_UDB15_MSK, 0x4000648f\r
+.set CYDEV_UWRK_UWRK8_B0_UDB00_ACTL, 0x40006490\r
+.set CYDEV_UWRK_UWRK8_B0_UDB01_ACTL, 0x40006491\r
+.set CYDEV_UWRK_UWRK8_B0_UDB02_ACTL, 0x40006492\r
+.set CYDEV_UWRK_UWRK8_B0_UDB03_ACTL, 0x40006493\r
+.set CYDEV_UWRK_UWRK8_B0_UDB04_ACTL, 0x40006494\r
+.set CYDEV_UWRK_UWRK8_B0_UDB05_ACTL, 0x40006495\r
+.set CYDEV_UWRK_UWRK8_B0_UDB06_ACTL, 0x40006496\r
+.set CYDEV_UWRK_UWRK8_B0_UDB07_ACTL, 0x40006497\r
+.set CYDEV_UWRK_UWRK8_B0_UDB08_ACTL, 0x40006498\r
+.set CYDEV_UWRK_UWRK8_B0_UDB09_ACTL, 0x40006499\r
+.set CYDEV_UWRK_UWRK8_B0_UDB10_ACTL, 0x4000649a\r
+.set CYDEV_UWRK_UWRK8_B0_UDB11_ACTL, 0x4000649b\r
+.set CYDEV_UWRK_UWRK8_B0_UDB12_ACTL, 0x4000649c\r
+.set CYDEV_UWRK_UWRK8_B0_UDB13_ACTL, 0x4000649d\r
+.set CYDEV_UWRK_UWRK8_B0_UDB14_ACTL, 0x4000649e\r
+.set CYDEV_UWRK_UWRK8_B0_UDB15_ACTL, 0x4000649f\r
+.set CYDEV_UWRK_UWRK8_B0_UDB00_MC, 0x400064a0\r
+.set CYDEV_UWRK_UWRK8_B0_UDB01_MC, 0x400064a1\r
+.set CYDEV_UWRK_UWRK8_B0_UDB02_MC, 0x400064a2\r
+.set CYDEV_UWRK_UWRK8_B0_UDB03_MC, 0x400064a3\r
+.set CYDEV_UWRK_UWRK8_B0_UDB04_MC, 0x400064a4\r
+.set CYDEV_UWRK_UWRK8_B0_UDB05_MC, 0x400064a5\r
+.set CYDEV_UWRK_UWRK8_B0_UDB06_MC, 0x400064a6\r
+.set CYDEV_UWRK_UWRK8_B0_UDB07_MC, 0x400064a7\r
+.set CYDEV_UWRK_UWRK8_B0_UDB08_MC, 0x400064a8\r
+.set CYDEV_UWRK_UWRK8_B0_UDB09_MC, 0x400064a9\r
+.set CYDEV_UWRK_UWRK8_B0_UDB10_MC, 0x400064aa\r
+.set CYDEV_UWRK_UWRK8_B0_UDB11_MC, 0x400064ab\r
+.set CYDEV_UWRK_UWRK8_B0_UDB12_MC, 0x400064ac\r
+.set CYDEV_UWRK_UWRK8_B0_UDB13_MC, 0x400064ad\r
+.set CYDEV_UWRK_UWRK8_B0_UDB14_MC, 0x400064ae\r
+.set CYDEV_UWRK_UWRK8_B0_UDB15_MC, 0x400064af\r
+.set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500\r
+.set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0\r
+.set CYDEV_UWRK_UWRK8_B1_UDB04_A0, 0x40006504\r
+.set CYDEV_UWRK_UWRK8_B1_UDB05_A0, 0x40006505\r
+.set CYDEV_UWRK_UWRK8_B1_UDB06_A0, 0x40006506\r
+.set CYDEV_UWRK_UWRK8_B1_UDB07_A0, 0x40006507\r
+.set CYDEV_UWRK_UWRK8_B1_UDB08_A0, 0x40006508\r
+.set CYDEV_UWRK_UWRK8_B1_UDB09_A0, 0x40006509\r
+.set CYDEV_UWRK_UWRK8_B1_UDB10_A0, 0x4000650a\r
+.set CYDEV_UWRK_UWRK8_B1_UDB11_A0, 0x4000650b\r
+.set CYDEV_UWRK_UWRK8_B1_UDB04_A1, 0x40006514\r
+.set CYDEV_UWRK_UWRK8_B1_UDB05_A1, 0x40006515\r
+.set CYDEV_UWRK_UWRK8_B1_UDB06_A1, 0x40006516\r
+.set CYDEV_UWRK_UWRK8_B1_UDB07_A1, 0x40006517\r
+.set CYDEV_UWRK_UWRK8_B1_UDB08_A1, 0x40006518\r
+.set CYDEV_UWRK_UWRK8_B1_UDB09_A1, 0x40006519\r
+.set CYDEV_UWRK_UWRK8_B1_UDB10_A1, 0x4000651a\r
+.set CYDEV_UWRK_UWRK8_B1_UDB11_A1, 0x4000651b\r
+.set CYDEV_UWRK_UWRK8_B1_UDB04_D0, 0x40006524\r
+.set CYDEV_UWRK_UWRK8_B1_UDB05_D0, 0x40006525\r
+.set CYDEV_UWRK_UWRK8_B1_UDB06_D0, 0x40006526\r
+.set CYDEV_UWRK_UWRK8_B1_UDB07_D0, 0x40006527\r
+.set CYDEV_UWRK_UWRK8_B1_UDB08_D0, 0x40006528\r
+.set CYDEV_UWRK_UWRK8_B1_UDB09_D0, 0x40006529\r
+.set CYDEV_UWRK_UWRK8_B1_UDB10_D0, 0x4000652a\r
+.set CYDEV_UWRK_UWRK8_B1_UDB11_D0, 0x4000652b\r
+.set CYDEV_UWRK_UWRK8_B1_UDB04_D1, 0x40006534\r
+.set CYDEV_UWRK_UWRK8_B1_UDB05_D1, 0x40006535\r
+.set CYDEV_UWRK_UWRK8_B1_UDB06_D1, 0x40006536\r
+.set CYDEV_UWRK_UWRK8_B1_UDB07_D1, 0x40006537\r
+.set CYDEV_UWRK_UWRK8_B1_UDB08_D1, 0x40006538\r
+.set CYDEV_UWRK_UWRK8_B1_UDB09_D1, 0x40006539\r
+.set CYDEV_UWRK_UWRK8_B1_UDB10_D1, 0x4000653a\r
+.set CYDEV_UWRK_UWRK8_B1_UDB11_D1, 0x4000653b\r
+.set CYDEV_UWRK_UWRK8_B1_UDB04_F0, 0x40006544\r
+.set CYDEV_UWRK_UWRK8_B1_UDB05_F0, 0x40006545\r
+.set CYDEV_UWRK_UWRK8_B1_UDB06_F0, 0x40006546\r
+.set CYDEV_UWRK_UWRK8_B1_UDB07_F0, 0x40006547\r
+.set CYDEV_UWRK_UWRK8_B1_UDB08_F0, 0x40006548\r
+.set CYDEV_UWRK_UWRK8_B1_UDB09_F0, 0x40006549\r
+.set CYDEV_UWRK_UWRK8_B1_UDB10_F0, 0x4000654a\r
+.set CYDEV_UWRK_UWRK8_B1_UDB11_F0, 0x4000654b\r
+.set CYDEV_UWRK_UWRK8_B1_UDB04_F1, 0x40006554\r
+.set CYDEV_UWRK_UWRK8_B1_UDB05_F1, 0x40006555\r
+.set CYDEV_UWRK_UWRK8_B1_UDB06_F1, 0x40006556\r
+.set CYDEV_UWRK_UWRK8_B1_UDB07_F1, 0x40006557\r
+.set CYDEV_UWRK_UWRK8_B1_UDB08_F1, 0x40006558\r
+.set CYDEV_UWRK_UWRK8_B1_UDB09_F1, 0x40006559\r
+.set CYDEV_UWRK_UWRK8_B1_UDB10_F1, 0x4000655a\r
+.set CYDEV_UWRK_UWRK8_B1_UDB11_F1, 0x4000655b\r
+.set CYDEV_UWRK_UWRK8_B1_UDB04_ST, 0x40006564\r
+.set CYDEV_UWRK_UWRK8_B1_UDB05_ST, 0x40006565\r
+.set CYDEV_UWRK_UWRK8_B1_UDB06_ST, 0x40006566\r
+.set CYDEV_UWRK_UWRK8_B1_UDB07_ST, 0x40006567\r
+.set CYDEV_UWRK_UWRK8_B1_UDB08_ST, 0x40006568\r
+.set CYDEV_UWRK_UWRK8_B1_UDB09_ST, 0x40006569\r
+.set CYDEV_UWRK_UWRK8_B1_UDB10_ST, 0x4000656a\r
+.set CYDEV_UWRK_UWRK8_B1_UDB11_ST, 0x4000656b\r
+.set CYDEV_UWRK_UWRK8_B1_UDB04_CTL, 0x40006574\r
+.set CYDEV_UWRK_UWRK8_B1_UDB05_CTL, 0x40006575\r
+.set CYDEV_UWRK_UWRK8_B1_UDB06_CTL, 0x40006576\r
+.set CYDEV_UWRK_UWRK8_B1_UDB07_CTL, 0x40006577\r
+.set CYDEV_UWRK_UWRK8_B1_UDB08_CTL, 0x40006578\r
+.set CYDEV_UWRK_UWRK8_B1_UDB09_CTL, 0x40006579\r
+.set CYDEV_UWRK_UWRK8_B1_UDB10_CTL, 0x4000657a\r
+.set CYDEV_UWRK_UWRK8_B1_UDB11_CTL, 0x4000657b\r
+.set CYDEV_UWRK_UWRK8_B1_UDB04_MSK, 0x40006584\r
+.set CYDEV_UWRK_UWRK8_B1_UDB05_MSK, 0x40006585\r
+.set CYDEV_UWRK_UWRK8_B1_UDB06_MSK, 0x40006586\r
+.set CYDEV_UWRK_UWRK8_B1_UDB07_MSK, 0x40006587\r
+.set CYDEV_UWRK_UWRK8_B1_UDB08_MSK, 0x40006588\r
+.set CYDEV_UWRK_UWRK8_B1_UDB09_MSK, 0x40006589\r
+.set CYDEV_UWRK_UWRK8_B1_UDB10_MSK, 0x4000658a\r
+.set CYDEV_UWRK_UWRK8_B1_UDB11_MSK, 0x4000658b\r
+.set CYDEV_UWRK_UWRK8_B1_UDB04_ACTL, 0x40006594\r
+.set CYDEV_UWRK_UWRK8_B1_UDB05_ACTL, 0x40006595\r
+.set CYDEV_UWRK_UWRK8_B1_UDB06_ACTL, 0x40006596\r
+.set CYDEV_UWRK_UWRK8_B1_UDB07_ACTL, 0x40006597\r
+.set CYDEV_UWRK_UWRK8_B1_UDB08_ACTL, 0x40006598\r
+.set CYDEV_UWRK_UWRK8_B1_UDB09_ACTL, 0x40006599\r
+.set CYDEV_UWRK_UWRK8_B1_UDB10_ACTL, 0x4000659a\r
+.set CYDEV_UWRK_UWRK8_B1_UDB11_ACTL, 0x4000659b\r
+.set CYDEV_UWRK_UWRK8_B1_UDB04_MC, 0x400065a4\r
+.set CYDEV_UWRK_UWRK8_B1_UDB05_MC, 0x400065a5\r
+.set CYDEV_UWRK_UWRK8_B1_UDB06_MC, 0x400065a6\r
+.set CYDEV_UWRK_UWRK8_B1_UDB07_MC, 0x400065a7\r
+.set CYDEV_UWRK_UWRK8_B1_UDB08_MC, 0x400065a8\r
+.set CYDEV_UWRK_UWRK8_B1_UDB09_MC, 0x400065a9\r
+.set CYDEV_UWRK_UWRK8_B1_UDB10_MC, 0x400065aa\r
+.set CYDEV_UWRK_UWRK8_B1_UDB11_MC, 0x400065ab\r
+.set CYDEV_UWRK_UWRK16_BASE, 0x40006800\r
+.set CYDEV_UWRK_UWRK16_SIZE, 0x00000760\r
+.set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800\r
+.set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1, 0x40006800\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1, 0x40006802\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1, 0x40006804\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1, 0x40006806\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1, 0x40006808\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1, 0x4000680a\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1, 0x4000680c\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1, 0x4000680e\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1, 0x40006810\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1, 0x40006812\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1, 0x40006814\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1, 0x40006816\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1, 0x40006818\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1, 0x4000681a\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1, 0x4000681c\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1, 0x4000681e\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1, 0x40006840\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1, 0x40006842\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1, 0x40006844\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1, 0x40006846\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1, 0x40006848\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1, 0x4000684a\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1, 0x4000684c\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1, 0x4000684e\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1, 0x40006850\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1, 0x40006852\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1, 0x40006854\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1, 0x40006856\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1, 0x40006858\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1, 0x4000685a\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1, 0x4000685c\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1, 0x4000685e\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1, 0x40006880\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1, 0x40006882\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1, 0x40006884\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1, 0x40006886\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1, 0x40006888\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1, 0x4000688a\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1, 0x4000688c\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1, 0x4000688e\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1, 0x40006890\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1, 0x40006892\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1, 0x40006894\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1, 0x40006896\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1, 0x40006898\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1, 0x4000689a\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1, 0x4000689c\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1, 0x4000689e\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL, 0x400068c0\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL, 0x400068c2\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL, 0x400068c4\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL, 0x400068c6\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL, 0x400068c8\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL, 0x400068ca\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL, 0x400068cc\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL, 0x400068ce\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL, 0x400068d0\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL, 0x400068d2\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL, 0x400068d4\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL, 0x400068d6\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL, 0x400068d8\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL, 0x400068da\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL, 0x400068dc\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL, 0x400068de\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL, 0x40006900\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL, 0x40006902\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL, 0x40006904\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL, 0x40006906\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL, 0x40006908\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL, 0x4000690a\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL, 0x4000690c\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL, 0x4000690e\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL, 0x40006910\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL, 0x40006912\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL, 0x40006914\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL, 0x40006916\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL, 0x40006918\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL, 0x4000691a\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL, 0x4000691c\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL, 0x4000691e\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00, 0x40006940\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00, 0x40006942\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00, 0x40006944\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00, 0x40006946\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00, 0x40006948\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00, 0x4000694a\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00, 0x4000694c\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00, 0x4000694e\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00, 0x40006950\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00, 0x40006952\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00, 0x40006954\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00, 0x40006956\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00, 0x40006958\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00, 0x4000695a\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00, 0x4000695c\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00, 0x4000695e\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1, 0x40006a08\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1, 0x40006a0a\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1, 0x40006a0c\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1, 0x40006a0e\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1, 0x40006a10\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1, 0x40006a12\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1, 0x40006a14\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1, 0x40006a16\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1, 0x40006a48\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1, 0x40006a4a\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1, 0x40006a4c\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1, 0x40006a4e\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1, 0x40006a50\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1, 0x40006a52\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1, 0x40006a54\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1, 0x40006a56\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1, 0x40006a88\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1, 0x40006a8a\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1, 0x40006a8c\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1, 0x40006a8e\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1, 0x40006a90\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1, 0x40006a92\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1, 0x40006a94\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1, 0x40006a96\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL, 0x40006ac8\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL, 0x40006aca\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL, 0x40006acc\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL, 0x40006ace\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL, 0x40006ad0\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL, 0x40006ad2\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL, 0x40006ad4\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL, 0x40006ad6\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL, 0x40006b08\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL, 0x40006b0a\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL, 0x40006b0c\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL, 0x40006b0e\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL, 0x40006b10\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL, 0x40006b12\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL, 0x40006b14\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL, 0x40006b16\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00, 0x40006b48\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00, 0x40006b4a\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00, 0x40006b4c\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00, 0x40006b4e\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00, 0x40006b50\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00, 0x40006b52\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00, 0x40006b54\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00, 0x40006b56\r
+.set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800\r
+.set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0, 0x40006800\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0, 0x40006802\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0, 0x40006804\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0, 0x40006806\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0, 0x40006808\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0, 0x4000680a\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0, 0x4000680c\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0, 0x4000680e\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0, 0x40006810\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0, 0x40006812\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0, 0x40006814\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0, 0x40006816\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0, 0x40006818\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0, 0x4000681a\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0, 0x4000681c\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1, 0x40006820\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1, 0x40006822\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1, 0x40006824\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1, 0x40006826\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1, 0x40006828\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1, 0x4000682a\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1, 0x4000682c\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1, 0x4000682e\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1, 0x40006830\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1, 0x40006832\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1, 0x40006834\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1, 0x40006836\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1, 0x40006838\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1, 0x4000683a\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1, 0x4000683c\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0, 0x40006840\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0, 0x40006842\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0, 0x40006844\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0, 0x40006846\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0, 0x40006848\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0, 0x4000684a\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0, 0x4000684c\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0, 0x4000684e\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0, 0x40006850\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0, 0x40006852\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0, 0x40006854\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0, 0x40006856\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0, 0x40006858\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0, 0x4000685a\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0, 0x4000685c\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1, 0x40006860\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1, 0x40006862\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1, 0x40006864\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1, 0x40006866\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1, 0x40006868\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1, 0x4000686a\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1, 0x4000686c\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1, 0x4000686e\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1, 0x40006870\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1, 0x40006872\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1, 0x40006874\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1, 0x40006876\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1, 0x40006878\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1, 0x4000687a\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1, 0x4000687c\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0, 0x40006880\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0, 0x40006882\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0, 0x40006884\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0, 0x40006886\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0, 0x40006888\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0, 0x4000688a\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0, 0x4000688c\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0, 0x4000688e\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0, 0x40006890\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0, 0x40006892\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0, 0x40006894\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0, 0x40006896\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0, 0x40006898\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0, 0x4000689a\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0, 0x4000689c\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1, 0x400068a0\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1, 0x400068a2\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1, 0x400068a4\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1, 0x400068a6\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1, 0x400068a8\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1, 0x400068aa\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1, 0x400068ac\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1, 0x400068ae\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1, 0x400068b0\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1, 0x400068b2\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1, 0x400068b4\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1, 0x400068b6\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1, 0x400068b8\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1, 0x400068ba\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1, 0x400068bc\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST, 0x400068c0\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST, 0x400068c2\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST, 0x400068c4\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST, 0x400068c6\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST, 0x400068c8\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST, 0x400068ca\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST, 0x400068cc\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST, 0x400068ce\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST, 0x400068d0\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST, 0x400068d2\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST, 0x400068d4\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST, 0x400068d6\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST, 0x400068d8\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST, 0x400068da\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST, 0x400068dc\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL, 0x400068e0\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL, 0x400068e2\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL, 0x400068e4\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL, 0x400068e6\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL, 0x400068e8\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL, 0x400068ea\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL, 0x400068ec\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL, 0x400068ee\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL, 0x400068f0\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL, 0x400068f2\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL, 0x400068f4\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL, 0x400068f6\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL, 0x400068f8\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL, 0x400068fa\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL, 0x400068fc\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK, 0x40006900\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK, 0x40006902\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK, 0x40006904\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK, 0x40006906\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK, 0x40006908\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK, 0x4000690a\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK, 0x4000690c\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK, 0x4000690e\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK, 0x40006910\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK, 0x40006912\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK, 0x40006914\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK, 0x40006916\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK, 0x40006918\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK, 0x4000691a\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK, 0x4000691c\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL, 0x40006920\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL, 0x40006922\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL, 0x40006924\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL, 0x40006926\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL, 0x40006928\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL, 0x4000692a\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL, 0x4000692c\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL, 0x4000692e\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL, 0x40006930\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL, 0x40006932\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL, 0x40006934\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL, 0x40006936\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL, 0x40006938\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL, 0x4000693a\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL, 0x4000693c\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC, 0x40006940\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC, 0x40006942\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC, 0x40006944\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC, 0x40006946\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC, 0x40006948\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC, 0x4000694a\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC, 0x4000694c\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC, 0x4000694e\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC, 0x40006950\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC, 0x40006952\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC, 0x40006954\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC, 0x40006956\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC, 0x40006958\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC, 0x4000695a\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC, 0x4000695c\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0, 0x40006a08\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0, 0x40006a0a\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0, 0x40006a0c\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0, 0x40006a0e\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0, 0x40006a10\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0, 0x40006a12\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0, 0x40006a14\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0, 0x40006a16\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1, 0x40006a28\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1, 0x40006a2a\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1, 0x40006a2c\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1, 0x40006a2e\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1, 0x40006a30\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1, 0x40006a32\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1, 0x40006a34\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1, 0x40006a36\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0, 0x40006a48\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0, 0x40006a4a\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0, 0x40006a4c\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0, 0x40006a4e\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0, 0x40006a50\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0, 0x40006a52\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0, 0x40006a54\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0, 0x40006a56\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1, 0x40006a68\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1, 0x40006a6a\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1, 0x40006a6c\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1, 0x40006a6e\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1, 0x40006a70\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1, 0x40006a72\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1, 0x40006a74\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1, 0x40006a76\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0, 0x40006a88\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0, 0x40006a8a\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0, 0x40006a8c\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0, 0x40006a8e\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0, 0x40006a90\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0, 0x40006a92\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0, 0x40006a94\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0, 0x40006a96\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1, 0x40006aa8\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1, 0x40006aaa\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1, 0x40006aac\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1, 0x40006aae\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1, 0x40006ab0\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1, 0x40006ab2\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1, 0x40006ab4\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1, 0x40006ab6\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST, 0x40006ac8\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST, 0x40006aca\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST, 0x40006acc\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST, 0x40006ace\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST, 0x40006ad0\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST, 0x40006ad2\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST, 0x40006ad4\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST, 0x40006ad6\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL, 0x40006ae8\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL, 0x40006aea\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL, 0x40006aec\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL, 0x40006aee\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL, 0x40006af0\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL, 0x40006af2\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL, 0x40006af4\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL, 0x40006af6\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK, 0x40006b08\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK, 0x40006b0a\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK, 0x40006b0c\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK, 0x40006b0e\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK, 0x40006b10\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK, 0x40006b12\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK, 0x40006b14\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK, 0x40006b16\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL, 0x40006b28\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL, 0x40006b2a\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL, 0x40006b2c\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL, 0x40006b2e\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL, 0x40006b30\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL, 0x40006b32\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL, 0x40006b34\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL, 0x40006b36\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC, 0x40006b48\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC, 0x40006b4a\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC, 0x40006b4c\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC, 0x40006b4e\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC, 0x40006b50\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC, 0x40006b52\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC, 0x40006b54\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC, 0x40006b56\r
+.set CYDEV_PHUB_BASE, 0x40007000\r
+.set CYDEV_PHUB_SIZE, 0x00000c00\r
+.set CYDEV_PHUB_CFG, 0x40007000\r
+.set CYDEV_PHUB_ERR, 0x40007004\r
+.set CYDEV_PHUB_ERR_ADR, 0x40007008\r
+.set CYDEV_PHUB_CH0_BASE, 0x40007010\r
+.set CYDEV_PHUB_CH0_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH0_BASIC_CFG, 0x40007010\r
+.set CYDEV_PHUB_CH0_ACTION, 0x40007014\r
+.set CYDEV_PHUB_CH0_BASIC_STATUS, 0x40007018\r
+.set CYDEV_PHUB_CH1_BASE, 0x40007020\r
+.set CYDEV_PHUB_CH1_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH1_BASIC_CFG, 0x40007020\r
+.set CYDEV_PHUB_CH1_ACTION, 0x40007024\r
+.set CYDEV_PHUB_CH1_BASIC_STATUS, 0x40007028\r
+.set CYDEV_PHUB_CH2_BASE, 0x40007030\r
+.set CYDEV_PHUB_CH2_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH2_BASIC_CFG, 0x40007030\r
+.set CYDEV_PHUB_CH2_ACTION, 0x40007034\r
+.set CYDEV_PHUB_CH2_BASIC_STATUS, 0x40007038\r
+.set CYDEV_PHUB_CH3_BASE, 0x40007040\r
+.set CYDEV_PHUB_CH3_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH3_BASIC_CFG, 0x40007040\r
+.set CYDEV_PHUB_CH3_ACTION, 0x40007044\r
+.set CYDEV_PHUB_CH3_BASIC_STATUS, 0x40007048\r
+.set CYDEV_PHUB_CH4_BASE, 0x40007050\r
+.set CYDEV_PHUB_CH4_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH4_BASIC_CFG, 0x40007050\r
+.set CYDEV_PHUB_CH4_ACTION, 0x40007054\r
+.set CYDEV_PHUB_CH4_BASIC_STATUS, 0x40007058\r
+.set CYDEV_PHUB_CH5_BASE, 0x40007060\r
+.set CYDEV_PHUB_CH5_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH5_BASIC_CFG, 0x40007060\r
+.set CYDEV_PHUB_CH5_ACTION, 0x40007064\r
+.set CYDEV_PHUB_CH5_BASIC_STATUS, 0x40007068\r
+.set CYDEV_PHUB_CH6_BASE, 0x40007070\r
+.set CYDEV_PHUB_CH6_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH6_BASIC_CFG, 0x40007070\r
+.set CYDEV_PHUB_CH6_ACTION, 0x40007074\r
+.set CYDEV_PHUB_CH6_BASIC_STATUS, 0x40007078\r
+.set CYDEV_PHUB_CH7_BASE, 0x40007080\r
+.set CYDEV_PHUB_CH7_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH7_BASIC_CFG, 0x40007080\r
+.set CYDEV_PHUB_CH7_ACTION, 0x40007084\r
+.set CYDEV_PHUB_CH7_BASIC_STATUS, 0x40007088\r
+.set CYDEV_PHUB_CH8_BASE, 0x40007090\r
+.set CYDEV_PHUB_CH8_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH8_BASIC_CFG, 0x40007090\r
+.set CYDEV_PHUB_CH8_ACTION, 0x40007094\r
+.set CYDEV_PHUB_CH8_BASIC_STATUS, 0x40007098\r
+.set CYDEV_PHUB_CH9_BASE, 0x400070a0\r
+.set CYDEV_PHUB_CH9_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH9_BASIC_CFG, 0x400070a0\r
+.set CYDEV_PHUB_CH9_ACTION, 0x400070a4\r
+.set CYDEV_PHUB_CH9_BASIC_STATUS, 0x400070a8\r
+.set CYDEV_PHUB_CH10_BASE, 0x400070b0\r
+.set CYDEV_PHUB_CH10_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH10_BASIC_CFG, 0x400070b0\r
+.set CYDEV_PHUB_CH10_ACTION, 0x400070b4\r
+.set CYDEV_PHUB_CH10_BASIC_STATUS, 0x400070b8\r
+.set CYDEV_PHUB_CH11_BASE, 0x400070c0\r
+.set CYDEV_PHUB_CH11_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH11_BASIC_CFG, 0x400070c0\r
+.set CYDEV_PHUB_CH11_ACTION, 0x400070c4\r
+.set CYDEV_PHUB_CH11_BASIC_STATUS, 0x400070c8\r
+.set CYDEV_PHUB_CH12_BASE, 0x400070d0\r
+.set CYDEV_PHUB_CH12_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH12_BASIC_CFG, 0x400070d0\r
+.set CYDEV_PHUB_CH12_ACTION, 0x400070d4\r
+.set CYDEV_PHUB_CH12_BASIC_STATUS, 0x400070d8\r
+.set CYDEV_PHUB_CH13_BASE, 0x400070e0\r
+.set CYDEV_PHUB_CH13_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH13_BASIC_CFG, 0x400070e0\r
+.set CYDEV_PHUB_CH13_ACTION, 0x400070e4\r
+.set CYDEV_PHUB_CH13_BASIC_STATUS, 0x400070e8\r
+.set CYDEV_PHUB_CH14_BASE, 0x400070f0\r
+.set CYDEV_PHUB_CH14_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH14_BASIC_CFG, 0x400070f0\r
+.set CYDEV_PHUB_CH14_ACTION, 0x400070f4\r
+.set CYDEV_PHUB_CH14_BASIC_STATUS, 0x400070f8\r
+.set CYDEV_PHUB_CH15_BASE, 0x40007100\r
+.set CYDEV_PHUB_CH15_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH15_BASIC_CFG, 0x40007100\r
+.set CYDEV_PHUB_CH15_ACTION, 0x40007104\r
+.set CYDEV_PHUB_CH15_BASIC_STATUS, 0x40007108\r
+.set CYDEV_PHUB_CH16_BASE, 0x40007110\r
+.set CYDEV_PHUB_CH16_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH16_BASIC_CFG, 0x40007110\r
+.set CYDEV_PHUB_CH16_ACTION, 0x40007114\r
+.set CYDEV_PHUB_CH16_BASIC_STATUS, 0x40007118\r
+.set CYDEV_PHUB_CH17_BASE, 0x40007120\r
+.set CYDEV_PHUB_CH17_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH17_BASIC_CFG, 0x40007120\r
+.set CYDEV_PHUB_CH17_ACTION, 0x40007124\r
+.set CYDEV_PHUB_CH17_BASIC_STATUS, 0x40007128\r
+.set CYDEV_PHUB_CH18_BASE, 0x40007130\r
+.set CYDEV_PHUB_CH18_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH18_BASIC_CFG, 0x40007130\r
+.set CYDEV_PHUB_CH18_ACTION, 0x40007134\r
+.set CYDEV_PHUB_CH18_BASIC_STATUS, 0x40007138\r
+.set CYDEV_PHUB_CH19_BASE, 0x40007140\r
+.set CYDEV_PHUB_CH19_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH19_BASIC_CFG, 0x40007140\r
+.set CYDEV_PHUB_CH19_ACTION, 0x40007144\r
+.set CYDEV_PHUB_CH19_BASIC_STATUS, 0x40007148\r
+.set CYDEV_PHUB_CH20_BASE, 0x40007150\r
+.set CYDEV_PHUB_CH20_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH20_BASIC_CFG, 0x40007150\r
+.set CYDEV_PHUB_CH20_ACTION, 0x40007154\r
+.set CYDEV_PHUB_CH20_BASIC_STATUS, 0x40007158\r
+.set CYDEV_PHUB_CH21_BASE, 0x40007160\r
+.set CYDEV_PHUB_CH21_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH21_BASIC_CFG, 0x40007160\r
+.set CYDEV_PHUB_CH21_ACTION, 0x40007164\r
+.set CYDEV_PHUB_CH21_BASIC_STATUS, 0x40007168\r
+.set CYDEV_PHUB_CH22_BASE, 0x40007170\r
+.set CYDEV_PHUB_CH22_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH22_BASIC_CFG, 0x40007170\r
+.set CYDEV_PHUB_CH22_ACTION, 0x40007174\r
+.set CYDEV_PHUB_CH22_BASIC_STATUS, 0x40007178\r
+.set CYDEV_PHUB_CH23_BASE, 0x40007180\r
+.set CYDEV_PHUB_CH23_SIZE, 0x0000000c\r
+.set CYDEV_PHUB_CH23_BASIC_CFG, 0x40007180\r
+.set CYDEV_PHUB_CH23_ACTION, 0x40007184\r
+.set CYDEV_PHUB_CH23_BASIC_STATUS, 0x40007188\r
+.set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600\r
+.set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM0_CFG0, 0x40007600\r
+.set CYDEV_PHUB_CFGMEM0_CFG1, 0x40007604\r
+.set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608\r
+.set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM1_CFG0, 0x40007608\r
+.set CYDEV_PHUB_CFGMEM1_CFG1, 0x4000760c\r
+.set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610\r
+.set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM2_CFG0, 0x40007610\r
+.set CYDEV_PHUB_CFGMEM2_CFG1, 0x40007614\r
+.set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618\r
+.set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM3_CFG0, 0x40007618\r
+.set CYDEV_PHUB_CFGMEM3_CFG1, 0x4000761c\r
+.set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620\r
+.set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM4_CFG0, 0x40007620\r
+.set CYDEV_PHUB_CFGMEM4_CFG1, 0x40007624\r
+.set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628\r
+.set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM5_CFG0, 0x40007628\r
+.set CYDEV_PHUB_CFGMEM5_CFG1, 0x4000762c\r
+.set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630\r
+.set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM6_CFG0, 0x40007630\r
+.set CYDEV_PHUB_CFGMEM6_CFG1, 0x40007634\r
+.set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638\r
+.set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM7_CFG0, 0x40007638\r
+.set CYDEV_PHUB_CFGMEM7_CFG1, 0x4000763c\r
+.set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640\r
+.set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM8_CFG0, 0x40007640\r
+.set CYDEV_PHUB_CFGMEM8_CFG1, 0x40007644\r
+.set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648\r
+.set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM9_CFG0, 0x40007648\r
+.set CYDEV_PHUB_CFGMEM9_CFG1, 0x4000764c\r
+.set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650\r
+.set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM10_CFG0, 0x40007650\r
+.set CYDEV_PHUB_CFGMEM10_CFG1, 0x40007654\r
+.set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658\r
+.set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM11_CFG0, 0x40007658\r
+.set CYDEV_PHUB_CFGMEM11_CFG1, 0x4000765c\r
+.set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660\r
+.set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM12_CFG0, 0x40007660\r
+.set CYDEV_PHUB_CFGMEM12_CFG1, 0x40007664\r
+.set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668\r
+.set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM13_CFG0, 0x40007668\r
+.set CYDEV_PHUB_CFGMEM13_CFG1, 0x4000766c\r
+.set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670\r
+.set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM14_CFG0, 0x40007670\r
+.set CYDEV_PHUB_CFGMEM14_CFG1, 0x40007674\r
+.set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678\r
+.set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM15_CFG0, 0x40007678\r
+.set CYDEV_PHUB_CFGMEM15_CFG1, 0x4000767c\r
+.set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680\r
+.set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM16_CFG0, 0x40007680\r
+.set CYDEV_PHUB_CFGMEM16_CFG1, 0x40007684\r
+.set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688\r
+.set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM17_CFG0, 0x40007688\r
+.set CYDEV_PHUB_CFGMEM17_CFG1, 0x4000768c\r
+.set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690\r
+.set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM18_CFG0, 0x40007690\r
+.set CYDEV_PHUB_CFGMEM18_CFG1, 0x40007694\r
+.set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698\r
+.set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM19_CFG0, 0x40007698\r
+.set CYDEV_PHUB_CFGMEM19_CFG1, 0x4000769c\r
+.set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0\r
+.set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM20_CFG0, 0x400076a0\r
+.set CYDEV_PHUB_CFGMEM20_CFG1, 0x400076a4\r
+.set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8\r
+.set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM21_CFG0, 0x400076a8\r
+.set CYDEV_PHUB_CFGMEM21_CFG1, 0x400076ac\r
+.set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0\r
+.set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM22_CFG0, 0x400076b0\r
+.set CYDEV_PHUB_CFGMEM22_CFG1, 0x400076b4\r
+.set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8\r
+.set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008\r
+.set CYDEV_PHUB_CFGMEM23_CFG0, 0x400076b8\r
+.set CYDEV_PHUB_CFGMEM23_CFG1, 0x400076bc\r
+.set CYDEV_PHUB_TDMEM0_BASE, 0x40007800\r
+.set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM0_ORIG_TD0, 0x40007800\r
+.set CYDEV_PHUB_TDMEM0_ORIG_TD1, 0x40007804\r
+.set CYDEV_PHUB_TDMEM1_BASE, 0x40007808\r
+.set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM1_ORIG_TD0, 0x40007808\r
+.set CYDEV_PHUB_TDMEM1_ORIG_TD1, 0x4000780c\r
+.set CYDEV_PHUB_TDMEM2_BASE, 0x40007810\r
+.set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM2_ORIG_TD0, 0x40007810\r
+.set CYDEV_PHUB_TDMEM2_ORIG_TD1, 0x40007814\r
+.set CYDEV_PHUB_TDMEM3_BASE, 0x40007818\r
+.set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM3_ORIG_TD0, 0x40007818\r
+.set CYDEV_PHUB_TDMEM3_ORIG_TD1, 0x4000781c\r
+.set CYDEV_PHUB_TDMEM4_BASE, 0x40007820\r
+.set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM4_ORIG_TD0, 0x40007820\r
+.set CYDEV_PHUB_TDMEM4_ORIG_TD1, 0x40007824\r
+.set CYDEV_PHUB_TDMEM5_BASE, 0x40007828\r
+.set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM5_ORIG_TD0, 0x40007828\r
+.set CYDEV_PHUB_TDMEM5_ORIG_TD1, 0x4000782c\r
+.set CYDEV_PHUB_TDMEM6_BASE, 0x40007830\r
+.set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM6_ORIG_TD0, 0x40007830\r
+.set CYDEV_PHUB_TDMEM6_ORIG_TD1, 0x40007834\r
+.set CYDEV_PHUB_TDMEM7_BASE, 0x40007838\r
+.set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM7_ORIG_TD0, 0x40007838\r
+.set CYDEV_PHUB_TDMEM7_ORIG_TD1, 0x4000783c\r
+.set CYDEV_PHUB_TDMEM8_BASE, 0x40007840\r
+.set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM8_ORIG_TD0, 0x40007840\r
+.set CYDEV_PHUB_TDMEM8_ORIG_TD1, 0x40007844\r
+.set CYDEV_PHUB_TDMEM9_BASE, 0x40007848\r
+.set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM9_ORIG_TD0, 0x40007848\r
+.set CYDEV_PHUB_TDMEM9_ORIG_TD1, 0x4000784c\r
+.set CYDEV_PHUB_TDMEM10_BASE, 0x40007850\r
+.set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM10_ORIG_TD0, 0x40007850\r
+.set CYDEV_PHUB_TDMEM10_ORIG_TD1, 0x40007854\r
+.set CYDEV_PHUB_TDMEM11_BASE, 0x40007858\r
+.set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM11_ORIG_TD0, 0x40007858\r
+.set CYDEV_PHUB_TDMEM11_ORIG_TD1, 0x4000785c\r
+.set CYDEV_PHUB_TDMEM12_BASE, 0x40007860\r
+.set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM12_ORIG_TD0, 0x40007860\r
+.set CYDEV_PHUB_TDMEM12_ORIG_TD1, 0x40007864\r
+.set CYDEV_PHUB_TDMEM13_BASE, 0x40007868\r
+.set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM13_ORIG_TD0, 0x40007868\r
+.set CYDEV_PHUB_TDMEM13_ORIG_TD1, 0x4000786c\r
+.set CYDEV_PHUB_TDMEM14_BASE, 0x40007870\r
+.set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM14_ORIG_TD0, 0x40007870\r
+.set CYDEV_PHUB_TDMEM14_ORIG_TD1, 0x40007874\r
+.set CYDEV_PHUB_TDMEM15_BASE, 0x40007878\r
+.set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM15_ORIG_TD0, 0x40007878\r
+.set CYDEV_PHUB_TDMEM15_ORIG_TD1, 0x4000787c\r
+.set CYDEV_PHUB_TDMEM16_BASE, 0x40007880\r
+.set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM16_ORIG_TD0, 0x40007880\r
+.set CYDEV_PHUB_TDMEM16_ORIG_TD1, 0x40007884\r
+.set CYDEV_PHUB_TDMEM17_BASE, 0x40007888\r
+.set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM17_ORIG_TD0, 0x40007888\r
+.set CYDEV_PHUB_TDMEM17_ORIG_TD1, 0x4000788c\r
+.set CYDEV_PHUB_TDMEM18_BASE, 0x40007890\r
+.set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM18_ORIG_TD0, 0x40007890\r
+.set CYDEV_PHUB_TDMEM18_ORIG_TD1, 0x40007894\r
+.set CYDEV_PHUB_TDMEM19_BASE, 0x40007898\r
+.set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM19_ORIG_TD0, 0x40007898\r
+.set CYDEV_PHUB_TDMEM19_ORIG_TD1, 0x4000789c\r
+.set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0\r
+.set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM20_ORIG_TD0, 0x400078a0\r
+.set CYDEV_PHUB_TDMEM20_ORIG_TD1, 0x400078a4\r
+.set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8\r
+.set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM21_ORIG_TD0, 0x400078a8\r
+.set CYDEV_PHUB_TDMEM21_ORIG_TD1, 0x400078ac\r
+.set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0\r
+.set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM22_ORIG_TD0, 0x400078b0\r
+.set CYDEV_PHUB_TDMEM22_ORIG_TD1, 0x400078b4\r
+.set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8\r
+.set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM23_ORIG_TD0, 0x400078b8\r
+.set CYDEV_PHUB_TDMEM23_ORIG_TD1, 0x400078bc\r
+.set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0\r
+.set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM24_ORIG_TD0, 0x400078c0\r
+.set CYDEV_PHUB_TDMEM24_ORIG_TD1, 0x400078c4\r
+.set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8\r
+.set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM25_ORIG_TD0, 0x400078c8\r
+.set CYDEV_PHUB_TDMEM25_ORIG_TD1, 0x400078cc\r
+.set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0\r
+.set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM26_ORIG_TD0, 0x400078d0\r
+.set CYDEV_PHUB_TDMEM26_ORIG_TD1, 0x400078d4\r
+.set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8\r
+.set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM27_ORIG_TD0, 0x400078d8\r
+.set CYDEV_PHUB_TDMEM27_ORIG_TD1, 0x400078dc\r
+.set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0\r
+.set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM28_ORIG_TD0, 0x400078e0\r
+.set CYDEV_PHUB_TDMEM28_ORIG_TD1, 0x400078e4\r
+.set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8\r
+.set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM29_ORIG_TD0, 0x400078e8\r
+.set CYDEV_PHUB_TDMEM29_ORIG_TD1, 0x400078ec\r
+.set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0\r
+.set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM30_ORIG_TD0, 0x400078f0\r
+.set CYDEV_PHUB_TDMEM30_ORIG_TD1, 0x400078f4\r
+.set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8\r
+.set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM31_ORIG_TD0, 0x400078f8\r
+.set CYDEV_PHUB_TDMEM31_ORIG_TD1, 0x400078fc\r
+.set CYDEV_PHUB_TDMEM32_BASE, 0x40007900\r
+.set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM32_ORIG_TD0, 0x40007900\r
+.set CYDEV_PHUB_TDMEM32_ORIG_TD1, 0x40007904\r
+.set CYDEV_PHUB_TDMEM33_BASE, 0x40007908\r
+.set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM33_ORIG_TD0, 0x40007908\r
+.set CYDEV_PHUB_TDMEM33_ORIG_TD1, 0x4000790c\r
+.set CYDEV_PHUB_TDMEM34_BASE, 0x40007910\r
+.set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM34_ORIG_TD0, 0x40007910\r
+.set CYDEV_PHUB_TDMEM34_ORIG_TD1, 0x40007914\r
+.set CYDEV_PHUB_TDMEM35_BASE, 0x40007918\r
+.set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM35_ORIG_TD0, 0x40007918\r
+.set CYDEV_PHUB_TDMEM35_ORIG_TD1, 0x4000791c\r
+.set CYDEV_PHUB_TDMEM36_BASE, 0x40007920\r
+.set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM36_ORIG_TD0, 0x40007920\r
+.set CYDEV_PHUB_TDMEM36_ORIG_TD1, 0x40007924\r
+.set CYDEV_PHUB_TDMEM37_BASE, 0x40007928\r
+.set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM37_ORIG_TD0, 0x40007928\r
+.set CYDEV_PHUB_TDMEM37_ORIG_TD1, 0x4000792c\r
+.set CYDEV_PHUB_TDMEM38_BASE, 0x40007930\r
+.set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM38_ORIG_TD0, 0x40007930\r
+.set CYDEV_PHUB_TDMEM38_ORIG_TD1, 0x40007934\r
+.set CYDEV_PHUB_TDMEM39_BASE, 0x40007938\r
+.set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM39_ORIG_TD0, 0x40007938\r
+.set CYDEV_PHUB_TDMEM39_ORIG_TD1, 0x4000793c\r
+.set CYDEV_PHUB_TDMEM40_BASE, 0x40007940\r
+.set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM40_ORIG_TD0, 0x40007940\r
+.set CYDEV_PHUB_TDMEM40_ORIG_TD1, 0x40007944\r
+.set CYDEV_PHUB_TDMEM41_BASE, 0x40007948\r
+.set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM41_ORIG_TD0, 0x40007948\r
+.set CYDEV_PHUB_TDMEM41_ORIG_TD1, 0x4000794c\r
+.set CYDEV_PHUB_TDMEM42_BASE, 0x40007950\r
+.set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM42_ORIG_TD0, 0x40007950\r
+.set CYDEV_PHUB_TDMEM42_ORIG_TD1, 0x40007954\r
+.set CYDEV_PHUB_TDMEM43_BASE, 0x40007958\r
+.set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM43_ORIG_TD0, 0x40007958\r
+.set CYDEV_PHUB_TDMEM43_ORIG_TD1, 0x4000795c\r
+.set CYDEV_PHUB_TDMEM44_BASE, 0x40007960\r
+.set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM44_ORIG_TD0, 0x40007960\r
+.set CYDEV_PHUB_TDMEM44_ORIG_TD1, 0x40007964\r
+.set CYDEV_PHUB_TDMEM45_BASE, 0x40007968\r
+.set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM45_ORIG_TD0, 0x40007968\r
+.set CYDEV_PHUB_TDMEM45_ORIG_TD1, 0x4000796c\r
+.set CYDEV_PHUB_TDMEM46_BASE, 0x40007970\r
+.set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM46_ORIG_TD0, 0x40007970\r
+.set CYDEV_PHUB_TDMEM46_ORIG_TD1, 0x40007974\r
+.set CYDEV_PHUB_TDMEM47_BASE, 0x40007978\r
+.set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM47_ORIG_TD0, 0x40007978\r
+.set CYDEV_PHUB_TDMEM47_ORIG_TD1, 0x4000797c\r
+.set CYDEV_PHUB_TDMEM48_BASE, 0x40007980\r
+.set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM48_ORIG_TD0, 0x40007980\r
+.set CYDEV_PHUB_TDMEM48_ORIG_TD1, 0x40007984\r
+.set CYDEV_PHUB_TDMEM49_BASE, 0x40007988\r
+.set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM49_ORIG_TD0, 0x40007988\r
+.set CYDEV_PHUB_TDMEM49_ORIG_TD1, 0x4000798c\r
+.set CYDEV_PHUB_TDMEM50_BASE, 0x40007990\r
+.set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM50_ORIG_TD0, 0x40007990\r
+.set CYDEV_PHUB_TDMEM50_ORIG_TD1, 0x40007994\r
+.set CYDEV_PHUB_TDMEM51_BASE, 0x40007998\r
+.set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM51_ORIG_TD0, 0x40007998\r
+.set CYDEV_PHUB_TDMEM51_ORIG_TD1, 0x4000799c\r
+.set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0\r
+.set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM52_ORIG_TD0, 0x400079a0\r
+.set CYDEV_PHUB_TDMEM52_ORIG_TD1, 0x400079a4\r
+.set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8\r
+.set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM53_ORIG_TD0, 0x400079a8\r
+.set CYDEV_PHUB_TDMEM53_ORIG_TD1, 0x400079ac\r
+.set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0\r
+.set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM54_ORIG_TD0, 0x400079b0\r
+.set CYDEV_PHUB_TDMEM54_ORIG_TD1, 0x400079b4\r
+.set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8\r
+.set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM55_ORIG_TD0, 0x400079b8\r
+.set CYDEV_PHUB_TDMEM55_ORIG_TD1, 0x400079bc\r
+.set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0\r
+.set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM56_ORIG_TD0, 0x400079c0\r
+.set CYDEV_PHUB_TDMEM56_ORIG_TD1, 0x400079c4\r
+.set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8\r
+.set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM57_ORIG_TD0, 0x400079c8\r
+.set CYDEV_PHUB_TDMEM57_ORIG_TD1, 0x400079cc\r
+.set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0\r
+.set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM58_ORIG_TD0, 0x400079d0\r
+.set CYDEV_PHUB_TDMEM58_ORIG_TD1, 0x400079d4\r
+.set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8\r
+.set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM59_ORIG_TD0, 0x400079d8\r
+.set CYDEV_PHUB_TDMEM59_ORIG_TD1, 0x400079dc\r
+.set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0\r
+.set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM60_ORIG_TD0, 0x400079e0\r
+.set CYDEV_PHUB_TDMEM60_ORIG_TD1, 0x400079e4\r
+.set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8\r
+.set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM61_ORIG_TD0, 0x400079e8\r
+.set CYDEV_PHUB_TDMEM61_ORIG_TD1, 0x400079ec\r
+.set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0\r
+.set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM62_ORIG_TD0, 0x400079f0\r
+.set CYDEV_PHUB_TDMEM62_ORIG_TD1, 0x400079f4\r
+.set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8\r
+.set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM63_ORIG_TD0, 0x400079f8\r
+.set CYDEV_PHUB_TDMEM63_ORIG_TD1, 0x400079fc\r
+.set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00\r
+.set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM64_ORIG_TD0, 0x40007a00\r
+.set CYDEV_PHUB_TDMEM64_ORIG_TD1, 0x40007a04\r
+.set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08\r
+.set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM65_ORIG_TD0, 0x40007a08\r
+.set CYDEV_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c\r
+.set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10\r
+.set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM66_ORIG_TD0, 0x40007a10\r
+.set CYDEV_PHUB_TDMEM66_ORIG_TD1, 0x40007a14\r
+.set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18\r
+.set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM67_ORIG_TD0, 0x40007a18\r
+.set CYDEV_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c\r
+.set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20\r
+.set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM68_ORIG_TD0, 0x40007a20\r
+.set CYDEV_PHUB_TDMEM68_ORIG_TD1, 0x40007a24\r
+.set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28\r
+.set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM69_ORIG_TD0, 0x40007a28\r
+.set CYDEV_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c\r
+.set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30\r
+.set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM70_ORIG_TD0, 0x40007a30\r
+.set CYDEV_PHUB_TDMEM70_ORIG_TD1, 0x40007a34\r
+.set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38\r
+.set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM71_ORIG_TD0, 0x40007a38\r
+.set CYDEV_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c\r
+.set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40\r
+.set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM72_ORIG_TD0, 0x40007a40\r
+.set CYDEV_PHUB_TDMEM72_ORIG_TD1, 0x40007a44\r
+.set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48\r
+.set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM73_ORIG_TD0, 0x40007a48\r
+.set CYDEV_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c\r
+.set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50\r
+.set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM74_ORIG_TD0, 0x40007a50\r
+.set CYDEV_PHUB_TDMEM74_ORIG_TD1, 0x40007a54\r
+.set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58\r
+.set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM75_ORIG_TD0, 0x40007a58\r
+.set CYDEV_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c\r
+.set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60\r
+.set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM76_ORIG_TD0, 0x40007a60\r
+.set CYDEV_PHUB_TDMEM76_ORIG_TD1, 0x40007a64\r
+.set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68\r
+.set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM77_ORIG_TD0, 0x40007a68\r
+.set CYDEV_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c\r
+.set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70\r
+.set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM78_ORIG_TD0, 0x40007a70\r
+.set CYDEV_PHUB_TDMEM78_ORIG_TD1, 0x40007a74\r
+.set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78\r
+.set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM79_ORIG_TD0, 0x40007a78\r
+.set CYDEV_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c\r
+.set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80\r
+.set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM80_ORIG_TD0, 0x40007a80\r
+.set CYDEV_PHUB_TDMEM80_ORIG_TD1, 0x40007a84\r
+.set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88\r
+.set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM81_ORIG_TD0, 0x40007a88\r
+.set CYDEV_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c\r
+.set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90\r
+.set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM82_ORIG_TD0, 0x40007a90\r
+.set CYDEV_PHUB_TDMEM82_ORIG_TD1, 0x40007a94\r
+.set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98\r
+.set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM83_ORIG_TD0, 0x40007a98\r
+.set CYDEV_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c\r
+.set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0\r
+.set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0\r
+.set CYDEV_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4\r
+.set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8\r
+.set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8\r
+.set CYDEV_PHUB_TDMEM85_ORIG_TD1, 0x40007aac\r
+.set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0\r
+.set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0\r
+.set CYDEV_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4\r
+.set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8\r
+.set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8\r
+.set CYDEV_PHUB_TDMEM87_ORIG_TD1, 0x40007abc\r
+.set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0\r
+.set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0\r
+.set CYDEV_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4\r
+.set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8\r
+.set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8\r
+.set CYDEV_PHUB_TDMEM89_ORIG_TD1, 0x40007acc\r
+.set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0\r
+.set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0\r
+.set CYDEV_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4\r
+.set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8\r
+.set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8\r
+.set CYDEV_PHUB_TDMEM91_ORIG_TD1, 0x40007adc\r
+.set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0\r
+.set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0\r
+.set CYDEV_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4\r
+.set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8\r
+.set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8\r
+.set CYDEV_PHUB_TDMEM93_ORIG_TD1, 0x40007aec\r
+.set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0\r
+.set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM94_ORIG_TD0, 0x40007af0\r
+.set CYDEV_PHUB_TDMEM94_ORIG_TD1, 0x40007af4\r
+.set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8\r
+.set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM95_ORIG_TD0, 0x40007af8\r
+.set CYDEV_PHUB_TDMEM95_ORIG_TD1, 0x40007afc\r
+.set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00\r
+.set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM96_ORIG_TD0, 0x40007b00\r
+.set CYDEV_PHUB_TDMEM96_ORIG_TD1, 0x40007b04\r
+.set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08\r
+.set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM97_ORIG_TD0, 0x40007b08\r
+.set CYDEV_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c\r
+.set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10\r
+.set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM98_ORIG_TD0, 0x40007b10\r
+.set CYDEV_PHUB_TDMEM98_ORIG_TD1, 0x40007b14\r
+.set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18\r
+.set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM99_ORIG_TD0, 0x40007b18\r
+.set CYDEV_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c\r
+.set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20\r
+.set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM100_ORIG_TD0, 0x40007b20\r
+.set CYDEV_PHUB_TDMEM100_ORIG_TD1, 0x40007b24\r
+.set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28\r
+.set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM101_ORIG_TD0, 0x40007b28\r
+.set CYDEV_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c\r
+.set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30\r
+.set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM102_ORIG_TD0, 0x40007b30\r
+.set CYDEV_PHUB_TDMEM102_ORIG_TD1, 0x40007b34\r
+.set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38\r
+.set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM103_ORIG_TD0, 0x40007b38\r
+.set CYDEV_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c\r
+.set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40\r
+.set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM104_ORIG_TD0, 0x40007b40\r
+.set CYDEV_PHUB_TDMEM104_ORIG_TD1, 0x40007b44\r
+.set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48\r
+.set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM105_ORIG_TD0, 0x40007b48\r
+.set CYDEV_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c\r
+.set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50\r
+.set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM106_ORIG_TD0, 0x40007b50\r
+.set CYDEV_PHUB_TDMEM106_ORIG_TD1, 0x40007b54\r
+.set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58\r
+.set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM107_ORIG_TD0, 0x40007b58\r
+.set CYDEV_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c\r
+.set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60\r
+.set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM108_ORIG_TD0, 0x40007b60\r
+.set CYDEV_PHUB_TDMEM108_ORIG_TD1, 0x40007b64\r
+.set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68\r
+.set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM109_ORIG_TD0, 0x40007b68\r
+.set CYDEV_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c\r
+.set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70\r
+.set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM110_ORIG_TD0, 0x40007b70\r
+.set CYDEV_PHUB_TDMEM110_ORIG_TD1, 0x40007b74\r
+.set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78\r
+.set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM111_ORIG_TD0, 0x40007b78\r
+.set CYDEV_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c\r
+.set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80\r
+.set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM112_ORIG_TD0, 0x40007b80\r
+.set CYDEV_PHUB_TDMEM112_ORIG_TD1, 0x40007b84\r
+.set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88\r
+.set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM113_ORIG_TD0, 0x40007b88\r
+.set CYDEV_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c\r
+.set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90\r
+.set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM114_ORIG_TD0, 0x40007b90\r
+.set CYDEV_PHUB_TDMEM114_ORIG_TD1, 0x40007b94\r
+.set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98\r
+.set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM115_ORIG_TD0, 0x40007b98\r
+.set CYDEV_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c\r
+.set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0\r
+.set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0\r
+.set CYDEV_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4\r
+.set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8\r
+.set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8\r
+.set CYDEV_PHUB_TDMEM117_ORIG_TD1, 0x40007bac\r
+.set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0\r
+.set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0\r
+.set CYDEV_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4\r
+.set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8\r
+.set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8\r
+.set CYDEV_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc\r
+.set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0\r
+.set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0\r
+.set CYDEV_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4\r
+.set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8\r
+.set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8\r
+.set CYDEV_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc\r
+.set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0\r
+.set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0\r
+.set CYDEV_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4\r
+.set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8\r
+.set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8\r
+.set CYDEV_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc\r
+.set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0\r
+.set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM124_ORIG_TD0, 0x40007be0\r
+.set CYDEV_PHUB_TDMEM124_ORIG_TD1, 0x40007be4\r
+.set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8\r
+.set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM125_ORIG_TD0, 0x40007be8\r
+.set CYDEV_PHUB_TDMEM125_ORIG_TD1, 0x40007bec\r
+.set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0\r
+.set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0\r
+.set CYDEV_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4\r
+.set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8\r
+.set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008\r
+.set CYDEV_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8\r
+.set CYDEV_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc\r
+.set CYDEV_EE_BASE, 0x40008000\r
+.set CYDEV_EE_SIZE, 0x00000800\r
+.set CYDEV_EE_DATA_MBASE, 0x40008000\r
+.set CYDEV_EE_DATA_MSIZE, 0x00000800\r
+.set CYDEV_CAN0_BASE, 0x4000a000\r
+.set CYDEV_CAN0_SIZE, 0x000002a0\r
+.set CYDEV_CAN0_CSR_BASE, 0x4000a000\r
+.set CYDEV_CAN0_CSR_SIZE, 0x00000018\r
+.set CYDEV_CAN0_CSR_INT_SR, 0x4000a000\r
+.set CYDEV_CAN0_CSR_INT_EN, 0x4000a004\r
+.set CYDEV_CAN0_CSR_BUF_SR, 0x4000a008\r
+.set CYDEV_CAN0_CSR_ERR_SR, 0x4000a00c\r
+.set CYDEV_CAN0_CSR_CMD, 0x4000a010\r
+.set CYDEV_CAN0_CSR_CFG, 0x4000a014\r
+.set CYDEV_CAN0_TX0_BASE, 0x4000a020\r
+.set CYDEV_CAN0_TX0_SIZE, 0x00000010\r
+.set CYDEV_CAN0_TX0_CMD, 0x4000a020\r
+.set CYDEV_CAN0_TX0_ID, 0x4000a024\r
+.set CYDEV_CAN0_TX0_DH, 0x4000a028\r
+.set CYDEV_CAN0_TX0_DL, 0x4000a02c\r
+.set CYDEV_CAN0_TX1_BASE, 0x4000a030\r
+.set CYDEV_CAN0_TX1_SIZE, 0x00000010\r
+.set CYDEV_CAN0_TX1_CMD, 0x4000a030\r
+.set CYDEV_CAN0_TX1_ID, 0x4000a034\r
+.set CYDEV_CAN0_TX1_DH, 0x4000a038\r
+.set CYDEV_CAN0_TX1_DL, 0x4000a03c\r
+.set CYDEV_CAN0_TX2_BASE, 0x4000a040\r
+.set CYDEV_CAN0_TX2_SIZE, 0x00000010\r
+.set CYDEV_CAN0_TX2_CMD, 0x4000a040\r
+.set CYDEV_CAN0_TX2_ID, 0x4000a044\r
+.set CYDEV_CAN0_TX2_DH, 0x4000a048\r
+.set CYDEV_CAN0_TX2_DL, 0x4000a04c\r
+.set CYDEV_CAN0_TX3_BASE, 0x4000a050\r
+.set CYDEV_CAN0_TX3_SIZE, 0x00000010\r
+.set CYDEV_CAN0_TX3_CMD, 0x4000a050\r
+.set CYDEV_CAN0_TX3_ID, 0x4000a054\r
+.set CYDEV_CAN0_TX3_DH, 0x4000a058\r
+.set CYDEV_CAN0_TX3_DL, 0x4000a05c\r
+.set CYDEV_CAN0_TX4_BASE, 0x4000a060\r
+.set CYDEV_CAN0_TX4_SIZE, 0x00000010\r
+.set CYDEV_CAN0_TX4_CMD, 0x4000a060\r
+.set CYDEV_CAN0_TX4_ID, 0x4000a064\r
+.set CYDEV_CAN0_TX4_DH, 0x4000a068\r
+.set CYDEV_CAN0_TX4_DL, 0x4000a06c\r
+.set CYDEV_CAN0_TX5_BASE, 0x4000a070\r
+.set CYDEV_CAN0_TX5_SIZE, 0x00000010\r
+.set CYDEV_CAN0_TX5_CMD, 0x4000a070\r
+.set CYDEV_CAN0_TX5_ID, 0x4000a074\r
+.set CYDEV_CAN0_TX5_DH, 0x4000a078\r
+.set CYDEV_CAN0_TX5_DL, 0x4000a07c\r
+.set CYDEV_CAN0_TX6_BASE, 0x4000a080\r
+.set CYDEV_CAN0_TX6_SIZE, 0x00000010\r
+.set CYDEV_CAN0_TX6_CMD, 0x4000a080\r
+.set CYDEV_CAN0_TX6_ID, 0x4000a084\r
+.set CYDEV_CAN0_TX6_DH, 0x4000a088\r
+.set CYDEV_CAN0_TX6_DL, 0x4000a08c\r
+.set CYDEV_CAN0_TX7_BASE, 0x4000a090\r
+.set CYDEV_CAN0_TX7_SIZE, 0x00000010\r
+.set CYDEV_CAN0_TX7_CMD, 0x4000a090\r
+.set CYDEV_CAN0_TX7_ID, 0x4000a094\r
+.set CYDEV_CAN0_TX7_DH, 0x4000a098\r
+.set CYDEV_CAN0_TX7_DL, 0x4000a09c\r
+.set CYDEV_CAN0_RX0_BASE, 0x4000a0a0\r
+.set CYDEV_CAN0_RX0_SIZE, 0x00000020\r
+.set CYDEV_CAN0_RX0_CMD, 0x4000a0a0\r
+.set CYDEV_CAN0_RX0_ID, 0x4000a0a4\r
+.set CYDEV_CAN0_RX0_DH, 0x4000a0a8\r
+.set CYDEV_CAN0_RX0_DL, 0x4000a0ac\r
+.set CYDEV_CAN0_RX0_AMR, 0x4000a0b0\r
+.set CYDEV_CAN0_RX0_ACR, 0x4000a0b4\r
+.set CYDEV_CAN0_RX0_AMRD, 0x4000a0b8\r
+.set CYDEV_CAN0_RX0_ACRD, 0x4000a0bc\r
+.set CYDEV_CAN0_RX1_BASE, 0x4000a0c0\r
+.set CYDEV_CAN0_RX1_SIZE, 0x00000020\r
+.set CYDEV_CAN0_RX1_CMD, 0x4000a0c0\r
+.set CYDEV_CAN0_RX1_ID, 0x4000a0c4\r
+.set CYDEV_CAN0_RX1_DH, 0x4000a0c8\r
+.set CYDEV_CAN0_RX1_DL, 0x4000a0cc\r
+.set CYDEV_CAN0_RX1_AMR, 0x4000a0d0\r
+.set CYDEV_CAN0_RX1_ACR, 0x4000a0d4\r
+.set CYDEV_CAN0_RX1_AMRD, 0x4000a0d8\r
+.set CYDEV_CAN0_RX1_ACRD, 0x4000a0dc\r
+.set CYDEV_CAN0_RX2_BASE, 0x4000a0e0\r
+.set CYDEV_CAN0_RX2_SIZE, 0x00000020\r
+.set CYDEV_CAN0_RX2_CMD, 0x4000a0e0\r
+.set CYDEV_CAN0_RX2_ID, 0x4000a0e4\r
+.set CYDEV_CAN0_RX2_DH, 0x4000a0e8\r
+.set CYDEV_CAN0_RX2_DL, 0x4000a0ec\r
+.set CYDEV_CAN0_RX2_AMR, 0x4000a0f0\r
+.set CYDEV_CAN0_RX2_ACR, 0x4000a0f4\r
+.set CYDEV_CAN0_RX2_AMRD, 0x4000a0f8\r
+.set CYDEV_CAN0_RX2_ACRD, 0x4000a0fc\r
+.set CYDEV_CAN0_RX3_BASE, 0x4000a100\r
+.set CYDEV_CAN0_RX3_SIZE, 0x00000020\r
+.set CYDEV_CAN0_RX3_CMD, 0x4000a100\r
+.set CYDEV_CAN0_RX3_ID, 0x4000a104\r
+.set CYDEV_CAN0_RX3_DH, 0x4000a108\r
+.set CYDEV_CAN0_RX3_DL, 0x4000a10c\r
+.set CYDEV_CAN0_RX3_AMR, 0x4000a110\r
+.set CYDEV_CAN0_RX3_ACR, 0x4000a114\r
+.set CYDEV_CAN0_RX3_AMRD, 0x4000a118\r
+.set CYDEV_CAN0_RX3_ACRD, 0x4000a11c\r
+.set CYDEV_CAN0_RX4_BASE, 0x4000a120\r
+.set CYDEV_CAN0_RX4_SIZE, 0x00000020\r
+.set CYDEV_CAN0_RX4_CMD, 0x4000a120\r
+.set CYDEV_CAN0_RX4_ID, 0x4000a124\r
+.set CYDEV_CAN0_RX4_DH, 0x4000a128\r
+.set CYDEV_CAN0_RX4_DL, 0x4000a12c\r
+.set CYDEV_CAN0_RX4_AMR, 0x4000a130\r
+.set CYDEV_CAN0_RX4_ACR, 0x4000a134\r
+.set CYDEV_CAN0_RX4_AMRD, 0x4000a138\r
+.set CYDEV_CAN0_RX4_ACRD, 0x4000a13c\r
+.set CYDEV_CAN0_RX5_BASE, 0x4000a140\r
+.set CYDEV_CAN0_RX5_SIZE, 0x00000020\r
+.set CYDEV_CAN0_RX5_CMD, 0x4000a140\r
+.set CYDEV_CAN0_RX5_ID, 0x4000a144\r
+.set CYDEV_CAN0_RX5_DH, 0x4000a148\r
+.set CYDEV_CAN0_RX5_DL, 0x4000a14c\r
+.set CYDEV_CAN0_RX5_AMR, 0x4000a150\r
+.set CYDEV_CAN0_RX5_ACR, 0x4000a154\r
+.set CYDEV_CAN0_RX5_AMRD, 0x4000a158\r
+.set CYDEV_CAN0_RX5_ACRD, 0x4000a15c\r
+.set CYDEV_CAN0_RX6_BASE, 0x4000a160\r
+.set CYDEV_CAN0_RX6_SIZE, 0x00000020\r
+.set CYDEV_CAN0_RX6_CMD, 0x4000a160\r
+.set CYDEV_CAN0_RX6_ID, 0x4000a164\r
+.set CYDEV_CAN0_RX6_DH, 0x4000a168\r
+.set CYDEV_CAN0_RX6_DL, 0x4000a16c\r
+.set CYDEV_CAN0_RX6_AMR, 0x4000a170\r
+.set CYDEV_CAN0_RX6_ACR, 0x4000a174\r
+.set CYDEV_CAN0_RX6_AMRD, 0x4000a178\r
+.set CYDEV_CAN0_RX6_ACRD, 0x4000a17c\r
+.set CYDEV_CAN0_RX7_BASE, 0x4000a180\r
+.set CYDEV_CAN0_RX7_SIZE, 0x00000020\r
+.set CYDEV_CAN0_RX7_CMD, 0x4000a180\r
+.set CYDEV_CAN0_RX7_ID, 0x4000a184\r
+.set CYDEV_CAN0_RX7_DH, 0x4000a188\r
+.set CYDEV_CAN0_RX7_DL, 0x4000a18c\r
+.set CYDEV_CAN0_RX7_AMR, 0x4000a190\r
+.set CYDEV_CAN0_RX7_ACR, 0x4000a194\r
+.set CYDEV_CAN0_RX7_AMRD, 0x4000a198\r
+.set CYDEV_CAN0_RX7_ACRD, 0x4000a19c\r
+.set CYDEV_CAN0_RX8_BASE, 0x4000a1a0\r
+.set CYDEV_CAN0_RX8_SIZE, 0x00000020\r
+.set CYDEV_CAN0_RX8_CMD, 0x4000a1a0\r
+.set CYDEV_CAN0_RX8_ID, 0x4000a1a4\r
+.set CYDEV_CAN0_RX8_DH, 0x4000a1a8\r
+.set CYDEV_CAN0_RX8_DL, 0x4000a1ac\r
+.set CYDEV_CAN0_RX8_AMR, 0x4000a1b0\r
+.set CYDEV_CAN0_RX8_ACR, 0x4000a1b4\r
+.set CYDEV_CAN0_RX8_AMRD, 0x4000a1b8\r
+.set CYDEV_CAN0_RX8_ACRD, 0x4000a1bc\r
+.set CYDEV_CAN0_RX9_BASE, 0x4000a1c0\r
+.set CYDEV_CAN0_RX9_SIZE, 0x00000020\r
+.set CYDEV_CAN0_RX9_CMD, 0x4000a1c0\r
+.set CYDEV_CAN0_RX9_ID, 0x4000a1c4\r
+.set CYDEV_CAN0_RX9_DH, 0x4000a1c8\r
+.set CYDEV_CAN0_RX9_DL, 0x4000a1cc\r
+.set CYDEV_CAN0_RX9_AMR, 0x4000a1d0\r
+.set CYDEV_CAN0_RX9_ACR, 0x4000a1d4\r
+.set CYDEV_CAN0_RX9_AMRD, 0x4000a1d8\r
+.set CYDEV_CAN0_RX9_ACRD, 0x4000a1dc\r
+.set CYDEV_CAN0_RX10_BASE, 0x4000a1e0\r
+.set CYDEV_CAN0_RX10_SIZE, 0x00000020\r
+.set CYDEV_CAN0_RX10_CMD, 0x4000a1e0\r
+.set CYDEV_CAN0_RX10_ID, 0x4000a1e4\r
+.set CYDEV_CAN0_RX10_DH, 0x4000a1e8\r
+.set CYDEV_CAN0_RX10_DL, 0x4000a1ec\r
+.set CYDEV_CAN0_RX10_AMR, 0x4000a1f0\r
+.set CYDEV_CAN0_RX10_ACR, 0x4000a1f4\r
+.set CYDEV_CAN0_RX10_AMRD, 0x4000a1f8\r
+.set CYDEV_CAN0_RX10_ACRD, 0x4000a1fc\r
+.set CYDEV_CAN0_RX11_BASE, 0x4000a200\r
+.set CYDEV_CAN0_RX11_SIZE, 0x00000020\r
+.set CYDEV_CAN0_RX11_CMD, 0x4000a200\r
+.set CYDEV_CAN0_RX11_ID, 0x4000a204\r
+.set CYDEV_CAN0_RX11_DH, 0x4000a208\r
+.set CYDEV_CAN0_RX11_DL, 0x4000a20c\r
+.set CYDEV_CAN0_RX11_AMR, 0x4000a210\r
+.set CYDEV_CAN0_RX11_ACR, 0x4000a214\r
+.set CYDEV_CAN0_RX11_AMRD, 0x4000a218\r
+.set CYDEV_CAN0_RX11_ACRD, 0x4000a21c\r
+.set CYDEV_CAN0_RX12_BASE, 0x4000a220\r
+.set CYDEV_CAN0_RX12_SIZE, 0x00000020\r
+.set CYDEV_CAN0_RX12_CMD, 0x4000a220\r
+.set CYDEV_CAN0_RX12_ID, 0x4000a224\r
+.set CYDEV_CAN0_RX12_DH, 0x4000a228\r
+.set CYDEV_CAN0_RX12_DL, 0x4000a22c\r
+.set CYDEV_CAN0_RX12_AMR, 0x4000a230\r
+.set CYDEV_CAN0_RX12_ACR, 0x4000a234\r
+.set CYDEV_CAN0_RX12_AMRD, 0x4000a238\r
+.set CYDEV_CAN0_RX12_ACRD, 0x4000a23c\r
+.set CYDEV_CAN0_RX13_BASE, 0x4000a240\r
+.set CYDEV_CAN0_RX13_SIZE, 0x00000020\r
+.set CYDEV_CAN0_RX13_CMD, 0x4000a240\r
+.set CYDEV_CAN0_RX13_ID, 0x4000a244\r
+.set CYDEV_CAN0_RX13_DH, 0x4000a248\r
+.set CYDEV_CAN0_RX13_DL, 0x4000a24c\r
+.set CYDEV_CAN0_RX13_AMR, 0x4000a250\r
+.set CYDEV_CAN0_RX13_ACR, 0x4000a254\r
+.set CYDEV_CAN0_RX13_AMRD, 0x4000a258\r
+.set CYDEV_CAN0_RX13_ACRD, 0x4000a25c\r
+.set CYDEV_CAN0_RX14_BASE, 0x4000a260\r
+.set CYDEV_CAN0_RX14_SIZE, 0x00000020\r
+.set CYDEV_CAN0_RX14_CMD, 0x4000a260\r
+.set CYDEV_CAN0_RX14_ID, 0x4000a264\r
+.set CYDEV_CAN0_RX14_DH, 0x4000a268\r
+.set CYDEV_CAN0_RX14_DL, 0x4000a26c\r
+.set CYDEV_CAN0_RX14_AMR, 0x4000a270\r
+.set CYDEV_CAN0_RX14_ACR, 0x4000a274\r
+.set CYDEV_CAN0_RX14_AMRD, 0x4000a278\r
+.set CYDEV_CAN0_RX14_ACRD, 0x4000a27c\r
+.set CYDEV_CAN0_RX15_BASE, 0x4000a280\r
+.set CYDEV_CAN0_RX15_SIZE, 0x00000020\r
+.set CYDEV_CAN0_RX15_CMD, 0x4000a280\r
+.set CYDEV_CAN0_RX15_ID, 0x4000a284\r
+.set CYDEV_CAN0_RX15_DH, 0x4000a288\r
+.set CYDEV_CAN0_RX15_DL, 0x4000a28c\r
+.set CYDEV_CAN0_RX15_AMR, 0x4000a290\r
+.set CYDEV_CAN0_RX15_ACR, 0x4000a294\r
+.set CYDEV_CAN0_RX15_AMRD, 0x4000a298\r
+.set CYDEV_CAN0_RX15_ACRD, 0x4000a29c\r
+.set CYDEV_DFB0_BASE, 0x4000c000\r
+.set CYDEV_DFB0_SIZE, 0x000007b5\r
+.set CYDEV_DFB0_DPA_SRAM_BASE, 0x4000c000\r
+.set CYDEV_DFB0_DPA_SRAM_SIZE, 0x00000200\r
+.set CYDEV_DFB0_DPA_SRAM_DATA_MBASE, 0x4000c000\r
+.set CYDEV_DFB0_DPA_SRAM_DATA_MSIZE, 0x00000200\r
+.set CYDEV_DFB0_DPB_SRAM_BASE, 0x4000c200\r
+.set CYDEV_DFB0_DPB_SRAM_SIZE, 0x00000200\r
+.set CYDEV_DFB0_DPB_SRAM_DATA_MBASE, 0x4000c200\r
+.set CYDEV_DFB0_DPB_SRAM_DATA_MSIZE, 0x00000200\r
+.set CYDEV_DFB0_CSA_SRAM_BASE, 0x4000c400\r
+.set CYDEV_DFB0_CSA_SRAM_SIZE, 0x00000100\r
+.set CYDEV_DFB0_CSA_SRAM_DATA_MBASE, 0x4000c400\r
+.set CYDEV_DFB0_CSA_SRAM_DATA_MSIZE, 0x00000100\r
+.set CYDEV_DFB0_CSB_SRAM_BASE, 0x4000c500\r
+.set CYDEV_DFB0_CSB_SRAM_SIZE, 0x00000100\r
+.set CYDEV_DFB0_CSB_SRAM_DATA_MBASE, 0x4000c500\r
+.set CYDEV_DFB0_CSB_SRAM_DATA_MSIZE, 0x00000100\r
+.set CYDEV_DFB0_FSM_SRAM_BASE, 0x4000c600\r
+.set CYDEV_DFB0_FSM_SRAM_SIZE, 0x00000100\r
+.set CYDEV_DFB0_FSM_SRAM_DATA_MBASE, 0x4000c600\r
+.set CYDEV_DFB0_FSM_SRAM_DATA_MSIZE, 0x00000100\r
+.set CYDEV_DFB0_ACU_SRAM_BASE, 0x4000c700\r
+.set CYDEV_DFB0_ACU_SRAM_SIZE, 0x00000040\r
+.set CYDEV_DFB0_ACU_SRAM_DATA_MBASE, 0x4000c700\r
+.set CYDEV_DFB0_ACU_SRAM_DATA_MSIZE, 0x00000040\r
+.set CYDEV_DFB0_CR, 0x4000c780\r
+.set CYDEV_DFB0_SR, 0x4000c784\r
+.set CYDEV_DFB0_RAM_EN, 0x4000c788\r
+.set CYDEV_DFB0_RAM_DIR, 0x4000c78c\r
+.set CYDEV_DFB0_SEMA, 0x4000c790\r
+.set CYDEV_DFB0_DSI_CTRL, 0x4000c794\r
+.set CYDEV_DFB0_INT_CTRL, 0x4000c798\r
+.set CYDEV_DFB0_DMA_CTRL, 0x4000c79c\r
+.set CYDEV_DFB0_STAGEA, 0x4000c7a0\r
+.set CYDEV_DFB0_STAGEAM, 0x4000c7a1\r
+.set CYDEV_DFB0_STAGEAH, 0x4000c7a2\r
+.set CYDEV_DFB0_STAGEB, 0x4000c7a4\r
+.set CYDEV_DFB0_STAGEBM, 0x4000c7a5\r
+.set CYDEV_DFB0_STAGEBH, 0x4000c7a6\r
+.set CYDEV_DFB0_HOLDA, 0x4000c7a8\r
+.set CYDEV_DFB0_HOLDAM, 0x4000c7a9\r
+.set CYDEV_DFB0_HOLDAH, 0x4000c7aa\r
+.set CYDEV_DFB0_HOLDAS, 0x4000c7ab\r
+.set CYDEV_DFB0_HOLDB, 0x4000c7ac\r
+.set CYDEV_DFB0_HOLDBM, 0x4000c7ad\r
+.set CYDEV_DFB0_HOLDBH, 0x4000c7ae\r
+.set CYDEV_DFB0_HOLDBS, 0x4000c7af\r
+.set CYDEV_DFB0_COHER, 0x4000c7b0\r
+.set CYDEV_DFB0_DALIGN, 0x4000c7b4\r
+.set CYDEV_UCFG_BASE, 0x40010000\r
+.set CYDEV_UCFG_SIZE, 0x00005040\r
+.set CYDEV_UCFG_B0_BASE, 0x40010000\r
+.set CYDEV_UCFG_B0_SIZE, 0x00000fef\r
+.set CYDEV_UCFG_B0_P0_BASE, 0x40010000\r
+.set CYDEV_UCFG_B0_P0_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B0_P0_U0_BASE, 0x40010000\r
+.set CYDEV_UCFG_B0_P0_U0_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B0_P0_U0_PLD_IT0, 0x40010000\r
+.set CYDEV_UCFG_B0_P0_U0_PLD_IT1, 0x40010004\r
+.set CYDEV_UCFG_B0_P0_U0_PLD_IT2, 0x40010008\r
+.set CYDEV_UCFG_B0_P0_U0_PLD_IT3, 0x4001000c\r
+.set CYDEV_UCFG_B0_P0_U0_PLD_IT4, 0x40010010\r
+.set CYDEV_UCFG_B0_P0_U0_PLD_IT5, 0x40010014\r
+.set CYDEV_UCFG_B0_P0_U0_PLD_IT6, 0x40010018\r
+.set CYDEV_UCFG_B0_P0_U0_PLD_IT7, 0x4001001c\r
+.set CYDEV_UCFG_B0_P0_U0_PLD_IT8, 0x40010020\r
+.set CYDEV_UCFG_B0_P0_U0_PLD_IT9, 0x40010024\r
+.set CYDEV_UCFG_B0_P0_U0_PLD_IT10, 0x40010028\r
+.set CYDEV_UCFG_B0_P0_U0_PLD_IT11, 0x4001002c\r
+.set CYDEV_UCFG_B0_P0_U0_PLD_ORT0, 0x40010030\r
+.set CYDEV_UCFG_B0_P0_U0_PLD_ORT1, 0x40010032\r
+.set CYDEV_UCFG_B0_P0_U0_PLD_ORT2, 0x40010034\r
+.set CYDEV_UCFG_B0_P0_U0_PLD_ORT3, 0x40010036\r
+.set CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST, 0x40010038\r
+.set CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB, 0x4001003a\r
+.set CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET, 0x4001003c\r
+.set CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS, 0x4001003e\r
+.set CYDEV_UCFG_B0_P0_U0_CFG0, 0x40010040\r
+.set CYDEV_UCFG_B0_P0_U0_CFG1, 0x40010041\r
+.set CYDEV_UCFG_B0_P0_U0_CFG2, 0x40010042\r
+.set CYDEV_UCFG_B0_P0_U0_CFG3, 0x40010043\r
+.set CYDEV_UCFG_B0_P0_U0_CFG4, 0x40010044\r
+.set CYDEV_UCFG_B0_P0_U0_CFG5, 0x40010045\r
+.set CYDEV_UCFG_B0_P0_U0_CFG6, 0x40010046\r
+.set CYDEV_UCFG_B0_P0_U0_CFG7, 0x40010047\r
+.set CYDEV_UCFG_B0_P0_U0_CFG8, 0x40010048\r
+.set CYDEV_UCFG_B0_P0_U0_CFG9, 0x40010049\r
+.set CYDEV_UCFG_B0_P0_U0_CFG10, 0x4001004a\r
+.set CYDEV_UCFG_B0_P0_U0_CFG11, 0x4001004b\r
+.set CYDEV_UCFG_B0_P0_U0_CFG12, 0x4001004c\r
+.set CYDEV_UCFG_B0_P0_U0_CFG13, 0x4001004d\r
+.set CYDEV_UCFG_B0_P0_U0_CFG14, 0x4001004e\r
+.set CYDEV_UCFG_B0_P0_U0_CFG15, 0x4001004f\r
+.set CYDEV_UCFG_B0_P0_U0_CFG16, 0x40010050\r
+.set CYDEV_UCFG_B0_P0_U0_CFG17, 0x40010051\r
+.set CYDEV_UCFG_B0_P0_U0_CFG18, 0x40010052\r
+.set CYDEV_UCFG_B0_P0_U0_CFG19, 0x40010053\r
+.set CYDEV_UCFG_B0_P0_U0_CFG20, 0x40010054\r
+.set CYDEV_UCFG_B0_P0_U0_CFG21, 0x40010055\r
+.set CYDEV_UCFG_B0_P0_U0_CFG22, 0x40010056\r
+.set CYDEV_UCFG_B0_P0_U0_CFG23, 0x40010057\r
+.set CYDEV_UCFG_B0_P0_U0_CFG24, 0x40010058\r
+.set CYDEV_UCFG_B0_P0_U0_CFG25, 0x40010059\r
+.set CYDEV_UCFG_B0_P0_U0_CFG26, 0x4001005a\r
+.set CYDEV_UCFG_B0_P0_U0_CFG27, 0x4001005b\r
+.set CYDEV_UCFG_B0_P0_U0_CFG28, 0x4001005c\r
+.set CYDEV_UCFG_B0_P0_U0_CFG29, 0x4001005d\r
+.set CYDEV_UCFG_B0_P0_U0_CFG30, 0x4001005e\r
+.set CYDEV_UCFG_B0_P0_U0_CFG31, 0x4001005f\r
+.set CYDEV_UCFG_B0_P0_U0_DCFG0, 0x40010060\r
+.set CYDEV_UCFG_B0_P0_U0_DCFG1, 0x40010062\r
+.set CYDEV_UCFG_B0_P0_U0_DCFG2, 0x40010064\r
+.set CYDEV_UCFG_B0_P0_U0_DCFG3, 0x40010066\r
+.set CYDEV_UCFG_B0_P0_U0_DCFG4, 0x40010068\r
+.set CYDEV_UCFG_B0_P0_U0_DCFG5, 0x4001006a\r
+.set CYDEV_UCFG_B0_P0_U0_DCFG6, 0x4001006c\r
+.set CYDEV_UCFG_B0_P0_U0_DCFG7, 0x4001006e\r
+.set CYDEV_UCFG_B0_P0_U1_BASE, 0x40010080\r
+.set CYDEV_UCFG_B0_P0_U1_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B0_P0_U1_PLD_IT0, 0x40010080\r
+.set CYDEV_UCFG_B0_P0_U1_PLD_IT1, 0x40010084\r
+.set CYDEV_UCFG_B0_P0_U1_PLD_IT2, 0x40010088\r
+.set CYDEV_UCFG_B0_P0_U1_PLD_IT3, 0x4001008c\r
+.set CYDEV_UCFG_B0_P0_U1_PLD_IT4, 0x40010090\r
+.set CYDEV_UCFG_B0_P0_U1_PLD_IT5, 0x40010094\r
+.set CYDEV_UCFG_B0_P0_U1_PLD_IT6, 0x40010098\r
+.set CYDEV_UCFG_B0_P0_U1_PLD_IT7, 0x4001009c\r
+.set CYDEV_UCFG_B0_P0_U1_PLD_IT8, 0x400100a0\r
+.set CYDEV_UCFG_B0_P0_U1_PLD_IT9, 0x400100a4\r
+.set CYDEV_UCFG_B0_P0_U1_PLD_IT10, 0x400100a8\r
+.set CYDEV_UCFG_B0_P0_U1_PLD_IT11, 0x400100ac\r
+.set CYDEV_UCFG_B0_P0_U1_PLD_ORT0, 0x400100b0\r
+.set CYDEV_UCFG_B0_P0_U1_PLD_ORT1, 0x400100b2\r
+.set CYDEV_UCFG_B0_P0_U1_PLD_ORT2, 0x400100b4\r
+.set CYDEV_UCFG_B0_P0_U1_PLD_ORT3, 0x400100b6\r
+.set CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST, 0x400100b8\r
+.set CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB, 0x400100ba\r
+.set CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET, 0x400100bc\r
+.set CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS, 0x400100be\r
+.set CYDEV_UCFG_B0_P0_U1_CFG0, 0x400100c0\r
+.set CYDEV_UCFG_B0_P0_U1_CFG1, 0x400100c1\r
+.set CYDEV_UCFG_B0_P0_U1_CFG2, 0x400100c2\r
+.set CYDEV_UCFG_B0_P0_U1_CFG3, 0x400100c3\r
+.set CYDEV_UCFG_B0_P0_U1_CFG4, 0x400100c4\r
+.set CYDEV_UCFG_B0_P0_U1_CFG5, 0x400100c5\r
+.set CYDEV_UCFG_B0_P0_U1_CFG6, 0x400100c6\r
+.set CYDEV_UCFG_B0_P0_U1_CFG7, 0x400100c7\r
+.set CYDEV_UCFG_B0_P0_U1_CFG8, 0x400100c8\r
+.set CYDEV_UCFG_B0_P0_U1_CFG9, 0x400100c9\r
+.set CYDEV_UCFG_B0_P0_U1_CFG10, 0x400100ca\r
+.set CYDEV_UCFG_B0_P0_U1_CFG11, 0x400100cb\r
+.set CYDEV_UCFG_B0_P0_U1_CFG12, 0x400100cc\r
+.set CYDEV_UCFG_B0_P0_U1_CFG13, 0x400100cd\r
+.set CYDEV_UCFG_B0_P0_U1_CFG14, 0x400100ce\r
+.set CYDEV_UCFG_B0_P0_U1_CFG15, 0x400100cf\r
+.set CYDEV_UCFG_B0_P0_U1_CFG16, 0x400100d0\r
+.set CYDEV_UCFG_B0_P0_U1_CFG17, 0x400100d1\r
+.set CYDEV_UCFG_B0_P0_U1_CFG18, 0x400100d2\r
+.set CYDEV_UCFG_B0_P0_U1_CFG19, 0x400100d3\r
+.set CYDEV_UCFG_B0_P0_U1_CFG20, 0x400100d4\r
+.set CYDEV_UCFG_B0_P0_U1_CFG21, 0x400100d5\r
+.set CYDEV_UCFG_B0_P0_U1_CFG22, 0x400100d6\r
+.set CYDEV_UCFG_B0_P0_U1_CFG23, 0x400100d7\r
+.set CYDEV_UCFG_B0_P0_U1_CFG24, 0x400100d8\r
+.set CYDEV_UCFG_B0_P0_U1_CFG25, 0x400100d9\r
+.set CYDEV_UCFG_B0_P0_U1_CFG26, 0x400100da\r
+.set CYDEV_UCFG_B0_P0_U1_CFG27, 0x400100db\r
+.set CYDEV_UCFG_B0_P0_U1_CFG28, 0x400100dc\r
+.set CYDEV_UCFG_B0_P0_U1_CFG29, 0x400100dd\r
+.set CYDEV_UCFG_B0_P0_U1_CFG30, 0x400100de\r
+.set CYDEV_UCFG_B0_P0_U1_CFG31, 0x400100df\r
+.set CYDEV_UCFG_B0_P0_U1_DCFG0, 0x400100e0\r
+.set CYDEV_UCFG_B0_P0_U1_DCFG1, 0x400100e2\r
+.set CYDEV_UCFG_B0_P0_U1_DCFG2, 0x400100e4\r
+.set CYDEV_UCFG_B0_P0_U1_DCFG3, 0x400100e6\r
+.set CYDEV_UCFG_B0_P0_U1_DCFG4, 0x400100e8\r
+.set CYDEV_UCFG_B0_P0_U1_DCFG5, 0x400100ea\r
+.set CYDEV_UCFG_B0_P0_U1_DCFG6, 0x400100ec\r
+.set CYDEV_UCFG_B0_P0_U1_DCFG7, 0x400100ee\r
+.set CYDEV_UCFG_B0_P0_ROUTE_BASE, 0x40010100\r
+.set CYDEV_UCFG_B0_P0_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B0_P1_BASE, 0x40010200\r
+.set CYDEV_UCFG_B0_P1_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B0_P1_U0_BASE, 0x40010200\r
+.set CYDEV_UCFG_B0_P1_U0_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B0_P1_U0_PLD_IT0, 0x40010200\r
+.set CYDEV_UCFG_B0_P1_U0_PLD_IT1, 0x40010204\r
+.set CYDEV_UCFG_B0_P1_U0_PLD_IT2, 0x40010208\r
+.set CYDEV_UCFG_B0_P1_U0_PLD_IT3, 0x4001020c\r
+.set CYDEV_UCFG_B0_P1_U0_PLD_IT4, 0x40010210\r
+.set CYDEV_UCFG_B0_P1_U0_PLD_IT5, 0x40010214\r
+.set CYDEV_UCFG_B0_P1_U0_PLD_IT6, 0x40010218\r
+.set CYDEV_UCFG_B0_P1_U0_PLD_IT7, 0x4001021c\r
+.set CYDEV_UCFG_B0_P1_U0_PLD_IT8, 0x40010220\r
+.set CYDEV_UCFG_B0_P1_U0_PLD_IT9, 0x40010224\r
+.set CYDEV_UCFG_B0_P1_U0_PLD_IT10, 0x40010228\r
+.set CYDEV_UCFG_B0_P1_U0_PLD_IT11, 0x4001022c\r
+.set CYDEV_UCFG_B0_P1_U0_PLD_ORT0, 0x40010230\r
+.set CYDEV_UCFG_B0_P1_U0_PLD_ORT1, 0x40010232\r
+.set CYDEV_UCFG_B0_P1_U0_PLD_ORT2, 0x40010234\r
+.set CYDEV_UCFG_B0_P1_U0_PLD_ORT3, 0x40010236\r
+.set CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST, 0x40010238\r
+.set CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB, 0x4001023a\r
+.set CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET, 0x4001023c\r
+.set CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS, 0x4001023e\r
+.set CYDEV_UCFG_B0_P1_U0_CFG0, 0x40010240\r
+.set CYDEV_UCFG_B0_P1_U0_CFG1, 0x40010241\r
+.set CYDEV_UCFG_B0_P1_U0_CFG2, 0x40010242\r
+.set CYDEV_UCFG_B0_P1_U0_CFG3, 0x40010243\r
+.set CYDEV_UCFG_B0_P1_U0_CFG4, 0x40010244\r
+.set CYDEV_UCFG_B0_P1_U0_CFG5, 0x40010245\r
+.set CYDEV_UCFG_B0_P1_U0_CFG6, 0x40010246\r
+.set CYDEV_UCFG_B0_P1_U0_CFG7, 0x40010247\r
+.set CYDEV_UCFG_B0_P1_U0_CFG8, 0x40010248\r
+.set CYDEV_UCFG_B0_P1_U0_CFG9, 0x40010249\r
+.set CYDEV_UCFG_B0_P1_U0_CFG10, 0x4001024a\r
+.set CYDEV_UCFG_B0_P1_U0_CFG11, 0x4001024b\r
+.set CYDEV_UCFG_B0_P1_U0_CFG12, 0x4001024c\r
+.set CYDEV_UCFG_B0_P1_U0_CFG13, 0x4001024d\r
+.set CYDEV_UCFG_B0_P1_U0_CFG14, 0x4001024e\r
+.set CYDEV_UCFG_B0_P1_U0_CFG15, 0x4001024f\r
+.set CYDEV_UCFG_B0_P1_U0_CFG16, 0x40010250\r
+.set CYDEV_UCFG_B0_P1_U0_CFG17, 0x40010251\r
+.set CYDEV_UCFG_B0_P1_U0_CFG18, 0x40010252\r
+.set CYDEV_UCFG_B0_P1_U0_CFG19, 0x40010253\r
+.set CYDEV_UCFG_B0_P1_U0_CFG20, 0x40010254\r
+.set CYDEV_UCFG_B0_P1_U0_CFG21, 0x40010255\r
+.set CYDEV_UCFG_B0_P1_U0_CFG22, 0x40010256\r
+.set CYDEV_UCFG_B0_P1_U0_CFG23, 0x40010257\r
+.set CYDEV_UCFG_B0_P1_U0_CFG24, 0x40010258\r
+.set CYDEV_UCFG_B0_P1_U0_CFG25, 0x40010259\r
+.set CYDEV_UCFG_B0_P1_U0_CFG26, 0x4001025a\r
+.set CYDEV_UCFG_B0_P1_U0_CFG27, 0x4001025b\r
+.set CYDEV_UCFG_B0_P1_U0_CFG28, 0x4001025c\r
+.set CYDEV_UCFG_B0_P1_U0_CFG29, 0x4001025d\r
+.set CYDEV_UCFG_B0_P1_U0_CFG30, 0x4001025e\r
+.set CYDEV_UCFG_B0_P1_U0_CFG31, 0x4001025f\r
+.set CYDEV_UCFG_B0_P1_U0_DCFG0, 0x40010260\r
+.set CYDEV_UCFG_B0_P1_U0_DCFG1, 0x40010262\r
+.set CYDEV_UCFG_B0_P1_U0_DCFG2, 0x40010264\r
+.set CYDEV_UCFG_B0_P1_U0_DCFG3, 0x40010266\r
+.set CYDEV_UCFG_B0_P1_U0_DCFG4, 0x40010268\r
+.set CYDEV_UCFG_B0_P1_U0_DCFG5, 0x4001026a\r
+.set CYDEV_UCFG_B0_P1_U0_DCFG6, 0x4001026c\r
+.set CYDEV_UCFG_B0_P1_U0_DCFG7, 0x4001026e\r
+.set CYDEV_UCFG_B0_P1_U1_BASE, 0x40010280\r
+.set CYDEV_UCFG_B0_P1_U1_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B0_P1_U1_PLD_IT0, 0x40010280\r
+.set CYDEV_UCFG_B0_P1_U1_PLD_IT1, 0x40010284\r
+.set CYDEV_UCFG_B0_P1_U1_PLD_IT2, 0x40010288\r
+.set CYDEV_UCFG_B0_P1_U1_PLD_IT3, 0x4001028c\r
+.set CYDEV_UCFG_B0_P1_U1_PLD_IT4, 0x40010290\r
+.set CYDEV_UCFG_B0_P1_U1_PLD_IT5, 0x40010294\r
+.set CYDEV_UCFG_B0_P1_U1_PLD_IT6, 0x40010298\r
+.set CYDEV_UCFG_B0_P1_U1_PLD_IT7, 0x4001029c\r
+.set CYDEV_UCFG_B0_P1_U1_PLD_IT8, 0x400102a0\r
+.set CYDEV_UCFG_B0_P1_U1_PLD_IT9, 0x400102a4\r
+.set CYDEV_UCFG_B0_P1_U1_PLD_IT10, 0x400102a8\r
+.set CYDEV_UCFG_B0_P1_U1_PLD_IT11, 0x400102ac\r
+.set CYDEV_UCFG_B0_P1_U1_PLD_ORT0, 0x400102b0\r
+.set CYDEV_UCFG_B0_P1_U1_PLD_ORT1, 0x400102b2\r
+.set CYDEV_UCFG_B0_P1_U1_PLD_ORT2, 0x400102b4\r
+.set CYDEV_UCFG_B0_P1_U1_PLD_ORT3, 0x400102b6\r
+.set CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST, 0x400102b8\r
+.set CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB, 0x400102ba\r
+.set CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET, 0x400102bc\r
+.set CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS, 0x400102be\r
+.set CYDEV_UCFG_B0_P1_U1_CFG0, 0x400102c0\r
+.set CYDEV_UCFG_B0_P1_U1_CFG1, 0x400102c1\r
+.set CYDEV_UCFG_B0_P1_U1_CFG2, 0x400102c2\r
+.set CYDEV_UCFG_B0_P1_U1_CFG3, 0x400102c3\r
+.set CYDEV_UCFG_B0_P1_U1_CFG4, 0x400102c4\r
+.set CYDEV_UCFG_B0_P1_U1_CFG5, 0x400102c5\r
+.set CYDEV_UCFG_B0_P1_U1_CFG6, 0x400102c6\r
+.set CYDEV_UCFG_B0_P1_U1_CFG7, 0x400102c7\r
+.set CYDEV_UCFG_B0_P1_U1_CFG8, 0x400102c8\r
+.set CYDEV_UCFG_B0_P1_U1_CFG9, 0x400102c9\r
+.set CYDEV_UCFG_B0_P1_U1_CFG10, 0x400102ca\r
+.set CYDEV_UCFG_B0_P1_U1_CFG11, 0x400102cb\r
+.set CYDEV_UCFG_B0_P1_U1_CFG12, 0x400102cc\r
+.set CYDEV_UCFG_B0_P1_U1_CFG13, 0x400102cd\r
+.set CYDEV_UCFG_B0_P1_U1_CFG14, 0x400102ce\r
+.set CYDEV_UCFG_B0_P1_U1_CFG15, 0x400102cf\r
+.set CYDEV_UCFG_B0_P1_U1_CFG16, 0x400102d0\r
+.set CYDEV_UCFG_B0_P1_U1_CFG17, 0x400102d1\r
+.set CYDEV_UCFG_B0_P1_U1_CFG18, 0x400102d2\r
+.set CYDEV_UCFG_B0_P1_U1_CFG19, 0x400102d3\r
+.set CYDEV_UCFG_B0_P1_U1_CFG20, 0x400102d4\r
+.set CYDEV_UCFG_B0_P1_U1_CFG21, 0x400102d5\r
+.set CYDEV_UCFG_B0_P1_U1_CFG22, 0x400102d6\r
+.set CYDEV_UCFG_B0_P1_U1_CFG23, 0x400102d7\r
+.set CYDEV_UCFG_B0_P1_U1_CFG24, 0x400102d8\r
+.set CYDEV_UCFG_B0_P1_U1_CFG25, 0x400102d9\r
+.set CYDEV_UCFG_B0_P1_U1_CFG26, 0x400102da\r
+.set CYDEV_UCFG_B0_P1_U1_CFG27, 0x400102db\r
+.set CYDEV_UCFG_B0_P1_U1_CFG28, 0x400102dc\r
+.set CYDEV_UCFG_B0_P1_U1_CFG29, 0x400102dd\r
+.set CYDEV_UCFG_B0_P1_U1_CFG30, 0x400102de\r
+.set CYDEV_UCFG_B0_P1_U1_CFG31, 0x400102df\r
+.set CYDEV_UCFG_B0_P1_U1_DCFG0, 0x400102e0\r
+.set CYDEV_UCFG_B0_P1_U1_DCFG1, 0x400102e2\r
+.set CYDEV_UCFG_B0_P1_U1_DCFG2, 0x400102e4\r
+.set CYDEV_UCFG_B0_P1_U1_DCFG3, 0x400102e6\r
+.set CYDEV_UCFG_B0_P1_U1_DCFG4, 0x400102e8\r
+.set CYDEV_UCFG_B0_P1_U1_DCFG5, 0x400102ea\r
+.set CYDEV_UCFG_B0_P1_U1_DCFG6, 0x400102ec\r
+.set CYDEV_UCFG_B0_P1_U1_DCFG7, 0x400102ee\r
+.set CYDEV_UCFG_B0_P1_ROUTE_BASE, 0x40010300\r
+.set CYDEV_UCFG_B0_P1_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B0_P2_BASE, 0x40010400\r
+.set CYDEV_UCFG_B0_P2_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B0_P2_U0_BASE, 0x40010400\r
+.set CYDEV_UCFG_B0_P2_U0_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B0_P2_U0_PLD_IT0, 0x40010400\r
+.set CYDEV_UCFG_B0_P2_U0_PLD_IT1, 0x40010404\r
+.set CYDEV_UCFG_B0_P2_U0_PLD_IT2, 0x40010408\r
+.set CYDEV_UCFG_B0_P2_U0_PLD_IT3, 0x4001040c\r
+.set CYDEV_UCFG_B0_P2_U0_PLD_IT4, 0x40010410\r
+.set CYDEV_UCFG_B0_P2_U0_PLD_IT5, 0x40010414\r
+.set CYDEV_UCFG_B0_P2_U0_PLD_IT6, 0x40010418\r
+.set CYDEV_UCFG_B0_P2_U0_PLD_IT7, 0x4001041c\r
+.set CYDEV_UCFG_B0_P2_U0_PLD_IT8, 0x40010420\r
+.set CYDEV_UCFG_B0_P2_U0_PLD_IT9, 0x40010424\r
+.set CYDEV_UCFG_B0_P2_U0_PLD_IT10, 0x40010428\r
+.set CYDEV_UCFG_B0_P2_U0_PLD_IT11, 0x4001042c\r
+.set CYDEV_UCFG_B0_P2_U0_PLD_ORT0, 0x40010430\r
+.set CYDEV_UCFG_B0_P2_U0_PLD_ORT1, 0x40010432\r
+.set CYDEV_UCFG_B0_P2_U0_PLD_ORT2, 0x40010434\r
+.set CYDEV_UCFG_B0_P2_U0_PLD_ORT3, 0x40010436\r
+.set CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST, 0x40010438\r
+.set CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB, 0x4001043a\r
+.set CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET, 0x4001043c\r
+.set CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS, 0x4001043e\r
+.set CYDEV_UCFG_B0_P2_U0_CFG0, 0x40010440\r
+.set CYDEV_UCFG_B0_P2_U0_CFG1, 0x40010441\r
+.set CYDEV_UCFG_B0_P2_U0_CFG2, 0x40010442\r
+.set CYDEV_UCFG_B0_P2_U0_CFG3, 0x40010443\r
+.set CYDEV_UCFG_B0_P2_U0_CFG4, 0x40010444\r
+.set CYDEV_UCFG_B0_P2_U0_CFG5, 0x40010445\r
+.set CYDEV_UCFG_B0_P2_U0_CFG6, 0x40010446\r
+.set CYDEV_UCFG_B0_P2_U0_CFG7, 0x40010447\r
+.set CYDEV_UCFG_B0_P2_U0_CFG8, 0x40010448\r
+.set CYDEV_UCFG_B0_P2_U0_CFG9, 0x40010449\r
+.set CYDEV_UCFG_B0_P2_U0_CFG10, 0x4001044a\r
+.set CYDEV_UCFG_B0_P2_U0_CFG11, 0x4001044b\r
+.set CYDEV_UCFG_B0_P2_U0_CFG12, 0x4001044c\r
+.set CYDEV_UCFG_B0_P2_U0_CFG13, 0x4001044d\r
+.set CYDEV_UCFG_B0_P2_U0_CFG14, 0x4001044e\r
+.set CYDEV_UCFG_B0_P2_U0_CFG15, 0x4001044f\r
+.set CYDEV_UCFG_B0_P2_U0_CFG16, 0x40010450\r
+.set CYDEV_UCFG_B0_P2_U0_CFG17, 0x40010451\r
+.set CYDEV_UCFG_B0_P2_U0_CFG18, 0x40010452\r
+.set CYDEV_UCFG_B0_P2_U0_CFG19, 0x40010453\r
+.set CYDEV_UCFG_B0_P2_U0_CFG20, 0x40010454\r
+.set CYDEV_UCFG_B0_P2_U0_CFG21, 0x40010455\r
+.set CYDEV_UCFG_B0_P2_U0_CFG22, 0x40010456\r
+.set CYDEV_UCFG_B0_P2_U0_CFG23, 0x40010457\r
+.set CYDEV_UCFG_B0_P2_U0_CFG24, 0x40010458\r
+.set CYDEV_UCFG_B0_P2_U0_CFG25, 0x40010459\r
+.set CYDEV_UCFG_B0_P2_U0_CFG26, 0x4001045a\r
+.set CYDEV_UCFG_B0_P2_U0_CFG27, 0x4001045b\r
+.set CYDEV_UCFG_B0_P2_U0_CFG28, 0x4001045c\r
+.set CYDEV_UCFG_B0_P2_U0_CFG29, 0x4001045d\r
+.set CYDEV_UCFG_B0_P2_U0_CFG30, 0x4001045e\r
+.set CYDEV_UCFG_B0_P2_U0_CFG31, 0x4001045f\r
+.set CYDEV_UCFG_B0_P2_U0_DCFG0, 0x40010460\r
+.set CYDEV_UCFG_B0_P2_U0_DCFG1, 0x40010462\r
+.set CYDEV_UCFG_B0_P2_U0_DCFG2, 0x40010464\r
+.set CYDEV_UCFG_B0_P2_U0_DCFG3, 0x40010466\r
+.set CYDEV_UCFG_B0_P2_U0_DCFG4, 0x40010468\r
+.set CYDEV_UCFG_B0_P2_U0_DCFG5, 0x4001046a\r
+.set CYDEV_UCFG_B0_P2_U0_DCFG6, 0x4001046c\r
+.set CYDEV_UCFG_B0_P2_U0_DCFG7, 0x4001046e\r
+.set CYDEV_UCFG_B0_P2_U1_BASE, 0x40010480\r
+.set CYDEV_UCFG_B0_P2_U1_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B0_P2_U1_PLD_IT0, 0x40010480\r
+.set CYDEV_UCFG_B0_P2_U1_PLD_IT1, 0x40010484\r
+.set CYDEV_UCFG_B0_P2_U1_PLD_IT2, 0x40010488\r
+.set CYDEV_UCFG_B0_P2_U1_PLD_IT3, 0x4001048c\r
+.set CYDEV_UCFG_B0_P2_U1_PLD_IT4, 0x40010490\r
+.set CYDEV_UCFG_B0_P2_U1_PLD_IT5, 0x40010494\r
+.set CYDEV_UCFG_B0_P2_U1_PLD_IT6, 0x40010498\r
+.set CYDEV_UCFG_B0_P2_U1_PLD_IT7, 0x4001049c\r
+.set CYDEV_UCFG_B0_P2_U1_PLD_IT8, 0x400104a0\r
+.set CYDEV_UCFG_B0_P2_U1_PLD_IT9, 0x400104a4\r
+.set CYDEV_UCFG_B0_P2_U1_PLD_IT10, 0x400104a8\r
+.set CYDEV_UCFG_B0_P2_U1_PLD_IT11, 0x400104ac\r
+.set CYDEV_UCFG_B0_P2_U1_PLD_ORT0, 0x400104b0\r
+.set CYDEV_UCFG_B0_P2_U1_PLD_ORT1, 0x400104b2\r
+.set CYDEV_UCFG_B0_P2_U1_PLD_ORT2, 0x400104b4\r
+.set CYDEV_UCFG_B0_P2_U1_PLD_ORT3, 0x400104b6\r
+.set CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST, 0x400104b8\r
+.set CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB, 0x400104ba\r
+.set CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET, 0x400104bc\r
+.set CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS, 0x400104be\r
+.set CYDEV_UCFG_B0_P2_U1_CFG0, 0x400104c0\r
+.set CYDEV_UCFG_B0_P2_U1_CFG1, 0x400104c1\r
+.set CYDEV_UCFG_B0_P2_U1_CFG2, 0x400104c2\r
+.set CYDEV_UCFG_B0_P2_U1_CFG3, 0x400104c3\r
+.set CYDEV_UCFG_B0_P2_U1_CFG4, 0x400104c4\r
+.set CYDEV_UCFG_B0_P2_U1_CFG5, 0x400104c5\r
+.set CYDEV_UCFG_B0_P2_U1_CFG6, 0x400104c6\r
+.set CYDEV_UCFG_B0_P2_U1_CFG7, 0x400104c7\r
+.set CYDEV_UCFG_B0_P2_U1_CFG8, 0x400104c8\r
+.set CYDEV_UCFG_B0_P2_U1_CFG9, 0x400104c9\r
+.set CYDEV_UCFG_B0_P2_U1_CFG10, 0x400104ca\r
+.set CYDEV_UCFG_B0_P2_U1_CFG11, 0x400104cb\r
+.set CYDEV_UCFG_B0_P2_U1_CFG12, 0x400104cc\r
+.set CYDEV_UCFG_B0_P2_U1_CFG13, 0x400104cd\r
+.set CYDEV_UCFG_B0_P2_U1_CFG14, 0x400104ce\r
+.set CYDEV_UCFG_B0_P2_U1_CFG15, 0x400104cf\r
+.set CYDEV_UCFG_B0_P2_U1_CFG16, 0x400104d0\r
+.set CYDEV_UCFG_B0_P2_U1_CFG17, 0x400104d1\r
+.set CYDEV_UCFG_B0_P2_U1_CFG18, 0x400104d2\r
+.set CYDEV_UCFG_B0_P2_U1_CFG19, 0x400104d3\r
+.set CYDEV_UCFG_B0_P2_U1_CFG20, 0x400104d4\r
+.set CYDEV_UCFG_B0_P2_U1_CFG21, 0x400104d5\r
+.set CYDEV_UCFG_B0_P2_U1_CFG22, 0x400104d6\r
+.set CYDEV_UCFG_B0_P2_U1_CFG23, 0x400104d7\r
+.set CYDEV_UCFG_B0_P2_U1_CFG24, 0x400104d8\r
+.set CYDEV_UCFG_B0_P2_U1_CFG25, 0x400104d9\r
+.set CYDEV_UCFG_B0_P2_U1_CFG26, 0x400104da\r
+.set CYDEV_UCFG_B0_P2_U1_CFG27, 0x400104db\r
+.set CYDEV_UCFG_B0_P2_U1_CFG28, 0x400104dc\r
+.set CYDEV_UCFG_B0_P2_U1_CFG29, 0x400104dd\r
+.set CYDEV_UCFG_B0_P2_U1_CFG30, 0x400104de\r
+.set CYDEV_UCFG_B0_P2_U1_CFG31, 0x400104df\r
+.set CYDEV_UCFG_B0_P2_U1_DCFG0, 0x400104e0\r
+.set CYDEV_UCFG_B0_P2_U1_DCFG1, 0x400104e2\r
+.set CYDEV_UCFG_B0_P2_U1_DCFG2, 0x400104e4\r
+.set CYDEV_UCFG_B0_P2_U1_DCFG3, 0x400104e6\r
+.set CYDEV_UCFG_B0_P2_U1_DCFG4, 0x400104e8\r
+.set CYDEV_UCFG_B0_P2_U1_DCFG5, 0x400104ea\r
+.set CYDEV_UCFG_B0_P2_U1_DCFG6, 0x400104ec\r
+.set CYDEV_UCFG_B0_P2_U1_DCFG7, 0x400104ee\r
+.set CYDEV_UCFG_B0_P2_ROUTE_BASE, 0x40010500\r
+.set CYDEV_UCFG_B0_P2_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B0_P3_BASE, 0x40010600\r
+.set CYDEV_UCFG_B0_P3_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B0_P3_U0_BASE, 0x40010600\r
+.set CYDEV_UCFG_B0_P3_U0_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B0_P3_U0_PLD_IT0, 0x40010600\r
+.set CYDEV_UCFG_B0_P3_U0_PLD_IT1, 0x40010604\r
+.set CYDEV_UCFG_B0_P3_U0_PLD_IT2, 0x40010608\r
+.set CYDEV_UCFG_B0_P3_U0_PLD_IT3, 0x4001060c\r
+.set CYDEV_UCFG_B0_P3_U0_PLD_IT4, 0x40010610\r
+.set CYDEV_UCFG_B0_P3_U0_PLD_IT5, 0x40010614\r
+.set CYDEV_UCFG_B0_P3_U0_PLD_IT6, 0x40010618\r
+.set CYDEV_UCFG_B0_P3_U0_PLD_IT7, 0x4001061c\r
+.set CYDEV_UCFG_B0_P3_U0_PLD_IT8, 0x40010620\r
+.set CYDEV_UCFG_B0_P3_U0_PLD_IT9, 0x40010624\r
+.set CYDEV_UCFG_B0_P3_U0_PLD_IT10, 0x40010628\r
+.set CYDEV_UCFG_B0_P3_U0_PLD_IT11, 0x4001062c\r
+.set CYDEV_UCFG_B0_P3_U0_PLD_ORT0, 0x40010630\r
+.set CYDEV_UCFG_B0_P3_U0_PLD_ORT1, 0x40010632\r
+.set CYDEV_UCFG_B0_P3_U0_PLD_ORT2, 0x40010634\r
+.set CYDEV_UCFG_B0_P3_U0_PLD_ORT3, 0x40010636\r
+.set CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST, 0x40010638\r
+.set CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB, 0x4001063a\r
+.set CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET, 0x4001063c\r
+.set CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS, 0x4001063e\r
+.set CYDEV_UCFG_B0_P3_U0_CFG0, 0x40010640\r
+.set CYDEV_UCFG_B0_P3_U0_CFG1, 0x40010641\r
+.set CYDEV_UCFG_B0_P3_U0_CFG2, 0x40010642\r
+.set CYDEV_UCFG_B0_P3_U0_CFG3, 0x40010643\r
+.set CYDEV_UCFG_B0_P3_U0_CFG4, 0x40010644\r
+.set CYDEV_UCFG_B0_P3_U0_CFG5, 0x40010645\r
+.set CYDEV_UCFG_B0_P3_U0_CFG6, 0x40010646\r
+.set CYDEV_UCFG_B0_P3_U0_CFG7, 0x40010647\r
+.set CYDEV_UCFG_B0_P3_U0_CFG8, 0x40010648\r
+.set CYDEV_UCFG_B0_P3_U0_CFG9, 0x40010649\r
+.set CYDEV_UCFG_B0_P3_U0_CFG10, 0x4001064a\r
+.set CYDEV_UCFG_B0_P3_U0_CFG11, 0x4001064b\r
+.set CYDEV_UCFG_B0_P3_U0_CFG12, 0x4001064c\r
+.set CYDEV_UCFG_B0_P3_U0_CFG13, 0x4001064d\r
+.set CYDEV_UCFG_B0_P3_U0_CFG14, 0x4001064e\r
+.set CYDEV_UCFG_B0_P3_U0_CFG15, 0x4001064f\r
+.set CYDEV_UCFG_B0_P3_U0_CFG16, 0x40010650\r
+.set CYDEV_UCFG_B0_P3_U0_CFG17, 0x40010651\r
+.set CYDEV_UCFG_B0_P3_U0_CFG18, 0x40010652\r
+.set CYDEV_UCFG_B0_P3_U0_CFG19, 0x40010653\r
+.set CYDEV_UCFG_B0_P3_U0_CFG20, 0x40010654\r
+.set CYDEV_UCFG_B0_P3_U0_CFG21, 0x40010655\r
+.set CYDEV_UCFG_B0_P3_U0_CFG22, 0x40010656\r
+.set CYDEV_UCFG_B0_P3_U0_CFG23, 0x40010657\r
+.set CYDEV_UCFG_B0_P3_U0_CFG24, 0x40010658\r
+.set CYDEV_UCFG_B0_P3_U0_CFG25, 0x40010659\r
+.set CYDEV_UCFG_B0_P3_U0_CFG26, 0x4001065a\r
+.set CYDEV_UCFG_B0_P3_U0_CFG27, 0x4001065b\r
+.set CYDEV_UCFG_B0_P3_U0_CFG28, 0x4001065c\r
+.set CYDEV_UCFG_B0_P3_U0_CFG29, 0x4001065d\r
+.set CYDEV_UCFG_B0_P3_U0_CFG30, 0x4001065e\r
+.set CYDEV_UCFG_B0_P3_U0_CFG31, 0x4001065f\r
+.set CYDEV_UCFG_B0_P3_U0_DCFG0, 0x40010660\r
+.set CYDEV_UCFG_B0_P3_U0_DCFG1, 0x40010662\r
+.set CYDEV_UCFG_B0_P3_U0_DCFG2, 0x40010664\r
+.set CYDEV_UCFG_B0_P3_U0_DCFG3, 0x40010666\r
+.set CYDEV_UCFG_B0_P3_U0_DCFG4, 0x40010668\r
+.set CYDEV_UCFG_B0_P3_U0_DCFG5, 0x4001066a\r
+.set CYDEV_UCFG_B0_P3_U0_DCFG6, 0x4001066c\r
+.set CYDEV_UCFG_B0_P3_U0_DCFG7, 0x4001066e\r
+.set CYDEV_UCFG_B0_P3_U1_BASE, 0x40010680\r
+.set CYDEV_UCFG_B0_P3_U1_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B0_P3_U1_PLD_IT0, 0x40010680\r
+.set CYDEV_UCFG_B0_P3_U1_PLD_IT1, 0x40010684\r
+.set CYDEV_UCFG_B0_P3_U1_PLD_IT2, 0x40010688\r
+.set CYDEV_UCFG_B0_P3_U1_PLD_IT3, 0x4001068c\r
+.set CYDEV_UCFG_B0_P3_U1_PLD_IT4, 0x40010690\r
+.set CYDEV_UCFG_B0_P3_U1_PLD_IT5, 0x40010694\r
+.set CYDEV_UCFG_B0_P3_U1_PLD_IT6, 0x40010698\r
+.set CYDEV_UCFG_B0_P3_U1_PLD_IT7, 0x4001069c\r
+.set CYDEV_UCFG_B0_P3_U1_PLD_IT8, 0x400106a0\r
+.set CYDEV_UCFG_B0_P3_U1_PLD_IT9, 0x400106a4\r
+.set CYDEV_UCFG_B0_P3_U1_PLD_IT10, 0x400106a8\r
+.set CYDEV_UCFG_B0_P3_U1_PLD_IT11, 0x400106ac\r
+.set CYDEV_UCFG_B0_P3_U1_PLD_ORT0, 0x400106b0\r
+.set CYDEV_UCFG_B0_P3_U1_PLD_ORT1, 0x400106b2\r
+.set CYDEV_UCFG_B0_P3_U1_PLD_ORT2, 0x400106b4\r
+.set CYDEV_UCFG_B0_P3_U1_PLD_ORT3, 0x400106b6\r
+.set CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST, 0x400106b8\r
+.set CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB, 0x400106ba\r
+.set CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET, 0x400106bc\r
+.set CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS, 0x400106be\r
+.set CYDEV_UCFG_B0_P3_U1_CFG0, 0x400106c0\r
+.set CYDEV_UCFG_B0_P3_U1_CFG1, 0x400106c1\r
+.set CYDEV_UCFG_B0_P3_U1_CFG2, 0x400106c2\r
+.set CYDEV_UCFG_B0_P3_U1_CFG3, 0x400106c3\r
+.set CYDEV_UCFG_B0_P3_U1_CFG4, 0x400106c4\r
+.set CYDEV_UCFG_B0_P3_U1_CFG5, 0x400106c5\r
+.set CYDEV_UCFG_B0_P3_U1_CFG6, 0x400106c6\r
+.set CYDEV_UCFG_B0_P3_U1_CFG7, 0x400106c7\r
+.set CYDEV_UCFG_B0_P3_U1_CFG8, 0x400106c8\r
+.set CYDEV_UCFG_B0_P3_U1_CFG9, 0x400106c9\r
+.set CYDEV_UCFG_B0_P3_U1_CFG10, 0x400106ca\r
+.set CYDEV_UCFG_B0_P3_U1_CFG11, 0x400106cb\r
+.set CYDEV_UCFG_B0_P3_U1_CFG12, 0x400106cc\r
+.set CYDEV_UCFG_B0_P3_U1_CFG13, 0x400106cd\r
+.set CYDEV_UCFG_B0_P3_U1_CFG14, 0x400106ce\r
+.set CYDEV_UCFG_B0_P3_U1_CFG15, 0x400106cf\r
+.set CYDEV_UCFG_B0_P3_U1_CFG16, 0x400106d0\r
+.set CYDEV_UCFG_B0_P3_U1_CFG17, 0x400106d1\r
+.set CYDEV_UCFG_B0_P3_U1_CFG18, 0x400106d2\r
+.set CYDEV_UCFG_B0_P3_U1_CFG19, 0x400106d3\r
+.set CYDEV_UCFG_B0_P3_U1_CFG20, 0x400106d4\r
+.set CYDEV_UCFG_B0_P3_U1_CFG21, 0x400106d5\r
+.set CYDEV_UCFG_B0_P3_U1_CFG22, 0x400106d6\r
+.set CYDEV_UCFG_B0_P3_U1_CFG23, 0x400106d7\r
+.set CYDEV_UCFG_B0_P3_U1_CFG24, 0x400106d8\r
+.set CYDEV_UCFG_B0_P3_U1_CFG25, 0x400106d9\r
+.set CYDEV_UCFG_B0_P3_U1_CFG26, 0x400106da\r
+.set CYDEV_UCFG_B0_P3_U1_CFG27, 0x400106db\r
+.set CYDEV_UCFG_B0_P3_U1_CFG28, 0x400106dc\r
+.set CYDEV_UCFG_B0_P3_U1_CFG29, 0x400106dd\r
+.set CYDEV_UCFG_B0_P3_U1_CFG30, 0x400106de\r
+.set CYDEV_UCFG_B0_P3_U1_CFG31, 0x400106df\r
+.set CYDEV_UCFG_B0_P3_U1_DCFG0, 0x400106e0\r
+.set CYDEV_UCFG_B0_P3_U1_DCFG1, 0x400106e2\r
+.set CYDEV_UCFG_B0_P3_U1_DCFG2, 0x400106e4\r
+.set CYDEV_UCFG_B0_P3_U1_DCFG3, 0x400106e6\r
+.set CYDEV_UCFG_B0_P3_U1_DCFG4, 0x400106e8\r
+.set CYDEV_UCFG_B0_P3_U1_DCFG5, 0x400106ea\r
+.set CYDEV_UCFG_B0_P3_U1_DCFG6, 0x400106ec\r
+.set CYDEV_UCFG_B0_P3_U1_DCFG7, 0x400106ee\r
+.set CYDEV_UCFG_B0_P3_ROUTE_BASE, 0x40010700\r
+.set CYDEV_UCFG_B0_P3_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B0_P4_BASE, 0x40010800\r
+.set CYDEV_UCFG_B0_P4_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B0_P4_U0_BASE, 0x40010800\r
+.set CYDEV_UCFG_B0_P4_U0_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B0_P4_U0_PLD_IT0, 0x40010800\r
+.set CYDEV_UCFG_B0_P4_U0_PLD_IT1, 0x40010804\r
+.set CYDEV_UCFG_B0_P4_U0_PLD_IT2, 0x40010808\r
+.set CYDEV_UCFG_B0_P4_U0_PLD_IT3, 0x4001080c\r
+.set CYDEV_UCFG_B0_P4_U0_PLD_IT4, 0x40010810\r
+.set CYDEV_UCFG_B0_P4_U0_PLD_IT5, 0x40010814\r
+.set CYDEV_UCFG_B0_P4_U0_PLD_IT6, 0x40010818\r
+.set CYDEV_UCFG_B0_P4_U0_PLD_IT7, 0x4001081c\r
+.set CYDEV_UCFG_B0_P4_U0_PLD_IT8, 0x40010820\r
+.set CYDEV_UCFG_B0_P4_U0_PLD_IT9, 0x40010824\r
+.set CYDEV_UCFG_B0_P4_U0_PLD_IT10, 0x40010828\r
+.set CYDEV_UCFG_B0_P4_U0_PLD_IT11, 0x4001082c\r
+.set CYDEV_UCFG_B0_P4_U0_PLD_ORT0, 0x40010830\r
+.set CYDEV_UCFG_B0_P4_U0_PLD_ORT1, 0x40010832\r
+.set CYDEV_UCFG_B0_P4_U0_PLD_ORT2, 0x40010834\r
+.set CYDEV_UCFG_B0_P4_U0_PLD_ORT3, 0x40010836\r
+.set CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST, 0x40010838\r
+.set CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB, 0x4001083a\r
+.set CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET, 0x4001083c\r
+.set CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS, 0x4001083e\r
+.set CYDEV_UCFG_B0_P4_U0_CFG0, 0x40010840\r
+.set CYDEV_UCFG_B0_P4_U0_CFG1, 0x40010841\r
+.set CYDEV_UCFG_B0_P4_U0_CFG2, 0x40010842\r
+.set CYDEV_UCFG_B0_P4_U0_CFG3, 0x40010843\r
+.set CYDEV_UCFG_B0_P4_U0_CFG4, 0x40010844\r
+.set CYDEV_UCFG_B0_P4_U0_CFG5, 0x40010845\r
+.set CYDEV_UCFG_B0_P4_U0_CFG6, 0x40010846\r
+.set CYDEV_UCFG_B0_P4_U0_CFG7, 0x40010847\r
+.set CYDEV_UCFG_B0_P4_U0_CFG8, 0x40010848\r
+.set CYDEV_UCFG_B0_P4_U0_CFG9, 0x40010849\r
+.set CYDEV_UCFG_B0_P4_U0_CFG10, 0x4001084a\r
+.set CYDEV_UCFG_B0_P4_U0_CFG11, 0x4001084b\r
+.set CYDEV_UCFG_B0_P4_U0_CFG12, 0x4001084c\r
+.set CYDEV_UCFG_B0_P4_U0_CFG13, 0x4001084d\r
+.set CYDEV_UCFG_B0_P4_U0_CFG14, 0x4001084e\r
+.set CYDEV_UCFG_B0_P4_U0_CFG15, 0x4001084f\r
+.set CYDEV_UCFG_B0_P4_U0_CFG16, 0x40010850\r
+.set CYDEV_UCFG_B0_P4_U0_CFG17, 0x40010851\r
+.set CYDEV_UCFG_B0_P4_U0_CFG18, 0x40010852\r
+.set CYDEV_UCFG_B0_P4_U0_CFG19, 0x40010853\r
+.set CYDEV_UCFG_B0_P4_U0_CFG20, 0x40010854\r
+.set CYDEV_UCFG_B0_P4_U0_CFG21, 0x40010855\r
+.set CYDEV_UCFG_B0_P4_U0_CFG22, 0x40010856\r
+.set CYDEV_UCFG_B0_P4_U0_CFG23, 0x40010857\r
+.set CYDEV_UCFG_B0_P4_U0_CFG24, 0x40010858\r
+.set CYDEV_UCFG_B0_P4_U0_CFG25, 0x40010859\r
+.set CYDEV_UCFG_B0_P4_U0_CFG26, 0x4001085a\r
+.set CYDEV_UCFG_B0_P4_U0_CFG27, 0x4001085b\r
+.set CYDEV_UCFG_B0_P4_U0_CFG28, 0x4001085c\r
+.set CYDEV_UCFG_B0_P4_U0_CFG29, 0x4001085d\r
+.set CYDEV_UCFG_B0_P4_U0_CFG30, 0x4001085e\r
+.set CYDEV_UCFG_B0_P4_U0_CFG31, 0x4001085f\r
+.set CYDEV_UCFG_B0_P4_U0_DCFG0, 0x40010860\r
+.set CYDEV_UCFG_B0_P4_U0_DCFG1, 0x40010862\r
+.set CYDEV_UCFG_B0_P4_U0_DCFG2, 0x40010864\r
+.set CYDEV_UCFG_B0_P4_U0_DCFG3, 0x40010866\r
+.set CYDEV_UCFG_B0_P4_U0_DCFG4, 0x40010868\r
+.set CYDEV_UCFG_B0_P4_U0_DCFG5, 0x4001086a\r
+.set CYDEV_UCFG_B0_P4_U0_DCFG6, 0x4001086c\r
+.set CYDEV_UCFG_B0_P4_U0_DCFG7, 0x4001086e\r
+.set CYDEV_UCFG_B0_P4_U1_BASE, 0x40010880\r
+.set CYDEV_UCFG_B0_P4_U1_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B0_P4_U1_PLD_IT0, 0x40010880\r
+.set CYDEV_UCFG_B0_P4_U1_PLD_IT1, 0x40010884\r
+.set CYDEV_UCFG_B0_P4_U1_PLD_IT2, 0x40010888\r
+.set CYDEV_UCFG_B0_P4_U1_PLD_IT3, 0x4001088c\r
+.set CYDEV_UCFG_B0_P4_U1_PLD_IT4, 0x40010890\r
+.set CYDEV_UCFG_B0_P4_U1_PLD_IT5, 0x40010894\r
+.set CYDEV_UCFG_B0_P4_U1_PLD_IT6, 0x40010898\r
+.set CYDEV_UCFG_B0_P4_U1_PLD_IT7, 0x4001089c\r
+.set CYDEV_UCFG_B0_P4_U1_PLD_IT8, 0x400108a0\r
+.set CYDEV_UCFG_B0_P4_U1_PLD_IT9, 0x400108a4\r
+.set CYDEV_UCFG_B0_P4_U1_PLD_IT10, 0x400108a8\r
+.set CYDEV_UCFG_B0_P4_U1_PLD_IT11, 0x400108ac\r
+.set CYDEV_UCFG_B0_P4_U1_PLD_ORT0, 0x400108b0\r
+.set CYDEV_UCFG_B0_P4_U1_PLD_ORT1, 0x400108b2\r
+.set CYDEV_UCFG_B0_P4_U1_PLD_ORT2, 0x400108b4\r
+.set CYDEV_UCFG_B0_P4_U1_PLD_ORT3, 0x400108b6\r
+.set CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST, 0x400108b8\r
+.set CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB, 0x400108ba\r
+.set CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET, 0x400108bc\r
+.set CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS, 0x400108be\r
+.set CYDEV_UCFG_B0_P4_U1_CFG0, 0x400108c0\r
+.set CYDEV_UCFG_B0_P4_U1_CFG1, 0x400108c1\r
+.set CYDEV_UCFG_B0_P4_U1_CFG2, 0x400108c2\r
+.set CYDEV_UCFG_B0_P4_U1_CFG3, 0x400108c3\r
+.set CYDEV_UCFG_B0_P4_U1_CFG4, 0x400108c4\r
+.set CYDEV_UCFG_B0_P4_U1_CFG5, 0x400108c5\r
+.set CYDEV_UCFG_B0_P4_U1_CFG6, 0x400108c6\r
+.set CYDEV_UCFG_B0_P4_U1_CFG7, 0x400108c7\r
+.set CYDEV_UCFG_B0_P4_U1_CFG8, 0x400108c8\r
+.set CYDEV_UCFG_B0_P4_U1_CFG9, 0x400108c9\r
+.set CYDEV_UCFG_B0_P4_U1_CFG10, 0x400108ca\r
+.set CYDEV_UCFG_B0_P4_U1_CFG11, 0x400108cb\r
+.set CYDEV_UCFG_B0_P4_U1_CFG12, 0x400108cc\r
+.set CYDEV_UCFG_B0_P4_U1_CFG13, 0x400108cd\r
+.set CYDEV_UCFG_B0_P4_U1_CFG14, 0x400108ce\r
+.set CYDEV_UCFG_B0_P4_U1_CFG15, 0x400108cf\r
+.set CYDEV_UCFG_B0_P4_U1_CFG16, 0x400108d0\r
+.set CYDEV_UCFG_B0_P4_U1_CFG17, 0x400108d1\r
+.set CYDEV_UCFG_B0_P4_U1_CFG18, 0x400108d2\r
+.set CYDEV_UCFG_B0_P4_U1_CFG19, 0x400108d3\r
+.set CYDEV_UCFG_B0_P4_U1_CFG20, 0x400108d4\r
+.set CYDEV_UCFG_B0_P4_U1_CFG21, 0x400108d5\r
+.set CYDEV_UCFG_B0_P4_U1_CFG22, 0x400108d6\r
+.set CYDEV_UCFG_B0_P4_U1_CFG23, 0x400108d7\r
+.set CYDEV_UCFG_B0_P4_U1_CFG24, 0x400108d8\r
+.set CYDEV_UCFG_B0_P4_U1_CFG25, 0x400108d9\r
+.set CYDEV_UCFG_B0_P4_U1_CFG26, 0x400108da\r
+.set CYDEV_UCFG_B0_P4_U1_CFG27, 0x400108db\r
+.set CYDEV_UCFG_B0_P4_U1_CFG28, 0x400108dc\r
+.set CYDEV_UCFG_B0_P4_U1_CFG29, 0x400108dd\r
+.set CYDEV_UCFG_B0_P4_U1_CFG30, 0x400108de\r
+.set CYDEV_UCFG_B0_P4_U1_CFG31, 0x400108df\r
+.set CYDEV_UCFG_B0_P4_U1_DCFG0, 0x400108e0\r
+.set CYDEV_UCFG_B0_P4_U1_DCFG1, 0x400108e2\r
+.set CYDEV_UCFG_B0_P4_U1_DCFG2, 0x400108e4\r
+.set CYDEV_UCFG_B0_P4_U1_DCFG3, 0x400108e6\r
+.set CYDEV_UCFG_B0_P4_U1_DCFG4, 0x400108e8\r
+.set CYDEV_UCFG_B0_P4_U1_DCFG5, 0x400108ea\r
+.set CYDEV_UCFG_B0_P4_U1_DCFG6, 0x400108ec\r
+.set CYDEV_UCFG_B0_P4_U1_DCFG7, 0x400108ee\r
+.set CYDEV_UCFG_B0_P4_ROUTE_BASE, 0x40010900\r
+.set CYDEV_UCFG_B0_P4_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B0_P5_BASE, 0x40010a00\r
+.set CYDEV_UCFG_B0_P5_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B0_P5_U0_BASE, 0x40010a00\r
+.set CYDEV_UCFG_B0_P5_U0_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B0_P5_U0_PLD_IT0, 0x40010a00\r
+.set CYDEV_UCFG_B0_P5_U0_PLD_IT1, 0x40010a04\r
+.set CYDEV_UCFG_B0_P5_U0_PLD_IT2, 0x40010a08\r
+.set CYDEV_UCFG_B0_P5_U0_PLD_IT3, 0x40010a0c\r
+.set CYDEV_UCFG_B0_P5_U0_PLD_IT4, 0x40010a10\r
+.set CYDEV_UCFG_B0_P5_U0_PLD_IT5, 0x40010a14\r
+.set CYDEV_UCFG_B0_P5_U0_PLD_IT6, 0x40010a18\r
+.set CYDEV_UCFG_B0_P5_U0_PLD_IT7, 0x40010a1c\r
+.set CYDEV_UCFG_B0_P5_U0_PLD_IT8, 0x40010a20\r
+.set CYDEV_UCFG_B0_P5_U0_PLD_IT9, 0x40010a24\r
+.set CYDEV_UCFG_B0_P5_U0_PLD_IT10, 0x40010a28\r
+.set CYDEV_UCFG_B0_P5_U0_PLD_IT11, 0x40010a2c\r
+.set CYDEV_UCFG_B0_P5_U0_PLD_ORT0, 0x40010a30\r
+.set CYDEV_UCFG_B0_P5_U0_PLD_ORT1, 0x40010a32\r
+.set CYDEV_UCFG_B0_P5_U0_PLD_ORT2, 0x40010a34\r
+.set CYDEV_UCFG_B0_P5_U0_PLD_ORT3, 0x40010a36\r
+.set CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST, 0x40010a38\r
+.set CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB, 0x40010a3a\r
+.set CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET, 0x40010a3c\r
+.set CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS, 0x40010a3e\r
+.set CYDEV_UCFG_B0_P5_U0_CFG0, 0x40010a40\r
+.set CYDEV_UCFG_B0_P5_U0_CFG1, 0x40010a41\r
+.set CYDEV_UCFG_B0_P5_U0_CFG2, 0x40010a42\r
+.set CYDEV_UCFG_B0_P5_U0_CFG3, 0x40010a43\r
+.set CYDEV_UCFG_B0_P5_U0_CFG4, 0x40010a44\r
+.set CYDEV_UCFG_B0_P5_U0_CFG5, 0x40010a45\r
+.set CYDEV_UCFG_B0_P5_U0_CFG6, 0x40010a46\r
+.set CYDEV_UCFG_B0_P5_U0_CFG7, 0x40010a47\r
+.set CYDEV_UCFG_B0_P5_U0_CFG8, 0x40010a48\r
+.set CYDEV_UCFG_B0_P5_U0_CFG9, 0x40010a49\r
+.set CYDEV_UCFG_B0_P5_U0_CFG10, 0x40010a4a\r
+.set CYDEV_UCFG_B0_P5_U0_CFG11, 0x40010a4b\r
+.set CYDEV_UCFG_B0_P5_U0_CFG12, 0x40010a4c\r
+.set CYDEV_UCFG_B0_P5_U0_CFG13, 0x40010a4d\r
+.set CYDEV_UCFG_B0_P5_U0_CFG14, 0x40010a4e\r
+.set CYDEV_UCFG_B0_P5_U0_CFG15, 0x40010a4f\r
+.set CYDEV_UCFG_B0_P5_U0_CFG16, 0x40010a50\r
+.set CYDEV_UCFG_B0_P5_U0_CFG17, 0x40010a51\r
+.set CYDEV_UCFG_B0_P5_U0_CFG18, 0x40010a52\r
+.set CYDEV_UCFG_B0_P5_U0_CFG19, 0x40010a53\r
+.set CYDEV_UCFG_B0_P5_U0_CFG20, 0x40010a54\r
+.set CYDEV_UCFG_B0_P5_U0_CFG21, 0x40010a55\r
+.set CYDEV_UCFG_B0_P5_U0_CFG22, 0x40010a56\r
+.set CYDEV_UCFG_B0_P5_U0_CFG23, 0x40010a57\r
+.set CYDEV_UCFG_B0_P5_U0_CFG24, 0x40010a58\r
+.set CYDEV_UCFG_B0_P5_U0_CFG25, 0x40010a59\r
+.set CYDEV_UCFG_B0_P5_U0_CFG26, 0x40010a5a\r
+.set CYDEV_UCFG_B0_P5_U0_CFG27, 0x40010a5b\r
+.set CYDEV_UCFG_B0_P5_U0_CFG28, 0x40010a5c\r
+.set CYDEV_UCFG_B0_P5_U0_CFG29, 0x40010a5d\r
+.set CYDEV_UCFG_B0_P5_U0_CFG30, 0x40010a5e\r
+.set CYDEV_UCFG_B0_P5_U0_CFG31, 0x40010a5f\r
+.set CYDEV_UCFG_B0_P5_U0_DCFG0, 0x40010a60\r
+.set CYDEV_UCFG_B0_P5_U0_DCFG1, 0x40010a62\r
+.set CYDEV_UCFG_B0_P5_U0_DCFG2, 0x40010a64\r
+.set CYDEV_UCFG_B0_P5_U0_DCFG3, 0x40010a66\r
+.set CYDEV_UCFG_B0_P5_U0_DCFG4, 0x40010a68\r
+.set CYDEV_UCFG_B0_P5_U0_DCFG5, 0x40010a6a\r
+.set CYDEV_UCFG_B0_P5_U0_DCFG6, 0x40010a6c\r
+.set CYDEV_UCFG_B0_P5_U0_DCFG7, 0x40010a6e\r
+.set CYDEV_UCFG_B0_P5_U1_BASE, 0x40010a80\r
+.set CYDEV_UCFG_B0_P5_U1_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B0_P5_U1_PLD_IT0, 0x40010a80\r
+.set CYDEV_UCFG_B0_P5_U1_PLD_IT1, 0x40010a84\r
+.set CYDEV_UCFG_B0_P5_U1_PLD_IT2, 0x40010a88\r
+.set CYDEV_UCFG_B0_P5_U1_PLD_IT3, 0x40010a8c\r
+.set CYDEV_UCFG_B0_P5_U1_PLD_IT4, 0x40010a90\r
+.set CYDEV_UCFG_B0_P5_U1_PLD_IT5, 0x40010a94\r
+.set CYDEV_UCFG_B0_P5_U1_PLD_IT6, 0x40010a98\r
+.set CYDEV_UCFG_B0_P5_U1_PLD_IT7, 0x40010a9c\r
+.set CYDEV_UCFG_B0_P5_U1_PLD_IT8, 0x40010aa0\r
+.set CYDEV_UCFG_B0_P5_U1_PLD_IT9, 0x40010aa4\r
+.set CYDEV_UCFG_B0_P5_U1_PLD_IT10, 0x40010aa8\r
+.set CYDEV_UCFG_B0_P5_U1_PLD_IT11, 0x40010aac\r
+.set CYDEV_UCFG_B0_P5_U1_PLD_ORT0, 0x40010ab0\r
+.set CYDEV_UCFG_B0_P5_U1_PLD_ORT1, 0x40010ab2\r
+.set CYDEV_UCFG_B0_P5_U1_PLD_ORT2, 0x40010ab4\r
+.set CYDEV_UCFG_B0_P5_U1_PLD_ORT3, 0x40010ab6\r
+.set CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST, 0x40010ab8\r
+.set CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB, 0x40010aba\r
+.set CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET, 0x40010abc\r
+.set CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS, 0x40010abe\r
+.set CYDEV_UCFG_B0_P5_U1_CFG0, 0x40010ac0\r
+.set CYDEV_UCFG_B0_P5_U1_CFG1, 0x40010ac1\r
+.set CYDEV_UCFG_B0_P5_U1_CFG2, 0x40010ac2\r
+.set CYDEV_UCFG_B0_P5_U1_CFG3, 0x40010ac3\r
+.set CYDEV_UCFG_B0_P5_U1_CFG4, 0x40010ac4\r
+.set CYDEV_UCFG_B0_P5_U1_CFG5, 0x40010ac5\r
+.set CYDEV_UCFG_B0_P5_U1_CFG6, 0x40010ac6\r
+.set CYDEV_UCFG_B0_P5_U1_CFG7, 0x40010ac7\r
+.set CYDEV_UCFG_B0_P5_U1_CFG8, 0x40010ac8\r
+.set CYDEV_UCFG_B0_P5_U1_CFG9, 0x40010ac9\r
+.set CYDEV_UCFG_B0_P5_U1_CFG10, 0x40010aca\r
+.set CYDEV_UCFG_B0_P5_U1_CFG11, 0x40010acb\r
+.set CYDEV_UCFG_B0_P5_U1_CFG12, 0x40010acc\r
+.set CYDEV_UCFG_B0_P5_U1_CFG13, 0x40010acd\r
+.set CYDEV_UCFG_B0_P5_U1_CFG14, 0x40010ace\r
+.set CYDEV_UCFG_B0_P5_U1_CFG15, 0x40010acf\r
+.set CYDEV_UCFG_B0_P5_U1_CFG16, 0x40010ad0\r
+.set CYDEV_UCFG_B0_P5_U1_CFG17, 0x40010ad1\r
+.set CYDEV_UCFG_B0_P5_U1_CFG18, 0x40010ad2\r
+.set CYDEV_UCFG_B0_P5_U1_CFG19, 0x40010ad3\r
+.set CYDEV_UCFG_B0_P5_U1_CFG20, 0x40010ad4\r
+.set CYDEV_UCFG_B0_P5_U1_CFG21, 0x40010ad5\r
+.set CYDEV_UCFG_B0_P5_U1_CFG22, 0x40010ad6\r
+.set CYDEV_UCFG_B0_P5_U1_CFG23, 0x40010ad7\r
+.set CYDEV_UCFG_B0_P5_U1_CFG24, 0x40010ad8\r
+.set CYDEV_UCFG_B0_P5_U1_CFG25, 0x40010ad9\r
+.set CYDEV_UCFG_B0_P5_U1_CFG26, 0x40010ada\r
+.set CYDEV_UCFG_B0_P5_U1_CFG27, 0x40010adb\r
+.set CYDEV_UCFG_B0_P5_U1_CFG28, 0x40010adc\r
+.set CYDEV_UCFG_B0_P5_U1_CFG29, 0x40010add\r
+.set CYDEV_UCFG_B0_P5_U1_CFG30, 0x40010ade\r
+.set CYDEV_UCFG_B0_P5_U1_CFG31, 0x40010adf\r
+.set CYDEV_UCFG_B0_P5_U1_DCFG0, 0x40010ae0\r
+.set CYDEV_UCFG_B0_P5_U1_DCFG1, 0x40010ae2\r
+.set CYDEV_UCFG_B0_P5_U1_DCFG2, 0x40010ae4\r
+.set CYDEV_UCFG_B0_P5_U1_DCFG3, 0x40010ae6\r
+.set CYDEV_UCFG_B0_P5_U1_DCFG4, 0x40010ae8\r
+.set CYDEV_UCFG_B0_P5_U1_DCFG5, 0x40010aea\r
+.set CYDEV_UCFG_B0_P5_U1_DCFG6, 0x40010aec\r
+.set CYDEV_UCFG_B0_P5_U1_DCFG7, 0x40010aee\r
+.set CYDEV_UCFG_B0_P5_ROUTE_BASE, 0x40010b00\r
+.set CYDEV_UCFG_B0_P5_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B0_P6_BASE, 0x40010c00\r
+.set CYDEV_UCFG_B0_P6_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B0_P6_U0_BASE, 0x40010c00\r
+.set CYDEV_UCFG_B0_P6_U0_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B0_P6_U0_PLD_IT0, 0x40010c00\r
+.set CYDEV_UCFG_B0_P6_U0_PLD_IT1, 0x40010c04\r
+.set CYDEV_UCFG_B0_P6_U0_PLD_IT2, 0x40010c08\r
+.set CYDEV_UCFG_B0_P6_U0_PLD_IT3, 0x40010c0c\r
+.set CYDEV_UCFG_B0_P6_U0_PLD_IT4, 0x40010c10\r
+.set CYDEV_UCFG_B0_P6_U0_PLD_IT5, 0x40010c14\r
+.set CYDEV_UCFG_B0_P6_U0_PLD_IT6, 0x40010c18\r
+.set CYDEV_UCFG_B0_P6_U0_PLD_IT7, 0x40010c1c\r
+.set CYDEV_UCFG_B0_P6_U0_PLD_IT8, 0x40010c20\r
+.set CYDEV_UCFG_B0_P6_U0_PLD_IT9, 0x40010c24\r
+.set CYDEV_UCFG_B0_P6_U0_PLD_IT10, 0x40010c28\r
+.set CYDEV_UCFG_B0_P6_U0_PLD_IT11, 0x40010c2c\r
+.set CYDEV_UCFG_B0_P6_U0_PLD_ORT0, 0x40010c30\r
+.set CYDEV_UCFG_B0_P6_U0_PLD_ORT1, 0x40010c32\r
+.set CYDEV_UCFG_B0_P6_U0_PLD_ORT2, 0x40010c34\r
+.set CYDEV_UCFG_B0_P6_U0_PLD_ORT3, 0x40010c36\r
+.set CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST, 0x40010c38\r
+.set CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB, 0x40010c3a\r
+.set CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET, 0x40010c3c\r
+.set CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS, 0x40010c3e\r
+.set CYDEV_UCFG_B0_P6_U0_CFG0, 0x40010c40\r
+.set CYDEV_UCFG_B0_P6_U0_CFG1, 0x40010c41\r
+.set CYDEV_UCFG_B0_P6_U0_CFG2, 0x40010c42\r
+.set CYDEV_UCFG_B0_P6_U0_CFG3, 0x40010c43\r
+.set CYDEV_UCFG_B0_P6_U0_CFG4, 0x40010c44\r
+.set CYDEV_UCFG_B0_P6_U0_CFG5, 0x40010c45\r
+.set CYDEV_UCFG_B0_P6_U0_CFG6, 0x40010c46\r
+.set CYDEV_UCFG_B0_P6_U0_CFG7, 0x40010c47\r
+.set CYDEV_UCFG_B0_P6_U0_CFG8, 0x40010c48\r
+.set CYDEV_UCFG_B0_P6_U0_CFG9, 0x40010c49\r
+.set CYDEV_UCFG_B0_P6_U0_CFG10, 0x40010c4a\r
+.set CYDEV_UCFG_B0_P6_U0_CFG11, 0x40010c4b\r
+.set CYDEV_UCFG_B0_P6_U0_CFG12, 0x40010c4c\r
+.set CYDEV_UCFG_B0_P6_U0_CFG13, 0x40010c4d\r
+.set CYDEV_UCFG_B0_P6_U0_CFG14, 0x40010c4e\r
+.set CYDEV_UCFG_B0_P6_U0_CFG15, 0x40010c4f\r
+.set CYDEV_UCFG_B0_P6_U0_CFG16, 0x40010c50\r
+.set CYDEV_UCFG_B0_P6_U0_CFG17, 0x40010c51\r
+.set CYDEV_UCFG_B0_P6_U0_CFG18, 0x40010c52\r
+.set CYDEV_UCFG_B0_P6_U0_CFG19, 0x40010c53\r
+.set CYDEV_UCFG_B0_P6_U0_CFG20, 0x40010c54\r
+.set CYDEV_UCFG_B0_P6_U0_CFG21, 0x40010c55\r
+.set CYDEV_UCFG_B0_P6_U0_CFG22, 0x40010c56\r
+.set CYDEV_UCFG_B0_P6_U0_CFG23, 0x40010c57\r
+.set CYDEV_UCFG_B0_P6_U0_CFG24, 0x40010c58\r
+.set CYDEV_UCFG_B0_P6_U0_CFG25, 0x40010c59\r
+.set CYDEV_UCFG_B0_P6_U0_CFG26, 0x40010c5a\r
+.set CYDEV_UCFG_B0_P6_U0_CFG27, 0x40010c5b\r
+.set CYDEV_UCFG_B0_P6_U0_CFG28, 0x40010c5c\r
+.set CYDEV_UCFG_B0_P6_U0_CFG29, 0x40010c5d\r
+.set CYDEV_UCFG_B0_P6_U0_CFG30, 0x40010c5e\r
+.set CYDEV_UCFG_B0_P6_U0_CFG31, 0x40010c5f\r
+.set CYDEV_UCFG_B0_P6_U0_DCFG0, 0x40010c60\r
+.set CYDEV_UCFG_B0_P6_U0_DCFG1, 0x40010c62\r
+.set CYDEV_UCFG_B0_P6_U0_DCFG2, 0x40010c64\r
+.set CYDEV_UCFG_B0_P6_U0_DCFG3, 0x40010c66\r
+.set CYDEV_UCFG_B0_P6_U0_DCFG4, 0x40010c68\r
+.set CYDEV_UCFG_B0_P6_U0_DCFG5, 0x40010c6a\r
+.set CYDEV_UCFG_B0_P6_U0_DCFG6, 0x40010c6c\r
+.set CYDEV_UCFG_B0_P6_U0_DCFG7, 0x40010c6e\r
+.set CYDEV_UCFG_B0_P6_U1_BASE, 0x40010c80\r
+.set CYDEV_UCFG_B0_P6_U1_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B0_P6_U1_PLD_IT0, 0x40010c80\r
+.set CYDEV_UCFG_B0_P6_U1_PLD_IT1, 0x40010c84\r
+.set CYDEV_UCFG_B0_P6_U1_PLD_IT2, 0x40010c88\r
+.set CYDEV_UCFG_B0_P6_U1_PLD_IT3, 0x40010c8c\r
+.set CYDEV_UCFG_B0_P6_U1_PLD_IT4, 0x40010c90\r
+.set CYDEV_UCFG_B0_P6_U1_PLD_IT5, 0x40010c94\r
+.set CYDEV_UCFG_B0_P6_U1_PLD_IT6, 0x40010c98\r
+.set CYDEV_UCFG_B0_P6_U1_PLD_IT7, 0x40010c9c\r
+.set CYDEV_UCFG_B0_P6_U1_PLD_IT8, 0x40010ca0\r
+.set CYDEV_UCFG_B0_P6_U1_PLD_IT9, 0x40010ca4\r
+.set CYDEV_UCFG_B0_P6_U1_PLD_IT10, 0x40010ca8\r
+.set CYDEV_UCFG_B0_P6_U1_PLD_IT11, 0x40010cac\r
+.set CYDEV_UCFG_B0_P6_U1_PLD_ORT0, 0x40010cb0\r
+.set CYDEV_UCFG_B0_P6_U1_PLD_ORT1, 0x40010cb2\r
+.set CYDEV_UCFG_B0_P6_U1_PLD_ORT2, 0x40010cb4\r
+.set CYDEV_UCFG_B0_P6_U1_PLD_ORT3, 0x40010cb6\r
+.set CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST, 0x40010cb8\r
+.set CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB, 0x40010cba\r
+.set CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET, 0x40010cbc\r
+.set CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS, 0x40010cbe\r
+.set CYDEV_UCFG_B0_P6_U1_CFG0, 0x40010cc0\r
+.set CYDEV_UCFG_B0_P6_U1_CFG1, 0x40010cc1\r
+.set CYDEV_UCFG_B0_P6_U1_CFG2, 0x40010cc2\r
+.set CYDEV_UCFG_B0_P6_U1_CFG3, 0x40010cc3\r
+.set CYDEV_UCFG_B0_P6_U1_CFG4, 0x40010cc4\r
+.set CYDEV_UCFG_B0_P6_U1_CFG5, 0x40010cc5\r
+.set CYDEV_UCFG_B0_P6_U1_CFG6, 0x40010cc6\r
+.set CYDEV_UCFG_B0_P6_U1_CFG7, 0x40010cc7\r
+.set CYDEV_UCFG_B0_P6_U1_CFG8, 0x40010cc8\r
+.set CYDEV_UCFG_B0_P6_U1_CFG9, 0x40010cc9\r
+.set CYDEV_UCFG_B0_P6_U1_CFG10, 0x40010cca\r
+.set CYDEV_UCFG_B0_P6_U1_CFG11, 0x40010ccb\r
+.set CYDEV_UCFG_B0_P6_U1_CFG12, 0x40010ccc\r
+.set CYDEV_UCFG_B0_P6_U1_CFG13, 0x40010ccd\r
+.set CYDEV_UCFG_B0_P6_U1_CFG14, 0x40010cce\r
+.set CYDEV_UCFG_B0_P6_U1_CFG15, 0x40010ccf\r
+.set CYDEV_UCFG_B0_P6_U1_CFG16, 0x40010cd0\r
+.set CYDEV_UCFG_B0_P6_U1_CFG17, 0x40010cd1\r
+.set CYDEV_UCFG_B0_P6_U1_CFG18, 0x40010cd2\r
+.set CYDEV_UCFG_B0_P6_U1_CFG19, 0x40010cd3\r
+.set CYDEV_UCFG_B0_P6_U1_CFG20, 0x40010cd4\r
+.set CYDEV_UCFG_B0_P6_U1_CFG21, 0x40010cd5\r
+.set CYDEV_UCFG_B0_P6_U1_CFG22, 0x40010cd6\r
+.set CYDEV_UCFG_B0_P6_U1_CFG23, 0x40010cd7\r
+.set CYDEV_UCFG_B0_P6_U1_CFG24, 0x40010cd8\r
+.set CYDEV_UCFG_B0_P6_U1_CFG25, 0x40010cd9\r
+.set CYDEV_UCFG_B0_P6_U1_CFG26, 0x40010cda\r
+.set CYDEV_UCFG_B0_P6_U1_CFG27, 0x40010cdb\r
+.set CYDEV_UCFG_B0_P6_U1_CFG28, 0x40010cdc\r
+.set CYDEV_UCFG_B0_P6_U1_CFG29, 0x40010cdd\r
+.set CYDEV_UCFG_B0_P6_U1_CFG30, 0x40010cde\r
+.set CYDEV_UCFG_B0_P6_U1_CFG31, 0x40010cdf\r
+.set CYDEV_UCFG_B0_P6_U1_DCFG0, 0x40010ce0\r
+.set CYDEV_UCFG_B0_P6_U1_DCFG1, 0x40010ce2\r
+.set CYDEV_UCFG_B0_P6_U1_DCFG2, 0x40010ce4\r
+.set CYDEV_UCFG_B0_P6_U1_DCFG3, 0x40010ce6\r
+.set CYDEV_UCFG_B0_P6_U1_DCFG4, 0x40010ce8\r
+.set CYDEV_UCFG_B0_P6_U1_DCFG5, 0x40010cea\r
+.set CYDEV_UCFG_B0_P6_U1_DCFG6, 0x40010cec\r
+.set CYDEV_UCFG_B0_P6_U1_DCFG7, 0x40010cee\r
+.set CYDEV_UCFG_B0_P6_ROUTE_BASE, 0x40010d00\r
+.set CYDEV_UCFG_B0_P6_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B0_P7_BASE, 0x40010e00\r
+.set CYDEV_UCFG_B0_P7_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B0_P7_U0_BASE, 0x40010e00\r
+.set CYDEV_UCFG_B0_P7_U0_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B0_P7_U0_PLD_IT0, 0x40010e00\r
+.set CYDEV_UCFG_B0_P7_U0_PLD_IT1, 0x40010e04\r
+.set CYDEV_UCFG_B0_P7_U0_PLD_IT2, 0x40010e08\r
+.set CYDEV_UCFG_B0_P7_U0_PLD_IT3, 0x40010e0c\r
+.set CYDEV_UCFG_B0_P7_U0_PLD_IT4, 0x40010e10\r
+.set CYDEV_UCFG_B0_P7_U0_PLD_IT5, 0x40010e14\r
+.set CYDEV_UCFG_B0_P7_U0_PLD_IT6, 0x40010e18\r
+.set CYDEV_UCFG_B0_P7_U0_PLD_IT7, 0x40010e1c\r
+.set CYDEV_UCFG_B0_P7_U0_PLD_IT8, 0x40010e20\r
+.set CYDEV_UCFG_B0_P7_U0_PLD_IT9, 0x40010e24\r
+.set CYDEV_UCFG_B0_P7_U0_PLD_IT10, 0x40010e28\r
+.set CYDEV_UCFG_B0_P7_U0_PLD_IT11, 0x40010e2c\r
+.set CYDEV_UCFG_B0_P7_U0_PLD_ORT0, 0x40010e30\r
+.set CYDEV_UCFG_B0_P7_U0_PLD_ORT1, 0x40010e32\r
+.set CYDEV_UCFG_B0_P7_U0_PLD_ORT2, 0x40010e34\r
+.set CYDEV_UCFG_B0_P7_U0_PLD_ORT3, 0x40010e36\r
+.set CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST, 0x40010e38\r
+.set CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB, 0x40010e3a\r
+.set CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET, 0x40010e3c\r
+.set CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS, 0x40010e3e\r
+.set CYDEV_UCFG_B0_P7_U0_CFG0, 0x40010e40\r
+.set CYDEV_UCFG_B0_P7_U0_CFG1, 0x40010e41\r
+.set CYDEV_UCFG_B0_P7_U0_CFG2, 0x40010e42\r
+.set CYDEV_UCFG_B0_P7_U0_CFG3, 0x40010e43\r
+.set CYDEV_UCFG_B0_P7_U0_CFG4, 0x40010e44\r
+.set CYDEV_UCFG_B0_P7_U0_CFG5, 0x40010e45\r
+.set CYDEV_UCFG_B0_P7_U0_CFG6, 0x40010e46\r
+.set CYDEV_UCFG_B0_P7_U0_CFG7, 0x40010e47\r
+.set CYDEV_UCFG_B0_P7_U0_CFG8, 0x40010e48\r
+.set CYDEV_UCFG_B0_P7_U0_CFG9, 0x40010e49\r
+.set CYDEV_UCFG_B0_P7_U0_CFG10, 0x40010e4a\r
+.set CYDEV_UCFG_B0_P7_U0_CFG11, 0x40010e4b\r
+.set CYDEV_UCFG_B0_P7_U0_CFG12, 0x40010e4c\r
+.set CYDEV_UCFG_B0_P7_U0_CFG13, 0x40010e4d\r
+.set CYDEV_UCFG_B0_P7_U0_CFG14, 0x40010e4e\r
+.set CYDEV_UCFG_B0_P7_U0_CFG15, 0x40010e4f\r
+.set CYDEV_UCFG_B0_P7_U0_CFG16, 0x40010e50\r
+.set CYDEV_UCFG_B0_P7_U0_CFG17, 0x40010e51\r
+.set CYDEV_UCFG_B0_P7_U0_CFG18, 0x40010e52\r
+.set CYDEV_UCFG_B0_P7_U0_CFG19, 0x40010e53\r
+.set CYDEV_UCFG_B0_P7_U0_CFG20, 0x40010e54\r
+.set CYDEV_UCFG_B0_P7_U0_CFG21, 0x40010e55\r
+.set CYDEV_UCFG_B0_P7_U0_CFG22, 0x40010e56\r
+.set CYDEV_UCFG_B0_P7_U0_CFG23, 0x40010e57\r
+.set CYDEV_UCFG_B0_P7_U0_CFG24, 0x40010e58\r
+.set CYDEV_UCFG_B0_P7_U0_CFG25, 0x40010e59\r
+.set CYDEV_UCFG_B0_P7_U0_CFG26, 0x40010e5a\r
+.set CYDEV_UCFG_B0_P7_U0_CFG27, 0x40010e5b\r
+.set CYDEV_UCFG_B0_P7_U0_CFG28, 0x40010e5c\r
+.set CYDEV_UCFG_B0_P7_U0_CFG29, 0x40010e5d\r
+.set CYDEV_UCFG_B0_P7_U0_CFG30, 0x40010e5e\r
+.set CYDEV_UCFG_B0_P7_U0_CFG31, 0x40010e5f\r
+.set CYDEV_UCFG_B0_P7_U0_DCFG0, 0x40010e60\r
+.set CYDEV_UCFG_B0_P7_U0_DCFG1, 0x40010e62\r
+.set CYDEV_UCFG_B0_P7_U0_DCFG2, 0x40010e64\r
+.set CYDEV_UCFG_B0_P7_U0_DCFG3, 0x40010e66\r
+.set CYDEV_UCFG_B0_P7_U0_DCFG4, 0x40010e68\r
+.set CYDEV_UCFG_B0_P7_U0_DCFG5, 0x40010e6a\r
+.set CYDEV_UCFG_B0_P7_U0_DCFG6, 0x40010e6c\r
+.set CYDEV_UCFG_B0_P7_U0_DCFG7, 0x40010e6e\r
+.set CYDEV_UCFG_B0_P7_U1_BASE, 0x40010e80\r
+.set CYDEV_UCFG_B0_P7_U1_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B0_P7_U1_PLD_IT0, 0x40010e80\r
+.set CYDEV_UCFG_B0_P7_U1_PLD_IT1, 0x40010e84\r
+.set CYDEV_UCFG_B0_P7_U1_PLD_IT2, 0x40010e88\r
+.set CYDEV_UCFG_B0_P7_U1_PLD_IT3, 0x40010e8c\r
+.set CYDEV_UCFG_B0_P7_U1_PLD_IT4, 0x40010e90\r
+.set CYDEV_UCFG_B0_P7_U1_PLD_IT5, 0x40010e94\r
+.set CYDEV_UCFG_B0_P7_U1_PLD_IT6, 0x40010e98\r
+.set CYDEV_UCFG_B0_P7_U1_PLD_IT7, 0x40010e9c\r
+.set CYDEV_UCFG_B0_P7_U1_PLD_IT8, 0x40010ea0\r
+.set CYDEV_UCFG_B0_P7_U1_PLD_IT9, 0x40010ea4\r
+.set CYDEV_UCFG_B0_P7_U1_PLD_IT10, 0x40010ea8\r
+.set CYDEV_UCFG_B0_P7_U1_PLD_IT11, 0x40010eac\r
+.set CYDEV_UCFG_B0_P7_U1_PLD_ORT0, 0x40010eb0\r
+.set CYDEV_UCFG_B0_P7_U1_PLD_ORT1, 0x40010eb2\r
+.set CYDEV_UCFG_B0_P7_U1_PLD_ORT2, 0x40010eb4\r
+.set CYDEV_UCFG_B0_P7_U1_PLD_ORT3, 0x40010eb6\r
+.set CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST, 0x40010eb8\r
+.set CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB, 0x40010eba\r
+.set CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET, 0x40010ebc\r
+.set CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS, 0x40010ebe\r
+.set CYDEV_UCFG_B0_P7_U1_CFG0, 0x40010ec0\r
+.set CYDEV_UCFG_B0_P7_U1_CFG1, 0x40010ec1\r
+.set CYDEV_UCFG_B0_P7_U1_CFG2, 0x40010ec2\r
+.set CYDEV_UCFG_B0_P7_U1_CFG3, 0x40010ec3\r
+.set CYDEV_UCFG_B0_P7_U1_CFG4, 0x40010ec4\r
+.set CYDEV_UCFG_B0_P7_U1_CFG5, 0x40010ec5\r
+.set CYDEV_UCFG_B0_P7_U1_CFG6, 0x40010ec6\r
+.set CYDEV_UCFG_B0_P7_U1_CFG7, 0x40010ec7\r
+.set CYDEV_UCFG_B0_P7_U1_CFG8, 0x40010ec8\r
+.set CYDEV_UCFG_B0_P7_U1_CFG9, 0x40010ec9\r
+.set CYDEV_UCFG_B0_P7_U1_CFG10, 0x40010eca\r
+.set CYDEV_UCFG_B0_P7_U1_CFG11, 0x40010ecb\r
+.set CYDEV_UCFG_B0_P7_U1_CFG12, 0x40010ecc\r
+.set CYDEV_UCFG_B0_P7_U1_CFG13, 0x40010ecd\r
+.set CYDEV_UCFG_B0_P7_U1_CFG14, 0x40010ece\r
+.set CYDEV_UCFG_B0_P7_U1_CFG15, 0x40010ecf\r
+.set CYDEV_UCFG_B0_P7_U1_CFG16, 0x40010ed0\r
+.set CYDEV_UCFG_B0_P7_U1_CFG17, 0x40010ed1\r
+.set CYDEV_UCFG_B0_P7_U1_CFG18, 0x40010ed2\r
+.set CYDEV_UCFG_B0_P7_U1_CFG19, 0x40010ed3\r
+.set CYDEV_UCFG_B0_P7_U1_CFG20, 0x40010ed4\r
+.set CYDEV_UCFG_B0_P7_U1_CFG21, 0x40010ed5\r
+.set CYDEV_UCFG_B0_P7_U1_CFG22, 0x40010ed6\r
+.set CYDEV_UCFG_B0_P7_U1_CFG23, 0x40010ed7\r
+.set CYDEV_UCFG_B0_P7_U1_CFG24, 0x40010ed8\r
+.set CYDEV_UCFG_B0_P7_U1_CFG25, 0x40010ed9\r
+.set CYDEV_UCFG_B0_P7_U1_CFG26, 0x40010eda\r
+.set CYDEV_UCFG_B0_P7_U1_CFG27, 0x40010edb\r
+.set CYDEV_UCFG_B0_P7_U1_CFG28, 0x40010edc\r
+.set CYDEV_UCFG_B0_P7_U1_CFG29, 0x40010edd\r
+.set CYDEV_UCFG_B0_P7_U1_CFG30, 0x40010ede\r
+.set CYDEV_UCFG_B0_P7_U1_CFG31, 0x40010edf\r
+.set CYDEV_UCFG_B0_P7_U1_DCFG0, 0x40010ee0\r
+.set CYDEV_UCFG_B0_P7_U1_DCFG1, 0x40010ee2\r
+.set CYDEV_UCFG_B0_P7_U1_DCFG2, 0x40010ee4\r
+.set CYDEV_UCFG_B0_P7_U1_DCFG3, 0x40010ee6\r
+.set CYDEV_UCFG_B0_P7_U1_DCFG4, 0x40010ee8\r
+.set CYDEV_UCFG_B0_P7_U1_DCFG5, 0x40010eea\r
+.set CYDEV_UCFG_B0_P7_U1_DCFG6, 0x40010eec\r
+.set CYDEV_UCFG_B0_P7_U1_DCFG7, 0x40010eee\r
+.set CYDEV_UCFG_B0_P7_ROUTE_BASE, 0x40010f00\r
+.set CYDEV_UCFG_B0_P7_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B1_BASE, 0x40011000\r
+.set CYDEV_UCFG_B1_SIZE, 0x00000fef\r
+.set CYDEV_UCFG_B1_P2_BASE, 0x40011400\r
+.set CYDEV_UCFG_B1_P2_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B1_P2_U0_BASE, 0x40011400\r
+.set CYDEV_UCFG_B1_P2_U0_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B1_P2_U0_PLD_IT0, 0x40011400\r
+.set CYDEV_UCFG_B1_P2_U0_PLD_IT1, 0x40011404\r
+.set CYDEV_UCFG_B1_P2_U0_PLD_IT2, 0x40011408\r
+.set CYDEV_UCFG_B1_P2_U0_PLD_IT3, 0x4001140c\r
+.set CYDEV_UCFG_B1_P2_U0_PLD_IT4, 0x40011410\r
+.set CYDEV_UCFG_B1_P2_U0_PLD_IT5, 0x40011414\r
+.set CYDEV_UCFG_B1_P2_U0_PLD_IT6, 0x40011418\r
+.set CYDEV_UCFG_B1_P2_U0_PLD_IT7, 0x4001141c\r
+.set CYDEV_UCFG_B1_P2_U0_PLD_IT8, 0x40011420\r
+.set CYDEV_UCFG_B1_P2_U0_PLD_IT9, 0x40011424\r
+.set CYDEV_UCFG_B1_P2_U0_PLD_IT10, 0x40011428\r
+.set CYDEV_UCFG_B1_P2_U0_PLD_IT11, 0x4001142c\r
+.set CYDEV_UCFG_B1_P2_U0_PLD_ORT0, 0x40011430\r
+.set CYDEV_UCFG_B1_P2_U0_PLD_ORT1, 0x40011432\r
+.set CYDEV_UCFG_B1_P2_U0_PLD_ORT2, 0x40011434\r
+.set CYDEV_UCFG_B1_P2_U0_PLD_ORT3, 0x40011436\r
+.set CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST, 0x40011438\r
+.set CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB, 0x4001143a\r
+.set CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET, 0x4001143c\r
+.set CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS, 0x4001143e\r
+.set CYDEV_UCFG_B1_P2_U0_CFG0, 0x40011440\r
+.set CYDEV_UCFG_B1_P2_U0_CFG1, 0x40011441\r
+.set CYDEV_UCFG_B1_P2_U0_CFG2, 0x40011442\r
+.set CYDEV_UCFG_B1_P2_U0_CFG3, 0x40011443\r
+.set CYDEV_UCFG_B1_P2_U0_CFG4, 0x40011444\r
+.set CYDEV_UCFG_B1_P2_U0_CFG5, 0x40011445\r
+.set CYDEV_UCFG_B1_P2_U0_CFG6, 0x40011446\r
+.set CYDEV_UCFG_B1_P2_U0_CFG7, 0x40011447\r
+.set CYDEV_UCFG_B1_P2_U0_CFG8, 0x40011448\r
+.set CYDEV_UCFG_B1_P2_U0_CFG9, 0x40011449\r
+.set CYDEV_UCFG_B1_P2_U0_CFG10, 0x4001144a\r
+.set CYDEV_UCFG_B1_P2_U0_CFG11, 0x4001144b\r
+.set CYDEV_UCFG_B1_P2_U0_CFG12, 0x4001144c\r
+.set CYDEV_UCFG_B1_P2_U0_CFG13, 0x4001144d\r
+.set CYDEV_UCFG_B1_P2_U0_CFG14, 0x4001144e\r
+.set CYDEV_UCFG_B1_P2_U0_CFG15, 0x4001144f\r
+.set CYDEV_UCFG_B1_P2_U0_CFG16, 0x40011450\r
+.set CYDEV_UCFG_B1_P2_U0_CFG17, 0x40011451\r
+.set CYDEV_UCFG_B1_P2_U0_CFG18, 0x40011452\r
+.set CYDEV_UCFG_B1_P2_U0_CFG19, 0x40011453\r
+.set CYDEV_UCFG_B1_P2_U0_CFG20, 0x40011454\r
+.set CYDEV_UCFG_B1_P2_U0_CFG21, 0x40011455\r
+.set CYDEV_UCFG_B1_P2_U0_CFG22, 0x40011456\r
+.set CYDEV_UCFG_B1_P2_U0_CFG23, 0x40011457\r
+.set CYDEV_UCFG_B1_P2_U0_CFG24, 0x40011458\r
+.set CYDEV_UCFG_B1_P2_U0_CFG25, 0x40011459\r
+.set CYDEV_UCFG_B1_P2_U0_CFG26, 0x4001145a\r
+.set CYDEV_UCFG_B1_P2_U0_CFG27, 0x4001145b\r
+.set CYDEV_UCFG_B1_P2_U0_CFG28, 0x4001145c\r
+.set CYDEV_UCFG_B1_P2_U0_CFG29, 0x4001145d\r
+.set CYDEV_UCFG_B1_P2_U0_CFG30, 0x4001145e\r
+.set CYDEV_UCFG_B1_P2_U0_CFG31, 0x4001145f\r
+.set CYDEV_UCFG_B1_P2_U0_DCFG0, 0x40011460\r
+.set CYDEV_UCFG_B1_P2_U0_DCFG1, 0x40011462\r
+.set CYDEV_UCFG_B1_P2_U0_DCFG2, 0x40011464\r
+.set CYDEV_UCFG_B1_P2_U0_DCFG3, 0x40011466\r
+.set CYDEV_UCFG_B1_P2_U0_DCFG4, 0x40011468\r
+.set CYDEV_UCFG_B1_P2_U0_DCFG5, 0x4001146a\r
+.set CYDEV_UCFG_B1_P2_U0_DCFG6, 0x4001146c\r
+.set CYDEV_UCFG_B1_P2_U0_DCFG7, 0x4001146e\r
+.set CYDEV_UCFG_B1_P2_U1_BASE, 0x40011480\r
+.set CYDEV_UCFG_B1_P2_U1_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B1_P2_U1_PLD_IT0, 0x40011480\r
+.set CYDEV_UCFG_B1_P2_U1_PLD_IT1, 0x40011484\r
+.set CYDEV_UCFG_B1_P2_U1_PLD_IT2, 0x40011488\r
+.set CYDEV_UCFG_B1_P2_U1_PLD_IT3, 0x4001148c\r
+.set CYDEV_UCFG_B1_P2_U1_PLD_IT4, 0x40011490\r
+.set CYDEV_UCFG_B1_P2_U1_PLD_IT5, 0x40011494\r
+.set CYDEV_UCFG_B1_P2_U1_PLD_IT6, 0x40011498\r
+.set CYDEV_UCFG_B1_P2_U1_PLD_IT7, 0x4001149c\r
+.set CYDEV_UCFG_B1_P2_U1_PLD_IT8, 0x400114a0\r
+.set CYDEV_UCFG_B1_P2_U1_PLD_IT9, 0x400114a4\r
+.set CYDEV_UCFG_B1_P2_U1_PLD_IT10, 0x400114a8\r
+.set CYDEV_UCFG_B1_P2_U1_PLD_IT11, 0x400114ac\r
+.set CYDEV_UCFG_B1_P2_U1_PLD_ORT0, 0x400114b0\r
+.set CYDEV_UCFG_B1_P2_U1_PLD_ORT1, 0x400114b2\r
+.set CYDEV_UCFG_B1_P2_U1_PLD_ORT2, 0x400114b4\r
+.set CYDEV_UCFG_B1_P2_U1_PLD_ORT3, 0x400114b6\r
+.set CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST, 0x400114b8\r
+.set CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB, 0x400114ba\r
+.set CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET, 0x400114bc\r
+.set CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS, 0x400114be\r
+.set CYDEV_UCFG_B1_P2_U1_CFG0, 0x400114c0\r
+.set CYDEV_UCFG_B1_P2_U1_CFG1, 0x400114c1\r
+.set CYDEV_UCFG_B1_P2_U1_CFG2, 0x400114c2\r
+.set CYDEV_UCFG_B1_P2_U1_CFG3, 0x400114c3\r
+.set CYDEV_UCFG_B1_P2_U1_CFG4, 0x400114c4\r
+.set CYDEV_UCFG_B1_P2_U1_CFG5, 0x400114c5\r
+.set CYDEV_UCFG_B1_P2_U1_CFG6, 0x400114c6\r
+.set CYDEV_UCFG_B1_P2_U1_CFG7, 0x400114c7\r
+.set CYDEV_UCFG_B1_P2_U1_CFG8, 0x400114c8\r
+.set CYDEV_UCFG_B1_P2_U1_CFG9, 0x400114c9\r
+.set CYDEV_UCFG_B1_P2_U1_CFG10, 0x400114ca\r
+.set CYDEV_UCFG_B1_P2_U1_CFG11, 0x400114cb\r
+.set CYDEV_UCFG_B1_P2_U1_CFG12, 0x400114cc\r
+.set CYDEV_UCFG_B1_P2_U1_CFG13, 0x400114cd\r
+.set CYDEV_UCFG_B1_P2_U1_CFG14, 0x400114ce\r
+.set CYDEV_UCFG_B1_P2_U1_CFG15, 0x400114cf\r
+.set CYDEV_UCFG_B1_P2_U1_CFG16, 0x400114d0\r
+.set CYDEV_UCFG_B1_P2_U1_CFG17, 0x400114d1\r
+.set CYDEV_UCFG_B1_P2_U1_CFG18, 0x400114d2\r
+.set CYDEV_UCFG_B1_P2_U1_CFG19, 0x400114d3\r
+.set CYDEV_UCFG_B1_P2_U1_CFG20, 0x400114d4\r
+.set CYDEV_UCFG_B1_P2_U1_CFG21, 0x400114d5\r
+.set CYDEV_UCFG_B1_P2_U1_CFG22, 0x400114d6\r
+.set CYDEV_UCFG_B1_P2_U1_CFG23, 0x400114d7\r
+.set CYDEV_UCFG_B1_P2_U1_CFG24, 0x400114d8\r
+.set CYDEV_UCFG_B1_P2_U1_CFG25, 0x400114d9\r
+.set CYDEV_UCFG_B1_P2_U1_CFG26, 0x400114da\r
+.set CYDEV_UCFG_B1_P2_U1_CFG27, 0x400114db\r
+.set CYDEV_UCFG_B1_P2_U1_CFG28, 0x400114dc\r
+.set CYDEV_UCFG_B1_P2_U1_CFG29, 0x400114dd\r
+.set CYDEV_UCFG_B1_P2_U1_CFG30, 0x400114de\r
+.set CYDEV_UCFG_B1_P2_U1_CFG31, 0x400114df\r
+.set CYDEV_UCFG_B1_P2_U1_DCFG0, 0x400114e0\r
+.set CYDEV_UCFG_B1_P2_U1_DCFG1, 0x400114e2\r
+.set CYDEV_UCFG_B1_P2_U1_DCFG2, 0x400114e4\r
+.set CYDEV_UCFG_B1_P2_U1_DCFG3, 0x400114e6\r
+.set CYDEV_UCFG_B1_P2_U1_DCFG4, 0x400114e8\r
+.set CYDEV_UCFG_B1_P2_U1_DCFG5, 0x400114ea\r
+.set CYDEV_UCFG_B1_P2_U1_DCFG6, 0x400114ec\r
+.set CYDEV_UCFG_B1_P2_U1_DCFG7, 0x400114ee\r
+.set CYDEV_UCFG_B1_P2_ROUTE_BASE, 0x40011500\r
+.set CYDEV_UCFG_B1_P2_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B1_P3_BASE, 0x40011600\r
+.set CYDEV_UCFG_B1_P3_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B1_P3_U0_BASE, 0x40011600\r
+.set CYDEV_UCFG_B1_P3_U0_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B1_P3_U0_PLD_IT0, 0x40011600\r
+.set CYDEV_UCFG_B1_P3_U0_PLD_IT1, 0x40011604\r
+.set CYDEV_UCFG_B1_P3_U0_PLD_IT2, 0x40011608\r
+.set CYDEV_UCFG_B1_P3_U0_PLD_IT3, 0x4001160c\r
+.set CYDEV_UCFG_B1_P3_U0_PLD_IT4, 0x40011610\r
+.set CYDEV_UCFG_B1_P3_U0_PLD_IT5, 0x40011614\r
+.set CYDEV_UCFG_B1_P3_U0_PLD_IT6, 0x40011618\r
+.set CYDEV_UCFG_B1_P3_U0_PLD_IT7, 0x4001161c\r
+.set CYDEV_UCFG_B1_P3_U0_PLD_IT8, 0x40011620\r
+.set CYDEV_UCFG_B1_P3_U0_PLD_IT9, 0x40011624\r
+.set CYDEV_UCFG_B1_P3_U0_PLD_IT10, 0x40011628\r
+.set CYDEV_UCFG_B1_P3_U0_PLD_IT11, 0x4001162c\r
+.set CYDEV_UCFG_B1_P3_U0_PLD_ORT0, 0x40011630\r
+.set CYDEV_UCFG_B1_P3_U0_PLD_ORT1, 0x40011632\r
+.set CYDEV_UCFG_B1_P3_U0_PLD_ORT2, 0x40011634\r
+.set CYDEV_UCFG_B1_P3_U0_PLD_ORT3, 0x40011636\r
+.set CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST, 0x40011638\r
+.set CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB, 0x4001163a\r
+.set CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET, 0x4001163c\r
+.set CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS, 0x4001163e\r
+.set CYDEV_UCFG_B1_P3_U0_CFG0, 0x40011640\r
+.set CYDEV_UCFG_B1_P3_U0_CFG1, 0x40011641\r
+.set CYDEV_UCFG_B1_P3_U0_CFG2, 0x40011642\r
+.set CYDEV_UCFG_B1_P3_U0_CFG3, 0x40011643\r
+.set CYDEV_UCFG_B1_P3_U0_CFG4, 0x40011644\r
+.set CYDEV_UCFG_B1_P3_U0_CFG5, 0x40011645\r
+.set CYDEV_UCFG_B1_P3_U0_CFG6, 0x40011646\r
+.set CYDEV_UCFG_B1_P3_U0_CFG7, 0x40011647\r
+.set CYDEV_UCFG_B1_P3_U0_CFG8, 0x40011648\r
+.set CYDEV_UCFG_B1_P3_U0_CFG9, 0x40011649\r
+.set CYDEV_UCFG_B1_P3_U0_CFG10, 0x4001164a\r
+.set CYDEV_UCFG_B1_P3_U0_CFG11, 0x4001164b\r
+.set CYDEV_UCFG_B1_P3_U0_CFG12, 0x4001164c\r
+.set CYDEV_UCFG_B1_P3_U0_CFG13, 0x4001164d\r
+.set CYDEV_UCFG_B1_P3_U0_CFG14, 0x4001164e\r
+.set CYDEV_UCFG_B1_P3_U0_CFG15, 0x4001164f\r
+.set CYDEV_UCFG_B1_P3_U0_CFG16, 0x40011650\r
+.set CYDEV_UCFG_B1_P3_U0_CFG17, 0x40011651\r
+.set CYDEV_UCFG_B1_P3_U0_CFG18, 0x40011652\r
+.set CYDEV_UCFG_B1_P3_U0_CFG19, 0x40011653\r
+.set CYDEV_UCFG_B1_P3_U0_CFG20, 0x40011654\r
+.set CYDEV_UCFG_B1_P3_U0_CFG21, 0x40011655\r
+.set CYDEV_UCFG_B1_P3_U0_CFG22, 0x40011656\r
+.set CYDEV_UCFG_B1_P3_U0_CFG23, 0x40011657\r
+.set CYDEV_UCFG_B1_P3_U0_CFG24, 0x40011658\r
+.set CYDEV_UCFG_B1_P3_U0_CFG25, 0x40011659\r
+.set CYDEV_UCFG_B1_P3_U0_CFG26, 0x4001165a\r
+.set CYDEV_UCFG_B1_P3_U0_CFG27, 0x4001165b\r
+.set CYDEV_UCFG_B1_P3_U0_CFG28, 0x4001165c\r
+.set CYDEV_UCFG_B1_P3_U0_CFG29, 0x4001165d\r
+.set CYDEV_UCFG_B1_P3_U0_CFG30, 0x4001165e\r
+.set CYDEV_UCFG_B1_P3_U0_CFG31, 0x4001165f\r
+.set CYDEV_UCFG_B1_P3_U0_DCFG0, 0x40011660\r
+.set CYDEV_UCFG_B1_P3_U0_DCFG1, 0x40011662\r
+.set CYDEV_UCFG_B1_P3_U0_DCFG2, 0x40011664\r
+.set CYDEV_UCFG_B1_P3_U0_DCFG3, 0x40011666\r
+.set CYDEV_UCFG_B1_P3_U0_DCFG4, 0x40011668\r
+.set CYDEV_UCFG_B1_P3_U0_DCFG5, 0x4001166a\r
+.set CYDEV_UCFG_B1_P3_U0_DCFG6, 0x4001166c\r
+.set CYDEV_UCFG_B1_P3_U0_DCFG7, 0x4001166e\r
+.set CYDEV_UCFG_B1_P3_U1_BASE, 0x40011680\r
+.set CYDEV_UCFG_B1_P3_U1_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B1_P3_U1_PLD_IT0, 0x40011680\r
+.set CYDEV_UCFG_B1_P3_U1_PLD_IT1, 0x40011684\r
+.set CYDEV_UCFG_B1_P3_U1_PLD_IT2, 0x40011688\r
+.set CYDEV_UCFG_B1_P3_U1_PLD_IT3, 0x4001168c\r
+.set CYDEV_UCFG_B1_P3_U1_PLD_IT4, 0x40011690\r
+.set CYDEV_UCFG_B1_P3_U1_PLD_IT5, 0x40011694\r
+.set CYDEV_UCFG_B1_P3_U1_PLD_IT6, 0x40011698\r
+.set CYDEV_UCFG_B1_P3_U1_PLD_IT7, 0x4001169c\r
+.set CYDEV_UCFG_B1_P3_U1_PLD_IT8, 0x400116a0\r
+.set CYDEV_UCFG_B1_P3_U1_PLD_IT9, 0x400116a4\r
+.set CYDEV_UCFG_B1_P3_U1_PLD_IT10, 0x400116a8\r
+.set CYDEV_UCFG_B1_P3_U1_PLD_IT11, 0x400116ac\r
+.set CYDEV_UCFG_B1_P3_U1_PLD_ORT0, 0x400116b0\r
+.set CYDEV_UCFG_B1_P3_U1_PLD_ORT1, 0x400116b2\r
+.set CYDEV_UCFG_B1_P3_U1_PLD_ORT2, 0x400116b4\r
+.set CYDEV_UCFG_B1_P3_U1_PLD_ORT3, 0x400116b6\r
+.set CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST, 0x400116b8\r
+.set CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB, 0x400116ba\r
+.set CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET, 0x400116bc\r
+.set CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS, 0x400116be\r
+.set CYDEV_UCFG_B1_P3_U1_CFG0, 0x400116c0\r
+.set CYDEV_UCFG_B1_P3_U1_CFG1, 0x400116c1\r
+.set CYDEV_UCFG_B1_P3_U1_CFG2, 0x400116c2\r
+.set CYDEV_UCFG_B1_P3_U1_CFG3, 0x400116c3\r
+.set CYDEV_UCFG_B1_P3_U1_CFG4, 0x400116c4\r
+.set CYDEV_UCFG_B1_P3_U1_CFG5, 0x400116c5\r
+.set CYDEV_UCFG_B1_P3_U1_CFG6, 0x400116c6\r
+.set CYDEV_UCFG_B1_P3_U1_CFG7, 0x400116c7\r
+.set CYDEV_UCFG_B1_P3_U1_CFG8, 0x400116c8\r
+.set CYDEV_UCFG_B1_P3_U1_CFG9, 0x400116c9\r
+.set CYDEV_UCFG_B1_P3_U1_CFG10, 0x400116ca\r
+.set CYDEV_UCFG_B1_P3_U1_CFG11, 0x400116cb\r
+.set CYDEV_UCFG_B1_P3_U1_CFG12, 0x400116cc\r
+.set CYDEV_UCFG_B1_P3_U1_CFG13, 0x400116cd\r
+.set CYDEV_UCFG_B1_P3_U1_CFG14, 0x400116ce\r
+.set CYDEV_UCFG_B1_P3_U1_CFG15, 0x400116cf\r
+.set CYDEV_UCFG_B1_P3_U1_CFG16, 0x400116d0\r
+.set CYDEV_UCFG_B1_P3_U1_CFG17, 0x400116d1\r
+.set CYDEV_UCFG_B1_P3_U1_CFG18, 0x400116d2\r
+.set CYDEV_UCFG_B1_P3_U1_CFG19, 0x400116d3\r
+.set CYDEV_UCFG_B1_P3_U1_CFG20, 0x400116d4\r
+.set CYDEV_UCFG_B1_P3_U1_CFG21, 0x400116d5\r
+.set CYDEV_UCFG_B1_P3_U1_CFG22, 0x400116d6\r
+.set CYDEV_UCFG_B1_P3_U1_CFG23, 0x400116d7\r
+.set CYDEV_UCFG_B1_P3_U1_CFG24, 0x400116d8\r
+.set CYDEV_UCFG_B1_P3_U1_CFG25, 0x400116d9\r
+.set CYDEV_UCFG_B1_P3_U1_CFG26, 0x400116da\r
+.set CYDEV_UCFG_B1_P3_U1_CFG27, 0x400116db\r
+.set CYDEV_UCFG_B1_P3_U1_CFG28, 0x400116dc\r
+.set CYDEV_UCFG_B1_P3_U1_CFG29, 0x400116dd\r
+.set CYDEV_UCFG_B1_P3_U1_CFG30, 0x400116de\r
+.set CYDEV_UCFG_B1_P3_U1_CFG31, 0x400116df\r
+.set CYDEV_UCFG_B1_P3_U1_DCFG0, 0x400116e0\r
+.set CYDEV_UCFG_B1_P3_U1_DCFG1, 0x400116e2\r
+.set CYDEV_UCFG_B1_P3_U1_DCFG2, 0x400116e4\r
+.set CYDEV_UCFG_B1_P3_U1_DCFG3, 0x400116e6\r
+.set CYDEV_UCFG_B1_P3_U1_DCFG4, 0x400116e8\r
+.set CYDEV_UCFG_B1_P3_U1_DCFG5, 0x400116ea\r
+.set CYDEV_UCFG_B1_P3_U1_DCFG6, 0x400116ec\r
+.set CYDEV_UCFG_B1_P3_U1_DCFG7, 0x400116ee\r
+.set CYDEV_UCFG_B1_P3_ROUTE_BASE, 0x40011700\r
+.set CYDEV_UCFG_B1_P3_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B1_P4_BASE, 0x40011800\r
+.set CYDEV_UCFG_B1_P4_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B1_P4_U0_BASE, 0x40011800\r
+.set CYDEV_UCFG_B1_P4_U0_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B1_P4_U0_PLD_IT0, 0x40011800\r
+.set CYDEV_UCFG_B1_P4_U0_PLD_IT1, 0x40011804\r
+.set CYDEV_UCFG_B1_P4_U0_PLD_IT2, 0x40011808\r
+.set CYDEV_UCFG_B1_P4_U0_PLD_IT3, 0x4001180c\r
+.set CYDEV_UCFG_B1_P4_U0_PLD_IT4, 0x40011810\r
+.set CYDEV_UCFG_B1_P4_U0_PLD_IT5, 0x40011814\r
+.set CYDEV_UCFG_B1_P4_U0_PLD_IT6, 0x40011818\r
+.set CYDEV_UCFG_B1_P4_U0_PLD_IT7, 0x4001181c\r
+.set CYDEV_UCFG_B1_P4_U0_PLD_IT8, 0x40011820\r
+.set CYDEV_UCFG_B1_P4_U0_PLD_IT9, 0x40011824\r
+.set CYDEV_UCFG_B1_P4_U0_PLD_IT10, 0x40011828\r
+.set CYDEV_UCFG_B1_P4_U0_PLD_IT11, 0x4001182c\r
+.set CYDEV_UCFG_B1_P4_U0_PLD_ORT0, 0x40011830\r
+.set CYDEV_UCFG_B1_P4_U0_PLD_ORT1, 0x40011832\r
+.set CYDEV_UCFG_B1_P4_U0_PLD_ORT2, 0x40011834\r
+.set CYDEV_UCFG_B1_P4_U0_PLD_ORT3, 0x40011836\r
+.set CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST, 0x40011838\r
+.set CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB, 0x4001183a\r
+.set CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET, 0x4001183c\r
+.set CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS, 0x4001183e\r
+.set CYDEV_UCFG_B1_P4_U0_CFG0, 0x40011840\r
+.set CYDEV_UCFG_B1_P4_U0_CFG1, 0x40011841\r
+.set CYDEV_UCFG_B1_P4_U0_CFG2, 0x40011842\r
+.set CYDEV_UCFG_B1_P4_U0_CFG3, 0x40011843\r
+.set CYDEV_UCFG_B1_P4_U0_CFG4, 0x40011844\r
+.set CYDEV_UCFG_B1_P4_U0_CFG5, 0x40011845\r
+.set CYDEV_UCFG_B1_P4_U0_CFG6, 0x40011846\r
+.set CYDEV_UCFG_B1_P4_U0_CFG7, 0x40011847\r
+.set CYDEV_UCFG_B1_P4_U0_CFG8, 0x40011848\r
+.set CYDEV_UCFG_B1_P4_U0_CFG9, 0x40011849\r
+.set CYDEV_UCFG_B1_P4_U0_CFG10, 0x4001184a\r
+.set CYDEV_UCFG_B1_P4_U0_CFG11, 0x4001184b\r
+.set CYDEV_UCFG_B1_P4_U0_CFG12, 0x4001184c\r
+.set CYDEV_UCFG_B1_P4_U0_CFG13, 0x4001184d\r
+.set CYDEV_UCFG_B1_P4_U0_CFG14, 0x4001184e\r
+.set CYDEV_UCFG_B1_P4_U0_CFG15, 0x4001184f\r
+.set CYDEV_UCFG_B1_P4_U0_CFG16, 0x40011850\r
+.set CYDEV_UCFG_B1_P4_U0_CFG17, 0x40011851\r
+.set CYDEV_UCFG_B1_P4_U0_CFG18, 0x40011852\r
+.set CYDEV_UCFG_B1_P4_U0_CFG19, 0x40011853\r
+.set CYDEV_UCFG_B1_P4_U0_CFG20, 0x40011854\r
+.set CYDEV_UCFG_B1_P4_U0_CFG21, 0x40011855\r
+.set CYDEV_UCFG_B1_P4_U0_CFG22, 0x40011856\r
+.set CYDEV_UCFG_B1_P4_U0_CFG23, 0x40011857\r
+.set CYDEV_UCFG_B1_P4_U0_CFG24, 0x40011858\r
+.set CYDEV_UCFG_B1_P4_U0_CFG25, 0x40011859\r
+.set CYDEV_UCFG_B1_P4_U0_CFG26, 0x4001185a\r
+.set CYDEV_UCFG_B1_P4_U0_CFG27, 0x4001185b\r
+.set CYDEV_UCFG_B1_P4_U0_CFG28, 0x4001185c\r
+.set CYDEV_UCFG_B1_P4_U0_CFG29, 0x4001185d\r
+.set CYDEV_UCFG_B1_P4_U0_CFG30, 0x4001185e\r
+.set CYDEV_UCFG_B1_P4_U0_CFG31, 0x4001185f\r
+.set CYDEV_UCFG_B1_P4_U0_DCFG0, 0x40011860\r
+.set CYDEV_UCFG_B1_P4_U0_DCFG1, 0x40011862\r
+.set CYDEV_UCFG_B1_P4_U0_DCFG2, 0x40011864\r
+.set CYDEV_UCFG_B1_P4_U0_DCFG3, 0x40011866\r
+.set CYDEV_UCFG_B1_P4_U0_DCFG4, 0x40011868\r
+.set CYDEV_UCFG_B1_P4_U0_DCFG5, 0x4001186a\r
+.set CYDEV_UCFG_B1_P4_U0_DCFG6, 0x4001186c\r
+.set CYDEV_UCFG_B1_P4_U0_DCFG7, 0x4001186e\r
+.set CYDEV_UCFG_B1_P4_U1_BASE, 0x40011880\r
+.set CYDEV_UCFG_B1_P4_U1_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B1_P4_U1_PLD_IT0, 0x40011880\r
+.set CYDEV_UCFG_B1_P4_U1_PLD_IT1, 0x40011884\r
+.set CYDEV_UCFG_B1_P4_U1_PLD_IT2, 0x40011888\r
+.set CYDEV_UCFG_B1_P4_U1_PLD_IT3, 0x4001188c\r
+.set CYDEV_UCFG_B1_P4_U1_PLD_IT4, 0x40011890\r
+.set CYDEV_UCFG_B1_P4_U1_PLD_IT5, 0x40011894\r
+.set CYDEV_UCFG_B1_P4_U1_PLD_IT6, 0x40011898\r
+.set CYDEV_UCFG_B1_P4_U1_PLD_IT7, 0x4001189c\r
+.set CYDEV_UCFG_B1_P4_U1_PLD_IT8, 0x400118a0\r
+.set CYDEV_UCFG_B1_P4_U1_PLD_IT9, 0x400118a4\r
+.set CYDEV_UCFG_B1_P4_U1_PLD_IT10, 0x400118a8\r
+.set CYDEV_UCFG_B1_P4_U1_PLD_IT11, 0x400118ac\r
+.set CYDEV_UCFG_B1_P4_U1_PLD_ORT0, 0x400118b0\r
+.set CYDEV_UCFG_B1_P4_U1_PLD_ORT1, 0x400118b2\r
+.set CYDEV_UCFG_B1_P4_U1_PLD_ORT2, 0x400118b4\r
+.set CYDEV_UCFG_B1_P4_U1_PLD_ORT3, 0x400118b6\r
+.set CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST, 0x400118b8\r
+.set CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB, 0x400118ba\r
+.set CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET, 0x400118bc\r
+.set CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS, 0x400118be\r
+.set CYDEV_UCFG_B1_P4_U1_CFG0, 0x400118c0\r
+.set CYDEV_UCFG_B1_P4_U1_CFG1, 0x400118c1\r
+.set CYDEV_UCFG_B1_P4_U1_CFG2, 0x400118c2\r
+.set CYDEV_UCFG_B1_P4_U1_CFG3, 0x400118c3\r
+.set CYDEV_UCFG_B1_P4_U1_CFG4, 0x400118c4\r
+.set CYDEV_UCFG_B1_P4_U1_CFG5, 0x400118c5\r
+.set CYDEV_UCFG_B1_P4_U1_CFG6, 0x400118c6\r
+.set CYDEV_UCFG_B1_P4_U1_CFG7, 0x400118c7\r
+.set CYDEV_UCFG_B1_P4_U1_CFG8, 0x400118c8\r
+.set CYDEV_UCFG_B1_P4_U1_CFG9, 0x400118c9\r
+.set CYDEV_UCFG_B1_P4_U1_CFG10, 0x400118ca\r
+.set CYDEV_UCFG_B1_P4_U1_CFG11, 0x400118cb\r
+.set CYDEV_UCFG_B1_P4_U1_CFG12, 0x400118cc\r
+.set CYDEV_UCFG_B1_P4_U1_CFG13, 0x400118cd\r
+.set CYDEV_UCFG_B1_P4_U1_CFG14, 0x400118ce\r
+.set CYDEV_UCFG_B1_P4_U1_CFG15, 0x400118cf\r
+.set CYDEV_UCFG_B1_P4_U1_CFG16, 0x400118d0\r
+.set CYDEV_UCFG_B1_P4_U1_CFG17, 0x400118d1\r
+.set CYDEV_UCFG_B1_P4_U1_CFG18, 0x400118d2\r
+.set CYDEV_UCFG_B1_P4_U1_CFG19, 0x400118d3\r
+.set CYDEV_UCFG_B1_P4_U1_CFG20, 0x400118d4\r
+.set CYDEV_UCFG_B1_P4_U1_CFG21, 0x400118d5\r
+.set CYDEV_UCFG_B1_P4_U1_CFG22, 0x400118d6\r
+.set CYDEV_UCFG_B1_P4_U1_CFG23, 0x400118d7\r
+.set CYDEV_UCFG_B1_P4_U1_CFG24, 0x400118d8\r
+.set CYDEV_UCFG_B1_P4_U1_CFG25, 0x400118d9\r
+.set CYDEV_UCFG_B1_P4_U1_CFG26, 0x400118da\r
+.set CYDEV_UCFG_B1_P4_U1_CFG27, 0x400118db\r
+.set CYDEV_UCFG_B1_P4_U1_CFG28, 0x400118dc\r
+.set CYDEV_UCFG_B1_P4_U1_CFG29, 0x400118dd\r
+.set CYDEV_UCFG_B1_P4_U1_CFG30, 0x400118de\r
+.set CYDEV_UCFG_B1_P4_U1_CFG31, 0x400118df\r
+.set CYDEV_UCFG_B1_P4_U1_DCFG0, 0x400118e0\r
+.set CYDEV_UCFG_B1_P4_U1_DCFG1, 0x400118e2\r
+.set CYDEV_UCFG_B1_P4_U1_DCFG2, 0x400118e4\r
+.set CYDEV_UCFG_B1_P4_U1_DCFG3, 0x400118e6\r
+.set CYDEV_UCFG_B1_P4_U1_DCFG4, 0x400118e8\r
+.set CYDEV_UCFG_B1_P4_U1_DCFG5, 0x400118ea\r
+.set CYDEV_UCFG_B1_P4_U1_DCFG6, 0x400118ec\r
+.set CYDEV_UCFG_B1_P4_U1_DCFG7, 0x400118ee\r
+.set CYDEV_UCFG_B1_P4_ROUTE_BASE, 0x40011900\r
+.set CYDEV_UCFG_B1_P4_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B1_P5_BASE, 0x40011a00\r
+.set CYDEV_UCFG_B1_P5_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B1_P5_U0_BASE, 0x40011a00\r
+.set CYDEV_UCFG_B1_P5_U0_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B1_P5_U0_PLD_IT0, 0x40011a00\r
+.set CYDEV_UCFG_B1_P5_U0_PLD_IT1, 0x40011a04\r
+.set CYDEV_UCFG_B1_P5_U0_PLD_IT2, 0x40011a08\r
+.set CYDEV_UCFG_B1_P5_U0_PLD_IT3, 0x40011a0c\r
+.set CYDEV_UCFG_B1_P5_U0_PLD_IT4, 0x40011a10\r
+.set CYDEV_UCFG_B1_P5_U0_PLD_IT5, 0x40011a14\r
+.set CYDEV_UCFG_B1_P5_U0_PLD_IT6, 0x40011a18\r
+.set CYDEV_UCFG_B1_P5_U0_PLD_IT7, 0x40011a1c\r
+.set CYDEV_UCFG_B1_P5_U0_PLD_IT8, 0x40011a20\r
+.set CYDEV_UCFG_B1_P5_U0_PLD_IT9, 0x40011a24\r
+.set CYDEV_UCFG_B1_P5_U0_PLD_IT10, 0x40011a28\r
+.set CYDEV_UCFG_B1_P5_U0_PLD_IT11, 0x40011a2c\r
+.set CYDEV_UCFG_B1_P5_U0_PLD_ORT0, 0x40011a30\r
+.set CYDEV_UCFG_B1_P5_U0_PLD_ORT1, 0x40011a32\r
+.set CYDEV_UCFG_B1_P5_U0_PLD_ORT2, 0x40011a34\r
+.set CYDEV_UCFG_B1_P5_U0_PLD_ORT3, 0x40011a36\r
+.set CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST, 0x40011a38\r
+.set CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB, 0x40011a3a\r
+.set CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET, 0x40011a3c\r
+.set CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS, 0x40011a3e\r
+.set CYDEV_UCFG_B1_P5_U0_CFG0, 0x40011a40\r
+.set CYDEV_UCFG_B1_P5_U0_CFG1, 0x40011a41\r
+.set CYDEV_UCFG_B1_P5_U0_CFG2, 0x40011a42\r
+.set CYDEV_UCFG_B1_P5_U0_CFG3, 0x40011a43\r
+.set CYDEV_UCFG_B1_P5_U0_CFG4, 0x40011a44\r
+.set CYDEV_UCFG_B1_P5_U0_CFG5, 0x40011a45\r
+.set CYDEV_UCFG_B1_P5_U0_CFG6, 0x40011a46\r
+.set CYDEV_UCFG_B1_P5_U0_CFG7, 0x40011a47\r
+.set CYDEV_UCFG_B1_P5_U0_CFG8, 0x40011a48\r
+.set CYDEV_UCFG_B1_P5_U0_CFG9, 0x40011a49\r
+.set CYDEV_UCFG_B1_P5_U0_CFG10, 0x40011a4a\r
+.set CYDEV_UCFG_B1_P5_U0_CFG11, 0x40011a4b\r
+.set CYDEV_UCFG_B1_P5_U0_CFG12, 0x40011a4c\r
+.set CYDEV_UCFG_B1_P5_U0_CFG13, 0x40011a4d\r
+.set CYDEV_UCFG_B1_P5_U0_CFG14, 0x40011a4e\r
+.set CYDEV_UCFG_B1_P5_U0_CFG15, 0x40011a4f\r
+.set CYDEV_UCFG_B1_P5_U0_CFG16, 0x40011a50\r
+.set CYDEV_UCFG_B1_P5_U0_CFG17, 0x40011a51\r
+.set CYDEV_UCFG_B1_P5_U0_CFG18, 0x40011a52\r
+.set CYDEV_UCFG_B1_P5_U0_CFG19, 0x40011a53\r
+.set CYDEV_UCFG_B1_P5_U0_CFG20, 0x40011a54\r
+.set CYDEV_UCFG_B1_P5_U0_CFG21, 0x40011a55\r
+.set CYDEV_UCFG_B1_P5_U0_CFG22, 0x40011a56\r
+.set CYDEV_UCFG_B1_P5_U0_CFG23, 0x40011a57\r
+.set CYDEV_UCFG_B1_P5_U0_CFG24, 0x40011a58\r
+.set CYDEV_UCFG_B1_P5_U0_CFG25, 0x40011a59\r
+.set CYDEV_UCFG_B1_P5_U0_CFG26, 0x40011a5a\r
+.set CYDEV_UCFG_B1_P5_U0_CFG27, 0x40011a5b\r
+.set CYDEV_UCFG_B1_P5_U0_CFG28, 0x40011a5c\r
+.set CYDEV_UCFG_B1_P5_U0_CFG29, 0x40011a5d\r
+.set CYDEV_UCFG_B1_P5_U0_CFG30, 0x40011a5e\r
+.set CYDEV_UCFG_B1_P5_U0_CFG31, 0x40011a5f\r
+.set CYDEV_UCFG_B1_P5_U0_DCFG0, 0x40011a60\r
+.set CYDEV_UCFG_B1_P5_U0_DCFG1, 0x40011a62\r
+.set CYDEV_UCFG_B1_P5_U0_DCFG2, 0x40011a64\r
+.set CYDEV_UCFG_B1_P5_U0_DCFG3, 0x40011a66\r
+.set CYDEV_UCFG_B1_P5_U0_DCFG4, 0x40011a68\r
+.set CYDEV_UCFG_B1_P5_U0_DCFG5, 0x40011a6a\r
+.set CYDEV_UCFG_B1_P5_U0_DCFG6, 0x40011a6c\r
+.set CYDEV_UCFG_B1_P5_U0_DCFG7, 0x40011a6e\r
+.set CYDEV_UCFG_B1_P5_U1_BASE, 0x40011a80\r
+.set CYDEV_UCFG_B1_P5_U1_SIZE, 0x00000070\r
+.set CYDEV_UCFG_B1_P5_U1_PLD_IT0, 0x40011a80\r
+.set CYDEV_UCFG_B1_P5_U1_PLD_IT1, 0x40011a84\r
+.set CYDEV_UCFG_B1_P5_U1_PLD_IT2, 0x40011a88\r
+.set CYDEV_UCFG_B1_P5_U1_PLD_IT3, 0x40011a8c\r
+.set CYDEV_UCFG_B1_P5_U1_PLD_IT4, 0x40011a90\r
+.set CYDEV_UCFG_B1_P5_U1_PLD_IT5, 0x40011a94\r
+.set CYDEV_UCFG_B1_P5_U1_PLD_IT6, 0x40011a98\r
+.set CYDEV_UCFG_B1_P5_U1_PLD_IT7, 0x40011a9c\r
+.set CYDEV_UCFG_B1_P5_U1_PLD_IT8, 0x40011aa0\r
+.set CYDEV_UCFG_B1_P5_U1_PLD_IT9, 0x40011aa4\r
+.set CYDEV_UCFG_B1_P5_U1_PLD_IT10, 0x40011aa8\r
+.set CYDEV_UCFG_B1_P5_U1_PLD_IT11, 0x40011aac\r
+.set CYDEV_UCFG_B1_P5_U1_PLD_ORT0, 0x40011ab0\r
+.set CYDEV_UCFG_B1_P5_U1_PLD_ORT1, 0x40011ab2\r
+.set CYDEV_UCFG_B1_P5_U1_PLD_ORT2, 0x40011ab4\r
+.set CYDEV_UCFG_B1_P5_U1_PLD_ORT3, 0x40011ab6\r
+.set CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST, 0x40011ab8\r
+.set CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB, 0x40011aba\r
+.set CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET, 0x40011abc\r
+.set CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS, 0x40011abe\r
+.set CYDEV_UCFG_B1_P5_U1_CFG0, 0x40011ac0\r
+.set CYDEV_UCFG_B1_P5_U1_CFG1, 0x40011ac1\r
+.set CYDEV_UCFG_B1_P5_U1_CFG2, 0x40011ac2\r
+.set CYDEV_UCFG_B1_P5_U1_CFG3, 0x40011ac3\r
+.set CYDEV_UCFG_B1_P5_U1_CFG4, 0x40011ac4\r
+.set CYDEV_UCFG_B1_P5_U1_CFG5, 0x40011ac5\r
+.set CYDEV_UCFG_B1_P5_U1_CFG6, 0x40011ac6\r
+.set CYDEV_UCFG_B1_P5_U1_CFG7, 0x40011ac7\r
+.set CYDEV_UCFG_B1_P5_U1_CFG8, 0x40011ac8\r
+.set CYDEV_UCFG_B1_P5_U1_CFG9, 0x40011ac9\r
+.set CYDEV_UCFG_B1_P5_U1_CFG10, 0x40011aca\r
+.set CYDEV_UCFG_B1_P5_U1_CFG11, 0x40011acb\r
+.set CYDEV_UCFG_B1_P5_U1_CFG12, 0x40011acc\r
+.set CYDEV_UCFG_B1_P5_U1_CFG13, 0x40011acd\r
+.set CYDEV_UCFG_B1_P5_U1_CFG14, 0x40011ace\r
+.set CYDEV_UCFG_B1_P5_U1_CFG15, 0x40011acf\r
+.set CYDEV_UCFG_B1_P5_U1_CFG16, 0x40011ad0\r
+.set CYDEV_UCFG_B1_P5_U1_CFG17, 0x40011ad1\r
+.set CYDEV_UCFG_B1_P5_U1_CFG18, 0x40011ad2\r
+.set CYDEV_UCFG_B1_P5_U1_CFG19, 0x40011ad3\r
+.set CYDEV_UCFG_B1_P5_U1_CFG20, 0x40011ad4\r
+.set CYDEV_UCFG_B1_P5_U1_CFG21, 0x40011ad5\r
+.set CYDEV_UCFG_B1_P5_U1_CFG22, 0x40011ad6\r
+.set CYDEV_UCFG_B1_P5_U1_CFG23, 0x40011ad7\r
+.set CYDEV_UCFG_B1_P5_U1_CFG24, 0x40011ad8\r
+.set CYDEV_UCFG_B1_P5_U1_CFG25, 0x40011ad9\r
+.set CYDEV_UCFG_B1_P5_U1_CFG26, 0x40011ada\r
+.set CYDEV_UCFG_B1_P5_U1_CFG27, 0x40011adb\r
+.set CYDEV_UCFG_B1_P5_U1_CFG28, 0x40011adc\r
+.set CYDEV_UCFG_B1_P5_U1_CFG29, 0x40011add\r
+.set CYDEV_UCFG_B1_P5_U1_CFG30, 0x40011ade\r
+.set CYDEV_UCFG_B1_P5_U1_CFG31, 0x40011adf\r
+.set CYDEV_UCFG_B1_P5_U1_DCFG0, 0x40011ae0\r
+.set CYDEV_UCFG_B1_P5_U1_DCFG1, 0x40011ae2\r
+.set CYDEV_UCFG_B1_P5_U1_DCFG2, 0x40011ae4\r
+.set CYDEV_UCFG_B1_P5_U1_DCFG3, 0x40011ae6\r
+.set CYDEV_UCFG_B1_P5_U1_DCFG4, 0x40011ae8\r
+.set CYDEV_UCFG_B1_P5_U1_DCFG5, 0x40011aea\r
+.set CYDEV_UCFG_B1_P5_U1_DCFG6, 0x40011aec\r
+.set CYDEV_UCFG_B1_P5_U1_DCFG7, 0x40011aee\r
+.set CYDEV_UCFG_B1_P5_ROUTE_BASE, 0x40011b00\r
+.set CYDEV_UCFG_B1_P5_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI0_BASE, 0x40014000\r
+.set CYDEV_UCFG_DSI0_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI1_BASE, 0x40014100\r
+.set CYDEV_UCFG_DSI1_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI2_BASE, 0x40014200\r
+.set CYDEV_UCFG_DSI2_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI3_BASE, 0x40014300\r
+.set CYDEV_UCFG_DSI3_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI4_BASE, 0x40014400\r
+.set CYDEV_UCFG_DSI4_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI5_BASE, 0x40014500\r
+.set CYDEV_UCFG_DSI5_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI6_BASE, 0x40014600\r
+.set CYDEV_UCFG_DSI6_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI7_BASE, 0x40014700\r
+.set CYDEV_UCFG_DSI7_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI8_BASE, 0x40014800\r
+.set CYDEV_UCFG_DSI8_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI9_BASE, 0x40014900\r
+.set CYDEV_UCFG_DSI9_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI12_BASE, 0x40014c00\r
+.set CYDEV_UCFG_DSI12_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI13_BASE, 0x40014d00\r
+.set CYDEV_UCFG_DSI13_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_BCTL0_BASE, 0x40015000\r
+.set CYDEV_UCFG_BCTL0_SIZE, 0x00000010\r
+.set CYDEV_UCFG_BCTL0_MDCLK_EN, 0x40015000\r
+.set CYDEV_UCFG_BCTL0_MBCLK_EN, 0x40015001\r
+.set CYDEV_UCFG_BCTL0_WAIT_CFG, 0x40015002\r
+.set CYDEV_UCFG_BCTL0_BANK_CTL, 0x40015003\r
+.set CYDEV_UCFG_BCTL0_UDB_TEST_3, 0x40015007\r
+.set CYDEV_UCFG_BCTL0_DCLK_EN0, 0x40015008\r
+.set CYDEV_UCFG_BCTL0_BCLK_EN0, 0x40015009\r
+.set CYDEV_UCFG_BCTL0_DCLK_EN1, 0x4001500a\r
+.set CYDEV_UCFG_BCTL0_BCLK_EN1, 0x4001500b\r
+.set CYDEV_UCFG_BCTL0_DCLK_EN2, 0x4001500c\r
+.set CYDEV_UCFG_BCTL0_BCLK_EN2, 0x4001500d\r
+.set CYDEV_UCFG_BCTL0_DCLK_EN3, 0x4001500e\r
+.set CYDEV_UCFG_BCTL0_BCLK_EN3, 0x4001500f\r
+.set CYDEV_UCFG_BCTL1_BASE, 0x40015010\r
+.set CYDEV_UCFG_BCTL1_SIZE, 0x00000010\r
+.set CYDEV_UCFG_BCTL1_MDCLK_EN, 0x40015010\r
+.set CYDEV_UCFG_BCTL1_MBCLK_EN, 0x40015011\r
+.set CYDEV_UCFG_BCTL1_WAIT_CFG, 0x40015012\r
+.set CYDEV_UCFG_BCTL1_BANK_CTL, 0x40015013\r
+.set CYDEV_UCFG_BCTL1_UDB_TEST_3, 0x40015017\r
+.set CYDEV_UCFG_BCTL1_DCLK_EN0, 0x40015018\r
+.set CYDEV_UCFG_BCTL1_BCLK_EN0, 0x40015019\r
+.set CYDEV_UCFG_BCTL1_DCLK_EN1, 0x4001501a\r
+.set CYDEV_UCFG_BCTL1_BCLK_EN1, 0x4001501b\r
+.set CYDEV_UCFG_BCTL1_DCLK_EN2, 0x4001501c\r
+.set CYDEV_UCFG_BCTL1_BCLK_EN2, 0x4001501d\r
+.set CYDEV_UCFG_BCTL1_DCLK_EN3, 0x4001501e\r
+.set CYDEV_UCFG_BCTL1_BCLK_EN3, 0x4001501f\r
+.set CYDEV_IDMUX_BASE, 0x40015100\r
+.set CYDEV_IDMUX_SIZE, 0x00000016\r
+.set CYDEV_IDMUX_IRQ_CTL0, 0x40015100\r
+.set CYDEV_IDMUX_IRQ_CTL1, 0x40015101\r
+.set CYDEV_IDMUX_IRQ_CTL2, 0x40015102\r
+.set CYDEV_IDMUX_IRQ_CTL3, 0x40015103\r
+.set CYDEV_IDMUX_IRQ_CTL4, 0x40015104\r
+.set CYDEV_IDMUX_IRQ_CTL5, 0x40015105\r
+.set CYDEV_IDMUX_IRQ_CTL6, 0x40015106\r
+.set CYDEV_IDMUX_IRQ_CTL7, 0x40015107\r
+.set CYDEV_IDMUX_DRQ_CTL0, 0x40015110\r
+.set CYDEV_IDMUX_DRQ_CTL1, 0x40015111\r
+.set CYDEV_IDMUX_DRQ_CTL2, 0x40015112\r
+.set CYDEV_IDMUX_DRQ_CTL3, 0x40015113\r
+.set CYDEV_IDMUX_DRQ_CTL4, 0x40015114\r
+.set CYDEV_IDMUX_DRQ_CTL5, 0x40015115\r
+.set CYDEV_CACHERAM_BASE, 0x40030000\r
+.set CYDEV_CACHERAM_SIZE, 0x00000400\r
+.set CYDEV_CACHERAM_DATA_MBASE, 0x40030000\r
+.set CYDEV_CACHERAM_DATA_MSIZE, 0x00000400\r
+.set CYDEV_SFR_BASE, 0x40050100\r
+.set CYDEV_SFR_SIZE, 0x000000fb\r
+.set CYDEV_SFR_GPIO0, 0x40050180\r
+.set CYDEV_SFR_GPIRD0, 0x40050189\r
+.set CYDEV_SFR_GPIO0_SEL, 0x4005018a\r
+.set CYDEV_SFR_GPIO1, 0x40050190\r
+.set CYDEV_SFR_GPIRD1, 0x40050191\r
+.set CYDEV_SFR_GPIO2, 0x40050198\r
+.set CYDEV_SFR_GPIRD2, 0x40050199\r
+.set CYDEV_SFR_GPIO2_SEL, 0x4005019a\r
+.set CYDEV_SFR_GPIO1_SEL, 0x400501a2\r
+.set CYDEV_SFR_GPIO3, 0x400501b0\r
+.set CYDEV_SFR_GPIRD3, 0x400501b1\r
+.set CYDEV_SFR_GPIO3_SEL, 0x400501b2\r
+.set CYDEV_SFR_GPIO4, 0x400501c0\r
+.set CYDEV_SFR_GPIRD4, 0x400501c1\r
+.set CYDEV_SFR_GPIO4_SEL, 0x400501c2\r
+.set CYDEV_SFR_GPIO5, 0x400501c8\r
+.set CYDEV_SFR_GPIRD5, 0x400501c9\r
+.set CYDEV_SFR_GPIO5_SEL, 0x400501ca\r
+.set CYDEV_SFR_GPIO6, 0x400501d8\r
+.set CYDEV_SFR_GPIRD6, 0x400501d9\r
+.set CYDEV_SFR_GPIO6_SEL, 0x400501da\r
+.set CYDEV_SFR_GPIO12, 0x400501e8\r
+.set CYDEV_SFR_GPIRD12, 0x400501e9\r
+.set CYDEV_SFR_GPIO12_SEL, 0x400501f2\r
+.set CYDEV_SFR_GPIO15, 0x400501f8\r
+.set CYDEV_SFR_GPIRD15, 0x400501f9\r
+.set CYDEV_SFR_GPIO15_SEL, 0x400501fa\r
+.set CYDEV_P3BA_BASE, 0x40050300\r
+.set CYDEV_P3BA_SIZE, 0x0000002b\r
+.set CYDEV_P3BA_Y_START, 0x40050300\r
+.set CYDEV_P3BA_YROLL, 0x40050301\r
+.set CYDEV_P3BA_YCFG, 0x40050302\r
+.set CYDEV_P3BA_X_START1, 0x40050303\r
+.set CYDEV_P3BA_X_START2, 0x40050304\r
+.set CYDEV_P3BA_XROLL1, 0x40050305\r
+.set CYDEV_P3BA_XROLL2, 0x40050306\r
+.set CYDEV_P3BA_XINC, 0x40050307\r
+.set CYDEV_P3BA_XCFG, 0x40050308\r
+.set CYDEV_P3BA_OFFSETADDR1, 0x40050309\r
+.set CYDEV_P3BA_OFFSETADDR2, 0x4005030a\r
+.set CYDEV_P3BA_OFFSETADDR3, 0x4005030b\r
+.set CYDEV_P3BA_ABSADDR1, 0x4005030c\r
+.set CYDEV_P3BA_ABSADDR2, 0x4005030d\r
+.set CYDEV_P3BA_ABSADDR3, 0x4005030e\r
+.set CYDEV_P3BA_ABSADDR4, 0x4005030f\r
+.set CYDEV_P3BA_DATCFG1, 0x40050310\r
+.set CYDEV_P3BA_DATCFG2, 0x40050311\r
+.set CYDEV_P3BA_CMP_RSLT1, 0x40050314\r
+.set CYDEV_P3BA_CMP_RSLT2, 0x40050315\r
+.set CYDEV_P3BA_CMP_RSLT3, 0x40050316\r
+.set CYDEV_P3BA_CMP_RSLT4, 0x40050317\r
+.set CYDEV_P3BA_DATA_REG1, 0x40050318\r
+.set CYDEV_P3BA_DATA_REG2, 0x40050319\r
+.set CYDEV_P3BA_DATA_REG3, 0x4005031a\r
+.set CYDEV_P3BA_DATA_REG4, 0x4005031b\r
+.set CYDEV_P3BA_EXP_DATA1, 0x4005031c\r
+.set CYDEV_P3BA_EXP_DATA2, 0x4005031d\r
+.set CYDEV_P3BA_EXP_DATA3, 0x4005031e\r
+.set CYDEV_P3BA_EXP_DATA4, 0x4005031f\r
+.set CYDEV_P3BA_MSTR_HRDATA1, 0x40050320\r
+.set CYDEV_P3BA_MSTR_HRDATA2, 0x40050321\r
+.set CYDEV_P3BA_MSTR_HRDATA3, 0x40050322\r
+.set CYDEV_P3BA_MSTR_HRDATA4, 0x40050323\r
+.set CYDEV_P3BA_BIST_EN, 0x40050324\r
+.set CYDEV_P3BA_PHUB_MASTER_SSR, 0x40050325\r
+.set CYDEV_P3BA_SEQCFG1, 0x40050326\r
+.set CYDEV_P3BA_SEQCFG2, 0x40050327\r
+.set CYDEV_P3BA_Y_CURR, 0x40050328\r
+.set CYDEV_P3BA_X_CURR1, 0x40050329\r
+.set CYDEV_P3BA_X_CURR2, 0x4005032a\r
+.set CYDEV_PANTHER_BASE, 0x40080000\r
+.set CYDEV_PANTHER_SIZE, 0x00000020\r
+.set CYDEV_PANTHER_STCALIB_CFG, 0x40080000\r
+.set CYDEV_PANTHER_WAITPIPE, 0x40080004\r
+.set CYDEV_PANTHER_TRACE_CFG, 0x40080008\r
+.set CYDEV_PANTHER_DBG_CFG, 0x4008000c\r
+.set CYDEV_PANTHER_CM3_LCKRST_STAT, 0x40080018\r
+.set CYDEV_PANTHER_DEVICE_ID, 0x4008001c\r
+.set CYDEV_FLSECC_BASE, 0x48000000\r
+.set CYDEV_FLSECC_SIZE, 0x00008000\r
+.set CYDEV_FLSECC_DATA_MBASE, 0x48000000\r
+.set CYDEV_FLSECC_DATA_MSIZE, 0x00008000\r
+.set CYDEV_FLSHID_BASE, 0x49000000\r
+.set CYDEV_FLSHID_SIZE, 0x00000200\r
+.set CYDEV_FLSHID_RSVD_MBASE, 0x49000000\r
+.set CYDEV_FLSHID_RSVD_MSIZE, 0x00000080\r
+.set CYDEV_FLSHID_CUST_MDATA_MBASE, 0x49000080\r
+.set CYDEV_FLSHID_CUST_MDATA_MSIZE, 0x00000080\r
+.set CYDEV_FLSHID_CUST_TABLES_BASE, 0x49000100\r
+.set CYDEV_FLSHID_CUST_TABLES_SIZE, 0x00000040\r
+.set CYDEV_FLSHID_CUST_TABLES_Y_LOC, 0x49000100\r
+.set CYDEV_FLSHID_CUST_TABLES_X_LOC, 0x49000101\r
+.set CYDEV_FLSHID_CUST_TABLES_WAFER_NUM, 0x49000102\r
+.set CYDEV_FLSHID_CUST_TABLES_LOT_LSB, 0x49000103\r
+.set CYDEV_FLSHID_CUST_TABLES_LOT_MSB, 0x49000104\r
+.set CYDEV_FLSHID_CUST_TABLES_WRK_WK, 0x49000105\r
+.set CYDEV_FLSHID_CUST_TABLES_FAB_YR, 0x49000106\r
+.set CYDEV_FLSHID_CUST_TABLES_MINOR, 0x49000107\r
+.set CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ, 0x49000108\r
+.set CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ, 0x49000109\r
+.set CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ, 0x4900010a\r
+.set CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ, 0x4900010b\r
+.set CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ, 0x4900010c\r
+.set CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ, 0x4900010d\r
+.set CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ, 0x4900010e\r
+.set CYDEV_FLSHID_CUST_TABLES_IMO_USB, 0x4900010f\r
+.set CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS, 0x49000110\r
+.set CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS, 0x49000111\r
+.set CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS, 0x49000112\r
+.set CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS, 0x49000113\r
+.set CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS, 0x49000114\r
+.set CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS, 0x49000115\r
+.set CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS, 0x49000116\r
+.set CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS, 0x49000117\r
+.set CYDEV_FLSHID_CUST_TABLES_DEC_M1, 0x49000118\r
+.set CYDEV_FLSHID_CUST_TABLES_DEC_M2, 0x49000119\r
+.set CYDEV_FLSHID_CUST_TABLES_DEC_M3, 0x4900011a\r
+.set CYDEV_FLSHID_CUST_TABLES_DEC_M4, 0x4900011b\r
+.set CYDEV_FLSHID_CUST_TABLES_DEC_M5, 0x4900011c\r
+.set CYDEV_FLSHID_CUST_TABLES_DEC_M6, 0x4900011d\r
+.set CYDEV_FLSHID_CUST_TABLES_DEC_M7, 0x4900011e\r
+.set CYDEV_FLSHID_CUST_TABLES_DEC_M8, 0x4900011f\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC0_M1, 0x49000120\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC0_M2, 0x49000121\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC0_M3, 0x49000122\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC0_M4, 0x49000123\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC0_M5, 0x49000124\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC0_M6, 0x49000125\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC0_M7, 0x49000126\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC0_M8, 0x49000127\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC2_M1, 0x49000128\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC2_M2, 0x49000129\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC2_M3, 0x4900012a\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC2_M4, 0x4900012b\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC2_M5, 0x4900012c\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC2_M6, 0x4900012d\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC2_M7, 0x4900012e\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC2_M8, 0x4900012f\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC1_M1, 0x49000130\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC1_M2, 0x49000131\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC1_M3, 0x49000132\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC1_M4, 0x49000133\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC1_M5, 0x49000134\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC1_M6, 0x49000135\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC1_M7, 0x49000136\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC1_M8, 0x49000137\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC3_M1, 0x49000138\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC3_M2, 0x49000139\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC3_M3, 0x4900013a\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC3_M4, 0x4900013b\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC3_M5, 0x4900013c\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC3_M6, 0x4900013d\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC3_M7, 0x4900013e\r
+.set CYDEV_FLSHID_CUST_TABLES_DAC3_M8, 0x4900013f\r
+.set CYDEV_FLSHID_MFG_CFG_BASE, 0x49000180\r
+.set CYDEV_FLSHID_MFG_CFG_SIZE, 0x00000080\r
+.set CYDEV_FLSHID_MFG_CFG_IMO_TR1, 0x49000188\r
+.set CYDEV_FLSHID_MFG_CFG_CMP0_TR0, 0x490001ac\r
+.set CYDEV_FLSHID_MFG_CFG_CMP1_TR0, 0x490001ae\r
+.set CYDEV_FLSHID_MFG_CFG_CMP2_TR0, 0x490001b0\r
+.set CYDEV_FLSHID_MFG_CFG_CMP3_TR0, 0x490001b2\r
+.set CYDEV_FLSHID_MFG_CFG_CMP0_TR1, 0x490001b4\r
+.set CYDEV_FLSHID_MFG_CFG_CMP1_TR1, 0x490001b6\r
+.set CYDEV_FLSHID_MFG_CFG_CMP2_TR1, 0x490001b8\r
+.set CYDEV_FLSHID_MFG_CFG_CMP3_TR1, 0x490001ba\r
+.set CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM, 0x490001ce\r
+.set CYDEV_EXTMEM_BASE, 0x60000000\r
+.set CYDEV_EXTMEM_SIZE, 0x00800000\r
+.set CYDEV_EXTMEM_DATA_MBASE, 0x60000000\r
+.set CYDEV_EXTMEM_DATA_MSIZE, 0x00800000\r
+.set CYDEV_ITM_BASE, 0xe0000000\r
+.set CYDEV_ITM_SIZE, 0x00001000\r
+.set CYDEV_ITM_TRACE_EN, 0xe0000e00\r
+.set CYDEV_ITM_TRACE_PRIVILEGE, 0xe0000e40\r
+.set CYDEV_ITM_TRACE_CTRL, 0xe0000e80\r
+.set CYDEV_ITM_LOCK_ACCESS, 0xe0000fb0\r
+.set CYDEV_ITM_LOCK_STATUS, 0xe0000fb4\r
+.set CYDEV_ITM_PID4, 0xe0000fd0\r
+.set CYDEV_ITM_PID5, 0xe0000fd4\r
+.set CYDEV_ITM_PID6, 0xe0000fd8\r
+.set CYDEV_ITM_PID7, 0xe0000fdc\r
+.set CYDEV_ITM_PID0, 0xe0000fe0\r
+.set CYDEV_ITM_PID1, 0xe0000fe4\r
+.set CYDEV_ITM_PID2, 0xe0000fe8\r
+.set CYDEV_ITM_PID3, 0xe0000fec\r
+.set CYDEV_ITM_CID0, 0xe0000ff0\r
+.set CYDEV_ITM_CID1, 0xe0000ff4\r
+.set CYDEV_ITM_CID2, 0xe0000ff8\r
+.set CYDEV_ITM_CID3, 0xe0000ffc\r
+.set CYDEV_DWT_BASE, 0xe0001000\r
+.set CYDEV_DWT_SIZE, 0x0000005c\r
+.set CYDEV_DWT_CTRL, 0xe0001000\r
+.set CYDEV_DWT_CYCLE_COUNT, 0xe0001004\r
+.set CYDEV_DWT_CPI_COUNT, 0xe0001008\r
+.set CYDEV_DWT_EXC_OVHD_COUNT, 0xe000100c\r
+.set CYDEV_DWT_SLEEP_COUNT, 0xe0001010\r
+.set CYDEV_DWT_LSU_COUNT, 0xe0001014\r
+.set CYDEV_DWT_FOLD_COUNT, 0xe0001018\r
+.set CYDEV_DWT_PC_SAMPLE, 0xe000101c\r
+.set CYDEV_DWT_COMP_0, 0xe0001020\r
+.set CYDEV_DWT_MASK_0, 0xe0001024\r
+.set CYDEV_DWT_FUNCTION_0, 0xe0001028\r
+.set CYDEV_DWT_COMP_1, 0xe0001030\r
+.set CYDEV_DWT_MASK_1, 0xe0001034\r
+.set CYDEV_DWT_FUNCTION_1, 0xe0001038\r
+.set CYDEV_DWT_COMP_2, 0xe0001040\r
+.set CYDEV_DWT_MASK_2, 0xe0001044\r
+.set CYDEV_DWT_FUNCTION_2, 0xe0001048\r
+.set CYDEV_DWT_COMP_3, 0xe0001050\r
+.set CYDEV_DWT_MASK_3, 0xe0001054\r
+.set CYDEV_DWT_FUNCTION_3, 0xe0001058\r
+.set CYDEV_FPB_BASE, 0xe0002000\r
+.set CYDEV_FPB_SIZE, 0x00001000\r
+.set CYDEV_FPB_CTRL, 0xe0002000\r
+.set CYDEV_FPB_REMAP, 0xe0002004\r
+.set CYDEV_FPB_FP_COMP_0, 0xe0002008\r
+.set CYDEV_FPB_FP_COMP_1, 0xe000200c\r
+.set CYDEV_FPB_FP_COMP_2, 0xe0002010\r
+.set CYDEV_FPB_FP_COMP_3, 0xe0002014\r
+.set CYDEV_FPB_FP_COMP_4, 0xe0002018\r
+.set CYDEV_FPB_FP_COMP_5, 0xe000201c\r
+.set CYDEV_FPB_FP_COMP_6, 0xe0002020\r
+.set CYDEV_FPB_FP_COMP_7, 0xe0002024\r
+.set CYDEV_FPB_PID4, 0xe0002fd0\r
+.set CYDEV_FPB_PID5, 0xe0002fd4\r
+.set CYDEV_FPB_PID6, 0xe0002fd8\r
+.set CYDEV_FPB_PID7, 0xe0002fdc\r
+.set CYDEV_FPB_PID0, 0xe0002fe0\r
+.set CYDEV_FPB_PID1, 0xe0002fe4\r
+.set CYDEV_FPB_PID2, 0xe0002fe8\r
+.set CYDEV_FPB_PID3, 0xe0002fec\r
+.set CYDEV_FPB_CID0, 0xe0002ff0\r
+.set CYDEV_FPB_CID1, 0xe0002ff4\r
+.set CYDEV_FPB_CID2, 0xe0002ff8\r
+.set CYDEV_FPB_CID3, 0xe0002ffc\r
+.set CYDEV_NVIC_BASE, 0xe000e000\r
+.set CYDEV_NVIC_SIZE, 0x00000d3c\r
+.set CYDEV_NVIC_INT_CTL_TYPE, 0xe000e004\r
+.set CYDEV_NVIC_SYSTICK_CTL, 0xe000e010\r
+.set CYDEV_NVIC_SYSTICK_RELOAD, 0xe000e014\r
+.set CYDEV_NVIC_SYSTICK_CURRENT, 0xe000e018\r
+.set CYDEV_NVIC_SYSTICK_CAL, 0xe000e01c\r
+.set CYDEV_NVIC_SETENA0, 0xe000e100\r
+.set CYDEV_NVIC_CLRENA0, 0xe000e180\r
+.set CYDEV_NVIC_SETPEND0, 0xe000e200\r
+.set CYDEV_NVIC_CLRPEND0, 0xe000e280\r
+.set CYDEV_NVIC_ACTIVE0, 0xe000e300\r
+.set CYDEV_NVIC_PRI_0, 0xe000e400\r
+.set CYDEV_NVIC_PRI_1, 0xe000e401\r
+.set CYDEV_NVIC_PRI_2, 0xe000e402\r
+.set CYDEV_NVIC_PRI_3, 0xe000e403\r
+.set CYDEV_NVIC_PRI_4, 0xe000e404\r
+.set CYDEV_NVIC_PRI_5, 0xe000e405\r
+.set CYDEV_NVIC_PRI_6, 0xe000e406\r
+.set CYDEV_NVIC_PRI_7, 0xe000e407\r
+.set CYDEV_NVIC_PRI_8, 0xe000e408\r
+.set CYDEV_NVIC_PRI_9, 0xe000e409\r
+.set CYDEV_NVIC_PRI_10, 0xe000e40a\r
+.set CYDEV_NVIC_PRI_11, 0xe000e40b\r
+.set CYDEV_NVIC_PRI_12, 0xe000e40c\r
+.set CYDEV_NVIC_PRI_13, 0xe000e40d\r
+.set CYDEV_NVIC_PRI_14, 0xe000e40e\r
+.set CYDEV_NVIC_PRI_15, 0xe000e40f\r
+.set CYDEV_NVIC_PRI_16, 0xe000e410\r
+.set CYDEV_NVIC_PRI_17, 0xe000e411\r
+.set CYDEV_NVIC_PRI_18, 0xe000e412\r
+.set CYDEV_NVIC_PRI_19, 0xe000e413\r
+.set CYDEV_NVIC_PRI_20, 0xe000e414\r
+.set CYDEV_NVIC_PRI_21, 0xe000e415\r
+.set CYDEV_NVIC_PRI_22, 0xe000e416\r
+.set CYDEV_NVIC_PRI_23, 0xe000e417\r
+.set CYDEV_NVIC_PRI_24, 0xe000e418\r
+.set CYDEV_NVIC_PRI_25, 0xe000e419\r
+.set CYDEV_NVIC_PRI_26, 0xe000e41a\r
+.set CYDEV_NVIC_PRI_27, 0xe000e41b\r
+.set CYDEV_NVIC_PRI_28, 0xe000e41c\r
+.set CYDEV_NVIC_PRI_29, 0xe000e41d\r
+.set CYDEV_NVIC_PRI_30, 0xe000e41e\r
+.set CYDEV_NVIC_PRI_31, 0xe000e41f\r
+.set CYDEV_NVIC_CPUID_BASE, 0xe000ed00\r
+.set CYDEV_NVIC_INTR_CTRL_STATE, 0xe000ed04\r
+.set CYDEV_NVIC_VECT_OFFSET, 0xe000ed08\r
+.set CYDEV_NVIC_APPLN_INTR, 0xe000ed0c\r
+.set CYDEV_NVIC_SYSTEM_CONTROL, 0xe000ed10\r
+.set CYDEV_NVIC_CFG_CONTROL, 0xe000ed14\r
+.set CYDEV_NVIC_SYS_PRIO_HANDLER_4_7, 0xe000ed18\r
+.set CYDEV_NVIC_SYS_PRIO_HANDLER_8_11, 0xe000ed1c\r
+.set CYDEV_NVIC_SYS_PRIO_HANDLER_12_15, 0xe000ed20\r
+.set CYDEV_NVIC_SYS_HANDLER_CSR, 0xe000ed24\r
+.set CYDEV_NVIC_MEMMAN_FAULT_STATUS, 0xe000ed28\r
+.set CYDEV_NVIC_BUS_FAULT_STATUS, 0xe000ed29\r
+.set CYDEV_NVIC_USAGE_FAULT_STATUS, 0xe000ed2a\r
+.set CYDEV_NVIC_HARD_FAULT_STATUS, 0xe000ed2c\r
+.set CYDEV_NVIC_DEBUG_FAULT_STATUS, 0xe000ed30\r
+.set CYDEV_NVIC_MEMMAN_FAULT_ADD, 0xe000ed34\r
+.set CYDEV_NVIC_BUS_FAULT_ADD, 0xe000ed38\r
+.set CYDEV_CORE_DBG_BASE, 0xe000edf0\r
+.set CYDEV_CORE_DBG_SIZE, 0x00000010\r
+.set CYDEV_CORE_DBG_DBG_HLT_CS, 0xe000edf0\r
+.set CYDEV_CORE_DBG_DBG_REG_SEL, 0xe000edf4\r
+.set CYDEV_CORE_DBG_DBG_REG_DATA, 0xe000edf8\r
+.set CYDEV_CORE_DBG_EXC_MON_CTL, 0xe000edfc\r
+.set CYDEV_TPIU_BASE, 0xe0040000\r
+.set CYDEV_TPIU_SIZE, 0x00001000\r
+.set CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ, 0xe0040000\r
+.set CYDEV_TPIU_CURRENT_SYNC_PRT_SZ, 0xe0040004\r
+.set CYDEV_TPIU_ASYNC_CLK_PRESCALER, 0xe0040010\r
+.set CYDEV_TPIU_PROTOCOL, 0xe00400f0\r
+.set CYDEV_TPIU_FORM_FLUSH_STAT, 0xe0040300\r
+.set CYDEV_TPIU_FORM_FLUSH_CTRL, 0xe0040304\r
+.set CYDEV_TPIU_TRIGGER, 0xe0040ee8\r
+.set CYDEV_TPIU_ITETMDATA, 0xe0040eec\r
+.set CYDEV_TPIU_ITATBCTR2, 0xe0040ef0\r
+.set CYDEV_TPIU_ITATBCTR0, 0xe0040ef8\r
+.set CYDEV_TPIU_ITITMDATA, 0xe0040efc\r
+.set CYDEV_TPIU_ITCTRL, 0xe0040f00\r
+.set CYDEV_TPIU_DEVID, 0xe0040fc8\r
+.set CYDEV_TPIU_DEVTYPE, 0xe0040fcc\r
+.set CYDEV_TPIU_PID4, 0xe0040fd0\r
+.set CYDEV_TPIU_PID5, 0xe0040fd4\r
+.set CYDEV_TPIU_PID6, 0xe0040fd8\r
+.set CYDEV_TPIU_PID7, 0xe0040fdc\r
+.set CYDEV_TPIU_PID0, 0xe0040fe0\r
+.set CYDEV_TPIU_PID1, 0xe0040fe4\r
+.set CYDEV_TPIU_PID2, 0xe0040fe8\r
+.set CYDEV_TPIU_PID3, 0xe0040fec\r
+.set CYDEV_TPIU_CID0, 0xe0040ff0\r
+.set CYDEV_TPIU_CID1, 0xe0040ff4\r
+.set CYDEV_TPIU_CID2, 0xe0040ff8\r
+.set CYDEV_TPIU_CID3, 0xe0040ffc\r
+.set CYDEV_ETM_BASE, 0xe0041000\r
+.set CYDEV_ETM_SIZE, 0x00001000\r
+.set CYDEV_ETM_CTL, 0xe0041000\r
+.set CYDEV_ETM_CFG_CODE, 0xe0041004\r
+.set CYDEV_ETM_TRIG_EVENT, 0xe0041008\r
+.set CYDEV_ETM_STATUS, 0xe0041010\r
+.set CYDEV_ETM_SYS_CFG, 0xe0041014\r
+.set CYDEV_ETM_TRACE_ENB_EVENT, 0xe0041020\r
+.set CYDEV_ETM_TRACE_EN_CTRL1, 0xe0041024\r
+.set CYDEV_ETM_FIFOFULL_LEVEL, 0xe004102c\r
+.set CYDEV_ETM_SYNC_FREQ, 0xe00411e0\r
+.set CYDEV_ETM_ETM_ID, 0xe00411e4\r
+.set CYDEV_ETM_CFG_CODE_EXT, 0xe00411e8\r
+.set CYDEV_ETM_TR_SS_EMBICE_CTRL, 0xe00411f0\r
+.set CYDEV_ETM_CS_TRACE_ID, 0xe0041200\r
+.set CYDEV_ETM_OS_LOCK_ACCESS, 0xe0041300\r
+.set CYDEV_ETM_OS_LOCK_STATUS, 0xe0041304\r
+.set CYDEV_ETM_PDSR, 0xe0041314\r
+.set CYDEV_ETM_ITMISCIN, 0xe0041ee0\r
+.set CYDEV_ETM_ITTRIGOUT, 0xe0041ee8\r
+.set CYDEV_ETM_ITATBCTR2, 0xe0041ef0\r
+.set CYDEV_ETM_ITATBCTR0, 0xe0041ef8\r
+.set CYDEV_ETM_INT_MODE_CTRL, 0xe0041f00\r
+.set CYDEV_ETM_CLM_TAG_SET, 0xe0041fa0\r
+.set CYDEV_ETM_CLM_TAG_CLR, 0xe0041fa4\r
+.set CYDEV_ETM_LOCK_ACCESS, 0xe0041fb0\r
+.set CYDEV_ETM_LOCK_STATUS, 0xe0041fb4\r
+.set CYDEV_ETM_AUTH_STATUS, 0xe0041fb8\r
+.set CYDEV_ETM_DEV_TYPE, 0xe0041fcc\r
+.set CYDEV_ETM_PID4, 0xe0041fd0\r
+.set CYDEV_ETM_PID5, 0xe0041fd4\r
+.set CYDEV_ETM_PID6, 0xe0041fd8\r
+.set CYDEV_ETM_PID7, 0xe0041fdc\r
+.set CYDEV_ETM_PID0, 0xe0041fe0\r
+.set CYDEV_ETM_PID1, 0xe0041fe4\r
+.set CYDEV_ETM_PID2, 0xe0041fe8\r
+.set CYDEV_ETM_PID3, 0xe0041fec\r
+.set CYDEV_ETM_CID0, 0xe0041ff0\r
+.set CYDEV_ETM_CID1, 0xe0041ff4\r
+.set CYDEV_ETM_CID2, 0xe0041ff8\r
+.set CYDEV_ETM_CID3, 0xe0041ffc\r
+.set CYDEV_ROM_TABLE_BASE, 0xe00ff000\r
+.set CYDEV_ROM_TABLE_SIZE, 0x00001000\r
+.set CYDEV_ROM_TABLE_NVIC, 0xe00ff000\r
+.set CYDEV_ROM_TABLE_DWT, 0xe00ff004\r
+.set CYDEV_ROM_TABLE_FPB, 0xe00ff008\r
+.set CYDEV_ROM_TABLE_ITM, 0xe00ff00c\r
+.set CYDEV_ROM_TABLE_TPIU, 0xe00ff010\r
+.set CYDEV_ROM_TABLE_ETM, 0xe00ff014\r
+.set CYDEV_ROM_TABLE_END, 0xe00ff018\r
+.set CYDEV_ROM_TABLE_MEMTYPE, 0xe00fffcc\r
+.set CYDEV_ROM_TABLE_PID4, 0xe00fffd0\r
+.set CYDEV_ROM_TABLE_PID5, 0xe00fffd4\r
+.set CYDEV_ROM_TABLE_PID6, 0xe00fffd8\r
+.set CYDEV_ROM_TABLE_PID7, 0xe00fffdc\r
+.set CYDEV_ROM_TABLE_PID0, 0xe00fffe0\r
+.set CYDEV_ROM_TABLE_PID1, 0xe00fffe4\r
+.set CYDEV_ROM_TABLE_PID2, 0xe00fffe8\r
+.set CYDEV_ROM_TABLE_PID3, 0xe00fffec\r
+.set CYDEV_ROM_TABLE_CID0, 0xe00ffff0\r
+.set CYDEV_ROM_TABLE_CID1, 0xe00ffff4\r
+.set CYDEV_ROM_TABLE_CID2, 0xe00ffff8\r
+.set CYDEV_ROM_TABLE_CID3, 0xe00ffffc\r
+.set CYDEV_FLS_SIZE, CYDEV_FLASH_SIZE\r
+.set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE\r
+.set CYDEV_FLS_SECTOR_SIZE, 0x00010000\r
+.set CYDEV_FLS_ROW_SIZE, 0x00000100\r
+.set CYDEV_ECC_SECTOR_SIZE, 0x00002000\r
+.set CYDEV_ECC_ROW_SIZE, 0x00000020\r
+.set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400\r
+.set CYDEV_EEPROM_ROW_SIZE, 0x00000010\r
+.set CYDEV_PERIPH_BASE, CYDEV_CLKDIST_BASE\r
+.set CYCLK_LD_DISABLE, 0x00000004\r
+.set CYCLK_LD_SYNC_EN, 0x00000002\r
+.set CYCLK_LD_LOAD, 0x00000001\r
+.set CYCLK_PIPE, 0x00000080\r
+.set CYCLK_SSS, 0x00000040\r
+.set CYCLK_EARLY, 0x00000020\r
+.set CYCLK_DUTY, 0x00000010\r
+.set CYCLK_SYNC, 0x00000008\r
+.set CYCLK_SRC_SEL_CLK_SYNC_D, 0\r
+.set CYCLK_SRC_SEL_SYNC_DIG, 0\r
+.set CYCLK_SRC_SEL_IMO, 1\r
+.set CYCLK_SRC_SEL_XTAL_MHZ, 2\r
+.set CYCLK_SRC_SEL_XTALM, 2\r
+.set CYCLK_SRC_SEL_ILO, 3\r
+.set CYCLK_SRC_SEL_PLL, 4\r
+.set CYCLK_SRC_SEL_XTAL_KHZ, 5\r
+.set CYCLK_SRC_SEL_XTALK, 5\r
+.set CYCLK_SRC_SEL_DSI_G, 6\r
+.set CYCLK_SRC_SEL_DSI_D, 7\r
+.set CYCLK_SRC_SEL_CLK_SYNC_A, 0\r
+.set CYCLK_SRC_SEL_DSI_A, 7\r
--- /dev/null
+/*******************************************************************************\r
+* FILENAME: cydevicegnu_trm.inc\r
+* \r
+* PSoC Creator 2.2 Component Pack 6\r
+*\r
+* DESCRIPTION:\r
+* This file provides all of the address values for the entire PSoC device.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+********************************************************************************/\r
+\r
+.set CYDEV_FLASH_BASE, 0x00000000\r
+.set CYDEV_FLASH_SIZE, 0x00040000\r
+.set CYREG_FLASH_DATA_MBASE, 0x00000000\r
+.set CYREG_FLASH_DATA_MSIZE, 0x00040000\r
+.set CYDEV_SRAM_BASE, 0x1fff8000\r
+.set CYDEV_SRAM_SIZE, 0x00010000\r
+.set CYREG_SRAM_CODE64K_MBASE, 0x1fff8000\r
+.set CYREG_SRAM_CODE64K_MSIZE, 0x00004000\r
+.set CYREG_SRAM_CODE32K_MBASE, 0x1fffc000\r
+.set CYREG_SRAM_CODE32K_MSIZE, 0x00002000\r
+.set CYREG_SRAM_CODE16K_MBASE, 0x1fffe000\r
+.set CYREG_SRAM_CODE16K_MSIZE, 0x00001000\r
+.set CYREG_SRAM_CODE_MBASE, 0x1fff8000\r
+.set CYREG_SRAM_CODE_MSIZE, 0x00008000\r
+.set CYREG_SRAM_DATA_MBASE, 0x20000000\r
+.set CYREG_SRAM_DATA_MSIZE, 0x00008000\r
+.set CYREG_SRAM_DATA16K_MBASE, 0x20001000\r
+.set CYREG_SRAM_DATA16K_MSIZE, 0x00001000\r
+.set CYREG_SRAM_DATA32K_MBASE, 0x20002000\r
+.set CYREG_SRAM_DATA32K_MSIZE, 0x00002000\r
+.set CYREG_SRAM_DATA64K_MBASE, 0x20004000\r
+.set CYREG_SRAM_DATA64K_MSIZE, 0x00004000\r
+.set CYDEV_DMA_BASE, 0x20008000\r
+.set CYDEV_DMA_SIZE, 0x00008000\r
+.set CYREG_DMA_SRAM64K_MBASE, 0x20008000\r
+.set CYREG_DMA_SRAM64K_MSIZE, 0x00004000\r
+.set CYREG_DMA_SRAM32K_MBASE, 0x2000c000\r
+.set CYREG_DMA_SRAM32K_MSIZE, 0x00002000\r
+.set CYREG_DMA_SRAM16K_MBASE, 0x2000e000\r
+.set CYREG_DMA_SRAM16K_MSIZE, 0x00001000\r
+.set CYREG_DMA_SRAM_MBASE, 0x2000f000\r
+.set CYREG_DMA_SRAM_MSIZE, 0x00001000\r
+.set CYDEV_CLKDIST_BASE, 0x40004000\r
+.set CYDEV_CLKDIST_SIZE, 0x00000110\r
+.set CYREG_CLKDIST_CR, 0x40004000\r
+.set CYREG_CLKDIST_LD, 0x40004001\r
+.set CYREG_CLKDIST_WRK0, 0x40004002\r
+.set CYREG_CLKDIST_WRK1, 0x40004003\r
+.set CYREG_CLKDIST_MSTR0, 0x40004004\r
+.set CYREG_CLKDIST_MSTR1, 0x40004005\r
+.set CYREG_CLKDIST_BCFG0, 0x40004006\r
+.set CYREG_CLKDIST_BCFG1, 0x40004007\r
+.set CYREG_CLKDIST_BCFG2, 0x40004008\r
+.set CYREG_CLKDIST_UCFG, 0x40004009\r
+.set CYREG_CLKDIST_DLY0, 0x4000400a\r
+.set CYREG_CLKDIST_DLY1, 0x4000400b\r
+.set CYREG_CLKDIST_DMASK, 0x40004010\r
+.set CYREG_CLKDIST_AMASK, 0x40004014\r
+.set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080\r
+.set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003\r
+.set CYREG_CLKDIST_DCFG0_CFG0, 0x40004080\r
+.set CYREG_CLKDIST_DCFG0_CFG1, 0x40004081\r
+.set CYREG_CLKDIST_DCFG0_CFG2, 0x40004082\r
+.set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084\r
+.set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003\r
+.set CYREG_CLKDIST_DCFG1_CFG0, 0x40004084\r
+.set CYREG_CLKDIST_DCFG1_CFG1, 0x40004085\r
+.set CYREG_CLKDIST_DCFG1_CFG2, 0x40004086\r
+.set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088\r
+.set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003\r
+.set CYREG_CLKDIST_DCFG2_CFG0, 0x40004088\r
+.set CYREG_CLKDIST_DCFG2_CFG1, 0x40004089\r
+.set CYREG_CLKDIST_DCFG2_CFG2, 0x4000408a\r
+.set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c\r
+.set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003\r
+.set CYREG_CLKDIST_DCFG3_CFG0, 0x4000408c\r
+.set CYREG_CLKDIST_DCFG3_CFG1, 0x4000408d\r
+.set CYREG_CLKDIST_DCFG3_CFG2, 0x4000408e\r
+.set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090\r
+.set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003\r
+.set CYREG_CLKDIST_DCFG4_CFG0, 0x40004090\r
+.set CYREG_CLKDIST_DCFG4_CFG1, 0x40004091\r
+.set CYREG_CLKDIST_DCFG4_CFG2, 0x40004092\r
+.set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094\r
+.set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003\r
+.set CYREG_CLKDIST_DCFG5_CFG0, 0x40004094\r
+.set CYREG_CLKDIST_DCFG5_CFG1, 0x40004095\r
+.set CYREG_CLKDIST_DCFG5_CFG2, 0x40004096\r
+.set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098\r
+.set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003\r
+.set CYREG_CLKDIST_DCFG6_CFG0, 0x40004098\r
+.set CYREG_CLKDIST_DCFG6_CFG1, 0x40004099\r
+.set CYREG_CLKDIST_DCFG6_CFG2, 0x4000409a\r
+.set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c\r
+.set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003\r
+.set CYREG_CLKDIST_DCFG7_CFG0, 0x4000409c\r
+.set CYREG_CLKDIST_DCFG7_CFG1, 0x4000409d\r
+.set CYREG_CLKDIST_DCFG7_CFG2, 0x4000409e\r
+.set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100\r
+.set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004\r
+.set CYREG_CLKDIST_ACFG0_CFG0, 0x40004100\r
+.set CYREG_CLKDIST_ACFG0_CFG1, 0x40004101\r
+.set CYREG_CLKDIST_ACFG0_CFG2, 0x40004102\r
+.set CYREG_CLKDIST_ACFG0_CFG3, 0x40004103\r
+.set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104\r
+.set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004\r
+.set CYREG_CLKDIST_ACFG1_CFG0, 0x40004104\r
+.set CYREG_CLKDIST_ACFG1_CFG1, 0x40004105\r
+.set CYREG_CLKDIST_ACFG1_CFG2, 0x40004106\r
+.set CYREG_CLKDIST_ACFG1_CFG3, 0x40004107\r
+.set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108\r
+.set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004\r
+.set CYREG_CLKDIST_ACFG2_CFG0, 0x40004108\r
+.set CYREG_CLKDIST_ACFG2_CFG1, 0x40004109\r
+.set CYREG_CLKDIST_ACFG2_CFG2, 0x4000410a\r
+.set CYREG_CLKDIST_ACFG2_CFG3, 0x4000410b\r
+.set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c\r
+.set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004\r
+.set CYREG_CLKDIST_ACFG3_CFG0, 0x4000410c\r
+.set CYREG_CLKDIST_ACFG3_CFG1, 0x4000410d\r
+.set CYREG_CLKDIST_ACFG3_CFG2, 0x4000410e\r
+.set CYREG_CLKDIST_ACFG3_CFG3, 0x4000410f\r
+.set CYDEV_FASTCLK_BASE, 0x40004200\r
+.set CYDEV_FASTCLK_SIZE, 0x00000026\r
+.set CYDEV_FASTCLK_IMO_BASE, 0x40004200\r
+.set CYDEV_FASTCLK_IMO_SIZE, 0x00000001\r
+.set CYREG_FASTCLK_IMO_CR, 0x40004200\r
+.set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210\r
+.set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004\r
+.set CYREG_FASTCLK_XMHZ_CSR, 0x40004210\r
+.set CYREG_FASTCLK_XMHZ_CFG0, 0x40004212\r
+.set CYREG_FASTCLK_XMHZ_CFG1, 0x40004213\r
+.set CYDEV_FASTCLK_PLL_BASE, 0x40004220\r
+.set CYDEV_FASTCLK_PLL_SIZE, 0x00000006\r
+.set CYREG_FASTCLK_PLL_CFG0, 0x40004220\r
+.set CYREG_FASTCLK_PLL_CFG1, 0x40004221\r
+.set CYREG_FASTCLK_PLL_P, 0x40004222\r
+.set CYREG_FASTCLK_PLL_Q, 0x40004223\r
+.set CYREG_FASTCLK_PLL_SR, 0x40004225\r
+.set CYDEV_SLOWCLK_BASE, 0x40004300\r
+.set CYDEV_SLOWCLK_SIZE, 0x0000000b\r
+.set CYDEV_SLOWCLK_ILO_BASE, 0x40004300\r
+.set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002\r
+.set CYREG_SLOWCLK_ILO_CR0, 0x40004300\r
+.set CYREG_SLOWCLK_ILO_CR1, 0x40004301\r
+.set CYDEV_SLOWCLK_X32_BASE, 0x40004308\r
+.set CYDEV_SLOWCLK_X32_SIZE, 0x00000003\r
+.set CYREG_SLOWCLK_X32_CR, 0x40004308\r
+.set CYREG_SLOWCLK_X32_CFG, 0x40004309\r
+.set CYREG_SLOWCLK_X32_TST, 0x4000430a\r
+.set CYDEV_BOOST_BASE, 0x40004320\r
+.set CYDEV_BOOST_SIZE, 0x00000007\r
+.set CYREG_BOOST_CR0, 0x40004320\r
+.set CYREG_BOOST_CR1, 0x40004321\r
+.set CYREG_BOOST_CR2, 0x40004322\r
+.set CYREG_BOOST_CR3, 0x40004323\r
+.set CYREG_BOOST_SR, 0x40004324\r
+.set CYREG_BOOST_CR4, 0x40004325\r
+.set CYREG_BOOST_SR2, 0x40004326\r
+.set CYDEV_PWRSYS_BASE, 0x40004330\r
+.set CYDEV_PWRSYS_SIZE, 0x00000002\r
+.set CYREG_PWRSYS_CR0, 0x40004330\r
+.set CYREG_PWRSYS_CR1, 0x40004331\r
+.set CYDEV_PM_BASE, 0x40004380\r
+.set CYDEV_PM_SIZE, 0x00000057\r
+.set CYREG_PM_TW_CFG0, 0x40004380\r
+.set CYREG_PM_TW_CFG1, 0x40004381\r
+.set CYREG_PM_TW_CFG2, 0x40004382\r
+.set CYREG_PM_WDT_CFG, 0x40004383\r
+.set CYREG_PM_WDT_CR, 0x40004384\r
+.set CYREG_PM_INT_SR, 0x40004390\r
+.set CYREG_PM_MODE_CFG0, 0x40004391\r
+.set CYREG_PM_MODE_CFG1, 0x40004392\r
+.set CYREG_PM_MODE_CSR, 0x40004393\r
+.set CYREG_PM_USB_CR0, 0x40004394\r
+.set CYREG_PM_WAKEUP_CFG0, 0x40004398\r
+.set CYREG_PM_WAKEUP_CFG1, 0x40004399\r
+.set CYREG_PM_WAKEUP_CFG2, 0x4000439a\r
+.set CYDEV_PM_ACT_BASE, 0x400043a0\r
+.set CYDEV_PM_ACT_SIZE, 0x0000000e\r
+.set CYREG_PM_ACT_CFG0, 0x400043a0\r
+.set CYREG_PM_ACT_CFG1, 0x400043a1\r
+.set CYREG_PM_ACT_CFG2, 0x400043a2\r
+.set CYREG_PM_ACT_CFG3, 0x400043a3\r
+.set CYREG_PM_ACT_CFG4, 0x400043a4\r
+.set CYREG_PM_ACT_CFG5, 0x400043a5\r
+.set CYREG_PM_ACT_CFG6, 0x400043a6\r
+.set CYREG_PM_ACT_CFG7, 0x400043a7\r
+.set CYREG_PM_ACT_CFG8, 0x400043a8\r
+.set CYREG_PM_ACT_CFG9, 0x400043a9\r
+.set CYREG_PM_ACT_CFG10, 0x400043aa\r
+.set CYREG_PM_ACT_CFG11, 0x400043ab\r
+.set CYREG_PM_ACT_CFG12, 0x400043ac\r
+.set CYREG_PM_ACT_CFG13, 0x400043ad\r
+.set CYDEV_PM_STBY_BASE, 0x400043b0\r
+.set CYDEV_PM_STBY_SIZE, 0x0000000e\r
+.set CYREG_PM_STBY_CFG0, 0x400043b0\r
+.set CYREG_PM_STBY_CFG1, 0x400043b1\r
+.set CYREG_PM_STBY_CFG2, 0x400043b2\r
+.set CYREG_PM_STBY_CFG3, 0x400043b3\r
+.set CYREG_PM_STBY_CFG4, 0x400043b4\r
+.set CYREG_PM_STBY_CFG5, 0x400043b5\r
+.set CYREG_PM_STBY_CFG6, 0x400043b6\r
+.set CYREG_PM_STBY_CFG7, 0x400043b7\r
+.set CYREG_PM_STBY_CFG8, 0x400043b8\r
+.set CYREG_PM_STBY_CFG9, 0x400043b9\r
+.set CYREG_PM_STBY_CFG10, 0x400043ba\r
+.set CYREG_PM_STBY_CFG11, 0x400043bb\r
+.set CYREG_PM_STBY_CFG12, 0x400043bc\r
+.set CYREG_PM_STBY_CFG13, 0x400043bd\r
+.set CYDEV_PM_AVAIL_BASE, 0x400043c0\r
+.set CYDEV_PM_AVAIL_SIZE, 0x00000017\r
+.set CYREG_PM_AVAIL_CR0, 0x400043c0\r
+.set CYREG_PM_AVAIL_CR1, 0x400043c1\r
+.set CYREG_PM_AVAIL_CR2, 0x400043c2\r
+.set CYREG_PM_AVAIL_CR3, 0x400043c3\r
+.set CYREG_PM_AVAIL_CR4, 0x400043c4\r
+.set CYREG_PM_AVAIL_CR5, 0x400043c5\r
+.set CYREG_PM_AVAIL_CR6, 0x400043c6\r
+.set CYREG_PM_AVAIL_SR0, 0x400043d0\r
+.set CYREG_PM_AVAIL_SR1, 0x400043d1\r
+.set CYREG_PM_AVAIL_SR2, 0x400043d2\r
+.set CYREG_PM_AVAIL_SR3, 0x400043d3\r
+.set CYREG_PM_AVAIL_SR4, 0x400043d4\r
+.set CYREG_PM_AVAIL_SR5, 0x400043d5\r
+.set CYREG_PM_AVAIL_SR6, 0x400043d6\r
+.set CYDEV_PICU_BASE, 0x40004500\r
+.set CYDEV_PICU_SIZE, 0x000000b0\r
+.set CYDEV_PICU_INTTYPE_BASE, 0x40004500\r
+.set CYDEV_PICU_INTTYPE_SIZE, 0x00000080\r
+.set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500\r
+.set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008\r
+.set CYREG_PICU0_INTTYPE0, 0x40004500\r
+.set CYREG_PICU0_INTTYPE1, 0x40004501\r
+.set CYREG_PICU0_INTTYPE2, 0x40004502\r
+.set CYREG_PICU0_INTTYPE3, 0x40004503\r
+.set CYREG_PICU0_INTTYPE4, 0x40004504\r
+.set CYREG_PICU0_INTTYPE5, 0x40004505\r
+.set CYREG_PICU0_INTTYPE6, 0x40004506\r
+.set CYREG_PICU0_INTTYPE7, 0x40004507\r
+.set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508\r
+.set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008\r
+.set CYREG_PICU1_INTTYPE0, 0x40004508\r
+.set CYREG_PICU1_INTTYPE1, 0x40004509\r
+.set CYREG_PICU1_INTTYPE2, 0x4000450a\r
+.set CYREG_PICU1_INTTYPE3, 0x4000450b\r
+.set CYREG_PICU1_INTTYPE4, 0x4000450c\r
+.set CYREG_PICU1_INTTYPE5, 0x4000450d\r
+.set CYREG_PICU1_INTTYPE6, 0x4000450e\r
+.set CYREG_PICU1_INTTYPE7, 0x4000450f\r
+.set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510\r
+.set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008\r
+.set CYREG_PICU2_INTTYPE0, 0x40004510\r
+.set CYREG_PICU2_INTTYPE1, 0x40004511\r
+.set CYREG_PICU2_INTTYPE2, 0x40004512\r
+.set CYREG_PICU2_INTTYPE3, 0x40004513\r
+.set CYREG_PICU2_INTTYPE4, 0x40004514\r
+.set CYREG_PICU2_INTTYPE5, 0x40004515\r
+.set CYREG_PICU2_INTTYPE6, 0x40004516\r
+.set CYREG_PICU2_INTTYPE7, 0x40004517\r
+.set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518\r
+.set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008\r
+.set CYREG_PICU3_INTTYPE0, 0x40004518\r
+.set CYREG_PICU3_INTTYPE1, 0x40004519\r
+.set CYREG_PICU3_INTTYPE2, 0x4000451a\r
+.set CYREG_PICU3_INTTYPE3, 0x4000451b\r
+.set CYREG_PICU3_INTTYPE4, 0x4000451c\r
+.set CYREG_PICU3_INTTYPE5, 0x4000451d\r
+.set CYREG_PICU3_INTTYPE6, 0x4000451e\r
+.set CYREG_PICU3_INTTYPE7, 0x4000451f\r
+.set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520\r
+.set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008\r
+.set CYREG_PICU4_INTTYPE0, 0x40004520\r
+.set CYREG_PICU4_INTTYPE1, 0x40004521\r
+.set CYREG_PICU4_INTTYPE2, 0x40004522\r
+.set CYREG_PICU4_INTTYPE3, 0x40004523\r
+.set CYREG_PICU4_INTTYPE4, 0x40004524\r
+.set CYREG_PICU4_INTTYPE5, 0x40004525\r
+.set CYREG_PICU4_INTTYPE6, 0x40004526\r
+.set CYREG_PICU4_INTTYPE7, 0x40004527\r
+.set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528\r
+.set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008\r
+.set CYREG_PICU5_INTTYPE0, 0x40004528\r
+.set CYREG_PICU5_INTTYPE1, 0x40004529\r
+.set CYREG_PICU5_INTTYPE2, 0x4000452a\r
+.set CYREG_PICU5_INTTYPE3, 0x4000452b\r
+.set CYREG_PICU5_INTTYPE4, 0x4000452c\r
+.set CYREG_PICU5_INTTYPE5, 0x4000452d\r
+.set CYREG_PICU5_INTTYPE6, 0x4000452e\r
+.set CYREG_PICU5_INTTYPE7, 0x4000452f\r
+.set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530\r
+.set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008\r
+.set CYREG_PICU6_INTTYPE0, 0x40004530\r
+.set CYREG_PICU6_INTTYPE1, 0x40004531\r
+.set CYREG_PICU6_INTTYPE2, 0x40004532\r
+.set CYREG_PICU6_INTTYPE3, 0x40004533\r
+.set CYREG_PICU6_INTTYPE4, 0x40004534\r
+.set CYREG_PICU6_INTTYPE5, 0x40004535\r
+.set CYREG_PICU6_INTTYPE6, 0x40004536\r
+.set CYREG_PICU6_INTTYPE7, 0x40004537\r
+.set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560\r
+.set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008\r
+.set CYREG_PICU12_INTTYPE0, 0x40004560\r
+.set CYREG_PICU12_INTTYPE1, 0x40004561\r
+.set CYREG_PICU12_INTTYPE2, 0x40004562\r
+.set CYREG_PICU12_INTTYPE3, 0x40004563\r
+.set CYREG_PICU12_INTTYPE4, 0x40004564\r
+.set CYREG_PICU12_INTTYPE5, 0x40004565\r
+.set CYREG_PICU12_INTTYPE6, 0x40004566\r
+.set CYREG_PICU12_INTTYPE7, 0x40004567\r
+.set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578\r
+.set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008\r
+.set CYREG_PICU15_INTTYPE0, 0x40004578\r
+.set CYREG_PICU15_INTTYPE1, 0x40004579\r
+.set CYREG_PICU15_INTTYPE2, 0x4000457a\r
+.set CYREG_PICU15_INTTYPE3, 0x4000457b\r
+.set CYREG_PICU15_INTTYPE4, 0x4000457c\r
+.set CYREG_PICU15_INTTYPE5, 0x4000457d\r
+.set CYREG_PICU15_INTTYPE6, 0x4000457e\r
+.set CYREG_PICU15_INTTYPE7, 0x4000457f\r
+.set CYDEV_PICU_STAT_BASE, 0x40004580\r
+.set CYDEV_PICU_STAT_SIZE, 0x00000010\r
+.set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580\r
+.set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001\r
+.set CYREG_PICU0_INTSTAT, 0x40004580\r
+.set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581\r
+.set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001\r
+.set CYREG_PICU1_INTSTAT, 0x40004581\r
+.set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582\r
+.set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001\r
+.set CYREG_PICU2_INTSTAT, 0x40004582\r
+.set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583\r
+.set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001\r
+.set CYREG_PICU3_INTSTAT, 0x40004583\r
+.set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584\r
+.set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001\r
+.set CYREG_PICU4_INTSTAT, 0x40004584\r
+.set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585\r
+.set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001\r
+.set CYREG_PICU5_INTSTAT, 0x40004585\r
+.set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586\r
+.set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001\r
+.set CYREG_PICU6_INTSTAT, 0x40004586\r
+.set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c\r
+.set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001\r
+.set CYREG_PICU12_INTSTAT, 0x4000458c\r
+.set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f\r
+.set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001\r
+.set CYREG_PICU15_INTSTAT, 0x4000458f\r
+.set CYDEV_PICU_SNAP_BASE, 0x40004590\r
+.set CYDEV_PICU_SNAP_SIZE, 0x00000010\r
+.set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590\r
+.set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001\r
+.set CYREG_PICU0_SNAP, 0x40004590\r
+.set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591\r
+.set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001\r
+.set CYREG_PICU1_SNAP, 0x40004591\r
+.set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592\r
+.set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001\r
+.set CYREG_PICU2_SNAP, 0x40004592\r
+.set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593\r
+.set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001\r
+.set CYREG_PICU3_SNAP, 0x40004593\r
+.set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594\r
+.set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001\r
+.set CYREG_PICU4_SNAP, 0x40004594\r
+.set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595\r
+.set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001\r
+.set CYREG_PICU5_SNAP, 0x40004595\r
+.set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596\r
+.set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001\r
+.set CYREG_PICU6_SNAP, 0x40004596\r
+.set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c\r
+.set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001\r
+.set CYREG_PICU12_SNAP, 0x4000459c\r
+.set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f\r
+.set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001\r
+.set CYREG_PICU_15_SNAP_15, 0x4000459f\r
+.set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0\r
+.set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010\r
+.set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0\r
+.set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001\r
+.set CYREG_PICU0_DISABLE_COR, 0x400045a0\r
+.set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1\r
+.set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001\r
+.set CYREG_PICU1_DISABLE_COR, 0x400045a1\r
+.set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2\r
+.set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001\r
+.set CYREG_PICU2_DISABLE_COR, 0x400045a2\r
+.set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3\r
+.set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001\r
+.set CYREG_PICU3_DISABLE_COR, 0x400045a3\r
+.set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4\r
+.set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001\r
+.set CYREG_PICU4_DISABLE_COR, 0x400045a4\r
+.set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5\r
+.set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001\r
+.set CYREG_PICU5_DISABLE_COR, 0x400045a5\r
+.set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6\r
+.set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001\r
+.set CYREG_PICU6_DISABLE_COR, 0x400045a6\r
+.set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac\r
+.set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001\r
+.set CYREG_PICU12_DISABLE_COR, 0x400045ac\r
+.set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af\r
+.set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001\r
+.set CYREG_PICU15_DISABLE_COR, 0x400045af\r
+.set CYDEV_MFGCFG_BASE, 0x40004600\r
+.set CYDEV_MFGCFG_SIZE, 0x000000ed\r
+.set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600\r
+.set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038\r
+.set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608\r
+.set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001\r
+.set CYREG_DAC0_TR, 0x40004608\r
+.set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609\r
+.set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001\r
+.set CYREG_DAC1_TR, 0x40004609\r
+.set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a\r
+.set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001\r
+.set CYREG_DAC2_TR, 0x4000460a\r
+.set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b\r
+.set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001\r
+.set CYREG_DAC3_TR, 0x4000460b\r
+.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610\r
+.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001\r
+.set CYREG_NPUMP_DSM_TR0, 0x40004610\r
+.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611\r
+.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001\r
+.set CYREG_NPUMP_SC_TR0, 0x40004611\r
+.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612\r
+.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001\r
+.set CYREG_NPUMP_OPAMP_TR0, 0x40004612\r
+.set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614\r
+.set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001\r
+.set CYREG_SAR0_TR0, 0x40004614\r
+.set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616\r
+.set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001\r
+.set CYREG_SAR1_TR0, 0x40004616\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002\r
+.set CYREG_OPAMP0_TR0, 0x40004620\r
+.set CYREG_OPAMP0_TR1, 0x40004621\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002\r
+.set CYREG_OPAMP1_TR0, 0x40004622\r
+.set CYREG_OPAMP1_TR1, 0x40004623\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002\r
+.set CYREG_OPAMP2_TR0, 0x40004624\r
+.set CYREG_OPAMP2_TR1, 0x40004625\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626\r
+.set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002\r
+.set CYREG_OPAMP3_TR0, 0x40004626\r
+.set CYREG_OPAMP3_TR1, 0x40004627\r
+.set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630\r
+.set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002\r
+.set CYREG_CMP0_TR0, 0x40004630\r
+.set CYREG_CMP0_TR1, 0x40004631\r
+.set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632\r
+.set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002\r
+.set CYREG_CMP1_TR0, 0x40004632\r
+.set CYREG_CMP1_TR1, 0x40004633\r
+.set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634\r
+.set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002\r
+.set CYREG_CMP2_TR0, 0x40004634\r
+.set CYREG_CMP2_TR1, 0x40004635\r
+.set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636\r
+.set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002\r
+.set CYREG_CMP3_TR0, 0x40004636\r
+.set CYREG_CMP3_TR1, 0x40004637\r
+.set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680\r
+.set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b\r
+.set CYREG_PWRSYS_HIB_TR0, 0x40004680\r
+.set CYREG_PWRSYS_HIB_TR1, 0x40004681\r
+.set CYREG_PWRSYS_I2C_TR, 0x40004682\r
+.set CYREG_PWRSYS_SLP_TR, 0x40004683\r
+.set CYREG_PWRSYS_BUZZ_TR, 0x40004684\r
+.set CYREG_PWRSYS_WAKE_TR0, 0x40004685\r
+.set CYREG_PWRSYS_WAKE_TR1, 0x40004686\r
+.set CYREG_PWRSYS_BREF_TR, 0x40004687\r
+.set CYREG_PWRSYS_BG_TR, 0x40004688\r
+.set CYREG_PWRSYS_WAKE_TR2, 0x40004689\r
+.set CYREG_PWRSYS_WAKE_TR3, 0x4000468a\r
+.set CYDEV_MFGCFG_ILO_BASE, 0x40004690\r
+.set CYDEV_MFGCFG_ILO_SIZE, 0x00000002\r
+.set CYREG_ILO_TR0, 0x40004690\r
+.set CYREG_ILO_TR1, 0x40004691\r
+.set CYDEV_MFGCFG_X32_BASE, 0x40004698\r
+.set CYDEV_MFGCFG_X32_SIZE, 0x00000001\r
+.set CYREG_X32_TR, 0x40004698\r
+.set CYDEV_MFGCFG_IMO_BASE, 0x400046a0\r
+.set CYDEV_MFGCFG_IMO_SIZE, 0x00000005\r
+.set CYREG_IMO_TR0, 0x400046a0\r
+.set CYREG_IMO_TR1, 0x400046a1\r
+.set CYREG_IMO_GAIN, 0x400046a2\r
+.set CYREG_IMO_C36M, 0x400046a3\r
+.set CYREG_IMO_TR2, 0x400046a4\r
+.set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8\r
+.set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001\r
+.set CYREG_XMHZ_TR, 0x400046a8\r
+.set CYREG_MFGCFG_DLY, 0x400046c0\r
+.set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0\r
+.set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d\r
+.set CYREG_MLOGIC_DMPSTR, 0x400046e2\r
+.set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4\r
+.set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002\r
+.set CYREG_MLOGIC_SEG_CR, 0x400046e4\r
+.set CYREG_MLOGIC_SEG_CFG0, 0x400046e5\r
+.set CYREG_MLOGIC_DEBUG, 0x400046e8\r
+.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea\r
+.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001\r
+.set CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea\r
+.set CYREG_MLOGIC_REV_ID, 0x400046ec\r
+.set CYDEV_RESET_BASE, 0x400046f0\r
+.set CYDEV_RESET_SIZE, 0x0000000f\r
+.set CYREG_RESET_IPOR_CR0, 0x400046f0\r
+.set CYREG_RESET_IPOR_CR1, 0x400046f1\r
+.set CYREG_RESET_IPOR_CR2, 0x400046f2\r
+.set CYREG_RESET_IPOR_CR3, 0x400046f3\r
+.set CYREG_RESET_CR0, 0x400046f4\r
+.set CYREG_RESET_CR1, 0x400046f5\r
+.set CYREG_RESET_CR2, 0x400046f6\r
+.set CYREG_RESET_CR3, 0x400046f7\r
+.set CYREG_RESET_CR4, 0x400046f8\r
+.set CYREG_RESET_CR5, 0x400046f9\r
+.set CYREG_RESET_SR0, 0x400046fa\r
+.set CYREG_RESET_SR1, 0x400046fb\r
+.set CYREG_RESET_SR2, 0x400046fc\r
+.set CYREG_RESET_SR3, 0x400046fd\r
+.set CYREG_RESET_TR, 0x400046fe\r
+.set CYDEV_SPC_BASE, 0x40004700\r
+.set CYDEV_SPC_SIZE, 0x00000100\r
+.set CYREG_SPC_FM_EE_CR, 0x40004700\r
+.set CYREG_SPC_FM_EE_WAKE_CNT, 0x40004701\r
+.set CYREG_SPC_EE_SCR, 0x40004702\r
+.set CYREG_SPC_EE_ERR, 0x40004703\r
+.set CYREG_SPC_CPU_DATA, 0x40004720\r
+.set CYREG_SPC_DMA_DATA, 0x40004721\r
+.set CYREG_SPC_SR, 0x40004722\r
+.set CYREG_SPC_CR, 0x40004723\r
+.set CYDEV_SPC_DMM_MAP_BASE, 0x40004780\r
+.set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080\r
+.set CYREG_SPC_DMM_MAP_SRAM_MBASE, 0x40004780\r
+.set CYREG_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080\r
+.set CYDEV_CACHE_BASE, 0x40004800\r
+.set CYDEV_CACHE_SIZE, 0x0000009c\r
+.set CYREG_CACHE_CC_CTL, 0x40004800\r
+.set CYREG_CACHE_ECC_CORR, 0x40004880\r
+.set CYREG_CACHE_ECC_ERR, 0x40004888\r
+.set CYREG_CACHE_FLASH_ERR, 0x40004890\r
+.set CYREG_CACHE_HITMISS, 0x40004898\r
+.set CYDEV_I2C_BASE, 0x40004900\r
+.set CYDEV_I2C_SIZE, 0x000000e1\r
+.set CYREG_I2C_XCFG, 0x400049c8\r
+.set CYREG_I2C_ADR, 0x400049ca\r
+.set CYREG_I2C_CFG, 0x400049d6\r
+.set CYREG_I2C_CSR, 0x400049d7\r
+.set CYREG_I2C_D, 0x400049d8\r
+.set CYREG_I2C_MCSR, 0x400049d9\r
+.set CYREG_I2C_CLK_DIV1, 0x400049db\r
+.set CYREG_I2C_CLK_DIV2, 0x400049dc\r
+.set CYREG_I2C_TMOUT_CSR, 0x400049dd\r
+.set CYREG_I2C_TMOUT_SR, 0x400049de\r
+.set CYREG_I2C_TMOUT_CFG0, 0x400049df\r
+.set CYREG_I2C_TMOUT_CFG1, 0x400049e0\r
+.set CYDEV_DEC_BASE, 0x40004e00\r
+.set CYDEV_DEC_SIZE, 0x00000015\r
+.set CYREG_DEC_CR, 0x40004e00\r
+.set CYREG_DEC_SR, 0x40004e01\r
+.set CYREG_DEC_SHIFT1, 0x40004e02\r
+.set CYREG_DEC_SHIFT2, 0x40004e03\r
+.set CYREG_DEC_DR2, 0x40004e04\r
+.set CYREG_DEC_DR2H, 0x40004e05\r
+.set CYREG_DEC_DR1, 0x40004e06\r
+.set CYREG_DEC_OCOR, 0x40004e08\r
+.set CYREG_DEC_OCORM, 0x40004e09\r
+.set CYREG_DEC_OCORH, 0x40004e0a\r
+.set CYREG_DEC_GCOR, 0x40004e0c\r
+.set CYREG_DEC_GCORH, 0x40004e0d\r
+.set CYREG_DEC_GVAL, 0x40004e0e\r
+.set CYREG_DEC_OUTSAMP, 0x40004e10\r
+.set CYREG_DEC_OUTSAMPM, 0x40004e11\r
+.set CYREG_DEC_OUTSAMPH, 0x40004e12\r
+.set CYREG_DEC_OUTSAMPS, 0x40004e13\r
+.set CYREG_DEC_COHER, 0x40004e14\r
+.set CYDEV_TMR0_BASE, 0x40004f00\r
+.set CYDEV_TMR0_SIZE, 0x0000000c\r
+.set CYREG_TMR0_CFG0, 0x40004f00\r
+.set CYREG_TMR0_CFG1, 0x40004f01\r
+.set CYREG_TMR0_CFG2, 0x40004f02\r
+.set CYREG_TMR0_SR0, 0x40004f03\r
+.set CYREG_TMR0_PER0, 0x40004f04\r
+.set CYREG_TMR0_PER1, 0x40004f05\r
+.set CYREG_TMR0_CNT_CMP0, 0x40004f06\r
+.set CYREG_TMR0_CNT_CMP1, 0x40004f07\r
+.set CYREG_TMR0_CAP0, 0x40004f08\r
+.set CYREG_TMR0_CAP1, 0x40004f09\r
+.set CYREG_TMR0_RT0, 0x40004f0a\r
+.set CYREG_TMR0_RT1, 0x40004f0b\r
+.set CYDEV_TMR1_BASE, 0x40004f0c\r
+.set CYDEV_TMR1_SIZE, 0x0000000c\r
+.set CYREG_TMR1_CFG0, 0x40004f0c\r
+.set CYREG_TMR1_CFG1, 0x40004f0d\r
+.set CYREG_TMR1_CFG2, 0x40004f0e\r
+.set CYREG_TMR1_SR0, 0x40004f0f\r
+.set CYREG_TMR1_PER0, 0x40004f10\r
+.set CYREG_TMR1_PER1, 0x40004f11\r
+.set CYREG_TMR1_CNT_CMP0, 0x40004f12\r
+.set CYREG_TMR1_CNT_CMP1, 0x40004f13\r
+.set CYREG_TMR1_CAP0, 0x40004f14\r
+.set CYREG_TMR1_CAP1, 0x40004f15\r
+.set CYREG_TMR1_RT0, 0x40004f16\r
+.set CYREG_TMR1_RT1, 0x40004f17\r
+.set CYDEV_TMR2_BASE, 0x40004f18\r
+.set CYDEV_TMR2_SIZE, 0x0000000c\r
+.set CYREG_TMR2_CFG0, 0x40004f18\r
+.set CYREG_TMR2_CFG1, 0x40004f19\r
+.set CYREG_TMR2_CFG2, 0x40004f1a\r
+.set CYREG_TMR2_SR0, 0x40004f1b\r
+.set CYREG_TMR2_PER0, 0x40004f1c\r
+.set CYREG_TMR2_PER1, 0x40004f1d\r
+.set CYREG_TMR2_CNT_CMP0, 0x40004f1e\r
+.set CYREG_TMR2_CNT_CMP1, 0x40004f1f\r
+.set CYREG_TMR2_CAP0, 0x40004f20\r
+.set CYREG_TMR2_CAP1, 0x40004f21\r
+.set CYREG_TMR2_RT0, 0x40004f22\r
+.set CYREG_TMR2_RT1, 0x40004f23\r
+.set CYDEV_TMR3_BASE, 0x40004f24\r
+.set CYDEV_TMR3_SIZE, 0x0000000c\r
+.set CYREG_TMR3_CFG0, 0x40004f24\r
+.set CYREG_TMR3_CFG1, 0x40004f25\r
+.set CYREG_TMR3_CFG2, 0x40004f26\r
+.set CYREG_TMR3_SR0, 0x40004f27\r
+.set CYREG_TMR3_PER0, 0x40004f28\r
+.set CYREG_TMR3_PER1, 0x40004f29\r
+.set CYREG_TMR3_CNT_CMP0, 0x40004f2a\r
+.set CYREG_TMR3_CNT_CMP1, 0x40004f2b\r
+.set CYREG_TMR3_CAP0, 0x40004f2c\r
+.set CYREG_TMR3_CAP1, 0x40004f2d\r
+.set CYREG_TMR3_RT0, 0x40004f2e\r
+.set CYREG_TMR3_RT1, 0x40004f2f\r
+.set CYDEV_IO_BASE, 0x40005000\r
+.set CYDEV_IO_SIZE, 0x00000200\r
+.set CYDEV_IO_PC_BASE, 0x40005000\r
+.set CYDEV_IO_PC_SIZE, 0x00000080\r
+.set CYDEV_IO_PC_PRT0_BASE, 0x40005000\r
+.set CYDEV_IO_PC_PRT0_SIZE, 0x00000008\r
+.set CYREG_PRT0_PC0, 0x40005000\r
+.set CYREG_PRT0_PC1, 0x40005001\r
+.set CYREG_PRT0_PC2, 0x40005002\r
+.set CYREG_PRT0_PC3, 0x40005003\r
+.set CYREG_PRT0_PC4, 0x40005004\r
+.set CYREG_PRT0_PC5, 0x40005005\r
+.set CYREG_PRT0_PC6, 0x40005006\r
+.set CYREG_PRT0_PC7, 0x40005007\r
+.set CYDEV_IO_PC_PRT1_BASE, 0x40005008\r
+.set CYDEV_IO_PC_PRT1_SIZE, 0x00000008\r
+.set CYREG_PRT1_PC0, 0x40005008\r
+.set CYREG_PRT1_PC1, 0x40005009\r
+.set CYREG_PRT1_PC2, 0x4000500a\r
+.set CYREG_PRT1_PC3, 0x4000500b\r
+.set CYREG_PRT1_PC4, 0x4000500c\r
+.set CYREG_PRT1_PC5, 0x4000500d\r
+.set CYREG_PRT1_PC6, 0x4000500e\r
+.set CYREG_PRT1_PC7, 0x4000500f\r
+.set CYDEV_IO_PC_PRT2_BASE, 0x40005010\r
+.set CYDEV_IO_PC_PRT2_SIZE, 0x00000008\r
+.set CYREG_PRT2_PC0, 0x40005010\r
+.set CYREG_PRT2_PC1, 0x40005011\r
+.set CYREG_PRT2_PC2, 0x40005012\r
+.set CYREG_PRT2_PC3, 0x40005013\r
+.set CYREG_PRT2_PC4, 0x40005014\r
+.set CYREG_PRT2_PC5, 0x40005015\r
+.set CYREG_PRT2_PC6, 0x40005016\r
+.set CYREG_PRT2_PC7, 0x40005017\r
+.set CYDEV_IO_PC_PRT3_BASE, 0x40005018\r
+.set CYDEV_IO_PC_PRT3_SIZE, 0x00000008\r
+.set CYREG_PRT3_PC0, 0x40005018\r
+.set CYREG_PRT3_PC1, 0x40005019\r
+.set CYREG_PRT3_PC2, 0x4000501a\r
+.set CYREG_PRT3_PC3, 0x4000501b\r
+.set CYREG_PRT3_PC4, 0x4000501c\r
+.set CYREG_PRT3_PC5, 0x4000501d\r
+.set CYREG_PRT3_PC6, 0x4000501e\r
+.set CYREG_PRT3_PC7, 0x4000501f\r
+.set CYDEV_IO_PC_PRT4_BASE, 0x40005020\r
+.set CYDEV_IO_PC_PRT4_SIZE, 0x00000008\r
+.set CYREG_PRT4_PC0, 0x40005020\r
+.set CYREG_PRT4_PC1, 0x40005021\r
+.set CYREG_PRT4_PC2, 0x40005022\r
+.set CYREG_PRT4_PC3, 0x40005023\r
+.set CYREG_PRT4_PC4, 0x40005024\r
+.set CYREG_PRT4_PC5, 0x40005025\r
+.set CYREG_PRT4_PC6, 0x40005026\r
+.set CYREG_PRT4_PC7, 0x40005027\r
+.set CYDEV_IO_PC_PRT5_BASE, 0x40005028\r
+.set CYDEV_IO_PC_PRT5_SIZE, 0x00000008\r
+.set CYREG_PRT5_PC0, 0x40005028\r
+.set CYREG_PRT5_PC1, 0x40005029\r
+.set CYREG_PRT5_PC2, 0x4000502a\r
+.set CYREG_PRT5_PC3, 0x4000502b\r
+.set CYREG_PRT5_PC4, 0x4000502c\r
+.set CYREG_PRT5_PC5, 0x4000502d\r
+.set CYREG_PRT5_PC6, 0x4000502e\r
+.set CYREG_PRT5_PC7, 0x4000502f\r
+.set CYDEV_IO_PC_PRT6_BASE, 0x40005030\r
+.set CYDEV_IO_PC_PRT6_SIZE, 0x00000008\r
+.set CYREG_PRT6_PC0, 0x40005030\r
+.set CYREG_PRT6_PC1, 0x40005031\r
+.set CYREG_PRT6_PC2, 0x40005032\r
+.set CYREG_PRT6_PC3, 0x40005033\r
+.set CYREG_PRT6_PC4, 0x40005034\r
+.set CYREG_PRT6_PC5, 0x40005035\r
+.set CYREG_PRT6_PC6, 0x40005036\r
+.set CYREG_PRT6_PC7, 0x40005037\r
+.set CYDEV_IO_PC_PRT12_BASE, 0x40005060\r
+.set CYDEV_IO_PC_PRT12_SIZE, 0x00000008\r
+.set CYREG_PRT12_PC0, 0x40005060\r
+.set CYREG_PRT12_PC1, 0x40005061\r
+.set CYREG_PRT12_PC2, 0x40005062\r
+.set CYREG_PRT12_PC3, 0x40005063\r
+.set CYREG_PRT12_PC4, 0x40005064\r
+.set CYREG_PRT12_PC5, 0x40005065\r
+.set CYREG_PRT12_PC6, 0x40005066\r
+.set CYREG_PRT12_PC7, 0x40005067\r
+.set CYDEV_IO_PC_PRT15_BASE, 0x40005078\r
+.set CYDEV_IO_PC_PRT15_SIZE, 0x00000006\r
+.set CYREG_IO_PC_PRT15_PC0, 0x40005078\r
+.set CYREG_IO_PC_PRT15_PC1, 0x40005079\r
+.set CYREG_IO_PC_PRT15_PC2, 0x4000507a\r
+.set CYREG_IO_PC_PRT15_PC3, 0x4000507b\r
+.set CYREG_IO_PC_PRT15_PC4, 0x4000507c\r
+.set CYREG_IO_PC_PRT15_PC5, 0x4000507d\r
+.set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e\r
+.set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002\r
+.set CYREG_IO_PC_PRT15_7_6_PC0, 0x4000507e\r
+.set CYREG_IO_PC_PRT15_7_6_PC1, 0x4000507f\r
+.set CYDEV_IO_DR_BASE, 0x40005080\r
+.set CYDEV_IO_DR_SIZE, 0x00000010\r
+.set CYDEV_IO_DR_PRT0_BASE, 0x40005080\r
+.set CYDEV_IO_DR_PRT0_SIZE, 0x00000001\r
+.set CYREG_PRT0_DR_ALIAS, 0x40005080\r
+.set CYDEV_IO_DR_PRT1_BASE, 0x40005081\r
+.set CYDEV_IO_DR_PRT1_SIZE, 0x00000001\r
+.set CYREG_PRT1_DR_ALIAS, 0x40005081\r
+.set CYDEV_IO_DR_PRT2_BASE, 0x40005082\r
+.set CYDEV_IO_DR_PRT2_SIZE, 0x00000001\r
+.set CYREG_PRT2_DR_ALIAS, 0x40005082\r
+.set CYDEV_IO_DR_PRT3_BASE, 0x40005083\r
+.set CYDEV_IO_DR_PRT3_SIZE, 0x00000001\r
+.set CYREG_PRT3_DR_ALIAS, 0x40005083\r
+.set CYDEV_IO_DR_PRT4_BASE, 0x40005084\r
+.set CYDEV_IO_DR_PRT4_SIZE, 0x00000001\r
+.set CYREG_PRT4_DR_ALIAS, 0x40005084\r
+.set CYDEV_IO_DR_PRT5_BASE, 0x40005085\r
+.set CYDEV_IO_DR_PRT5_SIZE, 0x00000001\r
+.set CYREG_PRT5_DR_ALIAS, 0x40005085\r
+.set CYDEV_IO_DR_PRT6_BASE, 0x40005086\r
+.set CYDEV_IO_DR_PRT6_SIZE, 0x00000001\r
+.set CYREG_PRT6_DR_ALIAS, 0x40005086\r
+.set CYDEV_IO_DR_PRT12_BASE, 0x4000508c\r
+.set CYDEV_IO_DR_PRT12_SIZE, 0x00000001\r
+.set CYREG_PRT12_DR_ALIAS, 0x4000508c\r
+.set CYDEV_IO_DR_PRT15_BASE, 0x4000508f\r
+.set CYDEV_IO_DR_PRT15_SIZE, 0x00000001\r
+.set CYREG_PRT15_DR_15_ALIAS, 0x4000508f\r
+.set CYDEV_IO_PS_BASE, 0x40005090\r
+.set CYDEV_IO_PS_SIZE, 0x00000010\r
+.set CYDEV_IO_PS_PRT0_BASE, 0x40005090\r
+.set CYDEV_IO_PS_PRT0_SIZE, 0x00000001\r
+.set CYREG_PRT0_PS_ALIAS, 0x40005090\r
+.set CYDEV_IO_PS_PRT1_BASE, 0x40005091\r
+.set CYDEV_IO_PS_PRT1_SIZE, 0x00000001\r
+.set CYREG_PRT1_PS_ALIAS, 0x40005091\r
+.set CYDEV_IO_PS_PRT2_BASE, 0x40005092\r
+.set CYDEV_IO_PS_PRT2_SIZE, 0x00000001\r
+.set CYREG_PRT2_PS_ALIAS, 0x40005092\r
+.set CYDEV_IO_PS_PRT3_BASE, 0x40005093\r
+.set CYDEV_IO_PS_PRT3_SIZE, 0x00000001\r
+.set CYREG_PRT3_PS_ALIAS, 0x40005093\r
+.set CYDEV_IO_PS_PRT4_BASE, 0x40005094\r
+.set CYDEV_IO_PS_PRT4_SIZE, 0x00000001\r
+.set CYREG_PRT4_PS_ALIAS, 0x40005094\r
+.set CYDEV_IO_PS_PRT5_BASE, 0x40005095\r
+.set CYDEV_IO_PS_PRT5_SIZE, 0x00000001\r
+.set CYREG_PRT5_PS_ALIAS, 0x40005095\r
+.set CYDEV_IO_PS_PRT6_BASE, 0x40005096\r
+.set CYDEV_IO_PS_PRT6_SIZE, 0x00000001\r
+.set CYREG_PRT6_PS_ALIAS, 0x40005096\r
+.set CYDEV_IO_PS_PRT12_BASE, 0x4000509c\r
+.set CYDEV_IO_PS_PRT12_SIZE, 0x00000001\r
+.set CYREG_PRT12_PS_ALIAS, 0x4000509c\r
+.set CYDEV_IO_PS_PRT15_BASE, 0x4000509f\r
+.set CYDEV_IO_PS_PRT15_SIZE, 0x00000001\r
+.set CYREG_PRT15_PS15_ALIAS, 0x4000509f\r
+.set CYDEV_IO_PRT_BASE, 0x40005100\r
+.set CYDEV_IO_PRT_SIZE, 0x00000100\r
+.set CYDEV_IO_PRT_PRT0_BASE, 0x40005100\r
+.set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010\r
+.set CYREG_PRT0_DR, 0x40005100\r
+.set CYREG_PRT0_PS, 0x40005101\r
+.set CYREG_PRT0_DM0, 0x40005102\r
+.set CYREG_PRT0_DM1, 0x40005103\r
+.set CYREG_PRT0_DM2, 0x40005104\r
+.set CYREG_PRT0_SLW, 0x40005105\r
+.set CYREG_PRT0_BYP, 0x40005106\r
+.set CYREG_PRT0_BIE, 0x40005107\r
+.set CYREG_PRT0_INP_DIS, 0x40005108\r
+.set CYREG_PRT0_CTL, 0x40005109\r
+.set CYREG_PRT0_PRT, 0x4000510a\r
+.set CYREG_PRT0_BIT_MASK, 0x4000510b\r
+.set CYREG_PRT0_AMUX, 0x4000510c\r
+.set CYREG_PRT0_AG, 0x4000510d\r
+.set CYREG_PRT0_LCD_COM_SEG, 0x4000510e\r
+.set CYREG_PRT0_LCD_EN, 0x4000510f\r
+.set CYDEV_IO_PRT_PRT1_BASE, 0x40005110\r
+.set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010\r
+.set CYREG_PRT1_DR, 0x40005110\r
+.set CYREG_PRT1_PS, 0x40005111\r
+.set CYREG_PRT1_DM0, 0x40005112\r
+.set CYREG_PRT1_DM1, 0x40005113\r
+.set CYREG_PRT1_DM2, 0x40005114\r
+.set CYREG_PRT1_SLW, 0x40005115\r
+.set CYREG_PRT1_BYP, 0x40005116\r
+.set CYREG_PRT1_BIE, 0x40005117\r
+.set CYREG_PRT1_INP_DIS, 0x40005118\r
+.set CYREG_PRT1_CTL, 0x40005119\r
+.set CYREG_PRT1_PRT, 0x4000511a\r
+.set CYREG_PRT1_BIT_MASK, 0x4000511b\r
+.set CYREG_PRT1_AMUX, 0x4000511c\r
+.set CYREG_PRT1_AG, 0x4000511d\r
+.set CYREG_PRT1_LCD_COM_SEG, 0x4000511e\r
+.set CYREG_PRT1_LCD_EN, 0x4000511f\r
+.set CYDEV_IO_PRT_PRT2_BASE, 0x40005120\r
+.set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010\r
+.set CYREG_PRT2_DR, 0x40005120\r
+.set CYREG_PRT2_PS, 0x40005121\r
+.set CYREG_PRT2_DM0, 0x40005122\r
+.set CYREG_PRT2_DM1, 0x40005123\r
+.set CYREG_PRT2_DM2, 0x40005124\r
+.set CYREG_PRT2_SLW, 0x40005125\r
+.set CYREG_PRT2_BYP, 0x40005126\r
+.set CYREG_PRT2_BIE, 0x40005127\r
+.set CYREG_PRT2_INP_DIS, 0x40005128\r
+.set CYREG_PRT2_CTL, 0x40005129\r
+.set CYREG_PRT2_PRT, 0x4000512a\r
+.set CYREG_PRT2_BIT_MASK, 0x4000512b\r
+.set CYREG_PRT2_AMUX, 0x4000512c\r
+.set CYREG_PRT2_AG, 0x4000512d\r
+.set CYREG_PRT2_LCD_COM_SEG, 0x4000512e\r
+.set CYREG_PRT2_LCD_EN, 0x4000512f\r
+.set CYDEV_IO_PRT_PRT3_BASE, 0x40005130\r
+.set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010\r
+.set CYREG_PRT3_DR, 0x40005130\r
+.set CYREG_PRT3_PS, 0x40005131\r
+.set CYREG_PRT3_DM0, 0x40005132\r
+.set CYREG_PRT3_DM1, 0x40005133\r
+.set CYREG_PRT3_DM2, 0x40005134\r
+.set CYREG_PRT3_SLW, 0x40005135\r
+.set CYREG_PRT3_BYP, 0x40005136\r
+.set CYREG_PRT3_BIE, 0x40005137\r
+.set CYREG_PRT3_INP_DIS, 0x40005138\r
+.set CYREG_PRT3_CTL, 0x40005139\r
+.set CYREG_PRT3_PRT, 0x4000513a\r
+.set CYREG_PRT3_BIT_MASK, 0x4000513b\r
+.set CYREG_PRT3_AMUX, 0x4000513c\r
+.set CYREG_PRT3_AG, 0x4000513d\r
+.set CYREG_PRT3_LCD_COM_SEG, 0x4000513e\r
+.set CYREG_PRT3_LCD_EN, 0x4000513f\r
+.set CYDEV_IO_PRT_PRT4_BASE, 0x40005140\r
+.set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010\r
+.set CYREG_PRT4_DR, 0x40005140\r
+.set CYREG_PRT4_PS, 0x40005141\r
+.set CYREG_PRT4_DM0, 0x40005142\r
+.set CYREG_PRT4_DM1, 0x40005143\r
+.set CYREG_PRT4_DM2, 0x40005144\r
+.set CYREG_PRT4_SLW, 0x40005145\r
+.set CYREG_PRT4_BYP, 0x40005146\r
+.set CYREG_PRT4_BIE, 0x40005147\r
+.set CYREG_PRT4_INP_DIS, 0x40005148\r
+.set CYREG_PRT4_CTL, 0x40005149\r
+.set CYREG_PRT4_PRT, 0x4000514a\r
+.set CYREG_PRT4_BIT_MASK, 0x4000514b\r
+.set CYREG_PRT4_AMUX, 0x4000514c\r
+.set CYREG_PRT4_AG, 0x4000514d\r
+.set CYREG_PRT4_LCD_COM_SEG, 0x4000514e\r
+.set CYREG_PRT4_LCD_EN, 0x4000514f\r
+.set CYDEV_IO_PRT_PRT5_BASE, 0x40005150\r
+.set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010\r
+.set CYREG_PRT5_DR, 0x40005150\r
+.set CYREG_PRT5_PS, 0x40005151\r
+.set CYREG_PRT5_DM0, 0x40005152\r
+.set CYREG_PRT5_DM1, 0x40005153\r
+.set CYREG_PRT5_DM2, 0x40005154\r
+.set CYREG_PRT5_SLW, 0x40005155\r
+.set CYREG_PRT5_BYP, 0x40005156\r
+.set CYREG_PRT5_BIE, 0x40005157\r
+.set CYREG_PRT5_INP_DIS, 0x40005158\r
+.set CYREG_PRT5_CTL, 0x40005159\r
+.set CYREG_PRT5_PRT, 0x4000515a\r
+.set CYREG_PRT5_BIT_MASK, 0x4000515b\r
+.set CYREG_PRT5_AMUX, 0x4000515c\r
+.set CYREG_PRT5_AG, 0x4000515d\r
+.set CYREG_PRT5_LCD_COM_SEG, 0x4000515e\r
+.set CYREG_PRT5_LCD_EN, 0x4000515f\r
+.set CYDEV_IO_PRT_PRT6_BASE, 0x40005160\r
+.set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010\r
+.set CYREG_PRT6_DR, 0x40005160\r
+.set CYREG_PRT6_PS, 0x40005161\r
+.set CYREG_PRT6_DM0, 0x40005162\r
+.set CYREG_PRT6_DM1, 0x40005163\r
+.set CYREG_PRT6_DM2, 0x40005164\r
+.set CYREG_PRT6_SLW, 0x40005165\r
+.set CYREG_PRT6_BYP, 0x40005166\r
+.set CYREG_PRT6_BIE, 0x40005167\r
+.set CYREG_PRT6_INP_DIS, 0x40005168\r
+.set CYREG_PRT6_CTL, 0x40005169\r
+.set CYREG_PRT6_PRT, 0x4000516a\r
+.set CYREG_PRT6_BIT_MASK, 0x4000516b\r
+.set CYREG_PRT6_AMUX, 0x4000516c\r
+.set CYREG_PRT6_AG, 0x4000516d\r
+.set CYREG_PRT6_LCD_COM_SEG, 0x4000516e\r
+.set CYREG_PRT6_LCD_EN, 0x4000516f\r
+.set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0\r
+.set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010\r
+.set CYREG_PRT12_DR, 0x400051c0\r
+.set CYREG_PRT12_PS, 0x400051c1\r
+.set CYREG_PRT12_DM0, 0x400051c2\r
+.set CYREG_PRT12_DM1, 0x400051c3\r
+.set CYREG_PRT12_DM2, 0x400051c4\r
+.set CYREG_PRT12_SLW, 0x400051c5\r
+.set CYREG_PRT12_BYP, 0x400051c6\r
+.set CYREG_PRT12_BIE, 0x400051c7\r
+.set CYREG_PRT12_INP_DIS, 0x400051c8\r
+.set CYREG_PRT12_SIO_HYST_EN, 0x400051c9\r
+.set CYREG_PRT12_PRT, 0x400051ca\r
+.set CYREG_PRT12_BIT_MASK, 0x400051cb\r
+.set CYREG_PRT12_SIO_REG_HIFREQ, 0x400051cc\r
+.set CYREG_PRT12_AG, 0x400051cd\r
+.set CYREG_PRT12_SIO_CFG, 0x400051ce\r
+.set CYREG_PRT12_SIO_DIFF, 0x400051cf\r
+.set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0\r
+.set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010\r
+.set CYREG_PRT15_DR, 0x400051f0\r
+.set CYREG_PRT15_PS, 0x400051f1\r
+.set CYREG_PRT15_DM0, 0x400051f2\r
+.set CYREG_PRT15_DM1, 0x400051f3\r
+.set CYREG_PRT15_DM2, 0x400051f4\r
+.set CYREG_PRT15_SLW, 0x400051f5\r
+.set CYREG_PRT15_BYP, 0x400051f6\r
+.set CYREG_PRT15_BIE, 0x400051f7\r
+.set CYREG_PRT15_INP_DIS, 0x400051f8\r
+.set CYREG_PRT15_CTL, 0x400051f9\r
+.set CYREG_PRT15_PRT, 0x400051fa\r
+.set CYREG_PRT15_BIT_MASK, 0x400051fb\r
+.set CYREG_PRT15_AMUX, 0x400051fc\r
+.set CYREG_PRT15_AG, 0x400051fd\r
+.set CYREG_PRT15_LCD_COM_SEG, 0x400051fe\r
+.set CYREG_PRT15_LCD_EN, 0x400051ff\r
+.set CYDEV_PRTDSI_BASE, 0x40005200\r
+.set CYDEV_PRTDSI_SIZE, 0x0000007f\r
+.set CYDEV_PRTDSI_PRT0_BASE, 0x40005200\r
+.set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007\r
+.set CYREG_PRT0_OUT_SEL0, 0x40005200\r
+.set CYREG_PRT0_OUT_SEL1, 0x40005201\r
+.set CYREG_PRT0_OE_SEL0, 0x40005202\r
+.set CYREG_PRT0_OE_SEL1, 0x40005203\r
+.set CYREG_PRT0_DBL_SYNC_IN, 0x40005204\r
+.set CYREG_PRT0_SYNC_OUT, 0x40005205\r
+.set CYREG_PRT0_CAPS_SEL, 0x40005206\r
+.set CYDEV_PRTDSI_PRT1_BASE, 0x40005208\r
+.set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007\r
+.set CYREG_PRT1_OUT_SEL0, 0x40005208\r
+.set CYREG_PRT1_OUT_SEL1, 0x40005209\r
+.set CYREG_PRT1_OE_SEL0, 0x4000520a\r
+.set CYREG_PRT1_OE_SEL1, 0x4000520b\r
+.set CYREG_PRT1_DBL_SYNC_IN, 0x4000520c\r
+.set CYREG_PRT1_SYNC_OUT, 0x4000520d\r
+.set CYREG_PRT1_CAPS_SEL, 0x4000520e\r
+.set CYDEV_PRTDSI_PRT2_BASE, 0x40005210\r
+.set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007\r
+.set CYREG_PRT2_OUT_SEL0, 0x40005210\r
+.set CYREG_PRT2_OUT_SEL1, 0x40005211\r
+.set CYREG_PRT2_OE_SEL0, 0x40005212\r
+.set CYREG_PRT2_OE_SEL1, 0x40005213\r
+.set CYREG_PRT2_DBL_SYNC_IN, 0x40005214\r
+.set CYREG_PRT2_SYNC_OUT, 0x40005215\r
+.set CYREG_PRT2_CAPS_SEL, 0x40005216\r
+.set CYDEV_PRTDSI_PRT3_BASE, 0x40005218\r
+.set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007\r
+.set CYREG_PRT3_OUT_SEL0, 0x40005218\r
+.set CYREG_PRT3_OUT_SEL1, 0x40005219\r
+.set CYREG_PRT3_OE_SEL0, 0x4000521a\r
+.set CYREG_PRT3_OE_SEL1, 0x4000521b\r
+.set CYREG_PRT3_DBL_SYNC_IN, 0x4000521c\r
+.set CYREG_PRT3_SYNC_OUT, 0x4000521d\r
+.set CYREG_PRT3_CAPS_SEL, 0x4000521e\r
+.set CYDEV_PRTDSI_PRT4_BASE, 0x40005220\r
+.set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007\r
+.set CYREG_PRT4_OUT_SEL0, 0x40005220\r
+.set CYREG_PRT4_OUT_SEL1, 0x40005221\r
+.set CYREG_PRT4_OE_SEL0, 0x40005222\r
+.set CYREG_PRT4_OE_SEL1, 0x40005223\r
+.set CYREG_PRT4_DBL_SYNC_IN, 0x40005224\r
+.set CYREG_PRT4_SYNC_OUT, 0x40005225\r
+.set CYREG_PRT4_CAPS_SEL, 0x40005226\r
+.set CYDEV_PRTDSI_PRT5_BASE, 0x40005228\r
+.set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007\r
+.set CYREG_PRT5_OUT_SEL0, 0x40005228\r
+.set CYREG_PRT5_OUT_SEL1, 0x40005229\r
+.set CYREG_PRT5_OE_SEL0, 0x4000522a\r
+.set CYREG_PRT5_OE_SEL1, 0x4000522b\r
+.set CYREG_PRT5_DBL_SYNC_IN, 0x4000522c\r
+.set CYREG_PRT5_SYNC_OUT, 0x4000522d\r
+.set CYREG_PRT5_CAPS_SEL, 0x4000522e\r
+.set CYDEV_PRTDSI_PRT6_BASE, 0x40005230\r
+.set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007\r
+.set CYREG_PRT6_OUT_SEL0, 0x40005230\r
+.set CYREG_PRT6_OUT_SEL1, 0x40005231\r
+.set CYREG_PRT6_OE_SEL0, 0x40005232\r
+.set CYREG_PRT6_OE_SEL1, 0x40005233\r
+.set CYREG_PRT6_DBL_SYNC_IN, 0x40005234\r
+.set CYREG_PRT6_SYNC_OUT, 0x40005235\r
+.set CYREG_PRT6_CAPS_SEL, 0x40005236\r
+.set CYDEV_PRTDSI_PRT12_BASE, 0x40005260\r
+.set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006\r
+.set CYREG_PRT12_OUT_SEL0, 0x40005260\r
+.set CYREG_PRT12_OUT_SEL1, 0x40005261\r
+.set CYREG_PRT12_OE_SEL0, 0x40005262\r
+.set CYREG_PRT12_OE_SEL1, 0x40005263\r
+.set CYREG_PRT12_DBL_SYNC_IN, 0x40005264\r
+.set CYREG_PRT12_SYNC_OUT, 0x40005265\r
+.set CYDEV_PRTDSI_PRT15_BASE, 0x40005278\r
+.set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007\r
+.set CYREG_PRT15_OUT_SEL0, 0x40005278\r
+.set CYREG_PRT15_OUT_SEL1, 0x40005279\r
+.set CYREG_PRT15_OE_SEL0, 0x4000527a\r
+.set CYREG_PRT15_OE_SEL1, 0x4000527b\r
+.set CYREG_PRT15_DBL_SYNC_IN, 0x4000527c\r
+.set CYREG_PRT15_SYNC_OUT, 0x4000527d\r
+.set CYREG_PRT15_CAPS_SEL, 0x4000527e\r
+.set CYDEV_EMIF_BASE, 0x40005400\r
+.set CYDEV_EMIF_SIZE, 0x00000007\r
+.set CYREG_EMIF_NO_UDB, 0x40005400\r
+.set CYREG_EMIF_RP_WAIT_STATES, 0x40005401\r
+.set CYREG_EMIF_MEM_DWN, 0x40005402\r
+.set CYREG_EMIF_MEMCLK_DIV, 0x40005403\r
+.set CYREG_EMIF_CLOCK_EN, 0x40005404\r
+.set CYREG_EMIF_EM_TYPE, 0x40005405\r
+.set CYREG_EMIF_WP_WAIT_STATES, 0x40005406\r
+.set CYDEV_ANAIF_BASE, 0x40005800\r
+.set CYDEV_ANAIF_SIZE, 0x000003a9\r
+.set CYDEV_ANAIF_CFG_BASE, 0x40005800\r
+.set CYDEV_ANAIF_CFG_SIZE, 0x0000010f\r
+.set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800\r
+.set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003\r
+.set CYREG_SC0_CR0, 0x40005800\r
+.set CYREG_SC0_CR1, 0x40005801\r
+.set CYREG_SC0_CR2, 0x40005802\r
+.set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804\r
+.set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003\r
+.set CYREG_SC1_CR0, 0x40005804\r
+.set CYREG_SC1_CR1, 0x40005805\r
+.set CYREG_SC1_CR2, 0x40005806\r
+.set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808\r
+.set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003\r
+.set CYREG_SC2_CR0, 0x40005808\r
+.set CYREG_SC2_CR1, 0x40005809\r
+.set CYREG_SC2_CR2, 0x4000580a\r
+.set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c\r
+.set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003\r
+.set CYREG_SC3_CR0, 0x4000580c\r
+.set CYREG_SC3_CR1, 0x4000580d\r
+.set CYREG_SC3_CR2, 0x4000580e\r
+.set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820\r
+.set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003\r
+.set CYREG_DAC0_CR0, 0x40005820\r
+.set CYREG_DAC0_CR1, 0x40005821\r
+.set CYREG_DAC0_TST, 0x40005822\r
+.set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824\r
+.set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003\r
+.set CYREG_DAC1_CR0, 0x40005824\r
+.set CYREG_DAC1_CR1, 0x40005825\r
+.set CYREG_DAC1_TST, 0x40005826\r
+.set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828\r
+.set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003\r
+.set CYREG_DAC2_CR0, 0x40005828\r
+.set CYREG_DAC2_CR1, 0x40005829\r
+.set CYREG_DAC2_TST, 0x4000582a\r
+.set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c\r
+.set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003\r
+.set CYREG_DAC3_CR0, 0x4000582c\r
+.set CYREG_DAC3_CR1, 0x4000582d\r
+.set CYREG_DAC3_TST, 0x4000582e\r
+.set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840\r
+.set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001\r
+.set CYREG_CMP0_CR, 0x40005840\r
+.set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841\r
+.set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001\r
+.set CYREG_CMP1_CR, 0x40005841\r
+.set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842\r
+.set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001\r
+.set CYREG_CMP2_CR, 0x40005842\r
+.set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843\r
+.set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001\r
+.set CYREG_CMP3_CR, 0x40005843\r
+.set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848\r
+.set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002\r
+.set CYREG_LUT0_CR, 0x40005848\r
+.set CYREG_LUT0_MX, 0x40005849\r
+.set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a\r
+.set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002\r
+.set CYREG_LUT1_CR, 0x4000584a\r
+.set CYREG_LUT1_MX, 0x4000584b\r
+.set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c\r
+.set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002\r
+.set CYREG_LUT2_CR, 0x4000584c\r
+.set CYREG_LUT2_MX, 0x4000584d\r
+.set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e\r
+.set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002\r
+.set CYREG_LUT3_CR, 0x4000584e\r
+.set CYREG_LUT3_MX, 0x4000584f\r
+.set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858\r
+.set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002\r
+.set CYREG_OPAMP0_CR, 0x40005858\r
+.set CYREG_OPAMP0_RSVD, 0x40005859\r
+.set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a\r
+.set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002\r
+.set CYREG_OPAMP1_CR, 0x4000585a\r
+.set CYREG_OPAMP1_RSVD, 0x4000585b\r
+.set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c\r
+.set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002\r
+.set CYREG_OPAMP2_CR, 0x4000585c\r
+.set CYREG_OPAMP2_RSVD, 0x4000585d\r
+.set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e\r
+.set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002\r
+.set CYREG_OPAMP3_CR, 0x4000585e\r
+.set CYREG_OPAMP3_RSVD, 0x4000585f\r
+.set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868\r
+.set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002\r
+.set CYREG_LCDDAC_CR0, 0x40005868\r
+.set CYREG_LCDDAC_CR1, 0x40005869\r
+.set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a\r
+.set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001\r
+.set CYREG_LCDDRV_CR, 0x4000586a\r
+.set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b\r
+.set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001\r
+.set CYREG_LCDTMR_CFG, 0x4000586b\r
+.set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c\r
+.set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004\r
+.set CYREG_BG_CR0, 0x4000586c\r
+.set CYREG_BG_RSVD, 0x4000586d\r
+.set CYREG_BG_DFT0, 0x4000586e\r
+.set CYREG_BG_DFT1, 0x4000586f\r
+.set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870\r
+.set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002\r
+.set CYREG_CAPSL_CFG0, 0x40005870\r
+.set CYREG_CAPSL_CFG1, 0x40005871\r
+.set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872\r
+.set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002\r
+.set CYREG_CAPSR_CFG0, 0x40005872\r
+.set CYREG_CAPSR_CFG1, 0x40005873\r
+.set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876\r
+.set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002\r
+.set CYREG_PUMP_CR0, 0x40005876\r
+.set CYREG_PUMP_CR1, 0x40005877\r
+.set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878\r
+.set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002\r
+.set CYREG_LPF0_CR0, 0x40005878\r
+.set CYREG_LPF0_RSVD, 0x40005879\r
+.set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a\r
+.set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002\r
+.set CYREG_LPF1_CR0, 0x4000587a\r
+.set CYREG_LPF1_RSVD, 0x4000587b\r
+.set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c\r
+.set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001\r
+.set CYREG_ANAIF_CFG_MISC_CR0, 0x4000587c\r
+.set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880\r
+.set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020\r
+.set CYREG_DSM0_CR0, 0x40005880\r
+.set CYREG_DSM0_CR1, 0x40005881\r
+.set CYREG_DSM0_CR2, 0x40005882\r
+.set CYREG_DSM0_CR3, 0x40005883\r
+.set CYREG_DSM0_CR4, 0x40005884\r
+.set CYREG_DSM0_CR5, 0x40005885\r
+.set CYREG_DSM0_CR6, 0x40005886\r
+.set CYREG_DSM0_CR7, 0x40005887\r
+.set CYREG_DSM0_CR8, 0x40005888\r
+.set CYREG_DSM0_CR9, 0x40005889\r
+.set CYREG_DSM0_CR10, 0x4000588a\r
+.set CYREG_DSM0_CR11, 0x4000588b\r
+.set CYREG_DSM0_CR12, 0x4000588c\r
+.set CYREG_DSM0_CR13, 0x4000588d\r
+.set CYREG_DSM0_CR14, 0x4000588e\r
+.set CYREG_DSM0_CR15, 0x4000588f\r
+.set CYREG_DSM0_CR16, 0x40005890\r
+.set CYREG_DSM0_CR17, 0x40005891\r
+.set CYREG_DSM0_REF0, 0x40005892\r
+.set CYREG_DSM0_REF1, 0x40005893\r
+.set CYREG_DSM0_REF2, 0x40005894\r
+.set CYREG_DSM0_REF3, 0x40005895\r
+.set CYREG_DSM0_DEM0, 0x40005896\r
+.set CYREG_DSM0_DEM1, 0x40005897\r
+.set CYREG_DSM0_TST0, 0x40005898\r
+.set CYREG_DSM0_TST1, 0x40005899\r
+.set CYREG_DSM0_BUF0, 0x4000589a\r
+.set CYREG_DSM0_BUF1, 0x4000589b\r
+.set CYREG_DSM0_BUF2, 0x4000589c\r
+.set CYREG_DSM0_BUF3, 0x4000589d\r
+.set CYREG_DSM0_MISC, 0x4000589e\r
+.set CYREG_DSM0_RSVD1, 0x4000589f\r
+.set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900\r
+.set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007\r
+.set CYREG_SAR0_CSR0, 0x40005900\r
+.set CYREG_SAR0_CSR1, 0x40005901\r
+.set CYREG_SAR0_CSR2, 0x40005902\r
+.set CYREG_SAR0_CSR3, 0x40005903\r
+.set CYREG_SAR0_CSR4, 0x40005904\r
+.set CYREG_SAR0_CSR5, 0x40005905\r
+.set CYREG_SAR0_CSR6, 0x40005906\r
+.set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908\r
+.set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007\r
+.set CYREG_SAR1_CSR0, 0x40005908\r
+.set CYREG_SAR1_CSR1, 0x40005909\r
+.set CYREG_SAR1_CSR2, 0x4000590a\r
+.set CYREG_SAR1_CSR3, 0x4000590b\r
+.set CYREG_SAR1_CSR4, 0x4000590c\r
+.set CYREG_SAR1_CSR5, 0x4000590d\r
+.set CYREG_SAR1_CSR6, 0x4000590e\r
+.set CYDEV_ANAIF_RT_BASE, 0x40005a00\r
+.set CYDEV_ANAIF_RT_SIZE, 0x00000162\r
+.set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00\r
+.set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d\r
+.set CYREG_SC0_SW0, 0x40005a00\r
+.set CYREG_SC0_SW2, 0x40005a02\r
+.set CYREG_SC0_SW3, 0x40005a03\r
+.set CYREG_SC0_SW4, 0x40005a04\r
+.set CYREG_SC0_SW6, 0x40005a06\r
+.set CYREG_SC0_SW7, 0x40005a07\r
+.set CYREG_SC0_SW8, 0x40005a08\r
+.set CYREG_SC0_SW10, 0x40005a0a\r
+.set CYREG_SC0_CLK, 0x40005a0b\r
+.set CYREG_SC0_BST, 0x40005a0c\r
+.set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10\r
+.set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d\r
+.set CYREG_SC1_SW0, 0x40005a10\r
+.set CYREG_SC1_SW2, 0x40005a12\r
+.set CYREG_SC1_SW3, 0x40005a13\r
+.set CYREG_SC1_SW4, 0x40005a14\r
+.set CYREG_SC1_SW6, 0x40005a16\r
+.set CYREG_SC1_SW7, 0x40005a17\r
+.set CYREG_SC1_SW8, 0x40005a18\r
+.set CYREG_SC1_SW10, 0x40005a1a\r
+.set CYREG_SC1_CLK, 0x40005a1b\r
+.set CYREG_SC1_BST, 0x40005a1c\r
+.set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20\r
+.set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d\r
+.set CYREG_SC2_SW0, 0x40005a20\r
+.set CYREG_SC2_SW2, 0x40005a22\r
+.set CYREG_SC2_SW3, 0x40005a23\r
+.set CYREG_SC2_SW4, 0x40005a24\r
+.set CYREG_SC2_SW6, 0x40005a26\r
+.set CYREG_SC2_SW7, 0x40005a27\r
+.set CYREG_SC2_SW8, 0x40005a28\r
+.set CYREG_SC2_SW10, 0x40005a2a\r
+.set CYREG_SC2_CLK, 0x40005a2b\r
+.set CYREG_SC2_BST, 0x40005a2c\r
+.set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30\r
+.set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d\r
+.set CYREG_SC3_SW0, 0x40005a30\r
+.set CYREG_SC3_SW2, 0x40005a32\r
+.set CYREG_SC3_SW3, 0x40005a33\r
+.set CYREG_SC3_SW4, 0x40005a34\r
+.set CYREG_SC3_SW6, 0x40005a36\r
+.set CYREG_SC3_SW7, 0x40005a37\r
+.set CYREG_SC3_SW8, 0x40005a38\r
+.set CYREG_SC3_SW10, 0x40005a3a\r
+.set CYREG_SC3_CLK, 0x40005a3b\r
+.set CYREG_SC3_BST, 0x40005a3c\r
+.set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80\r
+.set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008\r
+.set CYREG_DAC0_SW0, 0x40005a80\r
+.set CYREG_DAC0_SW2, 0x40005a82\r
+.set CYREG_DAC0_SW3, 0x40005a83\r
+.set CYREG_DAC0_SW4, 0x40005a84\r
+.set CYREG_DAC0_STROBE, 0x40005a87\r
+.set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88\r
+.set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008\r
+.set CYREG_DAC1_SW0, 0x40005a88\r
+.set CYREG_DAC1_SW2, 0x40005a8a\r
+.set CYREG_DAC1_SW3, 0x40005a8b\r
+.set CYREG_DAC1_SW4, 0x40005a8c\r
+.set CYREG_DAC1_STROBE, 0x40005a8f\r
+.set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90\r
+.set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008\r
+.set CYREG_DAC2_SW0, 0x40005a90\r
+.set CYREG_DAC2_SW2, 0x40005a92\r
+.set CYREG_DAC2_SW3, 0x40005a93\r
+.set CYREG_DAC2_SW4, 0x40005a94\r
+.set CYREG_DAC2_STROBE, 0x40005a97\r
+.set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98\r
+.set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008\r
+.set CYREG_DAC3_SW0, 0x40005a98\r
+.set CYREG_DAC3_SW2, 0x40005a9a\r
+.set CYREG_DAC3_SW3, 0x40005a9b\r
+.set CYREG_DAC3_SW4, 0x40005a9c\r
+.set CYREG_DAC3_STROBE, 0x40005a9f\r
+.set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0\r
+.set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008\r
+.set CYREG_CMP0_SW0, 0x40005ac0\r
+.set CYREG_CMP0_SW2, 0x40005ac2\r
+.set CYREG_CMP0_SW3, 0x40005ac3\r
+.set CYREG_CMP0_SW4, 0x40005ac4\r
+.set CYREG_CMP0_SW6, 0x40005ac6\r
+.set CYREG_CMP0_CLK, 0x40005ac7\r
+.set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8\r
+.set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008\r
+.set CYREG_CMP1_SW0, 0x40005ac8\r
+.set CYREG_CMP1_SW2, 0x40005aca\r
+.set CYREG_CMP1_SW3, 0x40005acb\r
+.set CYREG_CMP1_SW4, 0x40005acc\r
+.set CYREG_CMP1_SW6, 0x40005ace\r
+.set CYREG_CMP1_CLK, 0x40005acf\r
+.set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0\r
+.set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008\r
+.set CYREG_CMP2_SW0, 0x40005ad0\r
+.set CYREG_CMP2_SW2, 0x40005ad2\r
+.set CYREG_CMP2_SW3, 0x40005ad3\r
+.set CYREG_CMP2_SW4, 0x40005ad4\r
+.set CYREG_CMP2_SW6, 0x40005ad6\r
+.set CYREG_CMP2_CLK, 0x40005ad7\r
+.set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8\r
+.set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008\r
+.set CYREG_CMP3_SW0, 0x40005ad8\r
+.set CYREG_CMP3_SW2, 0x40005ada\r
+.set CYREG_CMP3_SW3, 0x40005adb\r
+.set CYREG_CMP3_SW4, 0x40005adc\r
+.set CYREG_CMP3_SW6, 0x40005ade\r
+.set CYREG_CMP3_CLK, 0x40005adf\r
+.set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00\r
+.set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008\r
+.set CYREG_DSM0_SW0, 0x40005b00\r
+.set CYREG_DSM0_SW2, 0x40005b02\r
+.set CYREG_DSM0_SW3, 0x40005b03\r
+.set CYREG_DSM0_SW4, 0x40005b04\r
+.set CYREG_DSM0_SW6, 0x40005b06\r
+.set CYREG_DSM0_CLK, 0x40005b07\r
+.set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20\r
+.set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008\r
+.set CYREG_SAR0_SW0, 0x40005b20\r
+.set CYREG_SAR0_SW2, 0x40005b22\r
+.set CYREG_SAR0_SW3, 0x40005b23\r
+.set CYREG_SAR0_SW4, 0x40005b24\r
+.set CYREG_SAR0_SW6, 0x40005b26\r
+.set CYREG_SAR0_CLK, 0x40005b27\r
+.set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28\r
+.set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008\r
+.set CYREG_SAR1_SW0, 0x40005b28\r
+.set CYREG_SAR1_SW2, 0x40005b2a\r
+.set CYREG_SAR1_SW3, 0x40005b2b\r
+.set CYREG_SAR1_SW4, 0x40005b2c\r
+.set CYREG_SAR1_SW6, 0x40005b2e\r
+.set CYREG_SAR1_CLK, 0x40005b2f\r
+.set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40\r
+.set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002\r
+.set CYREG_OPAMP0_MX, 0x40005b40\r
+.set CYREG_OPAMP0_SW, 0x40005b41\r
+.set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42\r
+.set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002\r
+.set CYREG_OPAMP1_MX, 0x40005b42\r
+.set CYREG_OPAMP1_SW, 0x40005b43\r
+.set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44\r
+.set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002\r
+.set CYREG_OPAMP2_MX, 0x40005b44\r
+.set CYREG_OPAMP2_SW, 0x40005b45\r
+.set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46\r
+.set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002\r
+.set CYREG_OPAMP3_MX, 0x40005b46\r
+.set CYREG_OPAMP3_SW, 0x40005b47\r
+.set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50\r
+.set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005\r
+.set CYREG_LCDDAC_SW0, 0x40005b50\r
+.set CYREG_LCDDAC_SW1, 0x40005b51\r
+.set CYREG_LCDDAC_SW2, 0x40005b52\r
+.set CYREG_LCDDAC_SW3, 0x40005b53\r
+.set CYREG_LCDDAC_SW4, 0x40005b54\r
+.set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56\r
+.set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001\r
+.set CYREG_SC_MISC, 0x40005b56\r
+.set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58\r
+.set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004\r
+.set CYREG_BUS_SW0, 0x40005b58\r
+.set CYREG_BUS_SW2, 0x40005b5a\r
+.set CYREG_BUS_SW3, 0x40005b5b\r
+.set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c\r
+.set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006\r
+.set CYREG_DFT_CR0, 0x40005b5c\r
+.set CYREG_DFT_CR1, 0x40005b5d\r
+.set CYREG_DFT_CR2, 0x40005b5e\r
+.set CYREG_DFT_CR3, 0x40005b5f\r
+.set CYREG_DFT_CR4, 0x40005b60\r
+.set CYREG_DFT_CR5, 0x40005b61\r
+.set CYDEV_ANAIF_WRK_BASE, 0x40005b80\r
+.set CYDEV_ANAIF_WRK_SIZE, 0x00000029\r
+.set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80\r
+.set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001\r
+.set CYREG_DAC0_D, 0x40005b80\r
+.set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81\r
+.set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001\r
+.set CYREG_DAC1_D, 0x40005b81\r
+.set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82\r
+.set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001\r
+.set CYREG_DAC2_D, 0x40005b82\r
+.set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83\r
+.set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001\r
+.set CYREG_DAC3_D, 0x40005b83\r
+.set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88\r
+.set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002\r
+.set CYREG_DSM0_OUT0, 0x40005b88\r
+.set CYREG_DSM0_OUT1, 0x40005b89\r
+.set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90\r
+.set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005\r
+.set CYREG_LUT_SR, 0x40005b90\r
+.set CYREG_LUT_WRK1, 0x40005b91\r
+.set CYREG_LUT_MSK, 0x40005b92\r
+.set CYREG_LUT_CLK, 0x40005b93\r
+.set CYREG_LUT_CPTR, 0x40005b94\r
+.set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96\r
+.set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002\r
+.set CYREG_CMP_WRK, 0x40005b96\r
+.set CYREG_CMP_TST, 0x40005b97\r
+.set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98\r
+.set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005\r
+.set CYREG_SC_SR, 0x40005b98\r
+.set CYREG_SC_WRK1, 0x40005b99\r
+.set CYREG_SC_MSK, 0x40005b9a\r
+.set CYREG_SC_CMPINV, 0x40005b9b\r
+.set CYREG_SC_CPTR, 0x40005b9c\r
+.set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0\r
+.set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002\r
+.set CYREG_SAR0_WRK0, 0x40005ba0\r
+.set CYREG_SAR0_WRK1, 0x40005ba1\r
+.set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2\r
+.set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002\r
+.set CYREG_SAR1_WRK0, 0x40005ba2\r
+.set CYREG_SAR1_WRK1, 0x40005ba3\r
+.set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8\r
+.set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001\r
+.set CYREG_ANAIF_WRK_SARS_SOF, 0x40005ba8\r
+.set CYDEV_USB_BASE, 0x40006000\r
+.set CYDEV_USB_SIZE, 0x00000300\r
+.set CYREG_USB_EP0_DR0, 0x40006000\r
+.set CYREG_USB_EP0_DR1, 0x40006001\r
+.set CYREG_USB_EP0_DR2, 0x40006002\r
+.set CYREG_USB_EP0_DR3, 0x40006003\r
+.set CYREG_USB_EP0_DR4, 0x40006004\r
+.set CYREG_USB_EP0_DR5, 0x40006005\r
+.set CYREG_USB_EP0_DR6, 0x40006006\r
+.set CYREG_USB_EP0_DR7, 0x40006007\r
+.set CYREG_USB_CR0, 0x40006008\r
+.set CYREG_USB_CR1, 0x40006009\r
+.set CYREG_USB_SIE_EP_INT_EN, 0x4000600a\r
+.set CYREG_USB_SIE_EP_INT_SR, 0x4000600b\r
+.set CYDEV_USB_SIE_EP1_BASE, 0x4000600c\r
+.set CYDEV_USB_SIE_EP1_SIZE, 0x00000003\r
+.set CYREG_USB_SIE_EP1_CNT0, 0x4000600c\r
+.set CYREG_USB_SIE_EP1_CNT1, 0x4000600d\r
+.set CYREG_USB_SIE_EP1_CR0, 0x4000600e\r
+.set CYREG_USB_USBIO_CR0, 0x40006010\r
+.set CYREG_USB_USBIO_CR1, 0x40006012\r
+.set CYREG_USB_DYN_RECONFIG, 0x40006014\r
+.set CYREG_USB_SOF0, 0x40006018\r
+.set CYREG_USB_SOF1, 0x40006019\r
+.set CYDEV_USB_SIE_EP2_BASE, 0x4000601c\r
+.set CYDEV_USB_SIE_EP2_SIZE, 0x00000003\r
+.set CYREG_USB_SIE_EP2_CNT0, 0x4000601c\r
+.set CYREG_USB_SIE_EP2_CNT1, 0x4000601d\r
+.set CYREG_USB_SIE_EP2_CR0, 0x4000601e\r
+.set CYREG_USB_EP0_CR, 0x40006028\r
+.set CYREG_USB_EP0_CNT, 0x40006029\r
+.set CYDEV_USB_SIE_EP3_BASE, 0x4000602c\r
+.set CYDEV_USB_SIE_EP3_SIZE, 0x00000003\r
+.set CYREG_USB_SIE_EP3_CNT0, 0x4000602c\r
+.set CYREG_USB_SIE_EP3_CNT1, 0x4000602d\r
+.set CYREG_USB_SIE_EP3_CR0, 0x4000602e\r
+.set CYDEV_USB_SIE_EP4_BASE, 0x4000603c\r
+.set CYDEV_USB_SIE_EP4_SIZE, 0x00000003\r
+.set CYREG_USB_SIE_EP4_CNT0, 0x4000603c\r
+.set CYREG_USB_SIE_EP4_CNT1, 0x4000603d\r
+.set CYREG_USB_SIE_EP4_CR0, 0x4000603e\r
+.set CYDEV_USB_SIE_EP5_BASE, 0x4000604c\r
+.set CYDEV_USB_SIE_EP5_SIZE, 0x00000003\r
+.set CYREG_USB_SIE_EP5_CNT0, 0x4000604c\r
+.set CYREG_USB_SIE_EP5_CNT1, 0x4000604d\r
+.set CYREG_USB_SIE_EP5_CR0, 0x4000604e\r
+.set CYDEV_USB_SIE_EP6_BASE, 0x4000605c\r
+.set CYDEV_USB_SIE_EP6_SIZE, 0x00000003\r
+.set CYREG_USB_SIE_EP6_CNT0, 0x4000605c\r
+.set CYREG_USB_SIE_EP6_CNT1, 0x4000605d\r
+.set CYREG_USB_SIE_EP6_CR0, 0x4000605e\r
+.set CYDEV_USB_SIE_EP7_BASE, 0x4000606c\r
+.set CYDEV_USB_SIE_EP7_SIZE, 0x00000003\r
+.set CYREG_USB_SIE_EP7_CNT0, 0x4000606c\r
+.set CYREG_USB_SIE_EP7_CNT1, 0x4000606d\r
+.set CYREG_USB_SIE_EP7_CR0, 0x4000606e\r
+.set CYDEV_USB_SIE_EP8_BASE, 0x4000607c\r
+.set CYDEV_USB_SIE_EP8_SIZE, 0x00000003\r
+.set CYREG_USB_SIE_EP8_CNT0, 0x4000607c\r
+.set CYREG_USB_SIE_EP8_CNT1, 0x4000607d\r
+.set CYREG_USB_SIE_EP8_CR0, 0x4000607e\r
+.set CYDEV_USB_ARB_EP1_BASE, 0x40006080\r
+.set CYDEV_USB_ARB_EP1_SIZE, 0x00000003\r
+.set CYREG_USB_ARB_EP1_CFG, 0x40006080\r
+.set CYREG_USB_ARB_EP1_INT_EN, 0x40006081\r
+.set CYREG_USB_ARB_EP1_SR, 0x40006082\r
+.set CYDEV_USB_ARB_RW1_BASE, 0x40006084\r
+.set CYDEV_USB_ARB_RW1_SIZE, 0x00000005\r
+.set CYREG_USB_ARB_RW1_WA, 0x40006084\r
+.set CYREG_USB_ARB_RW1_WA_MSB, 0x40006085\r
+.set CYREG_USB_ARB_RW1_RA, 0x40006086\r
+.set CYREG_USB_ARB_RW1_RA_MSB, 0x40006087\r
+.set CYREG_USB_ARB_RW1_DR, 0x40006088\r
+.set CYREG_USB_BUF_SIZE, 0x4000608c\r
+.set CYREG_USB_EP_ACTIVE, 0x4000608e\r
+.set CYREG_USB_EP_TYPE, 0x4000608f\r
+.set CYDEV_USB_ARB_EP2_BASE, 0x40006090\r
+.set CYDEV_USB_ARB_EP2_SIZE, 0x00000003\r
+.set CYREG_USB_ARB_EP2_CFG, 0x40006090\r
+.set CYREG_USB_ARB_EP2_INT_EN, 0x40006091\r
+.set CYREG_USB_ARB_EP2_SR, 0x40006092\r
+.set CYDEV_USB_ARB_RW2_BASE, 0x40006094\r
+.set CYDEV_USB_ARB_RW2_SIZE, 0x00000005\r
+.set CYREG_USB_ARB_RW2_WA, 0x40006094\r
+.set CYREG_USB_ARB_RW2_WA_MSB, 0x40006095\r
+.set CYREG_USB_ARB_RW2_RA, 0x40006096\r
+.set CYREG_USB_ARB_RW2_RA_MSB, 0x40006097\r
+.set CYREG_USB_ARB_RW2_DR, 0x40006098\r
+.set CYREG_USB_ARB_CFG, 0x4000609c\r
+.set CYREG_USB_USB_CLK_EN, 0x4000609d\r
+.set CYREG_USB_ARB_INT_EN, 0x4000609e\r
+.set CYREG_USB_ARB_INT_SR, 0x4000609f\r
+.set CYDEV_USB_ARB_EP3_BASE, 0x400060a0\r
+.set CYDEV_USB_ARB_EP3_SIZE, 0x00000003\r
+.set CYREG_USB_ARB_EP3_CFG, 0x400060a0\r
+.set CYREG_USB_ARB_EP3_INT_EN, 0x400060a1\r
+.set CYREG_USB_ARB_EP3_SR, 0x400060a2\r
+.set CYDEV_USB_ARB_RW3_BASE, 0x400060a4\r
+.set CYDEV_USB_ARB_RW3_SIZE, 0x00000005\r
+.set CYREG_USB_ARB_RW3_WA, 0x400060a4\r
+.set CYREG_USB_ARB_RW3_WA_MSB, 0x400060a5\r
+.set CYREG_USB_ARB_RW3_RA, 0x400060a6\r
+.set CYREG_USB_ARB_RW3_RA_MSB, 0x400060a7\r
+.set CYREG_USB_ARB_RW3_DR, 0x400060a8\r
+.set CYREG_USB_CWA, 0x400060ac\r
+.set CYREG_USB_CWA_MSB, 0x400060ad\r
+.set CYDEV_USB_ARB_EP4_BASE, 0x400060b0\r
+.set CYDEV_USB_ARB_EP4_SIZE, 0x00000003\r
+.set CYREG_USB_ARB_EP4_CFG, 0x400060b0\r
+.set CYREG_USB_ARB_EP4_INT_EN, 0x400060b1\r
+.set CYREG_USB_ARB_EP4_SR, 0x400060b2\r
+.set CYDEV_USB_ARB_RW4_BASE, 0x400060b4\r
+.set CYDEV_USB_ARB_RW4_SIZE, 0x00000005\r
+.set CYREG_USB_ARB_RW4_WA, 0x400060b4\r
+.set CYREG_USB_ARB_RW4_WA_MSB, 0x400060b5\r
+.set CYREG_USB_ARB_RW4_RA, 0x400060b6\r
+.set CYREG_USB_ARB_RW4_RA_MSB, 0x400060b7\r
+.set CYREG_USB_ARB_RW4_DR, 0x400060b8\r
+.set CYREG_USB_DMA_THRES, 0x400060bc\r
+.set CYREG_USB_DMA_THRES_MSB, 0x400060bd\r
+.set CYDEV_USB_ARB_EP5_BASE, 0x400060c0\r
+.set CYDEV_USB_ARB_EP5_SIZE, 0x00000003\r
+.set CYREG_USB_ARB_EP5_CFG, 0x400060c0\r
+.set CYREG_USB_ARB_EP5_INT_EN, 0x400060c1\r
+.set CYREG_USB_ARB_EP5_SR, 0x400060c2\r
+.set CYDEV_USB_ARB_RW5_BASE, 0x400060c4\r
+.set CYDEV_USB_ARB_RW5_SIZE, 0x00000005\r
+.set CYREG_USB_ARB_RW5_WA, 0x400060c4\r
+.set CYREG_USB_ARB_RW5_WA_MSB, 0x400060c5\r
+.set CYREG_USB_ARB_RW5_RA, 0x400060c6\r
+.set CYREG_USB_ARB_RW5_RA_MSB, 0x400060c7\r
+.set CYREG_USB_ARB_RW5_DR, 0x400060c8\r
+.set CYREG_USB_BUS_RST_CNT, 0x400060cc\r
+.set CYDEV_USB_ARB_EP6_BASE, 0x400060d0\r
+.set CYDEV_USB_ARB_EP6_SIZE, 0x00000003\r
+.set CYREG_USB_ARB_EP6_CFG, 0x400060d0\r
+.set CYREG_USB_ARB_EP6_INT_EN, 0x400060d1\r
+.set CYREG_USB_ARB_EP6_SR, 0x400060d2\r
+.set CYDEV_USB_ARB_RW6_BASE, 0x400060d4\r
+.set CYDEV_USB_ARB_RW6_SIZE, 0x00000005\r
+.set CYREG_USB_ARB_RW6_WA, 0x400060d4\r
+.set CYREG_USB_ARB_RW6_WA_MSB, 0x400060d5\r
+.set CYREG_USB_ARB_RW6_RA, 0x400060d6\r
+.set CYREG_USB_ARB_RW6_RA_MSB, 0x400060d7\r
+.set CYREG_USB_ARB_RW6_DR, 0x400060d8\r
+.set CYDEV_USB_ARB_EP7_BASE, 0x400060e0\r
+.set CYDEV_USB_ARB_EP7_SIZE, 0x00000003\r
+.set CYREG_USB_ARB_EP7_CFG, 0x400060e0\r
+.set CYREG_USB_ARB_EP7_INT_EN, 0x400060e1\r
+.set CYREG_USB_ARB_EP7_SR, 0x400060e2\r
+.set CYDEV_USB_ARB_RW7_BASE, 0x400060e4\r
+.set CYDEV_USB_ARB_RW7_SIZE, 0x00000005\r
+.set CYREG_USB_ARB_RW7_WA, 0x400060e4\r
+.set CYREG_USB_ARB_RW7_WA_MSB, 0x400060e5\r
+.set CYREG_USB_ARB_RW7_RA, 0x400060e6\r
+.set CYREG_USB_ARB_RW7_RA_MSB, 0x400060e7\r
+.set CYREG_USB_ARB_RW7_DR, 0x400060e8\r
+.set CYDEV_USB_ARB_EP8_BASE, 0x400060f0\r
+.set CYDEV_USB_ARB_EP8_SIZE, 0x00000003\r
+.set CYREG_USB_ARB_EP8_CFG, 0x400060f0\r
+.set CYREG_USB_ARB_EP8_INT_EN, 0x400060f1\r
+.set CYREG_USB_ARB_EP8_SR, 0x400060f2\r
+.set CYDEV_USB_ARB_RW8_BASE, 0x400060f4\r
+.set CYDEV_USB_ARB_RW8_SIZE, 0x00000005\r
+.set CYREG_USB_ARB_RW8_WA, 0x400060f4\r
+.set CYREG_USB_ARB_RW8_WA_MSB, 0x400060f5\r
+.set CYREG_USB_ARB_RW8_RA, 0x400060f6\r
+.set CYREG_USB_ARB_RW8_RA_MSB, 0x400060f7\r
+.set CYREG_USB_ARB_RW8_DR, 0x400060f8\r
+.set CYDEV_USB_MEM_BASE, 0x40006100\r
+.set CYDEV_USB_MEM_SIZE, 0x00000200\r
+.set CYREG_USB_MEM_DATA_MBASE, 0x40006100\r
+.set CYREG_USB_MEM_DATA_MSIZE, 0x00000200\r
+.set CYDEV_UWRK_BASE, 0x40006400\r
+.set CYDEV_UWRK_SIZE, 0x00000b60\r
+.set CYDEV_UWRK_UWRK8_BASE, 0x40006400\r
+.set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0\r
+.set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400\r
+.set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0\r
+.set CYREG_B0_UDB00_A0, 0x40006400\r
+.set CYREG_B0_UDB01_A0, 0x40006401\r
+.set CYREG_B0_UDB02_A0, 0x40006402\r
+.set CYREG_B0_UDB03_A0, 0x40006403\r
+.set CYREG_B0_UDB04_A0, 0x40006404\r
+.set CYREG_B0_UDB05_A0, 0x40006405\r
+.set CYREG_B0_UDB06_A0, 0x40006406\r
+.set CYREG_B0_UDB07_A0, 0x40006407\r
+.set CYREG_B0_UDB08_A0, 0x40006408\r
+.set CYREG_B0_UDB09_A0, 0x40006409\r
+.set CYREG_B0_UDB10_A0, 0x4000640a\r
+.set CYREG_B0_UDB11_A0, 0x4000640b\r
+.set CYREG_B0_UDB12_A0, 0x4000640c\r
+.set CYREG_B0_UDB13_A0, 0x4000640d\r
+.set CYREG_B0_UDB14_A0, 0x4000640e\r
+.set CYREG_B0_UDB15_A0, 0x4000640f\r
+.set CYREG_B0_UDB00_A1, 0x40006410\r
+.set CYREG_B0_UDB01_A1, 0x40006411\r
+.set CYREG_B0_UDB02_A1, 0x40006412\r
+.set CYREG_B0_UDB03_A1, 0x40006413\r
+.set CYREG_B0_UDB04_A1, 0x40006414\r
+.set CYREG_B0_UDB05_A1, 0x40006415\r
+.set CYREG_B0_UDB06_A1, 0x40006416\r
+.set CYREG_B0_UDB07_A1, 0x40006417\r
+.set CYREG_B0_UDB08_A1, 0x40006418\r
+.set CYREG_B0_UDB09_A1, 0x40006419\r
+.set CYREG_B0_UDB10_A1, 0x4000641a\r
+.set CYREG_B0_UDB11_A1, 0x4000641b\r
+.set CYREG_B0_UDB12_A1, 0x4000641c\r
+.set CYREG_B0_UDB13_A1, 0x4000641d\r
+.set CYREG_B0_UDB14_A1, 0x4000641e\r
+.set CYREG_B0_UDB15_A1, 0x4000641f\r
+.set CYREG_B0_UDB00_D0, 0x40006420\r
+.set CYREG_B0_UDB01_D0, 0x40006421\r
+.set CYREG_B0_UDB02_D0, 0x40006422\r
+.set CYREG_B0_UDB03_D0, 0x40006423\r
+.set CYREG_B0_UDB04_D0, 0x40006424\r
+.set CYREG_B0_UDB05_D0, 0x40006425\r
+.set CYREG_B0_UDB06_D0, 0x40006426\r
+.set CYREG_B0_UDB07_D0, 0x40006427\r
+.set CYREG_B0_UDB08_D0, 0x40006428\r
+.set CYREG_B0_UDB09_D0, 0x40006429\r
+.set CYREG_B0_UDB10_D0, 0x4000642a\r
+.set CYREG_B0_UDB11_D0, 0x4000642b\r
+.set CYREG_B0_UDB12_D0, 0x4000642c\r
+.set CYREG_B0_UDB13_D0, 0x4000642d\r
+.set CYREG_B0_UDB14_D0, 0x4000642e\r
+.set CYREG_B0_UDB15_D0, 0x4000642f\r
+.set CYREG_B0_UDB00_D1, 0x40006430\r
+.set CYREG_B0_UDB01_D1, 0x40006431\r
+.set CYREG_B0_UDB02_D1, 0x40006432\r
+.set CYREG_B0_UDB03_D1, 0x40006433\r
+.set CYREG_B0_UDB04_D1, 0x40006434\r
+.set CYREG_B0_UDB05_D1, 0x40006435\r
+.set CYREG_B0_UDB06_D1, 0x40006436\r
+.set CYREG_B0_UDB07_D1, 0x40006437\r
+.set CYREG_B0_UDB08_D1, 0x40006438\r
+.set CYREG_B0_UDB09_D1, 0x40006439\r
+.set CYREG_B0_UDB10_D1, 0x4000643a\r
+.set CYREG_B0_UDB11_D1, 0x4000643b\r
+.set CYREG_B0_UDB12_D1, 0x4000643c\r
+.set CYREG_B0_UDB13_D1, 0x4000643d\r
+.set CYREG_B0_UDB14_D1, 0x4000643e\r
+.set CYREG_B0_UDB15_D1, 0x4000643f\r
+.set CYREG_B0_UDB00_F0, 0x40006440\r
+.set CYREG_B0_UDB01_F0, 0x40006441\r
+.set CYREG_B0_UDB02_F0, 0x40006442\r
+.set CYREG_B0_UDB03_F0, 0x40006443\r
+.set CYREG_B0_UDB04_F0, 0x40006444\r
+.set CYREG_B0_UDB05_F0, 0x40006445\r
+.set CYREG_B0_UDB06_F0, 0x40006446\r
+.set CYREG_B0_UDB07_F0, 0x40006447\r
+.set CYREG_B0_UDB08_F0, 0x40006448\r
+.set CYREG_B0_UDB09_F0, 0x40006449\r
+.set CYREG_B0_UDB10_F0, 0x4000644a\r
+.set CYREG_B0_UDB11_F0, 0x4000644b\r
+.set CYREG_B0_UDB12_F0, 0x4000644c\r
+.set CYREG_B0_UDB13_F0, 0x4000644d\r
+.set CYREG_B0_UDB14_F0, 0x4000644e\r
+.set CYREG_B0_UDB15_F0, 0x4000644f\r
+.set CYREG_B0_UDB00_F1, 0x40006450\r
+.set CYREG_B0_UDB01_F1, 0x40006451\r
+.set CYREG_B0_UDB02_F1, 0x40006452\r
+.set CYREG_B0_UDB03_F1, 0x40006453\r
+.set CYREG_B0_UDB04_F1, 0x40006454\r
+.set CYREG_B0_UDB05_F1, 0x40006455\r
+.set CYREG_B0_UDB06_F1, 0x40006456\r
+.set CYREG_B0_UDB07_F1, 0x40006457\r
+.set CYREG_B0_UDB08_F1, 0x40006458\r
+.set CYREG_B0_UDB09_F1, 0x40006459\r
+.set CYREG_B0_UDB10_F1, 0x4000645a\r
+.set CYREG_B0_UDB11_F1, 0x4000645b\r
+.set CYREG_B0_UDB12_F1, 0x4000645c\r
+.set CYREG_B0_UDB13_F1, 0x4000645d\r
+.set CYREG_B0_UDB14_F1, 0x4000645e\r
+.set CYREG_B0_UDB15_F1, 0x4000645f\r
+.set CYREG_B0_UDB00_ST, 0x40006460\r
+.set CYREG_B0_UDB01_ST, 0x40006461\r
+.set CYREG_B0_UDB02_ST, 0x40006462\r
+.set CYREG_B0_UDB03_ST, 0x40006463\r
+.set CYREG_B0_UDB04_ST, 0x40006464\r
+.set CYREG_B0_UDB05_ST, 0x40006465\r
+.set CYREG_B0_UDB06_ST, 0x40006466\r
+.set CYREG_B0_UDB07_ST, 0x40006467\r
+.set CYREG_B0_UDB08_ST, 0x40006468\r
+.set CYREG_B0_UDB09_ST, 0x40006469\r
+.set CYREG_B0_UDB10_ST, 0x4000646a\r
+.set CYREG_B0_UDB11_ST, 0x4000646b\r
+.set CYREG_B0_UDB12_ST, 0x4000646c\r
+.set CYREG_B0_UDB13_ST, 0x4000646d\r
+.set CYREG_B0_UDB14_ST, 0x4000646e\r
+.set CYREG_B0_UDB15_ST, 0x4000646f\r
+.set CYREG_B0_UDB00_CTL, 0x40006470\r
+.set CYREG_B0_UDB01_CTL, 0x40006471\r
+.set CYREG_B0_UDB02_CTL, 0x40006472\r
+.set CYREG_B0_UDB03_CTL, 0x40006473\r
+.set CYREG_B0_UDB04_CTL, 0x40006474\r
+.set CYREG_B0_UDB05_CTL, 0x40006475\r
+.set CYREG_B0_UDB06_CTL, 0x40006476\r
+.set CYREG_B0_UDB07_CTL, 0x40006477\r
+.set CYREG_B0_UDB08_CTL, 0x40006478\r
+.set CYREG_B0_UDB09_CTL, 0x40006479\r
+.set CYREG_B0_UDB10_CTL, 0x4000647a\r
+.set CYREG_B0_UDB11_CTL, 0x4000647b\r
+.set CYREG_B0_UDB12_CTL, 0x4000647c\r
+.set CYREG_B0_UDB13_CTL, 0x4000647d\r
+.set CYREG_B0_UDB14_CTL, 0x4000647e\r
+.set CYREG_B0_UDB15_CTL, 0x4000647f\r
+.set CYREG_B0_UDB00_MSK, 0x40006480\r
+.set CYREG_B0_UDB01_MSK, 0x40006481\r
+.set CYREG_B0_UDB02_MSK, 0x40006482\r
+.set CYREG_B0_UDB03_MSK, 0x40006483\r
+.set CYREG_B0_UDB04_MSK, 0x40006484\r
+.set CYREG_B0_UDB05_MSK, 0x40006485\r
+.set CYREG_B0_UDB06_MSK, 0x40006486\r
+.set CYREG_B0_UDB07_MSK, 0x40006487\r
+.set CYREG_B0_UDB08_MSK, 0x40006488\r
+.set CYREG_B0_UDB09_MSK, 0x40006489\r
+.set CYREG_B0_UDB10_MSK, 0x4000648a\r
+.set CYREG_B0_UDB11_MSK, 0x4000648b\r
+.set CYREG_B0_UDB12_MSK, 0x4000648c\r
+.set CYREG_B0_UDB13_MSK, 0x4000648d\r
+.set CYREG_B0_UDB14_MSK, 0x4000648e\r
+.set CYREG_B0_UDB15_MSK, 0x4000648f\r
+.set CYREG_B0_UDB00_ACTL, 0x40006490\r
+.set CYREG_B0_UDB01_ACTL, 0x40006491\r
+.set CYREG_B0_UDB02_ACTL, 0x40006492\r
+.set CYREG_B0_UDB03_ACTL, 0x40006493\r
+.set CYREG_B0_UDB04_ACTL, 0x40006494\r
+.set CYREG_B0_UDB05_ACTL, 0x40006495\r
+.set CYREG_B0_UDB06_ACTL, 0x40006496\r
+.set CYREG_B0_UDB07_ACTL, 0x40006497\r
+.set CYREG_B0_UDB08_ACTL, 0x40006498\r
+.set CYREG_B0_UDB09_ACTL, 0x40006499\r
+.set CYREG_B0_UDB10_ACTL, 0x4000649a\r
+.set CYREG_B0_UDB11_ACTL, 0x4000649b\r
+.set CYREG_B0_UDB12_ACTL, 0x4000649c\r
+.set CYREG_B0_UDB13_ACTL, 0x4000649d\r
+.set CYREG_B0_UDB14_ACTL, 0x4000649e\r
+.set CYREG_B0_UDB15_ACTL, 0x4000649f\r
+.set CYREG_B0_UDB00_MC, 0x400064a0\r
+.set CYREG_B0_UDB01_MC, 0x400064a1\r
+.set CYREG_B0_UDB02_MC, 0x400064a2\r
+.set CYREG_B0_UDB03_MC, 0x400064a3\r
+.set CYREG_B0_UDB04_MC, 0x400064a4\r
+.set CYREG_B0_UDB05_MC, 0x400064a5\r
+.set CYREG_B0_UDB06_MC, 0x400064a6\r
+.set CYREG_B0_UDB07_MC, 0x400064a7\r
+.set CYREG_B0_UDB08_MC, 0x400064a8\r
+.set CYREG_B0_UDB09_MC, 0x400064a9\r
+.set CYREG_B0_UDB10_MC, 0x400064aa\r
+.set CYREG_B0_UDB11_MC, 0x400064ab\r
+.set CYREG_B0_UDB12_MC, 0x400064ac\r
+.set CYREG_B0_UDB13_MC, 0x400064ad\r
+.set CYREG_B0_UDB14_MC, 0x400064ae\r
+.set CYREG_B0_UDB15_MC, 0x400064af\r
+.set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500\r
+.set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0\r
+.set CYREG_B1_UDB04_A0, 0x40006504\r
+.set CYREG_B1_UDB05_A0, 0x40006505\r
+.set CYREG_B1_UDB06_A0, 0x40006506\r
+.set CYREG_B1_UDB07_A0, 0x40006507\r
+.set CYREG_B1_UDB08_A0, 0x40006508\r
+.set CYREG_B1_UDB09_A0, 0x40006509\r
+.set CYREG_B1_UDB10_A0, 0x4000650a\r
+.set CYREG_B1_UDB11_A0, 0x4000650b\r
+.set CYREG_B1_UDB04_A1, 0x40006514\r
+.set CYREG_B1_UDB05_A1, 0x40006515\r
+.set CYREG_B1_UDB06_A1, 0x40006516\r
+.set CYREG_B1_UDB07_A1, 0x40006517\r
+.set CYREG_B1_UDB08_A1, 0x40006518\r
+.set CYREG_B1_UDB09_A1, 0x40006519\r
+.set CYREG_B1_UDB10_A1, 0x4000651a\r
+.set CYREG_B1_UDB11_A1, 0x4000651b\r
+.set CYREG_B1_UDB04_D0, 0x40006524\r
+.set CYREG_B1_UDB05_D0, 0x40006525\r
+.set CYREG_B1_UDB06_D0, 0x40006526\r
+.set CYREG_B1_UDB07_D0, 0x40006527\r
+.set CYREG_B1_UDB08_D0, 0x40006528\r
+.set CYREG_B1_UDB09_D0, 0x40006529\r
+.set CYREG_B1_UDB10_D0, 0x4000652a\r
+.set CYREG_B1_UDB11_D0, 0x4000652b\r
+.set CYREG_B1_UDB04_D1, 0x40006534\r
+.set CYREG_B1_UDB05_D1, 0x40006535\r
+.set CYREG_B1_UDB06_D1, 0x40006536\r
+.set CYREG_B1_UDB07_D1, 0x40006537\r
+.set CYREG_B1_UDB08_D1, 0x40006538\r
+.set CYREG_B1_UDB09_D1, 0x40006539\r
+.set CYREG_B1_UDB10_D1, 0x4000653a\r
+.set CYREG_B1_UDB11_D1, 0x4000653b\r
+.set CYREG_B1_UDB04_F0, 0x40006544\r
+.set CYREG_B1_UDB05_F0, 0x40006545\r
+.set CYREG_B1_UDB06_F0, 0x40006546\r
+.set CYREG_B1_UDB07_F0, 0x40006547\r
+.set CYREG_B1_UDB08_F0, 0x40006548\r
+.set CYREG_B1_UDB09_F0, 0x40006549\r
+.set CYREG_B1_UDB10_F0, 0x4000654a\r
+.set CYREG_B1_UDB11_F0, 0x4000654b\r
+.set CYREG_B1_UDB04_F1, 0x40006554\r
+.set CYREG_B1_UDB05_F1, 0x40006555\r
+.set CYREG_B1_UDB06_F1, 0x40006556\r
+.set CYREG_B1_UDB07_F1, 0x40006557\r
+.set CYREG_B1_UDB08_F1, 0x40006558\r
+.set CYREG_B1_UDB09_F1, 0x40006559\r
+.set CYREG_B1_UDB10_F1, 0x4000655a\r
+.set CYREG_B1_UDB11_F1, 0x4000655b\r
+.set CYREG_B1_UDB04_ST, 0x40006564\r
+.set CYREG_B1_UDB05_ST, 0x40006565\r
+.set CYREG_B1_UDB06_ST, 0x40006566\r
+.set CYREG_B1_UDB07_ST, 0x40006567\r
+.set CYREG_B1_UDB08_ST, 0x40006568\r
+.set CYREG_B1_UDB09_ST, 0x40006569\r
+.set CYREG_B1_UDB10_ST, 0x4000656a\r
+.set CYREG_B1_UDB11_ST, 0x4000656b\r
+.set CYREG_B1_UDB04_CTL, 0x40006574\r
+.set CYREG_B1_UDB05_CTL, 0x40006575\r
+.set CYREG_B1_UDB06_CTL, 0x40006576\r
+.set CYREG_B1_UDB07_CTL, 0x40006577\r
+.set CYREG_B1_UDB08_CTL, 0x40006578\r
+.set CYREG_B1_UDB09_CTL, 0x40006579\r
+.set CYREG_B1_UDB10_CTL, 0x4000657a\r
+.set CYREG_B1_UDB11_CTL, 0x4000657b\r
+.set CYREG_B1_UDB04_MSK, 0x40006584\r
+.set CYREG_B1_UDB05_MSK, 0x40006585\r
+.set CYREG_B1_UDB06_MSK, 0x40006586\r
+.set CYREG_B1_UDB07_MSK, 0x40006587\r
+.set CYREG_B1_UDB08_MSK, 0x40006588\r
+.set CYREG_B1_UDB09_MSK, 0x40006589\r
+.set CYREG_B1_UDB10_MSK, 0x4000658a\r
+.set CYREG_B1_UDB11_MSK, 0x4000658b\r
+.set CYREG_B1_UDB04_ACTL, 0x40006594\r
+.set CYREG_B1_UDB05_ACTL, 0x40006595\r
+.set CYREG_B1_UDB06_ACTL, 0x40006596\r
+.set CYREG_B1_UDB07_ACTL, 0x40006597\r
+.set CYREG_B1_UDB08_ACTL, 0x40006598\r
+.set CYREG_B1_UDB09_ACTL, 0x40006599\r
+.set CYREG_B1_UDB10_ACTL, 0x4000659a\r
+.set CYREG_B1_UDB11_ACTL, 0x4000659b\r
+.set CYREG_B1_UDB04_MC, 0x400065a4\r
+.set CYREG_B1_UDB05_MC, 0x400065a5\r
+.set CYREG_B1_UDB06_MC, 0x400065a6\r
+.set CYREG_B1_UDB07_MC, 0x400065a7\r
+.set CYREG_B1_UDB08_MC, 0x400065a8\r
+.set CYREG_B1_UDB09_MC, 0x400065a9\r
+.set CYREG_B1_UDB10_MC, 0x400065aa\r
+.set CYREG_B1_UDB11_MC, 0x400065ab\r
+.set CYDEV_UWRK_UWRK16_BASE, 0x40006800\r
+.set CYDEV_UWRK_UWRK16_SIZE, 0x00000760\r
+.set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800\r
+.set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800\r
+.set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160\r
+.set CYREG_B0_UDB00_A0_A1, 0x40006800\r
+.set CYREG_B0_UDB01_A0_A1, 0x40006802\r
+.set CYREG_B0_UDB02_A0_A1, 0x40006804\r
+.set CYREG_B0_UDB03_A0_A1, 0x40006806\r
+.set CYREG_B0_UDB04_A0_A1, 0x40006808\r
+.set CYREG_B0_UDB05_A0_A1, 0x4000680a\r
+.set CYREG_B0_UDB06_A0_A1, 0x4000680c\r
+.set CYREG_B0_UDB07_A0_A1, 0x4000680e\r
+.set CYREG_B0_UDB08_A0_A1, 0x40006810\r
+.set CYREG_B0_UDB09_A0_A1, 0x40006812\r
+.set CYREG_B0_UDB10_A0_A1, 0x40006814\r
+.set CYREG_B0_UDB11_A0_A1, 0x40006816\r
+.set CYREG_B0_UDB12_A0_A1, 0x40006818\r
+.set CYREG_B0_UDB13_A0_A1, 0x4000681a\r
+.set CYREG_B0_UDB14_A0_A1, 0x4000681c\r
+.set CYREG_B0_UDB15_A0_A1, 0x4000681e\r
+.set CYREG_B0_UDB00_D0_D1, 0x40006840\r
+.set CYREG_B0_UDB01_D0_D1, 0x40006842\r
+.set CYREG_B0_UDB02_D0_D1, 0x40006844\r
+.set CYREG_B0_UDB03_D0_D1, 0x40006846\r
+.set CYREG_B0_UDB04_D0_D1, 0x40006848\r
+.set CYREG_B0_UDB05_D0_D1, 0x4000684a\r
+.set CYREG_B0_UDB06_D0_D1, 0x4000684c\r
+.set CYREG_B0_UDB07_D0_D1, 0x4000684e\r
+.set CYREG_B0_UDB08_D0_D1, 0x40006850\r
+.set CYREG_B0_UDB09_D0_D1, 0x40006852\r
+.set CYREG_B0_UDB10_D0_D1, 0x40006854\r
+.set CYREG_B0_UDB11_D0_D1, 0x40006856\r
+.set CYREG_B0_UDB12_D0_D1, 0x40006858\r
+.set CYREG_B0_UDB13_D0_D1, 0x4000685a\r
+.set CYREG_B0_UDB14_D0_D1, 0x4000685c\r
+.set CYREG_B0_UDB15_D0_D1, 0x4000685e\r
+.set CYREG_B0_UDB00_F0_F1, 0x40006880\r
+.set CYREG_B0_UDB01_F0_F1, 0x40006882\r
+.set CYREG_B0_UDB02_F0_F1, 0x40006884\r
+.set CYREG_B0_UDB03_F0_F1, 0x40006886\r
+.set CYREG_B0_UDB04_F0_F1, 0x40006888\r
+.set CYREG_B0_UDB05_F0_F1, 0x4000688a\r
+.set CYREG_B0_UDB06_F0_F1, 0x4000688c\r
+.set CYREG_B0_UDB07_F0_F1, 0x4000688e\r
+.set CYREG_B0_UDB08_F0_F1, 0x40006890\r
+.set CYREG_B0_UDB09_F0_F1, 0x40006892\r
+.set CYREG_B0_UDB10_F0_F1, 0x40006894\r
+.set CYREG_B0_UDB11_F0_F1, 0x40006896\r
+.set CYREG_B0_UDB12_F0_F1, 0x40006898\r
+.set CYREG_B0_UDB13_F0_F1, 0x4000689a\r
+.set CYREG_B0_UDB14_F0_F1, 0x4000689c\r
+.set CYREG_B0_UDB15_F0_F1, 0x4000689e\r
+.set CYREG_B0_UDB00_ST_CTL, 0x400068c0\r
+.set CYREG_B0_UDB01_ST_CTL, 0x400068c2\r
+.set CYREG_B0_UDB02_ST_CTL, 0x400068c4\r
+.set CYREG_B0_UDB03_ST_CTL, 0x400068c6\r
+.set CYREG_B0_UDB04_ST_CTL, 0x400068c8\r
+.set CYREG_B0_UDB05_ST_CTL, 0x400068ca\r
+.set CYREG_B0_UDB06_ST_CTL, 0x400068cc\r
+.set CYREG_B0_UDB07_ST_CTL, 0x400068ce\r
+.set CYREG_B0_UDB08_ST_CTL, 0x400068d0\r
+.set CYREG_B0_UDB09_ST_CTL, 0x400068d2\r
+.set CYREG_B0_UDB10_ST_CTL, 0x400068d4\r
+.set CYREG_B0_UDB11_ST_CTL, 0x400068d6\r
+.set CYREG_B0_UDB12_ST_CTL, 0x400068d8\r
+.set CYREG_B0_UDB13_ST_CTL, 0x400068da\r
+.set CYREG_B0_UDB14_ST_CTL, 0x400068dc\r
+.set CYREG_B0_UDB15_ST_CTL, 0x400068de\r
+.set CYREG_B0_UDB00_MSK_ACTL, 0x40006900\r
+.set CYREG_B0_UDB01_MSK_ACTL, 0x40006902\r
+.set CYREG_B0_UDB02_MSK_ACTL, 0x40006904\r
+.set CYREG_B0_UDB03_MSK_ACTL, 0x40006906\r
+.set CYREG_B0_UDB04_MSK_ACTL, 0x40006908\r
+.set CYREG_B0_UDB05_MSK_ACTL, 0x4000690a\r
+.set CYREG_B0_UDB06_MSK_ACTL, 0x4000690c\r
+.set CYREG_B0_UDB07_MSK_ACTL, 0x4000690e\r
+.set CYREG_B0_UDB08_MSK_ACTL, 0x40006910\r
+.set CYREG_B0_UDB09_MSK_ACTL, 0x40006912\r
+.set CYREG_B0_UDB10_MSK_ACTL, 0x40006914\r
+.set CYREG_B0_UDB11_MSK_ACTL, 0x40006916\r
+.set CYREG_B0_UDB12_MSK_ACTL, 0x40006918\r
+.set CYREG_B0_UDB13_MSK_ACTL, 0x4000691a\r
+.set CYREG_B0_UDB14_MSK_ACTL, 0x4000691c\r
+.set CYREG_B0_UDB15_MSK_ACTL, 0x4000691e\r
+.set CYREG_B0_UDB00_MC_00, 0x40006940\r
+.set CYREG_B0_UDB01_MC_00, 0x40006942\r
+.set CYREG_B0_UDB02_MC_00, 0x40006944\r
+.set CYREG_B0_UDB03_MC_00, 0x40006946\r
+.set CYREG_B0_UDB04_MC_00, 0x40006948\r
+.set CYREG_B0_UDB05_MC_00, 0x4000694a\r
+.set CYREG_B0_UDB06_MC_00, 0x4000694c\r
+.set CYREG_B0_UDB07_MC_00, 0x4000694e\r
+.set CYREG_B0_UDB08_MC_00, 0x40006950\r
+.set CYREG_B0_UDB09_MC_00, 0x40006952\r
+.set CYREG_B0_UDB10_MC_00, 0x40006954\r
+.set CYREG_B0_UDB11_MC_00, 0x40006956\r
+.set CYREG_B0_UDB12_MC_00, 0x40006958\r
+.set CYREG_B0_UDB13_MC_00, 0x4000695a\r
+.set CYREG_B0_UDB14_MC_00, 0x4000695c\r
+.set CYREG_B0_UDB15_MC_00, 0x4000695e\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00\r
+.set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160\r
+.set CYREG_B1_UDB04_A0_A1, 0x40006a08\r
+.set CYREG_B1_UDB05_A0_A1, 0x40006a0a\r
+.set CYREG_B1_UDB06_A0_A1, 0x40006a0c\r
+.set CYREG_B1_UDB07_A0_A1, 0x40006a0e\r
+.set CYREG_B1_UDB08_A0_A1, 0x40006a10\r
+.set CYREG_B1_UDB09_A0_A1, 0x40006a12\r
+.set CYREG_B1_UDB10_A0_A1, 0x40006a14\r
+.set CYREG_B1_UDB11_A0_A1, 0x40006a16\r
+.set CYREG_B1_UDB04_D0_D1, 0x40006a48\r
+.set CYREG_B1_UDB05_D0_D1, 0x40006a4a\r
+.set CYREG_B1_UDB06_D0_D1, 0x40006a4c\r
+.set CYREG_B1_UDB07_D0_D1, 0x40006a4e\r
+.set CYREG_B1_UDB08_D0_D1, 0x40006a50\r
+.set CYREG_B1_UDB09_D0_D1, 0x40006a52\r
+.set CYREG_B1_UDB10_D0_D1, 0x40006a54\r
+.set CYREG_B1_UDB11_D0_D1, 0x40006a56\r
+.set CYREG_B1_UDB04_F0_F1, 0x40006a88\r
+.set CYREG_B1_UDB05_F0_F1, 0x40006a8a\r
+.set CYREG_B1_UDB06_F0_F1, 0x40006a8c\r
+.set CYREG_B1_UDB07_F0_F1, 0x40006a8e\r
+.set CYREG_B1_UDB08_F0_F1, 0x40006a90\r
+.set CYREG_B1_UDB09_F0_F1, 0x40006a92\r
+.set CYREG_B1_UDB10_F0_F1, 0x40006a94\r
+.set CYREG_B1_UDB11_F0_F1, 0x40006a96\r
+.set CYREG_B1_UDB04_ST_CTL, 0x40006ac8\r
+.set CYREG_B1_UDB05_ST_CTL, 0x40006aca\r
+.set CYREG_B1_UDB06_ST_CTL, 0x40006acc\r
+.set CYREG_B1_UDB07_ST_CTL, 0x40006ace\r
+.set CYREG_B1_UDB08_ST_CTL, 0x40006ad0\r
+.set CYREG_B1_UDB09_ST_CTL, 0x40006ad2\r
+.set CYREG_B1_UDB10_ST_CTL, 0x40006ad4\r
+.set CYREG_B1_UDB11_ST_CTL, 0x40006ad6\r
+.set CYREG_B1_UDB04_MSK_ACTL, 0x40006b08\r
+.set CYREG_B1_UDB05_MSK_ACTL, 0x40006b0a\r
+.set CYREG_B1_UDB06_MSK_ACTL, 0x40006b0c\r
+.set CYREG_B1_UDB07_MSK_ACTL, 0x40006b0e\r
+.set CYREG_B1_UDB08_MSK_ACTL, 0x40006b10\r
+.set CYREG_B1_UDB09_MSK_ACTL, 0x40006b12\r
+.set CYREG_B1_UDB10_MSK_ACTL, 0x40006b14\r
+.set CYREG_B1_UDB11_MSK_ACTL, 0x40006b16\r
+.set CYREG_B1_UDB04_MC_00, 0x40006b48\r
+.set CYREG_B1_UDB05_MC_00, 0x40006b4a\r
+.set CYREG_B1_UDB06_MC_00, 0x40006b4c\r
+.set CYREG_B1_UDB07_MC_00, 0x40006b4e\r
+.set CYREG_B1_UDB08_MC_00, 0x40006b50\r
+.set CYREG_B1_UDB09_MC_00, 0x40006b52\r
+.set CYREG_B1_UDB10_MC_00, 0x40006b54\r
+.set CYREG_B1_UDB11_MC_00, 0x40006b56\r
+.set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800\r
+.set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800\r
+.set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e\r
+.set CYREG_B0_UDB00_01_A0, 0x40006800\r
+.set CYREG_B0_UDB01_02_A0, 0x40006802\r
+.set CYREG_B0_UDB02_03_A0, 0x40006804\r
+.set CYREG_B0_UDB03_04_A0, 0x40006806\r
+.set CYREG_B0_UDB04_05_A0, 0x40006808\r
+.set CYREG_B0_UDB05_06_A0, 0x4000680a\r
+.set CYREG_B0_UDB06_07_A0, 0x4000680c\r
+.set CYREG_B0_UDB07_08_A0, 0x4000680e\r
+.set CYREG_B0_UDB08_09_A0, 0x40006810\r
+.set CYREG_B0_UDB09_10_A0, 0x40006812\r
+.set CYREG_B0_UDB10_11_A0, 0x40006814\r
+.set CYREG_B0_UDB11_12_A0, 0x40006816\r
+.set CYREG_B0_UDB12_13_A0, 0x40006818\r
+.set CYREG_B0_UDB13_14_A0, 0x4000681a\r
+.set CYREG_B0_UDB14_15_A0, 0x4000681c\r
+.set CYREG_B0_UDB00_01_A1, 0x40006820\r
+.set CYREG_B0_UDB01_02_A1, 0x40006822\r
+.set CYREG_B0_UDB02_03_A1, 0x40006824\r
+.set CYREG_B0_UDB03_04_A1, 0x40006826\r
+.set CYREG_B0_UDB04_05_A1, 0x40006828\r
+.set CYREG_B0_UDB05_06_A1, 0x4000682a\r
+.set CYREG_B0_UDB06_07_A1, 0x4000682c\r
+.set CYREG_B0_UDB07_08_A1, 0x4000682e\r
+.set CYREG_B0_UDB08_09_A1, 0x40006830\r
+.set CYREG_B0_UDB09_10_A1, 0x40006832\r
+.set CYREG_B0_UDB10_11_A1, 0x40006834\r
+.set CYREG_B0_UDB11_12_A1, 0x40006836\r
+.set CYREG_B0_UDB12_13_A1, 0x40006838\r
+.set CYREG_B0_UDB13_14_A1, 0x4000683a\r
+.set CYREG_B0_UDB14_15_A1, 0x4000683c\r
+.set CYREG_B0_UDB00_01_D0, 0x40006840\r
+.set CYREG_B0_UDB01_02_D0, 0x40006842\r
+.set CYREG_B0_UDB02_03_D0, 0x40006844\r
+.set CYREG_B0_UDB03_04_D0, 0x40006846\r
+.set CYREG_B0_UDB04_05_D0, 0x40006848\r
+.set CYREG_B0_UDB05_06_D0, 0x4000684a\r
+.set CYREG_B0_UDB06_07_D0, 0x4000684c\r
+.set CYREG_B0_UDB07_08_D0, 0x4000684e\r
+.set CYREG_B0_UDB08_09_D0, 0x40006850\r
+.set CYREG_B0_UDB09_10_D0, 0x40006852\r
+.set CYREG_B0_UDB10_11_D0, 0x40006854\r
+.set CYREG_B0_UDB11_12_D0, 0x40006856\r
+.set CYREG_B0_UDB12_13_D0, 0x40006858\r
+.set CYREG_B0_UDB13_14_D0, 0x4000685a\r
+.set CYREG_B0_UDB14_15_D0, 0x4000685c\r
+.set CYREG_B0_UDB00_01_D1, 0x40006860\r
+.set CYREG_B0_UDB01_02_D1, 0x40006862\r
+.set CYREG_B0_UDB02_03_D1, 0x40006864\r
+.set CYREG_B0_UDB03_04_D1, 0x40006866\r
+.set CYREG_B0_UDB04_05_D1, 0x40006868\r
+.set CYREG_B0_UDB05_06_D1, 0x4000686a\r
+.set CYREG_B0_UDB06_07_D1, 0x4000686c\r
+.set CYREG_B0_UDB07_08_D1, 0x4000686e\r
+.set CYREG_B0_UDB08_09_D1, 0x40006870\r
+.set CYREG_B0_UDB09_10_D1, 0x40006872\r
+.set CYREG_B0_UDB10_11_D1, 0x40006874\r
+.set CYREG_B0_UDB11_12_D1, 0x40006876\r
+.set CYREG_B0_UDB12_13_D1, 0x40006878\r
+.set CYREG_B0_UDB13_14_D1, 0x4000687a\r
+.set CYREG_B0_UDB14_15_D1, 0x4000687c\r
+.set CYREG_B0_UDB00_01_F0, 0x40006880\r
+.set CYREG_B0_UDB01_02_F0, 0x40006882\r
+.set CYREG_B0_UDB02_03_F0, 0x40006884\r
+.set CYREG_B0_UDB03_04_F0, 0x40006886\r
+.set CYREG_B0_UDB04_05_F0, 0x40006888\r
+.set CYREG_B0_UDB05_06_F0, 0x4000688a\r
+.set CYREG_B0_UDB06_07_F0, 0x4000688c\r
+.set CYREG_B0_UDB07_08_F0, 0x4000688e\r
+.set CYREG_B0_UDB08_09_F0, 0x40006890\r
+.set CYREG_B0_UDB09_10_F0, 0x40006892\r
+.set CYREG_B0_UDB10_11_F0, 0x40006894\r
+.set CYREG_B0_UDB11_12_F0, 0x40006896\r
+.set CYREG_B0_UDB12_13_F0, 0x40006898\r
+.set CYREG_B0_UDB13_14_F0, 0x4000689a\r
+.set CYREG_B0_UDB14_15_F0, 0x4000689c\r
+.set CYREG_B0_UDB00_01_F1, 0x400068a0\r
+.set CYREG_B0_UDB01_02_F1, 0x400068a2\r
+.set CYREG_B0_UDB02_03_F1, 0x400068a4\r
+.set CYREG_B0_UDB03_04_F1, 0x400068a6\r
+.set CYREG_B0_UDB04_05_F1, 0x400068a8\r
+.set CYREG_B0_UDB05_06_F1, 0x400068aa\r
+.set CYREG_B0_UDB06_07_F1, 0x400068ac\r
+.set CYREG_B0_UDB07_08_F1, 0x400068ae\r
+.set CYREG_B0_UDB08_09_F1, 0x400068b0\r
+.set CYREG_B0_UDB09_10_F1, 0x400068b2\r
+.set CYREG_B0_UDB10_11_F1, 0x400068b4\r
+.set CYREG_B0_UDB11_12_F1, 0x400068b6\r
+.set CYREG_B0_UDB12_13_F1, 0x400068b8\r
+.set CYREG_B0_UDB13_14_F1, 0x400068ba\r
+.set CYREG_B0_UDB14_15_F1, 0x400068bc\r
+.set CYREG_B0_UDB00_01_ST, 0x400068c0\r
+.set CYREG_B0_UDB01_02_ST, 0x400068c2\r
+.set CYREG_B0_UDB02_03_ST, 0x400068c4\r
+.set CYREG_B0_UDB03_04_ST, 0x400068c6\r
+.set CYREG_B0_UDB04_05_ST, 0x400068c8\r
+.set CYREG_B0_UDB05_06_ST, 0x400068ca\r
+.set CYREG_B0_UDB06_07_ST, 0x400068cc\r
+.set CYREG_B0_UDB07_08_ST, 0x400068ce\r
+.set CYREG_B0_UDB08_09_ST, 0x400068d0\r
+.set CYREG_B0_UDB09_10_ST, 0x400068d2\r
+.set CYREG_B0_UDB10_11_ST, 0x400068d4\r
+.set CYREG_B0_UDB11_12_ST, 0x400068d6\r
+.set CYREG_B0_UDB12_13_ST, 0x400068d8\r
+.set CYREG_B0_UDB13_14_ST, 0x400068da\r
+.set CYREG_B0_UDB14_15_ST, 0x400068dc\r
+.set CYREG_B0_UDB00_01_CTL, 0x400068e0\r
+.set CYREG_B0_UDB01_02_CTL, 0x400068e2\r
+.set CYREG_B0_UDB02_03_CTL, 0x400068e4\r
+.set CYREG_B0_UDB03_04_CTL, 0x400068e6\r
+.set CYREG_B0_UDB04_05_CTL, 0x400068e8\r
+.set CYREG_B0_UDB05_06_CTL, 0x400068ea\r
+.set CYREG_B0_UDB06_07_CTL, 0x400068ec\r
+.set CYREG_B0_UDB07_08_CTL, 0x400068ee\r
+.set CYREG_B0_UDB08_09_CTL, 0x400068f0\r
+.set CYREG_B0_UDB09_10_CTL, 0x400068f2\r
+.set CYREG_B0_UDB10_11_CTL, 0x400068f4\r
+.set CYREG_B0_UDB11_12_CTL, 0x400068f6\r
+.set CYREG_B0_UDB12_13_CTL, 0x400068f8\r
+.set CYREG_B0_UDB13_14_CTL, 0x400068fa\r
+.set CYREG_B0_UDB14_15_CTL, 0x400068fc\r
+.set CYREG_B0_UDB00_01_MSK, 0x40006900\r
+.set CYREG_B0_UDB01_02_MSK, 0x40006902\r
+.set CYREG_B0_UDB02_03_MSK, 0x40006904\r
+.set CYREG_B0_UDB03_04_MSK, 0x40006906\r
+.set CYREG_B0_UDB04_05_MSK, 0x40006908\r
+.set CYREG_B0_UDB05_06_MSK, 0x4000690a\r
+.set CYREG_B0_UDB06_07_MSK, 0x4000690c\r
+.set CYREG_B0_UDB07_08_MSK, 0x4000690e\r
+.set CYREG_B0_UDB08_09_MSK, 0x40006910\r
+.set CYREG_B0_UDB09_10_MSK, 0x40006912\r
+.set CYREG_B0_UDB10_11_MSK, 0x40006914\r
+.set CYREG_B0_UDB11_12_MSK, 0x40006916\r
+.set CYREG_B0_UDB12_13_MSK, 0x40006918\r
+.set CYREG_B0_UDB13_14_MSK, 0x4000691a\r
+.set CYREG_B0_UDB14_15_MSK, 0x4000691c\r
+.set CYREG_B0_UDB00_01_ACTL, 0x40006920\r
+.set CYREG_B0_UDB01_02_ACTL, 0x40006922\r
+.set CYREG_B0_UDB02_03_ACTL, 0x40006924\r
+.set CYREG_B0_UDB03_04_ACTL, 0x40006926\r
+.set CYREG_B0_UDB04_05_ACTL, 0x40006928\r
+.set CYREG_B0_UDB05_06_ACTL, 0x4000692a\r
+.set CYREG_B0_UDB06_07_ACTL, 0x4000692c\r
+.set CYREG_B0_UDB07_08_ACTL, 0x4000692e\r
+.set CYREG_B0_UDB08_09_ACTL, 0x40006930\r
+.set CYREG_B0_UDB09_10_ACTL, 0x40006932\r
+.set CYREG_B0_UDB10_11_ACTL, 0x40006934\r
+.set CYREG_B0_UDB11_12_ACTL, 0x40006936\r
+.set CYREG_B0_UDB12_13_ACTL, 0x40006938\r
+.set CYREG_B0_UDB13_14_ACTL, 0x4000693a\r
+.set CYREG_B0_UDB14_15_ACTL, 0x4000693c\r
+.set CYREG_B0_UDB00_01_MC, 0x40006940\r
+.set CYREG_B0_UDB01_02_MC, 0x40006942\r
+.set CYREG_B0_UDB02_03_MC, 0x40006944\r
+.set CYREG_B0_UDB03_04_MC, 0x40006946\r
+.set CYREG_B0_UDB04_05_MC, 0x40006948\r
+.set CYREG_B0_UDB05_06_MC, 0x4000694a\r
+.set CYREG_B0_UDB06_07_MC, 0x4000694c\r
+.set CYREG_B0_UDB07_08_MC, 0x4000694e\r
+.set CYREG_B0_UDB08_09_MC, 0x40006950\r
+.set CYREG_B0_UDB09_10_MC, 0x40006952\r
+.set CYREG_B0_UDB10_11_MC, 0x40006954\r
+.set CYREG_B0_UDB11_12_MC, 0x40006956\r
+.set CYREG_B0_UDB12_13_MC, 0x40006958\r
+.set CYREG_B0_UDB13_14_MC, 0x4000695a\r
+.set CYREG_B0_UDB14_15_MC, 0x4000695c\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00\r
+.set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e\r
+.set CYREG_B1_UDB04_05_A0, 0x40006a08\r
+.set CYREG_B1_UDB05_06_A0, 0x40006a0a\r
+.set CYREG_B1_UDB06_07_A0, 0x40006a0c\r
+.set CYREG_B1_UDB07_08_A0, 0x40006a0e\r
+.set CYREG_B1_UDB08_09_A0, 0x40006a10\r
+.set CYREG_B1_UDB09_10_A0, 0x40006a12\r
+.set CYREG_B1_UDB10_11_A0, 0x40006a14\r
+.set CYREG_B1_UDB11_12_A0, 0x40006a16\r
+.set CYREG_B1_UDB04_05_A1, 0x40006a28\r
+.set CYREG_B1_UDB05_06_A1, 0x40006a2a\r
+.set CYREG_B1_UDB06_07_A1, 0x40006a2c\r
+.set CYREG_B1_UDB07_08_A1, 0x40006a2e\r
+.set CYREG_B1_UDB08_09_A1, 0x40006a30\r
+.set CYREG_B1_UDB09_10_A1, 0x40006a32\r
+.set CYREG_B1_UDB10_11_A1, 0x40006a34\r
+.set CYREG_B1_UDB11_12_A1, 0x40006a36\r
+.set CYREG_B1_UDB04_05_D0, 0x40006a48\r
+.set CYREG_B1_UDB05_06_D0, 0x40006a4a\r
+.set CYREG_B1_UDB06_07_D0, 0x40006a4c\r
+.set CYREG_B1_UDB07_08_D0, 0x40006a4e\r
+.set CYREG_B1_UDB08_09_D0, 0x40006a50\r
+.set CYREG_B1_UDB09_10_D0, 0x40006a52\r
+.set CYREG_B1_UDB10_11_D0, 0x40006a54\r
+.set CYREG_B1_UDB11_12_D0, 0x40006a56\r
+.set CYREG_B1_UDB04_05_D1, 0x40006a68\r
+.set CYREG_B1_UDB05_06_D1, 0x40006a6a\r
+.set CYREG_B1_UDB06_07_D1, 0x40006a6c\r
+.set CYREG_B1_UDB07_08_D1, 0x40006a6e\r
+.set CYREG_B1_UDB08_09_D1, 0x40006a70\r
+.set CYREG_B1_UDB09_10_D1, 0x40006a72\r
+.set CYREG_B1_UDB10_11_D1, 0x40006a74\r
+.set CYREG_B1_UDB11_12_D1, 0x40006a76\r
+.set CYREG_B1_UDB04_05_F0, 0x40006a88\r
+.set CYREG_B1_UDB05_06_F0, 0x40006a8a\r
+.set CYREG_B1_UDB06_07_F0, 0x40006a8c\r
+.set CYREG_B1_UDB07_08_F0, 0x40006a8e\r
+.set CYREG_B1_UDB08_09_F0, 0x40006a90\r
+.set CYREG_B1_UDB09_10_F0, 0x40006a92\r
+.set CYREG_B1_UDB10_11_F0, 0x40006a94\r
+.set CYREG_B1_UDB11_12_F0, 0x40006a96\r
+.set CYREG_B1_UDB04_05_F1, 0x40006aa8\r
+.set CYREG_B1_UDB05_06_F1, 0x40006aaa\r
+.set CYREG_B1_UDB06_07_F1, 0x40006aac\r
+.set CYREG_B1_UDB07_08_F1, 0x40006aae\r
+.set CYREG_B1_UDB08_09_F1, 0x40006ab0\r
+.set CYREG_B1_UDB09_10_F1, 0x40006ab2\r
+.set CYREG_B1_UDB10_11_F1, 0x40006ab4\r
+.set CYREG_B1_UDB11_12_F1, 0x40006ab6\r
+.set CYREG_B1_UDB04_05_ST, 0x40006ac8\r
+.set CYREG_B1_UDB05_06_ST, 0x40006aca\r
+.set CYREG_B1_UDB06_07_ST, 0x40006acc\r
+.set CYREG_B1_UDB07_08_ST, 0x40006ace\r
+.set CYREG_B1_UDB08_09_ST, 0x40006ad0\r
+.set CYREG_B1_UDB09_10_ST, 0x40006ad2\r
+.set CYREG_B1_UDB10_11_ST, 0x40006ad4\r
+.set CYREG_B1_UDB11_12_ST, 0x40006ad6\r
+.set CYREG_B1_UDB04_05_CTL, 0x40006ae8\r
+.set CYREG_B1_UDB05_06_CTL, 0x40006aea\r
+.set CYREG_B1_UDB06_07_CTL, 0x40006aec\r
+.set CYREG_B1_UDB07_08_CTL, 0x40006aee\r
+.set CYREG_B1_UDB08_09_CTL, 0x40006af0\r
+.set CYREG_B1_UDB09_10_CTL, 0x40006af2\r
+.set CYREG_B1_UDB10_11_CTL, 0x40006af4\r
+.set CYREG_B1_UDB11_12_CTL, 0x40006af6\r
+.set CYREG_B1_UDB04_05_MSK, 0x40006b08\r
+.set CYREG_B1_UDB05_06_MSK, 0x40006b0a\r
+.set CYREG_B1_UDB06_07_MSK, 0x40006b0c\r
+.set CYREG_B1_UDB07_08_MSK, 0x40006b0e\r
+.set CYREG_B1_UDB08_09_MSK, 0x40006b10\r
+.set CYREG_B1_UDB09_10_MSK, 0x40006b12\r
+.set CYREG_B1_UDB10_11_MSK, 0x40006b14\r
+.set CYREG_B1_UDB11_12_MSK, 0x40006b16\r
+.set CYREG_B1_UDB04_05_ACTL, 0x40006b28\r
+.set CYREG_B1_UDB05_06_ACTL, 0x40006b2a\r
+.set CYREG_B1_UDB06_07_ACTL, 0x40006b2c\r
+.set CYREG_B1_UDB07_08_ACTL, 0x40006b2e\r
+.set CYREG_B1_UDB08_09_ACTL, 0x40006b30\r
+.set CYREG_B1_UDB09_10_ACTL, 0x40006b32\r
+.set CYREG_B1_UDB10_11_ACTL, 0x40006b34\r
+.set CYREG_B1_UDB11_12_ACTL, 0x40006b36\r
+.set CYREG_B1_UDB04_05_MC, 0x40006b48\r
+.set CYREG_B1_UDB05_06_MC, 0x40006b4a\r
+.set CYREG_B1_UDB06_07_MC, 0x40006b4c\r
+.set CYREG_B1_UDB07_08_MC, 0x40006b4e\r
+.set CYREG_B1_UDB08_09_MC, 0x40006b50\r
+.set CYREG_B1_UDB09_10_MC, 0x40006b52\r
+.set CYREG_B1_UDB10_11_MC, 0x40006b54\r
+.set CYREG_B1_UDB11_12_MC, 0x40006b56\r
+.set CYDEV_PHUB_BASE, 0x40007000\r
+.set CYDEV_PHUB_SIZE, 0x00000c00\r
+.set CYREG_PHUB_CFG, 0x40007000\r
+.set CYREG_PHUB_ERR, 0x40007004\r
+.set CYREG_PHUB_ERR_ADR, 0x40007008\r
+.set CYDEV_PHUB_CH0_BASE, 0x40007010\r
+.set CYDEV_PHUB_CH0_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH0_BASIC_CFG, 0x40007010\r
+.set CYREG_PHUB_CH0_ACTION, 0x40007014\r
+.set CYREG_PHUB_CH0_BASIC_STATUS, 0x40007018\r
+.set CYDEV_PHUB_CH1_BASE, 0x40007020\r
+.set CYDEV_PHUB_CH1_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH1_BASIC_CFG, 0x40007020\r
+.set CYREG_PHUB_CH1_ACTION, 0x40007024\r
+.set CYREG_PHUB_CH1_BASIC_STATUS, 0x40007028\r
+.set CYDEV_PHUB_CH2_BASE, 0x40007030\r
+.set CYDEV_PHUB_CH2_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH2_BASIC_CFG, 0x40007030\r
+.set CYREG_PHUB_CH2_ACTION, 0x40007034\r
+.set CYREG_PHUB_CH2_BASIC_STATUS, 0x40007038\r
+.set CYDEV_PHUB_CH3_BASE, 0x40007040\r
+.set CYDEV_PHUB_CH3_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH3_BASIC_CFG, 0x40007040\r
+.set CYREG_PHUB_CH3_ACTION, 0x40007044\r
+.set CYREG_PHUB_CH3_BASIC_STATUS, 0x40007048\r
+.set CYDEV_PHUB_CH4_BASE, 0x40007050\r
+.set CYDEV_PHUB_CH4_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH4_BASIC_CFG, 0x40007050\r
+.set CYREG_PHUB_CH4_ACTION, 0x40007054\r
+.set CYREG_PHUB_CH4_BASIC_STATUS, 0x40007058\r
+.set CYDEV_PHUB_CH5_BASE, 0x40007060\r
+.set CYDEV_PHUB_CH5_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH5_BASIC_CFG, 0x40007060\r
+.set CYREG_PHUB_CH5_ACTION, 0x40007064\r
+.set CYREG_PHUB_CH5_BASIC_STATUS, 0x40007068\r
+.set CYDEV_PHUB_CH6_BASE, 0x40007070\r
+.set CYDEV_PHUB_CH6_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH6_BASIC_CFG, 0x40007070\r
+.set CYREG_PHUB_CH6_ACTION, 0x40007074\r
+.set CYREG_PHUB_CH6_BASIC_STATUS, 0x40007078\r
+.set CYDEV_PHUB_CH7_BASE, 0x40007080\r
+.set CYDEV_PHUB_CH7_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH7_BASIC_CFG, 0x40007080\r
+.set CYREG_PHUB_CH7_ACTION, 0x40007084\r
+.set CYREG_PHUB_CH7_BASIC_STATUS, 0x40007088\r
+.set CYDEV_PHUB_CH8_BASE, 0x40007090\r
+.set CYDEV_PHUB_CH8_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH8_BASIC_CFG, 0x40007090\r
+.set CYREG_PHUB_CH8_ACTION, 0x40007094\r
+.set CYREG_PHUB_CH8_BASIC_STATUS, 0x40007098\r
+.set CYDEV_PHUB_CH9_BASE, 0x400070a0\r
+.set CYDEV_PHUB_CH9_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH9_BASIC_CFG, 0x400070a0\r
+.set CYREG_PHUB_CH9_ACTION, 0x400070a4\r
+.set CYREG_PHUB_CH9_BASIC_STATUS, 0x400070a8\r
+.set CYDEV_PHUB_CH10_BASE, 0x400070b0\r
+.set CYDEV_PHUB_CH10_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH10_BASIC_CFG, 0x400070b0\r
+.set CYREG_PHUB_CH10_ACTION, 0x400070b4\r
+.set CYREG_PHUB_CH10_BASIC_STATUS, 0x400070b8\r
+.set CYDEV_PHUB_CH11_BASE, 0x400070c0\r
+.set CYDEV_PHUB_CH11_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH11_BASIC_CFG, 0x400070c0\r
+.set CYREG_PHUB_CH11_ACTION, 0x400070c4\r
+.set CYREG_PHUB_CH11_BASIC_STATUS, 0x400070c8\r
+.set CYDEV_PHUB_CH12_BASE, 0x400070d0\r
+.set CYDEV_PHUB_CH12_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH12_BASIC_CFG, 0x400070d0\r
+.set CYREG_PHUB_CH12_ACTION, 0x400070d4\r
+.set CYREG_PHUB_CH12_BASIC_STATUS, 0x400070d8\r
+.set CYDEV_PHUB_CH13_BASE, 0x400070e0\r
+.set CYDEV_PHUB_CH13_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH13_BASIC_CFG, 0x400070e0\r
+.set CYREG_PHUB_CH13_ACTION, 0x400070e4\r
+.set CYREG_PHUB_CH13_BASIC_STATUS, 0x400070e8\r
+.set CYDEV_PHUB_CH14_BASE, 0x400070f0\r
+.set CYDEV_PHUB_CH14_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH14_BASIC_CFG, 0x400070f0\r
+.set CYREG_PHUB_CH14_ACTION, 0x400070f4\r
+.set CYREG_PHUB_CH14_BASIC_STATUS, 0x400070f8\r
+.set CYDEV_PHUB_CH15_BASE, 0x40007100\r
+.set CYDEV_PHUB_CH15_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH15_BASIC_CFG, 0x40007100\r
+.set CYREG_PHUB_CH15_ACTION, 0x40007104\r
+.set CYREG_PHUB_CH15_BASIC_STATUS, 0x40007108\r
+.set CYDEV_PHUB_CH16_BASE, 0x40007110\r
+.set CYDEV_PHUB_CH16_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH16_BASIC_CFG, 0x40007110\r
+.set CYREG_PHUB_CH16_ACTION, 0x40007114\r
+.set CYREG_PHUB_CH16_BASIC_STATUS, 0x40007118\r
+.set CYDEV_PHUB_CH17_BASE, 0x40007120\r
+.set CYDEV_PHUB_CH17_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH17_BASIC_CFG, 0x40007120\r
+.set CYREG_PHUB_CH17_ACTION, 0x40007124\r
+.set CYREG_PHUB_CH17_BASIC_STATUS, 0x40007128\r
+.set CYDEV_PHUB_CH18_BASE, 0x40007130\r
+.set CYDEV_PHUB_CH18_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH18_BASIC_CFG, 0x40007130\r
+.set CYREG_PHUB_CH18_ACTION, 0x40007134\r
+.set CYREG_PHUB_CH18_BASIC_STATUS, 0x40007138\r
+.set CYDEV_PHUB_CH19_BASE, 0x40007140\r
+.set CYDEV_PHUB_CH19_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH19_BASIC_CFG, 0x40007140\r
+.set CYREG_PHUB_CH19_ACTION, 0x40007144\r
+.set CYREG_PHUB_CH19_BASIC_STATUS, 0x40007148\r
+.set CYDEV_PHUB_CH20_BASE, 0x40007150\r
+.set CYDEV_PHUB_CH20_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH20_BASIC_CFG, 0x40007150\r
+.set CYREG_PHUB_CH20_ACTION, 0x40007154\r
+.set CYREG_PHUB_CH20_BASIC_STATUS, 0x40007158\r
+.set CYDEV_PHUB_CH21_BASE, 0x40007160\r
+.set CYDEV_PHUB_CH21_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH21_BASIC_CFG, 0x40007160\r
+.set CYREG_PHUB_CH21_ACTION, 0x40007164\r
+.set CYREG_PHUB_CH21_BASIC_STATUS, 0x40007168\r
+.set CYDEV_PHUB_CH22_BASE, 0x40007170\r
+.set CYDEV_PHUB_CH22_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH22_BASIC_CFG, 0x40007170\r
+.set CYREG_PHUB_CH22_ACTION, 0x40007174\r
+.set CYREG_PHUB_CH22_BASIC_STATUS, 0x40007178\r
+.set CYDEV_PHUB_CH23_BASE, 0x40007180\r
+.set CYDEV_PHUB_CH23_SIZE, 0x0000000c\r
+.set CYREG_PHUB_CH23_BASIC_CFG, 0x40007180\r
+.set CYREG_PHUB_CH23_ACTION, 0x40007184\r
+.set CYREG_PHUB_CH23_BASIC_STATUS, 0x40007188\r
+.set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600\r
+.set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM0_CFG0, 0x40007600\r
+.set CYREG_PHUB_CFGMEM0_CFG1, 0x40007604\r
+.set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608\r
+.set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM1_CFG0, 0x40007608\r
+.set CYREG_PHUB_CFGMEM1_CFG1, 0x4000760c\r
+.set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610\r
+.set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM2_CFG0, 0x40007610\r
+.set CYREG_PHUB_CFGMEM2_CFG1, 0x40007614\r
+.set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618\r
+.set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM3_CFG0, 0x40007618\r
+.set CYREG_PHUB_CFGMEM3_CFG1, 0x4000761c\r
+.set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620\r
+.set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM4_CFG0, 0x40007620\r
+.set CYREG_PHUB_CFGMEM4_CFG1, 0x40007624\r
+.set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628\r
+.set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM5_CFG0, 0x40007628\r
+.set CYREG_PHUB_CFGMEM5_CFG1, 0x4000762c\r
+.set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630\r
+.set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM6_CFG0, 0x40007630\r
+.set CYREG_PHUB_CFGMEM6_CFG1, 0x40007634\r
+.set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638\r
+.set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM7_CFG0, 0x40007638\r
+.set CYREG_PHUB_CFGMEM7_CFG1, 0x4000763c\r
+.set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640\r
+.set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM8_CFG0, 0x40007640\r
+.set CYREG_PHUB_CFGMEM8_CFG1, 0x40007644\r
+.set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648\r
+.set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM9_CFG0, 0x40007648\r
+.set CYREG_PHUB_CFGMEM9_CFG1, 0x4000764c\r
+.set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650\r
+.set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM10_CFG0, 0x40007650\r
+.set CYREG_PHUB_CFGMEM10_CFG1, 0x40007654\r
+.set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658\r
+.set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM11_CFG0, 0x40007658\r
+.set CYREG_PHUB_CFGMEM11_CFG1, 0x4000765c\r
+.set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660\r
+.set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM12_CFG0, 0x40007660\r
+.set CYREG_PHUB_CFGMEM12_CFG1, 0x40007664\r
+.set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668\r
+.set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM13_CFG0, 0x40007668\r
+.set CYREG_PHUB_CFGMEM13_CFG1, 0x4000766c\r
+.set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670\r
+.set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM14_CFG0, 0x40007670\r
+.set CYREG_PHUB_CFGMEM14_CFG1, 0x40007674\r
+.set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678\r
+.set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM15_CFG0, 0x40007678\r
+.set CYREG_PHUB_CFGMEM15_CFG1, 0x4000767c\r
+.set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680\r
+.set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM16_CFG0, 0x40007680\r
+.set CYREG_PHUB_CFGMEM16_CFG1, 0x40007684\r
+.set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688\r
+.set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM17_CFG0, 0x40007688\r
+.set CYREG_PHUB_CFGMEM17_CFG1, 0x4000768c\r
+.set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690\r
+.set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM18_CFG0, 0x40007690\r
+.set CYREG_PHUB_CFGMEM18_CFG1, 0x40007694\r
+.set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698\r
+.set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM19_CFG0, 0x40007698\r
+.set CYREG_PHUB_CFGMEM19_CFG1, 0x4000769c\r
+.set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0\r
+.set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM20_CFG0, 0x400076a0\r
+.set CYREG_PHUB_CFGMEM20_CFG1, 0x400076a4\r
+.set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8\r
+.set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM21_CFG0, 0x400076a8\r
+.set CYREG_PHUB_CFGMEM21_CFG1, 0x400076ac\r
+.set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0\r
+.set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM22_CFG0, 0x400076b0\r
+.set CYREG_PHUB_CFGMEM22_CFG1, 0x400076b4\r
+.set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8\r
+.set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008\r
+.set CYREG_PHUB_CFGMEM23_CFG0, 0x400076b8\r
+.set CYREG_PHUB_CFGMEM23_CFG1, 0x400076bc\r
+.set CYDEV_PHUB_TDMEM0_BASE, 0x40007800\r
+.set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM0_ORIG_TD0, 0x40007800\r
+.set CYREG_PHUB_TDMEM0_ORIG_TD1, 0x40007804\r
+.set CYDEV_PHUB_TDMEM1_BASE, 0x40007808\r
+.set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM1_ORIG_TD0, 0x40007808\r
+.set CYREG_PHUB_TDMEM1_ORIG_TD1, 0x4000780c\r
+.set CYDEV_PHUB_TDMEM2_BASE, 0x40007810\r
+.set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM2_ORIG_TD0, 0x40007810\r
+.set CYREG_PHUB_TDMEM2_ORIG_TD1, 0x40007814\r
+.set CYDEV_PHUB_TDMEM3_BASE, 0x40007818\r
+.set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM3_ORIG_TD0, 0x40007818\r
+.set CYREG_PHUB_TDMEM3_ORIG_TD1, 0x4000781c\r
+.set CYDEV_PHUB_TDMEM4_BASE, 0x40007820\r
+.set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM4_ORIG_TD0, 0x40007820\r
+.set CYREG_PHUB_TDMEM4_ORIG_TD1, 0x40007824\r
+.set CYDEV_PHUB_TDMEM5_BASE, 0x40007828\r
+.set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM5_ORIG_TD0, 0x40007828\r
+.set CYREG_PHUB_TDMEM5_ORIG_TD1, 0x4000782c\r
+.set CYDEV_PHUB_TDMEM6_BASE, 0x40007830\r
+.set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM6_ORIG_TD0, 0x40007830\r
+.set CYREG_PHUB_TDMEM6_ORIG_TD1, 0x40007834\r
+.set CYDEV_PHUB_TDMEM7_BASE, 0x40007838\r
+.set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM7_ORIG_TD0, 0x40007838\r
+.set CYREG_PHUB_TDMEM7_ORIG_TD1, 0x4000783c\r
+.set CYDEV_PHUB_TDMEM8_BASE, 0x40007840\r
+.set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM8_ORIG_TD0, 0x40007840\r
+.set CYREG_PHUB_TDMEM8_ORIG_TD1, 0x40007844\r
+.set CYDEV_PHUB_TDMEM9_BASE, 0x40007848\r
+.set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM9_ORIG_TD0, 0x40007848\r
+.set CYREG_PHUB_TDMEM9_ORIG_TD1, 0x4000784c\r
+.set CYDEV_PHUB_TDMEM10_BASE, 0x40007850\r
+.set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM10_ORIG_TD0, 0x40007850\r
+.set CYREG_PHUB_TDMEM10_ORIG_TD1, 0x40007854\r
+.set CYDEV_PHUB_TDMEM11_BASE, 0x40007858\r
+.set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM11_ORIG_TD0, 0x40007858\r
+.set CYREG_PHUB_TDMEM11_ORIG_TD1, 0x4000785c\r
+.set CYDEV_PHUB_TDMEM12_BASE, 0x40007860\r
+.set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM12_ORIG_TD0, 0x40007860\r
+.set CYREG_PHUB_TDMEM12_ORIG_TD1, 0x40007864\r
+.set CYDEV_PHUB_TDMEM13_BASE, 0x40007868\r
+.set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM13_ORIG_TD0, 0x40007868\r
+.set CYREG_PHUB_TDMEM13_ORIG_TD1, 0x4000786c\r
+.set CYDEV_PHUB_TDMEM14_BASE, 0x40007870\r
+.set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM14_ORIG_TD0, 0x40007870\r
+.set CYREG_PHUB_TDMEM14_ORIG_TD1, 0x40007874\r
+.set CYDEV_PHUB_TDMEM15_BASE, 0x40007878\r
+.set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM15_ORIG_TD0, 0x40007878\r
+.set CYREG_PHUB_TDMEM15_ORIG_TD1, 0x4000787c\r
+.set CYDEV_PHUB_TDMEM16_BASE, 0x40007880\r
+.set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM16_ORIG_TD0, 0x40007880\r
+.set CYREG_PHUB_TDMEM16_ORIG_TD1, 0x40007884\r
+.set CYDEV_PHUB_TDMEM17_BASE, 0x40007888\r
+.set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM17_ORIG_TD0, 0x40007888\r
+.set CYREG_PHUB_TDMEM17_ORIG_TD1, 0x4000788c\r
+.set CYDEV_PHUB_TDMEM18_BASE, 0x40007890\r
+.set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM18_ORIG_TD0, 0x40007890\r
+.set CYREG_PHUB_TDMEM18_ORIG_TD1, 0x40007894\r
+.set CYDEV_PHUB_TDMEM19_BASE, 0x40007898\r
+.set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM19_ORIG_TD0, 0x40007898\r
+.set CYREG_PHUB_TDMEM19_ORIG_TD1, 0x4000789c\r
+.set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0\r
+.set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM20_ORIG_TD0, 0x400078a0\r
+.set CYREG_PHUB_TDMEM20_ORIG_TD1, 0x400078a4\r
+.set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8\r
+.set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM21_ORIG_TD0, 0x400078a8\r
+.set CYREG_PHUB_TDMEM21_ORIG_TD1, 0x400078ac\r
+.set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0\r
+.set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM22_ORIG_TD0, 0x400078b0\r
+.set CYREG_PHUB_TDMEM22_ORIG_TD1, 0x400078b4\r
+.set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8\r
+.set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM23_ORIG_TD0, 0x400078b8\r
+.set CYREG_PHUB_TDMEM23_ORIG_TD1, 0x400078bc\r
+.set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0\r
+.set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM24_ORIG_TD0, 0x400078c0\r
+.set CYREG_PHUB_TDMEM24_ORIG_TD1, 0x400078c4\r
+.set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8\r
+.set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM25_ORIG_TD0, 0x400078c8\r
+.set CYREG_PHUB_TDMEM25_ORIG_TD1, 0x400078cc\r
+.set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0\r
+.set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM26_ORIG_TD0, 0x400078d0\r
+.set CYREG_PHUB_TDMEM26_ORIG_TD1, 0x400078d4\r
+.set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8\r
+.set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM27_ORIG_TD0, 0x400078d8\r
+.set CYREG_PHUB_TDMEM27_ORIG_TD1, 0x400078dc\r
+.set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0\r
+.set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM28_ORIG_TD0, 0x400078e0\r
+.set CYREG_PHUB_TDMEM28_ORIG_TD1, 0x400078e4\r
+.set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8\r
+.set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM29_ORIG_TD0, 0x400078e8\r
+.set CYREG_PHUB_TDMEM29_ORIG_TD1, 0x400078ec\r
+.set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0\r
+.set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM30_ORIG_TD0, 0x400078f0\r
+.set CYREG_PHUB_TDMEM30_ORIG_TD1, 0x400078f4\r
+.set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8\r
+.set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM31_ORIG_TD0, 0x400078f8\r
+.set CYREG_PHUB_TDMEM31_ORIG_TD1, 0x400078fc\r
+.set CYDEV_PHUB_TDMEM32_BASE, 0x40007900\r
+.set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM32_ORIG_TD0, 0x40007900\r
+.set CYREG_PHUB_TDMEM32_ORIG_TD1, 0x40007904\r
+.set CYDEV_PHUB_TDMEM33_BASE, 0x40007908\r
+.set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM33_ORIG_TD0, 0x40007908\r
+.set CYREG_PHUB_TDMEM33_ORIG_TD1, 0x4000790c\r
+.set CYDEV_PHUB_TDMEM34_BASE, 0x40007910\r
+.set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM34_ORIG_TD0, 0x40007910\r
+.set CYREG_PHUB_TDMEM34_ORIG_TD1, 0x40007914\r
+.set CYDEV_PHUB_TDMEM35_BASE, 0x40007918\r
+.set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM35_ORIG_TD0, 0x40007918\r
+.set CYREG_PHUB_TDMEM35_ORIG_TD1, 0x4000791c\r
+.set CYDEV_PHUB_TDMEM36_BASE, 0x40007920\r
+.set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM36_ORIG_TD0, 0x40007920\r
+.set CYREG_PHUB_TDMEM36_ORIG_TD1, 0x40007924\r
+.set CYDEV_PHUB_TDMEM37_BASE, 0x40007928\r
+.set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM37_ORIG_TD0, 0x40007928\r
+.set CYREG_PHUB_TDMEM37_ORIG_TD1, 0x4000792c\r
+.set CYDEV_PHUB_TDMEM38_BASE, 0x40007930\r
+.set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM38_ORIG_TD0, 0x40007930\r
+.set CYREG_PHUB_TDMEM38_ORIG_TD1, 0x40007934\r
+.set CYDEV_PHUB_TDMEM39_BASE, 0x40007938\r
+.set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM39_ORIG_TD0, 0x40007938\r
+.set CYREG_PHUB_TDMEM39_ORIG_TD1, 0x4000793c\r
+.set CYDEV_PHUB_TDMEM40_BASE, 0x40007940\r
+.set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM40_ORIG_TD0, 0x40007940\r
+.set CYREG_PHUB_TDMEM40_ORIG_TD1, 0x40007944\r
+.set CYDEV_PHUB_TDMEM41_BASE, 0x40007948\r
+.set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM41_ORIG_TD0, 0x40007948\r
+.set CYREG_PHUB_TDMEM41_ORIG_TD1, 0x4000794c\r
+.set CYDEV_PHUB_TDMEM42_BASE, 0x40007950\r
+.set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM42_ORIG_TD0, 0x40007950\r
+.set CYREG_PHUB_TDMEM42_ORIG_TD1, 0x40007954\r
+.set CYDEV_PHUB_TDMEM43_BASE, 0x40007958\r
+.set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM43_ORIG_TD0, 0x40007958\r
+.set CYREG_PHUB_TDMEM43_ORIG_TD1, 0x4000795c\r
+.set CYDEV_PHUB_TDMEM44_BASE, 0x40007960\r
+.set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM44_ORIG_TD0, 0x40007960\r
+.set CYREG_PHUB_TDMEM44_ORIG_TD1, 0x40007964\r
+.set CYDEV_PHUB_TDMEM45_BASE, 0x40007968\r
+.set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM45_ORIG_TD0, 0x40007968\r
+.set CYREG_PHUB_TDMEM45_ORIG_TD1, 0x4000796c\r
+.set CYDEV_PHUB_TDMEM46_BASE, 0x40007970\r
+.set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM46_ORIG_TD0, 0x40007970\r
+.set CYREG_PHUB_TDMEM46_ORIG_TD1, 0x40007974\r
+.set CYDEV_PHUB_TDMEM47_BASE, 0x40007978\r
+.set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM47_ORIG_TD0, 0x40007978\r
+.set CYREG_PHUB_TDMEM47_ORIG_TD1, 0x4000797c\r
+.set CYDEV_PHUB_TDMEM48_BASE, 0x40007980\r
+.set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM48_ORIG_TD0, 0x40007980\r
+.set CYREG_PHUB_TDMEM48_ORIG_TD1, 0x40007984\r
+.set CYDEV_PHUB_TDMEM49_BASE, 0x40007988\r
+.set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM49_ORIG_TD0, 0x40007988\r
+.set CYREG_PHUB_TDMEM49_ORIG_TD1, 0x4000798c\r
+.set CYDEV_PHUB_TDMEM50_BASE, 0x40007990\r
+.set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM50_ORIG_TD0, 0x40007990\r
+.set CYREG_PHUB_TDMEM50_ORIG_TD1, 0x40007994\r
+.set CYDEV_PHUB_TDMEM51_BASE, 0x40007998\r
+.set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM51_ORIG_TD0, 0x40007998\r
+.set CYREG_PHUB_TDMEM51_ORIG_TD1, 0x4000799c\r
+.set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0\r
+.set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM52_ORIG_TD0, 0x400079a0\r
+.set CYREG_PHUB_TDMEM52_ORIG_TD1, 0x400079a4\r
+.set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8\r
+.set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM53_ORIG_TD0, 0x400079a8\r
+.set CYREG_PHUB_TDMEM53_ORIG_TD1, 0x400079ac\r
+.set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0\r
+.set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM54_ORIG_TD0, 0x400079b0\r
+.set CYREG_PHUB_TDMEM54_ORIG_TD1, 0x400079b4\r
+.set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8\r
+.set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM55_ORIG_TD0, 0x400079b8\r
+.set CYREG_PHUB_TDMEM55_ORIG_TD1, 0x400079bc\r
+.set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0\r
+.set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM56_ORIG_TD0, 0x400079c0\r
+.set CYREG_PHUB_TDMEM56_ORIG_TD1, 0x400079c4\r
+.set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8\r
+.set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM57_ORIG_TD0, 0x400079c8\r
+.set CYREG_PHUB_TDMEM57_ORIG_TD1, 0x400079cc\r
+.set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0\r
+.set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM58_ORIG_TD0, 0x400079d0\r
+.set CYREG_PHUB_TDMEM58_ORIG_TD1, 0x400079d4\r
+.set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8\r
+.set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM59_ORIG_TD0, 0x400079d8\r
+.set CYREG_PHUB_TDMEM59_ORIG_TD1, 0x400079dc\r
+.set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0\r
+.set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM60_ORIG_TD0, 0x400079e0\r
+.set CYREG_PHUB_TDMEM60_ORIG_TD1, 0x400079e4\r
+.set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8\r
+.set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM61_ORIG_TD0, 0x400079e8\r
+.set CYREG_PHUB_TDMEM61_ORIG_TD1, 0x400079ec\r
+.set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0\r
+.set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM62_ORIG_TD0, 0x400079f0\r
+.set CYREG_PHUB_TDMEM62_ORIG_TD1, 0x400079f4\r
+.set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8\r
+.set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM63_ORIG_TD0, 0x400079f8\r
+.set CYREG_PHUB_TDMEM63_ORIG_TD1, 0x400079fc\r
+.set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00\r
+.set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM64_ORIG_TD0, 0x40007a00\r
+.set CYREG_PHUB_TDMEM64_ORIG_TD1, 0x40007a04\r
+.set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08\r
+.set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM65_ORIG_TD0, 0x40007a08\r
+.set CYREG_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c\r
+.set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10\r
+.set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM66_ORIG_TD0, 0x40007a10\r
+.set CYREG_PHUB_TDMEM66_ORIG_TD1, 0x40007a14\r
+.set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18\r
+.set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM67_ORIG_TD0, 0x40007a18\r
+.set CYREG_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c\r
+.set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20\r
+.set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM68_ORIG_TD0, 0x40007a20\r
+.set CYREG_PHUB_TDMEM68_ORIG_TD1, 0x40007a24\r
+.set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28\r
+.set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM69_ORIG_TD0, 0x40007a28\r
+.set CYREG_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c\r
+.set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30\r
+.set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM70_ORIG_TD0, 0x40007a30\r
+.set CYREG_PHUB_TDMEM70_ORIG_TD1, 0x40007a34\r
+.set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38\r
+.set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM71_ORIG_TD0, 0x40007a38\r
+.set CYREG_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c\r
+.set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40\r
+.set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM72_ORIG_TD0, 0x40007a40\r
+.set CYREG_PHUB_TDMEM72_ORIG_TD1, 0x40007a44\r
+.set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48\r
+.set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM73_ORIG_TD0, 0x40007a48\r
+.set CYREG_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c\r
+.set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50\r
+.set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM74_ORIG_TD0, 0x40007a50\r
+.set CYREG_PHUB_TDMEM74_ORIG_TD1, 0x40007a54\r
+.set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58\r
+.set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM75_ORIG_TD0, 0x40007a58\r
+.set CYREG_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c\r
+.set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60\r
+.set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM76_ORIG_TD0, 0x40007a60\r
+.set CYREG_PHUB_TDMEM76_ORIG_TD1, 0x40007a64\r
+.set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68\r
+.set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM77_ORIG_TD0, 0x40007a68\r
+.set CYREG_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c\r
+.set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70\r
+.set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM78_ORIG_TD0, 0x40007a70\r
+.set CYREG_PHUB_TDMEM78_ORIG_TD1, 0x40007a74\r
+.set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78\r
+.set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM79_ORIG_TD0, 0x40007a78\r
+.set CYREG_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c\r
+.set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80\r
+.set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM80_ORIG_TD0, 0x40007a80\r
+.set CYREG_PHUB_TDMEM80_ORIG_TD1, 0x40007a84\r
+.set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88\r
+.set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM81_ORIG_TD0, 0x40007a88\r
+.set CYREG_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c\r
+.set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90\r
+.set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM82_ORIG_TD0, 0x40007a90\r
+.set CYREG_PHUB_TDMEM82_ORIG_TD1, 0x40007a94\r
+.set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98\r
+.set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM83_ORIG_TD0, 0x40007a98\r
+.set CYREG_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c\r
+.set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0\r
+.set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0\r
+.set CYREG_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4\r
+.set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8\r
+.set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8\r
+.set CYREG_PHUB_TDMEM85_ORIG_TD1, 0x40007aac\r
+.set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0\r
+.set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0\r
+.set CYREG_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4\r
+.set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8\r
+.set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8\r
+.set CYREG_PHUB_TDMEM87_ORIG_TD1, 0x40007abc\r
+.set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0\r
+.set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0\r
+.set CYREG_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4\r
+.set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8\r
+.set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8\r
+.set CYREG_PHUB_TDMEM89_ORIG_TD1, 0x40007acc\r
+.set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0\r
+.set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0\r
+.set CYREG_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4\r
+.set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8\r
+.set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8\r
+.set CYREG_PHUB_TDMEM91_ORIG_TD1, 0x40007adc\r
+.set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0\r
+.set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0\r
+.set CYREG_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4\r
+.set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8\r
+.set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8\r
+.set CYREG_PHUB_TDMEM93_ORIG_TD1, 0x40007aec\r
+.set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0\r
+.set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM94_ORIG_TD0, 0x40007af0\r
+.set CYREG_PHUB_TDMEM94_ORIG_TD1, 0x40007af4\r
+.set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8\r
+.set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM95_ORIG_TD0, 0x40007af8\r
+.set CYREG_PHUB_TDMEM95_ORIG_TD1, 0x40007afc\r
+.set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00\r
+.set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM96_ORIG_TD0, 0x40007b00\r
+.set CYREG_PHUB_TDMEM96_ORIG_TD1, 0x40007b04\r
+.set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08\r
+.set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM97_ORIG_TD0, 0x40007b08\r
+.set CYREG_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c\r
+.set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10\r
+.set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM98_ORIG_TD0, 0x40007b10\r
+.set CYREG_PHUB_TDMEM98_ORIG_TD1, 0x40007b14\r
+.set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18\r
+.set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM99_ORIG_TD0, 0x40007b18\r
+.set CYREG_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c\r
+.set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20\r
+.set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM100_ORIG_TD0, 0x40007b20\r
+.set CYREG_PHUB_TDMEM100_ORIG_TD1, 0x40007b24\r
+.set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28\r
+.set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM101_ORIG_TD0, 0x40007b28\r
+.set CYREG_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c\r
+.set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30\r
+.set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM102_ORIG_TD0, 0x40007b30\r
+.set CYREG_PHUB_TDMEM102_ORIG_TD1, 0x40007b34\r
+.set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38\r
+.set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM103_ORIG_TD0, 0x40007b38\r
+.set CYREG_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c\r
+.set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40\r
+.set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM104_ORIG_TD0, 0x40007b40\r
+.set CYREG_PHUB_TDMEM104_ORIG_TD1, 0x40007b44\r
+.set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48\r
+.set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM105_ORIG_TD0, 0x40007b48\r
+.set CYREG_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c\r
+.set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50\r
+.set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM106_ORIG_TD0, 0x40007b50\r
+.set CYREG_PHUB_TDMEM106_ORIG_TD1, 0x40007b54\r
+.set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58\r
+.set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM107_ORIG_TD0, 0x40007b58\r
+.set CYREG_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c\r
+.set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60\r
+.set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM108_ORIG_TD0, 0x40007b60\r
+.set CYREG_PHUB_TDMEM108_ORIG_TD1, 0x40007b64\r
+.set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68\r
+.set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM109_ORIG_TD0, 0x40007b68\r
+.set CYREG_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c\r
+.set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70\r
+.set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM110_ORIG_TD0, 0x40007b70\r
+.set CYREG_PHUB_TDMEM110_ORIG_TD1, 0x40007b74\r
+.set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78\r
+.set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM111_ORIG_TD0, 0x40007b78\r
+.set CYREG_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c\r
+.set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80\r
+.set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM112_ORIG_TD0, 0x40007b80\r
+.set CYREG_PHUB_TDMEM112_ORIG_TD1, 0x40007b84\r
+.set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88\r
+.set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM113_ORIG_TD0, 0x40007b88\r
+.set CYREG_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c\r
+.set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90\r
+.set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM114_ORIG_TD0, 0x40007b90\r
+.set CYREG_PHUB_TDMEM114_ORIG_TD1, 0x40007b94\r
+.set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98\r
+.set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM115_ORIG_TD0, 0x40007b98\r
+.set CYREG_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c\r
+.set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0\r
+.set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0\r
+.set CYREG_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4\r
+.set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8\r
+.set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8\r
+.set CYREG_PHUB_TDMEM117_ORIG_TD1, 0x40007bac\r
+.set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0\r
+.set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0\r
+.set CYREG_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4\r
+.set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8\r
+.set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8\r
+.set CYREG_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc\r
+.set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0\r
+.set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0\r
+.set CYREG_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4\r
+.set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8\r
+.set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8\r
+.set CYREG_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc\r
+.set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0\r
+.set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0\r
+.set CYREG_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4\r
+.set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8\r
+.set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8\r
+.set CYREG_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc\r
+.set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0\r
+.set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM124_ORIG_TD0, 0x40007be0\r
+.set CYREG_PHUB_TDMEM124_ORIG_TD1, 0x40007be4\r
+.set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8\r
+.set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM125_ORIG_TD0, 0x40007be8\r
+.set CYREG_PHUB_TDMEM125_ORIG_TD1, 0x40007bec\r
+.set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0\r
+.set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0\r
+.set CYREG_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4\r
+.set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8\r
+.set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008\r
+.set CYREG_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8\r
+.set CYREG_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc\r
+.set CYDEV_EE_BASE, 0x40008000\r
+.set CYDEV_EE_SIZE, 0x00000800\r
+.set CYREG_EE_DATA_MBASE, 0x40008000\r
+.set CYREG_EE_DATA_MSIZE, 0x00000800\r
+.set CYDEV_CAN0_BASE, 0x4000a000\r
+.set CYDEV_CAN0_SIZE, 0x000002a0\r
+.set CYDEV_CAN0_CSR_BASE, 0x4000a000\r
+.set CYDEV_CAN0_CSR_SIZE, 0x00000018\r
+.set CYREG_CAN0_CSR_INT_SR, 0x4000a000\r
+.set CYREG_CAN0_CSR_INT_EN, 0x4000a004\r
+.set CYREG_CAN0_CSR_BUF_SR, 0x4000a008\r
+.set CYREG_CAN0_CSR_ERR_SR, 0x4000a00c\r
+.set CYREG_CAN0_CSR_CMD, 0x4000a010\r
+.set CYREG_CAN0_CSR_CFG, 0x4000a014\r
+.set CYDEV_CAN0_TX0_BASE, 0x4000a020\r
+.set CYDEV_CAN0_TX0_SIZE, 0x00000010\r
+.set CYREG_CAN0_TX0_CMD, 0x4000a020\r
+.set CYREG_CAN0_TX0_ID, 0x4000a024\r
+.set CYREG_CAN0_TX0_DH, 0x4000a028\r
+.set CYREG_CAN0_TX0_DL, 0x4000a02c\r
+.set CYDEV_CAN0_TX1_BASE, 0x4000a030\r
+.set CYDEV_CAN0_TX1_SIZE, 0x00000010\r
+.set CYREG_CAN0_TX1_CMD, 0x4000a030\r
+.set CYREG_CAN0_TX1_ID, 0x4000a034\r
+.set CYREG_CAN0_TX1_DH, 0x4000a038\r
+.set CYREG_CAN0_TX1_DL, 0x4000a03c\r
+.set CYDEV_CAN0_TX2_BASE, 0x4000a040\r
+.set CYDEV_CAN0_TX2_SIZE, 0x00000010\r
+.set CYREG_CAN0_TX2_CMD, 0x4000a040\r
+.set CYREG_CAN0_TX2_ID, 0x4000a044\r
+.set CYREG_CAN0_TX2_DH, 0x4000a048\r
+.set CYREG_CAN0_TX2_DL, 0x4000a04c\r
+.set CYDEV_CAN0_TX3_BASE, 0x4000a050\r
+.set CYDEV_CAN0_TX3_SIZE, 0x00000010\r
+.set CYREG_CAN0_TX3_CMD, 0x4000a050\r
+.set CYREG_CAN0_TX3_ID, 0x4000a054\r
+.set CYREG_CAN0_TX3_DH, 0x4000a058\r
+.set CYREG_CAN0_TX3_DL, 0x4000a05c\r
+.set CYDEV_CAN0_TX4_BASE, 0x4000a060\r
+.set CYDEV_CAN0_TX4_SIZE, 0x00000010\r
+.set CYREG_CAN0_TX4_CMD, 0x4000a060\r
+.set CYREG_CAN0_TX4_ID, 0x4000a064\r
+.set CYREG_CAN0_TX4_DH, 0x4000a068\r
+.set CYREG_CAN0_TX4_DL, 0x4000a06c\r
+.set CYDEV_CAN0_TX5_BASE, 0x4000a070\r
+.set CYDEV_CAN0_TX5_SIZE, 0x00000010\r
+.set CYREG_CAN0_TX5_CMD, 0x4000a070\r
+.set CYREG_CAN0_TX5_ID, 0x4000a074\r
+.set CYREG_CAN0_TX5_DH, 0x4000a078\r
+.set CYREG_CAN0_TX5_DL, 0x4000a07c\r
+.set CYDEV_CAN0_TX6_BASE, 0x4000a080\r
+.set CYDEV_CAN0_TX6_SIZE, 0x00000010\r
+.set CYREG_CAN0_TX6_CMD, 0x4000a080\r
+.set CYREG_CAN0_TX6_ID, 0x4000a084\r
+.set CYREG_CAN0_TX6_DH, 0x4000a088\r
+.set CYREG_CAN0_TX6_DL, 0x4000a08c\r
+.set CYDEV_CAN0_TX7_BASE, 0x4000a090\r
+.set CYDEV_CAN0_TX7_SIZE, 0x00000010\r
+.set CYREG_CAN0_TX7_CMD, 0x4000a090\r
+.set CYREG_CAN0_TX7_ID, 0x4000a094\r
+.set CYREG_CAN0_TX7_DH, 0x4000a098\r
+.set CYREG_CAN0_TX7_DL, 0x4000a09c\r
+.set CYDEV_CAN0_RX0_BASE, 0x4000a0a0\r
+.set CYDEV_CAN0_RX0_SIZE, 0x00000020\r
+.set CYREG_CAN0_RX0_CMD, 0x4000a0a0\r
+.set CYREG_CAN0_RX0_ID, 0x4000a0a4\r
+.set CYREG_CAN0_RX0_DH, 0x4000a0a8\r
+.set CYREG_CAN0_RX0_DL, 0x4000a0ac\r
+.set CYREG_CAN0_RX0_AMR, 0x4000a0b0\r
+.set CYREG_CAN0_RX0_ACR, 0x4000a0b4\r
+.set CYREG_CAN0_RX0_AMRD, 0x4000a0b8\r
+.set CYREG_CAN0_RX0_ACRD, 0x4000a0bc\r
+.set CYDEV_CAN0_RX1_BASE, 0x4000a0c0\r
+.set CYDEV_CAN0_RX1_SIZE, 0x00000020\r
+.set CYREG_CAN0_RX1_CMD, 0x4000a0c0\r
+.set CYREG_CAN0_RX1_ID, 0x4000a0c4\r
+.set CYREG_CAN0_RX1_DH, 0x4000a0c8\r
+.set CYREG_CAN0_RX1_DL, 0x4000a0cc\r
+.set CYREG_CAN0_RX1_AMR, 0x4000a0d0\r
+.set CYREG_CAN0_RX1_ACR, 0x4000a0d4\r
+.set CYREG_CAN0_RX1_AMRD, 0x4000a0d8\r
+.set CYREG_CAN0_RX1_ACRD, 0x4000a0dc\r
+.set CYDEV_CAN0_RX2_BASE, 0x4000a0e0\r
+.set CYDEV_CAN0_RX2_SIZE, 0x00000020\r
+.set CYREG_CAN0_RX2_CMD, 0x4000a0e0\r
+.set CYREG_CAN0_RX2_ID, 0x4000a0e4\r
+.set CYREG_CAN0_RX2_DH, 0x4000a0e8\r
+.set CYREG_CAN0_RX2_DL, 0x4000a0ec\r
+.set CYREG_CAN0_RX2_AMR, 0x4000a0f0\r
+.set CYREG_CAN0_RX2_ACR, 0x4000a0f4\r
+.set CYREG_CAN0_RX2_AMRD, 0x4000a0f8\r
+.set CYREG_CAN0_RX2_ACRD, 0x4000a0fc\r
+.set CYDEV_CAN0_RX3_BASE, 0x4000a100\r
+.set CYDEV_CAN0_RX3_SIZE, 0x00000020\r
+.set CYREG_CAN0_RX3_CMD, 0x4000a100\r
+.set CYREG_CAN0_RX3_ID, 0x4000a104\r
+.set CYREG_CAN0_RX3_DH, 0x4000a108\r
+.set CYREG_CAN0_RX3_DL, 0x4000a10c\r
+.set CYREG_CAN0_RX3_AMR, 0x4000a110\r
+.set CYREG_CAN0_RX3_ACR, 0x4000a114\r
+.set CYREG_CAN0_RX3_AMRD, 0x4000a118\r
+.set CYREG_CAN0_RX3_ACRD, 0x4000a11c\r
+.set CYDEV_CAN0_RX4_BASE, 0x4000a120\r
+.set CYDEV_CAN0_RX4_SIZE, 0x00000020\r
+.set CYREG_CAN0_RX4_CMD, 0x4000a120\r
+.set CYREG_CAN0_RX4_ID, 0x4000a124\r
+.set CYREG_CAN0_RX4_DH, 0x4000a128\r
+.set CYREG_CAN0_RX4_DL, 0x4000a12c\r
+.set CYREG_CAN0_RX4_AMR, 0x4000a130\r
+.set CYREG_CAN0_RX4_ACR, 0x4000a134\r
+.set CYREG_CAN0_RX4_AMRD, 0x4000a138\r
+.set CYREG_CAN0_RX4_ACRD, 0x4000a13c\r
+.set CYDEV_CAN0_RX5_BASE, 0x4000a140\r
+.set CYDEV_CAN0_RX5_SIZE, 0x00000020\r
+.set CYREG_CAN0_RX5_CMD, 0x4000a140\r
+.set CYREG_CAN0_RX5_ID, 0x4000a144\r
+.set CYREG_CAN0_RX5_DH, 0x4000a148\r
+.set CYREG_CAN0_RX5_DL, 0x4000a14c\r
+.set CYREG_CAN0_RX5_AMR, 0x4000a150\r
+.set CYREG_CAN0_RX5_ACR, 0x4000a154\r
+.set CYREG_CAN0_RX5_AMRD, 0x4000a158\r
+.set CYREG_CAN0_RX5_ACRD, 0x4000a15c\r
+.set CYDEV_CAN0_RX6_BASE, 0x4000a160\r
+.set CYDEV_CAN0_RX6_SIZE, 0x00000020\r
+.set CYREG_CAN0_RX6_CMD, 0x4000a160\r
+.set CYREG_CAN0_RX6_ID, 0x4000a164\r
+.set CYREG_CAN0_RX6_DH, 0x4000a168\r
+.set CYREG_CAN0_RX6_DL, 0x4000a16c\r
+.set CYREG_CAN0_RX6_AMR, 0x4000a170\r
+.set CYREG_CAN0_RX6_ACR, 0x4000a174\r
+.set CYREG_CAN0_RX6_AMRD, 0x4000a178\r
+.set CYREG_CAN0_RX6_ACRD, 0x4000a17c\r
+.set CYDEV_CAN0_RX7_BASE, 0x4000a180\r
+.set CYDEV_CAN0_RX7_SIZE, 0x00000020\r
+.set CYREG_CAN0_RX7_CMD, 0x4000a180\r
+.set CYREG_CAN0_RX7_ID, 0x4000a184\r
+.set CYREG_CAN0_RX7_DH, 0x4000a188\r
+.set CYREG_CAN0_RX7_DL, 0x4000a18c\r
+.set CYREG_CAN0_RX7_AMR, 0x4000a190\r
+.set CYREG_CAN0_RX7_ACR, 0x4000a194\r
+.set CYREG_CAN0_RX7_AMRD, 0x4000a198\r
+.set CYREG_CAN0_RX7_ACRD, 0x4000a19c\r
+.set CYDEV_CAN0_RX8_BASE, 0x4000a1a0\r
+.set CYDEV_CAN0_RX8_SIZE, 0x00000020\r
+.set CYREG_CAN0_RX8_CMD, 0x4000a1a0\r
+.set CYREG_CAN0_RX8_ID, 0x4000a1a4\r
+.set CYREG_CAN0_RX8_DH, 0x4000a1a8\r
+.set CYREG_CAN0_RX8_DL, 0x4000a1ac\r
+.set CYREG_CAN0_RX8_AMR, 0x4000a1b0\r
+.set CYREG_CAN0_RX8_ACR, 0x4000a1b4\r
+.set CYREG_CAN0_RX8_AMRD, 0x4000a1b8\r
+.set CYREG_CAN0_RX8_ACRD, 0x4000a1bc\r
+.set CYDEV_CAN0_RX9_BASE, 0x4000a1c0\r
+.set CYDEV_CAN0_RX9_SIZE, 0x00000020\r
+.set CYREG_CAN0_RX9_CMD, 0x4000a1c0\r
+.set CYREG_CAN0_RX9_ID, 0x4000a1c4\r
+.set CYREG_CAN0_RX9_DH, 0x4000a1c8\r
+.set CYREG_CAN0_RX9_DL, 0x4000a1cc\r
+.set CYREG_CAN0_RX9_AMR, 0x4000a1d0\r
+.set CYREG_CAN0_RX9_ACR, 0x4000a1d4\r
+.set CYREG_CAN0_RX9_AMRD, 0x4000a1d8\r
+.set CYREG_CAN0_RX9_ACRD, 0x4000a1dc\r
+.set CYDEV_CAN0_RX10_BASE, 0x4000a1e0\r
+.set CYDEV_CAN0_RX10_SIZE, 0x00000020\r
+.set CYREG_CAN0_RX10_CMD, 0x4000a1e0\r
+.set CYREG_CAN0_RX10_ID, 0x4000a1e4\r
+.set CYREG_CAN0_RX10_DH, 0x4000a1e8\r
+.set CYREG_CAN0_RX10_DL, 0x4000a1ec\r
+.set CYREG_CAN0_RX10_AMR, 0x4000a1f0\r
+.set CYREG_CAN0_RX10_ACR, 0x4000a1f4\r
+.set CYREG_CAN0_RX10_AMRD, 0x4000a1f8\r
+.set CYREG_CAN0_RX10_ACRD, 0x4000a1fc\r
+.set CYDEV_CAN0_RX11_BASE, 0x4000a200\r
+.set CYDEV_CAN0_RX11_SIZE, 0x00000020\r
+.set CYREG_CAN0_RX11_CMD, 0x4000a200\r
+.set CYREG_CAN0_RX11_ID, 0x4000a204\r
+.set CYREG_CAN0_RX11_DH, 0x4000a208\r
+.set CYREG_CAN0_RX11_DL, 0x4000a20c\r
+.set CYREG_CAN0_RX11_AMR, 0x4000a210\r
+.set CYREG_CAN0_RX11_ACR, 0x4000a214\r
+.set CYREG_CAN0_RX11_AMRD, 0x4000a218\r
+.set CYREG_CAN0_RX11_ACRD, 0x4000a21c\r
+.set CYDEV_CAN0_RX12_BASE, 0x4000a220\r
+.set CYDEV_CAN0_RX12_SIZE, 0x00000020\r
+.set CYREG_CAN0_RX12_CMD, 0x4000a220\r
+.set CYREG_CAN0_RX12_ID, 0x4000a224\r
+.set CYREG_CAN0_RX12_DH, 0x4000a228\r
+.set CYREG_CAN0_RX12_DL, 0x4000a22c\r
+.set CYREG_CAN0_RX12_AMR, 0x4000a230\r
+.set CYREG_CAN0_RX12_ACR, 0x4000a234\r
+.set CYREG_CAN0_RX12_AMRD, 0x4000a238\r
+.set CYREG_CAN0_RX12_ACRD, 0x4000a23c\r
+.set CYDEV_CAN0_RX13_BASE, 0x4000a240\r
+.set CYDEV_CAN0_RX13_SIZE, 0x00000020\r
+.set CYREG_CAN0_RX13_CMD, 0x4000a240\r
+.set CYREG_CAN0_RX13_ID, 0x4000a244\r
+.set CYREG_CAN0_RX13_DH, 0x4000a248\r
+.set CYREG_CAN0_RX13_DL, 0x4000a24c\r
+.set CYREG_CAN0_RX13_AMR, 0x4000a250\r
+.set CYREG_CAN0_RX13_ACR, 0x4000a254\r
+.set CYREG_CAN0_RX13_AMRD, 0x4000a258\r
+.set CYREG_CAN0_RX13_ACRD, 0x4000a25c\r
+.set CYDEV_CAN0_RX14_BASE, 0x4000a260\r
+.set CYDEV_CAN0_RX14_SIZE, 0x00000020\r
+.set CYREG_CAN0_RX14_CMD, 0x4000a260\r
+.set CYREG_CAN0_RX14_ID, 0x4000a264\r
+.set CYREG_CAN0_RX14_DH, 0x4000a268\r
+.set CYREG_CAN0_RX14_DL, 0x4000a26c\r
+.set CYREG_CAN0_RX14_AMR, 0x4000a270\r
+.set CYREG_CAN0_RX14_ACR, 0x4000a274\r
+.set CYREG_CAN0_RX14_AMRD, 0x4000a278\r
+.set CYREG_CAN0_RX14_ACRD, 0x4000a27c\r
+.set CYDEV_CAN0_RX15_BASE, 0x4000a280\r
+.set CYDEV_CAN0_RX15_SIZE, 0x00000020\r
+.set CYREG_CAN0_RX15_CMD, 0x4000a280\r
+.set CYREG_CAN0_RX15_ID, 0x4000a284\r
+.set CYREG_CAN0_RX15_DH, 0x4000a288\r
+.set CYREG_CAN0_RX15_DL, 0x4000a28c\r
+.set CYREG_CAN0_RX15_AMR, 0x4000a290\r
+.set CYREG_CAN0_RX15_ACR, 0x4000a294\r
+.set CYREG_CAN0_RX15_AMRD, 0x4000a298\r
+.set CYREG_CAN0_RX15_ACRD, 0x4000a29c\r
+.set CYDEV_DFB0_BASE, 0x4000c000\r
+.set CYDEV_DFB0_SIZE, 0x000007b5\r
+.set CYDEV_DFB0_DPA_SRAM_BASE, 0x4000c000\r
+.set CYDEV_DFB0_DPA_SRAM_SIZE, 0x00000200\r
+.set CYREG_DFB0_DPA_SRAM_DATA_MBASE, 0x4000c000\r
+.set CYREG_DFB0_DPA_SRAM_DATA_MSIZE, 0x00000200\r
+.set CYDEV_DFB0_DPB_SRAM_BASE, 0x4000c200\r
+.set CYDEV_DFB0_DPB_SRAM_SIZE, 0x00000200\r
+.set CYREG_DFB0_DPB_SRAM_DATA_MBASE, 0x4000c200\r
+.set CYREG_DFB0_DPB_SRAM_DATA_MSIZE, 0x00000200\r
+.set CYDEV_DFB0_CSA_SRAM_BASE, 0x4000c400\r
+.set CYDEV_DFB0_CSA_SRAM_SIZE, 0x00000100\r
+.set CYREG_DFB0_CSA_SRAM_DATA_MBASE, 0x4000c400\r
+.set CYREG_DFB0_CSA_SRAM_DATA_MSIZE, 0x00000100\r
+.set CYDEV_DFB0_CSB_SRAM_BASE, 0x4000c500\r
+.set CYDEV_DFB0_CSB_SRAM_SIZE, 0x00000100\r
+.set CYREG_DFB0_CSB_SRAM_DATA_MBASE, 0x4000c500\r
+.set CYREG_DFB0_CSB_SRAM_DATA_MSIZE, 0x00000100\r
+.set CYDEV_DFB0_FSM_SRAM_BASE, 0x4000c600\r
+.set CYDEV_DFB0_FSM_SRAM_SIZE, 0x00000100\r
+.set CYREG_DFB0_FSM_SRAM_DATA_MBASE, 0x4000c600\r
+.set CYREG_DFB0_FSM_SRAM_DATA_MSIZE, 0x00000100\r
+.set CYDEV_DFB0_ACU_SRAM_BASE, 0x4000c700\r
+.set CYDEV_DFB0_ACU_SRAM_SIZE, 0x00000040\r
+.set CYREG_DFB0_ACU_SRAM_DATA_MBASE, 0x4000c700\r
+.set CYREG_DFB0_ACU_SRAM_DATA_MSIZE, 0x00000040\r
+.set CYREG_DFB0_CR, 0x4000c780\r
+.set CYREG_DFB0_SR, 0x4000c784\r
+.set CYREG_DFB0_RAM_EN, 0x4000c788\r
+.set CYREG_DFB0_RAM_DIR, 0x4000c78c\r
+.set CYREG_DFB0_SEMA, 0x4000c790\r
+.set CYREG_DFB0_DSI_CTRL, 0x4000c794\r
+.set CYREG_DFB0_INT_CTRL, 0x4000c798\r
+.set CYREG_DFB0_DMA_CTRL, 0x4000c79c\r
+.set CYREG_DFB0_STAGEA, 0x4000c7a0\r
+.set CYREG_DFB0_STAGEAM, 0x4000c7a1\r
+.set CYREG_DFB0_STAGEAH, 0x4000c7a2\r
+.set CYREG_DFB0_STAGEB, 0x4000c7a4\r
+.set CYREG_DFB0_STAGEBM, 0x4000c7a5\r
+.set CYREG_DFB0_STAGEBH, 0x4000c7a6\r
+.set CYREG_DFB0_HOLDA, 0x4000c7a8\r
+.set CYREG_DFB0_HOLDAM, 0x4000c7a9\r
+.set CYREG_DFB0_HOLDAH, 0x4000c7aa\r
+.set CYREG_DFB0_HOLDAS, 0x4000c7ab\r
+.set CYREG_DFB0_HOLDB, 0x4000c7ac\r
+.set CYREG_DFB0_HOLDBM, 0x4000c7ad\r
+.set CYREG_DFB0_HOLDBH, 0x4000c7ae\r
+.set CYREG_DFB0_HOLDBS, 0x4000c7af\r
+.set CYREG_DFB0_COHER, 0x4000c7b0\r
+.set CYREG_DFB0_DALIGN, 0x4000c7b4\r
+.set CYDEV_UCFG_BASE, 0x40010000\r
+.set CYDEV_UCFG_SIZE, 0x00005040\r
+.set CYDEV_UCFG_B0_BASE, 0x40010000\r
+.set CYDEV_UCFG_B0_SIZE, 0x00000fef\r
+.set CYDEV_UCFG_B0_P0_BASE, 0x40010000\r
+.set CYDEV_UCFG_B0_P0_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B0_P0_U0_BASE, 0x40010000\r
+.set CYDEV_UCFG_B0_P0_U0_SIZE, 0x00000070\r
+.set CYREG_B0_P0_U0_PLD_IT0, 0x40010000\r
+.set CYREG_B0_P0_U0_PLD_IT1, 0x40010004\r
+.set CYREG_B0_P0_U0_PLD_IT2, 0x40010008\r
+.set CYREG_B0_P0_U0_PLD_IT3, 0x4001000c\r
+.set CYREG_B0_P0_U0_PLD_IT4, 0x40010010\r
+.set CYREG_B0_P0_U0_PLD_IT5, 0x40010014\r
+.set CYREG_B0_P0_U0_PLD_IT6, 0x40010018\r
+.set CYREG_B0_P0_U0_PLD_IT7, 0x4001001c\r
+.set CYREG_B0_P0_U0_PLD_IT8, 0x40010020\r
+.set CYREG_B0_P0_U0_PLD_IT9, 0x40010024\r
+.set CYREG_B0_P0_U0_PLD_IT10, 0x40010028\r
+.set CYREG_B0_P0_U0_PLD_IT11, 0x4001002c\r
+.set CYREG_B0_P0_U0_PLD_ORT0, 0x40010030\r
+.set CYREG_B0_P0_U0_PLD_ORT1, 0x40010032\r
+.set CYREG_B0_P0_U0_PLD_ORT2, 0x40010034\r
+.set CYREG_B0_P0_U0_PLD_ORT3, 0x40010036\r
+.set CYREG_B0_P0_U0_MC_CFG_CEN_CONST, 0x40010038\r
+.set CYREG_B0_P0_U0_MC_CFG_XORFB, 0x4001003a\r
+.set CYREG_B0_P0_U0_MC_CFG_SET_RESET, 0x4001003c\r
+.set CYREG_B0_P0_U0_MC_CFG_BYPASS, 0x4001003e\r
+.set CYREG_B0_P0_U0_CFG0, 0x40010040\r
+.set CYREG_B0_P0_U0_CFG1, 0x40010041\r
+.set CYREG_B0_P0_U0_CFG2, 0x40010042\r
+.set CYREG_B0_P0_U0_CFG3, 0x40010043\r
+.set CYREG_B0_P0_U0_CFG4, 0x40010044\r
+.set CYREG_B0_P0_U0_CFG5, 0x40010045\r
+.set CYREG_B0_P0_U0_CFG6, 0x40010046\r
+.set CYREG_B0_P0_U0_CFG7, 0x40010047\r
+.set CYREG_B0_P0_U0_CFG8, 0x40010048\r
+.set CYREG_B0_P0_U0_CFG9, 0x40010049\r
+.set CYREG_B0_P0_U0_CFG10, 0x4001004a\r
+.set CYREG_B0_P0_U0_CFG11, 0x4001004b\r
+.set CYREG_B0_P0_U0_CFG12, 0x4001004c\r
+.set CYREG_B0_P0_U0_CFG13, 0x4001004d\r
+.set CYREG_B0_P0_U0_CFG14, 0x4001004e\r
+.set CYREG_B0_P0_U0_CFG15, 0x4001004f\r
+.set CYREG_B0_P0_U0_CFG16, 0x40010050\r
+.set CYREG_B0_P0_U0_CFG17, 0x40010051\r
+.set CYREG_B0_P0_U0_CFG18, 0x40010052\r
+.set CYREG_B0_P0_U0_CFG19, 0x40010053\r
+.set CYREG_B0_P0_U0_CFG20, 0x40010054\r
+.set CYREG_B0_P0_U0_CFG21, 0x40010055\r
+.set CYREG_B0_P0_U0_CFG22, 0x40010056\r
+.set CYREG_B0_P0_U0_CFG23, 0x40010057\r
+.set CYREG_B0_P0_U0_CFG24, 0x40010058\r
+.set CYREG_B0_P0_U0_CFG25, 0x40010059\r
+.set CYREG_B0_P0_U0_CFG26, 0x4001005a\r
+.set CYREG_B0_P0_U0_CFG27, 0x4001005b\r
+.set CYREG_B0_P0_U0_CFG28, 0x4001005c\r
+.set CYREG_B0_P0_U0_CFG29, 0x4001005d\r
+.set CYREG_B0_P0_U0_CFG30, 0x4001005e\r
+.set CYREG_B0_P0_U0_CFG31, 0x4001005f\r
+.set CYREG_B0_P0_U0_DCFG0, 0x40010060\r
+.set CYREG_B0_P0_U0_DCFG1, 0x40010062\r
+.set CYREG_B0_P0_U0_DCFG2, 0x40010064\r
+.set CYREG_B0_P0_U0_DCFG3, 0x40010066\r
+.set CYREG_B0_P0_U0_DCFG4, 0x40010068\r
+.set CYREG_B0_P0_U0_DCFG5, 0x4001006a\r
+.set CYREG_B0_P0_U0_DCFG6, 0x4001006c\r
+.set CYREG_B0_P0_U0_DCFG7, 0x4001006e\r
+.set CYDEV_UCFG_B0_P0_U1_BASE, 0x40010080\r
+.set CYDEV_UCFG_B0_P0_U1_SIZE, 0x00000070\r
+.set CYREG_B0_P0_U1_PLD_IT0, 0x40010080\r
+.set CYREG_B0_P0_U1_PLD_IT1, 0x40010084\r
+.set CYREG_B0_P0_U1_PLD_IT2, 0x40010088\r
+.set CYREG_B0_P0_U1_PLD_IT3, 0x4001008c\r
+.set CYREG_B0_P0_U1_PLD_IT4, 0x40010090\r
+.set CYREG_B0_P0_U1_PLD_IT5, 0x40010094\r
+.set CYREG_B0_P0_U1_PLD_IT6, 0x40010098\r
+.set CYREG_B0_P0_U1_PLD_IT7, 0x4001009c\r
+.set CYREG_B0_P0_U1_PLD_IT8, 0x400100a0\r
+.set CYREG_B0_P0_U1_PLD_IT9, 0x400100a4\r
+.set CYREG_B0_P0_U1_PLD_IT10, 0x400100a8\r
+.set CYREG_B0_P0_U1_PLD_IT11, 0x400100ac\r
+.set CYREG_B0_P0_U1_PLD_ORT0, 0x400100b0\r
+.set CYREG_B0_P0_U1_PLD_ORT1, 0x400100b2\r
+.set CYREG_B0_P0_U1_PLD_ORT2, 0x400100b4\r
+.set CYREG_B0_P0_U1_PLD_ORT3, 0x400100b6\r
+.set CYREG_B0_P0_U1_MC_CFG_CEN_CONST, 0x400100b8\r
+.set CYREG_B0_P0_U1_MC_CFG_XORFB, 0x400100ba\r
+.set CYREG_B0_P0_U1_MC_CFG_SET_RESET, 0x400100bc\r
+.set CYREG_B0_P0_U1_MC_CFG_BYPASS, 0x400100be\r
+.set CYREG_B0_P0_U1_CFG0, 0x400100c0\r
+.set CYREG_B0_P0_U1_CFG1, 0x400100c1\r
+.set CYREG_B0_P0_U1_CFG2, 0x400100c2\r
+.set CYREG_B0_P0_U1_CFG3, 0x400100c3\r
+.set CYREG_B0_P0_U1_CFG4, 0x400100c4\r
+.set CYREG_B0_P0_U1_CFG5, 0x400100c5\r
+.set CYREG_B0_P0_U1_CFG6, 0x400100c6\r
+.set CYREG_B0_P0_U1_CFG7, 0x400100c7\r
+.set CYREG_B0_P0_U1_CFG8, 0x400100c8\r
+.set CYREG_B0_P0_U1_CFG9, 0x400100c9\r
+.set CYREG_B0_P0_U1_CFG10, 0x400100ca\r
+.set CYREG_B0_P0_U1_CFG11, 0x400100cb\r
+.set CYREG_B0_P0_U1_CFG12, 0x400100cc\r
+.set CYREG_B0_P0_U1_CFG13, 0x400100cd\r
+.set CYREG_B0_P0_U1_CFG14, 0x400100ce\r
+.set CYREG_B0_P0_U1_CFG15, 0x400100cf\r
+.set CYREG_B0_P0_U1_CFG16, 0x400100d0\r
+.set CYREG_B0_P0_U1_CFG17, 0x400100d1\r
+.set CYREG_B0_P0_U1_CFG18, 0x400100d2\r
+.set CYREG_B0_P0_U1_CFG19, 0x400100d3\r
+.set CYREG_B0_P0_U1_CFG20, 0x400100d4\r
+.set CYREG_B0_P0_U1_CFG21, 0x400100d5\r
+.set CYREG_B0_P0_U1_CFG22, 0x400100d6\r
+.set CYREG_B0_P0_U1_CFG23, 0x400100d7\r
+.set CYREG_B0_P0_U1_CFG24, 0x400100d8\r
+.set CYREG_B0_P0_U1_CFG25, 0x400100d9\r
+.set CYREG_B0_P0_U1_CFG26, 0x400100da\r
+.set CYREG_B0_P0_U1_CFG27, 0x400100db\r
+.set CYREG_B0_P0_U1_CFG28, 0x400100dc\r
+.set CYREG_B0_P0_U1_CFG29, 0x400100dd\r
+.set CYREG_B0_P0_U1_CFG30, 0x400100de\r
+.set CYREG_B0_P0_U1_CFG31, 0x400100df\r
+.set CYREG_B0_P0_U1_DCFG0, 0x400100e0\r
+.set CYREG_B0_P0_U1_DCFG1, 0x400100e2\r
+.set CYREG_B0_P0_U1_DCFG2, 0x400100e4\r
+.set CYREG_B0_P0_U1_DCFG3, 0x400100e6\r
+.set CYREG_B0_P0_U1_DCFG4, 0x400100e8\r
+.set CYREG_B0_P0_U1_DCFG5, 0x400100ea\r
+.set CYREG_B0_P0_U1_DCFG6, 0x400100ec\r
+.set CYREG_B0_P0_U1_DCFG7, 0x400100ee\r
+.set CYDEV_UCFG_B0_P0_ROUTE_BASE, 0x40010100\r
+.set CYDEV_UCFG_B0_P0_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B0_P1_BASE, 0x40010200\r
+.set CYDEV_UCFG_B0_P1_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B0_P1_U0_BASE, 0x40010200\r
+.set CYDEV_UCFG_B0_P1_U0_SIZE, 0x00000070\r
+.set CYREG_B0_P1_U0_PLD_IT0, 0x40010200\r
+.set CYREG_B0_P1_U0_PLD_IT1, 0x40010204\r
+.set CYREG_B0_P1_U0_PLD_IT2, 0x40010208\r
+.set CYREG_B0_P1_U0_PLD_IT3, 0x4001020c\r
+.set CYREG_B0_P1_U0_PLD_IT4, 0x40010210\r
+.set CYREG_B0_P1_U0_PLD_IT5, 0x40010214\r
+.set CYREG_B0_P1_U0_PLD_IT6, 0x40010218\r
+.set CYREG_B0_P1_U0_PLD_IT7, 0x4001021c\r
+.set CYREG_B0_P1_U0_PLD_IT8, 0x40010220\r
+.set CYREG_B0_P1_U0_PLD_IT9, 0x40010224\r
+.set CYREG_B0_P1_U0_PLD_IT10, 0x40010228\r
+.set CYREG_B0_P1_U0_PLD_IT11, 0x4001022c\r
+.set CYREG_B0_P1_U0_PLD_ORT0, 0x40010230\r
+.set CYREG_B0_P1_U0_PLD_ORT1, 0x40010232\r
+.set CYREG_B0_P1_U0_PLD_ORT2, 0x40010234\r
+.set CYREG_B0_P1_U0_PLD_ORT3, 0x40010236\r
+.set CYREG_B0_P1_U0_MC_CFG_CEN_CONST, 0x40010238\r
+.set CYREG_B0_P1_U0_MC_CFG_XORFB, 0x4001023a\r
+.set CYREG_B0_P1_U0_MC_CFG_SET_RESET, 0x4001023c\r
+.set CYREG_B0_P1_U0_MC_CFG_BYPASS, 0x4001023e\r
+.set CYREG_B0_P1_U0_CFG0, 0x40010240\r
+.set CYREG_B0_P1_U0_CFG1, 0x40010241\r
+.set CYREG_B0_P1_U0_CFG2, 0x40010242\r
+.set CYREG_B0_P1_U0_CFG3, 0x40010243\r
+.set CYREG_B0_P1_U0_CFG4, 0x40010244\r
+.set CYREG_B0_P1_U0_CFG5, 0x40010245\r
+.set CYREG_B0_P1_U0_CFG6, 0x40010246\r
+.set CYREG_B0_P1_U0_CFG7, 0x40010247\r
+.set CYREG_B0_P1_U0_CFG8, 0x40010248\r
+.set CYREG_B0_P1_U0_CFG9, 0x40010249\r
+.set CYREG_B0_P1_U0_CFG10, 0x4001024a\r
+.set CYREG_B0_P1_U0_CFG11, 0x4001024b\r
+.set CYREG_B0_P1_U0_CFG12, 0x4001024c\r
+.set CYREG_B0_P1_U0_CFG13, 0x4001024d\r
+.set CYREG_B0_P1_U0_CFG14, 0x4001024e\r
+.set CYREG_B0_P1_U0_CFG15, 0x4001024f\r
+.set CYREG_B0_P1_U0_CFG16, 0x40010250\r
+.set CYREG_B0_P1_U0_CFG17, 0x40010251\r
+.set CYREG_B0_P1_U0_CFG18, 0x40010252\r
+.set CYREG_B0_P1_U0_CFG19, 0x40010253\r
+.set CYREG_B0_P1_U0_CFG20, 0x40010254\r
+.set CYREG_B0_P1_U0_CFG21, 0x40010255\r
+.set CYREG_B0_P1_U0_CFG22, 0x40010256\r
+.set CYREG_B0_P1_U0_CFG23, 0x40010257\r
+.set CYREG_B0_P1_U0_CFG24, 0x40010258\r
+.set CYREG_B0_P1_U0_CFG25, 0x40010259\r
+.set CYREG_B0_P1_U0_CFG26, 0x4001025a\r
+.set CYREG_B0_P1_U0_CFG27, 0x4001025b\r
+.set CYREG_B0_P1_U0_CFG28, 0x4001025c\r
+.set CYREG_B0_P1_U0_CFG29, 0x4001025d\r
+.set CYREG_B0_P1_U0_CFG30, 0x4001025e\r
+.set CYREG_B0_P1_U0_CFG31, 0x4001025f\r
+.set CYREG_B0_P1_U0_DCFG0, 0x40010260\r
+.set CYREG_B0_P1_U0_DCFG1, 0x40010262\r
+.set CYREG_B0_P1_U0_DCFG2, 0x40010264\r
+.set CYREG_B0_P1_U0_DCFG3, 0x40010266\r
+.set CYREG_B0_P1_U0_DCFG4, 0x40010268\r
+.set CYREG_B0_P1_U0_DCFG5, 0x4001026a\r
+.set CYREG_B0_P1_U0_DCFG6, 0x4001026c\r
+.set CYREG_B0_P1_U0_DCFG7, 0x4001026e\r
+.set CYDEV_UCFG_B0_P1_U1_BASE, 0x40010280\r
+.set CYDEV_UCFG_B0_P1_U1_SIZE, 0x00000070\r
+.set CYREG_B0_P1_U1_PLD_IT0, 0x40010280\r
+.set CYREG_B0_P1_U1_PLD_IT1, 0x40010284\r
+.set CYREG_B0_P1_U1_PLD_IT2, 0x40010288\r
+.set CYREG_B0_P1_U1_PLD_IT3, 0x4001028c\r
+.set CYREG_B0_P1_U1_PLD_IT4, 0x40010290\r
+.set CYREG_B0_P1_U1_PLD_IT5, 0x40010294\r
+.set CYREG_B0_P1_U1_PLD_IT6, 0x40010298\r
+.set CYREG_B0_P1_U1_PLD_IT7, 0x4001029c\r
+.set CYREG_B0_P1_U1_PLD_IT8, 0x400102a0\r
+.set CYREG_B0_P1_U1_PLD_IT9, 0x400102a4\r
+.set CYREG_B0_P1_U1_PLD_IT10, 0x400102a8\r
+.set CYREG_B0_P1_U1_PLD_IT11, 0x400102ac\r
+.set CYREG_B0_P1_U1_PLD_ORT0, 0x400102b0\r
+.set CYREG_B0_P1_U1_PLD_ORT1, 0x400102b2\r
+.set CYREG_B0_P1_U1_PLD_ORT2, 0x400102b4\r
+.set CYREG_B0_P1_U1_PLD_ORT3, 0x400102b6\r
+.set CYREG_B0_P1_U1_MC_CFG_CEN_CONST, 0x400102b8\r
+.set CYREG_B0_P1_U1_MC_CFG_XORFB, 0x400102ba\r
+.set CYREG_B0_P1_U1_MC_CFG_SET_RESET, 0x400102bc\r
+.set CYREG_B0_P1_U1_MC_CFG_BYPASS, 0x400102be\r
+.set CYREG_B0_P1_U1_CFG0, 0x400102c0\r
+.set CYREG_B0_P1_U1_CFG1, 0x400102c1\r
+.set CYREG_B0_P1_U1_CFG2, 0x400102c2\r
+.set CYREG_B0_P1_U1_CFG3, 0x400102c3\r
+.set CYREG_B0_P1_U1_CFG4, 0x400102c4\r
+.set CYREG_B0_P1_U1_CFG5, 0x400102c5\r
+.set CYREG_B0_P1_U1_CFG6, 0x400102c6\r
+.set CYREG_B0_P1_U1_CFG7, 0x400102c7\r
+.set CYREG_B0_P1_U1_CFG8, 0x400102c8\r
+.set CYREG_B0_P1_U1_CFG9, 0x400102c9\r
+.set CYREG_B0_P1_U1_CFG10, 0x400102ca\r
+.set CYREG_B0_P1_U1_CFG11, 0x400102cb\r
+.set CYREG_B0_P1_U1_CFG12, 0x400102cc\r
+.set CYREG_B0_P1_U1_CFG13, 0x400102cd\r
+.set CYREG_B0_P1_U1_CFG14, 0x400102ce\r
+.set CYREG_B0_P1_U1_CFG15, 0x400102cf\r
+.set CYREG_B0_P1_U1_CFG16, 0x400102d0\r
+.set CYREG_B0_P1_U1_CFG17, 0x400102d1\r
+.set CYREG_B0_P1_U1_CFG18, 0x400102d2\r
+.set CYREG_B0_P1_U1_CFG19, 0x400102d3\r
+.set CYREG_B0_P1_U1_CFG20, 0x400102d4\r
+.set CYREG_B0_P1_U1_CFG21, 0x400102d5\r
+.set CYREG_B0_P1_U1_CFG22, 0x400102d6\r
+.set CYREG_B0_P1_U1_CFG23, 0x400102d7\r
+.set CYREG_B0_P1_U1_CFG24, 0x400102d8\r
+.set CYREG_B0_P1_U1_CFG25, 0x400102d9\r
+.set CYREG_B0_P1_U1_CFG26, 0x400102da\r
+.set CYREG_B0_P1_U1_CFG27, 0x400102db\r
+.set CYREG_B0_P1_U1_CFG28, 0x400102dc\r
+.set CYREG_B0_P1_U1_CFG29, 0x400102dd\r
+.set CYREG_B0_P1_U1_CFG30, 0x400102de\r
+.set CYREG_B0_P1_U1_CFG31, 0x400102df\r
+.set CYREG_B0_P1_U1_DCFG0, 0x400102e0\r
+.set CYREG_B0_P1_U1_DCFG1, 0x400102e2\r
+.set CYREG_B0_P1_U1_DCFG2, 0x400102e4\r
+.set CYREG_B0_P1_U1_DCFG3, 0x400102e6\r
+.set CYREG_B0_P1_U1_DCFG4, 0x400102e8\r
+.set CYREG_B0_P1_U1_DCFG5, 0x400102ea\r
+.set CYREG_B0_P1_U1_DCFG6, 0x400102ec\r
+.set CYREG_B0_P1_U1_DCFG7, 0x400102ee\r
+.set CYDEV_UCFG_B0_P1_ROUTE_BASE, 0x40010300\r
+.set CYDEV_UCFG_B0_P1_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B0_P2_BASE, 0x40010400\r
+.set CYDEV_UCFG_B0_P2_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B0_P2_U0_BASE, 0x40010400\r
+.set CYDEV_UCFG_B0_P2_U0_SIZE, 0x00000070\r
+.set CYREG_B0_P2_U0_PLD_IT0, 0x40010400\r
+.set CYREG_B0_P2_U0_PLD_IT1, 0x40010404\r
+.set CYREG_B0_P2_U0_PLD_IT2, 0x40010408\r
+.set CYREG_B0_P2_U0_PLD_IT3, 0x4001040c\r
+.set CYREG_B0_P2_U0_PLD_IT4, 0x40010410\r
+.set CYREG_B0_P2_U0_PLD_IT5, 0x40010414\r
+.set CYREG_B0_P2_U0_PLD_IT6, 0x40010418\r
+.set CYREG_B0_P2_U0_PLD_IT7, 0x4001041c\r
+.set CYREG_B0_P2_U0_PLD_IT8, 0x40010420\r
+.set CYREG_B0_P2_U0_PLD_IT9, 0x40010424\r
+.set CYREG_B0_P2_U0_PLD_IT10, 0x40010428\r
+.set CYREG_B0_P2_U0_PLD_IT11, 0x4001042c\r
+.set CYREG_B0_P2_U0_PLD_ORT0, 0x40010430\r
+.set CYREG_B0_P2_U0_PLD_ORT1, 0x40010432\r
+.set CYREG_B0_P2_U0_PLD_ORT2, 0x40010434\r
+.set CYREG_B0_P2_U0_PLD_ORT3, 0x40010436\r
+.set CYREG_B0_P2_U0_MC_CFG_CEN_CONST, 0x40010438\r
+.set CYREG_B0_P2_U0_MC_CFG_XORFB, 0x4001043a\r
+.set CYREG_B0_P2_U0_MC_CFG_SET_RESET, 0x4001043c\r
+.set CYREG_B0_P2_U0_MC_CFG_BYPASS, 0x4001043e\r
+.set CYREG_B0_P2_U0_CFG0, 0x40010440\r
+.set CYREG_B0_P2_U0_CFG1, 0x40010441\r
+.set CYREG_B0_P2_U0_CFG2, 0x40010442\r
+.set CYREG_B0_P2_U0_CFG3, 0x40010443\r
+.set CYREG_B0_P2_U0_CFG4, 0x40010444\r
+.set CYREG_B0_P2_U0_CFG5, 0x40010445\r
+.set CYREG_B0_P2_U0_CFG6, 0x40010446\r
+.set CYREG_B0_P2_U0_CFG7, 0x40010447\r
+.set CYREG_B0_P2_U0_CFG8, 0x40010448\r
+.set CYREG_B0_P2_U0_CFG9, 0x40010449\r
+.set CYREG_B0_P2_U0_CFG10, 0x4001044a\r
+.set CYREG_B0_P2_U0_CFG11, 0x4001044b\r
+.set CYREG_B0_P2_U0_CFG12, 0x4001044c\r
+.set CYREG_B0_P2_U0_CFG13, 0x4001044d\r
+.set CYREG_B0_P2_U0_CFG14, 0x4001044e\r
+.set CYREG_B0_P2_U0_CFG15, 0x4001044f\r
+.set CYREG_B0_P2_U0_CFG16, 0x40010450\r
+.set CYREG_B0_P2_U0_CFG17, 0x40010451\r
+.set CYREG_B0_P2_U0_CFG18, 0x40010452\r
+.set CYREG_B0_P2_U0_CFG19, 0x40010453\r
+.set CYREG_B0_P2_U0_CFG20, 0x40010454\r
+.set CYREG_B0_P2_U0_CFG21, 0x40010455\r
+.set CYREG_B0_P2_U0_CFG22, 0x40010456\r
+.set CYREG_B0_P2_U0_CFG23, 0x40010457\r
+.set CYREG_B0_P2_U0_CFG24, 0x40010458\r
+.set CYREG_B0_P2_U0_CFG25, 0x40010459\r
+.set CYREG_B0_P2_U0_CFG26, 0x4001045a\r
+.set CYREG_B0_P2_U0_CFG27, 0x4001045b\r
+.set CYREG_B0_P2_U0_CFG28, 0x4001045c\r
+.set CYREG_B0_P2_U0_CFG29, 0x4001045d\r
+.set CYREG_B0_P2_U0_CFG30, 0x4001045e\r
+.set CYREG_B0_P2_U0_CFG31, 0x4001045f\r
+.set CYREG_B0_P2_U0_DCFG0, 0x40010460\r
+.set CYREG_B0_P2_U0_DCFG1, 0x40010462\r
+.set CYREG_B0_P2_U0_DCFG2, 0x40010464\r
+.set CYREG_B0_P2_U0_DCFG3, 0x40010466\r
+.set CYREG_B0_P2_U0_DCFG4, 0x40010468\r
+.set CYREG_B0_P2_U0_DCFG5, 0x4001046a\r
+.set CYREG_B0_P2_U0_DCFG6, 0x4001046c\r
+.set CYREG_B0_P2_U0_DCFG7, 0x4001046e\r
+.set CYDEV_UCFG_B0_P2_U1_BASE, 0x40010480\r
+.set CYDEV_UCFG_B0_P2_U1_SIZE, 0x00000070\r
+.set CYREG_B0_P2_U1_PLD_IT0, 0x40010480\r
+.set CYREG_B0_P2_U1_PLD_IT1, 0x40010484\r
+.set CYREG_B0_P2_U1_PLD_IT2, 0x40010488\r
+.set CYREG_B0_P2_U1_PLD_IT3, 0x4001048c\r
+.set CYREG_B0_P2_U1_PLD_IT4, 0x40010490\r
+.set CYREG_B0_P2_U1_PLD_IT5, 0x40010494\r
+.set CYREG_B0_P2_U1_PLD_IT6, 0x40010498\r
+.set CYREG_B0_P2_U1_PLD_IT7, 0x4001049c\r
+.set CYREG_B0_P2_U1_PLD_IT8, 0x400104a0\r
+.set CYREG_B0_P2_U1_PLD_IT9, 0x400104a4\r
+.set CYREG_B0_P2_U1_PLD_IT10, 0x400104a8\r
+.set CYREG_B0_P2_U1_PLD_IT11, 0x400104ac\r
+.set CYREG_B0_P2_U1_PLD_ORT0, 0x400104b0\r
+.set CYREG_B0_P2_U1_PLD_ORT1, 0x400104b2\r
+.set CYREG_B0_P2_U1_PLD_ORT2, 0x400104b4\r
+.set CYREG_B0_P2_U1_PLD_ORT3, 0x400104b6\r
+.set CYREG_B0_P2_U1_MC_CFG_CEN_CONST, 0x400104b8\r
+.set CYREG_B0_P2_U1_MC_CFG_XORFB, 0x400104ba\r
+.set CYREG_B0_P2_U1_MC_CFG_SET_RESET, 0x400104bc\r
+.set CYREG_B0_P2_U1_MC_CFG_BYPASS, 0x400104be\r
+.set CYREG_B0_P2_U1_CFG0, 0x400104c0\r
+.set CYREG_B0_P2_U1_CFG1, 0x400104c1\r
+.set CYREG_B0_P2_U1_CFG2, 0x400104c2\r
+.set CYREG_B0_P2_U1_CFG3, 0x400104c3\r
+.set CYREG_B0_P2_U1_CFG4, 0x400104c4\r
+.set CYREG_B0_P2_U1_CFG5, 0x400104c5\r
+.set CYREG_B0_P2_U1_CFG6, 0x400104c6\r
+.set CYREG_B0_P2_U1_CFG7, 0x400104c7\r
+.set CYREG_B0_P2_U1_CFG8, 0x400104c8\r
+.set CYREG_B0_P2_U1_CFG9, 0x400104c9\r
+.set CYREG_B0_P2_U1_CFG10, 0x400104ca\r
+.set CYREG_B0_P2_U1_CFG11, 0x400104cb\r
+.set CYREG_B0_P2_U1_CFG12, 0x400104cc\r
+.set CYREG_B0_P2_U1_CFG13, 0x400104cd\r
+.set CYREG_B0_P2_U1_CFG14, 0x400104ce\r
+.set CYREG_B0_P2_U1_CFG15, 0x400104cf\r
+.set CYREG_B0_P2_U1_CFG16, 0x400104d0\r
+.set CYREG_B0_P2_U1_CFG17, 0x400104d1\r
+.set CYREG_B0_P2_U1_CFG18, 0x400104d2\r
+.set CYREG_B0_P2_U1_CFG19, 0x400104d3\r
+.set CYREG_B0_P2_U1_CFG20, 0x400104d4\r
+.set CYREG_B0_P2_U1_CFG21, 0x400104d5\r
+.set CYREG_B0_P2_U1_CFG22, 0x400104d6\r
+.set CYREG_B0_P2_U1_CFG23, 0x400104d7\r
+.set CYREG_B0_P2_U1_CFG24, 0x400104d8\r
+.set CYREG_B0_P2_U1_CFG25, 0x400104d9\r
+.set CYREG_B0_P2_U1_CFG26, 0x400104da\r
+.set CYREG_B0_P2_U1_CFG27, 0x400104db\r
+.set CYREG_B0_P2_U1_CFG28, 0x400104dc\r
+.set CYREG_B0_P2_U1_CFG29, 0x400104dd\r
+.set CYREG_B0_P2_U1_CFG30, 0x400104de\r
+.set CYREG_B0_P2_U1_CFG31, 0x400104df\r
+.set CYREG_B0_P2_U1_DCFG0, 0x400104e0\r
+.set CYREG_B0_P2_U1_DCFG1, 0x400104e2\r
+.set CYREG_B0_P2_U1_DCFG2, 0x400104e4\r
+.set CYREG_B0_P2_U1_DCFG3, 0x400104e6\r
+.set CYREG_B0_P2_U1_DCFG4, 0x400104e8\r
+.set CYREG_B0_P2_U1_DCFG5, 0x400104ea\r
+.set CYREG_B0_P2_U1_DCFG6, 0x400104ec\r
+.set CYREG_B0_P2_U1_DCFG7, 0x400104ee\r
+.set CYDEV_UCFG_B0_P2_ROUTE_BASE, 0x40010500\r
+.set CYDEV_UCFG_B0_P2_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B0_P3_BASE, 0x40010600\r
+.set CYDEV_UCFG_B0_P3_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B0_P3_U0_BASE, 0x40010600\r
+.set CYDEV_UCFG_B0_P3_U0_SIZE, 0x00000070\r
+.set CYREG_B0_P3_U0_PLD_IT0, 0x40010600\r
+.set CYREG_B0_P3_U0_PLD_IT1, 0x40010604\r
+.set CYREG_B0_P3_U0_PLD_IT2, 0x40010608\r
+.set CYREG_B0_P3_U0_PLD_IT3, 0x4001060c\r
+.set CYREG_B0_P3_U0_PLD_IT4, 0x40010610\r
+.set CYREG_B0_P3_U0_PLD_IT5, 0x40010614\r
+.set CYREG_B0_P3_U0_PLD_IT6, 0x40010618\r
+.set CYREG_B0_P3_U0_PLD_IT7, 0x4001061c\r
+.set CYREG_B0_P3_U0_PLD_IT8, 0x40010620\r
+.set CYREG_B0_P3_U0_PLD_IT9, 0x40010624\r
+.set CYREG_B0_P3_U0_PLD_IT10, 0x40010628\r
+.set CYREG_B0_P3_U0_PLD_IT11, 0x4001062c\r
+.set CYREG_B0_P3_U0_PLD_ORT0, 0x40010630\r
+.set CYREG_B0_P3_U0_PLD_ORT1, 0x40010632\r
+.set CYREG_B0_P3_U0_PLD_ORT2, 0x40010634\r
+.set CYREG_B0_P3_U0_PLD_ORT3, 0x40010636\r
+.set CYREG_B0_P3_U0_MC_CFG_CEN_CONST, 0x40010638\r
+.set CYREG_B0_P3_U0_MC_CFG_XORFB, 0x4001063a\r
+.set CYREG_B0_P3_U0_MC_CFG_SET_RESET, 0x4001063c\r
+.set CYREG_B0_P3_U0_MC_CFG_BYPASS, 0x4001063e\r
+.set CYREG_B0_P3_U0_CFG0, 0x40010640\r
+.set CYREG_B0_P3_U0_CFG1, 0x40010641\r
+.set CYREG_B0_P3_U0_CFG2, 0x40010642\r
+.set CYREG_B0_P3_U0_CFG3, 0x40010643\r
+.set CYREG_B0_P3_U0_CFG4, 0x40010644\r
+.set CYREG_B0_P3_U0_CFG5, 0x40010645\r
+.set CYREG_B0_P3_U0_CFG6, 0x40010646\r
+.set CYREG_B0_P3_U0_CFG7, 0x40010647\r
+.set CYREG_B0_P3_U0_CFG8, 0x40010648\r
+.set CYREG_B0_P3_U0_CFG9, 0x40010649\r
+.set CYREG_B0_P3_U0_CFG10, 0x4001064a\r
+.set CYREG_B0_P3_U0_CFG11, 0x4001064b\r
+.set CYREG_B0_P3_U0_CFG12, 0x4001064c\r
+.set CYREG_B0_P3_U0_CFG13, 0x4001064d\r
+.set CYREG_B0_P3_U0_CFG14, 0x4001064e\r
+.set CYREG_B0_P3_U0_CFG15, 0x4001064f\r
+.set CYREG_B0_P3_U0_CFG16, 0x40010650\r
+.set CYREG_B0_P3_U0_CFG17, 0x40010651\r
+.set CYREG_B0_P3_U0_CFG18, 0x40010652\r
+.set CYREG_B0_P3_U0_CFG19, 0x40010653\r
+.set CYREG_B0_P3_U0_CFG20, 0x40010654\r
+.set CYREG_B0_P3_U0_CFG21, 0x40010655\r
+.set CYREG_B0_P3_U0_CFG22, 0x40010656\r
+.set CYREG_B0_P3_U0_CFG23, 0x40010657\r
+.set CYREG_B0_P3_U0_CFG24, 0x40010658\r
+.set CYREG_B0_P3_U0_CFG25, 0x40010659\r
+.set CYREG_B0_P3_U0_CFG26, 0x4001065a\r
+.set CYREG_B0_P3_U0_CFG27, 0x4001065b\r
+.set CYREG_B0_P3_U0_CFG28, 0x4001065c\r
+.set CYREG_B0_P3_U0_CFG29, 0x4001065d\r
+.set CYREG_B0_P3_U0_CFG30, 0x4001065e\r
+.set CYREG_B0_P3_U0_CFG31, 0x4001065f\r
+.set CYREG_B0_P3_U0_DCFG0, 0x40010660\r
+.set CYREG_B0_P3_U0_DCFG1, 0x40010662\r
+.set CYREG_B0_P3_U0_DCFG2, 0x40010664\r
+.set CYREG_B0_P3_U0_DCFG3, 0x40010666\r
+.set CYREG_B0_P3_U0_DCFG4, 0x40010668\r
+.set CYREG_B0_P3_U0_DCFG5, 0x4001066a\r
+.set CYREG_B0_P3_U0_DCFG6, 0x4001066c\r
+.set CYREG_B0_P3_U0_DCFG7, 0x4001066e\r
+.set CYDEV_UCFG_B0_P3_U1_BASE, 0x40010680\r
+.set CYDEV_UCFG_B0_P3_U1_SIZE, 0x00000070\r
+.set CYREG_B0_P3_U1_PLD_IT0, 0x40010680\r
+.set CYREG_B0_P3_U1_PLD_IT1, 0x40010684\r
+.set CYREG_B0_P3_U1_PLD_IT2, 0x40010688\r
+.set CYREG_B0_P3_U1_PLD_IT3, 0x4001068c\r
+.set CYREG_B0_P3_U1_PLD_IT4, 0x40010690\r
+.set CYREG_B0_P3_U1_PLD_IT5, 0x40010694\r
+.set CYREG_B0_P3_U1_PLD_IT6, 0x40010698\r
+.set CYREG_B0_P3_U1_PLD_IT7, 0x4001069c\r
+.set CYREG_B0_P3_U1_PLD_IT8, 0x400106a0\r
+.set CYREG_B0_P3_U1_PLD_IT9, 0x400106a4\r
+.set CYREG_B0_P3_U1_PLD_IT10, 0x400106a8\r
+.set CYREG_B0_P3_U1_PLD_IT11, 0x400106ac\r
+.set CYREG_B0_P3_U1_PLD_ORT0, 0x400106b0\r
+.set CYREG_B0_P3_U1_PLD_ORT1, 0x400106b2\r
+.set CYREG_B0_P3_U1_PLD_ORT2, 0x400106b4\r
+.set CYREG_B0_P3_U1_PLD_ORT3, 0x400106b6\r
+.set CYREG_B0_P3_U1_MC_CFG_CEN_CONST, 0x400106b8\r
+.set CYREG_B0_P3_U1_MC_CFG_XORFB, 0x400106ba\r
+.set CYREG_B0_P3_U1_MC_CFG_SET_RESET, 0x400106bc\r
+.set CYREG_B0_P3_U1_MC_CFG_BYPASS, 0x400106be\r
+.set CYREG_B0_P3_U1_CFG0, 0x400106c0\r
+.set CYREG_B0_P3_U1_CFG1, 0x400106c1\r
+.set CYREG_B0_P3_U1_CFG2, 0x400106c2\r
+.set CYREG_B0_P3_U1_CFG3, 0x400106c3\r
+.set CYREG_B0_P3_U1_CFG4, 0x400106c4\r
+.set CYREG_B0_P3_U1_CFG5, 0x400106c5\r
+.set CYREG_B0_P3_U1_CFG6, 0x400106c6\r
+.set CYREG_B0_P3_U1_CFG7, 0x400106c7\r
+.set CYREG_B0_P3_U1_CFG8, 0x400106c8\r
+.set CYREG_B0_P3_U1_CFG9, 0x400106c9\r
+.set CYREG_B0_P3_U1_CFG10, 0x400106ca\r
+.set CYREG_B0_P3_U1_CFG11, 0x400106cb\r
+.set CYREG_B0_P3_U1_CFG12, 0x400106cc\r
+.set CYREG_B0_P3_U1_CFG13, 0x400106cd\r
+.set CYREG_B0_P3_U1_CFG14, 0x400106ce\r
+.set CYREG_B0_P3_U1_CFG15, 0x400106cf\r
+.set CYREG_B0_P3_U1_CFG16, 0x400106d0\r
+.set CYREG_B0_P3_U1_CFG17, 0x400106d1\r
+.set CYREG_B0_P3_U1_CFG18, 0x400106d2\r
+.set CYREG_B0_P3_U1_CFG19, 0x400106d3\r
+.set CYREG_B0_P3_U1_CFG20, 0x400106d4\r
+.set CYREG_B0_P3_U1_CFG21, 0x400106d5\r
+.set CYREG_B0_P3_U1_CFG22, 0x400106d6\r
+.set CYREG_B0_P3_U1_CFG23, 0x400106d7\r
+.set CYREG_B0_P3_U1_CFG24, 0x400106d8\r
+.set CYREG_B0_P3_U1_CFG25, 0x400106d9\r
+.set CYREG_B0_P3_U1_CFG26, 0x400106da\r
+.set CYREG_B0_P3_U1_CFG27, 0x400106db\r
+.set CYREG_B0_P3_U1_CFG28, 0x400106dc\r
+.set CYREG_B0_P3_U1_CFG29, 0x400106dd\r
+.set CYREG_B0_P3_U1_CFG30, 0x400106de\r
+.set CYREG_B0_P3_U1_CFG31, 0x400106df\r
+.set CYREG_B0_P3_U1_DCFG0, 0x400106e0\r
+.set CYREG_B0_P3_U1_DCFG1, 0x400106e2\r
+.set CYREG_B0_P3_U1_DCFG2, 0x400106e4\r
+.set CYREG_B0_P3_U1_DCFG3, 0x400106e6\r
+.set CYREG_B0_P3_U1_DCFG4, 0x400106e8\r
+.set CYREG_B0_P3_U1_DCFG5, 0x400106ea\r
+.set CYREG_B0_P3_U1_DCFG6, 0x400106ec\r
+.set CYREG_B0_P3_U1_DCFG7, 0x400106ee\r
+.set CYDEV_UCFG_B0_P3_ROUTE_BASE, 0x40010700\r
+.set CYDEV_UCFG_B0_P3_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B0_P4_BASE, 0x40010800\r
+.set CYDEV_UCFG_B0_P4_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B0_P4_U0_BASE, 0x40010800\r
+.set CYDEV_UCFG_B0_P4_U0_SIZE, 0x00000070\r
+.set CYREG_B0_P4_U0_PLD_IT0, 0x40010800\r
+.set CYREG_B0_P4_U0_PLD_IT1, 0x40010804\r
+.set CYREG_B0_P4_U0_PLD_IT2, 0x40010808\r
+.set CYREG_B0_P4_U0_PLD_IT3, 0x4001080c\r
+.set CYREG_B0_P4_U0_PLD_IT4, 0x40010810\r
+.set CYREG_B0_P4_U0_PLD_IT5, 0x40010814\r
+.set CYREG_B0_P4_U0_PLD_IT6, 0x40010818\r
+.set CYREG_B0_P4_U0_PLD_IT7, 0x4001081c\r
+.set CYREG_B0_P4_U0_PLD_IT8, 0x40010820\r
+.set CYREG_B0_P4_U0_PLD_IT9, 0x40010824\r
+.set CYREG_B0_P4_U0_PLD_IT10, 0x40010828\r
+.set CYREG_B0_P4_U0_PLD_IT11, 0x4001082c\r
+.set CYREG_B0_P4_U0_PLD_ORT0, 0x40010830\r
+.set CYREG_B0_P4_U0_PLD_ORT1, 0x40010832\r
+.set CYREG_B0_P4_U0_PLD_ORT2, 0x40010834\r
+.set CYREG_B0_P4_U0_PLD_ORT3, 0x40010836\r
+.set CYREG_B0_P4_U0_MC_CFG_CEN_CONST, 0x40010838\r
+.set CYREG_B0_P4_U0_MC_CFG_XORFB, 0x4001083a\r
+.set CYREG_B0_P4_U0_MC_CFG_SET_RESET, 0x4001083c\r
+.set CYREG_B0_P4_U0_MC_CFG_BYPASS, 0x4001083e\r
+.set CYREG_B0_P4_U0_CFG0, 0x40010840\r
+.set CYREG_B0_P4_U0_CFG1, 0x40010841\r
+.set CYREG_B0_P4_U0_CFG2, 0x40010842\r
+.set CYREG_B0_P4_U0_CFG3, 0x40010843\r
+.set CYREG_B0_P4_U0_CFG4, 0x40010844\r
+.set CYREG_B0_P4_U0_CFG5, 0x40010845\r
+.set CYREG_B0_P4_U0_CFG6, 0x40010846\r
+.set CYREG_B0_P4_U0_CFG7, 0x40010847\r
+.set CYREG_B0_P4_U0_CFG8, 0x40010848\r
+.set CYREG_B0_P4_U0_CFG9, 0x40010849\r
+.set CYREG_B0_P4_U0_CFG10, 0x4001084a\r
+.set CYREG_B0_P4_U0_CFG11, 0x4001084b\r
+.set CYREG_B0_P4_U0_CFG12, 0x4001084c\r
+.set CYREG_B0_P4_U0_CFG13, 0x4001084d\r
+.set CYREG_B0_P4_U0_CFG14, 0x4001084e\r
+.set CYREG_B0_P4_U0_CFG15, 0x4001084f\r
+.set CYREG_B0_P4_U0_CFG16, 0x40010850\r
+.set CYREG_B0_P4_U0_CFG17, 0x40010851\r
+.set CYREG_B0_P4_U0_CFG18, 0x40010852\r
+.set CYREG_B0_P4_U0_CFG19, 0x40010853\r
+.set CYREG_B0_P4_U0_CFG20, 0x40010854\r
+.set CYREG_B0_P4_U0_CFG21, 0x40010855\r
+.set CYREG_B0_P4_U0_CFG22, 0x40010856\r
+.set CYREG_B0_P4_U0_CFG23, 0x40010857\r
+.set CYREG_B0_P4_U0_CFG24, 0x40010858\r
+.set CYREG_B0_P4_U0_CFG25, 0x40010859\r
+.set CYREG_B0_P4_U0_CFG26, 0x4001085a\r
+.set CYREG_B0_P4_U0_CFG27, 0x4001085b\r
+.set CYREG_B0_P4_U0_CFG28, 0x4001085c\r
+.set CYREG_B0_P4_U0_CFG29, 0x4001085d\r
+.set CYREG_B0_P4_U0_CFG30, 0x4001085e\r
+.set CYREG_B0_P4_U0_CFG31, 0x4001085f\r
+.set CYREG_B0_P4_U0_DCFG0, 0x40010860\r
+.set CYREG_B0_P4_U0_DCFG1, 0x40010862\r
+.set CYREG_B0_P4_U0_DCFG2, 0x40010864\r
+.set CYREG_B0_P4_U0_DCFG3, 0x40010866\r
+.set CYREG_B0_P4_U0_DCFG4, 0x40010868\r
+.set CYREG_B0_P4_U0_DCFG5, 0x4001086a\r
+.set CYREG_B0_P4_U0_DCFG6, 0x4001086c\r
+.set CYREG_B0_P4_U0_DCFG7, 0x4001086e\r
+.set CYDEV_UCFG_B0_P4_U1_BASE, 0x40010880\r
+.set CYDEV_UCFG_B0_P4_U1_SIZE, 0x00000070\r
+.set CYREG_B0_P4_U1_PLD_IT0, 0x40010880\r
+.set CYREG_B0_P4_U1_PLD_IT1, 0x40010884\r
+.set CYREG_B0_P4_U1_PLD_IT2, 0x40010888\r
+.set CYREG_B0_P4_U1_PLD_IT3, 0x4001088c\r
+.set CYREG_B0_P4_U1_PLD_IT4, 0x40010890\r
+.set CYREG_B0_P4_U1_PLD_IT5, 0x40010894\r
+.set CYREG_B0_P4_U1_PLD_IT6, 0x40010898\r
+.set CYREG_B0_P4_U1_PLD_IT7, 0x4001089c\r
+.set CYREG_B0_P4_U1_PLD_IT8, 0x400108a0\r
+.set CYREG_B0_P4_U1_PLD_IT9, 0x400108a4\r
+.set CYREG_B0_P4_U1_PLD_IT10, 0x400108a8\r
+.set CYREG_B0_P4_U1_PLD_IT11, 0x400108ac\r
+.set CYREG_B0_P4_U1_PLD_ORT0, 0x400108b0\r
+.set CYREG_B0_P4_U1_PLD_ORT1, 0x400108b2\r
+.set CYREG_B0_P4_U1_PLD_ORT2, 0x400108b4\r
+.set CYREG_B0_P4_U1_PLD_ORT3, 0x400108b6\r
+.set CYREG_B0_P4_U1_MC_CFG_CEN_CONST, 0x400108b8\r
+.set CYREG_B0_P4_U1_MC_CFG_XORFB, 0x400108ba\r
+.set CYREG_B0_P4_U1_MC_CFG_SET_RESET, 0x400108bc\r
+.set CYREG_B0_P4_U1_MC_CFG_BYPASS, 0x400108be\r
+.set CYREG_B0_P4_U1_CFG0, 0x400108c0\r
+.set CYREG_B0_P4_U1_CFG1, 0x400108c1\r
+.set CYREG_B0_P4_U1_CFG2, 0x400108c2\r
+.set CYREG_B0_P4_U1_CFG3, 0x400108c3\r
+.set CYREG_B0_P4_U1_CFG4, 0x400108c4\r
+.set CYREG_B0_P4_U1_CFG5, 0x400108c5\r
+.set CYREG_B0_P4_U1_CFG6, 0x400108c6\r
+.set CYREG_B0_P4_U1_CFG7, 0x400108c7\r
+.set CYREG_B0_P4_U1_CFG8, 0x400108c8\r
+.set CYREG_B0_P4_U1_CFG9, 0x400108c9\r
+.set CYREG_B0_P4_U1_CFG10, 0x400108ca\r
+.set CYREG_B0_P4_U1_CFG11, 0x400108cb\r
+.set CYREG_B0_P4_U1_CFG12, 0x400108cc\r
+.set CYREG_B0_P4_U1_CFG13, 0x400108cd\r
+.set CYREG_B0_P4_U1_CFG14, 0x400108ce\r
+.set CYREG_B0_P4_U1_CFG15, 0x400108cf\r
+.set CYREG_B0_P4_U1_CFG16, 0x400108d0\r
+.set CYREG_B0_P4_U1_CFG17, 0x400108d1\r
+.set CYREG_B0_P4_U1_CFG18, 0x400108d2\r
+.set CYREG_B0_P4_U1_CFG19, 0x400108d3\r
+.set CYREG_B0_P4_U1_CFG20, 0x400108d4\r
+.set CYREG_B0_P4_U1_CFG21, 0x400108d5\r
+.set CYREG_B0_P4_U1_CFG22, 0x400108d6\r
+.set CYREG_B0_P4_U1_CFG23, 0x400108d7\r
+.set CYREG_B0_P4_U1_CFG24, 0x400108d8\r
+.set CYREG_B0_P4_U1_CFG25, 0x400108d9\r
+.set CYREG_B0_P4_U1_CFG26, 0x400108da\r
+.set CYREG_B0_P4_U1_CFG27, 0x400108db\r
+.set CYREG_B0_P4_U1_CFG28, 0x400108dc\r
+.set CYREG_B0_P4_U1_CFG29, 0x400108dd\r
+.set CYREG_B0_P4_U1_CFG30, 0x400108de\r
+.set CYREG_B0_P4_U1_CFG31, 0x400108df\r
+.set CYREG_B0_P4_U1_DCFG0, 0x400108e0\r
+.set CYREG_B0_P4_U1_DCFG1, 0x400108e2\r
+.set CYREG_B0_P4_U1_DCFG2, 0x400108e4\r
+.set CYREG_B0_P4_U1_DCFG3, 0x400108e6\r
+.set CYREG_B0_P4_U1_DCFG4, 0x400108e8\r
+.set CYREG_B0_P4_U1_DCFG5, 0x400108ea\r
+.set CYREG_B0_P4_U1_DCFG6, 0x400108ec\r
+.set CYREG_B0_P4_U1_DCFG7, 0x400108ee\r
+.set CYDEV_UCFG_B0_P4_ROUTE_BASE, 0x40010900\r
+.set CYDEV_UCFG_B0_P4_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B0_P5_BASE, 0x40010a00\r
+.set CYDEV_UCFG_B0_P5_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B0_P5_U0_BASE, 0x40010a00\r
+.set CYDEV_UCFG_B0_P5_U0_SIZE, 0x00000070\r
+.set CYREG_B0_P5_U0_PLD_IT0, 0x40010a00\r
+.set CYREG_B0_P5_U0_PLD_IT1, 0x40010a04\r
+.set CYREG_B0_P5_U0_PLD_IT2, 0x40010a08\r
+.set CYREG_B0_P5_U0_PLD_IT3, 0x40010a0c\r
+.set CYREG_B0_P5_U0_PLD_IT4, 0x40010a10\r
+.set CYREG_B0_P5_U0_PLD_IT5, 0x40010a14\r
+.set CYREG_B0_P5_U0_PLD_IT6, 0x40010a18\r
+.set CYREG_B0_P5_U0_PLD_IT7, 0x40010a1c\r
+.set CYREG_B0_P5_U0_PLD_IT8, 0x40010a20\r
+.set CYREG_B0_P5_U0_PLD_IT9, 0x40010a24\r
+.set CYREG_B0_P5_U0_PLD_IT10, 0x40010a28\r
+.set CYREG_B0_P5_U0_PLD_IT11, 0x40010a2c\r
+.set CYREG_B0_P5_U0_PLD_ORT0, 0x40010a30\r
+.set CYREG_B0_P5_U0_PLD_ORT1, 0x40010a32\r
+.set CYREG_B0_P5_U0_PLD_ORT2, 0x40010a34\r
+.set CYREG_B0_P5_U0_PLD_ORT3, 0x40010a36\r
+.set CYREG_B0_P5_U0_MC_CFG_CEN_CONST, 0x40010a38\r
+.set CYREG_B0_P5_U0_MC_CFG_XORFB, 0x40010a3a\r
+.set CYREG_B0_P5_U0_MC_CFG_SET_RESET, 0x40010a3c\r
+.set CYREG_B0_P5_U0_MC_CFG_BYPASS, 0x40010a3e\r
+.set CYREG_B0_P5_U0_CFG0, 0x40010a40\r
+.set CYREG_B0_P5_U0_CFG1, 0x40010a41\r
+.set CYREG_B0_P5_U0_CFG2, 0x40010a42\r
+.set CYREG_B0_P5_U0_CFG3, 0x40010a43\r
+.set CYREG_B0_P5_U0_CFG4, 0x40010a44\r
+.set CYREG_B0_P5_U0_CFG5, 0x40010a45\r
+.set CYREG_B0_P5_U0_CFG6, 0x40010a46\r
+.set CYREG_B0_P5_U0_CFG7, 0x40010a47\r
+.set CYREG_B0_P5_U0_CFG8, 0x40010a48\r
+.set CYREG_B0_P5_U0_CFG9, 0x40010a49\r
+.set CYREG_B0_P5_U0_CFG10, 0x40010a4a\r
+.set CYREG_B0_P5_U0_CFG11, 0x40010a4b\r
+.set CYREG_B0_P5_U0_CFG12, 0x40010a4c\r
+.set CYREG_B0_P5_U0_CFG13, 0x40010a4d\r
+.set CYREG_B0_P5_U0_CFG14, 0x40010a4e\r
+.set CYREG_B0_P5_U0_CFG15, 0x40010a4f\r
+.set CYREG_B0_P5_U0_CFG16, 0x40010a50\r
+.set CYREG_B0_P5_U0_CFG17, 0x40010a51\r
+.set CYREG_B0_P5_U0_CFG18, 0x40010a52\r
+.set CYREG_B0_P5_U0_CFG19, 0x40010a53\r
+.set CYREG_B0_P5_U0_CFG20, 0x40010a54\r
+.set CYREG_B0_P5_U0_CFG21, 0x40010a55\r
+.set CYREG_B0_P5_U0_CFG22, 0x40010a56\r
+.set CYREG_B0_P5_U0_CFG23, 0x40010a57\r
+.set CYREG_B0_P5_U0_CFG24, 0x40010a58\r
+.set CYREG_B0_P5_U0_CFG25, 0x40010a59\r
+.set CYREG_B0_P5_U0_CFG26, 0x40010a5a\r
+.set CYREG_B0_P5_U0_CFG27, 0x40010a5b\r
+.set CYREG_B0_P5_U0_CFG28, 0x40010a5c\r
+.set CYREG_B0_P5_U0_CFG29, 0x40010a5d\r
+.set CYREG_B0_P5_U0_CFG30, 0x40010a5e\r
+.set CYREG_B0_P5_U0_CFG31, 0x40010a5f\r
+.set CYREG_B0_P5_U0_DCFG0, 0x40010a60\r
+.set CYREG_B0_P5_U0_DCFG1, 0x40010a62\r
+.set CYREG_B0_P5_U0_DCFG2, 0x40010a64\r
+.set CYREG_B0_P5_U0_DCFG3, 0x40010a66\r
+.set CYREG_B0_P5_U0_DCFG4, 0x40010a68\r
+.set CYREG_B0_P5_U0_DCFG5, 0x40010a6a\r
+.set CYREG_B0_P5_U0_DCFG6, 0x40010a6c\r
+.set CYREG_B0_P5_U0_DCFG7, 0x40010a6e\r
+.set CYDEV_UCFG_B0_P5_U1_BASE, 0x40010a80\r
+.set CYDEV_UCFG_B0_P5_U1_SIZE, 0x00000070\r
+.set CYREG_B0_P5_U1_PLD_IT0, 0x40010a80\r
+.set CYREG_B0_P5_U1_PLD_IT1, 0x40010a84\r
+.set CYREG_B0_P5_U1_PLD_IT2, 0x40010a88\r
+.set CYREG_B0_P5_U1_PLD_IT3, 0x40010a8c\r
+.set CYREG_B0_P5_U1_PLD_IT4, 0x40010a90\r
+.set CYREG_B0_P5_U1_PLD_IT5, 0x40010a94\r
+.set CYREG_B0_P5_U1_PLD_IT6, 0x40010a98\r
+.set CYREG_B0_P5_U1_PLD_IT7, 0x40010a9c\r
+.set CYREG_B0_P5_U1_PLD_IT8, 0x40010aa0\r
+.set CYREG_B0_P5_U1_PLD_IT9, 0x40010aa4\r
+.set CYREG_B0_P5_U1_PLD_IT10, 0x40010aa8\r
+.set CYREG_B0_P5_U1_PLD_IT11, 0x40010aac\r
+.set CYREG_B0_P5_U1_PLD_ORT0, 0x40010ab0\r
+.set CYREG_B0_P5_U1_PLD_ORT1, 0x40010ab2\r
+.set CYREG_B0_P5_U1_PLD_ORT2, 0x40010ab4\r
+.set CYREG_B0_P5_U1_PLD_ORT3, 0x40010ab6\r
+.set CYREG_B0_P5_U1_MC_CFG_CEN_CONST, 0x40010ab8\r
+.set CYREG_B0_P5_U1_MC_CFG_XORFB, 0x40010aba\r
+.set CYREG_B0_P5_U1_MC_CFG_SET_RESET, 0x40010abc\r
+.set CYREG_B0_P5_U1_MC_CFG_BYPASS, 0x40010abe\r
+.set CYREG_B0_P5_U1_CFG0, 0x40010ac0\r
+.set CYREG_B0_P5_U1_CFG1, 0x40010ac1\r
+.set CYREG_B0_P5_U1_CFG2, 0x40010ac2\r
+.set CYREG_B0_P5_U1_CFG3, 0x40010ac3\r
+.set CYREG_B0_P5_U1_CFG4, 0x40010ac4\r
+.set CYREG_B0_P5_U1_CFG5, 0x40010ac5\r
+.set CYREG_B0_P5_U1_CFG6, 0x40010ac6\r
+.set CYREG_B0_P5_U1_CFG7, 0x40010ac7\r
+.set CYREG_B0_P5_U1_CFG8, 0x40010ac8\r
+.set CYREG_B0_P5_U1_CFG9, 0x40010ac9\r
+.set CYREG_B0_P5_U1_CFG10, 0x40010aca\r
+.set CYREG_B0_P5_U1_CFG11, 0x40010acb\r
+.set CYREG_B0_P5_U1_CFG12, 0x40010acc\r
+.set CYREG_B0_P5_U1_CFG13, 0x40010acd\r
+.set CYREG_B0_P5_U1_CFG14, 0x40010ace\r
+.set CYREG_B0_P5_U1_CFG15, 0x40010acf\r
+.set CYREG_B0_P5_U1_CFG16, 0x40010ad0\r
+.set CYREG_B0_P5_U1_CFG17, 0x40010ad1\r
+.set CYREG_B0_P5_U1_CFG18, 0x40010ad2\r
+.set CYREG_B0_P5_U1_CFG19, 0x40010ad3\r
+.set CYREG_B0_P5_U1_CFG20, 0x40010ad4\r
+.set CYREG_B0_P5_U1_CFG21, 0x40010ad5\r
+.set CYREG_B0_P5_U1_CFG22, 0x40010ad6\r
+.set CYREG_B0_P5_U1_CFG23, 0x40010ad7\r
+.set CYREG_B0_P5_U1_CFG24, 0x40010ad8\r
+.set CYREG_B0_P5_U1_CFG25, 0x40010ad9\r
+.set CYREG_B0_P5_U1_CFG26, 0x40010ada\r
+.set CYREG_B0_P5_U1_CFG27, 0x40010adb\r
+.set CYREG_B0_P5_U1_CFG28, 0x40010adc\r
+.set CYREG_B0_P5_U1_CFG29, 0x40010add\r
+.set CYREG_B0_P5_U1_CFG30, 0x40010ade\r
+.set CYREG_B0_P5_U1_CFG31, 0x40010adf\r
+.set CYREG_B0_P5_U1_DCFG0, 0x40010ae0\r
+.set CYREG_B0_P5_U1_DCFG1, 0x40010ae2\r
+.set CYREG_B0_P5_U1_DCFG2, 0x40010ae4\r
+.set CYREG_B0_P5_U1_DCFG3, 0x40010ae6\r
+.set CYREG_B0_P5_U1_DCFG4, 0x40010ae8\r
+.set CYREG_B0_P5_U1_DCFG5, 0x40010aea\r
+.set CYREG_B0_P5_U1_DCFG6, 0x40010aec\r
+.set CYREG_B0_P5_U1_DCFG7, 0x40010aee\r
+.set CYDEV_UCFG_B0_P5_ROUTE_BASE, 0x40010b00\r
+.set CYDEV_UCFG_B0_P5_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B0_P6_BASE, 0x40010c00\r
+.set CYDEV_UCFG_B0_P6_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B0_P6_U0_BASE, 0x40010c00\r
+.set CYDEV_UCFG_B0_P6_U0_SIZE, 0x00000070\r
+.set CYREG_B0_P6_U0_PLD_IT0, 0x40010c00\r
+.set CYREG_B0_P6_U0_PLD_IT1, 0x40010c04\r
+.set CYREG_B0_P6_U0_PLD_IT2, 0x40010c08\r
+.set CYREG_B0_P6_U0_PLD_IT3, 0x40010c0c\r
+.set CYREG_B0_P6_U0_PLD_IT4, 0x40010c10\r
+.set CYREG_B0_P6_U0_PLD_IT5, 0x40010c14\r
+.set CYREG_B0_P6_U0_PLD_IT6, 0x40010c18\r
+.set CYREG_B0_P6_U0_PLD_IT7, 0x40010c1c\r
+.set CYREG_B0_P6_U0_PLD_IT8, 0x40010c20\r
+.set CYREG_B0_P6_U0_PLD_IT9, 0x40010c24\r
+.set CYREG_B0_P6_U0_PLD_IT10, 0x40010c28\r
+.set CYREG_B0_P6_U0_PLD_IT11, 0x40010c2c\r
+.set CYREG_B0_P6_U0_PLD_ORT0, 0x40010c30\r
+.set CYREG_B0_P6_U0_PLD_ORT1, 0x40010c32\r
+.set CYREG_B0_P6_U0_PLD_ORT2, 0x40010c34\r
+.set CYREG_B0_P6_U0_PLD_ORT3, 0x40010c36\r
+.set CYREG_B0_P6_U0_MC_CFG_CEN_CONST, 0x40010c38\r
+.set CYREG_B0_P6_U0_MC_CFG_XORFB, 0x40010c3a\r
+.set CYREG_B0_P6_U0_MC_CFG_SET_RESET, 0x40010c3c\r
+.set CYREG_B0_P6_U0_MC_CFG_BYPASS, 0x40010c3e\r
+.set CYREG_B0_P6_U0_CFG0, 0x40010c40\r
+.set CYREG_B0_P6_U0_CFG1, 0x40010c41\r
+.set CYREG_B0_P6_U0_CFG2, 0x40010c42\r
+.set CYREG_B0_P6_U0_CFG3, 0x40010c43\r
+.set CYREG_B0_P6_U0_CFG4, 0x40010c44\r
+.set CYREG_B0_P6_U0_CFG5, 0x40010c45\r
+.set CYREG_B0_P6_U0_CFG6, 0x40010c46\r
+.set CYREG_B0_P6_U0_CFG7, 0x40010c47\r
+.set CYREG_B0_P6_U0_CFG8, 0x40010c48\r
+.set CYREG_B0_P6_U0_CFG9, 0x40010c49\r
+.set CYREG_B0_P6_U0_CFG10, 0x40010c4a\r
+.set CYREG_B0_P6_U0_CFG11, 0x40010c4b\r
+.set CYREG_B0_P6_U0_CFG12, 0x40010c4c\r
+.set CYREG_B0_P6_U0_CFG13, 0x40010c4d\r
+.set CYREG_B0_P6_U0_CFG14, 0x40010c4e\r
+.set CYREG_B0_P6_U0_CFG15, 0x40010c4f\r
+.set CYREG_B0_P6_U0_CFG16, 0x40010c50\r
+.set CYREG_B0_P6_U0_CFG17, 0x40010c51\r
+.set CYREG_B0_P6_U0_CFG18, 0x40010c52\r
+.set CYREG_B0_P6_U0_CFG19, 0x40010c53\r
+.set CYREG_B0_P6_U0_CFG20, 0x40010c54\r
+.set CYREG_B0_P6_U0_CFG21, 0x40010c55\r
+.set CYREG_B0_P6_U0_CFG22, 0x40010c56\r
+.set CYREG_B0_P6_U0_CFG23, 0x40010c57\r
+.set CYREG_B0_P6_U0_CFG24, 0x40010c58\r
+.set CYREG_B0_P6_U0_CFG25, 0x40010c59\r
+.set CYREG_B0_P6_U0_CFG26, 0x40010c5a\r
+.set CYREG_B0_P6_U0_CFG27, 0x40010c5b\r
+.set CYREG_B0_P6_U0_CFG28, 0x40010c5c\r
+.set CYREG_B0_P6_U0_CFG29, 0x40010c5d\r
+.set CYREG_B0_P6_U0_CFG30, 0x40010c5e\r
+.set CYREG_B0_P6_U0_CFG31, 0x40010c5f\r
+.set CYREG_B0_P6_U0_DCFG0, 0x40010c60\r
+.set CYREG_B0_P6_U0_DCFG1, 0x40010c62\r
+.set CYREG_B0_P6_U0_DCFG2, 0x40010c64\r
+.set CYREG_B0_P6_U0_DCFG3, 0x40010c66\r
+.set CYREG_B0_P6_U0_DCFG4, 0x40010c68\r
+.set CYREG_B0_P6_U0_DCFG5, 0x40010c6a\r
+.set CYREG_B0_P6_U0_DCFG6, 0x40010c6c\r
+.set CYREG_B0_P6_U0_DCFG7, 0x40010c6e\r
+.set CYDEV_UCFG_B0_P6_U1_BASE, 0x40010c80\r
+.set CYDEV_UCFG_B0_P6_U1_SIZE, 0x00000070\r
+.set CYREG_B0_P6_U1_PLD_IT0, 0x40010c80\r
+.set CYREG_B0_P6_U1_PLD_IT1, 0x40010c84\r
+.set CYREG_B0_P6_U1_PLD_IT2, 0x40010c88\r
+.set CYREG_B0_P6_U1_PLD_IT3, 0x40010c8c\r
+.set CYREG_B0_P6_U1_PLD_IT4, 0x40010c90\r
+.set CYREG_B0_P6_U1_PLD_IT5, 0x40010c94\r
+.set CYREG_B0_P6_U1_PLD_IT6, 0x40010c98\r
+.set CYREG_B0_P6_U1_PLD_IT7, 0x40010c9c\r
+.set CYREG_B0_P6_U1_PLD_IT8, 0x40010ca0\r
+.set CYREG_B0_P6_U1_PLD_IT9, 0x40010ca4\r
+.set CYREG_B0_P6_U1_PLD_IT10, 0x40010ca8\r
+.set CYREG_B0_P6_U1_PLD_IT11, 0x40010cac\r
+.set CYREG_B0_P6_U1_PLD_ORT0, 0x40010cb0\r
+.set CYREG_B0_P6_U1_PLD_ORT1, 0x40010cb2\r
+.set CYREG_B0_P6_U1_PLD_ORT2, 0x40010cb4\r
+.set CYREG_B0_P6_U1_PLD_ORT3, 0x40010cb6\r
+.set CYREG_B0_P6_U1_MC_CFG_CEN_CONST, 0x40010cb8\r
+.set CYREG_B0_P6_U1_MC_CFG_XORFB, 0x40010cba\r
+.set CYREG_B0_P6_U1_MC_CFG_SET_RESET, 0x40010cbc\r
+.set CYREG_B0_P6_U1_MC_CFG_BYPASS, 0x40010cbe\r
+.set CYREG_B0_P6_U1_CFG0, 0x40010cc0\r
+.set CYREG_B0_P6_U1_CFG1, 0x40010cc1\r
+.set CYREG_B0_P6_U1_CFG2, 0x40010cc2\r
+.set CYREG_B0_P6_U1_CFG3, 0x40010cc3\r
+.set CYREG_B0_P6_U1_CFG4, 0x40010cc4\r
+.set CYREG_B0_P6_U1_CFG5, 0x40010cc5\r
+.set CYREG_B0_P6_U1_CFG6, 0x40010cc6\r
+.set CYREG_B0_P6_U1_CFG7, 0x40010cc7\r
+.set CYREG_B0_P6_U1_CFG8, 0x40010cc8\r
+.set CYREG_B0_P6_U1_CFG9, 0x40010cc9\r
+.set CYREG_B0_P6_U1_CFG10, 0x40010cca\r
+.set CYREG_B0_P6_U1_CFG11, 0x40010ccb\r
+.set CYREG_B0_P6_U1_CFG12, 0x40010ccc\r
+.set CYREG_B0_P6_U1_CFG13, 0x40010ccd\r
+.set CYREG_B0_P6_U1_CFG14, 0x40010cce\r
+.set CYREG_B0_P6_U1_CFG15, 0x40010ccf\r
+.set CYREG_B0_P6_U1_CFG16, 0x40010cd0\r
+.set CYREG_B0_P6_U1_CFG17, 0x40010cd1\r
+.set CYREG_B0_P6_U1_CFG18, 0x40010cd2\r
+.set CYREG_B0_P6_U1_CFG19, 0x40010cd3\r
+.set CYREG_B0_P6_U1_CFG20, 0x40010cd4\r
+.set CYREG_B0_P6_U1_CFG21, 0x40010cd5\r
+.set CYREG_B0_P6_U1_CFG22, 0x40010cd6\r
+.set CYREG_B0_P6_U1_CFG23, 0x40010cd7\r
+.set CYREG_B0_P6_U1_CFG24, 0x40010cd8\r
+.set CYREG_B0_P6_U1_CFG25, 0x40010cd9\r
+.set CYREG_B0_P6_U1_CFG26, 0x40010cda\r
+.set CYREG_B0_P6_U1_CFG27, 0x40010cdb\r
+.set CYREG_B0_P6_U1_CFG28, 0x40010cdc\r
+.set CYREG_B0_P6_U1_CFG29, 0x40010cdd\r
+.set CYREG_B0_P6_U1_CFG30, 0x40010cde\r
+.set CYREG_B0_P6_U1_CFG31, 0x40010cdf\r
+.set CYREG_B0_P6_U1_DCFG0, 0x40010ce0\r
+.set CYREG_B0_P6_U1_DCFG1, 0x40010ce2\r
+.set CYREG_B0_P6_U1_DCFG2, 0x40010ce4\r
+.set CYREG_B0_P6_U1_DCFG3, 0x40010ce6\r
+.set CYREG_B0_P6_U1_DCFG4, 0x40010ce8\r
+.set CYREG_B0_P6_U1_DCFG5, 0x40010cea\r
+.set CYREG_B0_P6_U1_DCFG6, 0x40010cec\r
+.set CYREG_B0_P6_U1_DCFG7, 0x40010cee\r
+.set CYDEV_UCFG_B0_P6_ROUTE_BASE, 0x40010d00\r
+.set CYDEV_UCFG_B0_P6_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B0_P7_BASE, 0x40010e00\r
+.set CYDEV_UCFG_B0_P7_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B0_P7_U0_BASE, 0x40010e00\r
+.set CYDEV_UCFG_B0_P7_U0_SIZE, 0x00000070\r
+.set CYREG_B0_P7_U0_PLD_IT0, 0x40010e00\r
+.set CYREG_B0_P7_U0_PLD_IT1, 0x40010e04\r
+.set CYREG_B0_P7_U0_PLD_IT2, 0x40010e08\r
+.set CYREG_B0_P7_U0_PLD_IT3, 0x40010e0c\r
+.set CYREG_B0_P7_U0_PLD_IT4, 0x40010e10\r
+.set CYREG_B0_P7_U0_PLD_IT5, 0x40010e14\r
+.set CYREG_B0_P7_U0_PLD_IT6, 0x40010e18\r
+.set CYREG_B0_P7_U0_PLD_IT7, 0x40010e1c\r
+.set CYREG_B0_P7_U0_PLD_IT8, 0x40010e20\r
+.set CYREG_B0_P7_U0_PLD_IT9, 0x40010e24\r
+.set CYREG_B0_P7_U0_PLD_IT10, 0x40010e28\r
+.set CYREG_B0_P7_U0_PLD_IT11, 0x40010e2c\r
+.set CYREG_B0_P7_U0_PLD_ORT0, 0x40010e30\r
+.set CYREG_B0_P7_U0_PLD_ORT1, 0x40010e32\r
+.set CYREG_B0_P7_U0_PLD_ORT2, 0x40010e34\r
+.set CYREG_B0_P7_U0_PLD_ORT3, 0x40010e36\r
+.set CYREG_B0_P7_U0_MC_CFG_CEN_CONST, 0x40010e38\r
+.set CYREG_B0_P7_U0_MC_CFG_XORFB, 0x40010e3a\r
+.set CYREG_B0_P7_U0_MC_CFG_SET_RESET, 0x40010e3c\r
+.set CYREG_B0_P7_U0_MC_CFG_BYPASS, 0x40010e3e\r
+.set CYREG_B0_P7_U0_CFG0, 0x40010e40\r
+.set CYREG_B0_P7_U0_CFG1, 0x40010e41\r
+.set CYREG_B0_P7_U0_CFG2, 0x40010e42\r
+.set CYREG_B0_P7_U0_CFG3, 0x40010e43\r
+.set CYREG_B0_P7_U0_CFG4, 0x40010e44\r
+.set CYREG_B0_P7_U0_CFG5, 0x40010e45\r
+.set CYREG_B0_P7_U0_CFG6, 0x40010e46\r
+.set CYREG_B0_P7_U0_CFG7, 0x40010e47\r
+.set CYREG_B0_P7_U0_CFG8, 0x40010e48\r
+.set CYREG_B0_P7_U0_CFG9, 0x40010e49\r
+.set CYREG_B0_P7_U0_CFG10, 0x40010e4a\r
+.set CYREG_B0_P7_U0_CFG11, 0x40010e4b\r
+.set CYREG_B0_P7_U0_CFG12, 0x40010e4c\r
+.set CYREG_B0_P7_U0_CFG13, 0x40010e4d\r
+.set CYREG_B0_P7_U0_CFG14, 0x40010e4e\r
+.set CYREG_B0_P7_U0_CFG15, 0x40010e4f\r
+.set CYREG_B0_P7_U0_CFG16, 0x40010e50\r
+.set CYREG_B0_P7_U0_CFG17, 0x40010e51\r
+.set CYREG_B0_P7_U0_CFG18, 0x40010e52\r
+.set CYREG_B0_P7_U0_CFG19, 0x40010e53\r
+.set CYREG_B0_P7_U0_CFG20, 0x40010e54\r
+.set CYREG_B0_P7_U0_CFG21, 0x40010e55\r
+.set CYREG_B0_P7_U0_CFG22, 0x40010e56\r
+.set CYREG_B0_P7_U0_CFG23, 0x40010e57\r
+.set CYREG_B0_P7_U0_CFG24, 0x40010e58\r
+.set CYREG_B0_P7_U0_CFG25, 0x40010e59\r
+.set CYREG_B0_P7_U0_CFG26, 0x40010e5a\r
+.set CYREG_B0_P7_U0_CFG27, 0x40010e5b\r
+.set CYREG_B0_P7_U0_CFG28, 0x40010e5c\r
+.set CYREG_B0_P7_U0_CFG29, 0x40010e5d\r
+.set CYREG_B0_P7_U0_CFG30, 0x40010e5e\r
+.set CYREG_B0_P7_U0_CFG31, 0x40010e5f\r
+.set CYREG_B0_P7_U0_DCFG0, 0x40010e60\r
+.set CYREG_B0_P7_U0_DCFG1, 0x40010e62\r
+.set CYREG_B0_P7_U0_DCFG2, 0x40010e64\r
+.set CYREG_B0_P7_U0_DCFG3, 0x40010e66\r
+.set CYREG_B0_P7_U0_DCFG4, 0x40010e68\r
+.set CYREG_B0_P7_U0_DCFG5, 0x40010e6a\r
+.set CYREG_B0_P7_U0_DCFG6, 0x40010e6c\r
+.set CYREG_B0_P7_U0_DCFG7, 0x40010e6e\r
+.set CYDEV_UCFG_B0_P7_U1_BASE, 0x40010e80\r
+.set CYDEV_UCFG_B0_P7_U1_SIZE, 0x00000070\r
+.set CYREG_B0_P7_U1_PLD_IT0, 0x40010e80\r
+.set CYREG_B0_P7_U1_PLD_IT1, 0x40010e84\r
+.set CYREG_B0_P7_U1_PLD_IT2, 0x40010e88\r
+.set CYREG_B0_P7_U1_PLD_IT3, 0x40010e8c\r
+.set CYREG_B0_P7_U1_PLD_IT4, 0x40010e90\r
+.set CYREG_B0_P7_U1_PLD_IT5, 0x40010e94\r
+.set CYREG_B0_P7_U1_PLD_IT6, 0x40010e98\r
+.set CYREG_B0_P7_U1_PLD_IT7, 0x40010e9c\r
+.set CYREG_B0_P7_U1_PLD_IT8, 0x40010ea0\r
+.set CYREG_B0_P7_U1_PLD_IT9, 0x40010ea4\r
+.set CYREG_B0_P7_U1_PLD_IT10, 0x40010ea8\r
+.set CYREG_B0_P7_U1_PLD_IT11, 0x40010eac\r
+.set CYREG_B0_P7_U1_PLD_ORT0, 0x40010eb0\r
+.set CYREG_B0_P7_U1_PLD_ORT1, 0x40010eb2\r
+.set CYREG_B0_P7_U1_PLD_ORT2, 0x40010eb4\r
+.set CYREG_B0_P7_U1_PLD_ORT3, 0x40010eb6\r
+.set CYREG_B0_P7_U1_MC_CFG_CEN_CONST, 0x40010eb8\r
+.set CYREG_B0_P7_U1_MC_CFG_XORFB, 0x40010eba\r
+.set CYREG_B0_P7_U1_MC_CFG_SET_RESET, 0x40010ebc\r
+.set CYREG_B0_P7_U1_MC_CFG_BYPASS, 0x40010ebe\r
+.set CYREG_B0_P7_U1_CFG0, 0x40010ec0\r
+.set CYREG_B0_P7_U1_CFG1, 0x40010ec1\r
+.set CYREG_B0_P7_U1_CFG2, 0x40010ec2\r
+.set CYREG_B0_P7_U1_CFG3, 0x40010ec3\r
+.set CYREG_B0_P7_U1_CFG4, 0x40010ec4\r
+.set CYREG_B0_P7_U1_CFG5, 0x40010ec5\r
+.set CYREG_B0_P7_U1_CFG6, 0x40010ec6\r
+.set CYREG_B0_P7_U1_CFG7, 0x40010ec7\r
+.set CYREG_B0_P7_U1_CFG8, 0x40010ec8\r
+.set CYREG_B0_P7_U1_CFG9, 0x40010ec9\r
+.set CYREG_B0_P7_U1_CFG10, 0x40010eca\r
+.set CYREG_B0_P7_U1_CFG11, 0x40010ecb\r
+.set CYREG_B0_P7_U1_CFG12, 0x40010ecc\r
+.set CYREG_B0_P7_U1_CFG13, 0x40010ecd\r
+.set CYREG_B0_P7_U1_CFG14, 0x40010ece\r
+.set CYREG_B0_P7_U1_CFG15, 0x40010ecf\r
+.set CYREG_B0_P7_U1_CFG16, 0x40010ed0\r
+.set CYREG_B0_P7_U1_CFG17, 0x40010ed1\r
+.set CYREG_B0_P7_U1_CFG18, 0x40010ed2\r
+.set CYREG_B0_P7_U1_CFG19, 0x40010ed3\r
+.set CYREG_B0_P7_U1_CFG20, 0x40010ed4\r
+.set CYREG_B0_P7_U1_CFG21, 0x40010ed5\r
+.set CYREG_B0_P7_U1_CFG22, 0x40010ed6\r
+.set CYREG_B0_P7_U1_CFG23, 0x40010ed7\r
+.set CYREG_B0_P7_U1_CFG24, 0x40010ed8\r
+.set CYREG_B0_P7_U1_CFG25, 0x40010ed9\r
+.set CYREG_B0_P7_U1_CFG26, 0x40010eda\r
+.set CYREG_B0_P7_U1_CFG27, 0x40010edb\r
+.set CYREG_B0_P7_U1_CFG28, 0x40010edc\r
+.set CYREG_B0_P7_U1_CFG29, 0x40010edd\r
+.set CYREG_B0_P7_U1_CFG30, 0x40010ede\r
+.set CYREG_B0_P7_U1_CFG31, 0x40010edf\r
+.set CYREG_B0_P7_U1_DCFG0, 0x40010ee0\r
+.set CYREG_B0_P7_U1_DCFG1, 0x40010ee2\r
+.set CYREG_B0_P7_U1_DCFG2, 0x40010ee4\r
+.set CYREG_B0_P7_U1_DCFG3, 0x40010ee6\r
+.set CYREG_B0_P7_U1_DCFG4, 0x40010ee8\r
+.set CYREG_B0_P7_U1_DCFG5, 0x40010eea\r
+.set CYREG_B0_P7_U1_DCFG6, 0x40010eec\r
+.set CYREG_B0_P7_U1_DCFG7, 0x40010eee\r
+.set CYDEV_UCFG_B0_P7_ROUTE_BASE, 0x40010f00\r
+.set CYDEV_UCFG_B0_P7_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B1_BASE, 0x40011000\r
+.set CYDEV_UCFG_B1_SIZE, 0x00000fef\r
+.set CYDEV_UCFG_B1_P2_BASE, 0x40011400\r
+.set CYDEV_UCFG_B1_P2_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B1_P2_U0_BASE, 0x40011400\r
+.set CYDEV_UCFG_B1_P2_U0_SIZE, 0x00000070\r
+.set CYREG_B1_P2_U0_PLD_IT0, 0x40011400\r
+.set CYREG_B1_P2_U0_PLD_IT1, 0x40011404\r
+.set CYREG_B1_P2_U0_PLD_IT2, 0x40011408\r
+.set CYREG_B1_P2_U0_PLD_IT3, 0x4001140c\r
+.set CYREG_B1_P2_U0_PLD_IT4, 0x40011410\r
+.set CYREG_B1_P2_U0_PLD_IT5, 0x40011414\r
+.set CYREG_B1_P2_U0_PLD_IT6, 0x40011418\r
+.set CYREG_B1_P2_U0_PLD_IT7, 0x4001141c\r
+.set CYREG_B1_P2_U0_PLD_IT8, 0x40011420\r
+.set CYREG_B1_P2_U0_PLD_IT9, 0x40011424\r
+.set CYREG_B1_P2_U0_PLD_IT10, 0x40011428\r
+.set CYREG_B1_P2_U0_PLD_IT11, 0x4001142c\r
+.set CYREG_B1_P2_U0_PLD_ORT0, 0x40011430\r
+.set CYREG_B1_P2_U0_PLD_ORT1, 0x40011432\r
+.set CYREG_B1_P2_U0_PLD_ORT2, 0x40011434\r
+.set CYREG_B1_P2_U0_PLD_ORT3, 0x40011436\r
+.set CYREG_B1_P2_U0_MC_CFG_CEN_CONST, 0x40011438\r
+.set CYREG_B1_P2_U0_MC_CFG_XORFB, 0x4001143a\r
+.set CYREG_B1_P2_U0_MC_CFG_SET_RESET, 0x4001143c\r
+.set CYREG_B1_P2_U0_MC_CFG_BYPASS, 0x4001143e\r
+.set CYREG_B1_P2_U0_CFG0, 0x40011440\r
+.set CYREG_B1_P2_U0_CFG1, 0x40011441\r
+.set CYREG_B1_P2_U0_CFG2, 0x40011442\r
+.set CYREG_B1_P2_U0_CFG3, 0x40011443\r
+.set CYREG_B1_P2_U0_CFG4, 0x40011444\r
+.set CYREG_B1_P2_U0_CFG5, 0x40011445\r
+.set CYREG_B1_P2_U0_CFG6, 0x40011446\r
+.set CYREG_B1_P2_U0_CFG7, 0x40011447\r
+.set CYREG_B1_P2_U0_CFG8, 0x40011448\r
+.set CYREG_B1_P2_U0_CFG9, 0x40011449\r
+.set CYREG_B1_P2_U0_CFG10, 0x4001144a\r
+.set CYREG_B1_P2_U0_CFG11, 0x4001144b\r
+.set CYREG_B1_P2_U0_CFG12, 0x4001144c\r
+.set CYREG_B1_P2_U0_CFG13, 0x4001144d\r
+.set CYREG_B1_P2_U0_CFG14, 0x4001144e\r
+.set CYREG_B1_P2_U0_CFG15, 0x4001144f\r
+.set CYREG_B1_P2_U0_CFG16, 0x40011450\r
+.set CYREG_B1_P2_U0_CFG17, 0x40011451\r
+.set CYREG_B1_P2_U0_CFG18, 0x40011452\r
+.set CYREG_B1_P2_U0_CFG19, 0x40011453\r
+.set CYREG_B1_P2_U0_CFG20, 0x40011454\r
+.set CYREG_B1_P2_U0_CFG21, 0x40011455\r
+.set CYREG_B1_P2_U0_CFG22, 0x40011456\r
+.set CYREG_B1_P2_U0_CFG23, 0x40011457\r
+.set CYREG_B1_P2_U0_CFG24, 0x40011458\r
+.set CYREG_B1_P2_U0_CFG25, 0x40011459\r
+.set CYREG_B1_P2_U0_CFG26, 0x4001145a\r
+.set CYREG_B1_P2_U0_CFG27, 0x4001145b\r
+.set CYREG_B1_P2_U0_CFG28, 0x4001145c\r
+.set CYREG_B1_P2_U0_CFG29, 0x4001145d\r
+.set CYREG_B1_P2_U0_CFG30, 0x4001145e\r
+.set CYREG_B1_P2_U0_CFG31, 0x4001145f\r
+.set CYREG_B1_P2_U0_DCFG0, 0x40011460\r
+.set CYREG_B1_P2_U0_DCFG1, 0x40011462\r
+.set CYREG_B1_P2_U0_DCFG2, 0x40011464\r
+.set CYREG_B1_P2_U0_DCFG3, 0x40011466\r
+.set CYREG_B1_P2_U0_DCFG4, 0x40011468\r
+.set CYREG_B1_P2_U0_DCFG5, 0x4001146a\r
+.set CYREG_B1_P2_U0_DCFG6, 0x4001146c\r
+.set CYREG_B1_P2_U0_DCFG7, 0x4001146e\r
+.set CYDEV_UCFG_B1_P2_U1_BASE, 0x40011480\r
+.set CYDEV_UCFG_B1_P2_U1_SIZE, 0x00000070\r
+.set CYREG_B1_P2_U1_PLD_IT0, 0x40011480\r
+.set CYREG_B1_P2_U1_PLD_IT1, 0x40011484\r
+.set CYREG_B1_P2_U1_PLD_IT2, 0x40011488\r
+.set CYREG_B1_P2_U1_PLD_IT3, 0x4001148c\r
+.set CYREG_B1_P2_U1_PLD_IT4, 0x40011490\r
+.set CYREG_B1_P2_U1_PLD_IT5, 0x40011494\r
+.set CYREG_B1_P2_U1_PLD_IT6, 0x40011498\r
+.set CYREG_B1_P2_U1_PLD_IT7, 0x4001149c\r
+.set CYREG_B1_P2_U1_PLD_IT8, 0x400114a0\r
+.set CYREG_B1_P2_U1_PLD_IT9, 0x400114a4\r
+.set CYREG_B1_P2_U1_PLD_IT10, 0x400114a8\r
+.set CYREG_B1_P2_U1_PLD_IT11, 0x400114ac\r
+.set CYREG_B1_P2_U1_PLD_ORT0, 0x400114b0\r
+.set CYREG_B1_P2_U1_PLD_ORT1, 0x400114b2\r
+.set CYREG_B1_P2_U1_PLD_ORT2, 0x400114b4\r
+.set CYREG_B1_P2_U1_PLD_ORT3, 0x400114b6\r
+.set CYREG_B1_P2_U1_MC_CFG_CEN_CONST, 0x400114b8\r
+.set CYREG_B1_P2_U1_MC_CFG_XORFB, 0x400114ba\r
+.set CYREG_B1_P2_U1_MC_CFG_SET_RESET, 0x400114bc\r
+.set CYREG_B1_P2_U1_MC_CFG_BYPASS, 0x400114be\r
+.set CYREG_B1_P2_U1_CFG0, 0x400114c0\r
+.set CYREG_B1_P2_U1_CFG1, 0x400114c1\r
+.set CYREG_B1_P2_U1_CFG2, 0x400114c2\r
+.set CYREG_B1_P2_U1_CFG3, 0x400114c3\r
+.set CYREG_B1_P2_U1_CFG4, 0x400114c4\r
+.set CYREG_B1_P2_U1_CFG5, 0x400114c5\r
+.set CYREG_B1_P2_U1_CFG6, 0x400114c6\r
+.set CYREG_B1_P2_U1_CFG7, 0x400114c7\r
+.set CYREG_B1_P2_U1_CFG8, 0x400114c8\r
+.set CYREG_B1_P2_U1_CFG9, 0x400114c9\r
+.set CYREG_B1_P2_U1_CFG10, 0x400114ca\r
+.set CYREG_B1_P2_U1_CFG11, 0x400114cb\r
+.set CYREG_B1_P2_U1_CFG12, 0x400114cc\r
+.set CYREG_B1_P2_U1_CFG13, 0x400114cd\r
+.set CYREG_B1_P2_U1_CFG14, 0x400114ce\r
+.set CYREG_B1_P2_U1_CFG15, 0x400114cf\r
+.set CYREG_B1_P2_U1_CFG16, 0x400114d0\r
+.set CYREG_B1_P2_U1_CFG17, 0x400114d1\r
+.set CYREG_B1_P2_U1_CFG18, 0x400114d2\r
+.set CYREG_B1_P2_U1_CFG19, 0x400114d3\r
+.set CYREG_B1_P2_U1_CFG20, 0x400114d4\r
+.set CYREG_B1_P2_U1_CFG21, 0x400114d5\r
+.set CYREG_B1_P2_U1_CFG22, 0x400114d6\r
+.set CYREG_B1_P2_U1_CFG23, 0x400114d7\r
+.set CYREG_B1_P2_U1_CFG24, 0x400114d8\r
+.set CYREG_B1_P2_U1_CFG25, 0x400114d9\r
+.set CYREG_B1_P2_U1_CFG26, 0x400114da\r
+.set CYREG_B1_P2_U1_CFG27, 0x400114db\r
+.set CYREG_B1_P2_U1_CFG28, 0x400114dc\r
+.set CYREG_B1_P2_U1_CFG29, 0x400114dd\r
+.set CYREG_B1_P2_U1_CFG30, 0x400114de\r
+.set CYREG_B1_P2_U1_CFG31, 0x400114df\r
+.set CYREG_B1_P2_U1_DCFG0, 0x400114e0\r
+.set CYREG_B1_P2_U1_DCFG1, 0x400114e2\r
+.set CYREG_B1_P2_U1_DCFG2, 0x400114e4\r
+.set CYREG_B1_P2_U1_DCFG3, 0x400114e6\r
+.set CYREG_B1_P2_U1_DCFG4, 0x400114e8\r
+.set CYREG_B1_P2_U1_DCFG5, 0x400114ea\r
+.set CYREG_B1_P2_U1_DCFG6, 0x400114ec\r
+.set CYREG_B1_P2_U1_DCFG7, 0x400114ee\r
+.set CYDEV_UCFG_B1_P2_ROUTE_BASE, 0x40011500\r
+.set CYDEV_UCFG_B1_P2_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B1_P3_BASE, 0x40011600\r
+.set CYDEV_UCFG_B1_P3_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B1_P3_U0_BASE, 0x40011600\r
+.set CYDEV_UCFG_B1_P3_U0_SIZE, 0x00000070\r
+.set CYREG_B1_P3_U0_PLD_IT0, 0x40011600\r
+.set CYREG_B1_P3_U0_PLD_IT1, 0x40011604\r
+.set CYREG_B1_P3_U0_PLD_IT2, 0x40011608\r
+.set CYREG_B1_P3_U0_PLD_IT3, 0x4001160c\r
+.set CYREG_B1_P3_U0_PLD_IT4, 0x40011610\r
+.set CYREG_B1_P3_U0_PLD_IT5, 0x40011614\r
+.set CYREG_B1_P3_U0_PLD_IT6, 0x40011618\r
+.set CYREG_B1_P3_U0_PLD_IT7, 0x4001161c\r
+.set CYREG_B1_P3_U0_PLD_IT8, 0x40011620\r
+.set CYREG_B1_P3_U0_PLD_IT9, 0x40011624\r
+.set CYREG_B1_P3_U0_PLD_IT10, 0x40011628\r
+.set CYREG_B1_P3_U0_PLD_IT11, 0x4001162c\r
+.set CYREG_B1_P3_U0_PLD_ORT0, 0x40011630\r
+.set CYREG_B1_P3_U0_PLD_ORT1, 0x40011632\r
+.set CYREG_B1_P3_U0_PLD_ORT2, 0x40011634\r
+.set CYREG_B1_P3_U0_PLD_ORT3, 0x40011636\r
+.set CYREG_B1_P3_U0_MC_CFG_CEN_CONST, 0x40011638\r
+.set CYREG_B1_P3_U0_MC_CFG_XORFB, 0x4001163a\r
+.set CYREG_B1_P3_U0_MC_CFG_SET_RESET, 0x4001163c\r
+.set CYREG_B1_P3_U0_MC_CFG_BYPASS, 0x4001163e\r
+.set CYREG_B1_P3_U0_CFG0, 0x40011640\r
+.set CYREG_B1_P3_U0_CFG1, 0x40011641\r
+.set CYREG_B1_P3_U0_CFG2, 0x40011642\r
+.set CYREG_B1_P3_U0_CFG3, 0x40011643\r
+.set CYREG_B1_P3_U0_CFG4, 0x40011644\r
+.set CYREG_B1_P3_U0_CFG5, 0x40011645\r
+.set CYREG_B1_P3_U0_CFG6, 0x40011646\r
+.set CYREG_B1_P3_U0_CFG7, 0x40011647\r
+.set CYREG_B1_P3_U0_CFG8, 0x40011648\r
+.set CYREG_B1_P3_U0_CFG9, 0x40011649\r
+.set CYREG_B1_P3_U0_CFG10, 0x4001164a\r
+.set CYREG_B1_P3_U0_CFG11, 0x4001164b\r
+.set CYREG_B1_P3_U0_CFG12, 0x4001164c\r
+.set CYREG_B1_P3_U0_CFG13, 0x4001164d\r
+.set CYREG_B1_P3_U0_CFG14, 0x4001164e\r
+.set CYREG_B1_P3_U0_CFG15, 0x4001164f\r
+.set CYREG_B1_P3_U0_CFG16, 0x40011650\r
+.set CYREG_B1_P3_U0_CFG17, 0x40011651\r
+.set CYREG_B1_P3_U0_CFG18, 0x40011652\r
+.set CYREG_B1_P3_U0_CFG19, 0x40011653\r
+.set CYREG_B1_P3_U0_CFG20, 0x40011654\r
+.set CYREG_B1_P3_U0_CFG21, 0x40011655\r
+.set CYREG_B1_P3_U0_CFG22, 0x40011656\r
+.set CYREG_B1_P3_U0_CFG23, 0x40011657\r
+.set CYREG_B1_P3_U0_CFG24, 0x40011658\r
+.set CYREG_B1_P3_U0_CFG25, 0x40011659\r
+.set CYREG_B1_P3_U0_CFG26, 0x4001165a\r
+.set CYREG_B1_P3_U0_CFG27, 0x4001165b\r
+.set CYREG_B1_P3_U0_CFG28, 0x4001165c\r
+.set CYREG_B1_P3_U0_CFG29, 0x4001165d\r
+.set CYREG_B1_P3_U0_CFG30, 0x4001165e\r
+.set CYREG_B1_P3_U0_CFG31, 0x4001165f\r
+.set CYREG_B1_P3_U0_DCFG0, 0x40011660\r
+.set CYREG_B1_P3_U0_DCFG1, 0x40011662\r
+.set CYREG_B1_P3_U0_DCFG2, 0x40011664\r
+.set CYREG_B1_P3_U0_DCFG3, 0x40011666\r
+.set CYREG_B1_P3_U0_DCFG4, 0x40011668\r
+.set CYREG_B1_P3_U0_DCFG5, 0x4001166a\r
+.set CYREG_B1_P3_U0_DCFG6, 0x4001166c\r
+.set CYREG_B1_P3_U0_DCFG7, 0x4001166e\r
+.set CYDEV_UCFG_B1_P3_U1_BASE, 0x40011680\r
+.set CYDEV_UCFG_B1_P3_U1_SIZE, 0x00000070\r
+.set CYREG_B1_P3_U1_PLD_IT0, 0x40011680\r
+.set CYREG_B1_P3_U1_PLD_IT1, 0x40011684\r
+.set CYREG_B1_P3_U1_PLD_IT2, 0x40011688\r
+.set CYREG_B1_P3_U1_PLD_IT3, 0x4001168c\r
+.set CYREG_B1_P3_U1_PLD_IT4, 0x40011690\r
+.set CYREG_B1_P3_U1_PLD_IT5, 0x40011694\r
+.set CYREG_B1_P3_U1_PLD_IT6, 0x40011698\r
+.set CYREG_B1_P3_U1_PLD_IT7, 0x4001169c\r
+.set CYREG_B1_P3_U1_PLD_IT8, 0x400116a0\r
+.set CYREG_B1_P3_U1_PLD_IT9, 0x400116a4\r
+.set CYREG_B1_P3_U1_PLD_IT10, 0x400116a8\r
+.set CYREG_B1_P3_U1_PLD_IT11, 0x400116ac\r
+.set CYREG_B1_P3_U1_PLD_ORT0, 0x400116b0\r
+.set CYREG_B1_P3_U1_PLD_ORT1, 0x400116b2\r
+.set CYREG_B1_P3_U1_PLD_ORT2, 0x400116b4\r
+.set CYREG_B1_P3_U1_PLD_ORT3, 0x400116b6\r
+.set CYREG_B1_P3_U1_MC_CFG_CEN_CONST, 0x400116b8\r
+.set CYREG_B1_P3_U1_MC_CFG_XORFB, 0x400116ba\r
+.set CYREG_B1_P3_U1_MC_CFG_SET_RESET, 0x400116bc\r
+.set CYREG_B1_P3_U1_MC_CFG_BYPASS, 0x400116be\r
+.set CYREG_B1_P3_U1_CFG0, 0x400116c0\r
+.set CYREG_B1_P3_U1_CFG1, 0x400116c1\r
+.set CYREG_B1_P3_U1_CFG2, 0x400116c2\r
+.set CYREG_B1_P3_U1_CFG3, 0x400116c3\r
+.set CYREG_B1_P3_U1_CFG4, 0x400116c4\r
+.set CYREG_B1_P3_U1_CFG5, 0x400116c5\r
+.set CYREG_B1_P3_U1_CFG6, 0x400116c6\r
+.set CYREG_B1_P3_U1_CFG7, 0x400116c7\r
+.set CYREG_B1_P3_U1_CFG8, 0x400116c8\r
+.set CYREG_B1_P3_U1_CFG9, 0x400116c9\r
+.set CYREG_B1_P3_U1_CFG10, 0x400116ca\r
+.set CYREG_B1_P3_U1_CFG11, 0x400116cb\r
+.set CYREG_B1_P3_U1_CFG12, 0x400116cc\r
+.set CYREG_B1_P3_U1_CFG13, 0x400116cd\r
+.set CYREG_B1_P3_U1_CFG14, 0x400116ce\r
+.set CYREG_B1_P3_U1_CFG15, 0x400116cf\r
+.set CYREG_B1_P3_U1_CFG16, 0x400116d0\r
+.set CYREG_B1_P3_U1_CFG17, 0x400116d1\r
+.set CYREG_B1_P3_U1_CFG18, 0x400116d2\r
+.set CYREG_B1_P3_U1_CFG19, 0x400116d3\r
+.set CYREG_B1_P3_U1_CFG20, 0x400116d4\r
+.set CYREG_B1_P3_U1_CFG21, 0x400116d5\r
+.set CYREG_B1_P3_U1_CFG22, 0x400116d6\r
+.set CYREG_B1_P3_U1_CFG23, 0x400116d7\r
+.set CYREG_B1_P3_U1_CFG24, 0x400116d8\r
+.set CYREG_B1_P3_U1_CFG25, 0x400116d9\r
+.set CYREG_B1_P3_U1_CFG26, 0x400116da\r
+.set CYREG_B1_P3_U1_CFG27, 0x400116db\r
+.set CYREG_B1_P3_U1_CFG28, 0x400116dc\r
+.set CYREG_B1_P3_U1_CFG29, 0x400116dd\r
+.set CYREG_B1_P3_U1_CFG30, 0x400116de\r
+.set CYREG_B1_P3_U1_CFG31, 0x400116df\r
+.set CYREG_B1_P3_U1_DCFG0, 0x400116e0\r
+.set CYREG_B1_P3_U1_DCFG1, 0x400116e2\r
+.set CYREG_B1_P3_U1_DCFG2, 0x400116e4\r
+.set CYREG_B1_P3_U1_DCFG3, 0x400116e6\r
+.set CYREG_B1_P3_U1_DCFG4, 0x400116e8\r
+.set CYREG_B1_P3_U1_DCFG5, 0x400116ea\r
+.set CYREG_B1_P3_U1_DCFG6, 0x400116ec\r
+.set CYREG_B1_P3_U1_DCFG7, 0x400116ee\r
+.set CYDEV_UCFG_B1_P3_ROUTE_BASE, 0x40011700\r
+.set CYDEV_UCFG_B1_P3_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B1_P4_BASE, 0x40011800\r
+.set CYDEV_UCFG_B1_P4_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B1_P4_U0_BASE, 0x40011800\r
+.set CYDEV_UCFG_B1_P4_U0_SIZE, 0x00000070\r
+.set CYREG_B1_P4_U0_PLD_IT0, 0x40011800\r
+.set CYREG_B1_P4_U0_PLD_IT1, 0x40011804\r
+.set CYREG_B1_P4_U0_PLD_IT2, 0x40011808\r
+.set CYREG_B1_P4_U0_PLD_IT3, 0x4001180c\r
+.set CYREG_B1_P4_U0_PLD_IT4, 0x40011810\r
+.set CYREG_B1_P4_U0_PLD_IT5, 0x40011814\r
+.set CYREG_B1_P4_U0_PLD_IT6, 0x40011818\r
+.set CYREG_B1_P4_U0_PLD_IT7, 0x4001181c\r
+.set CYREG_B1_P4_U0_PLD_IT8, 0x40011820\r
+.set CYREG_B1_P4_U0_PLD_IT9, 0x40011824\r
+.set CYREG_B1_P4_U0_PLD_IT10, 0x40011828\r
+.set CYREG_B1_P4_U0_PLD_IT11, 0x4001182c\r
+.set CYREG_B1_P4_U0_PLD_ORT0, 0x40011830\r
+.set CYREG_B1_P4_U0_PLD_ORT1, 0x40011832\r
+.set CYREG_B1_P4_U0_PLD_ORT2, 0x40011834\r
+.set CYREG_B1_P4_U0_PLD_ORT3, 0x40011836\r
+.set CYREG_B1_P4_U0_MC_CFG_CEN_CONST, 0x40011838\r
+.set CYREG_B1_P4_U0_MC_CFG_XORFB, 0x4001183a\r
+.set CYREG_B1_P4_U0_MC_CFG_SET_RESET, 0x4001183c\r
+.set CYREG_B1_P4_U0_MC_CFG_BYPASS, 0x4001183e\r
+.set CYREG_B1_P4_U0_CFG0, 0x40011840\r
+.set CYREG_B1_P4_U0_CFG1, 0x40011841\r
+.set CYREG_B1_P4_U0_CFG2, 0x40011842\r
+.set CYREG_B1_P4_U0_CFG3, 0x40011843\r
+.set CYREG_B1_P4_U0_CFG4, 0x40011844\r
+.set CYREG_B1_P4_U0_CFG5, 0x40011845\r
+.set CYREG_B1_P4_U0_CFG6, 0x40011846\r
+.set CYREG_B1_P4_U0_CFG7, 0x40011847\r
+.set CYREG_B1_P4_U0_CFG8, 0x40011848\r
+.set CYREG_B1_P4_U0_CFG9, 0x40011849\r
+.set CYREG_B1_P4_U0_CFG10, 0x4001184a\r
+.set CYREG_B1_P4_U0_CFG11, 0x4001184b\r
+.set CYREG_B1_P4_U0_CFG12, 0x4001184c\r
+.set CYREG_B1_P4_U0_CFG13, 0x4001184d\r
+.set CYREG_B1_P4_U0_CFG14, 0x4001184e\r
+.set CYREG_B1_P4_U0_CFG15, 0x4001184f\r
+.set CYREG_B1_P4_U0_CFG16, 0x40011850\r
+.set CYREG_B1_P4_U0_CFG17, 0x40011851\r
+.set CYREG_B1_P4_U0_CFG18, 0x40011852\r
+.set CYREG_B1_P4_U0_CFG19, 0x40011853\r
+.set CYREG_B1_P4_U0_CFG20, 0x40011854\r
+.set CYREG_B1_P4_U0_CFG21, 0x40011855\r
+.set CYREG_B1_P4_U0_CFG22, 0x40011856\r
+.set CYREG_B1_P4_U0_CFG23, 0x40011857\r
+.set CYREG_B1_P4_U0_CFG24, 0x40011858\r
+.set CYREG_B1_P4_U0_CFG25, 0x40011859\r
+.set CYREG_B1_P4_U0_CFG26, 0x4001185a\r
+.set CYREG_B1_P4_U0_CFG27, 0x4001185b\r
+.set CYREG_B1_P4_U0_CFG28, 0x4001185c\r
+.set CYREG_B1_P4_U0_CFG29, 0x4001185d\r
+.set CYREG_B1_P4_U0_CFG30, 0x4001185e\r
+.set CYREG_B1_P4_U0_CFG31, 0x4001185f\r
+.set CYREG_B1_P4_U0_DCFG0, 0x40011860\r
+.set CYREG_B1_P4_U0_DCFG1, 0x40011862\r
+.set CYREG_B1_P4_U0_DCFG2, 0x40011864\r
+.set CYREG_B1_P4_U0_DCFG3, 0x40011866\r
+.set CYREG_B1_P4_U0_DCFG4, 0x40011868\r
+.set CYREG_B1_P4_U0_DCFG5, 0x4001186a\r
+.set CYREG_B1_P4_U0_DCFG6, 0x4001186c\r
+.set CYREG_B1_P4_U0_DCFG7, 0x4001186e\r
+.set CYDEV_UCFG_B1_P4_U1_BASE, 0x40011880\r
+.set CYDEV_UCFG_B1_P4_U1_SIZE, 0x00000070\r
+.set CYREG_B1_P4_U1_PLD_IT0, 0x40011880\r
+.set CYREG_B1_P4_U1_PLD_IT1, 0x40011884\r
+.set CYREG_B1_P4_U1_PLD_IT2, 0x40011888\r
+.set CYREG_B1_P4_U1_PLD_IT3, 0x4001188c\r
+.set CYREG_B1_P4_U1_PLD_IT4, 0x40011890\r
+.set CYREG_B1_P4_U1_PLD_IT5, 0x40011894\r
+.set CYREG_B1_P4_U1_PLD_IT6, 0x40011898\r
+.set CYREG_B1_P4_U1_PLD_IT7, 0x4001189c\r
+.set CYREG_B1_P4_U1_PLD_IT8, 0x400118a0\r
+.set CYREG_B1_P4_U1_PLD_IT9, 0x400118a4\r
+.set CYREG_B1_P4_U1_PLD_IT10, 0x400118a8\r
+.set CYREG_B1_P4_U1_PLD_IT11, 0x400118ac\r
+.set CYREG_B1_P4_U1_PLD_ORT0, 0x400118b0\r
+.set CYREG_B1_P4_U1_PLD_ORT1, 0x400118b2\r
+.set CYREG_B1_P4_U1_PLD_ORT2, 0x400118b4\r
+.set CYREG_B1_P4_U1_PLD_ORT3, 0x400118b6\r
+.set CYREG_B1_P4_U1_MC_CFG_CEN_CONST, 0x400118b8\r
+.set CYREG_B1_P4_U1_MC_CFG_XORFB, 0x400118ba\r
+.set CYREG_B1_P4_U1_MC_CFG_SET_RESET, 0x400118bc\r
+.set CYREG_B1_P4_U1_MC_CFG_BYPASS, 0x400118be\r
+.set CYREG_B1_P4_U1_CFG0, 0x400118c0\r
+.set CYREG_B1_P4_U1_CFG1, 0x400118c1\r
+.set CYREG_B1_P4_U1_CFG2, 0x400118c2\r
+.set CYREG_B1_P4_U1_CFG3, 0x400118c3\r
+.set CYREG_B1_P4_U1_CFG4, 0x400118c4\r
+.set CYREG_B1_P4_U1_CFG5, 0x400118c5\r
+.set CYREG_B1_P4_U1_CFG6, 0x400118c6\r
+.set CYREG_B1_P4_U1_CFG7, 0x400118c7\r
+.set CYREG_B1_P4_U1_CFG8, 0x400118c8\r
+.set CYREG_B1_P4_U1_CFG9, 0x400118c9\r
+.set CYREG_B1_P4_U1_CFG10, 0x400118ca\r
+.set CYREG_B1_P4_U1_CFG11, 0x400118cb\r
+.set CYREG_B1_P4_U1_CFG12, 0x400118cc\r
+.set CYREG_B1_P4_U1_CFG13, 0x400118cd\r
+.set CYREG_B1_P4_U1_CFG14, 0x400118ce\r
+.set CYREG_B1_P4_U1_CFG15, 0x400118cf\r
+.set CYREG_B1_P4_U1_CFG16, 0x400118d0\r
+.set CYREG_B1_P4_U1_CFG17, 0x400118d1\r
+.set CYREG_B1_P4_U1_CFG18, 0x400118d2\r
+.set CYREG_B1_P4_U1_CFG19, 0x400118d3\r
+.set CYREG_B1_P4_U1_CFG20, 0x400118d4\r
+.set CYREG_B1_P4_U1_CFG21, 0x400118d5\r
+.set CYREG_B1_P4_U1_CFG22, 0x400118d6\r
+.set CYREG_B1_P4_U1_CFG23, 0x400118d7\r
+.set CYREG_B1_P4_U1_CFG24, 0x400118d8\r
+.set CYREG_B1_P4_U1_CFG25, 0x400118d9\r
+.set CYREG_B1_P4_U1_CFG26, 0x400118da\r
+.set CYREG_B1_P4_U1_CFG27, 0x400118db\r
+.set CYREG_B1_P4_U1_CFG28, 0x400118dc\r
+.set CYREG_B1_P4_U1_CFG29, 0x400118dd\r
+.set CYREG_B1_P4_U1_CFG30, 0x400118de\r
+.set CYREG_B1_P4_U1_CFG31, 0x400118df\r
+.set CYREG_B1_P4_U1_DCFG0, 0x400118e0\r
+.set CYREG_B1_P4_U1_DCFG1, 0x400118e2\r
+.set CYREG_B1_P4_U1_DCFG2, 0x400118e4\r
+.set CYREG_B1_P4_U1_DCFG3, 0x400118e6\r
+.set CYREG_B1_P4_U1_DCFG4, 0x400118e8\r
+.set CYREG_B1_P4_U1_DCFG5, 0x400118ea\r
+.set CYREG_B1_P4_U1_DCFG6, 0x400118ec\r
+.set CYREG_B1_P4_U1_DCFG7, 0x400118ee\r
+.set CYDEV_UCFG_B1_P4_ROUTE_BASE, 0x40011900\r
+.set CYDEV_UCFG_B1_P4_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_B1_P5_BASE, 0x40011a00\r
+.set CYDEV_UCFG_B1_P5_SIZE, 0x000001ef\r
+.set CYDEV_UCFG_B1_P5_U0_BASE, 0x40011a00\r
+.set CYDEV_UCFG_B1_P5_U0_SIZE, 0x00000070\r
+.set CYREG_B1_P5_U0_PLD_IT0, 0x40011a00\r
+.set CYREG_B1_P5_U0_PLD_IT1, 0x40011a04\r
+.set CYREG_B1_P5_U0_PLD_IT2, 0x40011a08\r
+.set CYREG_B1_P5_U0_PLD_IT3, 0x40011a0c\r
+.set CYREG_B1_P5_U0_PLD_IT4, 0x40011a10\r
+.set CYREG_B1_P5_U0_PLD_IT5, 0x40011a14\r
+.set CYREG_B1_P5_U0_PLD_IT6, 0x40011a18\r
+.set CYREG_B1_P5_U0_PLD_IT7, 0x40011a1c\r
+.set CYREG_B1_P5_U0_PLD_IT8, 0x40011a20\r
+.set CYREG_B1_P5_U0_PLD_IT9, 0x40011a24\r
+.set CYREG_B1_P5_U0_PLD_IT10, 0x40011a28\r
+.set CYREG_B1_P5_U0_PLD_IT11, 0x40011a2c\r
+.set CYREG_B1_P5_U0_PLD_ORT0, 0x40011a30\r
+.set CYREG_B1_P5_U0_PLD_ORT1, 0x40011a32\r
+.set CYREG_B1_P5_U0_PLD_ORT2, 0x40011a34\r
+.set CYREG_B1_P5_U0_PLD_ORT3, 0x40011a36\r
+.set CYREG_B1_P5_U0_MC_CFG_CEN_CONST, 0x40011a38\r
+.set CYREG_B1_P5_U0_MC_CFG_XORFB, 0x40011a3a\r
+.set CYREG_B1_P5_U0_MC_CFG_SET_RESET, 0x40011a3c\r
+.set CYREG_B1_P5_U0_MC_CFG_BYPASS, 0x40011a3e\r
+.set CYREG_B1_P5_U0_CFG0, 0x40011a40\r
+.set CYREG_B1_P5_U0_CFG1, 0x40011a41\r
+.set CYREG_B1_P5_U0_CFG2, 0x40011a42\r
+.set CYREG_B1_P5_U0_CFG3, 0x40011a43\r
+.set CYREG_B1_P5_U0_CFG4, 0x40011a44\r
+.set CYREG_B1_P5_U0_CFG5, 0x40011a45\r
+.set CYREG_B1_P5_U0_CFG6, 0x40011a46\r
+.set CYREG_B1_P5_U0_CFG7, 0x40011a47\r
+.set CYREG_B1_P5_U0_CFG8, 0x40011a48\r
+.set CYREG_B1_P5_U0_CFG9, 0x40011a49\r
+.set CYREG_B1_P5_U0_CFG10, 0x40011a4a\r
+.set CYREG_B1_P5_U0_CFG11, 0x40011a4b\r
+.set CYREG_B1_P5_U0_CFG12, 0x40011a4c\r
+.set CYREG_B1_P5_U0_CFG13, 0x40011a4d\r
+.set CYREG_B1_P5_U0_CFG14, 0x40011a4e\r
+.set CYREG_B1_P5_U0_CFG15, 0x40011a4f\r
+.set CYREG_B1_P5_U0_CFG16, 0x40011a50\r
+.set CYREG_B1_P5_U0_CFG17, 0x40011a51\r
+.set CYREG_B1_P5_U0_CFG18, 0x40011a52\r
+.set CYREG_B1_P5_U0_CFG19, 0x40011a53\r
+.set CYREG_B1_P5_U0_CFG20, 0x40011a54\r
+.set CYREG_B1_P5_U0_CFG21, 0x40011a55\r
+.set CYREG_B1_P5_U0_CFG22, 0x40011a56\r
+.set CYREG_B1_P5_U0_CFG23, 0x40011a57\r
+.set CYREG_B1_P5_U0_CFG24, 0x40011a58\r
+.set CYREG_B1_P5_U0_CFG25, 0x40011a59\r
+.set CYREG_B1_P5_U0_CFG26, 0x40011a5a\r
+.set CYREG_B1_P5_U0_CFG27, 0x40011a5b\r
+.set CYREG_B1_P5_U0_CFG28, 0x40011a5c\r
+.set CYREG_B1_P5_U0_CFG29, 0x40011a5d\r
+.set CYREG_B1_P5_U0_CFG30, 0x40011a5e\r
+.set CYREG_B1_P5_U0_CFG31, 0x40011a5f\r
+.set CYREG_B1_P5_U0_DCFG0, 0x40011a60\r
+.set CYREG_B1_P5_U0_DCFG1, 0x40011a62\r
+.set CYREG_B1_P5_U0_DCFG2, 0x40011a64\r
+.set CYREG_B1_P5_U0_DCFG3, 0x40011a66\r
+.set CYREG_B1_P5_U0_DCFG4, 0x40011a68\r
+.set CYREG_B1_P5_U0_DCFG5, 0x40011a6a\r
+.set CYREG_B1_P5_U0_DCFG6, 0x40011a6c\r
+.set CYREG_B1_P5_U0_DCFG7, 0x40011a6e\r
+.set CYDEV_UCFG_B1_P5_U1_BASE, 0x40011a80\r
+.set CYDEV_UCFG_B1_P5_U1_SIZE, 0x00000070\r
+.set CYREG_B1_P5_U1_PLD_IT0, 0x40011a80\r
+.set CYREG_B1_P5_U1_PLD_IT1, 0x40011a84\r
+.set CYREG_B1_P5_U1_PLD_IT2, 0x40011a88\r
+.set CYREG_B1_P5_U1_PLD_IT3, 0x40011a8c\r
+.set CYREG_B1_P5_U1_PLD_IT4, 0x40011a90\r
+.set CYREG_B1_P5_U1_PLD_IT5, 0x40011a94\r
+.set CYREG_B1_P5_U1_PLD_IT6, 0x40011a98\r
+.set CYREG_B1_P5_U1_PLD_IT7, 0x40011a9c\r
+.set CYREG_B1_P5_U1_PLD_IT8, 0x40011aa0\r
+.set CYREG_B1_P5_U1_PLD_IT9, 0x40011aa4\r
+.set CYREG_B1_P5_U1_PLD_IT10, 0x40011aa8\r
+.set CYREG_B1_P5_U1_PLD_IT11, 0x40011aac\r
+.set CYREG_B1_P5_U1_PLD_ORT0, 0x40011ab0\r
+.set CYREG_B1_P5_U1_PLD_ORT1, 0x40011ab2\r
+.set CYREG_B1_P5_U1_PLD_ORT2, 0x40011ab4\r
+.set CYREG_B1_P5_U1_PLD_ORT3, 0x40011ab6\r
+.set CYREG_B1_P5_U1_MC_CFG_CEN_CONST, 0x40011ab8\r
+.set CYREG_B1_P5_U1_MC_CFG_XORFB, 0x40011aba\r
+.set CYREG_B1_P5_U1_MC_CFG_SET_RESET, 0x40011abc\r
+.set CYREG_B1_P5_U1_MC_CFG_BYPASS, 0x40011abe\r
+.set CYREG_B1_P5_U1_CFG0, 0x40011ac0\r
+.set CYREG_B1_P5_U1_CFG1, 0x40011ac1\r
+.set CYREG_B1_P5_U1_CFG2, 0x40011ac2\r
+.set CYREG_B1_P5_U1_CFG3, 0x40011ac3\r
+.set CYREG_B1_P5_U1_CFG4, 0x40011ac4\r
+.set CYREG_B1_P5_U1_CFG5, 0x40011ac5\r
+.set CYREG_B1_P5_U1_CFG6, 0x40011ac6\r
+.set CYREG_B1_P5_U1_CFG7, 0x40011ac7\r
+.set CYREG_B1_P5_U1_CFG8, 0x40011ac8\r
+.set CYREG_B1_P5_U1_CFG9, 0x40011ac9\r
+.set CYREG_B1_P5_U1_CFG10, 0x40011aca\r
+.set CYREG_B1_P5_U1_CFG11, 0x40011acb\r
+.set CYREG_B1_P5_U1_CFG12, 0x40011acc\r
+.set CYREG_B1_P5_U1_CFG13, 0x40011acd\r
+.set CYREG_B1_P5_U1_CFG14, 0x40011ace\r
+.set CYREG_B1_P5_U1_CFG15, 0x40011acf\r
+.set CYREG_B1_P5_U1_CFG16, 0x40011ad0\r
+.set CYREG_B1_P5_U1_CFG17, 0x40011ad1\r
+.set CYREG_B1_P5_U1_CFG18, 0x40011ad2\r
+.set CYREG_B1_P5_U1_CFG19, 0x40011ad3\r
+.set CYREG_B1_P5_U1_CFG20, 0x40011ad4\r
+.set CYREG_B1_P5_U1_CFG21, 0x40011ad5\r
+.set CYREG_B1_P5_U1_CFG22, 0x40011ad6\r
+.set CYREG_B1_P5_U1_CFG23, 0x40011ad7\r
+.set CYREG_B1_P5_U1_CFG24, 0x40011ad8\r
+.set CYREG_B1_P5_U1_CFG25, 0x40011ad9\r
+.set CYREG_B1_P5_U1_CFG26, 0x40011ada\r
+.set CYREG_B1_P5_U1_CFG27, 0x40011adb\r
+.set CYREG_B1_P5_U1_CFG28, 0x40011adc\r
+.set CYREG_B1_P5_U1_CFG29, 0x40011add\r
+.set CYREG_B1_P5_U1_CFG30, 0x40011ade\r
+.set CYREG_B1_P5_U1_CFG31, 0x40011adf\r
+.set CYREG_B1_P5_U1_DCFG0, 0x40011ae0\r
+.set CYREG_B1_P5_U1_DCFG1, 0x40011ae2\r
+.set CYREG_B1_P5_U1_DCFG2, 0x40011ae4\r
+.set CYREG_B1_P5_U1_DCFG3, 0x40011ae6\r
+.set CYREG_B1_P5_U1_DCFG4, 0x40011ae8\r
+.set CYREG_B1_P5_U1_DCFG5, 0x40011aea\r
+.set CYREG_B1_P5_U1_DCFG6, 0x40011aec\r
+.set CYREG_B1_P5_U1_DCFG7, 0x40011aee\r
+.set CYDEV_UCFG_B1_P5_ROUTE_BASE, 0x40011b00\r
+.set CYDEV_UCFG_B1_P5_ROUTE_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI0_BASE, 0x40014000\r
+.set CYDEV_UCFG_DSI0_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI1_BASE, 0x40014100\r
+.set CYDEV_UCFG_DSI1_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI2_BASE, 0x40014200\r
+.set CYDEV_UCFG_DSI2_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI3_BASE, 0x40014300\r
+.set CYDEV_UCFG_DSI3_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI4_BASE, 0x40014400\r
+.set CYDEV_UCFG_DSI4_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI5_BASE, 0x40014500\r
+.set CYDEV_UCFG_DSI5_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI6_BASE, 0x40014600\r
+.set CYDEV_UCFG_DSI6_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI7_BASE, 0x40014700\r
+.set CYDEV_UCFG_DSI7_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI8_BASE, 0x40014800\r
+.set CYDEV_UCFG_DSI8_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI9_BASE, 0x40014900\r
+.set CYDEV_UCFG_DSI9_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI12_BASE, 0x40014c00\r
+.set CYDEV_UCFG_DSI12_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_DSI13_BASE, 0x40014d00\r
+.set CYDEV_UCFG_DSI13_SIZE, 0x000000ef\r
+.set CYDEV_UCFG_BCTL0_BASE, 0x40015000\r
+.set CYDEV_UCFG_BCTL0_SIZE, 0x00000010\r
+.set CYREG_BCTL0_MDCLK_EN, 0x40015000\r
+.set CYREG_BCTL0_MBCLK_EN, 0x40015001\r
+.set CYREG_BCTL0_WAIT_CFG, 0x40015002\r
+.set CYREG_BCTL0_BANK_CTL, 0x40015003\r
+.set CYREG_BCTL0_UDB_TEST_3, 0x40015007\r
+.set CYREG_BCTL0_DCLK_EN0, 0x40015008\r
+.set CYREG_BCTL0_BCLK_EN0, 0x40015009\r
+.set CYREG_BCTL0_DCLK_EN1, 0x4001500a\r
+.set CYREG_BCTL0_BCLK_EN1, 0x4001500b\r
+.set CYREG_BCTL0_DCLK_EN2, 0x4001500c\r
+.set CYREG_BCTL0_BCLK_EN2, 0x4001500d\r
+.set CYREG_BCTL0_DCLK_EN3, 0x4001500e\r
+.set CYREG_BCTL0_BCLK_EN3, 0x4001500f\r
+.set CYDEV_UCFG_BCTL1_BASE, 0x40015010\r
+.set CYDEV_UCFG_BCTL1_SIZE, 0x00000010\r
+.set CYREG_BCTL1_MDCLK_EN, 0x40015010\r
+.set CYREG_BCTL1_MBCLK_EN, 0x40015011\r
+.set CYREG_BCTL1_WAIT_CFG, 0x40015012\r
+.set CYREG_BCTL1_BANK_CTL, 0x40015013\r
+.set CYREG_BCTL1_UDB_TEST_3, 0x40015017\r
+.set CYREG_BCTL1_DCLK_EN0, 0x40015018\r
+.set CYREG_BCTL1_BCLK_EN0, 0x40015019\r
+.set CYREG_BCTL1_DCLK_EN1, 0x4001501a\r
+.set CYREG_BCTL1_BCLK_EN1, 0x4001501b\r
+.set CYREG_BCTL1_DCLK_EN2, 0x4001501c\r
+.set CYREG_BCTL1_BCLK_EN2, 0x4001501d\r
+.set CYREG_BCTL1_DCLK_EN3, 0x4001501e\r
+.set CYREG_BCTL1_BCLK_EN3, 0x4001501f\r
+.set CYDEV_IDMUX_BASE, 0x40015100\r
+.set CYDEV_IDMUX_SIZE, 0x00000016\r
+.set CYREG_IDMUX_IRQ_CTL0, 0x40015100\r
+.set CYREG_IDMUX_IRQ_CTL1, 0x40015101\r
+.set CYREG_IDMUX_IRQ_CTL2, 0x40015102\r
+.set CYREG_IDMUX_IRQ_CTL3, 0x40015103\r
+.set CYREG_IDMUX_IRQ_CTL4, 0x40015104\r
+.set CYREG_IDMUX_IRQ_CTL5, 0x40015105\r
+.set CYREG_IDMUX_IRQ_CTL6, 0x40015106\r
+.set CYREG_IDMUX_IRQ_CTL7, 0x40015107\r
+.set CYREG_IDMUX_DRQ_CTL0, 0x40015110\r
+.set CYREG_IDMUX_DRQ_CTL1, 0x40015111\r
+.set CYREG_IDMUX_DRQ_CTL2, 0x40015112\r
+.set CYREG_IDMUX_DRQ_CTL3, 0x40015113\r
+.set CYREG_IDMUX_DRQ_CTL4, 0x40015114\r
+.set CYREG_IDMUX_DRQ_CTL5, 0x40015115\r
+.set CYDEV_CACHERAM_BASE, 0x40030000\r
+.set CYDEV_CACHERAM_SIZE, 0x00000400\r
+.set CYREG_CACHERAM_DATA_MBASE, 0x40030000\r
+.set CYREG_CACHERAM_DATA_MSIZE, 0x00000400\r
+.set CYDEV_SFR_BASE, 0x40050100\r
+.set CYDEV_SFR_SIZE, 0x000000fb\r
+.set CYREG_SFR_GPIO0, 0x40050180\r
+.set CYREG_SFR_GPIRD0, 0x40050189\r
+.set CYREG_SFR_GPIO0_SEL, 0x4005018a\r
+.set CYREG_SFR_GPIO1, 0x40050190\r
+.set CYREG_SFR_GPIRD1, 0x40050191\r
+.set CYREG_SFR_GPIO2, 0x40050198\r
+.set CYREG_SFR_GPIRD2, 0x40050199\r
+.set CYREG_SFR_GPIO2_SEL, 0x4005019a\r
+.set CYREG_SFR_GPIO1_SEL, 0x400501a2\r
+.set CYREG_SFR_GPIO3, 0x400501b0\r
+.set CYREG_SFR_GPIRD3, 0x400501b1\r
+.set CYREG_SFR_GPIO3_SEL, 0x400501b2\r
+.set CYREG_SFR_GPIO4, 0x400501c0\r
+.set CYREG_SFR_GPIRD4, 0x400501c1\r
+.set CYREG_SFR_GPIO4_SEL, 0x400501c2\r
+.set CYREG_SFR_GPIO5, 0x400501c8\r
+.set CYREG_SFR_GPIRD5, 0x400501c9\r
+.set CYREG_SFR_GPIO5_SEL, 0x400501ca\r
+.set CYREG_SFR_GPIO6, 0x400501d8\r
+.set CYREG_SFR_GPIRD6, 0x400501d9\r
+.set CYREG_SFR_GPIO6_SEL, 0x400501da\r
+.set CYREG_SFR_GPIO12, 0x400501e8\r
+.set CYREG_SFR_GPIRD12, 0x400501e9\r
+.set CYREG_SFR_GPIO12_SEL, 0x400501f2\r
+.set CYREG_SFR_GPIO15, 0x400501f8\r
+.set CYREG_SFR_GPIRD15, 0x400501f9\r
+.set CYREG_SFR_GPIO15_SEL, 0x400501fa\r
+.set CYDEV_P3BA_BASE, 0x40050300\r
+.set CYDEV_P3BA_SIZE, 0x0000002b\r
+.set CYREG_P3BA_Y_START, 0x40050300\r
+.set CYREG_P3BA_YROLL, 0x40050301\r
+.set CYREG_P3BA_YCFG, 0x40050302\r
+.set CYREG_P3BA_X_START1, 0x40050303\r
+.set CYREG_P3BA_X_START2, 0x40050304\r
+.set CYREG_P3BA_XROLL1, 0x40050305\r
+.set CYREG_P3BA_XROLL2, 0x40050306\r
+.set CYREG_P3BA_XINC, 0x40050307\r
+.set CYREG_P3BA_XCFG, 0x40050308\r
+.set CYREG_P3BA_OFFSETADDR1, 0x40050309\r
+.set CYREG_P3BA_OFFSETADDR2, 0x4005030a\r
+.set CYREG_P3BA_OFFSETADDR3, 0x4005030b\r
+.set CYREG_P3BA_ABSADDR1, 0x4005030c\r
+.set CYREG_P3BA_ABSADDR2, 0x4005030d\r
+.set CYREG_P3BA_ABSADDR3, 0x4005030e\r
+.set CYREG_P3BA_ABSADDR4, 0x4005030f\r
+.set CYREG_P3BA_DATCFG1, 0x40050310\r
+.set CYREG_P3BA_DATCFG2, 0x40050311\r
+.set CYREG_P3BA_CMP_RSLT1, 0x40050314\r
+.set CYREG_P3BA_CMP_RSLT2, 0x40050315\r
+.set CYREG_P3BA_CMP_RSLT3, 0x40050316\r
+.set CYREG_P3BA_CMP_RSLT4, 0x40050317\r
+.set CYREG_P3BA_DATA_REG1, 0x40050318\r
+.set CYREG_P3BA_DATA_REG2, 0x40050319\r
+.set CYREG_P3BA_DATA_REG3, 0x4005031a\r
+.set CYREG_P3BA_DATA_REG4, 0x4005031b\r
+.set CYREG_P3BA_EXP_DATA1, 0x4005031c\r
+.set CYREG_P3BA_EXP_DATA2, 0x4005031d\r
+.set CYREG_P3BA_EXP_DATA3, 0x4005031e\r
+.set CYREG_P3BA_EXP_DATA4, 0x4005031f\r
+.set CYREG_P3BA_MSTR_HRDATA1, 0x40050320\r
+.set CYREG_P3BA_MSTR_HRDATA2, 0x40050321\r
+.set CYREG_P3BA_MSTR_HRDATA3, 0x40050322\r
+.set CYREG_P3BA_MSTR_HRDATA4, 0x40050323\r
+.set CYREG_P3BA_BIST_EN, 0x40050324\r
+.set CYREG_P3BA_PHUB_MASTER_SSR, 0x40050325\r
+.set CYREG_P3BA_SEQCFG1, 0x40050326\r
+.set CYREG_P3BA_SEQCFG2, 0x40050327\r
+.set CYREG_P3BA_Y_CURR, 0x40050328\r
+.set CYREG_P3BA_X_CURR1, 0x40050329\r
+.set CYREG_P3BA_X_CURR2, 0x4005032a\r
+.set CYDEV_PANTHER_BASE, 0x40080000\r
+.set CYDEV_PANTHER_SIZE, 0x00000020\r
+.set CYREG_PANTHER_STCALIB_CFG, 0x40080000\r
+.set CYREG_PANTHER_WAITPIPE, 0x40080004\r
+.set CYREG_PANTHER_TRACE_CFG, 0x40080008\r
+.set CYREG_PANTHER_DBG_CFG, 0x4008000c\r
+.set CYREG_PANTHER_CM3_LCKRST_STAT, 0x40080018\r
+.set CYREG_PANTHER_DEVICE_ID, 0x4008001c\r
+.set CYDEV_FLSECC_BASE, 0x48000000\r
+.set CYDEV_FLSECC_SIZE, 0x00008000\r
+.set CYREG_FLSECC_DATA_MBASE, 0x48000000\r
+.set CYREG_FLSECC_DATA_MSIZE, 0x00008000\r
+.set CYDEV_FLSHID_BASE, 0x49000000\r
+.set CYDEV_FLSHID_SIZE, 0x00000200\r
+.set CYREG_FLSHID_RSVD_MBASE, 0x49000000\r
+.set CYREG_FLSHID_RSVD_MSIZE, 0x00000080\r
+.set CYREG_FLSHID_CUST_MDATA_MBASE, 0x49000080\r
+.set CYREG_FLSHID_CUST_MDATA_MSIZE, 0x00000080\r
+.set CYDEV_FLSHID_CUST_TABLES_BASE, 0x49000100\r
+.set CYDEV_FLSHID_CUST_TABLES_SIZE, 0x00000040\r
+.set CYREG_FLSHID_CUST_TABLES_Y_LOC, 0x49000100\r
+.set CYREG_FLSHID_CUST_TABLES_X_LOC, 0x49000101\r
+.set CYREG_FLSHID_CUST_TABLES_WAFER_NUM, 0x49000102\r
+.set CYREG_FLSHID_CUST_TABLES_LOT_LSB, 0x49000103\r
+.set CYREG_FLSHID_CUST_TABLES_LOT_MSB, 0x49000104\r
+.set CYREG_FLSHID_CUST_TABLES_WRK_WK, 0x49000105\r
+.set CYREG_FLSHID_CUST_TABLES_FAB_YR, 0x49000106\r
+.set CYREG_FLSHID_CUST_TABLES_MINOR, 0x49000107\r
+.set CYREG_FLSHID_CUST_TABLES_IMO_3MHZ, 0x49000108\r
+.set CYREG_FLSHID_CUST_TABLES_IMO_6MHZ, 0x49000109\r
+.set CYREG_FLSHID_CUST_TABLES_IMO_12MHZ, 0x4900010a\r
+.set CYREG_FLSHID_CUST_TABLES_IMO_24MHZ, 0x4900010b\r
+.set CYREG_FLSHID_CUST_TABLES_IMO_67MHZ, 0x4900010c\r
+.set CYREG_FLSHID_CUST_TABLES_IMO_80MHZ, 0x4900010d\r
+.set CYREG_FLSHID_CUST_TABLES_IMO_92MHZ, 0x4900010e\r
+.set CYREG_FLSHID_CUST_TABLES_IMO_USB, 0x4900010f\r
+.set CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS, 0x49000110\r
+.set CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS, 0x49000111\r
+.set CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS, 0x49000112\r
+.set CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS, 0x49000113\r
+.set CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS, 0x49000114\r
+.set CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS, 0x49000115\r
+.set CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS, 0x49000116\r
+.set CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS, 0x49000117\r
+.set CYREG_FLSHID_CUST_TABLES_DEC_M1, 0x49000118\r
+.set CYREG_FLSHID_CUST_TABLES_DEC_M2, 0x49000119\r
+.set CYREG_FLSHID_CUST_TABLES_DEC_M3, 0x4900011a\r
+.set CYREG_FLSHID_CUST_TABLES_DEC_M4, 0x4900011b\r
+.set CYREG_FLSHID_CUST_TABLES_DEC_M5, 0x4900011c\r
+.set CYREG_FLSHID_CUST_TABLES_DEC_M6, 0x4900011d\r
+.set CYREG_FLSHID_CUST_TABLES_DEC_M7, 0x4900011e\r
+.set CYREG_FLSHID_CUST_TABLES_DEC_M8, 0x4900011f\r
+.set CYREG_FLSHID_CUST_TABLES_DAC0_M1, 0x49000120\r
+.set CYREG_FLSHID_CUST_TABLES_DAC0_M2, 0x49000121\r
+.set CYREG_FLSHID_CUST_TABLES_DAC0_M3, 0x49000122\r
+.set CYREG_FLSHID_CUST_TABLES_DAC0_M4, 0x49000123\r
+.set CYREG_FLSHID_CUST_TABLES_DAC0_M5, 0x49000124\r
+.set CYREG_FLSHID_CUST_TABLES_DAC0_M6, 0x49000125\r
+.set CYREG_FLSHID_CUST_TABLES_DAC0_M7, 0x49000126\r
+.set CYREG_FLSHID_CUST_TABLES_DAC0_M8, 0x49000127\r
+.set CYREG_FLSHID_CUST_TABLES_DAC2_M1, 0x49000128\r
+.set CYREG_FLSHID_CUST_TABLES_DAC2_M2, 0x49000129\r
+.set CYREG_FLSHID_CUST_TABLES_DAC2_M3, 0x4900012a\r
+.set CYREG_FLSHID_CUST_TABLES_DAC2_M4, 0x4900012b\r
+.set CYREG_FLSHID_CUST_TABLES_DAC2_M5, 0x4900012c\r
+.set CYREG_FLSHID_CUST_TABLES_DAC2_M6, 0x4900012d\r
+.set CYREG_FLSHID_CUST_TABLES_DAC2_M7, 0x4900012e\r
+.set CYREG_FLSHID_CUST_TABLES_DAC2_M8, 0x4900012f\r
+.set CYREG_FLSHID_CUST_TABLES_DAC1_M1, 0x49000130\r
+.set CYREG_FLSHID_CUST_TABLES_DAC1_M2, 0x49000131\r
+.set CYREG_FLSHID_CUST_TABLES_DAC1_M3, 0x49000132\r
+.set CYREG_FLSHID_CUST_TABLES_DAC1_M4, 0x49000133\r
+.set CYREG_FLSHID_CUST_TABLES_DAC1_M5, 0x49000134\r
+.set CYREG_FLSHID_CUST_TABLES_DAC1_M6, 0x49000135\r
+.set CYREG_FLSHID_CUST_TABLES_DAC1_M7, 0x49000136\r
+.set CYREG_FLSHID_CUST_TABLES_DAC1_M8, 0x49000137\r
+.set CYREG_FLSHID_CUST_TABLES_DAC3_M1, 0x49000138\r
+.set CYREG_FLSHID_CUST_TABLES_DAC3_M2, 0x49000139\r
+.set CYREG_FLSHID_CUST_TABLES_DAC3_M3, 0x4900013a\r
+.set CYREG_FLSHID_CUST_TABLES_DAC3_M4, 0x4900013b\r
+.set CYREG_FLSHID_CUST_TABLES_DAC3_M5, 0x4900013c\r
+.set CYREG_FLSHID_CUST_TABLES_DAC3_M6, 0x4900013d\r
+.set CYREG_FLSHID_CUST_TABLES_DAC3_M7, 0x4900013e\r
+.set CYREG_FLSHID_CUST_TABLES_DAC3_M8, 0x4900013f\r
+.set CYDEV_FLSHID_MFG_CFG_BASE, 0x49000180\r
+.set CYDEV_FLSHID_MFG_CFG_SIZE, 0x00000080\r
+.set CYREG_FLSHID_MFG_CFG_IMO_TR1, 0x49000188\r
+.set CYREG_FLSHID_MFG_CFG_CMP0_TR0, 0x490001ac\r
+.set CYREG_FLSHID_MFG_CFG_CMP1_TR0, 0x490001ae\r
+.set CYREG_FLSHID_MFG_CFG_CMP2_TR0, 0x490001b0\r
+.set CYREG_FLSHID_MFG_CFG_CMP3_TR0, 0x490001b2\r
+.set CYREG_FLSHID_MFG_CFG_CMP0_TR1, 0x490001b4\r
+.set CYREG_FLSHID_MFG_CFG_CMP1_TR1, 0x490001b6\r
+.set CYREG_FLSHID_MFG_CFG_CMP2_TR1, 0x490001b8\r
+.set CYREG_FLSHID_MFG_CFG_CMP3_TR1, 0x490001ba\r
+.set CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM, 0x490001ce\r
+.set CYDEV_EXTMEM_BASE, 0x60000000\r
+.set CYDEV_EXTMEM_SIZE, 0x00800000\r
+.set CYREG_EXTMEM_DATA_MBASE, 0x60000000\r
+.set CYREG_EXTMEM_DATA_MSIZE, 0x00800000\r
+.set CYDEV_ITM_BASE, 0xe0000000\r
+.set CYDEV_ITM_SIZE, 0x00001000\r
+.set CYREG_ITM_TRACE_EN, 0xe0000e00\r
+.set CYREG_ITM_TRACE_PRIVILEGE, 0xe0000e40\r
+.set CYREG_ITM_TRACE_CTRL, 0xe0000e80\r
+.set CYREG_ITM_LOCK_ACCESS, 0xe0000fb0\r
+.set CYREG_ITM_LOCK_STATUS, 0xe0000fb4\r
+.set CYREG_ITM_PID4, 0xe0000fd0\r
+.set CYREG_ITM_PID5, 0xe0000fd4\r
+.set CYREG_ITM_PID6, 0xe0000fd8\r
+.set CYREG_ITM_PID7, 0xe0000fdc\r
+.set CYREG_ITM_PID0, 0xe0000fe0\r
+.set CYREG_ITM_PID1, 0xe0000fe4\r
+.set CYREG_ITM_PID2, 0xe0000fe8\r
+.set CYREG_ITM_PID3, 0xe0000fec\r
+.set CYREG_ITM_CID0, 0xe0000ff0\r
+.set CYREG_ITM_CID1, 0xe0000ff4\r
+.set CYREG_ITM_CID2, 0xe0000ff8\r
+.set CYREG_ITM_CID3, 0xe0000ffc\r
+.set CYDEV_DWT_BASE, 0xe0001000\r
+.set CYDEV_DWT_SIZE, 0x0000005c\r
+.set CYREG_DWT_CTRL, 0xe0001000\r
+.set CYREG_DWT_CYCLE_COUNT, 0xe0001004\r
+.set CYREG_DWT_CPI_COUNT, 0xe0001008\r
+.set CYREG_DWT_EXC_OVHD_COUNT, 0xe000100c\r
+.set CYREG_DWT_SLEEP_COUNT, 0xe0001010\r
+.set CYREG_DWT_LSU_COUNT, 0xe0001014\r
+.set CYREG_DWT_FOLD_COUNT, 0xe0001018\r
+.set CYREG_DWT_PC_SAMPLE, 0xe000101c\r
+.set CYREG_DWT_COMP_0, 0xe0001020\r
+.set CYREG_DWT_MASK_0, 0xe0001024\r
+.set CYREG_DWT_FUNCTION_0, 0xe0001028\r
+.set CYREG_DWT_COMP_1, 0xe0001030\r
+.set CYREG_DWT_MASK_1, 0xe0001034\r
+.set CYREG_DWT_FUNCTION_1, 0xe0001038\r
+.set CYREG_DWT_COMP_2, 0xe0001040\r
+.set CYREG_DWT_MASK_2, 0xe0001044\r
+.set CYREG_DWT_FUNCTION_2, 0xe0001048\r
+.set CYREG_DWT_COMP_3, 0xe0001050\r
+.set CYREG_DWT_MASK_3, 0xe0001054\r
+.set CYREG_DWT_FUNCTION_3, 0xe0001058\r
+.set CYDEV_FPB_BASE, 0xe0002000\r
+.set CYDEV_FPB_SIZE, 0x00001000\r
+.set CYREG_FPB_CTRL, 0xe0002000\r
+.set CYREG_FPB_REMAP, 0xe0002004\r
+.set CYREG_FPB_FP_COMP_0, 0xe0002008\r
+.set CYREG_FPB_FP_COMP_1, 0xe000200c\r
+.set CYREG_FPB_FP_COMP_2, 0xe0002010\r
+.set CYREG_FPB_FP_COMP_3, 0xe0002014\r
+.set CYREG_FPB_FP_COMP_4, 0xe0002018\r
+.set CYREG_FPB_FP_COMP_5, 0xe000201c\r
+.set CYREG_FPB_FP_COMP_6, 0xe0002020\r
+.set CYREG_FPB_FP_COMP_7, 0xe0002024\r
+.set CYREG_FPB_PID4, 0xe0002fd0\r
+.set CYREG_FPB_PID5, 0xe0002fd4\r
+.set CYREG_FPB_PID6, 0xe0002fd8\r
+.set CYREG_FPB_PID7, 0xe0002fdc\r
+.set CYREG_FPB_PID0, 0xe0002fe0\r
+.set CYREG_FPB_PID1, 0xe0002fe4\r
+.set CYREG_FPB_PID2, 0xe0002fe8\r
+.set CYREG_FPB_PID3, 0xe0002fec\r
+.set CYREG_FPB_CID0, 0xe0002ff0\r
+.set CYREG_FPB_CID1, 0xe0002ff4\r
+.set CYREG_FPB_CID2, 0xe0002ff8\r
+.set CYREG_FPB_CID3, 0xe0002ffc\r
+.set CYDEV_NVIC_BASE, 0xe000e000\r
+.set CYDEV_NVIC_SIZE, 0x00000d3c\r
+.set CYREG_NVIC_INT_CTL_TYPE, 0xe000e004\r
+.set CYREG_NVIC_SYSTICK_CTL, 0xe000e010\r
+.set CYREG_NVIC_SYSTICK_RELOAD, 0xe000e014\r
+.set CYREG_NVIC_SYSTICK_CURRENT, 0xe000e018\r
+.set CYREG_NVIC_SYSTICK_CAL, 0xe000e01c\r
+.set CYREG_NVIC_SETENA0, 0xe000e100\r
+.set CYREG_NVIC_CLRENA0, 0xe000e180\r
+.set CYREG_NVIC_SETPEND0, 0xe000e200\r
+.set CYREG_NVIC_CLRPEND0, 0xe000e280\r
+.set CYREG_NVIC_ACTIVE0, 0xe000e300\r
+.set CYREG_NVIC_PRI_0, 0xe000e400\r
+.set CYREG_NVIC_PRI_1, 0xe000e401\r
+.set CYREG_NVIC_PRI_2, 0xe000e402\r
+.set CYREG_NVIC_PRI_3, 0xe000e403\r
+.set CYREG_NVIC_PRI_4, 0xe000e404\r
+.set CYREG_NVIC_PRI_5, 0xe000e405\r
+.set CYREG_NVIC_PRI_6, 0xe000e406\r
+.set CYREG_NVIC_PRI_7, 0xe000e407\r
+.set CYREG_NVIC_PRI_8, 0xe000e408\r
+.set CYREG_NVIC_PRI_9, 0xe000e409\r
+.set CYREG_NVIC_PRI_10, 0xe000e40a\r
+.set CYREG_NVIC_PRI_11, 0xe000e40b\r
+.set CYREG_NVIC_PRI_12, 0xe000e40c\r
+.set CYREG_NVIC_PRI_13, 0xe000e40d\r
+.set CYREG_NVIC_PRI_14, 0xe000e40e\r
+.set CYREG_NVIC_PRI_15, 0xe000e40f\r
+.set CYREG_NVIC_PRI_16, 0xe000e410\r
+.set CYREG_NVIC_PRI_17, 0xe000e411\r
+.set CYREG_NVIC_PRI_18, 0xe000e412\r
+.set CYREG_NVIC_PRI_19, 0xe000e413\r
+.set CYREG_NVIC_PRI_20, 0xe000e414\r
+.set CYREG_NVIC_PRI_21, 0xe000e415\r
+.set CYREG_NVIC_PRI_22, 0xe000e416\r
+.set CYREG_NVIC_PRI_23, 0xe000e417\r
+.set CYREG_NVIC_PRI_24, 0xe000e418\r
+.set CYREG_NVIC_PRI_25, 0xe000e419\r
+.set CYREG_NVIC_PRI_26, 0xe000e41a\r
+.set CYREG_NVIC_PRI_27, 0xe000e41b\r
+.set CYREG_NVIC_PRI_28, 0xe000e41c\r
+.set CYREG_NVIC_PRI_29, 0xe000e41d\r
+.set CYREG_NVIC_PRI_30, 0xe000e41e\r
+.set CYREG_NVIC_PRI_31, 0xe000e41f\r
+.set CYREG_NVIC_CPUID_BASE, 0xe000ed00\r
+.set CYREG_NVIC_INTR_CTRL_STATE, 0xe000ed04\r
+.set CYREG_NVIC_VECT_OFFSET, 0xe000ed08\r
+.set CYREG_NVIC_APPLN_INTR, 0xe000ed0c\r
+.set CYREG_NVIC_SYSTEM_CONTROL, 0xe000ed10\r
+.set CYREG_NVIC_CFG_CONTROL, 0xe000ed14\r
+.set CYREG_NVIC_SYS_PRIO_HANDLER_4_7, 0xe000ed18\r
+.set CYREG_NVIC_SYS_PRIO_HANDLER_8_11, 0xe000ed1c\r
+.set CYREG_NVIC_SYS_PRIO_HANDLER_12_15, 0xe000ed20\r
+.set CYREG_NVIC_SYS_HANDLER_CSR, 0xe000ed24\r
+.set CYREG_NVIC_MEMMAN_FAULT_STATUS, 0xe000ed28\r
+.set CYREG_NVIC_BUS_FAULT_STATUS, 0xe000ed29\r
+.set CYREG_NVIC_USAGE_FAULT_STATUS, 0xe000ed2a\r
+.set CYREG_NVIC_HARD_FAULT_STATUS, 0xe000ed2c\r
+.set CYREG_NVIC_DEBUG_FAULT_STATUS, 0xe000ed30\r
+.set CYREG_NVIC_MEMMAN_FAULT_ADD, 0xe000ed34\r
+.set CYREG_NVIC_BUS_FAULT_ADD, 0xe000ed38\r
+.set CYDEV_CORE_DBG_BASE, 0xe000edf0\r
+.set CYDEV_CORE_DBG_SIZE, 0x00000010\r
+.set CYREG_CORE_DBG_DBG_HLT_CS, 0xe000edf0\r
+.set CYREG_CORE_DBG_DBG_REG_SEL, 0xe000edf4\r
+.set CYREG_CORE_DBG_DBG_REG_DATA, 0xe000edf8\r
+.set CYREG_CORE_DBG_EXC_MON_CTL, 0xe000edfc\r
+.set CYDEV_TPIU_BASE, 0xe0040000\r
+.set CYDEV_TPIU_SIZE, 0x00001000\r
+.set CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ, 0xe0040000\r
+.set CYREG_TPIU_CURRENT_SYNC_PRT_SZ, 0xe0040004\r
+.set CYREG_TPIU_ASYNC_CLK_PRESCALER, 0xe0040010\r
+.set CYREG_TPIU_PROTOCOL, 0xe00400f0\r
+.set CYREG_TPIU_FORM_FLUSH_STAT, 0xe0040300\r
+.set CYREG_TPIU_FORM_FLUSH_CTRL, 0xe0040304\r
+.set CYREG_TPIU_TRIGGER, 0xe0040ee8\r
+.set CYREG_TPIU_ITETMDATA, 0xe0040eec\r
+.set CYREG_TPIU_ITATBCTR2, 0xe0040ef0\r
+.set CYREG_TPIU_ITATBCTR0, 0xe0040ef8\r
+.set CYREG_TPIU_ITITMDATA, 0xe0040efc\r
+.set CYREG_TPIU_ITCTRL, 0xe0040f00\r
+.set CYREG_TPIU_DEVID, 0xe0040fc8\r
+.set CYREG_TPIU_DEVTYPE, 0xe0040fcc\r
+.set CYREG_TPIU_PID4, 0xe0040fd0\r
+.set CYREG_TPIU_PID5, 0xe0040fd4\r
+.set CYREG_TPIU_PID6, 0xe0040fd8\r
+.set CYREG_TPIU_PID7, 0xe0040fdc\r
+.set CYREG_TPIU_PID0, 0xe0040fe0\r
+.set CYREG_TPIU_PID1, 0xe0040fe4\r
+.set CYREG_TPIU_PID2, 0xe0040fe8\r
+.set CYREG_TPIU_PID3, 0xe0040fec\r
+.set CYREG_TPIU_CID0, 0xe0040ff0\r
+.set CYREG_TPIU_CID1, 0xe0040ff4\r
+.set CYREG_TPIU_CID2, 0xe0040ff8\r
+.set CYREG_TPIU_CID3, 0xe0040ffc\r
+.set CYDEV_ETM_BASE, 0xe0041000\r
+.set CYDEV_ETM_SIZE, 0x00001000\r
+.set CYREG_ETM_CTL, 0xe0041000\r
+.set CYREG_ETM_CFG_CODE, 0xe0041004\r
+.set CYREG_ETM_TRIG_EVENT, 0xe0041008\r
+.set CYREG_ETM_STATUS, 0xe0041010\r
+.set CYREG_ETM_SYS_CFG, 0xe0041014\r
+.set CYREG_ETM_TRACE_ENB_EVENT, 0xe0041020\r
+.set CYREG_ETM_TRACE_EN_CTRL1, 0xe0041024\r
+.set CYREG_ETM_FIFOFULL_LEVEL, 0xe004102c\r
+.set CYREG_ETM_SYNC_FREQ, 0xe00411e0\r
+.set CYREG_ETM_ETM_ID, 0xe00411e4\r
+.set CYREG_ETM_CFG_CODE_EXT, 0xe00411e8\r
+.set CYREG_ETM_TR_SS_EMBICE_CTRL, 0xe00411f0\r
+.set CYREG_ETM_CS_TRACE_ID, 0xe0041200\r
+.set CYREG_ETM_OS_LOCK_ACCESS, 0xe0041300\r
+.set CYREG_ETM_OS_LOCK_STATUS, 0xe0041304\r
+.set CYREG_ETM_PDSR, 0xe0041314\r
+.set CYREG_ETM_ITMISCIN, 0xe0041ee0\r
+.set CYREG_ETM_ITTRIGOUT, 0xe0041ee8\r
+.set CYREG_ETM_ITATBCTR2, 0xe0041ef0\r
+.set CYREG_ETM_ITATBCTR0, 0xe0041ef8\r
+.set CYREG_ETM_INT_MODE_CTRL, 0xe0041f00\r
+.set CYREG_ETM_CLM_TAG_SET, 0xe0041fa0\r
+.set CYREG_ETM_CLM_TAG_CLR, 0xe0041fa4\r
+.set CYREG_ETM_LOCK_ACCESS, 0xe0041fb0\r
+.set CYREG_ETM_LOCK_STATUS, 0xe0041fb4\r
+.set CYREG_ETM_AUTH_STATUS, 0xe0041fb8\r
+.set CYREG_ETM_DEV_TYPE, 0xe0041fcc\r
+.set CYREG_ETM_PID4, 0xe0041fd0\r
+.set CYREG_ETM_PID5, 0xe0041fd4\r
+.set CYREG_ETM_PID6, 0xe0041fd8\r
+.set CYREG_ETM_PID7, 0xe0041fdc\r
+.set CYREG_ETM_PID0, 0xe0041fe0\r
+.set CYREG_ETM_PID1, 0xe0041fe4\r
+.set CYREG_ETM_PID2, 0xe0041fe8\r
+.set CYREG_ETM_PID3, 0xe0041fec\r
+.set CYREG_ETM_CID0, 0xe0041ff0\r
+.set CYREG_ETM_CID1, 0xe0041ff4\r
+.set CYREG_ETM_CID2, 0xe0041ff8\r
+.set CYREG_ETM_CID3, 0xe0041ffc\r
+.set CYDEV_ROM_TABLE_BASE, 0xe00ff000\r
+.set CYDEV_ROM_TABLE_SIZE, 0x00001000\r
+.set CYREG_ROM_TABLE_NVIC, 0xe00ff000\r
+.set CYREG_ROM_TABLE_DWT, 0xe00ff004\r
+.set CYREG_ROM_TABLE_FPB, 0xe00ff008\r
+.set CYREG_ROM_TABLE_ITM, 0xe00ff00c\r
+.set CYREG_ROM_TABLE_TPIU, 0xe00ff010\r
+.set CYREG_ROM_TABLE_ETM, 0xe00ff014\r
+.set CYREG_ROM_TABLE_END, 0xe00ff018\r
+.set CYREG_ROM_TABLE_MEMTYPE, 0xe00fffcc\r
+.set CYREG_ROM_TABLE_PID4, 0xe00fffd0\r
+.set CYREG_ROM_TABLE_PID5, 0xe00fffd4\r
+.set CYREG_ROM_TABLE_PID6, 0xe00fffd8\r
+.set CYREG_ROM_TABLE_PID7, 0xe00fffdc\r
+.set CYREG_ROM_TABLE_PID0, 0xe00fffe0\r
+.set CYREG_ROM_TABLE_PID1, 0xe00fffe4\r
+.set CYREG_ROM_TABLE_PID2, 0xe00fffe8\r
+.set CYREG_ROM_TABLE_PID3, 0xe00fffec\r
+.set CYREG_ROM_TABLE_CID0, 0xe00ffff0\r
+.set CYREG_ROM_TABLE_CID1, 0xe00ffff4\r
+.set CYREG_ROM_TABLE_CID2, 0xe00ffff8\r
+.set CYREG_ROM_TABLE_CID3, 0xe00ffffc\r
+.set CYDEV_FLS_SIZE, CYDEV_FLASH_SIZE\r
+.set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE\r
+.set CYDEV_FLS_SECTOR_SIZE, 0x00010000\r
+.set CYDEV_FLS_ROW_SIZE, 0x00000100\r
+.set CYDEV_ECC_SECTOR_SIZE, 0x00002000\r
+.set CYDEV_ECC_ROW_SIZE, 0x00000020\r
+.set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400\r
+.set CYDEV_EEPROM_ROW_SIZE, 0x00000010\r
+.set CYDEV_PERIPH_BASE, CYDEV_CLKDIST_BASE\r
+.set CYCLK_LD_DISABLE, 0x00000004\r
+.set CYCLK_LD_SYNC_EN, 0x00000002\r
+.set CYCLK_LD_LOAD, 0x00000001\r
+.set CYCLK_PIPE, 0x00000080\r
+.set CYCLK_SSS, 0x00000040\r
+.set CYCLK_EARLY, 0x00000020\r
+.set CYCLK_DUTY, 0x00000010\r
+.set CYCLK_SYNC, 0x00000008\r
+.set CYCLK_SRC_SEL_CLK_SYNC_D, 0\r
+.set CYCLK_SRC_SEL_SYNC_DIG, 0\r
+.set CYCLK_SRC_SEL_IMO, 1\r
+.set CYCLK_SRC_SEL_XTAL_MHZ, 2\r
+.set CYCLK_SRC_SEL_XTALM, 2\r
+.set CYCLK_SRC_SEL_ILO, 3\r
+.set CYCLK_SRC_SEL_PLL, 4\r
+.set CYCLK_SRC_SEL_XTAL_KHZ, 5\r
+.set CYCLK_SRC_SEL_XTALK, 5\r
+.set CYCLK_SRC_SEL_DSI_G, 6\r
+.set CYCLK_SRC_SEL_DSI_D, 7\r
+.set CYCLK_SRC_SEL_CLK_SYNC_A, 0\r
+.set CYCLK_SRC_SEL_DSI_A, 7\r
--- /dev/null
+;\r
+; FILENAME: cydevicerv.inc\r
+; OBSOLETE: Do not use this file. Use the _trm version instead.\r
+; PSoC Creator 2.2 Component Pack 6\r
+;\r
+; DESCRIPTION:\r
+; This file provides all of the address values for the entire PSoC device.\r
+;\r
+;-------------------------------------------------------------------------------\r
+; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; You may use this file only in accordance with the license, terms, conditions, \r
+; disclaimers, and limitations in the end user license agreement accompanying \r
+; the software package with which this file was provided.\r
+;-------------------------------------------------------------------------------\r
+\r
+ IF :LNOT::DEF:CYDEV_FLASH_BASE\r
+CYDEV_FLASH_BASE EQU 0x00000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLASH_SIZE\r
+CYDEV_FLASH_SIZE EQU 0x00040000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLASH_DATA_MBASE\r
+CYDEV_FLASH_DATA_MBASE EQU 0x00000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLASH_DATA_MSIZE\r
+CYDEV_FLASH_DATA_MSIZE EQU 0x00040000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_BASE\r
+CYDEV_SRAM_BASE EQU 0x1fff8000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_SIZE\r
+CYDEV_SRAM_SIZE EQU 0x00010000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_CODE64K_MBASE\r
+CYDEV_SRAM_CODE64K_MBASE EQU 0x1fff8000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_CODE64K_MSIZE\r
+CYDEV_SRAM_CODE64K_MSIZE EQU 0x00004000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_CODE32K_MBASE\r
+CYDEV_SRAM_CODE32K_MBASE EQU 0x1fffc000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_CODE32K_MSIZE\r
+CYDEV_SRAM_CODE32K_MSIZE EQU 0x00002000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_CODE16K_MBASE\r
+CYDEV_SRAM_CODE16K_MBASE EQU 0x1fffe000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_CODE16K_MSIZE\r
+CYDEV_SRAM_CODE16K_MSIZE EQU 0x00001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_CODE_MBASE\r
+CYDEV_SRAM_CODE_MBASE EQU 0x1fff8000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_CODE_MSIZE\r
+CYDEV_SRAM_CODE_MSIZE EQU 0x00008000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_DATA_MBASE\r
+CYDEV_SRAM_DATA_MBASE EQU 0x20000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_DATA_MSIZE\r
+CYDEV_SRAM_DATA_MSIZE EQU 0x00008000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_DATA16K_MBASE\r
+CYDEV_SRAM_DATA16K_MBASE EQU 0x20001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_DATA16K_MSIZE\r
+CYDEV_SRAM_DATA16K_MSIZE EQU 0x00001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_DATA32K_MBASE\r
+CYDEV_SRAM_DATA32K_MBASE EQU 0x20002000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_DATA32K_MSIZE\r
+CYDEV_SRAM_DATA32K_MSIZE EQU 0x00002000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_DATA64K_MBASE\r
+CYDEV_SRAM_DATA64K_MBASE EQU 0x20004000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_DATA64K_MSIZE\r
+CYDEV_SRAM_DATA64K_MSIZE EQU 0x00004000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DMA_BASE\r
+CYDEV_DMA_BASE EQU 0x20008000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DMA_SIZE\r
+CYDEV_DMA_SIZE EQU 0x00008000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DMA_SRAM64K_MBASE\r
+CYDEV_DMA_SRAM64K_MBASE EQU 0x20008000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DMA_SRAM64K_MSIZE\r
+CYDEV_DMA_SRAM64K_MSIZE EQU 0x00004000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DMA_SRAM32K_MBASE\r
+CYDEV_DMA_SRAM32K_MBASE EQU 0x2000c000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DMA_SRAM32K_MSIZE\r
+CYDEV_DMA_SRAM32K_MSIZE EQU 0x00002000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DMA_SRAM16K_MBASE\r
+CYDEV_DMA_SRAM16K_MBASE EQU 0x2000e000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DMA_SRAM16K_MSIZE\r
+CYDEV_DMA_SRAM16K_MSIZE EQU 0x00001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DMA_SRAM_MBASE\r
+CYDEV_DMA_SRAM_MBASE EQU 0x2000f000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DMA_SRAM_MSIZE\r
+CYDEV_DMA_SRAM_MSIZE EQU 0x00001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_BASE\r
+CYDEV_CLKDIST_BASE EQU 0x40004000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_SIZE\r
+CYDEV_CLKDIST_SIZE EQU 0x00000110\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_CR\r
+CYDEV_CLKDIST_CR EQU 0x40004000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_LD\r
+CYDEV_CLKDIST_LD EQU 0x40004001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_WRK0\r
+CYDEV_CLKDIST_WRK0 EQU 0x40004002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_WRK1\r
+CYDEV_CLKDIST_WRK1 EQU 0x40004003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_MSTR0\r
+CYDEV_CLKDIST_MSTR0 EQU 0x40004004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_MSTR1\r
+CYDEV_CLKDIST_MSTR1 EQU 0x40004005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_BCFG0\r
+CYDEV_CLKDIST_BCFG0 EQU 0x40004006\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_BCFG1\r
+CYDEV_CLKDIST_BCFG1 EQU 0x40004007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_BCFG2\r
+CYDEV_CLKDIST_BCFG2 EQU 0x40004008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_UCFG\r
+CYDEV_CLKDIST_UCFG EQU 0x40004009\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DLY0\r
+CYDEV_CLKDIST_DLY0 EQU 0x4000400a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DLY1\r
+CYDEV_CLKDIST_DLY1 EQU 0x4000400b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DMASK\r
+CYDEV_CLKDIST_DMASK EQU 0x40004010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_AMASK\r
+CYDEV_CLKDIST_AMASK EQU 0x40004014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_BASE\r
+CYDEV_CLKDIST_DCFG0_BASE EQU 0x40004080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_SIZE\r
+CYDEV_CLKDIST_DCFG0_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG0\r
+CYDEV_CLKDIST_DCFG0_CFG0 EQU 0x40004080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG1\r
+CYDEV_CLKDIST_DCFG0_CFG1 EQU 0x40004081\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG2\r
+CYDEV_CLKDIST_DCFG0_CFG2 EQU 0x40004082\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_BASE\r
+CYDEV_CLKDIST_DCFG1_BASE EQU 0x40004084\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_SIZE\r
+CYDEV_CLKDIST_DCFG1_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG0\r
+CYDEV_CLKDIST_DCFG1_CFG0 EQU 0x40004084\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG1\r
+CYDEV_CLKDIST_DCFG1_CFG1 EQU 0x40004085\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG2\r
+CYDEV_CLKDIST_DCFG1_CFG2 EQU 0x40004086\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_BASE\r
+CYDEV_CLKDIST_DCFG2_BASE EQU 0x40004088\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_SIZE\r
+CYDEV_CLKDIST_DCFG2_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG0\r
+CYDEV_CLKDIST_DCFG2_CFG0 EQU 0x40004088\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG1\r
+CYDEV_CLKDIST_DCFG2_CFG1 EQU 0x40004089\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG2\r
+CYDEV_CLKDIST_DCFG2_CFG2 EQU 0x4000408a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_BASE\r
+CYDEV_CLKDIST_DCFG3_BASE EQU 0x4000408c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_SIZE\r
+CYDEV_CLKDIST_DCFG3_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG0\r
+CYDEV_CLKDIST_DCFG3_CFG0 EQU 0x4000408c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG1\r
+CYDEV_CLKDIST_DCFG3_CFG1 EQU 0x4000408d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG2\r
+CYDEV_CLKDIST_DCFG3_CFG2 EQU 0x4000408e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_BASE\r
+CYDEV_CLKDIST_DCFG4_BASE EQU 0x40004090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_SIZE\r
+CYDEV_CLKDIST_DCFG4_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG0\r
+CYDEV_CLKDIST_DCFG4_CFG0 EQU 0x40004090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG1\r
+CYDEV_CLKDIST_DCFG4_CFG1 EQU 0x40004091\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG2\r
+CYDEV_CLKDIST_DCFG4_CFG2 EQU 0x40004092\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_BASE\r
+CYDEV_CLKDIST_DCFG5_BASE EQU 0x40004094\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_SIZE\r
+CYDEV_CLKDIST_DCFG5_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG0\r
+CYDEV_CLKDIST_DCFG5_CFG0 EQU 0x40004094\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG1\r
+CYDEV_CLKDIST_DCFG5_CFG1 EQU 0x40004095\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG2\r
+CYDEV_CLKDIST_DCFG5_CFG2 EQU 0x40004096\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_BASE\r
+CYDEV_CLKDIST_DCFG6_BASE EQU 0x40004098\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_SIZE\r
+CYDEV_CLKDIST_DCFG6_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG0\r
+CYDEV_CLKDIST_DCFG6_CFG0 EQU 0x40004098\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG1\r
+CYDEV_CLKDIST_DCFG6_CFG1 EQU 0x40004099\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG2\r
+CYDEV_CLKDIST_DCFG6_CFG2 EQU 0x4000409a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_BASE\r
+CYDEV_CLKDIST_DCFG7_BASE EQU 0x4000409c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_SIZE\r
+CYDEV_CLKDIST_DCFG7_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG0\r
+CYDEV_CLKDIST_DCFG7_CFG0 EQU 0x4000409c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG1\r
+CYDEV_CLKDIST_DCFG7_CFG1 EQU 0x4000409d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG2\r
+CYDEV_CLKDIST_DCFG7_CFG2 EQU 0x4000409e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_BASE\r
+CYDEV_CLKDIST_ACFG0_BASE EQU 0x40004100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_SIZE\r
+CYDEV_CLKDIST_ACFG0_SIZE EQU 0x00000004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG0\r
+CYDEV_CLKDIST_ACFG0_CFG0 EQU 0x40004100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG1\r
+CYDEV_CLKDIST_ACFG0_CFG1 EQU 0x40004101\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG2\r
+CYDEV_CLKDIST_ACFG0_CFG2 EQU 0x40004102\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG3\r
+CYDEV_CLKDIST_ACFG0_CFG3 EQU 0x40004103\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_BASE\r
+CYDEV_CLKDIST_ACFG1_BASE EQU 0x40004104\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_SIZE\r
+CYDEV_CLKDIST_ACFG1_SIZE EQU 0x00000004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG0\r
+CYDEV_CLKDIST_ACFG1_CFG0 EQU 0x40004104\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG1\r
+CYDEV_CLKDIST_ACFG1_CFG1 EQU 0x40004105\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG2\r
+CYDEV_CLKDIST_ACFG1_CFG2 EQU 0x40004106\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG3\r
+CYDEV_CLKDIST_ACFG1_CFG3 EQU 0x40004107\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_BASE\r
+CYDEV_CLKDIST_ACFG2_BASE EQU 0x40004108\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_SIZE\r
+CYDEV_CLKDIST_ACFG2_SIZE EQU 0x00000004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG0\r
+CYDEV_CLKDIST_ACFG2_CFG0 EQU 0x40004108\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG1\r
+CYDEV_CLKDIST_ACFG2_CFG1 EQU 0x40004109\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG2\r
+CYDEV_CLKDIST_ACFG2_CFG2 EQU 0x4000410a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG3\r
+CYDEV_CLKDIST_ACFG2_CFG3 EQU 0x4000410b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_BASE\r
+CYDEV_CLKDIST_ACFG3_BASE EQU 0x4000410c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_SIZE\r
+CYDEV_CLKDIST_ACFG3_SIZE EQU 0x00000004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG0\r
+CYDEV_CLKDIST_ACFG3_CFG0 EQU 0x4000410c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG1\r
+CYDEV_CLKDIST_ACFG3_CFG1 EQU 0x4000410d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG2\r
+CYDEV_CLKDIST_ACFG3_CFG2 EQU 0x4000410e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG3\r
+CYDEV_CLKDIST_ACFG3_CFG3 EQU 0x4000410f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_BASE\r
+CYDEV_FASTCLK_BASE EQU 0x40004200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_SIZE\r
+CYDEV_FASTCLK_SIZE EQU 0x00000026\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_IMO_BASE\r
+CYDEV_FASTCLK_IMO_BASE EQU 0x40004200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_IMO_SIZE\r
+CYDEV_FASTCLK_IMO_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_IMO_CR\r
+CYDEV_FASTCLK_IMO_CR EQU 0x40004200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_BASE\r
+CYDEV_FASTCLK_XMHZ_BASE EQU 0x40004210\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_SIZE\r
+CYDEV_FASTCLK_XMHZ_SIZE EQU 0x00000004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CSR\r
+CYDEV_FASTCLK_XMHZ_CSR EQU 0x40004210\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CFG0\r
+CYDEV_FASTCLK_XMHZ_CFG0 EQU 0x40004212\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CFG1\r
+CYDEV_FASTCLK_XMHZ_CFG1 EQU 0x40004213\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_PLL_BASE\r
+CYDEV_FASTCLK_PLL_BASE EQU 0x40004220\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SIZE\r
+CYDEV_FASTCLK_PLL_SIZE EQU 0x00000006\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_PLL_CFG0\r
+CYDEV_FASTCLK_PLL_CFG0 EQU 0x40004220\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_PLL_CFG1\r
+CYDEV_FASTCLK_PLL_CFG1 EQU 0x40004221\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_PLL_P\r
+CYDEV_FASTCLK_PLL_P EQU 0x40004222\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_PLL_Q\r
+CYDEV_FASTCLK_PLL_Q EQU 0x40004223\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SR\r
+CYDEV_FASTCLK_PLL_SR EQU 0x40004225\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SLOWCLK_BASE\r
+CYDEV_SLOWCLK_BASE EQU 0x40004300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SLOWCLK_SIZE\r
+CYDEV_SLOWCLK_SIZE EQU 0x0000000b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_BASE\r
+CYDEV_SLOWCLK_ILO_BASE EQU 0x40004300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_SIZE\r
+CYDEV_SLOWCLK_ILO_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_CR0\r
+CYDEV_SLOWCLK_ILO_CR0 EQU 0x40004300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_CR1\r
+CYDEV_SLOWCLK_ILO_CR1 EQU 0x40004301\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SLOWCLK_X32_BASE\r
+CYDEV_SLOWCLK_X32_BASE EQU 0x40004308\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SLOWCLK_X32_SIZE\r
+CYDEV_SLOWCLK_X32_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SLOWCLK_X32_CR\r
+CYDEV_SLOWCLK_X32_CR EQU 0x40004308\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SLOWCLK_X32_CFG\r
+CYDEV_SLOWCLK_X32_CFG EQU 0x40004309\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SLOWCLK_X32_TST\r
+CYDEV_SLOWCLK_X32_TST EQU 0x4000430a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_BOOST_BASE\r
+CYDEV_BOOST_BASE EQU 0x40004320\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_BOOST_SIZE\r
+CYDEV_BOOST_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_BOOST_CR0\r
+CYDEV_BOOST_CR0 EQU 0x40004320\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_BOOST_CR1\r
+CYDEV_BOOST_CR1 EQU 0x40004321\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_BOOST_CR2\r
+CYDEV_BOOST_CR2 EQU 0x40004322\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_BOOST_CR3\r
+CYDEV_BOOST_CR3 EQU 0x40004323\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_BOOST_SR\r
+CYDEV_BOOST_SR EQU 0x40004324\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_BOOST_CR4\r
+CYDEV_BOOST_CR4 EQU 0x40004325\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_BOOST_SR2\r
+CYDEV_BOOST_SR2 EQU 0x40004326\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PWRSYS_BASE\r
+CYDEV_PWRSYS_BASE EQU 0x40004330\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PWRSYS_SIZE\r
+CYDEV_PWRSYS_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PWRSYS_CR0\r
+CYDEV_PWRSYS_CR0 EQU 0x40004330\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PWRSYS_CR1\r
+CYDEV_PWRSYS_CR1 EQU 0x40004331\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_BASE\r
+CYDEV_PM_BASE EQU 0x40004380\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_SIZE\r
+CYDEV_PM_SIZE EQU 0x00000057\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_TW_CFG0\r
+CYDEV_PM_TW_CFG0 EQU 0x40004380\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_TW_CFG1\r
+CYDEV_PM_TW_CFG1 EQU 0x40004381\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_TW_CFG2\r
+CYDEV_PM_TW_CFG2 EQU 0x40004382\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_WDT_CFG\r
+CYDEV_PM_WDT_CFG EQU 0x40004383\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_WDT_CR\r
+CYDEV_PM_WDT_CR EQU 0x40004384\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_INT_SR\r
+CYDEV_PM_INT_SR EQU 0x40004390\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_MODE_CFG0\r
+CYDEV_PM_MODE_CFG0 EQU 0x40004391\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_MODE_CFG1\r
+CYDEV_PM_MODE_CFG1 EQU 0x40004392\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_MODE_CSR\r
+CYDEV_PM_MODE_CSR EQU 0x40004393\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_USB_CR0\r
+CYDEV_PM_USB_CR0 EQU 0x40004394\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG0\r
+CYDEV_PM_WAKEUP_CFG0 EQU 0x40004398\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG1\r
+CYDEV_PM_WAKEUP_CFG1 EQU 0x40004399\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG2\r
+CYDEV_PM_WAKEUP_CFG2 EQU 0x4000439a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_ACT_BASE\r
+CYDEV_PM_ACT_BASE EQU 0x400043a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_ACT_SIZE\r
+CYDEV_PM_ACT_SIZE EQU 0x0000000e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_ACT_CFG0\r
+CYDEV_PM_ACT_CFG0 EQU 0x400043a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_ACT_CFG1\r
+CYDEV_PM_ACT_CFG1 EQU 0x400043a1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_ACT_CFG2\r
+CYDEV_PM_ACT_CFG2 EQU 0x400043a2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_ACT_CFG3\r
+CYDEV_PM_ACT_CFG3 EQU 0x400043a3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_ACT_CFG4\r
+CYDEV_PM_ACT_CFG4 EQU 0x400043a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_ACT_CFG5\r
+CYDEV_PM_ACT_CFG5 EQU 0x400043a5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_ACT_CFG6\r
+CYDEV_PM_ACT_CFG6 EQU 0x400043a6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_ACT_CFG7\r
+CYDEV_PM_ACT_CFG7 EQU 0x400043a7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_ACT_CFG8\r
+CYDEV_PM_ACT_CFG8 EQU 0x400043a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_ACT_CFG9\r
+CYDEV_PM_ACT_CFG9 EQU 0x400043a9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_ACT_CFG10\r
+CYDEV_PM_ACT_CFG10 EQU 0x400043aa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_ACT_CFG11\r
+CYDEV_PM_ACT_CFG11 EQU 0x400043ab\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_ACT_CFG12\r
+CYDEV_PM_ACT_CFG12 EQU 0x400043ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_ACT_CFG13\r
+CYDEV_PM_ACT_CFG13 EQU 0x400043ad\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_STBY_BASE\r
+CYDEV_PM_STBY_BASE EQU 0x400043b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_STBY_SIZE\r
+CYDEV_PM_STBY_SIZE EQU 0x0000000e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_STBY_CFG0\r
+CYDEV_PM_STBY_CFG0 EQU 0x400043b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_STBY_CFG1\r
+CYDEV_PM_STBY_CFG1 EQU 0x400043b1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_STBY_CFG2\r
+CYDEV_PM_STBY_CFG2 EQU 0x400043b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_STBY_CFG3\r
+CYDEV_PM_STBY_CFG3 EQU 0x400043b3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_STBY_CFG4\r
+CYDEV_PM_STBY_CFG4 EQU 0x400043b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_STBY_CFG5\r
+CYDEV_PM_STBY_CFG5 EQU 0x400043b5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_STBY_CFG6\r
+CYDEV_PM_STBY_CFG6 EQU 0x400043b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_STBY_CFG7\r
+CYDEV_PM_STBY_CFG7 EQU 0x400043b7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_STBY_CFG8\r
+CYDEV_PM_STBY_CFG8 EQU 0x400043b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_STBY_CFG9\r
+CYDEV_PM_STBY_CFG9 EQU 0x400043b9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_STBY_CFG10\r
+CYDEV_PM_STBY_CFG10 EQU 0x400043ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_STBY_CFG11\r
+CYDEV_PM_STBY_CFG11 EQU 0x400043bb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_STBY_CFG12\r
+CYDEV_PM_STBY_CFG12 EQU 0x400043bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_STBY_CFG13\r
+CYDEV_PM_STBY_CFG13 EQU 0x400043bd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_AVAIL_BASE\r
+CYDEV_PM_AVAIL_BASE EQU 0x400043c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_AVAIL_SIZE\r
+CYDEV_PM_AVAIL_SIZE EQU 0x00000017\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_AVAIL_CR0\r
+CYDEV_PM_AVAIL_CR0 EQU 0x400043c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_AVAIL_CR1\r
+CYDEV_PM_AVAIL_CR1 EQU 0x400043c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_AVAIL_CR2\r
+CYDEV_PM_AVAIL_CR2 EQU 0x400043c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_AVAIL_CR3\r
+CYDEV_PM_AVAIL_CR3 EQU 0x400043c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_AVAIL_CR4\r
+CYDEV_PM_AVAIL_CR4 EQU 0x400043c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_AVAIL_CR5\r
+CYDEV_PM_AVAIL_CR5 EQU 0x400043c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_AVAIL_CR6\r
+CYDEV_PM_AVAIL_CR6 EQU 0x400043c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_AVAIL_SR0\r
+CYDEV_PM_AVAIL_SR0 EQU 0x400043d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_AVAIL_SR1\r
+CYDEV_PM_AVAIL_SR1 EQU 0x400043d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_AVAIL_SR2\r
+CYDEV_PM_AVAIL_SR2 EQU 0x400043d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_AVAIL_SR3\r
+CYDEV_PM_AVAIL_SR3 EQU 0x400043d3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_AVAIL_SR4\r
+CYDEV_PM_AVAIL_SR4 EQU 0x400043d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_AVAIL_SR5\r
+CYDEV_PM_AVAIL_SR5 EQU 0x400043d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_AVAIL_SR6\r
+CYDEV_PM_AVAIL_SR6 EQU 0x400043d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_BASE\r
+CYDEV_PICU_BASE EQU 0x40004500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SIZE\r
+CYDEV_PICU_SIZE EQU 0x000000b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_BASE\r
+CYDEV_PICU_INTTYPE_BASE EQU 0x40004500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_SIZE\r
+CYDEV_PICU_INTTYPE_SIZE EQU 0x00000080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_BASE\r
+CYDEV_PICU_INTTYPE_PICU0_BASE EQU 0x40004500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_SIZE\r
+CYDEV_PICU_INTTYPE_PICU0_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE0\r
+CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 EQU 0x40004500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE1\r
+CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 EQU 0x40004501\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE2\r
+CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 EQU 0x40004502\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE3\r
+CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 EQU 0x40004503\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE4\r
+CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 EQU 0x40004504\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE5\r
+CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 EQU 0x40004505\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE6\r
+CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 EQU 0x40004506\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE7\r
+CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 EQU 0x40004507\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_BASE\r
+CYDEV_PICU_INTTYPE_PICU1_BASE EQU 0x40004508\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_SIZE\r
+CYDEV_PICU_INTTYPE_PICU1_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE0\r
+CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 EQU 0x40004508\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE1\r
+CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 EQU 0x40004509\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE2\r
+CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 EQU 0x4000450a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE3\r
+CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 EQU 0x4000450b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE4\r
+CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 EQU 0x4000450c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE5\r
+CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 EQU 0x4000450d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE6\r
+CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 EQU 0x4000450e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE7\r
+CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 EQU 0x4000450f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_BASE\r
+CYDEV_PICU_INTTYPE_PICU2_BASE EQU 0x40004510\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_SIZE\r
+CYDEV_PICU_INTTYPE_PICU2_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE0\r
+CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 EQU 0x40004510\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE1\r
+CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 EQU 0x40004511\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE2\r
+CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 EQU 0x40004512\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE3\r
+CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 EQU 0x40004513\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE4\r
+CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 EQU 0x40004514\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE5\r
+CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 EQU 0x40004515\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE6\r
+CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 EQU 0x40004516\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE7\r
+CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 EQU 0x40004517\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_BASE\r
+CYDEV_PICU_INTTYPE_PICU3_BASE EQU 0x40004518\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_SIZE\r
+CYDEV_PICU_INTTYPE_PICU3_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE0\r
+CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 EQU 0x40004518\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE1\r
+CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 EQU 0x40004519\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE2\r
+CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 EQU 0x4000451a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE3\r
+CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 EQU 0x4000451b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE4\r
+CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 EQU 0x4000451c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE5\r
+CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 EQU 0x4000451d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE6\r
+CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 EQU 0x4000451e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE7\r
+CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 EQU 0x4000451f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_BASE\r
+CYDEV_PICU_INTTYPE_PICU4_BASE EQU 0x40004520\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_SIZE\r
+CYDEV_PICU_INTTYPE_PICU4_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE0\r
+CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 EQU 0x40004520\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE1\r
+CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 EQU 0x40004521\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE2\r
+CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 EQU 0x40004522\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE3\r
+CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 EQU 0x40004523\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE4\r
+CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 EQU 0x40004524\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE5\r
+CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 EQU 0x40004525\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE6\r
+CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 EQU 0x40004526\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE7\r
+CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 EQU 0x40004527\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_BASE\r
+CYDEV_PICU_INTTYPE_PICU5_BASE EQU 0x40004528\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_SIZE\r
+CYDEV_PICU_INTTYPE_PICU5_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE0\r
+CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 EQU 0x40004528\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE1\r
+CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 EQU 0x40004529\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE2\r
+CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 EQU 0x4000452a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE3\r
+CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 EQU 0x4000452b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE4\r
+CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 EQU 0x4000452c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE5\r
+CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 EQU 0x4000452d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE6\r
+CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 EQU 0x4000452e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE7\r
+CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 EQU 0x4000452f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_BASE\r
+CYDEV_PICU_INTTYPE_PICU6_BASE EQU 0x40004530\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_SIZE\r
+CYDEV_PICU_INTTYPE_PICU6_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE0\r
+CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 EQU 0x40004530\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE1\r
+CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 EQU 0x40004531\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE2\r
+CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 EQU 0x40004532\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE3\r
+CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 EQU 0x40004533\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE4\r
+CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 EQU 0x40004534\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE5\r
+CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 EQU 0x40004535\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE6\r
+CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 EQU 0x40004536\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE7\r
+CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 EQU 0x40004537\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_BASE\r
+CYDEV_PICU_INTTYPE_PICU12_BASE EQU 0x40004560\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_SIZE\r
+CYDEV_PICU_INTTYPE_PICU12_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE0\r
+CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 EQU 0x40004560\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE1\r
+CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 EQU 0x40004561\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE2\r
+CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 EQU 0x40004562\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE3\r
+CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 EQU 0x40004563\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE4\r
+CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 EQU 0x40004564\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE5\r
+CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 EQU 0x40004565\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE6\r
+CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 EQU 0x40004566\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE7\r
+CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 EQU 0x40004567\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_BASE\r
+CYDEV_PICU_INTTYPE_PICU15_BASE EQU 0x40004578\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_SIZE\r
+CYDEV_PICU_INTTYPE_PICU15_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE0\r
+CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 EQU 0x40004578\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE1\r
+CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 EQU 0x40004579\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE2\r
+CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 EQU 0x4000457a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE3\r
+CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 EQU 0x4000457b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE4\r
+CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 EQU 0x4000457c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE5\r
+CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 EQU 0x4000457d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE6\r
+CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 EQU 0x4000457e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE7\r
+CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 EQU 0x4000457f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_BASE\r
+CYDEV_PICU_STAT_BASE EQU 0x40004580\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_SIZE\r
+CYDEV_PICU_STAT_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_BASE\r
+CYDEV_PICU_STAT_PICU0_BASE EQU 0x40004580\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_SIZE\r
+CYDEV_PICU_STAT_PICU0_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_INTSTAT\r
+CYDEV_PICU_STAT_PICU0_INTSTAT EQU 0x40004580\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_BASE\r
+CYDEV_PICU_STAT_PICU1_BASE EQU 0x40004581\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_SIZE\r
+CYDEV_PICU_STAT_PICU1_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_INTSTAT\r
+CYDEV_PICU_STAT_PICU1_INTSTAT EQU 0x40004581\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_BASE\r
+CYDEV_PICU_STAT_PICU2_BASE EQU 0x40004582\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_SIZE\r
+CYDEV_PICU_STAT_PICU2_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_INTSTAT\r
+CYDEV_PICU_STAT_PICU2_INTSTAT EQU 0x40004582\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_BASE\r
+CYDEV_PICU_STAT_PICU3_BASE EQU 0x40004583\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_SIZE\r
+CYDEV_PICU_STAT_PICU3_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_INTSTAT\r
+CYDEV_PICU_STAT_PICU3_INTSTAT EQU 0x40004583\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_BASE\r
+CYDEV_PICU_STAT_PICU4_BASE EQU 0x40004584\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_SIZE\r
+CYDEV_PICU_STAT_PICU4_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_INTSTAT\r
+CYDEV_PICU_STAT_PICU4_INTSTAT EQU 0x40004584\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_BASE\r
+CYDEV_PICU_STAT_PICU5_BASE EQU 0x40004585\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_SIZE\r
+CYDEV_PICU_STAT_PICU5_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_INTSTAT\r
+CYDEV_PICU_STAT_PICU5_INTSTAT EQU 0x40004585\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_BASE\r
+CYDEV_PICU_STAT_PICU6_BASE EQU 0x40004586\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_SIZE\r
+CYDEV_PICU_STAT_PICU6_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_INTSTAT\r
+CYDEV_PICU_STAT_PICU6_INTSTAT EQU 0x40004586\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_BASE\r
+CYDEV_PICU_STAT_PICU12_BASE EQU 0x4000458c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_SIZE\r
+CYDEV_PICU_STAT_PICU12_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_INTSTAT\r
+CYDEV_PICU_STAT_PICU12_INTSTAT EQU 0x4000458c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_BASE\r
+CYDEV_PICU_STAT_PICU15_BASE EQU 0x4000458f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_SIZE\r
+CYDEV_PICU_STAT_PICU15_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_INTSTAT\r
+CYDEV_PICU_STAT_PICU15_INTSTAT EQU 0x4000458f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_BASE\r
+CYDEV_PICU_SNAP_BASE EQU 0x40004590\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_SIZE\r
+CYDEV_PICU_SNAP_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_BASE\r
+CYDEV_PICU_SNAP_PICU0_BASE EQU 0x40004590\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SIZE\r
+CYDEV_PICU_SNAP_PICU0_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SNAP\r
+CYDEV_PICU_SNAP_PICU0_SNAP EQU 0x40004590\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_BASE\r
+CYDEV_PICU_SNAP_PICU1_BASE EQU 0x40004591\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SIZE\r
+CYDEV_PICU_SNAP_PICU1_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SNAP\r
+CYDEV_PICU_SNAP_PICU1_SNAP EQU 0x40004591\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_BASE\r
+CYDEV_PICU_SNAP_PICU2_BASE EQU 0x40004592\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SIZE\r
+CYDEV_PICU_SNAP_PICU2_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SNAP\r
+CYDEV_PICU_SNAP_PICU2_SNAP EQU 0x40004592\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_BASE\r
+CYDEV_PICU_SNAP_PICU3_BASE EQU 0x40004593\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SIZE\r
+CYDEV_PICU_SNAP_PICU3_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SNAP\r
+CYDEV_PICU_SNAP_PICU3_SNAP EQU 0x40004593\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_BASE\r
+CYDEV_PICU_SNAP_PICU4_BASE EQU 0x40004594\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SIZE\r
+CYDEV_PICU_SNAP_PICU4_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SNAP\r
+CYDEV_PICU_SNAP_PICU4_SNAP EQU 0x40004594\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_BASE\r
+CYDEV_PICU_SNAP_PICU5_BASE EQU 0x40004595\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SIZE\r
+CYDEV_PICU_SNAP_PICU5_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SNAP\r
+CYDEV_PICU_SNAP_PICU5_SNAP EQU 0x40004595\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_BASE\r
+CYDEV_PICU_SNAP_PICU6_BASE EQU 0x40004596\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SIZE\r
+CYDEV_PICU_SNAP_PICU6_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SNAP\r
+CYDEV_PICU_SNAP_PICU6_SNAP EQU 0x40004596\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_BASE\r
+CYDEV_PICU_SNAP_PICU12_BASE EQU 0x4000459c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SIZE\r
+CYDEV_PICU_SNAP_PICU12_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SNAP\r
+CYDEV_PICU_SNAP_PICU12_SNAP EQU 0x4000459c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_BASE\r
+CYDEV_PICU_SNAP_PICU_15_BASE EQU 0x4000459f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SIZE\r
+CYDEV_PICU_SNAP_PICU_15_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SNAP_15\r
+CYDEV_PICU_SNAP_PICU_15_SNAP_15 EQU 0x4000459f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_BASE\r
+CYDEV_PICU_DISABLE_COR_BASE EQU 0x400045a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_SIZE\r
+CYDEV_PICU_DISABLE_COR_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_BASE\r
+CYDEV_PICU_DISABLE_COR_PICU0_BASE EQU 0x400045a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_SIZE\r
+CYDEV_PICU_DISABLE_COR_PICU0_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR\r
+CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR EQU 0x400045a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_BASE\r
+CYDEV_PICU_DISABLE_COR_PICU1_BASE EQU 0x400045a1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_SIZE\r
+CYDEV_PICU_DISABLE_COR_PICU1_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR\r
+CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR EQU 0x400045a1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_BASE\r
+CYDEV_PICU_DISABLE_COR_PICU2_BASE EQU 0x400045a2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_SIZE\r
+CYDEV_PICU_DISABLE_COR_PICU2_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR\r
+CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR EQU 0x400045a2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_BASE\r
+CYDEV_PICU_DISABLE_COR_PICU3_BASE EQU 0x400045a3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_SIZE\r
+CYDEV_PICU_DISABLE_COR_PICU3_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR\r
+CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR EQU 0x400045a3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_BASE\r
+CYDEV_PICU_DISABLE_COR_PICU4_BASE EQU 0x400045a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_SIZE\r
+CYDEV_PICU_DISABLE_COR_PICU4_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR\r
+CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR EQU 0x400045a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_BASE\r
+CYDEV_PICU_DISABLE_COR_PICU5_BASE EQU 0x400045a5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_SIZE\r
+CYDEV_PICU_DISABLE_COR_PICU5_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR\r
+CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR EQU 0x400045a5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_BASE\r
+CYDEV_PICU_DISABLE_COR_PICU6_BASE EQU 0x400045a6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_SIZE\r
+CYDEV_PICU_DISABLE_COR_PICU6_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR\r
+CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR EQU 0x400045a6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_BASE\r
+CYDEV_PICU_DISABLE_COR_PICU12_BASE EQU 0x400045ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_SIZE\r
+CYDEV_PICU_DISABLE_COR_PICU12_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR\r
+CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR EQU 0x400045ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_BASE\r
+CYDEV_PICU_DISABLE_COR_PICU15_BASE EQU 0x400045af\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_SIZE\r
+CYDEV_PICU_DISABLE_COR_PICU15_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR\r
+CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR EQU 0x400045af\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_BASE\r
+CYDEV_MFGCFG_BASE EQU 0x40004600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_SIZE\r
+CYDEV_MFGCFG_SIZE EQU 0x000000ed\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_BASE\r
+CYDEV_MFGCFG_ANAIF_BASE EQU 0x40004600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SIZE\r
+CYDEV_MFGCFG_ANAIF_SIZE EQU 0x00000038\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_BASE\r
+CYDEV_MFGCFG_ANAIF_DAC0_BASE EQU 0x40004608\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_SIZE\r
+CYDEV_MFGCFG_ANAIF_DAC0_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_TR\r
+CYDEV_MFGCFG_ANAIF_DAC0_TR EQU 0x40004608\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_BASE\r
+CYDEV_MFGCFG_ANAIF_DAC1_BASE EQU 0x40004609\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_SIZE\r
+CYDEV_MFGCFG_ANAIF_DAC1_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_TR\r
+CYDEV_MFGCFG_ANAIF_DAC1_TR EQU 0x40004609\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_BASE\r
+CYDEV_MFGCFG_ANAIF_DAC2_BASE EQU 0x4000460a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_SIZE\r
+CYDEV_MFGCFG_ANAIF_DAC2_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_TR\r
+CYDEV_MFGCFG_ANAIF_DAC2_TR EQU 0x4000460a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_BASE\r
+CYDEV_MFGCFG_ANAIF_DAC3_BASE EQU 0x4000460b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_SIZE\r
+CYDEV_MFGCFG_ANAIF_DAC3_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_TR\r
+CYDEV_MFGCFG_ANAIF_DAC3_TR EQU 0x4000460b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE\r
+CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE EQU 0x40004610\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE\r
+CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0\r
+CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 EQU 0x40004610\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE\r
+CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE EQU 0x40004611\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE\r
+CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0\r
+CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 EQU 0x40004611\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE\r
+CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE EQU 0x40004612\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE\r
+CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0\r
+CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 EQU 0x40004612\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_BASE\r
+CYDEV_MFGCFG_ANAIF_SAR0_BASE EQU 0x40004614\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_SIZE\r
+CYDEV_MFGCFG_ANAIF_SAR0_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_TR0\r
+CYDEV_MFGCFG_ANAIF_SAR0_TR0 EQU 0x40004614\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_BASE\r
+CYDEV_MFGCFG_ANAIF_SAR1_BASE EQU 0x40004616\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_SIZE\r
+CYDEV_MFGCFG_ANAIF_SAR1_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_TR0\r
+CYDEV_MFGCFG_ANAIF_SAR1_TR0 EQU 0x40004616\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_BASE\r
+CYDEV_MFGCFG_ANAIF_OPAMP0_BASE EQU 0x40004620\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE\r
+CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_TR0\r
+CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 EQU 0x40004620\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_TR1\r
+CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 EQU 0x40004621\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_BASE\r
+CYDEV_MFGCFG_ANAIF_OPAMP1_BASE EQU 0x40004622\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE\r
+CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_TR0\r
+CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 EQU 0x40004622\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_TR1\r
+CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 EQU 0x40004623\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_BASE\r
+CYDEV_MFGCFG_ANAIF_OPAMP2_BASE EQU 0x40004624\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE\r
+CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_TR0\r
+CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 EQU 0x40004624\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_TR1\r
+CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 EQU 0x40004625\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_BASE\r
+CYDEV_MFGCFG_ANAIF_OPAMP3_BASE EQU 0x40004626\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE\r
+CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_TR0\r
+CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 EQU 0x40004626\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_TR1\r
+CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 EQU 0x40004627\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_BASE\r
+CYDEV_MFGCFG_ANAIF_CMP0_BASE EQU 0x40004630\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_SIZE\r
+CYDEV_MFGCFG_ANAIF_CMP0_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_TR0\r
+CYDEV_MFGCFG_ANAIF_CMP0_TR0 EQU 0x40004630\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_TR1\r
+CYDEV_MFGCFG_ANAIF_CMP0_TR1 EQU 0x40004631\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_BASE\r
+CYDEV_MFGCFG_ANAIF_CMP1_BASE EQU 0x40004632\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_SIZE\r
+CYDEV_MFGCFG_ANAIF_CMP1_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_TR0\r
+CYDEV_MFGCFG_ANAIF_CMP1_TR0 EQU 0x40004632\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_TR1\r
+CYDEV_MFGCFG_ANAIF_CMP1_TR1 EQU 0x40004633\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_BASE\r
+CYDEV_MFGCFG_ANAIF_CMP2_BASE EQU 0x40004634\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_SIZE\r
+CYDEV_MFGCFG_ANAIF_CMP2_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_TR0\r
+CYDEV_MFGCFG_ANAIF_CMP2_TR0 EQU 0x40004634\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_TR1\r
+CYDEV_MFGCFG_ANAIF_CMP2_TR1 EQU 0x40004635\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_BASE\r
+CYDEV_MFGCFG_ANAIF_CMP3_BASE EQU 0x40004636\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_SIZE\r
+CYDEV_MFGCFG_ANAIF_CMP3_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_TR0\r
+CYDEV_MFGCFG_ANAIF_CMP3_TR0 EQU 0x40004636\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_TR1\r
+CYDEV_MFGCFG_ANAIF_CMP3_TR1 EQU 0x40004637\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BASE\r
+CYDEV_MFGCFG_PWRSYS_BASE EQU 0x40004680\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SIZE\r
+CYDEV_MFGCFG_PWRSYS_SIZE EQU 0x0000000b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_HIB_TR0\r
+CYDEV_MFGCFG_PWRSYS_HIB_TR0 EQU 0x40004680\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_HIB_TR1\r
+CYDEV_MFGCFG_PWRSYS_HIB_TR1 EQU 0x40004681\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_I2C_TR\r
+CYDEV_MFGCFG_PWRSYS_I2C_TR EQU 0x40004682\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SLP_TR\r
+CYDEV_MFGCFG_PWRSYS_SLP_TR EQU 0x40004683\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BUZZ_TR\r
+CYDEV_MFGCFG_PWRSYS_BUZZ_TR EQU 0x40004684\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR0\r
+CYDEV_MFGCFG_PWRSYS_WAKE_TR0 EQU 0x40004685\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR1\r
+CYDEV_MFGCFG_PWRSYS_WAKE_TR1 EQU 0x40004686\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BREF_TR\r
+CYDEV_MFGCFG_PWRSYS_BREF_TR EQU 0x40004687\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BG_TR\r
+CYDEV_MFGCFG_PWRSYS_BG_TR EQU 0x40004688\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR2\r
+CYDEV_MFGCFG_PWRSYS_WAKE_TR2 EQU 0x40004689\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR3\r
+CYDEV_MFGCFG_PWRSYS_WAKE_TR3 EQU 0x4000468a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ILO_BASE\r
+CYDEV_MFGCFG_ILO_BASE EQU 0x40004690\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ILO_SIZE\r
+CYDEV_MFGCFG_ILO_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ILO_TR0\r
+CYDEV_MFGCFG_ILO_TR0 EQU 0x40004690\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ILO_TR1\r
+CYDEV_MFGCFG_ILO_TR1 EQU 0x40004691\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_X32_BASE\r
+CYDEV_MFGCFG_X32_BASE EQU 0x40004698\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_X32_SIZE\r
+CYDEV_MFGCFG_X32_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_X32_TR\r
+CYDEV_MFGCFG_X32_TR EQU 0x40004698\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_IMO_BASE\r
+CYDEV_MFGCFG_IMO_BASE EQU 0x400046a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_IMO_SIZE\r
+CYDEV_MFGCFG_IMO_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR0\r
+CYDEV_MFGCFG_IMO_TR0 EQU 0x400046a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR1\r
+CYDEV_MFGCFG_IMO_TR1 EQU 0x400046a1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_IMO_GAIN\r
+CYDEV_MFGCFG_IMO_GAIN EQU 0x400046a2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_IMO_C36M\r
+CYDEV_MFGCFG_IMO_C36M EQU 0x400046a3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR2\r
+CYDEV_MFGCFG_IMO_TR2 EQU 0x400046a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_BASE\r
+CYDEV_MFGCFG_XMHZ_BASE EQU 0x400046a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_SIZE\r
+CYDEV_MFGCFG_XMHZ_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_TR\r
+CYDEV_MFGCFG_XMHZ_TR EQU 0x400046a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_DLY\r
+CYDEV_MFGCFG_DLY EQU 0x400046c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_BASE\r
+CYDEV_MFGCFG_MLOGIC_BASE EQU 0x400046e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SIZE\r
+CYDEV_MFGCFG_MLOGIC_SIZE EQU 0x0000000d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_DMPSTR\r
+CYDEV_MFGCFG_MLOGIC_DMPSTR EQU 0x400046e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_BASE\r
+CYDEV_MFGCFG_MLOGIC_SEG_BASE EQU 0x400046e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_SIZE\r
+CYDEV_MFGCFG_MLOGIC_SEG_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_CR\r
+CYDEV_MFGCFG_MLOGIC_SEG_CR EQU 0x400046e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_CFG0\r
+CYDEV_MFGCFG_MLOGIC_SEG_CFG0 EQU 0x400046e5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_DEBUG\r
+CYDEV_MFGCFG_MLOGIC_DEBUG EQU 0x400046e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE\r
+CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE EQU 0x400046ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE\r
+CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR\r
+CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR EQU 0x400046ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_REV_ID\r
+CYDEV_MFGCFG_MLOGIC_REV_ID EQU 0x400046ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_RESET_BASE\r
+CYDEV_RESET_BASE EQU 0x400046f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_RESET_SIZE\r
+CYDEV_RESET_SIZE EQU 0x0000000f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_RESET_IPOR_CR0\r
+CYDEV_RESET_IPOR_CR0 EQU 0x400046f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_RESET_IPOR_CR1\r
+CYDEV_RESET_IPOR_CR1 EQU 0x400046f1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_RESET_IPOR_CR2\r
+CYDEV_RESET_IPOR_CR2 EQU 0x400046f2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_RESET_IPOR_CR3\r
+CYDEV_RESET_IPOR_CR3 EQU 0x400046f3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_RESET_CR0\r
+CYDEV_RESET_CR0 EQU 0x400046f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_RESET_CR1\r
+CYDEV_RESET_CR1 EQU 0x400046f5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_RESET_CR2\r
+CYDEV_RESET_CR2 EQU 0x400046f6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_RESET_CR3\r
+CYDEV_RESET_CR3 EQU 0x400046f7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_RESET_CR4\r
+CYDEV_RESET_CR4 EQU 0x400046f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_RESET_CR5\r
+CYDEV_RESET_CR5 EQU 0x400046f9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_RESET_SR0\r
+CYDEV_RESET_SR0 EQU 0x400046fa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_RESET_SR1\r
+CYDEV_RESET_SR1 EQU 0x400046fb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_RESET_SR2\r
+CYDEV_RESET_SR2 EQU 0x400046fc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_RESET_SR3\r
+CYDEV_RESET_SR3 EQU 0x400046fd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_RESET_TR\r
+CYDEV_RESET_TR EQU 0x400046fe\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SPC_BASE\r
+CYDEV_SPC_BASE EQU 0x40004700\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SPC_SIZE\r
+CYDEV_SPC_SIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SPC_FM_EE_CR\r
+CYDEV_SPC_FM_EE_CR EQU 0x40004700\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SPC_FM_EE_WAKE_CNT\r
+CYDEV_SPC_FM_EE_WAKE_CNT EQU 0x40004701\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SPC_EE_SCR\r
+CYDEV_SPC_EE_SCR EQU 0x40004702\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SPC_EE_ERR\r
+CYDEV_SPC_EE_ERR EQU 0x40004703\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SPC_CPU_DATA\r
+CYDEV_SPC_CPU_DATA EQU 0x40004720\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SPC_DMA_DATA\r
+CYDEV_SPC_DMA_DATA EQU 0x40004721\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SPC_SR\r
+CYDEV_SPC_SR EQU 0x40004722\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SPC_CR\r
+CYDEV_SPC_CR EQU 0x40004723\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_BASE\r
+CYDEV_SPC_DMM_MAP_BASE EQU 0x40004780\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SIZE\r
+CYDEV_SPC_DMM_MAP_SIZE EQU 0x00000080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SRAM_MBASE\r
+CYDEV_SPC_DMM_MAP_SRAM_MBASE EQU 0x40004780\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SRAM_MSIZE\r
+CYDEV_SPC_DMM_MAP_SRAM_MSIZE EQU 0x00000080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CACHE_BASE\r
+CYDEV_CACHE_BASE EQU 0x40004800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CACHE_SIZE\r
+CYDEV_CACHE_SIZE EQU 0x0000009c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CACHE_CC_CTL\r
+CYDEV_CACHE_CC_CTL EQU 0x40004800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CACHE_ECC_CORR\r
+CYDEV_CACHE_ECC_CORR EQU 0x40004880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CACHE_ECC_ERR\r
+CYDEV_CACHE_ECC_ERR EQU 0x40004888\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CACHE_FLASH_ERR\r
+CYDEV_CACHE_FLASH_ERR EQU 0x40004890\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CACHE_HITMISS\r
+CYDEV_CACHE_HITMISS EQU 0x40004898\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_I2C_BASE\r
+CYDEV_I2C_BASE EQU 0x40004900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_I2C_SIZE\r
+CYDEV_I2C_SIZE EQU 0x000000e1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_I2C_XCFG\r
+CYDEV_I2C_XCFG EQU 0x400049c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_I2C_ADR\r
+CYDEV_I2C_ADR EQU 0x400049ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_I2C_CFG\r
+CYDEV_I2C_CFG EQU 0x400049d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_I2C_CSR\r
+CYDEV_I2C_CSR EQU 0x400049d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_I2C_D\r
+CYDEV_I2C_D EQU 0x400049d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_I2C_MCSR\r
+CYDEV_I2C_MCSR EQU 0x400049d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_I2C_CLK_DIV1\r
+CYDEV_I2C_CLK_DIV1 EQU 0x400049db\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_I2C_CLK_DIV2\r
+CYDEV_I2C_CLK_DIV2 EQU 0x400049dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_I2C_TMOUT_CSR\r
+CYDEV_I2C_TMOUT_CSR EQU 0x400049dd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_I2C_TMOUT_SR\r
+CYDEV_I2C_TMOUT_SR EQU 0x400049de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_I2C_TMOUT_CFG0\r
+CYDEV_I2C_TMOUT_CFG0 EQU 0x400049df\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_I2C_TMOUT_CFG1\r
+CYDEV_I2C_TMOUT_CFG1 EQU 0x400049e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_BASE\r
+CYDEV_DEC_BASE EQU 0x40004e00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_SIZE\r
+CYDEV_DEC_SIZE EQU 0x00000015\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_CR\r
+CYDEV_DEC_CR EQU 0x40004e00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_SR\r
+CYDEV_DEC_SR EQU 0x40004e01\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_SHIFT1\r
+CYDEV_DEC_SHIFT1 EQU 0x40004e02\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_SHIFT2\r
+CYDEV_DEC_SHIFT2 EQU 0x40004e03\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_DR2\r
+CYDEV_DEC_DR2 EQU 0x40004e04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_DR2H\r
+CYDEV_DEC_DR2H EQU 0x40004e05\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_DR1\r
+CYDEV_DEC_DR1 EQU 0x40004e06\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_OCOR\r
+CYDEV_DEC_OCOR EQU 0x40004e08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_OCORM\r
+CYDEV_DEC_OCORM EQU 0x40004e09\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_OCORH\r
+CYDEV_DEC_OCORH EQU 0x40004e0a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_GCOR\r
+CYDEV_DEC_GCOR EQU 0x40004e0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_GCORH\r
+CYDEV_DEC_GCORH EQU 0x40004e0d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_GVAL\r
+CYDEV_DEC_GVAL EQU 0x40004e0e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_OUTSAMP\r
+CYDEV_DEC_OUTSAMP EQU 0x40004e10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_OUTSAMPM\r
+CYDEV_DEC_OUTSAMPM EQU 0x40004e11\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_OUTSAMPH\r
+CYDEV_DEC_OUTSAMPH EQU 0x40004e12\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_OUTSAMPS\r
+CYDEV_DEC_OUTSAMPS EQU 0x40004e13\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_COHER\r
+CYDEV_DEC_COHER EQU 0x40004e14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR0_BASE\r
+CYDEV_TMR0_BASE EQU 0x40004f00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR0_SIZE\r
+CYDEV_TMR0_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR0_CFG0\r
+CYDEV_TMR0_CFG0 EQU 0x40004f00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR0_CFG1\r
+CYDEV_TMR0_CFG1 EQU 0x40004f01\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR0_CFG2\r
+CYDEV_TMR0_CFG2 EQU 0x40004f02\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR0_SR0\r
+CYDEV_TMR0_SR0 EQU 0x40004f03\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR0_PER0\r
+CYDEV_TMR0_PER0 EQU 0x40004f04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR0_PER1\r
+CYDEV_TMR0_PER1 EQU 0x40004f05\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR0_CNT_CMP0\r
+CYDEV_TMR0_CNT_CMP0 EQU 0x40004f06\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR0_CNT_CMP1\r
+CYDEV_TMR0_CNT_CMP1 EQU 0x40004f07\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR0_CAP0\r
+CYDEV_TMR0_CAP0 EQU 0x40004f08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR0_CAP1\r
+CYDEV_TMR0_CAP1 EQU 0x40004f09\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR0_RT0\r
+CYDEV_TMR0_RT0 EQU 0x40004f0a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR0_RT1\r
+CYDEV_TMR0_RT1 EQU 0x40004f0b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR1_BASE\r
+CYDEV_TMR1_BASE EQU 0x40004f0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR1_SIZE\r
+CYDEV_TMR1_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR1_CFG0\r
+CYDEV_TMR1_CFG0 EQU 0x40004f0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR1_CFG1\r
+CYDEV_TMR1_CFG1 EQU 0x40004f0d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR1_CFG2\r
+CYDEV_TMR1_CFG2 EQU 0x40004f0e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR1_SR0\r
+CYDEV_TMR1_SR0 EQU 0x40004f0f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR1_PER0\r
+CYDEV_TMR1_PER0 EQU 0x40004f10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR1_PER1\r
+CYDEV_TMR1_PER1 EQU 0x40004f11\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR1_CNT_CMP0\r
+CYDEV_TMR1_CNT_CMP0 EQU 0x40004f12\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR1_CNT_CMP1\r
+CYDEV_TMR1_CNT_CMP1 EQU 0x40004f13\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR1_CAP0\r
+CYDEV_TMR1_CAP0 EQU 0x40004f14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR1_CAP1\r
+CYDEV_TMR1_CAP1 EQU 0x40004f15\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR1_RT0\r
+CYDEV_TMR1_RT0 EQU 0x40004f16\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR1_RT1\r
+CYDEV_TMR1_RT1 EQU 0x40004f17\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR2_BASE\r
+CYDEV_TMR2_BASE EQU 0x40004f18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR2_SIZE\r
+CYDEV_TMR2_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR2_CFG0\r
+CYDEV_TMR2_CFG0 EQU 0x40004f18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR2_CFG1\r
+CYDEV_TMR2_CFG1 EQU 0x40004f19\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR2_CFG2\r
+CYDEV_TMR2_CFG2 EQU 0x40004f1a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR2_SR0\r
+CYDEV_TMR2_SR0 EQU 0x40004f1b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR2_PER0\r
+CYDEV_TMR2_PER0 EQU 0x40004f1c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR2_PER1\r
+CYDEV_TMR2_PER1 EQU 0x40004f1d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR2_CNT_CMP0\r
+CYDEV_TMR2_CNT_CMP0 EQU 0x40004f1e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR2_CNT_CMP1\r
+CYDEV_TMR2_CNT_CMP1 EQU 0x40004f1f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR2_CAP0\r
+CYDEV_TMR2_CAP0 EQU 0x40004f20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR2_CAP1\r
+CYDEV_TMR2_CAP1 EQU 0x40004f21\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR2_RT0\r
+CYDEV_TMR2_RT0 EQU 0x40004f22\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR2_RT1\r
+CYDEV_TMR2_RT1 EQU 0x40004f23\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR3_BASE\r
+CYDEV_TMR3_BASE EQU 0x40004f24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR3_SIZE\r
+CYDEV_TMR3_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR3_CFG0\r
+CYDEV_TMR3_CFG0 EQU 0x40004f24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR3_CFG1\r
+CYDEV_TMR3_CFG1 EQU 0x40004f25\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR3_CFG2\r
+CYDEV_TMR3_CFG2 EQU 0x40004f26\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR3_SR0\r
+CYDEV_TMR3_SR0 EQU 0x40004f27\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR3_PER0\r
+CYDEV_TMR3_PER0 EQU 0x40004f28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR3_PER1\r
+CYDEV_TMR3_PER1 EQU 0x40004f29\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR3_CNT_CMP0\r
+CYDEV_TMR3_CNT_CMP0 EQU 0x40004f2a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR3_CNT_CMP1\r
+CYDEV_TMR3_CNT_CMP1 EQU 0x40004f2b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR3_CAP0\r
+CYDEV_TMR3_CAP0 EQU 0x40004f2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR3_CAP1\r
+CYDEV_TMR3_CAP1 EQU 0x40004f2d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR3_RT0\r
+CYDEV_TMR3_RT0 EQU 0x40004f2e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR3_RT1\r
+CYDEV_TMR3_RT1 EQU 0x40004f2f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_BASE\r
+CYDEV_IO_BASE EQU 0x40005000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_SIZE\r
+CYDEV_IO_SIZE EQU 0x00000200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_BASE\r
+CYDEV_IO_PC_BASE EQU 0x40005000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_SIZE\r
+CYDEV_IO_PC_SIZE EQU 0x00000080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT0_BASE\r
+CYDEV_IO_PC_PRT0_BASE EQU 0x40005000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT0_SIZE\r
+CYDEV_IO_PC_PRT0_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC0\r
+CYDEV_IO_PC_PRT0_PC0 EQU 0x40005000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC1\r
+CYDEV_IO_PC_PRT0_PC1 EQU 0x40005001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC2\r
+CYDEV_IO_PC_PRT0_PC2 EQU 0x40005002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC3\r
+CYDEV_IO_PC_PRT0_PC3 EQU 0x40005003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC4\r
+CYDEV_IO_PC_PRT0_PC4 EQU 0x40005004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC5\r
+CYDEV_IO_PC_PRT0_PC5 EQU 0x40005005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC6\r
+CYDEV_IO_PC_PRT0_PC6 EQU 0x40005006\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC7\r
+CYDEV_IO_PC_PRT0_PC7 EQU 0x40005007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT1_BASE\r
+CYDEV_IO_PC_PRT1_BASE EQU 0x40005008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT1_SIZE\r
+CYDEV_IO_PC_PRT1_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC0\r
+CYDEV_IO_PC_PRT1_PC0 EQU 0x40005008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC1\r
+CYDEV_IO_PC_PRT1_PC1 EQU 0x40005009\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC2\r
+CYDEV_IO_PC_PRT1_PC2 EQU 0x4000500a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC3\r
+CYDEV_IO_PC_PRT1_PC3 EQU 0x4000500b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC4\r
+CYDEV_IO_PC_PRT1_PC4 EQU 0x4000500c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC5\r
+CYDEV_IO_PC_PRT1_PC5 EQU 0x4000500d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC6\r
+CYDEV_IO_PC_PRT1_PC6 EQU 0x4000500e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC7\r
+CYDEV_IO_PC_PRT1_PC7 EQU 0x4000500f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT2_BASE\r
+CYDEV_IO_PC_PRT2_BASE EQU 0x40005010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT2_SIZE\r
+CYDEV_IO_PC_PRT2_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC0\r
+CYDEV_IO_PC_PRT2_PC0 EQU 0x40005010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC1\r
+CYDEV_IO_PC_PRT2_PC1 EQU 0x40005011\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC2\r
+CYDEV_IO_PC_PRT2_PC2 EQU 0x40005012\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC3\r
+CYDEV_IO_PC_PRT2_PC3 EQU 0x40005013\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC4\r
+CYDEV_IO_PC_PRT2_PC4 EQU 0x40005014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC5\r
+CYDEV_IO_PC_PRT2_PC5 EQU 0x40005015\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC6\r
+CYDEV_IO_PC_PRT2_PC6 EQU 0x40005016\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC7\r
+CYDEV_IO_PC_PRT2_PC7 EQU 0x40005017\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT3_BASE\r
+CYDEV_IO_PC_PRT3_BASE EQU 0x40005018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT3_SIZE\r
+CYDEV_IO_PC_PRT3_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC0\r
+CYDEV_IO_PC_PRT3_PC0 EQU 0x40005018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC1\r
+CYDEV_IO_PC_PRT3_PC1 EQU 0x40005019\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC2\r
+CYDEV_IO_PC_PRT3_PC2 EQU 0x4000501a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC3\r
+CYDEV_IO_PC_PRT3_PC3 EQU 0x4000501b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC4\r
+CYDEV_IO_PC_PRT3_PC4 EQU 0x4000501c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC5\r
+CYDEV_IO_PC_PRT3_PC5 EQU 0x4000501d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC6\r
+CYDEV_IO_PC_PRT3_PC6 EQU 0x4000501e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC7\r
+CYDEV_IO_PC_PRT3_PC7 EQU 0x4000501f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT4_BASE\r
+CYDEV_IO_PC_PRT4_BASE EQU 0x40005020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT4_SIZE\r
+CYDEV_IO_PC_PRT4_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC0\r
+CYDEV_IO_PC_PRT4_PC0 EQU 0x40005020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC1\r
+CYDEV_IO_PC_PRT4_PC1 EQU 0x40005021\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC2\r
+CYDEV_IO_PC_PRT4_PC2 EQU 0x40005022\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC3\r
+CYDEV_IO_PC_PRT4_PC3 EQU 0x40005023\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC4\r
+CYDEV_IO_PC_PRT4_PC4 EQU 0x40005024\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC5\r
+CYDEV_IO_PC_PRT4_PC5 EQU 0x40005025\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC6\r
+CYDEV_IO_PC_PRT4_PC6 EQU 0x40005026\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC7\r
+CYDEV_IO_PC_PRT4_PC7 EQU 0x40005027\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT5_BASE\r
+CYDEV_IO_PC_PRT5_BASE EQU 0x40005028\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT5_SIZE\r
+CYDEV_IO_PC_PRT5_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC0\r
+CYDEV_IO_PC_PRT5_PC0 EQU 0x40005028\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC1\r
+CYDEV_IO_PC_PRT5_PC1 EQU 0x40005029\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC2\r
+CYDEV_IO_PC_PRT5_PC2 EQU 0x4000502a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC3\r
+CYDEV_IO_PC_PRT5_PC3 EQU 0x4000502b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC4\r
+CYDEV_IO_PC_PRT5_PC4 EQU 0x4000502c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC5\r
+CYDEV_IO_PC_PRT5_PC5 EQU 0x4000502d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC6\r
+CYDEV_IO_PC_PRT5_PC6 EQU 0x4000502e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC7\r
+CYDEV_IO_PC_PRT5_PC7 EQU 0x4000502f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT6_BASE\r
+CYDEV_IO_PC_PRT6_BASE EQU 0x40005030\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT6_SIZE\r
+CYDEV_IO_PC_PRT6_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC0\r
+CYDEV_IO_PC_PRT6_PC0 EQU 0x40005030\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC1\r
+CYDEV_IO_PC_PRT6_PC1 EQU 0x40005031\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC2\r
+CYDEV_IO_PC_PRT6_PC2 EQU 0x40005032\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC3\r
+CYDEV_IO_PC_PRT6_PC3 EQU 0x40005033\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC4\r
+CYDEV_IO_PC_PRT6_PC4 EQU 0x40005034\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC5\r
+CYDEV_IO_PC_PRT6_PC5 EQU 0x40005035\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC6\r
+CYDEV_IO_PC_PRT6_PC6 EQU 0x40005036\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC7\r
+CYDEV_IO_PC_PRT6_PC7 EQU 0x40005037\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT12_BASE\r
+CYDEV_IO_PC_PRT12_BASE EQU 0x40005060\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT12_SIZE\r
+CYDEV_IO_PC_PRT12_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC0\r
+CYDEV_IO_PC_PRT12_PC0 EQU 0x40005060\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC1\r
+CYDEV_IO_PC_PRT12_PC1 EQU 0x40005061\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC2\r
+CYDEV_IO_PC_PRT12_PC2 EQU 0x40005062\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC3\r
+CYDEV_IO_PC_PRT12_PC3 EQU 0x40005063\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC4\r
+CYDEV_IO_PC_PRT12_PC4 EQU 0x40005064\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC5\r
+CYDEV_IO_PC_PRT12_PC5 EQU 0x40005065\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC6\r
+CYDEV_IO_PC_PRT12_PC6 EQU 0x40005066\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC7\r
+CYDEV_IO_PC_PRT12_PC7 EQU 0x40005067\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT15_BASE\r
+CYDEV_IO_PC_PRT15_BASE EQU 0x40005078\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT15_SIZE\r
+CYDEV_IO_PC_PRT15_SIZE EQU 0x00000006\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC0\r
+CYDEV_IO_PC_PRT15_PC0 EQU 0x40005078\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC1\r
+CYDEV_IO_PC_PRT15_PC1 EQU 0x40005079\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC2\r
+CYDEV_IO_PC_PRT15_PC2 EQU 0x4000507a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC3\r
+CYDEV_IO_PC_PRT15_PC3 EQU 0x4000507b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC4\r
+CYDEV_IO_PC_PRT15_PC4 EQU 0x4000507c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC5\r
+CYDEV_IO_PC_PRT15_PC5 EQU 0x4000507d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_BASE\r
+CYDEV_IO_PC_PRT15_7_6_BASE EQU 0x4000507e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_SIZE\r
+CYDEV_IO_PC_PRT15_7_6_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_PC0\r
+CYDEV_IO_PC_PRT15_7_6_PC0 EQU 0x4000507e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_PC1\r
+CYDEV_IO_PC_PRT15_7_6_PC1 EQU 0x4000507f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_BASE\r
+CYDEV_IO_DR_BASE EQU 0x40005080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_SIZE\r
+CYDEV_IO_DR_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT0_BASE\r
+CYDEV_IO_DR_PRT0_BASE EQU 0x40005080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT0_SIZE\r
+CYDEV_IO_DR_PRT0_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT0_DR_ALIAS\r
+CYDEV_IO_DR_PRT0_DR_ALIAS EQU 0x40005080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT1_BASE\r
+CYDEV_IO_DR_PRT1_BASE EQU 0x40005081\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT1_SIZE\r
+CYDEV_IO_DR_PRT1_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT1_DR_ALIAS\r
+CYDEV_IO_DR_PRT1_DR_ALIAS EQU 0x40005081\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT2_BASE\r
+CYDEV_IO_DR_PRT2_BASE EQU 0x40005082\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT2_SIZE\r
+CYDEV_IO_DR_PRT2_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT2_DR_ALIAS\r
+CYDEV_IO_DR_PRT2_DR_ALIAS EQU 0x40005082\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT3_BASE\r
+CYDEV_IO_DR_PRT3_BASE EQU 0x40005083\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT3_SIZE\r
+CYDEV_IO_DR_PRT3_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT3_DR_ALIAS\r
+CYDEV_IO_DR_PRT3_DR_ALIAS EQU 0x40005083\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT4_BASE\r
+CYDEV_IO_DR_PRT4_BASE EQU 0x40005084\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT4_SIZE\r
+CYDEV_IO_DR_PRT4_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT4_DR_ALIAS\r
+CYDEV_IO_DR_PRT4_DR_ALIAS EQU 0x40005084\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT5_BASE\r
+CYDEV_IO_DR_PRT5_BASE EQU 0x40005085\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT5_SIZE\r
+CYDEV_IO_DR_PRT5_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT5_DR_ALIAS\r
+CYDEV_IO_DR_PRT5_DR_ALIAS EQU 0x40005085\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT6_BASE\r
+CYDEV_IO_DR_PRT6_BASE EQU 0x40005086\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT6_SIZE\r
+CYDEV_IO_DR_PRT6_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT6_DR_ALIAS\r
+CYDEV_IO_DR_PRT6_DR_ALIAS EQU 0x40005086\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT12_BASE\r
+CYDEV_IO_DR_PRT12_BASE EQU 0x4000508c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT12_SIZE\r
+CYDEV_IO_DR_PRT12_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT12_DR_ALIAS\r
+CYDEV_IO_DR_PRT12_DR_ALIAS EQU 0x4000508c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT15_BASE\r
+CYDEV_IO_DR_PRT15_BASE EQU 0x4000508f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT15_SIZE\r
+CYDEV_IO_DR_PRT15_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT15_DR_15_ALIAS\r
+CYDEV_IO_DR_PRT15_DR_15_ALIAS EQU 0x4000508f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_BASE\r
+CYDEV_IO_PS_BASE EQU 0x40005090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_SIZE\r
+CYDEV_IO_PS_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT0_BASE\r
+CYDEV_IO_PS_PRT0_BASE EQU 0x40005090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT0_SIZE\r
+CYDEV_IO_PS_PRT0_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT0_PS_ALIAS\r
+CYDEV_IO_PS_PRT0_PS_ALIAS EQU 0x40005090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT1_BASE\r
+CYDEV_IO_PS_PRT1_BASE EQU 0x40005091\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT1_SIZE\r
+CYDEV_IO_PS_PRT1_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT1_PS_ALIAS\r
+CYDEV_IO_PS_PRT1_PS_ALIAS EQU 0x40005091\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT2_BASE\r
+CYDEV_IO_PS_PRT2_BASE EQU 0x40005092\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT2_SIZE\r
+CYDEV_IO_PS_PRT2_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT2_PS_ALIAS\r
+CYDEV_IO_PS_PRT2_PS_ALIAS EQU 0x40005092\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT3_BASE\r
+CYDEV_IO_PS_PRT3_BASE EQU 0x40005093\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT3_SIZE\r
+CYDEV_IO_PS_PRT3_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT3_PS_ALIAS\r
+CYDEV_IO_PS_PRT3_PS_ALIAS EQU 0x40005093\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT4_BASE\r
+CYDEV_IO_PS_PRT4_BASE EQU 0x40005094\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT4_SIZE\r
+CYDEV_IO_PS_PRT4_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT4_PS_ALIAS\r
+CYDEV_IO_PS_PRT4_PS_ALIAS EQU 0x40005094\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT5_BASE\r
+CYDEV_IO_PS_PRT5_BASE EQU 0x40005095\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT5_SIZE\r
+CYDEV_IO_PS_PRT5_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT5_PS_ALIAS\r
+CYDEV_IO_PS_PRT5_PS_ALIAS EQU 0x40005095\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT6_BASE\r
+CYDEV_IO_PS_PRT6_BASE EQU 0x40005096\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT6_SIZE\r
+CYDEV_IO_PS_PRT6_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT6_PS_ALIAS\r
+CYDEV_IO_PS_PRT6_PS_ALIAS EQU 0x40005096\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT12_BASE\r
+CYDEV_IO_PS_PRT12_BASE EQU 0x4000509c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT12_SIZE\r
+CYDEV_IO_PS_PRT12_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT12_PS_ALIAS\r
+CYDEV_IO_PS_PRT12_PS_ALIAS EQU 0x4000509c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT15_BASE\r
+CYDEV_IO_PS_PRT15_BASE EQU 0x4000509f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT15_SIZE\r
+CYDEV_IO_PS_PRT15_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT15_PS15_ALIAS\r
+CYDEV_IO_PS_PRT15_PS15_ALIAS EQU 0x4000509f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_BASE\r
+CYDEV_IO_PRT_BASE EQU 0x40005100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_SIZE\r
+CYDEV_IO_PRT_SIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BASE\r
+CYDEV_IO_PRT_PRT0_BASE EQU 0x40005100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SIZE\r
+CYDEV_IO_PRT_PRT0_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DR\r
+CYDEV_IO_PRT_PRT0_DR EQU 0x40005100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_PS\r
+CYDEV_IO_PRT_PRT0_PS EQU 0x40005101\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM0\r
+CYDEV_IO_PRT_PRT0_DM0 EQU 0x40005102\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM1\r
+CYDEV_IO_PRT_PRT0_DM1 EQU 0x40005103\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM2\r
+CYDEV_IO_PRT_PRT0_DM2 EQU 0x40005104\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SLW\r
+CYDEV_IO_PRT_PRT0_SLW EQU 0x40005105\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BYP\r
+CYDEV_IO_PRT_PRT0_BYP EQU 0x40005106\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BIE\r
+CYDEV_IO_PRT_PRT0_BIE EQU 0x40005107\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_INP_DIS\r
+CYDEV_IO_PRT_PRT0_INP_DIS EQU 0x40005108\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_CTL\r
+CYDEV_IO_PRT_PRT0_CTL EQU 0x40005109\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_PRT\r
+CYDEV_IO_PRT_PRT0_PRT EQU 0x4000510a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BIT_MASK\r
+CYDEV_IO_PRT_PRT0_BIT_MASK EQU 0x4000510b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_AMUX\r
+CYDEV_IO_PRT_PRT0_AMUX EQU 0x4000510c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_AG\r
+CYDEV_IO_PRT_PRT0_AG EQU 0x4000510d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_LCD_COM_SEG\r
+CYDEV_IO_PRT_PRT0_LCD_COM_SEG EQU 0x4000510e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_LCD_EN\r
+CYDEV_IO_PRT_PRT0_LCD_EN EQU 0x4000510f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BASE\r
+CYDEV_IO_PRT_PRT1_BASE EQU 0x40005110\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SIZE\r
+CYDEV_IO_PRT_PRT1_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DR\r
+CYDEV_IO_PRT_PRT1_DR EQU 0x40005110\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_PS\r
+CYDEV_IO_PRT_PRT1_PS EQU 0x40005111\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM0\r
+CYDEV_IO_PRT_PRT1_DM0 EQU 0x40005112\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM1\r
+CYDEV_IO_PRT_PRT1_DM1 EQU 0x40005113\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM2\r
+CYDEV_IO_PRT_PRT1_DM2 EQU 0x40005114\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SLW\r
+CYDEV_IO_PRT_PRT1_SLW EQU 0x40005115\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BYP\r
+CYDEV_IO_PRT_PRT1_BYP EQU 0x40005116\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BIE\r
+CYDEV_IO_PRT_PRT1_BIE EQU 0x40005117\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_INP_DIS\r
+CYDEV_IO_PRT_PRT1_INP_DIS EQU 0x40005118\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_CTL\r
+CYDEV_IO_PRT_PRT1_CTL EQU 0x40005119\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_PRT\r
+CYDEV_IO_PRT_PRT1_PRT EQU 0x4000511a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BIT_MASK\r
+CYDEV_IO_PRT_PRT1_BIT_MASK EQU 0x4000511b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_AMUX\r
+CYDEV_IO_PRT_PRT1_AMUX EQU 0x4000511c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_AG\r
+CYDEV_IO_PRT_PRT1_AG EQU 0x4000511d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_LCD_COM_SEG\r
+CYDEV_IO_PRT_PRT1_LCD_COM_SEG EQU 0x4000511e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_LCD_EN\r
+CYDEV_IO_PRT_PRT1_LCD_EN EQU 0x4000511f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BASE\r
+CYDEV_IO_PRT_PRT2_BASE EQU 0x40005120\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SIZE\r
+CYDEV_IO_PRT_PRT2_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DR\r
+CYDEV_IO_PRT_PRT2_DR EQU 0x40005120\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_PS\r
+CYDEV_IO_PRT_PRT2_PS EQU 0x40005121\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM0\r
+CYDEV_IO_PRT_PRT2_DM0 EQU 0x40005122\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM1\r
+CYDEV_IO_PRT_PRT2_DM1 EQU 0x40005123\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM2\r
+CYDEV_IO_PRT_PRT2_DM2 EQU 0x40005124\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SLW\r
+CYDEV_IO_PRT_PRT2_SLW EQU 0x40005125\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BYP\r
+CYDEV_IO_PRT_PRT2_BYP EQU 0x40005126\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BIE\r
+CYDEV_IO_PRT_PRT2_BIE EQU 0x40005127\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_INP_DIS\r
+CYDEV_IO_PRT_PRT2_INP_DIS EQU 0x40005128\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_CTL\r
+CYDEV_IO_PRT_PRT2_CTL EQU 0x40005129\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_PRT\r
+CYDEV_IO_PRT_PRT2_PRT EQU 0x4000512a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BIT_MASK\r
+CYDEV_IO_PRT_PRT2_BIT_MASK EQU 0x4000512b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_AMUX\r
+CYDEV_IO_PRT_PRT2_AMUX EQU 0x4000512c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_AG\r
+CYDEV_IO_PRT_PRT2_AG EQU 0x4000512d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_LCD_COM_SEG\r
+CYDEV_IO_PRT_PRT2_LCD_COM_SEG EQU 0x4000512e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_LCD_EN\r
+CYDEV_IO_PRT_PRT2_LCD_EN EQU 0x4000512f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BASE\r
+CYDEV_IO_PRT_PRT3_BASE EQU 0x40005130\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SIZE\r
+CYDEV_IO_PRT_PRT3_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DR\r
+CYDEV_IO_PRT_PRT3_DR EQU 0x40005130\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_PS\r
+CYDEV_IO_PRT_PRT3_PS EQU 0x40005131\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM0\r
+CYDEV_IO_PRT_PRT3_DM0 EQU 0x40005132\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM1\r
+CYDEV_IO_PRT_PRT3_DM1 EQU 0x40005133\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM2\r
+CYDEV_IO_PRT_PRT3_DM2 EQU 0x40005134\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SLW\r
+CYDEV_IO_PRT_PRT3_SLW EQU 0x40005135\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BYP\r
+CYDEV_IO_PRT_PRT3_BYP EQU 0x40005136\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BIE\r
+CYDEV_IO_PRT_PRT3_BIE EQU 0x40005137\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_INP_DIS\r
+CYDEV_IO_PRT_PRT3_INP_DIS EQU 0x40005138\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_CTL\r
+CYDEV_IO_PRT_PRT3_CTL EQU 0x40005139\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_PRT\r
+CYDEV_IO_PRT_PRT3_PRT EQU 0x4000513a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BIT_MASK\r
+CYDEV_IO_PRT_PRT3_BIT_MASK EQU 0x4000513b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_AMUX\r
+CYDEV_IO_PRT_PRT3_AMUX EQU 0x4000513c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_AG\r
+CYDEV_IO_PRT_PRT3_AG EQU 0x4000513d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_LCD_COM_SEG\r
+CYDEV_IO_PRT_PRT3_LCD_COM_SEG EQU 0x4000513e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_LCD_EN\r
+CYDEV_IO_PRT_PRT3_LCD_EN EQU 0x4000513f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BASE\r
+CYDEV_IO_PRT_PRT4_BASE EQU 0x40005140\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SIZE\r
+CYDEV_IO_PRT_PRT4_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DR\r
+CYDEV_IO_PRT_PRT4_DR EQU 0x40005140\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_PS\r
+CYDEV_IO_PRT_PRT4_PS EQU 0x40005141\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM0\r
+CYDEV_IO_PRT_PRT4_DM0 EQU 0x40005142\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM1\r
+CYDEV_IO_PRT_PRT4_DM1 EQU 0x40005143\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM2\r
+CYDEV_IO_PRT_PRT4_DM2 EQU 0x40005144\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SLW\r
+CYDEV_IO_PRT_PRT4_SLW EQU 0x40005145\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BYP\r
+CYDEV_IO_PRT_PRT4_BYP EQU 0x40005146\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BIE\r
+CYDEV_IO_PRT_PRT4_BIE EQU 0x40005147\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_INP_DIS\r
+CYDEV_IO_PRT_PRT4_INP_DIS EQU 0x40005148\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_CTL\r
+CYDEV_IO_PRT_PRT4_CTL EQU 0x40005149\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_PRT\r
+CYDEV_IO_PRT_PRT4_PRT EQU 0x4000514a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BIT_MASK\r
+CYDEV_IO_PRT_PRT4_BIT_MASK EQU 0x4000514b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_AMUX\r
+CYDEV_IO_PRT_PRT4_AMUX EQU 0x4000514c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_AG\r
+CYDEV_IO_PRT_PRT4_AG EQU 0x4000514d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_LCD_COM_SEG\r
+CYDEV_IO_PRT_PRT4_LCD_COM_SEG EQU 0x4000514e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_LCD_EN\r
+CYDEV_IO_PRT_PRT4_LCD_EN EQU 0x4000514f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BASE\r
+CYDEV_IO_PRT_PRT5_BASE EQU 0x40005150\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SIZE\r
+CYDEV_IO_PRT_PRT5_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DR\r
+CYDEV_IO_PRT_PRT5_DR EQU 0x40005150\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_PS\r
+CYDEV_IO_PRT_PRT5_PS EQU 0x40005151\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM0\r
+CYDEV_IO_PRT_PRT5_DM0 EQU 0x40005152\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM1\r
+CYDEV_IO_PRT_PRT5_DM1 EQU 0x40005153\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM2\r
+CYDEV_IO_PRT_PRT5_DM2 EQU 0x40005154\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SLW\r
+CYDEV_IO_PRT_PRT5_SLW EQU 0x40005155\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BYP\r
+CYDEV_IO_PRT_PRT5_BYP EQU 0x40005156\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BIE\r
+CYDEV_IO_PRT_PRT5_BIE EQU 0x40005157\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_INP_DIS\r
+CYDEV_IO_PRT_PRT5_INP_DIS EQU 0x40005158\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_CTL\r
+CYDEV_IO_PRT_PRT5_CTL EQU 0x40005159\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_PRT\r
+CYDEV_IO_PRT_PRT5_PRT EQU 0x4000515a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BIT_MASK\r
+CYDEV_IO_PRT_PRT5_BIT_MASK EQU 0x4000515b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_AMUX\r
+CYDEV_IO_PRT_PRT5_AMUX EQU 0x4000515c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_AG\r
+CYDEV_IO_PRT_PRT5_AG EQU 0x4000515d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_LCD_COM_SEG\r
+CYDEV_IO_PRT_PRT5_LCD_COM_SEG EQU 0x4000515e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_LCD_EN\r
+CYDEV_IO_PRT_PRT5_LCD_EN EQU 0x4000515f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BASE\r
+CYDEV_IO_PRT_PRT6_BASE EQU 0x40005160\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SIZE\r
+CYDEV_IO_PRT_PRT6_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DR\r
+CYDEV_IO_PRT_PRT6_DR EQU 0x40005160\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_PS\r
+CYDEV_IO_PRT_PRT6_PS EQU 0x40005161\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM0\r
+CYDEV_IO_PRT_PRT6_DM0 EQU 0x40005162\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM1\r
+CYDEV_IO_PRT_PRT6_DM1 EQU 0x40005163\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM2\r
+CYDEV_IO_PRT_PRT6_DM2 EQU 0x40005164\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SLW\r
+CYDEV_IO_PRT_PRT6_SLW EQU 0x40005165\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BYP\r
+CYDEV_IO_PRT_PRT6_BYP EQU 0x40005166\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BIE\r
+CYDEV_IO_PRT_PRT6_BIE EQU 0x40005167\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_INP_DIS\r
+CYDEV_IO_PRT_PRT6_INP_DIS EQU 0x40005168\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_CTL\r
+CYDEV_IO_PRT_PRT6_CTL EQU 0x40005169\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_PRT\r
+CYDEV_IO_PRT_PRT6_PRT EQU 0x4000516a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BIT_MASK\r
+CYDEV_IO_PRT_PRT6_BIT_MASK EQU 0x4000516b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_AMUX\r
+CYDEV_IO_PRT_PRT6_AMUX EQU 0x4000516c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_AG\r
+CYDEV_IO_PRT_PRT6_AG EQU 0x4000516d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_LCD_COM_SEG\r
+CYDEV_IO_PRT_PRT6_LCD_COM_SEG EQU 0x4000516e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_LCD_EN\r
+CYDEV_IO_PRT_PRT6_LCD_EN EQU 0x4000516f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BASE\r
+CYDEV_IO_PRT_PRT12_BASE EQU 0x400051c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIZE\r
+CYDEV_IO_PRT_PRT12_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DR\r
+CYDEV_IO_PRT_PRT12_DR EQU 0x400051c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_PS\r
+CYDEV_IO_PRT_PRT12_PS EQU 0x400051c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM0\r
+CYDEV_IO_PRT_PRT12_DM0 EQU 0x400051c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM1\r
+CYDEV_IO_PRT_PRT12_DM1 EQU 0x400051c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM2\r
+CYDEV_IO_PRT_PRT12_DM2 EQU 0x400051c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SLW\r
+CYDEV_IO_PRT_PRT12_SLW EQU 0x400051c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BYP\r
+CYDEV_IO_PRT_PRT12_BYP EQU 0x400051c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BIE\r
+CYDEV_IO_PRT_PRT12_BIE EQU 0x400051c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_INP_DIS\r
+CYDEV_IO_PRT_PRT12_INP_DIS EQU 0x400051c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_HYST_EN\r
+CYDEV_IO_PRT_PRT12_SIO_HYST_EN EQU 0x400051c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_PRT\r
+CYDEV_IO_PRT_PRT12_PRT EQU 0x400051ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BIT_MASK\r
+CYDEV_IO_PRT_PRT12_BIT_MASK EQU 0x400051cb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ\r
+CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ EQU 0x400051cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_AG\r
+CYDEV_IO_PRT_PRT12_AG EQU 0x400051cd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_CFG\r
+CYDEV_IO_PRT_PRT12_SIO_CFG EQU 0x400051ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_DIFF\r
+CYDEV_IO_PRT_PRT12_SIO_DIFF EQU 0x400051cf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BASE\r
+CYDEV_IO_PRT_PRT15_BASE EQU 0x400051f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SIZE\r
+CYDEV_IO_PRT_PRT15_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DR\r
+CYDEV_IO_PRT_PRT15_DR EQU 0x400051f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_PS\r
+CYDEV_IO_PRT_PRT15_PS EQU 0x400051f1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM0\r
+CYDEV_IO_PRT_PRT15_DM0 EQU 0x400051f2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM1\r
+CYDEV_IO_PRT_PRT15_DM1 EQU 0x400051f3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM2\r
+CYDEV_IO_PRT_PRT15_DM2 EQU 0x400051f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SLW\r
+CYDEV_IO_PRT_PRT15_SLW EQU 0x400051f5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BYP\r
+CYDEV_IO_PRT_PRT15_BYP EQU 0x400051f6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BIE\r
+CYDEV_IO_PRT_PRT15_BIE EQU 0x400051f7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_INP_DIS\r
+CYDEV_IO_PRT_PRT15_INP_DIS EQU 0x400051f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_CTL\r
+CYDEV_IO_PRT_PRT15_CTL EQU 0x400051f9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_PRT\r
+CYDEV_IO_PRT_PRT15_PRT EQU 0x400051fa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BIT_MASK\r
+CYDEV_IO_PRT_PRT15_BIT_MASK EQU 0x400051fb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_AMUX\r
+CYDEV_IO_PRT_PRT15_AMUX EQU 0x400051fc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_AG\r
+CYDEV_IO_PRT_PRT15_AG EQU 0x400051fd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_LCD_COM_SEG\r
+CYDEV_IO_PRT_PRT15_LCD_COM_SEG EQU 0x400051fe\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_LCD_EN\r
+CYDEV_IO_PRT_PRT15_LCD_EN EQU 0x400051ff\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_BASE\r
+CYDEV_PRTDSI_BASE EQU 0x40005200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_SIZE\r
+CYDEV_PRTDSI_SIZE EQU 0x0000007f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_BASE\r
+CYDEV_PRTDSI_PRT0_BASE EQU 0x40005200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SIZE\r
+CYDEV_PRTDSI_PRT0_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OUT_SEL0\r
+CYDEV_PRTDSI_PRT0_OUT_SEL0 EQU 0x40005200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OUT_SEL1\r
+CYDEV_PRTDSI_PRT0_OUT_SEL1 EQU 0x40005201\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OE_SEL0\r
+CYDEV_PRTDSI_PRT0_OE_SEL0 EQU 0x40005202\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OE_SEL1\r
+CYDEV_PRTDSI_PRT0_OE_SEL1 EQU 0x40005203\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_DBL_SYNC_IN\r
+CYDEV_PRTDSI_PRT0_DBL_SYNC_IN EQU 0x40005204\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SYNC_OUT\r
+CYDEV_PRTDSI_PRT0_SYNC_OUT EQU 0x40005205\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_CAPS_SEL\r
+CYDEV_PRTDSI_PRT0_CAPS_SEL EQU 0x40005206\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_BASE\r
+CYDEV_PRTDSI_PRT1_BASE EQU 0x40005208\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SIZE\r
+CYDEV_PRTDSI_PRT1_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OUT_SEL0\r
+CYDEV_PRTDSI_PRT1_OUT_SEL0 EQU 0x40005208\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OUT_SEL1\r
+CYDEV_PRTDSI_PRT1_OUT_SEL1 EQU 0x40005209\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OE_SEL0\r
+CYDEV_PRTDSI_PRT1_OE_SEL0 EQU 0x4000520a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OE_SEL1\r
+CYDEV_PRTDSI_PRT1_OE_SEL1 EQU 0x4000520b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_DBL_SYNC_IN\r
+CYDEV_PRTDSI_PRT1_DBL_SYNC_IN EQU 0x4000520c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SYNC_OUT\r
+CYDEV_PRTDSI_PRT1_SYNC_OUT EQU 0x4000520d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_CAPS_SEL\r
+CYDEV_PRTDSI_PRT1_CAPS_SEL EQU 0x4000520e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_BASE\r
+CYDEV_PRTDSI_PRT2_BASE EQU 0x40005210\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SIZE\r
+CYDEV_PRTDSI_PRT2_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OUT_SEL0\r
+CYDEV_PRTDSI_PRT2_OUT_SEL0 EQU 0x40005210\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OUT_SEL1\r
+CYDEV_PRTDSI_PRT2_OUT_SEL1 EQU 0x40005211\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OE_SEL0\r
+CYDEV_PRTDSI_PRT2_OE_SEL0 EQU 0x40005212\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OE_SEL1\r
+CYDEV_PRTDSI_PRT2_OE_SEL1 EQU 0x40005213\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_DBL_SYNC_IN\r
+CYDEV_PRTDSI_PRT2_DBL_SYNC_IN EQU 0x40005214\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SYNC_OUT\r
+CYDEV_PRTDSI_PRT2_SYNC_OUT EQU 0x40005215\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_CAPS_SEL\r
+CYDEV_PRTDSI_PRT2_CAPS_SEL EQU 0x40005216\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_BASE\r
+CYDEV_PRTDSI_PRT3_BASE EQU 0x40005218\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SIZE\r
+CYDEV_PRTDSI_PRT3_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OUT_SEL0\r
+CYDEV_PRTDSI_PRT3_OUT_SEL0 EQU 0x40005218\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OUT_SEL1\r
+CYDEV_PRTDSI_PRT3_OUT_SEL1 EQU 0x40005219\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OE_SEL0\r
+CYDEV_PRTDSI_PRT3_OE_SEL0 EQU 0x4000521a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OE_SEL1\r
+CYDEV_PRTDSI_PRT3_OE_SEL1 EQU 0x4000521b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_DBL_SYNC_IN\r
+CYDEV_PRTDSI_PRT3_DBL_SYNC_IN EQU 0x4000521c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SYNC_OUT\r
+CYDEV_PRTDSI_PRT3_SYNC_OUT EQU 0x4000521d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_CAPS_SEL\r
+CYDEV_PRTDSI_PRT3_CAPS_SEL EQU 0x4000521e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_BASE\r
+CYDEV_PRTDSI_PRT4_BASE EQU 0x40005220\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SIZE\r
+CYDEV_PRTDSI_PRT4_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OUT_SEL0\r
+CYDEV_PRTDSI_PRT4_OUT_SEL0 EQU 0x40005220\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OUT_SEL1\r
+CYDEV_PRTDSI_PRT4_OUT_SEL1 EQU 0x40005221\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OE_SEL0\r
+CYDEV_PRTDSI_PRT4_OE_SEL0 EQU 0x40005222\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OE_SEL1\r
+CYDEV_PRTDSI_PRT4_OE_SEL1 EQU 0x40005223\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_DBL_SYNC_IN\r
+CYDEV_PRTDSI_PRT4_DBL_SYNC_IN EQU 0x40005224\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SYNC_OUT\r
+CYDEV_PRTDSI_PRT4_SYNC_OUT EQU 0x40005225\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_CAPS_SEL\r
+CYDEV_PRTDSI_PRT4_CAPS_SEL EQU 0x40005226\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_BASE\r
+CYDEV_PRTDSI_PRT5_BASE EQU 0x40005228\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SIZE\r
+CYDEV_PRTDSI_PRT5_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OUT_SEL0\r
+CYDEV_PRTDSI_PRT5_OUT_SEL0 EQU 0x40005228\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OUT_SEL1\r
+CYDEV_PRTDSI_PRT5_OUT_SEL1 EQU 0x40005229\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OE_SEL0\r
+CYDEV_PRTDSI_PRT5_OE_SEL0 EQU 0x4000522a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OE_SEL1\r
+CYDEV_PRTDSI_PRT5_OE_SEL1 EQU 0x4000522b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_DBL_SYNC_IN\r
+CYDEV_PRTDSI_PRT5_DBL_SYNC_IN EQU 0x4000522c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SYNC_OUT\r
+CYDEV_PRTDSI_PRT5_SYNC_OUT EQU 0x4000522d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_CAPS_SEL\r
+CYDEV_PRTDSI_PRT5_CAPS_SEL EQU 0x4000522e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_BASE\r
+CYDEV_PRTDSI_PRT6_BASE EQU 0x40005230\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SIZE\r
+CYDEV_PRTDSI_PRT6_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OUT_SEL0\r
+CYDEV_PRTDSI_PRT6_OUT_SEL0 EQU 0x40005230\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OUT_SEL1\r
+CYDEV_PRTDSI_PRT6_OUT_SEL1 EQU 0x40005231\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OE_SEL0\r
+CYDEV_PRTDSI_PRT6_OE_SEL0 EQU 0x40005232\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OE_SEL1\r
+CYDEV_PRTDSI_PRT6_OE_SEL1 EQU 0x40005233\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_DBL_SYNC_IN\r
+CYDEV_PRTDSI_PRT6_DBL_SYNC_IN EQU 0x40005234\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SYNC_OUT\r
+CYDEV_PRTDSI_PRT6_SYNC_OUT EQU 0x40005235\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_CAPS_SEL\r
+CYDEV_PRTDSI_PRT6_CAPS_SEL EQU 0x40005236\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_BASE\r
+CYDEV_PRTDSI_PRT12_BASE EQU 0x40005260\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SIZE\r
+CYDEV_PRTDSI_PRT12_SIZE EQU 0x00000006\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OUT_SEL0\r
+CYDEV_PRTDSI_PRT12_OUT_SEL0 EQU 0x40005260\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OUT_SEL1\r
+CYDEV_PRTDSI_PRT12_OUT_SEL1 EQU 0x40005261\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OE_SEL0\r
+CYDEV_PRTDSI_PRT12_OE_SEL0 EQU 0x40005262\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OE_SEL1\r
+CYDEV_PRTDSI_PRT12_OE_SEL1 EQU 0x40005263\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_DBL_SYNC_IN\r
+CYDEV_PRTDSI_PRT12_DBL_SYNC_IN EQU 0x40005264\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SYNC_OUT\r
+CYDEV_PRTDSI_PRT12_SYNC_OUT EQU 0x40005265\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_BASE\r
+CYDEV_PRTDSI_PRT15_BASE EQU 0x40005278\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SIZE\r
+CYDEV_PRTDSI_PRT15_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OUT_SEL0\r
+CYDEV_PRTDSI_PRT15_OUT_SEL0 EQU 0x40005278\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OUT_SEL1\r
+CYDEV_PRTDSI_PRT15_OUT_SEL1 EQU 0x40005279\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OE_SEL0\r
+CYDEV_PRTDSI_PRT15_OE_SEL0 EQU 0x4000527a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OE_SEL1\r
+CYDEV_PRTDSI_PRT15_OE_SEL1 EQU 0x4000527b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_DBL_SYNC_IN\r
+CYDEV_PRTDSI_PRT15_DBL_SYNC_IN EQU 0x4000527c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SYNC_OUT\r
+CYDEV_PRTDSI_PRT15_SYNC_OUT EQU 0x4000527d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_CAPS_SEL\r
+CYDEV_PRTDSI_PRT15_CAPS_SEL EQU 0x4000527e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EMIF_BASE\r
+CYDEV_EMIF_BASE EQU 0x40005400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EMIF_SIZE\r
+CYDEV_EMIF_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EMIF_NO_UDB\r
+CYDEV_EMIF_NO_UDB EQU 0x40005400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EMIF_RP_WAIT_STATES\r
+CYDEV_EMIF_RP_WAIT_STATES EQU 0x40005401\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EMIF_MEM_DWN\r
+CYDEV_EMIF_MEM_DWN EQU 0x40005402\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EMIF_MEMCLK_DIV\r
+CYDEV_EMIF_MEMCLK_DIV EQU 0x40005403\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EMIF_CLOCK_EN\r
+CYDEV_EMIF_CLOCK_EN EQU 0x40005404\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EMIF_EM_TYPE\r
+CYDEV_EMIF_EM_TYPE EQU 0x40005405\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EMIF_WP_WAIT_STATES\r
+CYDEV_EMIF_WP_WAIT_STATES EQU 0x40005406\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_BASE\r
+CYDEV_ANAIF_BASE EQU 0x40005800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_SIZE\r
+CYDEV_ANAIF_SIZE EQU 0x000003a9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_BASE\r
+CYDEV_ANAIF_CFG_BASE EQU 0x40005800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SIZE\r
+CYDEV_ANAIF_CFG_SIZE EQU 0x0000010f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_BASE\r
+CYDEV_ANAIF_CFG_SC0_BASE EQU 0x40005800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_SIZE\r
+CYDEV_ANAIF_CFG_SC0_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR0\r
+CYDEV_ANAIF_CFG_SC0_CR0 EQU 0x40005800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR1\r
+CYDEV_ANAIF_CFG_SC0_CR1 EQU 0x40005801\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR2\r
+CYDEV_ANAIF_CFG_SC0_CR2 EQU 0x40005802\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_BASE\r
+CYDEV_ANAIF_CFG_SC1_BASE EQU 0x40005804\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_SIZE\r
+CYDEV_ANAIF_CFG_SC1_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR0\r
+CYDEV_ANAIF_CFG_SC1_CR0 EQU 0x40005804\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR1\r
+CYDEV_ANAIF_CFG_SC1_CR1 EQU 0x40005805\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR2\r
+CYDEV_ANAIF_CFG_SC1_CR2 EQU 0x40005806\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_BASE\r
+CYDEV_ANAIF_CFG_SC2_BASE EQU 0x40005808\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_SIZE\r
+CYDEV_ANAIF_CFG_SC2_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR0\r
+CYDEV_ANAIF_CFG_SC2_CR0 EQU 0x40005808\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR1\r
+CYDEV_ANAIF_CFG_SC2_CR1 EQU 0x40005809\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR2\r
+CYDEV_ANAIF_CFG_SC2_CR2 EQU 0x4000580a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_BASE\r
+CYDEV_ANAIF_CFG_SC3_BASE EQU 0x4000580c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_SIZE\r
+CYDEV_ANAIF_CFG_SC3_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR0\r
+CYDEV_ANAIF_CFG_SC3_CR0 EQU 0x4000580c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR1\r
+CYDEV_ANAIF_CFG_SC3_CR1 EQU 0x4000580d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR2\r
+CYDEV_ANAIF_CFG_SC3_CR2 EQU 0x4000580e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_BASE\r
+CYDEV_ANAIF_CFG_DAC0_BASE EQU 0x40005820\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_SIZE\r
+CYDEV_ANAIF_CFG_DAC0_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_CR0\r
+CYDEV_ANAIF_CFG_DAC0_CR0 EQU 0x40005820\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_CR1\r
+CYDEV_ANAIF_CFG_DAC0_CR1 EQU 0x40005821\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_TST\r
+CYDEV_ANAIF_CFG_DAC0_TST EQU 0x40005822\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_BASE\r
+CYDEV_ANAIF_CFG_DAC1_BASE EQU 0x40005824\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_SIZE\r
+CYDEV_ANAIF_CFG_DAC1_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_CR0\r
+CYDEV_ANAIF_CFG_DAC1_CR0 EQU 0x40005824\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_CR1\r
+CYDEV_ANAIF_CFG_DAC1_CR1 EQU 0x40005825\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_TST\r
+CYDEV_ANAIF_CFG_DAC1_TST EQU 0x40005826\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_BASE\r
+CYDEV_ANAIF_CFG_DAC2_BASE EQU 0x40005828\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_SIZE\r
+CYDEV_ANAIF_CFG_DAC2_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_CR0\r
+CYDEV_ANAIF_CFG_DAC2_CR0 EQU 0x40005828\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_CR1\r
+CYDEV_ANAIF_CFG_DAC2_CR1 EQU 0x40005829\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_TST\r
+CYDEV_ANAIF_CFG_DAC2_TST EQU 0x4000582a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_BASE\r
+CYDEV_ANAIF_CFG_DAC3_BASE EQU 0x4000582c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_SIZE\r
+CYDEV_ANAIF_CFG_DAC3_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_CR0\r
+CYDEV_ANAIF_CFG_DAC3_CR0 EQU 0x4000582c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_CR1\r
+CYDEV_ANAIF_CFG_DAC3_CR1 EQU 0x4000582d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_TST\r
+CYDEV_ANAIF_CFG_DAC3_TST EQU 0x4000582e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_BASE\r
+CYDEV_ANAIF_CFG_CMP0_BASE EQU 0x40005840\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_SIZE\r
+CYDEV_ANAIF_CFG_CMP0_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_CR\r
+CYDEV_ANAIF_CFG_CMP0_CR EQU 0x40005840\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_BASE\r
+CYDEV_ANAIF_CFG_CMP1_BASE EQU 0x40005841\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_SIZE\r
+CYDEV_ANAIF_CFG_CMP1_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_CR\r
+CYDEV_ANAIF_CFG_CMP1_CR EQU 0x40005841\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_BASE\r
+CYDEV_ANAIF_CFG_CMP2_BASE EQU 0x40005842\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_SIZE\r
+CYDEV_ANAIF_CFG_CMP2_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_CR\r
+CYDEV_ANAIF_CFG_CMP2_CR EQU 0x40005842\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_BASE\r
+CYDEV_ANAIF_CFG_CMP3_BASE EQU 0x40005843\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_SIZE\r
+CYDEV_ANAIF_CFG_CMP3_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_CR\r
+CYDEV_ANAIF_CFG_CMP3_CR EQU 0x40005843\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_BASE\r
+CYDEV_ANAIF_CFG_LUT0_BASE EQU 0x40005848\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_SIZE\r
+CYDEV_ANAIF_CFG_LUT0_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_CR\r
+CYDEV_ANAIF_CFG_LUT0_CR EQU 0x40005848\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_MX\r
+CYDEV_ANAIF_CFG_LUT0_MX EQU 0x40005849\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_BASE\r
+CYDEV_ANAIF_CFG_LUT1_BASE EQU 0x4000584a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_SIZE\r
+CYDEV_ANAIF_CFG_LUT1_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_CR\r
+CYDEV_ANAIF_CFG_LUT1_CR EQU 0x4000584a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_MX\r
+CYDEV_ANAIF_CFG_LUT1_MX EQU 0x4000584b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_BASE\r
+CYDEV_ANAIF_CFG_LUT2_BASE EQU 0x4000584c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_SIZE\r
+CYDEV_ANAIF_CFG_LUT2_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_CR\r
+CYDEV_ANAIF_CFG_LUT2_CR EQU 0x4000584c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_MX\r
+CYDEV_ANAIF_CFG_LUT2_MX EQU 0x4000584d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_BASE\r
+CYDEV_ANAIF_CFG_LUT3_BASE EQU 0x4000584e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_SIZE\r
+CYDEV_ANAIF_CFG_LUT3_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_CR\r
+CYDEV_ANAIF_CFG_LUT3_CR EQU 0x4000584e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_MX\r
+CYDEV_ANAIF_CFG_LUT3_MX EQU 0x4000584f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_BASE\r
+CYDEV_ANAIF_CFG_OPAMP0_BASE EQU 0x40005858\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_SIZE\r
+CYDEV_ANAIF_CFG_OPAMP0_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_CR\r
+CYDEV_ANAIF_CFG_OPAMP0_CR EQU 0x40005858\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_RSVD\r
+CYDEV_ANAIF_CFG_OPAMP0_RSVD EQU 0x40005859\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_BASE\r
+CYDEV_ANAIF_CFG_OPAMP1_BASE EQU 0x4000585a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_SIZE\r
+CYDEV_ANAIF_CFG_OPAMP1_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_CR\r
+CYDEV_ANAIF_CFG_OPAMP1_CR EQU 0x4000585a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_RSVD\r
+CYDEV_ANAIF_CFG_OPAMP1_RSVD EQU 0x4000585b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_BASE\r
+CYDEV_ANAIF_CFG_OPAMP2_BASE EQU 0x4000585c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_SIZE\r
+CYDEV_ANAIF_CFG_OPAMP2_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_CR\r
+CYDEV_ANAIF_CFG_OPAMP2_CR EQU 0x4000585c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_RSVD\r
+CYDEV_ANAIF_CFG_OPAMP2_RSVD EQU 0x4000585d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_BASE\r
+CYDEV_ANAIF_CFG_OPAMP3_BASE EQU 0x4000585e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_SIZE\r
+CYDEV_ANAIF_CFG_OPAMP3_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_CR\r
+CYDEV_ANAIF_CFG_OPAMP3_CR EQU 0x4000585e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_RSVD\r
+CYDEV_ANAIF_CFG_OPAMP3_RSVD EQU 0x4000585f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_BASE\r
+CYDEV_ANAIF_CFG_LCDDAC_BASE EQU 0x40005868\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_SIZE\r
+CYDEV_ANAIF_CFG_LCDDAC_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_CR0\r
+CYDEV_ANAIF_CFG_LCDDAC_CR0 EQU 0x40005868\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_CR1\r
+CYDEV_ANAIF_CFG_LCDDAC_CR1 EQU 0x40005869\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_BASE\r
+CYDEV_ANAIF_CFG_LCDDRV_BASE EQU 0x4000586a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_SIZE\r
+CYDEV_ANAIF_CFG_LCDDRV_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_CR\r
+CYDEV_ANAIF_CFG_LCDDRV_CR EQU 0x4000586a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_BASE\r
+CYDEV_ANAIF_CFG_LCDTMR_BASE EQU 0x4000586b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_SIZE\r
+CYDEV_ANAIF_CFG_LCDTMR_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_CFG\r
+CYDEV_ANAIF_CFG_LCDTMR_CFG EQU 0x4000586b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_BASE\r
+CYDEV_ANAIF_CFG_BG_BASE EQU 0x4000586c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_SIZE\r
+CYDEV_ANAIF_CFG_BG_SIZE EQU 0x00000004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_CR0\r
+CYDEV_ANAIF_CFG_BG_CR0 EQU 0x4000586c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_RSVD\r
+CYDEV_ANAIF_CFG_BG_RSVD EQU 0x4000586d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_DFT0\r
+CYDEV_ANAIF_CFG_BG_DFT0 EQU 0x4000586e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_DFT1\r
+CYDEV_ANAIF_CFG_BG_DFT1 EQU 0x4000586f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_BASE\r
+CYDEV_ANAIF_CFG_CAPSL_BASE EQU 0x40005870\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_SIZE\r
+CYDEV_ANAIF_CFG_CAPSL_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_CFG0\r
+CYDEV_ANAIF_CFG_CAPSL_CFG0 EQU 0x40005870\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_CFG1\r
+CYDEV_ANAIF_CFG_CAPSL_CFG1 EQU 0x40005871\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_BASE\r
+CYDEV_ANAIF_CFG_CAPSR_BASE EQU 0x40005872\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_SIZE\r
+CYDEV_ANAIF_CFG_CAPSR_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_CFG0\r
+CYDEV_ANAIF_CFG_CAPSR_CFG0 EQU 0x40005872\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_CFG1\r
+CYDEV_ANAIF_CFG_CAPSR_CFG1 EQU 0x40005873\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_BASE\r
+CYDEV_ANAIF_CFG_PUMP_BASE EQU 0x40005876\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_SIZE\r
+CYDEV_ANAIF_CFG_PUMP_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_CR0\r
+CYDEV_ANAIF_CFG_PUMP_CR0 EQU 0x40005876\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_CR1\r
+CYDEV_ANAIF_CFG_PUMP_CR1 EQU 0x40005877\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_BASE\r
+CYDEV_ANAIF_CFG_LPF0_BASE EQU 0x40005878\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_SIZE\r
+CYDEV_ANAIF_CFG_LPF0_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_CR0\r
+CYDEV_ANAIF_CFG_LPF0_CR0 EQU 0x40005878\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_RSVD\r
+CYDEV_ANAIF_CFG_LPF0_RSVD EQU 0x40005879\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_BASE\r
+CYDEV_ANAIF_CFG_LPF1_BASE EQU 0x4000587a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_SIZE\r
+CYDEV_ANAIF_CFG_LPF1_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_CR0\r
+CYDEV_ANAIF_CFG_LPF1_CR0 EQU 0x4000587a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_RSVD\r
+CYDEV_ANAIF_CFG_LPF1_RSVD EQU 0x4000587b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_BASE\r
+CYDEV_ANAIF_CFG_MISC_BASE EQU 0x4000587c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_SIZE\r
+CYDEV_ANAIF_CFG_MISC_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_CR0\r
+CYDEV_ANAIF_CFG_MISC_CR0 EQU 0x4000587c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BASE\r
+CYDEV_ANAIF_CFG_DSM0_BASE EQU 0x40005880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_SIZE\r
+CYDEV_ANAIF_CFG_DSM0_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR0\r
+CYDEV_ANAIF_CFG_DSM0_CR0 EQU 0x40005880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR1\r
+CYDEV_ANAIF_CFG_DSM0_CR1 EQU 0x40005881\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR2\r
+CYDEV_ANAIF_CFG_DSM0_CR2 EQU 0x40005882\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR3\r
+CYDEV_ANAIF_CFG_DSM0_CR3 EQU 0x40005883\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR4\r
+CYDEV_ANAIF_CFG_DSM0_CR4 EQU 0x40005884\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR5\r
+CYDEV_ANAIF_CFG_DSM0_CR5 EQU 0x40005885\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR6\r
+CYDEV_ANAIF_CFG_DSM0_CR6 EQU 0x40005886\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR7\r
+CYDEV_ANAIF_CFG_DSM0_CR7 EQU 0x40005887\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR8\r
+CYDEV_ANAIF_CFG_DSM0_CR8 EQU 0x40005888\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR9\r
+CYDEV_ANAIF_CFG_DSM0_CR9 EQU 0x40005889\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR10\r
+CYDEV_ANAIF_CFG_DSM0_CR10 EQU 0x4000588a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR11\r
+CYDEV_ANAIF_CFG_DSM0_CR11 EQU 0x4000588b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR12\r
+CYDEV_ANAIF_CFG_DSM0_CR12 EQU 0x4000588c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR13\r
+CYDEV_ANAIF_CFG_DSM0_CR13 EQU 0x4000588d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR14\r
+CYDEV_ANAIF_CFG_DSM0_CR14 EQU 0x4000588e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR15\r
+CYDEV_ANAIF_CFG_DSM0_CR15 EQU 0x4000588f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR16\r
+CYDEV_ANAIF_CFG_DSM0_CR16 EQU 0x40005890\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR17\r
+CYDEV_ANAIF_CFG_DSM0_CR17 EQU 0x40005891\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF0\r
+CYDEV_ANAIF_CFG_DSM0_REF0 EQU 0x40005892\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF1\r
+CYDEV_ANAIF_CFG_DSM0_REF1 EQU 0x40005893\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF2\r
+CYDEV_ANAIF_CFG_DSM0_REF2 EQU 0x40005894\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF3\r
+CYDEV_ANAIF_CFG_DSM0_REF3 EQU 0x40005895\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_DEM0\r
+CYDEV_ANAIF_CFG_DSM0_DEM0 EQU 0x40005896\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_DEM1\r
+CYDEV_ANAIF_CFG_DSM0_DEM1 EQU 0x40005897\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_TST0\r
+CYDEV_ANAIF_CFG_DSM0_TST0 EQU 0x40005898\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_TST1\r
+CYDEV_ANAIF_CFG_DSM0_TST1 EQU 0x40005899\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF0\r
+CYDEV_ANAIF_CFG_DSM0_BUF0 EQU 0x4000589a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF1\r
+CYDEV_ANAIF_CFG_DSM0_BUF1 EQU 0x4000589b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF2\r
+CYDEV_ANAIF_CFG_DSM0_BUF2 EQU 0x4000589c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF3\r
+CYDEV_ANAIF_CFG_DSM0_BUF3 EQU 0x4000589d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_MISC\r
+CYDEV_ANAIF_CFG_DSM0_MISC EQU 0x4000589e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_RSVD1\r
+CYDEV_ANAIF_CFG_DSM0_RSVD1 EQU 0x4000589f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_BASE\r
+CYDEV_ANAIF_CFG_SAR0_BASE EQU 0x40005900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_SIZE\r
+CYDEV_ANAIF_CFG_SAR0_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR0\r
+CYDEV_ANAIF_CFG_SAR0_CSR0 EQU 0x40005900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR1\r
+CYDEV_ANAIF_CFG_SAR0_CSR1 EQU 0x40005901\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR2\r
+CYDEV_ANAIF_CFG_SAR0_CSR2 EQU 0x40005902\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR3\r
+CYDEV_ANAIF_CFG_SAR0_CSR3 EQU 0x40005903\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR4\r
+CYDEV_ANAIF_CFG_SAR0_CSR4 EQU 0x40005904\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR5\r
+CYDEV_ANAIF_CFG_SAR0_CSR5 EQU 0x40005905\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR6\r
+CYDEV_ANAIF_CFG_SAR0_CSR6 EQU 0x40005906\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_BASE\r
+CYDEV_ANAIF_CFG_SAR1_BASE EQU 0x40005908\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_SIZE\r
+CYDEV_ANAIF_CFG_SAR1_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR0\r
+CYDEV_ANAIF_CFG_SAR1_CSR0 EQU 0x40005908\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR1\r
+CYDEV_ANAIF_CFG_SAR1_CSR1 EQU 0x40005909\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR2\r
+CYDEV_ANAIF_CFG_SAR1_CSR2 EQU 0x4000590a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR3\r
+CYDEV_ANAIF_CFG_SAR1_CSR3 EQU 0x4000590b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR4\r
+CYDEV_ANAIF_CFG_SAR1_CSR4 EQU 0x4000590c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR5\r
+CYDEV_ANAIF_CFG_SAR1_CSR5 EQU 0x4000590d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR6\r
+CYDEV_ANAIF_CFG_SAR1_CSR6 EQU 0x4000590e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_BASE\r
+CYDEV_ANAIF_RT_BASE EQU 0x40005a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SIZE\r
+CYDEV_ANAIF_RT_SIZE EQU 0x00000162\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BASE\r
+CYDEV_ANAIF_RT_SC0_BASE EQU 0x40005a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SIZE\r
+CYDEV_ANAIF_RT_SC0_SIZE EQU 0x0000000d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW0\r
+CYDEV_ANAIF_RT_SC0_SW0 EQU 0x40005a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW2\r
+CYDEV_ANAIF_RT_SC0_SW2 EQU 0x40005a02\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW3\r
+CYDEV_ANAIF_RT_SC0_SW3 EQU 0x40005a03\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW4\r
+CYDEV_ANAIF_RT_SC0_SW4 EQU 0x40005a04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW6\r
+CYDEV_ANAIF_RT_SC0_SW6 EQU 0x40005a06\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW7\r
+CYDEV_ANAIF_RT_SC0_SW7 EQU 0x40005a07\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW8\r
+CYDEV_ANAIF_RT_SC0_SW8 EQU 0x40005a08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW10\r
+CYDEV_ANAIF_RT_SC0_SW10 EQU 0x40005a0a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_CLK\r
+CYDEV_ANAIF_RT_SC0_CLK EQU 0x40005a0b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BST\r
+CYDEV_ANAIF_RT_SC0_BST EQU 0x40005a0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BASE\r
+CYDEV_ANAIF_RT_SC1_BASE EQU 0x40005a10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SIZE\r
+CYDEV_ANAIF_RT_SC1_SIZE EQU 0x0000000d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW0\r
+CYDEV_ANAIF_RT_SC1_SW0 EQU 0x40005a10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW2\r
+CYDEV_ANAIF_RT_SC1_SW2 EQU 0x40005a12\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW3\r
+CYDEV_ANAIF_RT_SC1_SW3 EQU 0x40005a13\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW4\r
+CYDEV_ANAIF_RT_SC1_SW4 EQU 0x40005a14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW6\r
+CYDEV_ANAIF_RT_SC1_SW6 EQU 0x40005a16\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW7\r
+CYDEV_ANAIF_RT_SC1_SW7 EQU 0x40005a17\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW8\r
+CYDEV_ANAIF_RT_SC1_SW8 EQU 0x40005a18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW10\r
+CYDEV_ANAIF_RT_SC1_SW10 EQU 0x40005a1a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_CLK\r
+CYDEV_ANAIF_RT_SC1_CLK EQU 0x40005a1b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BST\r
+CYDEV_ANAIF_RT_SC1_BST EQU 0x40005a1c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BASE\r
+CYDEV_ANAIF_RT_SC2_BASE EQU 0x40005a20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SIZE\r
+CYDEV_ANAIF_RT_SC2_SIZE EQU 0x0000000d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW0\r
+CYDEV_ANAIF_RT_SC2_SW0 EQU 0x40005a20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW2\r
+CYDEV_ANAIF_RT_SC2_SW2 EQU 0x40005a22\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW3\r
+CYDEV_ANAIF_RT_SC2_SW3 EQU 0x40005a23\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW4\r
+CYDEV_ANAIF_RT_SC2_SW4 EQU 0x40005a24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW6\r
+CYDEV_ANAIF_RT_SC2_SW6 EQU 0x40005a26\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW7\r
+CYDEV_ANAIF_RT_SC2_SW7 EQU 0x40005a27\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW8\r
+CYDEV_ANAIF_RT_SC2_SW8 EQU 0x40005a28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW10\r
+CYDEV_ANAIF_RT_SC2_SW10 EQU 0x40005a2a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_CLK\r
+CYDEV_ANAIF_RT_SC2_CLK EQU 0x40005a2b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BST\r
+CYDEV_ANAIF_RT_SC2_BST EQU 0x40005a2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BASE\r
+CYDEV_ANAIF_RT_SC3_BASE EQU 0x40005a30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SIZE\r
+CYDEV_ANAIF_RT_SC3_SIZE EQU 0x0000000d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW0\r
+CYDEV_ANAIF_RT_SC3_SW0 EQU 0x40005a30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW2\r
+CYDEV_ANAIF_RT_SC3_SW2 EQU 0x40005a32\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW3\r
+CYDEV_ANAIF_RT_SC3_SW3 EQU 0x40005a33\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW4\r
+CYDEV_ANAIF_RT_SC3_SW4 EQU 0x40005a34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW6\r
+CYDEV_ANAIF_RT_SC3_SW6 EQU 0x40005a36\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW7\r
+CYDEV_ANAIF_RT_SC3_SW7 EQU 0x40005a37\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW8\r
+CYDEV_ANAIF_RT_SC3_SW8 EQU 0x40005a38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW10\r
+CYDEV_ANAIF_RT_SC3_SW10 EQU 0x40005a3a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_CLK\r
+CYDEV_ANAIF_RT_SC3_CLK EQU 0x40005a3b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BST\r
+CYDEV_ANAIF_RT_SC3_BST EQU 0x40005a3c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_BASE\r
+CYDEV_ANAIF_RT_DAC0_BASE EQU 0x40005a80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SIZE\r
+CYDEV_ANAIF_RT_DAC0_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW0\r
+CYDEV_ANAIF_RT_DAC0_SW0 EQU 0x40005a80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW2\r
+CYDEV_ANAIF_RT_DAC0_SW2 EQU 0x40005a82\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW3\r
+CYDEV_ANAIF_RT_DAC0_SW3 EQU 0x40005a83\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW4\r
+CYDEV_ANAIF_RT_DAC0_SW4 EQU 0x40005a84\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_STROBE\r
+CYDEV_ANAIF_RT_DAC0_STROBE EQU 0x40005a87\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_BASE\r
+CYDEV_ANAIF_RT_DAC1_BASE EQU 0x40005a88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SIZE\r
+CYDEV_ANAIF_RT_DAC1_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW0\r
+CYDEV_ANAIF_RT_DAC1_SW0 EQU 0x40005a88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW2\r
+CYDEV_ANAIF_RT_DAC1_SW2 EQU 0x40005a8a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW3\r
+CYDEV_ANAIF_RT_DAC1_SW3 EQU 0x40005a8b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW4\r
+CYDEV_ANAIF_RT_DAC1_SW4 EQU 0x40005a8c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_STROBE\r
+CYDEV_ANAIF_RT_DAC1_STROBE EQU 0x40005a8f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_BASE\r
+CYDEV_ANAIF_RT_DAC2_BASE EQU 0x40005a90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SIZE\r
+CYDEV_ANAIF_RT_DAC2_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW0\r
+CYDEV_ANAIF_RT_DAC2_SW0 EQU 0x40005a90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW2\r
+CYDEV_ANAIF_RT_DAC2_SW2 EQU 0x40005a92\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW3\r
+CYDEV_ANAIF_RT_DAC2_SW3 EQU 0x40005a93\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW4\r
+CYDEV_ANAIF_RT_DAC2_SW4 EQU 0x40005a94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_STROBE\r
+CYDEV_ANAIF_RT_DAC2_STROBE EQU 0x40005a97\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_BASE\r
+CYDEV_ANAIF_RT_DAC3_BASE EQU 0x40005a98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SIZE\r
+CYDEV_ANAIF_RT_DAC3_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW0\r
+CYDEV_ANAIF_RT_DAC3_SW0 EQU 0x40005a98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW2\r
+CYDEV_ANAIF_RT_DAC3_SW2 EQU 0x40005a9a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW3\r
+CYDEV_ANAIF_RT_DAC3_SW3 EQU 0x40005a9b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW4\r
+CYDEV_ANAIF_RT_DAC3_SW4 EQU 0x40005a9c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_STROBE\r
+CYDEV_ANAIF_RT_DAC3_STROBE EQU 0x40005a9f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_BASE\r
+CYDEV_ANAIF_RT_CMP0_BASE EQU 0x40005ac0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SIZE\r
+CYDEV_ANAIF_RT_CMP0_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW0\r
+CYDEV_ANAIF_RT_CMP0_SW0 EQU 0x40005ac0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW2\r
+CYDEV_ANAIF_RT_CMP0_SW2 EQU 0x40005ac2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW3\r
+CYDEV_ANAIF_RT_CMP0_SW3 EQU 0x40005ac3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW4\r
+CYDEV_ANAIF_RT_CMP0_SW4 EQU 0x40005ac4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW6\r
+CYDEV_ANAIF_RT_CMP0_SW6 EQU 0x40005ac6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_CLK\r
+CYDEV_ANAIF_RT_CMP0_CLK EQU 0x40005ac7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_BASE\r
+CYDEV_ANAIF_RT_CMP1_BASE EQU 0x40005ac8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SIZE\r
+CYDEV_ANAIF_RT_CMP1_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW0\r
+CYDEV_ANAIF_RT_CMP1_SW0 EQU 0x40005ac8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW2\r
+CYDEV_ANAIF_RT_CMP1_SW2 EQU 0x40005aca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW3\r
+CYDEV_ANAIF_RT_CMP1_SW3 EQU 0x40005acb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW4\r
+CYDEV_ANAIF_RT_CMP1_SW4 EQU 0x40005acc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW6\r
+CYDEV_ANAIF_RT_CMP1_SW6 EQU 0x40005ace\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_CLK\r
+CYDEV_ANAIF_RT_CMP1_CLK EQU 0x40005acf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_BASE\r
+CYDEV_ANAIF_RT_CMP2_BASE EQU 0x40005ad0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SIZE\r
+CYDEV_ANAIF_RT_CMP2_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW0\r
+CYDEV_ANAIF_RT_CMP2_SW0 EQU 0x40005ad0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW2\r
+CYDEV_ANAIF_RT_CMP2_SW2 EQU 0x40005ad2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW3\r
+CYDEV_ANAIF_RT_CMP2_SW3 EQU 0x40005ad3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW4\r
+CYDEV_ANAIF_RT_CMP2_SW4 EQU 0x40005ad4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW6\r
+CYDEV_ANAIF_RT_CMP2_SW6 EQU 0x40005ad6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_CLK\r
+CYDEV_ANAIF_RT_CMP2_CLK EQU 0x40005ad7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_BASE\r
+CYDEV_ANAIF_RT_CMP3_BASE EQU 0x40005ad8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SIZE\r
+CYDEV_ANAIF_RT_CMP3_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW0\r
+CYDEV_ANAIF_RT_CMP3_SW0 EQU 0x40005ad8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW2\r
+CYDEV_ANAIF_RT_CMP3_SW2 EQU 0x40005ada\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW3\r
+CYDEV_ANAIF_RT_CMP3_SW3 EQU 0x40005adb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW4\r
+CYDEV_ANAIF_RT_CMP3_SW4 EQU 0x40005adc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW6\r
+CYDEV_ANAIF_RT_CMP3_SW6 EQU 0x40005ade\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_CLK\r
+CYDEV_ANAIF_RT_CMP3_CLK EQU 0x40005adf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_BASE\r
+CYDEV_ANAIF_RT_DSM0_BASE EQU 0x40005b00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SIZE\r
+CYDEV_ANAIF_RT_DSM0_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW0\r
+CYDEV_ANAIF_RT_DSM0_SW0 EQU 0x40005b00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW2\r
+CYDEV_ANAIF_RT_DSM0_SW2 EQU 0x40005b02\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW3\r
+CYDEV_ANAIF_RT_DSM0_SW3 EQU 0x40005b03\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW4\r
+CYDEV_ANAIF_RT_DSM0_SW4 EQU 0x40005b04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW6\r
+CYDEV_ANAIF_RT_DSM0_SW6 EQU 0x40005b06\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_CLK\r
+CYDEV_ANAIF_RT_DSM0_CLK EQU 0x40005b07\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_BASE\r
+CYDEV_ANAIF_RT_SAR0_BASE EQU 0x40005b20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SIZE\r
+CYDEV_ANAIF_RT_SAR0_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW0\r
+CYDEV_ANAIF_RT_SAR0_SW0 EQU 0x40005b20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW2\r
+CYDEV_ANAIF_RT_SAR0_SW2 EQU 0x40005b22\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW3\r
+CYDEV_ANAIF_RT_SAR0_SW3 EQU 0x40005b23\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW4\r
+CYDEV_ANAIF_RT_SAR0_SW4 EQU 0x40005b24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW6\r
+CYDEV_ANAIF_RT_SAR0_SW6 EQU 0x40005b26\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_CLK\r
+CYDEV_ANAIF_RT_SAR0_CLK EQU 0x40005b27\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_BASE\r
+CYDEV_ANAIF_RT_SAR1_BASE EQU 0x40005b28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SIZE\r
+CYDEV_ANAIF_RT_SAR1_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW0\r
+CYDEV_ANAIF_RT_SAR1_SW0 EQU 0x40005b28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW2\r
+CYDEV_ANAIF_RT_SAR1_SW2 EQU 0x40005b2a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW3\r
+CYDEV_ANAIF_RT_SAR1_SW3 EQU 0x40005b2b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW4\r
+CYDEV_ANAIF_RT_SAR1_SW4 EQU 0x40005b2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW6\r
+CYDEV_ANAIF_RT_SAR1_SW6 EQU 0x40005b2e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_CLK\r
+CYDEV_ANAIF_RT_SAR1_CLK EQU 0x40005b2f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_BASE\r
+CYDEV_ANAIF_RT_OPAMP0_BASE EQU 0x40005b40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SIZE\r
+CYDEV_ANAIF_RT_OPAMP0_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_MX\r
+CYDEV_ANAIF_RT_OPAMP0_MX EQU 0x40005b40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SW\r
+CYDEV_ANAIF_RT_OPAMP0_SW EQU 0x40005b41\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_BASE\r
+CYDEV_ANAIF_RT_OPAMP1_BASE EQU 0x40005b42\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SIZE\r
+CYDEV_ANAIF_RT_OPAMP1_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_MX\r
+CYDEV_ANAIF_RT_OPAMP1_MX EQU 0x40005b42\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SW\r
+CYDEV_ANAIF_RT_OPAMP1_SW EQU 0x40005b43\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_BASE\r
+CYDEV_ANAIF_RT_OPAMP2_BASE EQU 0x40005b44\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SIZE\r
+CYDEV_ANAIF_RT_OPAMP2_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_MX\r
+CYDEV_ANAIF_RT_OPAMP2_MX EQU 0x40005b44\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SW\r
+CYDEV_ANAIF_RT_OPAMP2_SW EQU 0x40005b45\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_BASE\r
+CYDEV_ANAIF_RT_OPAMP3_BASE EQU 0x40005b46\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SIZE\r
+CYDEV_ANAIF_RT_OPAMP3_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_MX\r
+CYDEV_ANAIF_RT_OPAMP3_MX EQU 0x40005b46\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SW\r
+CYDEV_ANAIF_RT_OPAMP3_SW EQU 0x40005b47\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_BASE\r
+CYDEV_ANAIF_RT_LCDDAC_BASE EQU 0x40005b50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SIZE\r
+CYDEV_ANAIF_RT_LCDDAC_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW0\r
+CYDEV_ANAIF_RT_LCDDAC_SW0 EQU 0x40005b50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW1\r
+CYDEV_ANAIF_RT_LCDDAC_SW1 EQU 0x40005b51\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW2\r
+CYDEV_ANAIF_RT_LCDDAC_SW2 EQU 0x40005b52\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW3\r
+CYDEV_ANAIF_RT_LCDDAC_SW3 EQU 0x40005b53\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW4\r
+CYDEV_ANAIF_RT_LCDDAC_SW4 EQU 0x40005b54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_BASE\r
+CYDEV_ANAIF_RT_SC_BASE EQU 0x40005b56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_SIZE\r
+CYDEV_ANAIF_RT_SC_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_MISC\r
+CYDEV_ANAIF_RT_SC_MISC EQU 0x40005b56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_BASE\r
+CYDEV_ANAIF_RT_BUS_BASE EQU 0x40005b58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SIZE\r
+CYDEV_ANAIF_RT_BUS_SIZE EQU 0x00000004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW0\r
+CYDEV_ANAIF_RT_BUS_SW0 EQU 0x40005b58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW2\r
+CYDEV_ANAIF_RT_BUS_SW2 EQU 0x40005b5a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW3\r
+CYDEV_ANAIF_RT_BUS_SW3 EQU 0x40005b5b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_BASE\r
+CYDEV_ANAIF_RT_DFT_BASE EQU 0x40005b5c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_SIZE\r
+CYDEV_ANAIF_RT_DFT_SIZE EQU 0x00000006\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR0\r
+CYDEV_ANAIF_RT_DFT_CR0 EQU 0x40005b5c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR1\r
+CYDEV_ANAIF_RT_DFT_CR1 EQU 0x40005b5d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR2\r
+CYDEV_ANAIF_RT_DFT_CR2 EQU 0x40005b5e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR3\r
+CYDEV_ANAIF_RT_DFT_CR3 EQU 0x40005b5f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR4\r
+CYDEV_ANAIF_RT_DFT_CR4 EQU 0x40005b60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR5\r
+CYDEV_ANAIF_RT_DFT_CR5 EQU 0x40005b61\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_BASE\r
+CYDEV_ANAIF_WRK_BASE EQU 0x40005b80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SIZE\r
+CYDEV_ANAIF_WRK_SIZE EQU 0x00000029\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_BASE\r
+CYDEV_ANAIF_WRK_DAC0_BASE EQU 0x40005b80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_SIZE\r
+CYDEV_ANAIF_WRK_DAC0_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_D\r
+CYDEV_ANAIF_WRK_DAC0_D EQU 0x40005b80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_BASE\r
+CYDEV_ANAIF_WRK_DAC1_BASE EQU 0x40005b81\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_SIZE\r
+CYDEV_ANAIF_WRK_DAC1_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_D\r
+CYDEV_ANAIF_WRK_DAC1_D EQU 0x40005b81\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_BASE\r
+CYDEV_ANAIF_WRK_DAC2_BASE EQU 0x40005b82\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_SIZE\r
+CYDEV_ANAIF_WRK_DAC2_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_D\r
+CYDEV_ANAIF_WRK_DAC2_D EQU 0x40005b82\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_BASE\r
+CYDEV_ANAIF_WRK_DAC3_BASE EQU 0x40005b83\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_SIZE\r
+CYDEV_ANAIF_WRK_DAC3_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_D\r
+CYDEV_ANAIF_WRK_DAC3_D EQU 0x40005b83\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_BASE\r
+CYDEV_ANAIF_WRK_DSM0_BASE EQU 0x40005b88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_SIZE\r
+CYDEV_ANAIF_WRK_DSM0_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_OUT0\r
+CYDEV_ANAIF_WRK_DSM0_OUT0 EQU 0x40005b88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_OUT1\r
+CYDEV_ANAIF_WRK_DSM0_OUT1 EQU 0x40005b89\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_BASE\r
+CYDEV_ANAIF_WRK_LUT_BASE EQU 0x40005b90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SIZE\r
+CYDEV_ANAIF_WRK_LUT_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SR\r
+CYDEV_ANAIF_WRK_LUT_SR EQU 0x40005b90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_WRK1\r
+CYDEV_ANAIF_WRK_LUT_WRK1 EQU 0x40005b91\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_MSK\r
+CYDEV_ANAIF_WRK_LUT_MSK EQU 0x40005b92\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_CLK\r
+CYDEV_ANAIF_WRK_LUT_CLK EQU 0x40005b93\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_CPTR\r
+CYDEV_ANAIF_WRK_LUT_CPTR EQU 0x40005b94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_BASE\r
+CYDEV_ANAIF_WRK_CMP_BASE EQU 0x40005b96\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_SIZE\r
+CYDEV_ANAIF_WRK_CMP_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_WRK\r
+CYDEV_ANAIF_WRK_CMP_WRK EQU 0x40005b96\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_TST\r
+CYDEV_ANAIF_WRK_CMP_TST EQU 0x40005b97\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_BASE\r
+CYDEV_ANAIF_WRK_SC_BASE EQU 0x40005b98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SIZE\r
+CYDEV_ANAIF_WRK_SC_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SR\r
+CYDEV_ANAIF_WRK_SC_SR EQU 0x40005b98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_WRK1\r
+CYDEV_ANAIF_WRK_SC_WRK1 EQU 0x40005b99\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_MSK\r
+CYDEV_ANAIF_WRK_SC_MSK EQU 0x40005b9a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_CMPINV\r
+CYDEV_ANAIF_WRK_SC_CMPINV EQU 0x40005b9b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_CPTR\r
+CYDEV_ANAIF_WRK_SC_CPTR EQU 0x40005b9c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_BASE\r
+CYDEV_ANAIF_WRK_SAR0_BASE EQU 0x40005ba0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_SIZE\r
+CYDEV_ANAIF_WRK_SAR0_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_WRK0\r
+CYDEV_ANAIF_WRK_SAR0_WRK0 EQU 0x40005ba0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_WRK1\r
+CYDEV_ANAIF_WRK_SAR0_WRK1 EQU 0x40005ba1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_BASE\r
+CYDEV_ANAIF_WRK_SAR1_BASE EQU 0x40005ba2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_SIZE\r
+CYDEV_ANAIF_WRK_SAR1_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_WRK0\r
+CYDEV_ANAIF_WRK_SAR1_WRK0 EQU 0x40005ba2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_WRK1\r
+CYDEV_ANAIF_WRK_SAR1_WRK1 EQU 0x40005ba3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_BASE\r
+CYDEV_ANAIF_WRK_SARS_BASE EQU 0x40005ba8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SIZE\r
+CYDEV_ANAIF_WRK_SARS_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SOF\r
+CYDEV_ANAIF_WRK_SARS_SOF EQU 0x40005ba8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_BASE\r
+CYDEV_USB_BASE EQU 0x40006000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIZE\r
+CYDEV_USB_SIZE EQU 0x00000300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_EP0_DR0\r
+CYDEV_USB_EP0_DR0 EQU 0x40006000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_EP0_DR1\r
+CYDEV_USB_EP0_DR1 EQU 0x40006001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_EP0_DR2\r
+CYDEV_USB_EP0_DR2 EQU 0x40006002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_EP0_DR3\r
+CYDEV_USB_EP0_DR3 EQU 0x40006003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_EP0_DR4\r
+CYDEV_USB_EP0_DR4 EQU 0x40006004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_EP0_DR5\r
+CYDEV_USB_EP0_DR5 EQU 0x40006005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_EP0_DR6\r
+CYDEV_USB_EP0_DR6 EQU 0x40006006\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_EP0_DR7\r
+CYDEV_USB_EP0_DR7 EQU 0x40006007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_CR0\r
+CYDEV_USB_CR0 EQU 0x40006008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_CR1\r
+CYDEV_USB_CR1 EQU 0x40006009\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP_INT_EN\r
+CYDEV_USB_SIE_EP_INT_EN EQU 0x4000600a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP_INT_SR\r
+CYDEV_USB_SIE_EP_INT_SR EQU 0x4000600b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP1_BASE\r
+CYDEV_USB_SIE_EP1_BASE EQU 0x4000600c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP1_SIZE\r
+CYDEV_USB_SIE_EP1_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CNT0\r
+CYDEV_USB_SIE_EP1_CNT0 EQU 0x4000600c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CNT1\r
+CYDEV_USB_SIE_EP1_CNT1 EQU 0x4000600d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CR0\r
+CYDEV_USB_SIE_EP1_CR0 EQU 0x4000600e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_USBIO_CR0\r
+CYDEV_USB_USBIO_CR0 EQU 0x40006010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_USBIO_CR1\r
+CYDEV_USB_USBIO_CR1 EQU 0x40006012\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_DYN_RECONFIG\r
+CYDEV_USB_DYN_RECONFIG EQU 0x40006014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SOF0\r
+CYDEV_USB_SOF0 EQU 0x40006018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SOF1\r
+CYDEV_USB_SOF1 EQU 0x40006019\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP2_BASE\r
+CYDEV_USB_SIE_EP2_BASE EQU 0x4000601c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP2_SIZE\r
+CYDEV_USB_SIE_EP2_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CNT0\r
+CYDEV_USB_SIE_EP2_CNT0 EQU 0x4000601c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CNT1\r
+CYDEV_USB_SIE_EP2_CNT1 EQU 0x4000601d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CR0\r
+CYDEV_USB_SIE_EP2_CR0 EQU 0x4000601e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_EP0_CR\r
+CYDEV_USB_EP0_CR EQU 0x40006028\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_EP0_CNT\r
+CYDEV_USB_EP0_CNT EQU 0x40006029\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP3_BASE\r
+CYDEV_USB_SIE_EP3_BASE EQU 0x4000602c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP3_SIZE\r
+CYDEV_USB_SIE_EP3_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CNT0\r
+CYDEV_USB_SIE_EP3_CNT0 EQU 0x4000602c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CNT1\r
+CYDEV_USB_SIE_EP3_CNT1 EQU 0x4000602d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CR0\r
+CYDEV_USB_SIE_EP3_CR0 EQU 0x4000602e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP4_BASE\r
+CYDEV_USB_SIE_EP4_BASE EQU 0x4000603c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP4_SIZE\r
+CYDEV_USB_SIE_EP4_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CNT0\r
+CYDEV_USB_SIE_EP4_CNT0 EQU 0x4000603c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CNT1\r
+CYDEV_USB_SIE_EP4_CNT1 EQU 0x4000603d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CR0\r
+CYDEV_USB_SIE_EP4_CR0 EQU 0x4000603e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP5_BASE\r
+CYDEV_USB_SIE_EP5_BASE EQU 0x4000604c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP5_SIZE\r
+CYDEV_USB_SIE_EP5_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CNT0\r
+CYDEV_USB_SIE_EP5_CNT0 EQU 0x4000604c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CNT1\r
+CYDEV_USB_SIE_EP5_CNT1 EQU 0x4000604d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CR0\r
+CYDEV_USB_SIE_EP5_CR0 EQU 0x4000604e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP6_BASE\r
+CYDEV_USB_SIE_EP6_BASE EQU 0x4000605c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP6_SIZE\r
+CYDEV_USB_SIE_EP6_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CNT0\r
+CYDEV_USB_SIE_EP6_CNT0 EQU 0x4000605c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CNT1\r
+CYDEV_USB_SIE_EP6_CNT1 EQU 0x4000605d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CR0\r
+CYDEV_USB_SIE_EP6_CR0 EQU 0x4000605e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP7_BASE\r
+CYDEV_USB_SIE_EP7_BASE EQU 0x4000606c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP7_SIZE\r
+CYDEV_USB_SIE_EP7_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CNT0\r
+CYDEV_USB_SIE_EP7_CNT0 EQU 0x4000606c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CNT1\r
+CYDEV_USB_SIE_EP7_CNT1 EQU 0x4000606d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CR0\r
+CYDEV_USB_SIE_EP7_CR0 EQU 0x4000606e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP8_BASE\r
+CYDEV_USB_SIE_EP8_BASE EQU 0x4000607c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP8_SIZE\r
+CYDEV_USB_SIE_EP8_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CNT0\r
+CYDEV_USB_SIE_EP8_CNT0 EQU 0x4000607c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CNT1\r
+CYDEV_USB_SIE_EP8_CNT1 EQU 0x4000607d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CR0\r
+CYDEV_USB_SIE_EP8_CR0 EQU 0x4000607e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP1_BASE\r
+CYDEV_USB_ARB_EP1_BASE EQU 0x40006080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SIZE\r
+CYDEV_USB_ARB_EP1_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP1_CFG\r
+CYDEV_USB_ARB_EP1_CFG EQU 0x40006080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP1_INT_EN\r
+CYDEV_USB_ARB_EP1_INT_EN EQU 0x40006081\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SR\r
+CYDEV_USB_ARB_EP1_SR EQU 0x40006082\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW1_BASE\r
+CYDEV_USB_ARB_RW1_BASE EQU 0x40006084\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW1_SIZE\r
+CYDEV_USB_ARB_RW1_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW1_WA\r
+CYDEV_USB_ARB_RW1_WA EQU 0x40006084\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW1_WA_MSB\r
+CYDEV_USB_ARB_RW1_WA_MSB EQU 0x40006085\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW1_RA\r
+CYDEV_USB_ARB_RW1_RA EQU 0x40006086\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW1_RA_MSB\r
+CYDEV_USB_ARB_RW1_RA_MSB EQU 0x40006087\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW1_DR\r
+CYDEV_USB_ARB_RW1_DR EQU 0x40006088\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_BUF_SIZE\r
+CYDEV_USB_BUF_SIZE EQU 0x4000608c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_EP_ACTIVE\r
+CYDEV_USB_EP_ACTIVE EQU 0x4000608e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_EP_TYPE\r
+CYDEV_USB_EP_TYPE EQU 0x4000608f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP2_BASE\r
+CYDEV_USB_ARB_EP2_BASE EQU 0x40006090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SIZE\r
+CYDEV_USB_ARB_EP2_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP2_CFG\r
+CYDEV_USB_ARB_EP2_CFG EQU 0x40006090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP2_INT_EN\r
+CYDEV_USB_ARB_EP2_INT_EN EQU 0x40006091\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SR\r
+CYDEV_USB_ARB_EP2_SR EQU 0x40006092\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW2_BASE\r
+CYDEV_USB_ARB_RW2_BASE EQU 0x40006094\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW2_SIZE\r
+CYDEV_USB_ARB_RW2_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW2_WA\r
+CYDEV_USB_ARB_RW2_WA EQU 0x40006094\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW2_WA_MSB\r
+CYDEV_USB_ARB_RW2_WA_MSB EQU 0x40006095\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW2_RA\r
+CYDEV_USB_ARB_RW2_RA EQU 0x40006096\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW2_RA_MSB\r
+CYDEV_USB_ARB_RW2_RA_MSB EQU 0x40006097\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW2_DR\r
+CYDEV_USB_ARB_RW2_DR EQU 0x40006098\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_CFG\r
+CYDEV_USB_ARB_CFG EQU 0x4000609c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_USB_CLK_EN\r
+CYDEV_USB_USB_CLK_EN EQU 0x4000609d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_INT_EN\r
+CYDEV_USB_ARB_INT_EN EQU 0x4000609e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_INT_SR\r
+CYDEV_USB_ARB_INT_SR EQU 0x4000609f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP3_BASE\r
+CYDEV_USB_ARB_EP3_BASE EQU 0x400060a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SIZE\r
+CYDEV_USB_ARB_EP3_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP3_CFG\r
+CYDEV_USB_ARB_EP3_CFG EQU 0x400060a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP3_INT_EN\r
+CYDEV_USB_ARB_EP3_INT_EN EQU 0x400060a1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SR\r
+CYDEV_USB_ARB_EP3_SR EQU 0x400060a2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW3_BASE\r
+CYDEV_USB_ARB_RW3_BASE EQU 0x400060a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW3_SIZE\r
+CYDEV_USB_ARB_RW3_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW3_WA\r
+CYDEV_USB_ARB_RW3_WA EQU 0x400060a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW3_WA_MSB\r
+CYDEV_USB_ARB_RW3_WA_MSB EQU 0x400060a5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW3_RA\r
+CYDEV_USB_ARB_RW3_RA EQU 0x400060a6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW3_RA_MSB\r
+CYDEV_USB_ARB_RW3_RA_MSB EQU 0x400060a7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW3_DR\r
+CYDEV_USB_ARB_RW3_DR EQU 0x400060a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_CWA\r
+CYDEV_USB_CWA EQU 0x400060ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_CWA_MSB\r
+CYDEV_USB_CWA_MSB EQU 0x400060ad\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP4_BASE\r
+CYDEV_USB_ARB_EP4_BASE EQU 0x400060b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SIZE\r
+CYDEV_USB_ARB_EP4_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP4_CFG\r
+CYDEV_USB_ARB_EP4_CFG EQU 0x400060b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP4_INT_EN\r
+CYDEV_USB_ARB_EP4_INT_EN EQU 0x400060b1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SR\r
+CYDEV_USB_ARB_EP4_SR EQU 0x400060b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW4_BASE\r
+CYDEV_USB_ARB_RW4_BASE EQU 0x400060b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW4_SIZE\r
+CYDEV_USB_ARB_RW4_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW4_WA\r
+CYDEV_USB_ARB_RW4_WA EQU 0x400060b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW4_WA_MSB\r
+CYDEV_USB_ARB_RW4_WA_MSB EQU 0x400060b5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW4_RA\r
+CYDEV_USB_ARB_RW4_RA EQU 0x400060b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW4_RA_MSB\r
+CYDEV_USB_ARB_RW4_RA_MSB EQU 0x400060b7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW4_DR\r
+CYDEV_USB_ARB_RW4_DR EQU 0x400060b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_DMA_THRES\r
+CYDEV_USB_DMA_THRES EQU 0x400060bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_DMA_THRES_MSB\r
+CYDEV_USB_DMA_THRES_MSB EQU 0x400060bd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP5_BASE\r
+CYDEV_USB_ARB_EP5_BASE EQU 0x400060c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SIZE\r
+CYDEV_USB_ARB_EP5_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP5_CFG\r
+CYDEV_USB_ARB_EP5_CFG EQU 0x400060c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP5_INT_EN\r
+CYDEV_USB_ARB_EP5_INT_EN EQU 0x400060c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SR\r
+CYDEV_USB_ARB_EP5_SR EQU 0x400060c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW5_BASE\r
+CYDEV_USB_ARB_RW5_BASE EQU 0x400060c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW5_SIZE\r
+CYDEV_USB_ARB_RW5_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW5_WA\r
+CYDEV_USB_ARB_RW5_WA EQU 0x400060c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW5_WA_MSB\r
+CYDEV_USB_ARB_RW5_WA_MSB EQU 0x400060c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW5_RA\r
+CYDEV_USB_ARB_RW5_RA EQU 0x400060c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW5_RA_MSB\r
+CYDEV_USB_ARB_RW5_RA_MSB EQU 0x400060c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW5_DR\r
+CYDEV_USB_ARB_RW5_DR EQU 0x400060c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_BUS_RST_CNT\r
+CYDEV_USB_BUS_RST_CNT EQU 0x400060cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP6_BASE\r
+CYDEV_USB_ARB_EP6_BASE EQU 0x400060d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SIZE\r
+CYDEV_USB_ARB_EP6_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP6_CFG\r
+CYDEV_USB_ARB_EP6_CFG EQU 0x400060d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP6_INT_EN\r
+CYDEV_USB_ARB_EP6_INT_EN EQU 0x400060d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SR\r
+CYDEV_USB_ARB_EP6_SR EQU 0x400060d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW6_BASE\r
+CYDEV_USB_ARB_RW6_BASE EQU 0x400060d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW6_SIZE\r
+CYDEV_USB_ARB_RW6_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW6_WA\r
+CYDEV_USB_ARB_RW6_WA EQU 0x400060d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW6_WA_MSB\r
+CYDEV_USB_ARB_RW6_WA_MSB EQU 0x400060d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW6_RA\r
+CYDEV_USB_ARB_RW6_RA EQU 0x400060d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW6_RA_MSB\r
+CYDEV_USB_ARB_RW6_RA_MSB EQU 0x400060d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW6_DR\r
+CYDEV_USB_ARB_RW6_DR EQU 0x400060d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP7_BASE\r
+CYDEV_USB_ARB_EP7_BASE EQU 0x400060e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SIZE\r
+CYDEV_USB_ARB_EP7_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP7_CFG\r
+CYDEV_USB_ARB_EP7_CFG EQU 0x400060e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP7_INT_EN\r
+CYDEV_USB_ARB_EP7_INT_EN EQU 0x400060e1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SR\r
+CYDEV_USB_ARB_EP7_SR EQU 0x400060e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW7_BASE\r
+CYDEV_USB_ARB_RW7_BASE EQU 0x400060e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW7_SIZE\r
+CYDEV_USB_ARB_RW7_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW7_WA\r
+CYDEV_USB_ARB_RW7_WA EQU 0x400060e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW7_WA_MSB\r
+CYDEV_USB_ARB_RW7_WA_MSB EQU 0x400060e5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW7_RA\r
+CYDEV_USB_ARB_RW7_RA EQU 0x400060e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW7_RA_MSB\r
+CYDEV_USB_ARB_RW7_RA_MSB EQU 0x400060e7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW7_DR\r
+CYDEV_USB_ARB_RW7_DR EQU 0x400060e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP8_BASE\r
+CYDEV_USB_ARB_EP8_BASE EQU 0x400060f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SIZE\r
+CYDEV_USB_ARB_EP8_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP8_CFG\r
+CYDEV_USB_ARB_EP8_CFG EQU 0x400060f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP8_INT_EN\r
+CYDEV_USB_ARB_EP8_INT_EN EQU 0x400060f1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SR\r
+CYDEV_USB_ARB_EP8_SR EQU 0x400060f2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW8_BASE\r
+CYDEV_USB_ARB_RW8_BASE EQU 0x400060f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW8_SIZE\r
+CYDEV_USB_ARB_RW8_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW8_WA\r
+CYDEV_USB_ARB_RW8_WA EQU 0x400060f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW8_WA_MSB\r
+CYDEV_USB_ARB_RW8_WA_MSB EQU 0x400060f5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW8_RA\r
+CYDEV_USB_ARB_RW8_RA EQU 0x400060f6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW8_RA_MSB\r
+CYDEV_USB_ARB_RW8_RA_MSB EQU 0x400060f7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW8_DR\r
+CYDEV_USB_ARB_RW8_DR EQU 0x400060f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_MEM_BASE\r
+CYDEV_USB_MEM_BASE EQU 0x40006100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_MEM_SIZE\r
+CYDEV_USB_MEM_SIZE EQU 0x00000200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_MEM_DATA_MBASE\r
+CYDEV_USB_MEM_DATA_MBASE EQU 0x40006100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_MEM_DATA_MSIZE\r
+CYDEV_USB_MEM_DATA_MSIZE EQU 0x00000200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_BASE\r
+CYDEV_UWRK_BASE EQU 0x40006400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_SIZE\r
+CYDEV_UWRK_SIZE EQU 0x00000b60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_BASE\r
+CYDEV_UWRK_UWRK8_BASE EQU 0x40006400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_SIZE\r
+CYDEV_UWRK_UWRK8_SIZE EQU 0x000003b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_BASE\r
+CYDEV_UWRK_UWRK8_B0_BASE EQU 0x40006400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_SIZE\r
+CYDEV_UWRK_UWRK8_B0_SIZE EQU 0x000000b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_A0\r
+CYDEV_UWRK_UWRK8_B0_UDB00_A0 EQU 0x40006400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_A0\r
+CYDEV_UWRK_UWRK8_B0_UDB01_A0 EQU 0x40006401\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_A0\r
+CYDEV_UWRK_UWRK8_B0_UDB02_A0 EQU 0x40006402\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_A0\r
+CYDEV_UWRK_UWRK8_B0_UDB03_A0 EQU 0x40006403\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_A0\r
+CYDEV_UWRK_UWRK8_B0_UDB04_A0 EQU 0x40006404\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_A0\r
+CYDEV_UWRK_UWRK8_B0_UDB05_A0 EQU 0x40006405\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_A0\r
+CYDEV_UWRK_UWRK8_B0_UDB06_A0 EQU 0x40006406\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_A0\r
+CYDEV_UWRK_UWRK8_B0_UDB07_A0 EQU 0x40006407\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_A0\r
+CYDEV_UWRK_UWRK8_B0_UDB08_A0 EQU 0x40006408\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_A0\r
+CYDEV_UWRK_UWRK8_B0_UDB09_A0 EQU 0x40006409\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_A0\r
+CYDEV_UWRK_UWRK8_B0_UDB10_A0 EQU 0x4000640a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_A0\r
+CYDEV_UWRK_UWRK8_B0_UDB11_A0 EQU 0x4000640b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_A0\r
+CYDEV_UWRK_UWRK8_B0_UDB12_A0 EQU 0x4000640c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_A0\r
+CYDEV_UWRK_UWRK8_B0_UDB13_A0 EQU 0x4000640d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_A0\r
+CYDEV_UWRK_UWRK8_B0_UDB14_A0 EQU 0x4000640e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_A0\r
+CYDEV_UWRK_UWRK8_B0_UDB15_A0 EQU 0x4000640f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_A1\r
+CYDEV_UWRK_UWRK8_B0_UDB00_A1 EQU 0x40006410\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_A1\r
+CYDEV_UWRK_UWRK8_B0_UDB01_A1 EQU 0x40006411\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_A1\r
+CYDEV_UWRK_UWRK8_B0_UDB02_A1 EQU 0x40006412\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_A1\r
+CYDEV_UWRK_UWRK8_B0_UDB03_A1 EQU 0x40006413\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_A1\r
+CYDEV_UWRK_UWRK8_B0_UDB04_A1 EQU 0x40006414\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_A1\r
+CYDEV_UWRK_UWRK8_B0_UDB05_A1 EQU 0x40006415\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_A1\r
+CYDEV_UWRK_UWRK8_B0_UDB06_A1 EQU 0x40006416\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_A1\r
+CYDEV_UWRK_UWRK8_B0_UDB07_A1 EQU 0x40006417\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_A1\r
+CYDEV_UWRK_UWRK8_B0_UDB08_A1 EQU 0x40006418\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_A1\r
+CYDEV_UWRK_UWRK8_B0_UDB09_A1 EQU 0x40006419\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_A1\r
+CYDEV_UWRK_UWRK8_B0_UDB10_A1 EQU 0x4000641a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_A1\r
+CYDEV_UWRK_UWRK8_B0_UDB11_A1 EQU 0x4000641b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_A1\r
+CYDEV_UWRK_UWRK8_B0_UDB12_A1 EQU 0x4000641c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_A1\r
+CYDEV_UWRK_UWRK8_B0_UDB13_A1 EQU 0x4000641d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_A1\r
+CYDEV_UWRK_UWRK8_B0_UDB14_A1 EQU 0x4000641e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_A1\r
+CYDEV_UWRK_UWRK8_B0_UDB15_A1 EQU 0x4000641f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_D0\r
+CYDEV_UWRK_UWRK8_B0_UDB00_D0 EQU 0x40006420\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_D0\r
+CYDEV_UWRK_UWRK8_B0_UDB01_D0 EQU 0x40006421\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_D0\r
+CYDEV_UWRK_UWRK8_B0_UDB02_D0 EQU 0x40006422\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_D0\r
+CYDEV_UWRK_UWRK8_B0_UDB03_D0 EQU 0x40006423\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_D0\r
+CYDEV_UWRK_UWRK8_B0_UDB04_D0 EQU 0x40006424\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_D0\r
+CYDEV_UWRK_UWRK8_B0_UDB05_D0 EQU 0x40006425\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_D0\r
+CYDEV_UWRK_UWRK8_B0_UDB06_D0 EQU 0x40006426\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_D0\r
+CYDEV_UWRK_UWRK8_B0_UDB07_D0 EQU 0x40006427\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_D0\r
+CYDEV_UWRK_UWRK8_B0_UDB08_D0 EQU 0x40006428\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_D0\r
+CYDEV_UWRK_UWRK8_B0_UDB09_D0 EQU 0x40006429\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_D0\r
+CYDEV_UWRK_UWRK8_B0_UDB10_D0 EQU 0x4000642a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_D0\r
+CYDEV_UWRK_UWRK8_B0_UDB11_D0 EQU 0x4000642b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_D0\r
+CYDEV_UWRK_UWRK8_B0_UDB12_D0 EQU 0x4000642c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_D0\r
+CYDEV_UWRK_UWRK8_B0_UDB13_D0 EQU 0x4000642d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_D0\r
+CYDEV_UWRK_UWRK8_B0_UDB14_D0 EQU 0x4000642e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_D0\r
+CYDEV_UWRK_UWRK8_B0_UDB15_D0 EQU 0x4000642f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_D1\r
+CYDEV_UWRK_UWRK8_B0_UDB00_D1 EQU 0x40006430\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_D1\r
+CYDEV_UWRK_UWRK8_B0_UDB01_D1 EQU 0x40006431\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_D1\r
+CYDEV_UWRK_UWRK8_B0_UDB02_D1 EQU 0x40006432\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_D1\r
+CYDEV_UWRK_UWRK8_B0_UDB03_D1 EQU 0x40006433\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_D1\r
+CYDEV_UWRK_UWRK8_B0_UDB04_D1 EQU 0x40006434\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_D1\r
+CYDEV_UWRK_UWRK8_B0_UDB05_D1 EQU 0x40006435\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_D1\r
+CYDEV_UWRK_UWRK8_B0_UDB06_D1 EQU 0x40006436\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_D1\r
+CYDEV_UWRK_UWRK8_B0_UDB07_D1 EQU 0x40006437\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_D1\r
+CYDEV_UWRK_UWRK8_B0_UDB08_D1 EQU 0x40006438\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_D1\r
+CYDEV_UWRK_UWRK8_B0_UDB09_D1 EQU 0x40006439\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_D1\r
+CYDEV_UWRK_UWRK8_B0_UDB10_D1 EQU 0x4000643a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_D1\r
+CYDEV_UWRK_UWRK8_B0_UDB11_D1 EQU 0x4000643b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_D1\r
+CYDEV_UWRK_UWRK8_B0_UDB12_D1 EQU 0x4000643c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_D1\r
+CYDEV_UWRK_UWRK8_B0_UDB13_D1 EQU 0x4000643d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_D1\r
+CYDEV_UWRK_UWRK8_B0_UDB14_D1 EQU 0x4000643e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_D1\r
+CYDEV_UWRK_UWRK8_B0_UDB15_D1 EQU 0x4000643f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_F0\r
+CYDEV_UWRK_UWRK8_B0_UDB00_F0 EQU 0x40006440\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_F0\r
+CYDEV_UWRK_UWRK8_B0_UDB01_F0 EQU 0x40006441\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_F0\r
+CYDEV_UWRK_UWRK8_B0_UDB02_F0 EQU 0x40006442\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_F0\r
+CYDEV_UWRK_UWRK8_B0_UDB03_F0 EQU 0x40006443\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_F0\r
+CYDEV_UWRK_UWRK8_B0_UDB04_F0 EQU 0x40006444\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_F0\r
+CYDEV_UWRK_UWRK8_B0_UDB05_F0 EQU 0x40006445\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_F0\r
+CYDEV_UWRK_UWRK8_B0_UDB06_F0 EQU 0x40006446\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_F0\r
+CYDEV_UWRK_UWRK8_B0_UDB07_F0 EQU 0x40006447\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_F0\r
+CYDEV_UWRK_UWRK8_B0_UDB08_F0 EQU 0x40006448\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_F0\r
+CYDEV_UWRK_UWRK8_B0_UDB09_F0 EQU 0x40006449\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_F0\r
+CYDEV_UWRK_UWRK8_B0_UDB10_F0 EQU 0x4000644a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_F0\r
+CYDEV_UWRK_UWRK8_B0_UDB11_F0 EQU 0x4000644b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_F0\r
+CYDEV_UWRK_UWRK8_B0_UDB12_F0 EQU 0x4000644c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_F0\r
+CYDEV_UWRK_UWRK8_B0_UDB13_F0 EQU 0x4000644d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_F0\r
+CYDEV_UWRK_UWRK8_B0_UDB14_F0 EQU 0x4000644e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_F0\r
+CYDEV_UWRK_UWRK8_B0_UDB15_F0 EQU 0x4000644f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_F1\r
+CYDEV_UWRK_UWRK8_B0_UDB00_F1 EQU 0x40006450\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_F1\r
+CYDEV_UWRK_UWRK8_B0_UDB01_F1 EQU 0x40006451\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_F1\r
+CYDEV_UWRK_UWRK8_B0_UDB02_F1 EQU 0x40006452\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_F1\r
+CYDEV_UWRK_UWRK8_B0_UDB03_F1 EQU 0x40006453\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_F1\r
+CYDEV_UWRK_UWRK8_B0_UDB04_F1 EQU 0x40006454\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_F1\r
+CYDEV_UWRK_UWRK8_B0_UDB05_F1 EQU 0x40006455\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_F1\r
+CYDEV_UWRK_UWRK8_B0_UDB06_F1 EQU 0x40006456\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_F1\r
+CYDEV_UWRK_UWRK8_B0_UDB07_F1 EQU 0x40006457\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_F1\r
+CYDEV_UWRK_UWRK8_B0_UDB08_F1 EQU 0x40006458\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_F1\r
+CYDEV_UWRK_UWRK8_B0_UDB09_F1 EQU 0x40006459\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_F1\r
+CYDEV_UWRK_UWRK8_B0_UDB10_F1 EQU 0x4000645a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_F1\r
+CYDEV_UWRK_UWRK8_B0_UDB11_F1 EQU 0x4000645b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_F1\r
+CYDEV_UWRK_UWRK8_B0_UDB12_F1 EQU 0x4000645c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_F1\r
+CYDEV_UWRK_UWRK8_B0_UDB13_F1 EQU 0x4000645d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_F1\r
+CYDEV_UWRK_UWRK8_B0_UDB14_F1 EQU 0x4000645e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_F1\r
+CYDEV_UWRK_UWRK8_B0_UDB15_F1 EQU 0x4000645f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_ST\r
+CYDEV_UWRK_UWRK8_B0_UDB00_ST EQU 0x40006460\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_ST\r
+CYDEV_UWRK_UWRK8_B0_UDB01_ST EQU 0x40006461\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_ST\r
+CYDEV_UWRK_UWRK8_B0_UDB02_ST EQU 0x40006462\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_ST\r
+CYDEV_UWRK_UWRK8_B0_UDB03_ST EQU 0x40006463\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_ST\r
+CYDEV_UWRK_UWRK8_B0_UDB04_ST EQU 0x40006464\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_ST\r
+CYDEV_UWRK_UWRK8_B0_UDB05_ST EQU 0x40006465\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_ST\r
+CYDEV_UWRK_UWRK8_B0_UDB06_ST EQU 0x40006466\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_ST\r
+CYDEV_UWRK_UWRK8_B0_UDB07_ST EQU 0x40006467\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_ST\r
+CYDEV_UWRK_UWRK8_B0_UDB08_ST EQU 0x40006468\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_ST\r
+CYDEV_UWRK_UWRK8_B0_UDB09_ST EQU 0x40006469\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_ST\r
+CYDEV_UWRK_UWRK8_B0_UDB10_ST EQU 0x4000646a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_ST\r
+CYDEV_UWRK_UWRK8_B0_UDB11_ST EQU 0x4000646b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_ST\r
+CYDEV_UWRK_UWRK8_B0_UDB12_ST EQU 0x4000646c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_ST\r
+CYDEV_UWRK_UWRK8_B0_UDB13_ST EQU 0x4000646d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_ST\r
+CYDEV_UWRK_UWRK8_B0_UDB14_ST EQU 0x4000646e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_ST\r
+CYDEV_UWRK_UWRK8_B0_UDB15_ST EQU 0x4000646f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_CTL\r
+CYDEV_UWRK_UWRK8_B0_UDB00_CTL EQU 0x40006470\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_CTL\r
+CYDEV_UWRK_UWRK8_B0_UDB01_CTL EQU 0x40006471\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_CTL\r
+CYDEV_UWRK_UWRK8_B0_UDB02_CTL EQU 0x40006472\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_CTL\r
+CYDEV_UWRK_UWRK8_B0_UDB03_CTL EQU 0x40006473\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_CTL\r
+CYDEV_UWRK_UWRK8_B0_UDB04_CTL EQU 0x40006474\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_CTL\r
+CYDEV_UWRK_UWRK8_B0_UDB05_CTL EQU 0x40006475\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_CTL\r
+CYDEV_UWRK_UWRK8_B0_UDB06_CTL EQU 0x40006476\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_CTL\r
+CYDEV_UWRK_UWRK8_B0_UDB07_CTL EQU 0x40006477\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_CTL\r
+CYDEV_UWRK_UWRK8_B0_UDB08_CTL EQU 0x40006478\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_CTL\r
+CYDEV_UWRK_UWRK8_B0_UDB09_CTL EQU 0x40006479\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_CTL\r
+CYDEV_UWRK_UWRK8_B0_UDB10_CTL EQU 0x4000647a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_CTL\r
+CYDEV_UWRK_UWRK8_B0_UDB11_CTL EQU 0x4000647b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_CTL\r
+CYDEV_UWRK_UWRK8_B0_UDB12_CTL EQU 0x4000647c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_CTL\r
+CYDEV_UWRK_UWRK8_B0_UDB13_CTL EQU 0x4000647d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_CTL\r
+CYDEV_UWRK_UWRK8_B0_UDB14_CTL EQU 0x4000647e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_CTL\r
+CYDEV_UWRK_UWRK8_B0_UDB15_CTL EQU 0x4000647f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_MSK\r
+CYDEV_UWRK_UWRK8_B0_UDB00_MSK EQU 0x40006480\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_MSK\r
+CYDEV_UWRK_UWRK8_B0_UDB01_MSK EQU 0x40006481\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_MSK\r
+CYDEV_UWRK_UWRK8_B0_UDB02_MSK EQU 0x40006482\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_MSK\r
+CYDEV_UWRK_UWRK8_B0_UDB03_MSK EQU 0x40006483\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_MSK\r
+CYDEV_UWRK_UWRK8_B0_UDB04_MSK EQU 0x40006484\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_MSK\r
+CYDEV_UWRK_UWRK8_B0_UDB05_MSK EQU 0x40006485\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_MSK\r
+CYDEV_UWRK_UWRK8_B0_UDB06_MSK EQU 0x40006486\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_MSK\r
+CYDEV_UWRK_UWRK8_B0_UDB07_MSK EQU 0x40006487\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_MSK\r
+CYDEV_UWRK_UWRK8_B0_UDB08_MSK EQU 0x40006488\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_MSK\r
+CYDEV_UWRK_UWRK8_B0_UDB09_MSK EQU 0x40006489\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_MSK\r
+CYDEV_UWRK_UWRK8_B0_UDB10_MSK EQU 0x4000648a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_MSK\r
+CYDEV_UWRK_UWRK8_B0_UDB11_MSK EQU 0x4000648b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_MSK\r
+CYDEV_UWRK_UWRK8_B0_UDB12_MSK EQU 0x4000648c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_MSK\r
+CYDEV_UWRK_UWRK8_B0_UDB13_MSK EQU 0x4000648d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_MSK\r
+CYDEV_UWRK_UWRK8_B0_UDB14_MSK EQU 0x4000648e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_MSK\r
+CYDEV_UWRK_UWRK8_B0_UDB15_MSK EQU 0x4000648f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_ACTL\r
+CYDEV_UWRK_UWRK8_B0_UDB00_ACTL EQU 0x40006490\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_ACTL\r
+CYDEV_UWRK_UWRK8_B0_UDB01_ACTL EQU 0x40006491\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_ACTL\r
+CYDEV_UWRK_UWRK8_B0_UDB02_ACTL EQU 0x40006492\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_ACTL\r
+CYDEV_UWRK_UWRK8_B0_UDB03_ACTL EQU 0x40006493\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_ACTL\r
+CYDEV_UWRK_UWRK8_B0_UDB04_ACTL EQU 0x40006494\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_ACTL\r
+CYDEV_UWRK_UWRK8_B0_UDB05_ACTL EQU 0x40006495\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_ACTL\r
+CYDEV_UWRK_UWRK8_B0_UDB06_ACTL EQU 0x40006496\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_ACTL\r
+CYDEV_UWRK_UWRK8_B0_UDB07_ACTL EQU 0x40006497\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_ACTL\r
+CYDEV_UWRK_UWRK8_B0_UDB08_ACTL EQU 0x40006498\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_ACTL\r
+CYDEV_UWRK_UWRK8_B0_UDB09_ACTL EQU 0x40006499\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_ACTL\r
+CYDEV_UWRK_UWRK8_B0_UDB10_ACTL EQU 0x4000649a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_ACTL\r
+CYDEV_UWRK_UWRK8_B0_UDB11_ACTL EQU 0x4000649b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_ACTL\r
+CYDEV_UWRK_UWRK8_B0_UDB12_ACTL EQU 0x4000649c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_ACTL\r
+CYDEV_UWRK_UWRK8_B0_UDB13_ACTL EQU 0x4000649d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_ACTL\r
+CYDEV_UWRK_UWRK8_B0_UDB14_ACTL EQU 0x4000649e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_ACTL\r
+CYDEV_UWRK_UWRK8_B0_UDB15_ACTL EQU 0x4000649f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_MC\r
+CYDEV_UWRK_UWRK8_B0_UDB00_MC EQU 0x400064a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_MC\r
+CYDEV_UWRK_UWRK8_B0_UDB01_MC EQU 0x400064a1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_MC\r
+CYDEV_UWRK_UWRK8_B0_UDB02_MC EQU 0x400064a2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_MC\r
+CYDEV_UWRK_UWRK8_B0_UDB03_MC EQU 0x400064a3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_MC\r
+CYDEV_UWRK_UWRK8_B0_UDB04_MC EQU 0x400064a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_MC\r
+CYDEV_UWRK_UWRK8_B0_UDB05_MC EQU 0x400064a5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_MC\r
+CYDEV_UWRK_UWRK8_B0_UDB06_MC EQU 0x400064a6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_MC\r
+CYDEV_UWRK_UWRK8_B0_UDB07_MC EQU 0x400064a7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_MC\r
+CYDEV_UWRK_UWRK8_B0_UDB08_MC EQU 0x400064a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_MC\r
+CYDEV_UWRK_UWRK8_B0_UDB09_MC EQU 0x400064a9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_MC\r
+CYDEV_UWRK_UWRK8_B0_UDB10_MC EQU 0x400064aa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_MC\r
+CYDEV_UWRK_UWRK8_B0_UDB11_MC EQU 0x400064ab\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_MC\r
+CYDEV_UWRK_UWRK8_B0_UDB12_MC EQU 0x400064ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_MC\r
+CYDEV_UWRK_UWRK8_B0_UDB13_MC EQU 0x400064ad\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_MC\r
+CYDEV_UWRK_UWRK8_B0_UDB14_MC EQU 0x400064ae\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_MC\r
+CYDEV_UWRK_UWRK8_B0_UDB15_MC EQU 0x400064af\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_BASE\r
+CYDEV_UWRK_UWRK8_B1_BASE EQU 0x40006500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_SIZE\r
+CYDEV_UWRK_UWRK8_B1_SIZE EQU 0x000000b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_A0\r
+CYDEV_UWRK_UWRK8_B1_UDB04_A0 EQU 0x40006504\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_A0\r
+CYDEV_UWRK_UWRK8_B1_UDB05_A0 EQU 0x40006505\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_A0\r
+CYDEV_UWRK_UWRK8_B1_UDB06_A0 EQU 0x40006506\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_A0\r
+CYDEV_UWRK_UWRK8_B1_UDB07_A0 EQU 0x40006507\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_A0\r
+CYDEV_UWRK_UWRK8_B1_UDB08_A0 EQU 0x40006508\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_A0\r
+CYDEV_UWRK_UWRK8_B1_UDB09_A0 EQU 0x40006509\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_A0\r
+CYDEV_UWRK_UWRK8_B1_UDB10_A0 EQU 0x4000650a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_A0\r
+CYDEV_UWRK_UWRK8_B1_UDB11_A0 EQU 0x4000650b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_A1\r
+CYDEV_UWRK_UWRK8_B1_UDB04_A1 EQU 0x40006514\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_A1\r
+CYDEV_UWRK_UWRK8_B1_UDB05_A1 EQU 0x40006515\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_A1\r
+CYDEV_UWRK_UWRK8_B1_UDB06_A1 EQU 0x40006516\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_A1\r
+CYDEV_UWRK_UWRK8_B1_UDB07_A1 EQU 0x40006517\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_A1\r
+CYDEV_UWRK_UWRK8_B1_UDB08_A1 EQU 0x40006518\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_A1\r
+CYDEV_UWRK_UWRK8_B1_UDB09_A1 EQU 0x40006519\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_A1\r
+CYDEV_UWRK_UWRK8_B1_UDB10_A1 EQU 0x4000651a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_A1\r
+CYDEV_UWRK_UWRK8_B1_UDB11_A1 EQU 0x4000651b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_D0\r
+CYDEV_UWRK_UWRK8_B1_UDB04_D0 EQU 0x40006524\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_D0\r
+CYDEV_UWRK_UWRK8_B1_UDB05_D0 EQU 0x40006525\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_D0\r
+CYDEV_UWRK_UWRK8_B1_UDB06_D0 EQU 0x40006526\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_D0\r
+CYDEV_UWRK_UWRK8_B1_UDB07_D0 EQU 0x40006527\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_D0\r
+CYDEV_UWRK_UWRK8_B1_UDB08_D0 EQU 0x40006528\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_D0\r
+CYDEV_UWRK_UWRK8_B1_UDB09_D0 EQU 0x40006529\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_D0\r
+CYDEV_UWRK_UWRK8_B1_UDB10_D0 EQU 0x4000652a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_D0\r
+CYDEV_UWRK_UWRK8_B1_UDB11_D0 EQU 0x4000652b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_D1\r
+CYDEV_UWRK_UWRK8_B1_UDB04_D1 EQU 0x40006534\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_D1\r
+CYDEV_UWRK_UWRK8_B1_UDB05_D1 EQU 0x40006535\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_D1\r
+CYDEV_UWRK_UWRK8_B1_UDB06_D1 EQU 0x40006536\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_D1\r
+CYDEV_UWRK_UWRK8_B1_UDB07_D1 EQU 0x40006537\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_D1\r
+CYDEV_UWRK_UWRK8_B1_UDB08_D1 EQU 0x40006538\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_D1\r
+CYDEV_UWRK_UWRK8_B1_UDB09_D1 EQU 0x40006539\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_D1\r
+CYDEV_UWRK_UWRK8_B1_UDB10_D1 EQU 0x4000653a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_D1\r
+CYDEV_UWRK_UWRK8_B1_UDB11_D1 EQU 0x4000653b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_F0\r
+CYDEV_UWRK_UWRK8_B1_UDB04_F0 EQU 0x40006544\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_F0\r
+CYDEV_UWRK_UWRK8_B1_UDB05_F0 EQU 0x40006545\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_F0\r
+CYDEV_UWRK_UWRK8_B1_UDB06_F0 EQU 0x40006546\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_F0\r
+CYDEV_UWRK_UWRK8_B1_UDB07_F0 EQU 0x40006547\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_F0\r
+CYDEV_UWRK_UWRK8_B1_UDB08_F0 EQU 0x40006548\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_F0\r
+CYDEV_UWRK_UWRK8_B1_UDB09_F0 EQU 0x40006549\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_F0\r
+CYDEV_UWRK_UWRK8_B1_UDB10_F0 EQU 0x4000654a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_F0\r
+CYDEV_UWRK_UWRK8_B1_UDB11_F0 EQU 0x4000654b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_F1\r
+CYDEV_UWRK_UWRK8_B1_UDB04_F1 EQU 0x40006554\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_F1\r
+CYDEV_UWRK_UWRK8_B1_UDB05_F1 EQU 0x40006555\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_F1\r
+CYDEV_UWRK_UWRK8_B1_UDB06_F1 EQU 0x40006556\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_F1\r
+CYDEV_UWRK_UWRK8_B1_UDB07_F1 EQU 0x40006557\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_F1\r
+CYDEV_UWRK_UWRK8_B1_UDB08_F1 EQU 0x40006558\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_F1\r
+CYDEV_UWRK_UWRK8_B1_UDB09_F1 EQU 0x40006559\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_F1\r
+CYDEV_UWRK_UWRK8_B1_UDB10_F1 EQU 0x4000655a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_F1\r
+CYDEV_UWRK_UWRK8_B1_UDB11_F1 EQU 0x4000655b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_ST\r
+CYDEV_UWRK_UWRK8_B1_UDB04_ST EQU 0x40006564\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_ST\r
+CYDEV_UWRK_UWRK8_B1_UDB05_ST EQU 0x40006565\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_ST\r
+CYDEV_UWRK_UWRK8_B1_UDB06_ST EQU 0x40006566\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_ST\r
+CYDEV_UWRK_UWRK8_B1_UDB07_ST EQU 0x40006567\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_ST\r
+CYDEV_UWRK_UWRK8_B1_UDB08_ST EQU 0x40006568\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_ST\r
+CYDEV_UWRK_UWRK8_B1_UDB09_ST EQU 0x40006569\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_ST\r
+CYDEV_UWRK_UWRK8_B1_UDB10_ST EQU 0x4000656a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_ST\r
+CYDEV_UWRK_UWRK8_B1_UDB11_ST EQU 0x4000656b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_CTL\r
+CYDEV_UWRK_UWRK8_B1_UDB04_CTL EQU 0x40006574\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_CTL\r
+CYDEV_UWRK_UWRK8_B1_UDB05_CTL EQU 0x40006575\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_CTL\r
+CYDEV_UWRK_UWRK8_B1_UDB06_CTL EQU 0x40006576\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_CTL\r
+CYDEV_UWRK_UWRK8_B1_UDB07_CTL EQU 0x40006577\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_CTL\r
+CYDEV_UWRK_UWRK8_B1_UDB08_CTL EQU 0x40006578\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_CTL\r
+CYDEV_UWRK_UWRK8_B1_UDB09_CTL EQU 0x40006579\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_CTL\r
+CYDEV_UWRK_UWRK8_B1_UDB10_CTL EQU 0x4000657a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_CTL\r
+CYDEV_UWRK_UWRK8_B1_UDB11_CTL EQU 0x4000657b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_MSK\r
+CYDEV_UWRK_UWRK8_B1_UDB04_MSK EQU 0x40006584\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_MSK\r
+CYDEV_UWRK_UWRK8_B1_UDB05_MSK EQU 0x40006585\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_MSK\r
+CYDEV_UWRK_UWRK8_B1_UDB06_MSK EQU 0x40006586\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_MSK\r
+CYDEV_UWRK_UWRK8_B1_UDB07_MSK EQU 0x40006587\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_MSK\r
+CYDEV_UWRK_UWRK8_B1_UDB08_MSK EQU 0x40006588\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_MSK\r
+CYDEV_UWRK_UWRK8_B1_UDB09_MSK EQU 0x40006589\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_MSK\r
+CYDEV_UWRK_UWRK8_B1_UDB10_MSK EQU 0x4000658a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_MSK\r
+CYDEV_UWRK_UWRK8_B1_UDB11_MSK EQU 0x4000658b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_ACTL\r
+CYDEV_UWRK_UWRK8_B1_UDB04_ACTL EQU 0x40006594\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_ACTL\r
+CYDEV_UWRK_UWRK8_B1_UDB05_ACTL EQU 0x40006595\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_ACTL\r
+CYDEV_UWRK_UWRK8_B1_UDB06_ACTL EQU 0x40006596\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_ACTL\r
+CYDEV_UWRK_UWRK8_B1_UDB07_ACTL EQU 0x40006597\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_ACTL\r
+CYDEV_UWRK_UWRK8_B1_UDB08_ACTL EQU 0x40006598\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_ACTL\r
+CYDEV_UWRK_UWRK8_B1_UDB09_ACTL EQU 0x40006599\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_ACTL\r
+CYDEV_UWRK_UWRK8_B1_UDB10_ACTL EQU 0x4000659a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_ACTL\r
+CYDEV_UWRK_UWRK8_B1_UDB11_ACTL EQU 0x4000659b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_MC\r
+CYDEV_UWRK_UWRK8_B1_UDB04_MC EQU 0x400065a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_MC\r
+CYDEV_UWRK_UWRK8_B1_UDB05_MC EQU 0x400065a5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_MC\r
+CYDEV_UWRK_UWRK8_B1_UDB06_MC EQU 0x400065a6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_MC\r
+CYDEV_UWRK_UWRK8_B1_UDB07_MC EQU 0x400065a7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_MC\r
+CYDEV_UWRK_UWRK8_B1_UDB08_MC EQU 0x400065a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_MC\r
+CYDEV_UWRK_UWRK8_B1_UDB09_MC EQU 0x400065a9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_MC\r
+CYDEV_UWRK_UWRK8_B1_UDB10_MC EQU 0x400065aa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_MC\r
+CYDEV_UWRK_UWRK8_B1_UDB11_MC EQU 0x400065ab\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_BASE\r
+CYDEV_UWRK_UWRK16_BASE EQU 0x40006800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_SIZE\r
+CYDEV_UWRK_UWRK16_SIZE EQU 0x00000760\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_BASE\r
+CYDEV_UWRK_UWRK16_CAT_BASE EQU 0x40006800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_SIZE\r
+CYDEV_UWRK_UWRK16_CAT_SIZE EQU 0x00000760\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_BASE\r
+CYDEV_UWRK_UWRK16_CAT_B0_BASE EQU 0x40006800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_SIZE\r
+CYDEV_UWRK_UWRK16_CAT_B0_SIZE EQU 0x00000160\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 EQU 0x40006800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 EQU 0x40006802\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 EQU 0x40006804\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 EQU 0x40006806\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 EQU 0x40006808\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 EQU 0x4000680a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 EQU 0x4000680c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 EQU 0x4000680e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 EQU 0x40006810\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 EQU 0x40006812\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 EQU 0x40006814\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 EQU 0x40006816\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 EQU 0x40006818\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 EQU 0x4000681a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 EQU 0x4000681c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 EQU 0x4000681e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 EQU 0x40006840\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 EQU 0x40006842\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 EQU 0x40006844\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 EQU 0x40006846\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 EQU 0x40006848\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 EQU 0x4000684a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 EQU 0x4000684c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 EQU 0x4000684e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 EQU 0x40006850\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 EQU 0x40006852\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 EQU 0x40006854\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 EQU 0x40006856\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 EQU 0x40006858\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 EQU 0x4000685a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 EQU 0x4000685c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 EQU 0x4000685e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 EQU 0x40006880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 EQU 0x40006882\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 EQU 0x40006884\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 EQU 0x40006886\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 EQU 0x40006888\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 EQU 0x4000688a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 EQU 0x4000688c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 EQU 0x4000688e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 EQU 0x40006890\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 EQU 0x40006892\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 EQU 0x40006894\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 EQU 0x40006896\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 EQU 0x40006898\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 EQU 0x4000689a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 EQU 0x4000689c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 EQU 0x4000689e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL EQU 0x400068c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL EQU 0x400068c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL EQU 0x400068c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL EQU 0x400068c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL EQU 0x400068c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL EQU 0x400068ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL EQU 0x400068cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL EQU 0x400068ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL EQU 0x400068d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL EQU 0x400068d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL EQU 0x400068d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL EQU 0x400068d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL EQU 0x400068d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL EQU 0x400068da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL EQU 0x400068dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL EQU 0x400068de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL EQU 0x40006900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL EQU 0x40006902\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL EQU 0x40006904\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL EQU 0x40006906\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL EQU 0x40006908\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL EQU 0x4000690a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL EQU 0x4000690c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL EQU 0x4000690e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL EQU 0x40006910\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL EQU 0x40006912\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL EQU 0x40006914\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL EQU 0x40006916\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL EQU 0x40006918\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL EQU 0x4000691a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL EQU 0x4000691c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL EQU 0x4000691e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 EQU 0x40006940\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 EQU 0x40006942\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 EQU 0x40006944\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 EQU 0x40006946\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 EQU 0x40006948\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 EQU 0x4000694a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 EQU 0x4000694c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 EQU 0x4000694e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 EQU 0x40006950\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 EQU 0x40006952\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 EQU 0x40006954\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 EQU 0x40006956\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 EQU 0x40006958\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 EQU 0x4000695a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 EQU 0x4000695c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 EQU 0x4000695e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_BASE\r
+CYDEV_UWRK_UWRK16_CAT_B1_BASE EQU 0x40006a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_SIZE\r
+CYDEV_UWRK_UWRK16_CAT_B1_SIZE EQU 0x00000160\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 EQU 0x40006a08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 EQU 0x40006a0a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 EQU 0x40006a0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 EQU 0x40006a0e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 EQU 0x40006a10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 EQU 0x40006a12\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 EQU 0x40006a14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 EQU 0x40006a16\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 EQU 0x40006a48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 EQU 0x40006a4a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 EQU 0x40006a4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 EQU 0x40006a4e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 EQU 0x40006a50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 EQU 0x40006a52\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 EQU 0x40006a54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 EQU 0x40006a56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 EQU 0x40006a88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 EQU 0x40006a8a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 EQU 0x40006a8c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 EQU 0x40006a8e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 EQU 0x40006a90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 EQU 0x40006a92\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 EQU 0x40006a94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 EQU 0x40006a96\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL EQU 0x40006ac8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL EQU 0x40006aca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL EQU 0x40006acc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL EQU 0x40006ace\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL EQU 0x40006ad0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL EQU 0x40006ad2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL EQU 0x40006ad4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL EQU 0x40006ad6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL EQU 0x40006b08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL EQU 0x40006b0a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL EQU 0x40006b0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL EQU 0x40006b0e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL EQU 0x40006b10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL EQU 0x40006b12\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL EQU 0x40006b14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL EQU 0x40006b16\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 EQU 0x40006b48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 EQU 0x40006b4a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 EQU 0x40006b4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 EQU 0x40006b4e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 EQU 0x40006b50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 EQU 0x40006b52\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 EQU 0x40006b54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00\r
+CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 EQU 0x40006b56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_BASE\r
+CYDEV_UWRK_UWRK16_DEF_BASE EQU 0x40006800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_SIZE\r
+CYDEV_UWRK_UWRK16_DEF_SIZE EQU 0x0000075e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_BASE\r
+CYDEV_UWRK_UWRK16_DEF_B0_BASE EQU 0x40006800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_SIZE\r
+CYDEV_UWRK_UWRK16_DEF_B0_SIZE EQU 0x0000015e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 EQU 0x40006800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 EQU 0x40006802\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 EQU 0x40006804\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 EQU 0x40006806\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 EQU 0x40006808\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 EQU 0x4000680a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 EQU 0x4000680c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 EQU 0x4000680e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 EQU 0x40006810\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 EQU 0x40006812\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 EQU 0x40006814\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 EQU 0x40006816\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 EQU 0x40006818\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 EQU 0x4000681a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 EQU 0x4000681c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 EQU 0x40006820\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 EQU 0x40006822\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 EQU 0x40006824\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 EQU 0x40006826\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 EQU 0x40006828\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 EQU 0x4000682a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 EQU 0x4000682c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 EQU 0x4000682e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 EQU 0x40006830\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 EQU 0x40006832\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 EQU 0x40006834\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 EQU 0x40006836\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 EQU 0x40006838\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 EQU 0x4000683a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 EQU 0x4000683c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 EQU 0x40006840\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 EQU 0x40006842\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 EQU 0x40006844\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 EQU 0x40006846\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 EQU 0x40006848\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 EQU 0x4000684a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 EQU 0x4000684c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 EQU 0x4000684e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 EQU 0x40006850\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 EQU 0x40006852\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 EQU 0x40006854\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 EQU 0x40006856\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 EQU 0x40006858\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 EQU 0x4000685a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 EQU 0x4000685c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 EQU 0x40006860\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 EQU 0x40006862\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 EQU 0x40006864\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 EQU 0x40006866\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 EQU 0x40006868\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 EQU 0x4000686a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 EQU 0x4000686c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 EQU 0x4000686e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 EQU 0x40006870\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 EQU 0x40006872\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 EQU 0x40006874\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 EQU 0x40006876\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 EQU 0x40006878\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 EQU 0x4000687a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 EQU 0x4000687c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 EQU 0x40006880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 EQU 0x40006882\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 EQU 0x40006884\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 EQU 0x40006886\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 EQU 0x40006888\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 EQU 0x4000688a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 EQU 0x4000688c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 EQU 0x4000688e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 EQU 0x40006890\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 EQU 0x40006892\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 EQU 0x40006894\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 EQU 0x40006896\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 EQU 0x40006898\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 EQU 0x4000689a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 EQU 0x4000689c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 EQU 0x400068a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 EQU 0x400068a2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 EQU 0x400068a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 EQU 0x400068a6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 EQU 0x400068a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 EQU 0x400068aa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 EQU 0x400068ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 EQU 0x400068ae\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 EQU 0x400068b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 EQU 0x400068b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 EQU 0x400068b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 EQU 0x400068b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 EQU 0x400068b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 EQU 0x400068ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 EQU 0x400068bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST EQU 0x400068c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST EQU 0x400068c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST EQU 0x400068c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST EQU 0x400068c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST EQU 0x400068c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST EQU 0x400068ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST EQU 0x400068cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST EQU 0x400068ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST EQU 0x400068d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST EQU 0x400068d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST EQU 0x400068d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST EQU 0x400068d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST EQU 0x400068d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST EQU 0x400068da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST EQU 0x400068dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL EQU 0x400068e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL EQU 0x400068e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL EQU 0x400068e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL EQU 0x400068e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL EQU 0x400068e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL EQU 0x400068ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL EQU 0x400068ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL EQU 0x400068ee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL EQU 0x400068f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL EQU 0x400068f2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL EQU 0x400068f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL EQU 0x400068f6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL EQU 0x400068f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL EQU 0x400068fa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL EQU 0x400068fc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK EQU 0x40006900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK EQU 0x40006902\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK EQU 0x40006904\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK EQU 0x40006906\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK EQU 0x40006908\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK EQU 0x4000690a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK EQU 0x4000690c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK EQU 0x4000690e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK EQU 0x40006910\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK EQU 0x40006912\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK EQU 0x40006914\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK EQU 0x40006916\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK EQU 0x40006918\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK EQU 0x4000691a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK EQU 0x4000691c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL EQU 0x40006920\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL EQU 0x40006922\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL EQU 0x40006924\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL EQU 0x40006926\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL EQU 0x40006928\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL EQU 0x4000692a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL EQU 0x4000692c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL EQU 0x4000692e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL EQU 0x40006930\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL EQU 0x40006932\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL EQU 0x40006934\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL EQU 0x40006936\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL EQU 0x40006938\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL EQU 0x4000693a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL EQU 0x4000693c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC EQU 0x40006940\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC EQU 0x40006942\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC EQU 0x40006944\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC EQU 0x40006946\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC EQU 0x40006948\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC EQU 0x4000694a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC EQU 0x4000694c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC EQU 0x4000694e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC EQU 0x40006950\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC EQU 0x40006952\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC EQU 0x40006954\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC EQU 0x40006956\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC EQU 0x40006958\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC EQU 0x4000695a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC\r
+CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC EQU 0x4000695c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_BASE\r
+CYDEV_UWRK_UWRK16_DEF_B1_BASE EQU 0x40006a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_SIZE\r
+CYDEV_UWRK_UWRK16_DEF_B1_SIZE EQU 0x0000015e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 EQU 0x40006a08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 EQU 0x40006a0a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 EQU 0x40006a0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 EQU 0x40006a0e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 EQU 0x40006a10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 EQU 0x40006a12\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 EQU 0x40006a14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 EQU 0x40006a16\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 EQU 0x40006a28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 EQU 0x40006a2a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 EQU 0x40006a2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 EQU 0x40006a2e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 EQU 0x40006a30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 EQU 0x40006a32\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 EQU 0x40006a34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 EQU 0x40006a36\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 EQU 0x40006a48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 EQU 0x40006a4a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 EQU 0x40006a4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 EQU 0x40006a4e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 EQU 0x40006a50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 EQU 0x40006a52\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 EQU 0x40006a54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 EQU 0x40006a56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 EQU 0x40006a68\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 EQU 0x40006a6a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 EQU 0x40006a6c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 EQU 0x40006a6e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 EQU 0x40006a70\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 EQU 0x40006a72\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 EQU 0x40006a74\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 EQU 0x40006a76\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 EQU 0x40006a88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 EQU 0x40006a8a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 EQU 0x40006a8c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 EQU 0x40006a8e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 EQU 0x40006a90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 EQU 0x40006a92\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 EQU 0x40006a94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 EQU 0x40006a96\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 EQU 0x40006aa8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 EQU 0x40006aaa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 EQU 0x40006aac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 EQU 0x40006aae\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 EQU 0x40006ab0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 EQU 0x40006ab2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 EQU 0x40006ab4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 EQU 0x40006ab6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST EQU 0x40006ac8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST EQU 0x40006aca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST EQU 0x40006acc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST EQU 0x40006ace\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST EQU 0x40006ad0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST EQU 0x40006ad2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST EQU 0x40006ad4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST EQU 0x40006ad6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL EQU 0x40006ae8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL EQU 0x40006aea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL EQU 0x40006aec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL EQU 0x40006aee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL EQU 0x40006af0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL EQU 0x40006af2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL EQU 0x40006af4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL EQU 0x40006af6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK EQU 0x40006b08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK EQU 0x40006b0a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK EQU 0x40006b0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK EQU 0x40006b0e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK EQU 0x40006b10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK EQU 0x40006b12\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK EQU 0x40006b14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK EQU 0x40006b16\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL EQU 0x40006b28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL EQU 0x40006b2a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL EQU 0x40006b2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL EQU 0x40006b2e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL EQU 0x40006b30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL EQU 0x40006b32\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL EQU 0x40006b34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL EQU 0x40006b36\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC EQU 0x40006b48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC EQU 0x40006b4a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC EQU 0x40006b4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC EQU 0x40006b4e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC EQU 0x40006b50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC EQU 0x40006b52\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC EQU 0x40006b54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC\r
+CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC EQU 0x40006b56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_BASE\r
+CYDEV_PHUB_BASE EQU 0x40007000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_SIZE\r
+CYDEV_PHUB_SIZE EQU 0x00000c00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFG\r
+CYDEV_PHUB_CFG EQU 0x40007000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_ERR\r
+CYDEV_PHUB_ERR EQU 0x40007004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_ERR_ADR\r
+CYDEV_PHUB_ERR_ADR EQU 0x40007008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH0_BASE\r
+CYDEV_PHUB_CH0_BASE EQU 0x40007010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH0_SIZE\r
+CYDEV_PHUB_CH0_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH0_BASIC_CFG\r
+CYDEV_PHUB_CH0_BASIC_CFG EQU 0x40007010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH0_ACTION\r
+CYDEV_PHUB_CH0_ACTION EQU 0x40007014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH0_BASIC_STATUS\r
+CYDEV_PHUB_CH0_BASIC_STATUS EQU 0x40007018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH1_BASE\r
+CYDEV_PHUB_CH1_BASE EQU 0x40007020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH1_SIZE\r
+CYDEV_PHUB_CH1_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH1_BASIC_CFG\r
+CYDEV_PHUB_CH1_BASIC_CFG EQU 0x40007020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH1_ACTION\r
+CYDEV_PHUB_CH1_ACTION EQU 0x40007024\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH1_BASIC_STATUS\r
+CYDEV_PHUB_CH1_BASIC_STATUS EQU 0x40007028\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH2_BASE\r
+CYDEV_PHUB_CH2_BASE EQU 0x40007030\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH2_SIZE\r
+CYDEV_PHUB_CH2_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH2_BASIC_CFG\r
+CYDEV_PHUB_CH2_BASIC_CFG EQU 0x40007030\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH2_ACTION\r
+CYDEV_PHUB_CH2_ACTION EQU 0x40007034\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH2_BASIC_STATUS\r
+CYDEV_PHUB_CH2_BASIC_STATUS EQU 0x40007038\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH3_BASE\r
+CYDEV_PHUB_CH3_BASE EQU 0x40007040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH3_SIZE\r
+CYDEV_PHUB_CH3_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH3_BASIC_CFG\r
+CYDEV_PHUB_CH3_BASIC_CFG EQU 0x40007040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH3_ACTION\r
+CYDEV_PHUB_CH3_ACTION EQU 0x40007044\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH3_BASIC_STATUS\r
+CYDEV_PHUB_CH3_BASIC_STATUS EQU 0x40007048\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH4_BASE\r
+CYDEV_PHUB_CH4_BASE EQU 0x40007050\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH4_SIZE\r
+CYDEV_PHUB_CH4_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH4_BASIC_CFG\r
+CYDEV_PHUB_CH4_BASIC_CFG EQU 0x40007050\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH4_ACTION\r
+CYDEV_PHUB_CH4_ACTION EQU 0x40007054\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH4_BASIC_STATUS\r
+CYDEV_PHUB_CH4_BASIC_STATUS EQU 0x40007058\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH5_BASE\r
+CYDEV_PHUB_CH5_BASE EQU 0x40007060\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH5_SIZE\r
+CYDEV_PHUB_CH5_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH5_BASIC_CFG\r
+CYDEV_PHUB_CH5_BASIC_CFG EQU 0x40007060\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH5_ACTION\r
+CYDEV_PHUB_CH5_ACTION EQU 0x40007064\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH5_BASIC_STATUS\r
+CYDEV_PHUB_CH5_BASIC_STATUS EQU 0x40007068\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH6_BASE\r
+CYDEV_PHUB_CH6_BASE EQU 0x40007070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH6_SIZE\r
+CYDEV_PHUB_CH6_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH6_BASIC_CFG\r
+CYDEV_PHUB_CH6_BASIC_CFG EQU 0x40007070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH6_ACTION\r
+CYDEV_PHUB_CH6_ACTION EQU 0x40007074\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH6_BASIC_STATUS\r
+CYDEV_PHUB_CH6_BASIC_STATUS EQU 0x40007078\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH7_BASE\r
+CYDEV_PHUB_CH7_BASE EQU 0x40007080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH7_SIZE\r
+CYDEV_PHUB_CH7_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH7_BASIC_CFG\r
+CYDEV_PHUB_CH7_BASIC_CFG EQU 0x40007080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH7_ACTION\r
+CYDEV_PHUB_CH7_ACTION EQU 0x40007084\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH7_BASIC_STATUS\r
+CYDEV_PHUB_CH7_BASIC_STATUS EQU 0x40007088\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH8_BASE\r
+CYDEV_PHUB_CH8_BASE EQU 0x40007090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH8_SIZE\r
+CYDEV_PHUB_CH8_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH8_BASIC_CFG\r
+CYDEV_PHUB_CH8_BASIC_CFG EQU 0x40007090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH8_ACTION\r
+CYDEV_PHUB_CH8_ACTION EQU 0x40007094\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH8_BASIC_STATUS\r
+CYDEV_PHUB_CH8_BASIC_STATUS EQU 0x40007098\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH9_BASE\r
+CYDEV_PHUB_CH9_BASE EQU 0x400070a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH9_SIZE\r
+CYDEV_PHUB_CH9_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH9_BASIC_CFG\r
+CYDEV_PHUB_CH9_BASIC_CFG EQU 0x400070a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH9_ACTION\r
+CYDEV_PHUB_CH9_ACTION EQU 0x400070a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH9_BASIC_STATUS\r
+CYDEV_PHUB_CH9_BASIC_STATUS EQU 0x400070a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH10_BASE\r
+CYDEV_PHUB_CH10_BASE EQU 0x400070b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH10_SIZE\r
+CYDEV_PHUB_CH10_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH10_BASIC_CFG\r
+CYDEV_PHUB_CH10_BASIC_CFG EQU 0x400070b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH10_ACTION\r
+CYDEV_PHUB_CH10_ACTION EQU 0x400070b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH10_BASIC_STATUS\r
+CYDEV_PHUB_CH10_BASIC_STATUS EQU 0x400070b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH11_BASE\r
+CYDEV_PHUB_CH11_BASE EQU 0x400070c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH11_SIZE\r
+CYDEV_PHUB_CH11_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH11_BASIC_CFG\r
+CYDEV_PHUB_CH11_BASIC_CFG EQU 0x400070c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH11_ACTION\r
+CYDEV_PHUB_CH11_ACTION EQU 0x400070c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH11_BASIC_STATUS\r
+CYDEV_PHUB_CH11_BASIC_STATUS EQU 0x400070c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH12_BASE\r
+CYDEV_PHUB_CH12_BASE EQU 0x400070d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH12_SIZE\r
+CYDEV_PHUB_CH12_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH12_BASIC_CFG\r
+CYDEV_PHUB_CH12_BASIC_CFG EQU 0x400070d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH12_ACTION\r
+CYDEV_PHUB_CH12_ACTION EQU 0x400070d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH12_BASIC_STATUS\r
+CYDEV_PHUB_CH12_BASIC_STATUS EQU 0x400070d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH13_BASE\r
+CYDEV_PHUB_CH13_BASE EQU 0x400070e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH13_SIZE\r
+CYDEV_PHUB_CH13_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH13_BASIC_CFG\r
+CYDEV_PHUB_CH13_BASIC_CFG EQU 0x400070e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH13_ACTION\r
+CYDEV_PHUB_CH13_ACTION EQU 0x400070e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH13_BASIC_STATUS\r
+CYDEV_PHUB_CH13_BASIC_STATUS EQU 0x400070e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH14_BASE\r
+CYDEV_PHUB_CH14_BASE EQU 0x400070f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH14_SIZE\r
+CYDEV_PHUB_CH14_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH14_BASIC_CFG\r
+CYDEV_PHUB_CH14_BASIC_CFG EQU 0x400070f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH14_ACTION\r
+CYDEV_PHUB_CH14_ACTION EQU 0x400070f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH14_BASIC_STATUS\r
+CYDEV_PHUB_CH14_BASIC_STATUS EQU 0x400070f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH15_BASE\r
+CYDEV_PHUB_CH15_BASE EQU 0x40007100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH15_SIZE\r
+CYDEV_PHUB_CH15_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH15_BASIC_CFG\r
+CYDEV_PHUB_CH15_BASIC_CFG EQU 0x40007100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH15_ACTION\r
+CYDEV_PHUB_CH15_ACTION EQU 0x40007104\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH15_BASIC_STATUS\r
+CYDEV_PHUB_CH15_BASIC_STATUS EQU 0x40007108\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH16_BASE\r
+CYDEV_PHUB_CH16_BASE EQU 0x40007110\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH16_SIZE\r
+CYDEV_PHUB_CH16_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH16_BASIC_CFG\r
+CYDEV_PHUB_CH16_BASIC_CFG EQU 0x40007110\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH16_ACTION\r
+CYDEV_PHUB_CH16_ACTION EQU 0x40007114\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH16_BASIC_STATUS\r
+CYDEV_PHUB_CH16_BASIC_STATUS EQU 0x40007118\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH17_BASE\r
+CYDEV_PHUB_CH17_BASE EQU 0x40007120\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH17_SIZE\r
+CYDEV_PHUB_CH17_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH17_BASIC_CFG\r
+CYDEV_PHUB_CH17_BASIC_CFG EQU 0x40007120\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH17_ACTION\r
+CYDEV_PHUB_CH17_ACTION EQU 0x40007124\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH17_BASIC_STATUS\r
+CYDEV_PHUB_CH17_BASIC_STATUS EQU 0x40007128\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH18_BASE\r
+CYDEV_PHUB_CH18_BASE EQU 0x40007130\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH18_SIZE\r
+CYDEV_PHUB_CH18_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH18_BASIC_CFG\r
+CYDEV_PHUB_CH18_BASIC_CFG EQU 0x40007130\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH18_ACTION\r
+CYDEV_PHUB_CH18_ACTION EQU 0x40007134\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH18_BASIC_STATUS\r
+CYDEV_PHUB_CH18_BASIC_STATUS EQU 0x40007138\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH19_BASE\r
+CYDEV_PHUB_CH19_BASE EQU 0x40007140\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH19_SIZE\r
+CYDEV_PHUB_CH19_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH19_BASIC_CFG\r
+CYDEV_PHUB_CH19_BASIC_CFG EQU 0x40007140\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH19_ACTION\r
+CYDEV_PHUB_CH19_ACTION EQU 0x40007144\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH19_BASIC_STATUS\r
+CYDEV_PHUB_CH19_BASIC_STATUS EQU 0x40007148\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH20_BASE\r
+CYDEV_PHUB_CH20_BASE EQU 0x40007150\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH20_SIZE\r
+CYDEV_PHUB_CH20_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH20_BASIC_CFG\r
+CYDEV_PHUB_CH20_BASIC_CFG EQU 0x40007150\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH20_ACTION\r
+CYDEV_PHUB_CH20_ACTION EQU 0x40007154\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH20_BASIC_STATUS\r
+CYDEV_PHUB_CH20_BASIC_STATUS EQU 0x40007158\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH21_BASE\r
+CYDEV_PHUB_CH21_BASE EQU 0x40007160\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH21_SIZE\r
+CYDEV_PHUB_CH21_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH21_BASIC_CFG\r
+CYDEV_PHUB_CH21_BASIC_CFG EQU 0x40007160\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH21_ACTION\r
+CYDEV_PHUB_CH21_ACTION EQU 0x40007164\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH21_BASIC_STATUS\r
+CYDEV_PHUB_CH21_BASIC_STATUS EQU 0x40007168\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH22_BASE\r
+CYDEV_PHUB_CH22_BASE EQU 0x40007170\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH22_SIZE\r
+CYDEV_PHUB_CH22_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH22_BASIC_CFG\r
+CYDEV_PHUB_CH22_BASIC_CFG EQU 0x40007170\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH22_ACTION\r
+CYDEV_PHUB_CH22_ACTION EQU 0x40007174\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH22_BASIC_STATUS\r
+CYDEV_PHUB_CH22_BASIC_STATUS EQU 0x40007178\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH23_BASE\r
+CYDEV_PHUB_CH23_BASE EQU 0x40007180\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH23_SIZE\r
+CYDEV_PHUB_CH23_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH23_BASIC_CFG\r
+CYDEV_PHUB_CH23_BASIC_CFG EQU 0x40007180\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH23_ACTION\r
+CYDEV_PHUB_CH23_ACTION EQU 0x40007184\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH23_BASIC_STATUS\r
+CYDEV_PHUB_CH23_BASIC_STATUS EQU 0x40007188\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_BASE\r
+CYDEV_PHUB_CFGMEM0_BASE EQU 0x40007600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_SIZE\r
+CYDEV_PHUB_CFGMEM0_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_CFG0\r
+CYDEV_PHUB_CFGMEM0_CFG0 EQU 0x40007600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_CFG1\r
+CYDEV_PHUB_CFGMEM0_CFG1 EQU 0x40007604\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_BASE\r
+CYDEV_PHUB_CFGMEM1_BASE EQU 0x40007608\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_SIZE\r
+CYDEV_PHUB_CFGMEM1_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_CFG0\r
+CYDEV_PHUB_CFGMEM1_CFG0 EQU 0x40007608\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_CFG1\r
+CYDEV_PHUB_CFGMEM1_CFG1 EQU 0x4000760c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_BASE\r
+CYDEV_PHUB_CFGMEM2_BASE EQU 0x40007610\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_SIZE\r
+CYDEV_PHUB_CFGMEM2_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_CFG0\r
+CYDEV_PHUB_CFGMEM2_CFG0 EQU 0x40007610\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_CFG1\r
+CYDEV_PHUB_CFGMEM2_CFG1 EQU 0x40007614\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_BASE\r
+CYDEV_PHUB_CFGMEM3_BASE EQU 0x40007618\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_SIZE\r
+CYDEV_PHUB_CFGMEM3_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_CFG0\r
+CYDEV_PHUB_CFGMEM3_CFG0 EQU 0x40007618\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_CFG1\r
+CYDEV_PHUB_CFGMEM3_CFG1 EQU 0x4000761c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_BASE\r
+CYDEV_PHUB_CFGMEM4_BASE EQU 0x40007620\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_SIZE\r
+CYDEV_PHUB_CFGMEM4_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_CFG0\r
+CYDEV_PHUB_CFGMEM4_CFG0 EQU 0x40007620\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_CFG1\r
+CYDEV_PHUB_CFGMEM4_CFG1 EQU 0x40007624\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_BASE\r
+CYDEV_PHUB_CFGMEM5_BASE EQU 0x40007628\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_SIZE\r
+CYDEV_PHUB_CFGMEM5_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_CFG0\r
+CYDEV_PHUB_CFGMEM5_CFG0 EQU 0x40007628\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_CFG1\r
+CYDEV_PHUB_CFGMEM5_CFG1 EQU 0x4000762c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_BASE\r
+CYDEV_PHUB_CFGMEM6_BASE EQU 0x40007630\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_SIZE\r
+CYDEV_PHUB_CFGMEM6_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_CFG0\r
+CYDEV_PHUB_CFGMEM6_CFG0 EQU 0x40007630\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_CFG1\r
+CYDEV_PHUB_CFGMEM6_CFG1 EQU 0x40007634\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_BASE\r
+CYDEV_PHUB_CFGMEM7_BASE EQU 0x40007638\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_SIZE\r
+CYDEV_PHUB_CFGMEM7_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_CFG0\r
+CYDEV_PHUB_CFGMEM7_CFG0 EQU 0x40007638\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_CFG1\r
+CYDEV_PHUB_CFGMEM7_CFG1 EQU 0x4000763c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_BASE\r
+CYDEV_PHUB_CFGMEM8_BASE EQU 0x40007640\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_SIZE\r
+CYDEV_PHUB_CFGMEM8_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_CFG0\r
+CYDEV_PHUB_CFGMEM8_CFG0 EQU 0x40007640\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_CFG1\r
+CYDEV_PHUB_CFGMEM8_CFG1 EQU 0x40007644\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_BASE\r
+CYDEV_PHUB_CFGMEM9_BASE EQU 0x40007648\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_SIZE\r
+CYDEV_PHUB_CFGMEM9_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_CFG0\r
+CYDEV_PHUB_CFGMEM9_CFG0 EQU 0x40007648\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_CFG1\r
+CYDEV_PHUB_CFGMEM9_CFG1 EQU 0x4000764c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_BASE\r
+CYDEV_PHUB_CFGMEM10_BASE EQU 0x40007650\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_SIZE\r
+CYDEV_PHUB_CFGMEM10_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_CFG0\r
+CYDEV_PHUB_CFGMEM10_CFG0 EQU 0x40007650\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_CFG1\r
+CYDEV_PHUB_CFGMEM10_CFG1 EQU 0x40007654\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_BASE\r
+CYDEV_PHUB_CFGMEM11_BASE EQU 0x40007658\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_SIZE\r
+CYDEV_PHUB_CFGMEM11_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_CFG0\r
+CYDEV_PHUB_CFGMEM11_CFG0 EQU 0x40007658\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_CFG1\r
+CYDEV_PHUB_CFGMEM11_CFG1 EQU 0x4000765c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_BASE\r
+CYDEV_PHUB_CFGMEM12_BASE EQU 0x40007660\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_SIZE\r
+CYDEV_PHUB_CFGMEM12_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_CFG0\r
+CYDEV_PHUB_CFGMEM12_CFG0 EQU 0x40007660\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_CFG1\r
+CYDEV_PHUB_CFGMEM12_CFG1 EQU 0x40007664\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_BASE\r
+CYDEV_PHUB_CFGMEM13_BASE EQU 0x40007668\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_SIZE\r
+CYDEV_PHUB_CFGMEM13_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_CFG0\r
+CYDEV_PHUB_CFGMEM13_CFG0 EQU 0x40007668\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_CFG1\r
+CYDEV_PHUB_CFGMEM13_CFG1 EQU 0x4000766c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_BASE\r
+CYDEV_PHUB_CFGMEM14_BASE EQU 0x40007670\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_SIZE\r
+CYDEV_PHUB_CFGMEM14_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_CFG0\r
+CYDEV_PHUB_CFGMEM14_CFG0 EQU 0x40007670\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_CFG1\r
+CYDEV_PHUB_CFGMEM14_CFG1 EQU 0x40007674\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_BASE\r
+CYDEV_PHUB_CFGMEM15_BASE EQU 0x40007678\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_SIZE\r
+CYDEV_PHUB_CFGMEM15_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_CFG0\r
+CYDEV_PHUB_CFGMEM15_CFG0 EQU 0x40007678\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_CFG1\r
+CYDEV_PHUB_CFGMEM15_CFG1 EQU 0x4000767c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_BASE\r
+CYDEV_PHUB_CFGMEM16_BASE EQU 0x40007680\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_SIZE\r
+CYDEV_PHUB_CFGMEM16_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_CFG0\r
+CYDEV_PHUB_CFGMEM16_CFG0 EQU 0x40007680\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_CFG1\r
+CYDEV_PHUB_CFGMEM16_CFG1 EQU 0x40007684\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_BASE\r
+CYDEV_PHUB_CFGMEM17_BASE EQU 0x40007688\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_SIZE\r
+CYDEV_PHUB_CFGMEM17_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_CFG0\r
+CYDEV_PHUB_CFGMEM17_CFG0 EQU 0x40007688\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_CFG1\r
+CYDEV_PHUB_CFGMEM17_CFG1 EQU 0x4000768c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_BASE\r
+CYDEV_PHUB_CFGMEM18_BASE EQU 0x40007690\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_SIZE\r
+CYDEV_PHUB_CFGMEM18_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_CFG0\r
+CYDEV_PHUB_CFGMEM18_CFG0 EQU 0x40007690\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_CFG1\r
+CYDEV_PHUB_CFGMEM18_CFG1 EQU 0x40007694\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_BASE\r
+CYDEV_PHUB_CFGMEM19_BASE EQU 0x40007698\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_SIZE\r
+CYDEV_PHUB_CFGMEM19_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_CFG0\r
+CYDEV_PHUB_CFGMEM19_CFG0 EQU 0x40007698\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_CFG1\r
+CYDEV_PHUB_CFGMEM19_CFG1 EQU 0x4000769c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_BASE\r
+CYDEV_PHUB_CFGMEM20_BASE EQU 0x400076a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_SIZE\r
+CYDEV_PHUB_CFGMEM20_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_CFG0\r
+CYDEV_PHUB_CFGMEM20_CFG0 EQU 0x400076a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_CFG1\r
+CYDEV_PHUB_CFGMEM20_CFG1 EQU 0x400076a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_BASE\r
+CYDEV_PHUB_CFGMEM21_BASE EQU 0x400076a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_SIZE\r
+CYDEV_PHUB_CFGMEM21_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_CFG0\r
+CYDEV_PHUB_CFGMEM21_CFG0 EQU 0x400076a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_CFG1\r
+CYDEV_PHUB_CFGMEM21_CFG1 EQU 0x400076ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_BASE\r
+CYDEV_PHUB_CFGMEM22_BASE EQU 0x400076b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_SIZE\r
+CYDEV_PHUB_CFGMEM22_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_CFG0\r
+CYDEV_PHUB_CFGMEM22_CFG0 EQU 0x400076b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_CFG1\r
+CYDEV_PHUB_CFGMEM22_CFG1 EQU 0x400076b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_BASE\r
+CYDEV_PHUB_CFGMEM23_BASE EQU 0x400076b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_SIZE\r
+CYDEV_PHUB_CFGMEM23_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_CFG0\r
+CYDEV_PHUB_CFGMEM23_CFG0 EQU 0x400076b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_CFG1\r
+CYDEV_PHUB_CFGMEM23_CFG1 EQU 0x400076bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_BASE\r
+CYDEV_PHUB_TDMEM0_BASE EQU 0x40007800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_SIZE\r
+CYDEV_PHUB_TDMEM0_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_ORIG_TD0\r
+CYDEV_PHUB_TDMEM0_ORIG_TD0 EQU 0x40007800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_ORIG_TD1\r
+CYDEV_PHUB_TDMEM0_ORIG_TD1 EQU 0x40007804\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_BASE\r
+CYDEV_PHUB_TDMEM1_BASE EQU 0x40007808\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_SIZE\r
+CYDEV_PHUB_TDMEM1_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_ORIG_TD0\r
+CYDEV_PHUB_TDMEM1_ORIG_TD0 EQU 0x40007808\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_ORIG_TD1\r
+CYDEV_PHUB_TDMEM1_ORIG_TD1 EQU 0x4000780c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_BASE\r
+CYDEV_PHUB_TDMEM2_BASE EQU 0x40007810\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_SIZE\r
+CYDEV_PHUB_TDMEM2_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_ORIG_TD0\r
+CYDEV_PHUB_TDMEM2_ORIG_TD0 EQU 0x40007810\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_ORIG_TD1\r
+CYDEV_PHUB_TDMEM2_ORIG_TD1 EQU 0x40007814\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_BASE\r
+CYDEV_PHUB_TDMEM3_BASE EQU 0x40007818\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_SIZE\r
+CYDEV_PHUB_TDMEM3_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_ORIG_TD0\r
+CYDEV_PHUB_TDMEM3_ORIG_TD0 EQU 0x40007818\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_ORIG_TD1\r
+CYDEV_PHUB_TDMEM3_ORIG_TD1 EQU 0x4000781c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_BASE\r
+CYDEV_PHUB_TDMEM4_BASE EQU 0x40007820\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_SIZE\r
+CYDEV_PHUB_TDMEM4_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_ORIG_TD0\r
+CYDEV_PHUB_TDMEM4_ORIG_TD0 EQU 0x40007820\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_ORIG_TD1\r
+CYDEV_PHUB_TDMEM4_ORIG_TD1 EQU 0x40007824\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_BASE\r
+CYDEV_PHUB_TDMEM5_BASE EQU 0x40007828\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_SIZE\r
+CYDEV_PHUB_TDMEM5_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_ORIG_TD0\r
+CYDEV_PHUB_TDMEM5_ORIG_TD0 EQU 0x40007828\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_ORIG_TD1\r
+CYDEV_PHUB_TDMEM5_ORIG_TD1 EQU 0x4000782c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_BASE\r
+CYDEV_PHUB_TDMEM6_BASE EQU 0x40007830\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_SIZE\r
+CYDEV_PHUB_TDMEM6_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_ORIG_TD0\r
+CYDEV_PHUB_TDMEM6_ORIG_TD0 EQU 0x40007830\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_ORIG_TD1\r
+CYDEV_PHUB_TDMEM6_ORIG_TD1 EQU 0x40007834\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_BASE\r
+CYDEV_PHUB_TDMEM7_BASE EQU 0x40007838\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_SIZE\r
+CYDEV_PHUB_TDMEM7_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_ORIG_TD0\r
+CYDEV_PHUB_TDMEM7_ORIG_TD0 EQU 0x40007838\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_ORIG_TD1\r
+CYDEV_PHUB_TDMEM7_ORIG_TD1 EQU 0x4000783c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_BASE\r
+CYDEV_PHUB_TDMEM8_BASE EQU 0x40007840\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_SIZE\r
+CYDEV_PHUB_TDMEM8_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_ORIG_TD0\r
+CYDEV_PHUB_TDMEM8_ORIG_TD0 EQU 0x40007840\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_ORIG_TD1\r
+CYDEV_PHUB_TDMEM8_ORIG_TD1 EQU 0x40007844\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_BASE\r
+CYDEV_PHUB_TDMEM9_BASE EQU 0x40007848\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_SIZE\r
+CYDEV_PHUB_TDMEM9_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_ORIG_TD0\r
+CYDEV_PHUB_TDMEM9_ORIG_TD0 EQU 0x40007848\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_ORIG_TD1\r
+CYDEV_PHUB_TDMEM9_ORIG_TD1 EQU 0x4000784c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_BASE\r
+CYDEV_PHUB_TDMEM10_BASE EQU 0x40007850\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_SIZE\r
+CYDEV_PHUB_TDMEM10_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_ORIG_TD0\r
+CYDEV_PHUB_TDMEM10_ORIG_TD0 EQU 0x40007850\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_ORIG_TD1\r
+CYDEV_PHUB_TDMEM10_ORIG_TD1 EQU 0x40007854\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_BASE\r
+CYDEV_PHUB_TDMEM11_BASE EQU 0x40007858\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_SIZE\r
+CYDEV_PHUB_TDMEM11_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_ORIG_TD0\r
+CYDEV_PHUB_TDMEM11_ORIG_TD0 EQU 0x40007858\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_ORIG_TD1\r
+CYDEV_PHUB_TDMEM11_ORIG_TD1 EQU 0x4000785c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_BASE\r
+CYDEV_PHUB_TDMEM12_BASE EQU 0x40007860\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_SIZE\r
+CYDEV_PHUB_TDMEM12_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_ORIG_TD0\r
+CYDEV_PHUB_TDMEM12_ORIG_TD0 EQU 0x40007860\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_ORIG_TD1\r
+CYDEV_PHUB_TDMEM12_ORIG_TD1 EQU 0x40007864\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_BASE\r
+CYDEV_PHUB_TDMEM13_BASE EQU 0x40007868\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_SIZE\r
+CYDEV_PHUB_TDMEM13_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_ORIG_TD0\r
+CYDEV_PHUB_TDMEM13_ORIG_TD0 EQU 0x40007868\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_ORIG_TD1\r
+CYDEV_PHUB_TDMEM13_ORIG_TD1 EQU 0x4000786c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_BASE\r
+CYDEV_PHUB_TDMEM14_BASE EQU 0x40007870\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_SIZE\r
+CYDEV_PHUB_TDMEM14_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_ORIG_TD0\r
+CYDEV_PHUB_TDMEM14_ORIG_TD0 EQU 0x40007870\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_ORIG_TD1\r
+CYDEV_PHUB_TDMEM14_ORIG_TD1 EQU 0x40007874\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_BASE\r
+CYDEV_PHUB_TDMEM15_BASE EQU 0x40007878\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_SIZE\r
+CYDEV_PHUB_TDMEM15_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_ORIG_TD0\r
+CYDEV_PHUB_TDMEM15_ORIG_TD0 EQU 0x40007878\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_ORIG_TD1\r
+CYDEV_PHUB_TDMEM15_ORIG_TD1 EQU 0x4000787c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_BASE\r
+CYDEV_PHUB_TDMEM16_BASE EQU 0x40007880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_SIZE\r
+CYDEV_PHUB_TDMEM16_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_ORIG_TD0\r
+CYDEV_PHUB_TDMEM16_ORIG_TD0 EQU 0x40007880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_ORIG_TD1\r
+CYDEV_PHUB_TDMEM16_ORIG_TD1 EQU 0x40007884\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_BASE\r
+CYDEV_PHUB_TDMEM17_BASE EQU 0x40007888\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_SIZE\r
+CYDEV_PHUB_TDMEM17_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_ORIG_TD0\r
+CYDEV_PHUB_TDMEM17_ORIG_TD0 EQU 0x40007888\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_ORIG_TD1\r
+CYDEV_PHUB_TDMEM17_ORIG_TD1 EQU 0x4000788c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_BASE\r
+CYDEV_PHUB_TDMEM18_BASE EQU 0x40007890\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_SIZE\r
+CYDEV_PHUB_TDMEM18_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_ORIG_TD0\r
+CYDEV_PHUB_TDMEM18_ORIG_TD0 EQU 0x40007890\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_ORIG_TD1\r
+CYDEV_PHUB_TDMEM18_ORIG_TD1 EQU 0x40007894\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_BASE\r
+CYDEV_PHUB_TDMEM19_BASE EQU 0x40007898\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_SIZE\r
+CYDEV_PHUB_TDMEM19_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_ORIG_TD0\r
+CYDEV_PHUB_TDMEM19_ORIG_TD0 EQU 0x40007898\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_ORIG_TD1\r
+CYDEV_PHUB_TDMEM19_ORIG_TD1 EQU 0x4000789c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_BASE\r
+CYDEV_PHUB_TDMEM20_BASE EQU 0x400078a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_SIZE\r
+CYDEV_PHUB_TDMEM20_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_ORIG_TD0\r
+CYDEV_PHUB_TDMEM20_ORIG_TD0 EQU 0x400078a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_ORIG_TD1\r
+CYDEV_PHUB_TDMEM20_ORIG_TD1 EQU 0x400078a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_BASE\r
+CYDEV_PHUB_TDMEM21_BASE EQU 0x400078a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_SIZE\r
+CYDEV_PHUB_TDMEM21_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_ORIG_TD0\r
+CYDEV_PHUB_TDMEM21_ORIG_TD0 EQU 0x400078a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_ORIG_TD1\r
+CYDEV_PHUB_TDMEM21_ORIG_TD1 EQU 0x400078ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_BASE\r
+CYDEV_PHUB_TDMEM22_BASE EQU 0x400078b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_SIZE\r
+CYDEV_PHUB_TDMEM22_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_ORIG_TD0\r
+CYDEV_PHUB_TDMEM22_ORIG_TD0 EQU 0x400078b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_ORIG_TD1\r
+CYDEV_PHUB_TDMEM22_ORIG_TD1 EQU 0x400078b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_BASE\r
+CYDEV_PHUB_TDMEM23_BASE EQU 0x400078b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_SIZE\r
+CYDEV_PHUB_TDMEM23_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_ORIG_TD0\r
+CYDEV_PHUB_TDMEM23_ORIG_TD0 EQU 0x400078b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_ORIG_TD1\r
+CYDEV_PHUB_TDMEM23_ORIG_TD1 EQU 0x400078bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_BASE\r
+CYDEV_PHUB_TDMEM24_BASE EQU 0x400078c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_SIZE\r
+CYDEV_PHUB_TDMEM24_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_ORIG_TD0\r
+CYDEV_PHUB_TDMEM24_ORIG_TD0 EQU 0x400078c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_ORIG_TD1\r
+CYDEV_PHUB_TDMEM24_ORIG_TD1 EQU 0x400078c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_BASE\r
+CYDEV_PHUB_TDMEM25_BASE EQU 0x400078c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_SIZE\r
+CYDEV_PHUB_TDMEM25_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_ORIG_TD0\r
+CYDEV_PHUB_TDMEM25_ORIG_TD0 EQU 0x400078c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_ORIG_TD1\r
+CYDEV_PHUB_TDMEM25_ORIG_TD1 EQU 0x400078cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_BASE\r
+CYDEV_PHUB_TDMEM26_BASE EQU 0x400078d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_SIZE\r
+CYDEV_PHUB_TDMEM26_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_ORIG_TD0\r
+CYDEV_PHUB_TDMEM26_ORIG_TD0 EQU 0x400078d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_ORIG_TD1\r
+CYDEV_PHUB_TDMEM26_ORIG_TD1 EQU 0x400078d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_BASE\r
+CYDEV_PHUB_TDMEM27_BASE EQU 0x400078d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_SIZE\r
+CYDEV_PHUB_TDMEM27_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_ORIG_TD0\r
+CYDEV_PHUB_TDMEM27_ORIG_TD0 EQU 0x400078d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_ORIG_TD1\r
+CYDEV_PHUB_TDMEM27_ORIG_TD1 EQU 0x400078dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_BASE\r
+CYDEV_PHUB_TDMEM28_BASE EQU 0x400078e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_SIZE\r
+CYDEV_PHUB_TDMEM28_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_ORIG_TD0\r
+CYDEV_PHUB_TDMEM28_ORIG_TD0 EQU 0x400078e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_ORIG_TD1\r
+CYDEV_PHUB_TDMEM28_ORIG_TD1 EQU 0x400078e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_BASE\r
+CYDEV_PHUB_TDMEM29_BASE EQU 0x400078e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_SIZE\r
+CYDEV_PHUB_TDMEM29_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_ORIG_TD0\r
+CYDEV_PHUB_TDMEM29_ORIG_TD0 EQU 0x400078e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_ORIG_TD1\r
+CYDEV_PHUB_TDMEM29_ORIG_TD1 EQU 0x400078ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_BASE\r
+CYDEV_PHUB_TDMEM30_BASE EQU 0x400078f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_SIZE\r
+CYDEV_PHUB_TDMEM30_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_ORIG_TD0\r
+CYDEV_PHUB_TDMEM30_ORIG_TD0 EQU 0x400078f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_ORIG_TD1\r
+CYDEV_PHUB_TDMEM30_ORIG_TD1 EQU 0x400078f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_BASE\r
+CYDEV_PHUB_TDMEM31_BASE EQU 0x400078f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_SIZE\r
+CYDEV_PHUB_TDMEM31_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_ORIG_TD0\r
+CYDEV_PHUB_TDMEM31_ORIG_TD0 EQU 0x400078f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_ORIG_TD1\r
+CYDEV_PHUB_TDMEM31_ORIG_TD1 EQU 0x400078fc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_BASE\r
+CYDEV_PHUB_TDMEM32_BASE EQU 0x40007900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_SIZE\r
+CYDEV_PHUB_TDMEM32_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_ORIG_TD0\r
+CYDEV_PHUB_TDMEM32_ORIG_TD0 EQU 0x40007900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_ORIG_TD1\r
+CYDEV_PHUB_TDMEM32_ORIG_TD1 EQU 0x40007904\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_BASE\r
+CYDEV_PHUB_TDMEM33_BASE EQU 0x40007908\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_SIZE\r
+CYDEV_PHUB_TDMEM33_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_ORIG_TD0\r
+CYDEV_PHUB_TDMEM33_ORIG_TD0 EQU 0x40007908\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_ORIG_TD1\r
+CYDEV_PHUB_TDMEM33_ORIG_TD1 EQU 0x4000790c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_BASE\r
+CYDEV_PHUB_TDMEM34_BASE EQU 0x40007910\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_SIZE\r
+CYDEV_PHUB_TDMEM34_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_ORIG_TD0\r
+CYDEV_PHUB_TDMEM34_ORIG_TD0 EQU 0x40007910\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_ORIG_TD1\r
+CYDEV_PHUB_TDMEM34_ORIG_TD1 EQU 0x40007914\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_BASE\r
+CYDEV_PHUB_TDMEM35_BASE EQU 0x40007918\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_SIZE\r
+CYDEV_PHUB_TDMEM35_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_ORIG_TD0\r
+CYDEV_PHUB_TDMEM35_ORIG_TD0 EQU 0x40007918\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_ORIG_TD1\r
+CYDEV_PHUB_TDMEM35_ORIG_TD1 EQU 0x4000791c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_BASE\r
+CYDEV_PHUB_TDMEM36_BASE EQU 0x40007920\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_SIZE\r
+CYDEV_PHUB_TDMEM36_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_ORIG_TD0\r
+CYDEV_PHUB_TDMEM36_ORIG_TD0 EQU 0x40007920\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_ORIG_TD1\r
+CYDEV_PHUB_TDMEM36_ORIG_TD1 EQU 0x40007924\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_BASE\r
+CYDEV_PHUB_TDMEM37_BASE EQU 0x40007928\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_SIZE\r
+CYDEV_PHUB_TDMEM37_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_ORIG_TD0\r
+CYDEV_PHUB_TDMEM37_ORIG_TD0 EQU 0x40007928\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_ORIG_TD1\r
+CYDEV_PHUB_TDMEM37_ORIG_TD1 EQU 0x4000792c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_BASE\r
+CYDEV_PHUB_TDMEM38_BASE EQU 0x40007930\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_SIZE\r
+CYDEV_PHUB_TDMEM38_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_ORIG_TD0\r
+CYDEV_PHUB_TDMEM38_ORIG_TD0 EQU 0x40007930\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_ORIG_TD1\r
+CYDEV_PHUB_TDMEM38_ORIG_TD1 EQU 0x40007934\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_BASE\r
+CYDEV_PHUB_TDMEM39_BASE EQU 0x40007938\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_SIZE\r
+CYDEV_PHUB_TDMEM39_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_ORIG_TD0\r
+CYDEV_PHUB_TDMEM39_ORIG_TD0 EQU 0x40007938\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_ORIG_TD1\r
+CYDEV_PHUB_TDMEM39_ORIG_TD1 EQU 0x4000793c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_BASE\r
+CYDEV_PHUB_TDMEM40_BASE EQU 0x40007940\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_SIZE\r
+CYDEV_PHUB_TDMEM40_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_ORIG_TD0\r
+CYDEV_PHUB_TDMEM40_ORIG_TD0 EQU 0x40007940\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_ORIG_TD1\r
+CYDEV_PHUB_TDMEM40_ORIG_TD1 EQU 0x40007944\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_BASE\r
+CYDEV_PHUB_TDMEM41_BASE EQU 0x40007948\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_SIZE\r
+CYDEV_PHUB_TDMEM41_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_ORIG_TD0\r
+CYDEV_PHUB_TDMEM41_ORIG_TD0 EQU 0x40007948\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_ORIG_TD1\r
+CYDEV_PHUB_TDMEM41_ORIG_TD1 EQU 0x4000794c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_BASE\r
+CYDEV_PHUB_TDMEM42_BASE EQU 0x40007950\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_SIZE\r
+CYDEV_PHUB_TDMEM42_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_ORIG_TD0\r
+CYDEV_PHUB_TDMEM42_ORIG_TD0 EQU 0x40007950\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_ORIG_TD1\r
+CYDEV_PHUB_TDMEM42_ORIG_TD1 EQU 0x40007954\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_BASE\r
+CYDEV_PHUB_TDMEM43_BASE EQU 0x40007958\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_SIZE\r
+CYDEV_PHUB_TDMEM43_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_ORIG_TD0\r
+CYDEV_PHUB_TDMEM43_ORIG_TD0 EQU 0x40007958\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_ORIG_TD1\r
+CYDEV_PHUB_TDMEM43_ORIG_TD1 EQU 0x4000795c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_BASE\r
+CYDEV_PHUB_TDMEM44_BASE EQU 0x40007960\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_SIZE\r
+CYDEV_PHUB_TDMEM44_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_ORIG_TD0\r
+CYDEV_PHUB_TDMEM44_ORIG_TD0 EQU 0x40007960\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_ORIG_TD1\r
+CYDEV_PHUB_TDMEM44_ORIG_TD1 EQU 0x40007964\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_BASE\r
+CYDEV_PHUB_TDMEM45_BASE EQU 0x40007968\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_SIZE\r
+CYDEV_PHUB_TDMEM45_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_ORIG_TD0\r
+CYDEV_PHUB_TDMEM45_ORIG_TD0 EQU 0x40007968\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_ORIG_TD1\r
+CYDEV_PHUB_TDMEM45_ORIG_TD1 EQU 0x4000796c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_BASE\r
+CYDEV_PHUB_TDMEM46_BASE EQU 0x40007970\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_SIZE\r
+CYDEV_PHUB_TDMEM46_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_ORIG_TD0\r
+CYDEV_PHUB_TDMEM46_ORIG_TD0 EQU 0x40007970\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_ORIG_TD1\r
+CYDEV_PHUB_TDMEM46_ORIG_TD1 EQU 0x40007974\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_BASE\r
+CYDEV_PHUB_TDMEM47_BASE EQU 0x40007978\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_SIZE\r
+CYDEV_PHUB_TDMEM47_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_ORIG_TD0\r
+CYDEV_PHUB_TDMEM47_ORIG_TD0 EQU 0x40007978\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_ORIG_TD1\r
+CYDEV_PHUB_TDMEM47_ORIG_TD1 EQU 0x4000797c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_BASE\r
+CYDEV_PHUB_TDMEM48_BASE EQU 0x40007980\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_SIZE\r
+CYDEV_PHUB_TDMEM48_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_ORIG_TD0\r
+CYDEV_PHUB_TDMEM48_ORIG_TD0 EQU 0x40007980\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_ORIG_TD1\r
+CYDEV_PHUB_TDMEM48_ORIG_TD1 EQU 0x40007984\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_BASE\r
+CYDEV_PHUB_TDMEM49_BASE EQU 0x40007988\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_SIZE\r
+CYDEV_PHUB_TDMEM49_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_ORIG_TD0\r
+CYDEV_PHUB_TDMEM49_ORIG_TD0 EQU 0x40007988\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_ORIG_TD1\r
+CYDEV_PHUB_TDMEM49_ORIG_TD1 EQU 0x4000798c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_BASE\r
+CYDEV_PHUB_TDMEM50_BASE EQU 0x40007990\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_SIZE\r
+CYDEV_PHUB_TDMEM50_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_ORIG_TD0\r
+CYDEV_PHUB_TDMEM50_ORIG_TD0 EQU 0x40007990\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_ORIG_TD1\r
+CYDEV_PHUB_TDMEM50_ORIG_TD1 EQU 0x40007994\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_BASE\r
+CYDEV_PHUB_TDMEM51_BASE EQU 0x40007998\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_SIZE\r
+CYDEV_PHUB_TDMEM51_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_ORIG_TD0\r
+CYDEV_PHUB_TDMEM51_ORIG_TD0 EQU 0x40007998\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_ORIG_TD1\r
+CYDEV_PHUB_TDMEM51_ORIG_TD1 EQU 0x4000799c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_BASE\r
+CYDEV_PHUB_TDMEM52_BASE EQU 0x400079a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_SIZE\r
+CYDEV_PHUB_TDMEM52_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_ORIG_TD0\r
+CYDEV_PHUB_TDMEM52_ORIG_TD0 EQU 0x400079a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_ORIG_TD1\r
+CYDEV_PHUB_TDMEM52_ORIG_TD1 EQU 0x400079a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_BASE\r
+CYDEV_PHUB_TDMEM53_BASE EQU 0x400079a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_SIZE\r
+CYDEV_PHUB_TDMEM53_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_ORIG_TD0\r
+CYDEV_PHUB_TDMEM53_ORIG_TD0 EQU 0x400079a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_ORIG_TD1\r
+CYDEV_PHUB_TDMEM53_ORIG_TD1 EQU 0x400079ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_BASE\r
+CYDEV_PHUB_TDMEM54_BASE EQU 0x400079b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_SIZE\r
+CYDEV_PHUB_TDMEM54_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_ORIG_TD0\r
+CYDEV_PHUB_TDMEM54_ORIG_TD0 EQU 0x400079b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_ORIG_TD1\r
+CYDEV_PHUB_TDMEM54_ORIG_TD1 EQU 0x400079b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_BASE\r
+CYDEV_PHUB_TDMEM55_BASE EQU 0x400079b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_SIZE\r
+CYDEV_PHUB_TDMEM55_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_ORIG_TD0\r
+CYDEV_PHUB_TDMEM55_ORIG_TD0 EQU 0x400079b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_ORIG_TD1\r
+CYDEV_PHUB_TDMEM55_ORIG_TD1 EQU 0x400079bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_BASE\r
+CYDEV_PHUB_TDMEM56_BASE EQU 0x400079c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_SIZE\r
+CYDEV_PHUB_TDMEM56_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_ORIG_TD0\r
+CYDEV_PHUB_TDMEM56_ORIG_TD0 EQU 0x400079c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_ORIG_TD1\r
+CYDEV_PHUB_TDMEM56_ORIG_TD1 EQU 0x400079c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_BASE\r
+CYDEV_PHUB_TDMEM57_BASE EQU 0x400079c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_SIZE\r
+CYDEV_PHUB_TDMEM57_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_ORIG_TD0\r
+CYDEV_PHUB_TDMEM57_ORIG_TD0 EQU 0x400079c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_ORIG_TD1\r
+CYDEV_PHUB_TDMEM57_ORIG_TD1 EQU 0x400079cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_BASE\r
+CYDEV_PHUB_TDMEM58_BASE EQU 0x400079d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_SIZE\r
+CYDEV_PHUB_TDMEM58_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_ORIG_TD0\r
+CYDEV_PHUB_TDMEM58_ORIG_TD0 EQU 0x400079d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_ORIG_TD1\r
+CYDEV_PHUB_TDMEM58_ORIG_TD1 EQU 0x400079d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_BASE\r
+CYDEV_PHUB_TDMEM59_BASE EQU 0x400079d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_SIZE\r
+CYDEV_PHUB_TDMEM59_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_ORIG_TD0\r
+CYDEV_PHUB_TDMEM59_ORIG_TD0 EQU 0x400079d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_ORIG_TD1\r
+CYDEV_PHUB_TDMEM59_ORIG_TD1 EQU 0x400079dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_BASE\r
+CYDEV_PHUB_TDMEM60_BASE EQU 0x400079e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_SIZE\r
+CYDEV_PHUB_TDMEM60_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_ORIG_TD0\r
+CYDEV_PHUB_TDMEM60_ORIG_TD0 EQU 0x400079e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_ORIG_TD1\r
+CYDEV_PHUB_TDMEM60_ORIG_TD1 EQU 0x400079e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_BASE\r
+CYDEV_PHUB_TDMEM61_BASE EQU 0x400079e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_SIZE\r
+CYDEV_PHUB_TDMEM61_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_ORIG_TD0\r
+CYDEV_PHUB_TDMEM61_ORIG_TD0 EQU 0x400079e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_ORIG_TD1\r
+CYDEV_PHUB_TDMEM61_ORIG_TD1 EQU 0x400079ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_BASE\r
+CYDEV_PHUB_TDMEM62_BASE EQU 0x400079f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_SIZE\r
+CYDEV_PHUB_TDMEM62_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_ORIG_TD0\r
+CYDEV_PHUB_TDMEM62_ORIG_TD0 EQU 0x400079f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_ORIG_TD1\r
+CYDEV_PHUB_TDMEM62_ORIG_TD1 EQU 0x400079f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_BASE\r
+CYDEV_PHUB_TDMEM63_BASE EQU 0x400079f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_SIZE\r
+CYDEV_PHUB_TDMEM63_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_ORIG_TD0\r
+CYDEV_PHUB_TDMEM63_ORIG_TD0 EQU 0x400079f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_ORIG_TD1\r
+CYDEV_PHUB_TDMEM63_ORIG_TD1 EQU 0x400079fc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_BASE\r
+CYDEV_PHUB_TDMEM64_BASE EQU 0x40007a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_SIZE\r
+CYDEV_PHUB_TDMEM64_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_ORIG_TD0\r
+CYDEV_PHUB_TDMEM64_ORIG_TD0 EQU 0x40007a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_ORIG_TD1\r
+CYDEV_PHUB_TDMEM64_ORIG_TD1 EQU 0x40007a04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_BASE\r
+CYDEV_PHUB_TDMEM65_BASE EQU 0x40007a08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_SIZE\r
+CYDEV_PHUB_TDMEM65_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_ORIG_TD0\r
+CYDEV_PHUB_TDMEM65_ORIG_TD0 EQU 0x40007a08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_ORIG_TD1\r
+CYDEV_PHUB_TDMEM65_ORIG_TD1 EQU 0x40007a0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_BASE\r
+CYDEV_PHUB_TDMEM66_BASE EQU 0x40007a10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_SIZE\r
+CYDEV_PHUB_TDMEM66_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_ORIG_TD0\r
+CYDEV_PHUB_TDMEM66_ORIG_TD0 EQU 0x40007a10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_ORIG_TD1\r
+CYDEV_PHUB_TDMEM66_ORIG_TD1 EQU 0x40007a14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_BASE\r
+CYDEV_PHUB_TDMEM67_BASE EQU 0x40007a18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_SIZE\r
+CYDEV_PHUB_TDMEM67_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_ORIG_TD0\r
+CYDEV_PHUB_TDMEM67_ORIG_TD0 EQU 0x40007a18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_ORIG_TD1\r
+CYDEV_PHUB_TDMEM67_ORIG_TD1 EQU 0x40007a1c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_BASE\r
+CYDEV_PHUB_TDMEM68_BASE EQU 0x40007a20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_SIZE\r
+CYDEV_PHUB_TDMEM68_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_ORIG_TD0\r
+CYDEV_PHUB_TDMEM68_ORIG_TD0 EQU 0x40007a20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_ORIG_TD1\r
+CYDEV_PHUB_TDMEM68_ORIG_TD1 EQU 0x40007a24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_BASE\r
+CYDEV_PHUB_TDMEM69_BASE EQU 0x40007a28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_SIZE\r
+CYDEV_PHUB_TDMEM69_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_ORIG_TD0\r
+CYDEV_PHUB_TDMEM69_ORIG_TD0 EQU 0x40007a28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_ORIG_TD1\r
+CYDEV_PHUB_TDMEM69_ORIG_TD1 EQU 0x40007a2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_BASE\r
+CYDEV_PHUB_TDMEM70_BASE EQU 0x40007a30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_SIZE\r
+CYDEV_PHUB_TDMEM70_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_ORIG_TD0\r
+CYDEV_PHUB_TDMEM70_ORIG_TD0 EQU 0x40007a30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_ORIG_TD1\r
+CYDEV_PHUB_TDMEM70_ORIG_TD1 EQU 0x40007a34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_BASE\r
+CYDEV_PHUB_TDMEM71_BASE EQU 0x40007a38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_SIZE\r
+CYDEV_PHUB_TDMEM71_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_ORIG_TD0\r
+CYDEV_PHUB_TDMEM71_ORIG_TD0 EQU 0x40007a38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_ORIG_TD1\r
+CYDEV_PHUB_TDMEM71_ORIG_TD1 EQU 0x40007a3c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_BASE\r
+CYDEV_PHUB_TDMEM72_BASE EQU 0x40007a40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_SIZE\r
+CYDEV_PHUB_TDMEM72_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_ORIG_TD0\r
+CYDEV_PHUB_TDMEM72_ORIG_TD0 EQU 0x40007a40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_ORIG_TD1\r
+CYDEV_PHUB_TDMEM72_ORIG_TD1 EQU 0x40007a44\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_BASE\r
+CYDEV_PHUB_TDMEM73_BASE EQU 0x40007a48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_SIZE\r
+CYDEV_PHUB_TDMEM73_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_ORIG_TD0\r
+CYDEV_PHUB_TDMEM73_ORIG_TD0 EQU 0x40007a48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_ORIG_TD1\r
+CYDEV_PHUB_TDMEM73_ORIG_TD1 EQU 0x40007a4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_BASE\r
+CYDEV_PHUB_TDMEM74_BASE EQU 0x40007a50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_SIZE\r
+CYDEV_PHUB_TDMEM74_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_ORIG_TD0\r
+CYDEV_PHUB_TDMEM74_ORIG_TD0 EQU 0x40007a50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_ORIG_TD1\r
+CYDEV_PHUB_TDMEM74_ORIG_TD1 EQU 0x40007a54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_BASE\r
+CYDEV_PHUB_TDMEM75_BASE EQU 0x40007a58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_SIZE\r
+CYDEV_PHUB_TDMEM75_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_ORIG_TD0\r
+CYDEV_PHUB_TDMEM75_ORIG_TD0 EQU 0x40007a58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_ORIG_TD1\r
+CYDEV_PHUB_TDMEM75_ORIG_TD1 EQU 0x40007a5c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_BASE\r
+CYDEV_PHUB_TDMEM76_BASE EQU 0x40007a60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_SIZE\r
+CYDEV_PHUB_TDMEM76_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_ORIG_TD0\r
+CYDEV_PHUB_TDMEM76_ORIG_TD0 EQU 0x40007a60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_ORIG_TD1\r
+CYDEV_PHUB_TDMEM76_ORIG_TD1 EQU 0x40007a64\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_BASE\r
+CYDEV_PHUB_TDMEM77_BASE EQU 0x40007a68\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_SIZE\r
+CYDEV_PHUB_TDMEM77_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_ORIG_TD0\r
+CYDEV_PHUB_TDMEM77_ORIG_TD0 EQU 0x40007a68\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_ORIG_TD1\r
+CYDEV_PHUB_TDMEM77_ORIG_TD1 EQU 0x40007a6c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_BASE\r
+CYDEV_PHUB_TDMEM78_BASE EQU 0x40007a70\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_SIZE\r
+CYDEV_PHUB_TDMEM78_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_ORIG_TD0\r
+CYDEV_PHUB_TDMEM78_ORIG_TD0 EQU 0x40007a70\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_ORIG_TD1\r
+CYDEV_PHUB_TDMEM78_ORIG_TD1 EQU 0x40007a74\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_BASE\r
+CYDEV_PHUB_TDMEM79_BASE EQU 0x40007a78\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_SIZE\r
+CYDEV_PHUB_TDMEM79_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_ORIG_TD0\r
+CYDEV_PHUB_TDMEM79_ORIG_TD0 EQU 0x40007a78\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_ORIG_TD1\r
+CYDEV_PHUB_TDMEM79_ORIG_TD1 EQU 0x40007a7c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_BASE\r
+CYDEV_PHUB_TDMEM80_BASE EQU 0x40007a80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_SIZE\r
+CYDEV_PHUB_TDMEM80_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_ORIG_TD0\r
+CYDEV_PHUB_TDMEM80_ORIG_TD0 EQU 0x40007a80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_ORIG_TD1\r
+CYDEV_PHUB_TDMEM80_ORIG_TD1 EQU 0x40007a84\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_BASE\r
+CYDEV_PHUB_TDMEM81_BASE EQU 0x40007a88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_SIZE\r
+CYDEV_PHUB_TDMEM81_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_ORIG_TD0\r
+CYDEV_PHUB_TDMEM81_ORIG_TD0 EQU 0x40007a88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_ORIG_TD1\r
+CYDEV_PHUB_TDMEM81_ORIG_TD1 EQU 0x40007a8c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_BASE\r
+CYDEV_PHUB_TDMEM82_BASE EQU 0x40007a90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_SIZE\r
+CYDEV_PHUB_TDMEM82_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_ORIG_TD0\r
+CYDEV_PHUB_TDMEM82_ORIG_TD0 EQU 0x40007a90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_ORIG_TD1\r
+CYDEV_PHUB_TDMEM82_ORIG_TD1 EQU 0x40007a94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_BASE\r
+CYDEV_PHUB_TDMEM83_BASE EQU 0x40007a98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_SIZE\r
+CYDEV_PHUB_TDMEM83_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_ORIG_TD0\r
+CYDEV_PHUB_TDMEM83_ORIG_TD0 EQU 0x40007a98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_ORIG_TD1\r
+CYDEV_PHUB_TDMEM83_ORIG_TD1 EQU 0x40007a9c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_BASE\r
+CYDEV_PHUB_TDMEM84_BASE EQU 0x40007aa0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_SIZE\r
+CYDEV_PHUB_TDMEM84_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_ORIG_TD0\r
+CYDEV_PHUB_TDMEM84_ORIG_TD0 EQU 0x40007aa0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_ORIG_TD1\r
+CYDEV_PHUB_TDMEM84_ORIG_TD1 EQU 0x40007aa4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_BASE\r
+CYDEV_PHUB_TDMEM85_BASE EQU 0x40007aa8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_SIZE\r
+CYDEV_PHUB_TDMEM85_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_ORIG_TD0\r
+CYDEV_PHUB_TDMEM85_ORIG_TD0 EQU 0x40007aa8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_ORIG_TD1\r
+CYDEV_PHUB_TDMEM85_ORIG_TD1 EQU 0x40007aac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_BASE\r
+CYDEV_PHUB_TDMEM86_BASE EQU 0x40007ab0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_SIZE\r
+CYDEV_PHUB_TDMEM86_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_ORIG_TD0\r
+CYDEV_PHUB_TDMEM86_ORIG_TD0 EQU 0x40007ab0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_ORIG_TD1\r
+CYDEV_PHUB_TDMEM86_ORIG_TD1 EQU 0x40007ab4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_BASE\r
+CYDEV_PHUB_TDMEM87_BASE EQU 0x40007ab8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_SIZE\r
+CYDEV_PHUB_TDMEM87_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_ORIG_TD0\r
+CYDEV_PHUB_TDMEM87_ORIG_TD0 EQU 0x40007ab8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_ORIG_TD1\r
+CYDEV_PHUB_TDMEM87_ORIG_TD1 EQU 0x40007abc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_BASE\r
+CYDEV_PHUB_TDMEM88_BASE EQU 0x40007ac0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_SIZE\r
+CYDEV_PHUB_TDMEM88_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_ORIG_TD0\r
+CYDEV_PHUB_TDMEM88_ORIG_TD0 EQU 0x40007ac0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_ORIG_TD1\r
+CYDEV_PHUB_TDMEM88_ORIG_TD1 EQU 0x40007ac4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_BASE\r
+CYDEV_PHUB_TDMEM89_BASE EQU 0x40007ac8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_SIZE\r
+CYDEV_PHUB_TDMEM89_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_ORIG_TD0\r
+CYDEV_PHUB_TDMEM89_ORIG_TD0 EQU 0x40007ac8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_ORIG_TD1\r
+CYDEV_PHUB_TDMEM89_ORIG_TD1 EQU 0x40007acc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_BASE\r
+CYDEV_PHUB_TDMEM90_BASE EQU 0x40007ad0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_SIZE\r
+CYDEV_PHUB_TDMEM90_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_ORIG_TD0\r
+CYDEV_PHUB_TDMEM90_ORIG_TD0 EQU 0x40007ad0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_ORIG_TD1\r
+CYDEV_PHUB_TDMEM90_ORIG_TD1 EQU 0x40007ad4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_BASE\r
+CYDEV_PHUB_TDMEM91_BASE EQU 0x40007ad8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_SIZE\r
+CYDEV_PHUB_TDMEM91_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_ORIG_TD0\r
+CYDEV_PHUB_TDMEM91_ORIG_TD0 EQU 0x40007ad8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_ORIG_TD1\r
+CYDEV_PHUB_TDMEM91_ORIG_TD1 EQU 0x40007adc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_BASE\r
+CYDEV_PHUB_TDMEM92_BASE EQU 0x40007ae0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_SIZE\r
+CYDEV_PHUB_TDMEM92_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_ORIG_TD0\r
+CYDEV_PHUB_TDMEM92_ORIG_TD0 EQU 0x40007ae0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_ORIG_TD1\r
+CYDEV_PHUB_TDMEM92_ORIG_TD1 EQU 0x40007ae4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_BASE\r
+CYDEV_PHUB_TDMEM93_BASE EQU 0x40007ae8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_SIZE\r
+CYDEV_PHUB_TDMEM93_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_ORIG_TD0\r
+CYDEV_PHUB_TDMEM93_ORIG_TD0 EQU 0x40007ae8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_ORIG_TD1\r
+CYDEV_PHUB_TDMEM93_ORIG_TD1 EQU 0x40007aec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_BASE\r
+CYDEV_PHUB_TDMEM94_BASE EQU 0x40007af0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_SIZE\r
+CYDEV_PHUB_TDMEM94_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_ORIG_TD0\r
+CYDEV_PHUB_TDMEM94_ORIG_TD0 EQU 0x40007af0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_ORIG_TD1\r
+CYDEV_PHUB_TDMEM94_ORIG_TD1 EQU 0x40007af4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_BASE\r
+CYDEV_PHUB_TDMEM95_BASE EQU 0x40007af8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_SIZE\r
+CYDEV_PHUB_TDMEM95_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_ORIG_TD0\r
+CYDEV_PHUB_TDMEM95_ORIG_TD0 EQU 0x40007af8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_ORIG_TD1\r
+CYDEV_PHUB_TDMEM95_ORIG_TD1 EQU 0x40007afc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_BASE\r
+CYDEV_PHUB_TDMEM96_BASE EQU 0x40007b00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_SIZE\r
+CYDEV_PHUB_TDMEM96_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_ORIG_TD0\r
+CYDEV_PHUB_TDMEM96_ORIG_TD0 EQU 0x40007b00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_ORIG_TD1\r
+CYDEV_PHUB_TDMEM96_ORIG_TD1 EQU 0x40007b04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_BASE\r
+CYDEV_PHUB_TDMEM97_BASE EQU 0x40007b08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_SIZE\r
+CYDEV_PHUB_TDMEM97_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_ORIG_TD0\r
+CYDEV_PHUB_TDMEM97_ORIG_TD0 EQU 0x40007b08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_ORIG_TD1\r
+CYDEV_PHUB_TDMEM97_ORIG_TD1 EQU 0x40007b0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_BASE\r
+CYDEV_PHUB_TDMEM98_BASE EQU 0x40007b10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_SIZE\r
+CYDEV_PHUB_TDMEM98_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_ORIG_TD0\r
+CYDEV_PHUB_TDMEM98_ORIG_TD0 EQU 0x40007b10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_ORIG_TD1\r
+CYDEV_PHUB_TDMEM98_ORIG_TD1 EQU 0x40007b14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_BASE\r
+CYDEV_PHUB_TDMEM99_BASE EQU 0x40007b18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_SIZE\r
+CYDEV_PHUB_TDMEM99_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_ORIG_TD0\r
+CYDEV_PHUB_TDMEM99_ORIG_TD0 EQU 0x40007b18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_ORIG_TD1\r
+CYDEV_PHUB_TDMEM99_ORIG_TD1 EQU 0x40007b1c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_BASE\r
+CYDEV_PHUB_TDMEM100_BASE EQU 0x40007b20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_SIZE\r
+CYDEV_PHUB_TDMEM100_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_ORIG_TD0\r
+CYDEV_PHUB_TDMEM100_ORIG_TD0 EQU 0x40007b20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_ORIG_TD1\r
+CYDEV_PHUB_TDMEM100_ORIG_TD1 EQU 0x40007b24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_BASE\r
+CYDEV_PHUB_TDMEM101_BASE EQU 0x40007b28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_SIZE\r
+CYDEV_PHUB_TDMEM101_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_ORIG_TD0\r
+CYDEV_PHUB_TDMEM101_ORIG_TD0 EQU 0x40007b28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_ORIG_TD1\r
+CYDEV_PHUB_TDMEM101_ORIG_TD1 EQU 0x40007b2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_BASE\r
+CYDEV_PHUB_TDMEM102_BASE EQU 0x40007b30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_SIZE\r
+CYDEV_PHUB_TDMEM102_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_ORIG_TD0\r
+CYDEV_PHUB_TDMEM102_ORIG_TD0 EQU 0x40007b30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_ORIG_TD1\r
+CYDEV_PHUB_TDMEM102_ORIG_TD1 EQU 0x40007b34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_BASE\r
+CYDEV_PHUB_TDMEM103_BASE EQU 0x40007b38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_SIZE\r
+CYDEV_PHUB_TDMEM103_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_ORIG_TD0\r
+CYDEV_PHUB_TDMEM103_ORIG_TD0 EQU 0x40007b38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_ORIG_TD1\r
+CYDEV_PHUB_TDMEM103_ORIG_TD1 EQU 0x40007b3c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_BASE\r
+CYDEV_PHUB_TDMEM104_BASE EQU 0x40007b40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_SIZE\r
+CYDEV_PHUB_TDMEM104_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_ORIG_TD0\r
+CYDEV_PHUB_TDMEM104_ORIG_TD0 EQU 0x40007b40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_ORIG_TD1\r
+CYDEV_PHUB_TDMEM104_ORIG_TD1 EQU 0x40007b44\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_BASE\r
+CYDEV_PHUB_TDMEM105_BASE EQU 0x40007b48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_SIZE\r
+CYDEV_PHUB_TDMEM105_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_ORIG_TD0\r
+CYDEV_PHUB_TDMEM105_ORIG_TD0 EQU 0x40007b48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_ORIG_TD1\r
+CYDEV_PHUB_TDMEM105_ORIG_TD1 EQU 0x40007b4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_BASE\r
+CYDEV_PHUB_TDMEM106_BASE EQU 0x40007b50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_SIZE\r
+CYDEV_PHUB_TDMEM106_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_ORIG_TD0\r
+CYDEV_PHUB_TDMEM106_ORIG_TD0 EQU 0x40007b50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_ORIG_TD1\r
+CYDEV_PHUB_TDMEM106_ORIG_TD1 EQU 0x40007b54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_BASE\r
+CYDEV_PHUB_TDMEM107_BASE EQU 0x40007b58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_SIZE\r
+CYDEV_PHUB_TDMEM107_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_ORIG_TD0\r
+CYDEV_PHUB_TDMEM107_ORIG_TD0 EQU 0x40007b58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_ORIG_TD1\r
+CYDEV_PHUB_TDMEM107_ORIG_TD1 EQU 0x40007b5c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_BASE\r
+CYDEV_PHUB_TDMEM108_BASE EQU 0x40007b60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_SIZE\r
+CYDEV_PHUB_TDMEM108_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_ORIG_TD0\r
+CYDEV_PHUB_TDMEM108_ORIG_TD0 EQU 0x40007b60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_ORIG_TD1\r
+CYDEV_PHUB_TDMEM108_ORIG_TD1 EQU 0x40007b64\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_BASE\r
+CYDEV_PHUB_TDMEM109_BASE EQU 0x40007b68\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_SIZE\r
+CYDEV_PHUB_TDMEM109_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_ORIG_TD0\r
+CYDEV_PHUB_TDMEM109_ORIG_TD0 EQU 0x40007b68\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_ORIG_TD1\r
+CYDEV_PHUB_TDMEM109_ORIG_TD1 EQU 0x40007b6c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_BASE\r
+CYDEV_PHUB_TDMEM110_BASE EQU 0x40007b70\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_SIZE\r
+CYDEV_PHUB_TDMEM110_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_ORIG_TD0\r
+CYDEV_PHUB_TDMEM110_ORIG_TD0 EQU 0x40007b70\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_ORIG_TD1\r
+CYDEV_PHUB_TDMEM110_ORIG_TD1 EQU 0x40007b74\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_BASE\r
+CYDEV_PHUB_TDMEM111_BASE EQU 0x40007b78\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_SIZE\r
+CYDEV_PHUB_TDMEM111_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_ORIG_TD0\r
+CYDEV_PHUB_TDMEM111_ORIG_TD0 EQU 0x40007b78\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_ORIG_TD1\r
+CYDEV_PHUB_TDMEM111_ORIG_TD1 EQU 0x40007b7c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_BASE\r
+CYDEV_PHUB_TDMEM112_BASE EQU 0x40007b80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_SIZE\r
+CYDEV_PHUB_TDMEM112_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_ORIG_TD0\r
+CYDEV_PHUB_TDMEM112_ORIG_TD0 EQU 0x40007b80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_ORIG_TD1\r
+CYDEV_PHUB_TDMEM112_ORIG_TD1 EQU 0x40007b84\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_BASE\r
+CYDEV_PHUB_TDMEM113_BASE EQU 0x40007b88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_SIZE\r
+CYDEV_PHUB_TDMEM113_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_ORIG_TD0\r
+CYDEV_PHUB_TDMEM113_ORIG_TD0 EQU 0x40007b88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_ORIG_TD1\r
+CYDEV_PHUB_TDMEM113_ORIG_TD1 EQU 0x40007b8c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_BASE\r
+CYDEV_PHUB_TDMEM114_BASE EQU 0x40007b90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_SIZE\r
+CYDEV_PHUB_TDMEM114_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_ORIG_TD0\r
+CYDEV_PHUB_TDMEM114_ORIG_TD0 EQU 0x40007b90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_ORIG_TD1\r
+CYDEV_PHUB_TDMEM114_ORIG_TD1 EQU 0x40007b94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_BASE\r
+CYDEV_PHUB_TDMEM115_BASE EQU 0x40007b98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_SIZE\r
+CYDEV_PHUB_TDMEM115_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_ORIG_TD0\r
+CYDEV_PHUB_TDMEM115_ORIG_TD0 EQU 0x40007b98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_ORIG_TD1\r
+CYDEV_PHUB_TDMEM115_ORIG_TD1 EQU 0x40007b9c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_BASE\r
+CYDEV_PHUB_TDMEM116_BASE EQU 0x40007ba0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_SIZE\r
+CYDEV_PHUB_TDMEM116_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_ORIG_TD0\r
+CYDEV_PHUB_TDMEM116_ORIG_TD0 EQU 0x40007ba0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_ORIG_TD1\r
+CYDEV_PHUB_TDMEM116_ORIG_TD1 EQU 0x40007ba4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_BASE\r
+CYDEV_PHUB_TDMEM117_BASE EQU 0x40007ba8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_SIZE\r
+CYDEV_PHUB_TDMEM117_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_ORIG_TD0\r
+CYDEV_PHUB_TDMEM117_ORIG_TD0 EQU 0x40007ba8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_ORIG_TD1\r
+CYDEV_PHUB_TDMEM117_ORIG_TD1 EQU 0x40007bac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_BASE\r
+CYDEV_PHUB_TDMEM118_BASE EQU 0x40007bb0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_SIZE\r
+CYDEV_PHUB_TDMEM118_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_ORIG_TD0\r
+CYDEV_PHUB_TDMEM118_ORIG_TD0 EQU 0x40007bb0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_ORIG_TD1\r
+CYDEV_PHUB_TDMEM118_ORIG_TD1 EQU 0x40007bb4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_BASE\r
+CYDEV_PHUB_TDMEM119_BASE EQU 0x40007bb8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_SIZE\r
+CYDEV_PHUB_TDMEM119_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_ORIG_TD0\r
+CYDEV_PHUB_TDMEM119_ORIG_TD0 EQU 0x40007bb8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_ORIG_TD1\r
+CYDEV_PHUB_TDMEM119_ORIG_TD1 EQU 0x40007bbc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_BASE\r
+CYDEV_PHUB_TDMEM120_BASE EQU 0x40007bc0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_SIZE\r
+CYDEV_PHUB_TDMEM120_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_ORIG_TD0\r
+CYDEV_PHUB_TDMEM120_ORIG_TD0 EQU 0x40007bc0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_ORIG_TD1\r
+CYDEV_PHUB_TDMEM120_ORIG_TD1 EQU 0x40007bc4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_BASE\r
+CYDEV_PHUB_TDMEM121_BASE EQU 0x40007bc8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_SIZE\r
+CYDEV_PHUB_TDMEM121_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_ORIG_TD0\r
+CYDEV_PHUB_TDMEM121_ORIG_TD0 EQU 0x40007bc8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_ORIG_TD1\r
+CYDEV_PHUB_TDMEM121_ORIG_TD1 EQU 0x40007bcc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_BASE\r
+CYDEV_PHUB_TDMEM122_BASE EQU 0x40007bd0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_SIZE\r
+CYDEV_PHUB_TDMEM122_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_ORIG_TD0\r
+CYDEV_PHUB_TDMEM122_ORIG_TD0 EQU 0x40007bd0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_ORIG_TD1\r
+CYDEV_PHUB_TDMEM122_ORIG_TD1 EQU 0x40007bd4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_BASE\r
+CYDEV_PHUB_TDMEM123_BASE EQU 0x40007bd8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_SIZE\r
+CYDEV_PHUB_TDMEM123_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_ORIG_TD0\r
+CYDEV_PHUB_TDMEM123_ORIG_TD0 EQU 0x40007bd8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_ORIG_TD1\r
+CYDEV_PHUB_TDMEM123_ORIG_TD1 EQU 0x40007bdc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_BASE\r
+CYDEV_PHUB_TDMEM124_BASE EQU 0x40007be0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_SIZE\r
+CYDEV_PHUB_TDMEM124_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_ORIG_TD0\r
+CYDEV_PHUB_TDMEM124_ORIG_TD0 EQU 0x40007be0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_ORIG_TD1\r
+CYDEV_PHUB_TDMEM124_ORIG_TD1 EQU 0x40007be4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_BASE\r
+CYDEV_PHUB_TDMEM125_BASE EQU 0x40007be8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_SIZE\r
+CYDEV_PHUB_TDMEM125_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_ORIG_TD0\r
+CYDEV_PHUB_TDMEM125_ORIG_TD0 EQU 0x40007be8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_ORIG_TD1\r
+CYDEV_PHUB_TDMEM125_ORIG_TD1 EQU 0x40007bec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_BASE\r
+CYDEV_PHUB_TDMEM126_BASE EQU 0x40007bf0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_SIZE\r
+CYDEV_PHUB_TDMEM126_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_ORIG_TD0\r
+CYDEV_PHUB_TDMEM126_ORIG_TD0 EQU 0x40007bf0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_ORIG_TD1\r
+CYDEV_PHUB_TDMEM126_ORIG_TD1 EQU 0x40007bf4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_BASE\r
+CYDEV_PHUB_TDMEM127_BASE EQU 0x40007bf8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_SIZE\r
+CYDEV_PHUB_TDMEM127_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_ORIG_TD0\r
+CYDEV_PHUB_TDMEM127_ORIG_TD0 EQU 0x40007bf8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_ORIG_TD1\r
+CYDEV_PHUB_TDMEM127_ORIG_TD1 EQU 0x40007bfc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EE_BASE\r
+CYDEV_EE_BASE EQU 0x40008000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EE_SIZE\r
+CYDEV_EE_SIZE EQU 0x00000800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EE_DATA_MBASE\r
+CYDEV_EE_DATA_MBASE EQU 0x40008000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EE_DATA_MSIZE\r
+CYDEV_EE_DATA_MSIZE EQU 0x00000800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_BASE\r
+CYDEV_CAN0_BASE EQU 0x4000a000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_SIZE\r
+CYDEV_CAN0_SIZE EQU 0x000002a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_CSR_BASE\r
+CYDEV_CAN0_CSR_BASE EQU 0x4000a000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_CSR_SIZE\r
+CYDEV_CAN0_CSR_SIZE EQU 0x00000018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_CSR_INT_SR\r
+CYDEV_CAN0_CSR_INT_SR EQU 0x4000a000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_CSR_INT_EN\r
+CYDEV_CAN0_CSR_INT_EN EQU 0x4000a004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_CSR_BUF_SR\r
+CYDEV_CAN0_CSR_BUF_SR EQU 0x4000a008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_CSR_ERR_SR\r
+CYDEV_CAN0_CSR_ERR_SR EQU 0x4000a00c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_CSR_CMD\r
+CYDEV_CAN0_CSR_CMD EQU 0x4000a010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_CSR_CFG\r
+CYDEV_CAN0_CSR_CFG EQU 0x4000a014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX0_BASE\r
+CYDEV_CAN0_TX0_BASE EQU 0x4000a020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX0_SIZE\r
+CYDEV_CAN0_TX0_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX0_CMD\r
+CYDEV_CAN0_TX0_CMD EQU 0x4000a020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX0_ID\r
+CYDEV_CAN0_TX0_ID EQU 0x4000a024\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX0_DH\r
+CYDEV_CAN0_TX0_DH EQU 0x4000a028\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX0_DL\r
+CYDEV_CAN0_TX0_DL EQU 0x4000a02c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX1_BASE\r
+CYDEV_CAN0_TX1_BASE EQU 0x4000a030\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX1_SIZE\r
+CYDEV_CAN0_TX1_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX1_CMD\r
+CYDEV_CAN0_TX1_CMD EQU 0x4000a030\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX1_ID\r
+CYDEV_CAN0_TX1_ID EQU 0x4000a034\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX1_DH\r
+CYDEV_CAN0_TX1_DH EQU 0x4000a038\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX1_DL\r
+CYDEV_CAN0_TX1_DL EQU 0x4000a03c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX2_BASE\r
+CYDEV_CAN0_TX2_BASE EQU 0x4000a040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX2_SIZE\r
+CYDEV_CAN0_TX2_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX2_CMD\r
+CYDEV_CAN0_TX2_CMD EQU 0x4000a040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX2_ID\r
+CYDEV_CAN0_TX2_ID EQU 0x4000a044\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX2_DH\r
+CYDEV_CAN0_TX2_DH EQU 0x4000a048\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX2_DL\r
+CYDEV_CAN0_TX2_DL EQU 0x4000a04c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX3_BASE\r
+CYDEV_CAN0_TX3_BASE EQU 0x4000a050\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX3_SIZE\r
+CYDEV_CAN0_TX3_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX3_CMD\r
+CYDEV_CAN0_TX3_CMD EQU 0x4000a050\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX3_ID\r
+CYDEV_CAN0_TX3_ID EQU 0x4000a054\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX3_DH\r
+CYDEV_CAN0_TX3_DH EQU 0x4000a058\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX3_DL\r
+CYDEV_CAN0_TX3_DL EQU 0x4000a05c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX4_BASE\r
+CYDEV_CAN0_TX4_BASE EQU 0x4000a060\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX4_SIZE\r
+CYDEV_CAN0_TX4_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX4_CMD\r
+CYDEV_CAN0_TX4_CMD EQU 0x4000a060\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX4_ID\r
+CYDEV_CAN0_TX4_ID EQU 0x4000a064\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX4_DH\r
+CYDEV_CAN0_TX4_DH EQU 0x4000a068\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX4_DL\r
+CYDEV_CAN0_TX4_DL EQU 0x4000a06c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX5_BASE\r
+CYDEV_CAN0_TX5_BASE EQU 0x4000a070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX5_SIZE\r
+CYDEV_CAN0_TX5_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX5_CMD\r
+CYDEV_CAN0_TX5_CMD EQU 0x4000a070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX5_ID\r
+CYDEV_CAN0_TX5_ID EQU 0x4000a074\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX5_DH\r
+CYDEV_CAN0_TX5_DH EQU 0x4000a078\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX5_DL\r
+CYDEV_CAN0_TX5_DL EQU 0x4000a07c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX6_BASE\r
+CYDEV_CAN0_TX6_BASE EQU 0x4000a080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX6_SIZE\r
+CYDEV_CAN0_TX6_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX6_CMD\r
+CYDEV_CAN0_TX6_CMD EQU 0x4000a080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX6_ID\r
+CYDEV_CAN0_TX6_ID EQU 0x4000a084\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX6_DH\r
+CYDEV_CAN0_TX6_DH EQU 0x4000a088\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX6_DL\r
+CYDEV_CAN0_TX6_DL EQU 0x4000a08c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX7_BASE\r
+CYDEV_CAN0_TX7_BASE EQU 0x4000a090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX7_SIZE\r
+CYDEV_CAN0_TX7_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX7_CMD\r
+CYDEV_CAN0_TX7_CMD EQU 0x4000a090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX7_ID\r
+CYDEV_CAN0_TX7_ID EQU 0x4000a094\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX7_DH\r
+CYDEV_CAN0_TX7_DH EQU 0x4000a098\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX7_DL\r
+CYDEV_CAN0_TX7_DL EQU 0x4000a09c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX0_BASE\r
+CYDEV_CAN0_RX0_BASE EQU 0x4000a0a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX0_SIZE\r
+CYDEV_CAN0_RX0_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX0_CMD\r
+CYDEV_CAN0_RX0_CMD EQU 0x4000a0a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX0_ID\r
+CYDEV_CAN0_RX0_ID EQU 0x4000a0a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX0_DH\r
+CYDEV_CAN0_RX0_DH EQU 0x4000a0a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX0_DL\r
+CYDEV_CAN0_RX0_DL EQU 0x4000a0ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX0_AMR\r
+CYDEV_CAN0_RX0_AMR EQU 0x4000a0b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX0_ACR\r
+CYDEV_CAN0_RX0_ACR EQU 0x4000a0b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX0_AMRD\r
+CYDEV_CAN0_RX0_AMRD EQU 0x4000a0b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX0_ACRD\r
+CYDEV_CAN0_RX0_ACRD EQU 0x4000a0bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX1_BASE\r
+CYDEV_CAN0_RX1_BASE EQU 0x4000a0c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX1_SIZE\r
+CYDEV_CAN0_RX1_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX1_CMD\r
+CYDEV_CAN0_RX1_CMD EQU 0x4000a0c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX1_ID\r
+CYDEV_CAN0_RX1_ID EQU 0x4000a0c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX1_DH\r
+CYDEV_CAN0_RX1_DH EQU 0x4000a0c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX1_DL\r
+CYDEV_CAN0_RX1_DL EQU 0x4000a0cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX1_AMR\r
+CYDEV_CAN0_RX1_AMR EQU 0x4000a0d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX1_ACR\r
+CYDEV_CAN0_RX1_ACR EQU 0x4000a0d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX1_AMRD\r
+CYDEV_CAN0_RX1_AMRD EQU 0x4000a0d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX1_ACRD\r
+CYDEV_CAN0_RX1_ACRD EQU 0x4000a0dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX2_BASE\r
+CYDEV_CAN0_RX2_BASE EQU 0x4000a0e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX2_SIZE\r
+CYDEV_CAN0_RX2_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX2_CMD\r
+CYDEV_CAN0_RX2_CMD EQU 0x4000a0e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX2_ID\r
+CYDEV_CAN0_RX2_ID EQU 0x4000a0e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX2_DH\r
+CYDEV_CAN0_RX2_DH EQU 0x4000a0e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX2_DL\r
+CYDEV_CAN0_RX2_DL EQU 0x4000a0ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX2_AMR\r
+CYDEV_CAN0_RX2_AMR EQU 0x4000a0f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX2_ACR\r
+CYDEV_CAN0_RX2_ACR EQU 0x4000a0f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX2_AMRD\r
+CYDEV_CAN0_RX2_AMRD EQU 0x4000a0f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX2_ACRD\r
+CYDEV_CAN0_RX2_ACRD EQU 0x4000a0fc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX3_BASE\r
+CYDEV_CAN0_RX3_BASE EQU 0x4000a100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX3_SIZE\r
+CYDEV_CAN0_RX3_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX3_CMD\r
+CYDEV_CAN0_RX3_CMD EQU 0x4000a100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX3_ID\r
+CYDEV_CAN0_RX3_ID EQU 0x4000a104\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX3_DH\r
+CYDEV_CAN0_RX3_DH EQU 0x4000a108\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX3_DL\r
+CYDEV_CAN0_RX3_DL EQU 0x4000a10c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX3_AMR\r
+CYDEV_CAN0_RX3_AMR EQU 0x4000a110\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX3_ACR\r
+CYDEV_CAN0_RX3_ACR EQU 0x4000a114\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX3_AMRD\r
+CYDEV_CAN0_RX3_AMRD EQU 0x4000a118\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX3_ACRD\r
+CYDEV_CAN0_RX3_ACRD EQU 0x4000a11c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX4_BASE\r
+CYDEV_CAN0_RX4_BASE EQU 0x4000a120\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX4_SIZE\r
+CYDEV_CAN0_RX4_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX4_CMD\r
+CYDEV_CAN0_RX4_CMD EQU 0x4000a120\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX4_ID\r
+CYDEV_CAN0_RX4_ID EQU 0x4000a124\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX4_DH\r
+CYDEV_CAN0_RX4_DH EQU 0x4000a128\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX4_DL\r
+CYDEV_CAN0_RX4_DL EQU 0x4000a12c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX4_AMR\r
+CYDEV_CAN0_RX4_AMR EQU 0x4000a130\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX4_ACR\r
+CYDEV_CAN0_RX4_ACR EQU 0x4000a134\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX4_AMRD\r
+CYDEV_CAN0_RX4_AMRD EQU 0x4000a138\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX4_ACRD\r
+CYDEV_CAN0_RX4_ACRD EQU 0x4000a13c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX5_BASE\r
+CYDEV_CAN0_RX5_BASE EQU 0x4000a140\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX5_SIZE\r
+CYDEV_CAN0_RX5_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX5_CMD\r
+CYDEV_CAN0_RX5_CMD EQU 0x4000a140\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX5_ID\r
+CYDEV_CAN0_RX5_ID EQU 0x4000a144\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX5_DH\r
+CYDEV_CAN0_RX5_DH EQU 0x4000a148\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX5_DL\r
+CYDEV_CAN0_RX5_DL EQU 0x4000a14c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX5_AMR\r
+CYDEV_CAN0_RX5_AMR EQU 0x4000a150\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX5_ACR\r
+CYDEV_CAN0_RX5_ACR EQU 0x4000a154\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX5_AMRD\r
+CYDEV_CAN0_RX5_AMRD EQU 0x4000a158\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX5_ACRD\r
+CYDEV_CAN0_RX5_ACRD EQU 0x4000a15c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX6_BASE\r
+CYDEV_CAN0_RX6_BASE EQU 0x4000a160\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX6_SIZE\r
+CYDEV_CAN0_RX6_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX6_CMD\r
+CYDEV_CAN0_RX6_CMD EQU 0x4000a160\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX6_ID\r
+CYDEV_CAN0_RX6_ID EQU 0x4000a164\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX6_DH\r
+CYDEV_CAN0_RX6_DH EQU 0x4000a168\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX6_DL\r
+CYDEV_CAN0_RX6_DL EQU 0x4000a16c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX6_AMR\r
+CYDEV_CAN0_RX6_AMR EQU 0x4000a170\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX6_ACR\r
+CYDEV_CAN0_RX6_ACR EQU 0x4000a174\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX6_AMRD\r
+CYDEV_CAN0_RX6_AMRD EQU 0x4000a178\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX6_ACRD\r
+CYDEV_CAN0_RX6_ACRD EQU 0x4000a17c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX7_BASE\r
+CYDEV_CAN0_RX7_BASE EQU 0x4000a180\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX7_SIZE\r
+CYDEV_CAN0_RX7_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX7_CMD\r
+CYDEV_CAN0_RX7_CMD EQU 0x4000a180\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX7_ID\r
+CYDEV_CAN0_RX7_ID EQU 0x4000a184\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX7_DH\r
+CYDEV_CAN0_RX7_DH EQU 0x4000a188\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX7_DL\r
+CYDEV_CAN0_RX7_DL EQU 0x4000a18c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX7_AMR\r
+CYDEV_CAN0_RX7_AMR EQU 0x4000a190\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX7_ACR\r
+CYDEV_CAN0_RX7_ACR EQU 0x4000a194\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX7_AMRD\r
+CYDEV_CAN0_RX7_AMRD EQU 0x4000a198\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX7_ACRD\r
+CYDEV_CAN0_RX7_ACRD EQU 0x4000a19c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX8_BASE\r
+CYDEV_CAN0_RX8_BASE EQU 0x4000a1a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX8_SIZE\r
+CYDEV_CAN0_RX8_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX8_CMD\r
+CYDEV_CAN0_RX8_CMD EQU 0x4000a1a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX8_ID\r
+CYDEV_CAN0_RX8_ID EQU 0x4000a1a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX8_DH\r
+CYDEV_CAN0_RX8_DH EQU 0x4000a1a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX8_DL\r
+CYDEV_CAN0_RX8_DL EQU 0x4000a1ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX8_AMR\r
+CYDEV_CAN0_RX8_AMR EQU 0x4000a1b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX8_ACR\r
+CYDEV_CAN0_RX8_ACR EQU 0x4000a1b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX8_AMRD\r
+CYDEV_CAN0_RX8_AMRD EQU 0x4000a1b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX8_ACRD\r
+CYDEV_CAN0_RX8_ACRD EQU 0x4000a1bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX9_BASE\r
+CYDEV_CAN0_RX9_BASE EQU 0x4000a1c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX9_SIZE\r
+CYDEV_CAN0_RX9_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX9_CMD\r
+CYDEV_CAN0_RX9_CMD EQU 0x4000a1c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX9_ID\r
+CYDEV_CAN0_RX9_ID EQU 0x4000a1c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX9_DH\r
+CYDEV_CAN0_RX9_DH EQU 0x4000a1c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX9_DL\r
+CYDEV_CAN0_RX9_DL EQU 0x4000a1cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX9_AMR\r
+CYDEV_CAN0_RX9_AMR EQU 0x4000a1d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX9_ACR\r
+CYDEV_CAN0_RX9_ACR EQU 0x4000a1d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX9_AMRD\r
+CYDEV_CAN0_RX9_AMRD EQU 0x4000a1d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX9_ACRD\r
+CYDEV_CAN0_RX9_ACRD EQU 0x4000a1dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX10_BASE\r
+CYDEV_CAN0_RX10_BASE EQU 0x4000a1e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX10_SIZE\r
+CYDEV_CAN0_RX10_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX10_CMD\r
+CYDEV_CAN0_RX10_CMD EQU 0x4000a1e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX10_ID\r
+CYDEV_CAN0_RX10_ID EQU 0x4000a1e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX10_DH\r
+CYDEV_CAN0_RX10_DH EQU 0x4000a1e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX10_DL\r
+CYDEV_CAN0_RX10_DL EQU 0x4000a1ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX10_AMR\r
+CYDEV_CAN0_RX10_AMR EQU 0x4000a1f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX10_ACR\r
+CYDEV_CAN0_RX10_ACR EQU 0x4000a1f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX10_AMRD\r
+CYDEV_CAN0_RX10_AMRD EQU 0x4000a1f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX10_ACRD\r
+CYDEV_CAN0_RX10_ACRD EQU 0x4000a1fc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX11_BASE\r
+CYDEV_CAN0_RX11_BASE EQU 0x4000a200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX11_SIZE\r
+CYDEV_CAN0_RX11_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX11_CMD\r
+CYDEV_CAN0_RX11_CMD EQU 0x4000a200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX11_ID\r
+CYDEV_CAN0_RX11_ID EQU 0x4000a204\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX11_DH\r
+CYDEV_CAN0_RX11_DH EQU 0x4000a208\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX11_DL\r
+CYDEV_CAN0_RX11_DL EQU 0x4000a20c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX11_AMR\r
+CYDEV_CAN0_RX11_AMR EQU 0x4000a210\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX11_ACR\r
+CYDEV_CAN0_RX11_ACR EQU 0x4000a214\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX11_AMRD\r
+CYDEV_CAN0_RX11_AMRD EQU 0x4000a218\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX11_ACRD\r
+CYDEV_CAN0_RX11_ACRD EQU 0x4000a21c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX12_BASE\r
+CYDEV_CAN0_RX12_BASE EQU 0x4000a220\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX12_SIZE\r
+CYDEV_CAN0_RX12_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX12_CMD\r
+CYDEV_CAN0_RX12_CMD EQU 0x4000a220\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX12_ID\r
+CYDEV_CAN0_RX12_ID EQU 0x4000a224\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX12_DH\r
+CYDEV_CAN0_RX12_DH EQU 0x4000a228\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX12_DL\r
+CYDEV_CAN0_RX12_DL EQU 0x4000a22c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX12_AMR\r
+CYDEV_CAN0_RX12_AMR EQU 0x4000a230\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX12_ACR\r
+CYDEV_CAN0_RX12_ACR EQU 0x4000a234\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX12_AMRD\r
+CYDEV_CAN0_RX12_AMRD EQU 0x4000a238\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX12_ACRD\r
+CYDEV_CAN0_RX12_ACRD EQU 0x4000a23c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX13_BASE\r
+CYDEV_CAN0_RX13_BASE EQU 0x4000a240\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX13_SIZE\r
+CYDEV_CAN0_RX13_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX13_CMD\r
+CYDEV_CAN0_RX13_CMD EQU 0x4000a240\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX13_ID\r
+CYDEV_CAN0_RX13_ID EQU 0x4000a244\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX13_DH\r
+CYDEV_CAN0_RX13_DH EQU 0x4000a248\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX13_DL\r
+CYDEV_CAN0_RX13_DL EQU 0x4000a24c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX13_AMR\r
+CYDEV_CAN0_RX13_AMR EQU 0x4000a250\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX13_ACR\r
+CYDEV_CAN0_RX13_ACR EQU 0x4000a254\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX13_AMRD\r
+CYDEV_CAN0_RX13_AMRD EQU 0x4000a258\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX13_ACRD\r
+CYDEV_CAN0_RX13_ACRD EQU 0x4000a25c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX14_BASE\r
+CYDEV_CAN0_RX14_BASE EQU 0x4000a260\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX14_SIZE\r
+CYDEV_CAN0_RX14_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX14_CMD\r
+CYDEV_CAN0_RX14_CMD EQU 0x4000a260\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX14_ID\r
+CYDEV_CAN0_RX14_ID EQU 0x4000a264\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX14_DH\r
+CYDEV_CAN0_RX14_DH EQU 0x4000a268\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX14_DL\r
+CYDEV_CAN0_RX14_DL EQU 0x4000a26c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX14_AMR\r
+CYDEV_CAN0_RX14_AMR EQU 0x4000a270\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX14_ACR\r
+CYDEV_CAN0_RX14_ACR EQU 0x4000a274\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX14_AMRD\r
+CYDEV_CAN0_RX14_AMRD EQU 0x4000a278\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX14_ACRD\r
+CYDEV_CAN0_RX14_ACRD EQU 0x4000a27c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX15_BASE\r
+CYDEV_CAN0_RX15_BASE EQU 0x4000a280\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX15_SIZE\r
+CYDEV_CAN0_RX15_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX15_CMD\r
+CYDEV_CAN0_RX15_CMD EQU 0x4000a280\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX15_ID\r
+CYDEV_CAN0_RX15_ID EQU 0x4000a284\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX15_DH\r
+CYDEV_CAN0_RX15_DH EQU 0x4000a288\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX15_DL\r
+CYDEV_CAN0_RX15_DL EQU 0x4000a28c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX15_AMR\r
+CYDEV_CAN0_RX15_AMR EQU 0x4000a290\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX15_ACR\r
+CYDEV_CAN0_RX15_ACR EQU 0x4000a294\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX15_AMRD\r
+CYDEV_CAN0_RX15_AMRD EQU 0x4000a298\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX15_ACRD\r
+CYDEV_CAN0_RX15_ACRD EQU 0x4000a29c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_BASE\r
+CYDEV_DFB0_BASE EQU 0x4000c000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_SIZE\r
+CYDEV_DFB0_SIZE EQU 0x000007b5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_BASE\r
+CYDEV_DFB0_DPA_SRAM_BASE EQU 0x4000c000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_SIZE\r
+CYDEV_DFB0_DPA_SRAM_SIZE EQU 0x00000200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_DATA_MBASE\r
+CYDEV_DFB0_DPA_SRAM_DATA_MBASE EQU 0x4000c000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_DATA_MSIZE\r
+CYDEV_DFB0_DPA_SRAM_DATA_MSIZE EQU 0x00000200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_BASE\r
+CYDEV_DFB0_DPB_SRAM_BASE EQU 0x4000c200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_SIZE\r
+CYDEV_DFB0_DPB_SRAM_SIZE EQU 0x00000200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_DATA_MBASE\r
+CYDEV_DFB0_DPB_SRAM_DATA_MBASE EQU 0x4000c200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_DATA_MSIZE\r
+CYDEV_DFB0_DPB_SRAM_DATA_MSIZE EQU 0x00000200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_BASE\r
+CYDEV_DFB0_CSA_SRAM_BASE EQU 0x4000c400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_SIZE\r
+CYDEV_DFB0_CSA_SRAM_SIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_DATA_MBASE\r
+CYDEV_DFB0_CSA_SRAM_DATA_MBASE EQU 0x4000c400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_DATA_MSIZE\r
+CYDEV_DFB0_CSA_SRAM_DATA_MSIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_BASE\r
+CYDEV_DFB0_CSB_SRAM_BASE EQU 0x4000c500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_SIZE\r
+CYDEV_DFB0_CSB_SRAM_SIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_DATA_MBASE\r
+CYDEV_DFB0_CSB_SRAM_DATA_MBASE EQU 0x4000c500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_DATA_MSIZE\r
+CYDEV_DFB0_CSB_SRAM_DATA_MSIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_BASE\r
+CYDEV_DFB0_FSM_SRAM_BASE EQU 0x4000c600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_SIZE\r
+CYDEV_DFB0_FSM_SRAM_SIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_DATA_MBASE\r
+CYDEV_DFB0_FSM_SRAM_DATA_MBASE EQU 0x4000c600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_DATA_MSIZE\r
+CYDEV_DFB0_FSM_SRAM_DATA_MSIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_BASE\r
+CYDEV_DFB0_ACU_SRAM_BASE EQU 0x4000c700\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_SIZE\r
+CYDEV_DFB0_ACU_SRAM_SIZE EQU 0x00000040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_DATA_MBASE\r
+CYDEV_DFB0_ACU_SRAM_DATA_MBASE EQU 0x4000c700\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_DATA_MSIZE\r
+CYDEV_DFB0_ACU_SRAM_DATA_MSIZE EQU 0x00000040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_CR\r
+CYDEV_DFB0_CR EQU 0x4000c780\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_SR\r
+CYDEV_DFB0_SR EQU 0x4000c784\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_RAM_EN\r
+CYDEV_DFB0_RAM_EN EQU 0x4000c788\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_RAM_DIR\r
+CYDEV_DFB0_RAM_DIR EQU 0x4000c78c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_SEMA\r
+CYDEV_DFB0_SEMA EQU 0x4000c790\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_DSI_CTRL\r
+CYDEV_DFB0_DSI_CTRL EQU 0x4000c794\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_INT_CTRL\r
+CYDEV_DFB0_INT_CTRL EQU 0x4000c798\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_DMA_CTRL\r
+CYDEV_DFB0_DMA_CTRL EQU 0x4000c79c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_STAGEA\r
+CYDEV_DFB0_STAGEA EQU 0x4000c7a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_STAGEAM\r
+CYDEV_DFB0_STAGEAM EQU 0x4000c7a1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_STAGEAH\r
+CYDEV_DFB0_STAGEAH EQU 0x4000c7a2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_STAGEB\r
+CYDEV_DFB0_STAGEB EQU 0x4000c7a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_STAGEBM\r
+CYDEV_DFB0_STAGEBM EQU 0x4000c7a5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_STAGEBH\r
+CYDEV_DFB0_STAGEBH EQU 0x4000c7a6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_HOLDA\r
+CYDEV_DFB0_HOLDA EQU 0x4000c7a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_HOLDAM\r
+CYDEV_DFB0_HOLDAM EQU 0x4000c7a9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_HOLDAH\r
+CYDEV_DFB0_HOLDAH EQU 0x4000c7aa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_HOLDAS\r
+CYDEV_DFB0_HOLDAS EQU 0x4000c7ab\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_HOLDB\r
+CYDEV_DFB0_HOLDB EQU 0x4000c7ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_HOLDBM\r
+CYDEV_DFB0_HOLDBM EQU 0x4000c7ad\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_HOLDBH\r
+CYDEV_DFB0_HOLDBH EQU 0x4000c7ae\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_HOLDBS\r
+CYDEV_DFB0_HOLDBS EQU 0x4000c7af\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_COHER\r
+CYDEV_DFB0_COHER EQU 0x4000c7b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_DALIGN\r
+CYDEV_DFB0_DALIGN EQU 0x4000c7b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BASE\r
+CYDEV_UCFG_BASE EQU 0x40010000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_SIZE\r
+CYDEV_UCFG_SIZE EQU 0x00005040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_BASE\r
+CYDEV_UCFG_B0_BASE EQU 0x40010000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_SIZE\r
+CYDEV_UCFG_B0_SIZE EQU 0x00000fef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_BASE\r
+CYDEV_UCFG_B0_P0_BASE EQU 0x40010000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_SIZE\r
+CYDEV_UCFG_B0_P0_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_BASE\r
+CYDEV_UCFG_B0_P0_U0_BASE EQU 0x40010000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_SIZE\r
+CYDEV_UCFG_B0_P0_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT0\r
+CYDEV_UCFG_B0_P0_U0_PLD_IT0 EQU 0x40010000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT1\r
+CYDEV_UCFG_B0_P0_U0_PLD_IT1 EQU 0x40010004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT2\r
+CYDEV_UCFG_B0_P0_U0_PLD_IT2 EQU 0x40010008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT3\r
+CYDEV_UCFG_B0_P0_U0_PLD_IT3 EQU 0x4001000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT4\r
+CYDEV_UCFG_B0_P0_U0_PLD_IT4 EQU 0x40010010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT5\r
+CYDEV_UCFG_B0_P0_U0_PLD_IT5 EQU 0x40010014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT6\r
+CYDEV_UCFG_B0_P0_U0_PLD_IT6 EQU 0x40010018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT7\r
+CYDEV_UCFG_B0_P0_U0_PLD_IT7 EQU 0x4001001c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT8\r
+CYDEV_UCFG_B0_P0_U0_PLD_IT8 EQU 0x40010020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT9\r
+CYDEV_UCFG_B0_P0_U0_PLD_IT9 EQU 0x40010024\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT10\r
+CYDEV_UCFG_B0_P0_U0_PLD_IT10 EQU 0x40010028\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT11\r
+CYDEV_UCFG_B0_P0_U0_PLD_IT11 EQU 0x4001002c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT0\r
+CYDEV_UCFG_B0_P0_U0_PLD_ORT0 EQU 0x40010030\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT1\r
+CYDEV_UCFG_B0_P0_U0_PLD_ORT1 EQU 0x40010032\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT2\r
+CYDEV_UCFG_B0_P0_U0_PLD_ORT2 EQU 0x40010034\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT3\r
+CYDEV_UCFG_B0_P0_U0_PLD_ORT3 EQU 0x40010036\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST EQU 0x40010038\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB\r
+CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB EQU 0x4001003a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET EQU 0x4001003c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS\r
+CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS EQU 0x4001003e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG0\r
+CYDEV_UCFG_B0_P0_U0_CFG0 EQU 0x40010040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG1\r
+CYDEV_UCFG_B0_P0_U0_CFG1 EQU 0x40010041\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG2\r
+CYDEV_UCFG_B0_P0_U0_CFG2 EQU 0x40010042\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG3\r
+CYDEV_UCFG_B0_P0_U0_CFG3 EQU 0x40010043\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG4\r
+CYDEV_UCFG_B0_P0_U0_CFG4 EQU 0x40010044\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG5\r
+CYDEV_UCFG_B0_P0_U0_CFG5 EQU 0x40010045\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG6\r
+CYDEV_UCFG_B0_P0_U0_CFG6 EQU 0x40010046\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG7\r
+CYDEV_UCFG_B0_P0_U0_CFG7 EQU 0x40010047\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG8\r
+CYDEV_UCFG_B0_P0_U0_CFG8 EQU 0x40010048\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG9\r
+CYDEV_UCFG_B0_P0_U0_CFG9 EQU 0x40010049\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG10\r
+CYDEV_UCFG_B0_P0_U0_CFG10 EQU 0x4001004a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG11\r
+CYDEV_UCFG_B0_P0_U0_CFG11 EQU 0x4001004b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG12\r
+CYDEV_UCFG_B0_P0_U0_CFG12 EQU 0x4001004c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG13\r
+CYDEV_UCFG_B0_P0_U0_CFG13 EQU 0x4001004d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG14\r
+CYDEV_UCFG_B0_P0_U0_CFG14 EQU 0x4001004e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG15\r
+CYDEV_UCFG_B0_P0_U0_CFG15 EQU 0x4001004f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG16\r
+CYDEV_UCFG_B0_P0_U0_CFG16 EQU 0x40010050\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG17\r
+CYDEV_UCFG_B0_P0_U0_CFG17 EQU 0x40010051\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG18\r
+CYDEV_UCFG_B0_P0_U0_CFG18 EQU 0x40010052\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG19\r
+CYDEV_UCFG_B0_P0_U0_CFG19 EQU 0x40010053\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG20\r
+CYDEV_UCFG_B0_P0_U0_CFG20 EQU 0x40010054\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG21\r
+CYDEV_UCFG_B0_P0_U0_CFG21 EQU 0x40010055\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG22\r
+CYDEV_UCFG_B0_P0_U0_CFG22 EQU 0x40010056\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG23\r
+CYDEV_UCFG_B0_P0_U0_CFG23 EQU 0x40010057\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG24\r
+CYDEV_UCFG_B0_P0_U0_CFG24 EQU 0x40010058\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG25\r
+CYDEV_UCFG_B0_P0_U0_CFG25 EQU 0x40010059\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG26\r
+CYDEV_UCFG_B0_P0_U0_CFG26 EQU 0x4001005a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG27\r
+CYDEV_UCFG_B0_P0_U0_CFG27 EQU 0x4001005b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG28\r
+CYDEV_UCFG_B0_P0_U0_CFG28 EQU 0x4001005c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG29\r
+CYDEV_UCFG_B0_P0_U0_CFG29 EQU 0x4001005d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG30\r
+CYDEV_UCFG_B0_P0_U0_CFG30 EQU 0x4001005e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG31\r
+CYDEV_UCFG_B0_P0_U0_CFG31 EQU 0x4001005f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG0\r
+CYDEV_UCFG_B0_P0_U0_DCFG0 EQU 0x40010060\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG1\r
+CYDEV_UCFG_B0_P0_U0_DCFG1 EQU 0x40010062\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG2\r
+CYDEV_UCFG_B0_P0_U0_DCFG2 EQU 0x40010064\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG3\r
+CYDEV_UCFG_B0_P0_U0_DCFG3 EQU 0x40010066\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG4\r
+CYDEV_UCFG_B0_P0_U0_DCFG4 EQU 0x40010068\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG5\r
+CYDEV_UCFG_B0_P0_U0_DCFG5 EQU 0x4001006a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG6\r
+CYDEV_UCFG_B0_P0_U0_DCFG6 EQU 0x4001006c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG7\r
+CYDEV_UCFG_B0_P0_U0_DCFG7 EQU 0x4001006e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_BASE\r
+CYDEV_UCFG_B0_P0_U1_BASE EQU 0x40010080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_SIZE\r
+CYDEV_UCFG_B0_P0_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT0\r
+CYDEV_UCFG_B0_P0_U1_PLD_IT0 EQU 0x40010080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT1\r
+CYDEV_UCFG_B0_P0_U1_PLD_IT1 EQU 0x40010084\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT2\r
+CYDEV_UCFG_B0_P0_U1_PLD_IT2 EQU 0x40010088\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT3\r
+CYDEV_UCFG_B0_P0_U1_PLD_IT3 EQU 0x4001008c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT4\r
+CYDEV_UCFG_B0_P0_U1_PLD_IT4 EQU 0x40010090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT5\r
+CYDEV_UCFG_B0_P0_U1_PLD_IT5 EQU 0x40010094\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT6\r
+CYDEV_UCFG_B0_P0_U1_PLD_IT6 EQU 0x40010098\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT7\r
+CYDEV_UCFG_B0_P0_U1_PLD_IT7 EQU 0x4001009c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT8\r
+CYDEV_UCFG_B0_P0_U1_PLD_IT8 EQU 0x400100a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT9\r
+CYDEV_UCFG_B0_P0_U1_PLD_IT9 EQU 0x400100a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT10\r
+CYDEV_UCFG_B0_P0_U1_PLD_IT10 EQU 0x400100a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT11\r
+CYDEV_UCFG_B0_P0_U1_PLD_IT11 EQU 0x400100ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT0\r
+CYDEV_UCFG_B0_P0_U1_PLD_ORT0 EQU 0x400100b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT1\r
+CYDEV_UCFG_B0_P0_U1_PLD_ORT1 EQU 0x400100b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT2\r
+CYDEV_UCFG_B0_P0_U1_PLD_ORT2 EQU 0x400100b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT3\r
+CYDEV_UCFG_B0_P0_U1_PLD_ORT3 EQU 0x400100b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST EQU 0x400100b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB\r
+CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB EQU 0x400100ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET EQU 0x400100bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS\r
+CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS EQU 0x400100be\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG0\r
+CYDEV_UCFG_B0_P0_U1_CFG0 EQU 0x400100c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG1\r
+CYDEV_UCFG_B0_P0_U1_CFG1 EQU 0x400100c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG2\r
+CYDEV_UCFG_B0_P0_U1_CFG2 EQU 0x400100c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG3\r
+CYDEV_UCFG_B0_P0_U1_CFG3 EQU 0x400100c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG4\r
+CYDEV_UCFG_B0_P0_U1_CFG4 EQU 0x400100c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG5\r
+CYDEV_UCFG_B0_P0_U1_CFG5 EQU 0x400100c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG6\r
+CYDEV_UCFG_B0_P0_U1_CFG6 EQU 0x400100c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG7\r
+CYDEV_UCFG_B0_P0_U1_CFG7 EQU 0x400100c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG8\r
+CYDEV_UCFG_B0_P0_U1_CFG8 EQU 0x400100c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG9\r
+CYDEV_UCFG_B0_P0_U1_CFG9 EQU 0x400100c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG10\r
+CYDEV_UCFG_B0_P0_U1_CFG10 EQU 0x400100ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG11\r
+CYDEV_UCFG_B0_P0_U1_CFG11 EQU 0x400100cb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG12\r
+CYDEV_UCFG_B0_P0_U1_CFG12 EQU 0x400100cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG13\r
+CYDEV_UCFG_B0_P0_U1_CFG13 EQU 0x400100cd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG14\r
+CYDEV_UCFG_B0_P0_U1_CFG14 EQU 0x400100ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG15\r
+CYDEV_UCFG_B0_P0_U1_CFG15 EQU 0x400100cf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG16\r
+CYDEV_UCFG_B0_P0_U1_CFG16 EQU 0x400100d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG17\r
+CYDEV_UCFG_B0_P0_U1_CFG17 EQU 0x400100d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG18\r
+CYDEV_UCFG_B0_P0_U1_CFG18 EQU 0x400100d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG19\r
+CYDEV_UCFG_B0_P0_U1_CFG19 EQU 0x400100d3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG20\r
+CYDEV_UCFG_B0_P0_U1_CFG20 EQU 0x400100d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG21\r
+CYDEV_UCFG_B0_P0_U1_CFG21 EQU 0x400100d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG22\r
+CYDEV_UCFG_B0_P0_U1_CFG22 EQU 0x400100d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG23\r
+CYDEV_UCFG_B0_P0_U1_CFG23 EQU 0x400100d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG24\r
+CYDEV_UCFG_B0_P0_U1_CFG24 EQU 0x400100d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG25\r
+CYDEV_UCFG_B0_P0_U1_CFG25 EQU 0x400100d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG26\r
+CYDEV_UCFG_B0_P0_U1_CFG26 EQU 0x400100da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG27\r
+CYDEV_UCFG_B0_P0_U1_CFG27 EQU 0x400100db\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG28\r
+CYDEV_UCFG_B0_P0_U1_CFG28 EQU 0x400100dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG29\r
+CYDEV_UCFG_B0_P0_U1_CFG29 EQU 0x400100dd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG30\r
+CYDEV_UCFG_B0_P0_U1_CFG30 EQU 0x400100de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG31\r
+CYDEV_UCFG_B0_P0_U1_CFG31 EQU 0x400100df\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG0\r
+CYDEV_UCFG_B0_P0_U1_DCFG0 EQU 0x400100e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG1\r
+CYDEV_UCFG_B0_P0_U1_DCFG1 EQU 0x400100e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG2\r
+CYDEV_UCFG_B0_P0_U1_DCFG2 EQU 0x400100e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG3\r
+CYDEV_UCFG_B0_P0_U1_DCFG3 EQU 0x400100e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG4\r
+CYDEV_UCFG_B0_P0_U1_DCFG4 EQU 0x400100e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG5\r
+CYDEV_UCFG_B0_P0_U1_DCFG5 EQU 0x400100ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG6\r
+CYDEV_UCFG_B0_P0_U1_DCFG6 EQU 0x400100ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG7\r
+CYDEV_UCFG_B0_P0_U1_DCFG7 EQU 0x400100ee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_BASE\r
+CYDEV_UCFG_B0_P0_ROUTE_BASE EQU 0x40010100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_SIZE\r
+CYDEV_UCFG_B0_P0_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_BASE\r
+CYDEV_UCFG_B0_P1_BASE EQU 0x40010200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_SIZE\r
+CYDEV_UCFG_B0_P1_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_BASE\r
+CYDEV_UCFG_B0_P1_U0_BASE EQU 0x40010200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_SIZE\r
+CYDEV_UCFG_B0_P1_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT0\r
+CYDEV_UCFG_B0_P1_U0_PLD_IT0 EQU 0x40010200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT1\r
+CYDEV_UCFG_B0_P1_U0_PLD_IT1 EQU 0x40010204\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT2\r
+CYDEV_UCFG_B0_P1_U0_PLD_IT2 EQU 0x40010208\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT3\r
+CYDEV_UCFG_B0_P1_U0_PLD_IT3 EQU 0x4001020c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT4\r
+CYDEV_UCFG_B0_P1_U0_PLD_IT4 EQU 0x40010210\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT5\r
+CYDEV_UCFG_B0_P1_U0_PLD_IT5 EQU 0x40010214\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT6\r
+CYDEV_UCFG_B0_P1_U0_PLD_IT6 EQU 0x40010218\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT7\r
+CYDEV_UCFG_B0_P1_U0_PLD_IT7 EQU 0x4001021c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT8\r
+CYDEV_UCFG_B0_P1_U0_PLD_IT8 EQU 0x40010220\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT9\r
+CYDEV_UCFG_B0_P1_U0_PLD_IT9 EQU 0x40010224\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT10\r
+CYDEV_UCFG_B0_P1_U0_PLD_IT10 EQU 0x40010228\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT11\r
+CYDEV_UCFG_B0_P1_U0_PLD_IT11 EQU 0x4001022c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT0\r
+CYDEV_UCFG_B0_P1_U0_PLD_ORT0 EQU 0x40010230\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT1\r
+CYDEV_UCFG_B0_P1_U0_PLD_ORT1 EQU 0x40010232\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT2\r
+CYDEV_UCFG_B0_P1_U0_PLD_ORT2 EQU 0x40010234\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT3\r
+CYDEV_UCFG_B0_P1_U0_PLD_ORT3 EQU 0x40010236\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST EQU 0x40010238\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB\r
+CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB EQU 0x4001023a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET EQU 0x4001023c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS\r
+CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS EQU 0x4001023e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG0\r
+CYDEV_UCFG_B0_P1_U0_CFG0 EQU 0x40010240\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG1\r
+CYDEV_UCFG_B0_P1_U0_CFG1 EQU 0x40010241\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG2\r
+CYDEV_UCFG_B0_P1_U0_CFG2 EQU 0x40010242\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG3\r
+CYDEV_UCFG_B0_P1_U0_CFG3 EQU 0x40010243\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG4\r
+CYDEV_UCFG_B0_P1_U0_CFG4 EQU 0x40010244\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG5\r
+CYDEV_UCFG_B0_P1_U0_CFG5 EQU 0x40010245\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG6\r
+CYDEV_UCFG_B0_P1_U0_CFG6 EQU 0x40010246\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG7\r
+CYDEV_UCFG_B0_P1_U0_CFG7 EQU 0x40010247\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG8\r
+CYDEV_UCFG_B0_P1_U0_CFG8 EQU 0x40010248\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG9\r
+CYDEV_UCFG_B0_P1_U0_CFG9 EQU 0x40010249\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG10\r
+CYDEV_UCFG_B0_P1_U0_CFG10 EQU 0x4001024a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG11\r
+CYDEV_UCFG_B0_P1_U0_CFG11 EQU 0x4001024b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG12\r
+CYDEV_UCFG_B0_P1_U0_CFG12 EQU 0x4001024c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG13\r
+CYDEV_UCFG_B0_P1_U0_CFG13 EQU 0x4001024d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG14\r
+CYDEV_UCFG_B0_P1_U0_CFG14 EQU 0x4001024e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG15\r
+CYDEV_UCFG_B0_P1_U0_CFG15 EQU 0x4001024f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG16\r
+CYDEV_UCFG_B0_P1_U0_CFG16 EQU 0x40010250\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG17\r
+CYDEV_UCFG_B0_P1_U0_CFG17 EQU 0x40010251\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG18\r
+CYDEV_UCFG_B0_P1_U0_CFG18 EQU 0x40010252\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG19\r
+CYDEV_UCFG_B0_P1_U0_CFG19 EQU 0x40010253\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG20\r
+CYDEV_UCFG_B0_P1_U0_CFG20 EQU 0x40010254\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG21\r
+CYDEV_UCFG_B0_P1_U0_CFG21 EQU 0x40010255\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG22\r
+CYDEV_UCFG_B0_P1_U0_CFG22 EQU 0x40010256\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG23\r
+CYDEV_UCFG_B0_P1_U0_CFG23 EQU 0x40010257\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG24\r
+CYDEV_UCFG_B0_P1_U0_CFG24 EQU 0x40010258\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG25\r
+CYDEV_UCFG_B0_P1_U0_CFG25 EQU 0x40010259\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG26\r
+CYDEV_UCFG_B0_P1_U0_CFG26 EQU 0x4001025a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG27\r
+CYDEV_UCFG_B0_P1_U0_CFG27 EQU 0x4001025b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG28\r
+CYDEV_UCFG_B0_P1_U0_CFG28 EQU 0x4001025c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG29\r
+CYDEV_UCFG_B0_P1_U0_CFG29 EQU 0x4001025d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG30\r
+CYDEV_UCFG_B0_P1_U0_CFG30 EQU 0x4001025e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG31\r
+CYDEV_UCFG_B0_P1_U0_CFG31 EQU 0x4001025f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG0\r
+CYDEV_UCFG_B0_P1_U0_DCFG0 EQU 0x40010260\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG1\r
+CYDEV_UCFG_B0_P1_U0_DCFG1 EQU 0x40010262\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG2\r
+CYDEV_UCFG_B0_P1_U0_DCFG2 EQU 0x40010264\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG3\r
+CYDEV_UCFG_B0_P1_U0_DCFG3 EQU 0x40010266\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG4\r
+CYDEV_UCFG_B0_P1_U0_DCFG4 EQU 0x40010268\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG5\r
+CYDEV_UCFG_B0_P1_U0_DCFG5 EQU 0x4001026a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG6\r
+CYDEV_UCFG_B0_P1_U0_DCFG6 EQU 0x4001026c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG7\r
+CYDEV_UCFG_B0_P1_U0_DCFG7 EQU 0x4001026e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_BASE\r
+CYDEV_UCFG_B0_P1_U1_BASE EQU 0x40010280\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_SIZE\r
+CYDEV_UCFG_B0_P1_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT0\r
+CYDEV_UCFG_B0_P1_U1_PLD_IT0 EQU 0x40010280\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT1\r
+CYDEV_UCFG_B0_P1_U1_PLD_IT1 EQU 0x40010284\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT2\r
+CYDEV_UCFG_B0_P1_U1_PLD_IT2 EQU 0x40010288\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT3\r
+CYDEV_UCFG_B0_P1_U1_PLD_IT3 EQU 0x4001028c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT4\r
+CYDEV_UCFG_B0_P1_U1_PLD_IT4 EQU 0x40010290\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT5\r
+CYDEV_UCFG_B0_P1_U1_PLD_IT5 EQU 0x40010294\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT6\r
+CYDEV_UCFG_B0_P1_U1_PLD_IT6 EQU 0x40010298\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT7\r
+CYDEV_UCFG_B0_P1_U1_PLD_IT7 EQU 0x4001029c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT8\r
+CYDEV_UCFG_B0_P1_U1_PLD_IT8 EQU 0x400102a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT9\r
+CYDEV_UCFG_B0_P1_U1_PLD_IT9 EQU 0x400102a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT10\r
+CYDEV_UCFG_B0_P1_U1_PLD_IT10 EQU 0x400102a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT11\r
+CYDEV_UCFG_B0_P1_U1_PLD_IT11 EQU 0x400102ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT0\r
+CYDEV_UCFG_B0_P1_U1_PLD_ORT0 EQU 0x400102b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT1\r
+CYDEV_UCFG_B0_P1_U1_PLD_ORT1 EQU 0x400102b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT2\r
+CYDEV_UCFG_B0_P1_U1_PLD_ORT2 EQU 0x400102b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT3\r
+CYDEV_UCFG_B0_P1_U1_PLD_ORT3 EQU 0x400102b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST EQU 0x400102b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB\r
+CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB EQU 0x400102ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET EQU 0x400102bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS\r
+CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS EQU 0x400102be\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG0\r
+CYDEV_UCFG_B0_P1_U1_CFG0 EQU 0x400102c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG1\r
+CYDEV_UCFG_B0_P1_U1_CFG1 EQU 0x400102c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG2\r
+CYDEV_UCFG_B0_P1_U1_CFG2 EQU 0x400102c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG3\r
+CYDEV_UCFG_B0_P1_U1_CFG3 EQU 0x400102c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG4\r
+CYDEV_UCFG_B0_P1_U1_CFG4 EQU 0x400102c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG5\r
+CYDEV_UCFG_B0_P1_U1_CFG5 EQU 0x400102c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG6\r
+CYDEV_UCFG_B0_P1_U1_CFG6 EQU 0x400102c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG7\r
+CYDEV_UCFG_B0_P1_U1_CFG7 EQU 0x400102c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG8\r
+CYDEV_UCFG_B0_P1_U1_CFG8 EQU 0x400102c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG9\r
+CYDEV_UCFG_B0_P1_U1_CFG9 EQU 0x400102c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG10\r
+CYDEV_UCFG_B0_P1_U1_CFG10 EQU 0x400102ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG11\r
+CYDEV_UCFG_B0_P1_U1_CFG11 EQU 0x400102cb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG12\r
+CYDEV_UCFG_B0_P1_U1_CFG12 EQU 0x400102cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG13\r
+CYDEV_UCFG_B0_P1_U1_CFG13 EQU 0x400102cd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG14\r
+CYDEV_UCFG_B0_P1_U1_CFG14 EQU 0x400102ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG15\r
+CYDEV_UCFG_B0_P1_U1_CFG15 EQU 0x400102cf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG16\r
+CYDEV_UCFG_B0_P1_U1_CFG16 EQU 0x400102d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG17\r
+CYDEV_UCFG_B0_P1_U1_CFG17 EQU 0x400102d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG18\r
+CYDEV_UCFG_B0_P1_U1_CFG18 EQU 0x400102d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG19\r
+CYDEV_UCFG_B0_P1_U1_CFG19 EQU 0x400102d3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG20\r
+CYDEV_UCFG_B0_P1_U1_CFG20 EQU 0x400102d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG21\r
+CYDEV_UCFG_B0_P1_U1_CFG21 EQU 0x400102d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG22\r
+CYDEV_UCFG_B0_P1_U1_CFG22 EQU 0x400102d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG23\r
+CYDEV_UCFG_B0_P1_U1_CFG23 EQU 0x400102d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG24\r
+CYDEV_UCFG_B0_P1_U1_CFG24 EQU 0x400102d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG25\r
+CYDEV_UCFG_B0_P1_U1_CFG25 EQU 0x400102d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG26\r
+CYDEV_UCFG_B0_P1_U1_CFG26 EQU 0x400102da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG27\r
+CYDEV_UCFG_B0_P1_U1_CFG27 EQU 0x400102db\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG28\r
+CYDEV_UCFG_B0_P1_U1_CFG28 EQU 0x400102dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG29\r
+CYDEV_UCFG_B0_P1_U1_CFG29 EQU 0x400102dd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG30\r
+CYDEV_UCFG_B0_P1_U1_CFG30 EQU 0x400102de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG31\r
+CYDEV_UCFG_B0_P1_U1_CFG31 EQU 0x400102df\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG0\r
+CYDEV_UCFG_B0_P1_U1_DCFG0 EQU 0x400102e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG1\r
+CYDEV_UCFG_B0_P1_U1_DCFG1 EQU 0x400102e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG2\r
+CYDEV_UCFG_B0_P1_U1_DCFG2 EQU 0x400102e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG3\r
+CYDEV_UCFG_B0_P1_U1_DCFG3 EQU 0x400102e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG4\r
+CYDEV_UCFG_B0_P1_U1_DCFG4 EQU 0x400102e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG5\r
+CYDEV_UCFG_B0_P1_U1_DCFG5 EQU 0x400102ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG6\r
+CYDEV_UCFG_B0_P1_U1_DCFG6 EQU 0x400102ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG7\r
+CYDEV_UCFG_B0_P1_U1_DCFG7 EQU 0x400102ee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_BASE\r
+CYDEV_UCFG_B0_P1_ROUTE_BASE EQU 0x40010300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_SIZE\r
+CYDEV_UCFG_B0_P1_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_BASE\r
+CYDEV_UCFG_B0_P2_BASE EQU 0x40010400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_SIZE\r
+CYDEV_UCFG_B0_P2_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_BASE\r
+CYDEV_UCFG_B0_P2_U0_BASE EQU 0x40010400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_SIZE\r
+CYDEV_UCFG_B0_P2_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT0\r
+CYDEV_UCFG_B0_P2_U0_PLD_IT0 EQU 0x40010400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT1\r
+CYDEV_UCFG_B0_P2_U0_PLD_IT1 EQU 0x40010404\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT2\r
+CYDEV_UCFG_B0_P2_U0_PLD_IT2 EQU 0x40010408\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT3\r
+CYDEV_UCFG_B0_P2_U0_PLD_IT3 EQU 0x4001040c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT4\r
+CYDEV_UCFG_B0_P2_U0_PLD_IT4 EQU 0x40010410\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT5\r
+CYDEV_UCFG_B0_P2_U0_PLD_IT5 EQU 0x40010414\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT6\r
+CYDEV_UCFG_B0_P2_U0_PLD_IT6 EQU 0x40010418\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT7\r
+CYDEV_UCFG_B0_P2_U0_PLD_IT7 EQU 0x4001041c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT8\r
+CYDEV_UCFG_B0_P2_U0_PLD_IT8 EQU 0x40010420\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT9\r
+CYDEV_UCFG_B0_P2_U0_PLD_IT9 EQU 0x40010424\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT10\r
+CYDEV_UCFG_B0_P2_U0_PLD_IT10 EQU 0x40010428\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT11\r
+CYDEV_UCFG_B0_P2_U0_PLD_IT11 EQU 0x4001042c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT0\r
+CYDEV_UCFG_B0_P2_U0_PLD_ORT0 EQU 0x40010430\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT1\r
+CYDEV_UCFG_B0_P2_U0_PLD_ORT1 EQU 0x40010432\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT2\r
+CYDEV_UCFG_B0_P2_U0_PLD_ORT2 EQU 0x40010434\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT3\r
+CYDEV_UCFG_B0_P2_U0_PLD_ORT3 EQU 0x40010436\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST EQU 0x40010438\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB\r
+CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB EQU 0x4001043a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET EQU 0x4001043c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS\r
+CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS EQU 0x4001043e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG0\r
+CYDEV_UCFG_B0_P2_U0_CFG0 EQU 0x40010440\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG1\r
+CYDEV_UCFG_B0_P2_U0_CFG1 EQU 0x40010441\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG2\r
+CYDEV_UCFG_B0_P2_U0_CFG2 EQU 0x40010442\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG3\r
+CYDEV_UCFG_B0_P2_U0_CFG3 EQU 0x40010443\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG4\r
+CYDEV_UCFG_B0_P2_U0_CFG4 EQU 0x40010444\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG5\r
+CYDEV_UCFG_B0_P2_U0_CFG5 EQU 0x40010445\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG6\r
+CYDEV_UCFG_B0_P2_U0_CFG6 EQU 0x40010446\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG7\r
+CYDEV_UCFG_B0_P2_U0_CFG7 EQU 0x40010447\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG8\r
+CYDEV_UCFG_B0_P2_U0_CFG8 EQU 0x40010448\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG9\r
+CYDEV_UCFG_B0_P2_U0_CFG9 EQU 0x40010449\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG10\r
+CYDEV_UCFG_B0_P2_U0_CFG10 EQU 0x4001044a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG11\r
+CYDEV_UCFG_B0_P2_U0_CFG11 EQU 0x4001044b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG12\r
+CYDEV_UCFG_B0_P2_U0_CFG12 EQU 0x4001044c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG13\r
+CYDEV_UCFG_B0_P2_U0_CFG13 EQU 0x4001044d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG14\r
+CYDEV_UCFG_B0_P2_U0_CFG14 EQU 0x4001044e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG15\r
+CYDEV_UCFG_B0_P2_U0_CFG15 EQU 0x4001044f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG16\r
+CYDEV_UCFG_B0_P2_U0_CFG16 EQU 0x40010450\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG17\r
+CYDEV_UCFG_B0_P2_U0_CFG17 EQU 0x40010451\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG18\r
+CYDEV_UCFG_B0_P2_U0_CFG18 EQU 0x40010452\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG19\r
+CYDEV_UCFG_B0_P2_U0_CFG19 EQU 0x40010453\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG20\r
+CYDEV_UCFG_B0_P2_U0_CFG20 EQU 0x40010454\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG21\r
+CYDEV_UCFG_B0_P2_U0_CFG21 EQU 0x40010455\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG22\r
+CYDEV_UCFG_B0_P2_U0_CFG22 EQU 0x40010456\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG23\r
+CYDEV_UCFG_B0_P2_U0_CFG23 EQU 0x40010457\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG24\r
+CYDEV_UCFG_B0_P2_U0_CFG24 EQU 0x40010458\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG25\r
+CYDEV_UCFG_B0_P2_U0_CFG25 EQU 0x40010459\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG26\r
+CYDEV_UCFG_B0_P2_U0_CFG26 EQU 0x4001045a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG27\r
+CYDEV_UCFG_B0_P2_U0_CFG27 EQU 0x4001045b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG28\r
+CYDEV_UCFG_B0_P2_U0_CFG28 EQU 0x4001045c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG29\r
+CYDEV_UCFG_B0_P2_U0_CFG29 EQU 0x4001045d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG30\r
+CYDEV_UCFG_B0_P2_U0_CFG30 EQU 0x4001045e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG31\r
+CYDEV_UCFG_B0_P2_U0_CFG31 EQU 0x4001045f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG0\r
+CYDEV_UCFG_B0_P2_U0_DCFG0 EQU 0x40010460\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG1\r
+CYDEV_UCFG_B0_P2_U0_DCFG1 EQU 0x40010462\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG2\r
+CYDEV_UCFG_B0_P2_U0_DCFG2 EQU 0x40010464\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG3\r
+CYDEV_UCFG_B0_P2_U0_DCFG3 EQU 0x40010466\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG4\r
+CYDEV_UCFG_B0_P2_U0_DCFG4 EQU 0x40010468\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG5\r
+CYDEV_UCFG_B0_P2_U0_DCFG5 EQU 0x4001046a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG6\r
+CYDEV_UCFG_B0_P2_U0_DCFG6 EQU 0x4001046c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG7\r
+CYDEV_UCFG_B0_P2_U0_DCFG7 EQU 0x4001046e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_BASE\r
+CYDEV_UCFG_B0_P2_U1_BASE EQU 0x40010480\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_SIZE\r
+CYDEV_UCFG_B0_P2_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT0\r
+CYDEV_UCFG_B0_P2_U1_PLD_IT0 EQU 0x40010480\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT1\r
+CYDEV_UCFG_B0_P2_U1_PLD_IT1 EQU 0x40010484\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT2\r
+CYDEV_UCFG_B0_P2_U1_PLD_IT2 EQU 0x40010488\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT3\r
+CYDEV_UCFG_B0_P2_U1_PLD_IT3 EQU 0x4001048c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT4\r
+CYDEV_UCFG_B0_P2_U1_PLD_IT4 EQU 0x40010490\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT5\r
+CYDEV_UCFG_B0_P2_U1_PLD_IT5 EQU 0x40010494\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT6\r
+CYDEV_UCFG_B0_P2_U1_PLD_IT6 EQU 0x40010498\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT7\r
+CYDEV_UCFG_B0_P2_U1_PLD_IT7 EQU 0x4001049c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT8\r
+CYDEV_UCFG_B0_P2_U1_PLD_IT8 EQU 0x400104a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT9\r
+CYDEV_UCFG_B0_P2_U1_PLD_IT9 EQU 0x400104a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT10\r
+CYDEV_UCFG_B0_P2_U1_PLD_IT10 EQU 0x400104a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT11\r
+CYDEV_UCFG_B0_P2_U1_PLD_IT11 EQU 0x400104ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT0\r
+CYDEV_UCFG_B0_P2_U1_PLD_ORT0 EQU 0x400104b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT1\r
+CYDEV_UCFG_B0_P2_U1_PLD_ORT1 EQU 0x400104b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT2\r
+CYDEV_UCFG_B0_P2_U1_PLD_ORT2 EQU 0x400104b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT3\r
+CYDEV_UCFG_B0_P2_U1_PLD_ORT3 EQU 0x400104b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST EQU 0x400104b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB\r
+CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB EQU 0x400104ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET EQU 0x400104bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS\r
+CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS EQU 0x400104be\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG0\r
+CYDEV_UCFG_B0_P2_U1_CFG0 EQU 0x400104c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG1\r
+CYDEV_UCFG_B0_P2_U1_CFG1 EQU 0x400104c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG2\r
+CYDEV_UCFG_B0_P2_U1_CFG2 EQU 0x400104c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG3\r
+CYDEV_UCFG_B0_P2_U1_CFG3 EQU 0x400104c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG4\r
+CYDEV_UCFG_B0_P2_U1_CFG4 EQU 0x400104c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG5\r
+CYDEV_UCFG_B0_P2_U1_CFG5 EQU 0x400104c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG6\r
+CYDEV_UCFG_B0_P2_U1_CFG6 EQU 0x400104c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG7\r
+CYDEV_UCFG_B0_P2_U1_CFG7 EQU 0x400104c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG8\r
+CYDEV_UCFG_B0_P2_U1_CFG8 EQU 0x400104c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG9\r
+CYDEV_UCFG_B0_P2_U1_CFG9 EQU 0x400104c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG10\r
+CYDEV_UCFG_B0_P2_U1_CFG10 EQU 0x400104ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG11\r
+CYDEV_UCFG_B0_P2_U1_CFG11 EQU 0x400104cb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG12\r
+CYDEV_UCFG_B0_P2_U1_CFG12 EQU 0x400104cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG13\r
+CYDEV_UCFG_B0_P2_U1_CFG13 EQU 0x400104cd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG14\r
+CYDEV_UCFG_B0_P2_U1_CFG14 EQU 0x400104ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG15\r
+CYDEV_UCFG_B0_P2_U1_CFG15 EQU 0x400104cf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG16\r
+CYDEV_UCFG_B0_P2_U1_CFG16 EQU 0x400104d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG17\r
+CYDEV_UCFG_B0_P2_U1_CFG17 EQU 0x400104d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG18\r
+CYDEV_UCFG_B0_P2_U1_CFG18 EQU 0x400104d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG19\r
+CYDEV_UCFG_B0_P2_U1_CFG19 EQU 0x400104d3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG20\r
+CYDEV_UCFG_B0_P2_U1_CFG20 EQU 0x400104d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG21\r
+CYDEV_UCFG_B0_P2_U1_CFG21 EQU 0x400104d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG22\r
+CYDEV_UCFG_B0_P2_U1_CFG22 EQU 0x400104d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG23\r
+CYDEV_UCFG_B0_P2_U1_CFG23 EQU 0x400104d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG24\r
+CYDEV_UCFG_B0_P2_U1_CFG24 EQU 0x400104d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG25\r
+CYDEV_UCFG_B0_P2_U1_CFG25 EQU 0x400104d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG26\r
+CYDEV_UCFG_B0_P2_U1_CFG26 EQU 0x400104da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG27\r
+CYDEV_UCFG_B0_P2_U1_CFG27 EQU 0x400104db\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG28\r
+CYDEV_UCFG_B0_P2_U1_CFG28 EQU 0x400104dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG29\r
+CYDEV_UCFG_B0_P2_U1_CFG29 EQU 0x400104dd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG30\r
+CYDEV_UCFG_B0_P2_U1_CFG30 EQU 0x400104de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG31\r
+CYDEV_UCFG_B0_P2_U1_CFG31 EQU 0x400104df\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG0\r
+CYDEV_UCFG_B0_P2_U1_DCFG0 EQU 0x400104e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG1\r
+CYDEV_UCFG_B0_P2_U1_DCFG1 EQU 0x400104e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG2\r
+CYDEV_UCFG_B0_P2_U1_DCFG2 EQU 0x400104e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG3\r
+CYDEV_UCFG_B0_P2_U1_DCFG3 EQU 0x400104e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG4\r
+CYDEV_UCFG_B0_P2_U1_DCFG4 EQU 0x400104e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG5\r
+CYDEV_UCFG_B0_P2_U1_DCFG5 EQU 0x400104ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG6\r
+CYDEV_UCFG_B0_P2_U1_DCFG6 EQU 0x400104ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG7\r
+CYDEV_UCFG_B0_P2_U1_DCFG7 EQU 0x400104ee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_BASE\r
+CYDEV_UCFG_B0_P2_ROUTE_BASE EQU 0x40010500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_SIZE\r
+CYDEV_UCFG_B0_P2_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_BASE\r
+CYDEV_UCFG_B0_P3_BASE EQU 0x40010600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_SIZE\r
+CYDEV_UCFG_B0_P3_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_BASE\r
+CYDEV_UCFG_B0_P3_U0_BASE EQU 0x40010600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_SIZE\r
+CYDEV_UCFG_B0_P3_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT0\r
+CYDEV_UCFG_B0_P3_U0_PLD_IT0 EQU 0x40010600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT1\r
+CYDEV_UCFG_B0_P3_U0_PLD_IT1 EQU 0x40010604\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT2\r
+CYDEV_UCFG_B0_P3_U0_PLD_IT2 EQU 0x40010608\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT3\r
+CYDEV_UCFG_B0_P3_U0_PLD_IT3 EQU 0x4001060c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT4\r
+CYDEV_UCFG_B0_P3_U0_PLD_IT4 EQU 0x40010610\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT5\r
+CYDEV_UCFG_B0_P3_U0_PLD_IT5 EQU 0x40010614\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT6\r
+CYDEV_UCFG_B0_P3_U0_PLD_IT6 EQU 0x40010618\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT7\r
+CYDEV_UCFG_B0_P3_U0_PLD_IT7 EQU 0x4001061c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT8\r
+CYDEV_UCFG_B0_P3_U0_PLD_IT8 EQU 0x40010620\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT9\r
+CYDEV_UCFG_B0_P3_U0_PLD_IT9 EQU 0x40010624\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT10\r
+CYDEV_UCFG_B0_P3_U0_PLD_IT10 EQU 0x40010628\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT11\r
+CYDEV_UCFG_B0_P3_U0_PLD_IT11 EQU 0x4001062c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT0\r
+CYDEV_UCFG_B0_P3_U0_PLD_ORT0 EQU 0x40010630\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT1\r
+CYDEV_UCFG_B0_P3_U0_PLD_ORT1 EQU 0x40010632\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT2\r
+CYDEV_UCFG_B0_P3_U0_PLD_ORT2 EQU 0x40010634\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT3\r
+CYDEV_UCFG_B0_P3_U0_PLD_ORT3 EQU 0x40010636\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST EQU 0x40010638\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB\r
+CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB EQU 0x4001063a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET EQU 0x4001063c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS\r
+CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS EQU 0x4001063e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG0\r
+CYDEV_UCFG_B0_P3_U0_CFG0 EQU 0x40010640\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG1\r
+CYDEV_UCFG_B0_P3_U0_CFG1 EQU 0x40010641\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG2\r
+CYDEV_UCFG_B0_P3_U0_CFG2 EQU 0x40010642\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG3\r
+CYDEV_UCFG_B0_P3_U0_CFG3 EQU 0x40010643\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG4\r
+CYDEV_UCFG_B0_P3_U0_CFG4 EQU 0x40010644\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG5\r
+CYDEV_UCFG_B0_P3_U0_CFG5 EQU 0x40010645\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG6\r
+CYDEV_UCFG_B0_P3_U0_CFG6 EQU 0x40010646\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG7\r
+CYDEV_UCFG_B0_P3_U0_CFG7 EQU 0x40010647\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG8\r
+CYDEV_UCFG_B0_P3_U0_CFG8 EQU 0x40010648\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG9\r
+CYDEV_UCFG_B0_P3_U0_CFG9 EQU 0x40010649\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG10\r
+CYDEV_UCFG_B0_P3_U0_CFG10 EQU 0x4001064a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG11\r
+CYDEV_UCFG_B0_P3_U0_CFG11 EQU 0x4001064b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG12\r
+CYDEV_UCFG_B0_P3_U0_CFG12 EQU 0x4001064c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG13\r
+CYDEV_UCFG_B0_P3_U0_CFG13 EQU 0x4001064d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG14\r
+CYDEV_UCFG_B0_P3_U0_CFG14 EQU 0x4001064e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG15\r
+CYDEV_UCFG_B0_P3_U0_CFG15 EQU 0x4001064f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG16\r
+CYDEV_UCFG_B0_P3_U0_CFG16 EQU 0x40010650\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG17\r
+CYDEV_UCFG_B0_P3_U0_CFG17 EQU 0x40010651\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG18\r
+CYDEV_UCFG_B0_P3_U0_CFG18 EQU 0x40010652\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG19\r
+CYDEV_UCFG_B0_P3_U0_CFG19 EQU 0x40010653\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG20\r
+CYDEV_UCFG_B0_P3_U0_CFG20 EQU 0x40010654\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG21\r
+CYDEV_UCFG_B0_P3_U0_CFG21 EQU 0x40010655\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG22\r
+CYDEV_UCFG_B0_P3_U0_CFG22 EQU 0x40010656\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG23\r
+CYDEV_UCFG_B0_P3_U0_CFG23 EQU 0x40010657\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG24\r
+CYDEV_UCFG_B0_P3_U0_CFG24 EQU 0x40010658\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG25\r
+CYDEV_UCFG_B0_P3_U0_CFG25 EQU 0x40010659\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG26\r
+CYDEV_UCFG_B0_P3_U0_CFG26 EQU 0x4001065a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG27\r
+CYDEV_UCFG_B0_P3_U0_CFG27 EQU 0x4001065b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG28\r
+CYDEV_UCFG_B0_P3_U0_CFG28 EQU 0x4001065c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG29\r
+CYDEV_UCFG_B0_P3_U0_CFG29 EQU 0x4001065d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG30\r
+CYDEV_UCFG_B0_P3_U0_CFG30 EQU 0x4001065e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG31\r
+CYDEV_UCFG_B0_P3_U0_CFG31 EQU 0x4001065f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG0\r
+CYDEV_UCFG_B0_P3_U0_DCFG0 EQU 0x40010660\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG1\r
+CYDEV_UCFG_B0_P3_U0_DCFG1 EQU 0x40010662\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG2\r
+CYDEV_UCFG_B0_P3_U0_DCFG2 EQU 0x40010664\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG3\r
+CYDEV_UCFG_B0_P3_U0_DCFG3 EQU 0x40010666\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG4\r
+CYDEV_UCFG_B0_P3_U0_DCFG4 EQU 0x40010668\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG5\r
+CYDEV_UCFG_B0_P3_U0_DCFG5 EQU 0x4001066a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG6\r
+CYDEV_UCFG_B0_P3_U0_DCFG6 EQU 0x4001066c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG7\r
+CYDEV_UCFG_B0_P3_U0_DCFG7 EQU 0x4001066e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_BASE\r
+CYDEV_UCFG_B0_P3_U1_BASE EQU 0x40010680\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_SIZE\r
+CYDEV_UCFG_B0_P3_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT0\r
+CYDEV_UCFG_B0_P3_U1_PLD_IT0 EQU 0x40010680\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT1\r
+CYDEV_UCFG_B0_P3_U1_PLD_IT1 EQU 0x40010684\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT2\r
+CYDEV_UCFG_B0_P3_U1_PLD_IT2 EQU 0x40010688\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT3\r
+CYDEV_UCFG_B0_P3_U1_PLD_IT3 EQU 0x4001068c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT4\r
+CYDEV_UCFG_B0_P3_U1_PLD_IT4 EQU 0x40010690\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT5\r
+CYDEV_UCFG_B0_P3_U1_PLD_IT5 EQU 0x40010694\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT6\r
+CYDEV_UCFG_B0_P3_U1_PLD_IT6 EQU 0x40010698\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT7\r
+CYDEV_UCFG_B0_P3_U1_PLD_IT7 EQU 0x4001069c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT8\r
+CYDEV_UCFG_B0_P3_U1_PLD_IT8 EQU 0x400106a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT9\r
+CYDEV_UCFG_B0_P3_U1_PLD_IT9 EQU 0x400106a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT10\r
+CYDEV_UCFG_B0_P3_U1_PLD_IT10 EQU 0x400106a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT11\r
+CYDEV_UCFG_B0_P3_U1_PLD_IT11 EQU 0x400106ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT0\r
+CYDEV_UCFG_B0_P3_U1_PLD_ORT0 EQU 0x400106b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT1\r
+CYDEV_UCFG_B0_P3_U1_PLD_ORT1 EQU 0x400106b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT2\r
+CYDEV_UCFG_B0_P3_U1_PLD_ORT2 EQU 0x400106b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT3\r
+CYDEV_UCFG_B0_P3_U1_PLD_ORT3 EQU 0x400106b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST EQU 0x400106b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB\r
+CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB EQU 0x400106ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET EQU 0x400106bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS\r
+CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS EQU 0x400106be\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG0\r
+CYDEV_UCFG_B0_P3_U1_CFG0 EQU 0x400106c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG1\r
+CYDEV_UCFG_B0_P3_U1_CFG1 EQU 0x400106c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG2\r
+CYDEV_UCFG_B0_P3_U1_CFG2 EQU 0x400106c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG3\r
+CYDEV_UCFG_B0_P3_U1_CFG3 EQU 0x400106c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG4\r
+CYDEV_UCFG_B0_P3_U1_CFG4 EQU 0x400106c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG5\r
+CYDEV_UCFG_B0_P3_U1_CFG5 EQU 0x400106c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG6\r
+CYDEV_UCFG_B0_P3_U1_CFG6 EQU 0x400106c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG7\r
+CYDEV_UCFG_B0_P3_U1_CFG7 EQU 0x400106c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG8\r
+CYDEV_UCFG_B0_P3_U1_CFG8 EQU 0x400106c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG9\r
+CYDEV_UCFG_B0_P3_U1_CFG9 EQU 0x400106c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG10\r
+CYDEV_UCFG_B0_P3_U1_CFG10 EQU 0x400106ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG11\r
+CYDEV_UCFG_B0_P3_U1_CFG11 EQU 0x400106cb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG12\r
+CYDEV_UCFG_B0_P3_U1_CFG12 EQU 0x400106cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG13\r
+CYDEV_UCFG_B0_P3_U1_CFG13 EQU 0x400106cd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG14\r
+CYDEV_UCFG_B0_P3_U1_CFG14 EQU 0x400106ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG15\r
+CYDEV_UCFG_B0_P3_U1_CFG15 EQU 0x400106cf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG16\r
+CYDEV_UCFG_B0_P3_U1_CFG16 EQU 0x400106d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG17\r
+CYDEV_UCFG_B0_P3_U1_CFG17 EQU 0x400106d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG18\r
+CYDEV_UCFG_B0_P3_U1_CFG18 EQU 0x400106d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG19\r
+CYDEV_UCFG_B0_P3_U1_CFG19 EQU 0x400106d3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG20\r
+CYDEV_UCFG_B0_P3_U1_CFG20 EQU 0x400106d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG21\r
+CYDEV_UCFG_B0_P3_U1_CFG21 EQU 0x400106d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG22\r
+CYDEV_UCFG_B0_P3_U1_CFG22 EQU 0x400106d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG23\r
+CYDEV_UCFG_B0_P3_U1_CFG23 EQU 0x400106d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG24\r
+CYDEV_UCFG_B0_P3_U1_CFG24 EQU 0x400106d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG25\r
+CYDEV_UCFG_B0_P3_U1_CFG25 EQU 0x400106d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG26\r
+CYDEV_UCFG_B0_P3_U1_CFG26 EQU 0x400106da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG27\r
+CYDEV_UCFG_B0_P3_U1_CFG27 EQU 0x400106db\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG28\r
+CYDEV_UCFG_B0_P3_U1_CFG28 EQU 0x400106dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG29\r
+CYDEV_UCFG_B0_P3_U1_CFG29 EQU 0x400106dd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG30\r
+CYDEV_UCFG_B0_P3_U1_CFG30 EQU 0x400106de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG31\r
+CYDEV_UCFG_B0_P3_U1_CFG31 EQU 0x400106df\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG0\r
+CYDEV_UCFG_B0_P3_U1_DCFG0 EQU 0x400106e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG1\r
+CYDEV_UCFG_B0_P3_U1_DCFG1 EQU 0x400106e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG2\r
+CYDEV_UCFG_B0_P3_U1_DCFG2 EQU 0x400106e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG3\r
+CYDEV_UCFG_B0_P3_U1_DCFG3 EQU 0x400106e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG4\r
+CYDEV_UCFG_B0_P3_U1_DCFG4 EQU 0x400106e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG5\r
+CYDEV_UCFG_B0_P3_U1_DCFG5 EQU 0x400106ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG6\r
+CYDEV_UCFG_B0_P3_U1_DCFG6 EQU 0x400106ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG7\r
+CYDEV_UCFG_B0_P3_U1_DCFG7 EQU 0x400106ee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_BASE\r
+CYDEV_UCFG_B0_P3_ROUTE_BASE EQU 0x40010700\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_SIZE\r
+CYDEV_UCFG_B0_P3_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_BASE\r
+CYDEV_UCFG_B0_P4_BASE EQU 0x40010800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_SIZE\r
+CYDEV_UCFG_B0_P4_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_BASE\r
+CYDEV_UCFG_B0_P4_U0_BASE EQU 0x40010800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_SIZE\r
+CYDEV_UCFG_B0_P4_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT0\r
+CYDEV_UCFG_B0_P4_U0_PLD_IT0 EQU 0x40010800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT1\r
+CYDEV_UCFG_B0_P4_U0_PLD_IT1 EQU 0x40010804\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT2\r
+CYDEV_UCFG_B0_P4_U0_PLD_IT2 EQU 0x40010808\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT3\r
+CYDEV_UCFG_B0_P4_U0_PLD_IT3 EQU 0x4001080c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT4\r
+CYDEV_UCFG_B0_P4_U0_PLD_IT4 EQU 0x40010810\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT5\r
+CYDEV_UCFG_B0_P4_U0_PLD_IT5 EQU 0x40010814\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT6\r
+CYDEV_UCFG_B0_P4_U0_PLD_IT6 EQU 0x40010818\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT7\r
+CYDEV_UCFG_B0_P4_U0_PLD_IT7 EQU 0x4001081c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT8\r
+CYDEV_UCFG_B0_P4_U0_PLD_IT8 EQU 0x40010820\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT9\r
+CYDEV_UCFG_B0_P4_U0_PLD_IT9 EQU 0x40010824\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT10\r
+CYDEV_UCFG_B0_P4_U0_PLD_IT10 EQU 0x40010828\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT11\r
+CYDEV_UCFG_B0_P4_U0_PLD_IT11 EQU 0x4001082c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT0\r
+CYDEV_UCFG_B0_P4_U0_PLD_ORT0 EQU 0x40010830\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT1\r
+CYDEV_UCFG_B0_P4_U0_PLD_ORT1 EQU 0x40010832\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT2\r
+CYDEV_UCFG_B0_P4_U0_PLD_ORT2 EQU 0x40010834\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT3\r
+CYDEV_UCFG_B0_P4_U0_PLD_ORT3 EQU 0x40010836\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST EQU 0x40010838\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB\r
+CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB EQU 0x4001083a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET EQU 0x4001083c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS\r
+CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS EQU 0x4001083e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG0\r
+CYDEV_UCFG_B0_P4_U0_CFG0 EQU 0x40010840\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG1\r
+CYDEV_UCFG_B0_P4_U0_CFG1 EQU 0x40010841\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG2\r
+CYDEV_UCFG_B0_P4_U0_CFG2 EQU 0x40010842\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG3\r
+CYDEV_UCFG_B0_P4_U0_CFG3 EQU 0x40010843\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG4\r
+CYDEV_UCFG_B0_P4_U0_CFG4 EQU 0x40010844\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG5\r
+CYDEV_UCFG_B0_P4_U0_CFG5 EQU 0x40010845\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG6\r
+CYDEV_UCFG_B0_P4_U0_CFG6 EQU 0x40010846\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG7\r
+CYDEV_UCFG_B0_P4_U0_CFG7 EQU 0x40010847\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG8\r
+CYDEV_UCFG_B0_P4_U0_CFG8 EQU 0x40010848\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG9\r
+CYDEV_UCFG_B0_P4_U0_CFG9 EQU 0x40010849\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG10\r
+CYDEV_UCFG_B0_P4_U0_CFG10 EQU 0x4001084a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG11\r
+CYDEV_UCFG_B0_P4_U0_CFG11 EQU 0x4001084b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG12\r
+CYDEV_UCFG_B0_P4_U0_CFG12 EQU 0x4001084c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG13\r
+CYDEV_UCFG_B0_P4_U0_CFG13 EQU 0x4001084d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG14\r
+CYDEV_UCFG_B0_P4_U0_CFG14 EQU 0x4001084e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG15\r
+CYDEV_UCFG_B0_P4_U0_CFG15 EQU 0x4001084f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG16\r
+CYDEV_UCFG_B0_P4_U0_CFG16 EQU 0x40010850\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG17\r
+CYDEV_UCFG_B0_P4_U0_CFG17 EQU 0x40010851\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG18\r
+CYDEV_UCFG_B0_P4_U0_CFG18 EQU 0x40010852\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG19\r
+CYDEV_UCFG_B0_P4_U0_CFG19 EQU 0x40010853\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG20\r
+CYDEV_UCFG_B0_P4_U0_CFG20 EQU 0x40010854\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG21\r
+CYDEV_UCFG_B0_P4_U0_CFG21 EQU 0x40010855\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG22\r
+CYDEV_UCFG_B0_P4_U0_CFG22 EQU 0x40010856\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG23\r
+CYDEV_UCFG_B0_P4_U0_CFG23 EQU 0x40010857\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG24\r
+CYDEV_UCFG_B0_P4_U0_CFG24 EQU 0x40010858\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG25\r
+CYDEV_UCFG_B0_P4_U0_CFG25 EQU 0x40010859\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG26\r
+CYDEV_UCFG_B0_P4_U0_CFG26 EQU 0x4001085a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG27\r
+CYDEV_UCFG_B0_P4_U0_CFG27 EQU 0x4001085b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG28\r
+CYDEV_UCFG_B0_P4_U0_CFG28 EQU 0x4001085c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG29\r
+CYDEV_UCFG_B0_P4_U0_CFG29 EQU 0x4001085d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG30\r
+CYDEV_UCFG_B0_P4_U0_CFG30 EQU 0x4001085e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG31\r
+CYDEV_UCFG_B0_P4_U0_CFG31 EQU 0x4001085f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG0\r
+CYDEV_UCFG_B0_P4_U0_DCFG0 EQU 0x40010860\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG1\r
+CYDEV_UCFG_B0_P4_U0_DCFG1 EQU 0x40010862\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG2\r
+CYDEV_UCFG_B0_P4_U0_DCFG2 EQU 0x40010864\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG3\r
+CYDEV_UCFG_B0_P4_U0_DCFG3 EQU 0x40010866\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG4\r
+CYDEV_UCFG_B0_P4_U0_DCFG4 EQU 0x40010868\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG5\r
+CYDEV_UCFG_B0_P4_U0_DCFG5 EQU 0x4001086a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG6\r
+CYDEV_UCFG_B0_P4_U0_DCFG6 EQU 0x4001086c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG7\r
+CYDEV_UCFG_B0_P4_U0_DCFG7 EQU 0x4001086e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_BASE\r
+CYDEV_UCFG_B0_P4_U1_BASE EQU 0x40010880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_SIZE\r
+CYDEV_UCFG_B0_P4_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT0\r
+CYDEV_UCFG_B0_P4_U1_PLD_IT0 EQU 0x40010880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT1\r
+CYDEV_UCFG_B0_P4_U1_PLD_IT1 EQU 0x40010884\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT2\r
+CYDEV_UCFG_B0_P4_U1_PLD_IT2 EQU 0x40010888\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT3\r
+CYDEV_UCFG_B0_P4_U1_PLD_IT3 EQU 0x4001088c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT4\r
+CYDEV_UCFG_B0_P4_U1_PLD_IT4 EQU 0x40010890\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT5\r
+CYDEV_UCFG_B0_P4_U1_PLD_IT5 EQU 0x40010894\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT6\r
+CYDEV_UCFG_B0_P4_U1_PLD_IT6 EQU 0x40010898\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT7\r
+CYDEV_UCFG_B0_P4_U1_PLD_IT7 EQU 0x4001089c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT8\r
+CYDEV_UCFG_B0_P4_U1_PLD_IT8 EQU 0x400108a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT9\r
+CYDEV_UCFG_B0_P4_U1_PLD_IT9 EQU 0x400108a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT10\r
+CYDEV_UCFG_B0_P4_U1_PLD_IT10 EQU 0x400108a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT11\r
+CYDEV_UCFG_B0_P4_U1_PLD_IT11 EQU 0x400108ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT0\r
+CYDEV_UCFG_B0_P4_U1_PLD_ORT0 EQU 0x400108b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT1\r
+CYDEV_UCFG_B0_P4_U1_PLD_ORT1 EQU 0x400108b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT2\r
+CYDEV_UCFG_B0_P4_U1_PLD_ORT2 EQU 0x400108b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT3\r
+CYDEV_UCFG_B0_P4_U1_PLD_ORT3 EQU 0x400108b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST EQU 0x400108b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB\r
+CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB EQU 0x400108ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET EQU 0x400108bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS\r
+CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS EQU 0x400108be\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG0\r
+CYDEV_UCFG_B0_P4_U1_CFG0 EQU 0x400108c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG1\r
+CYDEV_UCFG_B0_P4_U1_CFG1 EQU 0x400108c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG2\r
+CYDEV_UCFG_B0_P4_U1_CFG2 EQU 0x400108c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG3\r
+CYDEV_UCFG_B0_P4_U1_CFG3 EQU 0x400108c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG4\r
+CYDEV_UCFG_B0_P4_U1_CFG4 EQU 0x400108c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG5\r
+CYDEV_UCFG_B0_P4_U1_CFG5 EQU 0x400108c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG6\r
+CYDEV_UCFG_B0_P4_U1_CFG6 EQU 0x400108c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG7\r
+CYDEV_UCFG_B0_P4_U1_CFG7 EQU 0x400108c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG8\r
+CYDEV_UCFG_B0_P4_U1_CFG8 EQU 0x400108c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG9\r
+CYDEV_UCFG_B0_P4_U1_CFG9 EQU 0x400108c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG10\r
+CYDEV_UCFG_B0_P4_U1_CFG10 EQU 0x400108ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG11\r
+CYDEV_UCFG_B0_P4_U1_CFG11 EQU 0x400108cb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG12\r
+CYDEV_UCFG_B0_P4_U1_CFG12 EQU 0x400108cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG13\r
+CYDEV_UCFG_B0_P4_U1_CFG13 EQU 0x400108cd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG14\r
+CYDEV_UCFG_B0_P4_U1_CFG14 EQU 0x400108ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG15\r
+CYDEV_UCFG_B0_P4_U1_CFG15 EQU 0x400108cf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG16\r
+CYDEV_UCFG_B0_P4_U1_CFG16 EQU 0x400108d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG17\r
+CYDEV_UCFG_B0_P4_U1_CFG17 EQU 0x400108d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG18\r
+CYDEV_UCFG_B0_P4_U1_CFG18 EQU 0x400108d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG19\r
+CYDEV_UCFG_B0_P4_U1_CFG19 EQU 0x400108d3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG20\r
+CYDEV_UCFG_B0_P4_U1_CFG20 EQU 0x400108d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG21\r
+CYDEV_UCFG_B0_P4_U1_CFG21 EQU 0x400108d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG22\r
+CYDEV_UCFG_B0_P4_U1_CFG22 EQU 0x400108d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG23\r
+CYDEV_UCFG_B0_P4_U1_CFG23 EQU 0x400108d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG24\r
+CYDEV_UCFG_B0_P4_U1_CFG24 EQU 0x400108d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG25\r
+CYDEV_UCFG_B0_P4_U1_CFG25 EQU 0x400108d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG26\r
+CYDEV_UCFG_B0_P4_U1_CFG26 EQU 0x400108da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG27\r
+CYDEV_UCFG_B0_P4_U1_CFG27 EQU 0x400108db\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG28\r
+CYDEV_UCFG_B0_P4_U1_CFG28 EQU 0x400108dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG29\r
+CYDEV_UCFG_B0_P4_U1_CFG29 EQU 0x400108dd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG30\r
+CYDEV_UCFG_B0_P4_U1_CFG30 EQU 0x400108de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG31\r
+CYDEV_UCFG_B0_P4_U1_CFG31 EQU 0x400108df\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG0\r
+CYDEV_UCFG_B0_P4_U1_DCFG0 EQU 0x400108e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG1\r
+CYDEV_UCFG_B0_P4_U1_DCFG1 EQU 0x400108e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG2\r
+CYDEV_UCFG_B0_P4_U1_DCFG2 EQU 0x400108e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG3\r
+CYDEV_UCFG_B0_P4_U1_DCFG3 EQU 0x400108e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG4\r
+CYDEV_UCFG_B0_P4_U1_DCFG4 EQU 0x400108e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG5\r
+CYDEV_UCFG_B0_P4_U1_DCFG5 EQU 0x400108ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG6\r
+CYDEV_UCFG_B0_P4_U1_DCFG6 EQU 0x400108ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG7\r
+CYDEV_UCFG_B0_P4_U1_DCFG7 EQU 0x400108ee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_BASE\r
+CYDEV_UCFG_B0_P4_ROUTE_BASE EQU 0x40010900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_SIZE\r
+CYDEV_UCFG_B0_P4_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_BASE\r
+CYDEV_UCFG_B0_P5_BASE EQU 0x40010a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_SIZE\r
+CYDEV_UCFG_B0_P5_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_BASE\r
+CYDEV_UCFG_B0_P5_U0_BASE EQU 0x40010a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_SIZE\r
+CYDEV_UCFG_B0_P5_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT0\r
+CYDEV_UCFG_B0_P5_U0_PLD_IT0 EQU 0x40010a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT1\r
+CYDEV_UCFG_B0_P5_U0_PLD_IT1 EQU 0x40010a04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT2\r
+CYDEV_UCFG_B0_P5_U0_PLD_IT2 EQU 0x40010a08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT3\r
+CYDEV_UCFG_B0_P5_U0_PLD_IT3 EQU 0x40010a0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT4\r
+CYDEV_UCFG_B0_P5_U0_PLD_IT4 EQU 0x40010a10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT5\r
+CYDEV_UCFG_B0_P5_U0_PLD_IT5 EQU 0x40010a14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT6\r
+CYDEV_UCFG_B0_P5_U0_PLD_IT6 EQU 0x40010a18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT7\r
+CYDEV_UCFG_B0_P5_U0_PLD_IT7 EQU 0x40010a1c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT8\r
+CYDEV_UCFG_B0_P5_U0_PLD_IT8 EQU 0x40010a20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT9\r
+CYDEV_UCFG_B0_P5_U0_PLD_IT9 EQU 0x40010a24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT10\r
+CYDEV_UCFG_B0_P5_U0_PLD_IT10 EQU 0x40010a28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT11\r
+CYDEV_UCFG_B0_P5_U0_PLD_IT11 EQU 0x40010a2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT0\r
+CYDEV_UCFG_B0_P5_U0_PLD_ORT0 EQU 0x40010a30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT1\r
+CYDEV_UCFG_B0_P5_U0_PLD_ORT1 EQU 0x40010a32\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT2\r
+CYDEV_UCFG_B0_P5_U0_PLD_ORT2 EQU 0x40010a34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT3\r
+CYDEV_UCFG_B0_P5_U0_PLD_ORT3 EQU 0x40010a36\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST EQU 0x40010a38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB\r
+CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB EQU 0x40010a3a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET EQU 0x40010a3c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS\r
+CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS EQU 0x40010a3e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG0\r
+CYDEV_UCFG_B0_P5_U0_CFG0 EQU 0x40010a40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG1\r
+CYDEV_UCFG_B0_P5_U0_CFG1 EQU 0x40010a41\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG2\r
+CYDEV_UCFG_B0_P5_U0_CFG2 EQU 0x40010a42\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG3\r
+CYDEV_UCFG_B0_P5_U0_CFG3 EQU 0x40010a43\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG4\r
+CYDEV_UCFG_B0_P5_U0_CFG4 EQU 0x40010a44\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG5\r
+CYDEV_UCFG_B0_P5_U0_CFG5 EQU 0x40010a45\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG6\r
+CYDEV_UCFG_B0_P5_U0_CFG6 EQU 0x40010a46\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG7\r
+CYDEV_UCFG_B0_P5_U0_CFG7 EQU 0x40010a47\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG8\r
+CYDEV_UCFG_B0_P5_U0_CFG8 EQU 0x40010a48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG9\r
+CYDEV_UCFG_B0_P5_U0_CFG9 EQU 0x40010a49\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG10\r
+CYDEV_UCFG_B0_P5_U0_CFG10 EQU 0x40010a4a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG11\r
+CYDEV_UCFG_B0_P5_U0_CFG11 EQU 0x40010a4b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG12\r
+CYDEV_UCFG_B0_P5_U0_CFG12 EQU 0x40010a4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG13\r
+CYDEV_UCFG_B0_P5_U0_CFG13 EQU 0x40010a4d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG14\r
+CYDEV_UCFG_B0_P5_U0_CFG14 EQU 0x40010a4e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG15\r
+CYDEV_UCFG_B0_P5_U0_CFG15 EQU 0x40010a4f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG16\r
+CYDEV_UCFG_B0_P5_U0_CFG16 EQU 0x40010a50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG17\r
+CYDEV_UCFG_B0_P5_U0_CFG17 EQU 0x40010a51\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG18\r
+CYDEV_UCFG_B0_P5_U0_CFG18 EQU 0x40010a52\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG19\r
+CYDEV_UCFG_B0_P5_U0_CFG19 EQU 0x40010a53\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG20\r
+CYDEV_UCFG_B0_P5_U0_CFG20 EQU 0x40010a54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG21\r
+CYDEV_UCFG_B0_P5_U0_CFG21 EQU 0x40010a55\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG22\r
+CYDEV_UCFG_B0_P5_U0_CFG22 EQU 0x40010a56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG23\r
+CYDEV_UCFG_B0_P5_U0_CFG23 EQU 0x40010a57\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG24\r
+CYDEV_UCFG_B0_P5_U0_CFG24 EQU 0x40010a58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG25\r
+CYDEV_UCFG_B0_P5_U0_CFG25 EQU 0x40010a59\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG26\r
+CYDEV_UCFG_B0_P5_U0_CFG26 EQU 0x40010a5a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG27\r
+CYDEV_UCFG_B0_P5_U0_CFG27 EQU 0x40010a5b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG28\r
+CYDEV_UCFG_B0_P5_U0_CFG28 EQU 0x40010a5c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG29\r
+CYDEV_UCFG_B0_P5_U0_CFG29 EQU 0x40010a5d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG30\r
+CYDEV_UCFG_B0_P5_U0_CFG30 EQU 0x40010a5e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG31\r
+CYDEV_UCFG_B0_P5_U0_CFG31 EQU 0x40010a5f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG0\r
+CYDEV_UCFG_B0_P5_U0_DCFG0 EQU 0x40010a60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG1\r
+CYDEV_UCFG_B0_P5_U0_DCFG1 EQU 0x40010a62\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG2\r
+CYDEV_UCFG_B0_P5_U0_DCFG2 EQU 0x40010a64\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG3\r
+CYDEV_UCFG_B0_P5_U0_DCFG3 EQU 0x40010a66\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG4\r
+CYDEV_UCFG_B0_P5_U0_DCFG4 EQU 0x40010a68\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG5\r
+CYDEV_UCFG_B0_P5_U0_DCFG5 EQU 0x40010a6a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG6\r
+CYDEV_UCFG_B0_P5_U0_DCFG6 EQU 0x40010a6c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG7\r
+CYDEV_UCFG_B0_P5_U0_DCFG7 EQU 0x40010a6e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_BASE\r
+CYDEV_UCFG_B0_P5_U1_BASE EQU 0x40010a80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_SIZE\r
+CYDEV_UCFG_B0_P5_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT0\r
+CYDEV_UCFG_B0_P5_U1_PLD_IT0 EQU 0x40010a80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT1\r
+CYDEV_UCFG_B0_P5_U1_PLD_IT1 EQU 0x40010a84\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT2\r
+CYDEV_UCFG_B0_P5_U1_PLD_IT2 EQU 0x40010a88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT3\r
+CYDEV_UCFG_B0_P5_U1_PLD_IT3 EQU 0x40010a8c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT4\r
+CYDEV_UCFG_B0_P5_U1_PLD_IT4 EQU 0x40010a90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT5\r
+CYDEV_UCFG_B0_P5_U1_PLD_IT5 EQU 0x40010a94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT6\r
+CYDEV_UCFG_B0_P5_U1_PLD_IT6 EQU 0x40010a98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT7\r
+CYDEV_UCFG_B0_P5_U1_PLD_IT7 EQU 0x40010a9c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT8\r
+CYDEV_UCFG_B0_P5_U1_PLD_IT8 EQU 0x40010aa0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT9\r
+CYDEV_UCFG_B0_P5_U1_PLD_IT9 EQU 0x40010aa4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT10\r
+CYDEV_UCFG_B0_P5_U1_PLD_IT10 EQU 0x40010aa8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT11\r
+CYDEV_UCFG_B0_P5_U1_PLD_IT11 EQU 0x40010aac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT0\r
+CYDEV_UCFG_B0_P5_U1_PLD_ORT0 EQU 0x40010ab0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT1\r
+CYDEV_UCFG_B0_P5_U1_PLD_ORT1 EQU 0x40010ab2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT2\r
+CYDEV_UCFG_B0_P5_U1_PLD_ORT2 EQU 0x40010ab4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT3\r
+CYDEV_UCFG_B0_P5_U1_PLD_ORT3 EQU 0x40010ab6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST EQU 0x40010ab8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB\r
+CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB EQU 0x40010aba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET EQU 0x40010abc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS\r
+CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS EQU 0x40010abe\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG0\r
+CYDEV_UCFG_B0_P5_U1_CFG0 EQU 0x40010ac0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG1\r
+CYDEV_UCFG_B0_P5_U1_CFG1 EQU 0x40010ac1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG2\r
+CYDEV_UCFG_B0_P5_U1_CFG2 EQU 0x40010ac2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG3\r
+CYDEV_UCFG_B0_P5_U1_CFG3 EQU 0x40010ac3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG4\r
+CYDEV_UCFG_B0_P5_U1_CFG4 EQU 0x40010ac4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG5\r
+CYDEV_UCFG_B0_P5_U1_CFG5 EQU 0x40010ac5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG6\r
+CYDEV_UCFG_B0_P5_U1_CFG6 EQU 0x40010ac6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG7\r
+CYDEV_UCFG_B0_P5_U1_CFG7 EQU 0x40010ac7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG8\r
+CYDEV_UCFG_B0_P5_U1_CFG8 EQU 0x40010ac8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG9\r
+CYDEV_UCFG_B0_P5_U1_CFG9 EQU 0x40010ac9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG10\r
+CYDEV_UCFG_B0_P5_U1_CFG10 EQU 0x40010aca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG11\r
+CYDEV_UCFG_B0_P5_U1_CFG11 EQU 0x40010acb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG12\r
+CYDEV_UCFG_B0_P5_U1_CFG12 EQU 0x40010acc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG13\r
+CYDEV_UCFG_B0_P5_U1_CFG13 EQU 0x40010acd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG14\r
+CYDEV_UCFG_B0_P5_U1_CFG14 EQU 0x40010ace\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG15\r
+CYDEV_UCFG_B0_P5_U1_CFG15 EQU 0x40010acf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG16\r
+CYDEV_UCFG_B0_P5_U1_CFG16 EQU 0x40010ad0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG17\r
+CYDEV_UCFG_B0_P5_U1_CFG17 EQU 0x40010ad1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG18\r
+CYDEV_UCFG_B0_P5_U1_CFG18 EQU 0x40010ad2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG19\r
+CYDEV_UCFG_B0_P5_U1_CFG19 EQU 0x40010ad3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG20\r
+CYDEV_UCFG_B0_P5_U1_CFG20 EQU 0x40010ad4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG21\r
+CYDEV_UCFG_B0_P5_U1_CFG21 EQU 0x40010ad5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG22\r
+CYDEV_UCFG_B0_P5_U1_CFG22 EQU 0x40010ad6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG23\r
+CYDEV_UCFG_B0_P5_U1_CFG23 EQU 0x40010ad7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG24\r
+CYDEV_UCFG_B0_P5_U1_CFG24 EQU 0x40010ad8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG25\r
+CYDEV_UCFG_B0_P5_U1_CFG25 EQU 0x40010ad9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG26\r
+CYDEV_UCFG_B0_P5_U1_CFG26 EQU 0x40010ada\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG27\r
+CYDEV_UCFG_B0_P5_U1_CFG27 EQU 0x40010adb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG28\r
+CYDEV_UCFG_B0_P5_U1_CFG28 EQU 0x40010adc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG29\r
+CYDEV_UCFG_B0_P5_U1_CFG29 EQU 0x40010add\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG30\r
+CYDEV_UCFG_B0_P5_U1_CFG30 EQU 0x40010ade\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG31\r
+CYDEV_UCFG_B0_P5_U1_CFG31 EQU 0x40010adf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG0\r
+CYDEV_UCFG_B0_P5_U1_DCFG0 EQU 0x40010ae0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG1\r
+CYDEV_UCFG_B0_P5_U1_DCFG1 EQU 0x40010ae2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG2\r
+CYDEV_UCFG_B0_P5_U1_DCFG2 EQU 0x40010ae4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG3\r
+CYDEV_UCFG_B0_P5_U1_DCFG3 EQU 0x40010ae6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG4\r
+CYDEV_UCFG_B0_P5_U1_DCFG4 EQU 0x40010ae8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG5\r
+CYDEV_UCFG_B0_P5_U1_DCFG5 EQU 0x40010aea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG6\r
+CYDEV_UCFG_B0_P5_U1_DCFG6 EQU 0x40010aec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG7\r
+CYDEV_UCFG_B0_P5_U1_DCFG7 EQU 0x40010aee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_BASE\r
+CYDEV_UCFG_B0_P5_ROUTE_BASE EQU 0x40010b00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_SIZE\r
+CYDEV_UCFG_B0_P5_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_BASE\r
+CYDEV_UCFG_B0_P6_BASE EQU 0x40010c00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_SIZE\r
+CYDEV_UCFG_B0_P6_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_BASE\r
+CYDEV_UCFG_B0_P6_U0_BASE EQU 0x40010c00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_SIZE\r
+CYDEV_UCFG_B0_P6_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT0\r
+CYDEV_UCFG_B0_P6_U0_PLD_IT0 EQU 0x40010c00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT1\r
+CYDEV_UCFG_B0_P6_U0_PLD_IT1 EQU 0x40010c04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT2\r
+CYDEV_UCFG_B0_P6_U0_PLD_IT2 EQU 0x40010c08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT3\r
+CYDEV_UCFG_B0_P6_U0_PLD_IT3 EQU 0x40010c0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT4\r
+CYDEV_UCFG_B0_P6_U0_PLD_IT4 EQU 0x40010c10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT5\r
+CYDEV_UCFG_B0_P6_U0_PLD_IT5 EQU 0x40010c14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT6\r
+CYDEV_UCFG_B0_P6_U0_PLD_IT6 EQU 0x40010c18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT7\r
+CYDEV_UCFG_B0_P6_U0_PLD_IT7 EQU 0x40010c1c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT8\r
+CYDEV_UCFG_B0_P6_U0_PLD_IT8 EQU 0x40010c20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT9\r
+CYDEV_UCFG_B0_P6_U0_PLD_IT9 EQU 0x40010c24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT10\r
+CYDEV_UCFG_B0_P6_U0_PLD_IT10 EQU 0x40010c28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT11\r
+CYDEV_UCFG_B0_P6_U0_PLD_IT11 EQU 0x40010c2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT0\r
+CYDEV_UCFG_B0_P6_U0_PLD_ORT0 EQU 0x40010c30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT1\r
+CYDEV_UCFG_B0_P6_U0_PLD_ORT1 EQU 0x40010c32\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT2\r
+CYDEV_UCFG_B0_P6_U0_PLD_ORT2 EQU 0x40010c34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT3\r
+CYDEV_UCFG_B0_P6_U0_PLD_ORT3 EQU 0x40010c36\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST EQU 0x40010c38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB\r
+CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB EQU 0x40010c3a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET EQU 0x40010c3c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS\r
+CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS EQU 0x40010c3e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG0\r
+CYDEV_UCFG_B0_P6_U0_CFG0 EQU 0x40010c40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG1\r
+CYDEV_UCFG_B0_P6_U0_CFG1 EQU 0x40010c41\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG2\r
+CYDEV_UCFG_B0_P6_U0_CFG2 EQU 0x40010c42\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG3\r
+CYDEV_UCFG_B0_P6_U0_CFG3 EQU 0x40010c43\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG4\r
+CYDEV_UCFG_B0_P6_U0_CFG4 EQU 0x40010c44\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG5\r
+CYDEV_UCFG_B0_P6_U0_CFG5 EQU 0x40010c45\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG6\r
+CYDEV_UCFG_B0_P6_U0_CFG6 EQU 0x40010c46\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG7\r
+CYDEV_UCFG_B0_P6_U0_CFG7 EQU 0x40010c47\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG8\r
+CYDEV_UCFG_B0_P6_U0_CFG8 EQU 0x40010c48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG9\r
+CYDEV_UCFG_B0_P6_U0_CFG9 EQU 0x40010c49\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG10\r
+CYDEV_UCFG_B0_P6_U0_CFG10 EQU 0x40010c4a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG11\r
+CYDEV_UCFG_B0_P6_U0_CFG11 EQU 0x40010c4b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG12\r
+CYDEV_UCFG_B0_P6_U0_CFG12 EQU 0x40010c4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG13\r
+CYDEV_UCFG_B0_P6_U0_CFG13 EQU 0x40010c4d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG14\r
+CYDEV_UCFG_B0_P6_U0_CFG14 EQU 0x40010c4e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG15\r
+CYDEV_UCFG_B0_P6_U0_CFG15 EQU 0x40010c4f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG16\r
+CYDEV_UCFG_B0_P6_U0_CFG16 EQU 0x40010c50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG17\r
+CYDEV_UCFG_B0_P6_U0_CFG17 EQU 0x40010c51\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG18\r
+CYDEV_UCFG_B0_P6_U0_CFG18 EQU 0x40010c52\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG19\r
+CYDEV_UCFG_B0_P6_U0_CFG19 EQU 0x40010c53\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG20\r
+CYDEV_UCFG_B0_P6_U0_CFG20 EQU 0x40010c54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG21\r
+CYDEV_UCFG_B0_P6_U0_CFG21 EQU 0x40010c55\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG22\r
+CYDEV_UCFG_B0_P6_U0_CFG22 EQU 0x40010c56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG23\r
+CYDEV_UCFG_B0_P6_U0_CFG23 EQU 0x40010c57\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG24\r
+CYDEV_UCFG_B0_P6_U0_CFG24 EQU 0x40010c58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG25\r
+CYDEV_UCFG_B0_P6_U0_CFG25 EQU 0x40010c59\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG26\r
+CYDEV_UCFG_B0_P6_U0_CFG26 EQU 0x40010c5a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG27\r
+CYDEV_UCFG_B0_P6_U0_CFG27 EQU 0x40010c5b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG28\r
+CYDEV_UCFG_B0_P6_U0_CFG28 EQU 0x40010c5c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG29\r
+CYDEV_UCFG_B0_P6_U0_CFG29 EQU 0x40010c5d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG30\r
+CYDEV_UCFG_B0_P6_U0_CFG30 EQU 0x40010c5e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG31\r
+CYDEV_UCFG_B0_P6_U0_CFG31 EQU 0x40010c5f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG0\r
+CYDEV_UCFG_B0_P6_U0_DCFG0 EQU 0x40010c60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG1\r
+CYDEV_UCFG_B0_P6_U0_DCFG1 EQU 0x40010c62\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG2\r
+CYDEV_UCFG_B0_P6_U0_DCFG2 EQU 0x40010c64\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG3\r
+CYDEV_UCFG_B0_P6_U0_DCFG3 EQU 0x40010c66\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG4\r
+CYDEV_UCFG_B0_P6_U0_DCFG4 EQU 0x40010c68\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG5\r
+CYDEV_UCFG_B0_P6_U0_DCFG5 EQU 0x40010c6a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG6\r
+CYDEV_UCFG_B0_P6_U0_DCFG6 EQU 0x40010c6c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG7\r
+CYDEV_UCFG_B0_P6_U0_DCFG7 EQU 0x40010c6e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_BASE\r
+CYDEV_UCFG_B0_P6_U1_BASE EQU 0x40010c80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_SIZE\r
+CYDEV_UCFG_B0_P6_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT0\r
+CYDEV_UCFG_B0_P6_U1_PLD_IT0 EQU 0x40010c80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT1\r
+CYDEV_UCFG_B0_P6_U1_PLD_IT1 EQU 0x40010c84\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT2\r
+CYDEV_UCFG_B0_P6_U1_PLD_IT2 EQU 0x40010c88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT3\r
+CYDEV_UCFG_B0_P6_U1_PLD_IT3 EQU 0x40010c8c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT4\r
+CYDEV_UCFG_B0_P6_U1_PLD_IT4 EQU 0x40010c90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT5\r
+CYDEV_UCFG_B0_P6_U1_PLD_IT5 EQU 0x40010c94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT6\r
+CYDEV_UCFG_B0_P6_U1_PLD_IT6 EQU 0x40010c98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT7\r
+CYDEV_UCFG_B0_P6_U1_PLD_IT7 EQU 0x40010c9c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT8\r
+CYDEV_UCFG_B0_P6_U1_PLD_IT8 EQU 0x40010ca0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT9\r
+CYDEV_UCFG_B0_P6_U1_PLD_IT9 EQU 0x40010ca4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT10\r
+CYDEV_UCFG_B0_P6_U1_PLD_IT10 EQU 0x40010ca8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT11\r
+CYDEV_UCFG_B0_P6_U1_PLD_IT11 EQU 0x40010cac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT0\r
+CYDEV_UCFG_B0_P6_U1_PLD_ORT0 EQU 0x40010cb0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT1\r
+CYDEV_UCFG_B0_P6_U1_PLD_ORT1 EQU 0x40010cb2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT2\r
+CYDEV_UCFG_B0_P6_U1_PLD_ORT2 EQU 0x40010cb4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT3\r
+CYDEV_UCFG_B0_P6_U1_PLD_ORT3 EQU 0x40010cb6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST EQU 0x40010cb8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB\r
+CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB EQU 0x40010cba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET EQU 0x40010cbc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS\r
+CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS EQU 0x40010cbe\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG0\r
+CYDEV_UCFG_B0_P6_U1_CFG0 EQU 0x40010cc0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG1\r
+CYDEV_UCFG_B0_P6_U1_CFG1 EQU 0x40010cc1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG2\r
+CYDEV_UCFG_B0_P6_U1_CFG2 EQU 0x40010cc2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG3\r
+CYDEV_UCFG_B0_P6_U1_CFG3 EQU 0x40010cc3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG4\r
+CYDEV_UCFG_B0_P6_U1_CFG4 EQU 0x40010cc4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG5\r
+CYDEV_UCFG_B0_P6_U1_CFG5 EQU 0x40010cc5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG6\r
+CYDEV_UCFG_B0_P6_U1_CFG6 EQU 0x40010cc6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG7\r
+CYDEV_UCFG_B0_P6_U1_CFG7 EQU 0x40010cc7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG8\r
+CYDEV_UCFG_B0_P6_U1_CFG8 EQU 0x40010cc8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG9\r
+CYDEV_UCFG_B0_P6_U1_CFG9 EQU 0x40010cc9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG10\r
+CYDEV_UCFG_B0_P6_U1_CFG10 EQU 0x40010cca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG11\r
+CYDEV_UCFG_B0_P6_U1_CFG11 EQU 0x40010ccb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG12\r
+CYDEV_UCFG_B0_P6_U1_CFG12 EQU 0x40010ccc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG13\r
+CYDEV_UCFG_B0_P6_U1_CFG13 EQU 0x40010ccd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG14\r
+CYDEV_UCFG_B0_P6_U1_CFG14 EQU 0x40010cce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG15\r
+CYDEV_UCFG_B0_P6_U1_CFG15 EQU 0x40010ccf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG16\r
+CYDEV_UCFG_B0_P6_U1_CFG16 EQU 0x40010cd0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG17\r
+CYDEV_UCFG_B0_P6_U1_CFG17 EQU 0x40010cd1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG18\r
+CYDEV_UCFG_B0_P6_U1_CFG18 EQU 0x40010cd2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG19\r
+CYDEV_UCFG_B0_P6_U1_CFG19 EQU 0x40010cd3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG20\r
+CYDEV_UCFG_B0_P6_U1_CFG20 EQU 0x40010cd4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG21\r
+CYDEV_UCFG_B0_P6_U1_CFG21 EQU 0x40010cd5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG22\r
+CYDEV_UCFG_B0_P6_U1_CFG22 EQU 0x40010cd6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG23\r
+CYDEV_UCFG_B0_P6_U1_CFG23 EQU 0x40010cd7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG24\r
+CYDEV_UCFG_B0_P6_U1_CFG24 EQU 0x40010cd8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG25\r
+CYDEV_UCFG_B0_P6_U1_CFG25 EQU 0x40010cd9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG26\r
+CYDEV_UCFG_B0_P6_U1_CFG26 EQU 0x40010cda\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG27\r
+CYDEV_UCFG_B0_P6_U1_CFG27 EQU 0x40010cdb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG28\r
+CYDEV_UCFG_B0_P6_U1_CFG28 EQU 0x40010cdc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG29\r
+CYDEV_UCFG_B0_P6_U1_CFG29 EQU 0x40010cdd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG30\r
+CYDEV_UCFG_B0_P6_U1_CFG30 EQU 0x40010cde\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG31\r
+CYDEV_UCFG_B0_P6_U1_CFG31 EQU 0x40010cdf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG0\r
+CYDEV_UCFG_B0_P6_U1_DCFG0 EQU 0x40010ce0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG1\r
+CYDEV_UCFG_B0_P6_U1_DCFG1 EQU 0x40010ce2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG2\r
+CYDEV_UCFG_B0_P6_U1_DCFG2 EQU 0x40010ce4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG3\r
+CYDEV_UCFG_B0_P6_U1_DCFG3 EQU 0x40010ce6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG4\r
+CYDEV_UCFG_B0_P6_U1_DCFG4 EQU 0x40010ce8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG5\r
+CYDEV_UCFG_B0_P6_U1_DCFG5 EQU 0x40010cea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG6\r
+CYDEV_UCFG_B0_P6_U1_DCFG6 EQU 0x40010cec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG7\r
+CYDEV_UCFG_B0_P6_U1_DCFG7 EQU 0x40010cee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_BASE\r
+CYDEV_UCFG_B0_P6_ROUTE_BASE EQU 0x40010d00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_SIZE\r
+CYDEV_UCFG_B0_P6_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_BASE\r
+CYDEV_UCFG_B0_P7_BASE EQU 0x40010e00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_SIZE\r
+CYDEV_UCFG_B0_P7_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_BASE\r
+CYDEV_UCFG_B0_P7_U0_BASE EQU 0x40010e00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_SIZE\r
+CYDEV_UCFG_B0_P7_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT0\r
+CYDEV_UCFG_B0_P7_U0_PLD_IT0 EQU 0x40010e00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT1\r
+CYDEV_UCFG_B0_P7_U0_PLD_IT1 EQU 0x40010e04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT2\r
+CYDEV_UCFG_B0_P7_U0_PLD_IT2 EQU 0x40010e08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT3\r
+CYDEV_UCFG_B0_P7_U0_PLD_IT3 EQU 0x40010e0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT4\r
+CYDEV_UCFG_B0_P7_U0_PLD_IT4 EQU 0x40010e10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT5\r
+CYDEV_UCFG_B0_P7_U0_PLD_IT5 EQU 0x40010e14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT6\r
+CYDEV_UCFG_B0_P7_U0_PLD_IT6 EQU 0x40010e18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT7\r
+CYDEV_UCFG_B0_P7_U0_PLD_IT7 EQU 0x40010e1c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT8\r
+CYDEV_UCFG_B0_P7_U0_PLD_IT8 EQU 0x40010e20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT9\r
+CYDEV_UCFG_B0_P7_U0_PLD_IT9 EQU 0x40010e24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT10\r
+CYDEV_UCFG_B0_P7_U0_PLD_IT10 EQU 0x40010e28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT11\r
+CYDEV_UCFG_B0_P7_U0_PLD_IT11 EQU 0x40010e2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT0\r
+CYDEV_UCFG_B0_P7_U0_PLD_ORT0 EQU 0x40010e30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT1\r
+CYDEV_UCFG_B0_P7_U0_PLD_ORT1 EQU 0x40010e32\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT2\r
+CYDEV_UCFG_B0_P7_U0_PLD_ORT2 EQU 0x40010e34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT3\r
+CYDEV_UCFG_B0_P7_U0_PLD_ORT3 EQU 0x40010e36\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST EQU 0x40010e38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB\r
+CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB EQU 0x40010e3a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET EQU 0x40010e3c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS\r
+CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS EQU 0x40010e3e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG0\r
+CYDEV_UCFG_B0_P7_U0_CFG0 EQU 0x40010e40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG1\r
+CYDEV_UCFG_B0_P7_U0_CFG1 EQU 0x40010e41\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG2\r
+CYDEV_UCFG_B0_P7_U0_CFG2 EQU 0x40010e42\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG3\r
+CYDEV_UCFG_B0_P7_U0_CFG3 EQU 0x40010e43\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG4\r
+CYDEV_UCFG_B0_P7_U0_CFG4 EQU 0x40010e44\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG5\r
+CYDEV_UCFG_B0_P7_U0_CFG5 EQU 0x40010e45\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG6\r
+CYDEV_UCFG_B0_P7_U0_CFG6 EQU 0x40010e46\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG7\r
+CYDEV_UCFG_B0_P7_U0_CFG7 EQU 0x40010e47\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG8\r
+CYDEV_UCFG_B0_P7_U0_CFG8 EQU 0x40010e48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG9\r
+CYDEV_UCFG_B0_P7_U0_CFG9 EQU 0x40010e49\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG10\r
+CYDEV_UCFG_B0_P7_U0_CFG10 EQU 0x40010e4a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG11\r
+CYDEV_UCFG_B0_P7_U0_CFG11 EQU 0x40010e4b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG12\r
+CYDEV_UCFG_B0_P7_U0_CFG12 EQU 0x40010e4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG13\r
+CYDEV_UCFG_B0_P7_U0_CFG13 EQU 0x40010e4d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG14\r
+CYDEV_UCFG_B0_P7_U0_CFG14 EQU 0x40010e4e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG15\r
+CYDEV_UCFG_B0_P7_U0_CFG15 EQU 0x40010e4f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG16\r
+CYDEV_UCFG_B0_P7_U0_CFG16 EQU 0x40010e50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG17\r
+CYDEV_UCFG_B0_P7_U0_CFG17 EQU 0x40010e51\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG18\r
+CYDEV_UCFG_B0_P7_U0_CFG18 EQU 0x40010e52\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG19\r
+CYDEV_UCFG_B0_P7_U0_CFG19 EQU 0x40010e53\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG20\r
+CYDEV_UCFG_B0_P7_U0_CFG20 EQU 0x40010e54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG21\r
+CYDEV_UCFG_B0_P7_U0_CFG21 EQU 0x40010e55\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG22\r
+CYDEV_UCFG_B0_P7_U0_CFG22 EQU 0x40010e56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG23\r
+CYDEV_UCFG_B0_P7_U0_CFG23 EQU 0x40010e57\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG24\r
+CYDEV_UCFG_B0_P7_U0_CFG24 EQU 0x40010e58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG25\r
+CYDEV_UCFG_B0_P7_U0_CFG25 EQU 0x40010e59\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG26\r
+CYDEV_UCFG_B0_P7_U0_CFG26 EQU 0x40010e5a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG27\r
+CYDEV_UCFG_B0_P7_U0_CFG27 EQU 0x40010e5b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG28\r
+CYDEV_UCFG_B0_P7_U0_CFG28 EQU 0x40010e5c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG29\r
+CYDEV_UCFG_B0_P7_U0_CFG29 EQU 0x40010e5d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG30\r
+CYDEV_UCFG_B0_P7_U0_CFG30 EQU 0x40010e5e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG31\r
+CYDEV_UCFG_B0_P7_U0_CFG31 EQU 0x40010e5f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG0\r
+CYDEV_UCFG_B0_P7_U0_DCFG0 EQU 0x40010e60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG1\r
+CYDEV_UCFG_B0_P7_U0_DCFG1 EQU 0x40010e62\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG2\r
+CYDEV_UCFG_B0_P7_U0_DCFG2 EQU 0x40010e64\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG3\r
+CYDEV_UCFG_B0_P7_U0_DCFG3 EQU 0x40010e66\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG4\r
+CYDEV_UCFG_B0_P7_U0_DCFG4 EQU 0x40010e68\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG5\r
+CYDEV_UCFG_B0_P7_U0_DCFG5 EQU 0x40010e6a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG6\r
+CYDEV_UCFG_B0_P7_U0_DCFG6 EQU 0x40010e6c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG7\r
+CYDEV_UCFG_B0_P7_U0_DCFG7 EQU 0x40010e6e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_BASE\r
+CYDEV_UCFG_B0_P7_U1_BASE EQU 0x40010e80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_SIZE\r
+CYDEV_UCFG_B0_P7_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT0\r
+CYDEV_UCFG_B0_P7_U1_PLD_IT0 EQU 0x40010e80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT1\r
+CYDEV_UCFG_B0_P7_U1_PLD_IT1 EQU 0x40010e84\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT2\r
+CYDEV_UCFG_B0_P7_U1_PLD_IT2 EQU 0x40010e88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT3\r
+CYDEV_UCFG_B0_P7_U1_PLD_IT3 EQU 0x40010e8c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT4\r
+CYDEV_UCFG_B0_P7_U1_PLD_IT4 EQU 0x40010e90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT5\r
+CYDEV_UCFG_B0_P7_U1_PLD_IT5 EQU 0x40010e94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT6\r
+CYDEV_UCFG_B0_P7_U1_PLD_IT6 EQU 0x40010e98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT7\r
+CYDEV_UCFG_B0_P7_U1_PLD_IT7 EQU 0x40010e9c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT8\r
+CYDEV_UCFG_B0_P7_U1_PLD_IT8 EQU 0x40010ea0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT9\r
+CYDEV_UCFG_B0_P7_U1_PLD_IT9 EQU 0x40010ea4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT10\r
+CYDEV_UCFG_B0_P7_U1_PLD_IT10 EQU 0x40010ea8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT11\r
+CYDEV_UCFG_B0_P7_U1_PLD_IT11 EQU 0x40010eac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT0\r
+CYDEV_UCFG_B0_P7_U1_PLD_ORT0 EQU 0x40010eb0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT1\r
+CYDEV_UCFG_B0_P7_U1_PLD_ORT1 EQU 0x40010eb2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT2\r
+CYDEV_UCFG_B0_P7_U1_PLD_ORT2 EQU 0x40010eb4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT3\r
+CYDEV_UCFG_B0_P7_U1_PLD_ORT3 EQU 0x40010eb6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST EQU 0x40010eb8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB\r
+CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB EQU 0x40010eba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET EQU 0x40010ebc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS\r
+CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS EQU 0x40010ebe\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG0\r
+CYDEV_UCFG_B0_P7_U1_CFG0 EQU 0x40010ec0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG1\r
+CYDEV_UCFG_B0_P7_U1_CFG1 EQU 0x40010ec1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG2\r
+CYDEV_UCFG_B0_P7_U1_CFG2 EQU 0x40010ec2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG3\r
+CYDEV_UCFG_B0_P7_U1_CFG3 EQU 0x40010ec3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG4\r
+CYDEV_UCFG_B0_P7_U1_CFG4 EQU 0x40010ec4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG5\r
+CYDEV_UCFG_B0_P7_U1_CFG5 EQU 0x40010ec5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG6\r
+CYDEV_UCFG_B0_P7_U1_CFG6 EQU 0x40010ec6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG7\r
+CYDEV_UCFG_B0_P7_U1_CFG7 EQU 0x40010ec7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG8\r
+CYDEV_UCFG_B0_P7_U1_CFG8 EQU 0x40010ec8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG9\r
+CYDEV_UCFG_B0_P7_U1_CFG9 EQU 0x40010ec9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG10\r
+CYDEV_UCFG_B0_P7_U1_CFG10 EQU 0x40010eca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG11\r
+CYDEV_UCFG_B0_P7_U1_CFG11 EQU 0x40010ecb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG12\r
+CYDEV_UCFG_B0_P7_U1_CFG12 EQU 0x40010ecc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG13\r
+CYDEV_UCFG_B0_P7_U1_CFG13 EQU 0x40010ecd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG14\r
+CYDEV_UCFG_B0_P7_U1_CFG14 EQU 0x40010ece\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG15\r
+CYDEV_UCFG_B0_P7_U1_CFG15 EQU 0x40010ecf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG16\r
+CYDEV_UCFG_B0_P7_U1_CFG16 EQU 0x40010ed0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG17\r
+CYDEV_UCFG_B0_P7_U1_CFG17 EQU 0x40010ed1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG18\r
+CYDEV_UCFG_B0_P7_U1_CFG18 EQU 0x40010ed2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG19\r
+CYDEV_UCFG_B0_P7_U1_CFG19 EQU 0x40010ed3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG20\r
+CYDEV_UCFG_B0_P7_U1_CFG20 EQU 0x40010ed4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG21\r
+CYDEV_UCFG_B0_P7_U1_CFG21 EQU 0x40010ed5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG22\r
+CYDEV_UCFG_B0_P7_U1_CFG22 EQU 0x40010ed6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG23\r
+CYDEV_UCFG_B0_P7_U1_CFG23 EQU 0x40010ed7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG24\r
+CYDEV_UCFG_B0_P7_U1_CFG24 EQU 0x40010ed8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG25\r
+CYDEV_UCFG_B0_P7_U1_CFG25 EQU 0x40010ed9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG26\r
+CYDEV_UCFG_B0_P7_U1_CFG26 EQU 0x40010eda\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG27\r
+CYDEV_UCFG_B0_P7_U1_CFG27 EQU 0x40010edb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG28\r
+CYDEV_UCFG_B0_P7_U1_CFG28 EQU 0x40010edc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG29\r
+CYDEV_UCFG_B0_P7_U1_CFG29 EQU 0x40010edd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG30\r
+CYDEV_UCFG_B0_P7_U1_CFG30 EQU 0x40010ede\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG31\r
+CYDEV_UCFG_B0_P7_U1_CFG31 EQU 0x40010edf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG0\r
+CYDEV_UCFG_B0_P7_U1_DCFG0 EQU 0x40010ee0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG1\r
+CYDEV_UCFG_B0_P7_U1_DCFG1 EQU 0x40010ee2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG2\r
+CYDEV_UCFG_B0_P7_U1_DCFG2 EQU 0x40010ee4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG3\r
+CYDEV_UCFG_B0_P7_U1_DCFG3 EQU 0x40010ee6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG4\r
+CYDEV_UCFG_B0_P7_U1_DCFG4 EQU 0x40010ee8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG5\r
+CYDEV_UCFG_B0_P7_U1_DCFG5 EQU 0x40010eea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG6\r
+CYDEV_UCFG_B0_P7_U1_DCFG6 EQU 0x40010eec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG7\r
+CYDEV_UCFG_B0_P7_U1_DCFG7 EQU 0x40010eee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_BASE\r
+CYDEV_UCFG_B0_P7_ROUTE_BASE EQU 0x40010f00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_SIZE\r
+CYDEV_UCFG_B0_P7_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_BASE\r
+CYDEV_UCFG_B1_BASE EQU 0x40011000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_SIZE\r
+CYDEV_UCFG_B1_SIZE EQU 0x00000fef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_BASE\r
+CYDEV_UCFG_B1_P2_BASE EQU 0x40011400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_SIZE\r
+CYDEV_UCFG_B1_P2_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_BASE\r
+CYDEV_UCFG_B1_P2_U0_BASE EQU 0x40011400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_SIZE\r
+CYDEV_UCFG_B1_P2_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT0\r
+CYDEV_UCFG_B1_P2_U0_PLD_IT0 EQU 0x40011400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT1\r
+CYDEV_UCFG_B1_P2_U0_PLD_IT1 EQU 0x40011404\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT2\r
+CYDEV_UCFG_B1_P2_U0_PLD_IT2 EQU 0x40011408\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT3\r
+CYDEV_UCFG_B1_P2_U0_PLD_IT3 EQU 0x4001140c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT4\r
+CYDEV_UCFG_B1_P2_U0_PLD_IT4 EQU 0x40011410\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT5\r
+CYDEV_UCFG_B1_P2_U0_PLD_IT5 EQU 0x40011414\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT6\r
+CYDEV_UCFG_B1_P2_U0_PLD_IT6 EQU 0x40011418\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT7\r
+CYDEV_UCFG_B1_P2_U0_PLD_IT7 EQU 0x4001141c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT8\r
+CYDEV_UCFG_B1_P2_U0_PLD_IT8 EQU 0x40011420\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT9\r
+CYDEV_UCFG_B1_P2_U0_PLD_IT9 EQU 0x40011424\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT10\r
+CYDEV_UCFG_B1_P2_U0_PLD_IT10 EQU 0x40011428\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT11\r
+CYDEV_UCFG_B1_P2_U0_PLD_IT11 EQU 0x4001142c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT0\r
+CYDEV_UCFG_B1_P2_U0_PLD_ORT0 EQU 0x40011430\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT1\r
+CYDEV_UCFG_B1_P2_U0_PLD_ORT1 EQU 0x40011432\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT2\r
+CYDEV_UCFG_B1_P2_U0_PLD_ORT2 EQU 0x40011434\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT3\r
+CYDEV_UCFG_B1_P2_U0_PLD_ORT3 EQU 0x40011436\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST EQU 0x40011438\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB\r
+CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB EQU 0x4001143a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET EQU 0x4001143c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS\r
+CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS EQU 0x4001143e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG0\r
+CYDEV_UCFG_B1_P2_U0_CFG0 EQU 0x40011440\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG1\r
+CYDEV_UCFG_B1_P2_U0_CFG1 EQU 0x40011441\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG2\r
+CYDEV_UCFG_B1_P2_U0_CFG2 EQU 0x40011442\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG3\r
+CYDEV_UCFG_B1_P2_U0_CFG3 EQU 0x40011443\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG4\r
+CYDEV_UCFG_B1_P2_U0_CFG4 EQU 0x40011444\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG5\r
+CYDEV_UCFG_B1_P2_U0_CFG5 EQU 0x40011445\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG6\r
+CYDEV_UCFG_B1_P2_U0_CFG6 EQU 0x40011446\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG7\r
+CYDEV_UCFG_B1_P2_U0_CFG7 EQU 0x40011447\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG8\r
+CYDEV_UCFG_B1_P2_U0_CFG8 EQU 0x40011448\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG9\r
+CYDEV_UCFG_B1_P2_U0_CFG9 EQU 0x40011449\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG10\r
+CYDEV_UCFG_B1_P2_U0_CFG10 EQU 0x4001144a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG11\r
+CYDEV_UCFG_B1_P2_U0_CFG11 EQU 0x4001144b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG12\r
+CYDEV_UCFG_B1_P2_U0_CFG12 EQU 0x4001144c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG13\r
+CYDEV_UCFG_B1_P2_U0_CFG13 EQU 0x4001144d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG14\r
+CYDEV_UCFG_B1_P2_U0_CFG14 EQU 0x4001144e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG15\r
+CYDEV_UCFG_B1_P2_U0_CFG15 EQU 0x4001144f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG16\r
+CYDEV_UCFG_B1_P2_U0_CFG16 EQU 0x40011450\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG17\r
+CYDEV_UCFG_B1_P2_U0_CFG17 EQU 0x40011451\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG18\r
+CYDEV_UCFG_B1_P2_U0_CFG18 EQU 0x40011452\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG19\r
+CYDEV_UCFG_B1_P2_U0_CFG19 EQU 0x40011453\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG20\r
+CYDEV_UCFG_B1_P2_U0_CFG20 EQU 0x40011454\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG21\r
+CYDEV_UCFG_B1_P2_U0_CFG21 EQU 0x40011455\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG22\r
+CYDEV_UCFG_B1_P2_U0_CFG22 EQU 0x40011456\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG23\r
+CYDEV_UCFG_B1_P2_U0_CFG23 EQU 0x40011457\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG24\r
+CYDEV_UCFG_B1_P2_U0_CFG24 EQU 0x40011458\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG25\r
+CYDEV_UCFG_B1_P2_U0_CFG25 EQU 0x40011459\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG26\r
+CYDEV_UCFG_B1_P2_U0_CFG26 EQU 0x4001145a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG27\r
+CYDEV_UCFG_B1_P2_U0_CFG27 EQU 0x4001145b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG28\r
+CYDEV_UCFG_B1_P2_U0_CFG28 EQU 0x4001145c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG29\r
+CYDEV_UCFG_B1_P2_U0_CFG29 EQU 0x4001145d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG30\r
+CYDEV_UCFG_B1_P2_U0_CFG30 EQU 0x4001145e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG31\r
+CYDEV_UCFG_B1_P2_U0_CFG31 EQU 0x4001145f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG0\r
+CYDEV_UCFG_B1_P2_U0_DCFG0 EQU 0x40011460\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG1\r
+CYDEV_UCFG_B1_P2_U0_DCFG1 EQU 0x40011462\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG2\r
+CYDEV_UCFG_B1_P2_U0_DCFG2 EQU 0x40011464\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG3\r
+CYDEV_UCFG_B1_P2_U0_DCFG3 EQU 0x40011466\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG4\r
+CYDEV_UCFG_B1_P2_U0_DCFG4 EQU 0x40011468\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG5\r
+CYDEV_UCFG_B1_P2_U0_DCFG5 EQU 0x4001146a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG6\r
+CYDEV_UCFG_B1_P2_U0_DCFG6 EQU 0x4001146c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG7\r
+CYDEV_UCFG_B1_P2_U0_DCFG7 EQU 0x4001146e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_BASE\r
+CYDEV_UCFG_B1_P2_U1_BASE EQU 0x40011480\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_SIZE\r
+CYDEV_UCFG_B1_P2_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT0\r
+CYDEV_UCFG_B1_P2_U1_PLD_IT0 EQU 0x40011480\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT1\r
+CYDEV_UCFG_B1_P2_U1_PLD_IT1 EQU 0x40011484\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT2\r
+CYDEV_UCFG_B1_P2_U1_PLD_IT2 EQU 0x40011488\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT3\r
+CYDEV_UCFG_B1_P2_U1_PLD_IT3 EQU 0x4001148c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT4\r
+CYDEV_UCFG_B1_P2_U1_PLD_IT4 EQU 0x40011490\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT5\r
+CYDEV_UCFG_B1_P2_U1_PLD_IT5 EQU 0x40011494\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT6\r
+CYDEV_UCFG_B1_P2_U1_PLD_IT6 EQU 0x40011498\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT7\r
+CYDEV_UCFG_B1_P2_U1_PLD_IT7 EQU 0x4001149c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT8\r
+CYDEV_UCFG_B1_P2_U1_PLD_IT8 EQU 0x400114a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT9\r
+CYDEV_UCFG_B1_P2_U1_PLD_IT9 EQU 0x400114a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT10\r
+CYDEV_UCFG_B1_P2_U1_PLD_IT10 EQU 0x400114a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT11\r
+CYDEV_UCFG_B1_P2_U1_PLD_IT11 EQU 0x400114ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT0\r
+CYDEV_UCFG_B1_P2_U1_PLD_ORT0 EQU 0x400114b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT1\r
+CYDEV_UCFG_B1_P2_U1_PLD_ORT1 EQU 0x400114b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT2\r
+CYDEV_UCFG_B1_P2_U1_PLD_ORT2 EQU 0x400114b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT3\r
+CYDEV_UCFG_B1_P2_U1_PLD_ORT3 EQU 0x400114b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST EQU 0x400114b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB\r
+CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB EQU 0x400114ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET EQU 0x400114bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS\r
+CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS EQU 0x400114be\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG0\r
+CYDEV_UCFG_B1_P2_U1_CFG0 EQU 0x400114c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG1\r
+CYDEV_UCFG_B1_P2_U1_CFG1 EQU 0x400114c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG2\r
+CYDEV_UCFG_B1_P2_U1_CFG2 EQU 0x400114c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG3\r
+CYDEV_UCFG_B1_P2_U1_CFG3 EQU 0x400114c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG4\r
+CYDEV_UCFG_B1_P2_U1_CFG4 EQU 0x400114c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG5\r
+CYDEV_UCFG_B1_P2_U1_CFG5 EQU 0x400114c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG6\r
+CYDEV_UCFG_B1_P2_U1_CFG6 EQU 0x400114c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG7\r
+CYDEV_UCFG_B1_P2_U1_CFG7 EQU 0x400114c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG8\r
+CYDEV_UCFG_B1_P2_U1_CFG8 EQU 0x400114c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG9\r
+CYDEV_UCFG_B1_P2_U1_CFG9 EQU 0x400114c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG10\r
+CYDEV_UCFG_B1_P2_U1_CFG10 EQU 0x400114ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG11\r
+CYDEV_UCFG_B1_P2_U1_CFG11 EQU 0x400114cb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG12\r
+CYDEV_UCFG_B1_P2_U1_CFG12 EQU 0x400114cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG13\r
+CYDEV_UCFG_B1_P2_U1_CFG13 EQU 0x400114cd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG14\r
+CYDEV_UCFG_B1_P2_U1_CFG14 EQU 0x400114ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG15\r
+CYDEV_UCFG_B1_P2_U1_CFG15 EQU 0x400114cf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG16\r
+CYDEV_UCFG_B1_P2_U1_CFG16 EQU 0x400114d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG17\r
+CYDEV_UCFG_B1_P2_U1_CFG17 EQU 0x400114d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG18\r
+CYDEV_UCFG_B1_P2_U1_CFG18 EQU 0x400114d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG19\r
+CYDEV_UCFG_B1_P2_U1_CFG19 EQU 0x400114d3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG20\r
+CYDEV_UCFG_B1_P2_U1_CFG20 EQU 0x400114d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG21\r
+CYDEV_UCFG_B1_P2_U1_CFG21 EQU 0x400114d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG22\r
+CYDEV_UCFG_B1_P2_U1_CFG22 EQU 0x400114d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG23\r
+CYDEV_UCFG_B1_P2_U1_CFG23 EQU 0x400114d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG24\r
+CYDEV_UCFG_B1_P2_U1_CFG24 EQU 0x400114d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG25\r
+CYDEV_UCFG_B1_P2_U1_CFG25 EQU 0x400114d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG26\r
+CYDEV_UCFG_B1_P2_U1_CFG26 EQU 0x400114da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG27\r
+CYDEV_UCFG_B1_P2_U1_CFG27 EQU 0x400114db\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG28\r
+CYDEV_UCFG_B1_P2_U1_CFG28 EQU 0x400114dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG29\r
+CYDEV_UCFG_B1_P2_U1_CFG29 EQU 0x400114dd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG30\r
+CYDEV_UCFG_B1_P2_U1_CFG30 EQU 0x400114de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG31\r
+CYDEV_UCFG_B1_P2_U1_CFG31 EQU 0x400114df\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG0\r
+CYDEV_UCFG_B1_P2_U1_DCFG0 EQU 0x400114e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG1\r
+CYDEV_UCFG_B1_P2_U1_DCFG1 EQU 0x400114e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG2\r
+CYDEV_UCFG_B1_P2_U1_DCFG2 EQU 0x400114e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG3\r
+CYDEV_UCFG_B1_P2_U1_DCFG3 EQU 0x400114e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG4\r
+CYDEV_UCFG_B1_P2_U1_DCFG4 EQU 0x400114e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG5\r
+CYDEV_UCFG_B1_P2_U1_DCFG5 EQU 0x400114ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG6\r
+CYDEV_UCFG_B1_P2_U1_DCFG6 EQU 0x400114ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG7\r
+CYDEV_UCFG_B1_P2_U1_DCFG7 EQU 0x400114ee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_BASE\r
+CYDEV_UCFG_B1_P2_ROUTE_BASE EQU 0x40011500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_SIZE\r
+CYDEV_UCFG_B1_P2_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_BASE\r
+CYDEV_UCFG_B1_P3_BASE EQU 0x40011600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_SIZE\r
+CYDEV_UCFG_B1_P3_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_BASE\r
+CYDEV_UCFG_B1_P3_U0_BASE EQU 0x40011600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_SIZE\r
+CYDEV_UCFG_B1_P3_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT0\r
+CYDEV_UCFG_B1_P3_U0_PLD_IT0 EQU 0x40011600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT1\r
+CYDEV_UCFG_B1_P3_U0_PLD_IT1 EQU 0x40011604\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT2\r
+CYDEV_UCFG_B1_P3_U0_PLD_IT2 EQU 0x40011608\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT3\r
+CYDEV_UCFG_B1_P3_U0_PLD_IT3 EQU 0x4001160c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT4\r
+CYDEV_UCFG_B1_P3_U0_PLD_IT4 EQU 0x40011610\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT5\r
+CYDEV_UCFG_B1_P3_U0_PLD_IT5 EQU 0x40011614\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT6\r
+CYDEV_UCFG_B1_P3_U0_PLD_IT6 EQU 0x40011618\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT7\r
+CYDEV_UCFG_B1_P3_U0_PLD_IT7 EQU 0x4001161c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT8\r
+CYDEV_UCFG_B1_P3_U0_PLD_IT8 EQU 0x40011620\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT9\r
+CYDEV_UCFG_B1_P3_U0_PLD_IT9 EQU 0x40011624\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT10\r
+CYDEV_UCFG_B1_P3_U0_PLD_IT10 EQU 0x40011628\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT11\r
+CYDEV_UCFG_B1_P3_U0_PLD_IT11 EQU 0x4001162c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT0\r
+CYDEV_UCFG_B1_P3_U0_PLD_ORT0 EQU 0x40011630\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT1\r
+CYDEV_UCFG_B1_P3_U0_PLD_ORT1 EQU 0x40011632\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT2\r
+CYDEV_UCFG_B1_P3_U0_PLD_ORT2 EQU 0x40011634\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT3\r
+CYDEV_UCFG_B1_P3_U0_PLD_ORT3 EQU 0x40011636\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST EQU 0x40011638\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB\r
+CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB EQU 0x4001163a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET EQU 0x4001163c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS\r
+CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS EQU 0x4001163e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG0\r
+CYDEV_UCFG_B1_P3_U0_CFG0 EQU 0x40011640\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG1\r
+CYDEV_UCFG_B1_P3_U0_CFG1 EQU 0x40011641\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG2\r
+CYDEV_UCFG_B1_P3_U0_CFG2 EQU 0x40011642\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG3\r
+CYDEV_UCFG_B1_P3_U0_CFG3 EQU 0x40011643\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG4\r
+CYDEV_UCFG_B1_P3_U0_CFG4 EQU 0x40011644\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG5\r
+CYDEV_UCFG_B1_P3_U0_CFG5 EQU 0x40011645\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG6\r
+CYDEV_UCFG_B1_P3_U0_CFG6 EQU 0x40011646\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG7\r
+CYDEV_UCFG_B1_P3_U0_CFG7 EQU 0x40011647\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG8\r
+CYDEV_UCFG_B1_P3_U0_CFG8 EQU 0x40011648\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG9\r
+CYDEV_UCFG_B1_P3_U0_CFG9 EQU 0x40011649\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG10\r
+CYDEV_UCFG_B1_P3_U0_CFG10 EQU 0x4001164a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG11\r
+CYDEV_UCFG_B1_P3_U0_CFG11 EQU 0x4001164b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG12\r
+CYDEV_UCFG_B1_P3_U0_CFG12 EQU 0x4001164c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG13\r
+CYDEV_UCFG_B1_P3_U0_CFG13 EQU 0x4001164d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG14\r
+CYDEV_UCFG_B1_P3_U0_CFG14 EQU 0x4001164e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG15\r
+CYDEV_UCFG_B1_P3_U0_CFG15 EQU 0x4001164f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG16\r
+CYDEV_UCFG_B1_P3_U0_CFG16 EQU 0x40011650\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG17\r
+CYDEV_UCFG_B1_P3_U0_CFG17 EQU 0x40011651\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG18\r
+CYDEV_UCFG_B1_P3_U0_CFG18 EQU 0x40011652\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG19\r
+CYDEV_UCFG_B1_P3_U0_CFG19 EQU 0x40011653\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG20\r
+CYDEV_UCFG_B1_P3_U0_CFG20 EQU 0x40011654\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG21\r
+CYDEV_UCFG_B1_P3_U0_CFG21 EQU 0x40011655\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG22\r
+CYDEV_UCFG_B1_P3_U0_CFG22 EQU 0x40011656\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG23\r
+CYDEV_UCFG_B1_P3_U0_CFG23 EQU 0x40011657\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG24\r
+CYDEV_UCFG_B1_P3_U0_CFG24 EQU 0x40011658\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG25\r
+CYDEV_UCFG_B1_P3_U0_CFG25 EQU 0x40011659\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG26\r
+CYDEV_UCFG_B1_P3_U0_CFG26 EQU 0x4001165a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG27\r
+CYDEV_UCFG_B1_P3_U0_CFG27 EQU 0x4001165b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG28\r
+CYDEV_UCFG_B1_P3_U0_CFG28 EQU 0x4001165c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG29\r
+CYDEV_UCFG_B1_P3_U0_CFG29 EQU 0x4001165d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG30\r
+CYDEV_UCFG_B1_P3_U0_CFG30 EQU 0x4001165e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG31\r
+CYDEV_UCFG_B1_P3_U0_CFG31 EQU 0x4001165f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG0\r
+CYDEV_UCFG_B1_P3_U0_DCFG0 EQU 0x40011660\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG1\r
+CYDEV_UCFG_B1_P3_U0_DCFG1 EQU 0x40011662\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG2\r
+CYDEV_UCFG_B1_P3_U0_DCFG2 EQU 0x40011664\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG3\r
+CYDEV_UCFG_B1_P3_U0_DCFG3 EQU 0x40011666\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG4\r
+CYDEV_UCFG_B1_P3_U0_DCFG4 EQU 0x40011668\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG5\r
+CYDEV_UCFG_B1_P3_U0_DCFG5 EQU 0x4001166a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG6\r
+CYDEV_UCFG_B1_P3_U0_DCFG6 EQU 0x4001166c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG7\r
+CYDEV_UCFG_B1_P3_U0_DCFG7 EQU 0x4001166e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_BASE\r
+CYDEV_UCFG_B1_P3_U1_BASE EQU 0x40011680\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_SIZE\r
+CYDEV_UCFG_B1_P3_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT0\r
+CYDEV_UCFG_B1_P3_U1_PLD_IT0 EQU 0x40011680\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT1\r
+CYDEV_UCFG_B1_P3_U1_PLD_IT1 EQU 0x40011684\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT2\r
+CYDEV_UCFG_B1_P3_U1_PLD_IT2 EQU 0x40011688\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT3\r
+CYDEV_UCFG_B1_P3_U1_PLD_IT3 EQU 0x4001168c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT4\r
+CYDEV_UCFG_B1_P3_U1_PLD_IT4 EQU 0x40011690\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT5\r
+CYDEV_UCFG_B1_P3_U1_PLD_IT5 EQU 0x40011694\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT6\r
+CYDEV_UCFG_B1_P3_U1_PLD_IT6 EQU 0x40011698\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT7\r
+CYDEV_UCFG_B1_P3_U1_PLD_IT7 EQU 0x4001169c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT8\r
+CYDEV_UCFG_B1_P3_U1_PLD_IT8 EQU 0x400116a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT9\r
+CYDEV_UCFG_B1_P3_U1_PLD_IT9 EQU 0x400116a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT10\r
+CYDEV_UCFG_B1_P3_U1_PLD_IT10 EQU 0x400116a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT11\r
+CYDEV_UCFG_B1_P3_U1_PLD_IT11 EQU 0x400116ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT0\r
+CYDEV_UCFG_B1_P3_U1_PLD_ORT0 EQU 0x400116b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT1\r
+CYDEV_UCFG_B1_P3_U1_PLD_ORT1 EQU 0x400116b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT2\r
+CYDEV_UCFG_B1_P3_U1_PLD_ORT2 EQU 0x400116b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT3\r
+CYDEV_UCFG_B1_P3_U1_PLD_ORT3 EQU 0x400116b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST EQU 0x400116b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB\r
+CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB EQU 0x400116ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET EQU 0x400116bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS\r
+CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS EQU 0x400116be\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG0\r
+CYDEV_UCFG_B1_P3_U1_CFG0 EQU 0x400116c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG1\r
+CYDEV_UCFG_B1_P3_U1_CFG1 EQU 0x400116c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG2\r
+CYDEV_UCFG_B1_P3_U1_CFG2 EQU 0x400116c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG3\r
+CYDEV_UCFG_B1_P3_U1_CFG3 EQU 0x400116c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG4\r
+CYDEV_UCFG_B1_P3_U1_CFG4 EQU 0x400116c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG5\r
+CYDEV_UCFG_B1_P3_U1_CFG5 EQU 0x400116c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG6\r
+CYDEV_UCFG_B1_P3_U1_CFG6 EQU 0x400116c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG7\r
+CYDEV_UCFG_B1_P3_U1_CFG7 EQU 0x400116c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG8\r
+CYDEV_UCFG_B1_P3_U1_CFG8 EQU 0x400116c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG9\r
+CYDEV_UCFG_B1_P3_U1_CFG9 EQU 0x400116c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG10\r
+CYDEV_UCFG_B1_P3_U1_CFG10 EQU 0x400116ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG11\r
+CYDEV_UCFG_B1_P3_U1_CFG11 EQU 0x400116cb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG12\r
+CYDEV_UCFG_B1_P3_U1_CFG12 EQU 0x400116cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG13\r
+CYDEV_UCFG_B1_P3_U1_CFG13 EQU 0x400116cd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG14\r
+CYDEV_UCFG_B1_P3_U1_CFG14 EQU 0x400116ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG15\r
+CYDEV_UCFG_B1_P3_U1_CFG15 EQU 0x400116cf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG16\r
+CYDEV_UCFG_B1_P3_U1_CFG16 EQU 0x400116d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG17\r
+CYDEV_UCFG_B1_P3_U1_CFG17 EQU 0x400116d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG18\r
+CYDEV_UCFG_B1_P3_U1_CFG18 EQU 0x400116d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG19\r
+CYDEV_UCFG_B1_P3_U1_CFG19 EQU 0x400116d3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG20\r
+CYDEV_UCFG_B1_P3_U1_CFG20 EQU 0x400116d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG21\r
+CYDEV_UCFG_B1_P3_U1_CFG21 EQU 0x400116d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG22\r
+CYDEV_UCFG_B1_P3_U1_CFG22 EQU 0x400116d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG23\r
+CYDEV_UCFG_B1_P3_U1_CFG23 EQU 0x400116d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG24\r
+CYDEV_UCFG_B1_P3_U1_CFG24 EQU 0x400116d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG25\r
+CYDEV_UCFG_B1_P3_U1_CFG25 EQU 0x400116d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG26\r
+CYDEV_UCFG_B1_P3_U1_CFG26 EQU 0x400116da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG27\r
+CYDEV_UCFG_B1_P3_U1_CFG27 EQU 0x400116db\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG28\r
+CYDEV_UCFG_B1_P3_U1_CFG28 EQU 0x400116dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG29\r
+CYDEV_UCFG_B1_P3_U1_CFG29 EQU 0x400116dd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG30\r
+CYDEV_UCFG_B1_P3_U1_CFG30 EQU 0x400116de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG31\r
+CYDEV_UCFG_B1_P3_U1_CFG31 EQU 0x400116df\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG0\r
+CYDEV_UCFG_B1_P3_U1_DCFG0 EQU 0x400116e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG1\r
+CYDEV_UCFG_B1_P3_U1_DCFG1 EQU 0x400116e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG2\r
+CYDEV_UCFG_B1_P3_U1_DCFG2 EQU 0x400116e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG3\r
+CYDEV_UCFG_B1_P3_U1_DCFG3 EQU 0x400116e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG4\r
+CYDEV_UCFG_B1_P3_U1_DCFG4 EQU 0x400116e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG5\r
+CYDEV_UCFG_B1_P3_U1_DCFG5 EQU 0x400116ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG6\r
+CYDEV_UCFG_B1_P3_U1_DCFG6 EQU 0x400116ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG7\r
+CYDEV_UCFG_B1_P3_U1_DCFG7 EQU 0x400116ee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_BASE\r
+CYDEV_UCFG_B1_P3_ROUTE_BASE EQU 0x40011700\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_SIZE\r
+CYDEV_UCFG_B1_P3_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_BASE\r
+CYDEV_UCFG_B1_P4_BASE EQU 0x40011800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_SIZE\r
+CYDEV_UCFG_B1_P4_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_BASE\r
+CYDEV_UCFG_B1_P4_U0_BASE EQU 0x40011800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_SIZE\r
+CYDEV_UCFG_B1_P4_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT0\r
+CYDEV_UCFG_B1_P4_U0_PLD_IT0 EQU 0x40011800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT1\r
+CYDEV_UCFG_B1_P4_U0_PLD_IT1 EQU 0x40011804\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT2\r
+CYDEV_UCFG_B1_P4_U0_PLD_IT2 EQU 0x40011808\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT3\r
+CYDEV_UCFG_B1_P4_U0_PLD_IT3 EQU 0x4001180c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT4\r
+CYDEV_UCFG_B1_P4_U0_PLD_IT4 EQU 0x40011810\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT5\r
+CYDEV_UCFG_B1_P4_U0_PLD_IT5 EQU 0x40011814\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT6\r
+CYDEV_UCFG_B1_P4_U0_PLD_IT6 EQU 0x40011818\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT7\r
+CYDEV_UCFG_B1_P4_U0_PLD_IT7 EQU 0x4001181c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT8\r
+CYDEV_UCFG_B1_P4_U0_PLD_IT8 EQU 0x40011820\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT9\r
+CYDEV_UCFG_B1_P4_U0_PLD_IT9 EQU 0x40011824\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT10\r
+CYDEV_UCFG_B1_P4_U0_PLD_IT10 EQU 0x40011828\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT11\r
+CYDEV_UCFG_B1_P4_U0_PLD_IT11 EQU 0x4001182c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT0\r
+CYDEV_UCFG_B1_P4_U0_PLD_ORT0 EQU 0x40011830\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT1\r
+CYDEV_UCFG_B1_P4_U0_PLD_ORT1 EQU 0x40011832\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT2\r
+CYDEV_UCFG_B1_P4_U0_PLD_ORT2 EQU 0x40011834\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT3\r
+CYDEV_UCFG_B1_P4_U0_PLD_ORT3 EQU 0x40011836\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST EQU 0x40011838\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB\r
+CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB EQU 0x4001183a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET EQU 0x4001183c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS\r
+CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS EQU 0x4001183e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG0\r
+CYDEV_UCFG_B1_P4_U0_CFG0 EQU 0x40011840\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG1\r
+CYDEV_UCFG_B1_P4_U0_CFG1 EQU 0x40011841\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG2\r
+CYDEV_UCFG_B1_P4_U0_CFG2 EQU 0x40011842\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG3\r
+CYDEV_UCFG_B1_P4_U0_CFG3 EQU 0x40011843\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG4\r
+CYDEV_UCFG_B1_P4_U0_CFG4 EQU 0x40011844\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG5\r
+CYDEV_UCFG_B1_P4_U0_CFG5 EQU 0x40011845\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG6\r
+CYDEV_UCFG_B1_P4_U0_CFG6 EQU 0x40011846\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG7\r
+CYDEV_UCFG_B1_P4_U0_CFG7 EQU 0x40011847\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG8\r
+CYDEV_UCFG_B1_P4_U0_CFG8 EQU 0x40011848\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG9\r
+CYDEV_UCFG_B1_P4_U0_CFG9 EQU 0x40011849\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG10\r
+CYDEV_UCFG_B1_P4_U0_CFG10 EQU 0x4001184a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG11\r
+CYDEV_UCFG_B1_P4_U0_CFG11 EQU 0x4001184b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG12\r
+CYDEV_UCFG_B1_P4_U0_CFG12 EQU 0x4001184c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG13\r
+CYDEV_UCFG_B1_P4_U0_CFG13 EQU 0x4001184d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG14\r
+CYDEV_UCFG_B1_P4_U0_CFG14 EQU 0x4001184e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG15\r
+CYDEV_UCFG_B1_P4_U0_CFG15 EQU 0x4001184f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG16\r
+CYDEV_UCFG_B1_P4_U0_CFG16 EQU 0x40011850\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG17\r
+CYDEV_UCFG_B1_P4_U0_CFG17 EQU 0x40011851\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG18\r
+CYDEV_UCFG_B1_P4_U0_CFG18 EQU 0x40011852\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG19\r
+CYDEV_UCFG_B1_P4_U0_CFG19 EQU 0x40011853\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG20\r
+CYDEV_UCFG_B1_P4_U0_CFG20 EQU 0x40011854\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG21\r
+CYDEV_UCFG_B1_P4_U0_CFG21 EQU 0x40011855\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG22\r
+CYDEV_UCFG_B1_P4_U0_CFG22 EQU 0x40011856\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG23\r
+CYDEV_UCFG_B1_P4_U0_CFG23 EQU 0x40011857\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG24\r
+CYDEV_UCFG_B1_P4_U0_CFG24 EQU 0x40011858\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG25\r
+CYDEV_UCFG_B1_P4_U0_CFG25 EQU 0x40011859\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG26\r
+CYDEV_UCFG_B1_P4_U0_CFG26 EQU 0x4001185a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG27\r
+CYDEV_UCFG_B1_P4_U0_CFG27 EQU 0x4001185b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG28\r
+CYDEV_UCFG_B1_P4_U0_CFG28 EQU 0x4001185c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG29\r
+CYDEV_UCFG_B1_P4_U0_CFG29 EQU 0x4001185d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG30\r
+CYDEV_UCFG_B1_P4_U0_CFG30 EQU 0x4001185e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG31\r
+CYDEV_UCFG_B1_P4_U0_CFG31 EQU 0x4001185f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG0\r
+CYDEV_UCFG_B1_P4_U0_DCFG0 EQU 0x40011860\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG1\r
+CYDEV_UCFG_B1_P4_U0_DCFG1 EQU 0x40011862\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG2\r
+CYDEV_UCFG_B1_P4_U0_DCFG2 EQU 0x40011864\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG3\r
+CYDEV_UCFG_B1_P4_U0_DCFG3 EQU 0x40011866\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG4\r
+CYDEV_UCFG_B1_P4_U0_DCFG4 EQU 0x40011868\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG5\r
+CYDEV_UCFG_B1_P4_U0_DCFG5 EQU 0x4001186a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG6\r
+CYDEV_UCFG_B1_P4_U0_DCFG6 EQU 0x4001186c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG7\r
+CYDEV_UCFG_B1_P4_U0_DCFG7 EQU 0x4001186e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_BASE\r
+CYDEV_UCFG_B1_P4_U1_BASE EQU 0x40011880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_SIZE\r
+CYDEV_UCFG_B1_P4_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT0\r
+CYDEV_UCFG_B1_P4_U1_PLD_IT0 EQU 0x40011880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT1\r
+CYDEV_UCFG_B1_P4_U1_PLD_IT1 EQU 0x40011884\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT2\r
+CYDEV_UCFG_B1_P4_U1_PLD_IT2 EQU 0x40011888\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT3\r
+CYDEV_UCFG_B1_P4_U1_PLD_IT3 EQU 0x4001188c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT4\r
+CYDEV_UCFG_B1_P4_U1_PLD_IT4 EQU 0x40011890\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT5\r
+CYDEV_UCFG_B1_P4_U1_PLD_IT5 EQU 0x40011894\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT6\r
+CYDEV_UCFG_B1_P4_U1_PLD_IT6 EQU 0x40011898\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT7\r
+CYDEV_UCFG_B1_P4_U1_PLD_IT7 EQU 0x4001189c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT8\r
+CYDEV_UCFG_B1_P4_U1_PLD_IT8 EQU 0x400118a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT9\r
+CYDEV_UCFG_B1_P4_U1_PLD_IT9 EQU 0x400118a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT10\r
+CYDEV_UCFG_B1_P4_U1_PLD_IT10 EQU 0x400118a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT11\r
+CYDEV_UCFG_B1_P4_U1_PLD_IT11 EQU 0x400118ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT0\r
+CYDEV_UCFG_B1_P4_U1_PLD_ORT0 EQU 0x400118b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT1\r
+CYDEV_UCFG_B1_P4_U1_PLD_ORT1 EQU 0x400118b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT2\r
+CYDEV_UCFG_B1_P4_U1_PLD_ORT2 EQU 0x400118b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT3\r
+CYDEV_UCFG_B1_P4_U1_PLD_ORT3 EQU 0x400118b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST EQU 0x400118b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB\r
+CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB EQU 0x400118ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET EQU 0x400118bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS\r
+CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS EQU 0x400118be\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG0\r
+CYDEV_UCFG_B1_P4_U1_CFG0 EQU 0x400118c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG1\r
+CYDEV_UCFG_B1_P4_U1_CFG1 EQU 0x400118c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG2\r
+CYDEV_UCFG_B1_P4_U1_CFG2 EQU 0x400118c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG3\r
+CYDEV_UCFG_B1_P4_U1_CFG3 EQU 0x400118c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG4\r
+CYDEV_UCFG_B1_P4_U1_CFG4 EQU 0x400118c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG5\r
+CYDEV_UCFG_B1_P4_U1_CFG5 EQU 0x400118c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG6\r
+CYDEV_UCFG_B1_P4_U1_CFG6 EQU 0x400118c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG7\r
+CYDEV_UCFG_B1_P4_U1_CFG7 EQU 0x400118c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG8\r
+CYDEV_UCFG_B1_P4_U1_CFG8 EQU 0x400118c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG9\r
+CYDEV_UCFG_B1_P4_U1_CFG9 EQU 0x400118c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG10\r
+CYDEV_UCFG_B1_P4_U1_CFG10 EQU 0x400118ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG11\r
+CYDEV_UCFG_B1_P4_U1_CFG11 EQU 0x400118cb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG12\r
+CYDEV_UCFG_B1_P4_U1_CFG12 EQU 0x400118cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG13\r
+CYDEV_UCFG_B1_P4_U1_CFG13 EQU 0x400118cd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG14\r
+CYDEV_UCFG_B1_P4_U1_CFG14 EQU 0x400118ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG15\r
+CYDEV_UCFG_B1_P4_U1_CFG15 EQU 0x400118cf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG16\r
+CYDEV_UCFG_B1_P4_U1_CFG16 EQU 0x400118d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG17\r
+CYDEV_UCFG_B1_P4_U1_CFG17 EQU 0x400118d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG18\r
+CYDEV_UCFG_B1_P4_U1_CFG18 EQU 0x400118d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG19\r
+CYDEV_UCFG_B1_P4_U1_CFG19 EQU 0x400118d3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG20\r
+CYDEV_UCFG_B1_P4_U1_CFG20 EQU 0x400118d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG21\r
+CYDEV_UCFG_B1_P4_U1_CFG21 EQU 0x400118d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG22\r
+CYDEV_UCFG_B1_P4_U1_CFG22 EQU 0x400118d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG23\r
+CYDEV_UCFG_B1_P4_U1_CFG23 EQU 0x400118d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG24\r
+CYDEV_UCFG_B1_P4_U1_CFG24 EQU 0x400118d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG25\r
+CYDEV_UCFG_B1_P4_U1_CFG25 EQU 0x400118d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG26\r
+CYDEV_UCFG_B1_P4_U1_CFG26 EQU 0x400118da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG27\r
+CYDEV_UCFG_B1_P4_U1_CFG27 EQU 0x400118db\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG28\r
+CYDEV_UCFG_B1_P4_U1_CFG28 EQU 0x400118dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG29\r
+CYDEV_UCFG_B1_P4_U1_CFG29 EQU 0x400118dd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG30\r
+CYDEV_UCFG_B1_P4_U1_CFG30 EQU 0x400118de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG31\r
+CYDEV_UCFG_B1_P4_U1_CFG31 EQU 0x400118df\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG0\r
+CYDEV_UCFG_B1_P4_U1_DCFG0 EQU 0x400118e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG1\r
+CYDEV_UCFG_B1_P4_U1_DCFG1 EQU 0x400118e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG2\r
+CYDEV_UCFG_B1_P4_U1_DCFG2 EQU 0x400118e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG3\r
+CYDEV_UCFG_B1_P4_U1_DCFG3 EQU 0x400118e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG4\r
+CYDEV_UCFG_B1_P4_U1_DCFG4 EQU 0x400118e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG5\r
+CYDEV_UCFG_B1_P4_U1_DCFG5 EQU 0x400118ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG6\r
+CYDEV_UCFG_B1_P4_U1_DCFG6 EQU 0x400118ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG7\r
+CYDEV_UCFG_B1_P4_U1_DCFG7 EQU 0x400118ee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_BASE\r
+CYDEV_UCFG_B1_P4_ROUTE_BASE EQU 0x40011900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_SIZE\r
+CYDEV_UCFG_B1_P4_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_BASE\r
+CYDEV_UCFG_B1_P5_BASE EQU 0x40011a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_SIZE\r
+CYDEV_UCFG_B1_P5_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_BASE\r
+CYDEV_UCFG_B1_P5_U0_BASE EQU 0x40011a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_SIZE\r
+CYDEV_UCFG_B1_P5_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT0\r
+CYDEV_UCFG_B1_P5_U0_PLD_IT0 EQU 0x40011a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT1\r
+CYDEV_UCFG_B1_P5_U0_PLD_IT1 EQU 0x40011a04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT2\r
+CYDEV_UCFG_B1_P5_U0_PLD_IT2 EQU 0x40011a08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT3\r
+CYDEV_UCFG_B1_P5_U0_PLD_IT3 EQU 0x40011a0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT4\r
+CYDEV_UCFG_B1_P5_U0_PLD_IT4 EQU 0x40011a10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT5\r
+CYDEV_UCFG_B1_P5_U0_PLD_IT5 EQU 0x40011a14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT6\r
+CYDEV_UCFG_B1_P5_U0_PLD_IT6 EQU 0x40011a18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT7\r
+CYDEV_UCFG_B1_P5_U0_PLD_IT7 EQU 0x40011a1c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT8\r
+CYDEV_UCFG_B1_P5_U0_PLD_IT8 EQU 0x40011a20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT9\r
+CYDEV_UCFG_B1_P5_U0_PLD_IT9 EQU 0x40011a24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT10\r
+CYDEV_UCFG_B1_P5_U0_PLD_IT10 EQU 0x40011a28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT11\r
+CYDEV_UCFG_B1_P5_U0_PLD_IT11 EQU 0x40011a2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT0\r
+CYDEV_UCFG_B1_P5_U0_PLD_ORT0 EQU 0x40011a30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT1\r
+CYDEV_UCFG_B1_P5_U0_PLD_ORT1 EQU 0x40011a32\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT2\r
+CYDEV_UCFG_B1_P5_U0_PLD_ORT2 EQU 0x40011a34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT3\r
+CYDEV_UCFG_B1_P5_U0_PLD_ORT3 EQU 0x40011a36\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST EQU 0x40011a38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB\r
+CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB EQU 0x40011a3a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET EQU 0x40011a3c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS\r
+CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS EQU 0x40011a3e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG0\r
+CYDEV_UCFG_B1_P5_U0_CFG0 EQU 0x40011a40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG1\r
+CYDEV_UCFG_B1_P5_U0_CFG1 EQU 0x40011a41\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG2\r
+CYDEV_UCFG_B1_P5_U0_CFG2 EQU 0x40011a42\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG3\r
+CYDEV_UCFG_B1_P5_U0_CFG3 EQU 0x40011a43\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG4\r
+CYDEV_UCFG_B1_P5_U0_CFG4 EQU 0x40011a44\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG5\r
+CYDEV_UCFG_B1_P5_U0_CFG5 EQU 0x40011a45\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG6\r
+CYDEV_UCFG_B1_P5_U0_CFG6 EQU 0x40011a46\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG7\r
+CYDEV_UCFG_B1_P5_U0_CFG7 EQU 0x40011a47\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG8\r
+CYDEV_UCFG_B1_P5_U0_CFG8 EQU 0x40011a48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG9\r
+CYDEV_UCFG_B1_P5_U0_CFG9 EQU 0x40011a49\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG10\r
+CYDEV_UCFG_B1_P5_U0_CFG10 EQU 0x40011a4a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG11\r
+CYDEV_UCFG_B1_P5_U0_CFG11 EQU 0x40011a4b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG12\r
+CYDEV_UCFG_B1_P5_U0_CFG12 EQU 0x40011a4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG13\r
+CYDEV_UCFG_B1_P5_U0_CFG13 EQU 0x40011a4d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG14\r
+CYDEV_UCFG_B1_P5_U0_CFG14 EQU 0x40011a4e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG15\r
+CYDEV_UCFG_B1_P5_U0_CFG15 EQU 0x40011a4f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG16\r
+CYDEV_UCFG_B1_P5_U0_CFG16 EQU 0x40011a50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG17\r
+CYDEV_UCFG_B1_P5_U0_CFG17 EQU 0x40011a51\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG18\r
+CYDEV_UCFG_B1_P5_U0_CFG18 EQU 0x40011a52\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG19\r
+CYDEV_UCFG_B1_P5_U0_CFG19 EQU 0x40011a53\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG20\r
+CYDEV_UCFG_B1_P5_U0_CFG20 EQU 0x40011a54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG21\r
+CYDEV_UCFG_B1_P5_U0_CFG21 EQU 0x40011a55\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG22\r
+CYDEV_UCFG_B1_P5_U0_CFG22 EQU 0x40011a56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG23\r
+CYDEV_UCFG_B1_P5_U0_CFG23 EQU 0x40011a57\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG24\r
+CYDEV_UCFG_B1_P5_U0_CFG24 EQU 0x40011a58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG25\r
+CYDEV_UCFG_B1_P5_U0_CFG25 EQU 0x40011a59\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG26\r
+CYDEV_UCFG_B1_P5_U0_CFG26 EQU 0x40011a5a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG27\r
+CYDEV_UCFG_B1_P5_U0_CFG27 EQU 0x40011a5b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG28\r
+CYDEV_UCFG_B1_P5_U0_CFG28 EQU 0x40011a5c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG29\r
+CYDEV_UCFG_B1_P5_U0_CFG29 EQU 0x40011a5d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG30\r
+CYDEV_UCFG_B1_P5_U0_CFG30 EQU 0x40011a5e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG31\r
+CYDEV_UCFG_B1_P5_U0_CFG31 EQU 0x40011a5f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG0\r
+CYDEV_UCFG_B1_P5_U0_DCFG0 EQU 0x40011a60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG1\r
+CYDEV_UCFG_B1_P5_U0_DCFG1 EQU 0x40011a62\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG2\r
+CYDEV_UCFG_B1_P5_U0_DCFG2 EQU 0x40011a64\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG3\r
+CYDEV_UCFG_B1_P5_U0_DCFG3 EQU 0x40011a66\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG4\r
+CYDEV_UCFG_B1_P5_U0_DCFG4 EQU 0x40011a68\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG5\r
+CYDEV_UCFG_B1_P5_U0_DCFG5 EQU 0x40011a6a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG6\r
+CYDEV_UCFG_B1_P5_U0_DCFG6 EQU 0x40011a6c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG7\r
+CYDEV_UCFG_B1_P5_U0_DCFG7 EQU 0x40011a6e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_BASE\r
+CYDEV_UCFG_B1_P5_U1_BASE EQU 0x40011a80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_SIZE\r
+CYDEV_UCFG_B1_P5_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT0\r
+CYDEV_UCFG_B1_P5_U1_PLD_IT0 EQU 0x40011a80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT1\r
+CYDEV_UCFG_B1_P5_U1_PLD_IT1 EQU 0x40011a84\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT2\r
+CYDEV_UCFG_B1_P5_U1_PLD_IT2 EQU 0x40011a88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT3\r
+CYDEV_UCFG_B1_P5_U1_PLD_IT3 EQU 0x40011a8c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT4\r
+CYDEV_UCFG_B1_P5_U1_PLD_IT4 EQU 0x40011a90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT5\r
+CYDEV_UCFG_B1_P5_U1_PLD_IT5 EQU 0x40011a94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT6\r
+CYDEV_UCFG_B1_P5_U1_PLD_IT6 EQU 0x40011a98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT7\r
+CYDEV_UCFG_B1_P5_U1_PLD_IT7 EQU 0x40011a9c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT8\r
+CYDEV_UCFG_B1_P5_U1_PLD_IT8 EQU 0x40011aa0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT9\r
+CYDEV_UCFG_B1_P5_U1_PLD_IT9 EQU 0x40011aa4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT10\r
+CYDEV_UCFG_B1_P5_U1_PLD_IT10 EQU 0x40011aa8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT11\r
+CYDEV_UCFG_B1_P5_U1_PLD_IT11 EQU 0x40011aac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT0\r
+CYDEV_UCFG_B1_P5_U1_PLD_ORT0 EQU 0x40011ab0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT1\r
+CYDEV_UCFG_B1_P5_U1_PLD_ORT1 EQU 0x40011ab2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT2\r
+CYDEV_UCFG_B1_P5_U1_PLD_ORT2 EQU 0x40011ab4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT3\r
+CYDEV_UCFG_B1_P5_U1_PLD_ORT3 EQU 0x40011ab6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST\r
+CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST EQU 0x40011ab8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB\r
+CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB EQU 0x40011aba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET\r
+CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET EQU 0x40011abc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS\r
+CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS EQU 0x40011abe\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG0\r
+CYDEV_UCFG_B1_P5_U1_CFG0 EQU 0x40011ac0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG1\r
+CYDEV_UCFG_B1_P5_U1_CFG1 EQU 0x40011ac1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG2\r
+CYDEV_UCFG_B1_P5_U1_CFG2 EQU 0x40011ac2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG3\r
+CYDEV_UCFG_B1_P5_U1_CFG3 EQU 0x40011ac3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG4\r
+CYDEV_UCFG_B1_P5_U1_CFG4 EQU 0x40011ac4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG5\r
+CYDEV_UCFG_B1_P5_U1_CFG5 EQU 0x40011ac5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG6\r
+CYDEV_UCFG_B1_P5_U1_CFG6 EQU 0x40011ac6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG7\r
+CYDEV_UCFG_B1_P5_U1_CFG7 EQU 0x40011ac7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG8\r
+CYDEV_UCFG_B1_P5_U1_CFG8 EQU 0x40011ac8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG9\r
+CYDEV_UCFG_B1_P5_U1_CFG9 EQU 0x40011ac9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG10\r
+CYDEV_UCFG_B1_P5_U1_CFG10 EQU 0x40011aca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG11\r
+CYDEV_UCFG_B1_P5_U1_CFG11 EQU 0x40011acb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG12\r
+CYDEV_UCFG_B1_P5_U1_CFG12 EQU 0x40011acc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG13\r
+CYDEV_UCFG_B1_P5_U1_CFG13 EQU 0x40011acd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG14\r
+CYDEV_UCFG_B1_P5_U1_CFG14 EQU 0x40011ace\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG15\r
+CYDEV_UCFG_B1_P5_U1_CFG15 EQU 0x40011acf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG16\r
+CYDEV_UCFG_B1_P5_U1_CFG16 EQU 0x40011ad0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG17\r
+CYDEV_UCFG_B1_P5_U1_CFG17 EQU 0x40011ad1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG18\r
+CYDEV_UCFG_B1_P5_U1_CFG18 EQU 0x40011ad2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG19\r
+CYDEV_UCFG_B1_P5_U1_CFG19 EQU 0x40011ad3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG20\r
+CYDEV_UCFG_B1_P5_U1_CFG20 EQU 0x40011ad4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG21\r
+CYDEV_UCFG_B1_P5_U1_CFG21 EQU 0x40011ad5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG22\r
+CYDEV_UCFG_B1_P5_U1_CFG22 EQU 0x40011ad6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG23\r
+CYDEV_UCFG_B1_P5_U1_CFG23 EQU 0x40011ad7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG24\r
+CYDEV_UCFG_B1_P5_U1_CFG24 EQU 0x40011ad8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG25\r
+CYDEV_UCFG_B1_P5_U1_CFG25 EQU 0x40011ad9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG26\r
+CYDEV_UCFG_B1_P5_U1_CFG26 EQU 0x40011ada\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG27\r
+CYDEV_UCFG_B1_P5_U1_CFG27 EQU 0x40011adb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG28\r
+CYDEV_UCFG_B1_P5_U1_CFG28 EQU 0x40011adc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG29\r
+CYDEV_UCFG_B1_P5_U1_CFG29 EQU 0x40011add\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG30\r
+CYDEV_UCFG_B1_P5_U1_CFG30 EQU 0x40011ade\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG31\r
+CYDEV_UCFG_B1_P5_U1_CFG31 EQU 0x40011adf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG0\r
+CYDEV_UCFG_B1_P5_U1_DCFG0 EQU 0x40011ae0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG1\r
+CYDEV_UCFG_B1_P5_U1_DCFG1 EQU 0x40011ae2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG2\r
+CYDEV_UCFG_B1_P5_U1_DCFG2 EQU 0x40011ae4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG3\r
+CYDEV_UCFG_B1_P5_U1_DCFG3 EQU 0x40011ae6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG4\r
+CYDEV_UCFG_B1_P5_U1_DCFG4 EQU 0x40011ae8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG5\r
+CYDEV_UCFG_B1_P5_U1_DCFG5 EQU 0x40011aea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG6\r
+CYDEV_UCFG_B1_P5_U1_DCFG6 EQU 0x40011aec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG7\r
+CYDEV_UCFG_B1_P5_U1_DCFG7 EQU 0x40011aee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_BASE\r
+CYDEV_UCFG_B1_P5_ROUTE_BASE EQU 0x40011b00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_SIZE\r
+CYDEV_UCFG_B1_P5_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI0_BASE\r
+CYDEV_UCFG_DSI0_BASE EQU 0x40014000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI0_SIZE\r
+CYDEV_UCFG_DSI0_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI1_BASE\r
+CYDEV_UCFG_DSI1_BASE EQU 0x40014100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI1_SIZE\r
+CYDEV_UCFG_DSI1_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI2_BASE\r
+CYDEV_UCFG_DSI2_BASE EQU 0x40014200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI2_SIZE\r
+CYDEV_UCFG_DSI2_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI3_BASE\r
+CYDEV_UCFG_DSI3_BASE EQU 0x40014300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI3_SIZE\r
+CYDEV_UCFG_DSI3_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI4_BASE\r
+CYDEV_UCFG_DSI4_BASE EQU 0x40014400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI4_SIZE\r
+CYDEV_UCFG_DSI4_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI5_BASE\r
+CYDEV_UCFG_DSI5_BASE EQU 0x40014500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI5_SIZE\r
+CYDEV_UCFG_DSI5_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI6_BASE\r
+CYDEV_UCFG_DSI6_BASE EQU 0x40014600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI6_SIZE\r
+CYDEV_UCFG_DSI6_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI7_BASE\r
+CYDEV_UCFG_DSI7_BASE EQU 0x40014700\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI7_SIZE\r
+CYDEV_UCFG_DSI7_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI8_BASE\r
+CYDEV_UCFG_DSI8_BASE EQU 0x40014800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI8_SIZE\r
+CYDEV_UCFG_DSI8_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI9_BASE\r
+CYDEV_UCFG_DSI9_BASE EQU 0x40014900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI9_SIZE\r
+CYDEV_UCFG_DSI9_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI12_BASE\r
+CYDEV_UCFG_DSI12_BASE EQU 0x40014c00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI12_SIZE\r
+CYDEV_UCFG_DSI12_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI13_BASE\r
+CYDEV_UCFG_DSI13_BASE EQU 0x40014d00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI13_SIZE\r
+CYDEV_UCFG_DSI13_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BASE\r
+CYDEV_UCFG_BCTL0_BASE EQU 0x40015000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL0_SIZE\r
+CYDEV_UCFG_BCTL0_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL0_MDCLK_EN\r
+CYDEV_UCFG_BCTL0_MDCLK_EN EQU 0x40015000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL0_MBCLK_EN\r
+CYDEV_UCFG_BCTL0_MBCLK_EN EQU 0x40015001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL0_WAIT_CFG\r
+CYDEV_UCFG_BCTL0_WAIT_CFG EQU 0x40015002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BANK_CTL\r
+CYDEV_UCFG_BCTL0_BANK_CTL EQU 0x40015003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL0_UDB_TEST_3\r
+CYDEV_UCFG_BCTL0_UDB_TEST_3 EQU 0x40015007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN0\r
+CYDEV_UCFG_BCTL0_DCLK_EN0 EQU 0x40015008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN0\r
+CYDEV_UCFG_BCTL0_BCLK_EN0 EQU 0x40015009\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN1\r
+CYDEV_UCFG_BCTL0_DCLK_EN1 EQU 0x4001500a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN1\r
+CYDEV_UCFG_BCTL0_BCLK_EN1 EQU 0x4001500b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN2\r
+CYDEV_UCFG_BCTL0_DCLK_EN2 EQU 0x4001500c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN2\r
+CYDEV_UCFG_BCTL0_BCLK_EN2 EQU 0x4001500d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN3\r
+CYDEV_UCFG_BCTL0_DCLK_EN3 EQU 0x4001500e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN3\r
+CYDEV_UCFG_BCTL0_BCLK_EN3 EQU 0x4001500f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BASE\r
+CYDEV_UCFG_BCTL1_BASE EQU 0x40015010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL1_SIZE\r
+CYDEV_UCFG_BCTL1_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL1_MDCLK_EN\r
+CYDEV_UCFG_BCTL1_MDCLK_EN EQU 0x40015010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL1_MBCLK_EN\r
+CYDEV_UCFG_BCTL1_MBCLK_EN EQU 0x40015011\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL1_WAIT_CFG\r
+CYDEV_UCFG_BCTL1_WAIT_CFG EQU 0x40015012\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BANK_CTL\r
+CYDEV_UCFG_BCTL1_BANK_CTL EQU 0x40015013\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL1_UDB_TEST_3\r
+CYDEV_UCFG_BCTL1_UDB_TEST_3 EQU 0x40015017\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN0\r
+CYDEV_UCFG_BCTL1_DCLK_EN0 EQU 0x40015018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN0\r
+CYDEV_UCFG_BCTL1_BCLK_EN0 EQU 0x40015019\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN1\r
+CYDEV_UCFG_BCTL1_DCLK_EN1 EQU 0x4001501a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN1\r
+CYDEV_UCFG_BCTL1_BCLK_EN1 EQU 0x4001501b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN2\r
+CYDEV_UCFG_BCTL1_DCLK_EN2 EQU 0x4001501c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN2\r
+CYDEV_UCFG_BCTL1_BCLK_EN2 EQU 0x4001501d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN3\r
+CYDEV_UCFG_BCTL1_DCLK_EN3 EQU 0x4001501e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN3\r
+CYDEV_UCFG_BCTL1_BCLK_EN3 EQU 0x4001501f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IDMUX_BASE\r
+CYDEV_IDMUX_BASE EQU 0x40015100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IDMUX_SIZE\r
+CYDEV_IDMUX_SIZE EQU 0x00000016\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL0\r
+CYDEV_IDMUX_IRQ_CTL0 EQU 0x40015100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL1\r
+CYDEV_IDMUX_IRQ_CTL1 EQU 0x40015101\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL2\r
+CYDEV_IDMUX_IRQ_CTL2 EQU 0x40015102\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL3\r
+CYDEV_IDMUX_IRQ_CTL3 EQU 0x40015103\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL4\r
+CYDEV_IDMUX_IRQ_CTL4 EQU 0x40015104\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL5\r
+CYDEV_IDMUX_IRQ_CTL5 EQU 0x40015105\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL6\r
+CYDEV_IDMUX_IRQ_CTL6 EQU 0x40015106\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL7\r
+CYDEV_IDMUX_IRQ_CTL7 EQU 0x40015107\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL0\r
+CYDEV_IDMUX_DRQ_CTL0 EQU 0x40015110\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL1\r
+CYDEV_IDMUX_DRQ_CTL1 EQU 0x40015111\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL2\r
+CYDEV_IDMUX_DRQ_CTL2 EQU 0x40015112\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL3\r
+CYDEV_IDMUX_DRQ_CTL3 EQU 0x40015113\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL4\r
+CYDEV_IDMUX_DRQ_CTL4 EQU 0x40015114\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL5\r
+CYDEV_IDMUX_DRQ_CTL5 EQU 0x40015115\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CACHERAM_BASE\r
+CYDEV_CACHERAM_BASE EQU 0x40030000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CACHERAM_SIZE\r
+CYDEV_CACHERAM_SIZE EQU 0x00000400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CACHERAM_DATA_MBASE\r
+CYDEV_CACHERAM_DATA_MBASE EQU 0x40030000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CACHERAM_DATA_MSIZE\r
+CYDEV_CACHERAM_DATA_MSIZE EQU 0x00000400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_BASE\r
+CYDEV_SFR_BASE EQU 0x40050100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_SIZE\r
+CYDEV_SFR_SIZE EQU 0x000000fb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIO0\r
+CYDEV_SFR_GPIO0 EQU 0x40050180\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIRD0\r
+CYDEV_SFR_GPIRD0 EQU 0x40050189\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIO0_SEL\r
+CYDEV_SFR_GPIO0_SEL EQU 0x4005018a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIO1\r
+CYDEV_SFR_GPIO1 EQU 0x40050190\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIRD1\r
+CYDEV_SFR_GPIRD1 EQU 0x40050191\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIO2\r
+CYDEV_SFR_GPIO2 EQU 0x40050198\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIRD2\r
+CYDEV_SFR_GPIRD2 EQU 0x40050199\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIO2_SEL\r
+CYDEV_SFR_GPIO2_SEL EQU 0x4005019a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIO1_SEL\r
+CYDEV_SFR_GPIO1_SEL EQU 0x400501a2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIO3\r
+CYDEV_SFR_GPIO3 EQU 0x400501b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIRD3\r
+CYDEV_SFR_GPIRD3 EQU 0x400501b1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIO3_SEL\r
+CYDEV_SFR_GPIO3_SEL EQU 0x400501b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIO4\r
+CYDEV_SFR_GPIO4 EQU 0x400501c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIRD4\r
+CYDEV_SFR_GPIRD4 EQU 0x400501c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIO4_SEL\r
+CYDEV_SFR_GPIO4_SEL EQU 0x400501c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIO5\r
+CYDEV_SFR_GPIO5 EQU 0x400501c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIRD5\r
+CYDEV_SFR_GPIRD5 EQU 0x400501c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIO5_SEL\r
+CYDEV_SFR_GPIO5_SEL EQU 0x400501ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIO6\r
+CYDEV_SFR_GPIO6 EQU 0x400501d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIRD6\r
+CYDEV_SFR_GPIRD6 EQU 0x400501d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIO6_SEL\r
+CYDEV_SFR_GPIO6_SEL EQU 0x400501da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIO12\r
+CYDEV_SFR_GPIO12 EQU 0x400501e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIRD12\r
+CYDEV_SFR_GPIRD12 EQU 0x400501e9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIO12_SEL\r
+CYDEV_SFR_GPIO12_SEL EQU 0x400501f2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIO15\r
+CYDEV_SFR_GPIO15 EQU 0x400501f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIRD15\r
+CYDEV_SFR_GPIRD15 EQU 0x400501f9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_GPIO15_SEL\r
+CYDEV_SFR_GPIO15_SEL EQU 0x400501fa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_BASE\r
+CYDEV_P3BA_BASE EQU 0x40050300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_SIZE\r
+CYDEV_P3BA_SIZE EQU 0x0000002b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_Y_START\r
+CYDEV_P3BA_Y_START EQU 0x40050300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_YROLL\r
+CYDEV_P3BA_YROLL EQU 0x40050301\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_YCFG\r
+CYDEV_P3BA_YCFG EQU 0x40050302\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_X_START1\r
+CYDEV_P3BA_X_START1 EQU 0x40050303\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_X_START2\r
+CYDEV_P3BA_X_START2 EQU 0x40050304\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_XROLL1\r
+CYDEV_P3BA_XROLL1 EQU 0x40050305\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_XROLL2\r
+CYDEV_P3BA_XROLL2 EQU 0x40050306\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_XINC\r
+CYDEV_P3BA_XINC EQU 0x40050307\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_XCFG\r
+CYDEV_P3BA_XCFG EQU 0x40050308\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR1\r
+CYDEV_P3BA_OFFSETADDR1 EQU 0x40050309\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR2\r
+CYDEV_P3BA_OFFSETADDR2 EQU 0x4005030a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR3\r
+CYDEV_P3BA_OFFSETADDR3 EQU 0x4005030b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_ABSADDR1\r
+CYDEV_P3BA_ABSADDR1 EQU 0x4005030c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_ABSADDR2\r
+CYDEV_P3BA_ABSADDR2 EQU 0x4005030d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_ABSADDR3\r
+CYDEV_P3BA_ABSADDR3 EQU 0x4005030e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_ABSADDR4\r
+CYDEV_P3BA_ABSADDR4 EQU 0x4005030f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_DATCFG1\r
+CYDEV_P3BA_DATCFG1 EQU 0x40050310\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_DATCFG2\r
+CYDEV_P3BA_DATCFG2 EQU 0x40050311\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT1\r
+CYDEV_P3BA_CMP_RSLT1 EQU 0x40050314\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT2\r
+CYDEV_P3BA_CMP_RSLT2 EQU 0x40050315\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT3\r
+CYDEV_P3BA_CMP_RSLT3 EQU 0x40050316\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT4\r
+CYDEV_P3BA_CMP_RSLT4 EQU 0x40050317\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_DATA_REG1\r
+CYDEV_P3BA_DATA_REG1 EQU 0x40050318\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_DATA_REG2\r
+CYDEV_P3BA_DATA_REG2 EQU 0x40050319\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_DATA_REG3\r
+CYDEV_P3BA_DATA_REG3 EQU 0x4005031a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_DATA_REG4\r
+CYDEV_P3BA_DATA_REG4 EQU 0x4005031b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA1\r
+CYDEV_P3BA_EXP_DATA1 EQU 0x4005031c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA2\r
+CYDEV_P3BA_EXP_DATA2 EQU 0x4005031d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA3\r
+CYDEV_P3BA_EXP_DATA3 EQU 0x4005031e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA4\r
+CYDEV_P3BA_EXP_DATA4 EQU 0x4005031f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA1\r
+CYDEV_P3BA_MSTR_HRDATA1 EQU 0x40050320\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA2\r
+CYDEV_P3BA_MSTR_HRDATA2 EQU 0x40050321\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA3\r
+CYDEV_P3BA_MSTR_HRDATA3 EQU 0x40050322\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA4\r
+CYDEV_P3BA_MSTR_HRDATA4 EQU 0x40050323\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_BIST_EN\r
+CYDEV_P3BA_BIST_EN EQU 0x40050324\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_PHUB_MASTER_SSR\r
+CYDEV_P3BA_PHUB_MASTER_SSR EQU 0x40050325\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_SEQCFG1\r
+CYDEV_P3BA_SEQCFG1 EQU 0x40050326\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_SEQCFG2\r
+CYDEV_P3BA_SEQCFG2 EQU 0x40050327\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_Y_CURR\r
+CYDEV_P3BA_Y_CURR EQU 0x40050328\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_X_CURR1\r
+CYDEV_P3BA_X_CURR1 EQU 0x40050329\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_X_CURR2\r
+CYDEV_P3BA_X_CURR2 EQU 0x4005032a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PANTHER_BASE\r
+CYDEV_PANTHER_BASE EQU 0x40080000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PANTHER_SIZE\r
+CYDEV_PANTHER_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PANTHER_STCALIB_CFG\r
+CYDEV_PANTHER_STCALIB_CFG EQU 0x40080000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PANTHER_WAITPIPE\r
+CYDEV_PANTHER_WAITPIPE EQU 0x40080004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PANTHER_TRACE_CFG\r
+CYDEV_PANTHER_TRACE_CFG EQU 0x40080008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PANTHER_DBG_CFG\r
+CYDEV_PANTHER_DBG_CFG EQU 0x4008000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PANTHER_CM3_LCKRST_STAT\r
+CYDEV_PANTHER_CM3_LCKRST_STAT EQU 0x40080018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PANTHER_DEVICE_ID\r
+CYDEV_PANTHER_DEVICE_ID EQU 0x4008001c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSECC_BASE\r
+CYDEV_FLSECC_BASE EQU 0x48000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSECC_SIZE\r
+CYDEV_FLSECC_SIZE EQU 0x00008000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSECC_DATA_MBASE\r
+CYDEV_FLSECC_DATA_MBASE EQU 0x48000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSECC_DATA_MSIZE\r
+CYDEV_FLSECC_DATA_MSIZE EQU 0x00008000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_BASE\r
+CYDEV_FLSHID_BASE EQU 0x49000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_SIZE\r
+CYDEV_FLSHID_SIZE EQU 0x00000200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_RSVD_MBASE\r
+CYDEV_FLSHID_RSVD_MBASE EQU 0x49000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_RSVD_MSIZE\r
+CYDEV_FLSHID_RSVD_MSIZE EQU 0x00000080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_MDATA_MBASE\r
+CYDEV_FLSHID_CUST_MDATA_MBASE EQU 0x49000080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_MDATA_MSIZE\r
+CYDEV_FLSHID_CUST_MDATA_MSIZE EQU 0x00000080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_BASE\r
+CYDEV_FLSHID_CUST_TABLES_BASE EQU 0x49000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_SIZE\r
+CYDEV_FLSHID_CUST_TABLES_SIZE EQU 0x00000040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_Y_LOC\r
+CYDEV_FLSHID_CUST_TABLES_Y_LOC EQU 0x49000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_X_LOC\r
+CYDEV_FLSHID_CUST_TABLES_X_LOC EQU 0x49000101\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_WAFER_NUM\r
+CYDEV_FLSHID_CUST_TABLES_WAFER_NUM EQU 0x49000102\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_LOT_LSB\r
+CYDEV_FLSHID_CUST_TABLES_LOT_LSB EQU 0x49000103\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_LOT_MSB\r
+CYDEV_FLSHID_CUST_TABLES_LOT_MSB EQU 0x49000104\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_WRK_WK\r
+CYDEV_FLSHID_CUST_TABLES_WRK_WK EQU 0x49000105\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_FAB_YR\r
+CYDEV_FLSHID_CUST_TABLES_FAB_YR EQU 0x49000106\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_MINOR\r
+CYDEV_FLSHID_CUST_TABLES_MINOR EQU 0x49000107\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ\r
+CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ EQU 0x49000108\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ\r
+CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ EQU 0x49000109\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ\r
+CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ EQU 0x4900010a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ\r
+CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ EQU 0x4900010b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ\r
+CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ EQU 0x4900010c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ\r
+CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ EQU 0x4900010d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ\r
+CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ EQU 0x4900010e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_USB\r
+CYDEV_FLSHID_CUST_TABLES_IMO_USB EQU 0x4900010f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS\r
+CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS EQU 0x49000110\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS\r
+CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS EQU 0x49000111\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS\r
+CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS EQU 0x49000112\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS\r
+CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS EQU 0x49000113\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS\r
+CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS EQU 0x49000114\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS\r
+CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS EQU 0x49000115\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS\r
+CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS EQU 0x49000116\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS\r
+CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS EQU 0x49000117\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M1\r
+CYDEV_FLSHID_CUST_TABLES_DEC_M1 EQU 0x49000118\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M2\r
+CYDEV_FLSHID_CUST_TABLES_DEC_M2 EQU 0x49000119\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M3\r
+CYDEV_FLSHID_CUST_TABLES_DEC_M3 EQU 0x4900011a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M4\r
+CYDEV_FLSHID_CUST_TABLES_DEC_M4 EQU 0x4900011b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M5\r
+CYDEV_FLSHID_CUST_TABLES_DEC_M5 EQU 0x4900011c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M6\r
+CYDEV_FLSHID_CUST_TABLES_DEC_M6 EQU 0x4900011d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M7\r
+CYDEV_FLSHID_CUST_TABLES_DEC_M7 EQU 0x4900011e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M8\r
+CYDEV_FLSHID_CUST_TABLES_DEC_M8 EQU 0x4900011f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M1\r
+CYDEV_FLSHID_CUST_TABLES_DAC0_M1 EQU 0x49000120\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M2\r
+CYDEV_FLSHID_CUST_TABLES_DAC0_M2 EQU 0x49000121\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M3\r
+CYDEV_FLSHID_CUST_TABLES_DAC0_M3 EQU 0x49000122\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M4\r
+CYDEV_FLSHID_CUST_TABLES_DAC0_M4 EQU 0x49000123\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M5\r
+CYDEV_FLSHID_CUST_TABLES_DAC0_M5 EQU 0x49000124\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M6\r
+CYDEV_FLSHID_CUST_TABLES_DAC0_M6 EQU 0x49000125\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M7\r
+CYDEV_FLSHID_CUST_TABLES_DAC0_M7 EQU 0x49000126\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M8\r
+CYDEV_FLSHID_CUST_TABLES_DAC0_M8 EQU 0x49000127\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M1\r
+CYDEV_FLSHID_CUST_TABLES_DAC2_M1 EQU 0x49000128\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M2\r
+CYDEV_FLSHID_CUST_TABLES_DAC2_M2 EQU 0x49000129\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M3\r
+CYDEV_FLSHID_CUST_TABLES_DAC2_M3 EQU 0x4900012a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M4\r
+CYDEV_FLSHID_CUST_TABLES_DAC2_M4 EQU 0x4900012b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M5\r
+CYDEV_FLSHID_CUST_TABLES_DAC2_M5 EQU 0x4900012c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M6\r
+CYDEV_FLSHID_CUST_TABLES_DAC2_M6 EQU 0x4900012d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M7\r
+CYDEV_FLSHID_CUST_TABLES_DAC2_M7 EQU 0x4900012e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M8\r
+CYDEV_FLSHID_CUST_TABLES_DAC2_M8 EQU 0x4900012f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M1\r
+CYDEV_FLSHID_CUST_TABLES_DAC1_M1 EQU 0x49000130\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M2\r
+CYDEV_FLSHID_CUST_TABLES_DAC1_M2 EQU 0x49000131\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M3\r
+CYDEV_FLSHID_CUST_TABLES_DAC1_M3 EQU 0x49000132\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M4\r
+CYDEV_FLSHID_CUST_TABLES_DAC1_M4 EQU 0x49000133\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M5\r
+CYDEV_FLSHID_CUST_TABLES_DAC1_M5 EQU 0x49000134\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M6\r
+CYDEV_FLSHID_CUST_TABLES_DAC1_M6 EQU 0x49000135\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M7\r
+CYDEV_FLSHID_CUST_TABLES_DAC1_M7 EQU 0x49000136\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M8\r
+CYDEV_FLSHID_CUST_TABLES_DAC1_M8 EQU 0x49000137\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M1\r
+CYDEV_FLSHID_CUST_TABLES_DAC3_M1 EQU 0x49000138\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M2\r
+CYDEV_FLSHID_CUST_TABLES_DAC3_M2 EQU 0x49000139\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M3\r
+CYDEV_FLSHID_CUST_TABLES_DAC3_M3 EQU 0x4900013a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M4\r
+CYDEV_FLSHID_CUST_TABLES_DAC3_M4 EQU 0x4900013b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M5\r
+CYDEV_FLSHID_CUST_TABLES_DAC3_M5 EQU 0x4900013c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M6\r
+CYDEV_FLSHID_CUST_TABLES_DAC3_M6 EQU 0x4900013d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M7\r
+CYDEV_FLSHID_CUST_TABLES_DAC3_M7 EQU 0x4900013e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M8\r
+CYDEV_FLSHID_CUST_TABLES_DAC3_M8 EQU 0x4900013f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BASE\r
+CYDEV_FLSHID_MFG_CFG_BASE EQU 0x49000180\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_SIZE\r
+CYDEV_FLSHID_MFG_CFG_SIZE EQU 0x00000080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_IMO_TR1\r
+CYDEV_FLSHID_MFG_CFG_IMO_TR1 EQU 0x49000188\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP0_TR0\r
+CYDEV_FLSHID_MFG_CFG_CMP0_TR0 EQU 0x490001ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP1_TR0\r
+CYDEV_FLSHID_MFG_CFG_CMP1_TR0 EQU 0x490001ae\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP2_TR0\r
+CYDEV_FLSHID_MFG_CFG_CMP2_TR0 EQU 0x490001b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP3_TR0\r
+CYDEV_FLSHID_MFG_CFG_CMP3_TR0 EQU 0x490001b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP0_TR1\r
+CYDEV_FLSHID_MFG_CFG_CMP0_TR1 EQU 0x490001b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP1_TR1\r
+CYDEV_FLSHID_MFG_CFG_CMP1_TR1 EQU 0x490001b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP2_TR1\r
+CYDEV_FLSHID_MFG_CFG_CMP2_TR1 EQU 0x490001b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP3_TR1\r
+CYDEV_FLSHID_MFG_CFG_CMP3_TR1 EQU 0x490001ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM\r
+CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM EQU 0x490001ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EXTMEM_BASE\r
+CYDEV_EXTMEM_BASE EQU 0x60000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EXTMEM_SIZE\r
+CYDEV_EXTMEM_SIZE EQU 0x00800000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EXTMEM_DATA_MBASE\r
+CYDEV_EXTMEM_DATA_MBASE EQU 0x60000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EXTMEM_DATA_MSIZE\r
+CYDEV_EXTMEM_DATA_MSIZE EQU 0x00800000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_BASE\r
+CYDEV_ITM_BASE EQU 0xe0000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_SIZE\r
+CYDEV_ITM_SIZE EQU 0x00001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_TRACE_EN\r
+CYDEV_ITM_TRACE_EN EQU 0xe0000e00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_TRACE_PRIVILEGE\r
+CYDEV_ITM_TRACE_PRIVILEGE EQU 0xe0000e40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_TRACE_CTRL\r
+CYDEV_ITM_TRACE_CTRL EQU 0xe0000e80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_LOCK_ACCESS\r
+CYDEV_ITM_LOCK_ACCESS EQU 0xe0000fb0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_LOCK_STATUS\r
+CYDEV_ITM_LOCK_STATUS EQU 0xe0000fb4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_PID4\r
+CYDEV_ITM_PID4 EQU 0xe0000fd0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_PID5\r
+CYDEV_ITM_PID5 EQU 0xe0000fd4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_PID6\r
+CYDEV_ITM_PID6 EQU 0xe0000fd8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_PID7\r
+CYDEV_ITM_PID7 EQU 0xe0000fdc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_PID0\r
+CYDEV_ITM_PID0 EQU 0xe0000fe0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_PID1\r
+CYDEV_ITM_PID1 EQU 0xe0000fe4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_PID2\r
+CYDEV_ITM_PID2 EQU 0xe0000fe8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_PID3\r
+CYDEV_ITM_PID3 EQU 0xe0000fec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_CID0\r
+CYDEV_ITM_CID0 EQU 0xe0000ff0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_CID1\r
+CYDEV_ITM_CID1 EQU 0xe0000ff4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_CID2\r
+CYDEV_ITM_CID2 EQU 0xe0000ff8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_CID3\r
+CYDEV_ITM_CID3 EQU 0xe0000ffc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_BASE\r
+CYDEV_DWT_BASE EQU 0xe0001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_SIZE\r
+CYDEV_DWT_SIZE EQU 0x0000005c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_CTRL\r
+CYDEV_DWT_CTRL EQU 0xe0001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_CYCLE_COUNT\r
+CYDEV_DWT_CYCLE_COUNT EQU 0xe0001004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_CPI_COUNT\r
+CYDEV_DWT_CPI_COUNT EQU 0xe0001008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_EXC_OVHD_COUNT\r
+CYDEV_DWT_EXC_OVHD_COUNT EQU 0xe000100c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_SLEEP_COUNT\r
+CYDEV_DWT_SLEEP_COUNT EQU 0xe0001010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_LSU_COUNT\r
+CYDEV_DWT_LSU_COUNT EQU 0xe0001014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_FOLD_COUNT\r
+CYDEV_DWT_FOLD_COUNT EQU 0xe0001018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_PC_SAMPLE\r
+CYDEV_DWT_PC_SAMPLE EQU 0xe000101c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_COMP_0\r
+CYDEV_DWT_COMP_0 EQU 0xe0001020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_MASK_0\r
+CYDEV_DWT_MASK_0 EQU 0xe0001024\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_FUNCTION_0\r
+CYDEV_DWT_FUNCTION_0 EQU 0xe0001028\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_COMP_1\r
+CYDEV_DWT_COMP_1 EQU 0xe0001030\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_MASK_1\r
+CYDEV_DWT_MASK_1 EQU 0xe0001034\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_FUNCTION_1\r
+CYDEV_DWT_FUNCTION_1 EQU 0xe0001038\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_COMP_2\r
+CYDEV_DWT_COMP_2 EQU 0xe0001040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_MASK_2\r
+CYDEV_DWT_MASK_2 EQU 0xe0001044\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_FUNCTION_2\r
+CYDEV_DWT_FUNCTION_2 EQU 0xe0001048\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_COMP_3\r
+CYDEV_DWT_COMP_3 EQU 0xe0001050\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_MASK_3\r
+CYDEV_DWT_MASK_3 EQU 0xe0001054\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_FUNCTION_3\r
+CYDEV_DWT_FUNCTION_3 EQU 0xe0001058\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_BASE\r
+CYDEV_FPB_BASE EQU 0xe0002000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_SIZE\r
+CYDEV_FPB_SIZE EQU 0x00001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_CTRL\r
+CYDEV_FPB_CTRL EQU 0xe0002000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_REMAP\r
+CYDEV_FPB_REMAP EQU 0xe0002004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_FP_COMP_0\r
+CYDEV_FPB_FP_COMP_0 EQU 0xe0002008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_FP_COMP_1\r
+CYDEV_FPB_FP_COMP_1 EQU 0xe000200c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_FP_COMP_2\r
+CYDEV_FPB_FP_COMP_2 EQU 0xe0002010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_FP_COMP_3\r
+CYDEV_FPB_FP_COMP_3 EQU 0xe0002014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_FP_COMP_4\r
+CYDEV_FPB_FP_COMP_4 EQU 0xe0002018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_FP_COMP_5\r
+CYDEV_FPB_FP_COMP_5 EQU 0xe000201c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_FP_COMP_6\r
+CYDEV_FPB_FP_COMP_6 EQU 0xe0002020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_FP_COMP_7\r
+CYDEV_FPB_FP_COMP_7 EQU 0xe0002024\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_PID4\r
+CYDEV_FPB_PID4 EQU 0xe0002fd0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_PID5\r
+CYDEV_FPB_PID5 EQU 0xe0002fd4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_PID6\r
+CYDEV_FPB_PID6 EQU 0xe0002fd8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_PID7\r
+CYDEV_FPB_PID7 EQU 0xe0002fdc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_PID0\r
+CYDEV_FPB_PID0 EQU 0xe0002fe0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_PID1\r
+CYDEV_FPB_PID1 EQU 0xe0002fe4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_PID2\r
+CYDEV_FPB_PID2 EQU 0xe0002fe8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_PID3\r
+CYDEV_FPB_PID3 EQU 0xe0002fec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_CID0\r
+CYDEV_FPB_CID0 EQU 0xe0002ff0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_CID1\r
+CYDEV_FPB_CID1 EQU 0xe0002ff4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_CID2\r
+CYDEV_FPB_CID2 EQU 0xe0002ff8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_CID3\r
+CYDEV_FPB_CID3 EQU 0xe0002ffc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_BASE\r
+CYDEV_NVIC_BASE EQU 0xe000e000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_SIZE\r
+CYDEV_NVIC_SIZE EQU 0x00000d3c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_INT_CTL_TYPE\r
+CYDEV_NVIC_INT_CTL_TYPE EQU 0xe000e004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CTL\r
+CYDEV_NVIC_SYSTICK_CTL EQU 0xe000e010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_RELOAD\r
+CYDEV_NVIC_SYSTICK_RELOAD EQU 0xe000e014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CURRENT\r
+CYDEV_NVIC_SYSTICK_CURRENT EQU 0xe000e018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CAL\r
+CYDEV_NVIC_SYSTICK_CAL EQU 0xe000e01c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_SETENA0\r
+CYDEV_NVIC_SETENA0 EQU 0xe000e100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_CLRENA0\r
+CYDEV_NVIC_CLRENA0 EQU 0xe000e180\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_SETPEND0\r
+CYDEV_NVIC_SETPEND0 EQU 0xe000e200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_CLRPEND0\r
+CYDEV_NVIC_CLRPEND0 EQU 0xe000e280\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_ACTIVE0\r
+CYDEV_NVIC_ACTIVE0 EQU 0xe000e300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_0\r
+CYDEV_NVIC_PRI_0 EQU 0xe000e400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_1\r
+CYDEV_NVIC_PRI_1 EQU 0xe000e401\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_2\r
+CYDEV_NVIC_PRI_2 EQU 0xe000e402\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_3\r
+CYDEV_NVIC_PRI_3 EQU 0xe000e403\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_4\r
+CYDEV_NVIC_PRI_4 EQU 0xe000e404\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_5\r
+CYDEV_NVIC_PRI_5 EQU 0xe000e405\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_6\r
+CYDEV_NVIC_PRI_6 EQU 0xe000e406\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_7\r
+CYDEV_NVIC_PRI_7 EQU 0xe000e407\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_8\r
+CYDEV_NVIC_PRI_8 EQU 0xe000e408\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_9\r
+CYDEV_NVIC_PRI_9 EQU 0xe000e409\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_10\r
+CYDEV_NVIC_PRI_10 EQU 0xe000e40a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_11\r
+CYDEV_NVIC_PRI_11 EQU 0xe000e40b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_12\r
+CYDEV_NVIC_PRI_12 EQU 0xe000e40c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_13\r
+CYDEV_NVIC_PRI_13 EQU 0xe000e40d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_14\r
+CYDEV_NVIC_PRI_14 EQU 0xe000e40e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_15\r
+CYDEV_NVIC_PRI_15 EQU 0xe000e40f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_16\r
+CYDEV_NVIC_PRI_16 EQU 0xe000e410\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_17\r
+CYDEV_NVIC_PRI_17 EQU 0xe000e411\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_18\r
+CYDEV_NVIC_PRI_18 EQU 0xe000e412\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_19\r
+CYDEV_NVIC_PRI_19 EQU 0xe000e413\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_20\r
+CYDEV_NVIC_PRI_20 EQU 0xe000e414\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_21\r
+CYDEV_NVIC_PRI_21 EQU 0xe000e415\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_22\r
+CYDEV_NVIC_PRI_22 EQU 0xe000e416\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_23\r
+CYDEV_NVIC_PRI_23 EQU 0xe000e417\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_24\r
+CYDEV_NVIC_PRI_24 EQU 0xe000e418\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_25\r
+CYDEV_NVIC_PRI_25 EQU 0xe000e419\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_26\r
+CYDEV_NVIC_PRI_26 EQU 0xe000e41a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_27\r
+CYDEV_NVIC_PRI_27 EQU 0xe000e41b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_28\r
+CYDEV_NVIC_PRI_28 EQU 0xe000e41c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_29\r
+CYDEV_NVIC_PRI_29 EQU 0xe000e41d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_30\r
+CYDEV_NVIC_PRI_30 EQU 0xe000e41e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_PRI_31\r
+CYDEV_NVIC_PRI_31 EQU 0xe000e41f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_CPUID_BASE\r
+CYDEV_NVIC_CPUID_BASE EQU 0xe000ed00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_INTR_CTRL_STATE\r
+CYDEV_NVIC_INTR_CTRL_STATE EQU 0xe000ed04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_VECT_OFFSET\r
+CYDEV_NVIC_VECT_OFFSET EQU 0xe000ed08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_APPLN_INTR\r
+CYDEV_NVIC_APPLN_INTR EQU 0xe000ed0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_SYSTEM_CONTROL\r
+CYDEV_NVIC_SYSTEM_CONTROL EQU 0xe000ed10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_CFG_CONTROL\r
+CYDEV_NVIC_CFG_CONTROL EQU 0xe000ed14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_4_7\r
+CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 EQU 0xe000ed18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_8_11\r
+CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 EQU 0xe000ed1c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_12_15\r
+CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 EQU 0xe000ed20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_SYS_HANDLER_CSR\r
+CYDEV_NVIC_SYS_HANDLER_CSR EQU 0xe000ed24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_MEMMAN_FAULT_STATUS\r
+CYDEV_NVIC_MEMMAN_FAULT_STATUS EQU 0xe000ed28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_BUS_FAULT_STATUS\r
+CYDEV_NVIC_BUS_FAULT_STATUS EQU 0xe000ed29\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_USAGE_FAULT_STATUS\r
+CYDEV_NVIC_USAGE_FAULT_STATUS EQU 0xe000ed2a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_HARD_FAULT_STATUS\r
+CYDEV_NVIC_HARD_FAULT_STATUS EQU 0xe000ed2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_DEBUG_FAULT_STATUS\r
+CYDEV_NVIC_DEBUG_FAULT_STATUS EQU 0xe000ed30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_MEMMAN_FAULT_ADD\r
+CYDEV_NVIC_MEMMAN_FAULT_ADD EQU 0xe000ed34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_BUS_FAULT_ADD\r
+CYDEV_NVIC_BUS_FAULT_ADD EQU 0xe000ed38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CORE_DBG_BASE\r
+CYDEV_CORE_DBG_BASE EQU 0xe000edf0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CORE_DBG_SIZE\r
+CYDEV_CORE_DBG_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_HLT_CS\r
+CYDEV_CORE_DBG_DBG_HLT_CS EQU 0xe000edf0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_REG_SEL\r
+CYDEV_CORE_DBG_DBG_REG_SEL EQU 0xe000edf4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_REG_DATA\r
+CYDEV_CORE_DBG_DBG_REG_DATA EQU 0xe000edf8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CORE_DBG_EXC_MON_CTL\r
+CYDEV_CORE_DBG_EXC_MON_CTL EQU 0xe000edfc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_BASE\r
+CYDEV_TPIU_BASE EQU 0xe0040000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_SIZE\r
+CYDEV_TPIU_SIZE EQU 0x00001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ\r
+CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ EQU 0xe0040000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_CURRENT_SYNC_PRT_SZ\r
+CYDEV_TPIU_CURRENT_SYNC_PRT_SZ EQU 0xe0040004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_ASYNC_CLK_PRESCALER\r
+CYDEV_TPIU_ASYNC_CLK_PRESCALER EQU 0xe0040010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_PROTOCOL\r
+CYDEV_TPIU_PROTOCOL EQU 0xe00400f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_FORM_FLUSH_STAT\r
+CYDEV_TPIU_FORM_FLUSH_STAT EQU 0xe0040300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_FORM_FLUSH_CTRL\r
+CYDEV_TPIU_FORM_FLUSH_CTRL EQU 0xe0040304\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_TRIGGER\r
+CYDEV_TPIU_TRIGGER EQU 0xe0040ee8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_ITETMDATA\r
+CYDEV_TPIU_ITETMDATA EQU 0xe0040eec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_ITATBCTR2\r
+CYDEV_TPIU_ITATBCTR2 EQU 0xe0040ef0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_ITATBCTR0\r
+CYDEV_TPIU_ITATBCTR0 EQU 0xe0040ef8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_ITITMDATA\r
+CYDEV_TPIU_ITITMDATA EQU 0xe0040efc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_ITCTRL\r
+CYDEV_TPIU_ITCTRL EQU 0xe0040f00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_DEVID\r
+CYDEV_TPIU_DEVID EQU 0xe0040fc8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_DEVTYPE\r
+CYDEV_TPIU_DEVTYPE EQU 0xe0040fcc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_PID4\r
+CYDEV_TPIU_PID4 EQU 0xe0040fd0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_PID5\r
+CYDEV_TPIU_PID5 EQU 0xe0040fd4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_PID6\r
+CYDEV_TPIU_PID6 EQU 0xe0040fd8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_PID7\r
+CYDEV_TPIU_PID7 EQU 0xe0040fdc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_PID0\r
+CYDEV_TPIU_PID0 EQU 0xe0040fe0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_PID1\r
+CYDEV_TPIU_PID1 EQU 0xe0040fe4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_PID2\r
+CYDEV_TPIU_PID2 EQU 0xe0040fe8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_PID3\r
+CYDEV_TPIU_PID3 EQU 0xe0040fec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_CID0\r
+CYDEV_TPIU_CID0 EQU 0xe0040ff0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_CID1\r
+CYDEV_TPIU_CID1 EQU 0xe0040ff4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_CID2\r
+CYDEV_TPIU_CID2 EQU 0xe0040ff8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_CID3\r
+CYDEV_TPIU_CID3 EQU 0xe0040ffc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_BASE\r
+CYDEV_ETM_BASE EQU 0xe0041000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_SIZE\r
+CYDEV_ETM_SIZE EQU 0x00001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_CTL\r
+CYDEV_ETM_CTL EQU 0xe0041000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_CFG_CODE\r
+CYDEV_ETM_CFG_CODE EQU 0xe0041004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_TRIG_EVENT\r
+CYDEV_ETM_TRIG_EVENT EQU 0xe0041008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_STATUS\r
+CYDEV_ETM_STATUS EQU 0xe0041010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_SYS_CFG\r
+CYDEV_ETM_SYS_CFG EQU 0xe0041014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_TRACE_ENB_EVENT\r
+CYDEV_ETM_TRACE_ENB_EVENT EQU 0xe0041020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_TRACE_EN_CTRL1\r
+CYDEV_ETM_TRACE_EN_CTRL1 EQU 0xe0041024\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_FIFOFULL_LEVEL\r
+CYDEV_ETM_FIFOFULL_LEVEL EQU 0xe004102c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_SYNC_FREQ\r
+CYDEV_ETM_SYNC_FREQ EQU 0xe00411e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_ETM_ID\r
+CYDEV_ETM_ETM_ID EQU 0xe00411e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_CFG_CODE_EXT\r
+CYDEV_ETM_CFG_CODE_EXT EQU 0xe00411e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_TR_SS_EMBICE_CTRL\r
+CYDEV_ETM_TR_SS_EMBICE_CTRL EQU 0xe00411f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_CS_TRACE_ID\r
+CYDEV_ETM_CS_TRACE_ID EQU 0xe0041200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_OS_LOCK_ACCESS\r
+CYDEV_ETM_OS_LOCK_ACCESS EQU 0xe0041300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_OS_LOCK_STATUS\r
+CYDEV_ETM_OS_LOCK_STATUS EQU 0xe0041304\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_PDSR\r
+CYDEV_ETM_PDSR EQU 0xe0041314\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_ITMISCIN\r
+CYDEV_ETM_ITMISCIN EQU 0xe0041ee0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_ITTRIGOUT\r
+CYDEV_ETM_ITTRIGOUT EQU 0xe0041ee8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_ITATBCTR2\r
+CYDEV_ETM_ITATBCTR2 EQU 0xe0041ef0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_ITATBCTR0\r
+CYDEV_ETM_ITATBCTR0 EQU 0xe0041ef8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_INT_MODE_CTRL\r
+CYDEV_ETM_INT_MODE_CTRL EQU 0xe0041f00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_CLM_TAG_SET\r
+CYDEV_ETM_CLM_TAG_SET EQU 0xe0041fa0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_CLM_TAG_CLR\r
+CYDEV_ETM_CLM_TAG_CLR EQU 0xe0041fa4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_LOCK_ACCESS\r
+CYDEV_ETM_LOCK_ACCESS EQU 0xe0041fb0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_LOCK_STATUS\r
+CYDEV_ETM_LOCK_STATUS EQU 0xe0041fb4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_AUTH_STATUS\r
+CYDEV_ETM_AUTH_STATUS EQU 0xe0041fb8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_DEV_TYPE\r
+CYDEV_ETM_DEV_TYPE EQU 0xe0041fcc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_PID4\r
+CYDEV_ETM_PID4 EQU 0xe0041fd0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_PID5\r
+CYDEV_ETM_PID5 EQU 0xe0041fd4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_PID6\r
+CYDEV_ETM_PID6 EQU 0xe0041fd8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_PID7\r
+CYDEV_ETM_PID7 EQU 0xe0041fdc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_PID0\r
+CYDEV_ETM_PID0 EQU 0xe0041fe0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_PID1\r
+CYDEV_ETM_PID1 EQU 0xe0041fe4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_PID2\r
+CYDEV_ETM_PID2 EQU 0xe0041fe8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_PID3\r
+CYDEV_ETM_PID3 EQU 0xe0041fec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_CID0\r
+CYDEV_ETM_CID0 EQU 0xe0041ff0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_CID1\r
+CYDEV_ETM_CID1 EQU 0xe0041ff4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_CID2\r
+CYDEV_ETM_CID2 EQU 0xe0041ff8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_CID3\r
+CYDEV_ETM_CID3 EQU 0xe0041ffc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_BASE\r
+CYDEV_ROM_TABLE_BASE EQU 0xe00ff000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_SIZE\r
+CYDEV_ROM_TABLE_SIZE EQU 0x00001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_NVIC\r
+CYDEV_ROM_TABLE_NVIC EQU 0xe00ff000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_DWT\r
+CYDEV_ROM_TABLE_DWT EQU 0xe00ff004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_FPB\r
+CYDEV_ROM_TABLE_FPB EQU 0xe00ff008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_ITM\r
+CYDEV_ROM_TABLE_ITM EQU 0xe00ff00c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_TPIU\r
+CYDEV_ROM_TABLE_TPIU EQU 0xe00ff010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_ETM\r
+CYDEV_ROM_TABLE_ETM EQU 0xe00ff014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_END\r
+CYDEV_ROM_TABLE_END EQU 0xe00ff018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_MEMTYPE\r
+CYDEV_ROM_TABLE_MEMTYPE EQU 0xe00fffcc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_PID4\r
+CYDEV_ROM_TABLE_PID4 EQU 0xe00fffd0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_PID5\r
+CYDEV_ROM_TABLE_PID5 EQU 0xe00fffd4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_PID6\r
+CYDEV_ROM_TABLE_PID6 EQU 0xe00fffd8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_PID7\r
+CYDEV_ROM_TABLE_PID7 EQU 0xe00fffdc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_PID0\r
+CYDEV_ROM_TABLE_PID0 EQU 0xe00fffe0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_PID1\r
+CYDEV_ROM_TABLE_PID1 EQU 0xe00fffe4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_PID2\r
+CYDEV_ROM_TABLE_PID2 EQU 0xe00fffe8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_PID3\r
+CYDEV_ROM_TABLE_PID3 EQU 0xe00fffec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_CID0\r
+CYDEV_ROM_TABLE_CID0 EQU 0xe00ffff0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_CID1\r
+CYDEV_ROM_TABLE_CID1 EQU 0xe00ffff4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_CID2\r
+CYDEV_ROM_TABLE_CID2 EQU 0xe00ffff8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_CID3\r
+CYDEV_ROM_TABLE_CID3 EQU 0xe00ffffc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLS_SIZE\r
+CYDEV_FLS_SIZE EQU CYDEV_FLASH_SIZE\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ECC_BASE\r
+CYDEV_ECC_BASE EQU CYDEV_FLSECC_BASE\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE\r
+CYDEV_FLS_SECTOR_SIZE EQU 0x00010000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE\r
+CYDEV_FLS_ROW_SIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE\r
+CYDEV_ECC_SECTOR_SIZE EQU 0x00002000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ECC_ROW_SIZE\r
+CYDEV_ECC_ROW_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EEPROM_SECTOR_SIZE\r
+CYDEV_EEPROM_SECTOR_SIZE EQU 0x00000400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EEPROM_ROW_SIZE\r
+CYDEV_EEPROM_ROW_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PERIPH_BASE\r
+CYDEV_PERIPH_BASE EQU CYDEV_CLKDIST_BASE\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_LD_DISABLE\r
+CYCLK_LD_DISABLE EQU 0x00000004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_LD_SYNC_EN\r
+CYCLK_LD_SYNC_EN EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_LD_LOAD\r
+CYCLK_LD_LOAD EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_PIPE\r
+CYCLK_PIPE EQU 0x00000080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SSS\r
+CYCLK_SSS EQU 0x00000040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_EARLY\r
+CYCLK_EARLY EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_DUTY\r
+CYCLK_DUTY EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SYNC\r
+CYCLK_SYNC EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_D\r
+CYCLK_SRC_SEL_CLK_SYNC_D EQU 0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_SYNC_DIG\r
+CYCLK_SRC_SEL_SYNC_DIG EQU 0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_IMO\r
+CYCLK_SRC_SEL_IMO EQU 1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_MHZ\r
+CYCLK_SRC_SEL_XTAL_MHZ EQU 2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_XTALM\r
+CYCLK_SRC_SEL_XTALM EQU 2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_ILO\r
+CYCLK_SRC_SEL_ILO EQU 3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_PLL\r
+CYCLK_SRC_SEL_PLL EQU 4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_KHZ\r
+CYCLK_SRC_SEL_XTAL_KHZ EQU 5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_XTALK\r
+CYCLK_SRC_SEL_XTALK EQU 5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_G\r
+CYCLK_SRC_SEL_DSI_G EQU 6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_D\r
+CYCLK_SRC_SEL_DSI_D EQU 7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_A\r
+CYCLK_SRC_SEL_CLK_SYNC_A EQU 0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_A\r
+CYCLK_SRC_SEL_DSI_A EQU 7\r
+ ENDIF\r
+ END\r
--- /dev/null
+;\r
+; FILENAME: cydevicerv_trm.inc\r
+; \r
+; PSoC Creator 2.2 Component Pack 6\r
+;\r
+; DESCRIPTION:\r
+; This file provides all of the address values for the entire PSoC device.\r
+;\r
+;-------------------------------------------------------------------------------\r
+; Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+; You may use this file only in accordance with the license, terms, conditions, \r
+; disclaimers, and limitations in the end user license agreement accompanying \r
+; the software package with which this file was provided.\r
+;-------------------------------------------------------------------------------\r
+\r
+ IF :LNOT::DEF:CYDEV_FLASH_BASE\r
+CYDEV_FLASH_BASE EQU 0x00000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLASH_SIZE\r
+CYDEV_FLASH_SIZE EQU 0x00040000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLASH_DATA_MBASE\r
+CYREG_FLASH_DATA_MBASE EQU 0x00000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLASH_DATA_MSIZE\r
+CYREG_FLASH_DATA_MSIZE EQU 0x00040000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_BASE\r
+CYDEV_SRAM_BASE EQU 0x1fff8000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SRAM_SIZE\r
+CYDEV_SRAM_SIZE EQU 0x00010000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SRAM_CODE64K_MBASE\r
+CYREG_SRAM_CODE64K_MBASE EQU 0x1fff8000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SRAM_CODE64K_MSIZE\r
+CYREG_SRAM_CODE64K_MSIZE EQU 0x00004000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SRAM_CODE32K_MBASE\r
+CYREG_SRAM_CODE32K_MBASE EQU 0x1fffc000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SRAM_CODE32K_MSIZE\r
+CYREG_SRAM_CODE32K_MSIZE EQU 0x00002000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SRAM_CODE16K_MBASE\r
+CYREG_SRAM_CODE16K_MBASE EQU 0x1fffe000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SRAM_CODE16K_MSIZE\r
+CYREG_SRAM_CODE16K_MSIZE EQU 0x00001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SRAM_CODE_MBASE\r
+CYREG_SRAM_CODE_MBASE EQU 0x1fff8000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SRAM_CODE_MSIZE\r
+CYREG_SRAM_CODE_MSIZE EQU 0x00008000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SRAM_DATA_MBASE\r
+CYREG_SRAM_DATA_MBASE EQU 0x20000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SRAM_DATA_MSIZE\r
+CYREG_SRAM_DATA_MSIZE EQU 0x00008000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SRAM_DATA16K_MBASE\r
+CYREG_SRAM_DATA16K_MBASE EQU 0x20001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SRAM_DATA16K_MSIZE\r
+CYREG_SRAM_DATA16K_MSIZE EQU 0x00001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SRAM_DATA32K_MBASE\r
+CYREG_SRAM_DATA32K_MBASE EQU 0x20002000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SRAM_DATA32K_MSIZE\r
+CYREG_SRAM_DATA32K_MSIZE EQU 0x00002000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SRAM_DATA64K_MBASE\r
+CYREG_SRAM_DATA64K_MBASE EQU 0x20004000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SRAM_DATA64K_MSIZE\r
+CYREG_SRAM_DATA64K_MSIZE EQU 0x00004000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DMA_BASE\r
+CYDEV_DMA_BASE EQU 0x20008000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DMA_SIZE\r
+CYDEV_DMA_SIZE EQU 0x00008000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DMA_SRAM64K_MBASE\r
+CYREG_DMA_SRAM64K_MBASE EQU 0x20008000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DMA_SRAM64K_MSIZE\r
+CYREG_DMA_SRAM64K_MSIZE EQU 0x00004000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DMA_SRAM32K_MBASE\r
+CYREG_DMA_SRAM32K_MBASE EQU 0x2000c000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DMA_SRAM32K_MSIZE\r
+CYREG_DMA_SRAM32K_MSIZE EQU 0x00002000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DMA_SRAM16K_MBASE\r
+CYREG_DMA_SRAM16K_MBASE EQU 0x2000e000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DMA_SRAM16K_MSIZE\r
+CYREG_DMA_SRAM16K_MSIZE EQU 0x00001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DMA_SRAM_MBASE\r
+CYREG_DMA_SRAM_MBASE EQU 0x2000f000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DMA_SRAM_MSIZE\r
+CYREG_DMA_SRAM_MSIZE EQU 0x00001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_BASE\r
+CYDEV_CLKDIST_BASE EQU 0x40004000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_SIZE\r
+CYDEV_CLKDIST_SIZE EQU 0x00000110\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_CR\r
+CYREG_CLKDIST_CR EQU 0x40004000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_LD\r
+CYREG_CLKDIST_LD EQU 0x40004001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_WRK0\r
+CYREG_CLKDIST_WRK0 EQU 0x40004002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_WRK1\r
+CYREG_CLKDIST_WRK1 EQU 0x40004003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_MSTR0\r
+CYREG_CLKDIST_MSTR0 EQU 0x40004004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_MSTR1\r
+CYREG_CLKDIST_MSTR1 EQU 0x40004005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_BCFG0\r
+CYREG_CLKDIST_BCFG0 EQU 0x40004006\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_BCFG1\r
+CYREG_CLKDIST_BCFG1 EQU 0x40004007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_BCFG2\r
+CYREG_CLKDIST_BCFG2 EQU 0x40004008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_UCFG\r
+CYREG_CLKDIST_UCFG EQU 0x40004009\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DLY0\r
+CYREG_CLKDIST_DLY0 EQU 0x4000400a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DLY1\r
+CYREG_CLKDIST_DLY1 EQU 0x4000400b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DMASK\r
+CYREG_CLKDIST_DMASK EQU 0x40004010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_AMASK\r
+CYREG_CLKDIST_AMASK EQU 0x40004014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_BASE\r
+CYDEV_CLKDIST_DCFG0_BASE EQU 0x40004080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_SIZE\r
+CYDEV_CLKDIST_DCFG0_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG0\r
+CYREG_CLKDIST_DCFG0_CFG0 EQU 0x40004080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG1\r
+CYREG_CLKDIST_DCFG0_CFG1 EQU 0x40004081\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG2\r
+CYREG_CLKDIST_DCFG0_CFG2 EQU 0x40004082\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_BASE\r
+CYDEV_CLKDIST_DCFG1_BASE EQU 0x40004084\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_SIZE\r
+CYDEV_CLKDIST_DCFG1_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG0\r
+CYREG_CLKDIST_DCFG1_CFG0 EQU 0x40004084\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG1\r
+CYREG_CLKDIST_DCFG1_CFG1 EQU 0x40004085\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG2\r
+CYREG_CLKDIST_DCFG1_CFG2 EQU 0x40004086\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_BASE\r
+CYDEV_CLKDIST_DCFG2_BASE EQU 0x40004088\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_SIZE\r
+CYDEV_CLKDIST_DCFG2_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG0\r
+CYREG_CLKDIST_DCFG2_CFG0 EQU 0x40004088\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG1\r
+CYREG_CLKDIST_DCFG2_CFG1 EQU 0x40004089\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG2\r
+CYREG_CLKDIST_DCFG2_CFG2 EQU 0x4000408a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_BASE\r
+CYDEV_CLKDIST_DCFG3_BASE EQU 0x4000408c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_SIZE\r
+CYDEV_CLKDIST_DCFG3_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG0\r
+CYREG_CLKDIST_DCFG3_CFG0 EQU 0x4000408c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG1\r
+CYREG_CLKDIST_DCFG3_CFG1 EQU 0x4000408d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG2\r
+CYREG_CLKDIST_DCFG3_CFG2 EQU 0x4000408e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_BASE\r
+CYDEV_CLKDIST_DCFG4_BASE EQU 0x40004090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_SIZE\r
+CYDEV_CLKDIST_DCFG4_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG0\r
+CYREG_CLKDIST_DCFG4_CFG0 EQU 0x40004090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG1\r
+CYREG_CLKDIST_DCFG4_CFG1 EQU 0x40004091\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG2\r
+CYREG_CLKDIST_DCFG4_CFG2 EQU 0x40004092\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_BASE\r
+CYDEV_CLKDIST_DCFG5_BASE EQU 0x40004094\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_SIZE\r
+CYDEV_CLKDIST_DCFG5_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG0\r
+CYREG_CLKDIST_DCFG5_CFG0 EQU 0x40004094\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG1\r
+CYREG_CLKDIST_DCFG5_CFG1 EQU 0x40004095\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG2\r
+CYREG_CLKDIST_DCFG5_CFG2 EQU 0x40004096\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_BASE\r
+CYDEV_CLKDIST_DCFG6_BASE EQU 0x40004098\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_SIZE\r
+CYDEV_CLKDIST_DCFG6_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG0\r
+CYREG_CLKDIST_DCFG6_CFG0 EQU 0x40004098\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG1\r
+CYREG_CLKDIST_DCFG6_CFG1 EQU 0x40004099\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG2\r
+CYREG_CLKDIST_DCFG6_CFG2 EQU 0x4000409a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_BASE\r
+CYDEV_CLKDIST_DCFG7_BASE EQU 0x4000409c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_SIZE\r
+CYDEV_CLKDIST_DCFG7_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG0\r
+CYREG_CLKDIST_DCFG7_CFG0 EQU 0x4000409c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG1\r
+CYREG_CLKDIST_DCFG7_CFG1 EQU 0x4000409d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG2\r
+CYREG_CLKDIST_DCFG7_CFG2 EQU 0x4000409e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_BASE\r
+CYDEV_CLKDIST_ACFG0_BASE EQU 0x40004100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_SIZE\r
+CYDEV_CLKDIST_ACFG0_SIZE EQU 0x00000004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG0\r
+CYREG_CLKDIST_ACFG0_CFG0 EQU 0x40004100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG1\r
+CYREG_CLKDIST_ACFG0_CFG1 EQU 0x40004101\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG2\r
+CYREG_CLKDIST_ACFG0_CFG2 EQU 0x40004102\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG3\r
+CYREG_CLKDIST_ACFG0_CFG3 EQU 0x40004103\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_BASE\r
+CYDEV_CLKDIST_ACFG1_BASE EQU 0x40004104\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_SIZE\r
+CYDEV_CLKDIST_ACFG1_SIZE EQU 0x00000004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG0\r
+CYREG_CLKDIST_ACFG1_CFG0 EQU 0x40004104\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG1\r
+CYREG_CLKDIST_ACFG1_CFG1 EQU 0x40004105\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG2\r
+CYREG_CLKDIST_ACFG1_CFG2 EQU 0x40004106\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG3\r
+CYREG_CLKDIST_ACFG1_CFG3 EQU 0x40004107\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_BASE\r
+CYDEV_CLKDIST_ACFG2_BASE EQU 0x40004108\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_SIZE\r
+CYDEV_CLKDIST_ACFG2_SIZE EQU 0x00000004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG0\r
+CYREG_CLKDIST_ACFG2_CFG0 EQU 0x40004108\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG1\r
+CYREG_CLKDIST_ACFG2_CFG1 EQU 0x40004109\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG2\r
+CYREG_CLKDIST_ACFG2_CFG2 EQU 0x4000410a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG3\r
+CYREG_CLKDIST_ACFG2_CFG3 EQU 0x4000410b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_BASE\r
+CYDEV_CLKDIST_ACFG3_BASE EQU 0x4000410c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_SIZE\r
+CYDEV_CLKDIST_ACFG3_SIZE EQU 0x00000004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG0\r
+CYREG_CLKDIST_ACFG3_CFG0 EQU 0x4000410c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG1\r
+CYREG_CLKDIST_ACFG3_CFG1 EQU 0x4000410d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG2\r
+CYREG_CLKDIST_ACFG3_CFG2 EQU 0x4000410e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG3\r
+CYREG_CLKDIST_ACFG3_CFG3 EQU 0x4000410f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_BASE\r
+CYDEV_FASTCLK_BASE EQU 0x40004200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_SIZE\r
+CYDEV_FASTCLK_SIZE EQU 0x00000026\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_IMO_BASE\r
+CYDEV_FASTCLK_IMO_BASE EQU 0x40004200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_IMO_SIZE\r
+CYDEV_FASTCLK_IMO_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FASTCLK_IMO_CR\r
+CYREG_FASTCLK_IMO_CR EQU 0x40004200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_BASE\r
+CYDEV_FASTCLK_XMHZ_BASE EQU 0x40004210\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_SIZE\r
+CYDEV_FASTCLK_XMHZ_SIZE EQU 0x00000004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CSR\r
+CYREG_FASTCLK_XMHZ_CSR EQU 0x40004210\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CFG0\r
+CYREG_FASTCLK_XMHZ_CFG0 EQU 0x40004212\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CFG1\r
+CYREG_FASTCLK_XMHZ_CFG1 EQU 0x40004213\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_PLL_BASE\r
+CYDEV_FASTCLK_PLL_BASE EQU 0x40004220\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SIZE\r
+CYDEV_FASTCLK_PLL_SIZE EQU 0x00000006\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FASTCLK_PLL_CFG0\r
+CYREG_FASTCLK_PLL_CFG0 EQU 0x40004220\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FASTCLK_PLL_CFG1\r
+CYREG_FASTCLK_PLL_CFG1 EQU 0x40004221\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FASTCLK_PLL_P\r
+CYREG_FASTCLK_PLL_P EQU 0x40004222\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FASTCLK_PLL_Q\r
+CYREG_FASTCLK_PLL_Q EQU 0x40004223\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FASTCLK_PLL_SR\r
+CYREG_FASTCLK_PLL_SR EQU 0x40004225\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SLOWCLK_BASE\r
+CYDEV_SLOWCLK_BASE EQU 0x40004300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SLOWCLK_SIZE\r
+CYDEV_SLOWCLK_SIZE EQU 0x0000000b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_BASE\r
+CYDEV_SLOWCLK_ILO_BASE EQU 0x40004300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_SIZE\r
+CYDEV_SLOWCLK_ILO_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SLOWCLK_ILO_CR0\r
+CYREG_SLOWCLK_ILO_CR0 EQU 0x40004300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SLOWCLK_ILO_CR1\r
+CYREG_SLOWCLK_ILO_CR1 EQU 0x40004301\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SLOWCLK_X32_BASE\r
+CYDEV_SLOWCLK_X32_BASE EQU 0x40004308\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SLOWCLK_X32_SIZE\r
+CYDEV_SLOWCLK_X32_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SLOWCLK_X32_CR\r
+CYREG_SLOWCLK_X32_CR EQU 0x40004308\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SLOWCLK_X32_CFG\r
+CYREG_SLOWCLK_X32_CFG EQU 0x40004309\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SLOWCLK_X32_TST\r
+CYREG_SLOWCLK_X32_TST EQU 0x4000430a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_BOOST_BASE\r
+CYDEV_BOOST_BASE EQU 0x40004320\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_BOOST_SIZE\r
+CYDEV_BOOST_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BOOST_CR0\r
+CYREG_BOOST_CR0 EQU 0x40004320\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BOOST_CR1\r
+CYREG_BOOST_CR1 EQU 0x40004321\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BOOST_CR2\r
+CYREG_BOOST_CR2 EQU 0x40004322\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BOOST_CR3\r
+CYREG_BOOST_CR3 EQU 0x40004323\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BOOST_SR\r
+CYREG_BOOST_SR EQU 0x40004324\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BOOST_CR4\r
+CYREG_BOOST_CR4 EQU 0x40004325\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BOOST_SR2\r
+CYREG_BOOST_SR2 EQU 0x40004326\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PWRSYS_BASE\r
+CYDEV_PWRSYS_BASE EQU 0x40004330\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PWRSYS_SIZE\r
+CYDEV_PWRSYS_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PWRSYS_CR0\r
+CYREG_PWRSYS_CR0 EQU 0x40004330\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PWRSYS_CR1\r
+CYREG_PWRSYS_CR1 EQU 0x40004331\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_BASE\r
+CYDEV_PM_BASE EQU 0x40004380\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_SIZE\r
+CYDEV_PM_SIZE EQU 0x00000057\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_TW_CFG0\r
+CYREG_PM_TW_CFG0 EQU 0x40004380\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_TW_CFG1\r
+CYREG_PM_TW_CFG1 EQU 0x40004381\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_TW_CFG2\r
+CYREG_PM_TW_CFG2 EQU 0x40004382\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_WDT_CFG\r
+CYREG_PM_WDT_CFG EQU 0x40004383\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_WDT_CR\r
+CYREG_PM_WDT_CR EQU 0x40004384\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_INT_SR\r
+CYREG_PM_INT_SR EQU 0x40004390\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_MODE_CFG0\r
+CYREG_PM_MODE_CFG0 EQU 0x40004391\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_MODE_CFG1\r
+CYREG_PM_MODE_CFG1 EQU 0x40004392\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_MODE_CSR\r
+CYREG_PM_MODE_CSR EQU 0x40004393\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_USB_CR0\r
+CYREG_PM_USB_CR0 EQU 0x40004394\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG0\r
+CYREG_PM_WAKEUP_CFG0 EQU 0x40004398\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG1\r
+CYREG_PM_WAKEUP_CFG1 EQU 0x40004399\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG2\r
+CYREG_PM_WAKEUP_CFG2 EQU 0x4000439a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_ACT_BASE\r
+CYDEV_PM_ACT_BASE EQU 0x400043a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_ACT_SIZE\r
+CYDEV_PM_ACT_SIZE EQU 0x0000000e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_ACT_CFG0\r
+CYREG_PM_ACT_CFG0 EQU 0x400043a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_ACT_CFG1\r
+CYREG_PM_ACT_CFG1 EQU 0x400043a1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_ACT_CFG2\r
+CYREG_PM_ACT_CFG2 EQU 0x400043a2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_ACT_CFG3\r
+CYREG_PM_ACT_CFG3 EQU 0x400043a3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_ACT_CFG4\r
+CYREG_PM_ACT_CFG4 EQU 0x400043a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_ACT_CFG5\r
+CYREG_PM_ACT_CFG5 EQU 0x400043a5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_ACT_CFG6\r
+CYREG_PM_ACT_CFG6 EQU 0x400043a6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_ACT_CFG7\r
+CYREG_PM_ACT_CFG7 EQU 0x400043a7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_ACT_CFG8\r
+CYREG_PM_ACT_CFG8 EQU 0x400043a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_ACT_CFG9\r
+CYREG_PM_ACT_CFG9 EQU 0x400043a9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_ACT_CFG10\r
+CYREG_PM_ACT_CFG10 EQU 0x400043aa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_ACT_CFG11\r
+CYREG_PM_ACT_CFG11 EQU 0x400043ab\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_ACT_CFG12\r
+CYREG_PM_ACT_CFG12 EQU 0x400043ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_ACT_CFG13\r
+CYREG_PM_ACT_CFG13 EQU 0x400043ad\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_STBY_BASE\r
+CYDEV_PM_STBY_BASE EQU 0x400043b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_STBY_SIZE\r
+CYDEV_PM_STBY_SIZE EQU 0x0000000e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_STBY_CFG0\r
+CYREG_PM_STBY_CFG0 EQU 0x400043b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_STBY_CFG1\r
+CYREG_PM_STBY_CFG1 EQU 0x400043b1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_STBY_CFG2\r
+CYREG_PM_STBY_CFG2 EQU 0x400043b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_STBY_CFG3\r
+CYREG_PM_STBY_CFG3 EQU 0x400043b3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_STBY_CFG4\r
+CYREG_PM_STBY_CFG4 EQU 0x400043b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_STBY_CFG5\r
+CYREG_PM_STBY_CFG5 EQU 0x400043b5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_STBY_CFG6\r
+CYREG_PM_STBY_CFG6 EQU 0x400043b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_STBY_CFG7\r
+CYREG_PM_STBY_CFG7 EQU 0x400043b7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_STBY_CFG8\r
+CYREG_PM_STBY_CFG8 EQU 0x400043b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_STBY_CFG9\r
+CYREG_PM_STBY_CFG9 EQU 0x400043b9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_STBY_CFG10\r
+CYREG_PM_STBY_CFG10 EQU 0x400043ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_STBY_CFG11\r
+CYREG_PM_STBY_CFG11 EQU 0x400043bb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_STBY_CFG12\r
+CYREG_PM_STBY_CFG12 EQU 0x400043bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_STBY_CFG13\r
+CYREG_PM_STBY_CFG13 EQU 0x400043bd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_AVAIL_BASE\r
+CYDEV_PM_AVAIL_BASE EQU 0x400043c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PM_AVAIL_SIZE\r
+CYDEV_PM_AVAIL_SIZE EQU 0x00000017\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_AVAIL_CR0\r
+CYREG_PM_AVAIL_CR0 EQU 0x400043c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_AVAIL_CR1\r
+CYREG_PM_AVAIL_CR1 EQU 0x400043c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_AVAIL_CR2\r
+CYREG_PM_AVAIL_CR2 EQU 0x400043c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_AVAIL_CR3\r
+CYREG_PM_AVAIL_CR3 EQU 0x400043c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_AVAIL_CR4\r
+CYREG_PM_AVAIL_CR4 EQU 0x400043c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_AVAIL_CR5\r
+CYREG_PM_AVAIL_CR5 EQU 0x400043c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_AVAIL_CR6\r
+CYREG_PM_AVAIL_CR6 EQU 0x400043c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_AVAIL_SR0\r
+CYREG_PM_AVAIL_SR0 EQU 0x400043d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_AVAIL_SR1\r
+CYREG_PM_AVAIL_SR1 EQU 0x400043d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_AVAIL_SR2\r
+CYREG_PM_AVAIL_SR2 EQU 0x400043d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_AVAIL_SR3\r
+CYREG_PM_AVAIL_SR3 EQU 0x400043d3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_AVAIL_SR4\r
+CYREG_PM_AVAIL_SR4 EQU 0x400043d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_AVAIL_SR5\r
+CYREG_PM_AVAIL_SR5 EQU 0x400043d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PM_AVAIL_SR6\r
+CYREG_PM_AVAIL_SR6 EQU 0x400043d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_BASE\r
+CYDEV_PICU_BASE EQU 0x40004500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SIZE\r
+CYDEV_PICU_SIZE EQU 0x000000b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_BASE\r
+CYDEV_PICU_INTTYPE_BASE EQU 0x40004500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_SIZE\r
+CYDEV_PICU_INTTYPE_SIZE EQU 0x00000080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_BASE\r
+CYDEV_PICU_INTTYPE_PICU0_BASE EQU 0x40004500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_SIZE\r
+CYDEV_PICU_INTTYPE_PICU0_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU0_INTTYPE0\r
+CYREG_PICU0_INTTYPE0 EQU 0x40004500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU0_INTTYPE1\r
+CYREG_PICU0_INTTYPE1 EQU 0x40004501\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU0_INTTYPE2\r
+CYREG_PICU0_INTTYPE2 EQU 0x40004502\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU0_INTTYPE3\r
+CYREG_PICU0_INTTYPE3 EQU 0x40004503\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU0_INTTYPE4\r
+CYREG_PICU0_INTTYPE4 EQU 0x40004504\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU0_INTTYPE5\r
+CYREG_PICU0_INTTYPE5 EQU 0x40004505\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU0_INTTYPE6\r
+CYREG_PICU0_INTTYPE6 EQU 0x40004506\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU0_INTTYPE7\r
+CYREG_PICU0_INTTYPE7 EQU 0x40004507\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_BASE\r
+CYDEV_PICU_INTTYPE_PICU1_BASE EQU 0x40004508\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_SIZE\r
+CYDEV_PICU_INTTYPE_PICU1_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU1_INTTYPE0\r
+CYREG_PICU1_INTTYPE0 EQU 0x40004508\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU1_INTTYPE1\r
+CYREG_PICU1_INTTYPE1 EQU 0x40004509\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU1_INTTYPE2\r
+CYREG_PICU1_INTTYPE2 EQU 0x4000450a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU1_INTTYPE3\r
+CYREG_PICU1_INTTYPE3 EQU 0x4000450b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU1_INTTYPE4\r
+CYREG_PICU1_INTTYPE4 EQU 0x4000450c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU1_INTTYPE5\r
+CYREG_PICU1_INTTYPE5 EQU 0x4000450d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU1_INTTYPE6\r
+CYREG_PICU1_INTTYPE6 EQU 0x4000450e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU1_INTTYPE7\r
+CYREG_PICU1_INTTYPE7 EQU 0x4000450f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_BASE\r
+CYDEV_PICU_INTTYPE_PICU2_BASE EQU 0x40004510\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_SIZE\r
+CYDEV_PICU_INTTYPE_PICU2_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU2_INTTYPE0\r
+CYREG_PICU2_INTTYPE0 EQU 0x40004510\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU2_INTTYPE1\r
+CYREG_PICU2_INTTYPE1 EQU 0x40004511\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU2_INTTYPE2\r
+CYREG_PICU2_INTTYPE2 EQU 0x40004512\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU2_INTTYPE3\r
+CYREG_PICU2_INTTYPE3 EQU 0x40004513\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU2_INTTYPE4\r
+CYREG_PICU2_INTTYPE4 EQU 0x40004514\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU2_INTTYPE5\r
+CYREG_PICU2_INTTYPE5 EQU 0x40004515\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU2_INTTYPE6\r
+CYREG_PICU2_INTTYPE6 EQU 0x40004516\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU2_INTTYPE7\r
+CYREG_PICU2_INTTYPE7 EQU 0x40004517\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_BASE\r
+CYDEV_PICU_INTTYPE_PICU3_BASE EQU 0x40004518\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_SIZE\r
+CYDEV_PICU_INTTYPE_PICU3_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU3_INTTYPE0\r
+CYREG_PICU3_INTTYPE0 EQU 0x40004518\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU3_INTTYPE1\r
+CYREG_PICU3_INTTYPE1 EQU 0x40004519\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU3_INTTYPE2\r
+CYREG_PICU3_INTTYPE2 EQU 0x4000451a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU3_INTTYPE3\r
+CYREG_PICU3_INTTYPE3 EQU 0x4000451b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU3_INTTYPE4\r
+CYREG_PICU3_INTTYPE4 EQU 0x4000451c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU3_INTTYPE5\r
+CYREG_PICU3_INTTYPE5 EQU 0x4000451d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU3_INTTYPE6\r
+CYREG_PICU3_INTTYPE6 EQU 0x4000451e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU3_INTTYPE7\r
+CYREG_PICU3_INTTYPE7 EQU 0x4000451f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_BASE\r
+CYDEV_PICU_INTTYPE_PICU4_BASE EQU 0x40004520\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_SIZE\r
+CYDEV_PICU_INTTYPE_PICU4_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU4_INTTYPE0\r
+CYREG_PICU4_INTTYPE0 EQU 0x40004520\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU4_INTTYPE1\r
+CYREG_PICU4_INTTYPE1 EQU 0x40004521\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU4_INTTYPE2\r
+CYREG_PICU4_INTTYPE2 EQU 0x40004522\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU4_INTTYPE3\r
+CYREG_PICU4_INTTYPE3 EQU 0x40004523\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU4_INTTYPE4\r
+CYREG_PICU4_INTTYPE4 EQU 0x40004524\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU4_INTTYPE5\r
+CYREG_PICU4_INTTYPE5 EQU 0x40004525\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU4_INTTYPE6\r
+CYREG_PICU4_INTTYPE6 EQU 0x40004526\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU4_INTTYPE7\r
+CYREG_PICU4_INTTYPE7 EQU 0x40004527\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_BASE\r
+CYDEV_PICU_INTTYPE_PICU5_BASE EQU 0x40004528\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_SIZE\r
+CYDEV_PICU_INTTYPE_PICU5_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU5_INTTYPE0\r
+CYREG_PICU5_INTTYPE0 EQU 0x40004528\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU5_INTTYPE1\r
+CYREG_PICU5_INTTYPE1 EQU 0x40004529\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU5_INTTYPE2\r
+CYREG_PICU5_INTTYPE2 EQU 0x4000452a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU5_INTTYPE3\r
+CYREG_PICU5_INTTYPE3 EQU 0x4000452b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU5_INTTYPE4\r
+CYREG_PICU5_INTTYPE4 EQU 0x4000452c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU5_INTTYPE5\r
+CYREG_PICU5_INTTYPE5 EQU 0x4000452d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU5_INTTYPE6\r
+CYREG_PICU5_INTTYPE6 EQU 0x4000452e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU5_INTTYPE7\r
+CYREG_PICU5_INTTYPE7 EQU 0x4000452f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_BASE\r
+CYDEV_PICU_INTTYPE_PICU6_BASE EQU 0x40004530\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_SIZE\r
+CYDEV_PICU_INTTYPE_PICU6_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU6_INTTYPE0\r
+CYREG_PICU6_INTTYPE0 EQU 0x40004530\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU6_INTTYPE1\r
+CYREG_PICU6_INTTYPE1 EQU 0x40004531\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU6_INTTYPE2\r
+CYREG_PICU6_INTTYPE2 EQU 0x40004532\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU6_INTTYPE3\r
+CYREG_PICU6_INTTYPE3 EQU 0x40004533\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU6_INTTYPE4\r
+CYREG_PICU6_INTTYPE4 EQU 0x40004534\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU6_INTTYPE5\r
+CYREG_PICU6_INTTYPE5 EQU 0x40004535\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU6_INTTYPE6\r
+CYREG_PICU6_INTTYPE6 EQU 0x40004536\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU6_INTTYPE7\r
+CYREG_PICU6_INTTYPE7 EQU 0x40004537\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_BASE\r
+CYDEV_PICU_INTTYPE_PICU12_BASE EQU 0x40004560\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_SIZE\r
+CYDEV_PICU_INTTYPE_PICU12_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU12_INTTYPE0\r
+CYREG_PICU12_INTTYPE0 EQU 0x40004560\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU12_INTTYPE1\r
+CYREG_PICU12_INTTYPE1 EQU 0x40004561\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU12_INTTYPE2\r
+CYREG_PICU12_INTTYPE2 EQU 0x40004562\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU12_INTTYPE3\r
+CYREG_PICU12_INTTYPE3 EQU 0x40004563\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU12_INTTYPE4\r
+CYREG_PICU12_INTTYPE4 EQU 0x40004564\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU12_INTTYPE5\r
+CYREG_PICU12_INTTYPE5 EQU 0x40004565\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU12_INTTYPE6\r
+CYREG_PICU12_INTTYPE6 EQU 0x40004566\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU12_INTTYPE7\r
+CYREG_PICU12_INTTYPE7 EQU 0x40004567\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_BASE\r
+CYDEV_PICU_INTTYPE_PICU15_BASE EQU 0x40004578\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_SIZE\r
+CYDEV_PICU_INTTYPE_PICU15_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU15_INTTYPE0\r
+CYREG_PICU15_INTTYPE0 EQU 0x40004578\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU15_INTTYPE1\r
+CYREG_PICU15_INTTYPE1 EQU 0x40004579\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU15_INTTYPE2\r
+CYREG_PICU15_INTTYPE2 EQU 0x4000457a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU15_INTTYPE3\r
+CYREG_PICU15_INTTYPE3 EQU 0x4000457b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU15_INTTYPE4\r
+CYREG_PICU15_INTTYPE4 EQU 0x4000457c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU15_INTTYPE5\r
+CYREG_PICU15_INTTYPE5 EQU 0x4000457d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU15_INTTYPE6\r
+CYREG_PICU15_INTTYPE6 EQU 0x4000457e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU15_INTTYPE7\r
+CYREG_PICU15_INTTYPE7 EQU 0x4000457f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_BASE\r
+CYDEV_PICU_STAT_BASE EQU 0x40004580\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_SIZE\r
+CYDEV_PICU_STAT_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_BASE\r
+CYDEV_PICU_STAT_PICU0_BASE EQU 0x40004580\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_SIZE\r
+CYDEV_PICU_STAT_PICU0_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU0_INTSTAT\r
+CYREG_PICU0_INTSTAT EQU 0x40004580\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_BASE\r
+CYDEV_PICU_STAT_PICU1_BASE EQU 0x40004581\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_SIZE\r
+CYDEV_PICU_STAT_PICU1_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU1_INTSTAT\r
+CYREG_PICU1_INTSTAT EQU 0x40004581\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_BASE\r
+CYDEV_PICU_STAT_PICU2_BASE EQU 0x40004582\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_SIZE\r
+CYDEV_PICU_STAT_PICU2_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU2_INTSTAT\r
+CYREG_PICU2_INTSTAT EQU 0x40004582\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_BASE\r
+CYDEV_PICU_STAT_PICU3_BASE EQU 0x40004583\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_SIZE\r
+CYDEV_PICU_STAT_PICU3_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU3_INTSTAT\r
+CYREG_PICU3_INTSTAT EQU 0x40004583\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_BASE\r
+CYDEV_PICU_STAT_PICU4_BASE EQU 0x40004584\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_SIZE\r
+CYDEV_PICU_STAT_PICU4_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU4_INTSTAT\r
+CYREG_PICU4_INTSTAT EQU 0x40004584\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_BASE\r
+CYDEV_PICU_STAT_PICU5_BASE EQU 0x40004585\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_SIZE\r
+CYDEV_PICU_STAT_PICU5_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU5_INTSTAT\r
+CYREG_PICU5_INTSTAT EQU 0x40004585\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_BASE\r
+CYDEV_PICU_STAT_PICU6_BASE EQU 0x40004586\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_SIZE\r
+CYDEV_PICU_STAT_PICU6_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU6_INTSTAT\r
+CYREG_PICU6_INTSTAT EQU 0x40004586\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_BASE\r
+CYDEV_PICU_STAT_PICU12_BASE EQU 0x4000458c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_SIZE\r
+CYDEV_PICU_STAT_PICU12_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU12_INTSTAT\r
+CYREG_PICU12_INTSTAT EQU 0x4000458c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_BASE\r
+CYDEV_PICU_STAT_PICU15_BASE EQU 0x4000458f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_SIZE\r
+CYDEV_PICU_STAT_PICU15_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU15_INTSTAT\r
+CYREG_PICU15_INTSTAT EQU 0x4000458f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_BASE\r
+CYDEV_PICU_SNAP_BASE EQU 0x40004590\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_SIZE\r
+CYDEV_PICU_SNAP_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_BASE\r
+CYDEV_PICU_SNAP_PICU0_BASE EQU 0x40004590\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SIZE\r
+CYDEV_PICU_SNAP_PICU0_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU0_SNAP\r
+CYREG_PICU0_SNAP EQU 0x40004590\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_BASE\r
+CYDEV_PICU_SNAP_PICU1_BASE EQU 0x40004591\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SIZE\r
+CYDEV_PICU_SNAP_PICU1_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU1_SNAP\r
+CYREG_PICU1_SNAP EQU 0x40004591\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_BASE\r
+CYDEV_PICU_SNAP_PICU2_BASE EQU 0x40004592\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SIZE\r
+CYDEV_PICU_SNAP_PICU2_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU2_SNAP\r
+CYREG_PICU2_SNAP EQU 0x40004592\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_BASE\r
+CYDEV_PICU_SNAP_PICU3_BASE EQU 0x40004593\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SIZE\r
+CYDEV_PICU_SNAP_PICU3_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU3_SNAP\r
+CYREG_PICU3_SNAP EQU 0x40004593\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_BASE\r
+CYDEV_PICU_SNAP_PICU4_BASE EQU 0x40004594\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SIZE\r
+CYDEV_PICU_SNAP_PICU4_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU4_SNAP\r
+CYREG_PICU4_SNAP EQU 0x40004594\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_BASE\r
+CYDEV_PICU_SNAP_PICU5_BASE EQU 0x40004595\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SIZE\r
+CYDEV_PICU_SNAP_PICU5_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU5_SNAP\r
+CYREG_PICU5_SNAP EQU 0x40004595\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_BASE\r
+CYDEV_PICU_SNAP_PICU6_BASE EQU 0x40004596\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SIZE\r
+CYDEV_PICU_SNAP_PICU6_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU6_SNAP\r
+CYREG_PICU6_SNAP EQU 0x40004596\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_BASE\r
+CYDEV_PICU_SNAP_PICU12_BASE EQU 0x4000459c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SIZE\r
+CYDEV_PICU_SNAP_PICU12_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU12_SNAP\r
+CYREG_PICU12_SNAP EQU 0x4000459c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_BASE\r
+CYDEV_PICU_SNAP_PICU_15_BASE EQU 0x4000459f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SIZE\r
+CYDEV_PICU_SNAP_PICU_15_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU_15_SNAP_15\r
+CYREG_PICU_15_SNAP_15 EQU 0x4000459f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_BASE\r
+CYDEV_PICU_DISABLE_COR_BASE EQU 0x400045a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_SIZE\r
+CYDEV_PICU_DISABLE_COR_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_BASE\r
+CYDEV_PICU_DISABLE_COR_PICU0_BASE EQU 0x400045a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_SIZE\r
+CYDEV_PICU_DISABLE_COR_PICU0_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU0_DISABLE_COR\r
+CYREG_PICU0_DISABLE_COR EQU 0x400045a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_BASE\r
+CYDEV_PICU_DISABLE_COR_PICU1_BASE EQU 0x400045a1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_SIZE\r
+CYDEV_PICU_DISABLE_COR_PICU1_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU1_DISABLE_COR\r
+CYREG_PICU1_DISABLE_COR EQU 0x400045a1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_BASE\r
+CYDEV_PICU_DISABLE_COR_PICU2_BASE EQU 0x400045a2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_SIZE\r
+CYDEV_PICU_DISABLE_COR_PICU2_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU2_DISABLE_COR\r
+CYREG_PICU2_DISABLE_COR EQU 0x400045a2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_BASE\r
+CYDEV_PICU_DISABLE_COR_PICU3_BASE EQU 0x400045a3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_SIZE\r
+CYDEV_PICU_DISABLE_COR_PICU3_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU3_DISABLE_COR\r
+CYREG_PICU3_DISABLE_COR EQU 0x400045a3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_BASE\r
+CYDEV_PICU_DISABLE_COR_PICU4_BASE EQU 0x400045a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_SIZE\r
+CYDEV_PICU_DISABLE_COR_PICU4_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU4_DISABLE_COR\r
+CYREG_PICU4_DISABLE_COR EQU 0x400045a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_BASE\r
+CYDEV_PICU_DISABLE_COR_PICU5_BASE EQU 0x400045a5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_SIZE\r
+CYDEV_PICU_DISABLE_COR_PICU5_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU5_DISABLE_COR\r
+CYREG_PICU5_DISABLE_COR EQU 0x400045a5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_BASE\r
+CYDEV_PICU_DISABLE_COR_PICU6_BASE EQU 0x400045a6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_SIZE\r
+CYDEV_PICU_DISABLE_COR_PICU6_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU6_DISABLE_COR\r
+CYREG_PICU6_DISABLE_COR EQU 0x400045a6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_BASE\r
+CYDEV_PICU_DISABLE_COR_PICU12_BASE EQU 0x400045ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_SIZE\r
+CYDEV_PICU_DISABLE_COR_PICU12_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU12_DISABLE_COR\r
+CYREG_PICU12_DISABLE_COR EQU 0x400045ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_BASE\r
+CYDEV_PICU_DISABLE_COR_PICU15_BASE EQU 0x400045af\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_SIZE\r
+CYDEV_PICU_DISABLE_COR_PICU15_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PICU15_DISABLE_COR\r
+CYREG_PICU15_DISABLE_COR EQU 0x400045af\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_BASE\r
+CYDEV_MFGCFG_BASE EQU 0x40004600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_SIZE\r
+CYDEV_MFGCFG_SIZE EQU 0x000000ed\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_BASE\r
+CYDEV_MFGCFG_ANAIF_BASE EQU 0x40004600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SIZE\r
+CYDEV_MFGCFG_ANAIF_SIZE EQU 0x00000038\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_BASE\r
+CYDEV_MFGCFG_ANAIF_DAC0_BASE EQU 0x40004608\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_SIZE\r
+CYDEV_MFGCFG_ANAIF_DAC0_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC0_TR\r
+CYREG_DAC0_TR EQU 0x40004608\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_BASE\r
+CYDEV_MFGCFG_ANAIF_DAC1_BASE EQU 0x40004609\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_SIZE\r
+CYDEV_MFGCFG_ANAIF_DAC1_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC1_TR\r
+CYREG_DAC1_TR EQU 0x40004609\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_BASE\r
+CYDEV_MFGCFG_ANAIF_DAC2_BASE EQU 0x4000460a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_SIZE\r
+CYDEV_MFGCFG_ANAIF_DAC2_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC2_TR\r
+CYREG_DAC2_TR EQU 0x4000460a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_BASE\r
+CYDEV_MFGCFG_ANAIF_DAC3_BASE EQU 0x4000460b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_SIZE\r
+CYDEV_MFGCFG_ANAIF_DAC3_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC3_TR\r
+CYREG_DAC3_TR EQU 0x4000460b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE\r
+CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE EQU 0x40004610\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE\r
+CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NPUMP_DSM_TR0\r
+CYREG_NPUMP_DSM_TR0 EQU 0x40004610\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE\r
+CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE EQU 0x40004611\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE\r
+CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NPUMP_SC_TR0\r
+CYREG_NPUMP_SC_TR0 EQU 0x40004611\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE\r
+CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE EQU 0x40004612\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE\r
+CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NPUMP_OPAMP_TR0\r
+CYREG_NPUMP_OPAMP_TR0 EQU 0x40004612\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_BASE\r
+CYDEV_MFGCFG_ANAIF_SAR0_BASE EQU 0x40004614\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_SIZE\r
+CYDEV_MFGCFG_ANAIF_SAR0_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR0_TR0\r
+CYREG_SAR0_TR0 EQU 0x40004614\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_BASE\r
+CYDEV_MFGCFG_ANAIF_SAR1_BASE EQU 0x40004616\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_SIZE\r
+CYDEV_MFGCFG_ANAIF_SAR1_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR1_TR0\r
+CYREG_SAR1_TR0 EQU 0x40004616\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_BASE\r
+CYDEV_MFGCFG_ANAIF_OPAMP0_BASE EQU 0x40004620\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE\r
+CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP0_TR0\r
+CYREG_OPAMP0_TR0 EQU 0x40004620\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP0_TR1\r
+CYREG_OPAMP0_TR1 EQU 0x40004621\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_BASE\r
+CYDEV_MFGCFG_ANAIF_OPAMP1_BASE EQU 0x40004622\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE\r
+CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP1_TR0\r
+CYREG_OPAMP1_TR0 EQU 0x40004622\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP1_TR1\r
+CYREG_OPAMP1_TR1 EQU 0x40004623\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_BASE\r
+CYDEV_MFGCFG_ANAIF_OPAMP2_BASE EQU 0x40004624\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE\r
+CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP2_TR0\r
+CYREG_OPAMP2_TR0 EQU 0x40004624\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP2_TR1\r
+CYREG_OPAMP2_TR1 EQU 0x40004625\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_BASE\r
+CYDEV_MFGCFG_ANAIF_OPAMP3_BASE EQU 0x40004626\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE\r
+CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP3_TR0\r
+CYREG_OPAMP3_TR0 EQU 0x40004626\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP3_TR1\r
+CYREG_OPAMP3_TR1 EQU 0x40004627\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_BASE\r
+CYDEV_MFGCFG_ANAIF_CMP0_BASE EQU 0x40004630\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_SIZE\r
+CYDEV_MFGCFG_ANAIF_CMP0_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP0_TR0\r
+CYREG_CMP0_TR0 EQU 0x40004630\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP0_TR1\r
+CYREG_CMP0_TR1 EQU 0x40004631\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_BASE\r
+CYDEV_MFGCFG_ANAIF_CMP1_BASE EQU 0x40004632\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_SIZE\r
+CYDEV_MFGCFG_ANAIF_CMP1_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP1_TR0\r
+CYREG_CMP1_TR0 EQU 0x40004632\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP1_TR1\r
+CYREG_CMP1_TR1 EQU 0x40004633\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_BASE\r
+CYDEV_MFGCFG_ANAIF_CMP2_BASE EQU 0x40004634\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_SIZE\r
+CYDEV_MFGCFG_ANAIF_CMP2_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP2_TR0\r
+CYREG_CMP2_TR0 EQU 0x40004634\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP2_TR1\r
+CYREG_CMP2_TR1 EQU 0x40004635\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_BASE\r
+CYDEV_MFGCFG_ANAIF_CMP3_BASE EQU 0x40004636\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_SIZE\r
+CYDEV_MFGCFG_ANAIF_CMP3_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP3_TR0\r
+CYREG_CMP3_TR0 EQU 0x40004636\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP3_TR1\r
+CYREG_CMP3_TR1 EQU 0x40004637\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BASE\r
+CYDEV_MFGCFG_PWRSYS_BASE EQU 0x40004680\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SIZE\r
+CYDEV_MFGCFG_PWRSYS_SIZE EQU 0x0000000b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PWRSYS_HIB_TR0\r
+CYREG_PWRSYS_HIB_TR0 EQU 0x40004680\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PWRSYS_HIB_TR1\r
+CYREG_PWRSYS_HIB_TR1 EQU 0x40004681\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PWRSYS_I2C_TR\r
+CYREG_PWRSYS_I2C_TR EQU 0x40004682\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PWRSYS_SLP_TR\r
+CYREG_PWRSYS_SLP_TR EQU 0x40004683\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PWRSYS_BUZZ_TR\r
+CYREG_PWRSYS_BUZZ_TR EQU 0x40004684\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR0\r
+CYREG_PWRSYS_WAKE_TR0 EQU 0x40004685\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR1\r
+CYREG_PWRSYS_WAKE_TR1 EQU 0x40004686\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PWRSYS_BREF_TR\r
+CYREG_PWRSYS_BREF_TR EQU 0x40004687\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PWRSYS_BG_TR\r
+CYREG_PWRSYS_BG_TR EQU 0x40004688\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR2\r
+CYREG_PWRSYS_WAKE_TR2 EQU 0x40004689\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR3\r
+CYREG_PWRSYS_WAKE_TR3 EQU 0x4000468a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ILO_BASE\r
+CYDEV_MFGCFG_ILO_BASE EQU 0x40004690\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_ILO_SIZE\r
+CYDEV_MFGCFG_ILO_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ILO_TR0\r
+CYREG_ILO_TR0 EQU 0x40004690\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ILO_TR1\r
+CYREG_ILO_TR1 EQU 0x40004691\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_X32_BASE\r
+CYDEV_MFGCFG_X32_BASE EQU 0x40004698\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_X32_SIZE\r
+CYDEV_MFGCFG_X32_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_X32_TR\r
+CYREG_X32_TR EQU 0x40004698\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_IMO_BASE\r
+CYDEV_MFGCFG_IMO_BASE EQU 0x400046a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_IMO_SIZE\r
+CYDEV_MFGCFG_IMO_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IMO_TR0\r
+CYREG_IMO_TR0 EQU 0x400046a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IMO_TR1\r
+CYREG_IMO_TR1 EQU 0x400046a1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IMO_GAIN\r
+CYREG_IMO_GAIN EQU 0x400046a2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IMO_C36M\r
+CYREG_IMO_C36M EQU 0x400046a3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IMO_TR2\r
+CYREG_IMO_TR2 EQU 0x400046a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_BASE\r
+CYDEV_MFGCFG_XMHZ_BASE EQU 0x400046a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_SIZE\r
+CYDEV_MFGCFG_XMHZ_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_XMHZ_TR\r
+CYREG_XMHZ_TR EQU 0x400046a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_MFGCFG_DLY\r
+CYREG_MFGCFG_DLY EQU 0x400046c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_BASE\r
+CYDEV_MFGCFG_MLOGIC_BASE EQU 0x400046e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SIZE\r
+CYDEV_MFGCFG_MLOGIC_SIZE EQU 0x0000000d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_MLOGIC_DMPSTR\r
+CYREG_MLOGIC_DMPSTR EQU 0x400046e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_BASE\r
+CYDEV_MFGCFG_MLOGIC_SEG_BASE EQU 0x400046e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_SIZE\r
+CYDEV_MFGCFG_MLOGIC_SEG_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_MLOGIC_SEG_CR\r
+CYREG_MLOGIC_SEG_CR EQU 0x400046e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_MLOGIC_SEG_CFG0\r
+CYREG_MLOGIC_SEG_CFG0 EQU 0x400046e5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_MLOGIC_DEBUG\r
+CYREG_MLOGIC_DEBUG EQU 0x400046e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE\r
+CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE EQU 0x400046ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE\r
+CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_MLOGIC_CPU_SCR_CPU_SCR\r
+CYREG_MLOGIC_CPU_SCR_CPU_SCR EQU 0x400046ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_MLOGIC_REV_ID\r
+CYREG_MLOGIC_REV_ID EQU 0x400046ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_RESET_BASE\r
+CYDEV_RESET_BASE EQU 0x400046f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_RESET_SIZE\r
+CYDEV_RESET_SIZE EQU 0x0000000f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_RESET_IPOR_CR0\r
+CYREG_RESET_IPOR_CR0 EQU 0x400046f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_RESET_IPOR_CR1\r
+CYREG_RESET_IPOR_CR1 EQU 0x400046f1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_RESET_IPOR_CR2\r
+CYREG_RESET_IPOR_CR2 EQU 0x400046f2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_RESET_IPOR_CR3\r
+CYREG_RESET_IPOR_CR3 EQU 0x400046f3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_RESET_CR0\r
+CYREG_RESET_CR0 EQU 0x400046f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_RESET_CR1\r
+CYREG_RESET_CR1 EQU 0x400046f5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_RESET_CR2\r
+CYREG_RESET_CR2 EQU 0x400046f6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_RESET_CR3\r
+CYREG_RESET_CR3 EQU 0x400046f7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_RESET_CR4\r
+CYREG_RESET_CR4 EQU 0x400046f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_RESET_CR5\r
+CYREG_RESET_CR5 EQU 0x400046f9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_RESET_SR0\r
+CYREG_RESET_SR0 EQU 0x400046fa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_RESET_SR1\r
+CYREG_RESET_SR1 EQU 0x400046fb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_RESET_SR2\r
+CYREG_RESET_SR2 EQU 0x400046fc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_RESET_SR3\r
+CYREG_RESET_SR3 EQU 0x400046fd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_RESET_TR\r
+CYREG_RESET_TR EQU 0x400046fe\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SPC_BASE\r
+CYDEV_SPC_BASE EQU 0x40004700\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SPC_SIZE\r
+CYDEV_SPC_SIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SPC_FM_EE_CR\r
+CYREG_SPC_FM_EE_CR EQU 0x40004700\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SPC_FM_EE_WAKE_CNT\r
+CYREG_SPC_FM_EE_WAKE_CNT EQU 0x40004701\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SPC_EE_SCR\r
+CYREG_SPC_EE_SCR EQU 0x40004702\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SPC_EE_ERR\r
+CYREG_SPC_EE_ERR EQU 0x40004703\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SPC_CPU_DATA\r
+CYREG_SPC_CPU_DATA EQU 0x40004720\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SPC_DMA_DATA\r
+CYREG_SPC_DMA_DATA EQU 0x40004721\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SPC_SR\r
+CYREG_SPC_SR EQU 0x40004722\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SPC_CR\r
+CYREG_SPC_CR EQU 0x40004723\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_BASE\r
+CYDEV_SPC_DMM_MAP_BASE EQU 0x40004780\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SIZE\r
+CYDEV_SPC_DMM_MAP_SIZE EQU 0x00000080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SPC_DMM_MAP_SRAM_MBASE\r
+CYREG_SPC_DMM_MAP_SRAM_MBASE EQU 0x40004780\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SPC_DMM_MAP_SRAM_MSIZE\r
+CYREG_SPC_DMM_MAP_SRAM_MSIZE EQU 0x00000080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CACHE_BASE\r
+CYDEV_CACHE_BASE EQU 0x40004800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CACHE_SIZE\r
+CYDEV_CACHE_SIZE EQU 0x0000009c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CACHE_CC_CTL\r
+CYREG_CACHE_CC_CTL EQU 0x40004800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CACHE_ECC_CORR\r
+CYREG_CACHE_ECC_CORR EQU 0x40004880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CACHE_ECC_ERR\r
+CYREG_CACHE_ECC_ERR EQU 0x40004888\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CACHE_FLASH_ERR\r
+CYREG_CACHE_FLASH_ERR EQU 0x40004890\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CACHE_HITMISS\r
+CYREG_CACHE_HITMISS EQU 0x40004898\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_I2C_BASE\r
+CYDEV_I2C_BASE EQU 0x40004900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_I2C_SIZE\r
+CYDEV_I2C_SIZE EQU 0x000000e1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_I2C_XCFG\r
+CYREG_I2C_XCFG EQU 0x400049c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_I2C_ADR\r
+CYREG_I2C_ADR EQU 0x400049ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_I2C_CFG\r
+CYREG_I2C_CFG EQU 0x400049d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_I2C_CSR\r
+CYREG_I2C_CSR EQU 0x400049d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_I2C_D\r
+CYREG_I2C_D EQU 0x400049d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_I2C_MCSR\r
+CYREG_I2C_MCSR EQU 0x400049d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_I2C_CLK_DIV1\r
+CYREG_I2C_CLK_DIV1 EQU 0x400049db\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_I2C_CLK_DIV2\r
+CYREG_I2C_CLK_DIV2 EQU 0x400049dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_I2C_TMOUT_CSR\r
+CYREG_I2C_TMOUT_CSR EQU 0x400049dd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_I2C_TMOUT_SR\r
+CYREG_I2C_TMOUT_SR EQU 0x400049de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_I2C_TMOUT_CFG0\r
+CYREG_I2C_TMOUT_CFG0 EQU 0x400049df\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_I2C_TMOUT_CFG1\r
+CYREG_I2C_TMOUT_CFG1 EQU 0x400049e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_BASE\r
+CYDEV_DEC_BASE EQU 0x40004e00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DEC_SIZE\r
+CYDEV_DEC_SIZE EQU 0x00000015\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DEC_CR\r
+CYREG_DEC_CR EQU 0x40004e00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DEC_SR\r
+CYREG_DEC_SR EQU 0x40004e01\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DEC_SHIFT1\r
+CYREG_DEC_SHIFT1 EQU 0x40004e02\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DEC_SHIFT2\r
+CYREG_DEC_SHIFT2 EQU 0x40004e03\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DEC_DR2\r
+CYREG_DEC_DR2 EQU 0x40004e04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DEC_DR2H\r
+CYREG_DEC_DR2H EQU 0x40004e05\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DEC_DR1\r
+CYREG_DEC_DR1 EQU 0x40004e06\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DEC_OCOR\r
+CYREG_DEC_OCOR EQU 0x40004e08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DEC_OCORM\r
+CYREG_DEC_OCORM EQU 0x40004e09\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DEC_OCORH\r
+CYREG_DEC_OCORH EQU 0x40004e0a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DEC_GCOR\r
+CYREG_DEC_GCOR EQU 0x40004e0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DEC_GCORH\r
+CYREG_DEC_GCORH EQU 0x40004e0d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DEC_GVAL\r
+CYREG_DEC_GVAL EQU 0x40004e0e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DEC_OUTSAMP\r
+CYREG_DEC_OUTSAMP EQU 0x40004e10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DEC_OUTSAMPM\r
+CYREG_DEC_OUTSAMPM EQU 0x40004e11\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DEC_OUTSAMPH\r
+CYREG_DEC_OUTSAMPH EQU 0x40004e12\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DEC_OUTSAMPS\r
+CYREG_DEC_OUTSAMPS EQU 0x40004e13\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DEC_COHER\r
+CYREG_DEC_COHER EQU 0x40004e14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR0_BASE\r
+CYDEV_TMR0_BASE EQU 0x40004f00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR0_SIZE\r
+CYDEV_TMR0_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR0_CFG0\r
+CYREG_TMR0_CFG0 EQU 0x40004f00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR0_CFG1\r
+CYREG_TMR0_CFG1 EQU 0x40004f01\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR0_CFG2\r
+CYREG_TMR0_CFG2 EQU 0x40004f02\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR0_SR0\r
+CYREG_TMR0_SR0 EQU 0x40004f03\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR0_PER0\r
+CYREG_TMR0_PER0 EQU 0x40004f04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR0_PER1\r
+CYREG_TMR0_PER1 EQU 0x40004f05\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR0_CNT_CMP0\r
+CYREG_TMR0_CNT_CMP0 EQU 0x40004f06\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR0_CNT_CMP1\r
+CYREG_TMR0_CNT_CMP1 EQU 0x40004f07\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR0_CAP0\r
+CYREG_TMR0_CAP0 EQU 0x40004f08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR0_CAP1\r
+CYREG_TMR0_CAP1 EQU 0x40004f09\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR0_RT0\r
+CYREG_TMR0_RT0 EQU 0x40004f0a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR0_RT1\r
+CYREG_TMR0_RT1 EQU 0x40004f0b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR1_BASE\r
+CYDEV_TMR1_BASE EQU 0x40004f0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR1_SIZE\r
+CYDEV_TMR1_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR1_CFG0\r
+CYREG_TMR1_CFG0 EQU 0x40004f0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR1_CFG1\r
+CYREG_TMR1_CFG1 EQU 0x40004f0d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR1_CFG2\r
+CYREG_TMR1_CFG2 EQU 0x40004f0e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR1_SR0\r
+CYREG_TMR1_SR0 EQU 0x40004f0f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR1_PER0\r
+CYREG_TMR1_PER0 EQU 0x40004f10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR1_PER1\r
+CYREG_TMR1_PER1 EQU 0x40004f11\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR1_CNT_CMP0\r
+CYREG_TMR1_CNT_CMP0 EQU 0x40004f12\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR1_CNT_CMP1\r
+CYREG_TMR1_CNT_CMP1 EQU 0x40004f13\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR1_CAP0\r
+CYREG_TMR1_CAP0 EQU 0x40004f14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR1_CAP1\r
+CYREG_TMR1_CAP1 EQU 0x40004f15\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR1_RT0\r
+CYREG_TMR1_RT0 EQU 0x40004f16\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR1_RT1\r
+CYREG_TMR1_RT1 EQU 0x40004f17\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR2_BASE\r
+CYDEV_TMR2_BASE EQU 0x40004f18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR2_SIZE\r
+CYDEV_TMR2_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR2_CFG0\r
+CYREG_TMR2_CFG0 EQU 0x40004f18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR2_CFG1\r
+CYREG_TMR2_CFG1 EQU 0x40004f19\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR2_CFG2\r
+CYREG_TMR2_CFG2 EQU 0x40004f1a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR2_SR0\r
+CYREG_TMR2_SR0 EQU 0x40004f1b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR2_PER0\r
+CYREG_TMR2_PER0 EQU 0x40004f1c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR2_PER1\r
+CYREG_TMR2_PER1 EQU 0x40004f1d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR2_CNT_CMP0\r
+CYREG_TMR2_CNT_CMP0 EQU 0x40004f1e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR2_CNT_CMP1\r
+CYREG_TMR2_CNT_CMP1 EQU 0x40004f1f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR2_CAP0\r
+CYREG_TMR2_CAP0 EQU 0x40004f20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR2_CAP1\r
+CYREG_TMR2_CAP1 EQU 0x40004f21\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR2_RT0\r
+CYREG_TMR2_RT0 EQU 0x40004f22\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR2_RT1\r
+CYREG_TMR2_RT1 EQU 0x40004f23\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR3_BASE\r
+CYDEV_TMR3_BASE EQU 0x40004f24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TMR3_SIZE\r
+CYDEV_TMR3_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR3_CFG0\r
+CYREG_TMR3_CFG0 EQU 0x40004f24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR3_CFG1\r
+CYREG_TMR3_CFG1 EQU 0x40004f25\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR3_CFG2\r
+CYREG_TMR3_CFG2 EQU 0x40004f26\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR3_SR0\r
+CYREG_TMR3_SR0 EQU 0x40004f27\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR3_PER0\r
+CYREG_TMR3_PER0 EQU 0x40004f28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR3_PER1\r
+CYREG_TMR3_PER1 EQU 0x40004f29\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR3_CNT_CMP0\r
+CYREG_TMR3_CNT_CMP0 EQU 0x40004f2a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR3_CNT_CMP1\r
+CYREG_TMR3_CNT_CMP1 EQU 0x40004f2b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR3_CAP0\r
+CYREG_TMR3_CAP0 EQU 0x40004f2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR3_CAP1\r
+CYREG_TMR3_CAP1 EQU 0x40004f2d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR3_RT0\r
+CYREG_TMR3_RT0 EQU 0x40004f2e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TMR3_RT1\r
+CYREG_TMR3_RT1 EQU 0x40004f2f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_BASE\r
+CYDEV_IO_BASE EQU 0x40005000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_SIZE\r
+CYDEV_IO_SIZE EQU 0x00000200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_BASE\r
+CYDEV_IO_PC_BASE EQU 0x40005000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_SIZE\r
+CYDEV_IO_PC_SIZE EQU 0x00000080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT0_BASE\r
+CYDEV_IO_PC_PRT0_BASE EQU 0x40005000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT0_SIZE\r
+CYDEV_IO_PC_PRT0_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_PC0\r
+CYREG_PRT0_PC0 EQU 0x40005000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_PC1\r
+CYREG_PRT0_PC1 EQU 0x40005001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_PC2\r
+CYREG_PRT0_PC2 EQU 0x40005002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_PC3\r
+CYREG_PRT0_PC3 EQU 0x40005003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_PC4\r
+CYREG_PRT0_PC4 EQU 0x40005004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_PC5\r
+CYREG_PRT0_PC5 EQU 0x40005005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_PC6\r
+CYREG_PRT0_PC6 EQU 0x40005006\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_PC7\r
+CYREG_PRT0_PC7 EQU 0x40005007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT1_BASE\r
+CYDEV_IO_PC_PRT1_BASE EQU 0x40005008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT1_SIZE\r
+CYDEV_IO_PC_PRT1_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_PC0\r
+CYREG_PRT1_PC0 EQU 0x40005008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_PC1\r
+CYREG_PRT1_PC1 EQU 0x40005009\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_PC2\r
+CYREG_PRT1_PC2 EQU 0x4000500a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_PC3\r
+CYREG_PRT1_PC3 EQU 0x4000500b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_PC4\r
+CYREG_PRT1_PC4 EQU 0x4000500c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_PC5\r
+CYREG_PRT1_PC5 EQU 0x4000500d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_PC6\r
+CYREG_PRT1_PC6 EQU 0x4000500e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_PC7\r
+CYREG_PRT1_PC7 EQU 0x4000500f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT2_BASE\r
+CYDEV_IO_PC_PRT2_BASE EQU 0x40005010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT2_SIZE\r
+CYDEV_IO_PC_PRT2_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_PC0\r
+CYREG_PRT2_PC0 EQU 0x40005010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_PC1\r
+CYREG_PRT2_PC1 EQU 0x40005011\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_PC2\r
+CYREG_PRT2_PC2 EQU 0x40005012\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_PC3\r
+CYREG_PRT2_PC3 EQU 0x40005013\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_PC4\r
+CYREG_PRT2_PC4 EQU 0x40005014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_PC5\r
+CYREG_PRT2_PC5 EQU 0x40005015\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_PC6\r
+CYREG_PRT2_PC6 EQU 0x40005016\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_PC7\r
+CYREG_PRT2_PC7 EQU 0x40005017\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT3_BASE\r
+CYDEV_IO_PC_PRT3_BASE EQU 0x40005018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT3_SIZE\r
+CYDEV_IO_PC_PRT3_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_PC0\r
+CYREG_PRT3_PC0 EQU 0x40005018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_PC1\r
+CYREG_PRT3_PC1 EQU 0x40005019\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_PC2\r
+CYREG_PRT3_PC2 EQU 0x4000501a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_PC3\r
+CYREG_PRT3_PC3 EQU 0x4000501b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_PC4\r
+CYREG_PRT3_PC4 EQU 0x4000501c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_PC5\r
+CYREG_PRT3_PC5 EQU 0x4000501d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_PC6\r
+CYREG_PRT3_PC6 EQU 0x4000501e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_PC7\r
+CYREG_PRT3_PC7 EQU 0x4000501f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT4_BASE\r
+CYDEV_IO_PC_PRT4_BASE EQU 0x40005020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT4_SIZE\r
+CYDEV_IO_PC_PRT4_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_PC0\r
+CYREG_PRT4_PC0 EQU 0x40005020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_PC1\r
+CYREG_PRT4_PC1 EQU 0x40005021\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_PC2\r
+CYREG_PRT4_PC2 EQU 0x40005022\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_PC3\r
+CYREG_PRT4_PC3 EQU 0x40005023\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_PC4\r
+CYREG_PRT4_PC4 EQU 0x40005024\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_PC5\r
+CYREG_PRT4_PC5 EQU 0x40005025\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_PC6\r
+CYREG_PRT4_PC6 EQU 0x40005026\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_PC7\r
+CYREG_PRT4_PC7 EQU 0x40005027\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT5_BASE\r
+CYDEV_IO_PC_PRT5_BASE EQU 0x40005028\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT5_SIZE\r
+CYDEV_IO_PC_PRT5_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_PC0\r
+CYREG_PRT5_PC0 EQU 0x40005028\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_PC1\r
+CYREG_PRT5_PC1 EQU 0x40005029\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_PC2\r
+CYREG_PRT5_PC2 EQU 0x4000502a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_PC3\r
+CYREG_PRT5_PC3 EQU 0x4000502b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_PC4\r
+CYREG_PRT5_PC4 EQU 0x4000502c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_PC5\r
+CYREG_PRT5_PC5 EQU 0x4000502d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_PC6\r
+CYREG_PRT5_PC6 EQU 0x4000502e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_PC7\r
+CYREG_PRT5_PC7 EQU 0x4000502f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT6_BASE\r
+CYDEV_IO_PC_PRT6_BASE EQU 0x40005030\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT6_SIZE\r
+CYDEV_IO_PC_PRT6_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_PC0\r
+CYREG_PRT6_PC0 EQU 0x40005030\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_PC1\r
+CYREG_PRT6_PC1 EQU 0x40005031\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_PC2\r
+CYREG_PRT6_PC2 EQU 0x40005032\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_PC3\r
+CYREG_PRT6_PC3 EQU 0x40005033\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_PC4\r
+CYREG_PRT6_PC4 EQU 0x40005034\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_PC5\r
+CYREG_PRT6_PC5 EQU 0x40005035\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_PC6\r
+CYREG_PRT6_PC6 EQU 0x40005036\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_PC7\r
+CYREG_PRT6_PC7 EQU 0x40005037\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT12_BASE\r
+CYDEV_IO_PC_PRT12_BASE EQU 0x40005060\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT12_SIZE\r
+CYDEV_IO_PC_PRT12_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_PC0\r
+CYREG_PRT12_PC0 EQU 0x40005060\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_PC1\r
+CYREG_PRT12_PC1 EQU 0x40005061\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_PC2\r
+CYREG_PRT12_PC2 EQU 0x40005062\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_PC3\r
+CYREG_PRT12_PC3 EQU 0x40005063\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_PC4\r
+CYREG_PRT12_PC4 EQU 0x40005064\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_PC5\r
+CYREG_PRT12_PC5 EQU 0x40005065\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_PC6\r
+CYREG_PRT12_PC6 EQU 0x40005066\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_PC7\r
+CYREG_PRT12_PC7 EQU 0x40005067\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT15_BASE\r
+CYDEV_IO_PC_PRT15_BASE EQU 0x40005078\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT15_SIZE\r
+CYDEV_IO_PC_PRT15_SIZE EQU 0x00000006\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC0\r
+CYREG_IO_PC_PRT15_PC0 EQU 0x40005078\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC1\r
+CYREG_IO_PC_PRT15_PC1 EQU 0x40005079\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC2\r
+CYREG_IO_PC_PRT15_PC2 EQU 0x4000507a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC3\r
+CYREG_IO_PC_PRT15_PC3 EQU 0x4000507b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC4\r
+CYREG_IO_PC_PRT15_PC4 EQU 0x4000507c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC5\r
+CYREG_IO_PC_PRT15_PC5 EQU 0x4000507d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_BASE\r
+CYDEV_IO_PC_PRT15_7_6_BASE EQU 0x4000507e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_SIZE\r
+CYDEV_IO_PC_PRT15_7_6_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IO_PC_PRT15_7_6_PC0\r
+CYREG_IO_PC_PRT15_7_6_PC0 EQU 0x4000507e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IO_PC_PRT15_7_6_PC1\r
+CYREG_IO_PC_PRT15_7_6_PC1 EQU 0x4000507f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_BASE\r
+CYDEV_IO_DR_BASE EQU 0x40005080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_SIZE\r
+CYDEV_IO_DR_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT0_BASE\r
+CYDEV_IO_DR_PRT0_BASE EQU 0x40005080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT0_SIZE\r
+CYDEV_IO_DR_PRT0_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_DR_ALIAS\r
+CYREG_PRT0_DR_ALIAS EQU 0x40005080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT1_BASE\r
+CYDEV_IO_DR_PRT1_BASE EQU 0x40005081\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT1_SIZE\r
+CYDEV_IO_DR_PRT1_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_DR_ALIAS\r
+CYREG_PRT1_DR_ALIAS EQU 0x40005081\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT2_BASE\r
+CYDEV_IO_DR_PRT2_BASE EQU 0x40005082\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT2_SIZE\r
+CYDEV_IO_DR_PRT2_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_DR_ALIAS\r
+CYREG_PRT2_DR_ALIAS EQU 0x40005082\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT3_BASE\r
+CYDEV_IO_DR_PRT3_BASE EQU 0x40005083\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT3_SIZE\r
+CYDEV_IO_DR_PRT3_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_DR_ALIAS\r
+CYREG_PRT3_DR_ALIAS EQU 0x40005083\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT4_BASE\r
+CYDEV_IO_DR_PRT4_BASE EQU 0x40005084\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT4_SIZE\r
+CYDEV_IO_DR_PRT4_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_DR_ALIAS\r
+CYREG_PRT4_DR_ALIAS EQU 0x40005084\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT5_BASE\r
+CYDEV_IO_DR_PRT5_BASE EQU 0x40005085\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT5_SIZE\r
+CYDEV_IO_DR_PRT5_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_DR_ALIAS\r
+CYREG_PRT5_DR_ALIAS EQU 0x40005085\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT6_BASE\r
+CYDEV_IO_DR_PRT6_BASE EQU 0x40005086\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT6_SIZE\r
+CYDEV_IO_DR_PRT6_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_DR_ALIAS\r
+CYREG_PRT6_DR_ALIAS EQU 0x40005086\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT12_BASE\r
+CYDEV_IO_DR_PRT12_BASE EQU 0x4000508c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT12_SIZE\r
+CYDEV_IO_DR_PRT12_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_DR_ALIAS\r
+CYREG_PRT12_DR_ALIAS EQU 0x4000508c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT15_BASE\r
+CYDEV_IO_DR_PRT15_BASE EQU 0x4000508f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_DR_PRT15_SIZE\r
+CYDEV_IO_DR_PRT15_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_DR_15_ALIAS\r
+CYREG_PRT15_DR_15_ALIAS EQU 0x4000508f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_BASE\r
+CYDEV_IO_PS_BASE EQU 0x40005090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_SIZE\r
+CYDEV_IO_PS_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT0_BASE\r
+CYDEV_IO_PS_PRT0_BASE EQU 0x40005090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT0_SIZE\r
+CYDEV_IO_PS_PRT0_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_PS_ALIAS\r
+CYREG_PRT0_PS_ALIAS EQU 0x40005090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT1_BASE\r
+CYDEV_IO_PS_PRT1_BASE EQU 0x40005091\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT1_SIZE\r
+CYDEV_IO_PS_PRT1_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_PS_ALIAS\r
+CYREG_PRT1_PS_ALIAS EQU 0x40005091\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT2_BASE\r
+CYDEV_IO_PS_PRT2_BASE EQU 0x40005092\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT2_SIZE\r
+CYDEV_IO_PS_PRT2_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_PS_ALIAS\r
+CYREG_PRT2_PS_ALIAS EQU 0x40005092\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT3_BASE\r
+CYDEV_IO_PS_PRT3_BASE EQU 0x40005093\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT3_SIZE\r
+CYDEV_IO_PS_PRT3_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_PS_ALIAS\r
+CYREG_PRT3_PS_ALIAS EQU 0x40005093\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT4_BASE\r
+CYDEV_IO_PS_PRT4_BASE EQU 0x40005094\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT4_SIZE\r
+CYDEV_IO_PS_PRT4_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_PS_ALIAS\r
+CYREG_PRT4_PS_ALIAS EQU 0x40005094\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT5_BASE\r
+CYDEV_IO_PS_PRT5_BASE EQU 0x40005095\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT5_SIZE\r
+CYDEV_IO_PS_PRT5_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_PS_ALIAS\r
+CYREG_PRT5_PS_ALIAS EQU 0x40005095\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT6_BASE\r
+CYDEV_IO_PS_PRT6_BASE EQU 0x40005096\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT6_SIZE\r
+CYDEV_IO_PS_PRT6_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_PS_ALIAS\r
+CYREG_PRT6_PS_ALIAS EQU 0x40005096\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT12_BASE\r
+CYDEV_IO_PS_PRT12_BASE EQU 0x4000509c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT12_SIZE\r
+CYDEV_IO_PS_PRT12_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_PS_ALIAS\r
+CYREG_PRT12_PS_ALIAS EQU 0x4000509c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT15_BASE\r
+CYDEV_IO_PS_PRT15_BASE EQU 0x4000509f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PS_PRT15_SIZE\r
+CYDEV_IO_PS_PRT15_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_PS15_ALIAS\r
+CYREG_PRT15_PS15_ALIAS EQU 0x4000509f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_BASE\r
+CYDEV_IO_PRT_BASE EQU 0x40005100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_SIZE\r
+CYDEV_IO_PRT_SIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BASE\r
+CYDEV_IO_PRT_PRT0_BASE EQU 0x40005100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SIZE\r
+CYDEV_IO_PRT_PRT0_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_DR\r
+CYREG_PRT0_DR EQU 0x40005100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_PS\r
+CYREG_PRT0_PS EQU 0x40005101\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_DM0\r
+CYREG_PRT0_DM0 EQU 0x40005102\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_DM1\r
+CYREG_PRT0_DM1 EQU 0x40005103\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_DM2\r
+CYREG_PRT0_DM2 EQU 0x40005104\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_SLW\r
+CYREG_PRT0_SLW EQU 0x40005105\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_BYP\r
+CYREG_PRT0_BYP EQU 0x40005106\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_BIE\r
+CYREG_PRT0_BIE EQU 0x40005107\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_INP_DIS\r
+CYREG_PRT0_INP_DIS EQU 0x40005108\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_CTL\r
+CYREG_PRT0_CTL EQU 0x40005109\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_PRT\r
+CYREG_PRT0_PRT EQU 0x4000510a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_BIT_MASK\r
+CYREG_PRT0_BIT_MASK EQU 0x4000510b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_AMUX\r
+CYREG_PRT0_AMUX EQU 0x4000510c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_AG\r
+CYREG_PRT0_AG EQU 0x4000510d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_LCD_COM_SEG\r
+CYREG_PRT0_LCD_COM_SEG EQU 0x4000510e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_LCD_EN\r
+CYREG_PRT0_LCD_EN EQU 0x4000510f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BASE\r
+CYDEV_IO_PRT_PRT1_BASE EQU 0x40005110\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SIZE\r
+CYDEV_IO_PRT_PRT1_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_DR\r
+CYREG_PRT1_DR EQU 0x40005110\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_PS\r
+CYREG_PRT1_PS EQU 0x40005111\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_DM0\r
+CYREG_PRT1_DM0 EQU 0x40005112\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_DM1\r
+CYREG_PRT1_DM1 EQU 0x40005113\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_DM2\r
+CYREG_PRT1_DM2 EQU 0x40005114\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_SLW\r
+CYREG_PRT1_SLW EQU 0x40005115\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_BYP\r
+CYREG_PRT1_BYP EQU 0x40005116\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_BIE\r
+CYREG_PRT1_BIE EQU 0x40005117\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_INP_DIS\r
+CYREG_PRT1_INP_DIS EQU 0x40005118\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_CTL\r
+CYREG_PRT1_CTL EQU 0x40005119\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_PRT\r
+CYREG_PRT1_PRT EQU 0x4000511a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_BIT_MASK\r
+CYREG_PRT1_BIT_MASK EQU 0x4000511b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_AMUX\r
+CYREG_PRT1_AMUX EQU 0x4000511c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_AG\r
+CYREG_PRT1_AG EQU 0x4000511d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_LCD_COM_SEG\r
+CYREG_PRT1_LCD_COM_SEG EQU 0x4000511e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_LCD_EN\r
+CYREG_PRT1_LCD_EN EQU 0x4000511f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BASE\r
+CYDEV_IO_PRT_PRT2_BASE EQU 0x40005120\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SIZE\r
+CYDEV_IO_PRT_PRT2_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_DR\r
+CYREG_PRT2_DR EQU 0x40005120\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_PS\r
+CYREG_PRT2_PS EQU 0x40005121\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_DM0\r
+CYREG_PRT2_DM0 EQU 0x40005122\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_DM1\r
+CYREG_PRT2_DM1 EQU 0x40005123\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_DM2\r
+CYREG_PRT2_DM2 EQU 0x40005124\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_SLW\r
+CYREG_PRT2_SLW EQU 0x40005125\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_BYP\r
+CYREG_PRT2_BYP EQU 0x40005126\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_BIE\r
+CYREG_PRT2_BIE EQU 0x40005127\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_INP_DIS\r
+CYREG_PRT2_INP_DIS EQU 0x40005128\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_CTL\r
+CYREG_PRT2_CTL EQU 0x40005129\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_PRT\r
+CYREG_PRT2_PRT EQU 0x4000512a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_BIT_MASK\r
+CYREG_PRT2_BIT_MASK EQU 0x4000512b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_AMUX\r
+CYREG_PRT2_AMUX EQU 0x4000512c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_AG\r
+CYREG_PRT2_AG EQU 0x4000512d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_LCD_COM_SEG\r
+CYREG_PRT2_LCD_COM_SEG EQU 0x4000512e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_LCD_EN\r
+CYREG_PRT2_LCD_EN EQU 0x4000512f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BASE\r
+CYDEV_IO_PRT_PRT3_BASE EQU 0x40005130\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SIZE\r
+CYDEV_IO_PRT_PRT3_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_DR\r
+CYREG_PRT3_DR EQU 0x40005130\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_PS\r
+CYREG_PRT3_PS EQU 0x40005131\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_DM0\r
+CYREG_PRT3_DM0 EQU 0x40005132\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_DM1\r
+CYREG_PRT3_DM1 EQU 0x40005133\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_DM2\r
+CYREG_PRT3_DM2 EQU 0x40005134\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_SLW\r
+CYREG_PRT3_SLW EQU 0x40005135\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_BYP\r
+CYREG_PRT3_BYP EQU 0x40005136\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_BIE\r
+CYREG_PRT3_BIE EQU 0x40005137\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_INP_DIS\r
+CYREG_PRT3_INP_DIS EQU 0x40005138\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_CTL\r
+CYREG_PRT3_CTL EQU 0x40005139\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_PRT\r
+CYREG_PRT3_PRT EQU 0x4000513a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_BIT_MASK\r
+CYREG_PRT3_BIT_MASK EQU 0x4000513b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_AMUX\r
+CYREG_PRT3_AMUX EQU 0x4000513c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_AG\r
+CYREG_PRT3_AG EQU 0x4000513d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_LCD_COM_SEG\r
+CYREG_PRT3_LCD_COM_SEG EQU 0x4000513e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_LCD_EN\r
+CYREG_PRT3_LCD_EN EQU 0x4000513f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BASE\r
+CYDEV_IO_PRT_PRT4_BASE EQU 0x40005140\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SIZE\r
+CYDEV_IO_PRT_PRT4_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_DR\r
+CYREG_PRT4_DR EQU 0x40005140\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_PS\r
+CYREG_PRT4_PS EQU 0x40005141\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_DM0\r
+CYREG_PRT4_DM0 EQU 0x40005142\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_DM1\r
+CYREG_PRT4_DM1 EQU 0x40005143\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_DM2\r
+CYREG_PRT4_DM2 EQU 0x40005144\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_SLW\r
+CYREG_PRT4_SLW EQU 0x40005145\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_BYP\r
+CYREG_PRT4_BYP EQU 0x40005146\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_BIE\r
+CYREG_PRT4_BIE EQU 0x40005147\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_INP_DIS\r
+CYREG_PRT4_INP_DIS EQU 0x40005148\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_CTL\r
+CYREG_PRT4_CTL EQU 0x40005149\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_PRT\r
+CYREG_PRT4_PRT EQU 0x4000514a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_BIT_MASK\r
+CYREG_PRT4_BIT_MASK EQU 0x4000514b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_AMUX\r
+CYREG_PRT4_AMUX EQU 0x4000514c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_AG\r
+CYREG_PRT4_AG EQU 0x4000514d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_LCD_COM_SEG\r
+CYREG_PRT4_LCD_COM_SEG EQU 0x4000514e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_LCD_EN\r
+CYREG_PRT4_LCD_EN EQU 0x4000514f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BASE\r
+CYDEV_IO_PRT_PRT5_BASE EQU 0x40005150\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SIZE\r
+CYDEV_IO_PRT_PRT5_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_DR\r
+CYREG_PRT5_DR EQU 0x40005150\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_PS\r
+CYREG_PRT5_PS EQU 0x40005151\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_DM0\r
+CYREG_PRT5_DM0 EQU 0x40005152\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_DM1\r
+CYREG_PRT5_DM1 EQU 0x40005153\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_DM2\r
+CYREG_PRT5_DM2 EQU 0x40005154\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_SLW\r
+CYREG_PRT5_SLW EQU 0x40005155\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_BYP\r
+CYREG_PRT5_BYP EQU 0x40005156\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_BIE\r
+CYREG_PRT5_BIE EQU 0x40005157\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_INP_DIS\r
+CYREG_PRT5_INP_DIS EQU 0x40005158\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_CTL\r
+CYREG_PRT5_CTL EQU 0x40005159\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_PRT\r
+CYREG_PRT5_PRT EQU 0x4000515a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_BIT_MASK\r
+CYREG_PRT5_BIT_MASK EQU 0x4000515b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_AMUX\r
+CYREG_PRT5_AMUX EQU 0x4000515c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_AG\r
+CYREG_PRT5_AG EQU 0x4000515d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_LCD_COM_SEG\r
+CYREG_PRT5_LCD_COM_SEG EQU 0x4000515e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_LCD_EN\r
+CYREG_PRT5_LCD_EN EQU 0x4000515f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BASE\r
+CYDEV_IO_PRT_PRT6_BASE EQU 0x40005160\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SIZE\r
+CYDEV_IO_PRT_PRT6_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_DR\r
+CYREG_PRT6_DR EQU 0x40005160\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_PS\r
+CYREG_PRT6_PS EQU 0x40005161\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_DM0\r
+CYREG_PRT6_DM0 EQU 0x40005162\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_DM1\r
+CYREG_PRT6_DM1 EQU 0x40005163\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_DM2\r
+CYREG_PRT6_DM2 EQU 0x40005164\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_SLW\r
+CYREG_PRT6_SLW EQU 0x40005165\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_BYP\r
+CYREG_PRT6_BYP EQU 0x40005166\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_BIE\r
+CYREG_PRT6_BIE EQU 0x40005167\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_INP_DIS\r
+CYREG_PRT6_INP_DIS EQU 0x40005168\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_CTL\r
+CYREG_PRT6_CTL EQU 0x40005169\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_PRT\r
+CYREG_PRT6_PRT EQU 0x4000516a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_BIT_MASK\r
+CYREG_PRT6_BIT_MASK EQU 0x4000516b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_AMUX\r
+CYREG_PRT6_AMUX EQU 0x4000516c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_AG\r
+CYREG_PRT6_AG EQU 0x4000516d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_LCD_COM_SEG\r
+CYREG_PRT6_LCD_COM_SEG EQU 0x4000516e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_LCD_EN\r
+CYREG_PRT6_LCD_EN EQU 0x4000516f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BASE\r
+CYDEV_IO_PRT_PRT12_BASE EQU 0x400051c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIZE\r
+CYDEV_IO_PRT_PRT12_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_DR\r
+CYREG_PRT12_DR EQU 0x400051c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_PS\r
+CYREG_PRT12_PS EQU 0x400051c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_DM0\r
+CYREG_PRT12_DM0 EQU 0x400051c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_DM1\r
+CYREG_PRT12_DM1 EQU 0x400051c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_DM2\r
+CYREG_PRT12_DM2 EQU 0x400051c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_SLW\r
+CYREG_PRT12_SLW EQU 0x400051c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_BYP\r
+CYREG_PRT12_BYP EQU 0x400051c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_BIE\r
+CYREG_PRT12_BIE EQU 0x400051c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_INP_DIS\r
+CYREG_PRT12_INP_DIS EQU 0x400051c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_SIO_HYST_EN\r
+CYREG_PRT12_SIO_HYST_EN EQU 0x400051c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_PRT\r
+CYREG_PRT12_PRT EQU 0x400051ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_BIT_MASK\r
+CYREG_PRT12_BIT_MASK EQU 0x400051cb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_SIO_REG_HIFREQ\r
+CYREG_PRT12_SIO_REG_HIFREQ EQU 0x400051cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_AG\r
+CYREG_PRT12_AG EQU 0x400051cd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_SIO_CFG\r
+CYREG_PRT12_SIO_CFG EQU 0x400051ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_SIO_DIFF\r
+CYREG_PRT12_SIO_DIFF EQU 0x400051cf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BASE\r
+CYDEV_IO_PRT_PRT15_BASE EQU 0x400051f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SIZE\r
+CYDEV_IO_PRT_PRT15_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_DR\r
+CYREG_PRT15_DR EQU 0x400051f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_PS\r
+CYREG_PRT15_PS EQU 0x400051f1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_DM0\r
+CYREG_PRT15_DM0 EQU 0x400051f2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_DM1\r
+CYREG_PRT15_DM1 EQU 0x400051f3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_DM2\r
+CYREG_PRT15_DM2 EQU 0x400051f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_SLW\r
+CYREG_PRT15_SLW EQU 0x400051f5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_BYP\r
+CYREG_PRT15_BYP EQU 0x400051f6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_BIE\r
+CYREG_PRT15_BIE EQU 0x400051f7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_INP_DIS\r
+CYREG_PRT15_INP_DIS EQU 0x400051f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_CTL\r
+CYREG_PRT15_CTL EQU 0x400051f9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_PRT\r
+CYREG_PRT15_PRT EQU 0x400051fa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_BIT_MASK\r
+CYREG_PRT15_BIT_MASK EQU 0x400051fb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_AMUX\r
+CYREG_PRT15_AMUX EQU 0x400051fc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_AG\r
+CYREG_PRT15_AG EQU 0x400051fd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_LCD_COM_SEG\r
+CYREG_PRT15_LCD_COM_SEG EQU 0x400051fe\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_LCD_EN\r
+CYREG_PRT15_LCD_EN EQU 0x400051ff\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_BASE\r
+CYDEV_PRTDSI_BASE EQU 0x40005200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_SIZE\r
+CYDEV_PRTDSI_SIZE EQU 0x0000007f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_BASE\r
+CYDEV_PRTDSI_PRT0_BASE EQU 0x40005200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SIZE\r
+CYDEV_PRTDSI_PRT0_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_OUT_SEL0\r
+CYREG_PRT0_OUT_SEL0 EQU 0x40005200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_OUT_SEL1\r
+CYREG_PRT0_OUT_SEL1 EQU 0x40005201\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_OE_SEL0\r
+CYREG_PRT0_OE_SEL0 EQU 0x40005202\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_OE_SEL1\r
+CYREG_PRT0_OE_SEL1 EQU 0x40005203\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_DBL_SYNC_IN\r
+CYREG_PRT0_DBL_SYNC_IN EQU 0x40005204\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_SYNC_OUT\r
+CYREG_PRT0_SYNC_OUT EQU 0x40005205\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT0_CAPS_SEL\r
+CYREG_PRT0_CAPS_SEL EQU 0x40005206\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_BASE\r
+CYDEV_PRTDSI_PRT1_BASE EQU 0x40005208\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SIZE\r
+CYDEV_PRTDSI_PRT1_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_OUT_SEL0\r
+CYREG_PRT1_OUT_SEL0 EQU 0x40005208\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_OUT_SEL1\r
+CYREG_PRT1_OUT_SEL1 EQU 0x40005209\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_OE_SEL0\r
+CYREG_PRT1_OE_SEL0 EQU 0x4000520a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_OE_SEL1\r
+CYREG_PRT1_OE_SEL1 EQU 0x4000520b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_DBL_SYNC_IN\r
+CYREG_PRT1_DBL_SYNC_IN EQU 0x4000520c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_SYNC_OUT\r
+CYREG_PRT1_SYNC_OUT EQU 0x4000520d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT1_CAPS_SEL\r
+CYREG_PRT1_CAPS_SEL EQU 0x4000520e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_BASE\r
+CYDEV_PRTDSI_PRT2_BASE EQU 0x40005210\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SIZE\r
+CYDEV_PRTDSI_PRT2_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_OUT_SEL0\r
+CYREG_PRT2_OUT_SEL0 EQU 0x40005210\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_OUT_SEL1\r
+CYREG_PRT2_OUT_SEL1 EQU 0x40005211\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_OE_SEL0\r
+CYREG_PRT2_OE_SEL0 EQU 0x40005212\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_OE_SEL1\r
+CYREG_PRT2_OE_SEL1 EQU 0x40005213\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_DBL_SYNC_IN\r
+CYREG_PRT2_DBL_SYNC_IN EQU 0x40005214\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_SYNC_OUT\r
+CYREG_PRT2_SYNC_OUT EQU 0x40005215\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT2_CAPS_SEL\r
+CYREG_PRT2_CAPS_SEL EQU 0x40005216\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_BASE\r
+CYDEV_PRTDSI_PRT3_BASE EQU 0x40005218\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SIZE\r
+CYDEV_PRTDSI_PRT3_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_OUT_SEL0\r
+CYREG_PRT3_OUT_SEL0 EQU 0x40005218\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_OUT_SEL1\r
+CYREG_PRT3_OUT_SEL1 EQU 0x40005219\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_OE_SEL0\r
+CYREG_PRT3_OE_SEL0 EQU 0x4000521a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_OE_SEL1\r
+CYREG_PRT3_OE_SEL1 EQU 0x4000521b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_DBL_SYNC_IN\r
+CYREG_PRT3_DBL_SYNC_IN EQU 0x4000521c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_SYNC_OUT\r
+CYREG_PRT3_SYNC_OUT EQU 0x4000521d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT3_CAPS_SEL\r
+CYREG_PRT3_CAPS_SEL EQU 0x4000521e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_BASE\r
+CYDEV_PRTDSI_PRT4_BASE EQU 0x40005220\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SIZE\r
+CYDEV_PRTDSI_PRT4_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_OUT_SEL0\r
+CYREG_PRT4_OUT_SEL0 EQU 0x40005220\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_OUT_SEL1\r
+CYREG_PRT4_OUT_SEL1 EQU 0x40005221\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_OE_SEL0\r
+CYREG_PRT4_OE_SEL0 EQU 0x40005222\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_OE_SEL1\r
+CYREG_PRT4_OE_SEL1 EQU 0x40005223\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_DBL_SYNC_IN\r
+CYREG_PRT4_DBL_SYNC_IN EQU 0x40005224\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_SYNC_OUT\r
+CYREG_PRT4_SYNC_OUT EQU 0x40005225\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT4_CAPS_SEL\r
+CYREG_PRT4_CAPS_SEL EQU 0x40005226\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_BASE\r
+CYDEV_PRTDSI_PRT5_BASE EQU 0x40005228\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SIZE\r
+CYDEV_PRTDSI_PRT5_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_OUT_SEL0\r
+CYREG_PRT5_OUT_SEL0 EQU 0x40005228\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_OUT_SEL1\r
+CYREG_PRT5_OUT_SEL1 EQU 0x40005229\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_OE_SEL0\r
+CYREG_PRT5_OE_SEL0 EQU 0x4000522a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_OE_SEL1\r
+CYREG_PRT5_OE_SEL1 EQU 0x4000522b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_DBL_SYNC_IN\r
+CYREG_PRT5_DBL_SYNC_IN EQU 0x4000522c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_SYNC_OUT\r
+CYREG_PRT5_SYNC_OUT EQU 0x4000522d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT5_CAPS_SEL\r
+CYREG_PRT5_CAPS_SEL EQU 0x4000522e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_BASE\r
+CYDEV_PRTDSI_PRT6_BASE EQU 0x40005230\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SIZE\r
+CYDEV_PRTDSI_PRT6_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_OUT_SEL0\r
+CYREG_PRT6_OUT_SEL0 EQU 0x40005230\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_OUT_SEL1\r
+CYREG_PRT6_OUT_SEL1 EQU 0x40005231\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_OE_SEL0\r
+CYREG_PRT6_OE_SEL0 EQU 0x40005232\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_OE_SEL1\r
+CYREG_PRT6_OE_SEL1 EQU 0x40005233\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_DBL_SYNC_IN\r
+CYREG_PRT6_DBL_SYNC_IN EQU 0x40005234\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_SYNC_OUT\r
+CYREG_PRT6_SYNC_OUT EQU 0x40005235\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT6_CAPS_SEL\r
+CYREG_PRT6_CAPS_SEL EQU 0x40005236\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_BASE\r
+CYDEV_PRTDSI_PRT12_BASE EQU 0x40005260\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SIZE\r
+CYDEV_PRTDSI_PRT12_SIZE EQU 0x00000006\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_OUT_SEL0\r
+CYREG_PRT12_OUT_SEL0 EQU 0x40005260\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_OUT_SEL1\r
+CYREG_PRT12_OUT_SEL1 EQU 0x40005261\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_OE_SEL0\r
+CYREG_PRT12_OE_SEL0 EQU 0x40005262\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_OE_SEL1\r
+CYREG_PRT12_OE_SEL1 EQU 0x40005263\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_DBL_SYNC_IN\r
+CYREG_PRT12_DBL_SYNC_IN EQU 0x40005264\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT12_SYNC_OUT\r
+CYREG_PRT12_SYNC_OUT EQU 0x40005265\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_BASE\r
+CYDEV_PRTDSI_PRT15_BASE EQU 0x40005278\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SIZE\r
+CYDEV_PRTDSI_PRT15_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_OUT_SEL0\r
+CYREG_PRT15_OUT_SEL0 EQU 0x40005278\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_OUT_SEL1\r
+CYREG_PRT15_OUT_SEL1 EQU 0x40005279\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_OE_SEL0\r
+CYREG_PRT15_OE_SEL0 EQU 0x4000527a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_OE_SEL1\r
+CYREG_PRT15_OE_SEL1 EQU 0x4000527b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_DBL_SYNC_IN\r
+CYREG_PRT15_DBL_SYNC_IN EQU 0x4000527c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_SYNC_OUT\r
+CYREG_PRT15_SYNC_OUT EQU 0x4000527d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PRT15_CAPS_SEL\r
+CYREG_PRT15_CAPS_SEL EQU 0x4000527e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EMIF_BASE\r
+CYDEV_EMIF_BASE EQU 0x40005400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EMIF_SIZE\r
+CYDEV_EMIF_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_EMIF_NO_UDB\r
+CYREG_EMIF_NO_UDB EQU 0x40005400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_EMIF_RP_WAIT_STATES\r
+CYREG_EMIF_RP_WAIT_STATES EQU 0x40005401\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_EMIF_MEM_DWN\r
+CYREG_EMIF_MEM_DWN EQU 0x40005402\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_EMIF_MEMCLK_DIV\r
+CYREG_EMIF_MEMCLK_DIV EQU 0x40005403\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_EMIF_CLOCK_EN\r
+CYREG_EMIF_CLOCK_EN EQU 0x40005404\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_EMIF_EM_TYPE\r
+CYREG_EMIF_EM_TYPE EQU 0x40005405\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_EMIF_WP_WAIT_STATES\r
+CYREG_EMIF_WP_WAIT_STATES EQU 0x40005406\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_BASE\r
+CYDEV_ANAIF_BASE EQU 0x40005800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_SIZE\r
+CYDEV_ANAIF_SIZE EQU 0x000003a9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_BASE\r
+CYDEV_ANAIF_CFG_BASE EQU 0x40005800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SIZE\r
+CYDEV_ANAIF_CFG_SIZE EQU 0x0000010f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_BASE\r
+CYDEV_ANAIF_CFG_SC0_BASE EQU 0x40005800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_SIZE\r
+CYDEV_ANAIF_CFG_SC0_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC0_CR0\r
+CYREG_SC0_CR0 EQU 0x40005800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC0_CR1\r
+CYREG_SC0_CR1 EQU 0x40005801\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC0_CR2\r
+CYREG_SC0_CR2 EQU 0x40005802\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_BASE\r
+CYDEV_ANAIF_CFG_SC1_BASE EQU 0x40005804\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_SIZE\r
+CYDEV_ANAIF_CFG_SC1_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC1_CR0\r
+CYREG_SC1_CR0 EQU 0x40005804\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC1_CR1\r
+CYREG_SC1_CR1 EQU 0x40005805\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC1_CR2\r
+CYREG_SC1_CR2 EQU 0x40005806\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_BASE\r
+CYDEV_ANAIF_CFG_SC2_BASE EQU 0x40005808\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_SIZE\r
+CYDEV_ANAIF_CFG_SC2_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC2_CR0\r
+CYREG_SC2_CR0 EQU 0x40005808\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC2_CR1\r
+CYREG_SC2_CR1 EQU 0x40005809\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC2_CR2\r
+CYREG_SC2_CR2 EQU 0x4000580a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_BASE\r
+CYDEV_ANAIF_CFG_SC3_BASE EQU 0x4000580c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_SIZE\r
+CYDEV_ANAIF_CFG_SC3_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC3_CR0\r
+CYREG_SC3_CR0 EQU 0x4000580c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC3_CR1\r
+CYREG_SC3_CR1 EQU 0x4000580d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC3_CR2\r
+CYREG_SC3_CR2 EQU 0x4000580e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_BASE\r
+CYDEV_ANAIF_CFG_DAC0_BASE EQU 0x40005820\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_SIZE\r
+CYDEV_ANAIF_CFG_DAC0_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC0_CR0\r
+CYREG_DAC0_CR0 EQU 0x40005820\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC0_CR1\r
+CYREG_DAC0_CR1 EQU 0x40005821\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC0_TST\r
+CYREG_DAC0_TST EQU 0x40005822\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_BASE\r
+CYDEV_ANAIF_CFG_DAC1_BASE EQU 0x40005824\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_SIZE\r
+CYDEV_ANAIF_CFG_DAC1_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC1_CR0\r
+CYREG_DAC1_CR0 EQU 0x40005824\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC1_CR1\r
+CYREG_DAC1_CR1 EQU 0x40005825\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC1_TST\r
+CYREG_DAC1_TST EQU 0x40005826\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_BASE\r
+CYDEV_ANAIF_CFG_DAC2_BASE EQU 0x40005828\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_SIZE\r
+CYDEV_ANAIF_CFG_DAC2_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC2_CR0\r
+CYREG_DAC2_CR0 EQU 0x40005828\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC2_CR1\r
+CYREG_DAC2_CR1 EQU 0x40005829\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC2_TST\r
+CYREG_DAC2_TST EQU 0x4000582a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_BASE\r
+CYDEV_ANAIF_CFG_DAC3_BASE EQU 0x4000582c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_SIZE\r
+CYDEV_ANAIF_CFG_DAC3_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC3_CR0\r
+CYREG_DAC3_CR0 EQU 0x4000582c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC3_CR1\r
+CYREG_DAC3_CR1 EQU 0x4000582d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC3_TST\r
+CYREG_DAC3_TST EQU 0x4000582e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_BASE\r
+CYDEV_ANAIF_CFG_CMP0_BASE EQU 0x40005840\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_SIZE\r
+CYDEV_ANAIF_CFG_CMP0_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP0_CR\r
+CYREG_CMP0_CR EQU 0x40005840\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_BASE\r
+CYDEV_ANAIF_CFG_CMP1_BASE EQU 0x40005841\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_SIZE\r
+CYDEV_ANAIF_CFG_CMP1_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP1_CR\r
+CYREG_CMP1_CR EQU 0x40005841\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_BASE\r
+CYDEV_ANAIF_CFG_CMP2_BASE EQU 0x40005842\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_SIZE\r
+CYDEV_ANAIF_CFG_CMP2_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP2_CR\r
+CYREG_CMP2_CR EQU 0x40005842\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_BASE\r
+CYDEV_ANAIF_CFG_CMP3_BASE EQU 0x40005843\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_SIZE\r
+CYDEV_ANAIF_CFG_CMP3_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP3_CR\r
+CYREG_CMP3_CR EQU 0x40005843\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_BASE\r
+CYDEV_ANAIF_CFG_LUT0_BASE EQU 0x40005848\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_SIZE\r
+CYDEV_ANAIF_CFG_LUT0_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LUT0_CR\r
+CYREG_LUT0_CR EQU 0x40005848\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LUT0_MX\r
+CYREG_LUT0_MX EQU 0x40005849\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_BASE\r
+CYDEV_ANAIF_CFG_LUT1_BASE EQU 0x4000584a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_SIZE\r
+CYDEV_ANAIF_CFG_LUT1_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LUT1_CR\r
+CYREG_LUT1_CR EQU 0x4000584a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LUT1_MX\r
+CYREG_LUT1_MX EQU 0x4000584b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_BASE\r
+CYDEV_ANAIF_CFG_LUT2_BASE EQU 0x4000584c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_SIZE\r
+CYDEV_ANAIF_CFG_LUT2_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LUT2_CR\r
+CYREG_LUT2_CR EQU 0x4000584c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LUT2_MX\r
+CYREG_LUT2_MX EQU 0x4000584d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_BASE\r
+CYDEV_ANAIF_CFG_LUT3_BASE EQU 0x4000584e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_SIZE\r
+CYDEV_ANAIF_CFG_LUT3_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LUT3_CR\r
+CYREG_LUT3_CR EQU 0x4000584e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LUT3_MX\r
+CYREG_LUT3_MX EQU 0x4000584f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_BASE\r
+CYDEV_ANAIF_CFG_OPAMP0_BASE EQU 0x40005858\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_SIZE\r
+CYDEV_ANAIF_CFG_OPAMP0_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP0_CR\r
+CYREG_OPAMP0_CR EQU 0x40005858\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP0_RSVD\r
+CYREG_OPAMP0_RSVD EQU 0x40005859\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_BASE\r
+CYDEV_ANAIF_CFG_OPAMP1_BASE EQU 0x4000585a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_SIZE\r
+CYDEV_ANAIF_CFG_OPAMP1_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP1_CR\r
+CYREG_OPAMP1_CR EQU 0x4000585a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP1_RSVD\r
+CYREG_OPAMP1_RSVD EQU 0x4000585b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_BASE\r
+CYDEV_ANAIF_CFG_OPAMP2_BASE EQU 0x4000585c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_SIZE\r
+CYDEV_ANAIF_CFG_OPAMP2_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP2_CR\r
+CYREG_OPAMP2_CR EQU 0x4000585c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP2_RSVD\r
+CYREG_OPAMP2_RSVD EQU 0x4000585d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_BASE\r
+CYDEV_ANAIF_CFG_OPAMP3_BASE EQU 0x4000585e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_SIZE\r
+CYDEV_ANAIF_CFG_OPAMP3_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP3_CR\r
+CYREG_OPAMP3_CR EQU 0x4000585e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP3_RSVD\r
+CYREG_OPAMP3_RSVD EQU 0x4000585f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_BASE\r
+CYDEV_ANAIF_CFG_LCDDAC_BASE EQU 0x40005868\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_SIZE\r
+CYDEV_ANAIF_CFG_LCDDAC_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LCDDAC_CR0\r
+CYREG_LCDDAC_CR0 EQU 0x40005868\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LCDDAC_CR1\r
+CYREG_LCDDAC_CR1 EQU 0x40005869\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_BASE\r
+CYDEV_ANAIF_CFG_LCDDRV_BASE EQU 0x4000586a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_SIZE\r
+CYDEV_ANAIF_CFG_LCDDRV_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LCDDRV_CR\r
+CYREG_LCDDRV_CR EQU 0x4000586a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_BASE\r
+CYDEV_ANAIF_CFG_LCDTMR_BASE EQU 0x4000586b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_SIZE\r
+CYDEV_ANAIF_CFG_LCDTMR_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LCDTMR_CFG\r
+CYREG_LCDTMR_CFG EQU 0x4000586b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_BASE\r
+CYDEV_ANAIF_CFG_BG_BASE EQU 0x4000586c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_SIZE\r
+CYDEV_ANAIF_CFG_BG_SIZE EQU 0x00000004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BG_CR0\r
+CYREG_BG_CR0 EQU 0x4000586c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BG_RSVD\r
+CYREG_BG_RSVD EQU 0x4000586d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BG_DFT0\r
+CYREG_BG_DFT0 EQU 0x4000586e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BG_DFT1\r
+CYREG_BG_DFT1 EQU 0x4000586f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_BASE\r
+CYDEV_ANAIF_CFG_CAPSL_BASE EQU 0x40005870\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_SIZE\r
+CYDEV_ANAIF_CFG_CAPSL_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAPSL_CFG0\r
+CYREG_CAPSL_CFG0 EQU 0x40005870\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAPSL_CFG1\r
+CYREG_CAPSL_CFG1 EQU 0x40005871\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_BASE\r
+CYDEV_ANAIF_CFG_CAPSR_BASE EQU 0x40005872\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_SIZE\r
+CYDEV_ANAIF_CFG_CAPSR_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAPSR_CFG0\r
+CYREG_CAPSR_CFG0 EQU 0x40005872\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAPSR_CFG1\r
+CYREG_CAPSR_CFG1 EQU 0x40005873\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_BASE\r
+CYDEV_ANAIF_CFG_PUMP_BASE EQU 0x40005876\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_SIZE\r
+CYDEV_ANAIF_CFG_PUMP_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PUMP_CR0\r
+CYREG_PUMP_CR0 EQU 0x40005876\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PUMP_CR1\r
+CYREG_PUMP_CR1 EQU 0x40005877\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_BASE\r
+CYDEV_ANAIF_CFG_LPF0_BASE EQU 0x40005878\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_SIZE\r
+CYDEV_ANAIF_CFG_LPF0_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LPF0_CR0\r
+CYREG_LPF0_CR0 EQU 0x40005878\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LPF0_RSVD\r
+CYREG_LPF0_RSVD EQU 0x40005879\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_BASE\r
+CYDEV_ANAIF_CFG_LPF1_BASE EQU 0x4000587a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_SIZE\r
+CYDEV_ANAIF_CFG_LPF1_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LPF1_CR0\r
+CYREG_LPF1_CR0 EQU 0x4000587a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LPF1_RSVD\r
+CYREG_LPF1_RSVD EQU 0x4000587b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_BASE\r
+CYDEV_ANAIF_CFG_MISC_BASE EQU 0x4000587c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_SIZE\r
+CYDEV_ANAIF_CFG_MISC_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ANAIF_CFG_MISC_CR0\r
+CYREG_ANAIF_CFG_MISC_CR0 EQU 0x4000587c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BASE\r
+CYDEV_ANAIF_CFG_DSM0_BASE EQU 0x40005880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_SIZE\r
+CYDEV_ANAIF_CFG_DSM0_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_CR0\r
+CYREG_DSM0_CR0 EQU 0x40005880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_CR1\r
+CYREG_DSM0_CR1 EQU 0x40005881\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_CR2\r
+CYREG_DSM0_CR2 EQU 0x40005882\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_CR3\r
+CYREG_DSM0_CR3 EQU 0x40005883\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_CR4\r
+CYREG_DSM0_CR4 EQU 0x40005884\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_CR5\r
+CYREG_DSM0_CR5 EQU 0x40005885\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_CR6\r
+CYREG_DSM0_CR6 EQU 0x40005886\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_CR7\r
+CYREG_DSM0_CR7 EQU 0x40005887\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_CR8\r
+CYREG_DSM0_CR8 EQU 0x40005888\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_CR9\r
+CYREG_DSM0_CR9 EQU 0x40005889\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_CR10\r
+CYREG_DSM0_CR10 EQU 0x4000588a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_CR11\r
+CYREG_DSM0_CR11 EQU 0x4000588b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_CR12\r
+CYREG_DSM0_CR12 EQU 0x4000588c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_CR13\r
+CYREG_DSM0_CR13 EQU 0x4000588d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_CR14\r
+CYREG_DSM0_CR14 EQU 0x4000588e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_CR15\r
+CYREG_DSM0_CR15 EQU 0x4000588f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_CR16\r
+CYREG_DSM0_CR16 EQU 0x40005890\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_CR17\r
+CYREG_DSM0_CR17 EQU 0x40005891\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_REF0\r
+CYREG_DSM0_REF0 EQU 0x40005892\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_REF1\r
+CYREG_DSM0_REF1 EQU 0x40005893\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_REF2\r
+CYREG_DSM0_REF2 EQU 0x40005894\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_REF3\r
+CYREG_DSM0_REF3 EQU 0x40005895\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_DEM0\r
+CYREG_DSM0_DEM0 EQU 0x40005896\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_DEM1\r
+CYREG_DSM0_DEM1 EQU 0x40005897\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_TST0\r
+CYREG_DSM0_TST0 EQU 0x40005898\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_TST1\r
+CYREG_DSM0_TST1 EQU 0x40005899\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_BUF0\r
+CYREG_DSM0_BUF0 EQU 0x4000589a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_BUF1\r
+CYREG_DSM0_BUF1 EQU 0x4000589b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_BUF2\r
+CYREG_DSM0_BUF2 EQU 0x4000589c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_BUF3\r
+CYREG_DSM0_BUF3 EQU 0x4000589d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_MISC\r
+CYREG_DSM0_MISC EQU 0x4000589e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_RSVD1\r
+CYREG_DSM0_RSVD1 EQU 0x4000589f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_BASE\r
+CYDEV_ANAIF_CFG_SAR0_BASE EQU 0x40005900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_SIZE\r
+CYDEV_ANAIF_CFG_SAR0_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR0_CSR0\r
+CYREG_SAR0_CSR0 EQU 0x40005900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR0_CSR1\r
+CYREG_SAR0_CSR1 EQU 0x40005901\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR0_CSR2\r
+CYREG_SAR0_CSR2 EQU 0x40005902\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR0_CSR3\r
+CYREG_SAR0_CSR3 EQU 0x40005903\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR0_CSR4\r
+CYREG_SAR0_CSR4 EQU 0x40005904\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR0_CSR5\r
+CYREG_SAR0_CSR5 EQU 0x40005905\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR0_CSR6\r
+CYREG_SAR0_CSR6 EQU 0x40005906\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_BASE\r
+CYDEV_ANAIF_CFG_SAR1_BASE EQU 0x40005908\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_SIZE\r
+CYDEV_ANAIF_CFG_SAR1_SIZE EQU 0x00000007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR1_CSR0\r
+CYREG_SAR1_CSR0 EQU 0x40005908\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR1_CSR1\r
+CYREG_SAR1_CSR1 EQU 0x40005909\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR1_CSR2\r
+CYREG_SAR1_CSR2 EQU 0x4000590a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR1_CSR3\r
+CYREG_SAR1_CSR3 EQU 0x4000590b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR1_CSR4\r
+CYREG_SAR1_CSR4 EQU 0x4000590c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR1_CSR5\r
+CYREG_SAR1_CSR5 EQU 0x4000590d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR1_CSR6\r
+CYREG_SAR1_CSR6 EQU 0x4000590e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_BASE\r
+CYDEV_ANAIF_RT_BASE EQU 0x40005a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SIZE\r
+CYDEV_ANAIF_RT_SIZE EQU 0x00000162\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BASE\r
+CYDEV_ANAIF_RT_SC0_BASE EQU 0x40005a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SIZE\r
+CYDEV_ANAIF_RT_SC0_SIZE EQU 0x0000000d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC0_SW0\r
+CYREG_SC0_SW0 EQU 0x40005a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC0_SW2\r
+CYREG_SC0_SW2 EQU 0x40005a02\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC0_SW3\r
+CYREG_SC0_SW3 EQU 0x40005a03\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC0_SW4\r
+CYREG_SC0_SW4 EQU 0x40005a04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC0_SW6\r
+CYREG_SC0_SW6 EQU 0x40005a06\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC0_SW7\r
+CYREG_SC0_SW7 EQU 0x40005a07\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC0_SW8\r
+CYREG_SC0_SW8 EQU 0x40005a08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC0_SW10\r
+CYREG_SC0_SW10 EQU 0x40005a0a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC0_CLK\r
+CYREG_SC0_CLK EQU 0x40005a0b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC0_BST\r
+CYREG_SC0_BST EQU 0x40005a0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BASE\r
+CYDEV_ANAIF_RT_SC1_BASE EQU 0x40005a10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SIZE\r
+CYDEV_ANAIF_RT_SC1_SIZE EQU 0x0000000d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC1_SW0\r
+CYREG_SC1_SW0 EQU 0x40005a10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC1_SW2\r
+CYREG_SC1_SW2 EQU 0x40005a12\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC1_SW3\r
+CYREG_SC1_SW3 EQU 0x40005a13\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC1_SW4\r
+CYREG_SC1_SW4 EQU 0x40005a14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC1_SW6\r
+CYREG_SC1_SW6 EQU 0x40005a16\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC1_SW7\r
+CYREG_SC1_SW7 EQU 0x40005a17\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC1_SW8\r
+CYREG_SC1_SW8 EQU 0x40005a18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC1_SW10\r
+CYREG_SC1_SW10 EQU 0x40005a1a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC1_CLK\r
+CYREG_SC1_CLK EQU 0x40005a1b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC1_BST\r
+CYREG_SC1_BST EQU 0x40005a1c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BASE\r
+CYDEV_ANAIF_RT_SC2_BASE EQU 0x40005a20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SIZE\r
+CYDEV_ANAIF_RT_SC2_SIZE EQU 0x0000000d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC2_SW0\r
+CYREG_SC2_SW0 EQU 0x40005a20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC2_SW2\r
+CYREG_SC2_SW2 EQU 0x40005a22\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC2_SW3\r
+CYREG_SC2_SW3 EQU 0x40005a23\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC2_SW4\r
+CYREG_SC2_SW4 EQU 0x40005a24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC2_SW6\r
+CYREG_SC2_SW6 EQU 0x40005a26\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC2_SW7\r
+CYREG_SC2_SW7 EQU 0x40005a27\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC2_SW8\r
+CYREG_SC2_SW8 EQU 0x40005a28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC2_SW10\r
+CYREG_SC2_SW10 EQU 0x40005a2a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC2_CLK\r
+CYREG_SC2_CLK EQU 0x40005a2b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC2_BST\r
+CYREG_SC2_BST EQU 0x40005a2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BASE\r
+CYDEV_ANAIF_RT_SC3_BASE EQU 0x40005a30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SIZE\r
+CYDEV_ANAIF_RT_SC3_SIZE EQU 0x0000000d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC3_SW0\r
+CYREG_SC3_SW0 EQU 0x40005a30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC3_SW2\r
+CYREG_SC3_SW2 EQU 0x40005a32\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC3_SW3\r
+CYREG_SC3_SW3 EQU 0x40005a33\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC3_SW4\r
+CYREG_SC3_SW4 EQU 0x40005a34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC3_SW6\r
+CYREG_SC3_SW6 EQU 0x40005a36\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC3_SW7\r
+CYREG_SC3_SW7 EQU 0x40005a37\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC3_SW8\r
+CYREG_SC3_SW8 EQU 0x40005a38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC3_SW10\r
+CYREG_SC3_SW10 EQU 0x40005a3a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC3_CLK\r
+CYREG_SC3_CLK EQU 0x40005a3b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC3_BST\r
+CYREG_SC3_BST EQU 0x40005a3c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_BASE\r
+CYDEV_ANAIF_RT_DAC0_BASE EQU 0x40005a80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SIZE\r
+CYDEV_ANAIF_RT_DAC0_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC0_SW0\r
+CYREG_DAC0_SW0 EQU 0x40005a80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC0_SW2\r
+CYREG_DAC0_SW2 EQU 0x40005a82\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC0_SW3\r
+CYREG_DAC0_SW3 EQU 0x40005a83\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC0_SW4\r
+CYREG_DAC0_SW4 EQU 0x40005a84\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC0_STROBE\r
+CYREG_DAC0_STROBE EQU 0x40005a87\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_BASE\r
+CYDEV_ANAIF_RT_DAC1_BASE EQU 0x40005a88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SIZE\r
+CYDEV_ANAIF_RT_DAC1_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC1_SW0\r
+CYREG_DAC1_SW0 EQU 0x40005a88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC1_SW2\r
+CYREG_DAC1_SW2 EQU 0x40005a8a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC1_SW3\r
+CYREG_DAC1_SW3 EQU 0x40005a8b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC1_SW4\r
+CYREG_DAC1_SW4 EQU 0x40005a8c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC1_STROBE\r
+CYREG_DAC1_STROBE EQU 0x40005a8f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_BASE\r
+CYDEV_ANAIF_RT_DAC2_BASE EQU 0x40005a90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SIZE\r
+CYDEV_ANAIF_RT_DAC2_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC2_SW0\r
+CYREG_DAC2_SW0 EQU 0x40005a90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC2_SW2\r
+CYREG_DAC2_SW2 EQU 0x40005a92\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC2_SW3\r
+CYREG_DAC2_SW3 EQU 0x40005a93\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC2_SW4\r
+CYREG_DAC2_SW4 EQU 0x40005a94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC2_STROBE\r
+CYREG_DAC2_STROBE EQU 0x40005a97\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_BASE\r
+CYDEV_ANAIF_RT_DAC3_BASE EQU 0x40005a98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SIZE\r
+CYDEV_ANAIF_RT_DAC3_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC3_SW0\r
+CYREG_DAC3_SW0 EQU 0x40005a98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC3_SW2\r
+CYREG_DAC3_SW2 EQU 0x40005a9a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC3_SW3\r
+CYREG_DAC3_SW3 EQU 0x40005a9b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC3_SW4\r
+CYREG_DAC3_SW4 EQU 0x40005a9c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC3_STROBE\r
+CYREG_DAC3_STROBE EQU 0x40005a9f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_BASE\r
+CYDEV_ANAIF_RT_CMP0_BASE EQU 0x40005ac0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SIZE\r
+CYDEV_ANAIF_RT_CMP0_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP0_SW0\r
+CYREG_CMP0_SW0 EQU 0x40005ac0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP0_SW2\r
+CYREG_CMP0_SW2 EQU 0x40005ac2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP0_SW3\r
+CYREG_CMP0_SW3 EQU 0x40005ac3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP0_SW4\r
+CYREG_CMP0_SW4 EQU 0x40005ac4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP0_SW6\r
+CYREG_CMP0_SW6 EQU 0x40005ac6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP0_CLK\r
+CYREG_CMP0_CLK EQU 0x40005ac7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_BASE\r
+CYDEV_ANAIF_RT_CMP1_BASE EQU 0x40005ac8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SIZE\r
+CYDEV_ANAIF_RT_CMP1_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP1_SW0\r
+CYREG_CMP1_SW0 EQU 0x40005ac8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP1_SW2\r
+CYREG_CMP1_SW2 EQU 0x40005aca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP1_SW3\r
+CYREG_CMP1_SW3 EQU 0x40005acb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP1_SW4\r
+CYREG_CMP1_SW4 EQU 0x40005acc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP1_SW6\r
+CYREG_CMP1_SW6 EQU 0x40005ace\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP1_CLK\r
+CYREG_CMP1_CLK EQU 0x40005acf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_BASE\r
+CYDEV_ANAIF_RT_CMP2_BASE EQU 0x40005ad0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SIZE\r
+CYDEV_ANAIF_RT_CMP2_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP2_SW0\r
+CYREG_CMP2_SW0 EQU 0x40005ad0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP2_SW2\r
+CYREG_CMP2_SW2 EQU 0x40005ad2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP2_SW3\r
+CYREG_CMP2_SW3 EQU 0x40005ad3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP2_SW4\r
+CYREG_CMP2_SW4 EQU 0x40005ad4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP2_SW6\r
+CYREG_CMP2_SW6 EQU 0x40005ad6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP2_CLK\r
+CYREG_CMP2_CLK EQU 0x40005ad7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_BASE\r
+CYDEV_ANAIF_RT_CMP3_BASE EQU 0x40005ad8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SIZE\r
+CYDEV_ANAIF_RT_CMP3_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP3_SW0\r
+CYREG_CMP3_SW0 EQU 0x40005ad8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP3_SW2\r
+CYREG_CMP3_SW2 EQU 0x40005ada\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP3_SW3\r
+CYREG_CMP3_SW3 EQU 0x40005adb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP3_SW4\r
+CYREG_CMP3_SW4 EQU 0x40005adc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP3_SW6\r
+CYREG_CMP3_SW6 EQU 0x40005ade\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP3_CLK\r
+CYREG_CMP3_CLK EQU 0x40005adf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_BASE\r
+CYDEV_ANAIF_RT_DSM0_BASE EQU 0x40005b00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SIZE\r
+CYDEV_ANAIF_RT_DSM0_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_SW0\r
+CYREG_DSM0_SW0 EQU 0x40005b00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_SW2\r
+CYREG_DSM0_SW2 EQU 0x40005b02\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_SW3\r
+CYREG_DSM0_SW3 EQU 0x40005b03\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_SW4\r
+CYREG_DSM0_SW4 EQU 0x40005b04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_SW6\r
+CYREG_DSM0_SW6 EQU 0x40005b06\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_CLK\r
+CYREG_DSM0_CLK EQU 0x40005b07\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_BASE\r
+CYDEV_ANAIF_RT_SAR0_BASE EQU 0x40005b20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SIZE\r
+CYDEV_ANAIF_RT_SAR0_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR0_SW0\r
+CYREG_SAR0_SW0 EQU 0x40005b20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR0_SW2\r
+CYREG_SAR0_SW2 EQU 0x40005b22\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR0_SW3\r
+CYREG_SAR0_SW3 EQU 0x40005b23\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR0_SW4\r
+CYREG_SAR0_SW4 EQU 0x40005b24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR0_SW6\r
+CYREG_SAR0_SW6 EQU 0x40005b26\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR0_CLK\r
+CYREG_SAR0_CLK EQU 0x40005b27\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_BASE\r
+CYDEV_ANAIF_RT_SAR1_BASE EQU 0x40005b28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SIZE\r
+CYDEV_ANAIF_RT_SAR1_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR1_SW0\r
+CYREG_SAR1_SW0 EQU 0x40005b28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR1_SW2\r
+CYREG_SAR1_SW2 EQU 0x40005b2a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR1_SW3\r
+CYREG_SAR1_SW3 EQU 0x40005b2b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR1_SW4\r
+CYREG_SAR1_SW4 EQU 0x40005b2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR1_SW6\r
+CYREG_SAR1_SW6 EQU 0x40005b2e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR1_CLK\r
+CYREG_SAR1_CLK EQU 0x40005b2f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_BASE\r
+CYDEV_ANAIF_RT_OPAMP0_BASE EQU 0x40005b40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SIZE\r
+CYDEV_ANAIF_RT_OPAMP0_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP0_MX\r
+CYREG_OPAMP0_MX EQU 0x40005b40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP0_SW\r
+CYREG_OPAMP0_SW EQU 0x40005b41\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_BASE\r
+CYDEV_ANAIF_RT_OPAMP1_BASE EQU 0x40005b42\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SIZE\r
+CYDEV_ANAIF_RT_OPAMP1_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP1_MX\r
+CYREG_OPAMP1_MX EQU 0x40005b42\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP1_SW\r
+CYREG_OPAMP1_SW EQU 0x40005b43\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_BASE\r
+CYDEV_ANAIF_RT_OPAMP2_BASE EQU 0x40005b44\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SIZE\r
+CYDEV_ANAIF_RT_OPAMP2_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP2_MX\r
+CYREG_OPAMP2_MX EQU 0x40005b44\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP2_SW\r
+CYREG_OPAMP2_SW EQU 0x40005b45\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_BASE\r
+CYDEV_ANAIF_RT_OPAMP3_BASE EQU 0x40005b46\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SIZE\r
+CYDEV_ANAIF_RT_OPAMP3_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP3_MX\r
+CYREG_OPAMP3_MX EQU 0x40005b46\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_OPAMP3_SW\r
+CYREG_OPAMP3_SW EQU 0x40005b47\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_BASE\r
+CYDEV_ANAIF_RT_LCDDAC_BASE EQU 0x40005b50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SIZE\r
+CYDEV_ANAIF_RT_LCDDAC_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LCDDAC_SW0\r
+CYREG_LCDDAC_SW0 EQU 0x40005b50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LCDDAC_SW1\r
+CYREG_LCDDAC_SW1 EQU 0x40005b51\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LCDDAC_SW2\r
+CYREG_LCDDAC_SW2 EQU 0x40005b52\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LCDDAC_SW3\r
+CYREG_LCDDAC_SW3 EQU 0x40005b53\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LCDDAC_SW4\r
+CYREG_LCDDAC_SW4 EQU 0x40005b54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_BASE\r
+CYDEV_ANAIF_RT_SC_BASE EQU 0x40005b56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_SIZE\r
+CYDEV_ANAIF_RT_SC_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC_MISC\r
+CYREG_SC_MISC EQU 0x40005b56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_BASE\r
+CYDEV_ANAIF_RT_BUS_BASE EQU 0x40005b58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SIZE\r
+CYDEV_ANAIF_RT_BUS_SIZE EQU 0x00000004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BUS_SW0\r
+CYREG_BUS_SW0 EQU 0x40005b58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BUS_SW2\r
+CYREG_BUS_SW2 EQU 0x40005b5a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BUS_SW3\r
+CYREG_BUS_SW3 EQU 0x40005b5b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_BASE\r
+CYDEV_ANAIF_RT_DFT_BASE EQU 0x40005b5c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_SIZE\r
+CYDEV_ANAIF_RT_DFT_SIZE EQU 0x00000006\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFT_CR0\r
+CYREG_DFT_CR0 EQU 0x40005b5c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFT_CR1\r
+CYREG_DFT_CR1 EQU 0x40005b5d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFT_CR2\r
+CYREG_DFT_CR2 EQU 0x40005b5e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFT_CR3\r
+CYREG_DFT_CR3 EQU 0x40005b5f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFT_CR4\r
+CYREG_DFT_CR4 EQU 0x40005b60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFT_CR5\r
+CYREG_DFT_CR5 EQU 0x40005b61\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_BASE\r
+CYDEV_ANAIF_WRK_BASE EQU 0x40005b80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SIZE\r
+CYDEV_ANAIF_WRK_SIZE EQU 0x00000029\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_BASE\r
+CYDEV_ANAIF_WRK_DAC0_BASE EQU 0x40005b80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_SIZE\r
+CYDEV_ANAIF_WRK_DAC0_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC0_D\r
+CYREG_DAC0_D EQU 0x40005b80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_BASE\r
+CYDEV_ANAIF_WRK_DAC1_BASE EQU 0x40005b81\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_SIZE\r
+CYDEV_ANAIF_WRK_DAC1_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC1_D\r
+CYREG_DAC1_D EQU 0x40005b81\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_BASE\r
+CYDEV_ANAIF_WRK_DAC2_BASE EQU 0x40005b82\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_SIZE\r
+CYDEV_ANAIF_WRK_DAC2_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC2_D\r
+CYREG_DAC2_D EQU 0x40005b82\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_BASE\r
+CYDEV_ANAIF_WRK_DAC3_BASE EQU 0x40005b83\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_SIZE\r
+CYDEV_ANAIF_WRK_DAC3_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DAC3_D\r
+CYREG_DAC3_D EQU 0x40005b83\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_BASE\r
+CYDEV_ANAIF_WRK_DSM0_BASE EQU 0x40005b88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_SIZE\r
+CYDEV_ANAIF_WRK_DSM0_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_OUT0\r
+CYREG_DSM0_OUT0 EQU 0x40005b88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DSM0_OUT1\r
+CYREG_DSM0_OUT1 EQU 0x40005b89\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_BASE\r
+CYDEV_ANAIF_WRK_LUT_BASE EQU 0x40005b90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SIZE\r
+CYDEV_ANAIF_WRK_LUT_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LUT_SR\r
+CYREG_LUT_SR EQU 0x40005b90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LUT_WRK1\r
+CYREG_LUT_WRK1 EQU 0x40005b91\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LUT_MSK\r
+CYREG_LUT_MSK EQU 0x40005b92\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LUT_CLK\r
+CYREG_LUT_CLK EQU 0x40005b93\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_LUT_CPTR\r
+CYREG_LUT_CPTR EQU 0x40005b94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_BASE\r
+CYDEV_ANAIF_WRK_CMP_BASE EQU 0x40005b96\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_SIZE\r
+CYDEV_ANAIF_WRK_CMP_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP_WRK\r
+CYREG_CMP_WRK EQU 0x40005b96\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CMP_TST\r
+CYREG_CMP_TST EQU 0x40005b97\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_BASE\r
+CYDEV_ANAIF_WRK_SC_BASE EQU 0x40005b98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SIZE\r
+CYDEV_ANAIF_WRK_SC_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC_SR\r
+CYREG_SC_SR EQU 0x40005b98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC_WRK1\r
+CYREG_SC_WRK1 EQU 0x40005b99\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC_MSK\r
+CYREG_SC_MSK EQU 0x40005b9a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC_CMPINV\r
+CYREG_SC_CMPINV EQU 0x40005b9b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SC_CPTR\r
+CYREG_SC_CPTR EQU 0x40005b9c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_BASE\r
+CYDEV_ANAIF_WRK_SAR0_BASE EQU 0x40005ba0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_SIZE\r
+CYDEV_ANAIF_WRK_SAR0_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR0_WRK0\r
+CYREG_SAR0_WRK0 EQU 0x40005ba0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR0_WRK1\r
+CYREG_SAR0_WRK1 EQU 0x40005ba1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_BASE\r
+CYDEV_ANAIF_WRK_SAR1_BASE EQU 0x40005ba2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_SIZE\r
+CYDEV_ANAIF_WRK_SAR1_SIZE EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR1_WRK0\r
+CYREG_SAR1_WRK0 EQU 0x40005ba2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SAR1_WRK1\r
+CYREG_SAR1_WRK1 EQU 0x40005ba3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_BASE\r
+CYDEV_ANAIF_WRK_SARS_BASE EQU 0x40005ba8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SIZE\r
+CYDEV_ANAIF_WRK_SARS_SIZE EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ANAIF_WRK_SARS_SOF\r
+CYREG_ANAIF_WRK_SARS_SOF EQU 0x40005ba8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_BASE\r
+CYDEV_USB_BASE EQU 0x40006000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIZE\r
+CYDEV_USB_SIZE EQU 0x00000300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_EP0_DR0\r
+CYREG_USB_EP0_DR0 EQU 0x40006000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_EP0_DR1\r
+CYREG_USB_EP0_DR1 EQU 0x40006001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_EP0_DR2\r
+CYREG_USB_EP0_DR2 EQU 0x40006002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_EP0_DR3\r
+CYREG_USB_EP0_DR3 EQU 0x40006003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_EP0_DR4\r
+CYREG_USB_EP0_DR4 EQU 0x40006004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_EP0_DR5\r
+CYREG_USB_EP0_DR5 EQU 0x40006005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_EP0_DR6\r
+CYREG_USB_EP0_DR6 EQU 0x40006006\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_EP0_DR7\r
+CYREG_USB_EP0_DR7 EQU 0x40006007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_CR0\r
+CYREG_USB_CR0 EQU 0x40006008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_CR1\r
+CYREG_USB_CR1 EQU 0x40006009\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP_INT_EN\r
+CYREG_USB_SIE_EP_INT_EN EQU 0x4000600a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP_INT_SR\r
+CYREG_USB_SIE_EP_INT_SR EQU 0x4000600b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP1_BASE\r
+CYDEV_USB_SIE_EP1_BASE EQU 0x4000600c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP1_SIZE\r
+CYDEV_USB_SIE_EP1_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP1_CNT0\r
+CYREG_USB_SIE_EP1_CNT0 EQU 0x4000600c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP1_CNT1\r
+CYREG_USB_SIE_EP1_CNT1 EQU 0x4000600d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP1_CR0\r
+CYREG_USB_SIE_EP1_CR0 EQU 0x4000600e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_USBIO_CR0\r
+CYREG_USB_USBIO_CR0 EQU 0x40006010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_USBIO_CR1\r
+CYREG_USB_USBIO_CR1 EQU 0x40006012\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_DYN_RECONFIG\r
+CYREG_USB_DYN_RECONFIG EQU 0x40006014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SOF0\r
+CYREG_USB_SOF0 EQU 0x40006018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SOF1\r
+CYREG_USB_SOF1 EQU 0x40006019\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP2_BASE\r
+CYDEV_USB_SIE_EP2_BASE EQU 0x4000601c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP2_SIZE\r
+CYDEV_USB_SIE_EP2_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP2_CNT0\r
+CYREG_USB_SIE_EP2_CNT0 EQU 0x4000601c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP2_CNT1\r
+CYREG_USB_SIE_EP2_CNT1 EQU 0x4000601d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP2_CR0\r
+CYREG_USB_SIE_EP2_CR0 EQU 0x4000601e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_EP0_CR\r
+CYREG_USB_EP0_CR EQU 0x40006028\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_EP0_CNT\r
+CYREG_USB_EP0_CNT EQU 0x40006029\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP3_BASE\r
+CYDEV_USB_SIE_EP3_BASE EQU 0x4000602c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP3_SIZE\r
+CYDEV_USB_SIE_EP3_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP3_CNT0\r
+CYREG_USB_SIE_EP3_CNT0 EQU 0x4000602c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP3_CNT1\r
+CYREG_USB_SIE_EP3_CNT1 EQU 0x4000602d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP3_CR0\r
+CYREG_USB_SIE_EP3_CR0 EQU 0x4000602e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP4_BASE\r
+CYDEV_USB_SIE_EP4_BASE EQU 0x4000603c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP4_SIZE\r
+CYDEV_USB_SIE_EP4_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP4_CNT0\r
+CYREG_USB_SIE_EP4_CNT0 EQU 0x4000603c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP4_CNT1\r
+CYREG_USB_SIE_EP4_CNT1 EQU 0x4000603d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP4_CR0\r
+CYREG_USB_SIE_EP4_CR0 EQU 0x4000603e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP5_BASE\r
+CYDEV_USB_SIE_EP5_BASE EQU 0x4000604c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP5_SIZE\r
+CYDEV_USB_SIE_EP5_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP5_CNT0\r
+CYREG_USB_SIE_EP5_CNT0 EQU 0x4000604c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP5_CNT1\r
+CYREG_USB_SIE_EP5_CNT1 EQU 0x4000604d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP5_CR0\r
+CYREG_USB_SIE_EP5_CR0 EQU 0x4000604e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP6_BASE\r
+CYDEV_USB_SIE_EP6_BASE EQU 0x4000605c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP6_SIZE\r
+CYDEV_USB_SIE_EP6_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP6_CNT0\r
+CYREG_USB_SIE_EP6_CNT0 EQU 0x4000605c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP6_CNT1\r
+CYREG_USB_SIE_EP6_CNT1 EQU 0x4000605d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP6_CR0\r
+CYREG_USB_SIE_EP6_CR0 EQU 0x4000605e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP7_BASE\r
+CYDEV_USB_SIE_EP7_BASE EQU 0x4000606c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP7_SIZE\r
+CYDEV_USB_SIE_EP7_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP7_CNT0\r
+CYREG_USB_SIE_EP7_CNT0 EQU 0x4000606c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP7_CNT1\r
+CYREG_USB_SIE_EP7_CNT1 EQU 0x4000606d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP7_CR0\r
+CYREG_USB_SIE_EP7_CR0 EQU 0x4000606e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP8_BASE\r
+CYDEV_USB_SIE_EP8_BASE EQU 0x4000607c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_SIE_EP8_SIZE\r
+CYDEV_USB_SIE_EP8_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP8_CNT0\r
+CYREG_USB_SIE_EP8_CNT0 EQU 0x4000607c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP8_CNT1\r
+CYREG_USB_SIE_EP8_CNT1 EQU 0x4000607d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_SIE_EP8_CR0\r
+CYREG_USB_SIE_EP8_CR0 EQU 0x4000607e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP1_BASE\r
+CYDEV_USB_ARB_EP1_BASE EQU 0x40006080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SIZE\r
+CYDEV_USB_ARB_EP1_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP1_CFG\r
+CYREG_USB_ARB_EP1_CFG EQU 0x40006080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP1_INT_EN\r
+CYREG_USB_ARB_EP1_INT_EN EQU 0x40006081\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP1_SR\r
+CYREG_USB_ARB_EP1_SR EQU 0x40006082\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW1_BASE\r
+CYDEV_USB_ARB_RW1_BASE EQU 0x40006084\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW1_SIZE\r
+CYDEV_USB_ARB_RW1_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW1_WA\r
+CYREG_USB_ARB_RW1_WA EQU 0x40006084\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW1_WA_MSB\r
+CYREG_USB_ARB_RW1_WA_MSB EQU 0x40006085\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW1_RA\r
+CYREG_USB_ARB_RW1_RA EQU 0x40006086\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW1_RA_MSB\r
+CYREG_USB_ARB_RW1_RA_MSB EQU 0x40006087\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW1_DR\r
+CYREG_USB_ARB_RW1_DR EQU 0x40006088\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_BUF_SIZE\r
+CYREG_USB_BUF_SIZE EQU 0x4000608c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_EP_ACTIVE\r
+CYREG_USB_EP_ACTIVE EQU 0x4000608e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_EP_TYPE\r
+CYREG_USB_EP_TYPE EQU 0x4000608f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP2_BASE\r
+CYDEV_USB_ARB_EP2_BASE EQU 0x40006090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SIZE\r
+CYDEV_USB_ARB_EP2_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP2_CFG\r
+CYREG_USB_ARB_EP2_CFG EQU 0x40006090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP2_INT_EN\r
+CYREG_USB_ARB_EP2_INT_EN EQU 0x40006091\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP2_SR\r
+CYREG_USB_ARB_EP2_SR EQU 0x40006092\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW2_BASE\r
+CYDEV_USB_ARB_RW2_BASE EQU 0x40006094\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW2_SIZE\r
+CYDEV_USB_ARB_RW2_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW2_WA\r
+CYREG_USB_ARB_RW2_WA EQU 0x40006094\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW2_WA_MSB\r
+CYREG_USB_ARB_RW2_WA_MSB EQU 0x40006095\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW2_RA\r
+CYREG_USB_ARB_RW2_RA EQU 0x40006096\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW2_RA_MSB\r
+CYREG_USB_ARB_RW2_RA_MSB EQU 0x40006097\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW2_DR\r
+CYREG_USB_ARB_RW2_DR EQU 0x40006098\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_CFG\r
+CYREG_USB_ARB_CFG EQU 0x4000609c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_USB_CLK_EN\r
+CYREG_USB_USB_CLK_EN EQU 0x4000609d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_INT_EN\r
+CYREG_USB_ARB_INT_EN EQU 0x4000609e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_INT_SR\r
+CYREG_USB_ARB_INT_SR EQU 0x4000609f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP3_BASE\r
+CYDEV_USB_ARB_EP3_BASE EQU 0x400060a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SIZE\r
+CYDEV_USB_ARB_EP3_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP3_CFG\r
+CYREG_USB_ARB_EP3_CFG EQU 0x400060a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP3_INT_EN\r
+CYREG_USB_ARB_EP3_INT_EN EQU 0x400060a1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP3_SR\r
+CYREG_USB_ARB_EP3_SR EQU 0x400060a2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW3_BASE\r
+CYDEV_USB_ARB_RW3_BASE EQU 0x400060a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW3_SIZE\r
+CYDEV_USB_ARB_RW3_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW3_WA\r
+CYREG_USB_ARB_RW3_WA EQU 0x400060a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW3_WA_MSB\r
+CYREG_USB_ARB_RW3_WA_MSB EQU 0x400060a5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW3_RA\r
+CYREG_USB_ARB_RW3_RA EQU 0x400060a6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW3_RA_MSB\r
+CYREG_USB_ARB_RW3_RA_MSB EQU 0x400060a7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW3_DR\r
+CYREG_USB_ARB_RW3_DR EQU 0x400060a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_CWA\r
+CYREG_USB_CWA EQU 0x400060ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_CWA_MSB\r
+CYREG_USB_CWA_MSB EQU 0x400060ad\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP4_BASE\r
+CYDEV_USB_ARB_EP4_BASE EQU 0x400060b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SIZE\r
+CYDEV_USB_ARB_EP4_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP4_CFG\r
+CYREG_USB_ARB_EP4_CFG EQU 0x400060b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP4_INT_EN\r
+CYREG_USB_ARB_EP4_INT_EN EQU 0x400060b1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP4_SR\r
+CYREG_USB_ARB_EP4_SR EQU 0x400060b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW4_BASE\r
+CYDEV_USB_ARB_RW4_BASE EQU 0x400060b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW4_SIZE\r
+CYDEV_USB_ARB_RW4_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW4_WA\r
+CYREG_USB_ARB_RW4_WA EQU 0x400060b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW4_WA_MSB\r
+CYREG_USB_ARB_RW4_WA_MSB EQU 0x400060b5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW4_RA\r
+CYREG_USB_ARB_RW4_RA EQU 0x400060b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW4_RA_MSB\r
+CYREG_USB_ARB_RW4_RA_MSB EQU 0x400060b7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW4_DR\r
+CYREG_USB_ARB_RW4_DR EQU 0x400060b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_DMA_THRES\r
+CYREG_USB_DMA_THRES EQU 0x400060bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_DMA_THRES_MSB\r
+CYREG_USB_DMA_THRES_MSB EQU 0x400060bd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP5_BASE\r
+CYDEV_USB_ARB_EP5_BASE EQU 0x400060c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SIZE\r
+CYDEV_USB_ARB_EP5_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP5_CFG\r
+CYREG_USB_ARB_EP5_CFG EQU 0x400060c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP5_INT_EN\r
+CYREG_USB_ARB_EP5_INT_EN EQU 0x400060c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP5_SR\r
+CYREG_USB_ARB_EP5_SR EQU 0x400060c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW5_BASE\r
+CYDEV_USB_ARB_RW5_BASE EQU 0x400060c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW5_SIZE\r
+CYDEV_USB_ARB_RW5_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW5_WA\r
+CYREG_USB_ARB_RW5_WA EQU 0x400060c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW5_WA_MSB\r
+CYREG_USB_ARB_RW5_WA_MSB EQU 0x400060c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW5_RA\r
+CYREG_USB_ARB_RW5_RA EQU 0x400060c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW5_RA_MSB\r
+CYREG_USB_ARB_RW5_RA_MSB EQU 0x400060c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW5_DR\r
+CYREG_USB_ARB_RW5_DR EQU 0x400060c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_BUS_RST_CNT\r
+CYREG_USB_BUS_RST_CNT EQU 0x400060cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP6_BASE\r
+CYDEV_USB_ARB_EP6_BASE EQU 0x400060d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SIZE\r
+CYDEV_USB_ARB_EP6_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP6_CFG\r
+CYREG_USB_ARB_EP6_CFG EQU 0x400060d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP6_INT_EN\r
+CYREG_USB_ARB_EP6_INT_EN EQU 0x400060d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP6_SR\r
+CYREG_USB_ARB_EP6_SR EQU 0x400060d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW6_BASE\r
+CYDEV_USB_ARB_RW6_BASE EQU 0x400060d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW6_SIZE\r
+CYDEV_USB_ARB_RW6_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW6_WA\r
+CYREG_USB_ARB_RW6_WA EQU 0x400060d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW6_WA_MSB\r
+CYREG_USB_ARB_RW6_WA_MSB EQU 0x400060d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW6_RA\r
+CYREG_USB_ARB_RW6_RA EQU 0x400060d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW6_RA_MSB\r
+CYREG_USB_ARB_RW6_RA_MSB EQU 0x400060d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW6_DR\r
+CYREG_USB_ARB_RW6_DR EQU 0x400060d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP7_BASE\r
+CYDEV_USB_ARB_EP7_BASE EQU 0x400060e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SIZE\r
+CYDEV_USB_ARB_EP7_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP7_CFG\r
+CYREG_USB_ARB_EP7_CFG EQU 0x400060e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP7_INT_EN\r
+CYREG_USB_ARB_EP7_INT_EN EQU 0x400060e1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP7_SR\r
+CYREG_USB_ARB_EP7_SR EQU 0x400060e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW7_BASE\r
+CYDEV_USB_ARB_RW7_BASE EQU 0x400060e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW7_SIZE\r
+CYDEV_USB_ARB_RW7_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW7_WA\r
+CYREG_USB_ARB_RW7_WA EQU 0x400060e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW7_WA_MSB\r
+CYREG_USB_ARB_RW7_WA_MSB EQU 0x400060e5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW7_RA\r
+CYREG_USB_ARB_RW7_RA EQU 0x400060e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW7_RA_MSB\r
+CYREG_USB_ARB_RW7_RA_MSB EQU 0x400060e7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW7_DR\r
+CYREG_USB_ARB_RW7_DR EQU 0x400060e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP8_BASE\r
+CYDEV_USB_ARB_EP8_BASE EQU 0x400060f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SIZE\r
+CYDEV_USB_ARB_EP8_SIZE EQU 0x00000003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP8_CFG\r
+CYREG_USB_ARB_EP8_CFG EQU 0x400060f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP8_INT_EN\r
+CYREG_USB_ARB_EP8_INT_EN EQU 0x400060f1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_EP8_SR\r
+CYREG_USB_ARB_EP8_SR EQU 0x400060f2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW8_BASE\r
+CYDEV_USB_ARB_RW8_BASE EQU 0x400060f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_ARB_RW8_SIZE\r
+CYDEV_USB_ARB_RW8_SIZE EQU 0x00000005\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW8_WA\r
+CYREG_USB_ARB_RW8_WA EQU 0x400060f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW8_WA_MSB\r
+CYREG_USB_ARB_RW8_WA_MSB EQU 0x400060f5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW8_RA\r
+CYREG_USB_ARB_RW8_RA EQU 0x400060f6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW8_RA_MSB\r
+CYREG_USB_ARB_RW8_RA_MSB EQU 0x400060f7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_ARB_RW8_DR\r
+CYREG_USB_ARB_RW8_DR EQU 0x400060f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_MEM_BASE\r
+CYDEV_USB_MEM_BASE EQU 0x40006100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_USB_MEM_SIZE\r
+CYDEV_USB_MEM_SIZE EQU 0x00000200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_MEM_DATA_MBASE\r
+CYREG_USB_MEM_DATA_MBASE EQU 0x40006100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_USB_MEM_DATA_MSIZE\r
+CYREG_USB_MEM_DATA_MSIZE EQU 0x00000200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_BASE\r
+CYDEV_UWRK_BASE EQU 0x40006400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_SIZE\r
+CYDEV_UWRK_SIZE EQU 0x00000b60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_BASE\r
+CYDEV_UWRK_UWRK8_BASE EQU 0x40006400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_SIZE\r
+CYDEV_UWRK_UWRK8_SIZE EQU 0x000003b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_BASE\r
+CYDEV_UWRK_UWRK8_B0_BASE EQU 0x40006400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_SIZE\r
+CYDEV_UWRK_UWRK8_B0_SIZE EQU 0x000000b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_A0\r
+CYREG_B0_UDB00_A0 EQU 0x40006400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_A0\r
+CYREG_B0_UDB01_A0 EQU 0x40006401\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_A0\r
+CYREG_B0_UDB02_A0 EQU 0x40006402\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_A0\r
+CYREG_B0_UDB03_A0 EQU 0x40006403\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_A0\r
+CYREG_B0_UDB04_A0 EQU 0x40006404\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_A0\r
+CYREG_B0_UDB05_A0 EQU 0x40006405\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_A0\r
+CYREG_B0_UDB06_A0 EQU 0x40006406\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_A0\r
+CYREG_B0_UDB07_A0 EQU 0x40006407\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_A0\r
+CYREG_B0_UDB08_A0 EQU 0x40006408\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_A0\r
+CYREG_B0_UDB09_A0 EQU 0x40006409\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_A0\r
+CYREG_B0_UDB10_A0 EQU 0x4000640a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_A0\r
+CYREG_B0_UDB11_A0 EQU 0x4000640b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_A0\r
+CYREG_B0_UDB12_A0 EQU 0x4000640c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_A0\r
+CYREG_B0_UDB13_A0 EQU 0x4000640d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_A0\r
+CYREG_B0_UDB14_A0 EQU 0x4000640e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB15_A0\r
+CYREG_B0_UDB15_A0 EQU 0x4000640f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_A1\r
+CYREG_B0_UDB00_A1 EQU 0x40006410\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_A1\r
+CYREG_B0_UDB01_A1 EQU 0x40006411\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_A1\r
+CYREG_B0_UDB02_A1 EQU 0x40006412\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_A1\r
+CYREG_B0_UDB03_A1 EQU 0x40006413\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_A1\r
+CYREG_B0_UDB04_A1 EQU 0x40006414\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_A1\r
+CYREG_B0_UDB05_A1 EQU 0x40006415\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_A1\r
+CYREG_B0_UDB06_A1 EQU 0x40006416\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_A1\r
+CYREG_B0_UDB07_A1 EQU 0x40006417\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_A1\r
+CYREG_B0_UDB08_A1 EQU 0x40006418\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_A1\r
+CYREG_B0_UDB09_A1 EQU 0x40006419\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_A1\r
+CYREG_B0_UDB10_A1 EQU 0x4000641a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_A1\r
+CYREG_B0_UDB11_A1 EQU 0x4000641b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_A1\r
+CYREG_B0_UDB12_A1 EQU 0x4000641c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_A1\r
+CYREG_B0_UDB13_A1 EQU 0x4000641d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_A1\r
+CYREG_B0_UDB14_A1 EQU 0x4000641e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB15_A1\r
+CYREG_B0_UDB15_A1 EQU 0x4000641f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_D0\r
+CYREG_B0_UDB00_D0 EQU 0x40006420\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_D0\r
+CYREG_B0_UDB01_D0 EQU 0x40006421\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_D0\r
+CYREG_B0_UDB02_D0 EQU 0x40006422\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_D0\r
+CYREG_B0_UDB03_D0 EQU 0x40006423\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_D0\r
+CYREG_B0_UDB04_D0 EQU 0x40006424\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_D0\r
+CYREG_B0_UDB05_D0 EQU 0x40006425\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_D0\r
+CYREG_B0_UDB06_D0 EQU 0x40006426\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_D0\r
+CYREG_B0_UDB07_D0 EQU 0x40006427\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_D0\r
+CYREG_B0_UDB08_D0 EQU 0x40006428\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_D0\r
+CYREG_B0_UDB09_D0 EQU 0x40006429\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_D0\r
+CYREG_B0_UDB10_D0 EQU 0x4000642a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_D0\r
+CYREG_B0_UDB11_D0 EQU 0x4000642b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_D0\r
+CYREG_B0_UDB12_D0 EQU 0x4000642c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_D0\r
+CYREG_B0_UDB13_D0 EQU 0x4000642d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_D0\r
+CYREG_B0_UDB14_D0 EQU 0x4000642e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB15_D0\r
+CYREG_B0_UDB15_D0 EQU 0x4000642f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_D1\r
+CYREG_B0_UDB00_D1 EQU 0x40006430\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_D1\r
+CYREG_B0_UDB01_D1 EQU 0x40006431\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_D1\r
+CYREG_B0_UDB02_D1 EQU 0x40006432\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_D1\r
+CYREG_B0_UDB03_D1 EQU 0x40006433\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_D1\r
+CYREG_B0_UDB04_D1 EQU 0x40006434\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_D1\r
+CYREG_B0_UDB05_D1 EQU 0x40006435\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_D1\r
+CYREG_B0_UDB06_D1 EQU 0x40006436\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_D1\r
+CYREG_B0_UDB07_D1 EQU 0x40006437\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_D1\r
+CYREG_B0_UDB08_D1 EQU 0x40006438\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_D1\r
+CYREG_B0_UDB09_D1 EQU 0x40006439\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_D1\r
+CYREG_B0_UDB10_D1 EQU 0x4000643a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_D1\r
+CYREG_B0_UDB11_D1 EQU 0x4000643b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_D1\r
+CYREG_B0_UDB12_D1 EQU 0x4000643c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_D1\r
+CYREG_B0_UDB13_D1 EQU 0x4000643d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_D1\r
+CYREG_B0_UDB14_D1 EQU 0x4000643e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB15_D1\r
+CYREG_B0_UDB15_D1 EQU 0x4000643f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_F0\r
+CYREG_B0_UDB00_F0 EQU 0x40006440\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_F0\r
+CYREG_B0_UDB01_F0 EQU 0x40006441\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_F0\r
+CYREG_B0_UDB02_F0 EQU 0x40006442\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_F0\r
+CYREG_B0_UDB03_F0 EQU 0x40006443\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_F0\r
+CYREG_B0_UDB04_F0 EQU 0x40006444\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_F0\r
+CYREG_B0_UDB05_F0 EQU 0x40006445\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_F0\r
+CYREG_B0_UDB06_F0 EQU 0x40006446\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_F0\r
+CYREG_B0_UDB07_F0 EQU 0x40006447\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_F0\r
+CYREG_B0_UDB08_F0 EQU 0x40006448\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_F0\r
+CYREG_B0_UDB09_F0 EQU 0x40006449\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_F0\r
+CYREG_B0_UDB10_F0 EQU 0x4000644a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_F0\r
+CYREG_B0_UDB11_F0 EQU 0x4000644b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_F0\r
+CYREG_B0_UDB12_F0 EQU 0x4000644c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_F0\r
+CYREG_B0_UDB13_F0 EQU 0x4000644d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_F0\r
+CYREG_B0_UDB14_F0 EQU 0x4000644e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB15_F0\r
+CYREG_B0_UDB15_F0 EQU 0x4000644f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_F1\r
+CYREG_B0_UDB00_F1 EQU 0x40006450\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_F1\r
+CYREG_B0_UDB01_F1 EQU 0x40006451\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_F1\r
+CYREG_B0_UDB02_F1 EQU 0x40006452\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_F1\r
+CYREG_B0_UDB03_F1 EQU 0x40006453\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_F1\r
+CYREG_B0_UDB04_F1 EQU 0x40006454\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_F1\r
+CYREG_B0_UDB05_F1 EQU 0x40006455\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_F1\r
+CYREG_B0_UDB06_F1 EQU 0x40006456\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_F1\r
+CYREG_B0_UDB07_F1 EQU 0x40006457\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_F1\r
+CYREG_B0_UDB08_F1 EQU 0x40006458\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_F1\r
+CYREG_B0_UDB09_F1 EQU 0x40006459\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_F1\r
+CYREG_B0_UDB10_F1 EQU 0x4000645a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_F1\r
+CYREG_B0_UDB11_F1 EQU 0x4000645b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_F1\r
+CYREG_B0_UDB12_F1 EQU 0x4000645c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_F1\r
+CYREG_B0_UDB13_F1 EQU 0x4000645d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_F1\r
+CYREG_B0_UDB14_F1 EQU 0x4000645e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB15_F1\r
+CYREG_B0_UDB15_F1 EQU 0x4000645f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_ST\r
+CYREG_B0_UDB00_ST EQU 0x40006460\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_ST\r
+CYREG_B0_UDB01_ST EQU 0x40006461\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_ST\r
+CYREG_B0_UDB02_ST EQU 0x40006462\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_ST\r
+CYREG_B0_UDB03_ST EQU 0x40006463\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_ST\r
+CYREG_B0_UDB04_ST EQU 0x40006464\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_ST\r
+CYREG_B0_UDB05_ST EQU 0x40006465\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_ST\r
+CYREG_B0_UDB06_ST EQU 0x40006466\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_ST\r
+CYREG_B0_UDB07_ST EQU 0x40006467\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_ST\r
+CYREG_B0_UDB08_ST EQU 0x40006468\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_ST\r
+CYREG_B0_UDB09_ST EQU 0x40006469\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_ST\r
+CYREG_B0_UDB10_ST EQU 0x4000646a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_ST\r
+CYREG_B0_UDB11_ST EQU 0x4000646b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_ST\r
+CYREG_B0_UDB12_ST EQU 0x4000646c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_ST\r
+CYREG_B0_UDB13_ST EQU 0x4000646d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_ST\r
+CYREG_B0_UDB14_ST EQU 0x4000646e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB15_ST\r
+CYREG_B0_UDB15_ST EQU 0x4000646f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_CTL\r
+CYREG_B0_UDB00_CTL EQU 0x40006470\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_CTL\r
+CYREG_B0_UDB01_CTL EQU 0x40006471\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_CTL\r
+CYREG_B0_UDB02_CTL EQU 0x40006472\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_CTL\r
+CYREG_B0_UDB03_CTL EQU 0x40006473\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_CTL\r
+CYREG_B0_UDB04_CTL EQU 0x40006474\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_CTL\r
+CYREG_B0_UDB05_CTL EQU 0x40006475\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_CTL\r
+CYREG_B0_UDB06_CTL EQU 0x40006476\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_CTL\r
+CYREG_B0_UDB07_CTL EQU 0x40006477\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_CTL\r
+CYREG_B0_UDB08_CTL EQU 0x40006478\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_CTL\r
+CYREG_B0_UDB09_CTL EQU 0x40006479\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_CTL\r
+CYREG_B0_UDB10_CTL EQU 0x4000647a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_CTL\r
+CYREG_B0_UDB11_CTL EQU 0x4000647b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_CTL\r
+CYREG_B0_UDB12_CTL EQU 0x4000647c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_CTL\r
+CYREG_B0_UDB13_CTL EQU 0x4000647d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_CTL\r
+CYREG_B0_UDB14_CTL EQU 0x4000647e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB15_CTL\r
+CYREG_B0_UDB15_CTL EQU 0x4000647f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_MSK\r
+CYREG_B0_UDB00_MSK EQU 0x40006480\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_MSK\r
+CYREG_B0_UDB01_MSK EQU 0x40006481\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_MSK\r
+CYREG_B0_UDB02_MSK EQU 0x40006482\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_MSK\r
+CYREG_B0_UDB03_MSK EQU 0x40006483\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_MSK\r
+CYREG_B0_UDB04_MSK EQU 0x40006484\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_MSK\r
+CYREG_B0_UDB05_MSK EQU 0x40006485\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_MSK\r
+CYREG_B0_UDB06_MSK EQU 0x40006486\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_MSK\r
+CYREG_B0_UDB07_MSK EQU 0x40006487\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_MSK\r
+CYREG_B0_UDB08_MSK EQU 0x40006488\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_MSK\r
+CYREG_B0_UDB09_MSK EQU 0x40006489\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_MSK\r
+CYREG_B0_UDB10_MSK EQU 0x4000648a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_MSK\r
+CYREG_B0_UDB11_MSK EQU 0x4000648b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_MSK\r
+CYREG_B0_UDB12_MSK EQU 0x4000648c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_MSK\r
+CYREG_B0_UDB13_MSK EQU 0x4000648d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_MSK\r
+CYREG_B0_UDB14_MSK EQU 0x4000648e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB15_MSK\r
+CYREG_B0_UDB15_MSK EQU 0x4000648f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_ACTL\r
+CYREG_B0_UDB00_ACTL EQU 0x40006490\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_ACTL\r
+CYREG_B0_UDB01_ACTL EQU 0x40006491\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_ACTL\r
+CYREG_B0_UDB02_ACTL EQU 0x40006492\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_ACTL\r
+CYREG_B0_UDB03_ACTL EQU 0x40006493\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_ACTL\r
+CYREG_B0_UDB04_ACTL EQU 0x40006494\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_ACTL\r
+CYREG_B0_UDB05_ACTL EQU 0x40006495\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_ACTL\r
+CYREG_B0_UDB06_ACTL EQU 0x40006496\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_ACTL\r
+CYREG_B0_UDB07_ACTL EQU 0x40006497\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_ACTL\r
+CYREG_B0_UDB08_ACTL EQU 0x40006498\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_ACTL\r
+CYREG_B0_UDB09_ACTL EQU 0x40006499\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_ACTL\r
+CYREG_B0_UDB10_ACTL EQU 0x4000649a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_ACTL\r
+CYREG_B0_UDB11_ACTL EQU 0x4000649b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_ACTL\r
+CYREG_B0_UDB12_ACTL EQU 0x4000649c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_ACTL\r
+CYREG_B0_UDB13_ACTL EQU 0x4000649d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_ACTL\r
+CYREG_B0_UDB14_ACTL EQU 0x4000649e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB15_ACTL\r
+CYREG_B0_UDB15_ACTL EQU 0x4000649f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_MC\r
+CYREG_B0_UDB00_MC EQU 0x400064a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_MC\r
+CYREG_B0_UDB01_MC EQU 0x400064a1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_MC\r
+CYREG_B0_UDB02_MC EQU 0x400064a2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_MC\r
+CYREG_B0_UDB03_MC EQU 0x400064a3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_MC\r
+CYREG_B0_UDB04_MC EQU 0x400064a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_MC\r
+CYREG_B0_UDB05_MC EQU 0x400064a5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_MC\r
+CYREG_B0_UDB06_MC EQU 0x400064a6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_MC\r
+CYREG_B0_UDB07_MC EQU 0x400064a7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_MC\r
+CYREG_B0_UDB08_MC EQU 0x400064a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_MC\r
+CYREG_B0_UDB09_MC EQU 0x400064a9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_MC\r
+CYREG_B0_UDB10_MC EQU 0x400064aa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_MC\r
+CYREG_B0_UDB11_MC EQU 0x400064ab\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_MC\r
+CYREG_B0_UDB12_MC EQU 0x400064ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_MC\r
+CYREG_B0_UDB13_MC EQU 0x400064ad\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_MC\r
+CYREG_B0_UDB14_MC EQU 0x400064ae\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB15_MC\r
+CYREG_B0_UDB15_MC EQU 0x400064af\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_BASE\r
+CYDEV_UWRK_UWRK8_B1_BASE EQU 0x40006500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_SIZE\r
+CYDEV_UWRK_UWRK8_B1_SIZE EQU 0x000000b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_A0\r
+CYREG_B1_UDB04_A0 EQU 0x40006504\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_A0\r
+CYREG_B1_UDB05_A0 EQU 0x40006505\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_A0\r
+CYREG_B1_UDB06_A0 EQU 0x40006506\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_A0\r
+CYREG_B1_UDB07_A0 EQU 0x40006507\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_A0\r
+CYREG_B1_UDB08_A0 EQU 0x40006508\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_A0\r
+CYREG_B1_UDB09_A0 EQU 0x40006509\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_A0\r
+CYREG_B1_UDB10_A0 EQU 0x4000650a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_A0\r
+CYREG_B1_UDB11_A0 EQU 0x4000650b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_A1\r
+CYREG_B1_UDB04_A1 EQU 0x40006514\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_A1\r
+CYREG_B1_UDB05_A1 EQU 0x40006515\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_A1\r
+CYREG_B1_UDB06_A1 EQU 0x40006516\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_A1\r
+CYREG_B1_UDB07_A1 EQU 0x40006517\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_A1\r
+CYREG_B1_UDB08_A1 EQU 0x40006518\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_A1\r
+CYREG_B1_UDB09_A1 EQU 0x40006519\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_A1\r
+CYREG_B1_UDB10_A1 EQU 0x4000651a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_A1\r
+CYREG_B1_UDB11_A1 EQU 0x4000651b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_D0\r
+CYREG_B1_UDB04_D0 EQU 0x40006524\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_D0\r
+CYREG_B1_UDB05_D0 EQU 0x40006525\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_D0\r
+CYREG_B1_UDB06_D0 EQU 0x40006526\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_D0\r
+CYREG_B1_UDB07_D0 EQU 0x40006527\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_D0\r
+CYREG_B1_UDB08_D0 EQU 0x40006528\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_D0\r
+CYREG_B1_UDB09_D0 EQU 0x40006529\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_D0\r
+CYREG_B1_UDB10_D0 EQU 0x4000652a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_D0\r
+CYREG_B1_UDB11_D0 EQU 0x4000652b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_D1\r
+CYREG_B1_UDB04_D1 EQU 0x40006534\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_D1\r
+CYREG_B1_UDB05_D1 EQU 0x40006535\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_D1\r
+CYREG_B1_UDB06_D1 EQU 0x40006536\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_D1\r
+CYREG_B1_UDB07_D1 EQU 0x40006537\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_D1\r
+CYREG_B1_UDB08_D1 EQU 0x40006538\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_D1\r
+CYREG_B1_UDB09_D1 EQU 0x40006539\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_D1\r
+CYREG_B1_UDB10_D1 EQU 0x4000653a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_D1\r
+CYREG_B1_UDB11_D1 EQU 0x4000653b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_F0\r
+CYREG_B1_UDB04_F0 EQU 0x40006544\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_F0\r
+CYREG_B1_UDB05_F0 EQU 0x40006545\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_F0\r
+CYREG_B1_UDB06_F0 EQU 0x40006546\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_F0\r
+CYREG_B1_UDB07_F0 EQU 0x40006547\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_F0\r
+CYREG_B1_UDB08_F0 EQU 0x40006548\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_F0\r
+CYREG_B1_UDB09_F0 EQU 0x40006549\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_F0\r
+CYREG_B1_UDB10_F0 EQU 0x4000654a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_F0\r
+CYREG_B1_UDB11_F0 EQU 0x4000654b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_F1\r
+CYREG_B1_UDB04_F1 EQU 0x40006554\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_F1\r
+CYREG_B1_UDB05_F1 EQU 0x40006555\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_F1\r
+CYREG_B1_UDB06_F1 EQU 0x40006556\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_F1\r
+CYREG_B1_UDB07_F1 EQU 0x40006557\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_F1\r
+CYREG_B1_UDB08_F1 EQU 0x40006558\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_F1\r
+CYREG_B1_UDB09_F1 EQU 0x40006559\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_F1\r
+CYREG_B1_UDB10_F1 EQU 0x4000655a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_F1\r
+CYREG_B1_UDB11_F1 EQU 0x4000655b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_ST\r
+CYREG_B1_UDB04_ST EQU 0x40006564\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_ST\r
+CYREG_B1_UDB05_ST EQU 0x40006565\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_ST\r
+CYREG_B1_UDB06_ST EQU 0x40006566\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_ST\r
+CYREG_B1_UDB07_ST EQU 0x40006567\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_ST\r
+CYREG_B1_UDB08_ST EQU 0x40006568\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_ST\r
+CYREG_B1_UDB09_ST EQU 0x40006569\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_ST\r
+CYREG_B1_UDB10_ST EQU 0x4000656a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_ST\r
+CYREG_B1_UDB11_ST EQU 0x4000656b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_CTL\r
+CYREG_B1_UDB04_CTL EQU 0x40006574\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_CTL\r
+CYREG_B1_UDB05_CTL EQU 0x40006575\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_CTL\r
+CYREG_B1_UDB06_CTL EQU 0x40006576\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_CTL\r
+CYREG_B1_UDB07_CTL EQU 0x40006577\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_CTL\r
+CYREG_B1_UDB08_CTL EQU 0x40006578\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_CTL\r
+CYREG_B1_UDB09_CTL EQU 0x40006579\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_CTL\r
+CYREG_B1_UDB10_CTL EQU 0x4000657a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_CTL\r
+CYREG_B1_UDB11_CTL EQU 0x4000657b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_MSK\r
+CYREG_B1_UDB04_MSK EQU 0x40006584\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_MSK\r
+CYREG_B1_UDB05_MSK EQU 0x40006585\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_MSK\r
+CYREG_B1_UDB06_MSK EQU 0x40006586\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_MSK\r
+CYREG_B1_UDB07_MSK EQU 0x40006587\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_MSK\r
+CYREG_B1_UDB08_MSK EQU 0x40006588\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_MSK\r
+CYREG_B1_UDB09_MSK EQU 0x40006589\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_MSK\r
+CYREG_B1_UDB10_MSK EQU 0x4000658a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_MSK\r
+CYREG_B1_UDB11_MSK EQU 0x4000658b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_ACTL\r
+CYREG_B1_UDB04_ACTL EQU 0x40006594\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_ACTL\r
+CYREG_B1_UDB05_ACTL EQU 0x40006595\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_ACTL\r
+CYREG_B1_UDB06_ACTL EQU 0x40006596\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_ACTL\r
+CYREG_B1_UDB07_ACTL EQU 0x40006597\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_ACTL\r
+CYREG_B1_UDB08_ACTL EQU 0x40006598\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_ACTL\r
+CYREG_B1_UDB09_ACTL EQU 0x40006599\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_ACTL\r
+CYREG_B1_UDB10_ACTL EQU 0x4000659a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_ACTL\r
+CYREG_B1_UDB11_ACTL EQU 0x4000659b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_MC\r
+CYREG_B1_UDB04_MC EQU 0x400065a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_MC\r
+CYREG_B1_UDB05_MC EQU 0x400065a5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_MC\r
+CYREG_B1_UDB06_MC EQU 0x400065a6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_MC\r
+CYREG_B1_UDB07_MC EQU 0x400065a7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_MC\r
+CYREG_B1_UDB08_MC EQU 0x400065a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_MC\r
+CYREG_B1_UDB09_MC EQU 0x400065a9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_MC\r
+CYREG_B1_UDB10_MC EQU 0x400065aa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_MC\r
+CYREG_B1_UDB11_MC EQU 0x400065ab\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_BASE\r
+CYDEV_UWRK_UWRK16_BASE EQU 0x40006800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_SIZE\r
+CYDEV_UWRK_UWRK16_SIZE EQU 0x00000760\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_BASE\r
+CYDEV_UWRK_UWRK16_CAT_BASE EQU 0x40006800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_SIZE\r
+CYDEV_UWRK_UWRK16_CAT_SIZE EQU 0x00000760\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_BASE\r
+CYDEV_UWRK_UWRK16_CAT_B0_BASE EQU 0x40006800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_SIZE\r
+CYDEV_UWRK_UWRK16_CAT_B0_SIZE EQU 0x00000160\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_A0_A1\r
+CYREG_B0_UDB00_A0_A1 EQU 0x40006800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_A0_A1\r
+CYREG_B0_UDB01_A0_A1 EQU 0x40006802\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_A0_A1\r
+CYREG_B0_UDB02_A0_A1 EQU 0x40006804\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_A0_A1\r
+CYREG_B0_UDB03_A0_A1 EQU 0x40006806\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_A0_A1\r
+CYREG_B0_UDB04_A0_A1 EQU 0x40006808\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_A0_A1\r
+CYREG_B0_UDB05_A0_A1 EQU 0x4000680a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_A0_A1\r
+CYREG_B0_UDB06_A0_A1 EQU 0x4000680c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_A0_A1\r
+CYREG_B0_UDB07_A0_A1 EQU 0x4000680e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_A0_A1\r
+CYREG_B0_UDB08_A0_A1 EQU 0x40006810\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_A0_A1\r
+CYREG_B0_UDB09_A0_A1 EQU 0x40006812\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_A0_A1\r
+CYREG_B0_UDB10_A0_A1 EQU 0x40006814\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_A0_A1\r
+CYREG_B0_UDB11_A0_A1 EQU 0x40006816\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_A0_A1\r
+CYREG_B0_UDB12_A0_A1 EQU 0x40006818\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_A0_A1\r
+CYREG_B0_UDB13_A0_A1 EQU 0x4000681a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_A0_A1\r
+CYREG_B0_UDB14_A0_A1 EQU 0x4000681c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB15_A0_A1\r
+CYREG_B0_UDB15_A0_A1 EQU 0x4000681e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_D0_D1\r
+CYREG_B0_UDB00_D0_D1 EQU 0x40006840\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_D0_D1\r
+CYREG_B0_UDB01_D0_D1 EQU 0x40006842\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_D0_D1\r
+CYREG_B0_UDB02_D0_D1 EQU 0x40006844\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_D0_D1\r
+CYREG_B0_UDB03_D0_D1 EQU 0x40006846\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_D0_D1\r
+CYREG_B0_UDB04_D0_D1 EQU 0x40006848\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_D0_D1\r
+CYREG_B0_UDB05_D0_D1 EQU 0x4000684a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_D0_D1\r
+CYREG_B0_UDB06_D0_D1 EQU 0x4000684c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_D0_D1\r
+CYREG_B0_UDB07_D0_D1 EQU 0x4000684e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_D0_D1\r
+CYREG_B0_UDB08_D0_D1 EQU 0x40006850\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_D0_D1\r
+CYREG_B0_UDB09_D0_D1 EQU 0x40006852\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_D0_D1\r
+CYREG_B0_UDB10_D0_D1 EQU 0x40006854\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_D0_D1\r
+CYREG_B0_UDB11_D0_D1 EQU 0x40006856\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_D0_D1\r
+CYREG_B0_UDB12_D0_D1 EQU 0x40006858\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_D0_D1\r
+CYREG_B0_UDB13_D0_D1 EQU 0x4000685a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_D0_D1\r
+CYREG_B0_UDB14_D0_D1 EQU 0x4000685c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB15_D0_D1\r
+CYREG_B0_UDB15_D0_D1 EQU 0x4000685e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_F0_F1\r
+CYREG_B0_UDB00_F0_F1 EQU 0x40006880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_F0_F1\r
+CYREG_B0_UDB01_F0_F1 EQU 0x40006882\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_F0_F1\r
+CYREG_B0_UDB02_F0_F1 EQU 0x40006884\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_F0_F1\r
+CYREG_B0_UDB03_F0_F1 EQU 0x40006886\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_F0_F1\r
+CYREG_B0_UDB04_F0_F1 EQU 0x40006888\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_F0_F1\r
+CYREG_B0_UDB05_F0_F1 EQU 0x4000688a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_F0_F1\r
+CYREG_B0_UDB06_F0_F1 EQU 0x4000688c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_F0_F1\r
+CYREG_B0_UDB07_F0_F1 EQU 0x4000688e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_F0_F1\r
+CYREG_B0_UDB08_F0_F1 EQU 0x40006890\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_F0_F1\r
+CYREG_B0_UDB09_F0_F1 EQU 0x40006892\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_F0_F1\r
+CYREG_B0_UDB10_F0_F1 EQU 0x40006894\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_F0_F1\r
+CYREG_B0_UDB11_F0_F1 EQU 0x40006896\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_F0_F1\r
+CYREG_B0_UDB12_F0_F1 EQU 0x40006898\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_F0_F1\r
+CYREG_B0_UDB13_F0_F1 EQU 0x4000689a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_F0_F1\r
+CYREG_B0_UDB14_F0_F1 EQU 0x4000689c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB15_F0_F1\r
+CYREG_B0_UDB15_F0_F1 EQU 0x4000689e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_ST_CTL\r
+CYREG_B0_UDB00_ST_CTL EQU 0x400068c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_ST_CTL\r
+CYREG_B0_UDB01_ST_CTL EQU 0x400068c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_ST_CTL\r
+CYREG_B0_UDB02_ST_CTL EQU 0x400068c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_ST_CTL\r
+CYREG_B0_UDB03_ST_CTL EQU 0x400068c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_ST_CTL\r
+CYREG_B0_UDB04_ST_CTL EQU 0x400068c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_ST_CTL\r
+CYREG_B0_UDB05_ST_CTL EQU 0x400068ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_ST_CTL\r
+CYREG_B0_UDB06_ST_CTL EQU 0x400068cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_ST_CTL\r
+CYREG_B0_UDB07_ST_CTL EQU 0x400068ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_ST_CTL\r
+CYREG_B0_UDB08_ST_CTL EQU 0x400068d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_ST_CTL\r
+CYREG_B0_UDB09_ST_CTL EQU 0x400068d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_ST_CTL\r
+CYREG_B0_UDB10_ST_CTL EQU 0x400068d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_ST_CTL\r
+CYREG_B0_UDB11_ST_CTL EQU 0x400068d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_ST_CTL\r
+CYREG_B0_UDB12_ST_CTL EQU 0x400068d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_ST_CTL\r
+CYREG_B0_UDB13_ST_CTL EQU 0x400068da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_ST_CTL\r
+CYREG_B0_UDB14_ST_CTL EQU 0x400068dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB15_ST_CTL\r
+CYREG_B0_UDB15_ST_CTL EQU 0x400068de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_MSK_ACTL\r
+CYREG_B0_UDB00_MSK_ACTL EQU 0x40006900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_MSK_ACTL\r
+CYREG_B0_UDB01_MSK_ACTL EQU 0x40006902\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_MSK_ACTL\r
+CYREG_B0_UDB02_MSK_ACTL EQU 0x40006904\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_MSK_ACTL\r
+CYREG_B0_UDB03_MSK_ACTL EQU 0x40006906\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_MSK_ACTL\r
+CYREG_B0_UDB04_MSK_ACTL EQU 0x40006908\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_MSK_ACTL\r
+CYREG_B0_UDB05_MSK_ACTL EQU 0x4000690a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_MSK_ACTL\r
+CYREG_B0_UDB06_MSK_ACTL EQU 0x4000690c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_MSK_ACTL\r
+CYREG_B0_UDB07_MSK_ACTL EQU 0x4000690e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_MSK_ACTL\r
+CYREG_B0_UDB08_MSK_ACTL EQU 0x40006910\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_MSK_ACTL\r
+CYREG_B0_UDB09_MSK_ACTL EQU 0x40006912\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_MSK_ACTL\r
+CYREG_B0_UDB10_MSK_ACTL EQU 0x40006914\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_MSK_ACTL\r
+CYREG_B0_UDB11_MSK_ACTL EQU 0x40006916\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_MSK_ACTL\r
+CYREG_B0_UDB12_MSK_ACTL EQU 0x40006918\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_MSK_ACTL\r
+CYREG_B0_UDB13_MSK_ACTL EQU 0x4000691a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_MSK_ACTL\r
+CYREG_B0_UDB14_MSK_ACTL EQU 0x4000691c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB15_MSK_ACTL\r
+CYREG_B0_UDB15_MSK_ACTL EQU 0x4000691e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_MC_00\r
+CYREG_B0_UDB00_MC_00 EQU 0x40006940\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_MC_00\r
+CYREG_B0_UDB01_MC_00 EQU 0x40006942\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_MC_00\r
+CYREG_B0_UDB02_MC_00 EQU 0x40006944\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_MC_00\r
+CYREG_B0_UDB03_MC_00 EQU 0x40006946\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_MC_00\r
+CYREG_B0_UDB04_MC_00 EQU 0x40006948\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_MC_00\r
+CYREG_B0_UDB05_MC_00 EQU 0x4000694a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_MC_00\r
+CYREG_B0_UDB06_MC_00 EQU 0x4000694c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_MC_00\r
+CYREG_B0_UDB07_MC_00 EQU 0x4000694e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_MC_00\r
+CYREG_B0_UDB08_MC_00 EQU 0x40006950\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_MC_00\r
+CYREG_B0_UDB09_MC_00 EQU 0x40006952\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_MC_00\r
+CYREG_B0_UDB10_MC_00 EQU 0x40006954\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_MC_00\r
+CYREG_B0_UDB11_MC_00 EQU 0x40006956\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_MC_00\r
+CYREG_B0_UDB12_MC_00 EQU 0x40006958\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_MC_00\r
+CYREG_B0_UDB13_MC_00 EQU 0x4000695a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_MC_00\r
+CYREG_B0_UDB14_MC_00 EQU 0x4000695c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB15_MC_00\r
+CYREG_B0_UDB15_MC_00 EQU 0x4000695e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_BASE\r
+CYDEV_UWRK_UWRK16_CAT_B1_BASE EQU 0x40006a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_SIZE\r
+CYDEV_UWRK_UWRK16_CAT_B1_SIZE EQU 0x00000160\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_A0_A1\r
+CYREG_B1_UDB04_A0_A1 EQU 0x40006a08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_A0_A1\r
+CYREG_B1_UDB05_A0_A1 EQU 0x40006a0a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_A0_A1\r
+CYREG_B1_UDB06_A0_A1 EQU 0x40006a0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_A0_A1\r
+CYREG_B1_UDB07_A0_A1 EQU 0x40006a0e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_A0_A1\r
+CYREG_B1_UDB08_A0_A1 EQU 0x40006a10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_A0_A1\r
+CYREG_B1_UDB09_A0_A1 EQU 0x40006a12\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_A0_A1\r
+CYREG_B1_UDB10_A0_A1 EQU 0x40006a14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_A0_A1\r
+CYREG_B1_UDB11_A0_A1 EQU 0x40006a16\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_D0_D1\r
+CYREG_B1_UDB04_D0_D1 EQU 0x40006a48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_D0_D1\r
+CYREG_B1_UDB05_D0_D1 EQU 0x40006a4a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_D0_D1\r
+CYREG_B1_UDB06_D0_D1 EQU 0x40006a4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_D0_D1\r
+CYREG_B1_UDB07_D0_D1 EQU 0x40006a4e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_D0_D1\r
+CYREG_B1_UDB08_D0_D1 EQU 0x40006a50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_D0_D1\r
+CYREG_B1_UDB09_D0_D1 EQU 0x40006a52\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_D0_D1\r
+CYREG_B1_UDB10_D0_D1 EQU 0x40006a54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_D0_D1\r
+CYREG_B1_UDB11_D0_D1 EQU 0x40006a56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_F0_F1\r
+CYREG_B1_UDB04_F0_F1 EQU 0x40006a88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_F0_F1\r
+CYREG_B1_UDB05_F0_F1 EQU 0x40006a8a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_F0_F1\r
+CYREG_B1_UDB06_F0_F1 EQU 0x40006a8c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_F0_F1\r
+CYREG_B1_UDB07_F0_F1 EQU 0x40006a8e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_F0_F1\r
+CYREG_B1_UDB08_F0_F1 EQU 0x40006a90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_F0_F1\r
+CYREG_B1_UDB09_F0_F1 EQU 0x40006a92\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_F0_F1\r
+CYREG_B1_UDB10_F0_F1 EQU 0x40006a94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_F0_F1\r
+CYREG_B1_UDB11_F0_F1 EQU 0x40006a96\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_ST_CTL\r
+CYREG_B1_UDB04_ST_CTL EQU 0x40006ac8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_ST_CTL\r
+CYREG_B1_UDB05_ST_CTL EQU 0x40006aca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_ST_CTL\r
+CYREG_B1_UDB06_ST_CTL EQU 0x40006acc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_ST_CTL\r
+CYREG_B1_UDB07_ST_CTL EQU 0x40006ace\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_ST_CTL\r
+CYREG_B1_UDB08_ST_CTL EQU 0x40006ad0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_ST_CTL\r
+CYREG_B1_UDB09_ST_CTL EQU 0x40006ad2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_ST_CTL\r
+CYREG_B1_UDB10_ST_CTL EQU 0x40006ad4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_ST_CTL\r
+CYREG_B1_UDB11_ST_CTL EQU 0x40006ad6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_MSK_ACTL\r
+CYREG_B1_UDB04_MSK_ACTL EQU 0x40006b08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_MSK_ACTL\r
+CYREG_B1_UDB05_MSK_ACTL EQU 0x40006b0a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_MSK_ACTL\r
+CYREG_B1_UDB06_MSK_ACTL EQU 0x40006b0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_MSK_ACTL\r
+CYREG_B1_UDB07_MSK_ACTL EQU 0x40006b0e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_MSK_ACTL\r
+CYREG_B1_UDB08_MSK_ACTL EQU 0x40006b10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_MSK_ACTL\r
+CYREG_B1_UDB09_MSK_ACTL EQU 0x40006b12\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_MSK_ACTL\r
+CYREG_B1_UDB10_MSK_ACTL EQU 0x40006b14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_MSK_ACTL\r
+CYREG_B1_UDB11_MSK_ACTL EQU 0x40006b16\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_MC_00\r
+CYREG_B1_UDB04_MC_00 EQU 0x40006b48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_MC_00\r
+CYREG_B1_UDB05_MC_00 EQU 0x40006b4a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_MC_00\r
+CYREG_B1_UDB06_MC_00 EQU 0x40006b4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_MC_00\r
+CYREG_B1_UDB07_MC_00 EQU 0x40006b4e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_MC_00\r
+CYREG_B1_UDB08_MC_00 EQU 0x40006b50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_MC_00\r
+CYREG_B1_UDB09_MC_00 EQU 0x40006b52\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_MC_00\r
+CYREG_B1_UDB10_MC_00 EQU 0x40006b54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_MC_00\r
+CYREG_B1_UDB11_MC_00 EQU 0x40006b56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_BASE\r
+CYDEV_UWRK_UWRK16_DEF_BASE EQU 0x40006800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_SIZE\r
+CYDEV_UWRK_UWRK16_DEF_SIZE EQU 0x0000075e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_BASE\r
+CYDEV_UWRK_UWRK16_DEF_B0_BASE EQU 0x40006800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_SIZE\r
+CYDEV_UWRK_UWRK16_DEF_B0_SIZE EQU 0x0000015e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_01_A0\r
+CYREG_B0_UDB00_01_A0 EQU 0x40006800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_02_A0\r
+CYREG_B0_UDB01_02_A0 EQU 0x40006802\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_03_A0\r
+CYREG_B0_UDB02_03_A0 EQU 0x40006804\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_04_A0\r
+CYREG_B0_UDB03_04_A0 EQU 0x40006806\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_05_A0\r
+CYREG_B0_UDB04_05_A0 EQU 0x40006808\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_06_A0\r
+CYREG_B0_UDB05_06_A0 EQU 0x4000680a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_07_A0\r
+CYREG_B0_UDB06_07_A0 EQU 0x4000680c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_08_A0\r
+CYREG_B0_UDB07_08_A0 EQU 0x4000680e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_09_A0\r
+CYREG_B0_UDB08_09_A0 EQU 0x40006810\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_10_A0\r
+CYREG_B0_UDB09_10_A0 EQU 0x40006812\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_11_A0\r
+CYREG_B0_UDB10_11_A0 EQU 0x40006814\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_12_A0\r
+CYREG_B0_UDB11_12_A0 EQU 0x40006816\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_13_A0\r
+CYREG_B0_UDB12_13_A0 EQU 0x40006818\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_14_A0\r
+CYREG_B0_UDB13_14_A0 EQU 0x4000681a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_15_A0\r
+CYREG_B0_UDB14_15_A0 EQU 0x4000681c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_01_A1\r
+CYREG_B0_UDB00_01_A1 EQU 0x40006820\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_02_A1\r
+CYREG_B0_UDB01_02_A1 EQU 0x40006822\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_03_A1\r
+CYREG_B0_UDB02_03_A1 EQU 0x40006824\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_04_A1\r
+CYREG_B0_UDB03_04_A1 EQU 0x40006826\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_05_A1\r
+CYREG_B0_UDB04_05_A1 EQU 0x40006828\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_06_A1\r
+CYREG_B0_UDB05_06_A1 EQU 0x4000682a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_07_A1\r
+CYREG_B0_UDB06_07_A1 EQU 0x4000682c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_08_A1\r
+CYREG_B0_UDB07_08_A1 EQU 0x4000682e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_09_A1\r
+CYREG_B0_UDB08_09_A1 EQU 0x40006830\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_10_A1\r
+CYREG_B0_UDB09_10_A1 EQU 0x40006832\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_11_A1\r
+CYREG_B0_UDB10_11_A1 EQU 0x40006834\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_12_A1\r
+CYREG_B0_UDB11_12_A1 EQU 0x40006836\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_13_A1\r
+CYREG_B0_UDB12_13_A1 EQU 0x40006838\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_14_A1\r
+CYREG_B0_UDB13_14_A1 EQU 0x4000683a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_15_A1\r
+CYREG_B0_UDB14_15_A1 EQU 0x4000683c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_01_D0\r
+CYREG_B0_UDB00_01_D0 EQU 0x40006840\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_02_D0\r
+CYREG_B0_UDB01_02_D0 EQU 0x40006842\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_03_D0\r
+CYREG_B0_UDB02_03_D0 EQU 0x40006844\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_04_D0\r
+CYREG_B0_UDB03_04_D0 EQU 0x40006846\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_05_D0\r
+CYREG_B0_UDB04_05_D0 EQU 0x40006848\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_06_D0\r
+CYREG_B0_UDB05_06_D0 EQU 0x4000684a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_07_D0\r
+CYREG_B0_UDB06_07_D0 EQU 0x4000684c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_08_D0\r
+CYREG_B0_UDB07_08_D0 EQU 0x4000684e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_09_D0\r
+CYREG_B0_UDB08_09_D0 EQU 0x40006850\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_10_D0\r
+CYREG_B0_UDB09_10_D0 EQU 0x40006852\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_11_D0\r
+CYREG_B0_UDB10_11_D0 EQU 0x40006854\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_12_D0\r
+CYREG_B0_UDB11_12_D0 EQU 0x40006856\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_13_D0\r
+CYREG_B0_UDB12_13_D0 EQU 0x40006858\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_14_D0\r
+CYREG_B0_UDB13_14_D0 EQU 0x4000685a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_15_D0\r
+CYREG_B0_UDB14_15_D0 EQU 0x4000685c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_01_D1\r
+CYREG_B0_UDB00_01_D1 EQU 0x40006860\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_02_D1\r
+CYREG_B0_UDB01_02_D1 EQU 0x40006862\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_03_D1\r
+CYREG_B0_UDB02_03_D1 EQU 0x40006864\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_04_D1\r
+CYREG_B0_UDB03_04_D1 EQU 0x40006866\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_05_D1\r
+CYREG_B0_UDB04_05_D1 EQU 0x40006868\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_06_D1\r
+CYREG_B0_UDB05_06_D1 EQU 0x4000686a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_07_D1\r
+CYREG_B0_UDB06_07_D1 EQU 0x4000686c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_08_D1\r
+CYREG_B0_UDB07_08_D1 EQU 0x4000686e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_09_D1\r
+CYREG_B0_UDB08_09_D1 EQU 0x40006870\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_10_D1\r
+CYREG_B0_UDB09_10_D1 EQU 0x40006872\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_11_D1\r
+CYREG_B0_UDB10_11_D1 EQU 0x40006874\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_12_D1\r
+CYREG_B0_UDB11_12_D1 EQU 0x40006876\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_13_D1\r
+CYREG_B0_UDB12_13_D1 EQU 0x40006878\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_14_D1\r
+CYREG_B0_UDB13_14_D1 EQU 0x4000687a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_15_D1\r
+CYREG_B0_UDB14_15_D1 EQU 0x4000687c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_01_F0\r
+CYREG_B0_UDB00_01_F0 EQU 0x40006880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_02_F0\r
+CYREG_B0_UDB01_02_F0 EQU 0x40006882\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_03_F0\r
+CYREG_B0_UDB02_03_F0 EQU 0x40006884\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_04_F0\r
+CYREG_B0_UDB03_04_F0 EQU 0x40006886\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_05_F0\r
+CYREG_B0_UDB04_05_F0 EQU 0x40006888\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_06_F0\r
+CYREG_B0_UDB05_06_F0 EQU 0x4000688a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_07_F0\r
+CYREG_B0_UDB06_07_F0 EQU 0x4000688c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_08_F0\r
+CYREG_B0_UDB07_08_F0 EQU 0x4000688e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_09_F0\r
+CYREG_B0_UDB08_09_F0 EQU 0x40006890\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_10_F0\r
+CYREG_B0_UDB09_10_F0 EQU 0x40006892\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_11_F0\r
+CYREG_B0_UDB10_11_F0 EQU 0x40006894\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_12_F0\r
+CYREG_B0_UDB11_12_F0 EQU 0x40006896\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_13_F0\r
+CYREG_B0_UDB12_13_F0 EQU 0x40006898\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_14_F0\r
+CYREG_B0_UDB13_14_F0 EQU 0x4000689a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_15_F0\r
+CYREG_B0_UDB14_15_F0 EQU 0x4000689c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_01_F1\r
+CYREG_B0_UDB00_01_F1 EQU 0x400068a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_02_F1\r
+CYREG_B0_UDB01_02_F1 EQU 0x400068a2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_03_F1\r
+CYREG_B0_UDB02_03_F1 EQU 0x400068a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_04_F1\r
+CYREG_B0_UDB03_04_F1 EQU 0x400068a6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_05_F1\r
+CYREG_B0_UDB04_05_F1 EQU 0x400068a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_06_F1\r
+CYREG_B0_UDB05_06_F1 EQU 0x400068aa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_07_F1\r
+CYREG_B0_UDB06_07_F1 EQU 0x400068ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_08_F1\r
+CYREG_B0_UDB07_08_F1 EQU 0x400068ae\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_09_F1\r
+CYREG_B0_UDB08_09_F1 EQU 0x400068b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_10_F1\r
+CYREG_B0_UDB09_10_F1 EQU 0x400068b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_11_F1\r
+CYREG_B0_UDB10_11_F1 EQU 0x400068b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_12_F1\r
+CYREG_B0_UDB11_12_F1 EQU 0x400068b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_13_F1\r
+CYREG_B0_UDB12_13_F1 EQU 0x400068b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_14_F1\r
+CYREG_B0_UDB13_14_F1 EQU 0x400068ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_15_F1\r
+CYREG_B0_UDB14_15_F1 EQU 0x400068bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_01_ST\r
+CYREG_B0_UDB00_01_ST EQU 0x400068c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_02_ST\r
+CYREG_B0_UDB01_02_ST EQU 0x400068c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_03_ST\r
+CYREG_B0_UDB02_03_ST EQU 0x400068c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_04_ST\r
+CYREG_B0_UDB03_04_ST EQU 0x400068c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_05_ST\r
+CYREG_B0_UDB04_05_ST EQU 0x400068c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_06_ST\r
+CYREG_B0_UDB05_06_ST EQU 0x400068ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_07_ST\r
+CYREG_B0_UDB06_07_ST EQU 0x400068cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_08_ST\r
+CYREG_B0_UDB07_08_ST EQU 0x400068ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_09_ST\r
+CYREG_B0_UDB08_09_ST EQU 0x400068d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_10_ST\r
+CYREG_B0_UDB09_10_ST EQU 0x400068d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_11_ST\r
+CYREG_B0_UDB10_11_ST EQU 0x400068d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_12_ST\r
+CYREG_B0_UDB11_12_ST EQU 0x400068d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_13_ST\r
+CYREG_B0_UDB12_13_ST EQU 0x400068d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_14_ST\r
+CYREG_B0_UDB13_14_ST EQU 0x400068da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_15_ST\r
+CYREG_B0_UDB14_15_ST EQU 0x400068dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_01_CTL\r
+CYREG_B0_UDB00_01_CTL EQU 0x400068e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_02_CTL\r
+CYREG_B0_UDB01_02_CTL EQU 0x400068e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_03_CTL\r
+CYREG_B0_UDB02_03_CTL EQU 0x400068e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_04_CTL\r
+CYREG_B0_UDB03_04_CTL EQU 0x400068e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_05_CTL\r
+CYREG_B0_UDB04_05_CTL EQU 0x400068e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_06_CTL\r
+CYREG_B0_UDB05_06_CTL EQU 0x400068ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_07_CTL\r
+CYREG_B0_UDB06_07_CTL EQU 0x400068ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_08_CTL\r
+CYREG_B0_UDB07_08_CTL EQU 0x400068ee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_09_CTL\r
+CYREG_B0_UDB08_09_CTL EQU 0x400068f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_10_CTL\r
+CYREG_B0_UDB09_10_CTL EQU 0x400068f2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_11_CTL\r
+CYREG_B0_UDB10_11_CTL EQU 0x400068f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_12_CTL\r
+CYREG_B0_UDB11_12_CTL EQU 0x400068f6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_13_CTL\r
+CYREG_B0_UDB12_13_CTL EQU 0x400068f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_14_CTL\r
+CYREG_B0_UDB13_14_CTL EQU 0x400068fa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_15_CTL\r
+CYREG_B0_UDB14_15_CTL EQU 0x400068fc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_01_MSK\r
+CYREG_B0_UDB00_01_MSK EQU 0x40006900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_02_MSK\r
+CYREG_B0_UDB01_02_MSK EQU 0x40006902\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_03_MSK\r
+CYREG_B0_UDB02_03_MSK EQU 0x40006904\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_04_MSK\r
+CYREG_B0_UDB03_04_MSK EQU 0x40006906\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_05_MSK\r
+CYREG_B0_UDB04_05_MSK EQU 0x40006908\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_06_MSK\r
+CYREG_B0_UDB05_06_MSK EQU 0x4000690a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_07_MSK\r
+CYREG_B0_UDB06_07_MSK EQU 0x4000690c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_08_MSK\r
+CYREG_B0_UDB07_08_MSK EQU 0x4000690e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_09_MSK\r
+CYREG_B0_UDB08_09_MSK EQU 0x40006910\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_10_MSK\r
+CYREG_B0_UDB09_10_MSK EQU 0x40006912\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_11_MSK\r
+CYREG_B0_UDB10_11_MSK EQU 0x40006914\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_12_MSK\r
+CYREG_B0_UDB11_12_MSK EQU 0x40006916\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_13_MSK\r
+CYREG_B0_UDB12_13_MSK EQU 0x40006918\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_14_MSK\r
+CYREG_B0_UDB13_14_MSK EQU 0x4000691a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_15_MSK\r
+CYREG_B0_UDB14_15_MSK EQU 0x4000691c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_01_ACTL\r
+CYREG_B0_UDB00_01_ACTL EQU 0x40006920\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_02_ACTL\r
+CYREG_B0_UDB01_02_ACTL EQU 0x40006922\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_03_ACTL\r
+CYREG_B0_UDB02_03_ACTL EQU 0x40006924\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_04_ACTL\r
+CYREG_B0_UDB03_04_ACTL EQU 0x40006926\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_05_ACTL\r
+CYREG_B0_UDB04_05_ACTL EQU 0x40006928\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_06_ACTL\r
+CYREG_B0_UDB05_06_ACTL EQU 0x4000692a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_07_ACTL\r
+CYREG_B0_UDB06_07_ACTL EQU 0x4000692c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_08_ACTL\r
+CYREG_B0_UDB07_08_ACTL EQU 0x4000692e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_09_ACTL\r
+CYREG_B0_UDB08_09_ACTL EQU 0x40006930\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_10_ACTL\r
+CYREG_B0_UDB09_10_ACTL EQU 0x40006932\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_11_ACTL\r
+CYREG_B0_UDB10_11_ACTL EQU 0x40006934\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_12_ACTL\r
+CYREG_B0_UDB11_12_ACTL EQU 0x40006936\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_13_ACTL\r
+CYREG_B0_UDB12_13_ACTL EQU 0x40006938\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_14_ACTL\r
+CYREG_B0_UDB13_14_ACTL EQU 0x4000693a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_15_ACTL\r
+CYREG_B0_UDB14_15_ACTL EQU 0x4000693c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB00_01_MC\r
+CYREG_B0_UDB00_01_MC EQU 0x40006940\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB01_02_MC\r
+CYREG_B0_UDB01_02_MC EQU 0x40006942\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB02_03_MC\r
+CYREG_B0_UDB02_03_MC EQU 0x40006944\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB03_04_MC\r
+CYREG_B0_UDB03_04_MC EQU 0x40006946\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB04_05_MC\r
+CYREG_B0_UDB04_05_MC EQU 0x40006948\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB05_06_MC\r
+CYREG_B0_UDB05_06_MC EQU 0x4000694a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB06_07_MC\r
+CYREG_B0_UDB06_07_MC EQU 0x4000694c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB07_08_MC\r
+CYREG_B0_UDB07_08_MC EQU 0x4000694e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB08_09_MC\r
+CYREG_B0_UDB08_09_MC EQU 0x40006950\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB09_10_MC\r
+CYREG_B0_UDB09_10_MC EQU 0x40006952\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB10_11_MC\r
+CYREG_B0_UDB10_11_MC EQU 0x40006954\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB11_12_MC\r
+CYREG_B0_UDB11_12_MC EQU 0x40006956\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB12_13_MC\r
+CYREG_B0_UDB12_13_MC EQU 0x40006958\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB13_14_MC\r
+CYREG_B0_UDB13_14_MC EQU 0x4000695a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_UDB14_15_MC\r
+CYREG_B0_UDB14_15_MC EQU 0x4000695c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_BASE\r
+CYDEV_UWRK_UWRK16_DEF_B1_BASE EQU 0x40006a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_SIZE\r
+CYDEV_UWRK_UWRK16_DEF_B1_SIZE EQU 0x0000015e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_05_A0\r
+CYREG_B1_UDB04_05_A0 EQU 0x40006a08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_06_A0\r
+CYREG_B1_UDB05_06_A0 EQU 0x40006a0a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_07_A0\r
+CYREG_B1_UDB06_07_A0 EQU 0x40006a0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_08_A0\r
+CYREG_B1_UDB07_08_A0 EQU 0x40006a0e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_09_A0\r
+CYREG_B1_UDB08_09_A0 EQU 0x40006a10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_10_A0\r
+CYREG_B1_UDB09_10_A0 EQU 0x40006a12\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_11_A0\r
+CYREG_B1_UDB10_11_A0 EQU 0x40006a14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_12_A0\r
+CYREG_B1_UDB11_12_A0 EQU 0x40006a16\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_05_A1\r
+CYREG_B1_UDB04_05_A1 EQU 0x40006a28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_06_A1\r
+CYREG_B1_UDB05_06_A1 EQU 0x40006a2a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_07_A1\r
+CYREG_B1_UDB06_07_A1 EQU 0x40006a2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_08_A1\r
+CYREG_B1_UDB07_08_A1 EQU 0x40006a2e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_09_A1\r
+CYREG_B1_UDB08_09_A1 EQU 0x40006a30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_10_A1\r
+CYREG_B1_UDB09_10_A1 EQU 0x40006a32\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_11_A1\r
+CYREG_B1_UDB10_11_A1 EQU 0x40006a34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_12_A1\r
+CYREG_B1_UDB11_12_A1 EQU 0x40006a36\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_05_D0\r
+CYREG_B1_UDB04_05_D0 EQU 0x40006a48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_06_D0\r
+CYREG_B1_UDB05_06_D0 EQU 0x40006a4a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_07_D0\r
+CYREG_B1_UDB06_07_D0 EQU 0x40006a4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_08_D0\r
+CYREG_B1_UDB07_08_D0 EQU 0x40006a4e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_09_D0\r
+CYREG_B1_UDB08_09_D0 EQU 0x40006a50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_10_D0\r
+CYREG_B1_UDB09_10_D0 EQU 0x40006a52\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_11_D0\r
+CYREG_B1_UDB10_11_D0 EQU 0x40006a54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_12_D0\r
+CYREG_B1_UDB11_12_D0 EQU 0x40006a56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_05_D1\r
+CYREG_B1_UDB04_05_D1 EQU 0x40006a68\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_06_D1\r
+CYREG_B1_UDB05_06_D1 EQU 0x40006a6a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_07_D1\r
+CYREG_B1_UDB06_07_D1 EQU 0x40006a6c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_08_D1\r
+CYREG_B1_UDB07_08_D1 EQU 0x40006a6e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_09_D1\r
+CYREG_B1_UDB08_09_D1 EQU 0x40006a70\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_10_D1\r
+CYREG_B1_UDB09_10_D1 EQU 0x40006a72\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_11_D1\r
+CYREG_B1_UDB10_11_D1 EQU 0x40006a74\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_12_D1\r
+CYREG_B1_UDB11_12_D1 EQU 0x40006a76\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_05_F0\r
+CYREG_B1_UDB04_05_F0 EQU 0x40006a88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_06_F0\r
+CYREG_B1_UDB05_06_F0 EQU 0x40006a8a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_07_F0\r
+CYREG_B1_UDB06_07_F0 EQU 0x40006a8c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_08_F0\r
+CYREG_B1_UDB07_08_F0 EQU 0x40006a8e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_09_F0\r
+CYREG_B1_UDB08_09_F0 EQU 0x40006a90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_10_F0\r
+CYREG_B1_UDB09_10_F0 EQU 0x40006a92\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_11_F0\r
+CYREG_B1_UDB10_11_F0 EQU 0x40006a94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_12_F0\r
+CYREG_B1_UDB11_12_F0 EQU 0x40006a96\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_05_F1\r
+CYREG_B1_UDB04_05_F1 EQU 0x40006aa8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_06_F1\r
+CYREG_B1_UDB05_06_F1 EQU 0x40006aaa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_07_F1\r
+CYREG_B1_UDB06_07_F1 EQU 0x40006aac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_08_F1\r
+CYREG_B1_UDB07_08_F1 EQU 0x40006aae\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_09_F1\r
+CYREG_B1_UDB08_09_F1 EQU 0x40006ab0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_10_F1\r
+CYREG_B1_UDB09_10_F1 EQU 0x40006ab2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_11_F1\r
+CYREG_B1_UDB10_11_F1 EQU 0x40006ab4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_12_F1\r
+CYREG_B1_UDB11_12_F1 EQU 0x40006ab6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_05_ST\r
+CYREG_B1_UDB04_05_ST EQU 0x40006ac8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_06_ST\r
+CYREG_B1_UDB05_06_ST EQU 0x40006aca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_07_ST\r
+CYREG_B1_UDB06_07_ST EQU 0x40006acc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_08_ST\r
+CYREG_B1_UDB07_08_ST EQU 0x40006ace\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_09_ST\r
+CYREG_B1_UDB08_09_ST EQU 0x40006ad0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_10_ST\r
+CYREG_B1_UDB09_10_ST EQU 0x40006ad2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_11_ST\r
+CYREG_B1_UDB10_11_ST EQU 0x40006ad4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_12_ST\r
+CYREG_B1_UDB11_12_ST EQU 0x40006ad6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_05_CTL\r
+CYREG_B1_UDB04_05_CTL EQU 0x40006ae8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_06_CTL\r
+CYREG_B1_UDB05_06_CTL EQU 0x40006aea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_07_CTL\r
+CYREG_B1_UDB06_07_CTL EQU 0x40006aec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_08_CTL\r
+CYREG_B1_UDB07_08_CTL EQU 0x40006aee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_09_CTL\r
+CYREG_B1_UDB08_09_CTL EQU 0x40006af0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_10_CTL\r
+CYREG_B1_UDB09_10_CTL EQU 0x40006af2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_11_CTL\r
+CYREG_B1_UDB10_11_CTL EQU 0x40006af4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_12_CTL\r
+CYREG_B1_UDB11_12_CTL EQU 0x40006af6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_05_MSK\r
+CYREG_B1_UDB04_05_MSK EQU 0x40006b08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_06_MSK\r
+CYREG_B1_UDB05_06_MSK EQU 0x40006b0a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_07_MSK\r
+CYREG_B1_UDB06_07_MSK EQU 0x40006b0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_08_MSK\r
+CYREG_B1_UDB07_08_MSK EQU 0x40006b0e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_09_MSK\r
+CYREG_B1_UDB08_09_MSK EQU 0x40006b10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_10_MSK\r
+CYREG_B1_UDB09_10_MSK EQU 0x40006b12\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_11_MSK\r
+CYREG_B1_UDB10_11_MSK EQU 0x40006b14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_12_MSK\r
+CYREG_B1_UDB11_12_MSK EQU 0x40006b16\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_05_ACTL\r
+CYREG_B1_UDB04_05_ACTL EQU 0x40006b28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_06_ACTL\r
+CYREG_B1_UDB05_06_ACTL EQU 0x40006b2a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_07_ACTL\r
+CYREG_B1_UDB06_07_ACTL EQU 0x40006b2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_08_ACTL\r
+CYREG_B1_UDB07_08_ACTL EQU 0x40006b2e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_09_ACTL\r
+CYREG_B1_UDB08_09_ACTL EQU 0x40006b30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_10_ACTL\r
+CYREG_B1_UDB09_10_ACTL EQU 0x40006b32\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_11_ACTL\r
+CYREG_B1_UDB10_11_ACTL EQU 0x40006b34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_12_ACTL\r
+CYREG_B1_UDB11_12_ACTL EQU 0x40006b36\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB04_05_MC\r
+CYREG_B1_UDB04_05_MC EQU 0x40006b48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB05_06_MC\r
+CYREG_B1_UDB05_06_MC EQU 0x40006b4a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB06_07_MC\r
+CYREG_B1_UDB06_07_MC EQU 0x40006b4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB07_08_MC\r
+CYREG_B1_UDB07_08_MC EQU 0x40006b4e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB08_09_MC\r
+CYREG_B1_UDB08_09_MC EQU 0x40006b50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB09_10_MC\r
+CYREG_B1_UDB09_10_MC EQU 0x40006b52\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB10_11_MC\r
+CYREG_B1_UDB10_11_MC EQU 0x40006b54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_UDB11_12_MC\r
+CYREG_B1_UDB11_12_MC EQU 0x40006b56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_BASE\r
+CYDEV_PHUB_BASE EQU 0x40007000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_SIZE\r
+CYDEV_PHUB_SIZE EQU 0x00000c00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFG\r
+CYREG_PHUB_CFG EQU 0x40007000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_ERR\r
+CYREG_PHUB_ERR EQU 0x40007004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_ERR_ADR\r
+CYREG_PHUB_ERR_ADR EQU 0x40007008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH0_BASE\r
+CYDEV_PHUB_CH0_BASE EQU 0x40007010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH0_SIZE\r
+CYDEV_PHUB_CH0_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH0_BASIC_CFG\r
+CYREG_PHUB_CH0_BASIC_CFG EQU 0x40007010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH0_ACTION\r
+CYREG_PHUB_CH0_ACTION EQU 0x40007014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH0_BASIC_STATUS\r
+CYREG_PHUB_CH0_BASIC_STATUS EQU 0x40007018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH1_BASE\r
+CYDEV_PHUB_CH1_BASE EQU 0x40007020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH1_SIZE\r
+CYDEV_PHUB_CH1_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH1_BASIC_CFG\r
+CYREG_PHUB_CH1_BASIC_CFG EQU 0x40007020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH1_ACTION\r
+CYREG_PHUB_CH1_ACTION EQU 0x40007024\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH1_BASIC_STATUS\r
+CYREG_PHUB_CH1_BASIC_STATUS EQU 0x40007028\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH2_BASE\r
+CYDEV_PHUB_CH2_BASE EQU 0x40007030\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH2_SIZE\r
+CYDEV_PHUB_CH2_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH2_BASIC_CFG\r
+CYREG_PHUB_CH2_BASIC_CFG EQU 0x40007030\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH2_ACTION\r
+CYREG_PHUB_CH2_ACTION EQU 0x40007034\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH2_BASIC_STATUS\r
+CYREG_PHUB_CH2_BASIC_STATUS EQU 0x40007038\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH3_BASE\r
+CYDEV_PHUB_CH3_BASE EQU 0x40007040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH3_SIZE\r
+CYDEV_PHUB_CH3_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH3_BASIC_CFG\r
+CYREG_PHUB_CH3_BASIC_CFG EQU 0x40007040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH3_ACTION\r
+CYREG_PHUB_CH3_ACTION EQU 0x40007044\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH3_BASIC_STATUS\r
+CYREG_PHUB_CH3_BASIC_STATUS EQU 0x40007048\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH4_BASE\r
+CYDEV_PHUB_CH4_BASE EQU 0x40007050\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH4_SIZE\r
+CYDEV_PHUB_CH4_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH4_BASIC_CFG\r
+CYREG_PHUB_CH4_BASIC_CFG EQU 0x40007050\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH4_ACTION\r
+CYREG_PHUB_CH4_ACTION EQU 0x40007054\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH4_BASIC_STATUS\r
+CYREG_PHUB_CH4_BASIC_STATUS EQU 0x40007058\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH5_BASE\r
+CYDEV_PHUB_CH5_BASE EQU 0x40007060\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH5_SIZE\r
+CYDEV_PHUB_CH5_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH5_BASIC_CFG\r
+CYREG_PHUB_CH5_BASIC_CFG EQU 0x40007060\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH5_ACTION\r
+CYREG_PHUB_CH5_ACTION EQU 0x40007064\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH5_BASIC_STATUS\r
+CYREG_PHUB_CH5_BASIC_STATUS EQU 0x40007068\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH6_BASE\r
+CYDEV_PHUB_CH6_BASE EQU 0x40007070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH6_SIZE\r
+CYDEV_PHUB_CH6_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH6_BASIC_CFG\r
+CYREG_PHUB_CH6_BASIC_CFG EQU 0x40007070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH6_ACTION\r
+CYREG_PHUB_CH6_ACTION EQU 0x40007074\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH6_BASIC_STATUS\r
+CYREG_PHUB_CH6_BASIC_STATUS EQU 0x40007078\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH7_BASE\r
+CYDEV_PHUB_CH7_BASE EQU 0x40007080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH7_SIZE\r
+CYDEV_PHUB_CH7_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH7_BASIC_CFG\r
+CYREG_PHUB_CH7_BASIC_CFG EQU 0x40007080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH7_ACTION\r
+CYREG_PHUB_CH7_ACTION EQU 0x40007084\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH7_BASIC_STATUS\r
+CYREG_PHUB_CH7_BASIC_STATUS EQU 0x40007088\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH8_BASE\r
+CYDEV_PHUB_CH8_BASE EQU 0x40007090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH8_SIZE\r
+CYDEV_PHUB_CH8_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH8_BASIC_CFG\r
+CYREG_PHUB_CH8_BASIC_CFG EQU 0x40007090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH8_ACTION\r
+CYREG_PHUB_CH8_ACTION EQU 0x40007094\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH8_BASIC_STATUS\r
+CYREG_PHUB_CH8_BASIC_STATUS EQU 0x40007098\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH9_BASE\r
+CYDEV_PHUB_CH9_BASE EQU 0x400070a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH9_SIZE\r
+CYDEV_PHUB_CH9_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH9_BASIC_CFG\r
+CYREG_PHUB_CH9_BASIC_CFG EQU 0x400070a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH9_ACTION\r
+CYREG_PHUB_CH9_ACTION EQU 0x400070a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH9_BASIC_STATUS\r
+CYREG_PHUB_CH9_BASIC_STATUS EQU 0x400070a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH10_BASE\r
+CYDEV_PHUB_CH10_BASE EQU 0x400070b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH10_SIZE\r
+CYDEV_PHUB_CH10_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH10_BASIC_CFG\r
+CYREG_PHUB_CH10_BASIC_CFG EQU 0x400070b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH10_ACTION\r
+CYREG_PHUB_CH10_ACTION EQU 0x400070b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH10_BASIC_STATUS\r
+CYREG_PHUB_CH10_BASIC_STATUS EQU 0x400070b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH11_BASE\r
+CYDEV_PHUB_CH11_BASE EQU 0x400070c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH11_SIZE\r
+CYDEV_PHUB_CH11_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH11_BASIC_CFG\r
+CYREG_PHUB_CH11_BASIC_CFG EQU 0x400070c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH11_ACTION\r
+CYREG_PHUB_CH11_ACTION EQU 0x400070c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH11_BASIC_STATUS\r
+CYREG_PHUB_CH11_BASIC_STATUS EQU 0x400070c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH12_BASE\r
+CYDEV_PHUB_CH12_BASE EQU 0x400070d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH12_SIZE\r
+CYDEV_PHUB_CH12_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH12_BASIC_CFG\r
+CYREG_PHUB_CH12_BASIC_CFG EQU 0x400070d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH12_ACTION\r
+CYREG_PHUB_CH12_ACTION EQU 0x400070d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH12_BASIC_STATUS\r
+CYREG_PHUB_CH12_BASIC_STATUS EQU 0x400070d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH13_BASE\r
+CYDEV_PHUB_CH13_BASE EQU 0x400070e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH13_SIZE\r
+CYDEV_PHUB_CH13_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH13_BASIC_CFG\r
+CYREG_PHUB_CH13_BASIC_CFG EQU 0x400070e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH13_ACTION\r
+CYREG_PHUB_CH13_ACTION EQU 0x400070e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH13_BASIC_STATUS\r
+CYREG_PHUB_CH13_BASIC_STATUS EQU 0x400070e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH14_BASE\r
+CYDEV_PHUB_CH14_BASE EQU 0x400070f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH14_SIZE\r
+CYDEV_PHUB_CH14_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH14_BASIC_CFG\r
+CYREG_PHUB_CH14_BASIC_CFG EQU 0x400070f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH14_ACTION\r
+CYREG_PHUB_CH14_ACTION EQU 0x400070f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH14_BASIC_STATUS\r
+CYREG_PHUB_CH14_BASIC_STATUS EQU 0x400070f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH15_BASE\r
+CYDEV_PHUB_CH15_BASE EQU 0x40007100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH15_SIZE\r
+CYDEV_PHUB_CH15_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH15_BASIC_CFG\r
+CYREG_PHUB_CH15_BASIC_CFG EQU 0x40007100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH15_ACTION\r
+CYREG_PHUB_CH15_ACTION EQU 0x40007104\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH15_BASIC_STATUS\r
+CYREG_PHUB_CH15_BASIC_STATUS EQU 0x40007108\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH16_BASE\r
+CYDEV_PHUB_CH16_BASE EQU 0x40007110\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH16_SIZE\r
+CYDEV_PHUB_CH16_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH16_BASIC_CFG\r
+CYREG_PHUB_CH16_BASIC_CFG EQU 0x40007110\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH16_ACTION\r
+CYREG_PHUB_CH16_ACTION EQU 0x40007114\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH16_BASIC_STATUS\r
+CYREG_PHUB_CH16_BASIC_STATUS EQU 0x40007118\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH17_BASE\r
+CYDEV_PHUB_CH17_BASE EQU 0x40007120\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH17_SIZE\r
+CYDEV_PHUB_CH17_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH17_BASIC_CFG\r
+CYREG_PHUB_CH17_BASIC_CFG EQU 0x40007120\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH17_ACTION\r
+CYREG_PHUB_CH17_ACTION EQU 0x40007124\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH17_BASIC_STATUS\r
+CYREG_PHUB_CH17_BASIC_STATUS EQU 0x40007128\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH18_BASE\r
+CYDEV_PHUB_CH18_BASE EQU 0x40007130\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH18_SIZE\r
+CYDEV_PHUB_CH18_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH18_BASIC_CFG\r
+CYREG_PHUB_CH18_BASIC_CFG EQU 0x40007130\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH18_ACTION\r
+CYREG_PHUB_CH18_ACTION EQU 0x40007134\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH18_BASIC_STATUS\r
+CYREG_PHUB_CH18_BASIC_STATUS EQU 0x40007138\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH19_BASE\r
+CYDEV_PHUB_CH19_BASE EQU 0x40007140\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH19_SIZE\r
+CYDEV_PHUB_CH19_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH19_BASIC_CFG\r
+CYREG_PHUB_CH19_BASIC_CFG EQU 0x40007140\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH19_ACTION\r
+CYREG_PHUB_CH19_ACTION EQU 0x40007144\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH19_BASIC_STATUS\r
+CYREG_PHUB_CH19_BASIC_STATUS EQU 0x40007148\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH20_BASE\r
+CYDEV_PHUB_CH20_BASE EQU 0x40007150\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH20_SIZE\r
+CYDEV_PHUB_CH20_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH20_BASIC_CFG\r
+CYREG_PHUB_CH20_BASIC_CFG EQU 0x40007150\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH20_ACTION\r
+CYREG_PHUB_CH20_ACTION EQU 0x40007154\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH20_BASIC_STATUS\r
+CYREG_PHUB_CH20_BASIC_STATUS EQU 0x40007158\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH21_BASE\r
+CYDEV_PHUB_CH21_BASE EQU 0x40007160\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH21_SIZE\r
+CYDEV_PHUB_CH21_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH21_BASIC_CFG\r
+CYREG_PHUB_CH21_BASIC_CFG EQU 0x40007160\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH21_ACTION\r
+CYREG_PHUB_CH21_ACTION EQU 0x40007164\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH21_BASIC_STATUS\r
+CYREG_PHUB_CH21_BASIC_STATUS EQU 0x40007168\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH22_BASE\r
+CYDEV_PHUB_CH22_BASE EQU 0x40007170\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH22_SIZE\r
+CYDEV_PHUB_CH22_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH22_BASIC_CFG\r
+CYREG_PHUB_CH22_BASIC_CFG EQU 0x40007170\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH22_ACTION\r
+CYREG_PHUB_CH22_ACTION EQU 0x40007174\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH22_BASIC_STATUS\r
+CYREG_PHUB_CH22_BASIC_STATUS EQU 0x40007178\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH23_BASE\r
+CYDEV_PHUB_CH23_BASE EQU 0x40007180\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CH23_SIZE\r
+CYDEV_PHUB_CH23_SIZE EQU 0x0000000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH23_BASIC_CFG\r
+CYREG_PHUB_CH23_BASIC_CFG EQU 0x40007180\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH23_ACTION\r
+CYREG_PHUB_CH23_ACTION EQU 0x40007184\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CH23_BASIC_STATUS\r
+CYREG_PHUB_CH23_BASIC_STATUS EQU 0x40007188\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_BASE\r
+CYDEV_PHUB_CFGMEM0_BASE EQU 0x40007600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_SIZE\r
+CYDEV_PHUB_CFGMEM0_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM0_CFG0\r
+CYREG_PHUB_CFGMEM0_CFG0 EQU 0x40007600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM0_CFG1\r
+CYREG_PHUB_CFGMEM0_CFG1 EQU 0x40007604\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_BASE\r
+CYDEV_PHUB_CFGMEM1_BASE EQU 0x40007608\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_SIZE\r
+CYDEV_PHUB_CFGMEM1_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM1_CFG0\r
+CYREG_PHUB_CFGMEM1_CFG0 EQU 0x40007608\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM1_CFG1\r
+CYREG_PHUB_CFGMEM1_CFG1 EQU 0x4000760c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_BASE\r
+CYDEV_PHUB_CFGMEM2_BASE EQU 0x40007610\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_SIZE\r
+CYDEV_PHUB_CFGMEM2_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM2_CFG0\r
+CYREG_PHUB_CFGMEM2_CFG0 EQU 0x40007610\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM2_CFG1\r
+CYREG_PHUB_CFGMEM2_CFG1 EQU 0x40007614\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_BASE\r
+CYDEV_PHUB_CFGMEM3_BASE EQU 0x40007618\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_SIZE\r
+CYDEV_PHUB_CFGMEM3_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM3_CFG0\r
+CYREG_PHUB_CFGMEM3_CFG0 EQU 0x40007618\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM3_CFG1\r
+CYREG_PHUB_CFGMEM3_CFG1 EQU 0x4000761c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_BASE\r
+CYDEV_PHUB_CFGMEM4_BASE EQU 0x40007620\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_SIZE\r
+CYDEV_PHUB_CFGMEM4_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM4_CFG0\r
+CYREG_PHUB_CFGMEM4_CFG0 EQU 0x40007620\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM4_CFG1\r
+CYREG_PHUB_CFGMEM4_CFG1 EQU 0x40007624\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_BASE\r
+CYDEV_PHUB_CFGMEM5_BASE EQU 0x40007628\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_SIZE\r
+CYDEV_PHUB_CFGMEM5_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM5_CFG0\r
+CYREG_PHUB_CFGMEM5_CFG0 EQU 0x40007628\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM5_CFG1\r
+CYREG_PHUB_CFGMEM5_CFG1 EQU 0x4000762c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_BASE\r
+CYDEV_PHUB_CFGMEM6_BASE EQU 0x40007630\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_SIZE\r
+CYDEV_PHUB_CFGMEM6_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM6_CFG0\r
+CYREG_PHUB_CFGMEM6_CFG0 EQU 0x40007630\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM6_CFG1\r
+CYREG_PHUB_CFGMEM6_CFG1 EQU 0x40007634\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_BASE\r
+CYDEV_PHUB_CFGMEM7_BASE EQU 0x40007638\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_SIZE\r
+CYDEV_PHUB_CFGMEM7_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM7_CFG0\r
+CYREG_PHUB_CFGMEM7_CFG0 EQU 0x40007638\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM7_CFG1\r
+CYREG_PHUB_CFGMEM7_CFG1 EQU 0x4000763c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_BASE\r
+CYDEV_PHUB_CFGMEM8_BASE EQU 0x40007640\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_SIZE\r
+CYDEV_PHUB_CFGMEM8_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM8_CFG0\r
+CYREG_PHUB_CFGMEM8_CFG0 EQU 0x40007640\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM8_CFG1\r
+CYREG_PHUB_CFGMEM8_CFG1 EQU 0x40007644\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_BASE\r
+CYDEV_PHUB_CFGMEM9_BASE EQU 0x40007648\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_SIZE\r
+CYDEV_PHUB_CFGMEM9_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM9_CFG0\r
+CYREG_PHUB_CFGMEM9_CFG0 EQU 0x40007648\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM9_CFG1\r
+CYREG_PHUB_CFGMEM9_CFG1 EQU 0x4000764c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_BASE\r
+CYDEV_PHUB_CFGMEM10_BASE EQU 0x40007650\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_SIZE\r
+CYDEV_PHUB_CFGMEM10_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM10_CFG0\r
+CYREG_PHUB_CFGMEM10_CFG0 EQU 0x40007650\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM10_CFG1\r
+CYREG_PHUB_CFGMEM10_CFG1 EQU 0x40007654\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_BASE\r
+CYDEV_PHUB_CFGMEM11_BASE EQU 0x40007658\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_SIZE\r
+CYDEV_PHUB_CFGMEM11_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM11_CFG0\r
+CYREG_PHUB_CFGMEM11_CFG0 EQU 0x40007658\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM11_CFG1\r
+CYREG_PHUB_CFGMEM11_CFG1 EQU 0x4000765c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_BASE\r
+CYDEV_PHUB_CFGMEM12_BASE EQU 0x40007660\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_SIZE\r
+CYDEV_PHUB_CFGMEM12_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM12_CFG0\r
+CYREG_PHUB_CFGMEM12_CFG0 EQU 0x40007660\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM12_CFG1\r
+CYREG_PHUB_CFGMEM12_CFG1 EQU 0x40007664\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_BASE\r
+CYDEV_PHUB_CFGMEM13_BASE EQU 0x40007668\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_SIZE\r
+CYDEV_PHUB_CFGMEM13_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM13_CFG0\r
+CYREG_PHUB_CFGMEM13_CFG0 EQU 0x40007668\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM13_CFG1\r
+CYREG_PHUB_CFGMEM13_CFG1 EQU 0x4000766c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_BASE\r
+CYDEV_PHUB_CFGMEM14_BASE EQU 0x40007670\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_SIZE\r
+CYDEV_PHUB_CFGMEM14_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM14_CFG0\r
+CYREG_PHUB_CFGMEM14_CFG0 EQU 0x40007670\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM14_CFG1\r
+CYREG_PHUB_CFGMEM14_CFG1 EQU 0x40007674\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_BASE\r
+CYDEV_PHUB_CFGMEM15_BASE EQU 0x40007678\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_SIZE\r
+CYDEV_PHUB_CFGMEM15_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM15_CFG0\r
+CYREG_PHUB_CFGMEM15_CFG0 EQU 0x40007678\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM15_CFG1\r
+CYREG_PHUB_CFGMEM15_CFG1 EQU 0x4000767c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_BASE\r
+CYDEV_PHUB_CFGMEM16_BASE EQU 0x40007680\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_SIZE\r
+CYDEV_PHUB_CFGMEM16_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM16_CFG0\r
+CYREG_PHUB_CFGMEM16_CFG0 EQU 0x40007680\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM16_CFG1\r
+CYREG_PHUB_CFGMEM16_CFG1 EQU 0x40007684\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_BASE\r
+CYDEV_PHUB_CFGMEM17_BASE EQU 0x40007688\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_SIZE\r
+CYDEV_PHUB_CFGMEM17_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM17_CFG0\r
+CYREG_PHUB_CFGMEM17_CFG0 EQU 0x40007688\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM17_CFG1\r
+CYREG_PHUB_CFGMEM17_CFG1 EQU 0x4000768c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_BASE\r
+CYDEV_PHUB_CFGMEM18_BASE EQU 0x40007690\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_SIZE\r
+CYDEV_PHUB_CFGMEM18_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM18_CFG0\r
+CYREG_PHUB_CFGMEM18_CFG0 EQU 0x40007690\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM18_CFG1\r
+CYREG_PHUB_CFGMEM18_CFG1 EQU 0x40007694\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_BASE\r
+CYDEV_PHUB_CFGMEM19_BASE EQU 0x40007698\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_SIZE\r
+CYDEV_PHUB_CFGMEM19_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM19_CFG0\r
+CYREG_PHUB_CFGMEM19_CFG0 EQU 0x40007698\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM19_CFG1\r
+CYREG_PHUB_CFGMEM19_CFG1 EQU 0x4000769c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_BASE\r
+CYDEV_PHUB_CFGMEM20_BASE EQU 0x400076a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_SIZE\r
+CYDEV_PHUB_CFGMEM20_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM20_CFG0\r
+CYREG_PHUB_CFGMEM20_CFG0 EQU 0x400076a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM20_CFG1\r
+CYREG_PHUB_CFGMEM20_CFG1 EQU 0x400076a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_BASE\r
+CYDEV_PHUB_CFGMEM21_BASE EQU 0x400076a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_SIZE\r
+CYDEV_PHUB_CFGMEM21_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM21_CFG0\r
+CYREG_PHUB_CFGMEM21_CFG0 EQU 0x400076a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM21_CFG1\r
+CYREG_PHUB_CFGMEM21_CFG1 EQU 0x400076ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_BASE\r
+CYDEV_PHUB_CFGMEM22_BASE EQU 0x400076b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_SIZE\r
+CYDEV_PHUB_CFGMEM22_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM22_CFG0\r
+CYREG_PHUB_CFGMEM22_CFG0 EQU 0x400076b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM22_CFG1\r
+CYREG_PHUB_CFGMEM22_CFG1 EQU 0x400076b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_BASE\r
+CYDEV_PHUB_CFGMEM23_BASE EQU 0x400076b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_SIZE\r
+CYDEV_PHUB_CFGMEM23_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM23_CFG0\r
+CYREG_PHUB_CFGMEM23_CFG0 EQU 0x400076b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_CFGMEM23_CFG1\r
+CYREG_PHUB_CFGMEM23_CFG1 EQU 0x400076bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_BASE\r
+CYDEV_PHUB_TDMEM0_BASE EQU 0x40007800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_SIZE\r
+CYDEV_PHUB_TDMEM0_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM0_ORIG_TD0\r
+CYREG_PHUB_TDMEM0_ORIG_TD0 EQU 0x40007800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM0_ORIG_TD1\r
+CYREG_PHUB_TDMEM0_ORIG_TD1 EQU 0x40007804\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_BASE\r
+CYDEV_PHUB_TDMEM1_BASE EQU 0x40007808\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_SIZE\r
+CYDEV_PHUB_TDMEM1_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM1_ORIG_TD0\r
+CYREG_PHUB_TDMEM1_ORIG_TD0 EQU 0x40007808\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM1_ORIG_TD1\r
+CYREG_PHUB_TDMEM1_ORIG_TD1 EQU 0x4000780c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_BASE\r
+CYDEV_PHUB_TDMEM2_BASE EQU 0x40007810\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_SIZE\r
+CYDEV_PHUB_TDMEM2_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM2_ORIG_TD0\r
+CYREG_PHUB_TDMEM2_ORIG_TD0 EQU 0x40007810\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM2_ORIG_TD1\r
+CYREG_PHUB_TDMEM2_ORIG_TD1 EQU 0x40007814\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_BASE\r
+CYDEV_PHUB_TDMEM3_BASE EQU 0x40007818\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_SIZE\r
+CYDEV_PHUB_TDMEM3_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM3_ORIG_TD0\r
+CYREG_PHUB_TDMEM3_ORIG_TD0 EQU 0x40007818\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM3_ORIG_TD1\r
+CYREG_PHUB_TDMEM3_ORIG_TD1 EQU 0x4000781c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_BASE\r
+CYDEV_PHUB_TDMEM4_BASE EQU 0x40007820\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_SIZE\r
+CYDEV_PHUB_TDMEM4_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM4_ORIG_TD0\r
+CYREG_PHUB_TDMEM4_ORIG_TD0 EQU 0x40007820\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM4_ORIG_TD1\r
+CYREG_PHUB_TDMEM4_ORIG_TD1 EQU 0x40007824\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_BASE\r
+CYDEV_PHUB_TDMEM5_BASE EQU 0x40007828\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_SIZE\r
+CYDEV_PHUB_TDMEM5_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM5_ORIG_TD0\r
+CYREG_PHUB_TDMEM5_ORIG_TD0 EQU 0x40007828\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM5_ORIG_TD1\r
+CYREG_PHUB_TDMEM5_ORIG_TD1 EQU 0x4000782c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_BASE\r
+CYDEV_PHUB_TDMEM6_BASE EQU 0x40007830\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_SIZE\r
+CYDEV_PHUB_TDMEM6_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM6_ORIG_TD0\r
+CYREG_PHUB_TDMEM6_ORIG_TD0 EQU 0x40007830\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM6_ORIG_TD1\r
+CYREG_PHUB_TDMEM6_ORIG_TD1 EQU 0x40007834\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_BASE\r
+CYDEV_PHUB_TDMEM7_BASE EQU 0x40007838\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_SIZE\r
+CYDEV_PHUB_TDMEM7_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM7_ORIG_TD0\r
+CYREG_PHUB_TDMEM7_ORIG_TD0 EQU 0x40007838\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM7_ORIG_TD1\r
+CYREG_PHUB_TDMEM7_ORIG_TD1 EQU 0x4000783c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_BASE\r
+CYDEV_PHUB_TDMEM8_BASE EQU 0x40007840\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_SIZE\r
+CYDEV_PHUB_TDMEM8_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM8_ORIG_TD0\r
+CYREG_PHUB_TDMEM8_ORIG_TD0 EQU 0x40007840\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM8_ORIG_TD1\r
+CYREG_PHUB_TDMEM8_ORIG_TD1 EQU 0x40007844\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_BASE\r
+CYDEV_PHUB_TDMEM9_BASE EQU 0x40007848\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_SIZE\r
+CYDEV_PHUB_TDMEM9_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM9_ORIG_TD0\r
+CYREG_PHUB_TDMEM9_ORIG_TD0 EQU 0x40007848\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM9_ORIG_TD1\r
+CYREG_PHUB_TDMEM9_ORIG_TD1 EQU 0x4000784c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_BASE\r
+CYDEV_PHUB_TDMEM10_BASE EQU 0x40007850\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_SIZE\r
+CYDEV_PHUB_TDMEM10_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM10_ORIG_TD0\r
+CYREG_PHUB_TDMEM10_ORIG_TD0 EQU 0x40007850\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM10_ORIG_TD1\r
+CYREG_PHUB_TDMEM10_ORIG_TD1 EQU 0x40007854\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_BASE\r
+CYDEV_PHUB_TDMEM11_BASE EQU 0x40007858\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_SIZE\r
+CYDEV_PHUB_TDMEM11_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM11_ORIG_TD0\r
+CYREG_PHUB_TDMEM11_ORIG_TD0 EQU 0x40007858\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM11_ORIG_TD1\r
+CYREG_PHUB_TDMEM11_ORIG_TD1 EQU 0x4000785c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_BASE\r
+CYDEV_PHUB_TDMEM12_BASE EQU 0x40007860\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_SIZE\r
+CYDEV_PHUB_TDMEM12_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM12_ORIG_TD0\r
+CYREG_PHUB_TDMEM12_ORIG_TD0 EQU 0x40007860\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM12_ORIG_TD1\r
+CYREG_PHUB_TDMEM12_ORIG_TD1 EQU 0x40007864\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_BASE\r
+CYDEV_PHUB_TDMEM13_BASE EQU 0x40007868\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_SIZE\r
+CYDEV_PHUB_TDMEM13_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM13_ORIG_TD0\r
+CYREG_PHUB_TDMEM13_ORIG_TD0 EQU 0x40007868\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM13_ORIG_TD1\r
+CYREG_PHUB_TDMEM13_ORIG_TD1 EQU 0x4000786c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_BASE\r
+CYDEV_PHUB_TDMEM14_BASE EQU 0x40007870\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_SIZE\r
+CYDEV_PHUB_TDMEM14_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM14_ORIG_TD0\r
+CYREG_PHUB_TDMEM14_ORIG_TD0 EQU 0x40007870\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM14_ORIG_TD1\r
+CYREG_PHUB_TDMEM14_ORIG_TD1 EQU 0x40007874\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_BASE\r
+CYDEV_PHUB_TDMEM15_BASE EQU 0x40007878\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_SIZE\r
+CYDEV_PHUB_TDMEM15_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM15_ORIG_TD0\r
+CYREG_PHUB_TDMEM15_ORIG_TD0 EQU 0x40007878\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM15_ORIG_TD1\r
+CYREG_PHUB_TDMEM15_ORIG_TD1 EQU 0x4000787c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_BASE\r
+CYDEV_PHUB_TDMEM16_BASE EQU 0x40007880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_SIZE\r
+CYDEV_PHUB_TDMEM16_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM16_ORIG_TD0\r
+CYREG_PHUB_TDMEM16_ORIG_TD0 EQU 0x40007880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM16_ORIG_TD1\r
+CYREG_PHUB_TDMEM16_ORIG_TD1 EQU 0x40007884\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_BASE\r
+CYDEV_PHUB_TDMEM17_BASE EQU 0x40007888\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_SIZE\r
+CYDEV_PHUB_TDMEM17_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM17_ORIG_TD0\r
+CYREG_PHUB_TDMEM17_ORIG_TD0 EQU 0x40007888\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM17_ORIG_TD1\r
+CYREG_PHUB_TDMEM17_ORIG_TD1 EQU 0x4000788c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_BASE\r
+CYDEV_PHUB_TDMEM18_BASE EQU 0x40007890\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_SIZE\r
+CYDEV_PHUB_TDMEM18_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM18_ORIG_TD0\r
+CYREG_PHUB_TDMEM18_ORIG_TD0 EQU 0x40007890\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM18_ORIG_TD1\r
+CYREG_PHUB_TDMEM18_ORIG_TD1 EQU 0x40007894\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_BASE\r
+CYDEV_PHUB_TDMEM19_BASE EQU 0x40007898\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_SIZE\r
+CYDEV_PHUB_TDMEM19_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM19_ORIG_TD0\r
+CYREG_PHUB_TDMEM19_ORIG_TD0 EQU 0x40007898\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM19_ORIG_TD1\r
+CYREG_PHUB_TDMEM19_ORIG_TD1 EQU 0x4000789c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_BASE\r
+CYDEV_PHUB_TDMEM20_BASE EQU 0x400078a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_SIZE\r
+CYDEV_PHUB_TDMEM20_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM20_ORIG_TD0\r
+CYREG_PHUB_TDMEM20_ORIG_TD0 EQU 0x400078a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM20_ORIG_TD1\r
+CYREG_PHUB_TDMEM20_ORIG_TD1 EQU 0x400078a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_BASE\r
+CYDEV_PHUB_TDMEM21_BASE EQU 0x400078a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_SIZE\r
+CYDEV_PHUB_TDMEM21_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM21_ORIG_TD0\r
+CYREG_PHUB_TDMEM21_ORIG_TD0 EQU 0x400078a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM21_ORIG_TD1\r
+CYREG_PHUB_TDMEM21_ORIG_TD1 EQU 0x400078ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_BASE\r
+CYDEV_PHUB_TDMEM22_BASE EQU 0x400078b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_SIZE\r
+CYDEV_PHUB_TDMEM22_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM22_ORIG_TD0\r
+CYREG_PHUB_TDMEM22_ORIG_TD0 EQU 0x400078b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM22_ORIG_TD1\r
+CYREG_PHUB_TDMEM22_ORIG_TD1 EQU 0x400078b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_BASE\r
+CYDEV_PHUB_TDMEM23_BASE EQU 0x400078b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_SIZE\r
+CYDEV_PHUB_TDMEM23_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM23_ORIG_TD0\r
+CYREG_PHUB_TDMEM23_ORIG_TD0 EQU 0x400078b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM23_ORIG_TD1\r
+CYREG_PHUB_TDMEM23_ORIG_TD1 EQU 0x400078bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_BASE\r
+CYDEV_PHUB_TDMEM24_BASE EQU 0x400078c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_SIZE\r
+CYDEV_PHUB_TDMEM24_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM24_ORIG_TD0\r
+CYREG_PHUB_TDMEM24_ORIG_TD0 EQU 0x400078c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM24_ORIG_TD1\r
+CYREG_PHUB_TDMEM24_ORIG_TD1 EQU 0x400078c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_BASE\r
+CYDEV_PHUB_TDMEM25_BASE EQU 0x400078c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_SIZE\r
+CYDEV_PHUB_TDMEM25_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM25_ORIG_TD0\r
+CYREG_PHUB_TDMEM25_ORIG_TD0 EQU 0x400078c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM25_ORIG_TD1\r
+CYREG_PHUB_TDMEM25_ORIG_TD1 EQU 0x400078cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_BASE\r
+CYDEV_PHUB_TDMEM26_BASE EQU 0x400078d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_SIZE\r
+CYDEV_PHUB_TDMEM26_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM26_ORIG_TD0\r
+CYREG_PHUB_TDMEM26_ORIG_TD0 EQU 0x400078d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM26_ORIG_TD1\r
+CYREG_PHUB_TDMEM26_ORIG_TD1 EQU 0x400078d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_BASE\r
+CYDEV_PHUB_TDMEM27_BASE EQU 0x400078d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_SIZE\r
+CYDEV_PHUB_TDMEM27_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM27_ORIG_TD0\r
+CYREG_PHUB_TDMEM27_ORIG_TD0 EQU 0x400078d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM27_ORIG_TD1\r
+CYREG_PHUB_TDMEM27_ORIG_TD1 EQU 0x400078dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_BASE\r
+CYDEV_PHUB_TDMEM28_BASE EQU 0x400078e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_SIZE\r
+CYDEV_PHUB_TDMEM28_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM28_ORIG_TD0\r
+CYREG_PHUB_TDMEM28_ORIG_TD0 EQU 0x400078e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM28_ORIG_TD1\r
+CYREG_PHUB_TDMEM28_ORIG_TD1 EQU 0x400078e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_BASE\r
+CYDEV_PHUB_TDMEM29_BASE EQU 0x400078e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_SIZE\r
+CYDEV_PHUB_TDMEM29_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM29_ORIG_TD0\r
+CYREG_PHUB_TDMEM29_ORIG_TD0 EQU 0x400078e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM29_ORIG_TD1\r
+CYREG_PHUB_TDMEM29_ORIG_TD1 EQU 0x400078ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_BASE\r
+CYDEV_PHUB_TDMEM30_BASE EQU 0x400078f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_SIZE\r
+CYDEV_PHUB_TDMEM30_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM30_ORIG_TD0\r
+CYREG_PHUB_TDMEM30_ORIG_TD0 EQU 0x400078f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM30_ORIG_TD1\r
+CYREG_PHUB_TDMEM30_ORIG_TD1 EQU 0x400078f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_BASE\r
+CYDEV_PHUB_TDMEM31_BASE EQU 0x400078f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_SIZE\r
+CYDEV_PHUB_TDMEM31_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM31_ORIG_TD0\r
+CYREG_PHUB_TDMEM31_ORIG_TD0 EQU 0x400078f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM31_ORIG_TD1\r
+CYREG_PHUB_TDMEM31_ORIG_TD1 EQU 0x400078fc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_BASE\r
+CYDEV_PHUB_TDMEM32_BASE EQU 0x40007900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_SIZE\r
+CYDEV_PHUB_TDMEM32_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM32_ORIG_TD0\r
+CYREG_PHUB_TDMEM32_ORIG_TD0 EQU 0x40007900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM32_ORIG_TD1\r
+CYREG_PHUB_TDMEM32_ORIG_TD1 EQU 0x40007904\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_BASE\r
+CYDEV_PHUB_TDMEM33_BASE EQU 0x40007908\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_SIZE\r
+CYDEV_PHUB_TDMEM33_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM33_ORIG_TD0\r
+CYREG_PHUB_TDMEM33_ORIG_TD0 EQU 0x40007908\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM33_ORIG_TD1\r
+CYREG_PHUB_TDMEM33_ORIG_TD1 EQU 0x4000790c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_BASE\r
+CYDEV_PHUB_TDMEM34_BASE EQU 0x40007910\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_SIZE\r
+CYDEV_PHUB_TDMEM34_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM34_ORIG_TD0\r
+CYREG_PHUB_TDMEM34_ORIG_TD0 EQU 0x40007910\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM34_ORIG_TD1\r
+CYREG_PHUB_TDMEM34_ORIG_TD1 EQU 0x40007914\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_BASE\r
+CYDEV_PHUB_TDMEM35_BASE EQU 0x40007918\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_SIZE\r
+CYDEV_PHUB_TDMEM35_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM35_ORIG_TD0\r
+CYREG_PHUB_TDMEM35_ORIG_TD0 EQU 0x40007918\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM35_ORIG_TD1\r
+CYREG_PHUB_TDMEM35_ORIG_TD1 EQU 0x4000791c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_BASE\r
+CYDEV_PHUB_TDMEM36_BASE EQU 0x40007920\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_SIZE\r
+CYDEV_PHUB_TDMEM36_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM36_ORIG_TD0\r
+CYREG_PHUB_TDMEM36_ORIG_TD0 EQU 0x40007920\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM36_ORIG_TD1\r
+CYREG_PHUB_TDMEM36_ORIG_TD1 EQU 0x40007924\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_BASE\r
+CYDEV_PHUB_TDMEM37_BASE EQU 0x40007928\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_SIZE\r
+CYDEV_PHUB_TDMEM37_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM37_ORIG_TD0\r
+CYREG_PHUB_TDMEM37_ORIG_TD0 EQU 0x40007928\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM37_ORIG_TD1\r
+CYREG_PHUB_TDMEM37_ORIG_TD1 EQU 0x4000792c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_BASE\r
+CYDEV_PHUB_TDMEM38_BASE EQU 0x40007930\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_SIZE\r
+CYDEV_PHUB_TDMEM38_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM38_ORIG_TD0\r
+CYREG_PHUB_TDMEM38_ORIG_TD0 EQU 0x40007930\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM38_ORIG_TD1\r
+CYREG_PHUB_TDMEM38_ORIG_TD1 EQU 0x40007934\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_BASE\r
+CYDEV_PHUB_TDMEM39_BASE EQU 0x40007938\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_SIZE\r
+CYDEV_PHUB_TDMEM39_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM39_ORIG_TD0\r
+CYREG_PHUB_TDMEM39_ORIG_TD0 EQU 0x40007938\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM39_ORIG_TD1\r
+CYREG_PHUB_TDMEM39_ORIG_TD1 EQU 0x4000793c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_BASE\r
+CYDEV_PHUB_TDMEM40_BASE EQU 0x40007940\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_SIZE\r
+CYDEV_PHUB_TDMEM40_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM40_ORIG_TD0\r
+CYREG_PHUB_TDMEM40_ORIG_TD0 EQU 0x40007940\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM40_ORIG_TD1\r
+CYREG_PHUB_TDMEM40_ORIG_TD1 EQU 0x40007944\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_BASE\r
+CYDEV_PHUB_TDMEM41_BASE EQU 0x40007948\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_SIZE\r
+CYDEV_PHUB_TDMEM41_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM41_ORIG_TD0\r
+CYREG_PHUB_TDMEM41_ORIG_TD0 EQU 0x40007948\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM41_ORIG_TD1\r
+CYREG_PHUB_TDMEM41_ORIG_TD1 EQU 0x4000794c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_BASE\r
+CYDEV_PHUB_TDMEM42_BASE EQU 0x40007950\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_SIZE\r
+CYDEV_PHUB_TDMEM42_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM42_ORIG_TD0\r
+CYREG_PHUB_TDMEM42_ORIG_TD0 EQU 0x40007950\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM42_ORIG_TD1\r
+CYREG_PHUB_TDMEM42_ORIG_TD1 EQU 0x40007954\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_BASE\r
+CYDEV_PHUB_TDMEM43_BASE EQU 0x40007958\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_SIZE\r
+CYDEV_PHUB_TDMEM43_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM43_ORIG_TD0\r
+CYREG_PHUB_TDMEM43_ORIG_TD0 EQU 0x40007958\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM43_ORIG_TD1\r
+CYREG_PHUB_TDMEM43_ORIG_TD1 EQU 0x4000795c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_BASE\r
+CYDEV_PHUB_TDMEM44_BASE EQU 0x40007960\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_SIZE\r
+CYDEV_PHUB_TDMEM44_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM44_ORIG_TD0\r
+CYREG_PHUB_TDMEM44_ORIG_TD0 EQU 0x40007960\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM44_ORIG_TD1\r
+CYREG_PHUB_TDMEM44_ORIG_TD1 EQU 0x40007964\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_BASE\r
+CYDEV_PHUB_TDMEM45_BASE EQU 0x40007968\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_SIZE\r
+CYDEV_PHUB_TDMEM45_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM45_ORIG_TD0\r
+CYREG_PHUB_TDMEM45_ORIG_TD0 EQU 0x40007968\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM45_ORIG_TD1\r
+CYREG_PHUB_TDMEM45_ORIG_TD1 EQU 0x4000796c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_BASE\r
+CYDEV_PHUB_TDMEM46_BASE EQU 0x40007970\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_SIZE\r
+CYDEV_PHUB_TDMEM46_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM46_ORIG_TD0\r
+CYREG_PHUB_TDMEM46_ORIG_TD0 EQU 0x40007970\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM46_ORIG_TD1\r
+CYREG_PHUB_TDMEM46_ORIG_TD1 EQU 0x40007974\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_BASE\r
+CYDEV_PHUB_TDMEM47_BASE EQU 0x40007978\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_SIZE\r
+CYDEV_PHUB_TDMEM47_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM47_ORIG_TD0\r
+CYREG_PHUB_TDMEM47_ORIG_TD0 EQU 0x40007978\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM47_ORIG_TD1\r
+CYREG_PHUB_TDMEM47_ORIG_TD1 EQU 0x4000797c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_BASE\r
+CYDEV_PHUB_TDMEM48_BASE EQU 0x40007980\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_SIZE\r
+CYDEV_PHUB_TDMEM48_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM48_ORIG_TD0\r
+CYREG_PHUB_TDMEM48_ORIG_TD0 EQU 0x40007980\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM48_ORIG_TD1\r
+CYREG_PHUB_TDMEM48_ORIG_TD1 EQU 0x40007984\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_BASE\r
+CYDEV_PHUB_TDMEM49_BASE EQU 0x40007988\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_SIZE\r
+CYDEV_PHUB_TDMEM49_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM49_ORIG_TD0\r
+CYREG_PHUB_TDMEM49_ORIG_TD0 EQU 0x40007988\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM49_ORIG_TD1\r
+CYREG_PHUB_TDMEM49_ORIG_TD1 EQU 0x4000798c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_BASE\r
+CYDEV_PHUB_TDMEM50_BASE EQU 0x40007990\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_SIZE\r
+CYDEV_PHUB_TDMEM50_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM50_ORIG_TD0\r
+CYREG_PHUB_TDMEM50_ORIG_TD0 EQU 0x40007990\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM50_ORIG_TD1\r
+CYREG_PHUB_TDMEM50_ORIG_TD1 EQU 0x40007994\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_BASE\r
+CYDEV_PHUB_TDMEM51_BASE EQU 0x40007998\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_SIZE\r
+CYDEV_PHUB_TDMEM51_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM51_ORIG_TD0\r
+CYREG_PHUB_TDMEM51_ORIG_TD0 EQU 0x40007998\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM51_ORIG_TD1\r
+CYREG_PHUB_TDMEM51_ORIG_TD1 EQU 0x4000799c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_BASE\r
+CYDEV_PHUB_TDMEM52_BASE EQU 0x400079a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_SIZE\r
+CYDEV_PHUB_TDMEM52_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM52_ORIG_TD0\r
+CYREG_PHUB_TDMEM52_ORIG_TD0 EQU 0x400079a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM52_ORIG_TD1\r
+CYREG_PHUB_TDMEM52_ORIG_TD1 EQU 0x400079a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_BASE\r
+CYDEV_PHUB_TDMEM53_BASE EQU 0x400079a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_SIZE\r
+CYDEV_PHUB_TDMEM53_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM53_ORIG_TD0\r
+CYREG_PHUB_TDMEM53_ORIG_TD0 EQU 0x400079a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM53_ORIG_TD1\r
+CYREG_PHUB_TDMEM53_ORIG_TD1 EQU 0x400079ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_BASE\r
+CYDEV_PHUB_TDMEM54_BASE EQU 0x400079b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_SIZE\r
+CYDEV_PHUB_TDMEM54_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM54_ORIG_TD0\r
+CYREG_PHUB_TDMEM54_ORIG_TD0 EQU 0x400079b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM54_ORIG_TD1\r
+CYREG_PHUB_TDMEM54_ORIG_TD1 EQU 0x400079b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_BASE\r
+CYDEV_PHUB_TDMEM55_BASE EQU 0x400079b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_SIZE\r
+CYDEV_PHUB_TDMEM55_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM55_ORIG_TD0\r
+CYREG_PHUB_TDMEM55_ORIG_TD0 EQU 0x400079b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM55_ORIG_TD1\r
+CYREG_PHUB_TDMEM55_ORIG_TD1 EQU 0x400079bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_BASE\r
+CYDEV_PHUB_TDMEM56_BASE EQU 0x400079c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_SIZE\r
+CYDEV_PHUB_TDMEM56_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM56_ORIG_TD0\r
+CYREG_PHUB_TDMEM56_ORIG_TD0 EQU 0x400079c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM56_ORIG_TD1\r
+CYREG_PHUB_TDMEM56_ORIG_TD1 EQU 0x400079c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_BASE\r
+CYDEV_PHUB_TDMEM57_BASE EQU 0x400079c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_SIZE\r
+CYDEV_PHUB_TDMEM57_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM57_ORIG_TD0\r
+CYREG_PHUB_TDMEM57_ORIG_TD0 EQU 0x400079c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM57_ORIG_TD1\r
+CYREG_PHUB_TDMEM57_ORIG_TD1 EQU 0x400079cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_BASE\r
+CYDEV_PHUB_TDMEM58_BASE EQU 0x400079d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_SIZE\r
+CYDEV_PHUB_TDMEM58_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM58_ORIG_TD0\r
+CYREG_PHUB_TDMEM58_ORIG_TD0 EQU 0x400079d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM58_ORIG_TD1\r
+CYREG_PHUB_TDMEM58_ORIG_TD1 EQU 0x400079d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_BASE\r
+CYDEV_PHUB_TDMEM59_BASE EQU 0x400079d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_SIZE\r
+CYDEV_PHUB_TDMEM59_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM59_ORIG_TD0\r
+CYREG_PHUB_TDMEM59_ORIG_TD0 EQU 0x400079d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM59_ORIG_TD1\r
+CYREG_PHUB_TDMEM59_ORIG_TD1 EQU 0x400079dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_BASE\r
+CYDEV_PHUB_TDMEM60_BASE EQU 0x400079e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_SIZE\r
+CYDEV_PHUB_TDMEM60_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM60_ORIG_TD0\r
+CYREG_PHUB_TDMEM60_ORIG_TD0 EQU 0x400079e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM60_ORIG_TD1\r
+CYREG_PHUB_TDMEM60_ORIG_TD1 EQU 0x400079e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_BASE\r
+CYDEV_PHUB_TDMEM61_BASE EQU 0x400079e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_SIZE\r
+CYDEV_PHUB_TDMEM61_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM61_ORIG_TD0\r
+CYREG_PHUB_TDMEM61_ORIG_TD0 EQU 0x400079e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM61_ORIG_TD1\r
+CYREG_PHUB_TDMEM61_ORIG_TD1 EQU 0x400079ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_BASE\r
+CYDEV_PHUB_TDMEM62_BASE EQU 0x400079f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_SIZE\r
+CYDEV_PHUB_TDMEM62_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM62_ORIG_TD0\r
+CYREG_PHUB_TDMEM62_ORIG_TD0 EQU 0x400079f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM62_ORIG_TD1\r
+CYREG_PHUB_TDMEM62_ORIG_TD1 EQU 0x400079f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_BASE\r
+CYDEV_PHUB_TDMEM63_BASE EQU 0x400079f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_SIZE\r
+CYDEV_PHUB_TDMEM63_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM63_ORIG_TD0\r
+CYREG_PHUB_TDMEM63_ORIG_TD0 EQU 0x400079f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM63_ORIG_TD1\r
+CYREG_PHUB_TDMEM63_ORIG_TD1 EQU 0x400079fc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_BASE\r
+CYDEV_PHUB_TDMEM64_BASE EQU 0x40007a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_SIZE\r
+CYDEV_PHUB_TDMEM64_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM64_ORIG_TD0\r
+CYREG_PHUB_TDMEM64_ORIG_TD0 EQU 0x40007a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM64_ORIG_TD1\r
+CYREG_PHUB_TDMEM64_ORIG_TD1 EQU 0x40007a04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_BASE\r
+CYDEV_PHUB_TDMEM65_BASE EQU 0x40007a08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_SIZE\r
+CYDEV_PHUB_TDMEM65_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM65_ORIG_TD0\r
+CYREG_PHUB_TDMEM65_ORIG_TD0 EQU 0x40007a08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM65_ORIG_TD1\r
+CYREG_PHUB_TDMEM65_ORIG_TD1 EQU 0x40007a0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_BASE\r
+CYDEV_PHUB_TDMEM66_BASE EQU 0x40007a10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_SIZE\r
+CYDEV_PHUB_TDMEM66_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM66_ORIG_TD0\r
+CYREG_PHUB_TDMEM66_ORIG_TD0 EQU 0x40007a10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM66_ORIG_TD1\r
+CYREG_PHUB_TDMEM66_ORIG_TD1 EQU 0x40007a14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_BASE\r
+CYDEV_PHUB_TDMEM67_BASE EQU 0x40007a18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_SIZE\r
+CYDEV_PHUB_TDMEM67_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM67_ORIG_TD0\r
+CYREG_PHUB_TDMEM67_ORIG_TD0 EQU 0x40007a18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM67_ORIG_TD1\r
+CYREG_PHUB_TDMEM67_ORIG_TD1 EQU 0x40007a1c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_BASE\r
+CYDEV_PHUB_TDMEM68_BASE EQU 0x40007a20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_SIZE\r
+CYDEV_PHUB_TDMEM68_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM68_ORIG_TD0\r
+CYREG_PHUB_TDMEM68_ORIG_TD0 EQU 0x40007a20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM68_ORIG_TD1\r
+CYREG_PHUB_TDMEM68_ORIG_TD1 EQU 0x40007a24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_BASE\r
+CYDEV_PHUB_TDMEM69_BASE EQU 0x40007a28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_SIZE\r
+CYDEV_PHUB_TDMEM69_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM69_ORIG_TD0\r
+CYREG_PHUB_TDMEM69_ORIG_TD0 EQU 0x40007a28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM69_ORIG_TD1\r
+CYREG_PHUB_TDMEM69_ORIG_TD1 EQU 0x40007a2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_BASE\r
+CYDEV_PHUB_TDMEM70_BASE EQU 0x40007a30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_SIZE\r
+CYDEV_PHUB_TDMEM70_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM70_ORIG_TD0\r
+CYREG_PHUB_TDMEM70_ORIG_TD0 EQU 0x40007a30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM70_ORIG_TD1\r
+CYREG_PHUB_TDMEM70_ORIG_TD1 EQU 0x40007a34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_BASE\r
+CYDEV_PHUB_TDMEM71_BASE EQU 0x40007a38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_SIZE\r
+CYDEV_PHUB_TDMEM71_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM71_ORIG_TD0\r
+CYREG_PHUB_TDMEM71_ORIG_TD0 EQU 0x40007a38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM71_ORIG_TD1\r
+CYREG_PHUB_TDMEM71_ORIG_TD1 EQU 0x40007a3c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_BASE\r
+CYDEV_PHUB_TDMEM72_BASE EQU 0x40007a40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_SIZE\r
+CYDEV_PHUB_TDMEM72_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM72_ORIG_TD0\r
+CYREG_PHUB_TDMEM72_ORIG_TD0 EQU 0x40007a40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM72_ORIG_TD1\r
+CYREG_PHUB_TDMEM72_ORIG_TD1 EQU 0x40007a44\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_BASE\r
+CYDEV_PHUB_TDMEM73_BASE EQU 0x40007a48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_SIZE\r
+CYDEV_PHUB_TDMEM73_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM73_ORIG_TD0\r
+CYREG_PHUB_TDMEM73_ORIG_TD0 EQU 0x40007a48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM73_ORIG_TD1\r
+CYREG_PHUB_TDMEM73_ORIG_TD1 EQU 0x40007a4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_BASE\r
+CYDEV_PHUB_TDMEM74_BASE EQU 0x40007a50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_SIZE\r
+CYDEV_PHUB_TDMEM74_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM74_ORIG_TD0\r
+CYREG_PHUB_TDMEM74_ORIG_TD0 EQU 0x40007a50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM74_ORIG_TD1\r
+CYREG_PHUB_TDMEM74_ORIG_TD1 EQU 0x40007a54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_BASE\r
+CYDEV_PHUB_TDMEM75_BASE EQU 0x40007a58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_SIZE\r
+CYDEV_PHUB_TDMEM75_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM75_ORIG_TD0\r
+CYREG_PHUB_TDMEM75_ORIG_TD0 EQU 0x40007a58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM75_ORIG_TD1\r
+CYREG_PHUB_TDMEM75_ORIG_TD1 EQU 0x40007a5c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_BASE\r
+CYDEV_PHUB_TDMEM76_BASE EQU 0x40007a60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_SIZE\r
+CYDEV_PHUB_TDMEM76_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM76_ORIG_TD0\r
+CYREG_PHUB_TDMEM76_ORIG_TD0 EQU 0x40007a60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM76_ORIG_TD1\r
+CYREG_PHUB_TDMEM76_ORIG_TD1 EQU 0x40007a64\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_BASE\r
+CYDEV_PHUB_TDMEM77_BASE EQU 0x40007a68\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_SIZE\r
+CYDEV_PHUB_TDMEM77_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM77_ORIG_TD0\r
+CYREG_PHUB_TDMEM77_ORIG_TD0 EQU 0x40007a68\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM77_ORIG_TD1\r
+CYREG_PHUB_TDMEM77_ORIG_TD1 EQU 0x40007a6c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_BASE\r
+CYDEV_PHUB_TDMEM78_BASE EQU 0x40007a70\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_SIZE\r
+CYDEV_PHUB_TDMEM78_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM78_ORIG_TD0\r
+CYREG_PHUB_TDMEM78_ORIG_TD0 EQU 0x40007a70\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM78_ORIG_TD1\r
+CYREG_PHUB_TDMEM78_ORIG_TD1 EQU 0x40007a74\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_BASE\r
+CYDEV_PHUB_TDMEM79_BASE EQU 0x40007a78\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_SIZE\r
+CYDEV_PHUB_TDMEM79_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM79_ORIG_TD0\r
+CYREG_PHUB_TDMEM79_ORIG_TD0 EQU 0x40007a78\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM79_ORIG_TD1\r
+CYREG_PHUB_TDMEM79_ORIG_TD1 EQU 0x40007a7c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_BASE\r
+CYDEV_PHUB_TDMEM80_BASE EQU 0x40007a80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_SIZE\r
+CYDEV_PHUB_TDMEM80_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM80_ORIG_TD0\r
+CYREG_PHUB_TDMEM80_ORIG_TD0 EQU 0x40007a80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM80_ORIG_TD1\r
+CYREG_PHUB_TDMEM80_ORIG_TD1 EQU 0x40007a84\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_BASE\r
+CYDEV_PHUB_TDMEM81_BASE EQU 0x40007a88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_SIZE\r
+CYDEV_PHUB_TDMEM81_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM81_ORIG_TD0\r
+CYREG_PHUB_TDMEM81_ORIG_TD0 EQU 0x40007a88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM81_ORIG_TD1\r
+CYREG_PHUB_TDMEM81_ORIG_TD1 EQU 0x40007a8c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_BASE\r
+CYDEV_PHUB_TDMEM82_BASE EQU 0x40007a90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_SIZE\r
+CYDEV_PHUB_TDMEM82_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM82_ORIG_TD0\r
+CYREG_PHUB_TDMEM82_ORIG_TD0 EQU 0x40007a90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM82_ORIG_TD1\r
+CYREG_PHUB_TDMEM82_ORIG_TD1 EQU 0x40007a94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_BASE\r
+CYDEV_PHUB_TDMEM83_BASE EQU 0x40007a98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_SIZE\r
+CYDEV_PHUB_TDMEM83_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM83_ORIG_TD0\r
+CYREG_PHUB_TDMEM83_ORIG_TD0 EQU 0x40007a98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM83_ORIG_TD1\r
+CYREG_PHUB_TDMEM83_ORIG_TD1 EQU 0x40007a9c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_BASE\r
+CYDEV_PHUB_TDMEM84_BASE EQU 0x40007aa0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_SIZE\r
+CYDEV_PHUB_TDMEM84_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM84_ORIG_TD0\r
+CYREG_PHUB_TDMEM84_ORIG_TD0 EQU 0x40007aa0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM84_ORIG_TD1\r
+CYREG_PHUB_TDMEM84_ORIG_TD1 EQU 0x40007aa4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_BASE\r
+CYDEV_PHUB_TDMEM85_BASE EQU 0x40007aa8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_SIZE\r
+CYDEV_PHUB_TDMEM85_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM85_ORIG_TD0\r
+CYREG_PHUB_TDMEM85_ORIG_TD0 EQU 0x40007aa8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM85_ORIG_TD1\r
+CYREG_PHUB_TDMEM85_ORIG_TD1 EQU 0x40007aac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_BASE\r
+CYDEV_PHUB_TDMEM86_BASE EQU 0x40007ab0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_SIZE\r
+CYDEV_PHUB_TDMEM86_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM86_ORIG_TD0\r
+CYREG_PHUB_TDMEM86_ORIG_TD0 EQU 0x40007ab0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM86_ORIG_TD1\r
+CYREG_PHUB_TDMEM86_ORIG_TD1 EQU 0x40007ab4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_BASE\r
+CYDEV_PHUB_TDMEM87_BASE EQU 0x40007ab8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_SIZE\r
+CYDEV_PHUB_TDMEM87_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM87_ORIG_TD0\r
+CYREG_PHUB_TDMEM87_ORIG_TD0 EQU 0x40007ab8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM87_ORIG_TD1\r
+CYREG_PHUB_TDMEM87_ORIG_TD1 EQU 0x40007abc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_BASE\r
+CYDEV_PHUB_TDMEM88_BASE EQU 0x40007ac0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_SIZE\r
+CYDEV_PHUB_TDMEM88_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM88_ORIG_TD0\r
+CYREG_PHUB_TDMEM88_ORIG_TD0 EQU 0x40007ac0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM88_ORIG_TD1\r
+CYREG_PHUB_TDMEM88_ORIG_TD1 EQU 0x40007ac4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_BASE\r
+CYDEV_PHUB_TDMEM89_BASE EQU 0x40007ac8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_SIZE\r
+CYDEV_PHUB_TDMEM89_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM89_ORIG_TD0\r
+CYREG_PHUB_TDMEM89_ORIG_TD0 EQU 0x40007ac8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM89_ORIG_TD1\r
+CYREG_PHUB_TDMEM89_ORIG_TD1 EQU 0x40007acc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_BASE\r
+CYDEV_PHUB_TDMEM90_BASE EQU 0x40007ad0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_SIZE\r
+CYDEV_PHUB_TDMEM90_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM90_ORIG_TD0\r
+CYREG_PHUB_TDMEM90_ORIG_TD0 EQU 0x40007ad0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM90_ORIG_TD1\r
+CYREG_PHUB_TDMEM90_ORIG_TD1 EQU 0x40007ad4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_BASE\r
+CYDEV_PHUB_TDMEM91_BASE EQU 0x40007ad8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_SIZE\r
+CYDEV_PHUB_TDMEM91_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM91_ORIG_TD0\r
+CYREG_PHUB_TDMEM91_ORIG_TD0 EQU 0x40007ad8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM91_ORIG_TD1\r
+CYREG_PHUB_TDMEM91_ORIG_TD1 EQU 0x40007adc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_BASE\r
+CYDEV_PHUB_TDMEM92_BASE EQU 0x40007ae0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_SIZE\r
+CYDEV_PHUB_TDMEM92_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM92_ORIG_TD0\r
+CYREG_PHUB_TDMEM92_ORIG_TD0 EQU 0x40007ae0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM92_ORIG_TD1\r
+CYREG_PHUB_TDMEM92_ORIG_TD1 EQU 0x40007ae4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_BASE\r
+CYDEV_PHUB_TDMEM93_BASE EQU 0x40007ae8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_SIZE\r
+CYDEV_PHUB_TDMEM93_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM93_ORIG_TD0\r
+CYREG_PHUB_TDMEM93_ORIG_TD0 EQU 0x40007ae8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM93_ORIG_TD1\r
+CYREG_PHUB_TDMEM93_ORIG_TD1 EQU 0x40007aec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_BASE\r
+CYDEV_PHUB_TDMEM94_BASE EQU 0x40007af0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_SIZE\r
+CYDEV_PHUB_TDMEM94_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM94_ORIG_TD0\r
+CYREG_PHUB_TDMEM94_ORIG_TD0 EQU 0x40007af0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM94_ORIG_TD1\r
+CYREG_PHUB_TDMEM94_ORIG_TD1 EQU 0x40007af4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_BASE\r
+CYDEV_PHUB_TDMEM95_BASE EQU 0x40007af8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_SIZE\r
+CYDEV_PHUB_TDMEM95_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM95_ORIG_TD0\r
+CYREG_PHUB_TDMEM95_ORIG_TD0 EQU 0x40007af8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM95_ORIG_TD1\r
+CYREG_PHUB_TDMEM95_ORIG_TD1 EQU 0x40007afc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_BASE\r
+CYDEV_PHUB_TDMEM96_BASE EQU 0x40007b00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_SIZE\r
+CYDEV_PHUB_TDMEM96_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM96_ORIG_TD0\r
+CYREG_PHUB_TDMEM96_ORIG_TD0 EQU 0x40007b00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM96_ORIG_TD1\r
+CYREG_PHUB_TDMEM96_ORIG_TD1 EQU 0x40007b04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_BASE\r
+CYDEV_PHUB_TDMEM97_BASE EQU 0x40007b08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_SIZE\r
+CYDEV_PHUB_TDMEM97_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM97_ORIG_TD0\r
+CYREG_PHUB_TDMEM97_ORIG_TD0 EQU 0x40007b08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM97_ORIG_TD1\r
+CYREG_PHUB_TDMEM97_ORIG_TD1 EQU 0x40007b0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_BASE\r
+CYDEV_PHUB_TDMEM98_BASE EQU 0x40007b10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_SIZE\r
+CYDEV_PHUB_TDMEM98_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM98_ORIG_TD0\r
+CYREG_PHUB_TDMEM98_ORIG_TD0 EQU 0x40007b10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM98_ORIG_TD1\r
+CYREG_PHUB_TDMEM98_ORIG_TD1 EQU 0x40007b14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_BASE\r
+CYDEV_PHUB_TDMEM99_BASE EQU 0x40007b18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_SIZE\r
+CYDEV_PHUB_TDMEM99_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM99_ORIG_TD0\r
+CYREG_PHUB_TDMEM99_ORIG_TD0 EQU 0x40007b18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM99_ORIG_TD1\r
+CYREG_PHUB_TDMEM99_ORIG_TD1 EQU 0x40007b1c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_BASE\r
+CYDEV_PHUB_TDMEM100_BASE EQU 0x40007b20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_SIZE\r
+CYDEV_PHUB_TDMEM100_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM100_ORIG_TD0\r
+CYREG_PHUB_TDMEM100_ORIG_TD0 EQU 0x40007b20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM100_ORIG_TD1\r
+CYREG_PHUB_TDMEM100_ORIG_TD1 EQU 0x40007b24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_BASE\r
+CYDEV_PHUB_TDMEM101_BASE EQU 0x40007b28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_SIZE\r
+CYDEV_PHUB_TDMEM101_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM101_ORIG_TD0\r
+CYREG_PHUB_TDMEM101_ORIG_TD0 EQU 0x40007b28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM101_ORIG_TD1\r
+CYREG_PHUB_TDMEM101_ORIG_TD1 EQU 0x40007b2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_BASE\r
+CYDEV_PHUB_TDMEM102_BASE EQU 0x40007b30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_SIZE\r
+CYDEV_PHUB_TDMEM102_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM102_ORIG_TD0\r
+CYREG_PHUB_TDMEM102_ORIG_TD0 EQU 0x40007b30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM102_ORIG_TD1\r
+CYREG_PHUB_TDMEM102_ORIG_TD1 EQU 0x40007b34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_BASE\r
+CYDEV_PHUB_TDMEM103_BASE EQU 0x40007b38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_SIZE\r
+CYDEV_PHUB_TDMEM103_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM103_ORIG_TD0\r
+CYREG_PHUB_TDMEM103_ORIG_TD0 EQU 0x40007b38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM103_ORIG_TD1\r
+CYREG_PHUB_TDMEM103_ORIG_TD1 EQU 0x40007b3c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_BASE\r
+CYDEV_PHUB_TDMEM104_BASE EQU 0x40007b40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_SIZE\r
+CYDEV_PHUB_TDMEM104_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM104_ORIG_TD0\r
+CYREG_PHUB_TDMEM104_ORIG_TD0 EQU 0x40007b40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM104_ORIG_TD1\r
+CYREG_PHUB_TDMEM104_ORIG_TD1 EQU 0x40007b44\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_BASE\r
+CYDEV_PHUB_TDMEM105_BASE EQU 0x40007b48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_SIZE\r
+CYDEV_PHUB_TDMEM105_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM105_ORIG_TD0\r
+CYREG_PHUB_TDMEM105_ORIG_TD0 EQU 0x40007b48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM105_ORIG_TD1\r
+CYREG_PHUB_TDMEM105_ORIG_TD1 EQU 0x40007b4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_BASE\r
+CYDEV_PHUB_TDMEM106_BASE EQU 0x40007b50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_SIZE\r
+CYDEV_PHUB_TDMEM106_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM106_ORIG_TD0\r
+CYREG_PHUB_TDMEM106_ORIG_TD0 EQU 0x40007b50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM106_ORIG_TD1\r
+CYREG_PHUB_TDMEM106_ORIG_TD1 EQU 0x40007b54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_BASE\r
+CYDEV_PHUB_TDMEM107_BASE EQU 0x40007b58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_SIZE\r
+CYDEV_PHUB_TDMEM107_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM107_ORIG_TD0\r
+CYREG_PHUB_TDMEM107_ORIG_TD0 EQU 0x40007b58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM107_ORIG_TD1\r
+CYREG_PHUB_TDMEM107_ORIG_TD1 EQU 0x40007b5c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_BASE\r
+CYDEV_PHUB_TDMEM108_BASE EQU 0x40007b60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_SIZE\r
+CYDEV_PHUB_TDMEM108_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM108_ORIG_TD0\r
+CYREG_PHUB_TDMEM108_ORIG_TD0 EQU 0x40007b60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM108_ORIG_TD1\r
+CYREG_PHUB_TDMEM108_ORIG_TD1 EQU 0x40007b64\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_BASE\r
+CYDEV_PHUB_TDMEM109_BASE EQU 0x40007b68\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_SIZE\r
+CYDEV_PHUB_TDMEM109_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM109_ORIG_TD0\r
+CYREG_PHUB_TDMEM109_ORIG_TD0 EQU 0x40007b68\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM109_ORIG_TD1\r
+CYREG_PHUB_TDMEM109_ORIG_TD1 EQU 0x40007b6c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_BASE\r
+CYDEV_PHUB_TDMEM110_BASE EQU 0x40007b70\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_SIZE\r
+CYDEV_PHUB_TDMEM110_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM110_ORIG_TD0\r
+CYREG_PHUB_TDMEM110_ORIG_TD0 EQU 0x40007b70\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM110_ORIG_TD1\r
+CYREG_PHUB_TDMEM110_ORIG_TD1 EQU 0x40007b74\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_BASE\r
+CYDEV_PHUB_TDMEM111_BASE EQU 0x40007b78\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_SIZE\r
+CYDEV_PHUB_TDMEM111_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM111_ORIG_TD0\r
+CYREG_PHUB_TDMEM111_ORIG_TD0 EQU 0x40007b78\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM111_ORIG_TD1\r
+CYREG_PHUB_TDMEM111_ORIG_TD1 EQU 0x40007b7c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_BASE\r
+CYDEV_PHUB_TDMEM112_BASE EQU 0x40007b80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_SIZE\r
+CYDEV_PHUB_TDMEM112_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM112_ORIG_TD0\r
+CYREG_PHUB_TDMEM112_ORIG_TD0 EQU 0x40007b80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM112_ORIG_TD1\r
+CYREG_PHUB_TDMEM112_ORIG_TD1 EQU 0x40007b84\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_BASE\r
+CYDEV_PHUB_TDMEM113_BASE EQU 0x40007b88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_SIZE\r
+CYDEV_PHUB_TDMEM113_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM113_ORIG_TD0\r
+CYREG_PHUB_TDMEM113_ORIG_TD0 EQU 0x40007b88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM113_ORIG_TD1\r
+CYREG_PHUB_TDMEM113_ORIG_TD1 EQU 0x40007b8c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_BASE\r
+CYDEV_PHUB_TDMEM114_BASE EQU 0x40007b90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_SIZE\r
+CYDEV_PHUB_TDMEM114_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM114_ORIG_TD0\r
+CYREG_PHUB_TDMEM114_ORIG_TD0 EQU 0x40007b90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM114_ORIG_TD1\r
+CYREG_PHUB_TDMEM114_ORIG_TD1 EQU 0x40007b94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_BASE\r
+CYDEV_PHUB_TDMEM115_BASE EQU 0x40007b98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_SIZE\r
+CYDEV_PHUB_TDMEM115_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM115_ORIG_TD0\r
+CYREG_PHUB_TDMEM115_ORIG_TD0 EQU 0x40007b98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM115_ORIG_TD1\r
+CYREG_PHUB_TDMEM115_ORIG_TD1 EQU 0x40007b9c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_BASE\r
+CYDEV_PHUB_TDMEM116_BASE EQU 0x40007ba0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_SIZE\r
+CYDEV_PHUB_TDMEM116_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM116_ORIG_TD0\r
+CYREG_PHUB_TDMEM116_ORIG_TD0 EQU 0x40007ba0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM116_ORIG_TD1\r
+CYREG_PHUB_TDMEM116_ORIG_TD1 EQU 0x40007ba4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_BASE\r
+CYDEV_PHUB_TDMEM117_BASE EQU 0x40007ba8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_SIZE\r
+CYDEV_PHUB_TDMEM117_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM117_ORIG_TD0\r
+CYREG_PHUB_TDMEM117_ORIG_TD0 EQU 0x40007ba8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM117_ORIG_TD1\r
+CYREG_PHUB_TDMEM117_ORIG_TD1 EQU 0x40007bac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_BASE\r
+CYDEV_PHUB_TDMEM118_BASE EQU 0x40007bb0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_SIZE\r
+CYDEV_PHUB_TDMEM118_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM118_ORIG_TD0\r
+CYREG_PHUB_TDMEM118_ORIG_TD0 EQU 0x40007bb0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM118_ORIG_TD1\r
+CYREG_PHUB_TDMEM118_ORIG_TD1 EQU 0x40007bb4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_BASE\r
+CYDEV_PHUB_TDMEM119_BASE EQU 0x40007bb8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_SIZE\r
+CYDEV_PHUB_TDMEM119_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM119_ORIG_TD0\r
+CYREG_PHUB_TDMEM119_ORIG_TD0 EQU 0x40007bb8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM119_ORIG_TD1\r
+CYREG_PHUB_TDMEM119_ORIG_TD1 EQU 0x40007bbc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_BASE\r
+CYDEV_PHUB_TDMEM120_BASE EQU 0x40007bc0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_SIZE\r
+CYDEV_PHUB_TDMEM120_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM120_ORIG_TD0\r
+CYREG_PHUB_TDMEM120_ORIG_TD0 EQU 0x40007bc0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM120_ORIG_TD1\r
+CYREG_PHUB_TDMEM120_ORIG_TD1 EQU 0x40007bc4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_BASE\r
+CYDEV_PHUB_TDMEM121_BASE EQU 0x40007bc8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_SIZE\r
+CYDEV_PHUB_TDMEM121_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM121_ORIG_TD0\r
+CYREG_PHUB_TDMEM121_ORIG_TD0 EQU 0x40007bc8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM121_ORIG_TD1\r
+CYREG_PHUB_TDMEM121_ORIG_TD1 EQU 0x40007bcc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_BASE\r
+CYDEV_PHUB_TDMEM122_BASE EQU 0x40007bd0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_SIZE\r
+CYDEV_PHUB_TDMEM122_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM122_ORIG_TD0\r
+CYREG_PHUB_TDMEM122_ORIG_TD0 EQU 0x40007bd0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM122_ORIG_TD1\r
+CYREG_PHUB_TDMEM122_ORIG_TD1 EQU 0x40007bd4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_BASE\r
+CYDEV_PHUB_TDMEM123_BASE EQU 0x40007bd8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_SIZE\r
+CYDEV_PHUB_TDMEM123_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM123_ORIG_TD0\r
+CYREG_PHUB_TDMEM123_ORIG_TD0 EQU 0x40007bd8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM123_ORIG_TD1\r
+CYREG_PHUB_TDMEM123_ORIG_TD1 EQU 0x40007bdc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_BASE\r
+CYDEV_PHUB_TDMEM124_BASE EQU 0x40007be0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_SIZE\r
+CYDEV_PHUB_TDMEM124_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM124_ORIG_TD0\r
+CYREG_PHUB_TDMEM124_ORIG_TD0 EQU 0x40007be0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM124_ORIG_TD1\r
+CYREG_PHUB_TDMEM124_ORIG_TD1 EQU 0x40007be4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_BASE\r
+CYDEV_PHUB_TDMEM125_BASE EQU 0x40007be8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_SIZE\r
+CYDEV_PHUB_TDMEM125_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM125_ORIG_TD0\r
+CYREG_PHUB_TDMEM125_ORIG_TD0 EQU 0x40007be8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM125_ORIG_TD1\r
+CYREG_PHUB_TDMEM125_ORIG_TD1 EQU 0x40007bec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_BASE\r
+CYDEV_PHUB_TDMEM126_BASE EQU 0x40007bf0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_SIZE\r
+CYDEV_PHUB_TDMEM126_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM126_ORIG_TD0\r
+CYREG_PHUB_TDMEM126_ORIG_TD0 EQU 0x40007bf0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM126_ORIG_TD1\r
+CYREG_PHUB_TDMEM126_ORIG_TD1 EQU 0x40007bf4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_BASE\r
+CYDEV_PHUB_TDMEM127_BASE EQU 0x40007bf8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_SIZE\r
+CYDEV_PHUB_TDMEM127_SIZE EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM127_ORIG_TD0\r
+CYREG_PHUB_TDMEM127_ORIG_TD0 EQU 0x40007bf8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PHUB_TDMEM127_ORIG_TD1\r
+CYREG_PHUB_TDMEM127_ORIG_TD1 EQU 0x40007bfc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EE_BASE\r
+CYDEV_EE_BASE EQU 0x40008000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EE_SIZE\r
+CYDEV_EE_SIZE EQU 0x00000800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_EE_DATA_MBASE\r
+CYREG_EE_DATA_MBASE EQU 0x40008000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_EE_DATA_MSIZE\r
+CYREG_EE_DATA_MSIZE EQU 0x00000800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_BASE\r
+CYDEV_CAN0_BASE EQU 0x4000a000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_SIZE\r
+CYDEV_CAN0_SIZE EQU 0x000002a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_CSR_BASE\r
+CYDEV_CAN0_CSR_BASE EQU 0x4000a000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_CSR_SIZE\r
+CYDEV_CAN0_CSR_SIZE EQU 0x00000018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_CSR_INT_SR\r
+CYREG_CAN0_CSR_INT_SR EQU 0x4000a000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_CSR_INT_EN\r
+CYREG_CAN0_CSR_INT_EN EQU 0x4000a004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_CSR_BUF_SR\r
+CYREG_CAN0_CSR_BUF_SR EQU 0x4000a008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_CSR_ERR_SR\r
+CYREG_CAN0_CSR_ERR_SR EQU 0x4000a00c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_CSR_CMD\r
+CYREG_CAN0_CSR_CMD EQU 0x4000a010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_CSR_CFG\r
+CYREG_CAN0_CSR_CFG EQU 0x4000a014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX0_BASE\r
+CYDEV_CAN0_TX0_BASE EQU 0x4000a020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX0_SIZE\r
+CYDEV_CAN0_TX0_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX0_CMD\r
+CYREG_CAN0_TX0_CMD EQU 0x4000a020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX0_ID\r
+CYREG_CAN0_TX0_ID EQU 0x4000a024\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX0_DH\r
+CYREG_CAN0_TX0_DH EQU 0x4000a028\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX0_DL\r
+CYREG_CAN0_TX0_DL EQU 0x4000a02c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX1_BASE\r
+CYDEV_CAN0_TX1_BASE EQU 0x4000a030\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX1_SIZE\r
+CYDEV_CAN0_TX1_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX1_CMD\r
+CYREG_CAN0_TX1_CMD EQU 0x4000a030\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX1_ID\r
+CYREG_CAN0_TX1_ID EQU 0x4000a034\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX1_DH\r
+CYREG_CAN0_TX1_DH EQU 0x4000a038\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX1_DL\r
+CYREG_CAN0_TX1_DL EQU 0x4000a03c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX2_BASE\r
+CYDEV_CAN0_TX2_BASE EQU 0x4000a040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX2_SIZE\r
+CYDEV_CAN0_TX2_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX2_CMD\r
+CYREG_CAN0_TX2_CMD EQU 0x4000a040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX2_ID\r
+CYREG_CAN0_TX2_ID EQU 0x4000a044\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX2_DH\r
+CYREG_CAN0_TX2_DH EQU 0x4000a048\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX2_DL\r
+CYREG_CAN0_TX2_DL EQU 0x4000a04c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX3_BASE\r
+CYDEV_CAN0_TX3_BASE EQU 0x4000a050\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX3_SIZE\r
+CYDEV_CAN0_TX3_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX3_CMD\r
+CYREG_CAN0_TX3_CMD EQU 0x4000a050\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX3_ID\r
+CYREG_CAN0_TX3_ID EQU 0x4000a054\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX3_DH\r
+CYREG_CAN0_TX3_DH EQU 0x4000a058\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX3_DL\r
+CYREG_CAN0_TX3_DL EQU 0x4000a05c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX4_BASE\r
+CYDEV_CAN0_TX4_BASE EQU 0x4000a060\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX4_SIZE\r
+CYDEV_CAN0_TX4_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX4_CMD\r
+CYREG_CAN0_TX4_CMD EQU 0x4000a060\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX4_ID\r
+CYREG_CAN0_TX4_ID EQU 0x4000a064\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX4_DH\r
+CYREG_CAN0_TX4_DH EQU 0x4000a068\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX4_DL\r
+CYREG_CAN0_TX4_DL EQU 0x4000a06c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX5_BASE\r
+CYDEV_CAN0_TX5_BASE EQU 0x4000a070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX5_SIZE\r
+CYDEV_CAN0_TX5_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX5_CMD\r
+CYREG_CAN0_TX5_CMD EQU 0x4000a070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX5_ID\r
+CYREG_CAN0_TX5_ID EQU 0x4000a074\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX5_DH\r
+CYREG_CAN0_TX5_DH EQU 0x4000a078\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX5_DL\r
+CYREG_CAN0_TX5_DL EQU 0x4000a07c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX6_BASE\r
+CYDEV_CAN0_TX6_BASE EQU 0x4000a080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX6_SIZE\r
+CYDEV_CAN0_TX6_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX6_CMD\r
+CYREG_CAN0_TX6_CMD EQU 0x4000a080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX6_ID\r
+CYREG_CAN0_TX6_ID EQU 0x4000a084\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX6_DH\r
+CYREG_CAN0_TX6_DH EQU 0x4000a088\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX6_DL\r
+CYREG_CAN0_TX6_DL EQU 0x4000a08c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX7_BASE\r
+CYDEV_CAN0_TX7_BASE EQU 0x4000a090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_TX7_SIZE\r
+CYDEV_CAN0_TX7_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX7_CMD\r
+CYREG_CAN0_TX7_CMD EQU 0x4000a090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX7_ID\r
+CYREG_CAN0_TX7_ID EQU 0x4000a094\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX7_DH\r
+CYREG_CAN0_TX7_DH EQU 0x4000a098\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_TX7_DL\r
+CYREG_CAN0_TX7_DL EQU 0x4000a09c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX0_BASE\r
+CYDEV_CAN0_RX0_BASE EQU 0x4000a0a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX0_SIZE\r
+CYDEV_CAN0_RX0_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX0_CMD\r
+CYREG_CAN0_RX0_CMD EQU 0x4000a0a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX0_ID\r
+CYREG_CAN0_RX0_ID EQU 0x4000a0a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX0_DH\r
+CYREG_CAN0_RX0_DH EQU 0x4000a0a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX0_DL\r
+CYREG_CAN0_RX0_DL EQU 0x4000a0ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX0_AMR\r
+CYREG_CAN0_RX0_AMR EQU 0x4000a0b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX0_ACR\r
+CYREG_CAN0_RX0_ACR EQU 0x4000a0b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX0_AMRD\r
+CYREG_CAN0_RX0_AMRD EQU 0x4000a0b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX0_ACRD\r
+CYREG_CAN0_RX0_ACRD EQU 0x4000a0bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX1_BASE\r
+CYDEV_CAN0_RX1_BASE EQU 0x4000a0c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX1_SIZE\r
+CYDEV_CAN0_RX1_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX1_CMD\r
+CYREG_CAN0_RX1_CMD EQU 0x4000a0c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX1_ID\r
+CYREG_CAN0_RX1_ID EQU 0x4000a0c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX1_DH\r
+CYREG_CAN0_RX1_DH EQU 0x4000a0c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX1_DL\r
+CYREG_CAN0_RX1_DL EQU 0x4000a0cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX1_AMR\r
+CYREG_CAN0_RX1_AMR EQU 0x4000a0d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX1_ACR\r
+CYREG_CAN0_RX1_ACR EQU 0x4000a0d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX1_AMRD\r
+CYREG_CAN0_RX1_AMRD EQU 0x4000a0d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX1_ACRD\r
+CYREG_CAN0_RX1_ACRD EQU 0x4000a0dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX2_BASE\r
+CYDEV_CAN0_RX2_BASE EQU 0x4000a0e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX2_SIZE\r
+CYDEV_CAN0_RX2_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX2_CMD\r
+CYREG_CAN0_RX2_CMD EQU 0x4000a0e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX2_ID\r
+CYREG_CAN0_RX2_ID EQU 0x4000a0e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX2_DH\r
+CYREG_CAN0_RX2_DH EQU 0x4000a0e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX2_DL\r
+CYREG_CAN0_RX2_DL EQU 0x4000a0ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX2_AMR\r
+CYREG_CAN0_RX2_AMR EQU 0x4000a0f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX2_ACR\r
+CYREG_CAN0_RX2_ACR EQU 0x4000a0f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX2_AMRD\r
+CYREG_CAN0_RX2_AMRD EQU 0x4000a0f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX2_ACRD\r
+CYREG_CAN0_RX2_ACRD EQU 0x4000a0fc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX3_BASE\r
+CYDEV_CAN0_RX3_BASE EQU 0x4000a100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX3_SIZE\r
+CYDEV_CAN0_RX3_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX3_CMD\r
+CYREG_CAN0_RX3_CMD EQU 0x4000a100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX3_ID\r
+CYREG_CAN0_RX3_ID EQU 0x4000a104\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX3_DH\r
+CYREG_CAN0_RX3_DH EQU 0x4000a108\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX3_DL\r
+CYREG_CAN0_RX3_DL EQU 0x4000a10c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX3_AMR\r
+CYREG_CAN0_RX3_AMR EQU 0x4000a110\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX3_ACR\r
+CYREG_CAN0_RX3_ACR EQU 0x4000a114\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX3_AMRD\r
+CYREG_CAN0_RX3_AMRD EQU 0x4000a118\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX3_ACRD\r
+CYREG_CAN0_RX3_ACRD EQU 0x4000a11c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX4_BASE\r
+CYDEV_CAN0_RX4_BASE EQU 0x4000a120\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX4_SIZE\r
+CYDEV_CAN0_RX4_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX4_CMD\r
+CYREG_CAN0_RX4_CMD EQU 0x4000a120\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX4_ID\r
+CYREG_CAN0_RX4_ID EQU 0x4000a124\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX4_DH\r
+CYREG_CAN0_RX4_DH EQU 0x4000a128\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX4_DL\r
+CYREG_CAN0_RX4_DL EQU 0x4000a12c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX4_AMR\r
+CYREG_CAN0_RX4_AMR EQU 0x4000a130\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX4_ACR\r
+CYREG_CAN0_RX4_ACR EQU 0x4000a134\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX4_AMRD\r
+CYREG_CAN0_RX4_AMRD EQU 0x4000a138\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX4_ACRD\r
+CYREG_CAN0_RX4_ACRD EQU 0x4000a13c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX5_BASE\r
+CYDEV_CAN0_RX5_BASE EQU 0x4000a140\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX5_SIZE\r
+CYDEV_CAN0_RX5_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX5_CMD\r
+CYREG_CAN0_RX5_CMD EQU 0x4000a140\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX5_ID\r
+CYREG_CAN0_RX5_ID EQU 0x4000a144\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX5_DH\r
+CYREG_CAN0_RX5_DH EQU 0x4000a148\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX5_DL\r
+CYREG_CAN0_RX5_DL EQU 0x4000a14c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX5_AMR\r
+CYREG_CAN0_RX5_AMR EQU 0x4000a150\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX5_ACR\r
+CYREG_CAN0_RX5_ACR EQU 0x4000a154\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX5_AMRD\r
+CYREG_CAN0_RX5_AMRD EQU 0x4000a158\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX5_ACRD\r
+CYREG_CAN0_RX5_ACRD EQU 0x4000a15c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX6_BASE\r
+CYDEV_CAN0_RX6_BASE EQU 0x4000a160\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX6_SIZE\r
+CYDEV_CAN0_RX6_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX6_CMD\r
+CYREG_CAN0_RX6_CMD EQU 0x4000a160\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX6_ID\r
+CYREG_CAN0_RX6_ID EQU 0x4000a164\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX6_DH\r
+CYREG_CAN0_RX6_DH EQU 0x4000a168\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX6_DL\r
+CYREG_CAN0_RX6_DL EQU 0x4000a16c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX6_AMR\r
+CYREG_CAN0_RX6_AMR EQU 0x4000a170\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX6_ACR\r
+CYREG_CAN0_RX6_ACR EQU 0x4000a174\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX6_AMRD\r
+CYREG_CAN0_RX6_AMRD EQU 0x4000a178\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX6_ACRD\r
+CYREG_CAN0_RX6_ACRD EQU 0x4000a17c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX7_BASE\r
+CYDEV_CAN0_RX7_BASE EQU 0x4000a180\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX7_SIZE\r
+CYDEV_CAN0_RX7_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX7_CMD\r
+CYREG_CAN0_RX7_CMD EQU 0x4000a180\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX7_ID\r
+CYREG_CAN0_RX7_ID EQU 0x4000a184\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX7_DH\r
+CYREG_CAN0_RX7_DH EQU 0x4000a188\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX7_DL\r
+CYREG_CAN0_RX7_DL EQU 0x4000a18c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX7_AMR\r
+CYREG_CAN0_RX7_AMR EQU 0x4000a190\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX7_ACR\r
+CYREG_CAN0_RX7_ACR EQU 0x4000a194\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX7_AMRD\r
+CYREG_CAN0_RX7_AMRD EQU 0x4000a198\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX7_ACRD\r
+CYREG_CAN0_RX7_ACRD EQU 0x4000a19c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX8_BASE\r
+CYDEV_CAN0_RX8_BASE EQU 0x4000a1a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX8_SIZE\r
+CYDEV_CAN0_RX8_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX8_CMD\r
+CYREG_CAN0_RX8_CMD EQU 0x4000a1a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX8_ID\r
+CYREG_CAN0_RX8_ID EQU 0x4000a1a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX8_DH\r
+CYREG_CAN0_RX8_DH EQU 0x4000a1a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX8_DL\r
+CYREG_CAN0_RX8_DL EQU 0x4000a1ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX8_AMR\r
+CYREG_CAN0_RX8_AMR EQU 0x4000a1b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX8_ACR\r
+CYREG_CAN0_RX8_ACR EQU 0x4000a1b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX8_AMRD\r
+CYREG_CAN0_RX8_AMRD EQU 0x4000a1b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX8_ACRD\r
+CYREG_CAN0_RX8_ACRD EQU 0x4000a1bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX9_BASE\r
+CYDEV_CAN0_RX9_BASE EQU 0x4000a1c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX9_SIZE\r
+CYDEV_CAN0_RX9_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX9_CMD\r
+CYREG_CAN0_RX9_CMD EQU 0x4000a1c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX9_ID\r
+CYREG_CAN0_RX9_ID EQU 0x4000a1c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX9_DH\r
+CYREG_CAN0_RX9_DH EQU 0x4000a1c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX9_DL\r
+CYREG_CAN0_RX9_DL EQU 0x4000a1cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX9_AMR\r
+CYREG_CAN0_RX9_AMR EQU 0x4000a1d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX9_ACR\r
+CYREG_CAN0_RX9_ACR EQU 0x4000a1d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX9_AMRD\r
+CYREG_CAN0_RX9_AMRD EQU 0x4000a1d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX9_ACRD\r
+CYREG_CAN0_RX9_ACRD EQU 0x4000a1dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX10_BASE\r
+CYDEV_CAN0_RX10_BASE EQU 0x4000a1e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX10_SIZE\r
+CYDEV_CAN0_RX10_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX10_CMD\r
+CYREG_CAN0_RX10_CMD EQU 0x4000a1e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX10_ID\r
+CYREG_CAN0_RX10_ID EQU 0x4000a1e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX10_DH\r
+CYREG_CAN0_RX10_DH EQU 0x4000a1e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX10_DL\r
+CYREG_CAN0_RX10_DL EQU 0x4000a1ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX10_AMR\r
+CYREG_CAN0_RX10_AMR EQU 0x4000a1f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX10_ACR\r
+CYREG_CAN0_RX10_ACR EQU 0x4000a1f4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX10_AMRD\r
+CYREG_CAN0_RX10_AMRD EQU 0x4000a1f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX10_ACRD\r
+CYREG_CAN0_RX10_ACRD EQU 0x4000a1fc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX11_BASE\r
+CYDEV_CAN0_RX11_BASE EQU 0x4000a200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX11_SIZE\r
+CYDEV_CAN0_RX11_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX11_CMD\r
+CYREG_CAN0_RX11_CMD EQU 0x4000a200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX11_ID\r
+CYREG_CAN0_RX11_ID EQU 0x4000a204\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX11_DH\r
+CYREG_CAN0_RX11_DH EQU 0x4000a208\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX11_DL\r
+CYREG_CAN0_RX11_DL EQU 0x4000a20c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX11_AMR\r
+CYREG_CAN0_RX11_AMR EQU 0x4000a210\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX11_ACR\r
+CYREG_CAN0_RX11_ACR EQU 0x4000a214\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX11_AMRD\r
+CYREG_CAN0_RX11_AMRD EQU 0x4000a218\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX11_ACRD\r
+CYREG_CAN0_RX11_ACRD EQU 0x4000a21c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX12_BASE\r
+CYDEV_CAN0_RX12_BASE EQU 0x4000a220\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX12_SIZE\r
+CYDEV_CAN0_RX12_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX12_CMD\r
+CYREG_CAN0_RX12_CMD EQU 0x4000a220\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX12_ID\r
+CYREG_CAN0_RX12_ID EQU 0x4000a224\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX12_DH\r
+CYREG_CAN0_RX12_DH EQU 0x4000a228\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX12_DL\r
+CYREG_CAN0_RX12_DL EQU 0x4000a22c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX12_AMR\r
+CYREG_CAN0_RX12_AMR EQU 0x4000a230\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX12_ACR\r
+CYREG_CAN0_RX12_ACR EQU 0x4000a234\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX12_AMRD\r
+CYREG_CAN0_RX12_AMRD EQU 0x4000a238\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX12_ACRD\r
+CYREG_CAN0_RX12_ACRD EQU 0x4000a23c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX13_BASE\r
+CYDEV_CAN0_RX13_BASE EQU 0x4000a240\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX13_SIZE\r
+CYDEV_CAN0_RX13_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX13_CMD\r
+CYREG_CAN0_RX13_CMD EQU 0x4000a240\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX13_ID\r
+CYREG_CAN0_RX13_ID EQU 0x4000a244\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX13_DH\r
+CYREG_CAN0_RX13_DH EQU 0x4000a248\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX13_DL\r
+CYREG_CAN0_RX13_DL EQU 0x4000a24c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX13_AMR\r
+CYREG_CAN0_RX13_AMR EQU 0x4000a250\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX13_ACR\r
+CYREG_CAN0_RX13_ACR EQU 0x4000a254\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX13_AMRD\r
+CYREG_CAN0_RX13_AMRD EQU 0x4000a258\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX13_ACRD\r
+CYREG_CAN0_RX13_ACRD EQU 0x4000a25c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX14_BASE\r
+CYDEV_CAN0_RX14_BASE EQU 0x4000a260\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX14_SIZE\r
+CYDEV_CAN0_RX14_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX14_CMD\r
+CYREG_CAN0_RX14_CMD EQU 0x4000a260\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX14_ID\r
+CYREG_CAN0_RX14_ID EQU 0x4000a264\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX14_DH\r
+CYREG_CAN0_RX14_DH EQU 0x4000a268\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX14_DL\r
+CYREG_CAN0_RX14_DL EQU 0x4000a26c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX14_AMR\r
+CYREG_CAN0_RX14_AMR EQU 0x4000a270\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX14_ACR\r
+CYREG_CAN0_RX14_ACR EQU 0x4000a274\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX14_AMRD\r
+CYREG_CAN0_RX14_AMRD EQU 0x4000a278\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX14_ACRD\r
+CYREG_CAN0_RX14_ACRD EQU 0x4000a27c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX15_BASE\r
+CYDEV_CAN0_RX15_BASE EQU 0x4000a280\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CAN0_RX15_SIZE\r
+CYDEV_CAN0_RX15_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX15_CMD\r
+CYREG_CAN0_RX15_CMD EQU 0x4000a280\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX15_ID\r
+CYREG_CAN0_RX15_ID EQU 0x4000a284\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX15_DH\r
+CYREG_CAN0_RX15_DH EQU 0x4000a288\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX15_DL\r
+CYREG_CAN0_RX15_DL EQU 0x4000a28c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX15_AMR\r
+CYREG_CAN0_RX15_AMR EQU 0x4000a290\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX15_ACR\r
+CYREG_CAN0_RX15_ACR EQU 0x4000a294\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX15_AMRD\r
+CYREG_CAN0_RX15_AMRD EQU 0x4000a298\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CAN0_RX15_ACRD\r
+CYREG_CAN0_RX15_ACRD EQU 0x4000a29c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_BASE\r
+CYDEV_DFB0_BASE EQU 0x4000c000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_SIZE\r
+CYDEV_DFB0_SIZE EQU 0x000007b5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_BASE\r
+CYDEV_DFB0_DPA_SRAM_BASE EQU 0x4000c000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_SIZE\r
+CYDEV_DFB0_DPA_SRAM_SIZE EQU 0x00000200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_DPA_SRAM_DATA_MBASE\r
+CYREG_DFB0_DPA_SRAM_DATA_MBASE EQU 0x4000c000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_DPA_SRAM_DATA_MSIZE\r
+CYREG_DFB0_DPA_SRAM_DATA_MSIZE EQU 0x00000200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_BASE\r
+CYDEV_DFB0_DPB_SRAM_BASE EQU 0x4000c200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_SIZE\r
+CYDEV_DFB0_DPB_SRAM_SIZE EQU 0x00000200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_DPB_SRAM_DATA_MBASE\r
+CYREG_DFB0_DPB_SRAM_DATA_MBASE EQU 0x4000c200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_DPB_SRAM_DATA_MSIZE\r
+CYREG_DFB0_DPB_SRAM_DATA_MSIZE EQU 0x00000200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_BASE\r
+CYDEV_DFB0_CSA_SRAM_BASE EQU 0x4000c400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_SIZE\r
+CYDEV_DFB0_CSA_SRAM_SIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_CSA_SRAM_DATA_MBASE\r
+CYREG_DFB0_CSA_SRAM_DATA_MBASE EQU 0x4000c400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_CSA_SRAM_DATA_MSIZE\r
+CYREG_DFB0_CSA_SRAM_DATA_MSIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_BASE\r
+CYDEV_DFB0_CSB_SRAM_BASE EQU 0x4000c500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_SIZE\r
+CYDEV_DFB0_CSB_SRAM_SIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_CSB_SRAM_DATA_MBASE\r
+CYREG_DFB0_CSB_SRAM_DATA_MBASE EQU 0x4000c500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_CSB_SRAM_DATA_MSIZE\r
+CYREG_DFB0_CSB_SRAM_DATA_MSIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_BASE\r
+CYDEV_DFB0_FSM_SRAM_BASE EQU 0x4000c600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_SIZE\r
+CYDEV_DFB0_FSM_SRAM_SIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_FSM_SRAM_DATA_MBASE\r
+CYREG_DFB0_FSM_SRAM_DATA_MBASE EQU 0x4000c600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_FSM_SRAM_DATA_MSIZE\r
+CYREG_DFB0_FSM_SRAM_DATA_MSIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_BASE\r
+CYDEV_DFB0_ACU_SRAM_BASE EQU 0x4000c700\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_SIZE\r
+CYDEV_DFB0_ACU_SRAM_SIZE EQU 0x00000040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_ACU_SRAM_DATA_MBASE\r
+CYREG_DFB0_ACU_SRAM_DATA_MBASE EQU 0x4000c700\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_ACU_SRAM_DATA_MSIZE\r
+CYREG_DFB0_ACU_SRAM_DATA_MSIZE EQU 0x00000040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_CR\r
+CYREG_DFB0_CR EQU 0x4000c780\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_SR\r
+CYREG_DFB0_SR EQU 0x4000c784\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_RAM_EN\r
+CYREG_DFB0_RAM_EN EQU 0x4000c788\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_RAM_DIR\r
+CYREG_DFB0_RAM_DIR EQU 0x4000c78c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_SEMA\r
+CYREG_DFB0_SEMA EQU 0x4000c790\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_DSI_CTRL\r
+CYREG_DFB0_DSI_CTRL EQU 0x4000c794\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_INT_CTRL\r
+CYREG_DFB0_INT_CTRL EQU 0x4000c798\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_DMA_CTRL\r
+CYREG_DFB0_DMA_CTRL EQU 0x4000c79c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_STAGEA\r
+CYREG_DFB0_STAGEA EQU 0x4000c7a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_STAGEAM\r
+CYREG_DFB0_STAGEAM EQU 0x4000c7a1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_STAGEAH\r
+CYREG_DFB0_STAGEAH EQU 0x4000c7a2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_STAGEB\r
+CYREG_DFB0_STAGEB EQU 0x4000c7a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_STAGEBM\r
+CYREG_DFB0_STAGEBM EQU 0x4000c7a5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_STAGEBH\r
+CYREG_DFB0_STAGEBH EQU 0x4000c7a6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_HOLDA\r
+CYREG_DFB0_HOLDA EQU 0x4000c7a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_HOLDAM\r
+CYREG_DFB0_HOLDAM EQU 0x4000c7a9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_HOLDAH\r
+CYREG_DFB0_HOLDAH EQU 0x4000c7aa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_HOLDAS\r
+CYREG_DFB0_HOLDAS EQU 0x4000c7ab\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_HOLDB\r
+CYREG_DFB0_HOLDB EQU 0x4000c7ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_HOLDBM\r
+CYREG_DFB0_HOLDBM EQU 0x4000c7ad\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_HOLDBH\r
+CYREG_DFB0_HOLDBH EQU 0x4000c7ae\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_HOLDBS\r
+CYREG_DFB0_HOLDBS EQU 0x4000c7af\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_COHER\r
+CYREG_DFB0_COHER EQU 0x4000c7b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DFB0_DALIGN\r
+CYREG_DFB0_DALIGN EQU 0x4000c7b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BASE\r
+CYDEV_UCFG_BASE EQU 0x40010000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_SIZE\r
+CYDEV_UCFG_SIZE EQU 0x00005040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_BASE\r
+CYDEV_UCFG_B0_BASE EQU 0x40010000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_SIZE\r
+CYDEV_UCFG_B0_SIZE EQU 0x00000fef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_BASE\r
+CYDEV_UCFG_B0_P0_BASE EQU 0x40010000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_SIZE\r
+CYDEV_UCFG_B0_P0_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_BASE\r
+CYDEV_UCFG_B0_P0_U0_BASE EQU 0x40010000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_SIZE\r
+CYDEV_UCFG_B0_P0_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT0\r
+CYREG_B0_P0_U0_PLD_IT0 EQU 0x40010000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT1\r
+CYREG_B0_P0_U0_PLD_IT1 EQU 0x40010004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT2\r
+CYREG_B0_P0_U0_PLD_IT2 EQU 0x40010008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT3\r
+CYREG_B0_P0_U0_PLD_IT3 EQU 0x4001000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT4\r
+CYREG_B0_P0_U0_PLD_IT4 EQU 0x40010010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT5\r
+CYREG_B0_P0_U0_PLD_IT5 EQU 0x40010014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT6\r
+CYREG_B0_P0_U0_PLD_IT6 EQU 0x40010018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT7\r
+CYREG_B0_P0_U0_PLD_IT7 EQU 0x4001001c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT8\r
+CYREG_B0_P0_U0_PLD_IT8 EQU 0x40010020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT9\r
+CYREG_B0_P0_U0_PLD_IT9 EQU 0x40010024\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT10\r
+CYREG_B0_P0_U0_PLD_IT10 EQU 0x40010028\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT11\r
+CYREG_B0_P0_U0_PLD_IT11 EQU 0x4001002c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT0\r
+CYREG_B0_P0_U0_PLD_ORT0 EQU 0x40010030\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT1\r
+CYREG_B0_P0_U0_PLD_ORT1 EQU 0x40010032\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT2\r
+CYREG_B0_P0_U0_PLD_ORT2 EQU 0x40010034\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT3\r
+CYREG_B0_P0_U0_PLD_ORT3 EQU 0x40010036\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_CEN_CONST\r
+CYREG_B0_P0_U0_MC_CFG_CEN_CONST EQU 0x40010038\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_XORFB\r
+CYREG_B0_P0_U0_MC_CFG_XORFB EQU 0x4001003a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_SET_RESET\r
+CYREG_B0_P0_U0_MC_CFG_SET_RESET EQU 0x4001003c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_BYPASS\r
+CYREG_B0_P0_U0_MC_CFG_BYPASS EQU 0x4001003e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG0\r
+CYREG_B0_P0_U0_CFG0 EQU 0x40010040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG1\r
+CYREG_B0_P0_U0_CFG1 EQU 0x40010041\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG2\r
+CYREG_B0_P0_U0_CFG2 EQU 0x40010042\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG3\r
+CYREG_B0_P0_U0_CFG3 EQU 0x40010043\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG4\r
+CYREG_B0_P0_U0_CFG4 EQU 0x40010044\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG5\r
+CYREG_B0_P0_U0_CFG5 EQU 0x40010045\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG6\r
+CYREG_B0_P0_U0_CFG6 EQU 0x40010046\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG7\r
+CYREG_B0_P0_U0_CFG7 EQU 0x40010047\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG8\r
+CYREG_B0_P0_U0_CFG8 EQU 0x40010048\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG9\r
+CYREG_B0_P0_U0_CFG9 EQU 0x40010049\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG10\r
+CYREG_B0_P0_U0_CFG10 EQU 0x4001004a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG11\r
+CYREG_B0_P0_U0_CFG11 EQU 0x4001004b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG12\r
+CYREG_B0_P0_U0_CFG12 EQU 0x4001004c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG13\r
+CYREG_B0_P0_U0_CFG13 EQU 0x4001004d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG14\r
+CYREG_B0_P0_U0_CFG14 EQU 0x4001004e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG15\r
+CYREG_B0_P0_U0_CFG15 EQU 0x4001004f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG16\r
+CYREG_B0_P0_U0_CFG16 EQU 0x40010050\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG17\r
+CYREG_B0_P0_U0_CFG17 EQU 0x40010051\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG18\r
+CYREG_B0_P0_U0_CFG18 EQU 0x40010052\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG19\r
+CYREG_B0_P0_U0_CFG19 EQU 0x40010053\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG20\r
+CYREG_B0_P0_U0_CFG20 EQU 0x40010054\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG21\r
+CYREG_B0_P0_U0_CFG21 EQU 0x40010055\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG22\r
+CYREG_B0_P0_U0_CFG22 EQU 0x40010056\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG23\r
+CYREG_B0_P0_U0_CFG23 EQU 0x40010057\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG24\r
+CYREG_B0_P0_U0_CFG24 EQU 0x40010058\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG25\r
+CYREG_B0_P0_U0_CFG25 EQU 0x40010059\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG26\r
+CYREG_B0_P0_U0_CFG26 EQU 0x4001005a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG27\r
+CYREG_B0_P0_U0_CFG27 EQU 0x4001005b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG28\r
+CYREG_B0_P0_U0_CFG28 EQU 0x4001005c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG29\r
+CYREG_B0_P0_U0_CFG29 EQU 0x4001005d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG30\r
+CYREG_B0_P0_U0_CFG30 EQU 0x4001005e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_CFG31\r
+CYREG_B0_P0_U0_CFG31 EQU 0x4001005f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG0\r
+CYREG_B0_P0_U0_DCFG0 EQU 0x40010060\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG1\r
+CYREG_B0_P0_U0_DCFG1 EQU 0x40010062\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG2\r
+CYREG_B0_P0_U0_DCFG2 EQU 0x40010064\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG3\r
+CYREG_B0_P0_U0_DCFG3 EQU 0x40010066\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG4\r
+CYREG_B0_P0_U0_DCFG4 EQU 0x40010068\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG5\r
+CYREG_B0_P0_U0_DCFG5 EQU 0x4001006a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG6\r
+CYREG_B0_P0_U0_DCFG6 EQU 0x4001006c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG7\r
+CYREG_B0_P0_U0_DCFG7 EQU 0x4001006e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_BASE\r
+CYDEV_UCFG_B0_P0_U1_BASE EQU 0x40010080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_SIZE\r
+CYDEV_UCFG_B0_P0_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT0\r
+CYREG_B0_P0_U1_PLD_IT0 EQU 0x40010080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT1\r
+CYREG_B0_P0_U1_PLD_IT1 EQU 0x40010084\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT2\r
+CYREG_B0_P0_U1_PLD_IT2 EQU 0x40010088\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT3\r
+CYREG_B0_P0_U1_PLD_IT3 EQU 0x4001008c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT4\r
+CYREG_B0_P0_U1_PLD_IT4 EQU 0x40010090\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT5\r
+CYREG_B0_P0_U1_PLD_IT5 EQU 0x40010094\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT6\r
+CYREG_B0_P0_U1_PLD_IT6 EQU 0x40010098\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT7\r
+CYREG_B0_P0_U1_PLD_IT7 EQU 0x4001009c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT8\r
+CYREG_B0_P0_U1_PLD_IT8 EQU 0x400100a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT9\r
+CYREG_B0_P0_U1_PLD_IT9 EQU 0x400100a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT10\r
+CYREG_B0_P0_U1_PLD_IT10 EQU 0x400100a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT11\r
+CYREG_B0_P0_U1_PLD_IT11 EQU 0x400100ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT0\r
+CYREG_B0_P0_U1_PLD_ORT0 EQU 0x400100b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT1\r
+CYREG_B0_P0_U1_PLD_ORT1 EQU 0x400100b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT2\r
+CYREG_B0_P0_U1_PLD_ORT2 EQU 0x400100b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT3\r
+CYREG_B0_P0_U1_PLD_ORT3 EQU 0x400100b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_CEN_CONST\r
+CYREG_B0_P0_U1_MC_CFG_CEN_CONST EQU 0x400100b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_XORFB\r
+CYREG_B0_P0_U1_MC_CFG_XORFB EQU 0x400100ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_SET_RESET\r
+CYREG_B0_P0_U1_MC_CFG_SET_RESET EQU 0x400100bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_BYPASS\r
+CYREG_B0_P0_U1_MC_CFG_BYPASS EQU 0x400100be\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG0\r
+CYREG_B0_P0_U1_CFG0 EQU 0x400100c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG1\r
+CYREG_B0_P0_U1_CFG1 EQU 0x400100c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG2\r
+CYREG_B0_P0_U1_CFG2 EQU 0x400100c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG3\r
+CYREG_B0_P0_U1_CFG3 EQU 0x400100c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG4\r
+CYREG_B0_P0_U1_CFG4 EQU 0x400100c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG5\r
+CYREG_B0_P0_U1_CFG5 EQU 0x400100c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG6\r
+CYREG_B0_P0_U1_CFG6 EQU 0x400100c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG7\r
+CYREG_B0_P0_U1_CFG7 EQU 0x400100c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG8\r
+CYREG_B0_P0_U1_CFG8 EQU 0x400100c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG9\r
+CYREG_B0_P0_U1_CFG9 EQU 0x400100c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG10\r
+CYREG_B0_P0_U1_CFG10 EQU 0x400100ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG11\r
+CYREG_B0_P0_U1_CFG11 EQU 0x400100cb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG12\r
+CYREG_B0_P0_U1_CFG12 EQU 0x400100cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG13\r
+CYREG_B0_P0_U1_CFG13 EQU 0x400100cd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG14\r
+CYREG_B0_P0_U1_CFG14 EQU 0x400100ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG15\r
+CYREG_B0_P0_U1_CFG15 EQU 0x400100cf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG16\r
+CYREG_B0_P0_U1_CFG16 EQU 0x400100d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG17\r
+CYREG_B0_P0_U1_CFG17 EQU 0x400100d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG18\r
+CYREG_B0_P0_U1_CFG18 EQU 0x400100d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG19\r
+CYREG_B0_P0_U1_CFG19 EQU 0x400100d3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG20\r
+CYREG_B0_P0_U1_CFG20 EQU 0x400100d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG21\r
+CYREG_B0_P0_U1_CFG21 EQU 0x400100d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG22\r
+CYREG_B0_P0_U1_CFG22 EQU 0x400100d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG23\r
+CYREG_B0_P0_U1_CFG23 EQU 0x400100d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG24\r
+CYREG_B0_P0_U1_CFG24 EQU 0x400100d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG25\r
+CYREG_B0_P0_U1_CFG25 EQU 0x400100d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG26\r
+CYREG_B0_P0_U1_CFG26 EQU 0x400100da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG27\r
+CYREG_B0_P0_U1_CFG27 EQU 0x400100db\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG28\r
+CYREG_B0_P0_U1_CFG28 EQU 0x400100dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG29\r
+CYREG_B0_P0_U1_CFG29 EQU 0x400100dd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG30\r
+CYREG_B0_P0_U1_CFG30 EQU 0x400100de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_CFG31\r
+CYREG_B0_P0_U1_CFG31 EQU 0x400100df\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG0\r
+CYREG_B0_P0_U1_DCFG0 EQU 0x400100e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG1\r
+CYREG_B0_P0_U1_DCFG1 EQU 0x400100e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG2\r
+CYREG_B0_P0_U1_DCFG2 EQU 0x400100e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG3\r
+CYREG_B0_P0_U1_DCFG3 EQU 0x400100e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG4\r
+CYREG_B0_P0_U1_DCFG4 EQU 0x400100e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG5\r
+CYREG_B0_P0_U1_DCFG5 EQU 0x400100ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG6\r
+CYREG_B0_P0_U1_DCFG6 EQU 0x400100ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG7\r
+CYREG_B0_P0_U1_DCFG7 EQU 0x400100ee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_BASE\r
+CYDEV_UCFG_B0_P0_ROUTE_BASE EQU 0x40010100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_SIZE\r
+CYDEV_UCFG_B0_P0_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_BASE\r
+CYDEV_UCFG_B0_P1_BASE EQU 0x40010200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_SIZE\r
+CYDEV_UCFG_B0_P1_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_BASE\r
+CYDEV_UCFG_B0_P1_U0_BASE EQU 0x40010200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_SIZE\r
+CYDEV_UCFG_B0_P1_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT0\r
+CYREG_B0_P1_U0_PLD_IT0 EQU 0x40010200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT1\r
+CYREG_B0_P1_U0_PLD_IT1 EQU 0x40010204\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT2\r
+CYREG_B0_P1_U0_PLD_IT2 EQU 0x40010208\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT3\r
+CYREG_B0_P1_U0_PLD_IT3 EQU 0x4001020c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT4\r
+CYREG_B0_P1_U0_PLD_IT4 EQU 0x40010210\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT5\r
+CYREG_B0_P1_U0_PLD_IT5 EQU 0x40010214\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT6\r
+CYREG_B0_P1_U0_PLD_IT6 EQU 0x40010218\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT7\r
+CYREG_B0_P1_U0_PLD_IT7 EQU 0x4001021c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT8\r
+CYREG_B0_P1_U0_PLD_IT8 EQU 0x40010220\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT9\r
+CYREG_B0_P1_U0_PLD_IT9 EQU 0x40010224\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT10\r
+CYREG_B0_P1_U0_PLD_IT10 EQU 0x40010228\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT11\r
+CYREG_B0_P1_U0_PLD_IT11 EQU 0x4001022c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT0\r
+CYREG_B0_P1_U0_PLD_ORT0 EQU 0x40010230\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT1\r
+CYREG_B0_P1_U0_PLD_ORT1 EQU 0x40010232\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT2\r
+CYREG_B0_P1_U0_PLD_ORT2 EQU 0x40010234\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT3\r
+CYREG_B0_P1_U0_PLD_ORT3 EQU 0x40010236\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_CEN_CONST\r
+CYREG_B0_P1_U0_MC_CFG_CEN_CONST EQU 0x40010238\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_XORFB\r
+CYREG_B0_P1_U0_MC_CFG_XORFB EQU 0x4001023a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_SET_RESET\r
+CYREG_B0_P1_U0_MC_CFG_SET_RESET EQU 0x4001023c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_BYPASS\r
+CYREG_B0_P1_U0_MC_CFG_BYPASS EQU 0x4001023e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG0\r
+CYREG_B0_P1_U0_CFG0 EQU 0x40010240\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG1\r
+CYREG_B0_P1_U0_CFG1 EQU 0x40010241\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG2\r
+CYREG_B0_P1_U0_CFG2 EQU 0x40010242\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG3\r
+CYREG_B0_P1_U0_CFG3 EQU 0x40010243\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG4\r
+CYREG_B0_P1_U0_CFG4 EQU 0x40010244\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG5\r
+CYREG_B0_P1_U0_CFG5 EQU 0x40010245\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG6\r
+CYREG_B0_P1_U0_CFG6 EQU 0x40010246\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG7\r
+CYREG_B0_P1_U0_CFG7 EQU 0x40010247\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG8\r
+CYREG_B0_P1_U0_CFG8 EQU 0x40010248\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG9\r
+CYREG_B0_P1_U0_CFG9 EQU 0x40010249\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG10\r
+CYREG_B0_P1_U0_CFG10 EQU 0x4001024a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG11\r
+CYREG_B0_P1_U0_CFG11 EQU 0x4001024b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG12\r
+CYREG_B0_P1_U0_CFG12 EQU 0x4001024c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG13\r
+CYREG_B0_P1_U0_CFG13 EQU 0x4001024d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG14\r
+CYREG_B0_P1_U0_CFG14 EQU 0x4001024e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG15\r
+CYREG_B0_P1_U0_CFG15 EQU 0x4001024f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG16\r
+CYREG_B0_P1_U0_CFG16 EQU 0x40010250\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG17\r
+CYREG_B0_P1_U0_CFG17 EQU 0x40010251\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG18\r
+CYREG_B0_P1_U0_CFG18 EQU 0x40010252\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG19\r
+CYREG_B0_P1_U0_CFG19 EQU 0x40010253\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG20\r
+CYREG_B0_P1_U0_CFG20 EQU 0x40010254\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG21\r
+CYREG_B0_P1_U0_CFG21 EQU 0x40010255\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG22\r
+CYREG_B0_P1_U0_CFG22 EQU 0x40010256\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG23\r
+CYREG_B0_P1_U0_CFG23 EQU 0x40010257\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG24\r
+CYREG_B0_P1_U0_CFG24 EQU 0x40010258\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG25\r
+CYREG_B0_P1_U0_CFG25 EQU 0x40010259\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG26\r
+CYREG_B0_P1_U0_CFG26 EQU 0x4001025a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG27\r
+CYREG_B0_P1_U0_CFG27 EQU 0x4001025b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG28\r
+CYREG_B0_P1_U0_CFG28 EQU 0x4001025c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG29\r
+CYREG_B0_P1_U0_CFG29 EQU 0x4001025d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG30\r
+CYREG_B0_P1_U0_CFG30 EQU 0x4001025e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_CFG31\r
+CYREG_B0_P1_U0_CFG31 EQU 0x4001025f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG0\r
+CYREG_B0_P1_U0_DCFG0 EQU 0x40010260\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG1\r
+CYREG_B0_P1_U0_DCFG1 EQU 0x40010262\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG2\r
+CYREG_B0_P1_U0_DCFG2 EQU 0x40010264\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG3\r
+CYREG_B0_P1_U0_DCFG3 EQU 0x40010266\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG4\r
+CYREG_B0_P1_U0_DCFG4 EQU 0x40010268\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG5\r
+CYREG_B0_P1_U0_DCFG5 EQU 0x4001026a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG6\r
+CYREG_B0_P1_U0_DCFG6 EQU 0x4001026c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG7\r
+CYREG_B0_P1_U0_DCFG7 EQU 0x4001026e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_BASE\r
+CYDEV_UCFG_B0_P1_U1_BASE EQU 0x40010280\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_SIZE\r
+CYDEV_UCFG_B0_P1_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT0\r
+CYREG_B0_P1_U1_PLD_IT0 EQU 0x40010280\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT1\r
+CYREG_B0_P1_U1_PLD_IT1 EQU 0x40010284\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT2\r
+CYREG_B0_P1_U1_PLD_IT2 EQU 0x40010288\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT3\r
+CYREG_B0_P1_U1_PLD_IT3 EQU 0x4001028c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT4\r
+CYREG_B0_P1_U1_PLD_IT4 EQU 0x40010290\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT5\r
+CYREG_B0_P1_U1_PLD_IT5 EQU 0x40010294\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT6\r
+CYREG_B0_P1_U1_PLD_IT6 EQU 0x40010298\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT7\r
+CYREG_B0_P1_U1_PLD_IT7 EQU 0x4001029c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT8\r
+CYREG_B0_P1_U1_PLD_IT8 EQU 0x400102a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT9\r
+CYREG_B0_P1_U1_PLD_IT9 EQU 0x400102a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT10\r
+CYREG_B0_P1_U1_PLD_IT10 EQU 0x400102a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT11\r
+CYREG_B0_P1_U1_PLD_IT11 EQU 0x400102ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT0\r
+CYREG_B0_P1_U1_PLD_ORT0 EQU 0x400102b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT1\r
+CYREG_B0_P1_U1_PLD_ORT1 EQU 0x400102b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT2\r
+CYREG_B0_P1_U1_PLD_ORT2 EQU 0x400102b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT3\r
+CYREG_B0_P1_U1_PLD_ORT3 EQU 0x400102b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_CEN_CONST\r
+CYREG_B0_P1_U1_MC_CFG_CEN_CONST EQU 0x400102b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_XORFB\r
+CYREG_B0_P1_U1_MC_CFG_XORFB EQU 0x400102ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_SET_RESET\r
+CYREG_B0_P1_U1_MC_CFG_SET_RESET EQU 0x400102bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_BYPASS\r
+CYREG_B0_P1_U1_MC_CFG_BYPASS EQU 0x400102be\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG0\r
+CYREG_B0_P1_U1_CFG0 EQU 0x400102c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG1\r
+CYREG_B0_P1_U1_CFG1 EQU 0x400102c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG2\r
+CYREG_B0_P1_U1_CFG2 EQU 0x400102c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG3\r
+CYREG_B0_P1_U1_CFG3 EQU 0x400102c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG4\r
+CYREG_B0_P1_U1_CFG4 EQU 0x400102c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG5\r
+CYREG_B0_P1_U1_CFG5 EQU 0x400102c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG6\r
+CYREG_B0_P1_U1_CFG6 EQU 0x400102c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG7\r
+CYREG_B0_P1_U1_CFG7 EQU 0x400102c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG8\r
+CYREG_B0_P1_U1_CFG8 EQU 0x400102c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG9\r
+CYREG_B0_P1_U1_CFG9 EQU 0x400102c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG10\r
+CYREG_B0_P1_U1_CFG10 EQU 0x400102ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG11\r
+CYREG_B0_P1_U1_CFG11 EQU 0x400102cb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG12\r
+CYREG_B0_P1_U1_CFG12 EQU 0x400102cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG13\r
+CYREG_B0_P1_U1_CFG13 EQU 0x400102cd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG14\r
+CYREG_B0_P1_U1_CFG14 EQU 0x400102ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG15\r
+CYREG_B0_P1_U1_CFG15 EQU 0x400102cf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG16\r
+CYREG_B0_P1_U1_CFG16 EQU 0x400102d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG17\r
+CYREG_B0_P1_U1_CFG17 EQU 0x400102d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG18\r
+CYREG_B0_P1_U1_CFG18 EQU 0x400102d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG19\r
+CYREG_B0_P1_U1_CFG19 EQU 0x400102d3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG20\r
+CYREG_B0_P1_U1_CFG20 EQU 0x400102d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG21\r
+CYREG_B0_P1_U1_CFG21 EQU 0x400102d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG22\r
+CYREG_B0_P1_U1_CFG22 EQU 0x400102d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG23\r
+CYREG_B0_P1_U1_CFG23 EQU 0x400102d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG24\r
+CYREG_B0_P1_U1_CFG24 EQU 0x400102d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG25\r
+CYREG_B0_P1_U1_CFG25 EQU 0x400102d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG26\r
+CYREG_B0_P1_U1_CFG26 EQU 0x400102da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG27\r
+CYREG_B0_P1_U1_CFG27 EQU 0x400102db\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG28\r
+CYREG_B0_P1_U1_CFG28 EQU 0x400102dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG29\r
+CYREG_B0_P1_U1_CFG29 EQU 0x400102dd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG30\r
+CYREG_B0_P1_U1_CFG30 EQU 0x400102de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_CFG31\r
+CYREG_B0_P1_U1_CFG31 EQU 0x400102df\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG0\r
+CYREG_B0_P1_U1_DCFG0 EQU 0x400102e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG1\r
+CYREG_B0_P1_U1_DCFG1 EQU 0x400102e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG2\r
+CYREG_B0_P1_U1_DCFG2 EQU 0x400102e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG3\r
+CYREG_B0_P1_U1_DCFG3 EQU 0x400102e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG4\r
+CYREG_B0_P1_U1_DCFG4 EQU 0x400102e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG5\r
+CYREG_B0_P1_U1_DCFG5 EQU 0x400102ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG6\r
+CYREG_B0_P1_U1_DCFG6 EQU 0x400102ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG7\r
+CYREG_B0_P1_U1_DCFG7 EQU 0x400102ee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_BASE\r
+CYDEV_UCFG_B0_P1_ROUTE_BASE EQU 0x40010300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_SIZE\r
+CYDEV_UCFG_B0_P1_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_BASE\r
+CYDEV_UCFG_B0_P2_BASE EQU 0x40010400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_SIZE\r
+CYDEV_UCFG_B0_P2_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_BASE\r
+CYDEV_UCFG_B0_P2_U0_BASE EQU 0x40010400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_SIZE\r
+CYDEV_UCFG_B0_P2_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT0\r
+CYREG_B0_P2_U0_PLD_IT0 EQU 0x40010400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT1\r
+CYREG_B0_P2_U0_PLD_IT1 EQU 0x40010404\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT2\r
+CYREG_B0_P2_U0_PLD_IT2 EQU 0x40010408\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT3\r
+CYREG_B0_P2_U0_PLD_IT3 EQU 0x4001040c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT4\r
+CYREG_B0_P2_U0_PLD_IT4 EQU 0x40010410\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT5\r
+CYREG_B0_P2_U0_PLD_IT5 EQU 0x40010414\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT6\r
+CYREG_B0_P2_U0_PLD_IT6 EQU 0x40010418\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT7\r
+CYREG_B0_P2_U0_PLD_IT7 EQU 0x4001041c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT8\r
+CYREG_B0_P2_U0_PLD_IT8 EQU 0x40010420\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT9\r
+CYREG_B0_P2_U0_PLD_IT9 EQU 0x40010424\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT10\r
+CYREG_B0_P2_U0_PLD_IT10 EQU 0x40010428\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT11\r
+CYREG_B0_P2_U0_PLD_IT11 EQU 0x4001042c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT0\r
+CYREG_B0_P2_U0_PLD_ORT0 EQU 0x40010430\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT1\r
+CYREG_B0_P2_U0_PLD_ORT1 EQU 0x40010432\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT2\r
+CYREG_B0_P2_U0_PLD_ORT2 EQU 0x40010434\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT3\r
+CYREG_B0_P2_U0_PLD_ORT3 EQU 0x40010436\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_CEN_CONST\r
+CYREG_B0_P2_U0_MC_CFG_CEN_CONST EQU 0x40010438\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_XORFB\r
+CYREG_B0_P2_U0_MC_CFG_XORFB EQU 0x4001043a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_SET_RESET\r
+CYREG_B0_P2_U0_MC_CFG_SET_RESET EQU 0x4001043c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_BYPASS\r
+CYREG_B0_P2_U0_MC_CFG_BYPASS EQU 0x4001043e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG0\r
+CYREG_B0_P2_U0_CFG0 EQU 0x40010440\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG1\r
+CYREG_B0_P2_U0_CFG1 EQU 0x40010441\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG2\r
+CYREG_B0_P2_U0_CFG2 EQU 0x40010442\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG3\r
+CYREG_B0_P2_U0_CFG3 EQU 0x40010443\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG4\r
+CYREG_B0_P2_U0_CFG4 EQU 0x40010444\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG5\r
+CYREG_B0_P2_U0_CFG5 EQU 0x40010445\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG6\r
+CYREG_B0_P2_U0_CFG6 EQU 0x40010446\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG7\r
+CYREG_B0_P2_U0_CFG7 EQU 0x40010447\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG8\r
+CYREG_B0_P2_U0_CFG8 EQU 0x40010448\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG9\r
+CYREG_B0_P2_U0_CFG9 EQU 0x40010449\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG10\r
+CYREG_B0_P2_U0_CFG10 EQU 0x4001044a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG11\r
+CYREG_B0_P2_U0_CFG11 EQU 0x4001044b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG12\r
+CYREG_B0_P2_U0_CFG12 EQU 0x4001044c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG13\r
+CYREG_B0_P2_U0_CFG13 EQU 0x4001044d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG14\r
+CYREG_B0_P2_U0_CFG14 EQU 0x4001044e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG15\r
+CYREG_B0_P2_U0_CFG15 EQU 0x4001044f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG16\r
+CYREG_B0_P2_U0_CFG16 EQU 0x40010450\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG17\r
+CYREG_B0_P2_U0_CFG17 EQU 0x40010451\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG18\r
+CYREG_B0_P2_U0_CFG18 EQU 0x40010452\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG19\r
+CYREG_B0_P2_U0_CFG19 EQU 0x40010453\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG20\r
+CYREG_B0_P2_U0_CFG20 EQU 0x40010454\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG21\r
+CYREG_B0_P2_U0_CFG21 EQU 0x40010455\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG22\r
+CYREG_B0_P2_U0_CFG22 EQU 0x40010456\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG23\r
+CYREG_B0_P2_U0_CFG23 EQU 0x40010457\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG24\r
+CYREG_B0_P2_U0_CFG24 EQU 0x40010458\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG25\r
+CYREG_B0_P2_U0_CFG25 EQU 0x40010459\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG26\r
+CYREG_B0_P2_U0_CFG26 EQU 0x4001045a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG27\r
+CYREG_B0_P2_U0_CFG27 EQU 0x4001045b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG28\r
+CYREG_B0_P2_U0_CFG28 EQU 0x4001045c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG29\r
+CYREG_B0_P2_U0_CFG29 EQU 0x4001045d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG30\r
+CYREG_B0_P2_U0_CFG30 EQU 0x4001045e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_CFG31\r
+CYREG_B0_P2_U0_CFG31 EQU 0x4001045f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG0\r
+CYREG_B0_P2_U0_DCFG0 EQU 0x40010460\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG1\r
+CYREG_B0_P2_U0_DCFG1 EQU 0x40010462\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG2\r
+CYREG_B0_P2_U0_DCFG2 EQU 0x40010464\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG3\r
+CYREG_B0_P2_U0_DCFG3 EQU 0x40010466\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG4\r
+CYREG_B0_P2_U0_DCFG4 EQU 0x40010468\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG5\r
+CYREG_B0_P2_U0_DCFG5 EQU 0x4001046a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG6\r
+CYREG_B0_P2_U0_DCFG6 EQU 0x4001046c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG7\r
+CYREG_B0_P2_U0_DCFG7 EQU 0x4001046e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_BASE\r
+CYDEV_UCFG_B0_P2_U1_BASE EQU 0x40010480\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_SIZE\r
+CYDEV_UCFG_B0_P2_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT0\r
+CYREG_B0_P2_U1_PLD_IT0 EQU 0x40010480\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT1\r
+CYREG_B0_P2_U1_PLD_IT1 EQU 0x40010484\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT2\r
+CYREG_B0_P2_U1_PLD_IT2 EQU 0x40010488\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT3\r
+CYREG_B0_P2_U1_PLD_IT3 EQU 0x4001048c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT4\r
+CYREG_B0_P2_U1_PLD_IT4 EQU 0x40010490\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT5\r
+CYREG_B0_P2_U1_PLD_IT5 EQU 0x40010494\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT6\r
+CYREG_B0_P2_U1_PLD_IT6 EQU 0x40010498\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT7\r
+CYREG_B0_P2_U1_PLD_IT7 EQU 0x4001049c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT8\r
+CYREG_B0_P2_U1_PLD_IT8 EQU 0x400104a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT9\r
+CYREG_B0_P2_U1_PLD_IT9 EQU 0x400104a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT10\r
+CYREG_B0_P2_U1_PLD_IT10 EQU 0x400104a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT11\r
+CYREG_B0_P2_U1_PLD_IT11 EQU 0x400104ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT0\r
+CYREG_B0_P2_U1_PLD_ORT0 EQU 0x400104b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT1\r
+CYREG_B0_P2_U1_PLD_ORT1 EQU 0x400104b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT2\r
+CYREG_B0_P2_U1_PLD_ORT2 EQU 0x400104b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT3\r
+CYREG_B0_P2_U1_PLD_ORT3 EQU 0x400104b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_CEN_CONST\r
+CYREG_B0_P2_U1_MC_CFG_CEN_CONST EQU 0x400104b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_XORFB\r
+CYREG_B0_P2_U1_MC_CFG_XORFB EQU 0x400104ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_SET_RESET\r
+CYREG_B0_P2_U1_MC_CFG_SET_RESET EQU 0x400104bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_BYPASS\r
+CYREG_B0_P2_U1_MC_CFG_BYPASS EQU 0x400104be\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG0\r
+CYREG_B0_P2_U1_CFG0 EQU 0x400104c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG1\r
+CYREG_B0_P2_U1_CFG1 EQU 0x400104c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG2\r
+CYREG_B0_P2_U1_CFG2 EQU 0x400104c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG3\r
+CYREG_B0_P2_U1_CFG3 EQU 0x400104c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG4\r
+CYREG_B0_P2_U1_CFG4 EQU 0x400104c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG5\r
+CYREG_B0_P2_U1_CFG5 EQU 0x400104c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG6\r
+CYREG_B0_P2_U1_CFG6 EQU 0x400104c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG7\r
+CYREG_B0_P2_U1_CFG7 EQU 0x400104c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG8\r
+CYREG_B0_P2_U1_CFG8 EQU 0x400104c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG9\r
+CYREG_B0_P2_U1_CFG9 EQU 0x400104c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG10\r
+CYREG_B0_P2_U1_CFG10 EQU 0x400104ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG11\r
+CYREG_B0_P2_U1_CFG11 EQU 0x400104cb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG12\r
+CYREG_B0_P2_U1_CFG12 EQU 0x400104cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG13\r
+CYREG_B0_P2_U1_CFG13 EQU 0x400104cd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG14\r
+CYREG_B0_P2_U1_CFG14 EQU 0x400104ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG15\r
+CYREG_B0_P2_U1_CFG15 EQU 0x400104cf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG16\r
+CYREG_B0_P2_U1_CFG16 EQU 0x400104d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG17\r
+CYREG_B0_P2_U1_CFG17 EQU 0x400104d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG18\r
+CYREG_B0_P2_U1_CFG18 EQU 0x400104d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG19\r
+CYREG_B0_P2_U1_CFG19 EQU 0x400104d3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG20\r
+CYREG_B0_P2_U1_CFG20 EQU 0x400104d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG21\r
+CYREG_B0_P2_U1_CFG21 EQU 0x400104d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG22\r
+CYREG_B0_P2_U1_CFG22 EQU 0x400104d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG23\r
+CYREG_B0_P2_U1_CFG23 EQU 0x400104d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG24\r
+CYREG_B0_P2_U1_CFG24 EQU 0x400104d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG25\r
+CYREG_B0_P2_U1_CFG25 EQU 0x400104d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG26\r
+CYREG_B0_P2_U1_CFG26 EQU 0x400104da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG27\r
+CYREG_B0_P2_U1_CFG27 EQU 0x400104db\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG28\r
+CYREG_B0_P2_U1_CFG28 EQU 0x400104dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG29\r
+CYREG_B0_P2_U1_CFG29 EQU 0x400104dd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG30\r
+CYREG_B0_P2_U1_CFG30 EQU 0x400104de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_CFG31\r
+CYREG_B0_P2_U1_CFG31 EQU 0x400104df\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG0\r
+CYREG_B0_P2_U1_DCFG0 EQU 0x400104e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG1\r
+CYREG_B0_P2_U1_DCFG1 EQU 0x400104e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG2\r
+CYREG_B0_P2_U1_DCFG2 EQU 0x400104e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG3\r
+CYREG_B0_P2_U1_DCFG3 EQU 0x400104e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG4\r
+CYREG_B0_P2_U1_DCFG4 EQU 0x400104e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG5\r
+CYREG_B0_P2_U1_DCFG5 EQU 0x400104ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG6\r
+CYREG_B0_P2_U1_DCFG6 EQU 0x400104ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG7\r
+CYREG_B0_P2_U1_DCFG7 EQU 0x400104ee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_BASE\r
+CYDEV_UCFG_B0_P2_ROUTE_BASE EQU 0x40010500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_SIZE\r
+CYDEV_UCFG_B0_P2_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_BASE\r
+CYDEV_UCFG_B0_P3_BASE EQU 0x40010600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_SIZE\r
+CYDEV_UCFG_B0_P3_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_BASE\r
+CYDEV_UCFG_B0_P3_U0_BASE EQU 0x40010600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_SIZE\r
+CYDEV_UCFG_B0_P3_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT0\r
+CYREG_B0_P3_U0_PLD_IT0 EQU 0x40010600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT1\r
+CYREG_B0_P3_U0_PLD_IT1 EQU 0x40010604\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT2\r
+CYREG_B0_P3_U0_PLD_IT2 EQU 0x40010608\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT3\r
+CYREG_B0_P3_U0_PLD_IT3 EQU 0x4001060c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT4\r
+CYREG_B0_P3_U0_PLD_IT4 EQU 0x40010610\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT5\r
+CYREG_B0_P3_U0_PLD_IT5 EQU 0x40010614\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT6\r
+CYREG_B0_P3_U0_PLD_IT6 EQU 0x40010618\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT7\r
+CYREG_B0_P3_U0_PLD_IT7 EQU 0x4001061c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT8\r
+CYREG_B0_P3_U0_PLD_IT8 EQU 0x40010620\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT9\r
+CYREG_B0_P3_U0_PLD_IT9 EQU 0x40010624\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT10\r
+CYREG_B0_P3_U0_PLD_IT10 EQU 0x40010628\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT11\r
+CYREG_B0_P3_U0_PLD_IT11 EQU 0x4001062c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT0\r
+CYREG_B0_P3_U0_PLD_ORT0 EQU 0x40010630\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT1\r
+CYREG_B0_P3_U0_PLD_ORT1 EQU 0x40010632\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT2\r
+CYREG_B0_P3_U0_PLD_ORT2 EQU 0x40010634\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT3\r
+CYREG_B0_P3_U0_PLD_ORT3 EQU 0x40010636\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_CEN_CONST\r
+CYREG_B0_P3_U0_MC_CFG_CEN_CONST EQU 0x40010638\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_XORFB\r
+CYREG_B0_P3_U0_MC_CFG_XORFB EQU 0x4001063a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_SET_RESET\r
+CYREG_B0_P3_U0_MC_CFG_SET_RESET EQU 0x4001063c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_BYPASS\r
+CYREG_B0_P3_U0_MC_CFG_BYPASS EQU 0x4001063e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG0\r
+CYREG_B0_P3_U0_CFG0 EQU 0x40010640\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG1\r
+CYREG_B0_P3_U0_CFG1 EQU 0x40010641\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG2\r
+CYREG_B0_P3_U0_CFG2 EQU 0x40010642\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG3\r
+CYREG_B0_P3_U0_CFG3 EQU 0x40010643\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG4\r
+CYREG_B0_P3_U0_CFG4 EQU 0x40010644\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG5\r
+CYREG_B0_P3_U0_CFG5 EQU 0x40010645\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG6\r
+CYREG_B0_P3_U0_CFG6 EQU 0x40010646\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG7\r
+CYREG_B0_P3_U0_CFG7 EQU 0x40010647\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG8\r
+CYREG_B0_P3_U0_CFG8 EQU 0x40010648\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG9\r
+CYREG_B0_P3_U0_CFG9 EQU 0x40010649\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG10\r
+CYREG_B0_P3_U0_CFG10 EQU 0x4001064a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG11\r
+CYREG_B0_P3_U0_CFG11 EQU 0x4001064b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG12\r
+CYREG_B0_P3_U0_CFG12 EQU 0x4001064c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG13\r
+CYREG_B0_P3_U0_CFG13 EQU 0x4001064d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG14\r
+CYREG_B0_P3_U0_CFG14 EQU 0x4001064e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG15\r
+CYREG_B0_P3_U0_CFG15 EQU 0x4001064f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG16\r
+CYREG_B0_P3_U0_CFG16 EQU 0x40010650\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG17\r
+CYREG_B0_P3_U0_CFG17 EQU 0x40010651\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG18\r
+CYREG_B0_P3_U0_CFG18 EQU 0x40010652\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG19\r
+CYREG_B0_P3_U0_CFG19 EQU 0x40010653\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG20\r
+CYREG_B0_P3_U0_CFG20 EQU 0x40010654\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG21\r
+CYREG_B0_P3_U0_CFG21 EQU 0x40010655\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG22\r
+CYREG_B0_P3_U0_CFG22 EQU 0x40010656\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG23\r
+CYREG_B0_P3_U0_CFG23 EQU 0x40010657\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG24\r
+CYREG_B0_P3_U0_CFG24 EQU 0x40010658\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG25\r
+CYREG_B0_P3_U0_CFG25 EQU 0x40010659\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG26\r
+CYREG_B0_P3_U0_CFG26 EQU 0x4001065a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG27\r
+CYREG_B0_P3_U0_CFG27 EQU 0x4001065b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG28\r
+CYREG_B0_P3_U0_CFG28 EQU 0x4001065c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG29\r
+CYREG_B0_P3_U0_CFG29 EQU 0x4001065d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG30\r
+CYREG_B0_P3_U0_CFG30 EQU 0x4001065e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_CFG31\r
+CYREG_B0_P3_U0_CFG31 EQU 0x4001065f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG0\r
+CYREG_B0_P3_U0_DCFG0 EQU 0x40010660\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG1\r
+CYREG_B0_P3_U0_DCFG1 EQU 0x40010662\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG2\r
+CYREG_B0_P3_U0_DCFG2 EQU 0x40010664\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG3\r
+CYREG_B0_P3_U0_DCFG3 EQU 0x40010666\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG4\r
+CYREG_B0_P3_U0_DCFG4 EQU 0x40010668\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG5\r
+CYREG_B0_P3_U0_DCFG5 EQU 0x4001066a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG6\r
+CYREG_B0_P3_U0_DCFG6 EQU 0x4001066c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG7\r
+CYREG_B0_P3_U0_DCFG7 EQU 0x4001066e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_BASE\r
+CYDEV_UCFG_B0_P3_U1_BASE EQU 0x40010680\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_SIZE\r
+CYDEV_UCFG_B0_P3_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT0\r
+CYREG_B0_P3_U1_PLD_IT0 EQU 0x40010680\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT1\r
+CYREG_B0_P3_U1_PLD_IT1 EQU 0x40010684\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT2\r
+CYREG_B0_P3_U1_PLD_IT2 EQU 0x40010688\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT3\r
+CYREG_B0_P3_U1_PLD_IT3 EQU 0x4001068c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT4\r
+CYREG_B0_P3_U1_PLD_IT4 EQU 0x40010690\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT5\r
+CYREG_B0_P3_U1_PLD_IT5 EQU 0x40010694\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT6\r
+CYREG_B0_P3_U1_PLD_IT6 EQU 0x40010698\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT7\r
+CYREG_B0_P3_U1_PLD_IT7 EQU 0x4001069c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT8\r
+CYREG_B0_P3_U1_PLD_IT8 EQU 0x400106a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT9\r
+CYREG_B0_P3_U1_PLD_IT9 EQU 0x400106a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT10\r
+CYREG_B0_P3_U1_PLD_IT10 EQU 0x400106a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT11\r
+CYREG_B0_P3_U1_PLD_IT11 EQU 0x400106ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT0\r
+CYREG_B0_P3_U1_PLD_ORT0 EQU 0x400106b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT1\r
+CYREG_B0_P3_U1_PLD_ORT1 EQU 0x400106b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT2\r
+CYREG_B0_P3_U1_PLD_ORT2 EQU 0x400106b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT3\r
+CYREG_B0_P3_U1_PLD_ORT3 EQU 0x400106b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_CEN_CONST\r
+CYREG_B0_P3_U1_MC_CFG_CEN_CONST EQU 0x400106b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_XORFB\r
+CYREG_B0_P3_U1_MC_CFG_XORFB EQU 0x400106ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_SET_RESET\r
+CYREG_B0_P3_U1_MC_CFG_SET_RESET EQU 0x400106bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_BYPASS\r
+CYREG_B0_P3_U1_MC_CFG_BYPASS EQU 0x400106be\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG0\r
+CYREG_B0_P3_U1_CFG0 EQU 0x400106c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG1\r
+CYREG_B0_P3_U1_CFG1 EQU 0x400106c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG2\r
+CYREG_B0_P3_U1_CFG2 EQU 0x400106c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG3\r
+CYREG_B0_P3_U1_CFG3 EQU 0x400106c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG4\r
+CYREG_B0_P3_U1_CFG4 EQU 0x400106c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG5\r
+CYREG_B0_P3_U1_CFG5 EQU 0x400106c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG6\r
+CYREG_B0_P3_U1_CFG6 EQU 0x400106c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG7\r
+CYREG_B0_P3_U1_CFG7 EQU 0x400106c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG8\r
+CYREG_B0_P3_U1_CFG8 EQU 0x400106c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG9\r
+CYREG_B0_P3_U1_CFG9 EQU 0x400106c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG10\r
+CYREG_B0_P3_U1_CFG10 EQU 0x400106ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG11\r
+CYREG_B0_P3_U1_CFG11 EQU 0x400106cb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG12\r
+CYREG_B0_P3_U1_CFG12 EQU 0x400106cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG13\r
+CYREG_B0_P3_U1_CFG13 EQU 0x400106cd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG14\r
+CYREG_B0_P3_U1_CFG14 EQU 0x400106ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG15\r
+CYREG_B0_P3_U1_CFG15 EQU 0x400106cf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG16\r
+CYREG_B0_P3_U1_CFG16 EQU 0x400106d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG17\r
+CYREG_B0_P3_U1_CFG17 EQU 0x400106d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG18\r
+CYREG_B0_P3_U1_CFG18 EQU 0x400106d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG19\r
+CYREG_B0_P3_U1_CFG19 EQU 0x400106d3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG20\r
+CYREG_B0_P3_U1_CFG20 EQU 0x400106d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG21\r
+CYREG_B0_P3_U1_CFG21 EQU 0x400106d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG22\r
+CYREG_B0_P3_U1_CFG22 EQU 0x400106d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG23\r
+CYREG_B0_P3_U1_CFG23 EQU 0x400106d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG24\r
+CYREG_B0_P3_U1_CFG24 EQU 0x400106d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG25\r
+CYREG_B0_P3_U1_CFG25 EQU 0x400106d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG26\r
+CYREG_B0_P3_U1_CFG26 EQU 0x400106da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG27\r
+CYREG_B0_P3_U1_CFG27 EQU 0x400106db\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG28\r
+CYREG_B0_P3_U1_CFG28 EQU 0x400106dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG29\r
+CYREG_B0_P3_U1_CFG29 EQU 0x400106dd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG30\r
+CYREG_B0_P3_U1_CFG30 EQU 0x400106de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_CFG31\r
+CYREG_B0_P3_U1_CFG31 EQU 0x400106df\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG0\r
+CYREG_B0_P3_U1_DCFG0 EQU 0x400106e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG1\r
+CYREG_B0_P3_U1_DCFG1 EQU 0x400106e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG2\r
+CYREG_B0_P3_U1_DCFG2 EQU 0x400106e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG3\r
+CYREG_B0_P3_U1_DCFG3 EQU 0x400106e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG4\r
+CYREG_B0_P3_U1_DCFG4 EQU 0x400106e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG5\r
+CYREG_B0_P3_U1_DCFG5 EQU 0x400106ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG6\r
+CYREG_B0_P3_U1_DCFG6 EQU 0x400106ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG7\r
+CYREG_B0_P3_U1_DCFG7 EQU 0x400106ee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_BASE\r
+CYDEV_UCFG_B0_P3_ROUTE_BASE EQU 0x40010700\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_SIZE\r
+CYDEV_UCFG_B0_P3_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_BASE\r
+CYDEV_UCFG_B0_P4_BASE EQU 0x40010800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_SIZE\r
+CYDEV_UCFG_B0_P4_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_BASE\r
+CYDEV_UCFG_B0_P4_U0_BASE EQU 0x40010800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_SIZE\r
+CYDEV_UCFG_B0_P4_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT0\r
+CYREG_B0_P4_U0_PLD_IT0 EQU 0x40010800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT1\r
+CYREG_B0_P4_U0_PLD_IT1 EQU 0x40010804\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT2\r
+CYREG_B0_P4_U0_PLD_IT2 EQU 0x40010808\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT3\r
+CYREG_B0_P4_U0_PLD_IT3 EQU 0x4001080c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT4\r
+CYREG_B0_P4_U0_PLD_IT4 EQU 0x40010810\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT5\r
+CYREG_B0_P4_U0_PLD_IT5 EQU 0x40010814\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT6\r
+CYREG_B0_P4_U0_PLD_IT6 EQU 0x40010818\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT7\r
+CYREG_B0_P4_U0_PLD_IT7 EQU 0x4001081c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT8\r
+CYREG_B0_P4_U0_PLD_IT8 EQU 0x40010820\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT9\r
+CYREG_B0_P4_U0_PLD_IT9 EQU 0x40010824\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT10\r
+CYREG_B0_P4_U0_PLD_IT10 EQU 0x40010828\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT11\r
+CYREG_B0_P4_U0_PLD_IT11 EQU 0x4001082c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT0\r
+CYREG_B0_P4_U0_PLD_ORT0 EQU 0x40010830\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT1\r
+CYREG_B0_P4_U0_PLD_ORT1 EQU 0x40010832\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT2\r
+CYREG_B0_P4_U0_PLD_ORT2 EQU 0x40010834\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT3\r
+CYREG_B0_P4_U0_PLD_ORT3 EQU 0x40010836\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_CEN_CONST\r
+CYREG_B0_P4_U0_MC_CFG_CEN_CONST EQU 0x40010838\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_XORFB\r
+CYREG_B0_P4_U0_MC_CFG_XORFB EQU 0x4001083a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_SET_RESET\r
+CYREG_B0_P4_U0_MC_CFG_SET_RESET EQU 0x4001083c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_BYPASS\r
+CYREG_B0_P4_U0_MC_CFG_BYPASS EQU 0x4001083e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG0\r
+CYREG_B0_P4_U0_CFG0 EQU 0x40010840\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG1\r
+CYREG_B0_P4_U0_CFG1 EQU 0x40010841\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG2\r
+CYREG_B0_P4_U0_CFG2 EQU 0x40010842\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG3\r
+CYREG_B0_P4_U0_CFG3 EQU 0x40010843\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG4\r
+CYREG_B0_P4_U0_CFG4 EQU 0x40010844\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG5\r
+CYREG_B0_P4_U0_CFG5 EQU 0x40010845\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG6\r
+CYREG_B0_P4_U0_CFG6 EQU 0x40010846\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG7\r
+CYREG_B0_P4_U0_CFG7 EQU 0x40010847\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG8\r
+CYREG_B0_P4_U0_CFG8 EQU 0x40010848\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG9\r
+CYREG_B0_P4_U0_CFG9 EQU 0x40010849\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG10\r
+CYREG_B0_P4_U0_CFG10 EQU 0x4001084a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG11\r
+CYREG_B0_P4_U0_CFG11 EQU 0x4001084b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG12\r
+CYREG_B0_P4_U0_CFG12 EQU 0x4001084c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG13\r
+CYREG_B0_P4_U0_CFG13 EQU 0x4001084d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG14\r
+CYREG_B0_P4_U0_CFG14 EQU 0x4001084e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG15\r
+CYREG_B0_P4_U0_CFG15 EQU 0x4001084f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG16\r
+CYREG_B0_P4_U0_CFG16 EQU 0x40010850\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG17\r
+CYREG_B0_P4_U0_CFG17 EQU 0x40010851\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG18\r
+CYREG_B0_P4_U0_CFG18 EQU 0x40010852\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG19\r
+CYREG_B0_P4_U0_CFG19 EQU 0x40010853\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG20\r
+CYREG_B0_P4_U0_CFG20 EQU 0x40010854\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG21\r
+CYREG_B0_P4_U0_CFG21 EQU 0x40010855\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG22\r
+CYREG_B0_P4_U0_CFG22 EQU 0x40010856\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG23\r
+CYREG_B0_P4_U0_CFG23 EQU 0x40010857\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG24\r
+CYREG_B0_P4_U0_CFG24 EQU 0x40010858\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG25\r
+CYREG_B0_P4_U0_CFG25 EQU 0x40010859\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG26\r
+CYREG_B0_P4_U0_CFG26 EQU 0x4001085a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG27\r
+CYREG_B0_P4_U0_CFG27 EQU 0x4001085b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG28\r
+CYREG_B0_P4_U0_CFG28 EQU 0x4001085c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG29\r
+CYREG_B0_P4_U0_CFG29 EQU 0x4001085d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG30\r
+CYREG_B0_P4_U0_CFG30 EQU 0x4001085e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_CFG31\r
+CYREG_B0_P4_U0_CFG31 EQU 0x4001085f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG0\r
+CYREG_B0_P4_U0_DCFG0 EQU 0x40010860\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG1\r
+CYREG_B0_P4_U0_DCFG1 EQU 0x40010862\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG2\r
+CYREG_B0_P4_U0_DCFG2 EQU 0x40010864\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG3\r
+CYREG_B0_P4_U0_DCFG3 EQU 0x40010866\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG4\r
+CYREG_B0_P4_U0_DCFG4 EQU 0x40010868\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG5\r
+CYREG_B0_P4_U0_DCFG5 EQU 0x4001086a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG6\r
+CYREG_B0_P4_U0_DCFG6 EQU 0x4001086c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG7\r
+CYREG_B0_P4_U0_DCFG7 EQU 0x4001086e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_BASE\r
+CYDEV_UCFG_B0_P4_U1_BASE EQU 0x40010880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_SIZE\r
+CYDEV_UCFG_B0_P4_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT0\r
+CYREG_B0_P4_U1_PLD_IT0 EQU 0x40010880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT1\r
+CYREG_B0_P4_U1_PLD_IT1 EQU 0x40010884\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT2\r
+CYREG_B0_P4_U1_PLD_IT2 EQU 0x40010888\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT3\r
+CYREG_B0_P4_U1_PLD_IT3 EQU 0x4001088c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT4\r
+CYREG_B0_P4_U1_PLD_IT4 EQU 0x40010890\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT5\r
+CYREG_B0_P4_U1_PLD_IT5 EQU 0x40010894\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT6\r
+CYREG_B0_P4_U1_PLD_IT6 EQU 0x40010898\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT7\r
+CYREG_B0_P4_U1_PLD_IT7 EQU 0x4001089c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT8\r
+CYREG_B0_P4_U1_PLD_IT8 EQU 0x400108a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT9\r
+CYREG_B0_P4_U1_PLD_IT9 EQU 0x400108a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT10\r
+CYREG_B0_P4_U1_PLD_IT10 EQU 0x400108a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT11\r
+CYREG_B0_P4_U1_PLD_IT11 EQU 0x400108ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT0\r
+CYREG_B0_P4_U1_PLD_ORT0 EQU 0x400108b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT1\r
+CYREG_B0_P4_U1_PLD_ORT1 EQU 0x400108b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT2\r
+CYREG_B0_P4_U1_PLD_ORT2 EQU 0x400108b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT3\r
+CYREG_B0_P4_U1_PLD_ORT3 EQU 0x400108b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_CEN_CONST\r
+CYREG_B0_P4_U1_MC_CFG_CEN_CONST EQU 0x400108b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_XORFB\r
+CYREG_B0_P4_U1_MC_CFG_XORFB EQU 0x400108ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_SET_RESET\r
+CYREG_B0_P4_U1_MC_CFG_SET_RESET EQU 0x400108bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_BYPASS\r
+CYREG_B0_P4_U1_MC_CFG_BYPASS EQU 0x400108be\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG0\r
+CYREG_B0_P4_U1_CFG0 EQU 0x400108c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG1\r
+CYREG_B0_P4_U1_CFG1 EQU 0x400108c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG2\r
+CYREG_B0_P4_U1_CFG2 EQU 0x400108c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG3\r
+CYREG_B0_P4_U1_CFG3 EQU 0x400108c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG4\r
+CYREG_B0_P4_U1_CFG4 EQU 0x400108c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG5\r
+CYREG_B0_P4_U1_CFG5 EQU 0x400108c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG6\r
+CYREG_B0_P4_U1_CFG6 EQU 0x400108c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG7\r
+CYREG_B0_P4_U1_CFG7 EQU 0x400108c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG8\r
+CYREG_B0_P4_U1_CFG8 EQU 0x400108c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG9\r
+CYREG_B0_P4_U1_CFG9 EQU 0x400108c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG10\r
+CYREG_B0_P4_U1_CFG10 EQU 0x400108ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG11\r
+CYREG_B0_P4_U1_CFG11 EQU 0x400108cb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG12\r
+CYREG_B0_P4_U1_CFG12 EQU 0x400108cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG13\r
+CYREG_B0_P4_U1_CFG13 EQU 0x400108cd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG14\r
+CYREG_B0_P4_U1_CFG14 EQU 0x400108ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG15\r
+CYREG_B0_P4_U1_CFG15 EQU 0x400108cf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG16\r
+CYREG_B0_P4_U1_CFG16 EQU 0x400108d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG17\r
+CYREG_B0_P4_U1_CFG17 EQU 0x400108d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG18\r
+CYREG_B0_P4_U1_CFG18 EQU 0x400108d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG19\r
+CYREG_B0_P4_U1_CFG19 EQU 0x400108d3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG20\r
+CYREG_B0_P4_U1_CFG20 EQU 0x400108d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG21\r
+CYREG_B0_P4_U1_CFG21 EQU 0x400108d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG22\r
+CYREG_B0_P4_U1_CFG22 EQU 0x400108d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG23\r
+CYREG_B0_P4_U1_CFG23 EQU 0x400108d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG24\r
+CYREG_B0_P4_U1_CFG24 EQU 0x400108d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG25\r
+CYREG_B0_P4_U1_CFG25 EQU 0x400108d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG26\r
+CYREG_B0_P4_U1_CFG26 EQU 0x400108da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG27\r
+CYREG_B0_P4_U1_CFG27 EQU 0x400108db\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG28\r
+CYREG_B0_P4_U1_CFG28 EQU 0x400108dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG29\r
+CYREG_B0_P4_U1_CFG29 EQU 0x400108dd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG30\r
+CYREG_B0_P4_U1_CFG30 EQU 0x400108de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_CFG31\r
+CYREG_B0_P4_U1_CFG31 EQU 0x400108df\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG0\r
+CYREG_B0_P4_U1_DCFG0 EQU 0x400108e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG1\r
+CYREG_B0_P4_U1_DCFG1 EQU 0x400108e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG2\r
+CYREG_B0_P4_U1_DCFG2 EQU 0x400108e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG3\r
+CYREG_B0_P4_U1_DCFG3 EQU 0x400108e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG4\r
+CYREG_B0_P4_U1_DCFG4 EQU 0x400108e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG5\r
+CYREG_B0_P4_U1_DCFG5 EQU 0x400108ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG6\r
+CYREG_B0_P4_U1_DCFG6 EQU 0x400108ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG7\r
+CYREG_B0_P4_U1_DCFG7 EQU 0x400108ee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_BASE\r
+CYDEV_UCFG_B0_P4_ROUTE_BASE EQU 0x40010900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_SIZE\r
+CYDEV_UCFG_B0_P4_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_BASE\r
+CYDEV_UCFG_B0_P5_BASE EQU 0x40010a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_SIZE\r
+CYDEV_UCFG_B0_P5_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_BASE\r
+CYDEV_UCFG_B0_P5_U0_BASE EQU 0x40010a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_SIZE\r
+CYDEV_UCFG_B0_P5_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT0\r
+CYREG_B0_P5_U0_PLD_IT0 EQU 0x40010a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT1\r
+CYREG_B0_P5_U0_PLD_IT1 EQU 0x40010a04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT2\r
+CYREG_B0_P5_U0_PLD_IT2 EQU 0x40010a08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT3\r
+CYREG_B0_P5_U0_PLD_IT3 EQU 0x40010a0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT4\r
+CYREG_B0_P5_U0_PLD_IT4 EQU 0x40010a10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT5\r
+CYREG_B0_P5_U0_PLD_IT5 EQU 0x40010a14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT6\r
+CYREG_B0_P5_U0_PLD_IT6 EQU 0x40010a18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT7\r
+CYREG_B0_P5_U0_PLD_IT7 EQU 0x40010a1c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT8\r
+CYREG_B0_P5_U0_PLD_IT8 EQU 0x40010a20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT9\r
+CYREG_B0_P5_U0_PLD_IT9 EQU 0x40010a24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT10\r
+CYREG_B0_P5_U0_PLD_IT10 EQU 0x40010a28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT11\r
+CYREG_B0_P5_U0_PLD_IT11 EQU 0x40010a2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT0\r
+CYREG_B0_P5_U0_PLD_ORT0 EQU 0x40010a30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT1\r
+CYREG_B0_P5_U0_PLD_ORT1 EQU 0x40010a32\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT2\r
+CYREG_B0_P5_U0_PLD_ORT2 EQU 0x40010a34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT3\r
+CYREG_B0_P5_U0_PLD_ORT3 EQU 0x40010a36\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_CEN_CONST\r
+CYREG_B0_P5_U0_MC_CFG_CEN_CONST EQU 0x40010a38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_XORFB\r
+CYREG_B0_P5_U0_MC_CFG_XORFB EQU 0x40010a3a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_SET_RESET\r
+CYREG_B0_P5_U0_MC_CFG_SET_RESET EQU 0x40010a3c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_BYPASS\r
+CYREG_B0_P5_U0_MC_CFG_BYPASS EQU 0x40010a3e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG0\r
+CYREG_B0_P5_U0_CFG0 EQU 0x40010a40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG1\r
+CYREG_B0_P5_U0_CFG1 EQU 0x40010a41\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG2\r
+CYREG_B0_P5_U0_CFG2 EQU 0x40010a42\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG3\r
+CYREG_B0_P5_U0_CFG3 EQU 0x40010a43\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG4\r
+CYREG_B0_P5_U0_CFG4 EQU 0x40010a44\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG5\r
+CYREG_B0_P5_U0_CFG5 EQU 0x40010a45\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG6\r
+CYREG_B0_P5_U0_CFG6 EQU 0x40010a46\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG7\r
+CYREG_B0_P5_U0_CFG7 EQU 0x40010a47\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG8\r
+CYREG_B0_P5_U0_CFG8 EQU 0x40010a48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG9\r
+CYREG_B0_P5_U0_CFG9 EQU 0x40010a49\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG10\r
+CYREG_B0_P5_U0_CFG10 EQU 0x40010a4a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG11\r
+CYREG_B0_P5_U0_CFG11 EQU 0x40010a4b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG12\r
+CYREG_B0_P5_U0_CFG12 EQU 0x40010a4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG13\r
+CYREG_B0_P5_U0_CFG13 EQU 0x40010a4d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG14\r
+CYREG_B0_P5_U0_CFG14 EQU 0x40010a4e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG15\r
+CYREG_B0_P5_U0_CFG15 EQU 0x40010a4f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG16\r
+CYREG_B0_P5_U0_CFG16 EQU 0x40010a50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG17\r
+CYREG_B0_P5_U0_CFG17 EQU 0x40010a51\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG18\r
+CYREG_B0_P5_U0_CFG18 EQU 0x40010a52\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG19\r
+CYREG_B0_P5_U0_CFG19 EQU 0x40010a53\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG20\r
+CYREG_B0_P5_U0_CFG20 EQU 0x40010a54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG21\r
+CYREG_B0_P5_U0_CFG21 EQU 0x40010a55\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG22\r
+CYREG_B0_P5_U0_CFG22 EQU 0x40010a56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG23\r
+CYREG_B0_P5_U0_CFG23 EQU 0x40010a57\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG24\r
+CYREG_B0_P5_U0_CFG24 EQU 0x40010a58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG25\r
+CYREG_B0_P5_U0_CFG25 EQU 0x40010a59\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG26\r
+CYREG_B0_P5_U0_CFG26 EQU 0x40010a5a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG27\r
+CYREG_B0_P5_U0_CFG27 EQU 0x40010a5b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG28\r
+CYREG_B0_P5_U0_CFG28 EQU 0x40010a5c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG29\r
+CYREG_B0_P5_U0_CFG29 EQU 0x40010a5d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG30\r
+CYREG_B0_P5_U0_CFG30 EQU 0x40010a5e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_CFG31\r
+CYREG_B0_P5_U0_CFG31 EQU 0x40010a5f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG0\r
+CYREG_B0_P5_U0_DCFG0 EQU 0x40010a60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG1\r
+CYREG_B0_P5_U0_DCFG1 EQU 0x40010a62\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG2\r
+CYREG_B0_P5_U0_DCFG2 EQU 0x40010a64\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG3\r
+CYREG_B0_P5_U0_DCFG3 EQU 0x40010a66\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG4\r
+CYREG_B0_P5_U0_DCFG4 EQU 0x40010a68\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG5\r
+CYREG_B0_P5_U0_DCFG5 EQU 0x40010a6a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG6\r
+CYREG_B0_P5_U0_DCFG6 EQU 0x40010a6c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG7\r
+CYREG_B0_P5_U0_DCFG7 EQU 0x40010a6e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_BASE\r
+CYDEV_UCFG_B0_P5_U1_BASE EQU 0x40010a80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_SIZE\r
+CYDEV_UCFG_B0_P5_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT0\r
+CYREG_B0_P5_U1_PLD_IT0 EQU 0x40010a80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT1\r
+CYREG_B0_P5_U1_PLD_IT1 EQU 0x40010a84\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT2\r
+CYREG_B0_P5_U1_PLD_IT2 EQU 0x40010a88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT3\r
+CYREG_B0_P5_U1_PLD_IT3 EQU 0x40010a8c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT4\r
+CYREG_B0_P5_U1_PLD_IT4 EQU 0x40010a90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT5\r
+CYREG_B0_P5_U1_PLD_IT5 EQU 0x40010a94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT6\r
+CYREG_B0_P5_U1_PLD_IT6 EQU 0x40010a98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT7\r
+CYREG_B0_P5_U1_PLD_IT7 EQU 0x40010a9c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT8\r
+CYREG_B0_P5_U1_PLD_IT8 EQU 0x40010aa0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT9\r
+CYREG_B0_P5_U1_PLD_IT9 EQU 0x40010aa4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT10\r
+CYREG_B0_P5_U1_PLD_IT10 EQU 0x40010aa8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT11\r
+CYREG_B0_P5_U1_PLD_IT11 EQU 0x40010aac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT0\r
+CYREG_B0_P5_U1_PLD_ORT0 EQU 0x40010ab0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT1\r
+CYREG_B0_P5_U1_PLD_ORT1 EQU 0x40010ab2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT2\r
+CYREG_B0_P5_U1_PLD_ORT2 EQU 0x40010ab4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT3\r
+CYREG_B0_P5_U1_PLD_ORT3 EQU 0x40010ab6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_CEN_CONST\r
+CYREG_B0_P5_U1_MC_CFG_CEN_CONST EQU 0x40010ab8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_XORFB\r
+CYREG_B0_P5_U1_MC_CFG_XORFB EQU 0x40010aba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_SET_RESET\r
+CYREG_B0_P5_U1_MC_CFG_SET_RESET EQU 0x40010abc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_BYPASS\r
+CYREG_B0_P5_U1_MC_CFG_BYPASS EQU 0x40010abe\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG0\r
+CYREG_B0_P5_U1_CFG0 EQU 0x40010ac0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG1\r
+CYREG_B0_P5_U1_CFG1 EQU 0x40010ac1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG2\r
+CYREG_B0_P5_U1_CFG2 EQU 0x40010ac2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG3\r
+CYREG_B0_P5_U1_CFG3 EQU 0x40010ac3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG4\r
+CYREG_B0_P5_U1_CFG4 EQU 0x40010ac4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG5\r
+CYREG_B0_P5_U1_CFG5 EQU 0x40010ac5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG6\r
+CYREG_B0_P5_U1_CFG6 EQU 0x40010ac6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG7\r
+CYREG_B0_P5_U1_CFG7 EQU 0x40010ac7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG8\r
+CYREG_B0_P5_U1_CFG8 EQU 0x40010ac8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG9\r
+CYREG_B0_P5_U1_CFG9 EQU 0x40010ac9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG10\r
+CYREG_B0_P5_U1_CFG10 EQU 0x40010aca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG11\r
+CYREG_B0_P5_U1_CFG11 EQU 0x40010acb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG12\r
+CYREG_B0_P5_U1_CFG12 EQU 0x40010acc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG13\r
+CYREG_B0_P5_U1_CFG13 EQU 0x40010acd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG14\r
+CYREG_B0_P5_U1_CFG14 EQU 0x40010ace\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG15\r
+CYREG_B0_P5_U1_CFG15 EQU 0x40010acf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG16\r
+CYREG_B0_P5_U1_CFG16 EQU 0x40010ad0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG17\r
+CYREG_B0_P5_U1_CFG17 EQU 0x40010ad1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG18\r
+CYREG_B0_P5_U1_CFG18 EQU 0x40010ad2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG19\r
+CYREG_B0_P5_U1_CFG19 EQU 0x40010ad3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG20\r
+CYREG_B0_P5_U1_CFG20 EQU 0x40010ad4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG21\r
+CYREG_B0_P5_U1_CFG21 EQU 0x40010ad5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG22\r
+CYREG_B0_P5_U1_CFG22 EQU 0x40010ad6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG23\r
+CYREG_B0_P5_U1_CFG23 EQU 0x40010ad7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG24\r
+CYREG_B0_P5_U1_CFG24 EQU 0x40010ad8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG25\r
+CYREG_B0_P5_U1_CFG25 EQU 0x40010ad9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG26\r
+CYREG_B0_P5_U1_CFG26 EQU 0x40010ada\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG27\r
+CYREG_B0_P5_U1_CFG27 EQU 0x40010adb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG28\r
+CYREG_B0_P5_U1_CFG28 EQU 0x40010adc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG29\r
+CYREG_B0_P5_U1_CFG29 EQU 0x40010add\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG30\r
+CYREG_B0_P5_U1_CFG30 EQU 0x40010ade\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_CFG31\r
+CYREG_B0_P5_U1_CFG31 EQU 0x40010adf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG0\r
+CYREG_B0_P5_U1_DCFG0 EQU 0x40010ae0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG1\r
+CYREG_B0_P5_U1_DCFG1 EQU 0x40010ae2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG2\r
+CYREG_B0_P5_U1_DCFG2 EQU 0x40010ae4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG3\r
+CYREG_B0_P5_U1_DCFG3 EQU 0x40010ae6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG4\r
+CYREG_B0_P5_U1_DCFG4 EQU 0x40010ae8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG5\r
+CYREG_B0_P5_U1_DCFG5 EQU 0x40010aea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG6\r
+CYREG_B0_P5_U1_DCFG6 EQU 0x40010aec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG7\r
+CYREG_B0_P5_U1_DCFG7 EQU 0x40010aee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_BASE\r
+CYDEV_UCFG_B0_P5_ROUTE_BASE EQU 0x40010b00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_SIZE\r
+CYDEV_UCFG_B0_P5_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_BASE\r
+CYDEV_UCFG_B0_P6_BASE EQU 0x40010c00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_SIZE\r
+CYDEV_UCFG_B0_P6_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_BASE\r
+CYDEV_UCFG_B0_P6_U0_BASE EQU 0x40010c00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_SIZE\r
+CYDEV_UCFG_B0_P6_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT0\r
+CYREG_B0_P6_U0_PLD_IT0 EQU 0x40010c00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT1\r
+CYREG_B0_P6_U0_PLD_IT1 EQU 0x40010c04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT2\r
+CYREG_B0_P6_U0_PLD_IT2 EQU 0x40010c08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT3\r
+CYREG_B0_P6_U0_PLD_IT3 EQU 0x40010c0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT4\r
+CYREG_B0_P6_U0_PLD_IT4 EQU 0x40010c10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT5\r
+CYREG_B0_P6_U0_PLD_IT5 EQU 0x40010c14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT6\r
+CYREG_B0_P6_U0_PLD_IT6 EQU 0x40010c18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT7\r
+CYREG_B0_P6_U0_PLD_IT7 EQU 0x40010c1c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT8\r
+CYREG_B0_P6_U0_PLD_IT8 EQU 0x40010c20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT9\r
+CYREG_B0_P6_U0_PLD_IT9 EQU 0x40010c24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT10\r
+CYREG_B0_P6_U0_PLD_IT10 EQU 0x40010c28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT11\r
+CYREG_B0_P6_U0_PLD_IT11 EQU 0x40010c2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT0\r
+CYREG_B0_P6_U0_PLD_ORT0 EQU 0x40010c30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT1\r
+CYREG_B0_P6_U0_PLD_ORT1 EQU 0x40010c32\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT2\r
+CYREG_B0_P6_U0_PLD_ORT2 EQU 0x40010c34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT3\r
+CYREG_B0_P6_U0_PLD_ORT3 EQU 0x40010c36\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_CEN_CONST\r
+CYREG_B0_P6_U0_MC_CFG_CEN_CONST EQU 0x40010c38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_XORFB\r
+CYREG_B0_P6_U0_MC_CFG_XORFB EQU 0x40010c3a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_SET_RESET\r
+CYREG_B0_P6_U0_MC_CFG_SET_RESET EQU 0x40010c3c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_BYPASS\r
+CYREG_B0_P6_U0_MC_CFG_BYPASS EQU 0x40010c3e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG0\r
+CYREG_B0_P6_U0_CFG0 EQU 0x40010c40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG1\r
+CYREG_B0_P6_U0_CFG1 EQU 0x40010c41\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG2\r
+CYREG_B0_P6_U0_CFG2 EQU 0x40010c42\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG3\r
+CYREG_B0_P6_U0_CFG3 EQU 0x40010c43\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG4\r
+CYREG_B0_P6_U0_CFG4 EQU 0x40010c44\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG5\r
+CYREG_B0_P6_U0_CFG5 EQU 0x40010c45\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG6\r
+CYREG_B0_P6_U0_CFG6 EQU 0x40010c46\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG7\r
+CYREG_B0_P6_U0_CFG7 EQU 0x40010c47\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG8\r
+CYREG_B0_P6_U0_CFG8 EQU 0x40010c48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG9\r
+CYREG_B0_P6_U0_CFG9 EQU 0x40010c49\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG10\r
+CYREG_B0_P6_U0_CFG10 EQU 0x40010c4a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG11\r
+CYREG_B0_P6_U0_CFG11 EQU 0x40010c4b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG12\r
+CYREG_B0_P6_U0_CFG12 EQU 0x40010c4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG13\r
+CYREG_B0_P6_U0_CFG13 EQU 0x40010c4d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG14\r
+CYREG_B0_P6_U0_CFG14 EQU 0x40010c4e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG15\r
+CYREG_B0_P6_U0_CFG15 EQU 0x40010c4f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG16\r
+CYREG_B0_P6_U0_CFG16 EQU 0x40010c50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG17\r
+CYREG_B0_P6_U0_CFG17 EQU 0x40010c51\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG18\r
+CYREG_B0_P6_U0_CFG18 EQU 0x40010c52\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG19\r
+CYREG_B0_P6_U0_CFG19 EQU 0x40010c53\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG20\r
+CYREG_B0_P6_U0_CFG20 EQU 0x40010c54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG21\r
+CYREG_B0_P6_U0_CFG21 EQU 0x40010c55\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG22\r
+CYREG_B0_P6_U0_CFG22 EQU 0x40010c56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG23\r
+CYREG_B0_P6_U0_CFG23 EQU 0x40010c57\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG24\r
+CYREG_B0_P6_U0_CFG24 EQU 0x40010c58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG25\r
+CYREG_B0_P6_U0_CFG25 EQU 0x40010c59\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG26\r
+CYREG_B0_P6_U0_CFG26 EQU 0x40010c5a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG27\r
+CYREG_B0_P6_U0_CFG27 EQU 0x40010c5b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG28\r
+CYREG_B0_P6_U0_CFG28 EQU 0x40010c5c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG29\r
+CYREG_B0_P6_U0_CFG29 EQU 0x40010c5d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG30\r
+CYREG_B0_P6_U0_CFG30 EQU 0x40010c5e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_CFG31\r
+CYREG_B0_P6_U0_CFG31 EQU 0x40010c5f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG0\r
+CYREG_B0_P6_U0_DCFG0 EQU 0x40010c60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG1\r
+CYREG_B0_P6_U0_DCFG1 EQU 0x40010c62\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG2\r
+CYREG_B0_P6_U0_DCFG2 EQU 0x40010c64\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG3\r
+CYREG_B0_P6_U0_DCFG3 EQU 0x40010c66\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG4\r
+CYREG_B0_P6_U0_DCFG4 EQU 0x40010c68\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG5\r
+CYREG_B0_P6_U0_DCFG5 EQU 0x40010c6a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG6\r
+CYREG_B0_P6_U0_DCFG6 EQU 0x40010c6c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG7\r
+CYREG_B0_P6_U0_DCFG7 EQU 0x40010c6e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_BASE\r
+CYDEV_UCFG_B0_P6_U1_BASE EQU 0x40010c80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_SIZE\r
+CYDEV_UCFG_B0_P6_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT0\r
+CYREG_B0_P6_U1_PLD_IT0 EQU 0x40010c80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT1\r
+CYREG_B0_P6_U1_PLD_IT1 EQU 0x40010c84\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT2\r
+CYREG_B0_P6_U1_PLD_IT2 EQU 0x40010c88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT3\r
+CYREG_B0_P6_U1_PLD_IT3 EQU 0x40010c8c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT4\r
+CYREG_B0_P6_U1_PLD_IT4 EQU 0x40010c90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT5\r
+CYREG_B0_P6_U1_PLD_IT5 EQU 0x40010c94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT6\r
+CYREG_B0_P6_U1_PLD_IT6 EQU 0x40010c98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT7\r
+CYREG_B0_P6_U1_PLD_IT7 EQU 0x40010c9c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT8\r
+CYREG_B0_P6_U1_PLD_IT8 EQU 0x40010ca0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT9\r
+CYREG_B0_P6_U1_PLD_IT9 EQU 0x40010ca4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT10\r
+CYREG_B0_P6_U1_PLD_IT10 EQU 0x40010ca8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT11\r
+CYREG_B0_P6_U1_PLD_IT11 EQU 0x40010cac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT0\r
+CYREG_B0_P6_U1_PLD_ORT0 EQU 0x40010cb0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT1\r
+CYREG_B0_P6_U1_PLD_ORT1 EQU 0x40010cb2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT2\r
+CYREG_B0_P6_U1_PLD_ORT2 EQU 0x40010cb4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT3\r
+CYREG_B0_P6_U1_PLD_ORT3 EQU 0x40010cb6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_CEN_CONST\r
+CYREG_B0_P6_U1_MC_CFG_CEN_CONST EQU 0x40010cb8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_XORFB\r
+CYREG_B0_P6_U1_MC_CFG_XORFB EQU 0x40010cba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_SET_RESET\r
+CYREG_B0_P6_U1_MC_CFG_SET_RESET EQU 0x40010cbc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_BYPASS\r
+CYREG_B0_P6_U1_MC_CFG_BYPASS EQU 0x40010cbe\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG0\r
+CYREG_B0_P6_U1_CFG0 EQU 0x40010cc0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG1\r
+CYREG_B0_P6_U1_CFG1 EQU 0x40010cc1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG2\r
+CYREG_B0_P6_U1_CFG2 EQU 0x40010cc2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG3\r
+CYREG_B0_P6_U1_CFG3 EQU 0x40010cc3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG4\r
+CYREG_B0_P6_U1_CFG4 EQU 0x40010cc4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG5\r
+CYREG_B0_P6_U1_CFG5 EQU 0x40010cc5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG6\r
+CYREG_B0_P6_U1_CFG6 EQU 0x40010cc6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG7\r
+CYREG_B0_P6_U1_CFG7 EQU 0x40010cc7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG8\r
+CYREG_B0_P6_U1_CFG8 EQU 0x40010cc8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG9\r
+CYREG_B0_P6_U1_CFG9 EQU 0x40010cc9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG10\r
+CYREG_B0_P6_U1_CFG10 EQU 0x40010cca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG11\r
+CYREG_B0_P6_U1_CFG11 EQU 0x40010ccb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG12\r
+CYREG_B0_P6_U1_CFG12 EQU 0x40010ccc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG13\r
+CYREG_B0_P6_U1_CFG13 EQU 0x40010ccd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG14\r
+CYREG_B0_P6_U1_CFG14 EQU 0x40010cce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG15\r
+CYREG_B0_P6_U1_CFG15 EQU 0x40010ccf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG16\r
+CYREG_B0_P6_U1_CFG16 EQU 0x40010cd0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG17\r
+CYREG_B0_P6_U1_CFG17 EQU 0x40010cd1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG18\r
+CYREG_B0_P6_U1_CFG18 EQU 0x40010cd2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG19\r
+CYREG_B0_P6_U1_CFG19 EQU 0x40010cd3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG20\r
+CYREG_B0_P6_U1_CFG20 EQU 0x40010cd4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG21\r
+CYREG_B0_P6_U1_CFG21 EQU 0x40010cd5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG22\r
+CYREG_B0_P6_U1_CFG22 EQU 0x40010cd6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG23\r
+CYREG_B0_P6_U1_CFG23 EQU 0x40010cd7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG24\r
+CYREG_B0_P6_U1_CFG24 EQU 0x40010cd8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG25\r
+CYREG_B0_P6_U1_CFG25 EQU 0x40010cd9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG26\r
+CYREG_B0_P6_U1_CFG26 EQU 0x40010cda\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG27\r
+CYREG_B0_P6_U1_CFG27 EQU 0x40010cdb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG28\r
+CYREG_B0_P6_U1_CFG28 EQU 0x40010cdc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG29\r
+CYREG_B0_P6_U1_CFG29 EQU 0x40010cdd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG30\r
+CYREG_B0_P6_U1_CFG30 EQU 0x40010cde\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_CFG31\r
+CYREG_B0_P6_U1_CFG31 EQU 0x40010cdf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG0\r
+CYREG_B0_P6_U1_DCFG0 EQU 0x40010ce0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG1\r
+CYREG_B0_P6_U1_DCFG1 EQU 0x40010ce2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG2\r
+CYREG_B0_P6_U1_DCFG2 EQU 0x40010ce4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG3\r
+CYREG_B0_P6_U1_DCFG3 EQU 0x40010ce6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG4\r
+CYREG_B0_P6_U1_DCFG4 EQU 0x40010ce8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG5\r
+CYREG_B0_P6_U1_DCFG5 EQU 0x40010cea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG6\r
+CYREG_B0_P6_U1_DCFG6 EQU 0x40010cec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG7\r
+CYREG_B0_P6_U1_DCFG7 EQU 0x40010cee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_BASE\r
+CYDEV_UCFG_B0_P6_ROUTE_BASE EQU 0x40010d00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_SIZE\r
+CYDEV_UCFG_B0_P6_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_BASE\r
+CYDEV_UCFG_B0_P7_BASE EQU 0x40010e00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_SIZE\r
+CYDEV_UCFG_B0_P7_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_BASE\r
+CYDEV_UCFG_B0_P7_U0_BASE EQU 0x40010e00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_SIZE\r
+CYDEV_UCFG_B0_P7_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT0\r
+CYREG_B0_P7_U0_PLD_IT0 EQU 0x40010e00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT1\r
+CYREG_B0_P7_U0_PLD_IT1 EQU 0x40010e04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT2\r
+CYREG_B0_P7_U0_PLD_IT2 EQU 0x40010e08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT3\r
+CYREG_B0_P7_U0_PLD_IT3 EQU 0x40010e0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT4\r
+CYREG_B0_P7_U0_PLD_IT4 EQU 0x40010e10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT5\r
+CYREG_B0_P7_U0_PLD_IT5 EQU 0x40010e14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT6\r
+CYREG_B0_P7_U0_PLD_IT6 EQU 0x40010e18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT7\r
+CYREG_B0_P7_U0_PLD_IT7 EQU 0x40010e1c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT8\r
+CYREG_B0_P7_U0_PLD_IT8 EQU 0x40010e20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT9\r
+CYREG_B0_P7_U0_PLD_IT9 EQU 0x40010e24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT10\r
+CYREG_B0_P7_U0_PLD_IT10 EQU 0x40010e28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT11\r
+CYREG_B0_P7_U0_PLD_IT11 EQU 0x40010e2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT0\r
+CYREG_B0_P7_U0_PLD_ORT0 EQU 0x40010e30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT1\r
+CYREG_B0_P7_U0_PLD_ORT1 EQU 0x40010e32\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT2\r
+CYREG_B0_P7_U0_PLD_ORT2 EQU 0x40010e34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT3\r
+CYREG_B0_P7_U0_PLD_ORT3 EQU 0x40010e36\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_CEN_CONST\r
+CYREG_B0_P7_U0_MC_CFG_CEN_CONST EQU 0x40010e38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_XORFB\r
+CYREG_B0_P7_U0_MC_CFG_XORFB EQU 0x40010e3a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_SET_RESET\r
+CYREG_B0_P7_U0_MC_CFG_SET_RESET EQU 0x40010e3c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_BYPASS\r
+CYREG_B0_P7_U0_MC_CFG_BYPASS EQU 0x40010e3e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG0\r
+CYREG_B0_P7_U0_CFG0 EQU 0x40010e40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG1\r
+CYREG_B0_P7_U0_CFG1 EQU 0x40010e41\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG2\r
+CYREG_B0_P7_U0_CFG2 EQU 0x40010e42\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG3\r
+CYREG_B0_P7_U0_CFG3 EQU 0x40010e43\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG4\r
+CYREG_B0_P7_U0_CFG4 EQU 0x40010e44\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG5\r
+CYREG_B0_P7_U0_CFG5 EQU 0x40010e45\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG6\r
+CYREG_B0_P7_U0_CFG6 EQU 0x40010e46\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG7\r
+CYREG_B0_P7_U0_CFG7 EQU 0x40010e47\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG8\r
+CYREG_B0_P7_U0_CFG8 EQU 0x40010e48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG9\r
+CYREG_B0_P7_U0_CFG9 EQU 0x40010e49\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG10\r
+CYREG_B0_P7_U0_CFG10 EQU 0x40010e4a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG11\r
+CYREG_B0_P7_U0_CFG11 EQU 0x40010e4b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG12\r
+CYREG_B0_P7_U0_CFG12 EQU 0x40010e4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG13\r
+CYREG_B0_P7_U0_CFG13 EQU 0x40010e4d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG14\r
+CYREG_B0_P7_U0_CFG14 EQU 0x40010e4e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG15\r
+CYREG_B0_P7_U0_CFG15 EQU 0x40010e4f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG16\r
+CYREG_B0_P7_U0_CFG16 EQU 0x40010e50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG17\r
+CYREG_B0_P7_U0_CFG17 EQU 0x40010e51\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG18\r
+CYREG_B0_P7_U0_CFG18 EQU 0x40010e52\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG19\r
+CYREG_B0_P7_U0_CFG19 EQU 0x40010e53\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG20\r
+CYREG_B0_P7_U0_CFG20 EQU 0x40010e54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG21\r
+CYREG_B0_P7_U0_CFG21 EQU 0x40010e55\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG22\r
+CYREG_B0_P7_U0_CFG22 EQU 0x40010e56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG23\r
+CYREG_B0_P7_U0_CFG23 EQU 0x40010e57\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG24\r
+CYREG_B0_P7_U0_CFG24 EQU 0x40010e58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG25\r
+CYREG_B0_P7_U0_CFG25 EQU 0x40010e59\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG26\r
+CYREG_B0_P7_U0_CFG26 EQU 0x40010e5a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG27\r
+CYREG_B0_P7_U0_CFG27 EQU 0x40010e5b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG28\r
+CYREG_B0_P7_U0_CFG28 EQU 0x40010e5c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG29\r
+CYREG_B0_P7_U0_CFG29 EQU 0x40010e5d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG30\r
+CYREG_B0_P7_U0_CFG30 EQU 0x40010e5e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_CFG31\r
+CYREG_B0_P7_U0_CFG31 EQU 0x40010e5f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG0\r
+CYREG_B0_P7_U0_DCFG0 EQU 0x40010e60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG1\r
+CYREG_B0_P7_U0_DCFG1 EQU 0x40010e62\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG2\r
+CYREG_B0_P7_U0_DCFG2 EQU 0x40010e64\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG3\r
+CYREG_B0_P7_U0_DCFG3 EQU 0x40010e66\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG4\r
+CYREG_B0_P7_U0_DCFG4 EQU 0x40010e68\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG5\r
+CYREG_B0_P7_U0_DCFG5 EQU 0x40010e6a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG6\r
+CYREG_B0_P7_U0_DCFG6 EQU 0x40010e6c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG7\r
+CYREG_B0_P7_U0_DCFG7 EQU 0x40010e6e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_BASE\r
+CYDEV_UCFG_B0_P7_U1_BASE EQU 0x40010e80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_SIZE\r
+CYDEV_UCFG_B0_P7_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT0\r
+CYREG_B0_P7_U1_PLD_IT0 EQU 0x40010e80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT1\r
+CYREG_B0_P7_U1_PLD_IT1 EQU 0x40010e84\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT2\r
+CYREG_B0_P7_U1_PLD_IT2 EQU 0x40010e88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT3\r
+CYREG_B0_P7_U1_PLD_IT3 EQU 0x40010e8c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT4\r
+CYREG_B0_P7_U1_PLD_IT4 EQU 0x40010e90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT5\r
+CYREG_B0_P7_U1_PLD_IT5 EQU 0x40010e94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT6\r
+CYREG_B0_P7_U1_PLD_IT6 EQU 0x40010e98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT7\r
+CYREG_B0_P7_U1_PLD_IT7 EQU 0x40010e9c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT8\r
+CYREG_B0_P7_U1_PLD_IT8 EQU 0x40010ea0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT9\r
+CYREG_B0_P7_U1_PLD_IT9 EQU 0x40010ea4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT10\r
+CYREG_B0_P7_U1_PLD_IT10 EQU 0x40010ea8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT11\r
+CYREG_B0_P7_U1_PLD_IT11 EQU 0x40010eac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT0\r
+CYREG_B0_P7_U1_PLD_ORT0 EQU 0x40010eb0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT1\r
+CYREG_B0_P7_U1_PLD_ORT1 EQU 0x40010eb2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT2\r
+CYREG_B0_P7_U1_PLD_ORT2 EQU 0x40010eb4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT3\r
+CYREG_B0_P7_U1_PLD_ORT3 EQU 0x40010eb6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_CEN_CONST\r
+CYREG_B0_P7_U1_MC_CFG_CEN_CONST EQU 0x40010eb8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_XORFB\r
+CYREG_B0_P7_U1_MC_CFG_XORFB EQU 0x40010eba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_SET_RESET\r
+CYREG_B0_P7_U1_MC_CFG_SET_RESET EQU 0x40010ebc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_BYPASS\r
+CYREG_B0_P7_U1_MC_CFG_BYPASS EQU 0x40010ebe\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG0\r
+CYREG_B0_P7_U1_CFG0 EQU 0x40010ec0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG1\r
+CYREG_B0_P7_U1_CFG1 EQU 0x40010ec1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG2\r
+CYREG_B0_P7_U1_CFG2 EQU 0x40010ec2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG3\r
+CYREG_B0_P7_U1_CFG3 EQU 0x40010ec3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG4\r
+CYREG_B0_P7_U1_CFG4 EQU 0x40010ec4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG5\r
+CYREG_B0_P7_U1_CFG5 EQU 0x40010ec5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG6\r
+CYREG_B0_P7_U1_CFG6 EQU 0x40010ec6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG7\r
+CYREG_B0_P7_U1_CFG7 EQU 0x40010ec7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG8\r
+CYREG_B0_P7_U1_CFG8 EQU 0x40010ec8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG9\r
+CYREG_B0_P7_U1_CFG9 EQU 0x40010ec9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG10\r
+CYREG_B0_P7_U1_CFG10 EQU 0x40010eca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG11\r
+CYREG_B0_P7_U1_CFG11 EQU 0x40010ecb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG12\r
+CYREG_B0_P7_U1_CFG12 EQU 0x40010ecc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG13\r
+CYREG_B0_P7_U1_CFG13 EQU 0x40010ecd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG14\r
+CYREG_B0_P7_U1_CFG14 EQU 0x40010ece\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG15\r
+CYREG_B0_P7_U1_CFG15 EQU 0x40010ecf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG16\r
+CYREG_B0_P7_U1_CFG16 EQU 0x40010ed0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG17\r
+CYREG_B0_P7_U1_CFG17 EQU 0x40010ed1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG18\r
+CYREG_B0_P7_U1_CFG18 EQU 0x40010ed2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG19\r
+CYREG_B0_P7_U1_CFG19 EQU 0x40010ed3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG20\r
+CYREG_B0_P7_U1_CFG20 EQU 0x40010ed4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG21\r
+CYREG_B0_P7_U1_CFG21 EQU 0x40010ed5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG22\r
+CYREG_B0_P7_U1_CFG22 EQU 0x40010ed6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG23\r
+CYREG_B0_P7_U1_CFG23 EQU 0x40010ed7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG24\r
+CYREG_B0_P7_U1_CFG24 EQU 0x40010ed8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG25\r
+CYREG_B0_P7_U1_CFG25 EQU 0x40010ed9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG26\r
+CYREG_B0_P7_U1_CFG26 EQU 0x40010eda\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG27\r
+CYREG_B0_P7_U1_CFG27 EQU 0x40010edb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG28\r
+CYREG_B0_P7_U1_CFG28 EQU 0x40010edc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG29\r
+CYREG_B0_P7_U1_CFG29 EQU 0x40010edd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG30\r
+CYREG_B0_P7_U1_CFG30 EQU 0x40010ede\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_CFG31\r
+CYREG_B0_P7_U1_CFG31 EQU 0x40010edf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG0\r
+CYREG_B0_P7_U1_DCFG0 EQU 0x40010ee0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG1\r
+CYREG_B0_P7_U1_DCFG1 EQU 0x40010ee2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG2\r
+CYREG_B0_P7_U1_DCFG2 EQU 0x40010ee4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG3\r
+CYREG_B0_P7_U1_DCFG3 EQU 0x40010ee6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG4\r
+CYREG_B0_P7_U1_DCFG4 EQU 0x40010ee8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG5\r
+CYREG_B0_P7_U1_DCFG5 EQU 0x40010eea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG6\r
+CYREG_B0_P7_U1_DCFG6 EQU 0x40010eec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG7\r
+CYREG_B0_P7_U1_DCFG7 EQU 0x40010eee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_BASE\r
+CYDEV_UCFG_B0_P7_ROUTE_BASE EQU 0x40010f00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_SIZE\r
+CYDEV_UCFG_B0_P7_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_BASE\r
+CYDEV_UCFG_B1_BASE EQU 0x40011000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_SIZE\r
+CYDEV_UCFG_B1_SIZE EQU 0x00000fef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_BASE\r
+CYDEV_UCFG_B1_P2_BASE EQU 0x40011400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_SIZE\r
+CYDEV_UCFG_B1_P2_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_BASE\r
+CYDEV_UCFG_B1_P2_U0_BASE EQU 0x40011400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_SIZE\r
+CYDEV_UCFG_B1_P2_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT0\r
+CYREG_B1_P2_U0_PLD_IT0 EQU 0x40011400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT1\r
+CYREG_B1_P2_U0_PLD_IT1 EQU 0x40011404\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT2\r
+CYREG_B1_P2_U0_PLD_IT2 EQU 0x40011408\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT3\r
+CYREG_B1_P2_U0_PLD_IT3 EQU 0x4001140c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT4\r
+CYREG_B1_P2_U0_PLD_IT4 EQU 0x40011410\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT5\r
+CYREG_B1_P2_U0_PLD_IT5 EQU 0x40011414\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT6\r
+CYREG_B1_P2_U0_PLD_IT6 EQU 0x40011418\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT7\r
+CYREG_B1_P2_U0_PLD_IT7 EQU 0x4001141c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT8\r
+CYREG_B1_P2_U0_PLD_IT8 EQU 0x40011420\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT9\r
+CYREG_B1_P2_U0_PLD_IT9 EQU 0x40011424\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT10\r
+CYREG_B1_P2_U0_PLD_IT10 EQU 0x40011428\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT11\r
+CYREG_B1_P2_U0_PLD_IT11 EQU 0x4001142c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT0\r
+CYREG_B1_P2_U0_PLD_ORT0 EQU 0x40011430\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT1\r
+CYREG_B1_P2_U0_PLD_ORT1 EQU 0x40011432\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT2\r
+CYREG_B1_P2_U0_PLD_ORT2 EQU 0x40011434\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT3\r
+CYREG_B1_P2_U0_PLD_ORT3 EQU 0x40011436\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_CEN_CONST\r
+CYREG_B1_P2_U0_MC_CFG_CEN_CONST EQU 0x40011438\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_XORFB\r
+CYREG_B1_P2_U0_MC_CFG_XORFB EQU 0x4001143a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_SET_RESET\r
+CYREG_B1_P2_U0_MC_CFG_SET_RESET EQU 0x4001143c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_BYPASS\r
+CYREG_B1_P2_U0_MC_CFG_BYPASS EQU 0x4001143e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG0\r
+CYREG_B1_P2_U0_CFG0 EQU 0x40011440\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG1\r
+CYREG_B1_P2_U0_CFG1 EQU 0x40011441\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG2\r
+CYREG_B1_P2_U0_CFG2 EQU 0x40011442\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG3\r
+CYREG_B1_P2_U0_CFG3 EQU 0x40011443\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG4\r
+CYREG_B1_P2_U0_CFG4 EQU 0x40011444\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG5\r
+CYREG_B1_P2_U0_CFG5 EQU 0x40011445\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG6\r
+CYREG_B1_P2_U0_CFG6 EQU 0x40011446\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG7\r
+CYREG_B1_P2_U0_CFG7 EQU 0x40011447\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG8\r
+CYREG_B1_P2_U0_CFG8 EQU 0x40011448\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG9\r
+CYREG_B1_P2_U0_CFG9 EQU 0x40011449\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG10\r
+CYREG_B1_P2_U0_CFG10 EQU 0x4001144a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG11\r
+CYREG_B1_P2_U0_CFG11 EQU 0x4001144b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG12\r
+CYREG_B1_P2_U0_CFG12 EQU 0x4001144c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG13\r
+CYREG_B1_P2_U0_CFG13 EQU 0x4001144d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG14\r
+CYREG_B1_P2_U0_CFG14 EQU 0x4001144e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG15\r
+CYREG_B1_P2_U0_CFG15 EQU 0x4001144f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG16\r
+CYREG_B1_P2_U0_CFG16 EQU 0x40011450\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG17\r
+CYREG_B1_P2_U0_CFG17 EQU 0x40011451\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG18\r
+CYREG_B1_P2_U0_CFG18 EQU 0x40011452\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG19\r
+CYREG_B1_P2_U0_CFG19 EQU 0x40011453\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG20\r
+CYREG_B1_P2_U0_CFG20 EQU 0x40011454\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG21\r
+CYREG_B1_P2_U0_CFG21 EQU 0x40011455\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG22\r
+CYREG_B1_P2_U0_CFG22 EQU 0x40011456\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG23\r
+CYREG_B1_P2_U0_CFG23 EQU 0x40011457\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG24\r
+CYREG_B1_P2_U0_CFG24 EQU 0x40011458\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG25\r
+CYREG_B1_P2_U0_CFG25 EQU 0x40011459\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG26\r
+CYREG_B1_P2_U0_CFG26 EQU 0x4001145a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG27\r
+CYREG_B1_P2_U0_CFG27 EQU 0x4001145b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG28\r
+CYREG_B1_P2_U0_CFG28 EQU 0x4001145c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG29\r
+CYREG_B1_P2_U0_CFG29 EQU 0x4001145d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG30\r
+CYREG_B1_P2_U0_CFG30 EQU 0x4001145e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_CFG31\r
+CYREG_B1_P2_U0_CFG31 EQU 0x4001145f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG0\r
+CYREG_B1_P2_U0_DCFG0 EQU 0x40011460\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG1\r
+CYREG_B1_P2_U0_DCFG1 EQU 0x40011462\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG2\r
+CYREG_B1_P2_U0_DCFG2 EQU 0x40011464\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG3\r
+CYREG_B1_P2_U0_DCFG3 EQU 0x40011466\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG4\r
+CYREG_B1_P2_U0_DCFG4 EQU 0x40011468\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG5\r
+CYREG_B1_P2_U0_DCFG5 EQU 0x4001146a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG6\r
+CYREG_B1_P2_U0_DCFG6 EQU 0x4001146c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG7\r
+CYREG_B1_P2_U0_DCFG7 EQU 0x4001146e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_BASE\r
+CYDEV_UCFG_B1_P2_U1_BASE EQU 0x40011480\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_SIZE\r
+CYDEV_UCFG_B1_P2_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT0\r
+CYREG_B1_P2_U1_PLD_IT0 EQU 0x40011480\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT1\r
+CYREG_B1_P2_U1_PLD_IT1 EQU 0x40011484\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT2\r
+CYREG_B1_P2_U1_PLD_IT2 EQU 0x40011488\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT3\r
+CYREG_B1_P2_U1_PLD_IT3 EQU 0x4001148c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT4\r
+CYREG_B1_P2_U1_PLD_IT4 EQU 0x40011490\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT5\r
+CYREG_B1_P2_U1_PLD_IT5 EQU 0x40011494\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT6\r
+CYREG_B1_P2_U1_PLD_IT6 EQU 0x40011498\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT7\r
+CYREG_B1_P2_U1_PLD_IT7 EQU 0x4001149c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT8\r
+CYREG_B1_P2_U1_PLD_IT8 EQU 0x400114a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT9\r
+CYREG_B1_P2_U1_PLD_IT9 EQU 0x400114a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT10\r
+CYREG_B1_P2_U1_PLD_IT10 EQU 0x400114a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT11\r
+CYREG_B1_P2_U1_PLD_IT11 EQU 0x400114ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT0\r
+CYREG_B1_P2_U1_PLD_ORT0 EQU 0x400114b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT1\r
+CYREG_B1_P2_U1_PLD_ORT1 EQU 0x400114b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT2\r
+CYREG_B1_P2_U1_PLD_ORT2 EQU 0x400114b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT3\r
+CYREG_B1_P2_U1_PLD_ORT3 EQU 0x400114b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_CEN_CONST\r
+CYREG_B1_P2_U1_MC_CFG_CEN_CONST EQU 0x400114b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_XORFB\r
+CYREG_B1_P2_U1_MC_CFG_XORFB EQU 0x400114ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_SET_RESET\r
+CYREG_B1_P2_U1_MC_CFG_SET_RESET EQU 0x400114bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_BYPASS\r
+CYREG_B1_P2_U1_MC_CFG_BYPASS EQU 0x400114be\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG0\r
+CYREG_B1_P2_U1_CFG0 EQU 0x400114c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG1\r
+CYREG_B1_P2_U1_CFG1 EQU 0x400114c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG2\r
+CYREG_B1_P2_U1_CFG2 EQU 0x400114c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG3\r
+CYREG_B1_P2_U1_CFG3 EQU 0x400114c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG4\r
+CYREG_B1_P2_U1_CFG4 EQU 0x400114c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG5\r
+CYREG_B1_P2_U1_CFG5 EQU 0x400114c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG6\r
+CYREG_B1_P2_U1_CFG6 EQU 0x400114c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG7\r
+CYREG_B1_P2_U1_CFG7 EQU 0x400114c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG8\r
+CYREG_B1_P2_U1_CFG8 EQU 0x400114c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG9\r
+CYREG_B1_P2_U1_CFG9 EQU 0x400114c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG10\r
+CYREG_B1_P2_U1_CFG10 EQU 0x400114ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG11\r
+CYREG_B1_P2_U1_CFG11 EQU 0x400114cb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG12\r
+CYREG_B1_P2_U1_CFG12 EQU 0x400114cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG13\r
+CYREG_B1_P2_U1_CFG13 EQU 0x400114cd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG14\r
+CYREG_B1_P2_U1_CFG14 EQU 0x400114ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG15\r
+CYREG_B1_P2_U1_CFG15 EQU 0x400114cf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG16\r
+CYREG_B1_P2_U1_CFG16 EQU 0x400114d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG17\r
+CYREG_B1_P2_U1_CFG17 EQU 0x400114d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG18\r
+CYREG_B1_P2_U1_CFG18 EQU 0x400114d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG19\r
+CYREG_B1_P2_U1_CFG19 EQU 0x400114d3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG20\r
+CYREG_B1_P2_U1_CFG20 EQU 0x400114d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG21\r
+CYREG_B1_P2_U1_CFG21 EQU 0x400114d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG22\r
+CYREG_B1_P2_U1_CFG22 EQU 0x400114d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG23\r
+CYREG_B1_P2_U1_CFG23 EQU 0x400114d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG24\r
+CYREG_B1_P2_U1_CFG24 EQU 0x400114d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG25\r
+CYREG_B1_P2_U1_CFG25 EQU 0x400114d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG26\r
+CYREG_B1_P2_U1_CFG26 EQU 0x400114da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG27\r
+CYREG_B1_P2_U1_CFG27 EQU 0x400114db\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG28\r
+CYREG_B1_P2_U1_CFG28 EQU 0x400114dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG29\r
+CYREG_B1_P2_U1_CFG29 EQU 0x400114dd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG30\r
+CYREG_B1_P2_U1_CFG30 EQU 0x400114de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_CFG31\r
+CYREG_B1_P2_U1_CFG31 EQU 0x400114df\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG0\r
+CYREG_B1_P2_U1_DCFG0 EQU 0x400114e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG1\r
+CYREG_B1_P2_U1_DCFG1 EQU 0x400114e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG2\r
+CYREG_B1_P2_U1_DCFG2 EQU 0x400114e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG3\r
+CYREG_B1_P2_U1_DCFG3 EQU 0x400114e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG4\r
+CYREG_B1_P2_U1_DCFG4 EQU 0x400114e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG5\r
+CYREG_B1_P2_U1_DCFG5 EQU 0x400114ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG6\r
+CYREG_B1_P2_U1_DCFG6 EQU 0x400114ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG7\r
+CYREG_B1_P2_U1_DCFG7 EQU 0x400114ee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_BASE\r
+CYDEV_UCFG_B1_P2_ROUTE_BASE EQU 0x40011500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_SIZE\r
+CYDEV_UCFG_B1_P2_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_BASE\r
+CYDEV_UCFG_B1_P3_BASE EQU 0x40011600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_SIZE\r
+CYDEV_UCFG_B1_P3_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_BASE\r
+CYDEV_UCFG_B1_P3_U0_BASE EQU 0x40011600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_SIZE\r
+CYDEV_UCFG_B1_P3_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT0\r
+CYREG_B1_P3_U0_PLD_IT0 EQU 0x40011600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT1\r
+CYREG_B1_P3_U0_PLD_IT1 EQU 0x40011604\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT2\r
+CYREG_B1_P3_U0_PLD_IT2 EQU 0x40011608\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT3\r
+CYREG_B1_P3_U0_PLD_IT3 EQU 0x4001160c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT4\r
+CYREG_B1_P3_U0_PLD_IT4 EQU 0x40011610\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT5\r
+CYREG_B1_P3_U0_PLD_IT5 EQU 0x40011614\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT6\r
+CYREG_B1_P3_U0_PLD_IT6 EQU 0x40011618\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT7\r
+CYREG_B1_P3_U0_PLD_IT7 EQU 0x4001161c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT8\r
+CYREG_B1_P3_U0_PLD_IT8 EQU 0x40011620\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT9\r
+CYREG_B1_P3_U0_PLD_IT9 EQU 0x40011624\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT10\r
+CYREG_B1_P3_U0_PLD_IT10 EQU 0x40011628\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT11\r
+CYREG_B1_P3_U0_PLD_IT11 EQU 0x4001162c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT0\r
+CYREG_B1_P3_U0_PLD_ORT0 EQU 0x40011630\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT1\r
+CYREG_B1_P3_U0_PLD_ORT1 EQU 0x40011632\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT2\r
+CYREG_B1_P3_U0_PLD_ORT2 EQU 0x40011634\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT3\r
+CYREG_B1_P3_U0_PLD_ORT3 EQU 0x40011636\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_CEN_CONST\r
+CYREG_B1_P3_U0_MC_CFG_CEN_CONST EQU 0x40011638\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_XORFB\r
+CYREG_B1_P3_U0_MC_CFG_XORFB EQU 0x4001163a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_SET_RESET\r
+CYREG_B1_P3_U0_MC_CFG_SET_RESET EQU 0x4001163c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_BYPASS\r
+CYREG_B1_P3_U0_MC_CFG_BYPASS EQU 0x4001163e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG0\r
+CYREG_B1_P3_U0_CFG0 EQU 0x40011640\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG1\r
+CYREG_B1_P3_U0_CFG1 EQU 0x40011641\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG2\r
+CYREG_B1_P3_U0_CFG2 EQU 0x40011642\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG3\r
+CYREG_B1_P3_U0_CFG3 EQU 0x40011643\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG4\r
+CYREG_B1_P3_U0_CFG4 EQU 0x40011644\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG5\r
+CYREG_B1_P3_U0_CFG5 EQU 0x40011645\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG6\r
+CYREG_B1_P3_U0_CFG6 EQU 0x40011646\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG7\r
+CYREG_B1_P3_U0_CFG7 EQU 0x40011647\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG8\r
+CYREG_B1_P3_U0_CFG8 EQU 0x40011648\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG9\r
+CYREG_B1_P3_U0_CFG9 EQU 0x40011649\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG10\r
+CYREG_B1_P3_U0_CFG10 EQU 0x4001164a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG11\r
+CYREG_B1_P3_U0_CFG11 EQU 0x4001164b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG12\r
+CYREG_B1_P3_U0_CFG12 EQU 0x4001164c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG13\r
+CYREG_B1_P3_U0_CFG13 EQU 0x4001164d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG14\r
+CYREG_B1_P3_U0_CFG14 EQU 0x4001164e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG15\r
+CYREG_B1_P3_U0_CFG15 EQU 0x4001164f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG16\r
+CYREG_B1_P3_U0_CFG16 EQU 0x40011650\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG17\r
+CYREG_B1_P3_U0_CFG17 EQU 0x40011651\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG18\r
+CYREG_B1_P3_U0_CFG18 EQU 0x40011652\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG19\r
+CYREG_B1_P3_U0_CFG19 EQU 0x40011653\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG20\r
+CYREG_B1_P3_U0_CFG20 EQU 0x40011654\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG21\r
+CYREG_B1_P3_U0_CFG21 EQU 0x40011655\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG22\r
+CYREG_B1_P3_U0_CFG22 EQU 0x40011656\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG23\r
+CYREG_B1_P3_U0_CFG23 EQU 0x40011657\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG24\r
+CYREG_B1_P3_U0_CFG24 EQU 0x40011658\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG25\r
+CYREG_B1_P3_U0_CFG25 EQU 0x40011659\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG26\r
+CYREG_B1_P3_U0_CFG26 EQU 0x4001165a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG27\r
+CYREG_B1_P3_U0_CFG27 EQU 0x4001165b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG28\r
+CYREG_B1_P3_U0_CFG28 EQU 0x4001165c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG29\r
+CYREG_B1_P3_U0_CFG29 EQU 0x4001165d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG30\r
+CYREG_B1_P3_U0_CFG30 EQU 0x4001165e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_CFG31\r
+CYREG_B1_P3_U0_CFG31 EQU 0x4001165f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG0\r
+CYREG_B1_P3_U0_DCFG0 EQU 0x40011660\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG1\r
+CYREG_B1_P3_U0_DCFG1 EQU 0x40011662\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG2\r
+CYREG_B1_P3_U0_DCFG2 EQU 0x40011664\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG3\r
+CYREG_B1_P3_U0_DCFG3 EQU 0x40011666\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG4\r
+CYREG_B1_P3_U0_DCFG4 EQU 0x40011668\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG5\r
+CYREG_B1_P3_U0_DCFG5 EQU 0x4001166a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG6\r
+CYREG_B1_P3_U0_DCFG6 EQU 0x4001166c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG7\r
+CYREG_B1_P3_U0_DCFG7 EQU 0x4001166e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_BASE\r
+CYDEV_UCFG_B1_P3_U1_BASE EQU 0x40011680\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_SIZE\r
+CYDEV_UCFG_B1_P3_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT0\r
+CYREG_B1_P3_U1_PLD_IT0 EQU 0x40011680\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT1\r
+CYREG_B1_P3_U1_PLD_IT1 EQU 0x40011684\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT2\r
+CYREG_B1_P3_U1_PLD_IT2 EQU 0x40011688\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT3\r
+CYREG_B1_P3_U1_PLD_IT3 EQU 0x4001168c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT4\r
+CYREG_B1_P3_U1_PLD_IT4 EQU 0x40011690\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT5\r
+CYREG_B1_P3_U1_PLD_IT5 EQU 0x40011694\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT6\r
+CYREG_B1_P3_U1_PLD_IT6 EQU 0x40011698\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT7\r
+CYREG_B1_P3_U1_PLD_IT7 EQU 0x4001169c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT8\r
+CYREG_B1_P3_U1_PLD_IT8 EQU 0x400116a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT9\r
+CYREG_B1_P3_U1_PLD_IT9 EQU 0x400116a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT10\r
+CYREG_B1_P3_U1_PLD_IT10 EQU 0x400116a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT11\r
+CYREG_B1_P3_U1_PLD_IT11 EQU 0x400116ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT0\r
+CYREG_B1_P3_U1_PLD_ORT0 EQU 0x400116b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT1\r
+CYREG_B1_P3_U1_PLD_ORT1 EQU 0x400116b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT2\r
+CYREG_B1_P3_U1_PLD_ORT2 EQU 0x400116b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT3\r
+CYREG_B1_P3_U1_PLD_ORT3 EQU 0x400116b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_CEN_CONST\r
+CYREG_B1_P3_U1_MC_CFG_CEN_CONST EQU 0x400116b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_XORFB\r
+CYREG_B1_P3_U1_MC_CFG_XORFB EQU 0x400116ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_SET_RESET\r
+CYREG_B1_P3_U1_MC_CFG_SET_RESET EQU 0x400116bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_BYPASS\r
+CYREG_B1_P3_U1_MC_CFG_BYPASS EQU 0x400116be\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG0\r
+CYREG_B1_P3_U1_CFG0 EQU 0x400116c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG1\r
+CYREG_B1_P3_U1_CFG1 EQU 0x400116c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG2\r
+CYREG_B1_P3_U1_CFG2 EQU 0x400116c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG3\r
+CYREG_B1_P3_U1_CFG3 EQU 0x400116c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG4\r
+CYREG_B1_P3_U1_CFG4 EQU 0x400116c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG5\r
+CYREG_B1_P3_U1_CFG5 EQU 0x400116c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG6\r
+CYREG_B1_P3_U1_CFG6 EQU 0x400116c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG7\r
+CYREG_B1_P3_U1_CFG7 EQU 0x400116c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG8\r
+CYREG_B1_P3_U1_CFG8 EQU 0x400116c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG9\r
+CYREG_B1_P3_U1_CFG9 EQU 0x400116c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG10\r
+CYREG_B1_P3_U1_CFG10 EQU 0x400116ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG11\r
+CYREG_B1_P3_U1_CFG11 EQU 0x400116cb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG12\r
+CYREG_B1_P3_U1_CFG12 EQU 0x400116cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG13\r
+CYREG_B1_P3_U1_CFG13 EQU 0x400116cd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG14\r
+CYREG_B1_P3_U1_CFG14 EQU 0x400116ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG15\r
+CYREG_B1_P3_U1_CFG15 EQU 0x400116cf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG16\r
+CYREG_B1_P3_U1_CFG16 EQU 0x400116d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG17\r
+CYREG_B1_P3_U1_CFG17 EQU 0x400116d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG18\r
+CYREG_B1_P3_U1_CFG18 EQU 0x400116d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG19\r
+CYREG_B1_P3_U1_CFG19 EQU 0x400116d3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG20\r
+CYREG_B1_P3_U1_CFG20 EQU 0x400116d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG21\r
+CYREG_B1_P3_U1_CFG21 EQU 0x400116d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG22\r
+CYREG_B1_P3_U1_CFG22 EQU 0x400116d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG23\r
+CYREG_B1_P3_U1_CFG23 EQU 0x400116d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG24\r
+CYREG_B1_P3_U1_CFG24 EQU 0x400116d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG25\r
+CYREG_B1_P3_U1_CFG25 EQU 0x400116d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG26\r
+CYREG_B1_P3_U1_CFG26 EQU 0x400116da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG27\r
+CYREG_B1_P3_U1_CFG27 EQU 0x400116db\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG28\r
+CYREG_B1_P3_U1_CFG28 EQU 0x400116dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG29\r
+CYREG_B1_P3_U1_CFG29 EQU 0x400116dd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG30\r
+CYREG_B1_P3_U1_CFG30 EQU 0x400116de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_CFG31\r
+CYREG_B1_P3_U1_CFG31 EQU 0x400116df\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG0\r
+CYREG_B1_P3_U1_DCFG0 EQU 0x400116e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG1\r
+CYREG_B1_P3_U1_DCFG1 EQU 0x400116e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG2\r
+CYREG_B1_P3_U1_DCFG2 EQU 0x400116e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG3\r
+CYREG_B1_P3_U1_DCFG3 EQU 0x400116e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG4\r
+CYREG_B1_P3_U1_DCFG4 EQU 0x400116e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG5\r
+CYREG_B1_P3_U1_DCFG5 EQU 0x400116ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG6\r
+CYREG_B1_P3_U1_DCFG6 EQU 0x400116ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG7\r
+CYREG_B1_P3_U1_DCFG7 EQU 0x400116ee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_BASE\r
+CYDEV_UCFG_B1_P3_ROUTE_BASE EQU 0x40011700\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_SIZE\r
+CYDEV_UCFG_B1_P3_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_BASE\r
+CYDEV_UCFG_B1_P4_BASE EQU 0x40011800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_SIZE\r
+CYDEV_UCFG_B1_P4_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_BASE\r
+CYDEV_UCFG_B1_P4_U0_BASE EQU 0x40011800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_SIZE\r
+CYDEV_UCFG_B1_P4_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT0\r
+CYREG_B1_P4_U0_PLD_IT0 EQU 0x40011800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT1\r
+CYREG_B1_P4_U0_PLD_IT1 EQU 0x40011804\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT2\r
+CYREG_B1_P4_U0_PLD_IT2 EQU 0x40011808\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT3\r
+CYREG_B1_P4_U0_PLD_IT3 EQU 0x4001180c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT4\r
+CYREG_B1_P4_U0_PLD_IT4 EQU 0x40011810\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT5\r
+CYREG_B1_P4_U0_PLD_IT5 EQU 0x40011814\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT6\r
+CYREG_B1_P4_U0_PLD_IT6 EQU 0x40011818\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT7\r
+CYREG_B1_P4_U0_PLD_IT7 EQU 0x4001181c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT8\r
+CYREG_B1_P4_U0_PLD_IT8 EQU 0x40011820\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT9\r
+CYREG_B1_P4_U0_PLD_IT9 EQU 0x40011824\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT10\r
+CYREG_B1_P4_U0_PLD_IT10 EQU 0x40011828\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT11\r
+CYREG_B1_P4_U0_PLD_IT11 EQU 0x4001182c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT0\r
+CYREG_B1_P4_U0_PLD_ORT0 EQU 0x40011830\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT1\r
+CYREG_B1_P4_U0_PLD_ORT1 EQU 0x40011832\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT2\r
+CYREG_B1_P4_U0_PLD_ORT2 EQU 0x40011834\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT3\r
+CYREG_B1_P4_U0_PLD_ORT3 EQU 0x40011836\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_CEN_CONST\r
+CYREG_B1_P4_U0_MC_CFG_CEN_CONST EQU 0x40011838\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_XORFB\r
+CYREG_B1_P4_U0_MC_CFG_XORFB EQU 0x4001183a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_SET_RESET\r
+CYREG_B1_P4_U0_MC_CFG_SET_RESET EQU 0x4001183c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_BYPASS\r
+CYREG_B1_P4_U0_MC_CFG_BYPASS EQU 0x4001183e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG0\r
+CYREG_B1_P4_U0_CFG0 EQU 0x40011840\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG1\r
+CYREG_B1_P4_U0_CFG1 EQU 0x40011841\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG2\r
+CYREG_B1_P4_U0_CFG2 EQU 0x40011842\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG3\r
+CYREG_B1_P4_U0_CFG3 EQU 0x40011843\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG4\r
+CYREG_B1_P4_U0_CFG4 EQU 0x40011844\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG5\r
+CYREG_B1_P4_U0_CFG5 EQU 0x40011845\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG6\r
+CYREG_B1_P4_U0_CFG6 EQU 0x40011846\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG7\r
+CYREG_B1_P4_U0_CFG7 EQU 0x40011847\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG8\r
+CYREG_B1_P4_U0_CFG8 EQU 0x40011848\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG9\r
+CYREG_B1_P4_U0_CFG9 EQU 0x40011849\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG10\r
+CYREG_B1_P4_U0_CFG10 EQU 0x4001184a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG11\r
+CYREG_B1_P4_U0_CFG11 EQU 0x4001184b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG12\r
+CYREG_B1_P4_U0_CFG12 EQU 0x4001184c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG13\r
+CYREG_B1_P4_U0_CFG13 EQU 0x4001184d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG14\r
+CYREG_B1_P4_U0_CFG14 EQU 0x4001184e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG15\r
+CYREG_B1_P4_U0_CFG15 EQU 0x4001184f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG16\r
+CYREG_B1_P4_U0_CFG16 EQU 0x40011850\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG17\r
+CYREG_B1_P4_U0_CFG17 EQU 0x40011851\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG18\r
+CYREG_B1_P4_U0_CFG18 EQU 0x40011852\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG19\r
+CYREG_B1_P4_U0_CFG19 EQU 0x40011853\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG20\r
+CYREG_B1_P4_U0_CFG20 EQU 0x40011854\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG21\r
+CYREG_B1_P4_U0_CFG21 EQU 0x40011855\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG22\r
+CYREG_B1_P4_U0_CFG22 EQU 0x40011856\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG23\r
+CYREG_B1_P4_U0_CFG23 EQU 0x40011857\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG24\r
+CYREG_B1_P4_U0_CFG24 EQU 0x40011858\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG25\r
+CYREG_B1_P4_U0_CFG25 EQU 0x40011859\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG26\r
+CYREG_B1_P4_U0_CFG26 EQU 0x4001185a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG27\r
+CYREG_B1_P4_U0_CFG27 EQU 0x4001185b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG28\r
+CYREG_B1_P4_U0_CFG28 EQU 0x4001185c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG29\r
+CYREG_B1_P4_U0_CFG29 EQU 0x4001185d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG30\r
+CYREG_B1_P4_U0_CFG30 EQU 0x4001185e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_CFG31\r
+CYREG_B1_P4_U0_CFG31 EQU 0x4001185f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG0\r
+CYREG_B1_P4_U0_DCFG0 EQU 0x40011860\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG1\r
+CYREG_B1_P4_U0_DCFG1 EQU 0x40011862\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG2\r
+CYREG_B1_P4_U0_DCFG2 EQU 0x40011864\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG3\r
+CYREG_B1_P4_U0_DCFG3 EQU 0x40011866\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG4\r
+CYREG_B1_P4_U0_DCFG4 EQU 0x40011868\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG5\r
+CYREG_B1_P4_U0_DCFG5 EQU 0x4001186a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG6\r
+CYREG_B1_P4_U0_DCFG6 EQU 0x4001186c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG7\r
+CYREG_B1_P4_U0_DCFG7 EQU 0x4001186e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_BASE\r
+CYDEV_UCFG_B1_P4_U1_BASE EQU 0x40011880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_SIZE\r
+CYDEV_UCFG_B1_P4_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT0\r
+CYREG_B1_P4_U1_PLD_IT0 EQU 0x40011880\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT1\r
+CYREG_B1_P4_U1_PLD_IT1 EQU 0x40011884\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT2\r
+CYREG_B1_P4_U1_PLD_IT2 EQU 0x40011888\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT3\r
+CYREG_B1_P4_U1_PLD_IT3 EQU 0x4001188c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT4\r
+CYREG_B1_P4_U1_PLD_IT4 EQU 0x40011890\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT5\r
+CYREG_B1_P4_U1_PLD_IT5 EQU 0x40011894\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT6\r
+CYREG_B1_P4_U1_PLD_IT6 EQU 0x40011898\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT7\r
+CYREG_B1_P4_U1_PLD_IT7 EQU 0x4001189c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT8\r
+CYREG_B1_P4_U1_PLD_IT8 EQU 0x400118a0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT9\r
+CYREG_B1_P4_U1_PLD_IT9 EQU 0x400118a4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT10\r
+CYREG_B1_P4_U1_PLD_IT10 EQU 0x400118a8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT11\r
+CYREG_B1_P4_U1_PLD_IT11 EQU 0x400118ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT0\r
+CYREG_B1_P4_U1_PLD_ORT0 EQU 0x400118b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT1\r
+CYREG_B1_P4_U1_PLD_ORT1 EQU 0x400118b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT2\r
+CYREG_B1_P4_U1_PLD_ORT2 EQU 0x400118b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT3\r
+CYREG_B1_P4_U1_PLD_ORT3 EQU 0x400118b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_CEN_CONST\r
+CYREG_B1_P4_U1_MC_CFG_CEN_CONST EQU 0x400118b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_XORFB\r
+CYREG_B1_P4_U1_MC_CFG_XORFB EQU 0x400118ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_SET_RESET\r
+CYREG_B1_P4_U1_MC_CFG_SET_RESET EQU 0x400118bc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_BYPASS\r
+CYREG_B1_P4_U1_MC_CFG_BYPASS EQU 0x400118be\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG0\r
+CYREG_B1_P4_U1_CFG0 EQU 0x400118c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG1\r
+CYREG_B1_P4_U1_CFG1 EQU 0x400118c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG2\r
+CYREG_B1_P4_U1_CFG2 EQU 0x400118c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG3\r
+CYREG_B1_P4_U1_CFG3 EQU 0x400118c3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG4\r
+CYREG_B1_P4_U1_CFG4 EQU 0x400118c4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG5\r
+CYREG_B1_P4_U1_CFG5 EQU 0x400118c5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG6\r
+CYREG_B1_P4_U1_CFG6 EQU 0x400118c6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG7\r
+CYREG_B1_P4_U1_CFG7 EQU 0x400118c7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG8\r
+CYREG_B1_P4_U1_CFG8 EQU 0x400118c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG9\r
+CYREG_B1_P4_U1_CFG9 EQU 0x400118c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG10\r
+CYREG_B1_P4_U1_CFG10 EQU 0x400118ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG11\r
+CYREG_B1_P4_U1_CFG11 EQU 0x400118cb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG12\r
+CYREG_B1_P4_U1_CFG12 EQU 0x400118cc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG13\r
+CYREG_B1_P4_U1_CFG13 EQU 0x400118cd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG14\r
+CYREG_B1_P4_U1_CFG14 EQU 0x400118ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG15\r
+CYREG_B1_P4_U1_CFG15 EQU 0x400118cf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG16\r
+CYREG_B1_P4_U1_CFG16 EQU 0x400118d0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG17\r
+CYREG_B1_P4_U1_CFG17 EQU 0x400118d1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG18\r
+CYREG_B1_P4_U1_CFG18 EQU 0x400118d2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG19\r
+CYREG_B1_P4_U1_CFG19 EQU 0x400118d3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG20\r
+CYREG_B1_P4_U1_CFG20 EQU 0x400118d4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG21\r
+CYREG_B1_P4_U1_CFG21 EQU 0x400118d5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG22\r
+CYREG_B1_P4_U1_CFG22 EQU 0x400118d6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG23\r
+CYREG_B1_P4_U1_CFG23 EQU 0x400118d7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG24\r
+CYREG_B1_P4_U1_CFG24 EQU 0x400118d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG25\r
+CYREG_B1_P4_U1_CFG25 EQU 0x400118d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG26\r
+CYREG_B1_P4_U1_CFG26 EQU 0x400118da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG27\r
+CYREG_B1_P4_U1_CFG27 EQU 0x400118db\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG28\r
+CYREG_B1_P4_U1_CFG28 EQU 0x400118dc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG29\r
+CYREG_B1_P4_U1_CFG29 EQU 0x400118dd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG30\r
+CYREG_B1_P4_U1_CFG30 EQU 0x400118de\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_CFG31\r
+CYREG_B1_P4_U1_CFG31 EQU 0x400118df\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG0\r
+CYREG_B1_P4_U1_DCFG0 EQU 0x400118e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG1\r
+CYREG_B1_P4_U1_DCFG1 EQU 0x400118e2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG2\r
+CYREG_B1_P4_U1_DCFG2 EQU 0x400118e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG3\r
+CYREG_B1_P4_U1_DCFG3 EQU 0x400118e6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG4\r
+CYREG_B1_P4_U1_DCFG4 EQU 0x400118e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG5\r
+CYREG_B1_P4_U1_DCFG5 EQU 0x400118ea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG6\r
+CYREG_B1_P4_U1_DCFG6 EQU 0x400118ec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG7\r
+CYREG_B1_P4_U1_DCFG7 EQU 0x400118ee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_BASE\r
+CYDEV_UCFG_B1_P4_ROUTE_BASE EQU 0x40011900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_SIZE\r
+CYDEV_UCFG_B1_P4_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_BASE\r
+CYDEV_UCFG_B1_P5_BASE EQU 0x40011a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_SIZE\r
+CYDEV_UCFG_B1_P5_SIZE EQU 0x000001ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_BASE\r
+CYDEV_UCFG_B1_P5_U0_BASE EQU 0x40011a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_SIZE\r
+CYDEV_UCFG_B1_P5_U0_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT0\r
+CYREG_B1_P5_U0_PLD_IT0 EQU 0x40011a00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT1\r
+CYREG_B1_P5_U0_PLD_IT1 EQU 0x40011a04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT2\r
+CYREG_B1_P5_U0_PLD_IT2 EQU 0x40011a08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT3\r
+CYREG_B1_P5_U0_PLD_IT3 EQU 0x40011a0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT4\r
+CYREG_B1_P5_U0_PLD_IT4 EQU 0x40011a10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT5\r
+CYREG_B1_P5_U0_PLD_IT5 EQU 0x40011a14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT6\r
+CYREG_B1_P5_U0_PLD_IT6 EQU 0x40011a18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT7\r
+CYREG_B1_P5_U0_PLD_IT7 EQU 0x40011a1c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT8\r
+CYREG_B1_P5_U0_PLD_IT8 EQU 0x40011a20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT9\r
+CYREG_B1_P5_U0_PLD_IT9 EQU 0x40011a24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT10\r
+CYREG_B1_P5_U0_PLD_IT10 EQU 0x40011a28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT11\r
+CYREG_B1_P5_U0_PLD_IT11 EQU 0x40011a2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT0\r
+CYREG_B1_P5_U0_PLD_ORT0 EQU 0x40011a30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT1\r
+CYREG_B1_P5_U0_PLD_ORT1 EQU 0x40011a32\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT2\r
+CYREG_B1_P5_U0_PLD_ORT2 EQU 0x40011a34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT3\r
+CYREG_B1_P5_U0_PLD_ORT3 EQU 0x40011a36\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_CEN_CONST\r
+CYREG_B1_P5_U0_MC_CFG_CEN_CONST EQU 0x40011a38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_XORFB\r
+CYREG_B1_P5_U0_MC_CFG_XORFB EQU 0x40011a3a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_SET_RESET\r
+CYREG_B1_P5_U0_MC_CFG_SET_RESET EQU 0x40011a3c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_BYPASS\r
+CYREG_B1_P5_U0_MC_CFG_BYPASS EQU 0x40011a3e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG0\r
+CYREG_B1_P5_U0_CFG0 EQU 0x40011a40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG1\r
+CYREG_B1_P5_U0_CFG1 EQU 0x40011a41\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG2\r
+CYREG_B1_P5_U0_CFG2 EQU 0x40011a42\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG3\r
+CYREG_B1_P5_U0_CFG3 EQU 0x40011a43\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG4\r
+CYREG_B1_P5_U0_CFG4 EQU 0x40011a44\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG5\r
+CYREG_B1_P5_U0_CFG5 EQU 0x40011a45\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG6\r
+CYREG_B1_P5_U0_CFG6 EQU 0x40011a46\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG7\r
+CYREG_B1_P5_U0_CFG7 EQU 0x40011a47\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG8\r
+CYREG_B1_P5_U0_CFG8 EQU 0x40011a48\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG9\r
+CYREG_B1_P5_U0_CFG9 EQU 0x40011a49\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG10\r
+CYREG_B1_P5_U0_CFG10 EQU 0x40011a4a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG11\r
+CYREG_B1_P5_U0_CFG11 EQU 0x40011a4b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG12\r
+CYREG_B1_P5_U0_CFG12 EQU 0x40011a4c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG13\r
+CYREG_B1_P5_U0_CFG13 EQU 0x40011a4d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG14\r
+CYREG_B1_P5_U0_CFG14 EQU 0x40011a4e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG15\r
+CYREG_B1_P5_U0_CFG15 EQU 0x40011a4f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG16\r
+CYREG_B1_P5_U0_CFG16 EQU 0x40011a50\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG17\r
+CYREG_B1_P5_U0_CFG17 EQU 0x40011a51\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG18\r
+CYREG_B1_P5_U0_CFG18 EQU 0x40011a52\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG19\r
+CYREG_B1_P5_U0_CFG19 EQU 0x40011a53\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG20\r
+CYREG_B1_P5_U0_CFG20 EQU 0x40011a54\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG21\r
+CYREG_B1_P5_U0_CFG21 EQU 0x40011a55\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG22\r
+CYREG_B1_P5_U0_CFG22 EQU 0x40011a56\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG23\r
+CYREG_B1_P5_U0_CFG23 EQU 0x40011a57\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG24\r
+CYREG_B1_P5_U0_CFG24 EQU 0x40011a58\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG25\r
+CYREG_B1_P5_U0_CFG25 EQU 0x40011a59\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG26\r
+CYREG_B1_P5_U0_CFG26 EQU 0x40011a5a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG27\r
+CYREG_B1_P5_U0_CFG27 EQU 0x40011a5b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG28\r
+CYREG_B1_P5_U0_CFG28 EQU 0x40011a5c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG29\r
+CYREG_B1_P5_U0_CFG29 EQU 0x40011a5d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG30\r
+CYREG_B1_P5_U0_CFG30 EQU 0x40011a5e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_CFG31\r
+CYREG_B1_P5_U0_CFG31 EQU 0x40011a5f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG0\r
+CYREG_B1_P5_U0_DCFG0 EQU 0x40011a60\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG1\r
+CYREG_B1_P5_U0_DCFG1 EQU 0x40011a62\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG2\r
+CYREG_B1_P5_U0_DCFG2 EQU 0x40011a64\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG3\r
+CYREG_B1_P5_U0_DCFG3 EQU 0x40011a66\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG4\r
+CYREG_B1_P5_U0_DCFG4 EQU 0x40011a68\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG5\r
+CYREG_B1_P5_U0_DCFG5 EQU 0x40011a6a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG6\r
+CYREG_B1_P5_U0_DCFG6 EQU 0x40011a6c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG7\r
+CYREG_B1_P5_U0_DCFG7 EQU 0x40011a6e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_BASE\r
+CYDEV_UCFG_B1_P5_U1_BASE EQU 0x40011a80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_SIZE\r
+CYDEV_UCFG_B1_P5_U1_SIZE EQU 0x00000070\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT0\r
+CYREG_B1_P5_U1_PLD_IT0 EQU 0x40011a80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT1\r
+CYREG_B1_P5_U1_PLD_IT1 EQU 0x40011a84\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT2\r
+CYREG_B1_P5_U1_PLD_IT2 EQU 0x40011a88\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT3\r
+CYREG_B1_P5_U1_PLD_IT3 EQU 0x40011a8c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT4\r
+CYREG_B1_P5_U1_PLD_IT4 EQU 0x40011a90\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT5\r
+CYREG_B1_P5_U1_PLD_IT5 EQU 0x40011a94\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT6\r
+CYREG_B1_P5_U1_PLD_IT6 EQU 0x40011a98\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT7\r
+CYREG_B1_P5_U1_PLD_IT7 EQU 0x40011a9c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT8\r
+CYREG_B1_P5_U1_PLD_IT8 EQU 0x40011aa0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT9\r
+CYREG_B1_P5_U1_PLD_IT9 EQU 0x40011aa4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT10\r
+CYREG_B1_P5_U1_PLD_IT10 EQU 0x40011aa8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT11\r
+CYREG_B1_P5_U1_PLD_IT11 EQU 0x40011aac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT0\r
+CYREG_B1_P5_U1_PLD_ORT0 EQU 0x40011ab0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT1\r
+CYREG_B1_P5_U1_PLD_ORT1 EQU 0x40011ab2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT2\r
+CYREG_B1_P5_U1_PLD_ORT2 EQU 0x40011ab4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT3\r
+CYREG_B1_P5_U1_PLD_ORT3 EQU 0x40011ab6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_CEN_CONST\r
+CYREG_B1_P5_U1_MC_CFG_CEN_CONST EQU 0x40011ab8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_XORFB\r
+CYREG_B1_P5_U1_MC_CFG_XORFB EQU 0x40011aba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_SET_RESET\r
+CYREG_B1_P5_U1_MC_CFG_SET_RESET EQU 0x40011abc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_BYPASS\r
+CYREG_B1_P5_U1_MC_CFG_BYPASS EQU 0x40011abe\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG0\r
+CYREG_B1_P5_U1_CFG0 EQU 0x40011ac0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG1\r
+CYREG_B1_P5_U1_CFG1 EQU 0x40011ac1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG2\r
+CYREG_B1_P5_U1_CFG2 EQU 0x40011ac2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG3\r
+CYREG_B1_P5_U1_CFG3 EQU 0x40011ac3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG4\r
+CYREG_B1_P5_U1_CFG4 EQU 0x40011ac4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG5\r
+CYREG_B1_P5_U1_CFG5 EQU 0x40011ac5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG6\r
+CYREG_B1_P5_U1_CFG6 EQU 0x40011ac6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG7\r
+CYREG_B1_P5_U1_CFG7 EQU 0x40011ac7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG8\r
+CYREG_B1_P5_U1_CFG8 EQU 0x40011ac8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG9\r
+CYREG_B1_P5_U1_CFG9 EQU 0x40011ac9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG10\r
+CYREG_B1_P5_U1_CFG10 EQU 0x40011aca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG11\r
+CYREG_B1_P5_U1_CFG11 EQU 0x40011acb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG12\r
+CYREG_B1_P5_U1_CFG12 EQU 0x40011acc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG13\r
+CYREG_B1_P5_U1_CFG13 EQU 0x40011acd\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG14\r
+CYREG_B1_P5_U1_CFG14 EQU 0x40011ace\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG15\r
+CYREG_B1_P5_U1_CFG15 EQU 0x40011acf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG16\r
+CYREG_B1_P5_U1_CFG16 EQU 0x40011ad0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG17\r
+CYREG_B1_P5_U1_CFG17 EQU 0x40011ad1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG18\r
+CYREG_B1_P5_U1_CFG18 EQU 0x40011ad2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG19\r
+CYREG_B1_P5_U1_CFG19 EQU 0x40011ad3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG20\r
+CYREG_B1_P5_U1_CFG20 EQU 0x40011ad4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG21\r
+CYREG_B1_P5_U1_CFG21 EQU 0x40011ad5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG22\r
+CYREG_B1_P5_U1_CFG22 EQU 0x40011ad6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG23\r
+CYREG_B1_P5_U1_CFG23 EQU 0x40011ad7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG24\r
+CYREG_B1_P5_U1_CFG24 EQU 0x40011ad8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG25\r
+CYREG_B1_P5_U1_CFG25 EQU 0x40011ad9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG26\r
+CYREG_B1_P5_U1_CFG26 EQU 0x40011ada\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG27\r
+CYREG_B1_P5_U1_CFG27 EQU 0x40011adb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG28\r
+CYREG_B1_P5_U1_CFG28 EQU 0x40011adc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG29\r
+CYREG_B1_P5_U1_CFG29 EQU 0x40011add\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG30\r
+CYREG_B1_P5_U1_CFG30 EQU 0x40011ade\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_CFG31\r
+CYREG_B1_P5_U1_CFG31 EQU 0x40011adf\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG0\r
+CYREG_B1_P5_U1_DCFG0 EQU 0x40011ae0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG1\r
+CYREG_B1_P5_U1_DCFG1 EQU 0x40011ae2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG2\r
+CYREG_B1_P5_U1_DCFG2 EQU 0x40011ae4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG3\r
+CYREG_B1_P5_U1_DCFG3 EQU 0x40011ae6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG4\r
+CYREG_B1_P5_U1_DCFG4 EQU 0x40011ae8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG5\r
+CYREG_B1_P5_U1_DCFG5 EQU 0x40011aea\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG6\r
+CYREG_B1_P5_U1_DCFG6 EQU 0x40011aec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG7\r
+CYREG_B1_P5_U1_DCFG7 EQU 0x40011aee\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_BASE\r
+CYDEV_UCFG_B1_P5_ROUTE_BASE EQU 0x40011b00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_SIZE\r
+CYDEV_UCFG_B1_P5_ROUTE_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI0_BASE\r
+CYDEV_UCFG_DSI0_BASE EQU 0x40014000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI0_SIZE\r
+CYDEV_UCFG_DSI0_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI1_BASE\r
+CYDEV_UCFG_DSI1_BASE EQU 0x40014100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI1_SIZE\r
+CYDEV_UCFG_DSI1_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI2_BASE\r
+CYDEV_UCFG_DSI2_BASE EQU 0x40014200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI2_SIZE\r
+CYDEV_UCFG_DSI2_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI3_BASE\r
+CYDEV_UCFG_DSI3_BASE EQU 0x40014300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI3_SIZE\r
+CYDEV_UCFG_DSI3_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI4_BASE\r
+CYDEV_UCFG_DSI4_BASE EQU 0x40014400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI4_SIZE\r
+CYDEV_UCFG_DSI4_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI5_BASE\r
+CYDEV_UCFG_DSI5_BASE EQU 0x40014500\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI5_SIZE\r
+CYDEV_UCFG_DSI5_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI6_BASE\r
+CYDEV_UCFG_DSI6_BASE EQU 0x40014600\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI6_SIZE\r
+CYDEV_UCFG_DSI6_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI7_BASE\r
+CYDEV_UCFG_DSI7_BASE EQU 0x40014700\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI7_SIZE\r
+CYDEV_UCFG_DSI7_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI8_BASE\r
+CYDEV_UCFG_DSI8_BASE EQU 0x40014800\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI8_SIZE\r
+CYDEV_UCFG_DSI8_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI9_BASE\r
+CYDEV_UCFG_DSI9_BASE EQU 0x40014900\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI9_SIZE\r
+CYDEV_UCFG_DSI9_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI12_BASE\r
+CYDEV_UCFG_DSI12_BASE EQU 0x40014c00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI12_SIZE\r
+CYDEV_UCFG_DSI12_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI13_BASE\r
+CYDEV_UCFG_DSI13_BASE EQU 0x40014d00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_DSI13_SIZE\r
+CYDEV_UCFG_DSI13_SIZE EQU 0x000000ef\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BASE\r
+CYDEV_UCFG_BCTL0_BASE EQU 0x40015000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL0_SIZE\r
+CYDEV_UCFG_BCTL0_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL0_MDCLK_EN\r
+CYREG_BCTL0_MDCLK_EN EQU 0x40015000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL0_MBCLK_EN\r
+CYREG_BCTL0_MBCLK_EN EQU 0x40015001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL0_WAIT_CFG\r
+CYREG_BCTL0_WAIT_CFG EQU 0x40015002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL0_BANK_CTL\r
+CYREG_BCTL0_BANK_CTL EQU 0x40015003\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL0_UDB_TEST_3\r
+CYREG_BCTL0_UDB_TEST_3 EQU 0x40015007\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN0\r
+CYREG_BCTL0_DCLK_EN0 EQU 0x40015008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN0\r
+CYREG_BCTL0_BCLK_EN0 EQU 0x40015009\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN1\r
+CYREG_BCTL0_DCLK_EN1 EQU 0x4001500a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN1\r
+CYREG_BCTL0_BCLK_EN1 EQU 0x4001500b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN2\r
+CYREG_BCTL0_DCLK_EN2 EQU 0x4001500c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN2\r
+CYREG_BCTL0_BCLK_EN2 EQU 0x4001500d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN3\r
+CYREG_BCTL0_DCLK_EN3 EQU 0x4001500e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN3\r
+CYREG_BCTL0_BCLK_EN3 EQU 0x4001500f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BASE\r
+CYDEV_UCFG_BCTL1_BASE EQU 0x40015010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_UCFG_BCTL1_SIZE\r
+CYDEV_UCFG_BCTL1_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL1_MDCLK_EN\r
+CYREG_BCTL1_MDCLK_EN EQU 0x40015010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL1_MBCLK_EN\r
+CYREG_BCTL1_MBCLK_EN EQU 0x40015011\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL1_WAIT_CFG\r
+CYREG_BCTL1_WAIT_CFG EQU 0x40015012\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL1_BANK_CTL\r
+CYREG_BCTL1_BANK_CTL EQU 0x40015013\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL1_UDB_TEST_3\r
+CYREG_BCTL1_UDB_TEST_3 EQU 0x40015017\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN0\r
+CYREG_BCTL1_DCLK_EN0 EQU 0x40015018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN0\r
+CYREG_BCTL1_BCLK_EN0 EQU 0x40015019\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN1\r
+CYREG_BCTL1_DCLK_EN1 EQU 0x4001501a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN1\r
+CYREG_BCTL1_BCLK_EN1 EQU 0x4001501b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN2\r
+CYREG_BCTL1_DCLK_EN2 EQU 0x4001501c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN2\r
+CYREG_BCTL1_BCLK_EN2 EQU 0x4001501d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN3\r
+CYREG_BCTL1_DCLK_EN3 EQU 0x4001501e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN3\r
+CYREG_BCTL1_BCLK_EN3 EQU 0x4001501f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IDMUX_BASE\r
+CYDEV_IDMUX_BASE EQU 0x40015100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_IDMUX_SIZE\r
+CYDEV_IDMUX_SIZE EQU 0x00000016\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL0\r
+CYREG_IDMUX_IRQ_CTL0 EQU 0x40015100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL1\r
+CYREG_IDMUX_IRQ_CTL1 EQU 0x40015101\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL2\r
+CYREG_IDMUX_IRQ_CTL2 EQU 0x40015102\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL3\r
+CYREG_IDMUX_IRQ_CTL3 EQU 0x40015103\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL4\r
+CYREG_IDMUX_IRQ_CTL4 EQU 0x40015104\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL5\r
+CYREG_IDMUX_IRQ_CTL5 EQU 0x40015105\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL6\r
+CYREG_IDMUX_IRQ_CTL6 EQU 0x40015106\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL7\r
+CYREG_IDMUX_IRQ_CTL7 EQU 0x40015107\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL0\r
+CYREG_IDMUX_DRQ_CTL0 EQU 0x40015110\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL1\r
+CYREG_IDMUX_DRQ_CTL1 EQU 0x40015111\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL2\r
+CYREG_IDMUX_DRQ_CTL2 EQU 0x40015112\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL3\r
+CYREG_IDMUX_DRQ_CTL3 EQU 0x40015113\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL4\r
+CYREG_IDMUX_DRQ_CTL4 EQU 0x40015114\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL5\r
+CYREG_IDMUX_DRQ_CTL5 EQU 0x40015115\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CACHERAM_BASE\r
+CYDEV_CACHERAM_BASE EQU 0x40030000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CACHERAM_SIZE\r
+CYDEV_CACHERAM_SIZE EQU 0x00000400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CACHERAM_DATA_MBASE\r
+CYREG_CACHERAM_DATA_MBASE EQU 0x40030000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CACHERAM_DATA_MSIZE\r
+CYREG_CACHERAM_DATA_MSIZE EQU 0x00000400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_BASE\r
+CYDEV_SFR_BASE EQU 0x40050100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_SFR_SIZE\r
+CYDEV_SFR_SIZE EQU 0x000000fb\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIO0\r
+CYREG_SFR_GPIO0 EQU 0x40050180\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIRD0\r
+CYREG_SFR_GPIRD0 EQU 0x40050189\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIO0_SEL\r
+CYREG_SFR_GPIO0_SEL EQU 0x4005018a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIO1\r
+CYREG_SFR_GPIO1 EQU 0x40050190\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIRD1\r
+CYREG_SFR_GPIRD1 EQU 0x40050191\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIO2\r
+CYREG_SFR_GPIO2 EQU 0x40050198\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIRD2\r
+CYREG_SFR_GPIRD2 EQU 0x40050199\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIO2_SEL\r
+CYREG_SFR_GPIO2_SEL EQU 0x4005019a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIO1_SEL\r
+CYREG_SFR_GPIO1_SEL EQU 0x400501a2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIO3\r
+CYREG_SFR_GPIO3 EQU 0x400501b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIRD3\r
+CYREG_SFR_GPIRD3 EQU 0x400501b1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIO3_SEL\r
+CYREG_SFR_GPIO3_SEL EQU 0x400501b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIO4\r
+CYREG_SFR_GPIO4 EQU 0x400501c0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIRD4\r
+CYREG_SFR_GPIRD4 EQU 0x400501c1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIO4_SEL\r
+CYREG_SFR_GPIO4_SEL EQU 0x400501c2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIO5\r
+CYREG_SFR_GPIO5 EQU 0x400501c8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIRD5\r
+CYREG_SFR_GPIRD5 EQU 0x400501c9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIO5_SEL\r
+CYREG_SFR_GPIO5_SEL EQU 0x400501ca\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIO6\r
+CYREG_SFR_GPIO6 EQU 0x400501d8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIRD6\r
+CYREG_SFR_GPIRD6 EQU 0x400501d9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIO6_SEL\r
+CYREG_SFR_GPIO6_SEL EQU 0x400501da\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIO12\r
+CYREG_SFR_GPIO12 EQU 0x400501e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIRD12\r
+CYREG_SFR_GPIRD12 EQU 0x400501e9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIO12_SEL\r
+CYREG_SFR_GPIO12_SEL EQU 0x400501f2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIO15\r
+CYREG_SFR_GPIO15 EQU 0x400501f8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIRD15\r
+CYREG_SFR_GPIRD15 EQU 0x400501f9\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_SFR_GPIO15_SEL\r
+CYREG_SFR_GPIO15_SEL EQU 0x400501fa\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_BASE\r
+CYDEV_P3BA_BASE EQU 0x40050300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_P3BA_SIZE\r
+CYDEV_P3BA_SIZE EQU 0x0000002b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_Y_START\r
+CYREG_P3BA_Y_START EQU 0x40050300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_YROLL\r
+CYREG_P3BA_YROLL EQU 0x40050301\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_YCFG\r
+CYREG_P3BA_YCFG EQU 0x40050302\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_X_START1\r
+CYREG_P3BA_X_START1 EQU 0x40050303\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_X_START2\r
+CYREG_P3BA_X_START2 EQU 0x40050304\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_XROLL1\r
+CYREG_P3BA_XROLL1 EQU 0x40050305\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_XROLL2\r
+CYREG_P3BA_XROLL2 EQU 0x40050306\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_XINC\r
+CYREG_P3BA_XINC EQU 0x40050307\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_XCFG\r
+CYREG_P3BA_XCFG EQU 0x40050308\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR1\r
+CYREG_P3BA_OFFSETADDR1 EQU 0x40050309\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR2\r
+CYREG_P3BA_OFFSETADDR2 EQU 0x4005030a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR3\r
+CYREG_P3BA_OFFSETADDR3 EQU 0x4005030b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_ABSADDR1\r
+CYREG_P3BA_ABSADDR1 EQU 0x4005030c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_ABSADDR2\r
+CYREG_P3BA_ABSADDR2 EQU 0x4005030d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_ABSADDR3\r
+CYREG_P3BA_ABSADDR3 EQU 0x4005030e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_ABSADDR4\r
+CYREG_P3BA_ABSADDR4 EQU 0x4005030f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_DATCFG1\r
+CYREG_P3BA_DATCFG1 EQU 0x40050310\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_DATCFG2\r
+CYREG_P3BA_DATCFG2 EQU 0x40050311\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT1\r
+CYREG_P3BA_CMP_RSLT1 EQU 0x40050314\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT2\r
+CYREG_P3BA_CMP_RSLT2 EQU 0x40050315\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT3\r
+CYREG_P3BA_CMP_RSLT3 EQU 0x40050316\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT4\r
+CYREG_P3BA_CMP_RSLT4 EQU 0x40050317\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_DATA_REG1\r
+CYREG_P3BA_DATA_REG1 EQU 0x40050318\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_DATA_REG2\r
+CYREG_P3BA_DATA_REG2 EQU 0x40050319\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_DATA_REG3\r
+CYREG_P3BA_DATA_REG3 EQU 0x4005031a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_DATA_REG4\r
+CYREG_P3BA_DATA_REG4 EQU 0x4005031b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_EXP_DATA1\r
+CYREG_P3BA_EXP_DATA1 EQU 0x4005031c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_EXP_DATA2\r
+CYREG_P3BA_EXP_DATA2 EQU 0x4005031d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_EXP_DATA3\r
+CYREG_P3BA_EXP_DATA3 EQU 0x4005031e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_EXP_DATA4\r
+CYREG_P3BA_EXP_DATA4 EQU 0x4005031f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA1\r
+CYREG_P3BA_MSTR_HRDATA1 EQU 0x40050320\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA2\r
+CYREG_P3BA_MSTR_HRDATA2 EQU 0x40050321\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA3\r
+CYREG_P3BA_MSTR_HRDATA3 EQU 0x40050322\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA4\r
+CYREG_P3BA_MSTR_HRDATA4 EQU 0x40050323\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_BIST_EN\r
+CYREG_P3BA_BIST_EN EQU 0x40050324\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_PHUB_MASTER_SSR\r
+CYREG_P3BA_PHUB_MASTER_SSR EQU 0x40050325\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_SEQCFG1\r
+CYREG_P3BA_SEQCFG1 EQU 0x40050326\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_SEQCFG2\r
+CYREG_P3BA_SEQCFG2 EQU 0x40050327\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_Y_CURR\r
+CYREG_P3BA_Y_CURR EQU 0x40050328\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_X_CURR1\r
+CYREG_P3BA_X_CURR1 EQU 0x40050329\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_P3BA_X_CURR2\r
+CYREG_P3BA_X_CURR2 EQU 0x4005032a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PANTHER_BASE\r
+CYDEV_PANTHER_BASE EQU 0x40080000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PANTHER_SIZE\r
+CYDEV_PANTHER_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PANTHER_STCALIB_CFG\r
+CYREG_PANTHER_STCALIB_CFG EQU 0x40080000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PANTHER_WAITPIPE\r
+CYREG_PANTHER_WAITPIPE EQU 0x40080004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PANTHER_TRACE_CFG\r
+CYREG_PANTHER_TRACE_CFG EQU 0x40080008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PANTHER_DBG_CFG\r
+CYREG_PANTHER_DBG_CFG EQU 0x4008000c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PANTHER_CM3_LCKRST_STAT\r
+CYREG_PANTHER_CM3_LCKRST_STAT EQU 0x40080018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_PANTHER_DEVICE_ID\r
+CYREG_PANTHER_DEVICE_ID EQU 0x4008001c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSECC_BASE\r
+CYDEV_FLSECC_BASE EQU 0x48000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSECC_SIZE\r
+CYDEV_FLSECC_SIZE EQU 0x00008000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSECC_DATA_MBASE\r
+CYREG_FLSECC_DATA_MBASE EQU 0x48000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSECC_DATA_MSIZE\r
+CYREG_FLSECC_DATA_MSIZE EQU 0x00008000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_BASE\r
+CYDEV_FLSHID_BASE EQU 0x49000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_SIZE\r
+CYDEV_FLSHID_SIZE EQU 0x00000200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_RSVD_MBASE\r
+CYREG_FLSHID_RSVD_MBASE EQU 0x49000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_RSVD_MSIZE\r
+CYREG_FLSHID_RSVD_MSIZE EQU 0x00000080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_MDATA_MBASE\r
+CYREG_FLSHID_CUST_MDATA_MBASE EQU 0x49000080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_MDATA_MSIZE\r
+CYREG_FLSHID_CUST_MDATA_MSIZE EQU 0x00000080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_BASE\r
+CYDEV_FLSHID_CUST_TABLES_BASE EQU 0x49000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_SIZE\r
+CYDEV_FLSHID_CUST_TABLES_SIZE EQU 0x00000040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_Y_LOC\r
+CYREG_FLSHID_CUST_TABLES_Y_LOC EQU 0x49000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_X_LOC\r
+CYREG_FLSHID_CUST_TABLES_X_LOC EQU 0x49000101\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_WAFER_NUM\r
+CYREG_FLSHID_CUST_TABLES_WAFER_NUM EQU 0x49000102\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_LOT_LSB\r
+CYREG_FLSHID_CUST_TABLES_LOT_LSB EQU 0x49000103\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_LOT_MSB\r
+CYREG_FLSHID_CUST_TABLES_LOT_MSB EQU 0x49000104\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_WRK_WK\r
+CYREG_FLSHID_CUST_TABLES_WRK_WK EQU 0x49000105\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_FAB_YR\r
+CYREG_FLSHID_CUST_TABLES_FAB_YR EQU 0x49000106\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_MINOR\r
+CYREG_FLSHID_CUST_TABLES_MINOR EQU 0x49000107\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_3MHZ\r
+CYREG_FLSHID_CUST_TABLES_IMO_3MHZ EQU 0x49000108\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_6MHZ\r
+CYREG_FLSHID_CUST_TABLES_IMO_6MHZ EQU 0x49000109\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_12MHZ\r
+CYREG_FLSHID_CUST_TABLES_IMO_12MHZ EQU 0x4900010a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_24MHZ\r
+CYREG_FLSHID_CUST_TABLES_IMO_24MHZ EQU 0x4900010b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_67MHZ\r
+CYREG_FLSHID_CUST_TABLES_IMO_67MHZ EQU 0x4900010c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_80MHZ\r
+CYREG_FLSHID_CUST_TABLES_IMO_80MHZ EQU 0x4900010d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_92MHZ\r
+CYREG_FLSHID_CUST_TABLES_IMO_92MHZ EQU 0x4900010e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_USB\r
+CYREG_FLSHID_CUST_TABLES_IMO_USB EQU 0x4900010f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS\r
+CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS EQU 0x49000110\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS\r
+CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS EQU 0x49000111\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS\r
+CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS EQU 0x49000112\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS\r
+CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS EQU 0x49000113\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS\r
+CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS EQU 0x49000114\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS\r
+CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS EQU 0x49000115\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS\r
+CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS EQU 0x49000116\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS\r
+CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS EQU 0x49000117\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M1\r
+CYREG_FLSHID_CUST_TABLES_DEC_M1 EQU 0x49000118\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M2\r
+CYREG_FLSHID_CUST_TABLES_DEC_M2 EQU 0x49000119\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M3\r
+CYREG_FLSHID_CUST_TABLES_DEC_M3 EQU 0x4900011a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M4\r
+CYREG_FLSHID_CUST_TABLES_DEC_M4 EQU 0x4900011b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M5\r
+CYREG_FLSHID_CUST_TABLES_DEC_M5 EQU 0x4900011c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M6\r
+CYREG_FLSHID_CUST_TABLES_DEC_M6 EQU 0x4900011d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M7\r
+CYREG_FLSHID_CUST_TABLES_DEC_M7 EQU 0x4900011e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M8\r
+CYREG_FLSHID_CUST_TABLES_DEC_M8 EQU 0x4900011f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M1\r
+CYREG_FLSHID_CUST_TABLES_DAC0_M1 EQU 0x49000120\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M2\r
+CYREG_FLSHID_CUST_TABLES_DAC0_M2 EQU 0x49000121\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M3\r
+CYREG_FLSHID_CUST_TABLES_DAC0_M3 EQU 0x49000122\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M4\r
+CYREG_FLSHID_CUST_TABLES_DAC0_M4 EQU 0x49000123\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M5\r
+CYREG_FLSHID_CUST_TABLES_DAC0_M5 EQU 0x49000124\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M6\r
+CYREG_FLSHID_CUST_TABLES_DAC0_M6 EQU 0x49000125\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M7\r
+CYREG_FLSHID_CUST_TABLES_DAC0_M7 EQU 0x49000126\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M8\r
+CYREG_FLSHID_CUST_TABLES_DAC0_M8 EQU 0x49000127\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M1\r
+CYREG_FLSHID_CUST_TABLES_DAC2_M1 EQU 0x49000128\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M2\r
+CYREG_FLSHID_CUST_TABLES_DAC2_M2 EQU 0x49000129\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M3\r
+CYREG_FLSHID_CUST_TABLES_DAC2_M3 EQU 0x4900012a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M4\r
+CYREG_FLSHID_CUST_TABLES_DAC2_M4 EQU 0x4900012b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M5\r
+CYREG_FLSHID_CUST_TABLES_DAC2_M5 EQU 0x4900012c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M6\r
+CYREG_FLSHID_CUST_TABLES_DAC2_M6 EQU 0x4900012d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M7\r
+CYREG_FLSHID_CUST_TABLES_DAC2_M7 EQU 0x4900012e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M8\r
+CYREG_FLSHID_CUST_TABLES_DAC2_M8 EQU 0x4900012f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M1\r
+CYREG_FLSHID_CUST_TABLES_DAC1_M1 EQU 0x49000130\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M2\r
+CYREG_FLSHID_CUST_TABLES_DAC1_M2 EQU 0x49000131\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M3\r
+CYREG_FLSHID_CUST_TABLES_DAC1_M3 EQU 0x49000132\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M4\r
+CYREG_FLSHID_CUST_TABLES_DAC1_M4 EQU 0x49000133\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M5\r
+CYREG_FLSHID_CUST_TABLES_DAC1_M5 EQU 0x49000134\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M6\r
+CYREG_FLSHID_CUST_TABLES_DAC1_M6 EQU 0x49000135\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M7\r
+CYREG_FLSHID_CUST_TABLES_DAC1_M7 EQU 0x49000136\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M8\r
+CYREG_FLSHID_CUST_TABLES_DAC1_M8 EQU 0x49000137\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M1\r
+CYREG_FLSHID_CUST_TABLES_DAC3_M1 EQU 0x49000138\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M2\r
+CYREG_FLSHID_CUST_TABLES_DAC3_M2 EQU 0x49000139\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M3\r
+CYREG_FLSHID_CUST_TABLES_DAC3_M3 EQU 0x4900013a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M4\r
+CYREG_FLSHID_CUST_TABLES_DAC3_M4 EQU 0x4900013b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M5\r
+CYREG_FLSHID_CUST_TABLES_DAC3_M5 EQU 0x4900013c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M6\r
+CYREG_FLSHID_CUST_TABLES_DAC3_M6 EQU 0x4900013d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M7\r
+CYREG_FLSHID_CUST_TABLES_DAC3_M7 EQU 0x4900013e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M8\r
+CYREG_FLSHID_CUST_TABLES_DAC3_M8 EQU 0x4900013f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BASE\r
+CYDEV_FLSHID_MFG_CFG_BASE EQU 0x49000180\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_SIZE\r
+CYDEV_FLSHID_MFG_CFG_SIZE EQU 0x00000080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_IMO_TR1\r
+CYREG_FLSHID_MFG_CFG_IMO_TR1 EQU 0x49000188\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP0_TR0\r
+CYREG_FLSHID_MFG_CFG_CMP0_TR0 EQU 0x490001ac\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP1_TR0\r
+CYREG_FLSHID_MFG_CFG_CMP1_TR0 EQU 0x490001ae\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP2_TR0\r
+CYREG_FLSHID_MFG_CFG_CMP2_TR0 EQU 0x490001b0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP3_TR0\r
+CYREG_FLSHID_MFG_CFG_CMP3_TR0 EQU 0x490001b2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP0_TR1\r
+CYREG_FLSHID_MFG_CFG_CMP0_TR1 EQU 0x490001b4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP1_TR1\r
+CYREG_FLSHID_MFG_CFG_CMP1_TR1 EQU 0x490001b6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP2_TR1\r
+CYREG_FLSHID_MFG_CFG_CMP2_TR1 EQU 0x490001b8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP3_TR1\r
+CYREG_FLSHID_MFG_CFG_CMP3_TR1 EQU 0x490001ba\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM\r
+CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM EQU 0x490001ce\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EXTMEM_BASE\r
+CYDEV_EXTMEM_BASE EQU 0x60000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EXTMEM_SIZE\r
+CYDEV_EXTMEM_SIZE EQU 0x00800000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_EXTMEM_DATA_MBASE\r
+CYREG_EXTMEM_DATA_MBASE EQU 0x60000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_EXTMEM_DATA_MSIZE\r
+CYREG_EXTMEM_DATA_MSIZE EQU 0x00800000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_BASE\r
+CYDEV_ITM_BASE EQU 0xe0000000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ITM_SIZE\r
+CYDEV_ITM_SIZE EQU 0x00001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ITM_TRACE_EN\r
+CYREG_ITM_TRACE_EN EQU 0xe0000e00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ITM_TRACE_PRIVILEGE\r
+CYREG_ITM_TRACE_PRIVILEGE EQU 0xe0000e40\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ITM_TRACE_CTRL\r
+CYREG_ITM_TRACE_CTRL EQU 0xe0000e80\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ITM_LOCK_ACCESS\r
+CYREG_ITM_LOCK_ACCESS EQU 0xe0000fb0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ITM_LOCK_STATUS\r
+CYREG_ITM_LOCK_STATUS EQU 0xe0000fb4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ITM_PID4\r
+CYREG_ITM_PID4 EQU 0xe0000fd0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ITM_PID5\r
+CYREG_ITM_PID5 EQU 0xe0000fd4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ITM_PID6\r
+CYREG_ITM_PID6 EQU 0xe0000fd8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ITM_PID7\r
+CYREG_ITM_PID7 EQU 0xe0000fdc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ITM_PID0\r
+CYREG_ITM_PID0 EQU 0xe0000fe0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ITM_PID1\r
+CYREG_ITM_PID1 EQU 0xe0000fe4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ITM_PID2\r
+CYREG_ITM_PID2 EQU 0xe0000fe8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ITM_PID3\r
+CYREG_ITM_PID3 EQU 0xe0000fec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ITM_CID0\r
+CYREG_ITM_CID0 EQU 0xe0000ff0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ITM_CID1\r
+CYREG_ITM_CID1 EQU 0xe0000ff4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ITM_CID2\r
+CYREG_ITM_CID2 EQU 0xe0000ff8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ITM_CID3\r
+CYREG_ITM_CID3 EQU 0xe0000ffc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_BASE\r
+CYDEV_DWT_BASE EQU 0xe0001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_DWT_SIZE\r
+CYDEV_DWT_SIZE EQU 0x0000005c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_CTRL\r
+CYREG_DWT_CTRL EQU 0xe0001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_CYCLE_COUNT\r
+CYREG_DWT_CYCLE_COUNT EQU 0xe0001004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_CPI_COUNT\r
+CYREG_DWT_CPI_COUNT EQU 0xe0001008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_EXC_OVHD_COUNT\r
+CYREG_DWT_EXC_OVHD_COUNT EQU 0xe000100c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_SLEEP_COUNT\r
+CYREG_DWT_SLEEP_COUNT EQU 0xe0001010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_LSU_COUNT\r
+CYREG_DWT_LSU_COUNT EQU 0xe0001014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_FOLD_COUNT\r
+CYREG_DWT_FOLD_COUNT EQU 0xe0001018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_PC_SAMPLE\r
+CYREG_DWT_PC_SAMPLE EQU 0xe000101c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_COMP_0\r
+CYREG_DWT_COMP_0 EQU 0xe0001020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_MASK_0\r
+CYREG_DWT_MASK_0 EQU 0xe0001024\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_FUNCTION_0\r
+CYREG_DWT_FUNCTION_0 EQU 0xe0001028\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_COMP_1\r
+CYREG_DWT_COMP_1 EQU 0xe0001030\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_MASK_1\r
+CYREG_DWT_MASK_1 EQU 0xe0001034\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_FUNCTION_1\r
+CYREG_DWT_FUNCTION_1 EQU 0xe0001038\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_COMP_2\r
+CYREG_DWT_COMP_2 EQU 0xe0001040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_MASK_2\r
+CYREG_DWT_MASK_2 EQU 0xe0001044\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_FUNCTION_2\r
+CYREG_DWT_FUNCTION_2 EQU 0xe0001048\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_COMP_3\r
+CYREG_DWT_COMP_3 EQU 0xe0001050\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_MASK_3\r
+CYREG_DWT_MASK_3 EQU 0xe0001054\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_DWT_FUNCTION_3\r
+CYREG_DWT_FUNCTION_3 EQU 0xe0001058\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_BASE\r
+CYDEV_FPB_BASE EQU 0xe0002000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FPB_SIZE\r
+CYDEV_FPB_SIZE EQU 0x00001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_CTRL\r
+CYREG_FPB_CTRL EQU 0xe0002000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_REMAP\r
+CYREG_FPB_REMAP EQU 0xe0002004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_FP_COMP_0\r
+CYREG_FPB_FP_COMP_0 EQU 0xe0002008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_FP_COMP_1\r
+CYREG_FPB_FP_COMP_1 EQU 0xe000200c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_FP_COMP_2\r
+CYREG_FPB_FP_COMP_2 EQU 0xe0002010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_FP_COMP_3\r
+CYREG_FPB_FP_COMP_3 EQU 0xe0002014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_FP_COMP_4\r
+CYREG_FPB_FP_COMP_4 EQU 0xe0002018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_FP_COMP_5\r
+CYREG_FPB_FP_COMP_5 EQU 0xe000201c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_FP_COMP_6\r
+CYREG_FPB_FP_COMP_6 EQU 0xe0002020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_FP_COMP_7\r
+CYREG_FPB_FP_COMP_7 EQU 0xe0002024\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_PID4\r
+CYREG_FPB_PID4 EQU 0xe0002fd0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_PID5\r
+CYREG_FPB_PID5 EQU 0xe0002fd4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_PID6\r
+CYREG_FPB_PID6 EQU 0xe0002fd8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_PID7\r
+CYREG_FPB_PID7 EQU 0xe0002fdc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_PID0\r
+CYREG_FPB_PID0 EQU 0xe0002fe0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_PID1\r
+CYREG_FPB_PID1 EQU 0xe0002fe4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_PID2\r
+CYREG_FPB_PID2 EQU 0xe0002fe8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_PID3\r
+CYREG_FPB_PID3 EQU 0xe0002fec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_CID0\r
+CYREG_FPB_CID0 EQU 0xe0002ff0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_CID1\r
+CYREG_FPB_CID1 EQU 0xe0002ff4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_CID2\r
+CYREG_FPB_CID2 EQU 0xe0002ff8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_FPB_CID3\r
+CYREG_FPB_CID3 EQU 0xe0002ffc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_BASE\r
+CYDEV_NVIC_BASE EQU 0xe000e000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_NVIC_SIZE\r
+CYDEV_NVIC_SIZE EQU 0x00000d3c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_INT_CTL_TYPE\r
+CYREG_NVIC_INT_CTL_TYPE EQU 0xe000e004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CTL\r
+CYREG_NVIC_SYSTICK_CTL EQU 0xe000e010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_SYSTICK_RELOAD\r
+CYREG_NVIC_SYSTICK_RELOAD EQU 0xe000e014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CURRENT\r
+CYREG_NVIC_SYSTICK_CURRENT EQU 0xe000e018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CAL\r
+CYREG_NVIC_SYSTICK_CAL EQU 0xe000e01c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_SETENA0\r
+CYREG_NVIC_SETENA0 EQU 0xe000e100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_CLRENA0\r
+CYREG_NVIC_CLRENA0 EQU 0xe000e180\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_SETPEND0\r
+CYREG_NVIC_SETPEND0 EQU 0xe000e200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_CLRPEND0\r
+CYREG_NVIC_CLRPEND0 EQU 0xe000e280\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_ACTIVE0\r
+CYREG_NVIC_ACTIVE0 EQU 0xe000e300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_0\r
+CYREG_NVIC_PRI_0 EQU 0xe000e400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_1\r
+CYREG_NVIC_PRI_1 EQU 0xe000e401\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_2\r
+CYREG_NVIC_PRI_2 EQU 0xe000e402\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_3\r
+CYREG_NVIC_PRI_3 EQU 0xe000e403\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_4\r
+CYREG_NVIC_PRI_4 EQU 0xe000e404\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_5\r
+CYREG_NVIC_PRI_5 EQU 0xe000e405\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_6\r
+CYREG_NVIC_PRI_6 EQU 0xe000e406\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_7\r
+CYREG_NVIC_PRI_7 EQU 0xe000e407\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_8\r
+CYREG_NVIC_PRI_8 EQU 0xe000e408\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_9\r
+CYREG_NVIC_PRI_9 EQU 0xe000e409\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_10\r
+CYREG_NVIC_PRI_10 EQU 0xe000e40a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_11\r
+CYREG_NVIC_PRI_11 EQU 0xe000e40b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_12\r
+CYREG_NVIC_PRI_12 EQU 0xe000e40c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_13\r
+CYREG_NVIC_PRI_13 EQU 0xe000e40d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_14\r
+CYREG_NVIC_PRI_14 EQU 0xe000e40e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_15\r
+CYREG_NVIC_PRI_15 EQU 0xe000e40f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_16\r
+CYREG_NVIC_PRI_16 EQU 0xe000e410\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_17\r
+CYREG_NVIC_PRI_17 EQU 0xe000e411\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_18\r
+CYREG_NVIC_PRI_18 EQU 0xe000e412\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_19\r
+CYREG_NVIC_PRI_19 EQU 0xe000e413\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_20\r
+CYREG_NVIC_PRI_20 EQU 0xe000e414\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_21\r
+CYREG_NVIC_PRI_21 EQU 0xe000e415\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_22\r
+CYREG_NVIC_PRI_22 EQU 0xe000e416\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_23\r
+CYREG_NVIC_PRI_23 EQU 0xe000e417\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_24\r
+CYREG_NVIC_PRI_24 EQU 0xe000e418\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_25\r
+CYREG_NVIC_PRI_25 EQU 0xe000e419\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_26\r
+CYREG_NVIC_PRI_26 EQU 0xe000e41a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_27\r
+CYREG_NVIC_PRI_27 EQU 0xe000e41b\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_28\r
+CYREG_NVIC_PRI_28 EQU 0xe000e41c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_29\r
+CYREG_NVIC_PRI_29 EQU 0xe000e41d\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_30\r
+CYREG_NVIC_PRI_30 EQU 0xe000e41e\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_PRI_31\r
+CYREG_NVIC_PRI_31 EQU 0xe000e41f\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_CPUID_BASE\r
+CYREG_NVIC_CPUID_BASE EQU 0xe000ed00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_INTR_CTRL_STATE\r
+CYREG_NVIC_INTR_CTRL_STATE EQU 0xe000ed04\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_VECT_OFFSET\r
+CYREG_NVIC_VECT_OFFSET EQU 0xe000ed08\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_APPLN_INTR\r
+CYREG_NVIC_APPLN_INTR EQU 0xe000ed0c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_SYSTEM_CONTROL\r
+CYREG_NVIC_SYSTEM_CONTROL EQU 0xe000ed10\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_CFG_CONTROL\r
+CYREG_NVIC_CFG_CONTROL EQU 0xe000ed14\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_4_7\r
+CYREG_NVIC_SYS_PRIO_HANDLER_4_7 EQU 0xe000ed18\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_8_11\r
+CYREG_NVIC_SYS_PRIO_HANDLER_8_11 EQU 0xe000ed1c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_12_15\r
+CYREG_NVIC_SYS_PRIO_HANDLER_12_15 EQU 0xe000ed20\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_SYS_HANDLER_CSR\r
+CYREG_NVIC_SYS_HANDLER_CSR EQU 0xe000ed24\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_MEMMAN_FAULT_STATUS\r
+CYREG_NVIC_MEMMAN_FAULT_STATUS EQU 0xe000ed28\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_BUS_FAULT_STATUS\r
+CYREG_NVIC_BUS_FAULT_STATUS EQU 0xe000ed29\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_USAGE_FAULT_STATUS\r
+CYREG_NVIC_USAGE_FAULT_STATUS EQU 0xe000ed2a\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_HARD_FAULT_STATUS\r
+CYREG_NVIC_HARD_FAULT_STATUS EQU 0xe000ed2c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_DEBUG_FAULT_STATUS\r
+CYREG_NVIC_DEBUG_FAULT_STATUS EQU 0xe000ed30\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_MEMMAN_FAULT_ADD\r
+CYREG_NVIC_MEMMAN_FAULT_ADD EQU 0xe000ed34\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_NVIC_BUS_FAULT_ADD\r
+CYREG_NVIC_BUS_FAULT_ADD EQU 0xe000ed38\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CORE_DBG_BASE\r
+CYDEV_CORE_DBG_BASE EQU 0xe000edf0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_CORE_DBG_SIZE\r
+CYDEV_CORE_DBG_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CORE_DBG_DBG_HLT_CS\r
+CYREG_CORE_DBG_DBG_HLT_CS EQU 0xe000edf0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CORE_DBG_DBG_REG_SEL\r
+CYREG_CORE_DBG_DBG_REG_SEL EQU 0xe000edf4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CORE_DBG_DBG_REG_DATA\r
+CYREG_CORE_DBG_DBG_REG_DATA EQU 0xe000edf8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_CORE_DBG_EXC_MON_CTL\r
+CYREG_CORE_DBG_EXC_MON_CTL EQU 0xe000edfc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_BASE\r
+CYDEV_TPIU_BASE EQU 0xe0040000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_TPIU_SIZE\r
+CYDEV_TPIU_SIZE EQU 0x00001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ\r
+CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ EQU 0xe0040000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_CURRENT_SYNC_PRT_SZ\r
+CYREG_TPIU_CURRENT_SYNC_PRT_SZ EQU 0xe0040004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_ASYNC_CLK_PRESCALER\r
+CYREG_TPIU_ASYNC_CLK_PRESCALER EQU 0xe0040010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_PROTOCOL\r
+CYREG_TPIU_PROTOCOL EQU 0xe00400f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_FORM_FLUSH_STAT\r
+CYREG_TPIU_FORM_FLUSH_STAT EQU 0xe0040300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_FORM_FLUSH_CTRL\r
+CYREG_TPIU_FORM_FLUSH_CTRL EQU 0xe0040304\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_TRIGGER\r
+CYREG_TPIU_TRIGGER EQU 0xe0040ee8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_ITETMDATA\r
+CYREG_TPIU_ITETMDATA EQU 0xe0040eec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_ITATBCTR2\r
+CYREG_TPIU_ITATBCTR2 EQU 0xe0040ef0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_ITATBCTR0\r
+CYREG_TPIU_ITATBCTR0 EQU 0xe0040ef8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_ITITMDATA\r
+CYREG_TPIU_ITITMDATA EQU 0xe0040efc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_ITCTRL\r
+CYREG_TPIU_ITCTRL EQU 0xe0040f00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_DEVID\r
+CYREG_TPIU_DEVID EQU 0xe0040fc8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_DEVTYPE\r
+CYREG_TPIU_DEVTYPE EQU 0xe0040fcc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_PID4\r
+CYREG_TPIU_PID4 EQU 0xe0040fd0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_PID5\r
+CYREG_TPIU_PID5 EQU 0xe0040fd4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_PID6\r
+CYREG_TPIU_PID6 EQU 0xe0040fd8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_PID7\r
+CYREG_TPIU_PID7 EQU 0xe0040fdc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_PID0\r
+CYREG_TPIU_PID0 EQU 0xe0040fe0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_PID1\r
+CYREG_TPIU_PID1 EQU 0xe0040fe4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_PID2\r
+CYREG_TPIU_PID2 EQU 0xe0040fe8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_PID3\r
+CYREG_TPIU_PID3 EQU 0xe0040fec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_CID0\r
+CYREG_TPIU_CID0 EQU 0xe0040ff0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_CID1\r
+CYREG_TPIU_CID1 EQU 0xe0040ff4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_CID2\r
+CYREG_TPIU_CID2 EQU 0xe0040ff8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_TPIU_CID3\r
+CYREG_TPIU_CID3 EQU 0xe0040ffc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_BASE\r
+CYDEV_ETM_BASE EQU 0xe0041000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ETM_SIZE\r
+CYDEV_ETM_SIZE EQU 0x00001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_CTL\r
+CYREG_ETM_CTL EQU 0xe0041000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_CFG_CODE\r
+CYREG_ETM_CFG_CODE EQU 0xe0041004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_TRIG_EVENT\r
+CYREG_ETM_TRIG_EVENT EQU 0xe0041008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_STATUS\r
+CYREG_ETM_STATUS EQU 0xe0041010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_SYS_CFG\r
+CYREG_ETM_SYS_CFG EQU 0xe0041014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_TRACE_ENB_EVENT\r
+CYREG_ETM_TRACE_ENB_EVENT EQU 0xe0041020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_TRACE_EN_CTRL1\r
+CYREG_ETM_TRACE_EN_CTRL1 EQU 0xe0041024\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_FIFOFULL_LEVEL\r
+CYREG_ETM_FIFOFULL_LEVEL EQU 0xe004102c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_SYNC_FREQ\r
+CYREG_ETM_SYNC_FREQ EQU 0xe00411e0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_ETM_ID\r
+CYREG_ETM_ETM_ID EQU 0xe00411e4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_CFG_CODE_EXT\r
+CYREG_ETM_CFG_CODE_EXT EQU 0xe00411e8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_TR_SS_EMBICE_CTRL\r
+CYREG_ETM_TR_SS_EMBICE_CTRL EQU 0xe00411f0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_CS_TRACE_ID\r
+CYREG_ETM_CS_TRACE_ID EQU 0xe0041200\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_OS_LOCK_ACCESS\r
+CYREG_ETM_OS_LOCK_ACCESS EQU 0xe0041300\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_OS_LOCK_STATUS\r
+CYREG_ETM_OS_LOCK_STATUS EQU 0xe0041304\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_PDSR\r
+CYREG_ETM_PDSR EQU 0xe0041314\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_ITMISCIN\r
+CYREG_ETM_ITMISCIN EQU 0xe0041ee0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_ITTRIGOUT\r
+CYREG_ETM_ITTRIGOUT EQU 0xe0041ee8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_ITATBCTR2\r
+CYREG_ETM_ITATBCTR2 EQU 0xe0041ef0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_ITATBCTR0\r
+CYREG_ETM_ITATBCTR0 EQU 0xe0041ef8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_INT_MODE_CTRL\r
+CYREG_ETM_INT_MODE_CTRL EQU 0xe0041f00\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_CLM_TAG_SET\r
+CYREG_ETM_CLM_TAG_SET EQU 0xe0041fa0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_CLM_TAG_CLR\r
+CYREG_ETM_CLM_TAG_CLR EQU 0xe0041fa4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_LOCK_ACCESS\r
+CYREG_ETM_LOCK_ACCESS EQU 0xe0041fb0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_LOCK_STATUS\r
+CYREG_ETM_LOCK_STATUS EQU 0xe0041fb4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_AUTH_STATUS\r
+CYREG_ETM_AUTH_STATUS EQU 0xe0041fb8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_DEV_TYPE\r
+CYREG_ETM_DEV_TYPE EQU 0xe0041fcc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_PID4\r
+CYREG_ETM_PID4 EQU 0xe0041fd0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_PID5\r
+CYREG_ETM_PID5 EQU 0xe0041fd4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_PID6\r
+CYREG_ETM_PID6 EQU 0xe0041fd8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_PID7\r
+CYREG_ETM_PID7 EQU 0xe0041fdc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_PID0\r
+CYREG_ETM_PID0 EQU 0xe0041fe0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_PID1\r
+CYREG_ETM_PID1 EQU 0xe0041fe4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_PID2\r
+CYREG_ETM_PID2 EQU 0xe0041fe8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_PID3\r
+CYREG_ETM_PID3 EQU 0xe0041fec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_CID0\r
+CYREG_ETM_CID0 EQU 0xe0041ff0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_CID1\r
+CYREG_ETM_CID1 EQU 0xe0041ff4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_CID2\r
+CYREG_ETM_CID2 EQU 0xe0041ff8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ETM_CID3\r
+CYREG_ETM_CID3 EQU 0xe0041ffc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_BASE\r
+CYDEV_ROM_TABLE_BASE EQU 0xe00ff000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ROM_TABLE_SIZE\r
+CYDEV_ROM_TABLE_SIZE EQU 0x00001000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_NVIC\r
+CYREG_ROM_TABLE_NVIC EQU 0xe00ff000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_DWT\r
+CYREG_ROM_TABLE_DWT EQU 0xe00ff004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_FPB\r
+CYREG_ROM_TABLE_FPB EQU 0xe00ff008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_ITM\r
+CYREG_ROM_TABLE_ITM EQU 0xe00ff00c\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_TPIU\r
+CYREG_ROM_TABLE_TPIU EQU 0xe00ff010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_ETM\r
+CYREG_ROM_TABLE_ETM EQU 0xe00ff014\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_END\r
+CYREG_ROM_TABLE_END EQU 0xe00ff018\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_MEMTYPE\r
+CYREG_ROM_TABLE_MEMTYPE EQU 0xe00fffcc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_PID4\r
+CYREG_ROM_TABLE_PID4 EQU 0xe00fffd0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_PID5\r
+CYREG_ROM_TABLE_PID5 EQU 0xe00fffd4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_PID6\r
+CYREG_ROM_TABLE_PID6 EQU 0xe00fffd8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_PID7\r
+CYREG_ROM_TABLE_PID7 EQU 0xe00fffdc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_PID0\r
+CYREG_ROM_TABLE_PID0 EQU 0xe00fffe0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_PID1\r
+CYREG_ROM_TABLE_PID1 EQU 0xe00fffe4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_PID2\r
+CYREG_ROM_TABLE_PID2 EQU 0xe00fffe8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_PID3\r
+CYREG_ROM_TABLE_PID3 EQU 0xe00fffec\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_CID0\r
+CYREG_ROM_TABLE_CID0 EQU 0xe00ffff0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_CID1\r
+CYREG_ROM_TABLE_CID1 EQU 0xe00ffff4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_CID2\r
+CYREG_ROM_TABLE_CID2 EQU 0xe00ffff8\r
+ ENDIF\r
+ IF :LNOT::DEF:CYREG_ROM_TABLE_CID3\r
+CYREG_ROM_TABLE_CID3 EQU 0xe00ffffc\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLS_SIZE\r
+CYDEV_FLS_SIZE EQU CYDEV_FLASH_SIZE\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ECC_BASE\r
+CYDEV_ECC_BASE EQU CYDEV_FLSECC_BASE\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE\r
+CYDEV_FLS_SECTOR_SIZE EQU 0x00010000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE\r
+CYDEV_FLS_ROW_SIZE EQU 0x00000100\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE\r
+CYDEV_ECC_SECTOR_SIZE EQU 0x00002000\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_ECC_ROW_SIZE\r
+CYDEV_ECC_ROW_SIZE EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EEPROM_SECTOR_SIZE\r
+CYDEV_EEPROM_SECTOR_SIZE EQU 0x00000400\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_EEPROM_ROW_SIZE\r
+CYDEV_EEPROM_ROW_SIZE EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYDEV_PERIPH_BASE\r
+CYDEV_PERIPH_BASE EQU CYDEV_CLKDIST_BASE\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_LD_DISABLE\r
+CYCLK_LD_DISABLE EQU 0x00000004\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_LD_SYNC_EN\r
+CYCLK_LD_SYNC_EN EQU 0x00000002\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_LD_LOAD\r
+CYCLK_LD_LOAD EQU 0x00000001\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_PIPE\r
+CYCLK_PIPE EQU 0x00000080\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SSS\r
+CYCLK_SSS EQU 0x00000040\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_EARLY\r
+CYCLK_EARLY EQU 0x00000020\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_DUTY\r
+CYCLK_DUTY EQU 0x00000010\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SYNC\r
+CYCLK_SYNC EQU 0x00000008\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_D\r
+CYCLK_SRC_SEL_CLK_SYNC_D EQU 0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_SYNC_DIG\r
+CYCLK_SRC_SEL_SYNC_DIG EQU 0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_IMO\r
+CYCLK_SRC_SEL_IMO EQU 1\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_MHZ\r
+CYCLK_SRC_SEL_XTAL_MHZ EQU 2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_XTALM\r
+CYCLK_SRC_SEL_XTALM EQU 2\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_ILO\r
+CYCLK_SRC_SEL_ILO EQU 3\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_PLL\r
+CYCLK_SRC_SEL_PLL EQU 4\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_KHZ\r
+CYCLK_SRC_SEL_XTAL_KHZ EQU 5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_XTALK\r
+CYCLK_SRC_SEL_XTALK EQU 5\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_G\r
+CYCLK_SRC_SEL_DSI_G EQU 6\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_D\r
+CYCLK_SRC_SEL_DSI_D EQU 7\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_A\r
+CYCLK_SRC_SEL_CLK_SYNC_A EQU 0\r
+ ENDIF\r
+ IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_A\r
+CYCLK_SRC_SEL_DSI_A EQU 7\r
+ ENDIF\r
+ END\r
--- /dev/null
+#ifndef INCLUDED_CYFITTER_H\r
+#define INCLUDED_CYFITTER_H\r
+#include <cydevice.h>\r
+#include <cydevice_trm.h>\r
+\r
+/* SDCard_RxInternalInterrupt */\r
+#define SDCard_RxInternalInterrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SDCard_RxInternalInterrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SDCard_RxInternalInterrupt__INTC_MASK 0x01u\r
+#define SDCard_RxInternalInterrupt__INTC_NUMBER 0u\r
+#define SDCard_RxInternalInterrupt__INTC_PRIOR_NUM 7u\r
+#define SDCard_RxInternalInterrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0\r
+#define SDCard_RxInternalInterrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SDCard_RxInternalInterrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SDCard_TxInternalInterrupt */\r
+#define SDCard_TxInternalInterrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
+#define SDCard_TxInternalInterrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
+#define SDCard_TxInternalInterrupt__INTC_MASK 0x02u\r
+#define SDCard_TxInternalInterrupt__INTC_NUMBER 1u\r
+#define SDCard_TxInternalInterrupt__INTC_PRIOR_NUM 7u\r
+#define SDCard_TxInternalInterrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1\r
+#define SDCard_TxInternalInterrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
+#define SDCard_TxInternalInterrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_Out_DBx */\r
+#define SCSI_Out_DBx__0__MASK 0x01u\r
+#define SCSI_Out_DBx__0__PC CYREG_PRT0_PC0\r
+#define SCSI_Out_DBx__0__PORT 0u\r
+#define SCSI_Out_DBx__0__SHIFT 0\r
+#define SCSI_Out_DBx__1__MASK 0x02u\r
+#define SCSI_Out_DBx__1__PC CYREG_PRT0_PC1\r
+#define SCSI_Out_DBx__1__PORT 0u\r
+#define SCSI_Out_DBx__1__SHIFT 1\r
+#define SCSI_Out_DBx__2__MASK 0x04u\r
+#define SCSI_Out_DBx__2__PC CYREG_PRT0_PC2\r
+#define SCSI_Out_DBx__2__PORT 0u\r
+#define SCSI_Out_DBx__2__SHIFT 2\r
+#define SCSI_Out_DBx__3__MASK 0x08u\r
+#define SCSI_Out_DBx__3__PC CYREG_PRT0_PC3\r
+#define SCSI_Out_DBx__3__PORT 0u\r
+#define SCSI_Out_DBx__3__SHIFT 3\r
+#define SCSI_Out_DBx__4__MASK 0x10u\r
+#define SCSI_Out_DBx__4__PC CYREG_PRT0_PC4\r
+#define SCSI_Out_DBx__4__PORT 0u\r
+#define SCSI_Out_DBx__4__SHIFT 4\r
+#define SCSI_Out_DBx__5__MASK 0x20u\r
+#define SCSI_Out_DBx__5__PC CYREG_PRT0_PC5\r
+#define SCSI_Out_DBx__5__PORT 0u\r
+#define SCSI_Out_DBx__5__SHIFT 5\r
+#define SCSI_Out_DBx__6__MASK 0x40u\r
+#define SCSI_Out_DBx__6__PC CYREG_PRT0_PC6\r
+#define SCSI_Out_DBx__6__PORT 0u\r
+#define SCSI_Out_DBx__6__SHIFT 6\r
+#define SCSI_Out_DBx__7__MASK 0x80u\r
+#define SCSI_Out_DBx__7__PC CYREG_PRT0_PC7\r
+#define SCSI_Out_DBx__7__PORT 0u\r
+#define SCSI_Out_DBx__7__SHIFT 7\r
+#define SCSI_Out_DBx__AG CYREG_PRT0_AG\r
+#define SCSI_Out_DBx__AMUX CYREG_PRT0_AMUX\r
+#define SCSI_Out_DBx__BIE CYREG_PRT0_BIE\r
+#define SCSI_Out_DBx__BIT_MASK CYREG_PRT0_BIT_MASK\r
+#define SCSI_Out_DBx__BYP CYREG_PRT0_BYP\r
+#define SCSI_Out_DBx__CTL CYREG_PRT0_CTL\r
+#define SCSI_Out_DBx__DM0 CYREG_PRT0_DM0\r
+#define SCSI_Out_DBx__DM1 CYREG_PRT0_DM1\r
+#define SCSI_Out_DBx__DM2 CYREG_PRT0_DM2\r
+#define SCSI_Out_DBx__DR CYREG_PRT0_DR\r
+#define SCSI_Out_DBx__INP_DIS CYREG_PRT0_INP_DIS\r
+#define SCSI_Out_DBx__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG\r
+#define SCSI_Out_DBx__LCD_EN CYREG_PRT0_LCD_EN\r
+#define SCSI_Out_DBx__MASK 0xFFu\r
+#define SCSI_Out_DBx__PORT 0u\r
+#define SCSI_Out_DBx__PRT CYREG_PRT0_PRT\r
+#define SCSI_Out_DBx__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL\r
+#define SCSI_Out_DBx__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN\r
+#define SCSI_Out_DBx__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0\r
+#define SCSI_Out_DBx__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1\r
+#define SCSI_Out_DBx__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0\r
+#define SCSI_Out_DBx__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1\r
+#define SCSI_Out_DBx__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT\r
+#define SCSI_Out_DBx__PS CYREG_PRT0_PS\r
+#define SCSI_Out_DBx__SCSI_Out_DB0__MASK 0x01u\r
+#define SCSI_Out_DBx__SCSI_Out_DB0__PC CYREG_PRT0_PC0\r
+#define SCSI_Out_DBx__SCSI_Out_DB0__PORT 0u\r
+#define SCSI_Out_DBx__SCSI_Out_DB0__SHIFT 0\r
+#define SCSI_Out_DBx__SCSI_Out_DB1__MASK 0x02u\r
+#define SCSI_Out_DBx__SCSI_Out_DB1__PC CYREG_PRT0_PC1\r
+#define SCSI_Out_DBx__SCSI_Out_DB1__PORT 0u\r
+#define SCSI_Out_DBx__SCSI_Out_DB1__SHIFT 1\r
+#define SCSI_Out_DBx__SCSI_Out_DB2__MASK 0x04u\r
+#define SCSI_Out_DBx__SCSI_Out_DB2__PC CYREG_PRT0_PC2\r
+#define SCSI_Out_DBx__SCSI_Out_DB2__PORT 0u\r
+#define SCSI_Out_DBx__SCSI_Out_DB2__SHIFT 2\r
+#define SCSI_Out_DBx__SCSI_Out_DB3__MASK 0x08u\r
+#define SCSI_Out_DBx__SCSI_Out_DB3__PC CYREG_PRT0_PC3\r
+#define SCSI_Out_DBx__SCSI_Out_DB3__PORT 0u\r
+#define SCSI_Out_DBx__SCSI_Out_DB3__SHIFT 3\r
+#define SCSI_Out_DBx__SCSI_Out_DB4__MASK 0x10u\r
+#define SCSI_Out_DBx__SCSI_Out_DB4__PC CYREG_PRT0_PC4\r
+#define SCSI_Out_DBx__SCSI_Out_DB4__PORT 0u\r
+#define SCSI_Out_DBx__SCSI_Out_DB4__SHIFT 4\r
+#define SCSI_Out_DBx__SCSI_Out_DB5__MASK 0x20u\r
+#define SCSI_Out_DBx__SCSI_Out_DB5__PC CYREG_PRT0_PC5\r
+#define SCSI_Out_DBx__SCSI_Out_DB5__PORT 0u\r
+#define SCSI_Out_DBx__SCSI_Out_DB5__SHIFT 5\r
+#define SCSI_Out_DBx__SCSI_Out_DB6__MASK 0x40u\r
+#define SCSI_Out_DBx__SCSI_Out_DB6__PC CYREG_PRT0_PC6\r
+#define SCSI_Out_DBx__SCSI_Out_DB6__PORT 0u\r
+#define SCSI_Out_DBx__SCSI_Out_DB6__SHIFT 6\r
+#define SCSI_Out_DBx__SCSI_Out_DB7__MASK 0x80u\r
+#define SCSI_Out_DBx__SCSI_Out_DB7__PC CYREG_PRT0_PC7\r
+#define SCSI_Out_DBx__SCSI_Out_DB7__PORT 0u\r
+#define SCSI_Out_DBx__SCSI_Out_DB7__SHIFT 7\r
+#define SCSI_Out_DBx__SHIFT 0\r
+#define SCSI_Out_DBx__SLW CYREG_PRT0_SLW\r
+\r
+/* SDCard_BSPIM */\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL\r
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL\r
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL\r
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK\r
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST\r
+#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
+#define SDCard_BSPIM_RxStsReg__4__POS 4\r
+#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
+#define SDCard_BSPIM_RxStsReg__5__POS 5\r
+#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
+#define SDCard_BSPIM_RxStsReg__6__POS 6\r
+#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST\r
+#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
+#define SDCard_BSPIM_TxStsReg__0__POS 0\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST\r
+#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
+#define SDCard_BSPIM_TxStsReg__1__POS 1\r
+#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
+#define SDCard_BSPIM_TxStsReg__2__POS 2\r
+#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u\r
+#define SDCard_BSPIM_TxStsReg__3__POS 3\r
+#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
+#define SDCard_BSPIM_TxStsReg__4__POS 4\r
+#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB07_08_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB07_08_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB07_08_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB07_08_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB07_08_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB07_08_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB07_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB07_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB07_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB07_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB07_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB07_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB07_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB07_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB07_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+\r
+/* SCSI_In_DBx */\r
+#define SCSI_In_DBx__0__MASK 0x01u\r
+#define SCSI_In_DBx__0__PC CYREG_PRT2_PC0\r
+#define SCSI_In_DBx__0__PORT 2u\r
+#define SCSI_In_DBx__0__SHIFT 0\r
+#define SCSI_In_DBx__1__MASK 0x02u\r
+#define SCSI_In_DBx__1__PC CYREG_PRT2_PC1\r
+#define SCSI_In_DBx__1__PORT 2u\r
+#define SCSI_In_DBx__1__SHIFT 1\r
+#define SCSI_In_DBx__2__MASK 0x04u\r
+#define SCSI_In_DBx__2__PC CYREG_PRT2_PC2\r
+#define SCSI_In_DBx__2__PORT 2u\r
+#define SCSI_In_DBx__2__SHIFT 2\r
+#define SCSI_In_DBx__3__MASK 0x08u\r
+#define SCSI_In_DBx__3__PC CYREG_PRT2_PC3\r
+#define SCSI_In_DBx__3__PORT 2u\r
+#define SCSI_In_DBx__3__SHIFT 3\r
+#define SCSI_In_DBx__4__MASK 0x10u\r
+#define SCSI_In_DBx__4__PC CYREG_PRT2_PC4\r
+#define SCSI_In_DBx__4__PORT 2u\r
+#define SCSI_In_DBx__4__SHIFT 4\r
+#define SCSI_In_DBx__5__MASK 0x20u\r
+#define SCSI_In_DBx__5__PC CYREG_PRT2_PC5\r
+#define SCSI_In_DBx__5__PORT 2u\r
+#define SCSI_In_DBx__5__SHIFT 5\r
+#define SCSI_In_DBx__6__MASK 0x40u\r
+#define SCSI_In_DBx__6__PC CYREG_PRT2_PC6\r
+#define SCSI_In_DBx__6__PORT 2u\r
+#define SCSI_In_DBx__6__SHIFT 6\r
+#define SCSI_In_DBx__7__MASK 0x80u\r
+#define SCSI_In_DBx__7__PC CYREG_PRT2_PC7\r
+#define SCSI_In_DBx__7__PORT 2u\r
+#define SCSI_In_DBx__7__SHIFT 7\r
+#define SCSI_In_DBx__AG CYREG_PRT2_AG\r
+#define SCSI_In_DBx__AMUX CYREG_PRT2_AMUX\r
+#define SCSI_In_DBx__BIE CYREG_PRT2_BIE\r
+#define SCSI_In_DBx__BIT_MASK CYREG_PRT2_BIT_MASK\r
+#define SCSI_In_DBx__BYP CYREG_PRT2_BYP\r
+#define SCSI_In_DBx__CTL CYREG_PRT2_CTL\r
+#define SCSI_In_DBx__DM0 CYREG_PRT2_DM0\r
+#define SCSI_In_DBx__DM1 CYREG_PRT2_DM1\r
+#define SCSI_In_DBx__DM2 CYREG_PRT2_DM2\r
+#define SCSI_In_DBx__DR CYREG_PRT2_DR\r
+#define SCSI_In_DBx__INP_DIS CYREG_PRT2_INP_DIS\r
+#define SCSI_In_DBx__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG\r
+#define SCSI_In_DBx__LCD_EN CYREG_PRT2_LCD_EN\r
+#define SCSI_In_DBx__MASK 0xFFu\r
+#define SCSI_In_DBx__PORT 2u\r
+#define SCSI_In_DBx__PRT CYREG_PRT2_PRT\r
+#define SCSI_In_DBx__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL\r
+#define SCSI_In_DBx__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN\r
+#define SCSI_In_DBx__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0\r
+#define SCSI_In_DBx__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1\r
+#define SCSI_In_DBx__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0\r
+#define SCSI_In_DBx__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1\r
+#define SCSI_In_DBx__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT\r
+#define SCSI_In_DBx__PS CYREG_PRT2_PS\r
+#define SCSI_In_DBx__SCSI_Out_DB0__MASK 0x01u\r
+#define SCSI_In_DBx__SCSI_Out_DB0__PC CYREG_PRT2_PC0\r
+#define SCSI_In_DBx__SCSI_Out_DB0__PORT 2u\r
+#define SCSI_In_DBx__SCSI_Out_DB0__SHIFT 0\r
+#define SCSI_In_DBx__SCSI_Out_DB1__MASK 0x02u\r
+#define SCSI_In_DBx__SCSI_Out_DB1__PC CYREG_PRT2_PC1\r
+#define SCSI_In_DBx__SCSI_Out_DB1__PORT 2u\r
+#define SCSI_In_DBx__SCSI_Out_DB1__SHIFT 1\r
+#define SCSI_In_DBx__SCSI_Out_DB2__MASK 0x04u\r
+#define SCSI_In_DBx__SCSI_Out_DB2__PC CYREG_PRT2_PC2\r
+#define SCSI_In_DBx__SCSI_Out_DB2__PORT 2u\r
+#define SCSI_In_DBx__SCSI_Out_DB2__SHIFT 2\r
+#define SCSI_In_DBx__SCSI_Out_DB3__MASK 0x08u\r
+#define SCSI_In_DBx__SCSI_Out_DB3__PC CYREG_PRT2_PC3\r
+#define SCSI_In_DBx__SCSI_Out_DB3__PORT 2u\r
+#define SCSI_In_DBx__SCSI_Out_DB3__SHIFT 3\r
+#define SCSI_In_DBx__SCSI_Out_DB4__MASK 0x10u\r
+#define SCSI_In_DBx__SCSI_Out_DB4__PC CYREG_PRT2_PC4\r
+#define SCSI_In_DBx__SCSI_Out_DB4__PORT 2u\r
+#define SCSI_In_DBx__SCSI_Out_DB4__SHIFT 4\r
+#define SCSI_In_DBx__SCSI_Out_DB5__MASK 0x20u\r
+#define SCSI_In_DBx__SCSI_Out_DB5__PC CYREG_PRT2_PC5\r
+#define SCSI_In_DBx__SCSI_Out_DB5__PORT 2u\r
+#define SCSI_In_DBx__SCSI_Out_DB5__SHIFT 5\r
+#define SCSI_In_DBx__SCSI_Out_DB6__MASK 0x40u\r
+#define SCSI_In_DBx__SCSI_Out_DB6__PC CYREG_PRT2_PC6\r
+#define SCSI_In_DBx__SCSI_Out_DB6__PORT 2u\r
+#define SCSI_In_DBx__SCSI_Out_DB6__SHIFT 6\r
+#define SCSI_In_DBx__SCSI_Out_DB7__MASK 0x80u\r
+#define SCSI_In_DBx__SCSI_Out_DB7__PC CYREG_PRT2_PC7\r
+#define SCSI_In_DBx__SCSI_Out_DB7__PORT 2u\r
+#define SCSI_In_DBx__SCSI_Out_DB7__SHIFT 7\r
+#define SCSI_In_DBx__SHIFT 0\r
+#define SCSI_In_DBx__SLW CYREG_PRT2_SLW\r
+\r
+/* SD_Data_Clk */\r
+#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0\r
+#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1\r
+#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2\r
+#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u\r
+#define SD_Data_Clk__INDEX 0x00u\r
+#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
+#define SD_Data_Clk__PM_ACT_MSK 0x01u\r
+#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
+#define SD_Data_Clk__PM_STBY_MSK 0x01u\r
+\r
+/* SD_Init_Clk */\r
+#define SD_Init_Clk__CFG0 CYREG_CLKDIST_DCFG1_CFG0\r
+#define SD_Init_Clk__CFG1 CYREG_CLKDIST_DCFG1_CFG1\r
+#define SD_Init_Clk__CFG2 CYREG_CLKDIST_DCFG1_CFG2\r
+#define SD_Init_Clk__CFG2_SRC_SEL_MASK 0x07u\r
+#define SD_Init_Clk__INDEX 0x01u\r
+#define SD_Init_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2\r
+#define SD_Init_Clk__PM_ACT_MSK 0x02u\r
+#define SD_Init_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2\r
+#define SD_Init_Clk__PM_STBY_MSK 0x02u\r
+\r
+/* SD_Clk_Ctl */\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB05_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB05_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB05_MSK\r
+#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL\r
+\r
+/* PARITY_EN */\r
+#define PARITY_EN__0__MASK 0x10u\r
+#define PARITY_EN__0__PC CYREG_PRT5_PC4\r
+#define PARITY_EN__0__PORT 5u\r
+#define PARITY_EN__0__SHIFT 4\r
+#define PARITY_EN__AG CYREG_PRT5_AG\r
+#define PARITY_EN__AMUX CYREG_PRT5_AMUX\r
+#define PARITY_EN__BIE CYREG_PRT5_BIE\r
+#define PARITY_EN__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define PARITY_EN__BYP CYREG_PRT5_BYP\r
+#define PARITY_EN__CTL CYREG_PRT5_CTL\r
+#define PARITY_EN__DM0 CYREG_PRT5_DM0\r
+#define PARITY_EN__DM1 CYREG_PRT5_DM1\r
+#define PARITY_EN__DM2 CYREG_PRT5_DM2\r
+#define PARITY_EN__DR CYREG_PRT5_DR\r
+#define PARITY_EN__INP_DIS CYREG_PRT5_INP_DIS\r
+#define PARITY_EN__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define PARITY_EN__LCD_EN CYREG_PRT5_LCD_EN\r
+#define PARITY_EN__MASK 0x10u\r
+#define PARITY_EN__PORT 5u\r
+#define PARITY_EN__PRT CYREG_PRT5_PRT\r
+#define PARITY_EN__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define PARITY_EN__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define PARITY_EN__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define PARITY_EN__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define PARITY_EN__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define PARITY_EN__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define PARITY_EN__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define PARITY_EN__PS CYREG_PRT5_PS\r
+#define PARITY_EN__SHIFT 4\r
+#define PARITY_EN__SLW CYREG_PRT5_SLW\r
+\r
+/* SCSI_Out */\r
+#define SCSI_Out__0__AG CYREG_PRT4_AG\r
+#define SCSI_Out__0__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__0__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__0__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__0__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__0__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__0__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__0__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__0__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__0__DR CYREG_PRT4_DR\r
+#define SCSI_Out__0__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__0__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__0__MASK 0x04u\r
+#define SCSI_Out__0__PC CYREG_PRT4_PC2\r
+#define SCSI_Out__0__PORT 4u\r
+#define SCSI_Out__0__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__0__PS CYREG_PRT4_PS\r
+#define SCSI_Out__0__SHIFT 2\r
+#define SCSI_Out__0__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__1__AG CYREG_PRT4_AG\r
+#define SCSI_Out__1__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__1__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__1__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__1__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__1__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__1__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__1__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__1__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__1__DR CYREG_PRT4_DR\r
+#define SCSI_Out__1__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__1__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__1__MASK 0x08u\r
+#define SCSI_Out__1__PC CYREG_PRT4_PC3\r
+#define SCSI_Out__1__PORT 4u\r
+#define SCSI_Out__1__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__1__PS CYREG_PRT4_PS\r
+#define SCSI_Out__1__SHIFT 3\r
+#define SCSI_Out__1__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__2__AG CYREG_PRT4_AG\r
+#define SCSI_Out__2__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__2__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__2__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__2__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__2__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__2__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__2__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__2__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__2__DR CYREG_PRT4_DR\r
+#define SCSI_Out__2__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__2__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__2__MASK 0x10u\r
+#define SCSI_Out__2__PC CYREG_PRT4_PC4\r
+#define SCSI_Out__2__PORT 4u\r
+#define SCSI_Out__2__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__2__PS CYREG_PRT4_PS\r
+#define SCSI_Out__2__SHIFT 4\r
+#define SCSI_Out__2__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__3__AG CYREG_PRT4_AG\r
+#define SCSI_Out__3__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__3__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__3__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__3__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__3__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__3__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__3__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__3__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__3__DR CYREG_PRT4_DR\r
+#define SCSI_Out__3__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__3__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__3__MASK 0x20u\r
+#define SCSI_Out__3__PC CYREG_PRT4_PC5\r
+#define SCSI_Out__3__PORT 4u\r
+#define SCSI_Out__3__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__3__PS CYREG_PRT4_PS\r
+#define SCSI_Out__3__SHIFT 5\r
+#define SCSI_Out__3__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__4__AG CYREG_PRT4_AG\r
+#define SCSI_Out__4__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__4__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__4__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__4__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__4__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__4__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__4__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__4__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__4__DR CYREG_PRT4_DR\r
+#define SCSI_Out__4__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__4__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__4__MASK 0x40u\r
+#define SCSI_Out__4__PC CYREG_PRT4_PC6\r
+#define SCSI_Out__4__PORT 4u\r
+#define SCSI_Out__4__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__4__PS CYREG_PRT4_PS\r
+#define SCSI_Out__4__SHIFT 6\r
+#define SCSI_Out__4__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__5__AG CYREG_PRT4_AG\r
+#define SCSI_Out__5__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__5__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__5__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__5__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__5__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__5__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__5__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__5__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__5__DR CYREG_PRT4_DR\r
+#define SCSI_Out__5__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__5__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__5__MASK 0x80u\r
+#define SCSI_Out__5__PC CYREG_PRT4_PC7\r
+#define SCSI_Out__5__PORT 4u\r
+#define SCSI_Out__5__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__5__PS CYREG_PRT4_PS\r
+#define SCSI_Out__5__SHIFT 7\r
+#define SCSI_Out__5__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__6__AG CYREG_PRT6_AG\r
+#define SCSI_Out__6__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out__6__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out__6__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out__6__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out__6__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out__6__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out__6__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out__6__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out__6__DR CYREG_PRT6_DR\r
+#define SCSI_Out__6__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out__6__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out__6__MASK 0x01u\r
+#define SCSI_Out__6__PC CYREG_PRT6_PC0\r
+#define SCSI_Out__6__PORT 6u\r
+#define SCSI_Out__6__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out__6__PS CYREG_PRT6_PS\r
+#define SCSI_Out__6__SHIFT 0\r
+#define SCSI_Out__6__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out__7__AG CYREG_PRT6_AG\r
+#define SCSI_Out__7__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out__7__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out__7__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out__7__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out__7__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out__7__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out__7__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out__7__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out__7__DR CYREG_PRT6_DR\r
+#define SCSI_Out__7__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out__7__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out__7__MASK 0x02u\r
+#define SCSI_Out__7__PC CYREG_PRT6_PC1\r
+#define SCSI_Out__7__PORT 6u\r
+#define SCSI_Out__7__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out__7__PS CYREG_PRT6_PS\r
+#define SCSI_Out__7__SHIFT 1\r
+#define SCSI_Out__7__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out__8__AG CYREG_PRT6_AG\r
+#define SCSI_Out__8__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out__8__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out__8__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out__8__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out__8__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out__8__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out__8__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out__8__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out__8__DR CYREG_PRT6_DR\r
+#define SCSI_Out__8__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out__8__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out__8__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out__8__MASK 0x04u\r
+#define SCSI_Out__8__PC CYREG_PRT6_PC2\r
+#define SCSI_Out__8__PORT 6u\r
+#define SCSI_Out__8__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out__8__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out__8__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out__8__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out__8__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out__8__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out__8__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out__8__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out__8__PS CYREG_PRT6_PS\r
+#define SCSI_Out__8__SHIFT 2\r
+#define SCSI_Out__8__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out__9__AG CYREG_PRT6_AG\r
+#define SCSI_Out__9__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out__9__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out__9__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out__9__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out__9__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out__9__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out__9__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out__9__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out__9__DR CYREG_PRT6_DR\r
+#define SCSI_Out__9__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out__9__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out__9__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out__9__MASK 0x08u\r
+#define SCSI_Out__9__PC CYREG_PRT6_PC3\r
+#define SCSI_Out__9__PORT 6u\r
+#define SCSI_Out__9__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out__9__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out__9__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out__9__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out__9__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out__9__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out__9__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out__9__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out__9__PS CYREG_PRT6_PS\r
+#define SCSI_Out__9__SHIFT 3\r
+#define SCSI_Out__9__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out__ACK__AG CYREG_PRT4_AG\r
+#define SCSI_Out__ACK__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__ACK__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__ACK__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__ACK__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__ACK__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__ACK__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__ACK__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__ACK__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__ACK__DR CYREG_PRT4_DR\r
+#define SCSI_Out__ACK__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__ACK__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__ACK__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__ACK__MASK 0x20u\r
+#define SCSI_Out__ACK__PC CYREG_PRT4_PC5\r
+#define SCSI_Out__ACK__PORT 4u\r
+#define SCSI_Out__ACK__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__ACK__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__ACK__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__ACK__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__ACK__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__ACK__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__ACK__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__ACK__PS CYREG_PRT4_PS\r
+#define SCSI_Out__ACK__SHIFT 5\r
+#define SCSI_Out__ACK__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__ATN__AG CYREG_PRT4_AG\r
+#define SCSI_Out__ATN__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__ATN__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__ATN__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__ATN__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__ATN__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__ATN__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__ATN__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__ATN__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__ATN__DR CYREG_PRT4_DR\r
+#define SCSI_Out__ATN__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__ATN__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__ATN__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__ATN__MASK 0x08u\r
+#define SCSI_Out__ATN__PC CYREG_PRT4_PC3\r
+#define SCSI_Out__ATN__PORT 4u\r
+#define SCSI_Out__ATN__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__ATN__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__ATN__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__ATN__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__ATN__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__ATN__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__ATN__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__ATN__PS CYREG_PRT4_PS\r
+#define SCSI_Out__ATN__SHIFT 3\r
+#define SCSI_Out__ATN__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__BSY__AG CYREG_PRT4_AG\r
+#define SCSI_Out__BSY__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__BSY__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__BSY__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__BSY__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__BSY__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__BSY__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__BSY__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__BSY__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__BSY__DR CYREG_PRT4_DR\r
+#define SCSI_Out__BSY__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__BSY__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__BSY__MASK 0x10u\r
+#define SCSI_Out__BSY__PC CYREG_PRT4_PC4\r
+#define SCSI_Out__BSY__PORT 4u\r
+#define SCSI_Out__BSY__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__BSY__PS CYREG_PRT4_PS\r
+#define SCSI_Out__BSY__SHIFT 4\r
+#define SCSI_Out__BSY__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__CD__AG CYREG_PRT6_AG\r
+#define SCSI_Out__CD__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out__CD__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out__CD__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out__CD__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out__CD__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out__CD__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out__CD__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out__CD__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out__CD__DR CYREG_PRT6_DR\r
+#define SCSI_Out__CD__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out__CD__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out__CD__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out__CD__MASK 0x02u\r
+#define SCSI_Out__CD__PC CYREG_PRT6_PC1\r
+#define SCSI_Out__CD__PORT 6u\r
+#define SCSI_Out__CD__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out__CD__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out__CD__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out__CD__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out__CD__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out__CD__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out__CD__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out__CD__PS CYREG_PRT6_PS\r
+#define SCSI_Out__CD__SHIFT 1\r
+#define SCSI_Out__CD__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out__DBP__AG CYREG_PRT4_AG\r
+#define SCSI_Out__DBP__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__DBP__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__DBP__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__DBP__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__DBP__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__DBP__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__DBP__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__DBP__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__DBP__DR CYREG_PRT4_DR\r
+#define SCSI_Out__DBP__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__DBP__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__DBP__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__DBP__MASK 0x04u\r
+#define SCSI_Out__DBP__PC CYREG_PRT4_PC2\r
+#define SCSI_Out__DBP__PORT 4u\r
+#define SCSI_Out__DBP__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__DBP__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__DBP__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__DBP__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__DBP__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__DBP__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__DBP__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__DBP__PS CYREG_PRT4_PS\r
+#define SCSI_Out__DBP__SHIFT 2\r
+#define SCSI_Out__DBP__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__IO__AG CYREG_PRT6_AG\r
+#define SCSI_Out__IO__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out__IO__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out__IO__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out__IO__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out__IO__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out__IO__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out__IO__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out__IO__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out__IO__DR CYREG_PRT6_DR\r
+#define SCSI_Out__IO__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out__IO__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out__IO__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out__IO__MASK 0x08u\r
+#define SCSI_Out__IO__PC CYREG_PRT6_PC3\r
+#define SCSI_Out__IO__PORT 6u\r
+#define SCSI_Out__IO__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out__IO__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out__IO__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out__IO__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out__IO__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out__IO__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out__IO__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out__IO__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out__IO__PS CYREG_PRT6_PS\r
+#define SCSI_Out__IO__SHIFT 3\r
+#define SCSI_Out__IO__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out__MSG__AG CYREG_PRT4_AG\r
+#define SCSI_Out__MSG__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__MSG__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__MSG__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__MSG__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__MSG__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__MSG__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__MSG__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__MSG__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__MSG__DR CYREG_PRT4_DR\r
+#define SCSI_Out__MSG__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__MSG__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__MSG__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__MSG__MASK 0x80u\r
+#define SCSI_Out__MSG__PC CYREG_PRT4_PC7\r
+#define SCSI_Out__MSG__PORT 4u\r
+#define SCSI_Out__MSG__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__MSG__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__MSG__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__MSG__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__MSG__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__MSG__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__MSG__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__MSG__PS CYREG_PRT4_PS\r
+#define SCSI_Out__MSG__SHIFT 7\r
+#define SCSI_Out__MSG__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__REQ__AG CYREG_PRT6_AG\r
+#define SCSI_Out__REQ__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out__REQ__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out__REQ__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out__REQ__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out__REQ__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out__REQ__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out__REQ__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out__REQ__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out__REQ__DR CYREG_PRT6_DR\r
+#define SCSI_Out__REQ__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out__REQ__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out__REQ__MASK 0x04u\r
+#define SCSI_Out__REQ__PC CYREG_PRT6_PC2\r
+#define SCSI_Out__REQ__PORT 6u\r
+#define SCSI_Out__REQ__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out__REQ__PS CYREG_PRT6_PS\r
+#define SCSI_Out__REQ__SHIFT 2\r
+#define SCSI_Out__REQ__SLW CYREG_PRT6_SLW\r
+#define SCSI_Out__RST__AG CYREG_PRT4_AG\r
+#define SCSI_Out__RST__AMUX CYREG_PRT4_AMUX\r
+#define SCSI_Out__RST__BIE CYREG_PRT4_BIE\r
+#define SCSI_Out__RST__BIT_MASK CYREG_PRT4_BIT_MASK\r
+#define SCSI_Out__RST__BYP CYREG_PRT4_BYP\r
+#define SCSI_Out__RST__CTL CYREG_PRT4_CTL\r
+#define SCSI_Out__RST__DM0 CYREG_PRT4_DM0\r
+#define SCSI_Out__RST__DM1 CYREG_PRT4_DM1\r
+#define SCSI_Out__RST__DM2 CYREG_PRT4_DM2\r
+#define SCSI_Out__RST__DR CYREG_PRT4_DR\r
+#define SCSI_Out__RST__INP_DIS CYREG_PRT4_INP_DIS\r
+#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG\r
+#define SCSI_Out__RST__LCD_EN CYREG_PRT4_LCD_EN\r
+#define SCSI_Out__RST__MASK 0x40u\r
+#define SCSI_Out__RST__PC CYREG_PRT4_PC6\r
+#define SCSI_Out__RST__PORT 4u\r
+#define SCSI_Out__RST__PRT CYREG_PRT4_PRT\r
+#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL\r
+#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN\r
+#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0\r
+#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1\r
+#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0\r
+#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1\r
+#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT\r
+#define SCSI_Out__RST__PS CYREG_PRT4_PS\r
+#define SCSI_Out__RST__SHIFT 6\r
+#define SCSI_Out__RST__SLW CYREG_PRT4_SLW\r
+#define SCSI_Out__SEL__AG CYREG_PRT6_AG\r
+#define SCSI_Out__SEL__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_Out__SEL__BIE CYREG_PRT6_BIE\r
+#define SCSI_Out__SEL__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_Out__SEL__BYP CYREG_PRT6_BYP\r
+#define SCSI_Out__SEL__CTL CYREG_PRT6_CTL\r
+#define SCSI_Out__SEL__DM0 CYREG_PRT6_DM0\r
+#define SCSI_Out__SEL__DM1 CYREG_PRT6_DM1\r
+#define SCSI_Out__SEL__DM2 CYREG_PRT6_DM2\r
+#define SCSI_Out__SEL__DR CYREG_PRT6_DR\r
+#define SCSI_Out__SEL__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_Out__SEL__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_Out__SEL__MASK 0x01u\r
+#define SCSI_Out__SEL__PC CYREG_PRT6_PC0\r
+#define SCSI_Out__SEL__PORT 6u\r
+#define SCSI_Out__SEL__PRT CYREG_PRT6_PRT\r
+#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_Out__SEL__PS CYREG_PRT6_PS\r
+#define SCSI_Out__SEL__SHIFT 0\r
+#define SCSI_Out__SEL__SLW CYREG_PRT6_SLW\r
+\r
+/* SCSI_ID */\r
+#define SCSI_ID__0__MASK 0x80u\r
+#define SCSI_ID__0__PC CYREG_PRT5_PC7\r
+#define SCSI_ID__0__PORT 5u\r
+#define SCSI_ID__0__SHIFT 7\r
+#define SCSI_ID__1__MASK 0x40u\r
+#define SCSI_ID__1__PC CYREG_PRT5_PC6\r
+#define SCSI_ID__1__PORT 5u\r
+#define SCSI_ID__1__SHIFT 6\r
+#define SCSI_ID__2__MASK 0x20u\r
+#define SCSI_ID__2__PC CYREG_PRT5_PC5\r
+#define SCSI_ID__2__PORT 5u\r
+#define SCSI_ID__2__SHIFT 5\r
+#define SCSI_ID__AG CYREG_PRT5_AG\r
+#define SCSI_ID__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_ID__BIE CYREG_PRT5_BIE\r
+#define SCSI_ID__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_ID__BYP CYREG_PRT5_BYP\r
+#define SCSI_ID__CTL CYREG_PRT5_CTL\r
+#define SCSI_ID__DM0 CYREG_PRT5_DM0\r
+#define SCSI_ID__DM1 CYREG_PRT5_DM1\r
+#define SCSI_ID__DM2 CYREG_PRT5_DM2\r
+#define SCSI_ID__DR CYREG_PRT5_DR\r
+#define SCSI_ID__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_ID__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_ID__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_ID__PORT 5u\r
+#define SCSI_ID__PRT CYREG_PRT5_PRT\r
+#define SCSI_ID__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_ID__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_ID__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_ID__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_ID__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_ID__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_ID__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_ID__PS CYREG_PRT5_PS\r
+#define SCSI_ID__SLW CYREG_PRT5_SLW\r
+\r
+/* SCSI_In */\r
+#define SCSI_In__0__AG CYREG_PRT12_AG\r
+#define SCSI_In__0__BIE CYREG_PRT12_BIE\r
+#define SCSI_In__0__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_In__0__BYP CYREG_PRT12_BYP\r
+#define SCSI_In__0__DM0 CYREG_PRT12_DM0\r
+#define SCSI_In__0__DM1 CYREG_PRT12_DM1\r
+#define SCSI_In__0__DM2 CYREG_PRT12_DM2\r
+#define SCSI_In__0__DR CYREG_PRT12_DR\r
+#define SCSI_In__0__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_In__0__MASK 0x10u\r
+#define SCSI_In__0__PC CYREG_PRT12_PC4\r
+#define SCSI_In__0__PORT 12u\r
+#define SCSI_In__0__PRT CYREG_PRT12_PRT\r
+#define SCSI_In__0__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_In__0__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_In__0__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_In__0__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_In__0__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_In__0__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_In__0__PS CYREG_PRT12_PS\r
+#define SCSI_In__0__SHIFT 4\r
+#define SCSI_In__0__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_In__0__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_In__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_In__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_In__0__SLW CYREG_PRT12_SLW\r
+#define SCSI_In__1__AG CYREG_PRT12_AG\r
+#define SCSI_In__1__BIE CYREG_PRT12_BIE\r
+#define SCSI_In__1__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_In__1__BYP CYREG_PRT12_BYP\r
+#define SCSI_In__1__DM0 CYREG_PRT12_DM0\r
+#define SCSI_In__1__DM1 CYREG_PRT12_DM1\r
+#define SCSI_In__1__DM2 CYREG_PRT12_DM2\r
+#define SCSI_In__1__DR CYREG_PRT12_DR\r
+#define SCSI_In__1__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_In__1__MASK 0x20u\r
+#define SCSI_In__1__PC CYREG_PRT12_PC5\r
+#define SCSI_In__1__PORT 12u\r
+#define SCSI_In__1__PRT CYREG_PRT12_PRT\r
+#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_In__1__PS CYREG_PRT12_PS\r
+#define SCSI_In__1__SHIFT 5\r
+#define SCSI_In__1__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_In__1__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_In__1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_In__1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_In__1__SLW CYREG_PRT12_SLW\r
+#define SCSI_In__2__AG CYREG_PRT6_AG\r
+#define SCSI_In__2__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_In__2__BIE CYREG_PRT6_BIE\r
+#define SCSI_In__2__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_In__2__BYP CYREG_PRT6_BYP\r
+#define SCSI_In__2__CTL CYREG_PRT6_CTL\r
+#define SCSI_In__2__DM0 CYREG_PRT6_DM0\r
+#define SCSI_In__2__DM1 CYREG_PRT6_DM1\r
+#define SCSI_In__2__DM2 CYREG_PRT6_DM2\r
+#define SCSI_In__2__DR CYREG_PRT6_DR\r
+#define SCSI_In__2__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_In__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_In__2__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_In__2__MASK 0x10u\r
+#define SCSI_In__2__PC CYREG_PRT6_PC4\r
+#define SCSI_In__2__PORT 6u\r
+#define SCSI_In__2__PRT CYREG_PRT6_PRT\r
+#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_In__2__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_In__2__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_In__2__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_In__2__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_In__2__PS CYREG_PRT6_PS\r
+#define SCSI_In__2__SHIFT 4\r
+#define SCSI_In__2__SLW CYREG_PRT6_SLW\r
+#define SCSI_In__3__AG CYREG_PRT6_AG\r
+#define SCSI_In__3__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_In__3__BIE CYREG_PRT6_BIE\r
+#define SCSI_In__3__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_In__3__BYP CYREG_PRT6_BYP\r
+#define SCSI_In__3__CTL CYREG_PRT6_CTL\r
+#define SCSI_In__3__DM0 CYREG_PRT6_DM0\r
+#define SCSI_In__3__DM1 CYREG_PRT6_DM1\r
+#define SCSI_In__3__DM2 CYREG_PRT6_DM2\r
+#define SCSI_In__3__DR CYREG_PRT6_DR\r
+#define SCSI_In__3__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_In__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_In__3__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_In__3__MASK 0x20u\r
+#define SCSI_In__3__PC CYREG_PRT6_PC5\r
+#define SCSI_In__3__PORT 6u\r
+#define SCSI_In__3__PRT CYREG_PRT6_PRT\r
+#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_In__3__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_In__3__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_In__3__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_In__3__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_In__3__PS CYREG_PRT6_PS\r
+#define SCSI_In__3__SHIFT 5\r
+#define SCSI_In__3__SLW CYREG_PRT6_SLW\r
+#define SCSI_In__4__AG CYREG_PRT6_AG\r
+#define SCSI_In__4__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_In__4__BIE CYREG_PRT6_BIE\r
+#define SCSI_In__4__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_In__4__BYP CYREG_PRT6_BYP\r
+#define SCSI_In__4__CTL CYREG_PRT6_CTL\r
+#define SCSI_In__4__DM0 CYREG_PRT6_DM0\r
+#define SCSI_In__4__DM1 CYREG_PRT6_DM1\r
+#define SCSI_In__4__DM2 CYREG_PRT6_DM2\r
+#define SCSI_In__4__DR CYREG_PRT6_DR\r
+#define SCSI_In__4__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_In__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_In__4__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_In__4__MASK 0x40u\r
+#define SCSI_In__4__PC CYREG_PRT6_PC6\r
+#define SCSI_In__4__PORT 6u\r
+#define SCSI_In__4__PRT CYREG_PRT6_PRT\r
+#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_In__4__PS CYREG_PRT6_PS\r
+#define SCSI_In__4__SHIFT 6\r
+#define SCSI_In__4__SLW CYREG_PRT6_SLW\r
+#define SCSI_In__5__AG CYREG_PRT6_AG\r
+#define SCSI_In__5__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_In__5__BIE CYREG_PRT6_BIE\r
+#define SCSI_In__5__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_In__5__BYP CYREG_PRT6_BYP\r
+#define SCSI_In__5__CTL CYREG_PRT6_CTL\r
+#define SCSI_In__5__DM0 CYREG_PRT6_DM0\r
+#define SCSI_In__5__DM1 CYREG_PRT6_DM1\r
+#define SCSI_In__5__DM2 CYREG_PRT6_DM2\r
+#define SCSI_In__5__DR CYREG_PRT6_DR\r
+#define SCSI_In__5__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_In__5__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_In__5__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_In__5__MASK 0x80u\r
+#define SCSI_In__5__PC CYREG_PRT6_PC7\r
+#define SCSI_In__5__PORT 6u\r
+#define SCSI_In__5__PRT CYREG_PRT6_PRT\r
+#define SCSI_In__5__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_In__5__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_In__5__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_In__5__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_In__5__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_In__5__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_In__5__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_In__5__PS CYREG_PRT6_PS\r
+#define SCSI_In__5__SHIFT 7\r
+#define SCSI_In__5__SLW CYREG_PRT6_SLW\r
+#define SCSI_In__6__AG CYREG_PRT5_AG\r
+#define SCSI_In__6__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__6__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__6__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__6__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__6__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__6__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__6__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__6__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__6__DR CYREG_PRT5_DR\r
+#define SCSI_In__6__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__6__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__6__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__6__MASK 0x01u\r
+#define SCSI_In__6__PC CYREG_PRT5_PC0\r
+#define SCSI_In__6__PORT 5u\r
+#define SCSI_In__6__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__6__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__6__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__6__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__6__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__6__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__6__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__6__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__6__PS CYREG_PRT5_PS\r
+#define SCSI_In__6__SHIFT 0\r
+#define SCSI_In__6__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__7__AG CYREG_PRT5_AG\r
+#define SCSI_In__7__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__7__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__7__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__7__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__7__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__7__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__7__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__7__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__7__DR CYREG_PRT5_DR\r
+#define SCSI_In__7__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__7__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__7__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__7__MASK 0x02u\r
+#define SCSI_In__7__PC CYREG_PRT5_PC1\r
+#define SCSI_In__7__PORT 5u\r
+#define SCSI_In__7__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__7__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__7__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__7__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__7__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__7__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__7__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__7__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__7__PS CYREG_PRT5_PS\r
+#define SCSI_In__7__SHIFT 1\r
+#define SCSI_In__7__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__8__AG CYREG_PRT5_AG\r
+#define SCSI_In__8__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__8__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__8__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__8__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__8__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__8__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__8__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__8__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__8__DR CYREG_PRT5_DR\r
+#define SCSI_In__8__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__8__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__8__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__8__MASK 0x04u\r
+#define SCSI_In__8__PC CYREG_PRT5_PC2\r
+#define SCSI_In__8__PORT 5u\r
+#define SCSI_In__8__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__8__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__8__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__8__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__8__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__8__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__8__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__8__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__8__PS CYREG_PRT5_PS\r
+#define SCSI_In__8__SHIFT 2\r
+#define SCSI_In__8__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__9__AG CYREG_PRT5_AG\r
+#define SCSI_In__9__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__9__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__9__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__9__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__9__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__9__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__9__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__9__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__9__DR CYREG_PRT5_DR\r
+#define SCSI_In__9__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__9__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__9__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__9__MASK 0x08u\r
+#define SCSI_In__9__PC CYREG_PRT5_PC3\r
+#define SCSI_In__9__PORT 5u\r
+#define SCSI_In__9__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__9__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__9__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__9__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__9__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__9__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__9__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__9__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__9__PS CYREG_PRT5_PS\r
+#define SCSI_In__9__SHIFT 3\r
+#define SCSI_In__9__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__ACK__AG CYREG_PRT6_AG\r
+#define SCSI_In__ACK__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_In__ACK__BIE CYREG_PRT6_BIE\r
+#define SCSI_In__ACK__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_In__ACK__BYP CYREG_PRT6_BYP\r
+#define SCSI_In__ACK__CTL CYREG_PRT6_CTL\r
+#define SCSI_In__ACK__DM0 CYREG_PRT6_DM0\r
+#define SCSI_In__ACK__DM1 CYREG_PRT6_DM1\r
+#define SCSI_In__ACK__DM2 CYREG_PRT6_DM2\r
+#define SCSI_In__ACK__DR CYREG_PRT6_DR\r
+#define SCSI_In__ACK__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_In__ACK__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_In__ACK__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_In__ACK__MASK 0x20u\r
+#define SCSI_In__ACK__PC CYREG_PRT6_PC5\r
+#define SCSI_In__ACK__PORT 6u\r
+#define SCSI_In__ACK__PRT CYREG_PRT6_PRT\r
+#define SCSI_In__ACK__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_In__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_In__ACK__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_In__ACK__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_In__ACK__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_In__ACK__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_In__ACK__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_In__ACK__PS CYREG_PRT6_PS\r
+#define SCSI_In__ACK__SHIFT 5\r
+#define SCSI_In__ACK__SLW CYREG_PRT6_SLW\r
+#define SCSI_In__ATN__AG CYREG_PRT12_AG\r
+#define SCSI_In__ATN__BIE CYREG_PRT12_BIE\r
+#define SCSI_In__ATN__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_In__ATN__BYP CYREG_PRT12_BYP\r
+#define SCSI_In__ATN__DM0 CYREG_PRT12_DM0\r
+#define SCSI_In__ATN__DM1 CYREG_PRT12_DM1\r
+#define SCSI_In__ATN__DM2 CYREG_PRT12_DM2\r
+#define SCSI_In__ATN__DR CYREG_PRT12_DR\r
+#define SCSI_In__ATN__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_In__ATN__MASK 0x20u\r
+#define SCSI_In__ATN__PC CYREG_PRT12_PC5\r
+#define SCSI_In__ATN__PORT 12u\r
+#define SCSI_In__ATN__PRT CYREG_PRT12_PRT\r
+#define SCSI_In__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_In__ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_In__ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_In__ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_In__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_In__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_In__ATN__PS CYREG_PRT12_PS\r
+#define SCSI_In__ATN__SHIFT 5\r
+#define SCSI_In__ATN__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_In__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_In__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_In__ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_In__ATN__SLW CYREG_PRT12_SLW\r
+#define SCSI_In__BSY__AG CYREG_PRT6_AG\r
+#define SCSI_In__BSY__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_In__BSY__BIE CYREG_PRT6_BIE\r
+#define SCSI_In__BSY__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_In__BSY__BYP CYREG_PRT6_BYP\r
+#define SCSI_In__BSY__CTL CYREG_PRT6_CTL\r
+#define SCSI_In__BSY__DM0 CYREG_PRT6_DM0\r
+#define SCSI_In__BSY__DM1 CYREG_PRT6_DM1\r
+#define SCSI_In__BSY__DM2 CYREG_PRT6_DM2\r
+#define SCSI_In__BSY__DR CYREG_PRT6_DR\r
+#define SCSI_In__BSY__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_In__BSY__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_In__BSY__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_In__BSY__MASK 0x10u\r
+#define SCSI_In__BSY__PC CYREG_PRT6_PC4\r
+#define SCSI_In__BSY__PORT 6u\r
+#define SCSI_In__BSY__PRT CYREG_PRT6_PRT\r
+#define SCSI_In__BSY__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_In__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_In__BSY__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_In__BSY__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_In__BSY__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_In__BSY__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_In__BSY__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_In__BSY__PS CYREG_PRT6_PS\r
+#define SCSI_In__BSY__SHIFT 4\r
+#define SCSI_In__BSY__SLW CYREG_PRT6_SLW\r
+#define SCSI_In__CD__AG CYREG_PRT5_AG\r
+#define SCSI_In__CD__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__CD__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__CD__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__CD__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__CD__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__CD__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__CD__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__CD__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__CD__DR CYREG_PRT5_DR\r
+#define SCSI_In__CD__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__CD__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__CD__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__CD__MASK 0x02u\r
+#define SCSI_In__CD__PC CYREG_PRT5_PC1\r
+#define SCSI_In__CD__PORT 5u\r
+#define SCSI_In__CD__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__CD__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__CD__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__CD__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__CD__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__CD__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__CD__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__CD__PS CYREG_PRT5_PS\r
+#define SCSI_In__CD__SHIFT 1\r
+#define SCSI_In__CD__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__DBP__AG CYREG_PRT12_AG\r
+#define SCSI_In__DBP__BIE CYREG_PRT12_BIE\r
+#define SCSI_In__DBP__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define SCSI_In__DBP__BYP CYREG_PRT12_BYP\r
+#define SCSI_In__DBP__DM0 CYREG_PRT12_DM0\r
+#define SCSI_In__DBP__DM1 CYREG_PRT12_DM1\r
+#define SCSI_In__DBP__DM2 CYREG_PRT12_DM2\r
+#define SCSI_In__DBP__DR CYREG_PRT12_DR\r
+#define SCSI_In__DBP__INP_DIS CYREG_PRT12_INP_DIS\r
+#define SCSI_In__DBP__MASK 0x10u\r
+#define SCSI_In__DBP__PC CYREG_PRT12_PC4\r
+#define SCSI_In__DBP__PORT 12u\r
+#define SCSI_In__DBP__PRT CYREG_PRT12_PRT\r
+#define SCSI_In__DBP__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define SCSI_In__DBP__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define SCSI_In__DBP__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define SCSI_In__DBP__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define SCSI_In__DBP__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define SCSI_In__DBP__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define SCSI_In__DBP__PS CYREG_PRT12_PS\r
+#define SCSI_In__DBP__SHIFT 4\r
+#define SCSI_In__DBP__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define SCSI_In__DBP__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define SCSI_In__DBP__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define SCSI_In__DBP__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define SCSI_In__DBP__SLW CYREG_PRT12_SLW\r
+#define SCSI_In__IO__AG CYREG_PRT5_AG\r
+#define SCSI_In__IO__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__IO__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__IO__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__IO__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__IO__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__IO__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__IO__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__IO__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__IO__DR CYREG_PRT5_DR\r
+#define SCSI_In__IO__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__IO__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__IO__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__IO__MASK 0x08u\r
+#define SCSI_In__IO__PC CYREG_PRT5_PC3\r
+#define SCSI_In__IO__PORT 5u\r
+#define SCSI_In__IO__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__IO__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__IO__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__IO__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__IO__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__IO__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__IO__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__IO__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__IO__PS CYREG_PRT5_PS\r
+#define SCSI_In__IO__SHIFT 3\r
+#define SCSI_In__IO__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__MSG__AG CYREG_PRT6_AG\r
+#define SCSI_In__MSG__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_In__MSG__BIE CYREG_PRT6_BIE\r
+#define SCSI_In__MSG__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_In__MSG__BYP CYREG_PRT6_BYP\r
+#define SCSI_In__MSG__CTL CYREG_PRT6_CTL\r
+#define SCSI_In__MSG__DM0 CYREG_PRT6_DM0\r
+#define SCSI_In__MSG__DM1 CYREG_PRT6_DM1\r
+#define SCSI_In__MSG__DM2 CYREG_PRT6_DM2\r
+#define SCSI_In__MSG__DR CYREG_PRT6_DR\r
+#define SCSI_In__MSG__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_In__MSG__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_In__MSG__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_In__MSG__MASK 0x80u\r
+#define SCSI_In__MSG__PC CYREG_PRT6_PC7\r
+#define SCSI_In__MSG__PORT 6u\r
+#define SCSI_In__MSG__PRT CYREG_PRT6_PRT\r
+#define SCSI_In__MSG__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_In__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_In__MSG__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_In__MSG__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_In__MSG__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_In__MSG__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_In__MSG__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_In__MSG__PS CYREG_PRT6_PS\r
+#define SCSI_In__MSG__SHIFT 7\r
+#define SCSI_In__MSG__SLW CYREG_PRT6_SLW\r
+#define SCSI_In__REQ__AG CYREG_PRT5_AG\r
+#define SCSI_In__REQ__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__REQ__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__REQ__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__REQ__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__REQ__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__REQ__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__REQ__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__REQ__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__REQ__DR CYREG_PRT5_DR\r
+#define SCSI_In__REQ__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__REQ__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__REQ__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__REQ__MASK 0x04u\r
+#define SCSI_In__REQ__PC CYREG_PRT5_PC2\r
+#define SCSI_In__REQ__PORT 5u\r
+#define SCSI_In__REQ__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__REQ__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__REQ__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__REQ__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__REQ__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__REQ__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__REQ__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__REQ__PS CYREG_PRT5_PS\r
+#define SCSI_In__REQ__SHIFT 2\r
+#define SCSI_In__REQ__SLW CYREG_PRT5_SLW\r
+#define SCSI_In__RST__AG CYREG_PRT6_AG\r
+#define SCSI_In__RST__AMUX CYREG_PRT6_AMUX\r
+#define SCSI_In__RST__BIE CYREG_PRT6_BIE\r
+#define SCSI_In__RST__BIT_MASK CYREG_PRT6_BIT_MASK\r
+#define SCSI_In__RST__BYP CYREG_PRT6_BYP\r
+#define SCSI_In__RST__CTL CYREG_PRT6_CTL\r
+#define SCSI_In__RST__DM0 CYREG_PRT6_DM0\r
+#define SCSI_In__RST__DM1 CYREG_PRT6_DM1\r
+#define SCSI_In__RST__DM2 CYREG_PRT6_DM2\r
+#define SCSI_In__RST__DR CYREG_PRT6_DR\r
+#define SCSI_In__RST__INP_DIS CYREG_PRT6_INP_DIS\r
+#define SCSI_In__RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG\r
+#define SCSI_In__RST__LCD_EN CYREG_PRT6_LCD_EN\r
+#define SCSI_In__RST__MASK 0x40u\r
+#define SCSI_In__RST__PC CYREG_PRT6_PC6\r
+#define SCSI_In__RST__PORT 6u\r
+#define SCSI_In__RST__PRT CYREG_PRT6_PRT\r
+#define SCSI_In__RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL\r
+#define SCSI_In__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN\r
+#define SCSI_In__RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0\r
+#define SCSI_In__RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1\r
+#define SCSI_In__RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0\r
+#define SCSI_In__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1\r
+#define SCSI_In__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT\r
+#define SCSI_In__RST__PS CYREG_PRT6_PS\r
+#define SCSI_In__RST__SHIFT 6\r
+#define SCSI_In__RST__SLW CYREG_PRT6_SLW\r
+#define SCSI_In__SEL__AG CYREG_PRT5_AG\r
+#define SCSI_In__SEL__AMUX CYREG_PRT5_AMUX\r
+#define SCSI_In__SEL__BIE CYREG_PRT5_BIE\r
+#define SCSI_In__SEL__BIT_MASK CYREG_PRT5_BIT_MASK\r
+#define SCSI_In__SEL__BYP CYREG_PRT5_BYP\r
+#define SCSI_In__SEL__CTL CYREG_PRT5_CTL\r
+#define SCSI_In__SEL__DM0 CYREG_PRT5_DM0\r
+#define SCSI_In__SEL__DM1 CYREG_PRT5_DM1\r
+#define SCSI_In__SEL__DM2 CYREG_PRT5_DM2\r
+#define SCSI_In__SEL__DR CYREG_PRT5_DR\r
+#define SCSI_In__SEL__INP_DIS CYREG_PRT5_INP_DIS\r
+#define SCSI_In__SEL__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG\r
+#define SCSI_In__SEL__LCD_EN CYREG_PRT5_LCD_EN\r
+#define SCSI_In__SEL__MASK 0x01u\r
+#define SCSI_In__SEL__PC CYREG_PRT5_PC0\r
+#define SCSI_In__SEL__PORT 5u\r
+#define SCSI_In__SEL__PRT CYREG_PRT5_PRT\r
+#define SCSI_In__SEL__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL\r
+#define SCSI_In__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN\r
+#define SCSI_In__SEL__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0\r
+#define SCSI_In__SEL__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1\r
+#define SCSI_In__SEL__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0\r
+#define SCSI_In__SEL__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1\r
+#define SCSI_In__SEL__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT\r
+#define SCSI_In__SEL__PS CYREG_PRT5_PS\r
+#define SCSI_In__SEL__SHIFT 0\r
+#define SCSI_In__SEL__SLW CYREG_PRT5_SLW\r
+\r
+/* SD_DAT1 */\r
+#define SD_DAT1__0__MASK 0x20u\r
+#define SD_DAT1__0__PC CYREG_PRT3_PC5\r
+#define SD_DAT1__0__PORT 3u\r
+#define SD_DAT1__0__SHIFT 5\r
+#define SD_DAT1__AG CYREG_PRT3_AG\r
+#define SD_DAT1__AMUX CYREG_PRT3_AMUX\r
+#define SD_DAT1__BIE CYREG_PRT3_BIE\r
+#define SD_DAT1__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_DAT1__BYP CYREG_PRT3_BYP\r
+#define SD_DAT1__CTL CYREG_PRT3_CTL\r
+#define SD_DAT1__DM0 CYREG_PRT3_DM0\r
+#define SD_DAT1__DM1 CYREG_PRT3_DM1\r
+#define SD_DAT1__DM2 CYREG_PRT3_DM2\r
+#define SD_DAT1__DR CYREG_PRT3_DR\r
+#define SD_DAT1__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_DAT1__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_DAT1__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_DAT1__MASK 0x20u\r
+#define SD_DAT1__PORT 3u\r
+#define SD_DAT1__PRT CYREG_PRT3_PRT\r
+#define SD_DAT1__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_DAT1__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_DAT1__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_DAT1__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_DAT1__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_DAT1__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_DAT1__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_DAT1__PS CYREG_PRT3_PS\r
+#define SD_DAT1__SHIFT 5\r
+#define SD_DAT1__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_DAT2 */\r
+#define SD_DAT2__0__MASK 0x01u\r
+#define SD_DAT2__0__PC CYREG_PRT3_PC0\r
+#define SD_DAT2__0__PORT 3u\r
+#define SD_DAT2__0__SHIFT 0\r
+#define SD_DAT2__AG CYREG_PRT3_AG\r
+#define SD_DAT2__AMUX CYREG_PRT3_AMUX\r
+#define SD_DAT2__BIE CYREG_PRT3_BIE\r
+#define SD_DAT2__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_DAT2__BYP CYREG_PRT3_BYP\r
+#define SD_DAT2__CTL CYREG_PRT3_CTL\r
+#define SD_DAT2__DM0 CYREG_PRT3_DM0\r
+#define SD_DAT2__DM1 CYREG_PRT3_DM1\r
+#define SD_DAT2__DM2 CYREG_PRT3_DM2\r
+#define SD_DAT2__DR CYREG_PRT3_DR\r
+#define SD_DAT2__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_DAT2__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_DAT2__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_DAT2__MASK 0x01u\r
+#define SD_DAT2__PORT 3u\r
+#define SD_DAT2__PRT CYREG_PRT3_PRT\r
+#define SD_DAT2__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_DAT2__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_DAT2__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_DAT2__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_DAT2__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_DAT2__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_DAT2__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_DAT2__PS CYREG_PRT3_PS\r
+#define SD_DAT2__SHIFT 0\r
+#define SD_DAT2__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_MISO */\r
+#define SD_MISO__0__MASK 0x10u\r
+#define SD_MISO__0__PC CYREG_PRT3_PC4\r
+#define SD_MISO__0__PORT 3u\r
+#define SD_MISO__0__SHIFT 4\r
+#define SD_MISO__AG CYREG_PRT3_AG\r
+#define SD_MISO__AMUX CYREG_PRT3_AMUX\r
+#define SD_MISO__BIE CYREG_PRT3_BIE\r
+#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_MISO__BYP CYREG_PRT3_BYP\r
+#define SD_MISO__CTL CYREG_PRT3_CTL\r
+#define SD_MISO__DM0 CYREG_PRT3_DM0\r
+#define SD_MISO__DM1 CYREG_PRT3_DM1\r
+#define SD_MISO__DM2 CYREG_PRT3_DM2\r
+#define SD_MISO__DR CYREG_PRT3_DR\r
+#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_MISO__MASK 0x10u\r
+#define SD_MISO__PORT 3u\r
+#define SD_MISO__PRT CYREG_PRT3_PRT\r
+#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_MISO__PS CYREG_PRT3_PS\r
+#define SD_MISO__SHIFT 4\r
+#define SD_MISO__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_MOSI */\r
+#define SD_MOSI__0__MASK 0x04u\r
+#define SD_MOSI__0__PC CYREG_PRT3_PC2\r
+#define SD_MOSI__0__PORT 3u\r
+#define SD_MOSI__0__SHIFT 2\r
+#define SD_MOSI__AG CYREG_PRT3_AG\r
+#define SD_MOSI__AMUX CYREG_PRT3_AMUX\r
+#define SD_MOSI__BIE CYREG_PRT3_BIE\r
+#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_MOSI__BYP CYREG_PRT3_BYP\r
+#define SD_MOSI__CTL CYREG_PRT3_CTL\r
+#define SD_MOSI__DM0 CYREG_PRT3_DM0\r
+#define SD_MOSI__DM1 CYREG_PRT3_DM1\r
+#define SD_MOSI__DM2 CYREG_PRT3_DM2\r
+#define SD_MOSI__DR CYREG_PRT3_DR\r
+#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_MOSI__MASK 0x04u\r
+#define SD_MOSI__PORT 3u\r
+#define SD_MOSI__PRT CYREG_PRT3_PRT\r
+#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_MOSI__PS CYREG_PRT3_PS\r
+#define SD_MOSI__SHIFT 2\r
+#define SD_MOSI__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_SCK */\r
+#define SD_SCK__0__MASK 0x08u\r
+#define SD_SCK__0__PC CYREG_PRT3_PC3\r
+#define SD_SCK__0__PORT 3u\r
+#define SD_SCK__0__SHIFT 3\r
+#define SD_SCK__AG CYREG_PRT3_AG\r
+#define SD_SCK__AMUX CYREG_PRT3_AMUX\r
+#define SD_SCK__BIE CYREG_PRT3_BIE\r
+#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_SCK__BYP CYREG_PRT3_BYP\r
+#define SD_SCK__CTL CYREG_PRT3_CTL\r
+#define SD_SCK__DM0 CYREG_PRT3_DM0\r
+#define SD_SCK__DM1 CYREG_PRT3_DM1\r
+#define SD_SCK__DM2 CYREG_PRT3_DM2\r
+#define SD_SCK__DR CYREG_PRT3_DR\r
+#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_SCK__MASK 0x08u\r
+#define SD_SCK__PORT 3u\r
+#define SD_SCK__PRT CYREG_PRT3_PRT\r
+#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_SCK__PS CYREG_PRT3_PS\r
+#define SD_SCK__SHIFT 3\r
+#define SD_SCK__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_CD */\r
+#define SD_CD__0__MASK 0x40u\r
+#define SD_CD__0__PC CYREG_PRT3_PC6\r
+#define SD_CD__0__PORT 3u\r
+#define SD_CD__0__SHIFT 6\r
+#define SD_CD__AG CYREG_PRT3_AG\r
+#define SD_CD__AMUX CYREG_PRT3_AMUX\r
+#define SD_CD__BIE CYREG_PRT3_BIE\r
+#define SD_CD__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_CD__BYP CYREG_PRT3_BYP\r
+#define SD_CD__CTL CYREG_PRT3_CTL\r
+#define SD_CD__DM0 CYREG_PRT3_DM0\r
+#define SD_CD__DM1 CYREG_PRT3_DM1\r
+#define SD_CD__DM2 CYREG_PRT3_DM2\r
+#define SD_CD__DR CYREG_PRT3_DR\r
+#define SD_CD__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_CD__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_CD__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_CD__MASK 0x40u\r
+#define SD_CD__PORT 3u\r
+#define SD_CD__PRT CYREG_PRT3_PRT\r
+#define SD_CD__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_CD__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_CD__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_CD__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_CD__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_CD__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_CD__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_CD__PS CYREG_PRT3_PS\r
+#define SD_CD__SHIFT 6\r
+#define SD_CD__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_CS */\r
+#define SD_CS__0__MASK 0x02u\r
+#define SD_CS__0__PC CYREG_PRT3_PC1\r
+#define SD_CS__0__PORT 3u\r
+#define SD_CS__0__SHIFT 1\r
+#define SD_CS__AG CYREG_PRT3_AG\r
+#define SD_CS__AMUX CYREG_PRT3_AMUX\r
+#define SD_CS__BIE CYREG_PRT3_BIE\r
+#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_CS__BYP CYREG_PRT3_BYP\r
+#define SD_CS__CTL CYREG_PRT3_CTL\r
+#define SD_CS__DM0 CYREG_PRT3_DM0\r
+#define SD_CS__DM1 CYREG_PRT3_DM1\r
+#define SD_CS__DM2 CYREG_PRT3_DM2\r
+#define SD_CS__DR CYREG_PRT3_DR\r
+#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_CS__MASK 0x02u\r
+#define SD_CS__PORT 3u\r
+#define SD_CS__PRT CYREG_PRT3_PRT\r
+#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_CS__PS CYREG_PRT3_PS\r
+#define SD_CS__SHIFT 1\r
+#define SD_CS__SLW CYREG_PRT3_SLW\r
+\r
+/* SD_WP */\r
+#define SD_WP__0__MASK 0x80u\r
+#define SD_WP__0__PC CYREG_PRT3_PC7\r
+#define SD_WP__0__PORT 3u\r
+#define SD_WP__0__SHIFT 7\r
+#define SD_WP__AG CYREG_PRT3_AG\r
+#define SD_WP__AMUX CYREG_PRT3_AMUX\r
+#define SD_WP__BIE CYREG_PRT3_BIE\r
+#define SD_WP__BIT_MASK CYREG_PRT3_BIT_MASK\r
+#define SD_WP__BYP CYREG_PRT3_BYP\r
+#define SD_WP__CTL CYREG_PRT3_CTL\r
+#define SD_WP__DM0 CYREG_PRT3_DM0\r
+#define SD_WP__DM1 CYREG_PRT3_DM1\r
+#define SD_WP__DM2 CYREG_PRT3_DM2\r
+#define SD_WP__DR CYREG_PRT3_DR\r
+#define SD_WP__INP_DIS CYREG_PRT3_INP_DIS\r
+#define SD_WP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG\r
+#define SD_WP__LCD_EN CYREG_PRT3_LCD_EN\r
+#define SD_WP__MASK 0x80u\r
+#define SD_WP__PORT 3u\r
+#define SD_WP__PRT CYREG_PRT3_PRT\r
+#define SD_WP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL\r
+#define SD_WP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN\r
+#define SD_WP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0\r
+#define SD_WP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1\r
+#define SD_WP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0\r
+#define SD_WP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1\r
+#define SD_WP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT\r
+#define SD_WP__PS CYREG_PRT3_PS\r
+#define SD_WP__SHIFT 7\r
+#define SD_WP__SLW CYREG_PRT3_SLW\r
+\r
+/* LED1 */\r
+#define LED1__0__MASK 0x08u\r
+#define LED1__0__PC CYREG_PRT12_PC3\r
+#define LED1__0__PORT 12u\r
+#define LED1__0__SHIFT 3\r
+#define LED1__AG CYREG_PRT12_AG\r
+#define LED1__BIE CYREG_PRT12_BIE\r
+#define LED1__BIT_MASK CYREG_PRT12_BIT_MASK\r
+#define LED1__BYP CYREG_PRT12_BYP\r
+#define LED1__DM0 CYREG_PRT12_DM0\r
+#define LED1__DM1 CYREG_PRT12_DM1\r
+#define LED1__DM2 CYREG_PRT12_DM2\r
+#define LED1__DR CYREG_PRT12_DR\r
+#define LED1__INP_DIS CYREG_PRT12_INP_DIS\r
+#define LED1__MASK 0x08u\r
+#define LED1__PORT 12u\r
+#define LED1__PRT CYREG_PRT12_PRT\r
+#define LED1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN\r
+#define LED1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0\r
+#define LED1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1\r
+#define LED1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0\r
+#define LED1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1\r
+#define LED1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT\r
+#define LED1__PS CYREG_PRT12_PS\r
+#define LED1__SHIFT 3\r
+#define LED1__SIO_CFG CYREG_PRT12_SIO_CFG\r
+#define LED1__SIO_DIFF CYREG_PRT12_SIO_DIFF\r
+#define LED1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN\r
+#define LED1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ\r
+#define LED1__SLW CYREG_PRT12_SLW\r
+\r
+/* Miscellaneous */\r
+/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */\r
+#define CYDEV_DEBUGGING_DPS_SWD_SWV 6\r
+#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0\r
+#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0\r
+#define CYDEV_CONFIG_FASTBOOT_ENABLED 1\r
+#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u\r
+#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u\r
+#define CYDEV_CHIP_MEMBER_5B 4u\r
+#define CYDEV_CHIP_FAMILY_PSOC5 3u\r
+#define CYDEV_CHIP_DIE_PSOC5LP 4u\r
+#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_DIE_PSOC5LP\r
+#define BCLK__BUS_CLK__HZ 64000000U\r
+#define BCLK__BUS_CLK__KHZ 64000U\r
+#define BCLK__BUS_CLK__MHZ 64U\r
+#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT\r
+#define CYDEV_CHIP_DIE_LEOPARD 1u\r
+#define CYDEV_CHIP_DIE_PANTHER 3u\r
+#define CYDEV_CHIP_DIE_PSOC4A 2u\r
+#define CYDEV_CHIP_DIE_UNKNOWN 0u\r
+#define CYDEV_CHIP_FAMILY_PSOC3 1u\r
+#define CYDEV_CHIP_FAMILY_PSOC4 2u\r
+#define CYDEV_CHIP_FAMILY_UNKNOWN 0u\r
+#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5\r
+#define CYDEV_CHIP_JTAG_ID 0x2E12F069u\r
+#define CYDEV_CHIP_MEMBER_3A 1u\r
+#define CYDEV_CHIP_MEMBER_4A 2u\r
+#define CYDEV_CHIP_MEMBER_5A 3u\r
+#define CYDEV_CHIP_MEMBER_UNKNOWN 0u\r
+#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B\r
+#define CYDEV_CHIP_REVISION_3A_ES1 0u\r
+#define CYDEV_CHIP_REVISION_3A_ES2 1u\r
+#define CYDEV_CHIP_REVISION_3A_ES3 3u\r
+#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u\r
+#define CYDEV_CHIP_REVISION_4A_ES0 17u\r
+#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u\r
+#define CYDEV_CHIP_REVISION_5A_ES0 0u\r
+#define CYDEV_CHIP_REVISION_5A_ES1 1u\r
+#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u\r
+#define CYDEV_CHIP_REVISION_5B_ES0 0u\r
+#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION\r
+#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REV_PSOC5LP_PRODUCTION\r
+#define CYDEV_CHIP_REV_LEOPARD_ES1 0u\r
+#define CYDEV_CHIP_REV_LEOPARD_ES2 1u\r
+#define CYDEV_CHIP_REV_LEOPARD_ES3 3u\r
+#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u\r
+#define CYDEV_CHIP_REV_PANTHER_ES0 0u\r
+#define CYDEV_CHIP_REV_PANTHER_ES1 1u\r
+#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u\r
+#define CYDEV_CHIP_REV_PSOC4A_ES0 17u\r
+#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u\r
+#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u\r
+#define CYDEV_CONFIGURATION_COMPRESSED 1\r
+#define CYDEV_CONFIGURATION_DMA 0\r
+#define CYDEV_CONFIGURATION_ECC 1\r
+#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED\r
+#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED\r
+#define CYDEV_CONFIGURATION_MODE_DMA 2\r
+#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1\r
+#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
+#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1\r
+#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2\r
+#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV\r
+#define CYDEV_DEBUGGING_DPS_Disable 3\r
+#define CYDEV_DEBUGGING_DPS_JTAG_4 1\r
+#define CYDEV_DEBUGGING_DPS_JTAG_5 0\r
+#define CYDEV_DEBUGGING_DPS_SWD 2\r
+#define CYDEV_DEBUGGING_ENABLE 1\r
+#define CYDEV_DEBUGGING_REQXRES 1\r
+#define CYDEV_DEBUGGING_XRES 0\r
+#define CYDEV_DEBUG_ENABLE_MASK 0x20u\r
+#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG\r
+#define CYDEV_DMA_CHANNELS_AVAILABLE 24u\r
+#define CYDEV_ECC_ENABLE 0\r
+#define CYDEV_HEAP_SIZE 0x1000\r
+#define CYDEV_INSTRUCT_CACHE_ENABLED 1\r
+#define CYDEV_INTR_RISING 0x00000003u\r
+#define CYDEV_PROJ_TYPE 0\r
+#define CYDEV_PROJ_TYPE_BOOTLOADER 1\r
+#define CYDEV_PROJ_TYPE_LOADABLE 2\r
+#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3\r
+#define CYDEV_PROJ_TYPE_STANDARD 0\r
+#define CYDEV_PROTECTION_ENABLE 0\r
+#define CYDEV_STACK_SIZE 0x4000\r
+#define CYDEV_USE_BUNDLED_CMSIS 1\r
+#define CYDEV_VARIABLE_VDDA 0\r
+#define CYDEV_VDDA 5.0\r
+#define CYDEV_VDDA_MV 5000\r
+#define CYDEV_VDDD 5.0\r
+#define CYDEV_VDDD_MV 5000\r
+#define CYDEV_VDDIO0 5.0\r
+#define CYDEV_VDDIO0_MV 5000\r
+#define CYDEV_VDDIO1 5.0\r
+#define CYDEV_VDDIO1_MV 5000\r
+#define CYDEV_VDDIO2 5.0\r
+#define CYDEV_VDDIO2_MV 5000\r
+#define CYDEV_VDDIO3 3.3\r
+#define CYDEV_VDDIO3_MV 3300\r
+#define CYDEV_VIO0 5\r
+#define CYDEV_VIO0_MV 5000\r
+#define CYDEV_VIO1 5\r
+#define CYDEV_VIO1_MV 5000\r
+#define CYDEV_VIO2 5\r
+#define CYDEV_VIO2_MV 5000\r
+#define CYDEV_VIO3 3.3\r
+#define CYDEV_VIO3_MV 3300\r
+#define DMA_CHANNELS_USED__MASK0 0x00000000u\r
+#define CYDEV_BOOTLOADER_ENABLE 0\r
+\r
+#endif /* INCLUDED_CYFITTER_H */\r
--- /dev/null
+/*******************************************************************************\r
+* FILENAME: cyfitter_cfg.c\r
+* PSoC Creator 2.2 Component Pack 6\r
+*\r
+* Description:\r
+* This file is automatically generated by PSoC Creator with device \r
+* initialization code. Except for the user defined sections in\r
+* CyClockStartupError(), this file should not be modified.\r
+*\r
+********************************************************************************\r
+* Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+********************************************************************************/\r
+\r
+#include <string.h>\r
+#include <cytypes.h>\r
+#include <cydevice_trm.h>\r
+#include <cyfitter.h>\r
+#include <CyLib.h>\r
+#include <cyfitter_cfg.h>\r
+\r
+/* Clock startup error codes */\r
+#define CYCLOCKSTART_NO_ERROR 0u\r
+#define CYCLOCKSTART_XTAL_ERROR 1u\r
+#define CYCLOCKSTART_32KHZ_ERROR 2u\r
+#define CYCLOCKSTART_PLL_ERROR 3u\r
+\r
+#ifdef CY_NEED_CYCLOCKSTARTUPERROR\r
+/*******************************************************************************\r
+* Function Name: CyClockStartupError\r
+********************************************************************************\r
+* Summary:\r
+* If an error is encountered during clock configuration (crystal startup error,\r
+* PLL lock error, etc.), the system will end up here. Unless reimplemented by\r
+* the customer, this function will stop in an infinite loop.\r
+*\r
+* Parameters:\r
+* void\r
+*\r
+* Return:\r
+* void\r
+*\r
+*******************************************************************************/\r
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
+__attribute__ ((unused))\r
+#endif\r
+static void CyClockStartupError(uint8 errorCode);\r
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
+__attribute__ ((unused))\r
+#endif\r
+static void CyClockStartupError(uint8 errorCode)\r
+{\r
+ /* To remove the compiler warning if errorCode not used. */\r
+ errorCode = errorCode;\r
+\r
+ /* `#START CyClockStartupError` */\r
+\r
+ /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */\r
+ /* we will end up here to allow the customer to implement something to */\r
+ /* deal with the clock condition. */\r
+\r
+ /* `#END` */\r
+\r
+ /* If nothing else, stop here since the clocks have not started */\r
+ /* correctly. */\r
+ while(1) {}\r
+}\r
+#endif\r
+\r
+\r
+#if defined(__GNUC__) || defined(__ARMCC_VERSION)\r
+ #define CYPACKED __attribute__ ((packed))\r
+ #define CYALIGNED __attribute__ ((aligned))\r
+ \r
+ #if defined(__ARMCC_VERSION)\r
+ #define CY_CFG_MEMORY_BARRIER() __memory_changed()\r
+ #else\r
+ #define CY_CFG_MEMORY_BARRIER() __sync_synchronize()\r
+ #endif\r
+ \r
+\r
+ __attribute__ ((unused))\r
+ static void CYMEMZERO(void *s, size_t n);\r
+ __attribute__ ((unused))\r
+ static void CYMEMZERO(void *s, size_t n)\r
+ {\r
+ (void)memset(s, 0, n);\r
+ }\r
+ __attribute__ ((unused))\r
+ static void CYCONFIGCPY(void *dest, const void *src, size_t n);\r
+ __attribute__ ((unused))\r
+ static void CYCONFIGCPY(void *dest, const void *src, size_t n)\r
+ {\r
+ (void)memcpy(dest, src, n);\r
+ }\r
+ __attribute__ ((unused))\r
+ static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n);\r
+ __attribute__ ((unused))\r
+ static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)\r
+ {\r
+ (void)memcpy(dest, src, n);\r
+ }\r
+#else\r
+ #error Unsupported toolchain\r
+#endif\r
+\r
+#define CY_CFG_BASE_ADDR_COUNT 16u\r
+typedef struct\r
+{\r
+ uint8 offset;\r
+ uint8 value;\r
+} CYPACKED cy_cfg_addrvalue_t;\r
+\r
+#define cy_cfg_addr_table ((const uint32 CYFAR *)0x48000000u)\r
+#define cy_cfg_data_table ((const cy_cfg_addrvalue_t CYFAR *)0x48000040u)\r
+\r
+/* UDB_1_1_0_CONFIG Address: CYDEV_UCFG_B1_P3_U1_BASE Size (bytes): 128 */\r
+#define BS_UDB_1_1_0_CONFIG_VAL ((const uint8 CYFAR *)0x480002CCu)\r
+\r
+/* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */\r
+#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x4800034Cu)\r
+\r
+/* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */\r
+#define BS_IOPINS0_7_VAL ((const uint8 CYFAR *)0x48000354u)\r
+\r
+/* IOPINS1_7 Address: CYREG_PRT12_DR + 0x0000000Bu Size (bytes): 5 */\r
+#define BS_IOPINS1_7_VAL ((const uint8 CYFAR *)0x48000360u)\r
+\r
+/* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */\r
+#define BS_IOPINS0_2_VAL ((const uint8 CYFAR *)0x48000368u)\r
+\r
+/* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */\r
+#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x48000370u)\r
+\r
+/* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */\r
+#define BS_IOPINS0_4_VAL ((const uint8 CYFAR *)0x4800037Cu)\r
+\r
+/* IOPINS0_5 Address: CYREG_PRT5_DR Size (bytes): 10 */\r
+#define BS_IOPINS0_5_VAL ((const uint8 CYFAR *)0x48000384u)\r
+\r
+/* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */\r
+#define BS_IOPINS0_6_VAL ((const uint8 CYFAR *)0x48000390u)\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: cfg_write_bytes32\r
+********************************************************************************\r
+* Summary:\r
+* This function is used for setting up the chip configuration areas that\r
+* contain relatively sparse data.\r
+*\r
+* Parameters:\r
+* void\r
+*\r
+* Return:\r
+* void\r
+*\r
+*******************************************************************************/\r
+static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]);\r
+static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[])\r
+{\r
+ /* For 32-bit little-endian architectures */\r
+ uint32 i, j = 0u;\r
+ for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++)\r
+ {\r
+ uint32 baseAddr = addr_table[i];\r
+ uint8 count = (uint8)baseAddr;\r
+ baseAddr &= 0xFFFFFF00u;\r
+ while (count != 0u)\r
+ {\r
+ CY_SET_XTND_REG8((void CYFAR *)(baseAddr + data_table[j].offset), data_table[j].value);\r
+ j++;\r
+ count--;\r
+ }\r
+ }\r
+}\r
+\r
+/*******************************************************************************\r
+* Function Name: ClockSetup\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Performs the initialization of all of the clocks in the device based on the\r
+* settings in the Clock tab of the DWR. This includes enabling the requested\r
+* clocks and setting the necessary dividers to produce the desired frequency. \r
+*\r
+* Parameters:\r
+* void\r
+*\r
+* Return:\r
+* void\r
+*\r
+*******************************************************************************/\r
+static void ClockSetup(void);\r
+static void ClockSetup(void)\r
+{\r
+ uint32 timeout;\r
+ uint8 pllLock;\r
+\r
+\r
+ /* Configure Digital Clocks based on settings from Clock DWR */\r
+ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0001u);\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x18u);\r
+ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x001Du);\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x19u);\r
+\r
+ /* Configure ILO based on settings from Clock DWR */\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x02u);\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_CR), 0x08u);\r
+\r
+ /* Configure IMO based on settings from Clock DWR */\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x02u);\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)));\r
+\r
+ /* Configure PLL based on settings from Clock DWR */\r
+ CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0818u);\r
+ CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1051u);\r
+ /* Wait up to 250us for the PLL to lock */\r
+ pllLock = 0u;\r
+ for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--) { \r
+ pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0));\r
+ CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */\r
+ }\r
+\r
+ /* Configure Bus/Master Clock based on settings from Clock DWR */\r
+ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u);\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u);\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u);\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u);\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u);\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u);\r
+\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x02u)));\r
+}\r
+\r
+\r
+/* Analog API Functions */\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: AnalogSetDefault\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets up the analog portions of the chip to default values based on chip\r
+* configuration options from the project.\r
+*\r
+* Parameters:\r
+* void\r
+*\r
+* Return:\r
+* void\r
+*\r
+*******************************************************************************/\r
+static void AnalogSetDefault(void);\r
+static void AnalogSetDefault(void)\r
+{\r
+ uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u));\r
+ CY_SET_XTND_REG8((void CYFAR *)CYREG_BG_DFT0, bg_xover_inl_trim & 0x07u);\r
+ CY_SET_XTND_REG8((void CYFAR *)CYREG_BG_DFT1, ((uint8)((uint8)bg_xover_inl_trim >> 4)) & 0x0Fu);\r
+ CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u);\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: SetAnalogRoutingPumps\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Enables or disables the analog pumps feeding analog routing switches.\r
+* Intended to be called at startup, based on the Vdda system configuration;\r
+* may be called during operation when the user informs us that the Vdda voltage\r
+* crossed the pump threshold.\r
+*\r
+* Parameters:\r
+* enabled - 1 to enable the pumps, 0 to disable the pumps\r
+*\r
+* Return:\r
+* void\r
+*\r
+*******************************************************************************/\r
+void SetAnalogRoutingPumps(uint8 enabled)\r
+{\r
+ uint8 regValue = CY_GET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0);\r
+ if (enabled != 0u)\r
+ {\r
+ regValue |= 0x00u;\r
+ }\r
+ else\r
+ {\r
+ regValue &= (uint8)~0x00u;\r
+ }\r
+ CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue);\r
+}\r
+\r
+#define CY_AMUX_UNUSED CYREG_BOOST_SR\r
+\r
+\r
+/*******************************************************************************\r
+* Function Name: cyfitter_cfg\r
+********************************************************************************\r
+* Summary:\r
+* This function is called by the start-up code for the selected device. It\r
+* performs all of the necessary device configuration based on the design\r
+* settings. This includes settings from the Design Wide Resources (DWR) such\r
+* as Clocks and Pins as well as any component configuration that is necessary.\r
+*\r
+* Parameters: \r
+* void\r
+*\r
+* Return:\r
+* void\r
+*\r
+*******************************************************************************/\r
+\r
+void cyfitter_cfg(void)\r
+{\r
+#ifdef CYGlobalIntDisable\r
+ /* Disable interrupts by default. Let user enable if/when they want. */\r
+ CYGlobalIntDisable\r
+#endif\r
+\r
+\r
+ /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */\r
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u));\r
+ /* Setup clocks based on selections from Clock DWR */\r
+ ClockSetup();\r
+ /* Enable/Disable Debug functionality based on settings from System DWR */\r
+ CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u));\r
+\r
+ {\r
+\r
+ typedef struct {\r
+ void CYFAR *address;\r
+ uint16 size;\r
+ } CYPACKED cfg_memset_t;\r
+\r
+\r
+ typedef struct {\r
+ void CYFAR *dest;\r
+ const void CYFAR *src;\r
+ uint16 size;\r
+ } CYPACKED cfg_memcpy_t;\r
+\r
+ static const cfg_memset_t CYCODE cfg_memset_list [] = {\r
+ /* address, size */\r
+ {(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
+ {(void CYFAR *)(CYREG_PRT15_DR), 16u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 640u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P3_ROUTE_BASE), 1280u},\r
+ {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
+ {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
+ {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},\r
+ };\r
+\r
+ static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
+ /* dest, src, size */\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P3_U1_BASE), BS_UDB_1_1_0_CONFIG_VAL, 128u},\r
+ };\r
+\r
+ uint8 CYDATA i;\r
+\r
+ /* Zero out critical memory blocks before beginning configuration */\r
+ for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++)\r
+ {\r
+ const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i];\r
+ CYMEMZERO(ms->address, (uint32)(ms->size));\r
+ }\r
+\r
+ /* Copy device configuration data into registers */\r
+ for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)\r
+ {\r
+ const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];\r
+ void * CYDATA destPtr = mc->dest;\r
+ const void * CYDATA srcPtr = mc->src;\r
+ uint16 CYDATA numBytes = mc->size;\r
+ CYCONFIGCPY(destPtr, srcPtr, numBytes);\r
+ }\r
+\r
+ cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);\r
+\r
+ /* Enable digital routing */\r
+ CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u);\r
+ CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u);\r
+\r
+ /* Enable UDB array */\r
+ CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u);\r
+ CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u);\r
+ }\r
+\r
+ /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */\r
+ CYCONFIGCPY((void CYFAR *)(CYREG_PRT0_DM0), (const void CYFAR *)(BS_IOPINS0_0_VAL), 8u);\r
+ CYCONFIGCPY((void CYFAR *)(CYREG_PRT12_DR), (const void CYFAR *)(BS_IOPINS0_7_VAL), 10u);\r
+ CYCONFIGCPY((void CYFAR *)(CYREG_PRT12_DR + 0x0000000Bu), (const void CYFAR *)(BS_IOPINS1_7_VAL), 5u);\r
+ CYCONFIGCPY((void CYFAR *)(CYREG_PRT2_DM0), (const void CYFAR *)(BS_IOPINS0_2_VAL), 8u);\r
+ CYCONFIGCPY((void CYFAR *)(CYREG_PRT3_DR), (const void CYFAR *)(BS_IOPINS0_3_VAL), 10u);\r
+ CYCONFIGCPY((void CYFAR *)(CYREG_PRT4_DM0), (const void CYFAR *)(BS_IOPINS0_4_VAL), 8u);\r
+ CYCONFIGCPY((void CYFAR *)(CYREG_PRT5_DR), (const void CYFAR *)(BS_IOPINS0_5_VAL), 10u);\r
+ CYCONFIGCPY((void CYFAR *)(CYREG_PRT6_DM0), (const void CYFAR *)(BS_IOPINS0_6_VAL), 8u);\r
+\r
+ /* Switch Boost to the precision bandgap reference from its internal reference */\r
+ CY_SET_REG8((void CYXDATA *)CYDEV_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYDEV_BOOST_CR2) | 0x08u));\r
+\r
+ /* Perform basic analog initialization to defaults */\r
+ AnalogSetDefault();\r
+\r
+ /* Configure alternate active mode */\r
+ CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 14u);\r
+}\r
--- /dev/null
+/*******************************************************************************\r
+* FILENAME: cyfitter_cfg.h\r
+* PSoC Creator 2.2 Component Pack 6\r
+*\r
+* Description:\r
+* This file is automatically generated by PSoC Creator.\r
+*\r
+********************************************************************************\r
+* Copyright 2012, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions, \r
+* disclaimers, and limitations in the end user license agreement accompanying \r
+* the software package with which this file was provided.\r
+********************************************************************************/\r
+\r
+#ifndef CYFITTER_CFG_H\r
+#define CYFITTER_CFG_H\r
+\r
+#include <cytypes.h>\r
+\r
+extern void cyfitter_cfg(void);\r
+\r
+/* Analog Set/Unset methods */\r
+extern void SetAnalogRoutingPumps(uint8 enabled);\r
+\r
+\r
+#endif /* CYFITTER_CFG_H */\r
+\r
+/*[]*/\r
--- /dev/null
+.ifndef INCLUDED_CYFITTERGNU_INC\r
+.set INCLUDED_CYFITTERGNU_INC, 1\r
+.include "cydevicegnu.inc"\r
+.include "cydevicegnu_trm.inc"\r
+\r
+/* SDCard_RxInternalInterrupt */\r
+.set SDCard_RxInternalInterrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SDCard_RxInternalInterrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SDCard_RxInternalInterrupt__INTC_MASK, 0x01\r
+.set SDCard_RxInternalInterrupt__INTC_NUMBER, 0\r
+.set SDCard_RxInternalInterrupt__INTC_PRIOR_NUM, 7\r
+.set SDCard_RxInternalInterrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0\r
+.set SDCard_RxInternalInterrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SDCard_RxInternalInterrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SDCard_TxInternalInterrupt */\r
+.set SDCard_TxInternalInterrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
+.set SDCard_TxInternalInterrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
+.set SDCard_TxInternalInterrupt__INTC_MASK, 0x02\r
+.set SDCard_TxInternalInterrupt__INTC_NUMBER, 1\r
+.set SDCard_TxInternalInterrupt__INTC_PRIOR_NUM, 7\r
+.set SDCard_TxInternalInterrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1\r
+.set SDCard_TxInternalInterrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
+.set SDCard_TxInternalInterrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
+\r
+/* SCSI_Out_DBx */\r
+.set SCSI_Out_DBx__0__MASK, 0x01\r
+.set SCSI_Out_DBx__0__PC, CYREG_PRT0_PC0\r
+.set SCSI_Out_DBx__0__PORT, 0\r
+.set SCSI_Out_DBx__0__SHIFT, 0\r
+.set SCSI_Out_DBx__1__MASK, 0x02\r
+.set SCSI_Out_DBx__1__PC, CYREG_PRT0_PC1\r
+.set SCSI_Out_DBx__1__PORT, 0\r
+.set SCSI_Out_DBx__1__SHIFT, 1\r
+.set SCSI_Out_DBx__2__MASK, 0x04\r
+.set SCSI_Out_DBx__2__PC, CYREG_PRT0_PC2\r
+.set SCSI_Out_DBx__2__PORT, 0\r
+.set SCSI_Out_DBx__2__SHIFT, 2\r
+.set SCSI_Out_DBx__3__MASK, 0x08\r
+.set SCSI_Out_DBx__3__PC, CYREG_PRT0_PC3\r
+.set SCSI_Out_DBx__3__PORT, 0\r
+.set SCSI_Out_DBx__3__SHIFT, 3\r
+.set SCSI_Out_DBx__4__MASK, 0x10\r
+.set SCSI_Out_DBx__4__PC, CYREG_PRT0_PC4\r
+.set SCSI_Out_DBx__4__PORT, 0\r
+.set SCSI_Out_DBx__4__SHIFT, 4\r
+.set SCSI_Out_DBx__5__MASK, 0x20\r
+.set SCSI_Out_DBx__5__PC, CYREG_PRT0_PC5\r
+.set SCSI_Out_DBx__5__PORT, 0\r
+.set SCSI_Out_DBx__5__SHIFT, 5\r
+.set SCSI_Out_DBx__6__MASK, 0x40\r
+.set SCSI_Out_DBx__6__PC, CYREG_PRT0_PC6\r
+.set SCSI_Out_DBx__6__PORT, 0\r
+.set SCSI_Out_DBx__6__SHIFT, 6\r
+.set SCSI_Out_DBx__7__MASK, 0x80\r
+.set SCSI_Out_DBx__7__PC, CYREG_PRT0_PC7\r
+.set SCSI_Out_DBx__7__PORT, 0\r
+.set SCSI_Out_DBx__7__SHIFT, 7\r
+.set SCSI_Out_DBx__AG, CYREG_PRT0_AG\r
+.set SCSI_Out_DBx__AMUX, CYREG_PRT0_AMUX\r
+.set SCSI_Out_DBx__BIE, CYREG_PRT0_BIE\r
+.set SCSI_Out_DBx__BIT_MASK, CYREG_PRT0_BIT_MASK\r
+.set SCSI_Out_DBx__BYP, CYREG_PRT0_BYP\r
+.set SCSI_Out_DBx__CTL, CYREG_PRT0_CTL\r
+.set SCSI_Out_DBx__DM0, CYREG_PRT0_DM0\r
+.set SCSI_Out_DBx__DM1, CYREG_PRT0_DM1\r
+.set SCSI_Out_DBx__DM2, CYREG_PRT0_DM2\r
+.set SCSI_Out_DBx__DR, CYREG_PRT0_DR\r
+.set SCSI_Out_DBx__INP_DIS, CYREG_PRT0_INP_DIS\r
+.set SCSI_Out_DBx__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG\r
+.set SCSI_Out_DBx__LCD_EN, CYREG_PRT0_LCD_EN\r
+.set SCSI_Out_DBx__MASK, 0xFF\r
+.set SCSI_Out_DBx__PORT, 0\r
+.set SCSI_Out_DBx__PRT, CYREG_PRT0_PRT\r
+.set SCSI_Out_DBx__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL\r
+.set SCSI_Out_DBx__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN\r
+.set SCSI_Out_DBx__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0\r
+.set SCSI_Out_DBx__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1\r
+.set SCSI_Out_DBx__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0\r
+.set SCSI_Out_DBx__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1\r
+.set SCSI_Out_DBx__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT\r
+.set SCSI_Out_DBx__PS, CYREG_PRT0_PS\r
+.set SCSI_Out_DBx__SCSI_Out_DB0__MASK, 0x01\r
+.set SCSI_Out_DBx__SCSI_Out_DB0__PC, CYREG_PRT0_PC0\r
+.set SCSI_Out_DBx__SCSI_Out_DB0__PORT, 0\r
+.set SCSI_Out_DBx__SCSI_Out_DB0__SHIFT, 0\r
+.set SCSI_Out_DBx__SCSI_Out_DB1__MASK, 0x02\r
+.set SCSI_Out_DBx__SCSI_Out_DB1__PC, CYREG_PRT0_PC1\r
+.set SCSI_Out_DBx__SCSI_Out_DB1__PORT, 0\r
+.set SCSI_Out_DBx__SCSI_Out_DB1__SHIFT, 1\r
+.set SCSI_Out_DBx__SCSI_Out_DB2__MASK, 0x04\r
+.set SCSI_Out_DBx__SCSI_Out_DB2__PC, CYREG_PRT0_PC2\r
+.set SCSI_Out_DBx__SCSI_Out_DB2__PORT, 0\r
+.set SCSI_Out_DBx__SCSI_Out_DB2__SHIFT, 2\r
+.set SCSI_Out_DBx__SCSI_Out_DB3__MASK, 0x08\r
+.set SCSI_Out_DBx__SCSI_Out_DB3__PC, CYREG_PRT0_PC3\r
+.set SCSI_Out_DBx__SCSI_Out_DB3__PORT, 0\r
+.set SCSI_Out_DBx__SCSI_Out_DB3__SHIFT, 3\r
+.set SCSI_Out_DBx__SCSI_Out_DB4__MASK, 0x10\r
+.set SCSI_Out_DBx__SCSI_Out_DB4__PC, CYREG_PRT0_PC4\r
+.set SCSI_Out_DBx__SCSI_Out_DB4__PORT, 0\r
+.set SCSI_Out_DBx__SCSI_Out_DB4__SHIFT, 4\r
+.set SCSI_Out_DBx__SCSI_Out_DB5__MASK, 0x20\r
+.set SCSI_Out_DBx__SCSI_Out_DB5__PC, CYREG_PRT0_PC5\r
+.set SCSI_Out_DBx__SCSI_Out_DB5__PORT, 0\r
+.set SCSI_Out_DBx__SCSI_Out_DB5__SHIFT, 5\r
+.set SCSI_Out_DBx__SCSI_Out_DB6__MASK, 0x40\r
+.set SCSI_Out_DBx__SCSI_Out_DB6__PC, CYREG_PRT0_PC6\r
+.set SCSI_Out_DBx__SCSI_Out_DB6__PORT, 0\r
+.set SCSI_Out_DBx__SCSI_Out_DB6__SHIFT, 6\r
+.set SCSI_Out_DBx__SCSI_Out_DB7__MASK, 0x80\r
+.set SCSI_Out_DBx__SCSI_Out_DB7__PC, CYREG_PRT0_PC7\r
+.set SCSI_Out_DBx__SCSI_Out_DB7__PORT, 0\r
+.set SCSI_Out_DBx__SCSI_Out_DB7__SHIFT, 7\r
+.set SCSI_Out_DBx__SHIFT, 0\r
+.set SCSI_Out_DBx__SLW, CYREG_PRT0_SLW\r
+\r
+/* SDCard_BSPIM */\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL\r
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL\r
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK\r
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST\r
+.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
+.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
+.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
+.set SDCard_BSPIM_RxStsReg__5__POS, 5\r
+.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
+.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
+.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST\r
+.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
+.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST\r
+.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
+.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
+.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
+.set SDCard_BSPIM_TxStsReg__2__POS, 2\r
+.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08\r
+.set SDCard_BSPIM_TxStsReg__3__POS, 3\r
+.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
+.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
+.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB07_08_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB07_08_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB07_08_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB07_08_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB07_08_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB07_08_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB07_A0_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB07_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB07_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB07_D0_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB07_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB07_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB07_F0_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB07_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB07_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+\r
+/* SCSI_In_DBx */\r
+.set SCSI_In_DBx__0__MASK, 0x01\r
+.set SCSI_In_DBx__0__PC, CYREG_PRT2_PC0\r
+.set SCSI_In_DBx__0__PORT, 2\r
+.set SCSI_In_DBx__0__SHIFT, 0\r
+.set SCSI_In_DBx__1__MASK, 0x02\r
+.set SCSI_In_DBx__1__PC, CYREG_PRT2_PC1\r
+.set SCSI_In_DBx__1__PORT, 2\r
+.set SCSI_In_DBx__1__SHIFT, 1\r
+.set SCSI_In_DBx__2__MASK, 0x04\r
+.set SCSI_In_DBx__2__PC, CYREG_PRT2_PC2\r
+.set SCSI_In_DBx__2__PORT, 2\r
+.set SCSI_In_DBx__2__SHIFT, 2\r
+.set SCSI_In_DBx__3__MASK, 0x08\r
+.set SCSI_In_DBx__3__PC, CYREG_PRT2_PC3\r
+.set SCSI_In_DBx__3__PORT, 2\r
+.set SCSI_In_DBx__3__SHIFT, 3\r
+.set SCSI_In_DBx__4__MASK, 0x10\r
+.set SCSI_In_DBx__4__PC, CYREG_PRT2_PC4\r
+.set SCSI_In_DBx__4__PORT, 2\r
+.set SCSI_In_DBx__4__SHIFT, 4\r
+.set SCSI_In_DBx__5__MASK, 0x20\r
+.set SCSI_In_DBx__5__PC, CYREG_PRT2_PC5\r
+.set SCSI_In_DBx__5__PORT, 2\r
+.set SCSI_In_DBx__5__SHIFT, 5\r
+.set SCSI_In_DBx__6__MASK, 0x40\r
+.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC6\r
+.set SCSI_In_DBx__6__PORT, 2\r
+.set SCSI_In_DBx__6__SHIFT, 6\r
+.set SCSI_In_DBx__7__MASK, 0x80\r
+.set SCSI_In_DBx__7__PC, CYREG_PRT2_PC7\r
+.set SCSI_In_DBx__7__PORT, 2\r
+.set SCSI_In_DBx__7__SHIFT, 7\r
+.set SCSI_In_DBx__AG, CYREG_PRT2_AG\r
+.set SCSI_In_DBx__AMUX, CYREG_PRT2_AMUX\r
+.set SCSI_In_DBx__BIE, CYREG_PRT2_BIE\r
+.set SCSI_In_DBx__BIT_MASK, CYREG_PRT2_BIT_MASK\r
+.set SCSI_In_DBx__BYP, CYREG_PRT2_BYP\r
+.set SCSI_In_DBx__CTL, CYREG_PRT2_CTL\r
+.set SCSI_In_DBx__DM0, CYREG_PRT2_DM0\r
+.set SCSI_In_DBx__DM1, CYREG_PRT2_DM1\r
+.set SCSI_In_DBx__DM2, CYREG_PRT2_DM2\r
+.set SCSI_In_DBx__DR, CYREG_PRT2_DR\r
+.set SCSI_In_DBx__INP_DIS, CYREG_PRT2_INP_DIS\r
+.set SCSI_In_DBx__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG\r
+.set SCSI_In_DBx__LCD_EN, CYREG_PRT2_LCD_EN\r
+.set SCSI_In_DBx__MASK, 0xFF\r
+.set SCSI_In_DBx__PORT, 2\r
+.set SCSI_In_DBx__PRT, CYREG_PRT2_PRT\r
+.set SCSI_In_DBx__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL\r
+.set SCSI_In_DBx__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN\r
+.set SCSI_In_DBx__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0\r
+.set SCSI_In_DBx__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1\r
+.set SCSI_In_DBx__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0\r
+.set SCSI_In_DBx__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1\r
+.set SCSI_In_DBx__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT\r
+.set SCSI_In_DBx__PS, CYREG_PRT2_PS\r
+.set SCSI_In_DBx__SCSI_Out_DB0__MASK, 0x01\r
+.set SCSI_In_DBx__SCSI_Out_DB0__PC, CYREG_PRT2_PC0\r
+.set SCSI_In_DBx__SCSI_Out_DB0__PORT, 2\r
+.set SCSI_In_DBx__SCSI_Out_DB0__SHIFT, 0\r
+.set SCSI_In_DBx__SCSI_Out_DB1__MASK, 0x02\r
+.set SCSI_In_DBx__SCSI_Out_DB1__PC, CYREG_PRT2_PC1\r
+.set SCSI_In_DBx__SCSI_Out_DB1__PORT, 2\r
+.set SCSI_In_DBx__SCSI_Out_DB1__SHIFT, 1\r
+.set SCSI_In_DBx__SCSI_Out_DB2__MASK, 0x04\r
+.set SCSI_In_DBx__SCSI_Out_DB2__PC, CYREG_PRT2_PC2\r
+.set SCSI_In_DBx__SCSI_Out_DB2__PORT, 2\r
+.set SCSI_In_DBx__SCSI_Out_DB2__SHIFT, 2\r
+.set SCSI_In_DBx__SCSI_Out_DB3__MASK, 0x08\r
+.set SCSI_In_DBx__SCSI_Out_DB3__PC, CYREG_PRT2_PC3\r
+.set SCSI_In_DBx__SCSI_Out_DB3__PORT, 2\r
+.set SCSI_In_DBx__SCSI_Out_DB3__SHIFT, 3\r
+.set SCSI_In_DBx__SCSI_Out_DB4__MASK, 0x10\r
+.set SCSI_In_DBx__SCSI_Out_DB4__PC, CYREG_PRT2_PC4\r
+.set SCSI_In_DBx__SCSI_Out_DB4__PORT, 2\r
+.set SCSI_In_DBx__SCSI_Out_DB4__SHIFT, 4\r
+.set SCSI_In_DBx__SCSI_Out_DB5__MASK, 0x20\r
+.set SCSI_In_DBx__SCSI_Out_DB5__PC, CYREG_PRT2_PC5\r
+.set SCSI_In_DBx__SCSI_Out_DB5__PORT, 2\r
+.set SCSI_In_DBx__SCSI_Out_DB5__SHIFT, 5\r
+.set SCSI_In_DBx__SCSI_Out_DB6__MASK, 0x40\r
+.set SCSI_In_DBx__SCSI_Out_DB6__PC, CYREG_PRT2_PC6\r
+.set SCSI_In_DBx__SCSI_Out_DB6__PORT, 2\r
+.set SCSI_In_DBx__SCSI_Out_DB6__SHIFT, 6\r
+.set SCSI_In_DBx__SCSI_Out_DB7__MASK, 0x80\r
+.set SCSI_In_DBx__SCSI_Out_DB7__PC, CYREG_PRT2_PC7\r
+.set SCSI_In_DBx__SCSI_Out_DB7__PORT, 2\r
+.set SCSI_In_DBx__SCSI_Out_DB7__SHIFT, 7\r
+.set SCSI_In_DBx__SHIFT, 0\r
+.set SCSI_In_DBx__SLW, CYREG_PRT2_SLW\r
+\r
+/* SD_Data_Clk */\r
+.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0\r
+.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1\r
+.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2\r
+.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07\r
+.set SD_Data_Clk__INDEX, 0x00\r
+.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
+.set SD_Data_Clk__PM_ACT_MSK, 0x01\r
+.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
+.set SD_Data_Clk__PM_STBY_MSK, 0x01\r
+\r
+/* SD_Init_Clk */\r
+.set SD_Init_Clk__CFG0, CYREG_CLKDIST_DCFG1_CFG0\r
+.set SD_Init_Clk__CFG1, CYREG_CLKDIST_DCFG1_CFG1\r
+.set SD_Init_Clk__CFG2, CYREG_CLKDIST_DCFG1_CFG2\r
+.set SD_Init_Clk__CFG2_SRC_SEL_MASK, 0x07\r
+.set SD_Init_Clk__INDEX, 0x01\r
+.set SD_Init_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2\r
+.set SD_Init_Clk__PM_ACT_MSK, 0x02\r
+.set SD_Init_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2\r
+.set SD_Init_Clk__PM_STBY_MSK, 0x02\r
+\r
+/* SD_Clk_Ctl */\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB05_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB05_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB05_MSK\r
+.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL\r
+\r
+/* PARITY_EN */\r
+.set PARITY_EN__0__MASK, 0x10\r
+.set PARITY_EN__0__PC, CYREG_PRT5_PC4\r
+.set PARITY_EN__0__PORT, 5\r
+.set PARITY_EN__0__SHIFT, 4\r
+.set PARITY_EN__AG, CYREG_PRT5_AG\r
+.set PARITY_EN__AMUX, CYREG_PRT5_AMUX\r
+.set PARITY_EN__BIE, CYREG_PRT5_BIE\r
+.set PARITY_EN__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set PARITY_EN__BYP, CYREG_PRT5_BYP\r
+.set PARITY_EN__CTL, CYREG_PRT5_CTL\r
+.set PARITY_EN__DM0, CYREG_PRT5_DM0\r
+.set PARITY_EN__DM1, CYREG_PRT5_DM1\r
+.set PARITY_EN__DM2, CYREG_PRT5_DM2\r
+.set PARITY_EN__DR, CYREG_PRT5_DR\r
+.set PARITY_EN__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set PARITY_EN__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set PARITY_EN__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set PARITY_EN__MASK, 0x10\r
+.set PARITY_EN__PORT, 5\r
+.set PARITY_EN__PRT, CYREG_PRT5_PRT\r
+.set PARITY_EN__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set PARITY_EN__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set PARITY_EN__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set PARITY_EN__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set PARITY_EN__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set PARITY_EN__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set PARITY_EN__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set PARITY_EN__PS, CYREG_PRT5_PS\r
+.set PARITY_EN__SHIFT, 4\r
+.set PARITY_EN__SLW, CYREG_PRT5_SLW\r
+\r
+/* SCSI_Out */\r
+.set SCSI_Out__0__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__0__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__0__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__0__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__0__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__0__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__0__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__0__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__0__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__0__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__0__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__0__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__0__MASK, 0x04\r
+.set SCSI_Out__0__PC, CYREG_PRT4_PC2\r
+.set SCSI_Out__0__PORT, 4\r
+.set SCSI_Out__0__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__0__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__0__SHIFT, 2\r
+.set SCSI_Out__0__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__1__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__1__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__1__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__1__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__1__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__1__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__1__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__1__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__1__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__1__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__1__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__1__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__1__MASK, 0x08\r
+.set SCSI_Out__1__PC, CYREG_PRT4_PC3\r
+.set SCSI_Out__1__PORT, 4\r
+.set SCSI_Out__1__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__1__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__1__SHIFT, 3\r
+.set SCSI_Out__1__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__2__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__2__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__2__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__2__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__2__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__2__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__2__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__2__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__2__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__2__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__2__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__2__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__2__MASK, 0x10\r
+.set SCSI_Out__2__PC, CYREG_PRT4_PC4\r
+.set SCSI_Out__2__PORT, 4\r
+.set SCSI_Out__2__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__2__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__2__SHIFT, 4\r
+.set SCSI_Out__2__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__3__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__3__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__3__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__3__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__3__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__3__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__3__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__3__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__3__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__3__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__3__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__3__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__3__MASK, 0x20\r
+.set SCSI_Out__3__PC, CYREG_PRT4_PC5\r
+.set SCSI_Out__3__PORT, 4\r
+.set SCSI_Out__3__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__3__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__3__SHIFT, 5\r
+.set SCSI_Out__3__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__4__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__4__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__4__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__4__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__4__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__4__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__4__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__4__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__4__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__4__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__4__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__4__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__4__MASK, 0x40\r
+.set SCSI_Out__4__PC, CYREG_PRT4_PC6\r
+.set SCSI_Out__4__PORT, 4\r
+.set SCSI_Out__4__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__4__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__4__SHIFT, 6\r
+.set SCSI_Out__4__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__5__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__5__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__5__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__5__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__5__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__5__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__5__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__5__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__5__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__5__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__5__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__5__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__5__MASK, 0x80\r
+.set SCSI_Out__5__PC, CYREG_PRT4_PC7\r
+.set SCSI_Out__5__PORT, 4\r
+.set SCSI_Out__5__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__5__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__5__SHIFT, 7\r
+.set SCSI_Out__5__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__6__AG, CYREG_PRT6_AG\r
+.set SCSI_Out__6__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out__6__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out__6__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out__6__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out__6__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out__6__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out__6__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out__6__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out__6__DR, CYREG_PRT6_DR\r
+.set SCSI_Out__6__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out__6__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out__6__MASK, 0x01\r
+.set SCSI_Out__6__PC, CYREG_PRT6_PC0\r
+.set SCSI_Out__6__PORT, 6\r
+.set SCSI_Out__6__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out__6__PS, CYREG_PRT6_PS\r
+.set SCSI_Out__6__SHIFT, 0\r
+.set SCSI_Out__6__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out__7__AG, CYREG_PRT6_AG\r
+.set SCSI_Out__7__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out__7__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out__7__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out__7__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out__7__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out__7__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out__7__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out__7__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out__7__DR, CYREG_PRT6_DR\r
+.set SCSI_Out__7__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out__7__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out__7__MASK, 0x02\r
+.set SCSI_Out__7__PC, CYREG_PRT6_PC1\r
+.set SCSI_Out__7__PORT, 6\r
+.set SCSI_Out__7__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out__7__PS, CYREG_PRT6_PS\r
+.set SCSI_Out__7__SHIFT, 1\r
+.set SCSI_Out__7__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out__8__AG, CYREG_PRT6_AG\r
+.set SCSI_Out__8__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out__8__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out__8__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out__8__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out__8__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out__8__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out__8__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out__8__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out__8__DR, CYREG_PRT6_DR\r
+.set SCSI_Out__8__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out__8__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out__8__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out__8__MASK, 0x04\r
+.set SCSI_Out__8__PC, CYREG_PRT6_PC2\r
+.set SCSI_Out__8__PORT, 6\r
+.set SCSI_Out__8__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out__8__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out__8__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out__8__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out__8__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out__8__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out__8__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out__8__PS, CYREG_PRT6_PS\r
+.set SCSI_Out__8__SHIFT, 2\r
+.set SCSI_Out__8__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out__9__AG, CYREG_PRT6_AG\r
+.set SCSI_Out__9__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out__9__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out__9__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out__9__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out__9__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out__9__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out__9__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out__9__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out__9__DR, CYREG_PRT6_DR\r
+.set SCSI_Out__9__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out__9__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out__9__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out__9__MASK, 0x08\r
+.set SCSI_Out__9__PC, CYREG_PRT6_PC3\r
+.set SCSI_Out__9__PORT, 6\r
+.set SCSI_Out__9__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out__9__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out__9__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out__9__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out__9__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out__9__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out__9__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out__9__PS, CYREG_PRT6_PS\r
+.set SCSI_Out__9__SHIFT, 3\r
+.set SCSI_Out__9__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out__ACK__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__ACK__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__ACK__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__ACK__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__ACK__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__ACK__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__ACK__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__ACK__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__ACK__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__ACK__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__ACK__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__ACK__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__ACK__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__ACK__MASK, 0x20\r
+.set SCSI_Out__ACK__PC, CYREG_PRT4_PC5\r
+.set SCSI_Out__ACK__PORT, 4\r
+.set SCSI_Out__ACK__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__ACK__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__ACK__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__ACK__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__ACK__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__ACK__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__ACK__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__ACK__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__ACK__SHIFT, 5\r
+.set SCSI_Out__ACK__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__ATN__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__ATN__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__ATN__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__ATN__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__ATN__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__ATN__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__ATN__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__ATN__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__ATN__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__ATN__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__ATN__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__ATN__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__ATN__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__ATN__MASK, 0x08\r
+.set SCSI_Out__ATN__PC, CYREG_PRT4_PC3\r
+.set SCSI_Out__ATN__PORT, 4\r
+.set SCSI_Out__ATN__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__ATN__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__ATN__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__ATN__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__ATN__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__ATN__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__ATN__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__ATN__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__ATN__SHIFT, 3\r
+.set SCSI_Out__ATN__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__BSY__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__BSY__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__BSY__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__BSY__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__BSY__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__BSY__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__BSY__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__BSY__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__BSY__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__BSY__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__BSY__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__BSY__MASK, 0x10\r
+.set SCSI_Out__BSY__PC, CYREG_PRT4_PC4\r
+.set SCSI_Out__BSY__PORT, 4\r
+.set SCSI_Out__BSY__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__BSY__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__BSY__SHIFT, 4\r
+.set SCSI_Out__BSY__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__CD__AG, CYREG_PRT6_AG\r
+.set SCSI_Out__CD__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out__CD__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out__CD__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out__CD__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out__CD__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out__CD__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out__CD__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out__CD__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out__CD__DR, CYREG_PRT6_DR\r
+.set SCSI_Out__CD__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out__CD__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out__CD__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out__CD__MASK, 0x02\r
+.set SCSI_Out__CD__PC, CYREG_PRT6_PC1\r
+.set SCSI_Out__CD__PORT, 6\r
+.set SCSI_Out__CD__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out__CD__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out__CD__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out__CD__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out__CD__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out__CD__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out__CD__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out__CD__PS, CYREG_PRT6_PS\r
+.set SCSI_Out__CD__SHIFT, 1\r
+.set SCSI_Out__CD__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out__DBP__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__DBP__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__DBP__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__DBP__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__DBP__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__DBP__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__DBP__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__DBP__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__DBP__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__DBP__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__DBP__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__DBP__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__DBP__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__DBP__MASK, 0x04\r
+.set SCSI_Out__DBP__PC, CYREG_PRT4_PC2\r
+.set SCSI_Out__DBP__PORT, 4\r
+.set SCSI_Out__DBP__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__DBP__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__DBP__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__DBP__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__DBP__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__DBP__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__DBP__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__DBP__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__DBP__SHIFT, 2\r
+.set SCSI_Out__DBP__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__IO__AG, CYREG_PRT6_AG\r
+.set SCSI_Out__IO__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out__IO__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out__IO__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out__IO__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out__IO__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out__IO__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out__IO__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out__IO__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out__IO__DR, CYREG_PRT6_DR\r
+.set SCSI_Out__IO__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out__IO__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out__IO__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out__IO__MASK, 0x08\r
+.set SCSI_Out__IO__PC, CYREG_PRT6_PC3\r
+.set SCSI_Out__IO__PORT, 6\r
+.set SCSI_Out__IO__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out__IO__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out__IO__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out__IO__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out__IO__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out__IO__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out__IO__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out__IO__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out__IO__PS, CYREG_PRT6_PS\r
+.set SCSI_Out__IO__SHIFT, 3\r
+.set SCSI_Out__IO__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out__MSG__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__MSG__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__MSG__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__MSG__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__MSG__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__MSG__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__MSG__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__MSG__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__MSG__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__MSG__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__MSG__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__MSG__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__MSG__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__MSG__MASK, 0x80\r
+.set SCSI_Out__MSG__PC, CYREG_PRT4_PC7\r
+.set SCSI_Out__MSG__PORT, 4\r
+.set SCSI_Out__MSG__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__MSG__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__MSG__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__MSG__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__MSG__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__MSG__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__MSG__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__MSG__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__MSG__SHIFT, 7\r
+.set SCSI_Out__MSG__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__REQ__AG, CYREG_PRT6_AG\r
+.set SCSI_Out__REQ__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out__REQ__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out__REQ__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out__REQ__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out__REQ__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out__REQ__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out__REQ__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out__REQ__DR, CYREG_PRT6_DR\r
+.set SCSI_Out__REQ__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out__REQ__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out__REQ__MASK, 0x04\r
+.set SCSI_Out__REQ__PC, CYREG_PRT6_PC2\r
+.set SCSI_Out__REQ__PORT, 6\r
+.set SCSI_Out__REQ__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out__REQ__PS, CYREG_PRT6_PS\r
+.set SCSI_Out__REQ__SHIFT, 2\r
+.set SCSI_Out__REQ__SLW, CYREG_PRT6_SLW\r
+.set SCSI_Out__RST__AG, CYREG_PRT4_AG\r
+.set SCSI_Out__RST__AMUX, CYREG_PRT4_AMUX\r
+.set SCSI_Out__RST__BIE, CYREG_PRT4_BIE\r
+.set SCSI_Out__RST__BIT_MASK, CYREG_PRT4_BIT_MASK\r
+.set SCSI_Out__RST__BYP, CYREG_PRT4_BYP\r
+.set SCSI_Out__RST__CTL, CYREG_PRT4_CTL\r
+.set SCSI_Out__RST__DM0, CYREG_PRT4_DM0\r
+.set SCSI_Out__RST__DM1, CYREG_PRT4_DM1\r
+.set SCSI_Out__RST__DM2, CYREG_PRT4_DM2\r
+.set SCSI_Out__RST__DR, CYREG_PRT4_DR\r
+.set SCSI_Out__RST__INP_DIS, CYREG_PRT4_INP_DIS\r
+.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG\r
+.set SCSI_Out__RST__LCD_EN, CYREG_PRT4_LCD_EN\r
+.set SCSI_Out__RST__MASK, 0x40\r
+.set SCSI_Out__RST__PC, CYREG_PRT4_PC6\r
+.set SCSI_Out__RST__PORT, 4\r
+.set SCSI_Out__RST__PRT, CYREG_PRT4_PRT\r
+.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL\r
+.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN\r
+.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0\r
+.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1\r
+.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0\r
+.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1\r
+.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT\r
+.set SCSI_Out__RST__PS, CYREG_PRT4_PS\r
+.set SCSI_Out__RST__SHIFT, 6\r
+.set SCSI_Out__RST__SLW, CYREG_PRT4_SLW\r
+.set SCSI_Out__SEL__AG, CYREG_PRT6_AG\r
+.set SCSI_Out__SEL__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_Out__SEL__BIE, CYREG_PRT6_BIE\r
+.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_Out__SEL__BYP, CYREG_PRT6_BYP\r
+.set SCSI_Out__SEL__CTL, CYREG_PRT6_CTL\r
+.set SCSI_Out__SEL__DM0, CYREG_PRT6_DM0\r
+.set SCSI_Out__SEL__DM1, CYREG_PRT6_DM1\r
+.set SCSI_Out__SEL__DM2, CYREG_PRT6_DM2\r
+.set SCSI_Out__SEL__DR, CYREG_PRT6_DR\r
+.set SCSI_Out__SEL__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_Out__SEL__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_Out__SEL__MASK, 0x01\r
+.set SCSI_Out__SEL__PC, CYREG_PRT6_PC0\r
+.set SCSI_Out__SEL__PORT, 6\r
+.set SCSI_Out__SEL__PRT, CYREG_PRT6_PRT\r
+.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_Out__SEL__PS, CYREG_PRT6_PS\r
+.set SCSI_Out__SEL__SHIFT, 0\r
+.set SCSI_Out__SEL__SLW, CYREG_PRT6_SLW\r
+\r
+/* SCSI_ID */\r
+.set SCSI_ID__0__MASK, 0x80\r
+.set SCSI_ID__0__PC, CYREG_PRT5_PC7\r
+.set SCSI_ID__0__PORT, 5\r
+.set SCSI_ID__0__SHIFT, 7\r
+.set SCSI_ID__1__MASK, 0x40\r
+.set SCSI_ID__1__PC, CYREG_PRT5_PC6\r
+.set SCSI_ID__1__PORT, 5\r
+.set SCSI_ID__1__SHIFT, 6\r
+.set SCSI_ID__2__MASK, 0x20\r
+.set SCSI_ID__2__PC, CYREG_PRT5_PC5\r
+.set SCSI_ID__2__PORT, 5\r
+.set SCSI_ID__2__SHIFT, 5\r
+.set SCSI_ID__AG, CYREG_PRT5_AG\r
+.set SCSI_ID__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_ID__BIE, CYREG_PRT5_BIE\r
+.set SCSI_ID__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_ID__BYP, CYREG_PRT5_BYP\r
+.set SCSI_ID__CTL, CYREG_PRT5_CTL\r
+.set SCSI_ID__DM0, CYREG_PRT5_DM0\r
+.set SCSI_ID__DM1, CYREG_PRT5_DM1\r
+.set SCSI_ID__DM2, CYREG_PRT5_DM2\r
+.set SCSI_ID__DR, CYREG_PRT5_DR\r
+.set SCSI_ID__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_ID__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_ID__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_ID__PORT, 5\r
+.set SCSI_ID__PRT, CYREG_PRT5_PRT\r
+.set SCSI_ID__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_ID__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_ID__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_ID__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_ID__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_ID__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_ID__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_ID__PS, CYREG_PRT5_PS\r
+.set SCSI_ID__SLW, CYREG_PRT5_SLW\r
+\r
+/* SCSI_In */\r
+.set SCSI_In__0__AG, CYREG_PRT12_AG\r
+.set SCSI_In__0__BIE, CYREG_PRT12_BIE\r
+.set SCSI_In__0__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_In__0__BYP, CYREG_PRT12_BYP\r
+.set SCSI_In__0__DM0, CYREG_PRT12_DM0\r
+.set SCSI_In__0__DM1, CYREG_PRT12_DM1\r
+.set SCSI_In__0__DM2, CYREG_PRT12_DM2\r
+.set SCSI_In__0__DR, CYREG_PRT12_DR\r
+.set SCSI_In__0__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_In__0__MASK, 0x10\r
+.set SCSI_In__0__PC, CYREG_PRT12_PC4\r
+.set SCSI_In__0__PORT, 12\r
+.set SCSI_In__0__PRT, CYREG_PRT12_PRT\r
+.set SCSI_In__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_In__0__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_In__0__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_In__0__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_In__0__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_In__0__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_In__0__PS, CYREG_PRT12_PS\r
+.set SCSI_In__0__SHIFT, 4\r
+.set SCSI_In__0__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_In__0__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_In__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_In__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_In__0__SLW, CYREG_PRT12_SLW\r
+.set SCSI_In__1__AG, CYREG_PRT12_AG\r
+.set SCSI_In__1__BIE, CYREG_PRT12_BIE\r
+.set SCSI_In__1__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_In__1__BYP, CYREG_PRT12_BYP\r
+.set SCSI_In__1__DM0, CYREG_PRT12_DM0\r
+.set SCSI_In__1__DM1, CYREG_PRT12_DM1\r
+.set SCSI_In__1__DM2, CYREG_PRT12_DM2\r
+.set SCSI_In__1__DR, CYREG_PRT12_DR\r
+.set SCSI_In__1__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_In__1__MASK, 0x20\r
+.set SCSI_In__1__PC, CYREG_PRT12_PC5\r
+.set SCSI_In__1__PORT, 12\r
+.set SCSI_In__1__PRT, CYREG_PRT12_PRT\r
+.set SCSI_In__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_In__1__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_In__1__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_In__1__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_In__1__PS, CYREG_PRT12_PS\r
+.set SCSI_In__1__SHIFT, 5\r
+.set SCSI_In__1__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_In__1__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_In__1__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_In__1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_In__1__SLW, CYREG_PRT12_SLW\r
+.set SCSI_In__2__AG, CYREG_PRT6_AG\r
+.set SCSI_In__2__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_In__2__BIE, CYREG_PRT6_BIE\r
+.set SCSI_In__2__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_In__2__BYP, CYREG_PRT6_BYP\r
+.set SCSI_In__2__CTL, CYREG_PRT6_CTL\r
+.set SCSI_In__2__DM0, CYREG_PRT6_DM0\r
+.set SCSI_In__2__DM1, CYREG_PRT6_DM1\r
+.set SCSI_In__2__DM2, CYREG_PRT6_DM2\r
+.set SCSI_In__2__DR, CYREG_PRT6_DR\r
+.set SCSI_In__2__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_In__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_In__2__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_In__2__MASK, 0x10\r
+.set SCSI_In__2__PC, CYREG_PRT6_PC4\r
+.set SCSI_In__2__PORT, 6\r
+.set SCSI_In__2__PRT, CYREG_PRT6_PRT\r
+.set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_In__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_In__2__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_In__2__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_In__2__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_In__2__PS, CYREG_PRT6_PS\r
+.set SCSI_In__2__SHIFT, 4\r
+.set SCSI_In__2__SLW, CYREG_PRT6_SLW\r
+.set SCSI_In__3__AG, CYREG_PRT6_AG\r
+.set SCSI_In__3__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_In__3__BIE, CYREG_PRT6_BIE\r
+.set SCSI_In__3__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_In__3__BYP, CYREG_PRT6_BYP\r
+.set SCSI_In__3__CTL, CYREG_PRT6_CTL\r
+.set SCSI_In__3__DM0, CYREG_PRT6_DM0\r
+.set SCSI_In__3__DM1, CYREG_PRT6_DM1\r
+.set SCSI_In__3__DM2, CYREG_PRT6_DM2\r
+.set SCSI_In__3__DR, CYREG_PRT6_DR\r
+.set SCSI_In__3__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_In__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_In__3__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_In__3__MASK, 0x20\r
+.set SCSI_In__3__PC, CYREG_PRT6_PC5\r
+.set SCSI_In__3__PORT, 6\r
+.set SCSI_In__3__PRT, CYREG_PRT6_PRT\r
+.set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_In__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_In__3__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_In__3__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_In__3__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_In__3__PS, CYREG_PRT6_PS\r
+.set SCSI_In__3__SHIFT, 5\r
+.set SCSI_In__3__SLW, CYREG_PRT6_SLW\r
+.set SCSI_In__4__AG, CYREG_PRT6_AG\r
+.set SCSI_In__4__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_In__4__BIE, CYREG_PRT6_BIE\r
+.set SCSI_In__4__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_In__4__BYP, CYREG_PRT6_BYP\r
+.set SCSI_In__4__CTL, CYREG_PRT6_CTL\r
+.set SCSI_In__4__DM0, CYREG_PRT6_DM0\r
+.set SCSI_In__4__DM1, CYREG_PRT6_DM1\r
+.set SCSI_In__4__DM2, CYREG_PRT6_DM2\r
+.set SCSI_In__4__DR, CYREG_PRT6_DR\r
+.set SCSI_In__4__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_In__4__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_In__4__MASK, 0x40\r
+.set SCSI_In__4__PC, CYREG_PRT6_PC6\r
+.set SCSI_In__4__PORT, 6\r
+.set SCSI_In__4__PRT, CYREG_PRT6_PRT\r
+.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_In__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_In__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_In__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_In__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_In__4__PS, CYREG_PRT6_PS\r
+.set SCSI_In__4__SHIFT, 6\r
+.set SCSI_In__4__SLW, CYREG_PRT6_SLW\r
+.set SCSI_In__5__AG, CYREG_PRT6_AG\r
+.set SCSI_In__5__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_In__5__BIE, CYREG_PRT6_BIE\r
+.set SCSI_In__5__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_In__5__BYP, CYREG_PRT6_BYP\r
+.set SCSI_In__5__CTL, CYREG_PRT6_CTL\r
+.set SCSI_In__5__DM0, CYREG_PRT6_DM0\r
+.set SCSI_In__5__DM1, CYREG_PRT6_DM1\r
+.set SCSI_In__5__DM2, CYREG_PRT6_DM2\r
+.set SCSI_In__5__DR, CYREG_PRT6_DR\r
+.set SCSI_In__5__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_In__5__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_In__5__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_In__5__MASK, 0x80\r
+.set SCSI_In__5__PC, CYREG_PRT6_PC7\r
+.set SCSI_In__5__PORT, 6\r
+.set SCSI_In__5__PRT, CYREG_PRT6_PRT\r
+.set SCSI_In__5__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_In__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_In__5__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_In__5__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_In__5__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_In__5__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_In__5__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_In__5__PS, CYREG_PRT6_PS\r
+.set SCSI_In__5__SHIFT, 7\r
+.set SCSI_In__5__SLW, CYREG_PRT6_SLW\r
+.set SCSI_In__6__AG, CYREG_PRT5_AG\r
+.set SCSI_In__6__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__6__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__6__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__6__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__6__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__6__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__6__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__6__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__6__DR, CYREG_PRT5_DR\r
+.set SCSI_In__6__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__6__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__6__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__6__MASK, 0x01\r
+.set SCSI_In__6__PC, CYREG_PRT5_PC0\r
+.set SCSI_In__6__PORT, 5\r
+.set SCSI_In__6__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__6__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__6__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__6__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__6__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__6__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__6__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__6__PS, CYREG_PRT5_PS\r
+.set SCSI_In__6__SHIFT, 0\r
+.set SCSI_In__6__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In__7__AG, CYREG_PRT5_AG\r
+.set SCSI_In__7__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__7__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__7__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__7__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__7__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__7__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__7__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__7__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__7__DR, CYREG_PRT5_DR\r
+.set SCSI_In__7__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__7__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__7__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__7__MASK, 0x02\r
+.set SCSI_In__7__PC, CYREG_PRT5_PC1\r
+.set SCSI_In__7__PORT, 5\r
+.set SCSI_In__7__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__7__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__7__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__7__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__7__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__7__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__7__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__7__PS, CYREG_PRT5_PS\r
+.set SCSI_In__7__SHIFT, 1\r
+.set SCSI_In__7__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In__8__AG, CYREG_PRT5_AG\r
+.set SCSI_In__8__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__8__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__8__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__8__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__8__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__8__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__8__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__8__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__8__DR, CYREG_PRT5_DR\r
+.set SCSI_In__8__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__8__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__8__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__8__MASK, 0x04\r
+.set SCSI_In__8__PC, CYREG_PRT5_PC2\r
+.set SCSI_In__8__PORT, 5\r
+.set SCSI_In__8__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__8__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__8__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__8__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__8__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__8__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__8__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__8__PS, CYREG_PRT5_PS\r
+.set SCSI_In__8__SHIFT, 2\r
+.set SCSI_In__8__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In__9__AG, CYREG_PRT5_AG\r
+.set SCSI_In__9__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__9__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__9__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__9__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__9__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__9__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__9__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__9__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__9__DR, CYREG_PRT5_DR\r
+.set SCSI_In__9__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__9__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__9__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__9__MASK, 0x08\r
+.set SCSI_In__9__PC, CYREG_PRT5_PC3\r
+.set SCSI_In__9__PORT, 5\r
+.set SCSI_In__9__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__9__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__9__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__9__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__9__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__9__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__9__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__9__PS, CYREG_PRT5_PS\r
+.set SCSI_In__9__SHIFT, 3\r
+.set SCSI_In__9__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In__ACK__AG, CYREG_PRT6_AG\r
+.set SCSI_In__ACK__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_In__ACK__BIE, CYREG_PRT6_BIE\r
+.set SCSI_In__ACK__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_In__ACK__BYP, CYREG_PRT6_BYP\r
+.set SCSI_In__ACK__CTL, CYREG_PRT6_CTL\r
+.set SCSI_In__ACK__DM0, CYREG_PRT6_DM0\r
+.set SCSI_In__ACK__DM1, CYREG_PRT6_DM1\r
+.set SCSI_In__ACK__DM2, CYREG_PRT6_DM2\r
+.set SCSI_In__ACK__DR, CYREG_PRT6_DR\r
+.set SCSI_In__ACK__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_In__ACK__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_In__ACK__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_In__ACK__MASK, 0x20\r
+.set SCSI_In__ACK__PC, CYREG_PRT6_PC5\r
+.set SCSI_In__ACK__PORT, 6\r
+.set SCSI_In__ACK__PRT, CYREG_PRT6_PRT\r
+.set SCSI_In__ACK__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_In__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_In__ACK__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_In__ACK__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_In__ACK__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_In__ACK__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_In__ACK__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_In__ACK__PS, CYREG_PRT6_PS\r
+.set SCSI_In__ACK__SHIFT, 5\r
+.set SCSI_In__ACK__SLW, CYREG_PRT6_SLW\r
+.set SCSI_In__ATN__AG, CYREG_PRT12_AG\r
+.set SCSI_In__ATN__BIE, CYREG_PRT12_BIE\r
+.set SCSI_In__ATN__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_In__ATN__BYP, CYREG_PRT12_BYP\r
+.set SCSI_In__ATN__DM0, CYREG_PRT12_DM0\r
+.set SCSI_In__ATN__DM1, CYREG_PRT12_DM1\r
+.set SCSI_In__ATN__DM2, CYREG_PRT12_DM2\r
+.set SCSI_In__ATN__DR, CYREG_PRT12_DR\r
+.set SCSI_In__ATN__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_In__ATN__MASK, 0x20\r
+.set SCSI_In__ATN__PC, CYREG_PRT12_PC5\r
+.set SCSI_In__ATN__PORT, 12\r
+.set SCSI_In__ATN__PRT, CYREG_PRT12_PRT\r
+.set SCSI_In__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_In__ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_In__ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_In__ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_In__ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_In__ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_In__ATN__PS, CYREG_PRT12_PS\r
+.set SCSI_In__ATN__SHIFT, 5\r
+.set SCSI_In__ATN__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_In__ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_In__ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_In__ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_In__ATN__SLW, CYREG_PRT12_SLW\r
+.set SCSI_In__BSY__AG, CYREG_PRT6_AG\r
+.set SCSI_In__BSY__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_In__BSY__BIE, CYREG_PRT6_BIE\r
+.set SCSI_In__BSY__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_In__BSY__BYP, CYREG_PRT6_BYP\r
+.set SCSI_In__BSY__CTL, CYREG_PRT6_CTL\r
+.set SCSI_In__BSY__DM0, CYREG_PRT6_DM0\r
+.set SCSI_In__BSY__DM1, CYREG_PRT6_DM1\r
+.set SCSI_In__BSY__DM2, CYREG_PRT6_DM2\r
+.set SCSI_In__BSY__DR, CYREG_PRT6_DR\r
+.set SCSI_In__BSY__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_In__BSY__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_In__BSY__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_In__BSY__MASK, 0x10\r
+.set SCSI_In__BSY__PC, CYREG_PRT6_PC4\r
+.set SCSI_In__BSY__PORT, 6\r
+.set SCSI_In__BSY__PRT, CYREG_PRT6_PRT\r
+.set SCSI_In__BSY__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_In__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_In__BSY__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_In__BSY__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_In__BSY__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_In__BSY__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_In__BSY__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_In__BSY__PS, CYREG_PRT6_PS\r
+.set SCSI_In__BSY__SHIFT, 4\r
+.set SCSI_In__BSY__SLW, CYREG_PRT6_SLW\r
+.set SCSI_In__CD__AG, CYREG_PRT5_AG\r
+.set SCSI_In__CD__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__CD__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__CD__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__CD__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__CD__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__CD__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__CD__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__CD__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__CD__DR, CYREG_PRT5_DR\r
+.set SCSI_In__CD__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__CD__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__CD__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__CD__MASK, 0x02\r
+.set SCSI_In__CD__PC, CYREG_PRT5_PC1\r
+.set SCSI_In__CD__PORT, 5\r
+.set SCSI_In__CD__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__CD__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__CD__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__CD__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__CD__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__CD__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__CD__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__CD__PS, CYREG_PRT5_PS\r
+.set SCSI_In__CD__SHIFT, 1\r
+.set SCSI_In__CD__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In__DBP__AG, CYREG_PRT12_AG\r
+.set SCSI_In__DBP__BIE, CYREG_PRT12_BIE\r
+.set SCSI_In__DBP__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set SCSI_In__DBP__BYP, CYREG_PRT12_BYP\r
+.set SCSI_In__DBP__DM0, CYREG_PRT12_DM0\r
+.set SCSI_In__DBP__DM1, CYREG_PRT12_DM1\r
+.set SCSI_In__DBP__DM2, CYREG_PRT12_DM2\r
+.set SCSI_In__DBP__DR, CYREG_PRT12_DR\r
+.set SCSI_In__DBP__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set SCSI_In__DBP__MASK, 0x10\r
+.set SCSI_In__DBP__PC, CYREG_PRT12_PC4\r
+.set SCSI_In__DBP__PORT, 12\r
+.set SCSI_In__DBP__PRT, CYREG_PRT12_PRT\r
+.set SCSI_In__DBP__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set SCSI_In__DBP__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set SCSI_In__DBP__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set SCSI_In__DBP__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set SCSI_In__DBP__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set SCSI_In__DBP__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set SCSI_In__DBP__PS, CYREG_PRT12_PS\r
+.set SCSI_In__DBP__SHIFT, 4\r
+.set SCSI_In__DBP__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set SCSI_In__DBP__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set SCSI_In__DBP__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set SCSI_In__DBP__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set SCSI_In__DBP__SLW, CYREG_PRT12_SLW\r
+.set SCSI_In__IO__AG, CYREG_PRT5_AG\r
+.set SCSI_In__IO__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__IO__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__IO__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__IO__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__IO__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__IO__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__IO__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__IO__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__IO__DR, CYREG_PRT5_DR\r
+.set SCSI_In__IO__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__IO__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__IO__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__IO__MASK, 0x08\r
+.set SCSI_In__IO__PC, CYREG_PRT5_PC3\r
+.set SCSI_In__IO__PORT, 5\r
+.set SCSI_In__IO__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__IO__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__IO__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__IO__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__IO__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__IO__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__IO__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__IO__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__IO__PS, CYREG_PRT5_PS\r
+.set SCSI_In__IO__SHIFT, 3\r
+.set SCSI_In__IO__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In__MSG__AG, CYREG_PRT6_AG\r
+.set SCSI_In__MSG__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_In__MSG__BIE, CYREG_PRT6_BIE\r
+.set SCSI_In__MSG__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_In__MSG__BYP, CYREG_PRT6_BYP\r
+.set SCSI_In__MSG__CTL, CYREG_PRT6_CTL\r
+.set SCSI_In__MSG__DM0, CYREG_PRT6_DM0\r
+.set SCSI_In__MSG__DM1, CYREG_PRT6_DM1\r
+.set SCSI_In__MSG__DM2, CYREG_PRT6_DM2\r
+.set SCSI_In__MSG__DR, CYREG_PRT6_DR\r
+.set SCSI_In__MSG__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_In__MSG__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_In__MSG__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_In__MSG__MASK, 0x80\r
+.set SCSI_In__MSG__PC, CYREG_PRT6_PC7\r
+.set SCSI_In__MSG__PORT, 6\r
+.set SCSI_In__MSG__PRT, CYREG_PRT6_PRT\r
+.set SCSI_In__MSG__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_In__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_In__MSG__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_In__MSG__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_In__MSG__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_In__MSG__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_In__MSG__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_In__MSG__PS, CYREG_PRT6_PS\r
+.set SCSI_In__MSG__SHIFT, 7\r
+.set SCSI_In__MSG__SLW, CYREG_PRT6_SLW\r
+.set SCSI_In__REQ__AG, CYREG_PRT5_AG\r
+.set SCSI_In__REQ__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__REQ__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__REQ__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__REQ__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__REQ__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__REQ__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__REQ__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__REQ__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__REQ__DR, CYREG_PRT5_DR\r
+.set SCSI_In__REQ__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__REQ__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__REQ__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__REQ__MASK, 0x04\r
+.set SCSI_In__REQ__PC, CYREG_PRT5_PC2\r
+.set SCSI_In__REQ__PORT, 5\r
+.set SCSI_In__REQ__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__REQ__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__REQ__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__REQ__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__REQ__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__REQ__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__REQ__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__REQ__PS, CYREG_PRT5_PS\r
+.set SCSI_In__REQ__SHIFT, 2\r
+.set SCSI_In__REQ__SLW, CYREG_PRT5_SLW\r
+.set SCSI_In__RST__AG, CYREG_PRT6_AG\r
+.set SCSI_In__RST__AMUX, CYREG_PRT6_AMUX\r
+.set SCSI_In__RST__BIE, CYREG_PRT6_BIE\r
+.set SCSI_In__RST__BIT_MASK, CYREG_PRT6_BIT_MASK\r
+.set SCSI_In__RST__BYP, CYREG_PRT6_BYP\r
+.set SCSI_In__RST__CTL, CYREG_PRT6_CTL\r
+.set SCSI_In__RST__DM0, CYREG_PRT6_DM0\r
+.set SCSI_In__RST__DM1, CYREG_PRT6_DM1\r
+.set SCSI_In__RST__DM2, CYREG_PRT6_DM2\r
+.set SCSI_In__RST__DR, CYREG_PRT6_DR\r
+.set SCSI_In__RST__INP_DIS, CYREG_PRT6_INP_DIS\r
+.set SCSI_In__RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG\r
+.set SCSI_In__RST__LCD_EN, CYREG_PRT6_LCD_EN\r
+.set SCSI_In__RST__MASK, 0x40\r
+.set SCSI_In__RST__PC, CYREG_PRT6_PC6\r
+.set SCSI_In__RST__PORT, 6\r
+.set SCSI_In__RST__PRT, CYREG_PRT6_PRT\r
+.set SCSI_In__RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL\r
+.set SCSI_In__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN\r
+.set SCSI_In__RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0\r
+.set SCSI_In__RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1\r
+.set SCSI_In__RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0\r
+.set SCSI_In__RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1\r
+.set SCSI_In__RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT\r
+.set SCSI_In__RST__PS, CYREG_PRT6_PS\r
+.set SCSI_In__RST__SHIFT, 6\r
+.set SCSI_In__RST__SLW, CYREG_PRT6_SLW\r
+.set SCSI_In__SEL__AG, CYREG_PRT5_AG\r
+.set SCSI_In__SEL__AMUX, CYREG_PRT5_AMUX\r
+.set SCSI_In__SEL__BIE, CYREG_PRT5_BIE\r
+.set SCSI_In__SEL__BIT_MASK, CYREG_PRT5_BIT_MASK\r
+.set SCSI_In__SEL__BYP, CYREG_PRT5_BYP\r
+.set SCSI_In__SEL__CTL, CYREG_PRT5_CTL\r
+.set SCSI_In__SEL__DM0, CYREG_PRT5_DM0\r
+.set SCSI_In__SEL__DM1, CYREG_PRT5_DM1\r
+.set SCSI_In__SEL__DM2, CYREG_PRT5_DM2\r
+.set SCSI_In__SEL__DR, CYREG_PRT5_DR\r
+.set SCSI_In__SEL__INP_DIS, CYREG_PRT5_INP_DIS\r
+.set SCSI_In__SEL__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG\r
+.set SCSI_In__SEL__LCD_EN, CYREG_PRT5_LCD_EN\r
+.set SCSI_In__SEL__MASK, 0x01\r
+.set SCSI_In__SEL__PC, CYREG_PRT5_PC0\r
+.set SCSI_In__SEL__PORT, 5\r
+.set SCSI_In__SEL__PRT, CYREG_PRT5_PRT\r
+.set SCSI_In__SEL__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL\r
+.set SCSI_In__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN\r
+.set SCSI_In__SEL__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0\r
+.set SCSI_In__SEL__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1\r
+.set SCSI_In__SEL__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0\r
+.set SCSI_In__SEL__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1\r
+.set SCSI_In__SEL__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT\r
+.set SCSI_In__SEL__PS, CYREG_PRT5_PS\r
+.set SCSI_In__SEL__SHIFT, 0\r
+.set SCSI_In__SEL__SLW, CYREG_PRT5_SLW\r
+\r
+/* SD_DAT1 */\r
+.set SD_DAT1__0__MASK, 0x20\r
+.set SD_DAT1__0__PC, CYREG_PRT3_PC5\r
+.set SD_DAT1__0__PORT, 3\r
+.set SD_DAT1__0__SHIFT, 5\r
+.set SD_DAT1__AG, CYREG_PRT3_AG\r
+.set SD_DAT1__AMUX, CYREG_PRT3_AMUX\r
+.set SD_DAT1__BIE, CYREG_PRT3_BIE\r
+.set SD_DAT1__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_DAT1__BYP, CYREG_PRT3_BYP\r
+.set SD_DAT1__CTL, CYREG_PRT3_CTL\r
+.set SD_DAT1__DM0, CYREG_PRT3_DM0\r
+.set SD_DAT1__DM1, CYREG_PRT3_DM1\r
+.set SD_DAT1__DM2, CYREG_PRT3_DM2\r
+.set SD_DAT1__DR, CYREG_PRT3_DR\r
+.set SD_DAT1__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_DAT1__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_DAT1__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_DAT1__MASK, 0x20\r
+.set SD_DAT1__PORT, 3\r
+.set SD_DAT1__PRT, CYREG_PRT3_PRT\r
+.set SD_DAT1__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_DAT1__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_DAT1__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_DAT1__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_DAT1__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_DAT1__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_DAT1__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_DAT1__PS, CYREG_PRT3_PS\r
+.set SD_DAT1__SHIFT, 5\r
+.set SD_DAT1__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_DAT2 */\r
+.set SD_DAT2__0__MASK, 0x01\r
+.set SD_DAT2__0__PC, CYREG_PRT3_PC0\r
+.set SD_DAT2__0__PORT, 3\r
+.set SD_DAT2__0__SHIFT, 0\r
+.set SD_DAT2__AG, CYREG_PRT3_AG\r
+.set SD_DAT2__AMUX, CYREG_PRT3_AMUX\r
+.set SD_DAT2__BIE, CYREG_PRT3_BIE\r
+.set SD_DAT2__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_DAT2__BYP, CYREG_PRT3_BYP\r
+.set SD_DAT2__CTL, CYREG_PRT3_CTL\r
+.set SD_DAT2__DM0, CYREG_PRT3_DM0\r
+.set SD_DAT2__DM1, CYREG_PRT3_DM1\r
+.set SD_DAT2__DM2, CYREG_PRT3_DM2\r
+.set SD_DAT2__DR, CYREG_PRT3_DR\r
+.set SD_DAT2__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_DAT2__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_DAT2__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_DAT2__MASK, 0x01\r
+.set SD_DAT2__PORT, 3\r
+.set SD_DAT2__PRT, CYREG_PRT3_PRT\r
+.set SD_DAT2__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_DAT2__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_DAT2__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_DAT2__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_DAT2__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_DAT2__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_DAT2__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_DAT2__PS, CYREG_PRT3_PS\r
+.set SD_DAT2__SHIFT, 0\r
+.set SD_DAT2__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_MISO */\r
+.set SD_MISO__0__MASK, 0x10\r
+.set SD_MISO__0__PC, CYREG_PRT3_PC4\r
+.set SD_MISO__0__PORT, 3\r
+.set SD_MISO__0__SHIFT, 4\r
+.set SD_MISO__AG, CYREG_PRT3_AG\r
+.set SD_MISO__AMUX, CYREG_PRT3_AMUX\r
+.set SD_MISO__BIE, CYREG_PRT3_BIE\r
+.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_MISO__BYP, CYREG_PRT3_BYP\r
+.set SD_MISO__CTL, CYREG_PRT3_CTL\r
+.set SD_MISO__DM0, CYREG_PRT3_DM0\r
+.set SD_MISO__DM1, CYREG_PRT3_DM1\r
+.set SD_MISO__DM2, CYREG_PRT3_DM2\r
+.set SD_MISO__DR, CYREG_PRT3_DR\r
+.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_MISO__MASK, 0x10\r
+.set SD_MISO__PORT, 3\r
+.set SD_MISO__PRT, CYREG_PRT3_PRT\r
+.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_MISO__PS, CYREG_PRT3_PS\r
+.set SD_MISO__SHIFT, 4\r
+.set SD_MISO__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_MOSI */\r
+.set SD_MOSI__0__MASK, 0x04\r
+.set SD_MOSI__0__PC, CYREG_PRT3_PC2\r
+.set SD_MOSI__0__PORT, 3\r
+.set SD_MOSI__0__SHIFT, 2\r
+.set SD_MOSI__AG, CYREG_PRT3_AG\r
+.set SD_MOSI__AMUX, CYREG_PRT3_AMUX\r
+.set SD_MOSI__BIE, CYREG_PRT3_BIE\r
+.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_MOSI__BYP, CYREG_PRT3_BYP\r
+.set SD_MOSI__CTL, CYREG_PRT3_CTL\r
+.set SD_MOSI__DM0, CYREG_PRT3_DM0\r
+.set SD_MOSI__DM1, CYREG_PRT3_DM1\r
+.set SD_MOSI__DM2, CYREG_PRT3_DM2\r
+.set SD_MOSI__DR, CYREG_PRT3_DR\r
+.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_MOSI__MASK, 0x04\r
+.set SD_MOSI__PORT, 3\r
+.set SD_MOSI__PRT, CYREG_PRT3_PRT\r
+.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_MOSI__PS, CYREG_PRT3_PS\r
+.set SD_MOSI__SHIFT, 2\r
+.set SD_MOSI__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_SCK */\r
+.set SD_SCK__0__MASK, 0x08\r
+.set SD_SCK__0__PC, CYREG_PRT3_PC3\r
+.set SD_SCK__0__PORT, 3\r
+.set SD_SCK__0__SHIFT, 3\r
+.set SD_SCK__AG, CYREG_PRT3_AG\r
+.set SD_SCK__AMUX, CYREG_PRT3_AMUX\r
+.set SD_SCK__BIE, CYREG_PRT3_BIE\r
+.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_SCK__BYP, CYREG_PRT3_BYP\r
+.set SD_SCK__CTL, CYREG_PRT3_CTL\r
+.set SD_SCK__DM0, CYREG_PRT3_DM0\r
+.set SD_SCK__DM1, CYREG_PRT3_DM1\r
+.set SD_SCK__DM2, CYREG_PRT3_DM2\r
+.set SD_SCK__DR, CYREG_PRT3_DR\r
+.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_SCK__MASK, 0x08\r
+.set SD_SCK__PORT, 3\r
+.set SD_SCK__PRT, CYREG_PRT3_PRT\r
+.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_SCK__PS, CYREG_PRT3_PS\r
+.set SD_SCK__SHIFT, 3\r
+.set SD_SCK__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_CD */\r
+.set SD_CD__0__MASK, 0x40\r
+.set SD_CD__0__PC, CYREG_PRT3_PC6\r
+.set SD_CD__0__PORT, 3\r
+.set SD_CD__0__SHIFT, 6\r
+.set SD_CD__AG, CYREG_PRT3_AG\r
+.set SD_CD__AMUX, CYREG_PRT3_AMUX\r
+.set SD_CD__BIE, CYREG_PRT3_BIE\r
+.set SD_CD__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_CD__BYP, CYREG_PRT3_BYP\r
+.set SD_CD__CTL, CYREG_PRT3_CTL\r
+.set SD_CD__DM0, CYREG_PRT3_DM0\r
+.set SD_CD__DM1, CYREG_PRT3_DM1\r
+.set SD_CD__DM2, CYREG_PRT3_DM2\r
+.set SD_CD__DR, CYREG_PRT3_DR\r
+.set SD_CD__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_CD__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_CD__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_CD__MASK, 0x40\r
+.set SD_CD__PORT, 3\r
+.set SD_CD__PRT, CYREG_PRT3_PRT\r
+.set SD_CD__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_CD__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_CD__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_CD__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_CD__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_CD__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_CD__PS, CYREG_PRT3_PS\r
+.set SD_CD__SHIFT, 6\r
+.set SD_CD__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_CS */\r
+.set SD_CS__0__MASK, 0x02\r
+.set SD_CS__0__PC, CYREG_PRT3_PC1\r
+.set SD_CS__0__PORT, 3\r
+.set SD_CS__0__SHIFT, 1\r
+.set SD_CS__AG, CYREG_PRT3_AG\r
+.set SD_CS__AMUX, CYREG_PRT3_AMUX\r
+.set SD_CS__BIE, CYREG_PRT3_BIE\r
+.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_CS__BYP, CYREG_PRT3_BYP\r
+.set SD_CS__CTL, CYREG_PRT3_CTL\r
+.set SD_CS__DM0, CYREG_PRT3_DM0\r
+.set SD_CS__DM1, CYREG_PRT3_DM1\r
+.set SD_CS__DM2, CYREG_PRT3_DM2\r
+.set SD_CS__DR, CYREG_PRT3_DR\r
+.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_CS__MASK, 0x02\r
+.set SD_CS__PORT, 3\r
+.set SD_CS__PRT, CYREG_PRT3_PRT\r
+.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_CS__PS, CYREG_PRT3_PS\r
+.set SD_CS__SHIFT, 1\r
+.set SD_CS__SLW, CYREG_PRT3_SLW\r
+\r
+/* SD_WP */\r
+.set SD_WP__0__MASK, 0x80\r
+.set SD_WP__0__PC, CYREG_PRT3_PC7\r
+.set SD_WP__0__PORT, 3\r
+.set SD_WP__0__SHIFT, 7\r
+.set SD_WP__AG, CYREG_PRT3_AG\r
+.set SD_WP__AMUX, CYREG_PRT3_AMUX\r
+.set SD_WP__BIE, CYREG_PRT3_BIE\r
+.set SD_WP__BIT_MASK, CYREG_PRT3_BIT_MASK\r
+.set SD_WP__BYP, CYREG_PRT3_BYP\r
+.set SD_WP__CTL, CYREG_PRT3_CTL\r
+.set SD_WP__DM0, CYREG_PRT3_DM0\r
+.set SD_WP__DM1, CYREG_PRT3_DM1\r
+.set SD_WP__DM2, CYREG_PRT3_DM2\r
+.set SD_WP__DR, CYREG_PRT3_DR\r
+.set SD_WP__INP_DIS, CYREG_PRT3_INP_DIS\r
+.set SD_WP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG\r
+.set SD_WP__LCD_EN, CYREG_PRT3_LCD_EN\r
+.set SD_WP__MASK, 0x80\r
+.set SD_WP__PORT, 3\r
+.set SD_WP__PRT, CYREG_PRT3_PRT\r
+.set SD_WP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL\r
+.set SD_WP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN\r
+.set SD_WP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0\r
+.set SD_WP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1\r
+.set SD_WP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0\r
+.set SD_WP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1\r
+.set SD_WP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT\r
+.set SD_WP__PS, CYREG_PRT3_PS\r
+.set SD_WP__SHIFT, 7\r
+.set SD_WP__SLW, CYREG_PRT3_SLW\r
+\r
+/* LED1 */\r
+.set LED1__0__MASK, 0x08\r
+.set LED1__0__PC, CYREG_PRT12_PC3\r
+.set LED1__0__PORT, 12\r
+.set LED1__0__SHIFT, 3\r
+.set LED1__AG, CYREG_PRT12_AG\r
+.set LED1__BIE, CYREG_PRT12_BIE\r
+.set LED1__BIT_MASK, CYREG_PRT12_BIT_MASK\r
+.set LED1__BYP, CYREG_PRT12_BYP\r
+.set LED1__DM0, CYREG_PRT12_DM0\r
+.set LED1__DM1, CYREG_PRT12_DM1\r
+.set LED1__DM2, CYREG_PRT12_DM2\r
+.set LED1__DR, CYREG_PRT12_DR\r
+.set LED1__INP_DIS, CYREG_PRT12_INP_DIS\r
+.set LED1__MASK, 0x08\r
+.set LED1__PORT, 12\r
+.set LED1__PRT, CYREG_PRT12_PRT\r
+.set LED1__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN\r
+.set LED1__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0\r
+.set LED1__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1\r
+.set LED1__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0\r
+.set LED1__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1\r
+.set LED1__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT\r
+.set LED1__PS, CYREG_PRT12_PS\r
+.set LED1__SHIFT, 3\r
+.set LED1__SIO_CFG, CYREG_PRT12_SIO_CFG\r
+.set LED1__SIO_DIFF, CYREG_PRT12_SIO_DIFF\r
+.set LED1__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN\r
+.set LED1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ\r
+.set LED1__SLW, CYREG_PRT12_SLW\r
+\r
+/* Miscellaneous */\r
+/* -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release */\r
+.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6\r
+.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0\r
+.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0\r
+.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1\r
+.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0\r
+.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0\r
+.set CYDEV_CHIP_MEMBER_5B, 4\r
+.set CYDEV_CHIP_FAMILY_PSOC5, 3\r
+.set CYDEV_CHIP_DIE_PSOC5LP, 4\r
+.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_DIE_PSOC5LP\r
+.set BCLK__BUS_CLK__HZ, 64000000\r
+.set BCLK__BUS_CLK__KHZ, 64000\r
+.set BCLK__BUS_CLK__MHZ, 64\r
+.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT\r
+.set CYDEV_CHIP_DIE_LEOPARD, 1\r
+.set CYDEV_CHIP_DIE_PANTHER, 3\r
+.set CYDEV_CHIP_DIE_PSOC4A, 2\r
+.set CYDEV_CHIP_DIE_UNKNOWN, 0\r
+.set CYDEV_CHIP_FAMILY_PSOC3, 1\r
+.set CYDEV_CHIP_FAMILY_PSOC4, 2\r
+.set CYDEV_CHIP_FAMILY_UNKNOWN, 0\r
+.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5\r
+.set CYDEV_CHIP_JTAG_ID, 0x2E12F069\r
+.set CYDEV_CHIP_MEMBER_3A, 1\r
+.set CYDEV_CHIP_MEMBER_4A, 2\r
+.set CYDEV_CHIP_MEMBER_5A, 3\r
+.set CYDEV_CHIP_MEMBER_UNKNOWN, 0\r
+.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B\r
+.set CYDEV_CHIP_REVISION_3A_ES1, 0\r
+.set CYDEV_CHIP_REVISION_3A_ES2, 1\r
+.set CYDEV_CHIP_REVISION_3A_ES3, 3\r
+.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3\r
+.set CYDEV_CHIP_REVISION_4A_ES0, 17\r
+.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17\r
+.set CYDEV_CHIP_REVISION_5A_ES0, 0\r
+.set CYDEV_CHIP_REVISION_5A_ES1, 1\r
+.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1\r
+.set CYDEV_CHIP_REVISION_5B_ES0, 0\r
+.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION\r
+.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REV_PSOC5LP_PRODUCTION\r
+.set CYDEV_CHIP_REV_LEOPARD_ES1, 0\r
+.set CYDEV_CHIP_REV_LEOPARD_ES2, 1\r
+.set CYDEV_CHIP_REV_LEOPARD_ES3, 3\r
+.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3\r
+.set CYDEV_CHIP_REV_PANTHER_ES0, 0\r
+.set CYDEV_CHIP_REV_PANTHER_ES1, 1\r
+.set CYDEV_CHIP_REV_PANTHER_PRODUCTION, 1\r
+.set CYDEV_CHIP_REV_PSOC4A_ES0, 17\r
+.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17\r
+.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0\r
+.set CYDEV_CONFIGURATION_COMPRESSED, 1\r
+.set CYDEV_CONFIGURATION_DMA, 0\r
+.set CYDEV_CONFIGURATION_ECC, 1\r
+.set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED\r
+.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED\r
+.set CYDEV_CONFIGURATION_MODE_DMA, 2\r
+.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1\r
+.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
+.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1\r
+.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2\r
+.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV\r
+.set CYDEV_DEBUGGING_DPS_Disable, 3\r
+.set CYDEV_DEBUGGING_DPS_JTAG_4, 1\r
+.set CYDEV_DEBUGGING_DPS_JTAG_5, 0\r
+.set CYDEV_DEBUGGING_DPS_SWD, 2\r
+.set CYDEV_DEBUGGING_ENABLE, 1\r
+.set CYDEV_DEBUGGING_REQXRES, 1\r
+.set CYDEV_DEBUGGING_XRES, 0\r
+.set CYDEV_DEBUG_ENABLE_MASK, 0x20\r
+.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG\r
+.set CYDEV_DMA_CHANNELS_AVAILABLE, 24\r
+.set CYDEV_ECC_ENABLE, 0\r
+.set CYDEV_HEAP_SIZE, 0x1000\r
+.set CYDEV_INSTRUCT_CACHE_ENABLED, 1\r
+.set CYDEV_INTR_RISING, 0x00000003\r
+.set CYDEV_PROJ_TYPE, 0\r
+.set CYDEV_PROJ_TYPE_BOOTLOADER, 1\r
+.set CYDEV_PROJ_TYPE_LOADABLE, 2\r
+.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3\r
+.set CYDEV_PROJ_TYPE_STANDARD, 0\r
+.set CYDEV_PROTECTION_ENABLE, 0\r
+.set CYDEV_STACK_SIZE, 0x4000\r
+.set CYDEV_USE_BUNDLED_CMSIS, 1\r
+.set CYDEV_VARIABLE_VDDA, 0\r
+.set CYDEV_VDDA_MV, 5000\r
+.set CYDEV_VDDD_MV, 5000\r
+.set CYDEV_VDDIO0_MV, 5000\r
+.set CYDEV_VDDIO1_MV, 5000\r
+.set CYDEV_VDDIO2_MV, 5000\r
+.set CYDEV_VDDIO3_MV, 3300\r
+.set CYDEV_VIO0, 5\r
+.set CYDEV_VIO0_MV, 5000\r
+.set CYDEV_VIO1, 5\r
+.set CYDEV_VIO1_MV, 5000\r
+.set CYDEV_VIO2, 5\r
+.set CYDEV_VIO2_MV, 5000\r
+.set CYDEV_VIO3_MV, 3300\r
+.set DMA_CHANNELS_USED__MASK0, 0x00000000\r
+.set CYDEV_BOOTLOADER_ENABLE, 0\r
+.endif\r
--- /dev/null
+ IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC\r
+INCLUDED_CYFITTERRV_INC EQU 1\r
+ GET cydevicerv.inc\r
+ GET cydevicerv_trm.inc\r
+\r
+; SDCard_RxInternalInterrupt\r
+SDCard_RxInternalInterrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SDCard_RxInternalInterrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SDCard_RxInternalInterrupt__INTC_MASK EQU 0x01\r
+SDCard_RxInternalInterrupt__INTC_NUMBER EQU 0\r
+SDCard_RxInternalInterrupt__INTC_PRIOR_NUM EQU 7\r
+SDCard_RxInternalInterrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0\r
+SDCard_RxInternalInterrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SDCard_RxInternalInterrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SDCard_TxInternalInterrupt\r
+SDCard_TxInternalInterrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
+SDCard_TxInternalInterrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
+SDCard_TxInternalInterrupt__INTC_MASK EQU 0x02\r
+SDCard_TxInternalInterrupt__INTC_NUMBER EQU 1\r
+SDCard_TxInternalInterrupt__INTC_PRIOR_NUM EQU 7\r
+SDCard_TxInternalInterrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1\r
+SDCard_TxInternalInterrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
+SDCard_TxInternalInterrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
+\r
+; SCSI_Out_DBx\r
+SCSI_Out_DBx__0__MASK EQU 0x01\r
+SCSI_Out_DBx__0__PC EQU CYREG_PRT0_PC0\r
+SCSI_Out_DBx__0__PORT EQU 0\r
+SCSI_Out_DBx__0__SHIFT EQU 0\r
+SCSI_Out_DBx__1__MASK EQU 0x02\r
+SCSI_Out_DBx__1__PC EQU CYREG_PRT0_PC1\r
+SCSI_Out_DBx__1__PORT EQU 0\r
+SCSI_Out_DBx__1__SHIFT EQU 1\r
+SCSI_Out_DBx__2__MASK EQU 0x04\r
+SCSI_Out_DBx__2__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out_DBx__2__PORT EQU 0\r
+SCSI_Out_DBx__2__SHIFT EQU 2\r
+SCSI_Out_DBx__3__MASK EQU 0x08\r
+SCSI_Out_DBx__3__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out_DBx__3__PORT EQU 0\r
+SCSI_Out_DBx__3__SHIFT EQU 3\r
+SCSI_Out_DBx__4__MASK EQU 0x10\r
+SCSI_Out_DBx__4__PC EQU CYREG_PRT0_PC4\r
+SCSI_Out_DBx__4__PORT EQU 0\r
+SCSI_Out_DBx__4__SHIFT EQU 4\r
+SCSI_Out_DBx__5__MASK EQU 0x20\r
+SCSI_Out_DBx__5__PC EQU CYREG_PRT0_PC5\r
+SCSI_Out_DBx__5__PORT EQU 0\r
+SCSI_Out_DBx__5__SHIFT EQU 5\r
+SCSI_Out_DBx__6__MASK EQU 0x40\r
+SCSI_Out_DBx__6__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out_DBx__6__PORT EQU 0\r
+SCSI_Out_DBx__6__SHIFT EQU 6\r
+SCSI_Out_DBx__7__MASK EQU 0x80\r
+SCSI_Out_DBx__7__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out_DBx__7__PORT EQU 0\r
+SCSI_Out_DBx__7__SHIFT EQU 7\r
+SCSI_Out_DBx__AG EQU CYREG_PRT0_AG\r
+SCSI_Out_DBx__AMUX EQU CYREG_PRT0_AMUX\r
+SCSI_Out_DBx__BIE EQU CYREG_PRT0_BIE\r
+SCSI_Out_DBx__BIT_MASK EQU CYREG_PRT0_BIT_MASK\r
+SCSI_Out_DBx__BYP EQU CYREG_PRT0_BYP\r
+SCSI_Out_DBx__CTL EQU CYREG_PRT0_CTL\r
+SCSI_Out_DBx__DM0 EQU CYREG_PRT0_DM0\r
+SCSI_Out_DBx__DM1 EQU CYREG_PRT0_DM1\r
+SCSI_Out_DBx__DM2 EQU CYREG_PRT0_DM2\r
+SCSI_Out_DBx__DR EQU CYREG_PRT0_DR\r
+SCSI_Out_DBx__INP_DIS EQU CYREG_PRT0_INP_DIS\r
+SCSI_Out_DBx__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG\r
+SCSI_Out_DBx__LCD_EN EQU CYREG_PRT0_LCD_EN\r
+SCSI_Out_DBx__MASK EQU 0xFF\r
+SCSI_Out_DBx__PORT EQU 0\r
+SCSI_Out_DBx__PRT EQU CYREG_PRT0_PRT\r
+SCSI_Out_DBx__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL\r
+SCSI_Out_DBx__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN\r
+SCSI_Out_DBx__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0\r
+SCSI_Out_DBx__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1\r
+SCSI_Out_DBx__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0\r
+SCSI_Out_DBx__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1\r
+SCSI_Out_DBx__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT\r
+SCSI_Out_DBx__PS EQU CYREG_PRT0_PS\r
+SCSI_Out_DBx__SCSI_Out_DB0__MASK EQU 0x01\r
+SCSI_Out_DBx__SCSI_Out_DB0__PC EQU CYREG_PRT0_PC0\r
+SCSI_Out_DBx__SCSI_Out_DB0__PORT EQU 0\r
+SCSI_Out_DBx__SCSI_Out_DB0__SHIFT EQU 0\r
+SCSI_Out_DBx__SCSI_Out_DB1__MASK EQU 0x02\r
+SCSI_Out_DBx__SCSI_Out_DB1__PC EQU CYREG_PRT0_PC1\r
+SCSI_Out_DBx__SCSI_Out_DB1__PORT EQU 0\r
+SCSI_Out_DBx__SCSI_Out_DB1__SHIFT EQU 1\r
+SCSI_Out_DBx__SCSI_Out_DB2__MASK EQU 0x04\r
+SCSI_Out_DBx__SCSI_Out_DB2__PC EQU CYREG_PRT0_PC2\r
+SCSI_Out_DBx__SCSI_Out_DB2__PORT EQU 0\r
+SCSI_Out_DBx__SCSI_Out_DB2__SHIFT EQU 2\r
+SCSI_Out_DBx__SCSI_Out_DB3__MASK EQU 0x08\r
+SCSI_Out_DBx__SCSI_Out_DB3__PC EQU CYREG_PRT0_PC3\r
+SCSI_Out_DBx__SCSI_Out_DB3__PORT EQU 0\r
+SCSI_Out_DBx__SCSI_Out_DB3__SHIFT EQU 3\r
+SCSI_Out_DBx__SCSI_Out_DB4__MASK EQU 0x10\r
+SCSI_Out_DBx__SCSI_Out_DB4__PC EQU CYREG_PRT0_PC4\r
+SCSI_Out_DBx__SCSI_Out_DB4__PORT EQU 0\r
+SCSI_Out_DBx__SCSI_Out_DB4__SHIFT EQU 4\r
+SCSI_Out_DBx__SCSI_Out_DB5__MASK EQU 0x20\r
+SCSI_Out_DBx__SCSI_Out_DB5__PC EQU CYREG_PRT0_PC5\r
+SCSI_Out_DBx__SCSI_Out_DB5__PORT EQU 0\r
+SCSI_Out_DBx__SCSI_Out_DB5__SHIFT EQU 5\r
+SCSI_Out_DBx__SCSI_Out_DB6__MASK EQU 0x40\r
+SCSI_Out_DBx__SCSI_Out_DB6__PC EQU CYREG_PRT0_PC6\r
+SCSI_Out_DBx__SCSI_Out_DB6__PORT EQU 0\r
+SCSI_Out_DBx__SCSI_Out_DB6__SHIFT EQU 6\r
+SCSI_Out_DBx__SCSI_Out_DB7__MASK EQU 0x80\r
+SCSI_Out_DBx__SCSI_Out_DB7__PC EQU CYREG_PRT0_PC7\r
+SCSI_Out_DBx__SCSI_Out_DB7__PORT EQU 0\r
+SCSI_Out_DBx__SCSI_Out_DB7__SHIFT EQU 7\r
+SCSI_Out_DBx__SHIFT EQU 0\r
+SCSI_Out_DBx__SLW EQU CYREG_PRT0_SLW\r
+\r
+; SDCard_BSPIM\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST\r
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST\r
+SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
+SDCard_BSPIM_RxStsReg__5__POS EQU 5\r
+SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
+SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
+SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST\r
+SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
+SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST\r
+SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
+SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
+SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
+SDCard_BSPIM_TxStsReg__2__POS EQU 2\r
+SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08\r
+SDCard_BSPIM_TxStsReg__3__POS EQU 3\r
+SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
+SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
+SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB07_08_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB07_08_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB07_08_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB07_08_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB07_08_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB07_08_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB07_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB07_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB07_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB07_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB07_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB07_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB07_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB07_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB07_F1\r
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+\r
+; SCSI_In_DBx\r
+SCSI_In_DBx__0__MASK EQU 0x01\r
+SCSI_In_DBx__0__PC EQU CYREG_PRT2_PC0\r
+SCSI_In_DBx__0__PORT EQU 2\r
+SCSI_In_DBx__0__SHIFT EQU 0\r
+SCSI_In_DBx__1__MASK EQU 0x02\r
+SCSI_In_DBx__1__PC EQU CYREG_PRT2_PC1\r
+SCSI_In_DBx__1__PORT EQU 2\r
+SCSI_In_DBx__1__SHIFT EQU 1\r
+SCSI_In_DBx__2__MASK EQU 0x04\r
+SCSI_In_DBx__2__PC EQU CYREG_PRT2_PC2\r
+SCSI_In_DBx__2__PORT EQU 2\r
+SCSI_In_DBx__2__SHIFT EQU 2\r
+SCSI_In_DBx__3__MASK EQU 0x08\r
+SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC3\r
+SCSI_In_DBx__3__PORT EQU 2\r
+SCSI_In_DBx__3__SHIFT EQU 3\r
+SCSI_In_DBx__4__MASK EQU 0x10\r
+SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__4__PORT EQU 2\r
+SCSI_In_DBx__4__SHIFT EQU 4\r
+SCSI_In_DBx__5__MASK EQU 0x20\r
+SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__5__PORT EQU 2\r
+SCSI_In_DBx__5__SHIFT EQU 5\r
+SCSI_In_DBx__6__MASK EQU 0x40\r
+SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC6\r
+SCSI_In_DBx__6__PORT EQU 2\r
+SCSI_In_DBx__6__SHIFT EQU 6\r
+SCSI_In_DBx__7__MASK EQU 0x80\r
+SCSI_In_DBx__7__PC EQU CYREG_PRT2_PC7\r
+SCSI_In_DBx__7__PORT EQU 2\r
+SCSI_In_DBx__7__SHIFT EQU 7\r
+SCSI_In_DBx__AG EQU CYREG_PRT2_AG\r
+SCSI_In_DBx__AMUX EQU CYREG_PRT2_AMUX\r
+SCSI_In_DBx__BIE EQU CYREG_PRT2_BIE\r
+SCSI_In_DBx__BIT_MASK EQU CYREG_PRT2_BIT_MASK\r
+SCSI_In_DBx__BYP EQU CYREG_PRT2_BYP\r
+SCSI_In_DBx__CTL EQU CYREG_PRT2_CTL\r
+SCSI_In_DBx__DM0 EQU CYREG_PRT2_DM0\r
+SCSI_In_DBx__DM1 EQU CYREG_PRT2_DM1\r
+SCSI_In_DBx__DM2 EQU CYREG_PRT2_DM2\r
+SCSI_In_DBx__DR EQU CYREG_PRT2_DR\r
+SCSI_In_DBx__INP_DIS EQU CYREG_PRT2_INP_DIS\r
+SCSI_In_DBx__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG\r
+SCSI_In_DBx__LCD_EN EQU CYREG_PRT2_LCD_EN\r
+SCSI_In_DBx__MASK EQU 0xFF\r
+SCSI_In_DBx__PORT EQU 2\r
+SCSI_In_DBx__PRT EQU CYREG_PRT2_PRT\r
+SCSI_In_DBx__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL\r
+SCSI_In_DBx__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN\r
+SCSI_In_DBx__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0\r
+SCSI_In_DBx__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1\r
+SCSI_In_DBx__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0\r
+SCSI_In_DBx__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1\r
+SCSI_In_DBx__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT\r
+SCSI_In_DBx__PS EQU CYREG_PRT2_PS\r
+SCSI_In_DBx__SCSI_Out_DB0__MASK EQU 0x01\r
+SCSI_In_DBx__SCSI_Out_DB0__PC EQU CYREG_PRT2_PC0\r
+SCSI_In_DBx__SCSI_Out_DB0__PORT EQU 2\r
+SCSI_In_DBx__SCSI_Out_DB0__SHIFT EQU 0\r
+SCSI_In_DBx__SCSI_Out_DB1__MASK EQU 0x02\r
+SCSI_In_DBx__SCSI_Out_DB1__PC EQU CYREG_PRT2_PC1\r
+SCSI_In_DBx__SCSI_Out_DB1__PORT EQU 2\r
+SCSI_In_DBx__SCSI_Out_DB1__SHIFT EQU 1\r
+SCSI_In_DBx__SCSI_Out_DB2__MASK EQU 0x04\r
+SCSI_In_DBx__SCSI_Out_DB2__PC EQU CYREG_PRT2_PC2\r
+SCSI_In_DBx__SCSI_Out_DB2__PORT EQU 2\r
+SCSI_In_DBx__SCSI_Out_DB2__SHIFT EQU 2\r
+SCSI_In_DBx__SCSI_Out_DB3__MASK EQU 0x08\r
+SCSI_In_DBx__SCSI_Out_DB3__PC EQU CYREG_PRT2_PC3\r
+SCSI_In_DBx__SCSI_Out_DB3__PORT EQU 2\r
+SCSI_In_DBx__SCSI_Out_DB3__SHIFT EQU 3\r
+SCSI_In_DBx__SCSI_Out_DB4__MASK EQU 0x10\r
+SCSI_In_DBx__SCSI_Out_DB4__PC EQU CYREG_PRT2_PC4\r
+SCSI_In_DBx__SCSI_Out_DB4__PORT EQU 2\r
+SCSI_In_DBx__SCSI_Out_DB4__SHIFT EQU 4\r
+SCSI_In_DBx__SCSI_Out_DB5__MASK EQU 0x20\r
+SCSI_In_DBx__SCSI_Out_DB5__PC EQU CYREG_PRT2_PC5\r
+SCSI_In_DBx__SCSI_Out_DB5__PORT EQU 2\r
+SCSI_In_DBx__SCSI_Out_DB5__SHIFT EQU 5\r
+SCSI_In_DBx__SCSI_Out_DB6__MASK EQU 0x40\r
+SCSI_In_DBx__SCSI_Out_DB6__PC EQU CYREG_PRT2_PC6\r
+SCSI_In_DBx__SCSI_Out_DB6__PORT EQU 2\r
+SCSI_In_DBx__SCSI_Out_DB6__SHIFT EQU 6\r
+SCSI_In_DBx__SCSI_Out_DB7__MASK EQU 0x80\r
+SCSI_In_DBx__SCSI_Out_DB7__PC EQU CYREG_PRT2_PC7\r
+SCSI_In_DBx__SCSI_Out_DB7__PORT EQU 2\r
+SCSI_In_DBx__SCSI_Out_DB7__SHIFT EQU 7\r
+SCSI_In_DBx__SHIFT EQU 0\r
+SCSI_In_DBx__SLW EQU CYREG_PRT2_SLW\r
+\r
+; SD_Data_Clk\r
+SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0\r
+SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1\r
+SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2\r
+SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
+SD_Data_Clk__INDEX EQU 0x00\r
+SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SD_Data_Clk__PM_ACT_MSK EQU 0x01\r
+SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SD_Data_Clk__PM_STBY_MSK EQU 0x01\r
+\r
+; SD_Init_Clk\r
+SD_Init_Clk__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0\r
+SD_Init_Clk__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1\r
+SD_Init_Clk__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2\r
+SD_Init_Clk__CFG2_SRC_SEL_MASK EQU 0x07\r
+SD_Init_Clk__INDEX EQU 0x01\r
+SD_Init_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2\r
+SD_Init_Clk__PM_ACT_MSK EQU 0x02\r
+SD_Init_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2\r
+SD_Init_Clk__PM_STBY_MSK EQU 0x02\r
+\r
+; SD_Clk_Ctl\r
+SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
+SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB05_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB05_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
+SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB05_MSK\r
+SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL\r
+\r
+; PARITY_EN\r
+PARITY_EN__0__MASK EQU 0x10\r
+PARITY_EN__0__PC EQU CYREG_PRT5_PC4\r
+PARITY_EN__0__PORT EQU 5\r
+PARITY_EN__0__SHIFT EQU 4\r
+PARITY_EN__AG EQU CYREG_PRT5_AG\r
+PARITY_EN__AMUX EQU CYREG_PRT5_AMUX\r
+PARITY_EN__BIE EQU CYREG_PRT5_BIE\r
+PARITY_EN__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+PARITY_EN__BYP EQU CYREG_PRT5_BYP\r
+PARITY_EN__CTL EQU CYREG_PRT5_CTL\r
+PARITY_EN__DM0 EQU CYREG_PRT5_DM0\r
+PARITY_EN__DM1 EQU CYREG_PRT5_DM1\r
+PARITY_EN__DM2 EQU CYREG_PRT5_DM2\r
+PARITY_EN__DR EQU CYREG_PRT5_DR\r
+PARITY_EN__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+PARITY_EN__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+PARITY_EN__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+PARITY_EN__MASK EQU 0x10\r
+PARITY_EN__PORT EQU 5\r
+PARITY_EN__PRT EQU CYREG_PRT5_PRT\r
+PARITY_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+PARITY_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+PARITY_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+PARITY_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+PARITY_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+PARITY_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+PARITY_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+PARITY_EN__PS EQU CYREG_PRT5_PS\r
+PARITY_EN__SHIFT EQU 4\r
+PARITY_EN__SLW EQU CYREG_PRT5_SLW\r
+\r
+; SCSI_Out\r
+SCSI_Out__0__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__0__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__0__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__0__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__0__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__0__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__0__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__0__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__0__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__0__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__0__MASK EQU 0x04\r
+SCSI_Out__0__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__0__PORT EQU 4\r
+SCSI_Out__0__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__0__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__0__SHIFT EQU 2\r
+SCSI_Out__0__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__1__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__1__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__1__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__1__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__1__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__1__MASK EQU 0x08\r
+SCSI_Out__1__PC EQU CYREG_PRT4_PC3\r
+SCSI_Out__1__PORT EQU 4\r
+SCSI_Out__1__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__1__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__1__SHIFT EQU 3\r
+SCSI_Out__1__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__2__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__2__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__2__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__2__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__2__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__2__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__2__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__2__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__2__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__2__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__2__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__2__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__2__MASK EQU 0x10\r
+SCSI_Out__2__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out__2__PORT EQU 4\r
+SCSI_Out__2__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__2__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__2__SHIFT EQU 4\r
+SCSI_Out__2__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__3__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__3__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__3__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__3__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__3__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__3__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__3__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__3__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__3__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__3__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__3__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__3__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__3__MASK EQU 0x20\r
+SCSI_Out__3__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out__3__PORT EQU 4\r
+SCSI_Out__3__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__3__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__3__SHIFT EQU 5\r
+SCSI_Out__3__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__4__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__4__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__4__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__4__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__4__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__4__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__4__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__4__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__4__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__4__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__4__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__4__MASK EQU 0x40\r
+SCSI_Out__4__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out__4__PORT EQU 4\r
+SCSI_Out__4__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__4__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__4__SHIFT EQU 6\r
+SCSI_Out__4__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__5__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__5__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__5__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__5__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__5__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__5__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__5__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__5__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__5__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__5__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__5__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__5__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__5__MASK EQU 0x80\r
+SCSI_Out__5__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out__5__PORT EQU 4\r
+SCSI_Out__5__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__5__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__5__SHIFT EQU 7\r
+SCSI_Out__5__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__6__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__6__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__6__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__6__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__6__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__6__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__6__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__6__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__6__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__6__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__6__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__6__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__6__MASK EQU 0x01\r
+SCSI_Out__6__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out__6__PORT EQU 6\r
+SCSI_Out__6__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__6__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__6__SHIFT EQU 0\r
+SCSI_Out__6__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__7__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__7__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__7__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__7__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__7__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__7__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__7__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__7__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__7__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__7__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__7__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__7__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__7__MASK EQU 0x02\r
+SCSI_Out__7__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out__7__PORT EQU 6\r
+SCSI_Out__7__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__7__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__7__SHIFT EQU 1\r
+SCSI_Out__7__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__8__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__8__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__8__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__8__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__8__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__8__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__8__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__8__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__8__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__8__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__8__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__8__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__8__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__8__MASK EQU 0x04\r
+SCSI_Out__8__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out__8__PORT EQU 6\r
+SCSI_Out__8__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__8__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__8__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__8__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__8__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__8__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__8__SHIFT EQU 2\r
+SCSI_Out__8__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__9__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__9__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__9__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__9__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__9__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__9__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__9__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__9__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__9__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__9__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__9__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__9__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__9__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__9__MASK EQU 0x08\r
+SCSI_Out__9__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out__9__PORT EQU 6\r
+SCSI_Out__9__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__9__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__9__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__9__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__9__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__9__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__9__SHIFT EQU 3\r
+SCSI_Out__9__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__ACK__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__ACK__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__ACK__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__ACK__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__ACK__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__ACK__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__ACK__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__ACK__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__ACK__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__ACK__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__ACK__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__ACK__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__ACK__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__ACK__MASK EQU 0x20\r
+SCSI_Out__ACK__PC EQU CYREG_PRT4_PC5\r
+SCSI_Out__ACK__PORT EQU 4\r
+SCSI_Out__ACK__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__ACK__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__ACK__SHIFT EQU 5\r
+SCSI_Out__ACK__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__ATN__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__ATN__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__ATN__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__ATN__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__ATN__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__ATN__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__ATN__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__ATN__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__ATN__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__ATN__MASK EQU 0x08\r
+SCSI_Out__ATN__PC EQU CYREG_PRT4_PC3\r
+SCSI_Out__ATN__PORT EQU 4\r
+SCSI_Out__ATN__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__ATN__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__ATN__SHIFT EQU 3\r
+SCSI_Out__ATN__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__BSY__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__BSY__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__BSY__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__BSY__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__BSY__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__BSY__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__BSY__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__BSY__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__BSY__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__BSY__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__BSY__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__BSY__MASK EQU 0x10\r
+SCSI_Out__BSY__PC EQU CYREG_PRT4_PC4\r
+SCSI_Out__BSY__PORT EQU 4\r
+SCSI_Out__BSY__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__BSY__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__BSY__SHIFT EQU 4\r
+SCSI_Out__BSY__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__CD__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__CD__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__CD__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__CD__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__CD__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__CD__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__CD__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__CD__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__CD__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__CD__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__CD__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__CD__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__CD__MASK EQU 0x02\r
+SCSI_Out__CD__PC EQU CYREG_PRT6_PC1\r
+SCSI_Out__CD__PORT EQU 6\r
+SCSI_Out__CD__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__CD__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__CD__SHIFT EQU 1\r
+SCSI_Out__CD__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__DBP__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__DBP__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__DBP__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__DBP__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__DBP__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__DBP__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__DBP__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__DBP__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__DBP__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__DBP__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__DBP__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__DBP__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__DBP__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__DBP__MASK EQU 0x04\r
+SCSI_Out__DBP__PC EQU CYREG_PRT4_PC2\r
+SCSI_Out__DBP__PORT EQU 4\r
+SCSI_Out__DBP__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__DBP__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__DBP__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__DBP__SHIFT EQU 2\r
+SCSI_Out__DBP__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__IO__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__IO__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__IO__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__IO__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__IO__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__IO__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__IO__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__IO__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__IO__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__IO__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__IO__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__IO__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__IO__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__IO__MASK EQU 0x08\r
+SCSI_Out__IO__PC EQU CYREG_PRT6_PC3\r
+SCSI_Out__IO__PORT EQU 6\r
+SCSI_Out__IO__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__IO__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__IO__SHIFT EQU 3\r
+SCSI_Out__IO__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__MSG__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__MSG__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__MSG__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__MSG__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__MSG__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__MSG__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__MSG__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__MSG__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__MSG__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__MSG__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__MSG__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__MSG__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__MSG__MASK EQU 0x80\r
+SCSI_Out__MSG__PC EQU CYREG_PRT4_PC7\r
+SCSI_Out__MSG__PORT EQU 4\r
+SCSI_Out__MSG__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__MSG__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__MSG__SHIFT EQU 7\r
+SCSI_Out__MSG__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__REQ__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__REQ__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__REQ__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__REQ__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__REQ__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__REQ__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__REQ__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__REQ__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__REQ__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__REQ__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__REQ__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__REQ__MASK EQU 0x04\r
+SCSI_Out__REQ__PC EQU CYREG_PRT6_PC2\r
+SCSI_Out__REQ__PORT EQU 6\r
+SCSI_Out__REQ__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__REQ__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__REQ__SHIFT EQU 2\r
+SCSI_Out__REQ__SLW EQU CYREG_PRT6_SLW\r
+SCSI_Out__RST__AG EQU CYREG_PRT4_AG\r
+SCSI_Out__RST__AMUX EQU CYREG_PRT4_AMUX\r
+SCSI_Out__RST__BIE EQU CYREG_PRT4_BIE\r
+SCSI_Out__RST__BIT_MASK EQU CYREG_PRT4_BIT_MASK\r
+SCSI_Out__RST__BYP EQU CYREG_PRT4_BYP\r
+SCSI_Out__RST__CTL EQU CYREG_PRT4_CTL\r
+SCSI_Out__RST__DM0 EQU CYREG_PRT4_DM0\r
+SCSI_Out__RST__DM1 EQU CYREG_PRT4_DM1\r
+SCSI_Out__RST__DM2 EQU CYREG_PRT4_DM2\r
+SCSI_Out__RST__DR EQU CYREG_PRT4_DR\r
+SCSI_Out__RST__INP_DIS EQU CYREG_PRT4_INP_DIS\r
+SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG\r
+SCSI_Out__RST__LCD_EN EQU CYREG_PRT4_LCD_EN\r
+SCSI_Out__RST__MASK EQU 0x40\r
+SCSI_Out__RST__PC EQU CYREG_PRT4_PC6\r
+SCSI_Out__RST__PORT EQU 4\r
+SCSI_Out__RST__PRT EQU CYREG_PRT4_PRT\r
+SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL\r
+SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN\r
+SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0\r
+SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1\r
+SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0\r
+SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1\r
+SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT\r
+SCSI_Out__RST__PS EQU CYREG_PRT4_PS\r
+SCSI_Out__RST__SHIFT EQU 6\r
+SCSI_Out__RST__SLW EQU CYREG_PRT4_SLW\r
+SCSI_Out__SEL__AG EQU CYREG_PRT6_AG\r
+SCSI_Out__SEL__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_Out__SEL__BIE EQU CYREG_PRT6_BIE\r
+SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_Out__SEL__BYP EQU CYREG_PRT6_BYP\r
+SCSI_Out__SEL__CTL EQU CYREG_PRT6_CTL\r
+SCSI_Out__SEL__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_Out__SEL__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_Out__SEL__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_Out__SEL__DR EQU CYREG_PRT6_DR\r
+SCSI_Out__SEL__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_Out__SEL__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_Out__SEL__MASK EQU 0x01\r
+SCSI_Out__SEL__PC EQU CYREG_PRT6_PC0\r
+SCSI_Out__SEL__PORT EQU 6\r
+SCSI_Out__SEL__PRT EQU CYREG_PRT6_PRT\r
+SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_Out__SEL__PS EQU CYREG_PRT6_PS\r
+SCSI_Out__SEL__SHIFT EQU 0\r
+SCSI_Out__SEL__SLW EQU CYREG_PRT6_SLW\r
+\r
+; SCSI_ID\r
+SCSI_ID__0__MASK EQU 0x80\r
+SCSI_ID__0__PC EQU CYREG_PRT5_PC7\r
+SCSI_ID__0__PORT EQU 5\r
+SCSI_ID__0__SHIFT EQU 7\r
+SCSI_ID__1__MASK EQU 0x40\r
+SCSI_ID__1__PC EQU CYREG_PRT5_PC6\r
+SCSI_ID__1__PORT EQU 5\r
+SCSI_ID__1__SHIFT EQU 6\r
+SCSI_ID__2__MASK EQU 0x20\r
+SCSI_ID__2__PC EQU CYREG_PRT5_PC5\r
+SCSI_ID__2__PORT EQU 5\r
+SCSI_ID__2__SHIFT EQU 5\r
+SCSI_ID__AG EQU CYREG_PRT5_AG\r
+SCSI_ID__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_ID__BIE EQU CYREG_PRT5_BIE\r
+SCSI_ID__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_ID__BYP EQU CYREG_PRT5_BYP\r
+SCSI_ID__CTL EQU CYREG_PRT5_CTL\r
+SCSI_ID__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_ID__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_ID__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_ID__DR EQU CYREG_PRT5_DR\r
+SCSI_ID__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_ID__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_ID__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_ID__PORT EQU 5\r
+SCSI_ID__PRT EQU CYREG_PRT5_PRT\r
+SCSI_ID__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_ID__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_ID__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_ID__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_ID__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_ID__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_ID__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_ID__PS EQU CYREG_PRT5_PS\r
+SCSI_ID__SLW EQU CYREG_PRT5_SLW\r
+\r
+; SCSI_In\r
+SCSI_In__0__AG EQU CYREG_PRT12_AG\r
+SCSI_In__0__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In__0__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In__0__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In__0__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In__0__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In__0__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In__0__DR EQU CYREG_PRT12_DR\r
+SCSI_In__0__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In__0__MASK EQU 0x10\r
+SCSI_In__0__PC EQU CYREG_PRT12_PC4\r
+SCSI_In__0__PORT EQU 12\r
+SCSI_In__0__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In__0__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In__0__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In__0__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In__0__PS EQU CYREG_PRT12_PS\r
+SCSI_In__0__SHIFT EQU 4\r
+SCSI_In__0__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In__0__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In__1__AG EQU CYREG_PRT12_AG\r
+SCSI_In__1__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In__1__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In__1__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In__1__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In__1__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In__1__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In__1__DR EQU CYREG_PRT12_DR\r
+SCSI_In__1__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In__1__MASK EQU 0x20\r
+SCSI_In__1__PC EQU CYREG_PRT12_PC5\r
+SCSI_In__1__PORT EQU 12\r
+SCSI_In__1__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In__1__PS EQU CYREG_PRT12_PS\r
+SCSI_In__1__SHIFT EQU 5\r
+SCSI_In__1__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In__1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In__1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In__1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In__1__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In__2__AG EQU CYREG_PRT6_AG\r
+SCSI_In__2__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__2__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__2__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__2__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__2__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__2__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__2__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__2__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__2__DR EQU CYREG_PRT6_DR\r
+SCSI_In__2__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__2__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__2__MASK EQU 0x10\r
+SCSI_In__2__PC EQU CYREG_PRT6_PC4\r
+SCSI_In__2__PORT EQU 6\r
+SCSI_In__2__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__2__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__2__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__2__PS EQU CYREG_PRT6_PS\r
+SCSI_In__2__SHIFT EQU 4\r
+SCSI_In__2__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__3__AG EQU CYREG_PRT6_AG\r
+SCSI_In__3__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__3__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__3__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__3__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__3__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__3__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__3__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__3__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__3__DR EQU CYREG_PRT6_DR\r
+SCSI_In__3__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__3__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__3__MASK EQU 0x20\r
+SCSI_In__3__PC EQU CYREG_PRT6_PC5\r
+SCSI_In__3__PORT EQU 6\r
+SCSI_In__3__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__3__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__3__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__3__PS EQU CYREG_PRT6_PS\r
+SCSI_In__3__SHIFT EQU 5\r
+SCSI_In__3__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__4__AG EQU CYREG_PRT6_AG\r
+SCSI_In__4__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__4__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__4__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__4__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__4__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__4__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__4__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__4__DR EQU CYREG_PRT6_DR\r
+SCSI_In__4__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__4__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__4__MASK EQU 0x40\r
+SCSI_In__4__PC EQU CYREG_PRT6_PC6\r
+SCSI_In__4__PORT EQU 6\r
+SCSI_In__4__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__4__PS EQU CYREG_PRT6_PS\r
+SCSI_In__4__SHIFT EQU 6\r
+SCSI_In__4__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__5__AG EQU CYREG_PRT6_AG\r
+SCSI_In__5__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__5__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__5__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__5__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__5__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__5__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__5__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__5__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__5__DR EQU CYREG_PRT6_DR\r
+SCSI_In__5__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__5__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__5__MASK EQU 0x80\r
+SCSI_In__5__PC EQU CYREG_PRT6_PC7\r
+SCSI_In__5__PORT EQU 6\r
+SCSI_In__5__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__5__PS EQU CYREG_PRT6_PS\r
+SCSI_In__5__SHIFT EQU 7\r
+SCSI_In__5__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__6__AG EQU CYREG_PRT5_AG\r
+SCSI_In__6__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__6__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__6__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__6__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__6__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__6__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__6__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__6__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__6__DR EQU CYREG_PRT5_DR\r
+SCSI_In__6__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__6__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__6__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__6__MASK EQU 0x01\r
+SCSI_In__6__PC EQU CYREG_PRT5_PC0\r
+SCSI_In__6__PORT EQU 5\r
+SCSI_In__6__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__6__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__6__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__6__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__6__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__6__PS EQU CYREG_PRT5_PS\r
+SCSI_In__6__SHIFT EQU 0\r
+SCSI_In__6__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__7__AG EQU CYREG_PRT5_AG\r
+SCSI_In__7__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__7__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__7__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__7__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__7__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__7__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__7__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__7__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__7__DR EQU CYREG_PRT5_DR\r
+SCSI_In__7__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__7__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__7__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__7__MASK EQU 0x02\r
+SCSI_In__7__PC EQU CYREG_PRT5_PC1\r
+SCSI_In__7__PORT EQU 5\r
+SCSI_In__7__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__7__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__7__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__7__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__7__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__7__PS EQU CYREG_PRT5_PS\r
+SCSI_In__7__SHIFT EQU 1\r
+SCSI_In__7__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__8__AG EQU CYREG_PRT5_AG\r
+SCSI_In__8__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__8__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__8__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__8__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__8__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__8__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__8__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__8__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__8__DR EQU CYREG_PRT5_DR\r
+SCSI_In__8__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__8__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__8__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__8__MASK EQU 0x04\r
+SCSI_In__8__PC EQU CYREG_PRT5_PC2\r
+SCSI_In__8__PORT EQU 5\r
+SCSI_In__8__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__8__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__8__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__8__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__8__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__8__PS EQU CYREG_PRT5_PS\r
+SCSI_In__8__SHIFT EQU 2\r
+SCSI_In__8__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__9__AG EQU CYREG_PRT5_AG\r
+SCSI_In__9__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__9__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__9__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__9__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__9__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__9__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__9__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__9__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__9__DR EQU CYREG_PRT5_DR\r
+SCSI_In__9__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__9__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__9__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__9__MASK EQU 0x08\r
+SCSI_In__9__PC EQU CYREG_PRT5_PC3\r
+SCSI_In__9__PORT EQU 5\r
+SCSI_In__9__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__9__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__9__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__9__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__9__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__9__PS EQU CYREG_PRT5_PS\r
+SCSI_In__9__SHIFT EQU 3\r
+SCSI_In__9__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__ACK__AG EQU CYREG_PRT6_AG\r
+SCSI_In__ACK__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__ACK__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__ACK__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__ACK__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__ACK__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__ACK__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__ACK__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__ACK__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__ACK__DR EQU CYREG_PRT6_DR\r
+SCSI_In__ACK__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__ACK__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__ACK__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__ACK__MASK EQU 0x20\r
+SCSI_In__ACK__PC EQU CYREG_PRT6_PC5\r
+SCSI_In__ACK__PORT EQU 6\r
+SCSI_In__ACK__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__ACK__PS EQU CYREG_PRT6_PS\r
+SCSI_In__ACK__SHIFT EQU 5\r
+SCSI_In__ACK__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__ATN__AG EQU CYREG_PRT12_AG\r
+SCSI_In__ATN__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In__ATN__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In__ATN__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In__ATN__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In__ATN__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In__ATN__DR EQU CYREG_PRT12_DR\r
+SCSI_In__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In__ATN__MASK EQU 0x20\r
+SCSI_In__ATN__PC EQU CYREG_PRT12_PC5\r
+SCSI_In__ATN__PORT EQU 12\r
+SCSI_In__ATN__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In__ATN__PS EQU CYREG_PRT12_PS\r
+SCSI_In__ATN__SHIFT EQU 5\r
+SCSI_In__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In__ATN__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In__BSY__AG EQU CYREG_PRT6_AG\r
+SCSI_In__BSY__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__BSY__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__BSY__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__BSY__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__BSY__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__BSY__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__BSY__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__BSY__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__BSY__DR EQU CYREG_PRT6_DR\r
+SCSI_In__BSY__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__BSY__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__BSY__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__BSY__MASK EQU 0x10\r
+SCSI_In__BSY__PC EQU CYREG_PRT6_PC4\r
+SCSI_In__BSY__PORT EQU 6\r
+SCSI_In__BSY__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__BSY__PS EQU CYREG_PRT6_PS\r
+SCSI_In__BSY__SHIFT EQU 4\r
+SCSI_In__BSY__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__CD__AG EQU CYREG_PRT5_AG\r
+SCSI_In__CD__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__CD__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__CD__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__CD__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__CD__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__CD__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__CD__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__CD__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__CD__DR EQU CYREG_PRT5_DR\r
+SCSI_In__CD__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__CD__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__CD__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__CD__MASK EQU 0x02\r
+SCSI_In__CD__PC EQU CYREG_PRT5_PC1\r
+SCSI_In__CD__PORT EQU 5\r
+SCSI_In__CD__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__CD__PS EQU CYREG_PRT5_PS\r
+SCSI_In__CD__SHIFT EQU 1\r
+SCSI_In__CD__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__DBP__AG EQU CYREG_PRT12_AG\r
+SCSI_In__DBP__BIE EQU CYREG_PRT12_BIE\r
+SCSI_In__DBP__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+SCSI_In__DBP__BYP EQU CYREG_PRT12_BYP\r
+SCSI_In__DBP__DM0 EQU CYREG_PRT12_DM0\r
+SCSI_In__DBP__DM1 EQU CYREG_PRT12_DM1\r
+SCSI_In__DBP__DM2 EQU CYREG_PRT12_DM2\r
+SCSI_In__DBP__DR EQU CYREG_PRT12_DR\r
+SCSI_In__DBP__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+SCSI_In__DBP__MASK EQU 0x10\r
+SCSI_In__DBP__PC EQU CYREG_PRT12_PC4\r
+SCSI_In__DBP__PORT EQU 12\r
+SCSI_In__DBP__PRT EQU CYREG_PRT12_PRT\r
+SCSI_In__DBP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+SCSI_In__DBP__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+SCSI_In__DBP__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+SCSI_In__DBP__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+SCSI_In__DBP__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+SCSI_In__DBP__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+SCSI_In__DBP__PS EQU CYREG_PRT12_PS\r
+SCSI_In__DBP__SHIFT EQU 4\r
+SCSI_In__DBP__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+SCSI_In__DBP__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+SCSI_In__DBP__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+SCSI_In__DBP__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+SCSI_In__DBP__SLW EQU CYREG_PRT12_SLW\r
+SCSI_In__IO__AG EQU CYREG_PRT5_AG\r
+SCSI_In__IO__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__IO__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__IO__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__IO__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__IO__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__IO__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__IO__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__IO__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__IO__DR EQU CYREG_PRT5_DR\r
+SCSI_In__IO__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__IO__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__IO__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__IO__MASK EQU 0x08\r
+SCSI_In__IO__PC EQU CYREG_PRT5_PC3\r
+SCSI_In__IO__PORT EQU 5\r
+SCSI_In__IO__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__IO__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__IO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__IO__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__IO__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__IO__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__IO__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__IO__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__IO__PS EQU CYREG_PRT5_PS\r
+SCSI_In__IO__SHIFT EQU 3\r
+SCSI_In__IO__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__MSG__AG EQU CYREG_PRT6_AG\r
+SCSI_In__MSG__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__MSG__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__MSG__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__MSG__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__MSG__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__MSG__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__MSG__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__MSG__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__MSG__DR EQU CYREG_PRT6_DR\r
+SCSI_In__MSG__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__MSG__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__MSG__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__MSG__MASK EQU 0x80\r
+SCSI_In__MSG__PC EQU CYREG_PRT6_PC7\r
+SCSI_In__MSG__PORT EQU 6\r
+SCSI_In__MSG__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__MSG__PS EQU CYREG_PRT6_PS\r
+SCSI_In__MSG__SHIFT EQU 7\r
+SCSI_In__MSG__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__REQ__AG EQU CYREG_PRT5_AG\r
+SCSI_In__REQ__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__REQ__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__REQ__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__REQ__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__REQ__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__REQ__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__REQ__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__REQ__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__REQ__DR EQU CYREG_PRT5_DR\r
+SCSI_In__REQ__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__REQ__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__REQ__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__REQ__MASK EQU 0x04\r
+SCSI_In__REQ__PC EQU CYREG_PRT5_PC2\r
+SCSI_In__REQ__PORT EQU 5\r
+SCSI_In__REQ__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__REQ__PS EQU CYREG_PRT5_PS\r
+SCSI_In__REQ__SHIFT EQU 2\r
+SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW\r
+SCSI_In__RST__AG EQU CYREG_PRT6_AG\r
+SCSI_In__RST__AMUX EQU CYREG_PRT6_AMUX\r
+SCSI_In__RST__BIE EQU CYREG_PRT6_BIE\r
+SCSI_In__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK\r
+SCSI_In__RST__BYP EQU CYREG_PRT6_BYP\r
+SCSI_In__RST__CTL EQU CYREG_PRT6_CTL\r
+SCSI_In__RST__DM0 EQU CYREG_PRT6_DM0\r
+SCSI_In__RST__DM1 EQU CYREG_PRT6_DM1\r
+SCSI_In__RST__DM2 EQU CYREG_PRT6_DM2\r
+SCSI_In__RST__DR EQU CYREG_PRT6_DR\r
+SCSI_In__RST__INP_DIS EQU CYREG_PRT6_INP_DIS\r
+SCSI_In__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG\r
+SCSI_In__RST__LCD_EN EQU CYREG_PRT6_LCD_EN\r
+SCSI_In__RST__MASK EQU 0x40\r
+SCSI_In__RST__PC EQU CYREG_PRT6_PC6\r
+SCSI_In__RST__PORT EQU 6\r
+SCSI_In__RST__PRT EQU CYREG_PRT6_PRT\r
+SCSI_In__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL\r
+SCSI_In__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN\r
+SCSI_In__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0\r
+SCSI_In__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1\r
+SCSI_In__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0\r
+SCSI_In__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1\r
+SCSI_In__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT\r
+SCSI_In__RST__PS EQU CYREG_PRT6_PS\r
+SCSI_In__RST__SHIFT EQU 6\r
+SCSI_In__RST__SLW EQU CYREG_PRT6_SLW\r
+SCSI_In__SEL__AG EQU CYREG_PRT5_AG\r
+SCSI_In__SEL__AMUX EQU CYREG_PRT5_AMUX\r
+SCSI_In__SEL__BIE EQU CYREG_PRT5_BIE\r
+SCSI_In__SEL__BIT_MASK EQU CYREG_PRT5_BIT_MASK\r
+SCSI_In__SEL__BYP EQU CYREG_PRT5_BYP\r
+SCSI_In__SEL__CTL EQU CYREG_PRT5_CTL\r
+SCSI_In__SEL__DM0 EQU CYREG_PRT5_DM0\r
+SCSI_In__SEL__DM1 EQU CYREG_PRT5_DM1\r
+SCSI_In__SEL__DM2 EQU CYREG_PRT5_DM2\r
+SCSI_In__SEL__DR EQU CYREG_PRT5_DR\r
+SCSI_In__SEL__INP_DIS EQU CYREG_PRT5_INP_DIS\r
+SCSI_In__SEL__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG\r
+SCSI_In__SEL__LCD_EN EQU CYREG_PRT5_LCD_EN\r
+SCSI_In__SEL__MASK EQU 0x01\r
+SCSI_In__SEL__PC EQU CYREG_PRT5_PC0\r
+SCSI_In__SEL__PORT EQU 5\r
+SCSI_In__SEL__PRT EQU CYREG_PRT5_PRT\r
+SCSI_In__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL\r
+SCSI_In__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN\r
+SCSI_In__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0\r
+SCSI_In__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1\r
+SCSI_In__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0\r
+SCSI_In__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1\r
+SCSI_In__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT\r
+SCSI_In__SEL__PS EQU CYREG_PRT5_PS\r
+SCSI_In__SEL__SHIFT EQU 0\r
+SCSI_In__SEL__SLW EQU CYREG_PRT5_SLW\r
+\r
+; SD_DAT1\r
+SD_DAT1__0__MASK EQU 0x20\r
+SD_DAT1__0__PC EQU CYREG_PRT3_PC5\r
+SD_DAT1__0__PORT EQU 3\r
+SD_DAT1__0__SHIFT EQU 5\r
+SD_DAT1__AG EQU CYREG_PRT3_AG\r
+SD_DAT1__AMUX EQU CYREG_PRT3_AMUX\r
+SD_DAT1__BIE EQU CYREG_PRT3_BIE\r
+SD_DAT1__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_DAT1__BYP EQU CYREG_PRT3_BYP\r
+SD_DAT1__CTL EQU CYREG_PRT3_CTL\r
+SD_DAT1__DM0 EQU CYREG_PRT3_DM0\r
+SD_DAT1__DM1 EQU CYREG_PRT3_DM1\r
+SD_DAT1__DM2 EQU CYREG_PRT3_DM2\r
+SD_DAT1__DR EQU CYREG_PRT3_DR\r
+SD_DAT1__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_DAT1__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_DAT1__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_DAT1__MASK EQU 0x20\r
+SD_DAT1__PORT EQU 3\r
+SD_DAT1__PRT EQU CYREG_PRT3_PRT\r
+SD_DAT1__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_DAT1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_DAT1__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_DAT1__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_DAT1__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_DAT1__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_DAT1__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_DAT1__PS EQU CYREG_PRT3_PS\r
+SD_DAT1__SHIFT EQU 5\r
+SD_DAT1__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_DAT2\r
+SD_DAT2__0__MASK EQU 0x01\r
+SD_DAT2__0__PC EQU CYREG_PRT3_PC0\r
+SD_DAT2__0__PORT EQU 3\r
+SD_DAT2__0__SHIFT EQU 0\r
+SD_DAT2__AG EQU CYREG_PRT3_AG\r
+SD_DAT2__AMUX EQU CYREG_PRT3_AMUX\r
+SD_DAT2__BIE EQU CYREG_PRT3_BIE\r
+SD_DAT2__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_DAT2__BYP EQU CYREG_PRT3_BYP\r
+SD_DAT2__CTL EQU CYREG_PRT3_CTL\r
+SD_DAT2__DM0 EQU CYREG_PRT3_DM0\r
+SD_DAT2__DM1 EQU CYREG_PRT3_DM1\r
+SD_DAT2__DM2 EQU CYREG_PRT3_DM2\r
+SD_DAT2__DR EQU CYREG_PRT3_DR\r
+SD_DAT2__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_DAT2__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_DAT2__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_DAT2__MASK EQU 0x01\r
+SD_DAT2__PORT EQU 3\r
+SD_DAT2__PRT EQU CYREG_PRT3_PRT\r
+SD_DAT2__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_DAT2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_DAT2__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_DAT2__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_DAT2__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_DAT2__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_DAT2__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_DAT2__PS EQU CYREG_PRT3_PS\r
+SD_DAT2__SHIFT EQU 0\r
+SD_DAT2__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_MISO\r
+SD_MISO__0__MASK EQU 0x10\r
+SD_MISO__0__PC EQU CYREG_PRT3_PC4\r
+SD_MISO__0__PORT EQU 3\r
+SD_MISO__0__SHIFT EQU 4\r
+SD_MISO__AG EQU CYREG_PRT3_AG\r
+SD_MISO__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MISO__BIE EQU CYREG_PRT3_BIE\r
+SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MISO__BYP EQU CYREG_PRT3_BYP\r
+SD_MISO__CTL EQU CYREG_PRT3_CTL\r
+SD_MISO__DM0 EQU CYREG_PRT3_DM0\r
+SD_MISO__DM1 EQU CYREG_PRT3_DM1\r
+SD_MISO__DM2 EQU CYREG_PRT3_DM2\r
+SD_MISO__DR EQU CYREG_PRT3_DR\r
+SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MISO__MASK EQU 0x10\r
+SD_MISO__PORT EQU 3\r
+SD_MISO__PRT EQU CYREG_PRT3_PRT\r
+SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MISO__PS EQU CYREG_PRT3_PS\r
+SD_MISO__SHIFT EQU 4\r
+SD_MISO__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_MOSI\r
+SD_MOSI__0__MASK EQU 0x04\r
+SD_MOSI__0__PC EQU CYREG_PRT3_PC2\r
+SD_MOSI__0__PORT EQU 3\r
+SD_MOSI__0__SHIFT EQU 2\r
+SD_MOSI__AG EQU CYREG_PRT3_AG\r
+SD_MOSI__AMUX EQU CYREG_PRT3_AMUX\r
+SD_MOSI__BIE EQU CYREG_PRT3_BIE\r
+SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_MOSI__BYP EQU CYREG_PRT3_BYP\r
+SD_MOSI__CTL EQU CYREG_PRT3_CTL\r
+SD_MOSI__DM0 EQU CYREG_PRT3_DM0\r
+SD_MOSI__DM1 EQU CYREG_PRT3_DM1\r
+SD_MOSI__DM2 EQU CYREG_PRT3_DM2\r
+SD_MOSI__DR EQU CYREG_PRT3_DR\r
+SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_MOSI__MASK EQU 0x04\r
+SD_MOSI__PORT EQU 3\r
+SD_MOSI__PRT EQU CYREG_PRT3_PRT\r
+SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_MOSI__PS EQU CYREG_PRT3_PS\r
+SD_MOSI__SHIFT EQU 2\r
+SD_MOSI__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_SCK\r
+SD_SCK__0__MASK EQU 0x08\r
+SD_SCK__0__PC EQU CYREG_PRT3_PC3\r
+SD_SCK__0__PORT EQU 3\r
+SD_SCK__0__SHIFT EQU 3\r
+SD_SCK__AG EQU CYREG_PRT3_AG\r
+SD_SCK__AMUX EQU CYREG_PRT3_AMUX\r
+SD_SCK__BIE EQU CYREG_PRT3_BIE\r
+SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_SCK__BYP EQU CYREG_PRT3_BYP\r
+SD_SCK__CTL EQU CYREG_PRT3_CTL\r
+SD_SCK__DM0 EQU CYREG_PRT3_DM0\r
+SD_SCK__DM1 EQU CYREG_PRT3_DM1\r
+SD_SCK__DM2 EQU CYREG_PRT3_DM2\r
+SD_SCK__DR EQU CYREG_PRT3_DR\r
+SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_SCK__MASK EQU 0x08\r
+SD_SCK__PORT EQU 3\r
+SD_SCK__PRT EQU CYREG_PRT3_PRT\r
+SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_SCK__PS EQU CYREG_PRT3_PS\r
+SD_SCK__SHIFT EQU 3\r
+SD_SCK__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_CD\r
+SD_CD__0__MASK EQU 0x40\r
+SD_CD__0__PC EQU CYREG_PRT3_PC6\r
+SD_CD__0__PORT EQU 3\r
+SD_CD__0__SHIFT EQU 6\r
+SD_CD__AG EQU CYREG_PRT3_AG\r
+SD_CD__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CD__BIE EQU CYREG_PRT3_BIE\r
+SD_CD__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CD__BYP EQU CYREG_PRT3_BYP\r
+SD_CD__CTL EQU CYREG_PRT3_CTL\r
+SD_CD__DM0 EQU CYREG_PRT3_DM0\r
+SD_CD__DM1 EQU CYREG_PRT3_DM1\r
+SD_CD__DM2 EQU CYREG_PRT3_DM2\r
+SD_CD__DR EQU CYREG_PRT3_DR\r
+SD_CD__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CD__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CD__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CD__MASK EQU 0x40\r
+SD_CD__PORT EQU 3\r
+SD_CD__PRT EQU CYREG_PRT3_PRT\r
+SD_CD__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CD__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CD__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CD__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CD__PS EQU CYREG_PRT3_PS\r
+SD_CD__SHIFT EQU 6\r
+SD_CD__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_CS\r
+SD_CS__0__MASK EQU 0x02\r
+SD_CS__0__PC EQU CYREG_PRT3_PC1\r
+SD_CS__0__PORT EQU 3\r
+SD_CS__0__SHIFT EQU 1\r
+SD_CS__AG EQU CYREG_PRT3_AG\r
+SD_CS__AMUX EQU CYREG_PRT3_AMUX\r
+SD_CS__BIE EQU CYREG_PRT3_BIE\r
+SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_CS__BYP EQU CYREG_PRT3_BYP\r
+SD_CS__CTL EQU CYREG_PRT3_CTL\r
+SD_CS__DM0 EQU CYREG_PRT3_DM0\r
+SD_CS__DM1 EQU CYREG_PRT3_DM1\r
+SD_CS__DM2 EQU CYREG_PRT3_DM2\r
+SD_CS__DR EQU CYREG_PRT3_DR\r
+SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_CS__MASK EQU 0x02\r
+SD_CS__PORT EQU 3\r
+SD_CS__PRT EQU CYREG_PRT3_PRT\r
+SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_CS__PS EQU CYREG_PRT3_PS\r
+SD_CS__SHIFT EQU 1\r
+SD_CS__SLW EQU CYREG_PRT3_SLW\r
+\r
+; SD_WP\r
+SD_WP__0__MASK EQU 0x80\r
+SD_WP__0__PC EQU CYREG_PRT3_PC7\r
+SD_WP__0__PORT EQU 3\r
+SD_WP__0__SHIFT EQU 7\r
+SD_WP__AG EQU CYREG_PRT3_AG\r
+SD_WP__AMUX EQU CYREG_PRT3_AMUX\r
+SD_WP__BIE EQU CYREG_PRT3_BIE\r
+SD_WP__BIT_MASK EQU CYREG_PRT3_BIT_MASK\r
+SD_WP__BYP EQU CYREG_PRT3_BYP\r
+SD_WP__CTL EQU CYREG_PRT3_CTL\r
+SD_WP__DM0 EQU CYREG_PRT3_DM0\r
+SD_WP__DM1 EQU CYREG_PRT3_DM1\r
+SD_WP__DM2 EQU CYREG_PRT3_DM2\r
+SD_WP__DR EQU CYREG_PRT3_DR\r
+SD_WP__INP_DIS EQU CYREG_PRT3_INP_DIS\r
+SD_WP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG\r
+SD_WP__LCD_EN EQU CYREG_PRT3_LCD_EN\r
+SD_WP__MASK EQU 0x80\r
+SD_WP__PORT EQU 3\r
+SD_WP__PRT EQU CYREG_PRT3_PRT\r
+SD_WP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL\r
+SD_WP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN\r
+SD_WP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0\r
+SD_WP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1\r
+SD_WP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0\r
+SD_WP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1\r
+SD_WP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT\r
+SD_WP__PS EQU CYREG_PRT3_PS\r
+SD_WP__SHIFT EQU 7\r
+SD_WP__SLW EQU CYREG_PRT3_SLW\r
+\r
+; LED1\r
+LED1__0__MASK EQU 0x08\r
+LED1__0__PC EQU CYREG_PRT12_PC3\r
+LED1__0__PORT EQU 12\r
+LED1__0__SHIFT EQU 3\r
+LED1__AG EQU CYREG_PRT12_AG\r
+LED1__BIE EQU CYREG_PRT12_BIE\r
+LED1__BIT_MASK EQU CYREG_PRT12_BIT_MASK\r
+LED1__BYP EQU CYREG_PRT12_BYP\r
+LED1__DM0 EQU CYREG_PRT12_DM0\r
+LED1__DM1 EQU CYREG_PRT12_DM1\r
+LED1__DM2 EQU CYREG_PRT12_DM2\r
+LED1__DR EQU CYREG_PRT12_DR\r
+LED1__INP_DIS EQU CYREG_PRT12_INP_DIS\r
+LED1__MASK EQU 0x08\r
+LED1__PORT EQU 12\r
+LED1__PRT EQU CYREG_PRT12_PRT\r
+LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN\r
+LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0\r
+LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1\r
+LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0\r
+LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1\r
+LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT\r
+LED1__PS EQU CYREG_PRT12_PS\r
+LED1__SHIFT EQU 3\r
+LED1__SIO_CFG EQU CYREG_PRT12_SIO_CFG\r
+LED1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF\r
+LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN\r
+LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ\r
+LED1__SLW EQU CYREG_PRT12_SLW\r
+\r
+; Miscellaneous\r
+; -- WARNING: define names containing LEOPARD or PANTHER are deprecated and will be removed in a future release\r
+CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6\r
+CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0\r
+CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0\r
+CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1\r
+CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0\r
+CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0\r
+CYDEV_CHIP_MEMBER_5B EQU 4\r
+CYDEV_CHIP_FAMILY_PSOC5 EQU 3\r
+CYDEV_CHIP_DIE_PSOC5LP EQU 4\r
+CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_DIE_PSOC5LP\r
+BCLK__BUS_CLK__HZ EQU 64000000\r
+BCLK__BUS_CLK__KHZ EQU 64000\r
+BCLK__BUS_CLK__MHZ EQU 64\r
+CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT\r
+CYDEV_CHIP_DIE_LEOPARD EQU 1\r
+CYDEV_CHIP_DIE_PANTHER EQU 3\r
+CYDEV_CHIP_DIE_PSOC4A EQU 2\r
+CYDEV_CHIP_DIE_UNKNOWN EQU 0\r
+CYDEV_CHIP_FAMILY_PSOC3 EQU 1\r
+CYDEV_CHIP_FAMILY_PSOC4 EQU 2\r
+CYDEV_CHIP_FAMILY_UNKNOWN EQU 0\r
+CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5\r
+CYDEV_CHIP_JTAG_ID EQU 0x2E12F069\r
+CYDEV_CHIP_MEMBER_3A EQU 1\r
+CYDEV_CHIP_MEMBER_4A EQU 2\r
+CYDEV_CHIP_MEMBER_5A EQU 3\r
+CYDEV_CHIP_MEMBER_UNKNOWN EQU 0\r
+CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B\r
+CYDEV_CHIP_REVISION_3A_ES1 EQU 0\r
+CYDEV_CHIP_REVISION_3A_ES2 EQU 1\r
+CYDEV_CHIP_REVISION_3A_ES3 EQU 3\r
+CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3\r
+CYDEV_CHIP_REVISION_4A_ES0 EQU 17\r
+CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17\r
+CYDEV_CHIP_REVISION_5A_ES0 EQU 0\r
+CYDEV_CHIP_REVISION_5A_ES1 EQU 1\r
+CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1\r
+CYDEV_CHIP_REVISION_5B_ES0 EQU 0\r
+CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION\r
+CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REV_PSOC5LP_PRODUCTION\r
+CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0\r
+CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1\r
+CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3\r
+CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3\r
+CYDEV_CHIP_REV_PANTHER_ES0 EQU 0\r
+CYDEV_CHIP_REV_PANTHER_ES1 EQU 1\r
+CYDEV_CHIP_REV_PANTHER_PRODUCTION EQU 1\r
+CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17\r
+CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17\r
+CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0\r
+CYDEV_CONFIGURATION_COMPRESSED EQU 1\r
+CYDEV_CONFIGURATION_DMA EQU 0\r
+CYDEV_CONFIGURATION_ECC EQU 1\r
+CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED\r
+CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED\r
+CYDEV_CONFIGURATION_MODE_DMA EQU 2\r
+CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1\r
+CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn\r
+CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1\r
+CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2\r
+CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV\r
+CYDEV_DEBUGGING_DPS_Disable EQU 3\r
+CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1\r
+CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0\r
+CYDEV_DEBUGGING_DPS_SWD EQU 2\r
+CYDEV_DEBUGGING_ENABLE EQU 1\r
+CYDEV_DEBUGGING_REQXRES EQU 1\r
+CYDEV_DEBUGGING_XRES EQU 0\r
+CYDEV_DEBUG_ENABLE_MASK EQU 0x20\r
+CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG\r
+CYDEV_DMA_CHANNELS_AVAILABLE EQU 24\r
+CYDEV_ECC_ENABLE EQU 0\r
+CYDEV_HEAP_SIZE EQU 0x1000\r
+CYDEV_INSTRUCT_CACHE_ENABLED EQU 1\r
+CYDEV_INTR_RISING EQU 0x00000003\r
+CYDEV_PROJ_TYPE EQU 0\r
+CYDEV_PROJ_TYPE_BOOTLOADER EQU 1\r
+CYDEV_PROJ_TYPE_LOADABLE EQU 2\r
+CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3\r
+CYDEV_PROJ_TYPE_STANDARD EQU 0\r
+CYDEV_PROTECTION_ENABLE EQU 0\r
+CYDEV_STACK_SIZE EQU 0x4000\r
+CYDEV_USE_BUNDLED_CMSIS EQU 1\r
+CYDEV_VARIABLE_VDDA EQU 0\r
+CYDEV_VDDA_MV EQU 5000\r
+CYDEV_VDDD_MV EQU 5000\r
+CYDEV_VDDIO0_MV EQU 5000\r
+CYDEV_VDDIO1_MV EQU 5000\r
+CYDEV_VDDIO2_MV EQU 5000\r
+CYDEV_VDDIO3_MV EQU 3300\r
+CYDEV_VIO0 EQU 5\r
+CYDEV_VIO0_MV EQU 5000\r
+CYDEV_VIO1 EQU 5\r
+CYDEV_VIO1_MV EQU 5000\r
+CYDEV_VIO2 EQU 5\r
+CYDEV_VIO2_MV EQU 5000\r
+CYDEV_VIO3_MV EQU 3300\r
+DMA_CHANNELS_USED__MASK0 EQU 0x00000000\r
+CYDEV_BOOTLOADER_ENABLE EQU 0\r
+ ENDIF\r
+ END\r
--- /dev/null
+/*******************************************************************************\r
+* File Name: cypins.h\r
+* Version 3.40\r
+*\r
+* Description:\r
+* This file contains the function prototypes and constants used for port/pin\r
+* in access and control.\r
+*\r
+* Note:\r
+* Documentation of the API's in this file is located in the\r
+* System Reference Guide provided with PSoC Creator.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_BOOT_CYPINS_H)\r
+#define CY_BOOT_CYPINS_H\r
+\r
+#include "cyfitter.h"\r
+#include "cytypes.h"\r
+\r
+\r
+/**************************************\r
+* API Parameter Constants\r
+**************************************/\r
+\r
+#define CY_PINS_PC_DRIVE_MODE_SHIFT (0x01u)\r
+#define CY_PINS_PC_DRIVE_MODE_MASK ((uint8)(0x07u << CY_PINS_PC_DRIVE_MODE_SHIFT))\r
+#define CY_PINS_PC_DRIVE_MODE_0 ((uint8)(0x00u << CY_PINS_PC_DRIVE_MODE_SHIFT))\r
+#define CY_PINS_PC_DRIVE_MODE_1 ((uint8)(0x01u << CY_PINS_PC_DRIVE_MODE_SHIFT))\r
+#define CY_PINS_PC_DRIVE_MODE_2 ((uint8)(0x02u << CY_PINS_PC_DRIVE_MODE_SHIFT))\r
+#define CY_PINS_PC_DRIVE_MODE_3 ((uint8)(0x03u << CY_PINS_PC_DRIVE_MODE_SHIFT))\r
+#define CY_PINS_PC_DRIVE_MODE_4 ((uint8)(0x04u << CY_PINS_PC_DRIVE_MODE_SHIFT))\r
+#define CY_PINS_PC_DRIVE_MODE_5 ((uint8)(0x05u << CY_PINS_PC_DRIVE_MODE_SHIFT))\r
+#define CY_PINS_PC_DRIVE_MODE_6 ((uint8)(0x06u << CY_PINS_PC_DRIVE_MODE_SHIFT))\r
+#define CY_PINS_PC_DRIVE_MODE_7 ((uint8)(0x07u << CY_PINS_PC_DRIVE_MODE_SHIFT))\r
+\r
+\r
+/* SetPinDriveMode */\r
+#define CY_PINS_DM_ALG_HIZ (CY_PINS_PC_DRIVE_MODE_0)\r
+#define CY_PINS_DM_DIG_HIZ (CY_PINS_PC_DRIVE_MODE_1)\r
+#define CY_PINS_DM_RES_UP (CY_PINS_PC_DRIVE_MODE_2)\r
+#define CY_PINS_DM_RES_DWN (CY_PINS_PC_DRIVE_MODE_3)\r
+#define CY_PINS_DM_OD_LO (CY_PINS_PC_DRIVE_MODE_4)\r
+#define CY_PINS_DM_OD_HI (CY_PINS_PC_DRIVE_MODE_5)\r
+#define CY_PINS_DM_STRONG (CY_PINS_PC_DRIVE_MODE_6)\r
+#define CY_PINS_DM_RES_UPDWN (CY_PINS_PC_DRIVE_MODE_7)\r
+\r
+\r
+/**************************************\r
+* Register Constants\r
+**************************************/\r
+\r
+/* Port Pin Configuration Register */\r
+#define CY_PINS_PC_DATAOUT (0x01u)\r
+#define CY_PINS_PC_PIN_FASTSLEW (0xBFu)\r
+#define CY_PINS_PC_PIN_SLOWSLEW (0x40u)\r
+#define CY_PINS_PC_PIN_STATE (0x10u)\r
+#define CY_PINS_PC_BIDIR_EN (0x20u)\r
+#define CY_PINS_PC_SLEW (0x40u)\r
+#define CY_PINS_PC_BYPASS (0x80u)\r
+\r
+\r
+/**************************************\r
+* Pin API Macros\r
+**************************************/\r
+\r
+/*******************************************************************************\r
+* Macro Name: CyPins_ReadPin\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Reads the current value on the pin (pin state, PS).\r
+*\r
+* Parameters:\r
+* pinPC: Port pin configuration register (uint16).\r
+* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
+* in the form:\r
+* CYREG_PRTx_PCy\r
+*\r
+* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
+*\r
+* Return:\r
+* Pin state\r
+* 0: Logic low value\r
+* Non-0: Logic high value\r
+*\r
+*******************************************************************************/\r
+#define CyPins_ReadPin(pinPC) ( *(reg8 *)(pinPC) & CY_PINS_PC_PIN_STATE )\r
+\r
+\r
+/*******************************************************************************\r
+* Macro Name: CyPins_SetPin\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Set the output value for the pin (data register, DR) to a logic high.\r
+*\r
+* Note that this only has an effect for pins configured as software pins that\r
+* are not driven by hardware.\r
+*\r
+* Parameters:\r
+* pinPC: Port pin configuration register (uint16).\r
+* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
+* in the form:\r
+* CYREG_PRTx_PCy\r
+*\r
+* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+#define CyPins_SetPin(pinPC) ( *(reg8 *)(pinPC) |= CY_PINS_PC_DATAOUT)\r
+\r
+\r
+/*******************************************************************************\r
+* Macro Name: CyPins_ClearPin\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* This macro sets the state of the specified pin to 0\r
+*\r
+* Parameters:\r
+* pinPC: address of a Pin Configuration register.\r
+* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
+* in the form:\r
+* CYREG_PRTx_PCy\r
+*\r
+* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+#define CyPins_ClearPin(pinPC) ( *(reg8 *)(pinPC) &= ((uint8)(~CY_PINS_PC_DATAOUT)))\r
+\r
+\r
+/*******************************************************************************\r
+* Macro Name: CyPins_SetPinDriveMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Sets the drive mode for the pin (DM).\r
+*\r
+* Parameters:\r
+* pinPC: Port pin configuration register (uint16)\r
+* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
+* in the form:\r
+* CYREG_PRTx_PCy\r
+*\r
+* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
+*\r
+* mode: Desired drive mode\r
+*\r
+* Define Source\r
+* PIN_DM_ALG_HIZ Analog HiZ\r
+* PIN_DM_DIG_HIZ Digital HiZ\r
+* PIN_DM_RES_UP Resistive pull up\r
+* PIN_DM_RES_DWN Resistive pull down\r
+* PIN_DM_OD_LO Open drain - drive low\r
+* PIN_DM_OD_HI Open drain - drive high\r
+* PIN_DM_STRONG Strong CMOS Output\r
+* PIN_DM_RES_UPDWN Resistive pull up/down\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+#define CyPins_SetPinDriveMode(pinPC, mode) \\r
+ ( *(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & ((uint8)(~CY_PINS_PC_DRIVE_MODE_MASK))) | \\r
+ ((mode) & CY_PINS_PC_DRIVE_MODE_MASK))\r
+\r
+\r
+/*******************************************************************************\r
+* Macro Name: CyPins_ReadPinDriveMode\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Reads the drive mode for the pin (DM).\r
+*\r
+* Parameters:\r
+* pinPC: Port pin configuration register (uint16)\r
+* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
+* in the form:\r
+* CYREG_PRTx_PCy\r
+*\r
+* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
+*\r
+*\r
+* Return:\r
+* mode: Current drive mode for the pin\r
+*\r
+* Define Source\r
+* PIN_DM_ALG_HIZ Analog HiZ\r
+* PIN_DM_DIG_HIZ Digital HiZ\r
+* PIN_DM_RES_UP Resistive pull up\r
+* PIN_DM_RES_DWN Resistive pull down\r
+* PIN_DM_OD_LO Open drain - drive low\r
+* PIN_DM_OD_HI Open drain - drive high\r
+* PIN_DM_STRONG Strong CMOS Output\r
+* PIN_DM_RES_UPDWN Resistive pull up/down\r
+*\r
+*******************************************************************************/\r
+#define CyPins_ReadPinDriveMode(pinPC) (*(reg8 *)(pinPC) & CY_PINS_PC_DRIVE_MODE_MASK)\r
+\r
+\r
+/*******************************************************************************\r
+* Macro Name: CyPins_FastSlew\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Set the slew rate for the pin to fast edge rate.\r
+* Note that this only applies for pins in strong output drive modes,\r
+* not to resistive drive modes.\r
+*\r
+* Parameters:\r
+* pinPC: address of a Pin Configuration register.\r
+* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
+* in the form:\r
+* CYREG_PRTx_PCy\r
+*\r
+* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
+*\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+#define CyPins_FastSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & CY_PINS_PC_PIN_FASTSLEW))\r
+\r
+\r
+/*******************************************************************************\r
+* Macro Name: CyPins_SlowSlew\r
+********************************************************************************\r
+*\r
+* Summary:\r
+* Set the slew rate for the pin to slow edge rate.\r
+* Note that this only applies for pins in strong output drive modes,\r
+* not to resistive drive modes.\r
+*\r
+* Parameters:\r
+* pinPC: address of a Pin Configuration register.\r
+* #defines for each pin on a chip are provided in the cydevice_trm.h file\r
+* in the form:\r
+* CYREG_PRTx_PCy\r
+*\r
+* where x is a port number 0 - 15 and y is a pin number 0 - 7\r
+*\r
+* Return:\r
+* None\r
+*\r
+*******************************************************************************/\r
+#define CyPins_SlowSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) | CY_PINS_PC_PIN_SLOWSLEW))\r
+\r
+\r
+/*******************************************************************************\r
+* Following code are OBSOLETE and must not be used starting from cy_boot 3.30\r
+*******************************************************************************/\r
+#define PC_DRIVE_MODE_SHIFT (CY_PINS_PC_DRIVE_MODE_SHIFT)\r
+#define PC_DRIVE_MODE_MASK (CY_PINS_PC_DRIVE_MODE_MASK)\r
+#define PC_DRIVE_MODE_0 (CY_PINS_PC_DRIVE_MODE_0)\r
+#define PC_DRIVE_MODE_1 (CY_PINS_PC_DRIVE_MODE_1)\r
+#define PC_DRIVE_MODE_2 (CY_PINS_PC_DRIVE_MODE_2)\r
+#define PC_DRIVE_MODE_3 (CY_PINS_PC_DRIVE_MODE_3)\r
+#define PC_DRIVE_MODE_4 (CY_PINS_PC_DRIVE_MODE_4)\r
+#define PC_DRIVE_MODE_5 (CY_PINS_PC_DRIVE_MODE_5)\r
+#define PC_DRIVE_MODE_6 (CY_PINS_PC_DRIVE_MODE_6)\r
+#define PC_DRIVE_MODE_7 (CY_PINS_PC_DRIVE_MODE_7)\r
+\r
+#define PIN_DM_ALG_HIZ (CY_PINS_DM_ALG_HIZ)\r
+#define PIN_DM_DIG_HIZ (CY_PINS_DM_DIG_HIZ)\r
+#define PIN_DM_RES_UP (CY_PINS_DM_RES_UP)\r
+#define PIN_DM_RES_DWN (CY_PINS_DM_RES_DWN)\r
+#define PIN_DM_OD_LO (CY_PINS_DM_OD_LO)\r
+#define PIN_DM_OD_HI (CY_PINS_DM_OD_HI)\r
+#define PIN_DM_STRONG (CY_PINS_DM_STRONG)\r
+#define PIN_DM_RES_UPDWN (CY_PINS_DM_RES_UPDWN)\r
+\r
+#define PC_DATAOUT (CY_PINS_PC_DATAOUT)\r
+#define PC_PIN_FASTSLEW (CY_PINS_PC_PIN_FASTSLEW)\r
+#define PC_PIN_SLOWSLEW (CY_PINS_PC_PIN_SLOWSLEW)\r
+#define PC_PIN_STATE (CY_PINS_PC_PIN_STATE)\r
+#define PC_BIDIR_EN (CY_PINS_PC_BIDIR_EN)\r
+#define PC_SLEW (CY_PINS_PC_SLEW)\r
+#define PC_BYPASS (CY_PINS_PC_BYPASS)\r
+\r
+#endif /* (CY_BOOT_CYPINS_H) */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* FILENAME: cytypes.h\r
+* Version 3.40\r
+*\r
+* Description:\r
+* CyTypes provides register access macros and approved types for use in\r
+* firmware.\r
+*\r
+* Note:\r
+* Due to endiannesses of the hardware and some compilers, the register\r
+* access macros for big endian compilers use some library calls to arrange\r
+* data the correct way.\r
+*\r
+* Register Access macros and functions perform their operations on an\r
+* input of type pointer to void. The arguments passed to it should be\r
+* pointers to the type associated with the register size.\r
+* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value)\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#if !defined(CY_BOOT_CYTYPES_H)\r
+#define CY_BOOT_CYTYPES_H\r
+\r
+#if defined(__C51__)\r
+ #include <intrins.h>\r
+#endif /* (__C51__) */\r
+\r
+/* ARM and C99 or later */\r
+#if defined(__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L)\r
+ #include <stdint.h>\r
+#endif /* (__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) */\r
+\r
+#include "cyfitter.h"\r
+\r
+\r
+\r
+/***************************************\r
+* Conditional Compilation Parameters\r
+***************************************/\r
+\r
+\r
+/*******************************************************************************\r
+* FAMILY encodes the overall architectural family\r
+*******************************************************************************/\r
+#define CY_PSOC3 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3)\r
+#define CY_PSOC4 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4)\r
+#define CY_PSOC5 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)\r
+\r
+\r
+/*******************************************************************************\r
+* MEMBER encodes both the family and the detailed architecture\r
+*******************************************************************************/\r
+#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)\r
+#ifdef CYDEV_CHIP_MEMBER_5B\r
+ #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)\r
+#else\r
+ #define CY_PSOC5LP 0\r
+#endif\r
+\r
+\r
+/*******************************************************************************\r
+* UDB revisions\r
+*******************************************************************************/\r
+#define CY_UDB_V0 (CY_PSOC5A)\r
+#define CY_UDB_V1 (!CY_UDB_V0)\r
+\r
+\r
+/*******************************************************************************\r
+* Base Types. Acceptable types from MISRA-C specifying signedness and size.\r
+*******************************************************************************/\r
+typedef unsigned char uint8;\r
+typedef unsigned short uint16;\r
+typedef unsigned long uint32;\r
+typedef signed char int8;\r
+typedef signed short int16;\r
+typedef signed long int32;\r
+typedef float float32;\r
+\r
+#if(!CY_PSOC3)\r
+\r
+ typedef double float64;\r
+ typedef long long int64;\r
+ typedef unsigned long long uint64;\r
+\r
+#endif /* (!CY_PSOC3) */\r
+\r
+/* Signed or unsigned depending on the compiler selection */\r
+typedef char char8;\r
+\r
+\r
+/*******************************************************************************\r
+* Memory address functions prototypes\r
+*******************************************************************************/\r
+#if(CY_PSOC3)\r
+\r
+ /***************************************************************************\r
+ * Prototypes for absolute memory address functions (cymem.a51) with built-in\r
+ * endian conversion. These functions should be called through the\r
+ * CY_GET_XTND_REGxx and CY_SET_XTND_REGxx macros.\r
+ ***************************************************************************/\r
+ extern uint8 cyread8 (volatile void far *addr);\r
+ extern void cywrite8 (volatile void far *addr, uint8 value);\r
+\r
+ extern uint16 cyread16 (volatile void far *addr);\r
+ extern uint16 cyread16_nodpx(volatile void far *addr);\r
+\r
+ extern void cywrite16 (volatile void far *addr, uint16 value);\r
+ extern void cywrite16_nodpx(volatile void far *addr, uint16 value);\r
+\r
+ extern uint32 cyread24 (volatile void far *addr);\r
+ extern uint32 cyread24_nodpx(volatile void far *addr);\r
+\r
+ extern void cywrite24 (volatile void far *addr, uint32 value);\r
+ extern void cywrite24_nodpx(volatile void far *addr, uint32 value);\r
+\r
+ extern uint32 cyread32 (volatile void far *addr);\r
+ extern uint32 cyread32_nodpx(volatile void far *addr);\r
+\r
+ extern void cywrite32 (volatile void far *addr, uint32 value);\r
+ extern void cywrite32_nodpx(volatile void far *addr, uint32 value);\r
+\r
+\r
+ /***************************************************************************\r
+ * Memory access routines from cymem.a51 for the generated device\r
+ * configuration code. These functions may be subject to change in future\r
+ * revisions of the cy_boot component and they are not available for all\r
+ * devices. Most code should use memset or memcpy instead.\r
+ ***************************************************************************/\r
+ void cymemzero(void far *addr, uint16 size);\r
+ void cyconfigcpy(uint16 size, const void far *src, void far *dest) large;\r
+ void cyconfigcpycode(uint16 size, const void code *src, void far *dest);\r
+\r
+ #define CYCONFIGCPY_DECLARED (1)\r
+\r
+#else\r
+\r
+ /* Prototype for function to set a 24-bit register. Located at cyutils.c */\r
+ extern void CySetReg24(uint32 volatile * addr, uint32 value);\r
+\r
+ #if(CY_PSOC4)\r
+\r
+ extern uint32 CyGetReg24(uint32 volatile * addr);\r
+\r
+ #endif /*(CY_PSOC4)*/\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
+/*******************************************************************************\r
+* Memory model definitions. To allow code to be 8051-ARM agnostic.\r
+*******************************************************************************/\r
+#if(CY_PSOC3)\r
+\r
+ #define CYBDATA bdata\r
+ #define CYBIT bit\r
+ #define CYCODE code\r
+ #define CYCOMPACT compact\r
+ #define CYDATA data\r
+ #define CYFAR far\r
+ #define CYIDATA idata\r
+ #define CYLARGE large\r
+ #define CYPDATA pdata\r
+ #define CYREENTRANT reentrant\r
+ #define CYSMALL small\r
+ #define CYXDATA xdata\r
+ #define XDATA xdata\r
+ \r
+ #define CY_NOINIT\r
+\r
+#else\r
+\r
+ #define CYBDATA\r
+ #define CYBIT uint8\r
+ #define CYCODE\r
+ #define CYCOMPACT\r
+ #define CYDATA\r
+ #define CYFAR\r
+ #define CYIDATA\r
+ #define CYLARGE\r
+ #define CYPDATA\r
+ #define CYREENTRANT\r
+ #define CYSMALL\r
+ #define CYXDATA\r
+ #define XDATA\r
+ \r
+ #if defined(__ARMCC_VERSION)\r
+ #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init))\r
+ #elif defined (__GNUC__)\r
+ #define CY_NOINIT __attribute__ ((section(".noinit")))\r
+ #endif /* (__ARMCC_VERSION) */\r
+\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
+#if(CY_PSOC3)\r
+\r
+ /* 8051 naturally returns an 8 bit value. */\r
+ typedef unsigned char cystatus;\r
+\r
+#else\r
+\r
+ /* ARM naturally returns a 32 bit value. */\r
+ typedef unsigned long cystatus;\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
+/*******************************************************************************\r
+* Hardware Register Types.\r
+*******************************************************************************/\r
+typedef volatile uint8 CYXDATA reg8;\r
+typedef volatile uint16 CYXDATA reg16;\r
+typedef volatile uint32 CYXDATA reg32;\r
+\r
+\r
+/*******************************************************************************\r
+* Interrupt Types and Macros\r
+*******************************************************************************/\r
+#if(CY_PSOC3)\r
+\r
+ #define CY_ISR(FuncName) void FuncName (void) interrupt 0\r
+ #define CY_ISR_PROTO(FuncName) void FuncName (void)\r
+ typedef void (CYCODE * cyisraddress)(void);\r
+\r
+#else\r
+\r
+ #define CY_ISR(FuncName) void FuncName (void)\r
+ #define CY_ISR_PROTO(FuncName) void FuncName (void)\r
+ typedef void (* cyisraddress)(void);\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
+/*******************************************************************************\r
+* Register Access\r
+*******************************************************************************/\r
+#if(CY_PSOC3)\r
+\r
+\r
+ /*******************************************************************************\r
+ * KEIL for the 8051 is a big endian compiler This causes problems as the on chip\r
+ * registers are little endian. Byte swapping for two and four byte registers is\r
+ * implemented in the functions below. This will require conditional compilation\r
+ * of function prototypes in code.\r
+ *******************************************************************************/\r
+\r
+ /* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */\r
+\r
+ #define CY_GET_REG8(addr) (*((reg8 *)(addr)))\r
+ #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value))\r
+\r
+ #define CY_GET_REG16(addr) cyread16_nodpx ((volatile void far *)(reg16 *)(addr))\r
+ #define CY_SET_REG16(addr, value) cywrite16_nodpx((volatile void far *)(reg16 *)(addr), value)\r
+\r
+ #define CY_GET_REG24(addr) cyread24_nodpx ((volatile void far *)(reg32 *)(addr))\r
+ #define CY_SET_REG24(addr, value) cywrite24_nodpx((volatile void far *)(reg32 *)(addr),value)\r
+\r
+ #define CY_GET_REG32(addr) cyread32_nodpx ((volatile void far *)(reg32 *)(addr))\r
+ #define CY_SET_REG32(addr, value) cywrite32_nodpx((volatile void far *)(reg32 *)(addr), value)\r
+\r
+ /* Access 8, 16, 24 and 32-bit registers, ABOVE THE FIRST 64K OF XDATA */\r
+ #define CY_GET_XTND_REG8(addr) cyread8((volatile void far *)(addr))\r
+ #define CY_SET_XTND_REG8(addr, value) cywrite8((volatile void far *)(addr), value)\r
+\r
+ #define CY_GET_XTND_REG16(addr) cyread16((volatile void far *)(addr))\r
+ #define CY_SET_XTND_REG16(addr, value) cywrite16((volatile void far *)(addr), value)\r
+\r
+ #define CY_GET_XTND_REG24(addr) cyread24((volatile void far *)(addr))\r
+ #define CY_SET_XTND_REG24(addr, value) cywrite24((volatile void far *)(addr), value)\r
+\r
+ #define CY_GET_XTND_REG32(addr) cyread32((volatile void far *)(addr))\r
+ #define CY_SET_XTND_REG32(addr, value) cywrite32((volatile void far *)(addr), value)\r
+\r
+#else\r
+\r
+ /* 8, 16, 24 and 32-bit register access macros */\r
+ #define CY_GET_REG8(addr) (*((reg8 *)(addr)))\r
+ #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value))\r
+\r
+ #define CY_GET_REG16(addr) (*((reg16 *)(addr)))\r
+ #define CY_SET_REG16(addr, value) (*((reg16 *)(addr)) = (uint16)(value))\r
+\r
+\r
+ #define CY_SET_REG24(addr, value) CySetReg24((reg32 *) (addr), (value))\r
+ #if(CY_PSOC4)\r
+ #define CY_GET_REG24(addr) CyGetReg24((reg32 *) (addr))\r
+ #else\r
+ #define CY_GET_REG24(addr) (*((reg32 *)(addr)) & 0x00FFFFFFu)\r
+ #endif /* (CY_PSOC4) */\r
+\r
+\r
+ #define CY_GET_REG32(addr) (*((reg32 *)(addr)))\r
+ #define CY_SET_REG32(addr, value) (*((reg32 *)(addr)) = (uint32)(value))\r
+\r
+\r
+ /* To allow code to be 8051-ARM agnostic. */\r
+ #define CY_GET_XTND_REG8(addr) CY_GET_REG8(addr)\r
+ #define CY_SET_XTND_REG8(addr, value) CY_SET_REG8(addr, value)\r
+\r
+ #define CY_GET_XTND_REG16(addr) CY_GET_REG16(addr)\r
+ #define CY_SET_XTND_REG16(addr, value) CY_SET_REG16(addr, value)\r
+\r
+ #define CY_GET_XTND_REG24(addr) CY_GET_REG24(addr)\r
+ #define CY_SET_XTND_REG24(addr, value) CY_SET_REG24(addr, value)\r
+\r
+ #define CY_GET_XTND_REG32(addr) CY_GET_REG32(addr)\r
+ #define CY_SET_XTND_REG32(addr, value) CY_SET_REG32(addr, value)\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+* Data manipulation defines\r
+*******************************************************************************/\r
+\r
+/* Get 8 bits of a 16 bit value. */\r
+#define LO8(x) ((uint8) (x))\r
+#define HI8(x) ((uint8) ((x) >> 8))\r
+\r
+/* Get 16 bits of a 32 bit value. */\r
+#define LO16(x) ((uint16) (x))\r
+#define HI16(x) ((uint16) ((uint32)(x) >> 16))\r
+\r
+/* Swap the byte ordering of a 32 bit value */\r
+#define CYSWAP_ENDIAN32(x) \\r
+ ((uint32)(((x) >> 24) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24)))\r
+\r
+/* Swap the byte ordering of a 16 bit value */\r
+#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | ((x) >> 8)))\r
+\r
+\r
+/*******************************************************************************\r
+* Defines the standard return values used PSoC content. A function is\r
+* not limited to these return values but can use them when returning standard\r
+* error values. Return values can be overloaded if documented in the function\r
+* header. On the 8051 a function can use a larger return type but still use the\r
+* defined return codes.\r
+*\r
+* Zero is successful, all other values indicate some form of failure. 1 - 0x7F -\r
+* standard defined values; 0x80 - ... - user or content defined values.\r
+*******************************************************************************/\r
+#define CYRET_SUCCESS (0x00u) /* Successful */\r
+#define CYRET_BAD_PARAM (0x01u) /* One or more invalid parameters */\r
+#define CYRET_INVALID_OBJECT (0x02u) /* Invalid object specified */\r
+#define CYRET_MEMORY (0x03u) /* Memory related failure */\r
+#define CYRET_LOCKED (0x04u) /* Resource lock failure */\r
+#define CYRET_EMPTY (0x05u) /* No more objects available */\r
+#define CYRET_BAD_DATA (0x06u) /* Bad data received (CRC or other error check) */\r
+#define CYRET_STARTED (0x07u) /* Operation started, but not necessarily completed yet */\r
+#define CYRET_FINISHED (0x08u) /* Operation completed */\r
+#define CYRET_CANCELED (0x09u) /* Operation canceled */\r
+#define CYRET_TIMEOUT (0x10u) /* Operation timed out */\r
+#define CYRET_INVALID_STATE (0x11u) /* Operation not setup or is in an improper state */\r
+#define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFu) /* Unknown failure */\r
+\r
+\r
+/*******************************************************************************\r
+* Intrinsic Defines: Processor NOP instruction\r
+*******************************************************************************/\r
+#if(CY_PSOC3)\r
+\r
+ #define CY_NOP _nop_()\r
+\r
+#else\r
+\r
+ #if defined(__ARMCC_VERSION)\r
+\r
+ /* RealView */\r
+ #define CY_NOP __nop()\r
+\r
+ #else\r
+\r
+ /* GCC */\r
+ #define CY_NOP __asm("NOP\n")\r
+\r
+ #endif /* defined(__ARMCC_VERSION) */\r
+\r
+#endif /* (CY_PSOC3) */\r
+\r
+\r
+/*******************************************************************************\r
+* Following code are OBSOLETE and must not be used starting from cy_boot 3.10\r
+*******************************************************************************/\r
+\r
+/* Device is PSoC 3 and the revision is ES2 or earlier */\r
+#define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \\r
+ (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2))\r
+\r
+/* Device is PSoC 3 and the revision is ES3 or later */\r
+#define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \\r
+ (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3))\r
+\r
+/* Device is PSoC 5 and the revision is ES1 or earlier */\r
+#define CY_PSOC5_ES1 (CY_PSOC5A && \\r
+ (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1))\r
+\r
+/* Device is PSoC 5 and the revision is ES2 or later */\r
+#define CY_PSOC5_ES2 (CY_PSOC5A && \\r
+ (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1))\r
+\r
+#endif /* CY_BOOT_CYTYPES_H */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+/*******************************************************************************\r
+* FILENAME: cyutils.c\r
+* Version 3.40\r
+*\r
+* Description:\r
+* CyUtils provides function to handle 24-bit value writes.\r
+*\r
+********************************************************************************\r
+* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+\r
+#include "cytypes.h"\r
+\r
+#if (!CY_PSOC3)\r
+\r
+ /***************************************************************************\r
+ * Function Name: CySetReg24\r
+ ****************************************************************************\r
+ *\r
+ * Summary:\r
+ * Writes the 24-bit value to the specified register.\r
+ *\r
+ * Parameters:\r
+ * addr : adress where data must be written\r
+ * value: data that must be written\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Reentrant:\r
+ * No\r
+ *\r
+ ***************************************************************************/\r
+ void CySetReg24(uint32 volatile * addr, uint32 value)\r
+ {\r
+ uint8 volatile *tmpAddr;\r
+\r
+ tmpAddr = (uint8 volatile *) addr;\r
+\r
+ tmpAddr[0u] = (uint8) value;\r
+ tmpAddr[1u] = (uint8) (value >> 8u);\r
+ tmpAddr[2u] = (uint8) (value >> 16u);\r
+ }\r
+\r
+\r
+ #if(CY_PSOC4)\r
+\r
+ /***************************************************************************\r
+ * Function Name: CyGetReg24\r
+ ****************************************************************************\r
+ *\r
+ * Summary:\r
+ * Reads the 24-bit value from the specified register.\r
+ *\r
+ * Parameters:\r
+ * addr : adress where data must be read\r
+ *\r
+ * Return:\r
+ * None\r
+ *\r
+ * Reentrant:\r
+ * No\r
+ *\r
+ ***************************************************************************/\r
+ uint32 CyGetReg24(uint32 volatile * addr)\r
+ {\r
+ uint8 volatile *tmpAddr;\r
+ uint32 value;\r
+\r
+ tmpAddr = (uint8 volatile *) addr;\r
+\r
+ value = (uint32) tmpAddr[0u];\r
+ value |= ((uint32) tmpAddr[1u] << 8u );\r
+ value |= ((uint32) tmpAddr[2u] << 16u);\r
+\r
+ return(value);\r
+ }\r
+\r
+ #endif /*(CY_PSOC4)*/\r
+\r
+#endif /* (!CY_PSOC3) */\r
+\r
+\r
+/* [] END OF FILE */\r
--- /dev/null
+@REM This script allows a 3rd party IDE to use CyHexTool to perform\r
+@REM any post processing that is necessary to convert the raw flash\r
+@REM image into a complete hex file to use in programming the PSoC.\r
+@REM USAGE: post_link.bat\r
+@REM arg1: Persistant path back to the directory containing the app project.\r
+@REM arg2: Path (relative to arg1) of the directory where the hex files go.\r
+@REM arg3: Name of the project.\r
+@REM NOTE: This script is auto generated. Do not modify.\r
+\r
+"C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\bin\cyvalidateide.exe" -dev CY8C5268AXI-LP047 -ide "%~1\%~3" -flsAddr 0x0 -flsSize 0x40000 -sramAddr 0x1FFF8000 -sramSize 0x10000\r
+@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% \r
+move "%~1\%~2\%~n3.hex" "%~1\%~2\%~n3.ihx"\r
+@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% \r
+"C:\Program Files (x86)\Cypress\PSoC Creator\2.2\PSoC Creator\bin\cyhextool" -o "%~1\%~2\%~n3.hex" -f "%~1\%~2\%~n3.ihx" -prot "%~dp0protect.hex" -id 2E12F069 -a EEPROM=90200000:800,PROGRAM=00000000:40000,CONFIG=80000000:8000,PROTECT=90400000:100 -meta 0001 -cunv 00004005 -wonv BC90ACAF -ecc "%~dp0config.hex" \r
+@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% \r
+CD /D "C:\Keil\UV4"\r
+@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% \r
+IF NOT EXIST "Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\SCSI2SD.svd" rem "Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\SCSI2SD.sfr"\r
+@IF %errorlevel% NEQ 0 EXIT /b %errorlevel% \r
--- /dev/null
+/*******************************************************************************\r
+ * File Name: project.h \r
+ * PSoC Creator 2.2 Component Pack 6\r
+ *\r
+ * Description:\r
+ * This file is automatically generated by PSoC Creator and should not \r
+ * be edited by hand.\r
+ *\r
+ *\r
+ ********************************************************************************\r
+ * Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.\r
+ * You may use this file only in accordance with the license, terms, conditions, \r
+ * disclaimers, and limitations in the end user license agreement accompanying \r
+ * the software package with which this file was provided.\r
+ ********************************************************************************/\r
+\r
+#include <cyfitter_cfg.h>\r
+#include <cydevice.h>\r
+#include <cydevice_trm.h>\r
+#include <cyfitter.h>\r
+#include <SCSI_In_DBx_aliases.h>\r
+#include <SCSI_In_DBx.h>\r
+#include <SCSI_Out_DBx_aliases.h>\r
+#include <SCSI_Out_DBx.h>\r
+#include <SDCard.h>\r
+#include <SDCard_PVT.h>\r
+#include <SD_MISO_aliases.h>\r
+#include <SD_MISO.h>\r
+#include <SD_MOSI_aliases.h>\r
+#include <SD_MOSI.h>\r
+#include <SD_SCK_aliases.h>\r
+#include <SD_SCK.h>\r
+#include <SD_CS_aliases.h>\r
+#include <SD_CS.h>\r
+#include <SD_DAT1_aliases.h>\r
+#include <SD_DAT1.h>\r
+#include <SD_DAT2_aliases.h>\r
+#include <SD_DAT2.h>\r
+#include <SD_WP_aliases.h>\r
+#include <SD_WP.h>\r
+#include <SD_CD_aliases.h>\r
+#include <SD_CD.h>\r
+#include <SCSI_ID_aliases.h>\r
+#include <PARITY_EN_aliases.h>\r
+#include <PARITY_EN.h>\r
+#include <SCSI_In_aliases.h>\r
+#include <SCSI_Out_aliases.h>\r
+#include <LED1_aliases.h>\r
+#include <LED1.h>\r
+#include <SD_Init_Clk.h>\r
+#include <SD_Data_Clk.h>\r
+#include <SD_Clk_Ctl.h>\r
+#include <core_cm3_psoc5.h>\r
+#include <core_cm3.h>\r
+#include <CyDmac.h>\r
+#include <CyFlash.h>\r
+#include <CyLib.h>\r
+#include <cypins.h>\r
+#include <cyPm.h>\r
+#include <CySpc.h>\r
+#include <cytypes.h>\r
+\r
+/*[]*/\r
+\r
--- /dev/null
+:4000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C0\r
+:400040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080\r
+:400080000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040\r
+:4000C0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000\r
+:00000001FF\r
--- /dev/null
+<?xml version="1.0" encoding="utf-8"?>\r
+<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
+ <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="PARITY_EN" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_ID" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_Clk_mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_Clk_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SD_Clk_Ctl_CONTROL_REG" address="0x40006575" bitWidth="8" desc="" />\r
+ </block>\r
+ <block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_Init_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <block name="TxInternalInterrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="RxInternalInterrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ </block>\r
+ <block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_WP" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+</blockRegMap>
\ No newline at end of file
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--- /dev/null
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+ <IncludeLibraryModules></IncludeLibraryModules>
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+ <SimDlgDll>DLM.DLL</SimDlgDll>
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+ <TargetDllName>SARMCM3.DLL</TargetDllName>
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+ <TargetDlgDll>TLM.DLL</TargetDlgDll>
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+ <FileName>SD_WP.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SD_WP.h</FilePath>
+ </File>
+ <File>
+ <FileName>SD_CD_aliases.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SD_CD_aliases.h</FilePath>
+ </File>
+ <File>
+ <FileName>SD_CD.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SD_CD.c</FilePath>
+ </File>
+ <File>
+ <FileName>SD_CD.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SD_CD.h</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_ID_aliases.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_ID_aliases.h</FilePath>
+ </File>
+ <File>
+ <FileName>PARITY_EN_aliases.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\PARITY_EN_aliases.h</FilePath>
+ </File>
+ <File>
+ <FileName>PARITY_EN.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\PARITY_EN.c</FilePath>
+ </File>
+ <File>
+ <FileName>PARITY_EN.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\PARITY_EN.h</FilePath>
+ </File>
+ <File>
+ <FileName>LED1_aliases.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\LED1_aliases.h</FilePath>
+ </File>
+ <File>
+ <FileName>LED1.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\LED1.c</FilePath>
+ </File>
+ <File>
+ <FileName>LED1.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\LED1.h</FilePath>
+ </File>
+ <File>
+ <FileName>cm3gcc.ld</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\cm3gcc.ld</FilePath>
+ </File>
+ <File>
+ <FileName>Cm3RealView.scat</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\Cm3RealView.scat</FilePath>
+ </File>
+ <File>
+ <FileName>core_cm3_psoc5.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\core_cm3_psoc5.h</FilePath>
+ </File>
+ <File>
+ <FileName>core_cm3.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\core_cm3.c</FilePath>
+ </File>
+ <File>
+ <FileName>core_cm3.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\core_cm3.h</FilePath>
+ </File>
+ <File>
+ <FileName>CyBootAsmGnu.s</FileName>
+ <FileType>2</FileType>
+ <FilePath>.\Generated_Source\PSoC5\CyBootAsmGnu.s</FilePath>
+ </File>
+ <File>
+ <FileName>CyDmac.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\CyDmac.c</FilePath>
+ </File>
+ <File>
+ <FileName>CyDmac.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\CyDmac.h</FilePath>
+ </File>
+ <File>
+ <FileName>CyFlash.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\CyFlash.c</FilePath>
+ </File>
+ <File>
+ <FileName>CyFlash.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\CyFlash.h</FilePath>
+ </File>
+ <File>
+ <FileName>CyLib.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\CyLib.c</FilePath>
+ </File>
+ <File>
+ <FileName>CyLib.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\CyLib.h</FilePath>
+ </File>
+ <File>
+ <FileName>cypins.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\cypins.h</FilePath>
+ </File>
+ <File>
+ <FileName>cyPm.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\cyPm.c</FilePath>
+ </File>
+ <File>
+ <FileName>cyPm.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\cyPm.h</FilePath>
+ </File>
+ <File>
+ <FileName>CySpc.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\CySpc.c</FilePath>
+ </File>
+ <File>
+ <FileName>CySpc.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\CySpc.h</FilePath>
+ </File>
+ <File>
+ <FileName>cytypes.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\cytypes.h</FilePath>
+ </File>
+ <File>
+ <FileName>cyutils.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\cyutils.c</FilePath>
+ </File>
+ <File>
+ <FileName>project.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\project.h</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_In_aliases.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_In_aliases.h</FilePath>
+ </File>
+ <File>
+ <FileName>SCSI_Out_aliases.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SCSI_Out_aliases.h</FilePath>
+ </File>
+ <File>
+ <FileName>SD_Init_Clk.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SD_Init_Clk.c</FilePath>
+ </File>
+ <File>
+ <FileName>SD_Init_Clk.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SD_Init_Clk.h</FilePath>
+ </File>
+ <File>
+ <FileName>SD_Data_Clk.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SD_Data_Clk.c</FilePath>
+ </File>
+ <File>
+ <FileName>SD_Data_Clk.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SD_Data_Clk.h</FilePath>
+ </File>
+ <File>
+ <FileName>SD_Clk_Ctl.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SD_Clk_Ctl.c</FilePath>
+ </File>
+ <File>
+ <FileName>SD_Clk_Ctl.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SD_Clk_Ctl.h</FilePath>
+ </File>
+ <File>
+ <FileName>SDCard.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SDCard.c</FilePath>
+ </File>
+ <File>
+ <FileName>SDCard.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SDCard.h</FilePath>
+ </File>
+ <File>
+ <FileName>SDCard_PM.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SDCard_PM.c</FilePath>
+ </File>
+ <File>
+ <FileName>SDCard_INT.c</FileName>
+ <FileType>1</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SDCard_INT.c</FilePath>
+ </File>
+ <File>
+ <FileName>SDCard_PVT.h</FileName>
+ <FileType>5</FileType>
+ <FilePath>.\Generated_Source\PSoC5\SDCard_PVT.h</FilePath>
+ </File>
+ </Files>
+ </Group>
+ </Groups>
+ </Target>
+ </Targets>
+</Project>
\ No newline at end of file
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//\r
+// This file is part of SCSI2SD.\r
+//\r
+// SCSI2SD is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License, or\r
+// (at your option) any later version.\r
+//\r
+// SCSI2SD is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
+#include "bits.h"\r
+\r
+const uint8 Lookup_OddParity[] =\r
+{\r
+1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,\r
+0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,\r
+0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,\r
+1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,\r
+0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,\r
+1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,\r
+1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,\r
+0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,\r
+0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,\r
+1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,\r
+1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,\r
+0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,\r
+1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1,\r
+0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,\r
+0,1,1,0,1,0,0,1,1,0,0,1,0,1,1,0,\r
+1,0,0,1,0,1,1,0,0,1,1,0,1,0,0,1\r
+};\r
+\r
+uint8 countBits(uint8 value)\r
+{\r
+ int i;\r
+ for (i = 0; value; value >>= 1)\r
+ {\r
+ i += value & 1;\r
+ }\r
+ return i;\r
+}\r
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//\r
+// This file is part of SCSI2SD.\r
+//\r
+// SCSI2SD is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License, or\r
+// (at your option) any later version.\r
+//\r
+// SCSI2SD is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
+#ifndef BITS_H\r
+#define BITS_H\r
+\r
+#include "device.h"\r
+\r
+// Contains the odd-parity flag for a given 8-bit value.\r
+extern const uint8 Lookup_OddParity[256];\r
+\r
+uint8 countBits(uint8 value);\r
+\r
+#endif
\ No newline at end of file
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//\r
+// This file is part of SCSI2SD.\r
+//\r
+// SCSI2SD is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License, or\r
+// (at your option) any later version.\r
+//\r
+// SCSI2SD is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
+\r
+#include "blinky.h"\r
+#include "device.h"\r
+\r
+void scsi2sd_test_blink(void)\r
+{\r
+ // Toggle LED.\r
+ while (1)\r
+ {\r
+ LED1_Write(0);\r
+ CyDelay(1000); // ms\r
+ LED1_Write(1);\r
+ CyDelay(250); // ms\r
+ }\r
+}
\ No newline at end of file
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//\r
+// This file is part of SCSI2SD.\r
+//\r
+// SCSI2SD is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License, or\r
+// (at your option) any later version.\r
+//\r
+// SCSI2SD is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
+\r
+#ifndef SCSI2SD_BLINKY_H\r
+#define SCSI2SD_BLINKY_H\r
+\r
+// Helloworld LED blink test.\r
+void scsi2sd_test_blink(void);\r
+\r
+\r
+#endif // SCSI2SD_POST_H\r
--- /dev/null
+/*******************************************************************************\r
+* This file is automatically generated by PSoC Creator\r
+* and should not be edited by hand.\r
+*\r
+* This file is necessary for your project to build.\r
+* Please do not delete it.\r
+********************************************************************************\r
+* Copyright 2008-2011, Cypress Semiconductor Corporation. All rights reserved.\r
+* You may use this file only in accordance with the license, terms, conditions,\r
+* disclaimers, and limitations in the end user license agreement accompanying\r
+* the software package with which this file was provided.\r
+*******************************************************************************/\r
+#ifndef DEVICE_H\r
+#define DEVICE_H\r
+#include <project.h>\r
+\r
+#endif\r
+/* [] END OF FILE */\r
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//\r
+// This file is part of SCSI2SD.\r
+//\r
+// SCSI2SD is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License, or\r
+// (at your option) any later version.\r
+//\r
+// SCSI2SD is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
+\r
+#include "device.h"\r
+#include "scsi.h"\r
+#include "diagnostic.h"\r
+\r
+#include <string.h>\r
+\r
+static const uint8 SupportedDiagnosticPages[] =\r
+{\r
+0x00, // Page Code\r
+0x00, // Reserved\r
+0x02, // Page length\r
+0x00, // Support "Supported diagnostic page"\r
+0x40 // Support "Translate address page"\r
+};\r
+\r
+void scsiSendDiagnostic()\r
+{\r
+ // SEND DIAGNOSTIC\r
+ // Pretend to do self-test. Actual data is returned via the\r
+ // RECEIVE DIAGNOSTIC RESULTS command.\r
+ int selfTest = scsiDev.cdb[1] & 0x04;\r
+ uint32 paramLength =\r
+ (((uint32) scsiDev.cdb[3]) << 8) +\r
+ scsiDev.cdb[4];\r
+\r
+ if (!selfTest)\r
+ {\r
+ // Initiator sends us page data.\r
+ scsiDev.dataLen = paramLength;\r
+ scsiDev.phase = DATA_OUT;\r
+\r
+ if (scsiDev.dataLen > sizeof (scsiDev.data))\r
+ {\r
+ // Nowhere to store this data!\r
+ // Shouldn't happen - our buffer should be many magnitudes larger\r
+ // than the required size for diagnostic parameters.\r
+ scsiDev.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.sense.asc = INVALID_FIELD_IN_CDB;\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ // Default command result will be a status of GOOD anyway.\r
+ }\r
+}\r
+\r
+void scsiReceiveDiagnostic()\r
+{\r
+ // RECEIVE DIAGNOSTIC RESULTS\r
+ // We assume scsiDev.data contains the contents of a previous\r
+ // SEND DIAGNOSTICS command. We only care about the page-code part\r
+ // of the parameter list.\r
+ uint8 pageCode = scsiDev.data[0];\r
+\r
+ int allocLength =\r
+ (((uint16) scsiDev.cdb[3]) << 8) +\r
+ scsiDev.cdb[4];\r
+\r
+\r
+ if (pageCode == 0x00)\r
+ {\r
+ memcpy(\r
+ scsiDev.data,\r
+ SupportedDiagnosticPages,\r
+ sizeof(SupportedDiagnosticPages));\r
+ scsiDev.dataLen = sizeof(SupportedDiagnosticPages);\r
+ scsiDev.phase = DATA_IN;\r
+ }\r
+ else if (pageCode == 0x40)\r
+ {\r
+ // Translate between logical block address, physical sector address, or\r
+ // physical bytes.\r
+ uint8 suppliedFmt = scsiDev.data[4] & 0x7;\r
+ uint8 translateFmt = scsiDev.data[5] & 0x7;\r
+\r
+ // Convert each supplied address back to a simple\r
+ // 64bit linear address, then convert back again.\r
+ uint64 fromByteAddr =\r
+ scsiByteAddress(suppliedFmt, &scsiDev.data[6]);\r
+\r
+ scsiSaveByteAddress(translateFmt, fromByteAddr, &scsiDev.data[6]);\r
+\r
+ // Fill out the rest of the response.\r
+ // (Clear out any optional bits).\r
+ scsiDev.data[4] = suppliedFmt;\r
+ scsiDev.data[5] = translateFmt;\r
+\r
+ scsiDev.dataLen = 14;\r
+ scsiDev.phase = DATA_IN;\r
+ }\r
+ else\r
+ {\r
+ // error.\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.sense.asc = INVALID_FIELD_IN_CDB;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+\r
+ if (scsiDev.phase == DATA_IN && scsiDev.dataLen > allocLength)\r
+ {\r
+ // simply truncate the response.\r
+ scsiDev.dataLen = allocLength;\r
+ }\r
+\r
+ uint8 lun = scsiDev.cdb[1] >> 5;\r
+ // Set the first byte to indicate LUN presence.\r
+ if (lun) // We only support lun 0\r
+ {\r
+ scsiDev.data[0] = 0x7F;\r
+ }\r
+}\r
+\r
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+#ifndef DIAGNOSTIC_H
+#define DIAGNOSTIC_H
+
+void scsiSendDiagnostic();
+void scsiReceiveDiagnostic();
+
+#endif
\ No newline at end of file
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//\r
+// This file is part of SCSI2SD.\r
+//\r
+// SCSI2SD is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License, or\r
+// (at your option) any later version.\r
+//\r
+// SCSI2SD is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
+\r
+#include "device.h"\r
+#include "scsi.h"\r
+#include "disk.h"\r
+\r
+#include <string.h>\r
+\r
+// Global\r
+BlockDevice blockDev;\r
+Transfer transfer;\r
+\r
+static void startRead(int nextBlock);\r
+static int sdInit();\r
+\r
+static void doFormatUnit()\r
+{\r
+ // Low-level formatting is not required.\r
+ // Nothing left to do.\r
+}\r
+\r
+static void doReadCapacity()\r
+{\r
+ uint32 lba = (((uint32) scsiDev.cdb[2]) << 24) +\r
+ (((uint32) scsiDev.cdb[3]) << 16) +\r
+ (((uint32) scsiDev.cdb[4]) << 8) +\r
+ scsiDev.cdb[5];\r
+ int pmi = scsiDev.cdb[8] & 1;\r
+\r
+ if (!pmi && lba)\r
+ {\r
+ // error.\r
+ // We don't do anything with the "partial medium indicator", and\r
+ // assume that delays are constant across each block. But the spec\r
+ // says we must return this error if pmi is specified incorrectly.\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.sense.asc = INVALID_FIELD_IN_CDB;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+ else if (blockDev.capacity > 0)\r
+ {\r
+ uint32 highestBlock = blockDev.capacity - 1;\r
+\r
+ scsiDev.data[0] = highestBlock >> 24;\r
+ scsiDev.data[1] = highestBlock >> 16;\r
+ scsiDev.data[2] = highestBlock >> 8;\r
+ scsiDev.data[3] = highestBlock;\r
+\r
+ scsiDev.data[4] = blockDev.bs >> 24;\r
+ scsiDev.data[5] = blockDev.bs >> 16;\r
+ scsiDev.data[6] = blockDev.bs >> 8;\r
+ scsiDev.data[7] = blockDev.bs;\r
+ scsiDev.dataLen = 8;\r
+ scsiDev.phase = DATA_IN;\r
+ }\r
+ else\r
+ {\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = NOT_READY;\r
+ scsiDev.sense.asc = MEDIUM_NOT_PRESENT;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+}\r
+\r
+static void doWrite(uint32 lba, uint32 blocks)\r
+{\r
+ if (blockDev.state & DISK_WP)\r
+ {\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.sense.asc = WRITE_PROTECTED;\r
+ scsiDev.phase = STATUS; \r
+ }\r
+ else if (((uint64) lba) + blocks > blockDev.capacity)\r
+ {\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.sense.asc = LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+ else\r
+ {\r
+ transfer.dir = TRANSFER_WRITE;\r
+ transfer.lba = lba;\r
+ transfer.blocks = blocks;\r
+ transfer.currentBlock = 0;\r
+ scsiDev.phase = DATA_OUT;\r
+ scsiDev.dataLen = SCSI_BLOCK_SIZE;\r
+ }\r
+}\r
+\r
+\r
+static void doRead(uint32 lba, uint32 blocks)\r
+{\r
+ if (((uint64) lba) + blocks > blockDev.capacity)\r
+ {\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.sense.asc = LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+ else\r
+ {\r
+ transfer.dir = TRANSFER_READ;\r
+ transfer.lba = lba;\r
+ transfer.blocks = blocks;\r
+ transfer.currentBlock = 0;\r
+ scsiDev.phase = DATA_IN;\r
+ scsiDev.dataLen = 0; // No data yet\r
+ startRead(0);\r
+ }\r
+}\r
+\r
+static void doSeek(uint32 lba)\r
+{\r
+ if (lba >= blockDev.capacity)\r
+ {\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.sense.asc = LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+}\r
+\r
+static int doTestUnitReady()\r
+{\r
+ int ready = 1;\r
+ if (!(blockDev.state & DISK_STARTED))\r
+ {\r
+ ready = 0;\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = NOT_READY;\r
+ scsiDev.sense.asc = LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+ else if (!(blockDev.state & DISK_PRESENT))\r
+ {\r
+ ready = 0;\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = NOT_READY;\r
+ scsiDev.sense.asc = MEDIUM_NOT_PRESENT;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+ else if (!(blockDev.state & DISK_INITIALISED))\r
+ {\r
+ ready = 0;\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = NOT_READY;\r
+ scsiDev.sense.asc = LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+ return ready;\r
+}\r
+\r
+// Handle direct-access scsi device commands\r
+int scsiDiskCommand()\r
+{\r
+ int commandHandled = 1;\r
+\r
+ uint8 command = scsiDev.cdb[0];\r
+ if (command == 0x1B)\r
+ {\r
+ // START STOP UNIT\r
+ // Enable or disable media access operations.\r
+ // Ignore load/eject requests. We can't do that.\r
+ //int immed = scsiDev.cdb[1] & 1;\r
+ int start = scsiDev.cdb[4] & 1;\r
+\r
+ if (start)\r
+ {\r
+ blockDev.state = blockDev.state | DISK_STARTED;\r
+ if (!(blockDev.state & DISK_INITIALISED))\r
+ {\r
+ if (sdInit())\r
+ {\r
+ blockDev.state = blockDev.state | DISK_INITIALISED;\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ blockDev.state = blockDev.state & (-1 ^ DISK_STARTED);\r
+ }\r
+ }\r
+ else if (command == 0x00)\r
+ {\r
+ // TEST UNIT READY\r
+ doTestUnitReady();\r
+ }\r
+ else if (!doTestUnitReady())\r
+ {\r
+ // Status and sense codes already set by doTestUnitReady\r
+ }\r
+ else if (command == 0x04)\r
+ {\r
+ // FORMAT UNIT\r
+ doFormatUnit();\r
+ }\r
+ else if (command == 0x08)\r
+ {\r
+ // READ(6)\r
+ uint32 lba =\r
+ (((uint32) scsiDev.cdb[1] & 0x1F) << 16) +\r
+ (((uint32) scsiDev.cdb[2]) << 8) +\r
+ scsiDev.cdb[3];\r
+ uint32 blocks = scsiDev.cdb[4];\r
+ if (blocks == 0) blocks = 256;\r
+ doRead(lba, blocks);\r
+ }\r
+\r
+ else if (command == 0x28)\r
+ {\r
+ // READ(10)\r
+ // Ignore all cache control bits - we don't support a memory cache.\r
+\r
+ uint32 lba =\r
+ (((uint32) scsiDev.cdb[2]) << 24) +\r
+ (((uint32) scsiDev.cdb[3]) << 16) +\r
+ (((uint32) scsiDev.cdb[4]) << 8) +\r
+ scsiDev.cdb[5];\r
+ uint32 blocks =\r
+ (((uint32) scsiDev.cdb[7]) << 8) +\r
+ scsiDev.cdb[8];\r
+\r
+ doRead(lba, blocks);\r
+ }\r
+\r
+ else if (command == 0x25)\r
+ {\r
+ // READ CAPACITY\r
+ doReadCapacity();\r
+ }\r
+\r
+ else if (command == 0x0B)\r
+ {\r
+ // SEEK(6)\r
+ uint32 lba =\r
+ (((uint32) scsiDev.cdb[1] & 0x1F) << 16) +\r
+ (((uint32) scsiDev.cdb[2]) << 8) +\r
+ scsiDev.cdb[3];\r
+\r
+ doSeek(lba);\r
+ }\r
+\r
+ else if (command == 0x2B)\r
+ {\r
+ // SEEK(10)\r
+ uint32 lba =\r
+ (((uint32) scsiDev.cdb[2]) << 24) +\r
+ (((uint32) scsiDev.cdb[3]) << 16) +\r
+ (((uint32) scsiDev.cdb[4]) << 8) +\r
+ scsiDev.cdb[5];\r
+\r
+ doSeek(lba);\r
+ }\r
+ else if (command == 0x0A)\r
+ {\r
+ // WRITE(6)\r
+ uint32 lba =\r
+ (((uint32) scsiDev.cdb[1] & 0x1F) << 16) +\r
+ (((uint32) scsiDev.cdb[2]) << 8) +\r
+ scsiDev.cdb[3];\r
+ uint32 blocks = scsiDev.cdb[4];\r
+ if (blocks == 0) blocks = 256;\r
+ doWrite(lba, blocks);\r
+ }\r
+\r
+ else if (command == 0x2A)\r
+ {\r
+ // WRITE(10)\r
+ // Ignore all cache control bits - we don't support a memory cache.\r
+\r
+ uint32 lba =\r
+ (((uint32) scsiDev.cdb[2]) << 24) +\r
+ (((uint32) scsiDev.cdb[3]) << 16) +\r
+ (((uint32) scsiDev.cdb[4]) << 8) +\r
+ scsiDev.cdb[5];\r
+ uint32 blocks =\r
+ (((uint32) scsiDev.cdb[7]) << 8) +\r
+ scsiDev.cdb[8];\r
+\r
+ doWrite(lba, blocks);\r
+ }\r
+ else if (command == 0x36)\r
+ {\r
+ // LOCK UNLOCK CACHE\r
+ // We don't have a cache to lock data into. do nothing.\r
+ }\r
+ else if (command == 0x34)\r
+ {\r
+ // PRE-FETCH.\r
+ // We don't have a cache to pre-fetch into. do nothing.\r
+ }\r
+ else if (command == 0x1E)\r
+ {\r
+ // PREVENT ALLOW MEDIUM REMOVAL\r
+ // Not much we can do to prevent the user removing the SD card.\r
+ // do nothing.\r
+ }\r
+ else if (command == 0x01)\r
+ {\r
+ // REZERO UNIT\r
+ // Set the lun to a vendor-specific state. Ignore.\r
+ }\r
+ else if (command == 0x35)\r
+ {\r
+ // SYNCHRONIZE CACHE\r
+ // We don't have a cache. do nothing.\r
+ }\r
+ else\r
+ {\r
+ commandHandled = 0;\r
+ }\r
+\r
+ return commandHandled;\r
+}\r
+\r
+\r
+static uint8 sdCrc7(uint8* chr, uint8 cnt, uint8 crc)\r
+{\r
+ uint8 a;\r
+ for(a = 0; a < cnt; a++)\r
+ {\r
+ uint8 Data = chr[a];\r
+ uint8 i;\r
+ for(i = 0; i < 8; i++)\r
+ {\r
+ crc <<= 1;\r
+ if( (Data & 0x80) ^ (crc & 0x80) ) {crc ^= 0x09;}\r
+ Data <<= 1;\r
+ }\r
+ }\r
+ return crc & 0x7F;\r
+}\r
+\r
+// Read and write 1 byte.\r
+static uint8 sdSpiByte(uint8 value)\r
+{\r
+ SDCard_WriteTxData(value);\r
+ while(!(SDCard_ReadTxStatus() & SDCard_STS_SPI_DONE))\r
+ {}\r
+ while (!SDCard_GetRxBufferSize()) {}\r
+ return SDCard_ReadRxData();\r
+}\r
+\r
+static void sdSendCommand(uint8 cmd, uint32 param)\r
+{\r
+ uint8 send[6];\r
+\r
+ send[0] = cmd | 0x40;\r
+ send[1] = param >> 24;\r
+ send[2] = param >> 16;\r
+ send[3] = param >> 8;\r
+ send[4] = param;\r
+ send[5] = (sdCrc7(send, 5, 0) << 1) | 1;\r
+\r
+ for(cmd = 0; cmd < sizeof(send); cmd++)\r
+ {\r
+ sdSpiByte(send[cmd]);\r
+ }\r
+}\r
+\r
+static uint8 sdReadResp()\r
+{\r
+ uint8 v;\r
+ uint8 i = 128;\r
+ do\r
+ {\r
+ v = sdSpiByte(0xFF);\r
+ } while(i-- && (v == 0xFF));\r
+ return v;\r
+}\r
+\r
+static uint8 sdWaitResp()\r
+{\r
+ uint8 v;\r
+ uint8 i = 255;\r
+ do\r
+ {\r
+ v = sdSpiByte(0xFF);\r
+ } while(i-- && (v != 0xFE));\r
+ return v;\r
+}\r
+\r
+\r
+static uint8 sdCommandAndResponse(uint8 cmd, uint32 param)\r
+{\r
+ SDCard_ClearRxBuffer();\r
+ sdSpiByte(0xFF);\r
+ sdSendCommand(cmd, param);\r
+ return sdReadResp();\r
+}\r
+\r
+\r
+static int sdInit()\r
+{\r
+ int result = 0;\r
+ SD_CS_Write(1); // Set CS inactive (active low)\r
+ SD_Init_Clk_Start(); // Turn on the slow 400KHz clock\r
+ SD_Clk_Ctl_Write(0); // Select the 400KHz clock source.\r
+ SDCard_Start(); // Enable SPI hardware\r
+ \r
+ // Power on sequence. 74 clock cycles of a "1" while CS unasserted.\r
+ int i;\r
+ for (i = 0; i < 10; ++i)\r
+ {\r
+ sdSpiByte(0xFF);\r
+ }\r
+\r
+ SD_CS_Write(0); // Set CS active (active low)\r
+ CyDelayUs(1);\r
+\r
+ uint8 v = sdCommandAndResponse(0, 0);\r
+ if(v != 1){goto bad;}\r
+\r
+ // TODO CMD8 + valid CC for ver2 + cards. arg 0x00..01AA\r
+\r
+\r
+ // TODO SDv2 support: ACMD41, fallback to CMD1\r
+\r
+ v = sdCommandAndResponse(1, 0);\r
+ for(i=0;v != 0 && i<50;++i){\r
+ CyDelay(50);\r
+ v = sdCommandAndResponse(1, 0);\r
+ }\r
+ if(v){goto bad;}\r
+ \r
+ v = sdCommandAndResponse(16, SCSI_BLOCK_SIZE); //Force sector size\r
+ if(v){goto bad;}\r
+ v = sdCommandAndResponse(59, 0); //crc off\r
+ if(v){goto bad;}\r
+\r
+ // now set the sd card up for full speed\r
+ SD_Data_Clk_Start(); // Turn on the fast clock\r
+ SD_Clk_Ctl_Write(1); // Select the fast clock source.\r
+ SD_Init_Clk_Stop(); // Stop the slow clock.\r
+ \r
+ v = sdCommandAndResponse(0x9, 0);\r
+ if(v){goto bad;}\r
+ v = sdWaitResp();\r
+ if (v != 0xFE) { goto bad; }\r
+ uint8 buf[16];\r
+ for (i = 0; i < 16; ++i)\r
+ {\r
+ buf[i] = sdSpiByte(0xFF);\r
+ }\r
+ sdSpiByte(0xFF); // CRC \r
+ sdSpiByte(0xFF); // CRC\r
+ uint32 c_size = (((((uint32)buf[6]) & 0x3) << 16) | (((uint32)buf[7]) << 8) | buf[8]) >> 6;\r
+ uint32 c_mult = (((((uint32)buf[9]) & 0x3) << 8) | ((uint32)buf[0xa])) >> 7;\r
+ uint32 sectorSize = buf[5] & 0x0F;\r
+ blockDev.capacity = ((c_size+1) * ((uint64)1 << (c_mult+2)) * ((uint64)1 << sectorSize)) / SCSI_BLOCK_SIZE;\r
+ result = 1;\r
+ goto out;\r
+ \r
+bad:\r
+ blockDev.capacity = 0;\r
+ \r
+out:\r
+ return result;\r
+\r
+}\r
+\r
+static void startRead(int nextBlock)\r
+{\r
+// TODO 4Gb limit\r
+// NOTE: CMD17 is NOT in hex. decimal 17.\r
+ uint8 v = sdCommandAndResponse(17, ((uint32)SCSI_BLOCK_SIZE) * (transfer.lba + transfer.currentBlock + nextBlock));\r
+ if (v)\r
+ {\r
+ scsiDiskReset();\r
+\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = HARDWARE_ERROR;\r
+ scsiDev.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+}\r
+\r
+static int readReady()\r
+{\r
+ uint8 v = sdWaitResp();\r
+ if (v == 0xFF)\r
+ {\r
+ return 0;\r
+ }\r
+ else if (v == 0xFE)\r
+ {\r
+ return 1;\r
+ }\r
+ else\r
+ {\r
+ scsiDiskReset();\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = HARDWARE_ERROR;\r
+ scsiDev.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
+ scsiDev.phase = STATUS;\r
+ return 0;\r
+ }\r
+}\r
+static void readSector()\r
+{\r
+// TODO this is slow. Really slow.\r
+// Even if we don't use DMA, we still want to read/write multiple bytes\r
+// at a time.\r
+/*\r
+ int i;\r
+ for (i = 0; i < SCSI_BLOCK_SIZE; ++i)\r
+ {\r
+ scsiDev.data[i] = sdSpiByte(0xFF);\r
+ }\r
+*/\r
+\r
+ // We have a spi FIFO of 4 bytes. use it.\r
+ // This is much better, byut after 4 bytes we're still\r
+ // blocking a bit.\r
+ int i;\r
+ for (i = 0; i < SCSI_BLOCK_SIZE; i+=4)\r
+ {\r
+ SDCard_WriteTxData(0xFF);\r
+ SDCard_WriteTxData(0xFF);\r
+ SDCard_WriteTxData(0xFF);\r
+ SDCard_WriteTxData(0xFF);\r
+\r
+ while(!(SDCard_ReadTxStatus() & SDCard_STS_SPI_DONE))\r
+ {}\r
+ scsiDev.data[i] = SDCard_ReadRxData();\r
+ scsiDev.data[i+1] = SDCard_ReadRxData();\r
+ scsiDev.data[i+2] = SDCard_ReadRxData();\r
+ scsiDev.data[i+3] = SDCard_ReadRxData();\r
+\r
+ }\r
+\r
+\r
+ sdSpiByte(0xFF); // CRC\r
+ sdSpiByte(0xFF); // CRC\r
+ scsiDev.dataLen = SCSI_BLOCK_SIZE;\r
+ scsiDev.dataPtr = 0;\r
+}\r
+\r
+static void writeSector()\r
+{\r
+ uint8 v = sdCommandAndResponse(24, ((uint32)SCSI_BLOCK_SIZE) * (transfer.lba + transfer.currentBlock));\r
+ if (v)\r
+ {\r
+ scsiDiskReset();\r
+\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = HARDWARE_ERROR;\r
+ scsiDev.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+ else\r
+ {\r
+ SDCard_WriteTxData(0xFE);\r
+ int i;\r
+ for (i = 0; i < SCSI_BLOCK_SIZE; ++i)\r
+ {\r
+ SDCard_WriteTxData(scsiDev.data[i]);\r
+ }\r
+ while(!(SDCard_ReadTxStatus() & SDCard_STS_SPI_DONE))\r
+ {}\r
+ sdSpiByte(0x00); // CRC\r
+ sdSpiByte(0x00); // CRC\r
+ SDCard_ClearRxBuffer(); \r
+ v = sdSpiByte(0x00); // Response\r
+ if (((v & 0x1F) >> 1) != 0x2) // Accepted.\r
+ {\r
+ scsiDiskReset();\r
+\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = HARDWARE_ERROR;\r
+ scsiDev.sense.asc = LOGICAL_UNIT_COMMUNICATION_FAILURE;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+ else\r
+ {\r
+ // Wait for the card to come out of busy.\r
+ v = sdSpiByte(0xFF);\r
+ while (v == 0)\r
+ {\r
+ v = sdSpiByte(0xFF);\r
+ }\r
+ uint8 r1 = sdCommandAndResponse(13, 0); // send status\r
+ uint8 r2 = sdSpiByte(0xFF);\r
+ if (r1 || r2)\r
+ {\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = HARDWARE_ERROR;\r
+ scsiDev.sense.asc = WRITE_ERROR_AUTO_REALLOCATION_FAILED;\r
+ scsiDev.phase = STATUS; \r
+ }\r
+ }\r
+ }\r
+}\r
+\r
+void scsiDiskPoll()\r
+{\r
+ if (scsiDev.phase == DATA_IN &&\r
+ transfer.currentBlock != transfer.blocks)\r
+ {\r
+ if (scsiDev.dataLen == 0)\r
+ {\r
+ if (readReady())\r
+ {\r
+ readSector();\r
+ if ((transfer.currentBlock + 1) < transfer.blocks)\r
+ {\r
+ startRead(1); // Tell SD card to grab data while we send\r
+ // buffer to SCSI.\r
+ }\r
+ }\r
+ }\r
+ else if (scsiDev.dataPtr == scsiDev.dataLen)\r
+ {\r
+ scsiDev.dataLen = 0;\r
+ scsiDev.dataPtr = 0;\r
+ transfer.currentBlock++;\r
+ if (transfer.currentBlock >= transfer.blocks)\r
+ {\r
+ scsiDev.phase = STATUS;\r
+ scsiDiskReset();\r
+ }\r
+ }\r
+ }\r
+ else if (scsiDev.phase == DATA_OUT &&\r
+ transfer.currentBlock != transfer.blocks)\r
+ {\r
+ if (scsiDev.dataPtr == SCSI_BLOCK_SIZE)\r
+ {\r
+ writeSector();\r
+ scsiDev.dataPtr = 0;\r
+ transfer.currentBlock++;\r
+ if (transfer.currentBlock >= transfer.blocks)\r
+ {\r
+ scsiDev.dataLen = 0;\r
+ scsiDev.phase = STATUS;\r
+ scsiDiskReset();\r
+ }\r
+ }\r
+ } \r
+}\r
+\r
+void scsiDiskReset()\r
+{\r
+ // todo if SPI command in progress, cancel it.\r
+ scsiDev.dataPtr = 0;\r
+ scsiDev.savedDataPtr = 0;\r
+ scsiDev.dataLen = 0;\r
+ transfer.lba = 0;\r
+ transfer.blocks = 0;\r
+ transfer.currentBlock = 0;\r
+}\r
+\r
+void scsiDiskInit()\r
+{\r
+ blockDev.bs = SCSI_BLOCK_SIZE;\r
+ blockDev.capacity = 0;\r
+ scsiDiskReset();\r
+\r
+ // Don't require the host to send us a START STOP UNIT command\r
+ blockDev.state = DISK_STARTED;\r
+ if (SD_WP_Read())\r
+ {\r
+ blockDev.state = blockDev.state | DISK_WP;\r
+ }\r
+\r
+ if (SD_CD_Read() == 0)\r
+ {\r
+ blockDev.state = blockDev.state | DISK_PRESENT;\r
+\r
+// todo IF FAILS, TRY AGAIN LATER.\r
+// 5000 works well with the Mac.\r
+ CyDelay(5000); // allow the card to wake up.\r
+ if (sdInit())\r
+ {\r
+ blockDev.state = blockDev.state | DISK_INITIALISED;\r
+ }\r
+ }\r
+}\r
+\r
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+#ifndef DISK_H
+#define DISK_H
+
+typedef enum
+{
+ DISK_STARTED = 1, // Controlled via START STOP UNIT
+ DISK_PRESENT = 2, // SD card is physically present
+ DISK_INITIALISED = 4, // SD card responded to init sequence
+ DISK_WP = 8 // Write-protect.
+} DISK_STATE;
+
+typedef enum
+{
+ TRANSFER_READ,
+ TRANSFER_WRITE
+} TRANSFER_DIR;
+
+typedef struct
+{
+ uint32 bs; // Block size.
+ uint32 capacity; // In blocks.
+
+ int state;
+} BlockDevice;
+
+typedef struct
+{
+ int dir;
+ uint32 lba;
+ uint32 blocks;
+
+ uint32 currentBlock;
+} Transfer;
+
+extern BlockDevice blockDev;
+extern Transfer transfer;
+
+void scsiDiskInit();
+void scsiDiskReset();
+void scsiDiskPoll();
+int scsiDiskCommand();
+
+#endif
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//\r
+// This file is part of SCSI2SD.\r
+//\r
+// SCSI2SD is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License, or\r
+// (at your option) any later version.\r
+//\r
+// SCSI2SD is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
+\r
+#include "geometry.h"\r
+#include "scsi.h"\r
+\r
+#include <string.h>\r
+\r
+// Standard mapping according to ECMA-107 and ISO/IEC 9293:1994\r
+// Sector always starts at 1. There is no 0 sector.\r
+uint64 CHS2LBA(uint32 c, uint8 h, uint32 s)\r
+{\r
+ return (\r
+ (((uint64)c) * SCSI_HEADS_PER_CYLINDER + h) *\r
+ (uint64) SCSI_SECTORS_PER_TRACK\r
+ ) + (s - 1);\r
+}\r
+\r
+\r
+void LBA2CHS(uint32 lba, uint32* c, uint8* h, uint32* s)\r
+{\r
+ *c = lba / (SCSI_SECTORS_PER_TRACK * SCSI_HEADS_PER_CYLINDER);\r
+ *h = (lba / SCSI_SECTORS_PER_TRACK) % SCSI_HEADS_PER_CYLINDER;\r
+ *s = (lba % SCSI_SECTORS_PER_TRACK) + 1;\r
+}\r
+\r
+uint64 scsiByteAddress(int format, const uint8* addr)\r
+{\r
+ uint64 result;\r
+ switch (format)\r
+ {\r
+ case ADDRESS_BLOCK:\r
+ {\r
+ uint32 lba =\r
+ (((uint32) addr[0]) << 24) +\r
+ (((uint32) addr[1]) << 16) +\r
+ (((uint32) addr[2]) << 8) +\r
+ addr[3];\r
+\r
+ result = (uint64) SCSI_BLOCK_SIZE * lba;\r
+ } break;\r
+\r
+ case ADDRESS_PHYSICAL_BYTE:\r
+ {\r
+ uint32 cyl =\r
+ (((uint32) addr[0]) << 16) +\r
+ (((uint32) addr[1]) << 8) +\r
+ addr[2];\r
+\r
+ uint8 head = addr[3];\r
+\r
+ uint32 bytes =\r
+ (((uint32) addr[4]) << 24) +\r
+ (((uint32) addr[5]) << 16) +\r
+ (((uint32) addr[6]) << 8) +\r
+ addr[7];\r
+\r
+ result = CHS2LBA(cyl, head, 1) * (uint64) SCSI_SECTOR_SIZE + bytes;\r
+ } break;\r
+\r
+ case ADDRESS_PHYSICAL_SECTOR:\r
+ {\r
+ uint32 cyl =\r
+ (((uint32) addr[0]) << 16) +\r
+ (((uint32) addr[1]) << 8) +\r
+ addr[2];\r
+\r
+ uint8 head = scsiDev.data[3];\r
+\r
+ uint32 sector =\r
+ (((uint32) addr[4]) << 24) +\r
+ (((uint32) addr[5]) << 16) +\r
+ (((uint32) addr[6]) << 8) +\r
+ addr[7];\r
+\r
+ result = CHS2LBA(cyl, head, sector) * (uint64) SCSI_SECTOR_SIZE;\r
+ } break;\r
+\r
+ default:\r
+ result = -1;\r
+ }\r
+\r
+ return result;\r
+}\r
+\r
+\r
+void scsiSaveByteAddress(int format, uint64 byteAddr, uint8* buf)\r
+{\r
+ uint32 lba = byteAddr / SCSI_BLOCK_SIZE;\r
+ uint32 byteOffset = byteAddr % SCSI_BLOCK_SIZE;\r
+\r
+ switch (format)\r
+ {\r
+ case ADDRESS_BLOCK:\r
+ {\r
+ buf[0] = lba >> 24;\r
+ buf[1] = lba >> 16;\r
+ buf[2] = lba >> 8;\r
+ buf[3] = lba;\r
+\r
+ buf[4] = 0;\r
+ buf[5] = 0;\r
+ buf[6] = 0;\r
+ buf[7] = 0;\r
+ } break;\r
+\r
+ case ADDRESS_PHYSICAL_BYTE:\r
+ {\r
+ uint32 cyl;\r
+ uint8 head;\r
+ uint32 sector;\r
+\r
+ LBA2CHS(lba, &cyl, &head, §or);\r
+\r
+ uint32 bytes = sector * SCSI_SECTOR_SIZE + byteOffset;\r
+\r
+ buf[0] = cyl >> 16;\r
+ buf[1] = cyl >> 8;\r
+ buf[2] = cyl;\r
+\r
+ buf[3] = head;\r
+\r
+ buf[4] = bytes >> 24;\r
+ buf[5] = bytes >> 16;\r
+ buf[6] = bytes >> 8;\r
+ buf[7] = bytes;\r
+ } break;\r
+\r
+ case ADDRESS_PHYSICAL_SECTOR:\r
+ {\r
+ uint32 cyl;\r
+ uint8 head;\r
+ uint32 sector;\r
+\r
+ LBA2CHS(lba, &cyl, &head, §or);\r
+\r
+ buf[0] = cyl >> 16;\r
+ buf[1] = cyl >> 8;\r
+ buf[2] = cyl;\r
+\r
+ buf[3] = head;\r
+\r
+ buf[4] = sector >> 24;\r
+ buf[5] = sector >> 16;\r
+ buf[6] = sector >> 8;\r
+ buf[7] = sector;\r
+ } break;\r
+\r
+ default:\r
+ memset(buf, 0, 8);\r
+ }\r
+\r
+}\r
+\r
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+#ifndef GEOMETRY_H
+#define GEOMETRY_H
+
+#include "device.h"
+
+// We make some assumptions that the block size and sector size
+// are always equal.
+#define SCSI_BLOCK_SIZE 512
+#define SCSI_SECTOR_SIZE 512
+
+// Max allowed by legacy IBM-PC Bios (6 bits)
+#define SCSI_SECTORS_PER_TRACK 63
+
+// MS-DOS up to 7.10 will crash on 256 heads.
+#define SCSI_HEADS_PER_CYLINDER 255
+
+typedef enum
+{
+ ADDRESS_BLOCK = 0,
+ ADDRESS_PHYSICAL_BYTE = 4,
+ ADDRESS_PHYSICAL_SECTOR = 5
+} SCSI_ADDRESS_FORMAT;
+
+
+uint64 CHS2LBA(uint32 c, uint8 h, uint32 s);
+void LBA2CHS(uint32 lba, uint32* c, uint8* h, uint32* s);
+
+// Convert an address in the given SCSI_ADDRESS_FORMAT to
+// a linear byte address.
+// addr must be >= 8 bytes.
+uint64 scsiByteAddress(int format, const uint8* addr);
+void scsiSaveByteAddress(int format, uint64 byteAddr, uint8* buf);
+
+
+#endif
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//\r
+// This file is part of SCSI2SD.\r
+//\r
+// SCSI2SD is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License, or\r
+// (at your option) any later version.\r
+//\r
+// SCSI2SD is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
+\r
+#include "device.h"\r
+#include "scsi.h"\r
+#include "inquiry.h"\r
+\r
+#include <string.h>\r
+\r
+static const uint8 StandardResponse[] =\r
+{\r
+0x00, // "Direct-access device". AKA standard hard disk\r
+0x00, // device type qualifier\r
+0x02, // Complies with ANSI SCSI-2.\r
+0x02, // SCSI-2 Inquiry response\r
+31, // standard length\r
+0, 0, //Reserved\r
+0, // We don't support anything at all\r
+'c','o','d','e','s','r','c',' ',\r
+'S','C','S','I','2','S','D',' ',' ',' ',' ',' ',' ',' ',' ',' ',\r
+'2','.','0','a'\r
+};\r
+\r
+static const uint8 SupportedVitalPages[] =\r
+{\r
+0x00, // "Direct-access device". AKA standard hard disk\r
+0x00, // Page Code\r
+0x00, // Reserved\r
+0x04, // Page length\r
+0x00, // Support "Supported vital product data pages"\r
+0x80, // Support "Unit serial number page"\r
+0x81, // Support "Implemented operating definition page"\r
+0x82 // Support "ASCII Implemented operating definition page"\r
+};\r
+\r
+static const uint8 UnitSerialNumber[] =\r
+{\r
+0x00, // "Direct-access device". AKA standard hard disk\r
+0x80, // Page Code\r
+0x00, // Reserved\r
+0x10, // Page length\r
+'c','o','d','e','s','r','c','-','1','2','3','4','5','6','7','8'\r
+};\r
+\r
+static const uint8 ImpOperatingDefinition[] =\r
+{\r
+0x00, // "Direct-access device". AKA standard hard disk\r
+0x81, // Page Code\r
+0x00, // Reserved\r
+0x03, // Page length\r
+0x03, // Current: SCSI-2 operating definition\r
+0x03, // Default: SCSI-2 operating definition\r
+0x03 // Supported (list): SCSI-2 operating definition.\r
+};\r
+\r
+static const uint8 AscImpOperatingDefinition[] =\r
+{\r
+0x00, // "Direct-access device". AKA standard hard disk\r
+0x82, // Page Code\r
+0x00, // Reserved\r
+0x07, // Page length\r
+0x06, // Ascii length\r
+'S','C','S','I','-','2'\r
+};\r
+\r
+void scsiInquiry()\r
+{\r
+ uint8 evpd = scsiDev.cdb[1] & 1; // enable vital product data.\r
+ uint8 pageCode = scsiDev.cdb[2];\r
+ uint8 lun = scsiDev.cdb[1] >> 5;\r
+ uint32 allocationLength = scsiDev.cdb[4];\r
+ if (allocationLength == 0) allocationLength = 256;\r
+\r
+ if (!evpd)\r
+ {\r
+ if (pageCode)\r
+ {\r
+ // error.\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.sense.asc = INVALID_FIELD_IN_CDB;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+ else\r
+ {\r
+ memcpy(scsiDev.data, StandardResponse, sizeof(StandardResponse));\r
+ scsiDev.dataLen = sizeof(StandardResponse);\r
+ scsiDev.phase = DATA_IN;\r
+ \r
+ if (!lun) scsiDev.unitAttention = 0;\r
+ }\r
+ }\r
+ else if (pageCode == 0x00)\r
+ {\r
+ memcpy(scsiDev.data, SupportedVitalPages, sizeof(SupportedVitalPages));\r
+ scsiDev.dataLen = sizeof(SupportedVitalPages);\r
+ scsiDev.phase = DATA_IN;\r
+ }\r
+ else if (pageCode == 0x80)\r
+ {\r
+ memcpy(scsiDev.data, UnitSerialNumber, sizeof(UnitSerialNumber));\r
+ scsiDev.dataLen = sizeof(UnitSerialNumber);\r
+ scsiDev.phase = DATA_IN;\r
+ }\r
+ else if (pageCode == 0x81)\r
+ {\r
+ memcpy(\r
+ scsiDev.data,\r
+ ImpOperatingDefinition,\r
+ sizeof(ImpOperatingDefinition));\r
+ scsiDev.dataLen = sizeof(ImpOperatingDefinition);\r
+ scsiDev.phase = DATA_IN;\r
+ }\r
+ else if (pageCode == 0x82)\r
+ {\r
+ memcpy(\r
+ scsiDev.data,\r
+ AscImpOperatingDefinition,\r
+ sizeof(AscImpOperatingDefinition));\r
+ scsiDev.dataLen = sizeof(AscImpOperatingDefinition);\r
+ scsiDev.phase = DATA_IN;\r
+ }\r
+ else\r
+ {\r
+ // error.\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.sense.asc = INVALID_FIELD_IN_CDB;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+\r
+\r
+ if (scsiDev.phase == DATA_IN && scsiDev.dataLen > allocationLength)\r
+ {\r
+ // Spec 8.2.5 requires us to simply truncate the response.\r
+ scsiDev.dataLen = allocationLength;\r
+ }\r
+\r
+\r
+ // Set the first byte to indicate LUN presence.\r
+ if (lun) // We only support lun 0\r
+ {\r
+ scsiDev.data[0] = 0x7F;\r
+ }\r
+}\r
+\r
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+#ifndef INQUIRY_H
+#define INQUIRY_H
+
+void scsiInquiry();
+
+#endif
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+#ifndef LED_H
+#define LED_H
+
+#include "device.h"
+
+#define ledOn() LED1_Write(0)
+#define ledOff() LED1_Write(1)
+
+#endif
\ No newline at end of file
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//\r
+// This file is part of SCSI2SD.\r
+//\r
+// SCSI2SD is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License, or\r
+// (at your option) any later version.\r
+//\r
+// SCSI2SD is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
+\r
+#include "loopback.h"\r
+#include "device.h"\r
+\r
+// Return true if all inputs are un-asserted (1)\r
+// Note that CyPins returns non-zero if pin is active. It does NOT\r
+// necessarily return 1.\r
+static int test_initial_inputs(void)\r
+{\r
+ uint8 dbx = SCSI_In_DBx_Read();\r
+ int result =\r
+ (dbx == 0xFF) &&\r
+ CyPins_ReadPin(SCSI_In_DBP) &&\r
+ CyPins_ReadPin(SCSI_In_ATN) &&\r
+ CyPins_ReadPin(SCSI_In_BSY) &&\r
+ CyPins_ReadPin(SCSI_In_ACK) &&\r
+ CyPins_ReadPin(SCSI_In_RST) &&\r
+ CyPins_ReadPin(SCSI_In_MSG) &&\r
+ CyPins_ReadPin(SCSI_In_SEL) &&\r
+ CyPins_ReadPin(SCSI_In_CD) &&\r
+ CyPins_ReadPin(SCSI_In_REQ) &&\r
+ CyPins_ReadPin(SCSI_In_IO);\r
+\r
+ return result;\r
+}\r
+\r
+static int test_data_lines(void)\r
+{\r
+ int result = 1;\r
+ int i;\r
+ for (i = 0; i < 8; ++i)\r
+ {\r
+ // We write using Active High\r
+ SCSI_Out_DBx_Write(1 << i);\r
+ CyDelay(1); // ms\r
+ \r
+ // And expect an Active Low response.\r
+ uint8 dbx = SCSI_In_DBx_Read();\r
+ result = result && (dbx == (0xFF ^ (1 << i)));\r
+ }\r
+ SCSI_Out_DBx_Write(0);\r
+ return result;\r
+}\r
+\r
+static int test_data_10MHz(void)\r
+{\r
+ // 10MHz = 100ns period.\r
+ // We'll try and go high -> low -> high in 100ns.\r
+ // At 66MHz, 50ns ~= 3 cycles.\r
+ \r
+ int result = 1;\r
+ int i;\r
+ for (i = 0; i < 100; ++i)\r
+ {\r
+ // We write using Active High\r
+ SCSI_Out_DBx_Write(0xFF);\r
+ CyDelayCycles(3);\r
+ // And expect an Active Low response.\r
+ uint8 dbx = SCSI_In_DBx_Read();\r
+ result = result && (dbx == 0);\r
+ \r
+ // We write using Active High\r
+ SCSI_Out_DBx_Write(0);\r
+ CyDelayCycles(3);\r
+ // And expect an Active Low response.\r
+ dbx = SCSI_In_DBx_Read();\r
+ result = result && (dbx == 0xFF);\r
+ }\r
+ SCSI_Out_DBx_Write(0);\r
+ return result;\r
+}\r
+\r
+static void test_error(void)\r
+{\r
+ // Toggle LED.\r
+ while (1)\r
+ {\r
+ LED1_Write(0);\r
+ CyDelay(250); // ms\r
+ LED1_Write(1);\r
+ CyDelay(250); // ms\r
+ }\r
+}\r
+\r
+static void test_success(void)\r
+{\r
+ // Toggle LED.\r
+ while (1)\r
+ {\r
+ LED1_Write(0);\r
+ CyDelay(1000); // ms\r
+ LED1_Write(1);\r
+ CyDelay(1000); // ms\r
+ }\r
+}\r
+void scsi2sd_test_loopback(void)\r
+{\r
+ if (!test_initial_inputs() || !test_data_lines() || !test_data_10MHz())\r
+ {\r
+ test_error();\r
+ }\r
+ else\r
+ {\r
+ test_success();\r
+ }\r
+}
\ No newline at end of file
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//\r
+// This file is part of SCSI2SD.\r
+//\r
+// SCSI2SD is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License, or\r
+// (at your option) any later version.\r
+//\r
+// SCSI2SD is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
+\r
+#ifndef SCSI2SD_LOOPBACK_H\r
+#define SCSI2SD_LOOPBACK_H\r
+\r
+// Loopback test\r
+// Ensure we can read-back whatever we write to the SCSI bus.\r
+// This testing should be performed in isolation, with the\r
+// terminator jumper and terminator power jumper installed.\r
+// ie. do not connect a SCSI cable and plug us in to another\r
+// device.\r
+void scsi2sd_test_loopback(void);\r
+\r
+\r
+#endif // SCSI2SD_POST_H\r
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//\r
+// This file is part of SCSI2SD.\r
+//\r
+// SCSI2SD is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License, or\r
+// (at your option) any later version.\r
+//\r
+// SCSI2SD is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
+\r
+#include "device.h"\r
+// #include "blinky.h"\r
+// #include "loopback.h"\r
+#include "scsi.h"\r
+#include "disk.h"\r
+#include "led.h"\r
+\r
+const char* Notice = "Copyright (C) 2013 Michael McMaster <michael@codesrc.com>";\r
+\r
+void main()\r
+{\r
+ // scsi2sd_test_blinky(); // Initial test. Will not return.\r
+ // scsi2sd_test_loopback(); // Second test. Will not return.\r
+ ledOff();\r
+\r
+ /* Uncomment this line to enable global interrupts. */\r
+ // MM: Try to avoid interrupts completely, as it will screw with our\r
+ // timing.\r
+ CyGlobalIntEnable;\r
+ \r
+ // TODO insert any initialisation code here.\r
+ scsiInit(0, 1); // ID 0 is mac boot disk\r
+ scsiDiskInit();\r
+\r
+ // Reading jumpers\r
+ // Is SD card detect asserted ?\r
+\r
+ // TODO POST ?\r
+\r
+ while (1)\r
+ {\r
+ scsiPoll();\r
+ scsiDiskPoll();\r
+ }\r
+}\r
+\r
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//\r
+// This file is part of SCSI2SD.\r
+//\r
+// SCSI2SD is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License, or\r
+// (at your option) any later version.\r
+//\r
+// SCSI2SD is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
+\r
+#include "device.h"\r
+#include "scsi.h"\r
+#include "mode.h"\r
+#include "disk.h"\r
+\r
+#include <string.h>\r
+\r
+static const uint8 DisconnectReconnectPage[] =\r
+{\r
+0x02, // Page code\r
+0x0E, // Page length\r
+0, // Buffer full ratio\r
+0, // Buffer empty ratio\r
+0x00, 10, // Bus inactivity limit, 100us increments. Allow 1ms.\r
+0x00, 0x00, // Disconnect time limit\r
+0x00, 0x00, // Connect time limit\r
+0x00, 0x00, // Maximum burst size\r
+0x00 ,// DTDC. Not used.\r
+0x00, 0x00, 0x00 // Reserved\r
+};\r
+\r
+static const uint8 FormatDevicePage[] =\r
+{\r
+x03, // Page code \r
+0x16, // Page length\r
+0x00, 0x00, // Single zone\r
+0x00, 0x00, // No alternate sectors\r
+0x00, 0x00, // No alternate tracks\r
+0x00, 0x00, // No alternate tracks per lun\r
+0x00, SCSI_SECTORS_PER_TRACK, // Sectors per track\r
+SCSI_SECTOR_SIZE >> 8, SCSI_SECTOR_SIZE & 0xFF, // Data bytes per physical sector\r
+0x00, 0x01, // Interleave\r
+0x00, 0x00, // Track skew factor\r
+0x00, 0x00, // Cylinder skew factor\r
+0xC0, // SSEC(set) HSEC(set) RMB SURF\r
+0x00, 0x00, 0x00 // Reserved\r
+};\r
+\r
+static const uint8 RigidDiskDriveGeometry[] =\r
+{\r
+0x04, // Page code\r
+0x16, // Page length\r
+0xFF, 0xFF, 0xFF, // Number of cylinders\r
+SCSI_HEADS_PER_CYLINDER, // Number of heads\r
+0xFF, 0xFF, 0xFF, // Starting cylinder-write precompensation\r
+0xFF, 0xFF, 0xFF, // Starting cylinder-reduced write current\r
+0x00, 0x1, // Drive step rate (units of 100ns)\r
+0x00, 0x00, 0x00, // Landing zone cylinder\r
+0x00, // RPL\r
+0x00, // Rotational offset\r
+0x00, // Reserved\r
+5400 >> 8, 5400 & 0xFF, // Medium rotation rate (RPM)\r
+0x00, 0x00 // Reserved\r
+};\r
+\r
+static const uint8 CachingPage[] =\r
+{\r
+0x08, // Page Code\r
+0x0A, // Page length\r
+0x01, // Read cache disable\r
+0x00, // No useful rention policy.\r
+0x00, 0x00, // Pre-fetch always disabled\r
+0x00, 0x00, // Minimum pre-fetch\r
+0x00, 0x00, // Maximum pre-fetch\r
+0x00, 0x00, // Maximum pre-fetch ceiling\r
+};\r
+\r
+static const uint8 ControlModePage[] =\r
+{\r
+0x0A, // Page code\r
+0x06, // Page length\r
+0x00, // No logging\r
+0x01, // Disable tagged queuing\r
+0x00, // No async event notifications\r
+0x00, // Reserved\r
+0x00, 0x00 // AEN holdoff period.\r
+};\r
+\r
+static void pageIn(int pc, int dataIdx, const uint8* pageData, int pageLen)\r
+{\r
+ memcpy(&scsiDev.data[dataIdx], pageData, pageLen);\r
+\r
+ if (pc == 0x01) // Mask out (un)changable values\r
+ {\r
+ memset(&scsiDev.data[dataIdx+2], 0, pageLen - 2);\r
+ }\r
+}\r
+\r
+static void doModeSense(\r
+ int sixByteCmd, int dbd, int pc, int pageCode, int allocLength)\r
+{\r
+ // TODO Apple HD SC Drive Setup requests Page 3 (FormatDevicePage) with an\r
+ // allocLength of 0x20. We need 0x24 if we include a block descriptor, and\r
+ // thus return CHECK CONDITION. A block descriptor is optional, so we\r
+ // chose to ignore it.\r
+ // TODO make configurable\r
+ dbd = 1;\r
+ \r
+ if (pc == 0x03) // Saved Values not supported.\r
+ {\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.sense.asc = SAVING_PARAMETERS_NOT_SUPPORTED;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+ else\r
+ {\r
+ ////////////// Mode Parameter Header\r
+ ////////////////////////////////////\r
+\r
+ // Skip the Mode Data Length, we set that last.\r
+ int idx = 1;\r
+ if (!sixByteCmd) ++idx;\r
+\r
+ scsiDev.data[idx++] = 0; // Medium type. 0 = default\r
+\r
+ // Device-specific parameter. Contains cache bits (0) and\r
+ // a Write-Protect bit.\r
+ scsiDev.data[idx++] = (blockDev.state & DISK_WP) ? 0x80 : 0;\r
+\r
+ if (sixByteCmd)\r
+ {\r
+ if (dbd)\r
+ {\r
+ scsiDev.data[idx++] = 0; // No block descriptor\r
+ }\r
+ else\r
+ {\r
+ // One block descriptor of length 8 bytes.\r
+ scsiDev.data[idx++] = 8;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ scsiDev.data[idx++] = 0; // Reserved\r
+ scsiDev.data[idx++] = 0; // Reserved\r
+ if (dbd)\r
+ {\r
+ scsiDev.data[idx++] = 0; // No block descriptor\r
+ scsiDev.data[idx++] = 0; // No block descriptor\r
+ }\r
+ else\r
+ {\r
+ // One block descriptor of length 8 bytes.\r
+ scsiDev.data[idx++] = 0;\r
+ scsiDev.data[idx++] = 8;\r
+ }\r
+ }\r
+\r
+ ////////////// Block Descriptor\r
+ ////////////////////////////////////\r
+ if (!dbd)\r
+ {\r
+ scsiDev.data[idx++] = 0; // Density code. Reserved for direct-access\r
+ // Number of blocks\r
+ // Zero == all remaining blocks shall have the medium\r
+ // characteristics specified.\r
+ scsiDev.data[idx++] = 0;\r
+ scsiDev.data[idx++] = 0;\r
+ scsiDev.data[idx++] = 0;\r
+\r
+ scsiDev.data[idx++] = 0; // reserved\r
+\r
+ // Block length\r
+ scsiDev.data[idx++] = SCSI_BLOCK_SIZE >> 16;\r
+ scsiDev.data[idx++] = SCSI_BLOCK_SIZE >> 8;\r
+ scsiDev.data[idx++] = SCSI_BLOCK_SIZE & 0xFF;\r
+ }\r
+\r
+ int pageFound = 1;\r
+\r
+ switch (pageCode)\r
+ {\r
+ case 0x3F:\r
+ // EVERYTHING\r
+\r
+ case 0x02:\r
+ pageIn(pc, idx, DisconnectReconnectPage, sizeof(DisconnectReconnectPage));\r
+ idx += sizeof(DisconnectReconnectPage);\r
+ if (pageCode != 0x3f) break;\r
+\r
+ case 0x03:\r
+ pageIn(pc, idx, FormatDevicePage, sizeof(FormatDevicePage));\r
+ idx += sizeof(FormatDevicePage);\r
+ if (pageCode != 0x3f) break;\r
+\r
+ case 0x04:\r
+ {\r
+ pageIn(pc, idx, RigidDiskDriveGeometry, sizeof(RigidDiskDriveGeometry));\r
+\r
+ if (pc != 0x01)\r
+ {\r
+ // Need to fill out the number of cylinders.\r
+ uint32 cyl;\r
+ uint8 head;\r
+ uint32 sector;\r
+ LBA2CHS(blockDev.capacity, &cyl, &head, §or);\r
+\r
+ scsiDev.data[idx+2] = cyl >> 16;\r
+ scsiDev.data[idx+3] = cyl >> 8;\r
+ scsiDev.data[idx+4] = cyl;\r
+\r
+ memcpy(&scsiDev.data[idx+6], &scsiDev.data[idx+2], 3);\r
+ memcpy(&scsiDev.data[idx+9], &scsiDev.data[idx+2], 3);\r
+ }\r
+\r
+ idx += sizeof(RigidDiskDriveGeometry);\r
+ if (pageCode != 0x3f) break;\r
+ }\r
+\r
+ case 0x08:\r
+ pageIn(pc, idx, CachingPage, sizeof(CachingPage));\r
+ idx += sizeof(CachingPage);\r
+ if (pageCode != 0x3f) break;\r
+\r
+ case 0x0A:\r
+ pageIn(pc, idx, ControlModePage, sizeof(ControlModePage));\r
+ idx += sizeof(ControlModePage);\r
+ break;\r
+\r
+ default:\r
+ // Unknown Page Code\r
+ pageFound = 0;\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.sense.asc = INVALID_FIELD_IN_CDB;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+\r
+\r
+ if (idx > allocLength)\r
+ {\r
+ // Initiator may not have space to receive results.\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.sense.asc = INVALID_FIELD_IN_CDB;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+ else if (pageFound)\r
+ {\r
+ // Go back and fill out the mode data length\r
+ if (sixByteCmd)\r
+ {\r
+ // Cannot currently exceed limits. yay\r
+ scsiDev.data[0] = idx - 1;\r
+ }\r
+ else\r
+ {\r
+ scsiDev.data[0] = ((idx - 2) >> 8);\r
+ scsiDev.data[1] = (idx - 2);\r
+ }\r
+\r
+ scsiDev.dataLen = idx;\r
+ scsiDev.phase = DATA_IN;\r
+ }\r
+ else\r
+ {\r
+ // Initiator may not have space to receive results.\r
+ scsiDev.status = CHECK_CONDITION;\r
+ scsiDev.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.sense.asc = INVALID_FIELD_IN_CDB;\r
+ scsiDev.phase = STATUS;\r
+ }\r
+ }\r
+}\r
+\r
+int scsiModeCommand()\r
+{\r
+ int commandHandled = 1;\r
+\r
+ uint8 command = scsiDev.cdb[0];\r
+\r
+ // We don't currently support the setting of any parameters.\r
+ // (ie. no MODE SELECT(6) or MODE SELECT(10) commands)\r
+\r
+ if (command == 0x1A)\r
+ {\r
+ // MODE SENSE(6)\r
+ int dbd = scsiDev.cdb[1] & 0x08; // Disable block descriptors\r
+ int pc = scsiDev.cdb[2] >> 6; // Page Control\r
+ int pageCode = scsiDev.cdb[2] & 0x3F;\r
+ int allocLength = scsiDev.cdb[4];\r
+ if (allocLength == 0) allocLength = 256;\r
+ doModeSense(1, dbd, pc, pageCode, allocLength);\r
+ }\r
+ else if (command == 0x5A)\r
+ {\r
+ // MODE SENSE(10)\r
+ int dbd = scsiDev.cdb[1] & 0x08; // Disable block descriptors\r
+ int pc = scsiDev.cdb[2] >> 6; // Page Control\r
+ int pageCode = scsiDev.cdb[2] & 0x3F;\r
+ int allocLength =\r
+ (((uint16) scsiDev.cdb[7]) << 8) +\r
+ scsiDev.cdb[8];\r
+ doModeSense(0, dbd, pc, pageCode, allocLength);\r
+ }\r
+ else\r
+ {\r
+ commandHandled = 0;\r
+ }\r
+\r
+ return commandHandled;\r
+}\r
+\r
+\r
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+#ifndef MODE_H
+#define MODE_H
+
+int scsiModeCommand();
+
+#endif
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//\r
+// This file is part of SCSI2SD.\r
+//\r
+// SCSI2SD is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License, or\r
+// (at your option) any later version.\r
+//\r
+// SCSI2SD is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
+\r
+#include "device.h"\r
+#include "scsi.h"\r
+#include "scsiPhy.h"\r
+#include "bits.h"\r
+#include "diagnostic.h"\r
+#include "disk.h"\r
+#include "inquiry.h"\r
+#include "led.h"\r
+#include "mode.h"\r
+#include "disk.h"\r
+\r
+#include <string.h>\r
+\r
+// Global SCSI device state.\r
+ScsiDevice scsiDev;\r
+\r
+static void enter_SelectionPhase();\r
+static void process_SelectionPhase();\r
+static void enter_BusFree();\r
+static void enter_MessageIn(uint8 message);\r
+static void process_MessageIn();\r
+static void enter_Status(uint8 status);\r
+static void process_Status();\r
+static void enter_DataIn(int len);\r
+static void process_DataIn();\r
+static void process_DataOut();\r
+static void process_Command();\r
+\r
+static void doReserveRelease();\r
+\r
+static void enter_BusFree()\r
+{\r
+ scsiEnterPhase(BUS_FREE);\r
+\r
+ ledOff();\r
+\r
+ scsiDev.phase = BUS_FREE;\r
+ SCSI_ClearPin(SCSI_Out_BSY);\r
+}\r
+\r
+static void enter_MessageIn(uint8 message)\r
+{\r
+ scsiDev.msgIn = message;\r
+ scsiDev.phase = MESSAGE_IN;\r
+}\r
+\r
+static void process_MessageIn()\r
+{\r
+ scsiEnterPhase(MESSAGE_IN);\r
+ scsiWrite(scsiDev.msgIn);\r
+\r
+ scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);\r
+\r
+\r
+ if (scsiDev.atnFlag)\r
+ {\r
+ // If there was a parity error, we go\r
+ // back to MESSAGE_OUT first, get out parity error message, then come\r
+ // back here.\r
+ }\r
+ else if (scsiDev.msgIn == MSG_COMMAND_COMPLETE)\r
+ {\r
+ enter_BusFree();\r
+ }\r
+ else\r
+ {\r
+ // MESSAGE_REJECT. Go back to command phase\r
+ scsiDev.phase = COMMAND;\r
+ }\r
+}\r
+\r
+static void enter_Status(uint8 status)\r
+{\r
+ scsiDev.status = status;\r
+ scsiDev.phase = STATUS;\r
+}\r
+\r
+static void process_Status()\r
+{\r
+ scsiEnterPhase(STATUS);\r
+ scsiWrite(scsiDev.status);\r
+\r
+ // Command Complete occurs AFTER a valid status has been\r
+ // sent. then we go bus-free.\r
+ enter_MessageIn(MSG_COMMAND_COMPLETE);\r
+}\r
+\r
+static void enter_DataIn(int len)\r
+{\r
+ scsiDev.dataLen = len;\r
+ scsiDev.phase = DATA_IN;\r
+}\r
+\r
+static void process_DataIn()\r
+{\r
+ if (scsiDev.dataLen > sizeof(scsiDev.data))\r
+ {\r
+ scsiDev.dataLen = sizeof(scsiDev.data);\r
+ }\r
+\r
+ scsiEnterPhase(DATA_IN);\r
+ while ((scsiDev.dataPtr < scsiDev.dataLen) &&\r
+ !scsiDev.resetFlag &&\r
+ !scsiDev.atnFlag)\r
+ {\r
+ scsiWrite(scsiDev.data[scsiDev.dataPtr]);\r
+ ++scsiDev.dataPtr;\r
+\r
+ // scsiWrite will update resetFlag.\r
+ scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);\r
+ }\r
+\r
+ if ((scsiDev.dataPtr >= scsiDev.dataLen) &&\r
+ (transfer.currentBlock == transfer.blocks))\r
+ {\r
+ enter_Status(GOOD);\r
+ }\r
+}\r
+\r
+static void process_DataOut()\r
+{\r
+ if (scsiDev.dataLen > sizeof(scsiDev.data))\r
+ {\r
+ scsiDev.dataLen = sizeof(scsiDev.data);\r
+ }\r
+\r
+ scsiEnterPhase(DATA_OUT);\r
+ while ((scsiDev.dataPtr < scsiDev.dataLen) &&\r
+ !scsiDev.resetFlag &&\r
+ !scsiDev.atnFlag)\r
+ {\r
+ scsiDev.parityError = 0;\r
+ scsiDev.data[scsiDev.dataPtr] = scsiRead();\r
+\r
+ if (scsiDev.parityError)\r
+ {\r
+ scsiDev.sense.code = ABORTED_COMMAND;\r
+ scsiDev.sense.asc = SCSI_PARITY_ERROR;\r
+ enter_Status(CHECK_CONDITION);\r
+ break;\r
+ }\r
+ ++scsiDev.dataPtr;\r
+\r
+ // scsiRead will update resetFlag.\r
+ scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);\r
+ }\r
+\r
+ if ((scsiDev.dataPtr >= scsiDev.dataLen) &&\r
+ (transfer.currentBlock == transfer.blocks))\r
+ {\r
+ enter_Status(GOOD);\r
+ }\r
+}\r
+\r
+static const uint8 CmdGroupBytes[8] = {6, 10, 10, 6, 6, 12, 6, 6};\r
+static void process_Command()\r
+{\r
+ scsiEnterPhase(COMMAND);\r
+ scsiDev.parityError = 0;\r
+\r
+ memset(scsiDev.cdb, 0, sizeof(scsiDev.cdb));\r
+ scsiDev.cdb[0] = scsiRead();\r
+\r
+ int group = scsiDev.cdb[0] >> 5;\r
+ int cmdSize = CmdGroupBytes[group];\r
+ int i;\r
+ for (i = 1; i < cmdSize; ++i)\r
+ {\r
+ scsiDev.cdb[i] = scsiRead();\r
+ }\r
+\r
+ uint8 command = scsiDev.cdb[0];\r
+ uint8 lun = scsiDev.cdb[1] >> 5;\r
+\r
+ if (scsiDev.parityError)\r
+ {\r
+ scsiDev.sense.code = ABORTED_COMMAND;\r
+ scsiDev.sense.asc = SCSI_PARITY_ERROR;\r
+ enter_Status(CHECK_CONDITION);\r
+ }\r
+ else if (command == 0x12)\r
+ {\r
+ scsiInquiry();\r
+ }\r
+ else if (command == 0x03)\r
+ {\r
+ // REQUEST SENSE\r
+ uint32 allocLength = scsiDev.cdb[4];\r
+ if (allocLength == 0) allocLength = 256;\r
+ memset(scsiDev.data, 0, 18);\r
+ scsiDev.data[0] = 0xF0;\r
+ scsiDev.data[2] = scsiDev.sense.code & 0x0F;\r
+\r
+ // TODO populate "information" field with requested LBA.\r
+ // TODO support more detailed sense data ?\r
+\r
+ scsiDev.data[12] = scsiDev.sense.asc >> 8;\r
+ scsiDev.data[13] = scsiDev.sense.asc;\r
+\r
+ // Silently truncate results. SCSI-2 spec 8.2.14.\r
+ enter_DataIn(allocLength < 18 ? allocLength : 18);\r
+\r
+ // This is a good time to clear out old sense information.\r
+ scsiDev.sense.code = NO_SENSE;\r
+ scsiDev.sense.asc = NO_ADDITIONAL_SENSE_INFORMATION;\r
+ }\r
+ // Some old SCSI drivers do NOT properly support\r
+ // unitAttention. OTOH, Linux seems to require it\r
+ // TODO MAKE CONFIGURABLE.\r
+ /* confirmed LCIII with unknown scsi driver fials here.\r
+ else if (scsiDev.unitAttention)\r
+ {\r
+ scsiDev.sense.code = UNIT_ATTENTION;\r
+ scsiDev.sense.asc = scsiDev.unitAttention;\r
+ enter_Status(CHECK_CONDITION);\r
+ }*/\r
+ else if (lun)\r
+ {\r
+ scsiDev.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.sense.asc = LOGICAL_UNIT_NOT_SUPPORTED;\r
+ enter_Status(CHECK_CONDITION);\r
+ }\r
+ else if (command == 0x17 || command == 0x16)\r
+ {\r
+ doReserveRelease();\r
+ }\r
+ else if ((scsiDev.reservedId >= 0) &&\r
+ (scsiDev.reservedId != scsiDev.initiatorId))\r
+ {\r
+ enter_Status(CONFLICT);\r
+ }\r
+ else if (command == 0x1C)\r
+ {\r
+ scsiReceiveDiagnostic();\r
+ }\r
+ else if (command == 0x1D)\r
+ {\r
+ scsiSendDiagnostic();\r
+ }\r
+ else if (\r
+ !scsiModeCommand() &&\r
+ !scsiDiskCommand())\r
+ {\r
+ scsiDev.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.sense.asc = INVALID_COMMAND_OPERATION_CODE;\r
+ enter_Status(CHECK_CONDITION);\r
+ }\r
+\r
+ // Successful\r
+ if (scsiDev.phase == COMMAND) // No status set, and not in DATA_IN\r
+ {\r
+ enter_Status(GOOD);\r
+ }\r
+\r
+ scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);\r
+}\r
+\r
+static void doReserveRelease()\r
+{\r
+ int extentReservation = scsiDev.cdb[1] & 1;\r
+ int thirdPty = scsiDev.cdb[1] & 0x10;\r
+ int thirdPtyId = (scsiDev.cdb[1] >> 1) & 0x7;\r
+ uint8 command = scsiDev.cdb[0];\r
+\r
+ int canRelease =\r
+ (!thirdPty && (scsiDev.initiatorId == scsiDev.reservedId)) ||\r
+ (thirdPty &&\r
+ (scsiDev.reserverId == scsiDev.initiatorId) &&\r
+ (scsiDev.reservedId == thirdPtyId)\r
+ );\r
+\r
+ if (extentReservation)\r
+ {\r
+ // Not supported.\r
+ scsiDev.sense.code = ILLEGAL_REQUEST;\r
+ scsiDev.sense.asc = INVALID_FIELD_IN_CDB;\r
+ enter_Status(CHECK_CONDITION);\r
+ }\r
+ else if (command == 0x17) // release\r
+ {\r
+ if ((scsiDev.reservedId < 0) || canRelease)\r
+ {\r
+ scsiDev.reservedId = -1;\r
+ scsiDev.reserverId = -1;\r
+ }\r
+ else\r
+ {\r
+ enter_Status(CONFLICT);\r
+ }\r
+ }\r
+ else // assume reserve.\r
+ {\r
+ if ((scsiDev.reservedId < 0) || canRelease)\r
+ {\r
+ scsiDev.reserverId = scsiDev.initiatorId;\r
+ if (thirdPty)\r
+ {\r
+ scsiDev.reservedId = thirdPtyId;\r
+ }\r
+ else\r
+ {\r
+ scsiDev.reservedId = scsiDev.initiatorId;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ // Already reserved by someone else!\r
+ enter_Status(CONFLICT);\r
+ }\r
+ }\r
+}\r
+\r
+static void scsiReset()\r
+{\r
+ ledOff();\r
+ SCSI_Out_DBx_Write(0);\r
+ SCSI_ClearPin(SCSI_Out_DBP);\r
+ SCSI_ClearPin(SCSI_Out_ATN);\r
+ SCSI_ClearPin(SCSI_Out_BSY);\r
+ SCSI_ClearPin(SCSI_Out_ACK);\r
+ SCSI_ClearPin(SCSI_Out_RST);\r
+ SCSI_ClearPin(SCSI_Out_SEL);\r
+ SCSI_ClearPin(SCSI_Out_REQ);\r
+ SCSI_ClearPin(SCSI_Out_MSG);\r
+ SCSI_ClearPin(SCSI_Out_CD);\r
+ SCSI_ClearPin(SCSI_Out_IO);\r
+\r
+ scsiDev.resetFlag = 0;\r
+ scsiDev.atnFlag = 0;\r
+ scsiDev.parityError = 0;\r
+ scsiDev.phase = BUS_FREE;\r
+ \r
+ if (scsiDev.unitAttention != POWER_ON_RESET)\r
+ {\r
+ scsiDev.unitAttention = SCSI_BUS_RESET;\r
+ }\r
+ scsiDev.reservedId = -1;\r
+ scsiDev.reserverId = -1;\r
+ scsiDev.sense.code = NO_SENSE;\r
+ scsiDev.sense.asc = NO_ADDITIONAL_SENSE_INFORMATION;\r
+ scsiDiskReset();\r
+\r
+ // Sleep to allow the bus to settle down a bit.\r
+ // We must be ready again within the "Reset to selection time" of\r
+ // 250ms.\r
+ // There is no guarantee that the RST line will be negated by then.\r
+ int reset;\r
+ do\r
+ {\r
+ CyDelay(10); // 10ms.\r
+ reset = SCSI_ReadPin(SCSI_In_RST);\r
+ } while (reset);\r
+}\r
+\r
+static void enter_SelectionPhase()\r
+{\r
+\r
+ scsiDev.atnFlag = 0;\r
+ scsiDev.parityError = 0;\r
+ scsiDev.dataPtr = 0;\r
+ scsiDev.savedDataPtr = 0;\r
+ scsiDev.status = GOOD;\r
+ scsiDev.phase = SELECTION;\r
+}\r
+\r
+static void process_SelectionPhase()\r
+{\r
+ uint8 mask = ~SCSI_In_DBx_Read();\r
+ int goodParity = (Lookup_OddParity[mask] == SCSI_ReadPin(SCSI_In_DBP));\r
+\r
+ scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);\r
+ int sel = SCSI_ReadPin(SCSI_In_SEL);\r
+ int bsy = SCSI_ReadPin(SCSI_In_BSY);\r
+ if (!bsy && sel &&\r
+ (mask & scsiDev.scsiIdMask) &&\r
+ goodParity && (countBits(mask) == 2))\r
+ {\r
+ // We've been selected!\r
+ // Assert BSY - Selection success!\r
+ // must happen within 200us (Selection abort time) of seeing our\r
+ // ID + SEL.\r
+ // (Note: the initiator will be waiting the "Selection time-out delay"\r
+ // for our BSY response, which is actually a very generous 250ms)\r
+ SCSI_SetPin(SCSI_Out_BSY);\r
+ ledOn();\r
+\r
+ // Wait until the end of the selection phase.\r
+ // Keep checking the ATN flag, as the initiator may assert it at any\r
+ // time before releasing SEL.\r
+ while (!scsiDev.resetFlag)\r
+ {\r
+ scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);\r
+ if (!SCSI_ReadPin(SCSI_In_SEL))\r
+ {\r
+ break;\r
+ }\r
+ scsiDev.resetFlag = SCSI_ReadPin(SCSI_In_RST);\r
+ }\r
+\r
+ // Save our initiator now that we're no longer in a time-critical\r
+ // section.\r
+ uint8 initiatorMask = mask ^ scsiDev.scsiIdMask;\r
+ scsiDev.initiatorId = 0;\r
+ int i;\r
+ for (i = 0; i < 8; ++i)\r
+ {\r
+ if (initiatorMask & (1 << i))\r
+ {\r
+ scsiDev.initiatorId = i;\r
+ break;\r
+ }\r
+ }\r
+\r
+ scsiDev.phase = COMMAND;\r
+ }\r
+ else if (!sel)\r
+ {\r
+ scsiDev.phase = BUS_BUSY;\r
+ }\r
+\r
+ scsiDev.resetFlag = scsiDev.resetFlag || SCSI_ReadPin(SCSI_In_RST);\r
+}\r
+\r
+static void process_MessageOut()\r
+{\r
+ scsiDev.atnFlag = 0;\r
+ scsiEnterPhase(MESSAGE_OUT);\r
+\r
+ scsiDev.parityError = 0;\r
+ scsiDev.msgOut = scsiRead();\r
+\r
+ if (scsiDev.parityError)\r
+ {\r
+ // Skip the remaining message bytes, and then start the MESSAGE_OUT\r
+ // phase again from the start. The initiator will re-send the\r
+ // same set of messages.\r
+ while (SCSI_ReadPin(SCSI_In_ATN) && !scsiDev.resetFlag)\r
+ {\r
+ scsiRead();\r
+ scsiDev.resetFlag = scsiDev.resetFlag || SCSI_ReadPin(SCSI_In_RST);\r
+ }\r
+\r
+ // Go-back and try the message again.\r
+ scsiDev.atnFlag = 1;\r
+ scsiDev.parityError = 0;\r
+ }\r
+ else if (scsiDev.msgOut == 0x00)\r
+ {\r
+ // COMMAND COMPLETE. but why would the target be receiving this ? nfi.\r
+ enter_BusFree();\r
+ }\r
+ else if (scsiDev.msgOut == 0x06)\r
+ {\r
+ // ABORT\r
+ scsiDiskReset();\r
+ enter_BusFree();\r
+ }\r
+ else if (scsiDev.msgOut == 0x0C)\r
+ {\r
+ // BUS DEVICE RESET\r
+\r
+ scsiDiskReset();\r
+\r
+ scsiDev.unitAttention = SCSI_BUS_RESET;\r
+\r
+ // ANY initiator can reset the reservation state via this message.\r
+ scsiDev.reservedId = -1;\r
+ scsiDev.reserverId = -1;\r
+ enter_BusFree();\r
+ }\r
+ else if (scsiDev.msgOut == 0x05)\r
+ {\r
+ // Initiate Detected Error\r
+ // Ignore for now\r
+ }\r
+ else if (scsiDev.msgOut == 0x0F)\r
+ {\r
+ // INITIATE RECOVERY\r
+ // Ignore for now\r
+ }\r
+ else if (scsiDev.msgOut == 0x10)\r
+ {\r
+ // RELEASE RECOVERY\r
+ // Ignore for now\r
+ enter_BusFree();\r
+ }\r
+ else if (scsiDev.msgOut == MSG_REJECT)\r
+ {\r
+ // Message Reject\r
+ // Oh well.\r
+ scsiDev.resetFlag = 1;\r
+ }\r
+ else if (scsiDev.msgOut == 0x08)\r
+ {\r
+ // NOP\r
+ }\r
+ else if (scsiDev.msgOut == 0x09)\r
+ {\r
+ // Message Parity Error\r
+ // Go back and re-send the last message.\r
+ scsiDev.phase = MESSAGE_IN;\r
+ }\r
+ else if (scsiDev.msgOut & 0x80) // 0x80 -> 0xFF\r
+ {\r
+ // IDENTIFY\r
+ // We don't disconnect, so ignore disconnect privilege.\r
+ if ((scsiDev.msgOut & 0x18) || // Reserved bits set.\r
+ (scsiDev.msgOut & 0x20) || // We don't have any target routines!\r
+ (scsiDev.msgOut & 0x7) // We only support LUN 0!\r
+ )\r
+ {\r
+ enter_MessageIn(MSG_REJECT);\r
+ }\r
+ }\r
+ else if (scsiDev.msgOut >= 0x20 && scsiDev.msgOut <= 0x2F)\r
+ {\r
+ // Two byte message. We don't support these. read and discard.\r
+ scsiRead();\r
+ }\r
+ else if (scsiDev.msgOut == 0x01)\r
+ {\r
+ // Extended message.\r
+ int msgLen = scsiRead();\r
+ if (msgLen == 0) msgLen = 256;\r
+ int i;\r
+ for (i = 0; i < msgLen && !scsiDev.resetFlag; ++i)\r
+ {\r
+ // Discard bytes.\r
+ scsiRead();\r
+ }\r
+\r
+ // We don't support ANY extended messages.\r
+ // Modify Data Pointer: We don't support reselection.\r
+ // Wide Data Transfer Request: No. 8bit only.\r
+ // Synchronous data transfer request. No, we can't do that.\r
+ // We don't support any 2-byte messages either.\r
+ // And we don't support any optional 1-byte messages.\r
+ // In each case, the correct response is MESSAGE REJECT.\r
+ enter_MessageIn(MSG_REJECT);\r
+ }\r
+ else\r
+ {\r
+ enter_MessageIn(MSG_REJECT);\r
+ }\r
+\r
+ // atnFlag will be forced to 1 if there was a parity error.\r
+ scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);\r
+}\r
+\r
+\r
+void scsiPoll(void)\r
+{\r
+ if (scsiDev.resetFlag || SCSI_ReadPin(SCSI_In_RST))\r
+ {\r
+ scsiReset();\r
+ }\r
+\r
+ switch (scsiDev.phase)\r
+ {\r
+ case BUS_FREE:\r
+ if (SCSI_ReadPin(SCSI_In_BSY))\r
+ {\r
+ scsiDev.phase = BUS_BUSY;\r
+ }\r
+ break;\r
+\r
+ case BUS_BUSY:\r
+ // Someone is using the bus. Perhaps they are trying to\r
+ // select us.\r
+ if (SCSI_ReadPin(SCSI_In_SEL))\r
+ {\r
+ enter_SelectionPhase();\r
+ }\r
+ else if (!SCSI_ReadPin(SCSI_In_BSY))\r
+ {\r
+ scsiDev.phase = BUS_FREE;\r
+ }\r
+ break;\r
+\r
+ case ARBITRATION:\r
+ // TODO Support reselection.\r
+ break;\r
+\r
+ case SELECTION:\r
+ process_SelectionPhase();\r
+ break;\r
+\r
+ case RESELECTION:\r
+ // Not currently supported!\r
+ break;\r
+\r
+ case COMMAND:\r
+ if (scsiDev.atnFlag)\r
+ {\r
+ process_MessageOut();\r
+ }\r
+ else\r
+ {\r
+ process_Command();\r
+ }\r
+ break;\r
+\r
+ case DATA_IN:\r
+ if (scsiDev.atnFlag)\r
+ {\r
+ process_MessageOut();\r
+ }\r
+ else\r
+ {\r
+ process_DataIn();\r
+ }\r
+ break;\r
+\r
+ case DATA_OUT:\r
+ if (scsiDev.atnFlag)\r
+ {\r
+ process_MessageOut();\r
+ }\r
+ else\r
+ {\r
+ process_DataOut();\r
+ } \r
+ break;\r
+\r
+ case STATUS:\r
+ if (scsiDev.atnFlag)\r
+ {\r
+ process_MessageOut();\r
+ }\r
+ else\r
+ {\r
+ process_Status();\r
+ }\r
+ break;\r
+\r
+ case MESSAGE_IN:\r
+ if (scsiDev.atnFlag)\r
+ {\r
+ process_MessageOut();\r
+ }\r
+ else\r
+ {\r
+ process_MessageIn();\r
+ }\r
+\r
+ break;\r
+\r
+ case MESSAGE_OUT:\r
+ process_MessageOut();\r
+ break;\r
+ }\r
+}\r
+\r
+void scsiInit(int scsiId, int enableParity)\r
+{\r
+ scsiDev.scsiIdMask = 1 << scsiId;\r
+ scsiDev.enableParity = enableParity;\r
+\r
+ scsiDev.atnFlag = 0;\r
+ scsiDev.resetFlag = 1;\r
+ scsiDev.phase = BUS_FREE;\r
+ scsiDev.reservedId = -1;\r
+ scsiDev.reserverId = -1;\r
+ scsiDev.unitAttention = POWER_ON_RESET;\r
+}\r
+\r
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+#ifndef SCSI_H
+#define SCSI_H
+
+// SCSI documentation goes here
+// SCSI-2.
+// Single LUN
+// No tagged-queuing support - single command at a time.
+// All read/write commands disconnect. State SD card latency.
+// Fixed 512 byte sector size.
+// 2TB limit, based on 32bit LBA (read16/write16 not supported)
+
+#include "geometry.h"
+#include "sense.h"
+
+typedef enum
+{
+ // internal bits
+ __scsiphase_msg = 1,
+ __scsiphase_cd = 2,
+ __scsiphase_io = 4,
+
+ BUS_FREE = -1,
+ BUS_BUSY = -2,
+ ARBITRATION = -3,
+ SELECTION = -4,
+ RESELECTION = -5,
+ STATUS = __scsiphase_cd | __scsiphase_io,
+ COMMAND = __scsiphase_cd,
+ DATA_IN = __scsiphase_io,
+ DATA_OUT = 0,
+ MESSAGE_IN = __scsiphase_msg | __scsiphase_cd | __scsiphase_io,
+ MESSAGE_OUT = __scsiphase_msg | __scsiphase_cd
+} SCSI_PHASE;
+
+typedef enum
+{
+ GOOD = 0,
+ CHECK_CONDITION = 2,
+ BUSY = 0x8,
+ CONFLICT = 0x18
+} SCSI_STATUS;
+
+typedef enum
+{
+ MSG_COMMAND_COMPLETE = 0,
+ MSG_REJECT = 0x7
+
+} SCSI_MESSAGE;
+
+typedef struct
+{
+ uint8_t scsiIdMask;
+ int enableParity;
+
+ // Set to true (1) if the ATN flag was set, and we need to
+ // enter the MESSAGE_OUT phase.
+ int atnFlag;
+
+ // Set to true (1) if the RST flag was set.
+ int resetFlag;
+
+ // Set to true (1) if a parity error was observed.
+ int parityError;
+
+ int phase;
+
+ uint8 data[SCSI_BLOCK_SIZE];
+ int dataPtr; // Index into data, reset on [re]selection to savedDataPtr
+ int savedDataPtr; // Index into data, initially 0.
+ int dataLen;
+
+ uint8 cdb[12]; // command descriptor block
+
+ // Only let the reserved initiator talk to us.
+ // A 3rd party may be sending the RESERVE/RELEASE commands
+ int initiatorId; // 0 -> 7. Set during the selection phase.
+ int reservedId;; // 0 -> 7 if reserved. -1 if not reserved.
+ int reserverId;; // 0 -> 7 if reserved. -1 if not reserved.
+
+ // SCSI_STATUS value.
+ // Change to SCSI_STATUS_CHECK_CONDITION when setting a SENSE value
+ uint8 status;
+
+ ScsiSense sense;
+
+ uint16 unitAttention; // Set to the sense qualifier key to be returned.
+
+ uint8 msgIn;
+ uint8 msgOut;
+} ScsiDevice;
+
+extern ScsiDevice scsiDev;
+
+void scsiInit(int scsiId, int enableParity);
+void scsiPoll(void);
+
+
+#endif
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>\r
+//\r
+// This file is part of SCSI2SD.\r
+//\r
+// SCSI2SD is free software: you can redistribute it and/or modify\r
+// it under the terms of the GNU General Public License as published by\r
+// the Free Software Foundation, either version 3 of the License, or\r
+// (at your option) any later version.\r
+//\r
+// SCSI2SD is distributed in the hope that it will be useful,\r
+// but WITHOUT ANY WARRANTY; without even the implied warranty of\r
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
+// GNU General Public License for more details.\r
+//\r
+// You should have received a copy of the GNU General Public License\r
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.\r
+\r
+#include "device.h"\r
+#include "scsi.h"\r
+#include "scsiPhy.h"\r
+#include "bits.h"\r
+\r
+// Spins until the SCSI pin is true, or the reset flag is set.\r
+static void waitForPinTrue(int pin)\r
+{\r
+ while (!scsiDev.resetFlag)\r
+ {\r
+ // TODO put some hardware gates in front of the RST pin, and store\r
+ // the state in a register. The minimum "Reset hold time" is 25us, which\r
+ // we can easily satisfy within this loop, but perhaps hard to satisfy\r
+ // if we don't call this function often.\r
+ scsiDev.resetFlag = SCSI_ReadPin(SCSI_In_RST);\r
+\r
+ if (SCSI_ReadPin(pin))\r
+ {\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+// Spins until the SCSI pin is true, or the reset flag is set.\r
+static void waitForPinFalse(int pin)\r
+{\r
+ while (!scsiDev.resetFlag)\r
+ {\r
+ // TODO put some hardware gates in front of the RST pin, and store\r
+ // the state in a register. The minimum "Reset hold time" is 25us, which\r
+ // we can easily satisfy within this loop, but perhaps hard to satisfy\r
+ // if we don't call this function often.\r
+ scsiDev.resetFlag = SCSI_ReadPin(SCSI_In_RST);\r
+\r
+ if (!SCSI_ReadPin(pin))\r
+ {\r
+ break;\r
+ }\r
+ }\r
+}\r
+\r
+static void deskewDelay(void)\r
+{\r
+ // Delay for deskew + cable skew. total 55 nanoseconds.\r
+ // Assumes 66MHz.\r
+ CyDelayCycles(4);\r
+}\r
+\r
+uint8 scsiRead(void)\r
+{\r
+ SCSI_SetPin(SCSI_Out_REQ);\r
+ waitForPinTrue(SCSI_In_ACK);\r
+ deskewDelay();\r
+\r
+ uint8 value = ~SCSI_In_DBx_Read();\r
+ scsiDev.parityError = scsiDev.parityError ||\r
+ (Lookup_OddParity[value] != SCSI_ReadPin(SCSI_In_DBP));\r
+\r
+ SCSI_ClearPin(SCSI_Out_REQ);\r
+ waitForPinFalse(SCSI_In_ACK);\r
+ return value;\r
+}\r
+\r
+void scsiWrite(uint8 value)\r
+{\r
+ SCSI_Out_DBx_Write(value);\r
+ if (Lookup_OddParity[value])\r
+ {\r
+ SCSI_SetPin(SCSI_Out_DBP);\r
+ }\r
+ deskewDelay();\r
+\r
+ SCSI_SetPin(SCSI_Out_REQ);\r
+\r
+ // Initiator reads data here.\r
+\r
+ waitForPinTrue(SCSI_In_ACK);\r
+\r
+ SCSI_ClearPin(SCSI_Out_DBP);\r
+ SCSI_Out_DBx_Write(0);\r
+ SCSI_ClearPin(SCSI_Out_REQ);\r
+\r
+ // Wait for ACK to clear.\r
+ waitForPinFalse(SCSI_In_ACK);\r
+}\r
+\r
+static void busSettleDelay(void)\r
+{\r
+ // Data Release time (switching IO) = 400ns\r
+ // + Bus Settle time (switching phase) = 400ns.\r
+ CyDelayUs(1); // Close enough.\r
+}\r
+\r
+void scsiEnterPhase(int phase)\r
+{\r
+ if (phase > 0)\r
+ {\r
+ if (phase & __scsiphase_msg)\r
+ {\r
+ SCSI_SetPin(SCSI_Out_MSG);\r
+ }\r
+ else\r
+ {\r
+ SCSI_ClearPin(SCSI_Out_MSG);\r
+ }\r
+\r
+ if (phase & __scsiphase_cd)\r
+ {\r
+ SCSI_SetPin(SCSI_Out_CD);\r
+ }\r
+ else\r
+ {\r
+ SCSI_ClearPin(SCSI_Out_CD);\r
+ }\r
+\r
+ if (phase & __scsiphase_io)\r
+ {\r
+ SCSI_SetPin(SCSI_Out_IO);\r
+ }\r
+ else\r
+ {\r
+ SCSI_ClearPin(SCSI_Out_IO);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ SCSI_ClearPin(SCSI_Out_MSG);\r
+ SCSI_ClearPin(SCSI_Out_CD);\r
+ SCSI_ClearPin(SCSI_Out_IO);\r
+ }\r
+ busSettleDelay();\r
+}\r
+\r
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+#ifndef SCSIPHY_H
+#define SCSIPHY_H
+
+#define SCSI_SetPin(pin) \
+ CyPins_SetPin((pin));
+
+#define SCSI_ClearPin(pin) \
+ CyPins_ClearPin((pin));
+
+// Active low: we interpret a 0 as "true", and non-zero as "false"
+#define SCSI_ReadPin(pin) \
+ (CyPins_ReadPin((pin)) == 0)
+
+// Contains the odd-parity flag for a given 8-bit value.
+extern const uint8 Lookup_OddParity[256];
+
+uint8 scsiRead(void);
+void scsiWrite(uint8 value);
+
+// Returns true if the ATN flag becomes set, indicating a parity error.
+int scsiWriteMsg(uint8 msg);
+
+void scsiEnterPhase(int phase);
+
+#endif
--- /dev/null
+// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
+//
+// This file is part of SCSI2SD.
+//
+// SCSI2SD is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// SCSI2SD is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
+#ifndef SENSE_H
+#define SENSE_H
+
+typedef enum
+{
+ NO_SENSE = 0,
+ RECOVERED_ERROR = 1,
+ NOT_READY = 2,
+ MEDIUM_ERROR = 3,
+ HARDWARE_ERROR = 4,
+ ILLEGAL_REQUEST = 5,
+ UNIT_ATTENTION = 6,
+ DATA_PROTECT = 7,
+ BLANK_CHECK = 8,
+ VENDOR_SPECIFIC = 9,
+ COPY_ABORTED = 0xA,
+ ABORTED_COMMAND = 0xB,
+ EQUAL = 0xC,
+ VOLUME_OVERFLOW = 0xD,
+ MISCOMPARE = 0xE,
+ RESERVED = 0xF
+} SCSI_SENSE;
+
+// Top 8 bits = ASC. Lower 8 bits = ASCQ.
+// Enum only contains definitions for direct-access related codes.
+typedef enum
+{
+ ADDRESS_MARK_NOT_FOUND_FOR_DATA_FIELD = 0x1300,
+ ADDRESS_MARK_NOT_FOUND_FOR_ID_FIELD = 0x1200,
+ CANNOT_READ_MEDIUM_INCOMPATIBLE_FORMAT = 0x3002,
+ CANNOT_READ_MEDIUM_UNKNOWN_FORMAT = 0x3001,
+ CHANGED_OPERATING_DEFINITION = 0x3F02,
+ COMMAND_PHASE_ERROR = 0x4A00,
+ COMMAND_SEQUENCE_ERROR = 0x2C00,
+ COMMANDS_CLEARED_BY_ANOTHER_INITIATOR = 0x2F00,
+ COPY_CANNOT_EXECUTE_SINCE_HOST_CANNOT_DISCONNECT = 0x2B00,
+ DATA_PATH_FAILURE = 0x4100,
+ DATA_PHASE_ERROR = 0x4B00,
+ DATA_SYNCHRONIZATION_MARK_ERROR = 0x1600,
+ DEFECT_LIST_ERROR = 0x1900,
+ DEFECT_LIST_ERROR_IN_GROWN_LIST = 0x1903,
+ DEFECT_LIST_ERROR_IN_PRIMARY_LIST = 0x1902,
+ DEFECT_LIST_NOT_AVAILABLE = 0x1901,
+ DEFECT_LIST_NOT_FOUND = 0x1C00,
+ DEFECT_LIST_UPDATE_FAILURE = 0x3201,
+ ERROR_LOG_OVERFLOW = 0x0A00,
+ ERROR_TOO_LONG_TO_CORRECT = 0x1102,
+ FORMAT_COMMAND_FAILED = 0x3101,
+ GROWN_DEFECT_LIST_NOT_FOUND = 0x1C02,
+ IO_PROCESS_TERMINATED = 0x0006,
+ ID_CRC_OR_ECC_ERROR = 0x1000,
+ ILLEGAL_FUNCTION = 0x2200,
+ INCOMPATIBLE_MEDIUM_INSTALLED = 0x3000,
+ INITIATOR_DETECTED_ERROR_MESSAGE_RECEIVED = 0x4800,
+ INQUIRY_DATA_HAS_CHANGED = 0x3F03,
+ INTERNAL_TARGET_FAILURE = 0x4400,
+ INVALID_BITS_IN_IDENTIFY_MESSAGE = 0x3D00,
+ INVALID_COMMAND_OPERATION_CODE = 0x2000,
+ INVALID_FIELD_IN_CDB = 0x2400,
+ INVALID_FIELD_IN_PARAMETER_LIST = 0x2600,
+ INVALID_MESSAGE_ERROR = 0x4900,
+ LOG_COUNTER_AT_MAXIMUM = 0x5B02,
+ LOG_EXCEPTION = 0x5B00,
+ LOG_LIST_CODES_EXHAUSTED = 0x5B03,
+ LOG_PARAMETERS_CHANGED = 0x2A02,
+ LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE = 0x2100,
+ LOGICAL_UNIT_COMMUNICATION_FAILURE = 0x0800,
+ LOGICAL_UNIT_COMMUNICATION_PARITY_ERROR = 0x0802,
+ LOGICAL_UNIT_COMMUNICATION_TIMEOUT = 0x0801,
+ LOGICAL_UNIT_DOES_NOT_RESPOND_TO_SELECTION = 0x0500,
+ LOGICAL_UNIT_FAILED_SELF_CONFIGURATION = 0x4C00,
+ LOGICAL_UNIT_HAS_NOT_SELF_CONFIGURED_YET = 0x3E00,
+ LOGICAL_UNIT_IS_IN_PROCESS_OF_BECOMING_READY = 0x0401,
+ LOGICAL_UNIT_NOT_READY_CAUSE_NOT_REPORTABLE = 0x0400,
+ LOGICAL_UNIT_NOT_READY_FORMAT_IN_PROGRESS = 0x0404,
+ LOGICAL_UNIT_NOT_READY_INITIALIZING_COMMAND_REQUIRED = 0x0402,
+ LOGICAL_UNIT_NOT_READY_MANUAL_INTERVENTION_REQUIRED = 0x0403,
+ LOGICAL_UNIT_NOT_SUPPORTED = 0x2500,
+ MECHANICAL_POSITIONING_ERROR = 0x1501,
+ MEDIA_LOAD_OR_EJECT_FAILED = 0x5300,
+ MEDIUM_FORMAT_CORRUPTED = 0x3100,
+ MEDIUM_NOT_PRESENT = 0x3A00,
+ MEDIUM_REMOVAL_PREVENTED = 0x5302,
+ MESSAGE_ERROR = 0x4300,
+ MICROCODE_HAS_BEEN_CHANGED = 0x3F01,
+ MISCOMPARE_DURING_VERIFY_OPERATION = 0x1D00,
+ MISCORRECTED_ERROR = 0x110A,
+ MODE_PARAMETERS_CHANGED = 0x2A01,
+ MULTIPLE_PERIPHERAL_DEVICES_SELECTED = 0x0700,
+ MULTIPLE_READ_ERRORS = 0x1103,
+ NO_ADDITIONAL_SENSE_INFORMATION = 0x0000,
+ NO_DEFECT_SPARE_LOCATION_AVAILABLE = 0x3200,
+ NO_INDEX_SECTOR_SIGNAL = 0x0100,
+ NO_REFERENCE_POSITION_FOUND = 0x0600,
+ NO_SEEK_COMPLETE = 0x0200,
+ NOT_READY_TO_READY_TRANSITION_MEDIUM_MAY_HAVE_CHANGED = 0x2800,
+ OPERATOR_MEDIUM_REMOVAL_REQUEST = 0x5A01,
+ OPERATOR_REQUEST_OR_STATE_CHANGE_INPUT = 0x5A00,
+ OPERATOR_SELECTED_WRITE_PERMIT = 0x5A03,
+ OPERATOR_SELECTED_WRITE_PROTECT = 0x5A02,
+ OVERLAPPED_COMMANDS_ATTEMPTED = 0x4E00,
+ PARAMETER_LIST_LENGTH_ERROR = 0x1A00,
+ PARAMETER_NOT_SUPPORTED = 0x2601,
+ PARAMETER_VALUE_INVALID = 0x2602,
+ PARAMETERS_CHANGED = 0x2A00,
+ PERIPHERAL_DEVICE_WRITE_FAULT = 0x0300,
+ POSITIONING_ERROR_DETECTED_BY_READ_OF_MEDIUM = 0x1502,
+ POWER_ON_RESET_OR_BUS_DEVICE_RESET_OCCURRED = 0x2900,
+ POWER_ON_RESET = 0x2901,
+ POWER_ON_OR_SELF_TEST_FAILURE = 0x4200,
+ PRIMARY_DEFECT_LIST_NOT_FOUND = 0x1C01,
+ RAM_FAILURE = 0x4000,
+ RANDOM_POSITIONING_ERROR = 0x1500,
+ READ_RETRIES_EXHAUSTED = 0x1101,
+ RECORD_NOT_FOUND = 0x1401,
+ RECORDED_ENTITY_NOT_FOUND = 0x1400,
+ RECOVERED_DATA_DATA_AUTO_REALLOCATED = 0x1802,
+ RECOVERED_DATA_RECOMMEND_REASSIGNMENT = 0x1805,
+ RECOVERED_DATA_RECOMMEND_REWRITE = 0x1806,
+ RECOVERED_DATA_USING_PREVIOUS_SECTOR_ID = 0x1705,
+ RECOVERED_DATA_WITH_ERROR_CORRECTION_RETRIES_APPLIED = 0x1801,
+ RECOVERED_DATA_WITH_ERROR_CORRECTION_APPLIED = 0x1800,
+ RECOVERED_DATA_WITH_NEGATIVE_HEAD_OFFSET = 0x1703,
+ RECOVERED_DATA_WITH_NO_ERROR_CORRECTION_APPLIED = 0x1700,
+ RECOVERED_DATA_WITH_POSITIVE_HEAD_OFFSET = 0x1702,
+ RECOVERED_DATA_WITH_RETRIES = 0x1701,
+ RECOVERED_DATA_WITHOUT_ECC_DATA_AUTO_REALLOCATED = 0x1706,
+ RECOVERED_DATA_WITHOUT_ECC_RECOMMEND_REASSIGNMENT = 0x1707,
+ RECOVERED_DATA_WITHOUT_ECC_RECOMMEND_REWRITE = 0x1708,
+ RECOVERED_ID_WITH_ECC_CORRECTION = 0x1E00,
+ ROUNDED_PARAMETER = 0x3700,
+ RPL_STATUS_CHANGE = 0x5C00,
+ SAVING_PARAMETERS_NOT_SUPPORTED = 0x3900,
+ SCSI_BUS_RESET = 0x2902,
+ SCSI_PARITY_ERROR = 0x4700,
+ SELECT_OR_RESELECT_FAILURE = 0x4500,
+ SPINDLES_NOT_SYNCHRONIZED = 0x5C02,
+ SPINDLES_SYNCHRONIZED = 0x5C01,
+ SYNCHRONOUS_DATA_TRANSFER_ERROR = 0x1B00,
+ TARGET_OPERATING_CONDITIONS_HAVE_CHANGED = 0x3F00,
+ THRESHOLD_CONDITION_MET = 0x5B01,
+ THRESHOLD_PARAMETERS_NOT_SUPPORTED = 0x2603,
+ TRACK_FOLLOWING_ERROR = 0x0900,
+ UNRECOVERED_READ_ERROR = 0x1100,
+ UNRECOVERED_READ_ERROR_AUTO_REALLOCATE_FAILED = 0x1104,
+ UNRECOVERED_READ_ERROR_RECOMMEND_REASSIGNMENT = 0x110B,
+ UNRECOVERED_READ_ERROR_RECOMMEND_REWRITE_THE_DATA = 0x110C,
+ UNSUCCESSFUL_SOFT_RESET = 0x4600,
+ WRITE_ERROR_AUTO_REALLOCATION_FAILED = 0x0C02,
+ WRITE_ERROR_RECOVERED_WITH_AUTO_REALLOCATION = 0x0C01,
+ WRITE_PROTECTED = 0x2700
+} SCSI_ASC_ASCQ;
+
+typedef struct
+{
+ uint8 code;
+ uint16 asc;
+} ScsiSense;
+
+#endif
projects / SCSI2SD.git / commitdiff