-201407XX 3.6
+201408XX 3.6
- Fix handling requests for LUNs other than 0 from SCSI-2 hosts.
+ - Handle glitches of the ACK line to improve stability and operate with
+ multiple devices on the SCSI bus.
+ - Re-add parity checking. This can be disabled using scsi2sd-config if
+ required.
20140718 3.5.2
- Fix blank SCSI ID in scsi2sd-config output.
-- Parity checking not implemented for the PSoC Datapath implementation
+- Everything works. If it doesn't, please report the bug to michael@codesrc.com
Apple IIgs using Apple II High Speed SCSI controller card (from v3.3)
Symbolics Lisp Machine XL1200, using 1280 byte sectors (from v3.4)
PDP-11/73 running RSX11M+ V4.6
+ Microvax 3100 Model 80 running VMS 7.3 (needs patch against v3.5.2 firmware)
Amiga 500+ with GVP A530
Atari TT030 System V
Casio FZ-20M
Requires TERMPWR jumper. The manual shows the pin25 of the DB25 connector is "not connected".
May require scsi2sd-config --apple flag
+ Yamaha EX5R
Other
\r
if (scsiDev.phase == DATA_OUT)\r
{\r
+ if (scsiDev.parityError)\r
+ {\r
+ scsiDev.sense.code = ABORTED_COMMAND;\r
+ scsiDev.sense.asc = SCSI_PARITY_ERROR;\r
+ scsiDev.status = CHECK_CONDITION;;\r
+ }\r
scsiDev.phase = STATUS;\r
}\r
scsiDiskReset();\r
scsiRead(scsiDev.data + scsiDev.dataPtr, len);\r
scsiDev.dataPtr += len;\r
\r
- // TODO re-implement parity checking\r
- if (0 && scsiDev.parityError && config->enableParity)\r
+ if (scsiDev.parityError && config->enableParity)\r
{\r
scsiDev.sense.code = ABORTED_COMMAND;\r
scsiDev.sense.asc = SCSI_PARITY_ERROR;\r
\r
while (scsiPhyRxFifoEmpty() && !scsiDev.resetFlag) {}\r
uint8_t val = scsiPhyRx();\r
+ scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();\r
\r
- while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {}\r
+ while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}\r
\r
return val;\r
}\r
++i;\r
}\r
}\r
- while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {}\r
+ scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();\r
+ while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}\r
}\r
\r
static void\r
if (dmaSentCount == dmaTotalCount)\r
{\r
dmaInProgress = 0;\r
- while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {}\r
+ scsiDev.parityError = scsiDev.parityError || SCSI_Parity_Error_Read();\r
return 1;\r
}\r
else\r
\r
while (!(scsiPhyStatus() & SCSI_PHY_TX_COMPLETE) && !scsiDev.resetFlag) {}\r
scsiPhyRxFifoClear();\r
-\r
- while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {}\r
}\r
\r
static void\r
CyDmaClearPendingDrq(scsiDmaTxChan);\r
\r
txDMAComplete = 0;\r
+ rxDMAComplete = 1;\r
\r
CyDmaChEnable(scsiDmaTxChan, 1);\r
}\r
{\r
scsiPhyRxFifoClear();\r
dmaInProgress = 0;\r
- while (SCSI_ReadPin(SCSI_In_ACK) && !scsiDev.resetFlag) {}\r
return 1;\r
}\r
else\r
// Allow the FIFOs to fill up again.\r
SCSI_ClearPin(SCSI_Out_RST);\r
scsiTarget_AUX_CTL = scsiTarget_AUX_CTL & ~(0x03);\r
+\r
+ SCSI_Parity_Error_Read(); // clear sticky bits\r
}\r
\r
static void scsiPhyInitDMA()\r
HI16(CYDEV_PERIPH_BASE),\r
HI16(CYDEV_SRAM_BASE)\r
);\r
- \r
+\r
scsiDmaTxChan =\r
SCSI_TX_DMA_DmaInitialize(\r
1, // Bytes per burst\r
\r
scsiDmaRxTd[0] = CyDmaTdAllocate();\r
scsiDmaTxTd[0] = CyDmaTdAllocate();\r
- \r
+\r
SCSI_RX_DMA_COMPLETE_StartEx(scsiRxCompleteISR);\r
SCSI_TX_DMA_COMPLETE_StartEx(scsiTxCompleteISR);\r
}\r
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Parity_Error.c
+* Version 1.80
+*
+* Description:
+* This file contains API to enable firmware to read the value of a Status
+* Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Parity_Error.h"
+
+#if !defined(SCSI_Parity_Error_sts_sts_reg__REMOVED) /* Check for removal by optimization */
+
+
+/*******************************************************************************
+* Function Name: SCSI_Parity_Error_Read
+********************************************************************************
+*
+* Summary:
+* Reads the current value assigned to the Status Register.
+*
+* Parameters:
+* None.
+*
+* Return:
+* The current value in the Status Register.
+*
+*******************************************************************************/
+uint8 SCSI_Parity_Error_Read(void)
+{
+ return SCSI_Parity_Error_Status;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Parity_Error_InterruptEnable
+********************************************************************************
+*
+* Summary:
+* Enables the Status Register interrupt.
+*
+* Parameters:
+* None.
+*
+* Return:
+* None.
+*
+*******************************************************************************/
+void SCSI_Parity_Error_InterruptEnable(void)
+{
+ uint8 interruptState;
+ interruptState = CyEnterCriticalSection();
+ SCSI_Parity_Error_Status_Aux_Ctrl |= SCSI_Parity_Error_STATUS_INTR_ENBL;
+ CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Parity_Error_InterruptDisable
+********************************************************************************
+*
+* Summary:
+* Disables the Status Register interrupt.
+*
+* Parameters:
+* None.
+*
+* Return:
+* None.
+*
+*******************************************************************************/
+void SCSI_Parity_Error_InterruptDisable(void)
+{
+ uint8 interruptState;
+ interruptState = CyEnterCriticalSection();
+ SCSI_Parity_Error_Status_Aux_Ctrl &= (uint8)(~SCSI_Parity_Error_STATUS_INTR_ENBL);
+ CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Parity_Error_WriteMask
+********************************************************************************
+*
+* Summary:
+* Writes the current mask value assigned to the Status Register.
+*
+* Parameters:
+* mask: Value to write into the mask register.
+*
+* Return:
+* None.
+*
+*******************************************************************************/
+void SCSI_Parity_Error_WriteMask(uint8 mask)
+{
+ #if(SCSI_Parity_Error_INPUTS < 8u)
+ mask &= (uint8)((((uint8)1u) << SCSI_Parity_Error_INPUTS) - 1u);
+ #endif /* End SCSI_Parity_Error_INPUTS < 8u */
+ SCSI_Parity_Error_Status_Mask = mask;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Parity_Error_ReadMask
+********************************************************************************
+*
+* Summary:
+* Reads the current interrupt mask assigned to the Status Register.
+*
+* Parameters:
+* None.
+*
+* Return:
+* The value of the interrupt mask of the Status Register.
+*
+*******************************************************************************/
+uint8 SCSI_Parity_Error_ReadMask(void)
+{
+ return SCSI_Parity_Error_Status_Mask;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Parity_Error.h
+* Version 1.80
+*
+* Description:
+* This file containts Status Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_STATUS_REG_SCSI_Parity_Error_H) /* CY_STATUS_REG_SCSI_Parity_Error_H */
+#define CY_STATUS_REG_SCSI_Parity_Error_H
+
+#include "cytypes.h"
+#include "CyLib.h"
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+uint8 SCSI_Parity_Error_Read(void) ;
+void SCSI_Parity_Error_InterruptEnable(void) ;
+void SCSI_Parity_Error_InterruptDisable(void) ;
+void SCSI_Parity_Error_WriteMask(uint8 mask) ;
+uint8 SCSI_Parity_Error_ReadMask(void) ;
+
+
+/***************************************
+* API Constants
+***************************************/
+
+#define SCSI_Parity_Error_STATUS_INTR_ENBL 0x10u
+
+
+/***************************************
+* Parameter Constants
+***************************************/
+
+/* Status Register Inputs */
+#define SCSI_Parity_Error_INPUTS 1
+
+
+/***************************************
+* Registers
+***************************************/
+
+/* Status Register */
+#define SCSI_Parity_Error_Status (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG )
+#define SCSI_Parity_Error_Status_PTR ( (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG )
+#define SCSI_Parity_Error_Status_Mask (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__MASK_REG )
+#define SCSI_Parity_Error_Status_Aux_Ctrl (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG )
+
+#endif /* End CY_STATUS_REG_SCSI_Parity_Error_H */
+
+
+/* [] END OF FILE */
#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0\r
#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0\r
\r
+/* SCSI_Parity_Error */\r
+#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u\r
+#define SCSI_Parity_Error_sts_sts_reg__0__POS 0\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB10_11_ST\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u\r
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB10_MSK\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB10_ACTL\r
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB10_ST\r
+\r
/* USBFS_bus_reset */\r
#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0\r
/* SCSI_CTL_PHASE */\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL\r
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK\r
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK\r
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL\r
\r
/* SCSI_Out_Bits */\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1\r
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u\r
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL\r
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK\r
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK\r
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
\r
/* USBFS_arb_int */\r
#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
/* SCSI_Out_Ctl */\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB07_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB07_CTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL\r
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB07_MSK\r
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK\r
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL\r
\r
/* SCSI_Out_DBx */\r
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG\r
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK\r
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL\r
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST\r
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_RxStsReg__4__POS 4\r
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u\r
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u\r
#define SDCard_BSPIM_RxStsReg__6__POS 6\r
#define SDCard_BSPIM_RxStsReg__MASK 0x70u\r
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB05_MSK\r
-#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB05_ST_CTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB05_ST_CTL\r
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB05_ST\r
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB05_MSK\r
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL\r
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB05_ST\r
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u\r
#define SDCard_BSPIM_TxStsReg__0__POS 0\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST\r
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u\r
#define SDCard_BSPIM_TxStsReg__1__POS 1\r
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u\r
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u\r
#define SDCard_BSPIM_TxStsReg__4__POS 4\r
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu\r
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB06_MSK\r
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB06_ST\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB05_06_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB05_06_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB05_06_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB05_06_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB05_06_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB05_06_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB05_A0_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB05_A0\r
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB05_A1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB05_D0_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB05_D0\r
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB05_D1\r
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB05_F0_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB05_F0\r
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB05_F1\r
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL\r
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK\r
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL\r
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB06_07_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB06_07_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB06_07_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB06_07_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB06_07_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB06_07_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB06_A0_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB06_A0\r
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB06_A1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB06_D0_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB06_D0\r
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB06_D1\r
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB06_ACTL\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB06_F0_F1\r
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB06_F0\r
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB06_F1\r
\r
/* USBFS_dp_int */\r
#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
/* scsiTarget */\r
#define scsiTarget_StatusReg__0__MASK 0x01u\r
#define scsiTarget_StatusReg__0__POS 0\r
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL\r
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST\r
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL\r
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST\r
#define scsiTarget_StatusReg__1__MASK 0x02u\r
#define scsiTarget_StatusReg__1__POS 1\r
#define scsiTarget_StatusReg__2__MASK 0x04u\r
#define scsiTarget_StatusReg__4__MASK 0x10u\r
#define scsiTarget_StatusReg__4__POS 4\r
#define scsiTarget_StatusReg__MASK 0x1Fu\r
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB00_MSK\r
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL\r
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB00_ST\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST\r
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB03_MSK\r
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL\r
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB03_ST\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL\r
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL\r
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK\r
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK\r
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK\r
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB03_CTL\r
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL\r
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB03_CTL\r
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL\r
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB03_MSK\r
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB03_04_A0\r
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB03_04_A1\r
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB03_04_D0\r
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB03_04_D1\r
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL\r
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB03_04_F0\r
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB03_04_F1\r
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB03_A0_A1\r
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB03_A0\r
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB03_A1\r
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB03_D0_D1\r
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB03_D0\r
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB03_D1\r
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB03_ACTL\r
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB03_F0_F1\r
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB03_F0\r
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB03_F1\r
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL\r
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB11_MSK\r
+#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL\r
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL\r
+#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL\r
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB11_ST\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST\r
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB04_MSK\r
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL\r
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB04_ST\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL\r
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL\r
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK\r
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK\r
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB04_CTL\r
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB04_CTL\r
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL\r
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB04_MSK\r
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB04_05_A0\r
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB04_05_A1\r
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB04_05_D0\r
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB04_05_D1\r
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL\r
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB04_05_F0\r
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB04_05_F1\r
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB04_A0_A1\r
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB04_A0\r
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB04_A1\r
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB04_D0_D1\r
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB04_D0\r
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB04_D1\r
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL\r
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB04_F0_F1\r
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB04_F0\r
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB04_F1\r
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL\r
\r
/* USBFS_ep_0 */\r
#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0\r
}\r
#endif\r
\r
-#define CY_CFG_BASE_ADDR_COUNT 36u\r
+#define CY_CFG_BASE_ADDR_COUNT 37u\r
CYPACKED typedef struct\r
{\r
uint8 offset;\r
static const uint32 CYCODE cy_cfg_addr_table[] = {\r
0x40004502u, /* Base address: 0x40004500 Count: 2 */\r
0x40004F02u, /* Base address: 0x40004F00 Count: 2 */\r
- 0x4000520Au, /* Base address: 0x40005200 Count: 10 */\r
+ 0x4000520Cu, /* Base address: 0x40005200 Count: 12 */\r
0x40006402u, /* Base address: 0x40006400 Count: 2 */\r
- 0x4001004Bu, /* Base address: 0x40010000 Count: 75 */\r
- 0x40010138u, /* Base address: 0x40010100 Count: 56 */\r
- 0x40010248u, /* Base address: 0x40010200 Count: 72 */\r
- 0x4001035Au, /* Base address: 0x40010300 Count: 90 */\r
- 0x40010462u, /* Base address: 0x40010400 Count: 98 */\r
- 0x40010551u, /* Base address: 0x40010500 Count: 81 */\r
- 0x40010657u, /* Base address: 0x40010600 Count: 87 */\r
- 0x40010752u, /* Base address: 0x40010700 Count: 82 */\r
- 0x4001090Au, /* Base address: 0x40010900 Count: 10 */\r
- 0x40010A04u, /* Base address: 0x40010A00 Count: 4 */\r
- 0x40010B1Au, /* Base address: 0x40010B00 Count: 26 */\r
- 0x40010C3Eu, /* Base address: 0x40010C00 Count: 62 */\r
- 0x40010D42u, /* Base address: 0x40010D00 Count: 66 */\r
- 0x40010F06u, /* Base address: 0x40010F00 Count: 6 */\r
- 0x40011506u, /* Base address: 0x40011500 Count: 6 */\r
- 0x40011652u, /* Base address: 0x40011600 Count: 82 */\r
- 0x4001174Eu, /* Base address: 0x40011700 Count: 78 */\r
- 0x40011907u, /* Base address: 0x40011900 Count: 7 */\r
- 0x40011B05u, /* Base address: 0x40011B00 Count: 5 */\r
- 0x40014017u, /* Base address: 0x40014000 Count: 23 */\r
- 0x40014116u, /* Base address: 0x40014100 Count: 22 */\r
- 0x40014210u, /* Base address: 0x40014200 Count: 16 */\r
- 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */\r
- 0x4001440Cu, /* Base address: 0x40014400 Count: 12 */\r
- 0x40014518u, /* Base address: 0x40014500 Count: 24 */\r
- 0x40014607u, /* Base address: 0x40014600 Count: 7 */\r
- 0x4001470Au, /* Base address: 0x40014700 Count: 10 */\r
- 0x40014807u, /* Base address: 0x40014800 Count: 7 */\r
- 0x40014909u, /* Base address: 0x40014900 Count: 9 */\r
- 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */\r
- 0x40015006u, /* Base address: 0x40015000 Count: 6 */\r
+ 0x4001004Au, /* Base address: 0x40010000 Count: 74 */\r
+ 0x40010137u, /* Base address: 0x40010100 Count: 55 */\r
+ 0x4001024Au, /* Base address: 0x40010200 Count: 74 */\r
+ 0x4001035Cu, /* Base address: 0x40010300 Count: 92 */\r
+ 0x4001043Au, /* Base address: 0x40010400 Count: 58 */\r
+ 0x4001055Cu, /* Base address: 0x40010500 Count: 92 */\r
+ 0x4001064Eu, /* Base address: 0x40010600 Count: 78 */\r
+ 0x40010757u, /* Base address: 0x40010700 Count: 87 */\r
+ 0x4001091Au, /* Base address: 0x40010900 Count: 26 */\r
+ 0x40010A3Bu, /* Base address: 0x40010A00 Count: 59 */\r
+ 0x40010B51u, /* Base address: 0x40010B00 Count: 81 */\r
+ 0x40010D23u, /* Base address: 0x40010D00 Count: 35 */\r
+ 0x40010E49u, /* Base address: 0x40010E00 Count: 73 */\r
+ 0x40010F35u, /* Base address: 0x40010F00 Count: 53 */\r
+ 0x4001145Bu, /* Base address: 0x40011400 Count: 91 */\r
+ 0x40011543u, /* Base address: 0x40011500 Count: 67 */\r
+ 0x4001161Eu, /* Base address: 0x40011600 Count: 30 */\r
+ 0x40011750u, /* Base address: 0x40011700 Count: 80 */\r
+ 0x4001190Du, /* Base address: 0x40011900 Count: 13 */\r
+ 0x40011B03u, /* Base address: 0x40011B00 Count: 3 */\r
+ 0x4001401Bu, /* Base address: 0x40014000 Count: 27 */\r
+ 0x40014119u, /* Base address: 0x40014100 Count: 25 */\r
+ 0x4001420Cu, /* Base address: 0x40014200 Count: 12 */\r
+ 0x4001430Eu, /* Base address: 0x40014300 Count: 14 */\r
+ 0x4001440Eu, /* Base address: 0x40014400 Count: 14 */\r
+ 0x40014514u, /* Base address: 0x40014500 Count: 20 */\r
+ 0x40014609u, /* Base address: 0x40014600 Count: 9 */\r
+ 0x4001470Cu, /* Base address: 0x40014700 Count: 12 */\r
+ 0x40014805u, /* Base address: 0x40014800 Count: 5 */\r
+ 0x4001490Fu, /* Base address: 0x40014900 Count: 15 */\r
+ 0x40014C04u, /* Base address: 0x40014C00 Count: 4 */\r
+ 0x40015002u, /* Base address: 0x40015000 Count: 2 */\r
0x40015104u, /* Base address: 0x40015100 Count: 4 */\r
};\r
\r
{0x36u, 0x02u},\r
{0x7Eu, 0x02u},\r
{0x01u, 0x20u},\r
- {0x0Au, 0x4Bu},\r
- {0x00u, 0x05u},\r
- {0x01u, 0x13u},\r
- {0x18u, 0x0Cu},\r
- {0x19u, 0x08u},\r
+ {0x0Au, 0x27u},\r
+ {0x00u, 0x04u},\r
+ {0x01u, 0x11u},\r
+ {0x18u, 0x04u},\r
{0x1Cu, 0x61u},\r
- {0x20u, 0x90u},\r
- {0x21u, 0x58u},\r
- {0x30u, 0x06u},\r
- {0x31u, 0x0Cu},\r
+ {0x20u, 0x68u},\r
+ {0x21u, 0xC0u},\r
+ {0x2Cu, 0x0Fu},\r
+ {0x30u, 0x09u},\r
+ {0x31u, 0x0Au},\r
+ {0x34u, 0x90u},\r
+ {0x64u, 0x20u},\r
{0x7Cu, 0x40u},\r
- {0x23u, 0x02u},\r
+ {0x24u, 0x02u},\r
{0x86u, 0x0Fu},\r
- {0x01u, 0x09u},\r
- {0x03u, 0x24u},\r
- {0x05u, 0x09u},\r
- {0x06u, 0x0Eu},\r
- {0x07u, 0x12u},\r
- {0x0Bu, 0x30u},\r
- {0x0Cu, 0x21u},\r
- {0x0Eu, 0x84u},\r
- {0x0Fu, 0x46u},\r
- {0x12u, 0x21u},\r
- {0x16u, 0xC0u},\r
- {0x18u, 0x21u},\r
- {0x1Au, 0x42u},\r
- {0x1Bu, 0x01u},\r
- {0x1Eu, 0x20u},\r
- {0x1Fu, 0x08u},\r
- {0x21u, 0x40u},\r
- {0x22u, 0x10u},\r
- {0x23u, 0x80u},\r
- {0x26u, 0x01u},\r
- {0x2Bu, 0x80u},\r
- {0x2Cu, 0x08u},\r
- {0x2Eu, 0x10u},\r
- {0x2Fu, 0x09u},\r
- {0x30u, 0x18u},\r
- {0x31u, 0x07u},\r
- {0x32u, 0xE0u},\r
- {0x33u, 0xC0u},\r
- {0x34u, 0x07u},\r
- {0x35u, 0x38u},\r
- {0x3Eu, 0x01u},\r
- {0x3Fu, 0x04u},\r
+ {0x03u, 0x80u},\r
+ {0x06u, 0x80u},\r
+ {0x07u, 0x07u},\r
+ {0x09u, 0x44u},\r
+ {0x0Bu, 0x88u},\r
+ {0x0Eu, 0x07u},\r
+ {0x10u, 0xAAu},\r
+ {0x11u, 0xAAu},\r
+ {0x12u, 0x55u},\r
+ {0x13u, 0x55u},\r
+ {0x14u, 0x99u},\r
+ {0x15u, 0x99u},\r
+ {0x16u, 0x22u},\r
+ {0x17u, 0x22u},\r
+ {0x1Au, 0x70u},\r
+ {0x1Bu, 0x70u},\r
+ {0x27u, 0x08u},\r
+ {0x28u, 0x44u},\r
+ {0x2Au, 0x88u},\r
+ {0x2Eu, 0x08u},\r
+ {0x30u, 0x0Fu},\r
+ {0x33u, 0x0Fu},\r
+ {0x34u, 0xF0u},\r
+ {0x35u, 0xF0u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
{0x5Cu, 0x11u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x30u},\r
- {0x81u, 0x01u},\r
- {0x82u, 0xC0u},\r
- {0x84u, 0x09u},\r
- {0x85u, 0x02u},\r
- {0x86u, 0x06u},\r
- {0x87u, 0x04u},\r
- {0x88u, 0xFFu},\r
- {0x8Bu, 0x02u},\r
- {0x8Cu, 0x50u},\r
- {0x8Du, 0x02u},\r
- {0x8Eu, 0xA0u},\r
- {0x8Fu, 0x08u},\r
- {0x91u, 0x01u},\r
- {0x94u, 0x03u},\r
- {0x96u, 0x0Cu},\r
- {0x97u, 0x0Cu},\r
- {0x98u, 0x90u},\r
- {0x9Au, 0x60u},\r
- {0x9Cu, 0xFFu},\r
- {0x9Fu, 0x02u},\r
- {0xA4u, 0x05u},\r
- {0xA5u, 0x01u},\r
- {0xA6u, 0x0Au},\r
- {0xA9u, 0x01u},\r
- {0xAAu, 0xFFu},\r
- {0xACu, 0x0Fu},\r
- {0xAEu, 0xF0u},\r
- {0xB5u, 0x0Eu},\r
- {0xB6u, 0xFFu},\r
- {0xB7u, 0x01u},\r
- {0xB9u, 0x80u},\r
+ {0x82u, 0x20u},\r
+ {0x84u, 0x02u},\r
+ {0x85u, 0x08u},\r
+ {0x86u, 0x0Du},\r
+ {0x88u, 0x02u},\r
+ {0x8Au, 0x04u},\r
+ {0x8Bu, 0x19u},\r
+ {0x8Cu, 0x0Du},\r
+ {0x8Du, 0x33u},\r
+ {0x8Fu, 0x4Cu},\r
+ {0x90u, 0x10u},\r
+ {0x91u, 0x18u},\r
+ {0x92u, 0x20u},\r
+ {0x93u, 0x60u},\r
+ {0x94u, 0x0Du},\r
+ {0x99u, 0x2Au},\r
+ {0x9Au, 0x10u},\r
+ {0x9Bu, 0x55u},\r
+ {0x9Cu, 0x0Du},\r
+ {0x9Du, 0x01u},\r
+ {0x9Fu, 0x06u},\r
+ {0xA0u, 0x02u},\r
+ {0xA2u, 0x08u},\r
+ {0xA3u, 0x10u},\r
+ {0xA4u, 0x0Du},\r
+ {0xA5u, 0x3Au},\r
+ {0xA7u, 0x45u},\r
+ {0xA8u, 0x01u},\r
+ {0xAAu, 0x02u},\r
+ {0xABu, 0x01u},\r
+ {0xACu, 0x0Du},\r
+ {0xB1u, 0x07u},\r
+ {0xB2u, 0x0Fu},\r
+ {0xB6u, 0x30u},\r
+ {0xB7u, 0x78u},\r
+ {0xBAu, 0x08u},\r
+ {0xBBu, 0x82u},\r
{0xBEu, 0x40u},\r
- {0xBFu, 0x40u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
{0xDCu, 0x10u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x88u},\r
- {0x03u, 0x20u},\r
- {0x05u, 0x20u},\r
- {0x06u, 0x42u},\r
- {0x07u, 0x60u},\r
- {0x08u, 0x01u},\r
- {0x0Au, 0x24u},\r
- {0x0Bu, 0x01u},\r
- {0x0Eu, 0x08u},\r
- {0x0Fu, 0x22u},\r
- {0x11u, 0x44u},\r
- {0x12u, 0x40u},\r
- {0x15u, 0xC0u},\r
- {0x16u, 0x01u},\r
- {0x17u, 0x18u},\r
- {0x19u, 0x02u},\r
- {0x1Au, 0x20u},\r
- {0x1Bu, 0x30u},\r
- {0x1Eu, 0x01u},\r
- {0x20u, 0x40u},\r
- {0x21u, 0x18u},\r
- {0x22u, 0x01u},\r
- {0x24u, 0x02u},\r
- {0x27u, 0x08u},\r
- {0x28u, 0x05u},\r
- {0x29u, 0x40u},\r
- {0x2Au, 0x11u},\r
- {0x2Du, 0x08u},\r
- {0x2Eu, 0x10u},\r
- {0x30u, 0xA0u},\r
- {0x35u, 0x40u},\r
- {0x36u, 0x02u},\r
- {0x37u, 0x08u},\r
- {0x38u, 0x44u},\r
- {0x39u, 0x22u},\r
- {0x3Cu, 0x80u},\r
- {0x3Du, 0x10u},\r
- {0x3Eu, 0x05u},\r
- {0x58u, 0x82u},\r
- {0x59u, 0x14u},\r
- {0x61u, 0x80u},\r
- {0x81u, 0x10u},\r
- {0x82u, 0x80u},\r
- {0x84u, 0x04u},\r
- {0x89u, 0x10u},\r
- {0x8Cu, 0x01u},\r
+ {0x00u, 0x48u},\r
+ {0x05u, 0x56u},\r
+ {0x09u, 0x0Au},\r
+ {0x0Au, 0x04u},\r
+ {0x0Du, 0x20u},\r
+ {0x0Eu, 0x11u},\r
+ {0x0Fu, 0x40u},\r
+ {0x11u, 0x50u},\r
+ {0x15u, 0x24u},\r
+ {0x16u, 0x02u},\r
+ {0x17u, 0x01u},\r
+ {0x18u, 0x40u},\r
+ {0x1Au, 0x0Cu},\r
+ {0x1Bu, 0x01u},\r
+ {0x1Cu, 0x02u},\r
+ {0x1Du, 0x04u},\r
+ {0x21u, 0x24u},\r
+ {0x27u, 0x42u},\r
+ {0x2Au, 0x08u},\r
+ {0x2Fu, 0x54u},\r
+ {0x31u, 0x2Au},\r
+ {0x36u, 0x10u},\r
+ {0x37u, 0x42u},\r
+ {0x38u, 0x02u},\r
+ {0x39u, 0x18u},\r
+ {0x3Bu, 0x24u},\r
+ {0x3Du, 0x08u},\r
+ {0x3Eu, 0x40u},\r
+ {0x3Fu, 0x20u},\r
+ {0x59u, 0x80u},\r
+ {0x5Bu, 0x20u},\r
+ {0x60u, 0x04u},\r
+ {0x62u, 0x80u},\r
+ {0x63u, 0x08u},\r
+ {0x6Cu, 0x02u},\r
+ {0x6Du, 0x08u},\r
+ {0x6Fu, 0x18u},\r
+ {0x83u, 0x18u},\r
+ {0x84u, 0x50u},\r
+ {0x88u, 0x01u},\r
+ {0x89u, 0x04u},\r
+ {0x8Au, 0x04u},\r
+ {0x8Bu, 0x02u},\r
+ {0x8Fu, 0x04u},\r
{0xC0u, 0xF5u},\r
- {0xC2u, 0xEFu},\r
- {0xC4u, 0xEDu},\r
- {0xCAu, 0x6Du},\r
- {0xCCu, 0xDCu},\r
- {0xCEu, 0xFFu},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x08u},\r
- {0xE2u, 0x48u},\r
+ {0xC2u, 0xFEu},\r
+ {0xC4u, 0xF3u},\r
+ {0xCAu, 0xE2u},\r
+ {0xCCu, 0xB7u},\r
+ {0xCEu, 0x77u},\r
+ {0xD6u, 0x0Cu},\r
+ {0xD8u, 0x0Cu},\r
+ {0xE0u, 0x04u},\r
+ {0xE2u, 0xA0u},\r
{0xE6u, 0x02u},\r
- {0x06u, 0xFFu},\r
- {0x08u, 0xFFu},\r
- {0x0Cu, 0x50u},\r
- {0x0Du, 0x04u},\r
- {0x0Eu, 0xA0u},\r
- {0x0Fu, 0x03u},\r
- {0x11u, 0x01u},\r
- {0x12u, 0xFFu},\r
- {0x13u, 0x06u},\r
- {0x14u, 0x03u},\r
- {0x15u, 0x03u},\r
- {0x16u, 0x0Cu},\r
- {0x17u, 0x04u},\r
- {0x18u, 0x60u},\r
- {0x19u, 0x05u},\r
- {0x1Au, 0x90u},\r
- {0x1Bu, 0x02u},\r
- {0x1Cu, 0x0Fu},\r
- {0x1Eu, 0xF0u},\r
- {0x24u, 0x05u},\r
- {0x26u, 0x0Au},\r
- {0x28u, 0x06u},\r
- {0x2Au, 0x09u},\r
- {0x2Cu, 0x30u},\r
- {0x2Eu, 0xC0u},\r
- {0x32u, 0xFFu},\r
- {0x37u, 0x07u},\r
- {0x3Bu, 0x80u},\r
- {0x3Eu, 0x04u},\r
+ {0x01u, 0x60u},\r
+ {0x04u, 0x06u},\r
+ {0x06u, 0x01u},\r
+ {0x08u, 0x04u},\r
+ {0x09u, 0x04u},\r
+ {0x0Bu, 0x03u},\r
+ {0x10u, 0x1Fu},\r
+ {0x11u, 0x2Du},\r
+ {0x13u, 0x12u},\r
+ {0x16u, 0x1Eu},\r
+ {0x18u, 0x01u},\r
+ {0x19u, 0x1Bu},\r
+ {0x1Au, 0x18u},\r
+ {0x1Bu, 0x44u},\r
+ {0x24u, 0x07u},\r
+ {0x26u, 0x08u},\r
+ {0x29u, 0x19u},\r
+ {0x2Au, 0x02u},\r
+ {0x2Bu, 0x26u},\r
+ {0x2Cu, 0x17u},\r
+ {0x30u, 0x1Eu},\r
+ {0x31u, 0x70u},\r
+ {0x33u, 0x07u},\r
+ {0x34u, 0x01u},\r
+ {0x35u, 0x08u},\r
+ {0x39u, 0x02u},\r
+ {0x3Bu, 0x08u},\r
+ {0x3Eu, 0x10u},\r
+ {0x3Fu, 0x10u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x01u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x82u, 0x3Fu},\r
- {0x84u, 0x01u},\r
- {0x89u, 0x01u},\r
- {0x8Cu, 0x34u},\r
- {0x8Eu, 0x4Bu},\r
- {0x98u, 0x0Bu},\r
- {0x9Au, 0x64u},\r
- {0x9Cu, 0x08u},\r
- {0x9Eu, 0x52u},\r
- {0xA6u, 0x20u},\r
- {0xB2u, 0x40u},\r
- {0xB4u, 0x07u},\r
- {0xB6u, 0x38u},\r
- {0xB7u, 0x01u},\r
- {0xBEu, 0x04u},\r
- {0xBFu, 0x40u},\r
- {0xC0u, 0x54u},\r
- {0xC1u, 0x02u},\r
- {0xC2u, 0x30u},\r
- {0xC5u, 0xE2u},\r
- {0xC6u, 0xCFu},\r
- {0xC7u, 0x0Du},\r
- {0xC8u, 0x1Fu},\r
- {0xC9u, 0xFFu},\r
- {0xCAu, 0xFFu},\r
- {0xCBu, 0xFFu},\r
- {0xCFu, 0x2Cu},\r
- {0xD6u, 0x01u},\r
+ {0x80u, 0x40u},\r
+ {0x81u, 0x02u},\r
+ {0x85u, 0x01u},\r
+ {0x8Au, 0x07u},\r
+ {0x8Du, 0x04u},\r
+ {0x8Eu, 0x20u},\r
+ {0x8Fu, 0x08u},\r
+ {0x90u, 0x0Au},\r
+ {0x92u, 0x05u},\r
+ {0x94u, 0x09u},\r
+ {0x96u, 0x02u},\r
+ {0x97u, 0x04u},\r
+ {0x98u, 0x04u},\r
+ {0x99u, 0x02u},\r
+ {0x9Au, 0x08u},\r
+ {0xA1u, 0x02u},\r
+ {0xA2u, 0x08u},\r
+ {0xA6u, 0x10u},\r
+ {0xABu, 0x08u},\r
+ {0xACu, 0x10u},\r
+ {0xADu, 0x02u},\r
+ {0xAEu, 0x20u},\r
+ {0xB0u, 0x30u},\r
+ {0xB1u, 0x02u},\r
+ {0xB2u, 0x0Fu},\r
+ {0xB3u, 0x01u},\r
+ {0xB4u, 0x40u},\r
+ {0xB7u, 0x0Cu},\r
+ {0xB9u, 0x02u},\r
+ {0xBEu, 0x11u},\r
+ {0xBFu, 0x45u},\r
+ {0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDAu, 0x04u},\r
{0xDBu, 0x04u},\r
{0xDCu, 0x01u},\r
- {0xDDu, 0x01u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0xE2u, 0xC0u},\r
- {0xE6u, 0x80u},\r
- {0xE8u, 0x40u},\r
- {0xE9u, 0x40u},\r
- {0xEEu, 0x08u},\r
- {0x00u, 0x80u},\r
- {0x02u, 0x40u},\r
- {0x03u, 0x10u},\r
- {0x05u, 0x20u},\r
- {0x06u, 0x02u},\r
- {0x07u, 0x10u},\r
- {0x0Au, 0x05u},\r
- {0x0Cu, 0x01u},\r
- {0x0Du, 0x40u},\r
- {0x0Eu, 0x08u},\r
+ {0x00u, 0x20u},\r
+ {0x02u, 0x82u},\r
+ {0x03u, 0x08u},\r
+ {0x04u, 0x20u},\r
+ {0x05u, 0x08u},\r
+ {0x09u, 0x0Au},\r
+ {0x0Au, 0x04u},\r
+ {0x0Eu, 0x44u},\r
{0x0Fu, 0x20u},\r
- {0x13u, 0x04u},\r
- {0x14u, 0x08u},\r
- {0x16u, 0x01u},\r
- {0x17u, 0x68u},\r
- {0x18u, 0x14u},\r
- {0x19u, 0x40u},\r
- {0x1Au, 0x0Du},\r
- {0x1Bu, 0x80u},\r
- {0x1Eu, 0x10u},\r
- {0x22u, 0x40u},\r
- {0x25u, 0x40u},\r
- {0x28u, 0x01u},\r
- {0x29u, 0x04u},\r
- {0x2Bu, 0x21u},\r
- {0x35u, 0x11u},\r
- {0x36u, 0x08u},\r
+ {0x11u, 0x01u},\r
+ {0x13u, 0x44u},\r
+ {0x14u, 0x21u},\r
+ {0x17u, 0x10u},\r
+ {0x19u, 0x20u},\r
+ {0x1Au, 0x80u},\r
+ {0x1Bu, 0x08u},\r
+ {0x1Du, 0x02u},\r
+ {0x1Eu, 0x40u},\r
+ {0x1Fu, 0x20u},\r
+ {0x20u, 0x12u},\r
+ {0x22u, 0x01u},\r
+ {0x24u, 0x80u},\r
+ {0x25u, 0x01u},\r
+ {0x27u, 0x28u},\r
+ {0x28u, 0x04u},\r
+ {0x29u, 0x01u},\r
+ {0x2Bu, 0x02u},\r
+ {0x2Eu, 0x20u},\r
+ {0x32u, 0x28u},\r
+ {0x35u, 0x10u},\r
+ {0x37u, 0x01u},\r
+ {0x38u, 0x04u},\r
+ {0x39u, 0x22u},\r
{0x3Au, 0x20u},\r
- {0x3Du, 0x80u},\r
- {0x3Eu, 0x80u},\r
- {0x40u, 0x14u},\r
- {0x41u, 0x01u},\r
- {0x49u, 0x40u},\r
- {0x4Au, 0x40u},\r
- {0x4Bu, 0x04u},\r
- {0x51u, 0x10u},\r
- {0x52u, 0x80u},\r
- {0x53u, 0x28u},\r
- {0x58u, 0x14u},\r
- {0x59u, 0x02u},\r
- {0x5Au, 0x80u},\r
+ {0x3Bu, 0x40u},\r
+ {0x3Du, 0x02u},\r
+ {0x3Fu, 0x10u},\r
+ {0x45u, 0x40u},\r
+ {0x46u, 0x02u},\r
+ {0x58u, 0x98u},\r
+ {0x5Cu, 0x40u},\r
+ {0x5Fu, 0x30u},\r
{0x60u, 0x02u},\r
- {0x62u, 0x04u},\r
- {0x63u, 0x88u},\r
- {0x68u, 0x80u},\r
- {0x69u, 0x54u},\r
- {0x70u, 0x20u},\r
- {0x73u, 0x51u},\r
- {0x83u, 0x04u},\r
- {0x84u, 0x80u},\r
- {0x86u, 0x42u},\r
- {0x88u, 0x02u},\r
- {0x89u, 0x02u},\r
- {0x8Cu, 0x04u},\r
- {0x8Du, 0x40u},\r
- {0x92u, 0x02u},\r
- {0x94u, 0x04u},\r
- {0x95u, 0x96u},\r
- {0x96u, 0x14u},\r
- {0x97u, 0x81u},\r
- {0x9Au, 0x30u},\r
- {0x9Bu, 0x08u},\r
- {0x9Cu, 0x80u},\r
- {0x9Du, 0x6Cu},\r
- {0x9Eu, 0x02u},\r
- {0x9Fu, 0x70u},\r
- {0xA0u, 0x04u},\r
- {0xA3u, 0x10u},\r
- {0xA4u, 0xE0u},\r
- {0xA5u, 0x80u},\r
- {0xA6u, 0x86u},\r
- {0xA7u, 0x09u},\r
- {0xAAu, 0x30u},\r
- {0xAFu, 0x40u},\r
- {0xB0u, 0x02u},\r
- {0xB1u, 0x0Au},\r
- {0xB3u, 0x08u},\r
- {0xC0u, 0xEDu},\r
- {0xC2u, 0xF3u},\r
- {0xC4u, 0xE4u},\r
- {0xCCu, 0xE0u},\r
- {0xCEu, 0x14u},\r
- {0xD0u, 0x07u},\r
- {0xD2u, 0x08u},\r
- {0xD6u, 0x0Fu},\r
- {0xD8u, 0x0Fu},\r
- {0xE6u, 0x0Cu},\r
- {0xEAu, 0x04u},\r
- {0xECu, 0x04u},\r
- {0xEEu, 0x21u},\r
- {0x01u, 0x9Bu},\r
- {0x03u, 0x04u},\r
- {0x04u, 0x03u},\r
- {0x06u, 0x0Cu},\r
- {0x07u, 0x40u},\r
- {0x08u, 0x30u},\r
- {0x09u, 0x0Cu},\r
- {0x0Au, 0xC0u},\r
- {0x0Bu, 0x80u},\r
- {0x0Cu, 0x0Fu},\r
- {0x0Du, 0x20u},\r
- {0x0Eu, 0xF0u},\r
- {0x0Fu, 0x40u},\r
- {0x10u, 0x50u},\r
- {0x12u, 0xA0u},\r
- {0x15u, 0x98u},\r
- {0x17u, 0x04u},\r
- {0x1Bu, 0x01u},\r
- {0x1Cu, 0x06u},\r
- {0x1Du, 0x80u},\r
- {0x1Eu, 0x09u},\r
- {0x1Fu, 0x17u},\r
- {0x20u, 0x05u},\r
- {0x22u, 0x0Au},\r
- {0x23u, 0x20u},\r
- {0x24u, 0x60u},\r
- {0x25u, 0x03u},\r
- {0x26u, 0x90u},\r
- {0x27u, 0x0Cu},\r
- {0x29u, 0x02u},\r
- {0x2Fu, 0x1Fu},\r
- {0x31u, 0x1Fu},\r
- {0x34u, 0xFFu},\r
- {0x35u, 0x60u},\r
- {0x37u, 0x80u},\r
- {0x3Eu, 0x10u},\r
- {0x3Fu, 0x50u},\r
+ {0x62u, 0x14u},\r
+ {0x66u, 0x80u},\r
+ {0x80u, 0x02u},\r
+ {0x81u, 0x02u},\r
+ {0x82u, 0x40u},\r
+ {0x84u, 0x01u},\r
+ {0x85u, 0x80u},\r
+ {0x88u, 0x04u},\r
+ {0x8Au, 0x01u},\r
+ {0x8Bu, 0x20u},\r
+ {0x8Cu, 0x0Au},\r
+ {0x90u, 0x04u},\r
+ {0x92u, 0x08u},\r
+ {0x93u, 0x04u},\r
+ {0x94u, 0x02u},\r
+ {0x95u, 0x64u},\r
+ {0x96u, 0x51u},\r
+ {0x97u, 0xE8u},\r
+ {0x98u, 0x10u},\r
+ {0x99u, 0x01u},\r
+ {0x9Bu, 0x50u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Du, 0xD2u},\r
+ {0x9Eu, 0x0Au},\r
+ {0x9Fu, 0x01u},\r
+ {0xA0u, 0x02u},\r
+ {0xA1u, 0x04u},\r
+ {0xA2u, 0x80u},\r
+ {0xA3u, 0x11u},\r
+ {0xA4u, 0x04u},\r
+ {0xA5u, 0x0Au},\r
+ {0xA6u, 0x10u},\r
+ {0xABu, 0x10u},\r
+ {0xAFu, 0x20u},\r
+ {0xB1u, 0x20u},\r
+ {0xB4u, 0x40u},\r
+ {0xB5u, 0x01u},\r
+ {0xC0u, 0x6Bu},\r
+ {0xC2u, 0x7Eu},\r
+ {0xC4u, 0xEDu},\r
+ {0xCAu, 0x2Du},\r
+ {0xCCu, 0xA6u},\r
+ {0xCEu, 0xABu},\r
+ {0xD6u, 0x1Eu},\r
+ {0xD8u, 0x1Eu},\r
+ {0xE0u, 0x01u},\r
+ {0xE2u, 0x28u},\r
+ {0xEAu, 0x02u},\r
+ {0xEEu, 0x01u},\r
+ {0x00u, 0x02u},\r
+ {0x09u, 0x01u},\r
+ {0x14u, 0x01u},\r
+ {0x28u, 0x04u},\r
+ {0x2Du, 0x02u},\r
+ {0x30u, 0x02u},\r
+ {0x31u, 0x01u},\r
+ {0x34u, 0x04u},\r
+ {0x36u, 0x01u},\r
+ {0x37u, 0x02u},\r
+ {0x3Eu, 0x51u},\r
+ {0x3Fu, 0x41u},\r
+ {0x40u, 0x24u},\r
+ {0x41u, 0x03u},\r
+ {0x42u, 0x10u},\r
+ {0x45u, 0xFCu},\r
+ {0x46u, 0xD2u},\r
+ {0x47u, 0x0Eu},\r
+ {0x48u, 0x1Fu},\r
+ {0x49u, 0xFFu},\r
+ {0x4Au, 0xFFu},\r
+ {0x4Bu, 0xFFu},\r
+ {0x4Fu, 0x2Cu},\r
+ {0x56u, 0x01u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Cu, 0x10u},\r
+ {0x5Au, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Du, 0x01u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0x35u},\r
- {0x89u, 0x39u},\r
- {0x8Bu, 0x42u},\r
- {0x8Fu, 0x04u},\r
- {0x91u, 0x20u},\r
- {0x95u, 0x4Au},\r
- {0x97u, 0x31u},\r
- {0x99u, 0x0Bu},\r
- {0x9Bu, 0x70u},\r
- {0x9Du, 0x12u},\r
- {0x9Fu, 0x01u},\r
- {0xA1u, 0x35u},\r
- {0xA5u, 0x15u},\r
- {0xA7u, 0x20u},\r
- {0xA9u, 0x05u},\r
- {0xABu, 0x30u},\r
- {0xADu, 0x30u},\r
- {0xAFu, 0x05u},\r
- {0xB3u, 0x78u},\r
- {0xB5u, 0x04u},\r
- {0xB7u, 0x03u},\r
- {0xB9u, 0x08u},\r
- {0xBBu, 0x80u},\r
+ {0x62u, 0xC0u},\r
+ {0x66u, 0x80u},\r
+ {0x68u, 0x40u},\r
+ {0x69u, 0x40u},\r
+ {0x6Eu, 0x08u},\r
+ {0x84u, 0x0Bu},\r
+ {0x86u, 0x14u},\r
+ {0x8Du, 0x01u},\r
+ {0x90u, 0x34u},\r
+ {0x92u, 0x0Bu},\r
+ {0x96u, 0x3Fu},\r
+ {0x98u, 0x08u},\r
+ {0x9Au, 0x22u},\r
+ {0x9Eu, 0x10u},\r
+ {0xA8u, 0x01u},\r
+ {0xAFu, 0x02u},\r
+ {0xB2u, 0x07u},\r
+ {0xB3u, 0x02u},\r
+ {0xB4u, 0x38u},\r
+ {0xB5u, 0x01u},\r
{0xBFu, 0x10u},\r
- {0xC0u, 0x62u},\r
- {0xC1u, 0x04u},\r
- {0xC2u, 0x10u},\r
- {0xC4u, 0x05u},\r
- {0xC5u, 0xCEu},\r
- {0xC6u, 0xFDu},\r
- {0xC7u, 0x0Bu},\r
- {0xC8u, 0x1Fu},\r
- {0xC9u, 0xFFu},\r
- {0xCAu, 0xFFu},\r
- {0xCBu, 0xFFu},\r
- {0xCCu, 0x22u},\r
- {0xCEu, 0xF0u},\r
- {0xCFu, 0x08u},\r
- {0xD0u, 0x04u},\r
- {0xD4u, 0x40u},\r
+ {0xD4u, 0x09u},\r
{0xD6u, 0x04u},\r
+ {0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
- {0xDAu, 0x04u},\r
{0xDBu, 0x04u},\r
+ {0xDCu, 0x01u},\r
{0xDFu, 0x01u},\r
- {0xE2u, 0xC0u},\r
- {0xE4u, 0x40u},\r
- {0xE5u, 0x01u},\r
- {0xE6u, 0x10u},\r
- {0xE7u, 0x11u},\r
- {0xE8u, 0xC0u},\r
- {0xE9u, 0x01u},\r
- {0xEBu, 0x11u},\r
- {0xECu, 0x40u},\r
- {0xEDu, 0x01u},\r
- {0xEEu, 0x40u},\r
- {0xEFu, 0x01u},\r
- {0x00u, 0x64u},\r
- {0x09u, 0x01u},\r
- {0x0Au, 0x02u},\r
- {0x10u, 0x40u},\r
- {0x12u, 0x10u},\r
- {0x19u, 0x20u},\r
- {0x20u, 0x80u},\r
- {0x21u, 0x81u},\r
- {0x22u, 0x10u},\r
- {0x24u, 0x02u},\r
- {0x26u, 0xACu},\r
- {0x28u, 0xC1u},\r
- {0x2Au, 0x48u},\r
- {0x2Bu, 0x08u},\r
- {0x2Du, 0x40u},\r
- {0x2Eu, 0x12u},\r
- {0x2Fu, 0x20u},\r
- {0x30u, 0x10u},\r
- {0x32u, 0x04u},\r
- {0x33u, 0x90u},\r
- {0x35u, 0x12u},\r
- {0x36u, 0x88u},\r
- {0x38u, 0x48u},\r
- {0x39u, 0xA2u},\r
- {0x3Du, 0x21u},\r
- {0x3Fu, 0x80u},\r
- {0x45u, 0x62u},\r
- {0x4Du, 0x82u},\r
- {0x4Eu, 0x08u},\r
- {0x4Fu, 0x05u},\r
- {0x55u, 0x04u},\r
- {0x56u, 0x24u},\r
- {0x57u, 0x40u},\r
- {0x64u, 0x02u},\r
- {0x66u, 0x20u},\r
- {0x67u, 0xA0u},\r
- {0x6Eu, 0x40u},\r
- {0x6Fu, 0x14u},\r
- {0x78u, 0x02u},\r
- {0x7Bu, 0x40u},\r
- {0x7Eu, 0x20u},\r
- {0x7Fu, 0x10u},\r
- {0x82u, 0x40u},\r
- {0x88u, 0x40u},\r
- {0x8Eu, 0x19u},\r
- {0x91u, 0x20u},\r
- {0x92u, 0x0Eu},\r
- {0x93u, 0x50u},\r
- {0x95u, 0x82u},\r
- {0x97u, 0x80u},\r
- {0x9Au, 0x90u},\r
- {0x9Bu, 0x08u},\r
- {0x9Cu, 0x08u},\r
- {0x9Du, 0x39u},\r
- {0x9Eu, 0x41u},\r
- {0x9Fu, 0x14u},\r
- {0xA0u, 0x04u},\r
- {0xA3u, 0x88u},\r
- {0xA4u, 0x40u},\r
- {0xA5u, 0x80u},\r
- {0xA6u, 0x0Au},\r
- {0xAAu, 0x04u},\r
- {0xABu, 0x14u},\r
- {0xACu, 0x15u},\r
- {0xB1u, 0x40u},\r
- {0xB3u, 0x08u},\r
- {0xB5u, 0x40u},\r
+ {0x02u, 0x40u},\r
+ {0x05u, 0x04u},\r
+ {0x08u, 0x08u},\r
+ {0x0Du, 0x42u},\r
+ {0x0Eu, 0x04u},\r
+ {0x0Fu, 0x20u},\r
+ {0x12u, 0x04u},\r
+ {0x17u, 0x10u},\r
+ {0x18u, 0x04u},\r
+ {0x19u, 0x01u},\r
+ {0x1Bu, 0x40u},\r
+ {0x1Du, 0x0Cu},\r
+ {0x1Eu, 0x24u},\r
+ {0x1Fu, 0x30u},\r
+ {0x23u, 0x81u},\r
+ {0x27u, 0x24u},\r
+ {0x28u, 0x06u},\r
+ {0x2Au, 0x10u},\r
+ {0x2Cu, 0x02u},\r
+ {0x3Au, 0x10u},\r
+ {0x3Eu, 0x80u},\r
+ {0x41u, 0x0Au},\r
+ {0x42u, 0x04u},\r
+ {0x43u, 0x40u},\r
+ {0x49u, 0x08u},\r
+ {0x4Bu, 0x02u},\r
+ {0x50u, 0x10u},\r
+ {0x51u, 0x40u},\r
+ {0x52u, 0x08u},\r
+ {0x53u, 0x40u},\r
+ {0x59u, 0x21u},\r
+ {0x5Bu, 0x84u},\r
+ {0x5Cu, 0x40u},\r
+ {0x5Du, 0x10u},\r
+ {0x5Eu, 0x02u},\r
+ {0x5Fu, 0x04u},\r
+ {0x60u, 0x14u},\r
+ {0x63u, 0x81u},\r
+ {0x64u, 0x40u},\r
+ {0x65u, 0x80u},\r
+ {0x68u, 0x04u},\r
+ {0x69u, 0x49u},\r
+ {0x70u, 0x09u},\r
+ {0x72u, 0x0Au},\r
+ {0x83u, 0x01u},\r
+ {0x86u, 0x08u},\r
+ {0x88u, 0x20u},\r
+ {0x8Au, 0x04u},\r
+ {0x8Bu, 0x04u},\r
+ {0x8Cu, 0x98u},\r
+ {0x90u, 0x90u},\r
+ {0x92u, 0x08u},\r
+ {0x93u, 0x10u},\r
+ {0x94u, 0x22u},\r
+ {0x95u, 0x67u},\r
+ {0x96u, 0x15u},\r
+ {0x97u, 0xE8u},\r
+ {0x98u, 0x02u},\r
+ {0x99u, 0x20u},\r
+ {0x9Au, 0x94u},\r
+ {0x9Bu, 0x58u},\r
+ {0x9Cu, 0x60u},\r
+ {0x9Du, 0x58u},\r
+ {0x9Eu, 0x08u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA0u, 0x10u},\r
+ {0xA1u, 0x06u},\r
+ {0xA2u, 0x80u},\r
+ {0xA3u, 0x11u},\r
+ {0xA4u, 0x04u},\r
+ {0xA5u, 0x48u},\r
+ {0xA6u, 0x30u},\r
+ {0xA7u, 0x02u},\r
+ {0xA8u, 0x40u},\r
+ {0xAAu, 0x02u},\r
+ {0xACu, 0x01u},\r
+ {0xADu, 0x0Au},\r
+ {0xAEu, 0x08u},\r
+ {0xB0u, 0x80u},\r
{0xB6u, 0x04u},\r
- {0xB7u, 0x40u},\r
- {0xC0u, 0x07u},\r
- {0xC2u, 0x09u},\r
- {0xC4u, 0x0Cu},\r
- {0xCAu, 0xFFu},\r
- {0xCCu, 0xFEu},\r
- {0xCEu, 0xBFu},\r
- {0xD0u, 0xB0u},\r
- {0xD2u, 0x30u},\r
- {0xD8u, 0xF0u},\r
- {0xE2u, 0x41u},\r
- {0xEAu, 0x0Au},\r
- {0xEEu, 0x06u},\r
- {0x00u, 0x24u},\r
- {0x01u, 0x01u},\r
- {0x04u, 0x6Cu},\r
- {0x05u, 0x10u},\r
- {0x0Au, 0x2Fu},\r
- {0x0Bu, 0x40u},\r
- {0x0Cu, 0x2Cu},\r
- {0x0Eu, 0x40u},\r
- {0x10u, 0x31u},\r
- {0x11u, 0x07u},\r
+ {0xC0u, 0x28u},\r
+ {0xC2u, 0xF4u},\r
+ {0xC4u, 0x42u},\r
+ {0xCAu, 0x18u},\r
+ {0xCEu, 0x14u},\r
+ {0xD0u, 0x0Fu},\r
+ {0xD6u, 0xFFu},\r
+ {0xD8u, 0x9Fu},\r
+ {0xE0u, 0x08u},\r
+ {0xE4u, 0x04u},\r
+ {0xEAu, 0x09u},\r
+ {0xEEu, 0x0Cu},\r
+ {0x08u, 0x14u},\r
+ {0x0Au, 0x43u},\r
+ {0x0Bu, 0xFFu},\r
+ {0x0Cu, 0xE0u},\r
+ {0x0Du, 0x69u},\r
+ {0x0Fu, 0x96u},\r
+ {0x11u, 0x0Fu},\r
{0x12u, 0x02u},\r
- {0x13u, 0xD8u},\r
- {0x14u, 0x40u},\r
- {0x15u, 0x08u},\r
- {0x16u, 0x2Cu},\r
- {0x17u, 0x61u},\r
- {0x18u, 0x11u},\r
- {0x19u, 0xA2u},\r
- {0x1Au, 0x0Eu},\r
- {0x1Bu, 0x08u},\r
- {0x1Cu, 0x08u},\r
- {0x1Du, 0x01u},\r
- {0x1Eu, 0x10u},\r
- {0x20u, 0x6Cu},\r
- {0x21u, 0x01u},\r
- {0x24u, 0x80u},\r
- {0x25u, 0x01u},\r
- {0x28u, 0x64u},\r
- {0x29u, 0x04u},\r
- {0x2Au, 0x08u},\r
- {0x2Cu, 0x80u},\r
- {0x2Du, 0x01u},\r
- {0x30u, 0x0Fu},\r
- {0x31u, 0x3Fu},\r
- {0x32u, 0x80u},\r
- {0x34u, 0x31u},\r
- {0x35u, 0xE0u},\r
- {0x36u, 0x40u},\r
- {0x37u, 0x08u},\r
- {0x38u, 0x08u},\r
- {0x39u, 0x02u},\r
- {0x3Au, 0x30u},\r
- {0x3Eu, 0x40u},\r
- {0x3Fu, 0x41u},\r
+ {0x13u, 0xF0u},\r
+ {0x15u, 0x33u},\r
+ {0x17u, 0xCCu},\r
+ {0x18u, 0x21u},\r
+ {0x1Au, 0x12u},\r
+ {0x1Bu, 0xFFu},\r
+ {0x1Du, 0x55u},\r
+ {0x1Eu, 0xECu},\r
+ {0x1Fu, 0xAAu},\r
+ {0x20u, 0x88u},\r
+ {0x21u, 0xFFu},\r
+ {0x22u, 0x13u},\r
+ {0x27u, 0xFFu},\r
+ {0x2Au, 0x01u},\r
+ {0x2Bu, 0xFFu},\r
+ {0x30u, 0x10u},\r
+ {0x31u, 0xFFu},\r
+ {0x34u, 0xE0u},\r
+ {0x36u, 0x0Fu},\r
+ {0x3Bu, 0x02u},\r
+ {0x3Eu, 0x11u},\r
{0x56u, 0x02u},\r
- {0x57u, 0x20u},\r
+ {0x57u, 0x28u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
+ {0x5Cu, 0x10u},\r
{0x5Fu, 0x01u},\r
- {0x81u, 0xC0u},\r
- {0x82u, 0x49u},\r
- {0x83u, 0x01u},\r
- {0x86u, 0x06u},\r
- {0x87u, 0x9Fu},\r
- {0x89u, 0xC0u},\r
- {0x8Bu, 0x08u},\r
- {0x8Cu, 0x09u},\r
- {0x8Du, 0xC0u},\r
- {0x8Eu, 0x24u},\r
- {0x8Fu, 0x02u},\r
- {0x91u, 0x90u},\r
- {0x93u, 0x40u},\r
- {0x97u, 0xFFu},\r
- {0x98u, 0x09u},\r
- {0x99u, 0xC0u},\r
- {0x9Au, 0x52u},\r
- {0x9Bu, 0x04u},\r
- {0x9Du, 0x80u},\r
- {0x9Eu, 0x30u},\r
- {0xA1u, 0x1Fu},\r
- {0xA3u, 0x20u},\r
- {0xA7u, 0x60u},\r
- {0xA9u, 0x7Fu},\r
- {0xAAu, 0x08u},\r
- {0xABu, 0x80u},\r
- {0xAEu, 0x01u},\r
- {0xB0u, 0x40u},\r
- {0xB3u, 0xFFu},\r
- {0xB4u, 0x07u},\r
- {0xB6u, 0x38u},\r
- {0xBEu, 0x01u},\r
- {0xBFu, 0x04u},\r
+ {0x84u, 0x40u},\r
+ {0x85u, 0x03u},\r
+ {0x86u, 0x1Fu},\r
+ {0x87u, 0x0Cu},\r
+ {0x89u, 0x50u},\r
+ {0x8Au, 0x70u},\r
+ {0x8Bu, 0xA0u},\r
+ {0x8Cu, 0x03u},\r
+ {0x8Du, 0x0Fu},\r
+ {0x8Eu, 0x0Cu},\r
+ {0x8Fu, 0xF0u},\r
+ {0x90u, 0x20u},\r
+ {0x92u, 0x4Fu},\r
+ {0x94u, 0x10u},\r
+ {0x95u, 0x05u},\r
+ {0x96u, 0x2Fu},\r
+ {0x97u, 0x0Au},\r
+ {0x98u, 0x05u},\r
+ {0x9Au, 0x0Au},\r
+ {0x9Bu, 0xFFu},\r
+ {0x9Fu, 0xFFu},\r
+ {0xA1u, 0x60u},\r
+ {0xA3u, 0x90u},\r
+ {0xA4u, 0x0Fu},\r
+ {0xA5u, 0xFFu},\r
+ {0xA9u, 0x30u},\r
+ {0xABu, 0xC0u},\r
+ {0xACu, 0x06u},\r
+ {0xADu, 0x06u},\r
+ {0xAEu, 0x09u},\r
+ {0xAFu, 0x09u},\r
+ {0xB4u, 0x7Fu},\r
+ {0xB5u, 0xFFu},\r
+ {0xB9u, 0x80u},\r
+ {0xBFu, 0x50u},\r
+ {0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
{0xDCu, 0x01u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x84u},\r
- {0x03u, 0x80u},\r
- {0x04u, 0x02u},\r
+ {0x01u, 0x20u},\r
+ {0x02u, 0x02u},\r
+ {0x03u, 0x20u},\r
+ {0x04u, 0x80u},\r
{0x05u, 0x10u},\r
- {0x06u, 0x20u},\r
- {0x07u, 0x01u},\r
- {0x08u, 0x80u},\r
- {0x0Au, 0x05u},\r
- {0x0Du, 0x02u},\r
- {0x0Eu, 0x18u},\r
- {0x0Fu, 0x01u},\r
- {0x13u, 0x50u},\r
- {0x15u, 0x09u},\r
- {0x17u, 0x50u},\r
- {0x18u, 0x04u},\r
- {0x1Au, 0x01u},\r
- {0x1Bu, 0x01u},\r
- {0x1Du, 0xB7u},\r
- {0x1Eu, 0x02u},\r
- {0x1Fu, 0x08u},\r
- {0x21u, 0x04u},\r
- {0x25u, 0x10u},\r
- {0x26u, 0x50u},\r
- {0x27u, 0x40u},\r
- {0x29u, 0x15u},\r
- {0x2Du, 0x40u},\r
- {0x2Eu, 0x02u},\r
- {0x2Fu, 0x28u},\r
- {0x32u, 0x88u},\r
- {0x33u, 0x11u},\r
- {0x35u, 0x11u},\r
- {0x36u, 0x88u},\r
- {0x38u, 0x80u},\r
- {0x39u, 0x10u},\r
- {0x3Au, 0x06u},\r
- {0x3Du, 0x29u},\r
- {0x45u, 0xC0u},\r
- {0x66u, 0x80u},\r
- {0x6Cu, 0x40u},\r
- {0x6Du, 0x51u},\r
- {0x6Eu, 0x10u},\r
- {0x6Fu, 0x31u},\r
- {0x75u, 0x80u},\r
- {0x76u, 0x02u},\r
+ {0x08u, 0x10u},\r
+ {0x09u, 0x0Au},\r
+ {0x0Bu, 0x80u},\r
+ {0x0Cu, 0x02u},\r
+ {0x0Du, 0x90u},\r
+ {0x11u, 0x08u},\r
+ {0x12u, 0x01u},\r
+ {0x17u, 0x21u},\r
+ {0x19u, 0x20u},\r
+ {0x1Cu, 0x48u},\r
+ {0x1Du, 0x80u},\r
+ {0x21u, 0x40u},\r
+ {0x22u, 0x20u},\r
+ {0x26u, 0x02u},\r
+ {0x28u, 0x40u},\r
+ {0x29u, 0x02u},\r
+ {0x2Au, 0x08u},\r
+ {0x2Bu, 0x05u},\r
+ {0x2Fu, 0x64u},\r
+ {0x32u, 0x44u},\r
+ {0x33u, 0x10u},\r
+ {0x34u, 0x04u},\r
+ {0x36u, 0x92u},\r
+ {0x38u, 0x04u},\r
+ {0x3Bu, 0x60u},\r
+ {0x3Eu, 0x80u},\r
+ {0x3Fu, 0x20u},\r
+ {0x58u, 0xA0u},\r
+ {0x60u, 0x08u},\r
+ {0x62u, 0x40u},\r
+ {0x67u, 0x10u},\r
+ {0x6Du, 0xC4u},\r
+ {0x6Eu, 0x15u},\r
+ {0x75u, 0xC0u},\r
+ {0x80u, 0x20u},\r
+ {0x82u, 0x08u},\r
+ {0x84u, 0x04u},\r
+ {0x8Au, 0x40u},\r
+ {0x8Bu, 0x40u},\r
+ {0x8Cu, 0x08u},\r
+ {0x8Du, 0x40u},\r
+ {0x90u, 0x80u},\r
+ {0x91u, 0x08u},\r
+ {0x92u, 0x08u},\r
+ {0x93u, 0x18u},\r
+ {0x94u, 0x40u},\r
+ {0x95u, 0x36u},\r
+ {0x96u, 0x11u},\r
+ {0x97u, 0x44u},\r
+ {0x98u, 0x94u},\r
+ {0x9Au, 0x83u},\r
+ {0x9Bu, 0x30u},\r
+ {0x9Cu, 0x08u},\r
+ {0x9Du, 0x50u},\r
+ {0x9Eu, 0x40u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA0u, 0x10u},\r
+ {0xA1u, 0x0Eu},\r
+ {0xA2u, 0x90u},\r
+ {0xA3u, 0x31u},\r
+ {0xA4u, 0x02u},\r
+ {0xA5u, 0x40u},\r
+ {0xA6u, 0x21u},\r
+ {0xA7u, 0x02u},\r
+ {0xA9u, 0x08u},\r
+ {0xAAu, 0x01u},\r
+ {0xADu, 0x80u},\r
+ {0xAFu, 0x08u},\r
+ {0xB0u, 0x10u},\r
+ {0xB5u, 0x08u},\r
+ {0xC0u, 0xC7u},\r
+ {0xC2u, 0xDEu},\r
+ {0xC4u, 0x55u},\r
+ {0xCAu, 0xEFu},\r
+ {0xCCu, 0xFEu},\r
+ {0xCEu, 0x3Eu},\r
+ {0xD6u, 0x0Cu},\r
+ {0xD8u, 0x4Cu},\r
+ {0xE2u, 0x02u},\r
+ {0xE6u, 0x1Du},\r
+ {0xEAu, 0x06u},\r
+ {0xECu, 0x04u},\r
{0x81u, 0x80u},\r
- {0x82u, 0x20u},\r
- {0x8Bu, 0x01u},\r
+ {0x8Bu, 0x0Au},\r
+ {0x8Fu, 0x80u},\r
{0x90u, 0x02u},\r
- {0x92u, 0x04u},\r
- {0x93u, 0x55u},\r
- {0x94u, 0x04u},\r
- {0x95u, 0xC1u},\r
- {0x96u, 0x10u},\r
- {0x98u, 0x10u},\r
- {0x99u, 0x20u},\r
- {0x9Au, 0x85u},\r
- {0x9Bu, 0x08u},\r
- {0x9Cu, 0x88u},\r
- {0x9Du, 0x19u},\r
- {0x9Eu, 0x02u},\r
- {0xA0u, 0x44u},\r
- {0xA1u, 0x04u},\r
- {0xA2u, 0x8Cu},\r
- {0xA3u, 0x80u},\r
- {0xA5u, 0x62u},\r
- {0xA6u, 0x02u},\r
- {0xA7u, 0x20u},\r
- {0xA8u, 0x04u},\r
- {0xA9u, 0x93u},\r
- {0xACu, 0x10u},\r
- {0xB0u, 0x01u},\r
- {0xC0u, 0xFDu},\r
- {0xC2u, 0xF3u},\r
- {0xC4u, 0xF3u},\r
- {0xCAu, 0xF7u},\r
- {0xCCu, 0xFFu},\r
- {0xCEu, 0xEFu},\r
- {0xD8u, 0x10u},\r
- {0xE2u, 0x89u},\r
- {0xE6u, 0x20u},\r
- {0xEAu, 0x08u},\r
- {0xEEu, 0x01u},\r
- {0x90u, 0x08u},\r
- {0x91u, 0x40u},\r
- {0x9Bu, 0x01u},\r
- {0x9Eu, 0x20u},\r
- {0xA2u, 0x10u},\r
- {0xA9u, 0x04u},\r
- {0xAEu, 0x40u},\r
- {0xE2u, 0x09u},\r
- {0xE6u, 0x20u},\r
- {0xEEu, 0x20u},\r
- {0xB9u, 0x08u},\r
- {0xBFu, 0x04u},\r
+ {0x92u, 0x01u},\r
+ {0x9Bu, 0x02u},\r
+ {0x9Fu, 0x48u},\r
+ {0xA0u, 0x80u},\r
+ {0xA1u, 0x80u},\r
+ {0xA2u, 0x04u},\r
+ {0xA3u, 0x08u},\r
+ {0xA4u, 0x10u},\r
+ {0xA6u, 0x20u},\r
+ {0xA7u, 0x80u},\r
+ {0xA8u, 0x08u},\r
+ {0xABu, 0x10u},\r
+ {0xADu, 0x21u},\r
+ {0xB3u, 0x10u},\r
+ {0xB4u, 0x08u},\r
+ {0xB5u, 0x02u},\r
+ {0xE0u, 0x40u},\r
+ {0xE2u, 0x22u},\r
+ {0xE4u, 0x80u},\r
+ {0xE6u, 0x0Cu},\r
+ {0xEAu, 0x22u},\r
+ {0xECu, 0x10u},\r
+ {0x00u, 0x06u},\r
+ {0x0Bu, 0x02u},\r
+ {0x0Cu, 0x04u},\r
+ {0x0Eu, 0x03u},\r
+ {0x11u, 0x02u},\r
+ {0x13u, 0x04u},\r
+ {0x14u, 0x06u},\r
+ {0x18u, 0x02u},\r
+ {0x1Au, 0x04u},\r
+ {0x1Bu, 0x04u},\r
+ {0x23u, 0x01u},\r
+ {0x30u, 0x01u},\r
+ {0x31u, 0x06u},\r
+ {0x33u, 0x01u},\r
+ {0x34u, 0x06u},\r
+ {0x3Au, 0x20u},\r
+ {0x3Fu, 0x01u},\r
+ {0x54u, 0x01u},\r
+ {0x58u, 0x04u},\r
+ {0x59u, 0x04u},\r
+ {0x5Bu, 0x04u},\r
+ {0x5Cu, 0x11u},\r
+ {0x5Du, 0x10u},\r
+ {0x5Fu, 0x01u},\r
+ {0x82u, 0xFFu},\r
+ {0x84u, 0x0Fu},\r
+ {0x86u, 0xF0u},\r
+ {0x87u, 0xFFu},\r
+ {0x88u, 0x33u},\r
+ {0x89u, 0xFFu},\r
+ {0x8Au, 0xCCu},\r
+ {0x92u, 0xFFu},\r
+ {0x93u, 0xFFu},\r
+ {0x94u, 0x55u},\r
+ {0x95u, 0x0Fu},\r
+ {0x96u, 0xAAu},\r
+ {0x97u, 0xF0u},\r
+ {0x9Au, 0xFFu},\r
+ {0x9Cu, 0xFFu},\r
+ {0x9Du, 0x33u},\r
+ {0x9Fu, 0xCCu},\r
+ {0xA1u, 0x96u},\r
+ {0xA3u, 0x69u},\r
+ {0xA4u, 0x69u},\r
+ {0xA6u, 0x96u},\r
+ {0xA7u, 0xFFu},\r
+ {0xABu, 0xFFu},\r
+ {0xADu, 0x55u},\r
+ {0xAEu, 0xFFu},\r
+ {0xAFu, 0xAAu},\r
+ {0xB3u, 0xFFu},\r
+ {0xB4u, 0xFFu},\r
+ {0xBAu, 0x20u},\r
+ {0xBBu, 0x08u},\r
+ {0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
+ {0xDCu, 0x11u},\r
{0xDFu, 0x01u},\r
- {0x27u, 0x20u},\r
- {0x83u, 0x20u},\r
- {0x8Bu, 0x04u},\r
+ {0x00u, 0x60u},\r
+ {0x01u, 0x12u},\r
+ {0x04u, 0x04u},\r
+ {0x07u, 0x88u},\r
+ {0x09u, 0x08u},\r
+ {0x0Au, 0x08u},\r
+ {0x0Du, 0x42u},\r
+ {0x0Eu, 0x04u},\r
+ {0x0Fu, 0x20u},\r
+ {0x14u, 0x02u},\r
+ {0x17u, 0x04u},\r
+ {0x19u, 0x03u},\r
+ {0x1Au, 0x0Cu},\r
+ {0x1Cu, 0x04u},\r
+ {0x1Fu, 0x10u},\r
+ {0x21u, 0x08u},\r
+ {0x23u, 0x40u},\r
+ {0x26u, 0x08u},\r
+ {0x27u, 0x10u},\r
+ {0x29u, 0x01u},\r
+ {0x2Cu, 0x08u},\r
+ {0x2Eu, 0x04u},\r
+ {0x2Fu, 0x81u},\r
+ {0x30u, 0x20u},\r
+ {0x32u, 0x01u},\r
+ {0x34u, 0x02u},\r
+ {0x36u, 0x88u},\r
+ {0x39u, 0x10u},\r
+ {0x3Eu, 0x10u},\r
+ {0x3Fu, 0x04u},\r
+ {0x5Au, 0x02u},\r
+ {0x5Bu, 0x42u},\r
+ {0x5Cu, 0x28u},\r
+ {0x5Du, 0x81u},\r
+ {0x65u, 0x40u},\r
+ {0x6Cu, 0x21u},\r
+ {0x6Eu, 0x89u},\r
+ {0x6Fu, 0x08u},\r
+ {0x74u, 0x81u},\r
+ {0x76u, 0x24u},\r
+ {0x80u, 0x20u},\r
+ {0x85u, 0x80u},\r
+ {0x8Au, 0x04u},\r
+ {0x8Bu, 0x84u},\r
+ {0x8Cu, 0x01u},\r
+ {0x8Du, 0x20u},\r
+ {0x90u, 0x40u},\r
+ {0x91u, 0x80u},\r
+ {0x92u, 0x10u},\r
+ {0x93u, 0x02u},\r
+ {0x94u, 0x01u},\r
+ {0x97u, 0x44u},\r
+ {0x98u, 0x02u},\r
+ {0x99u, 0x40u},\r
+ {0x9Bu, 0x06u},\r
+ {0x9Eu, 0x24u},\r
+ {0xA1u, 0x80u},\r
+ {0xA2u, 0x80u},\r
+ {0xA3u, 0x10u},\r
+ {0xA4u, 0x11u},\r
+ {0xA5u, 0x02u},\r
+ {0xA6u, 0x64u},\r
+ {0xA7u, 0x08u},\r
+ {0xAAu, 0x04u},\r
+ {0xACu, 0x01u},\r
+ {0xAEu, 0x03u},\r
+ {0xB0u, 0x40u},\r
+ {0xB7u, 0x04u},\r
+ {0xC0u, 0x79u},\r
+ {0xC2u, 0xF6u},\r
+ {0xC4u, 0xA0u},\r
+ {0xCAu, 0xF1u},\r
+ {0xCCu, 0xD5u},\r
+ {0xCEu, 0x64u},\r
+ {0xD6u, 0xF8u},\r
+ {0xD8u, 0x10u},\r
+ {0xE2u, 0x90u},\r
+ {0xE4u, 0x70u},\r
+ {0xEAu, 0x20u},\r
+ {0xECu, 0x10u},\r
+ {0xEEu, 0x04u},\r
+ {0x81u, 0x40u},\r
+ {0x82u, 0x12u},\r
+ {0x87u, 0x40u},\r
+ {0x89u, 0x40u},\r
+ {0x8Au, 0x20u},\r
{0x8Fu, 0x10u},\r
- {0x90u, 0x08u},\r
- {0x91u, 0x40u},\r
+ {0x90u, 0x40u},\r
+ {0x92u, 0x01u},\r
+ {0x93u, 0x02u},\r
+ {0x94u, 0x01u},\r
{0x97u, 0x04u},\r
- {0x99u, 0x04u},\r
- {0x9Au, 0x40u},\r
- {0x9Bu, 0x11u},\r
- {0x9Eu, 0x20u},\r
- {0xA2u, 0x10u},\r
- {0xA9u, 0x54u},\r
- {0xADu, 0x05u},\r
- {0xAFu, 0x01u},\r
- {0xB1u, 0x02u},\r
- {0xB2u, 0x18u},\r
- {0xB4u, 0x40u},\r
- {0xB5u, 0x41u},\r
- {0xE2u, 0x10u},\r
- {0xE4u, 0x20u},\r
- {0xE6u, 0x40u},\r
- {0xE8u, 0xC4u},\r
- {0xEAu, 0x01u},\r
- {0xECu, 0x80u},\r
- {0xEEu, 0x50u},\r
- {0x02u, 0x04u},\r
- {0x06u, 0x20u},\r
- {0x08u, 0x21u},\r
- {0x0Au, 0x42u},\r
- {0x0Eu, 0x04u},\r
- {0x11u, 0x20u},\r
- {0x13u, 0x90u},\r
- {0x15u, 0x04u},\r
- {0x16u, 0x18u},\r
- {0x17u, 0x08u},\r
+ {0x98u, 0x02u},\r
+ {0x9Bu, 0x02u},\r
+ {0x9Cu, 0x40u},\r
+ {0x9Eu, 0x26u},\r
+ {0xA1u, 0x80u},\r
+ {0xA2u, 0x80u},\r
+ {0xA4u, 0x10u},\r
+ {0xA5u, 0x02u},\r
+ {0xA6u, 0x66u},\r
+ {0xA7u, 0x08u},\r
+ {0xA8u, 0x02u},\r
+ {0xAEu, 0x04u},\r
+ {0xB2u, 0x04u},\r
+ {0xB3u, 0x08u},\r
+ {0xB4u, 0x90u},\r
+ {0xB7u, 0x04u},\r
+ {0xE0u, 0x90u},\r
+ {0xE2u, 0x48u},\r
+ {0xE4u, 0x02u},\r
+ {0xE6u, 0x80u},\r
+ {0xE8u, 0x40u},\r
+ {0xEAu, 0x02u},\r
+ {0xECu, 0x88u},\r
+ {0xEEu, 0x40u},\r
+ {0x02u, 0x08u},\r
+ {0x05u, 0x01u},\r
+ {0x06u, 0x10u},\r
+ {0x0Cu, 0x0Au},\r
+ {0x0Du, 0x02u},\r
+ {0x0Eu, 0x05u},\r
+ {0x0Fu, 0x04u},\r
+ {0x10u, 0x09u},\r
+ {0x12u, 0x02u},\r
+ {0x17u, 0x04u},\r
{0x18u, 0x04u},\r
- {0x1Au, 0x10u},\r
- {0x1Bu, 0x01u},\r
- {0x1Eu, 0x02u},\r
- {0x21u, 0x10u},\r
+ {0x1Au, 0x08u},\r
+ {0x1Bu, 0x02u},\r
+ {0x1Eu, 0x07u},\r
+ {0x20u, 0x20u},\r
{0x22u, 0x40u},\r
- {0x23u, 0x20u},\r
- {0x24u, 0x04u},\r
- {0x25u, 0x08u},\r
- {0x26u, 0x08u},\r
- {0x27u, 0x44u},\r
- {0x29u, 0x4Du},\r
- {0x2Au, 0x01u},\r
- {0x2Bu, 0xB2u},\r
- {0x2Cu, 0x80u},\r
- {0x2Fu, 0x02u},\r
- {0x30u, 0x03u},\r
- {0x31u, 0xC0u},\r
- {0x32u, 0x1Cu},\r
- {0x33u, 0x03u},\r
- {0x34u, 0x80u},\r
- {0x36u, 0x60u},\r
- {0x37u, 0x3Cu},\r
- {0x3Eu, 0x51u},\r
- {0x3Fu, 0x45u},\r
+ {0x26u, 0x20u},\r
+ {0x2Eu, 0x40u},\r
+ {0x30u, 0x10u},\r
+ {0x33u, 0x06u},\r
+ {0x34u, 0x60u},\r
+ {0x35u, 0x01u},\r
+ {0x36u, 0x0Fu},\r
+ {0x3Eu, 0x10u},\r
+ {0x3Fu, 0x04u},\r
+ {0x56u, 0x08u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
{0x5Bu, 0x04u},\r
- {0x5Cu, 0x01u},\r
+ {0x5Cu, 0x11u},\r
+ {0x5Du, 0x90u},\r
{0x5Fu, 0x01u},\r
- {0x8Bu, 0x08u},\r
- {0x8Cu, 0x01u},\r
- {0x8Du, 0x10u},\r
- {0x91u, 0x04u},\r
- {0x93u, 0x08u},\r
- {0x97u, 0x04u},\r
- {0x98u, 0x02u},\r
- {0xA5u, 0x01u},\r
- {0xA9u, 0x02u},\r
- {0xACu, 0x04u},\r
- {0xB0u, 0x02u},\r
- {0xB1u, 0x02u},\r
- {0xB3u, 0x10u},\r
- {0xB4u, 0x01u},\r
- {0xB5u, 0x0Cu},\r
- {0xB6u, 0x04u},\r
- {0xB7u, 0x01u},\r
- {0xBEu, 0x51u},\r
- {0xBFu, 0x55u},\r
+ {0x84u, 0x50u},\r
+ {0x85u, 0x09u},\r
+ {0x86u, 0xA0u},\r
+ {0x87u, 0x06u},\r
+ {0x88u, 0x60u},\r
+ {0x89u, 0x03u},\r
+ {0x8Au, 0x90u},\r
+ {0x8Bu, 0x0Cu},\r
+ {0x8Cu, 0x0Fu},\r
+ {0x8Eu, 0xF0u},\r
+ {0x8Fu, 0xFFu},\r
+ {0x91u, 0x0Fu},\r
+ {0x93u, 0xF0u},\r
+ {0x95u, 0x30u},\r
+ {0x97u, 0xC0u},\r
+ {0x9Bu, 0xFFu},\r
+ {0x9Cu, 0x05u},\r
+ {0x9Du, 0x90u},\r
+ {0x9Eu, 0x0Au},\r
+ {0x9Fu, 0x60u},\r
+ {0xA3u, 0xFFu},\r
+ {0xA4u, 0x03u},\r
+ {0xA5u, 0x05u},\r
+ {0xA6u, 0x0Cu},\r
+ {0xA7u, 0x0Au},\r
+ {0xA8u, 0x06u},\r
+ {0xA9u, 0x50u},\r
+ {0xAAu, 0x09u},\r
+ {0xABu, 0xA0u},\r
+ {0xACu, 0x30u},\r
+ {0xAEu, 0xC0u},\r
+ {0xB3u, 0xFFu},\r
+ {0xB6u, 0xFFu},\r
+ {0xBEu, 0x40u},\r
+ {0xBFu, 0x04u},\r
+ {0xD6u, 0x08u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
+ {0xDBu, 0x04u},\r
+ {0xDDu, 0x90u},\r
{0xDFu, 0x01u},\r
- {0x03u, 0x02u},\r
- {0x04u, 0x40u},\r
- {0x05u, 0x02u},\r
- {0x06u, 0x24u},\r
- {0x09u, 0x10u},\r
- {0x0Cu, 0x80u},\r
- {0x0Eu, 0x20u},\r
- {0x0Fu, 0x04u},\r
- {0x10u, 0x01u},\r
- {0x14u, 0x08u},\r
- {0x16u, 0x40u},\r
- {0x17u, 0x48u},\r
- {0x19u, 0x61u},\r
- {0x1Du, 0x90u},\r
- {0x1Eu, 0xA0u},\r
- {0x21u, 0x45u},\r
- {0x22u, 0x10u},\r
- {0x24u, 0x80u},\r
- {0x25u, 0x04u},\r
- {0x27u, 0x01u},\r
- {0x2Au, 0x18u},\r
- {0x2Cu, 0xA8u},\r
- {0x2Du, 0x40u},\r
- {0x31u, 0x02u},\r
- {0x32u, 0x08u},\r
- {0x34u, 0x08u},\r
- {0x36u, 0x11u},\r
- {0x39u, 0x10u},\r
- {0x3Au, 0x80u},\r
- {0x6Cu, 0x04u},\r
- {0x6Du, 0x50u},\r
- {0x6Eu, 0x02u},\r
- {0x6Fu, 0x10u},\r
- {0x74u, 0x90u},\r
- {0x75u, 0x04u},\r
- {0x76u, 0x40u},\r
- {0x81u, 0x10u},\r
- {0x83u, 0x40u},\r
- {0x84u, 0x01u},\r
- {0x85u, 0x10u},\r
- {0x87u, 0x02u},\r
- {0x89u, 0x60u},\r
- {0x8Au, 0x80u},\r
- {0x8Cu, 0x08u},\r
- {0x8Du, 0x02u},\r
- {0x8Eu, 0x1Cu},\r
- {0x8Fu, 0x08u},\r
- {0x94u, 0x80u},\r
- {0x98u, 0x08u},\r
- {0xA0u, 0x20u},\r
- {0xA4u, 0x10u},\r
- {0xA5u, 0x80u},\r
- {0xA6u, 0x40u},\r
- {0xA8u, 0x08u},\r
- {0xA9u, 0x80u},\r
- {0xC0u, 0xF1u},\r
- {0xC2u, 0xE2u},\r
- {0xC4u, 0xF1u},\r
- {0xCAu, 0xF6u},\r
- {0xCCu, 0xE3u},\r
- {0xCEu, 0x0Cu},\r
- {0xE2u, 0xAAu},\r
- {0xE4u, 0x50u},\r
- {0xE6u, 0x01u},\r
- {0xE8u, 0x80u},\r
- {0xEAu, 0x04u},\r
- {0x80u, 0x40u},\r
- {0x84u, 0x10u},\r
- {0x86u, 0x40u},\r
- {0x88u, 0x20u},\r
- {0xE0u, 0x01u},\r
- {0xE4u, 0x20u},\r
- {0xABu, 0x21u},\r
- {0xAFu, 0x80u},\r
- {0xB0u, 0x08u},\r
- {0xB1u, 0x40u},\r
- {0xB2u, 0x10u},\r
- {0xB7u, 0x40u},\r
- {0x00u, 0x21u},\r
- {0x01u, 0x02u},\r
+ {0x00u, 0x09u},\r
{0x02u, 0x02u},\r
- {0x03u, 0x0Du},\r
- {0x04u, 0xE0u},\r
- {0x05u, 0x60u},\r
- {0x08u, 0x88u},\r
- {0x09u, 0x0Du},\r
- {0x0Au, 0x03u},\r
+ {0x06u, 0x24u},\r
+ {0x07u, 0x02u},\r
+ {0x09u, 0x02u},\r
+ {0x0Au, 0x01u},\r
+ {0x0Bu, 0x04u},\r
{0x0Eu, 0x01u},\r
- {0x11u, 0x91u},\r
- {0x13u, 0x22u},\r
- {0x15u, 0x92u},\r
- {0x16u, 0xECu},\r
- {0x17u, 0x44u},\r
- {0x18u, 0x04u},\r
- {0x19u, 0xA2u},\r
- {0x1Au, 0x43u},\r
- {0x1Bu, 0x18u},\r
- {0x1Du, 0x0Du},\r
- {0x21u, 0x0Du},\r
- {0x25u, 0x0Du},\r
- {0x2Au, 0x12u},\r
- {0x2Du, 0x0Du},\r
- {0x30u, 0x10u},\r
- {0x31u, 0x0Fu},\r
- {0x32u, 0x0Fu},\r
- {0x35u, 0x70u},\r
- {0x36u, 0xE0u},\r
- {0x37u, 0x80u},\r
- {0x39u, 0x20u},\r
- {0x3Bu, 0x02u},\r
- {0x3Eu, 0x40u},\r
- {0x3Fu, 0x40u},\r
- {0x54u, 0x09u},\r
- {0x56u, 0x04u},\r
+ {0x11u, 0x04u},\r
+ {0x13u, 0x82u},\r
+ {0x14u, 0x04u},\r
+ {0x16u, 0x02u},\r
+ {0x17u, 0x08u},\r
+ {0x18u, 0x40u},\r
+ {0x1Au, 0x05u},\r
+ {0x1Du, 0x80u},\r
+ {0x1Fu, 0x80u},\r
+ {0x20u, 0x08u},\r
+ {0x22u, 0x04u},\r
+ {0x24u, 0x20u},\r
+ {0x2Cu, 0x20u},\r
+ {0x2Fu, 0x88u},\r
+ {0x30u, 0x20u},\r
+ {0x33u, 0x08u},\r
+ {0x36u, 0x64u},\r
+ {0x37u, 0x82u},\r
+ {0x38u, 0x04u},\r
+ {0x39u, 0x40u},\r
+ {0x3Cu, 0x20u},\r
+ {0x3Du, 0x04u},\r
+ {0x3Fu, 0x88u},\r
+ {0x58u, 0x40u},\r
+ {0x5Bu, 0x10u},\r
+ {0x5Cu, 0x80u},\r
+ {0x60u, 0x04u},\r
+ {0x62u, 0x80u},\r
+ {0x64u, 0x02u},\r
+ {0x69u, 0x40u},\r
+ {0x6Bu, 0x02u},\r
+ {0x83u, 0x40u},\r
+ {0x88u, 0x24u},\r
+ {0x8Fu, 0x11u},\r
+ {0xC0u, 0xEDu},\r
+ {0xC2u, 0x8Bu},\r
+ {0xC4u, 0xEDu},\r
+ {0xCAu, 0xE0u},\r
+ {0xCCu, 0xF6u},\r
+ {0xCEu, 0x7Au},\r
+ {0xD6u, 0x1Cu},\r
+ {0xD8u, 0x1Cu},\r
+ {0xE0u, 0x40u},\r
+ {0xE4u, 0xA0u},\r
+ {0xE6u, 0x02u},\r
+ {0x00u, 0x09u},\r
+ {0x02u, 0x06u},\r
+ {0x04u, 0x03u},\r
+ {0x05u, 0x03u},\r
+ {0x06u, 0x0Cu},\r
+ {0x07u, 0x0Cu},\r
+ {0x08u, 0x05u},\r
+ {0x09u, 0x50u},\r
+ {0x0Au, 0x0Au},\r
+ {0x0Bu, 0xA0u},\r
+ {0x0Du, 0x0Fu},\r
+ {0x0Fu, 0xF0u},\r
+ {0x10u, 0x0Fu},\r
+ {0x12u, 0xF0u},\r
+ {0x15u, 0x05u},\r
+ {0x16u, 0xFFu},\r
+ {0x17u, 0x0Au},\r
+ {0x18u, 0xFFu},\r
+ {0x1Bu, 0xFFu},\r
+ {0x1Cu, 0x90u},\r
+ {0x1Du, 0xFFu},\r
+ {0x1Eu, 0x60u},\r
+ {0x20u, 0xFFu},\r
+ {0x21u, 0x60u},\r
+ {0x23u, 0x90u},\r
+ {0x24u, 0x50u},\r
+ {0x26u, 0xA0u},\r
+ {0x27u, 0xFFu},\r
+ {0x28u, 0x30u},\r
+ {0x29u, 0x30u},\r
+ {0x2Au, 0xC0u},\r
+ {0x2Bu, 0xC0u},\r
+ {0x2Du, 0x06u},\r
+ {0x2Fu, 0x09u},\r
+ {0x30u, 0xFFu},\r
+ {0x31u, 0xFFu},\r
+ {0x3Eu, 0x01u},\r
+ {0x3Fu, 0x01u},\r
{0x58u, 0x04u},\r
{0x59u, 0x04u},\r
- {0x5Bu, 0x04u},\r
{0x5Fu, 0x01u},\r
- {0x80u, 0x50u},\r
- {0x81u, 0x30u},\r
- {0x82u, 0xA0u},\r
- {0x83u, 0xC0u},\r
- {0x84u, 0x03u},\r
- {0x85u, 0x06u},\r
- {0x86u, 0x0Cu},\r
- {0x87u, 0x09u},\r
- {0x89u, 0xFFu},\r
- {0x8Au, 0xFFu},\r
- {0x8Cu, 0x30u},\r
- {0x8Eu, 0xC0u},\r
- {0x90u, 0x0Fu},\r
- {0x92u, 0xF0u},\r
- {0x94u, 0x09u},\r
- {0x95u, 0x03u},\r
- {0x96u, 0x06u},\r
- {0x97u, 0x0Cu},\r
- {0x99u, 0x05u},\r
- {0x9Au, 0xFFu},\r
- {0x9Bu, 0x0Au},\r
- {0x9Du, 0x0Fu},\r
- {0x9Eu, 0xFFu},\r
- {0x9Fu, 0xF0u},\r
- {0xA0u, 0x90u},\r
- {0xA1u, 0x50u},\r
- {0xA2u, 0x60u},\r
- {0xA3u, 0xA0u},\r
- {0xA4u, 0x05u},\r
- {0xA6u, 0x0Au},\r
+ {0x80u, 0x22u},\r
+ {0x82u, 0x10u},\r
+ {0x83u, 0x9Fu},\r
+ {0x84u, 0x17u},\r
+ {0x85u, 0xC0u},\r
+ {0x86u, 0x28u},\r
+ {0x87u, 0x04u},\r
+ {0x88u, 0x29u},\r
+ {0x89u, 0xC0u},\r
+ {0x8Au, 0x16u},\r
+ {0x8Bu, 0x08u},\r
+ {0x8Cu, 0x16u},\r
+ {0x8Du, 0x80u},\r
+ {0x90u, 0x04u},\r
+ {0x91u, 0x7Fu},\r
+ {0x93u, 0x80u},\r
+ {0x94u, 0x40u},\r
+ {0x97u, 0x60u},\r
+ {0x98u, 0x12u},\r
+ {0x99u, 0x1Fu},\r
+ {0x9Au, 0x04u},\r
+ {0x9Bu, 0x20u},\r
+ {0x9Cu, 0x16u},\r
+ {0x9Du, 0xC0u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA0u, 0x31u},\r
+ {0xA1u, 0xC0u},\r
+ {0xA2u, 0x0Eu},\r
+ {0xA3u, 0x02u},\r
+ {0xA4u, 0x40u},\r
{0xA7u, 0xFFu},\r
- {0xABu, 0xFFu},\r
- {0xADu, 0x60u},\r
- {0xAFu, 0x90u},\r
- {0xB1u, 0xFFu},\r
- {0xB2u, 0xFFu},\r
- {0xBEu, 0x04u},\r
- {0xBFu, 0x01u},\r
+ {0xA8u, 0x10u},\r
+ {0xAAu, 0x06u},\r
+ {0xACu, 0x06u},\r
+ {0xADu, 0x90u},\r
+ {0xAEu, 0x10u},\r
+ {0xAFu, 0x40u},\r
+ {0xB0u, 0x30u},\r
+ {0xB2u, 0x40u},\r
+ {0xB4u, 0x0Fu},\r
+ {0xB5u, 0xFFu},\r
+ {0xB8u, 0x28u},\r
+ {0xBAu, 0x02u},\r
+ {0xBFu, 0x10u},\r
+ {0xD4u, 0x40u},\r
+ {0xD6u, 0x04u},\r
{0xD8u, 0x04u},\r
{0xD9u, 0x04u},\r
{0xDBu, 0x04u},\r
{0xDFu, 0x01u},\r
- {0x00u, 0x08u},\r
- {0x01u, 0x22u},\r
- {0x02u, 0x01u},\r
- {0x03u, 0x40u},\r
- {0x04u, 0x44u},\r
- {0x05u, 0x11u},\r
- {0x08u, 0x18u},\r
- {0x09u, 0x40u},\r
- {0x0Au, 0x80u},\r
- {0x0Eu, 0x28u},\r
- {0x10u, 0x20u},\r
- {0x12u, 0xC0u},\r
- {0x13u, 0x08u},\r
- {0x16u, 0x04u},\r
- {0x19u, 0x08u},\r
- {0x1Cu, 0x40u},\r
- {0x1Eu, 0x20u},\r
- {0x1Fu, 0x80u},\r
- {0x22u, 0x02u},\r
- {0x24u, 0x04u},\r
- {0x25u, 0x01u},\r
- {0x27u, 0x01u},\r
- {0x28u, 0x10u},\r
- {0x29u, 0x22u},\r
- {0x2Au, 0x40u},\r
- {0x2Du, 0x41u},\r
+ {0x00u, 0x04u},\r
+ {0x02u, 0x48u},\r
+ {0x05u, 0x91u},\r
+ {0x07u, 0x20u},\r
+ {0x08u, 0x50u},\r
+ {0x0Au, 0x20u},\r
+ {0x0Bu, 0x40u},\r
+ {0x0Eu, 0x25u},\r
+ {0x0Fu, 0x80u},\r
+ {0x10u, 0x84u},\r
+ {0x12u, 0x10u},\r
+ {0x15u, 0x50u},\r
+ {0x17u, 0x09u},\r
+ {0x1Bu, 0x02u},\r
+ {0x1Du, 0x15u},\r
+ {0x1Eu, 0x40u},\r
+ {0x1Fu, 0x20u},\r
+ {0x21u, 0x01u},\r
+ {0x27u, 0x08u},\r
+ {0x28u, 0x54u},\r
+ {0x2Au, 0x48u},\r
+ {0x2Bu, 0x05u},\r
+ {0x2Du, 0x40u},\r
+ {0x2Eu, 0x01u},\r
{0x2Fu, 0x20u},\r
- {0x30u, 0x20u},\r
- {0x32u, 0x48u},\r
- {0x35u, 0x91u},\r
- {0x36u, 0x04u},\r
- {0x3Au, 0x11u},\r
- {0x3Bu, 0x08u},\r
- {0x3Cu, 0x04u},\r
- {0x3Du, 0x02u},\r
- {0x3Eu, 0x10u},\r
- {0x46u, 0x80u},\r
- {0x47u, 0x01u},\r
- {0x48u, 0x04u},\r
- {0x4Au, 0x08u},\r
- {0x5Eu, 0x82u},\r
- {0x5Fu, 0x24u},\r
- {0x64u, 0x08u},\r
- {0x66u, 0x82u},\r
- {0x67u, 0x08u},\r
- {0x69u, 0x80u},\r
- {0x6Au, 0x80u},\r
- {0x82u, 0x80u},\r
- {0x8Au, 0x02u},\r
- {0x91u, 0x41u},\r
- {0x92u, 0x10u},\r
- {0x93u, 0x05u},\r
- {0x95u, 0x80u},\r
- {0x98u, 0x10u},\r
- {0x99u, 0xB1u},\r
- {0x9Au, 0x05u},\r
- {0x9Bu, 0x08u},\r
- {0x9Cu, 0x08u},\r
- {0x9Du, 0x08u},\r
- {0xA0u, 0x04u},\r
- {0xA2u, 0x45u},\r
- {0xA3u, 0x20u},\r
- {0xA6u, 0x02u},\r
- {0xA8u, 0x04u},\r
- {0xB2u, 0x10u},\r
- {0xC0u, 0xFFu},\r
- {0xC2u, 0x6Fu},\r
- {0xC4u, 0x4Cu},\r
+ {0x30u, 0x80u},\r
+ {0x32u, 0x5Cu},\r
+ {0x33u, 0x10u},\r
+ {0x35u, 0x84u},\r
+ {0x37u, 0x21u},\r
+ {0x38u, 0x04u},\r
+ {0x3Au, 0x10u},\r
+ {0x3Bu, 0x60u},\r
+ {0x3Du, 0x12u},\r
+ {0x3Eu, 0x54u},\r
+ {0x64u, 0xA0u},\r
+ {0x66u, 0x20u},\r
+ {0x67u, 0x01u},\r
+ {0x84u, 0x80u},\r
+ {0x8Eu, 0x04u},\r
+ {0x90u, 0x04u},\r
+ {0x91u, 0x40u},\r
+ {0x92u, 0x9Du},\r
+ {0x93u, 0x61u},\r
+ {0x95u, 0x02u},\r
+ {0x98u, 0x60u},\r
+ {0x99u, 0x80u},\r
+ {0x9Au, 0x28u},\r
+ {0x9Bu, 0x31u},\r
+ {0x9Du, 0x15u},\r
+ {0xA1u, 0x01u},\r
+ {0xA2u, 0x14u},\r
+ {0xA3u, 0x45u},\r
+ {0xA7u, 0x02u},\r
+ {0xA8u, 0x05u},\r
+ {0xAAu, 0x01u},\r
+ {0xB1u, 0x30u},\r
+ {0xB2u, 0x80u},\r
+ {0xC0u, 0xFEu},\r
+ {0xC2u, 0xFFu},\r
+ {0xC4u, 0xFEu},\r
{0xCAu, 0xDFu},\r
{0xCCu, 0xFEu},\r
- {0xCEu, 0xE7u},\r
- {0xD6u, 0xF0u},\r
- {0xD8u, 0x90u},\r
- {0xE2u, 0x80u},\r
- {0xE6u, 0x04u},\r
- {0xE8u, 0x04u},\r
- {0xEAu, 0x80u},\r
- {0xEEu, 0x02u},\r
- {0x81u, 0x40u},\r
- {0x90u, 0x08u},\r
- {0x91u, 0x40u},\r
- {0x9Bu, 0x01u},\r
- {0xA2u, 0x10u},\r
- {0xAAu, 0x20u},\r
+ {0xCEu, 0xFEu},\r
+ {0xD8u, 0xF0u},\r
+ {0xE2u, 0x40u},\r
+ {0xEAu, 0x04u},\r
+ {0x80u, 0x08u},\r
+ {0x82u, 0x84u},\r
+ {0x87u, 0x80u},\r
+ {0x88u, 0x02u},\r
+ {0x8Au, 0x41u},\r
+ {0x8Bu, 0x07u},\r
+ {0x8Cu, 0x04u},\r
+ {0x8Eu, 0x28u},\r
+ {0x90u, 0x53u},\r
+ {0x91u, 0xAAu},\r
+ {0x92u, 0xACu},\r
+ {0x93u, 0x55u},\r
+ {0x94u, 0x01u},\r
+ {0x95u, 0x99u},\r
+ {0x96u, 0x12u},\r
+ {0x97u, 0x22u},\r
+ {0x9Bu, 0x70u},\r
+ {0xA3u, 0x08u},\r
+ {0xA5u, 0x44u},\r
+ {0xA7u, 0x88u},\r
+ {0xB0u, 0x0Fu},\r
+ {0xB3u, 0x0Fu},\r
+ {0xB4u, 0xC0u},\r
+ {0xB5u, 0xF0u},\r
+ {0xB6u, 0x30u},\r
+ {0xBEu, 0x51u},\r
+ {0xD8u, 0x04u},\r
+ {0xD9u, 0x04u},\r
+ {0xDCu, 0x10u},\r
+ {0xDFu, 0x01u},\r
+ {0x00u, 0x20u},\r
+ {0x01u, 0x01u},\r
+ {0x02u, 0x01u},\r
+ {0x05u, 0x95u},\r
+ {0x07u, 0x08u},\r
+ {0x08u, 0x20u},\r
+ {0x09u, 0x10u},\r
+ {0x0Bu, 0x50u},\r
+ {0x0Cu, 0x02u},\r
+ {0x0Eu, 0x09u},\r
+ {0x15u, 0x64u},\r
+ {0x17u, 0x21u},\r
+ {0x18u, 0x02u},\r
+ {0x19u, 0x20u},\r
+ {0x1Au, 0x80u},\r
+ {0x1Eu, 0x28u},\r
+ {0x20u, 0x04u},\r
+ {0x21u, 0x20u},\r
+ {0x23u, 0x10u},\r
+ {0x24u, 0x01u},\r
+ {0x25u, 0x10u},\r
+ {0x26u, 0x03u},\r
+ {0x27u, 0x21u},\r
+ {0x2Au, 0x02u},\r
+ {0x2Bu, 0x20u},\r
+ {0x2Eu, 0x85u},\r
+ {0x31u, 0x2Au},\r
+ {0x35u, 0x81u},\r
+ {0x37u, 0x28u},\r
+ {0x39u, 0x08u},\r
+ {0x3Bu, 0x10u},\r
+ {0x3Cu, 0x01u},\r
+ {0x3Du, 0x48u},\r
+ {0x3Eu, 0x10u},\r
+ {0x47u, 0x29u},\r
+ {0x4Cu, 0x04u},\r
+ {0x4Eu, 0x02u},\r
+ {0x4Fu, 0x05u},\r
+ {0x54u, 0x02u},\r
+ {0x55u, 0x05u},\r
+ {0x56u, 0xA0u},\r
+ {0x57u, 0x40u},\r
+ {0x7Au, 0x80u},\r
+ {0x7Bu, 0x40u},\r
+ {0x89u, 0x20u},\r
+ {0x8Eu, 0x40u},\r
+ {0x91u, 0x4Du},\r
+ {0x92u, 0x1Du},\r
+ {0x93u, 0x60u},\r
+ {0x94u, 0x04u},\r
+ {0x95u, 0x32u},\r
+ {0x96u, 0x80u},\r
+ {0x97u, 0x04u},\r
+ {0x98u, 0x40u},\r
+ {0x99u, 0x80u},\r
+ {0x9Au, 0x0Au},\r
+ {0x9Bu, 0x10u},\r
+ {0x9Du, 0x10u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA0u, 0x10u},\r
+ {0xA1u, 0x0Au},\r
+ {0xA3u, 0x25u},\r
+ {0xA4u, 0x02u},\r
+ {0xA6u, 0x01u},\r
+ {0xA7u, 0x02u},\r
+ {0xA9u, 0x02u},\r
+ {0xADu, 0x01u},\r
+ {0xB3u, 0x10u},\r
+ {0xB5u, 0x20u},\r
+ {0xB7u, 0x04u},\r
+ {0xC0u, 0xFBu},\r
+ {0xC2u, 0xDCu},\r
+ {0xC4u, 0xF0u},\r
+ {0xCAu, 0xD3u},\r
+ {0xCCu, 0xF7u},\r
+ {0xCEu, 0xF6u},\r
+ {0xD0u, 0xE0u},\r
+ {0xD2u, 0x30u},\r
+ {0xEAu, 0x08u},\r
+ {0xEEu, 0x06u},\r
+ {0x8Eu, 0x20u},\r
+ {0xA0u, 0x80u},\r
+ {0xA4u, 0x10u},\r
+ {0xA6u, 0x20u},\r
+ {0xA8u, 0x01u},\r
+ {0xAEu, 0x01u},\r
+ {0xB3u, 0x08u},\r
+ {0xB6u, 0x04u},\r
+ {0xB7u, 0x40u},\r
+ {0xE0u, 0x30u},\r
+ {0xE8u, 0x10u},\r
+ {0xEAu, 0x60u},\r
{0xEEu, 0x02u},\r
- {0xB2u, 0x10u},\r
- {0xB3u, 0x01u},\r
- {0xB4u, 0x04u},\r
- {0xEAu, 0x90u},\r
- {0xEEu, 0x20u},\r
+ {0xA8u, 0x80u},\r
+ {0xB0u, 0x10u},\r
+ {0xECu, 0x80u},\r
{0x12u, 0x08u},\r
{0x15u, 0x80u},\r
- {0x17u, 0x01u},\r
- {0x33u, 0x01u},\r
- {0x36u, 0x88u},\r
- {0x39u, 0x84u},\r
- {0x3Du, 0x41u},\r
- {0x40u, 0x08u},\r
- {0x59u, 0x12u},\r
- {0x5Fu, 0x02u},\r
- {0x61u, 0x02u},\r
+ {0x17u, 0x04u},\r
+ {0x33u, 0x04u},\r
+ {0x36u, 0x28u},\r
+ {0x39u, 0x88u},\r
+ {0x3Du, 0x44u},\r
+ {0x43u, 0x80u},\r
+ {0x56u, 0x08u},\r
+ {0x5Au, 0x08u},\r
+ {0x5Cu, 0x08u},\r
+ {0x61u, 0x10u},\r
{0x65u, 0x04u},\r
- {0x81u, 0x40u},\r
- {0x87u, 0x02u},\r
- {0x8Du, 0x10u},\r
+ {0x81u, 0x80u},\r
+ {0x83u, 0x10u},\r
+ {0x87u, 0x80u},\r
+ {0x89u, 0x80u},\r
+ {0x8Au, 0x04u},\r
{0xC4u, 0xE0u},\r
{0xCCu, 0xE0u},\r
{0xCEu, 0xF0u},\r
{0xD0u, 0x10u},\r
- {0xD4u, 0x80u},\r
+ {0xD4u, 0x40u},\r
{0xD6u, 0xC0u},\r
{0xD8u, 0xC0u},\r
- {0xE6u, 0x60u},\r
- {0x31u, 0x22u},\r
+ {0xE2u, 0x20u},\r
+ {0xE6u, 0x90u},\r
+ {0x30u, 0x20u},\r
+ {0x32u, 0x04u},\r
+ {0x34u, 0x01u},\r
{0x36u, 0x40u},\r
- {0x37u, 0x04u},\r
- {0x54u, 0x02u},\r
- {0x56u, 0x80u},\r
- {0x59u, 0x40u},\r
- {0x63u, 0x80u},\r
- {0x85u, 0x04u},\r
- {0x95u, 0x04u},\r
+ {0x51u, 0x80u},\r
+ {0x57u, 0x10u},\r
+ {0x59u, 0x80u},\r
+ {0x62u, 0x08u},\r
+ {0x81u, 0x04u},\r
+ {0x82u, 0x08u},\r
+ {0x84u, 0x08u},\r
+ {0x8Au, 0x08u},\r
+ {0x95u, 0x4Cu},\r
+ {0x99u, 0x80u},\r
{0x9Cu, 0x08u},\r
- {0x9Du, 0x02u},\r
- {0xA6u, 0x80u},\r
- {0xA9u, 0x04u},\r
- {0xADu, 0x01u},\r
- {0xB1u, 0x02u},\r
+ {0x9Du, 0x14u},\r
+ {0x9Eu, 0x08u},\r
+ {0xA1u, 0x80u},\r
+ {0xA3u, 0x10u},\r
+ {0xA6u, 0x20u},\r
{0xCCu, 0xF0u},\r
- {0xD4u, 0xC0u},\r
- {0xD6u, 0x20u},\r
+ {0xD4u, 0xE0u},\r
{0xD8u, 0x40u},\r
- {0xE6u, 0x40u},\r
- {0xEAu, 0x10u},\r
- {0xEEu, 0x80u},\r
- {0x12u, 0x80u},\r
- {0x63u, 0x01u},\r
- {0x83u, 0x41u},\r
- {0x8Du, 0x02u},\r
- {0x9Cu, 0x08u},\r
- {0x9Du, 0x42u},\r
- {0x9Fu, 0x04u},\r
- {0xA5u, 0x22u},\r
- {0xA6u, 0xC0u},\r
- {0xA7u, 0x40u},\r
- {0xA8u, 0x02u},\r
- {0xAAu, 0x80u},\r
+ {0xE2u, 0x20u},\r
+ {0xE6u, 0x90u},\r
+ {0x12u, 0x20u},\r
+ {0x81u, 0x40u},\r
+ {0x85u, 0x04u},\r
+ {0x95u, 0x4Cu},\r
+ {0x96u, 0x08u},\r
+ {0x9Cu, 0x01u},\r
+ {0x9Du, 0x10u},\r
+ {0xA4u, 0x20u},\r
+ {0xA6u, 0x60u},\r
{0xC4u, 0x10u},\r
- {0xD6u, 0x40u},\r
- {0xE2u, 0xA0u},\r
- {0xEAu, 0xA0u},\r
- {0x83u, 0x04u},\r
- {0x85u, 0x20u},\r
- {0x89u, 0x42u},\r
- {0x9Cu, 0x08u},\r
- {0x9Du, 0x41u},\r
- {0x9Fu, 0x04u},\r
- {0xA5u, 0x22u},\r
+ {0xE2u, 0x10u},\r
+ {0xE6u, 0x20u},\r
+ {0x73u, 0x01u},\r
+ {0x84u, 0x20u},\r
+ {0x86u, 0x24u},\r
+ {0x8Fu, 0x01u},\r
+ {0x95u, 0x04u},\r
+ {0x96u, 0x08u},\r
+ {0x9Du, 0x10u},\r
+ {0xA4u, 0x20u},\r
{0xA6u, 0x40u},\r
- {0xA9u, 0x01u},\r
- {0xE2u, 0x90u},\r
- {0xE8u, 0x20u},\r
- {0x09u, 0x40u},\r
- {0x0Fu, 0x20u},\r
- {0x13u, 0x08u},\r
- {0x51u, 0x08u},\r
- {0x53u, 0x02u},\r
- {0x57u, 0x20u},\r
- {0x5Cu, 0x40u},\r
- {0x81u, 0x08u},\r
+ {0xACu, 0x01u},\r
+ {0xDCu, 0x20u},\r
+ {0xE2u, 0x40u},\r
+ {0xE6u, 0x50u},\r
+ {0xEAu, 0x40u},\r
+ {0x09u, 0x80u},\r
+ {0x0Fu, 0x80u},\r
+ {0x10u, 0x10u},\r
+ {0x53u, 0x80u},\r
+ {0x54u, 0x04u},\r
+ {0x59u, 0x20u},\r
+ {0x5Fu, 0x80u},\r
+ {0x84u, 0x10u},\r
+ {0x8Fu, 0x40u},\r
{0xC2u, 0x06u},\r
{0xC4u, 0x08u},\r
{0xD4u, 0x07u},\r
{0xD6u, 0x04u},\r
- {0x03u, 0x08u},\r
- {0x06u, 0x08u},\r
- {0x07u, 0x80u},\r
- {0x0Bu, 0x84u},\r
- {0x0Cu, 0x08u},\r
- {0x0Du, 0x10u},\r
- {0x82u, 0x08u},\r
- {0x84u, 0x08u},\r
- {0x87u, 0x40u},\r
- {0x8Bu, 0x04u},\r
+ {0xE6u, 0x02u},\r
+ {0x00u, 0x02u},\r
+ {0x03u, 0x01u},\r
+ {0x04u, 0x42u},\r
+ {0x0Bu, 0x22u},\r
+ {0x0Eu, 0x01u},\r
+ {0x0Fu, 0x20u},\r
+ {0x85u, 0x20u},\r
+ {0x86u, 0x01u},\r
{0x8Cu, 0x40u},\r
- {0x8Fu, 0x08u},\r
- {0x94u, 0x40u},\r
- {0xA1u, 0x40u},\r
- {0xA3u, 0x10u},\r
- {0xA7u, 0x02u},\r
- {0xABu, 0x08u},\r
- {0xB3u, 0x20u},\r
- {0xC0u, 0x07u},\r
+ {0x9Du, 0x20u},\r
+ {0x9Fu, 0x01u},\r
+ {0xA4u, 0x04u},\r
+ {0xAFu, 0x81u},\r
+ {0xB3u, 0x80u},\r
+ {0xB5u, 0x80u},\r
+ {0xC0u, 0x0Fu},\r
{0xC2u, 0x0Fu},\r
- {0xE0u, 0x02u},\r
- {0xE2u, 0x08u},\r
- {0xE6u, 0x04u},\r
- {0xE8u, 0x01u},\r
+ {0xE2u, 0x02u},\r
+ {0xEAu, 0x08u},\r
+ {0xECu, 0x04u},\r
{0x8Fu, 0x10u},\r
- {0xA1u, 0x40u},\r
+ {0x90u, 0x02u},\r
{0xA3u, 0x10u},\r
- {0xABu, 0x82u},\r
- {0xB1u, 0x10u},\r
+ {0xA4u, 0x04u},\r
+ {0xABu, 0x01u},\r
+ {0xB0u, 0x01u},\r
+ {0xB3u, 0x10u},\r
{0xE2u, 0x08u},\r
- {0xEEu, 0x04u},\r
- {0x09u, 0x40u},\r
- {0x0Bu, 0x80u},\r
- {0x0Fu, 0x41u},\r
- {0x83u, 0x01u},\r
- {0x87u, 0x40u},\r
- {0x89u, 0x40u},\r
- {0xB1u, 0x40u},\r
+ {0xEAu, 0x05u},\r
+ {0x09u, 0x02u},\r
+ {0x0Bu, 0x08u},\r
+ {0x0Eu, 0x04u},\r
+ {0x0Fu, 0x40u},\r
+ {0x80u, 0x01u},\r
+ {0x85u, 0x02u},\r
+ {0x87u, 0x04u},\r
+ {0x90u, 0x02u},\r
+ {0x96u, 0x04u},\r
+ {0xA4u, 0x04u},\r
+ {0xAEu, 0x04u},\r
{0xC2u, 0x0Fu},\r
- {0xE6u, 0x04u},\r
- {0xEEu, 0x04u},\r
- {0x88u, 0x08u},\r
- {0x9Cu, 0x08u},\r
- {0x9Du, 0x01u},\r
- {0xA3u, 0x20u},\r
+ {0x95u, 0x04u},\r
+ {0x9Du, 0x10u},\r
+ {0xA2u, 0x20u},\r
{0xAEu, 0x40u},\r
- {0xB3u, 0x20u},\r
{0xEEu, 0x40u},\r
- {0x05u, 0x01u},\r
- {0x57u, 0x21u},\r
- {0x9Du, 0x01u},\r
- {0xA3u, 0x21u},\r
- {0xAFu, 0x01u},\r
+ {0x07u, 0x40u},\r
+ {0x52u, 0x20u},\r
+ {0x57u, 0x80u},\r
+ {0x85u, 0x04u},\r
+ {0x8Fu, 0x80u},\r
+ {0x95u, 0x04u},\r
+ {0x9Fu, 0x40u},\r
+ {0xA2u, 0x20u},\r
+ {0xA9u, 0x10u},\r
+ {0xABu, 0x40u},\r
{0xC0u, 0x20u},\r
- {0xD4u, 0x40u},\r
- {0xD6u, 0x20u},\r
- {0xEEu, 0x10u},\r
+ {0xD4u, 0x60u},\r
+ {0xE6u, 0x40u},\r
+ {0xECu, 0x80u},\r
+ {0xEEu, 0x20u},\r
+ {0x88u, 0x04u},\r
+ {0xA4u, 0x04u},\r
{0xAFu, 0x40u},\r
- {0x00u, 0x03u},\r
- {0x08u, 0x03u},\r
- {0x0Au, 0x03u},\r
- {0x0Eu, 0x02u},\r
- {0x10u, 0x01u},\r
- {0x1Au, 0x01u},\r
+ {0xE0u, 0x04u},\r
+ {0x10u, 0x03u},\r
+ {0x1Au, 0x03u},\r
{0x00u, 0xFDu},\r
{0x01u, 0xABu},\r
{0x02u, 0x02u},\r
uint16 size;\r
} CYPACKED_ATTR cfg_memset_t;\r
\r
+\r
+ CYPACKED typedef struct {\r
+ void CYFAR *dest;\r
+ const void CYCODE *src;\r
+ uint16 size;\r
+ } CYPACKED_ATTR cfg_memcpy_t;\r
+\r
static const cfg_memset_t CYCODE cfg_memset_list [] = {\r
/* address, size */\r
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},\r
{(void CYFAR *)(CYREG_PRT1_DR), 16u},\r
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},\r
- {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 512u},\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P3_U1_BASE), 1408u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},\r
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},\r
- {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},\r
+ {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},\r
+ };\r
+\r
+ /* UDB_1_1_1_CONFIG Address: CYDEV_UCFG_B1_P3_U0_BASE Size (bytes): 128 */\r
+ static const uint8 CYCODE BS_UDB_1_1_1_CONFIG_VAL[] = {\r
+ 0x01u, 0x00u, 0x00u, 0x75u, 0x04u, 0x00u, 0x00u, 0x08u, 0x08u, 0x88u, 0x61u, 0x64u, 0x01u, 0x64u, 0x00u, 0x88u, \r
+ 0x10u, 0x24u, 0x00u, 0x00u, 0x00u, 0x03u, 0x00u, 0x70u, 0x00u, 0x07u, 0x40u, 0x10u, 0x01u, 0xECu, 0x00u, 0x00u, \r
+ 0xA2u, 0xECu, 0x08u, 0x00u, 0x01u, 0xACu, 0x00u, 0x40u, 0x07u, 0x00u, 0xD8u, 0x00u, 0x01u, 0x40u, 0x00u, 0x02u, \r
+ 0x00u, 0x80u, 0x3Fu, 0x71u, 0xE0u, 0x08u, 0x00u, 0x07u, 0x08u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x00u, 0x04u, 0x11u, \r
+ 0x34u, 0x02u, 0x50u, 0x00u, 0x06u, 0xDEu, 0xFCu, 0xBDu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, \r
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, \r
+ 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, \r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};\r
+\r
+ /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */\r
+ static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {\r
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x00u, 0x02u, 0x01u};\r
+\r
+ static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {\r
+ /* dest, src, size */\r
+ {(void CYFAR *)(CYDEV_UCFG_B1_P3_U0_BASE), BS_UDB_1_1_1_CONFIG_VAL, 128u},\r
+ {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},\r
};\r
\r
uint8 CYDATA i;\r
CYMEMZERO(ms->address, (uint32)(ms->size));\r
}\r
\r
+ /* Copy device configuration data into registers */\r
+ for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)\r
+ {\r
+ const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];\r
+ void * CYDATA destPtr = mc->dest;\r
+ const void CYCODE * CYDATA srcPtr = mc->src;\r
+ uint16 CYDATA numBytes = mc->size;\r
+ CYCONFIGCPYCODE(destPtr, srcPtr, numBytes);\r
+ }\r
+\r
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);\r
\r
/* Perform normal device configuration. Order is not critical for these items. */\r
.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0\r
.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0\r
\r
+/* SCSI_Parity_Error */\r
+.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01\r
+.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB10_11_ST\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01\r
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB10_MSK\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB10_ACTL\r
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB10_ST\r
+\r
/* USBFS_bus_reset */\r
.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0\r
/* SCSI_CTL_PHASE */\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL\r
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK\r
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK\r
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL\r
\r
/* SCSI_Out_Bits */\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02\r
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1\r
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04\r
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80\r
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL\r
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK\r
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK\r
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
\r
/* USBFS_arb_int */\r
.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
/* SCSI_Out_Ctl */\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB07_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB07_CTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL\r
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB07_MSK\r
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK\r
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL\r
\r
/* SCSI_Out_DBx */\r
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG\r
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK\r
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL\r
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST\r
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_RxStsReg__4__POS, 4\r
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20\r
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40\r
.set SDCard_BSPIM_RxStsReg__6__POS, 6\r
.set SDCard_BSPIM_RxStsReg__MASK, 0x70\r
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB05_MSK\r
-.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB05_ST_CTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB05_ST_CTL\r
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB05_ST\r
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB05_MSK\r
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL\r
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB05_ST\r
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01\r
.set SDCard_BSPIM_TxStsReg__0__POS, 0\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST\r
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02\r
.set SDCard_BSPIM_TxStsReg__1__POS, 1\r
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04\r
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10\r
.set SDCard_BSPIM_TxStsReg__4__POS, 4\r
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F\r
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB06_MSK\r
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB06_ST\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB05_06_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB05_06_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB05_06_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB05_06_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB05_06_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB05_06_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB05_A0_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB05_A0\r
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB05_A1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB05_D0_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB05_D0\r
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB05_D1\r
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB05_F0_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB05_F0\r
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB05_F1\r
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL\r
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK\r
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL\r
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB06_07_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB06_07_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB06_07_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB06_07_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB06_07_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB06_07_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB06_A0_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB06_A0\r
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB06_A1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB06_D0_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB06_D0\r
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB06_D1\r
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB06_ACTL\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB06_F0_F1\r
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB06_F0\r
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB06_F1\r
\r
/* USBFS_dp_int */\r
.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
/* scsiTarget */\r
.set scsiTarget_StatusReg__0__MASK, 0x01\r
.set scsiTarget_StatusReg__0__POS, 0\r
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL\r
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST\r
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL\r
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST\r
.set scsiTarget_StatusReg__1__MASK, 0x02\r
.set scsiTarget_StatusReg__1__POS, 1\r
.set scsiTarget_StatusReg__2__MASK, 0x04\r
.set scsiTarget_StatusReg__4__MASK, 0x10\r
.set scsiTarget_StatusReg__4__POS, 4\r
.set scsiTarget_StatusReg__MASK, 0x1F\r
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB00_MSK\r
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL\r
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB00_ST\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST\r
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB03_MSK\r
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL\r
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB03_ST\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL\r
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL\r
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK\r
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK\r
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB03_CTL\r
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL\r
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB03_CTL\r
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL\r
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB03_MSK\r
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB03_04_A0\r
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB03_04_A1\r
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB03_04_D0\r
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB03_04_D1\r
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL\r
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB03_04_F0\r
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB03_04_F1\r
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB03_A0_A1\r
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB03_A0\r
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB03_A1\r
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB03_D0_D1\r
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB03_D0\r
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB03_D1\r
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB03_ACTL\r
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB03_F0_F1\r
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB03_F0\r
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB03_F1\r
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL\r
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB11_MSK\r
+.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL\r
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL\r
+.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL\r
+.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL\r
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB11_ST\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST\r
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB04_MSK\r
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL\r
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB04_ST\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL\r
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL\r
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK\r
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK\r
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB04_CTL\r
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB04_CTL\r
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL\r
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB04_MSK\r
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB04_05_A0\r
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB04_05_A1\r
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB04_05_D0\r
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB04_05_D1\r
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL\r
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB04_05_F0\r
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB04_05_F1\r
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB04_A0_A1\r
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB04_A0\r
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB04_A1\r
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB04_D0_D1\r
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB04_D0\r
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB04_D1\r
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL\r
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB04_F0_F1\r
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB04_F0\r
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB04_F1\r
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL\r
\r
/* USBFS_ep_0 */\r
.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0\r
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
+/* SCSI_Parity_Error */\r
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB10_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB10_ST\r
+\r
/* USBFS_bus_reset */\r
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
/* SCSI_CTL_PHASE */\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
\r
/* SCSI_Out_Bits */\r
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
\r
/* USBFS_arb_int */\r
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
/* SCSI_Out_Ctl */\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
\r
/* SCSI_Out_DBx */\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB05_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB05_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB05_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB05_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB05_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB05_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1\r
\r
/* USBFS_dp_int */\r
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
/* scsiTarget */\r
scsiTarget_StatusReg__0__MASK EQU 0x01\r
scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST\r
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST\r
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0\r
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1\r
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0\r
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1\r
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0\r
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1\r
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1\r
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0\r
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1\r
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1\r
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0\r
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1\r
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1\r
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0\r
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1\r
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL\r
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB04_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB04_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB04_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB04_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB04_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB04_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB04_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
\r
/* USBFS_ep_0 */\r
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0\r
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0\r
\r
+; SCSI_Parity_Error\r
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB10_11_ST\r
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01\r
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB10_MSK\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL\r
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB10_ST\r
+\r
; USBFS_bus_reset\r
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0\r
; SCSI_CTL_PHASE\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL\r
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK\r
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK\r
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL\r
\r
; SCSI_Out_Bits\r
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK\r
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02\r
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1\r
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04\r
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6\r
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80\r
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL\r
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF\r
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK\r
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK\r
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
\r
; USBFS_arb_int\r
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
; SCSI_Out_Ctl\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01\r
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL\r
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01\r
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK\r
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK\r
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL\r
\r
; SCSI_Out_DBx\r
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG\r
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK\r
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL\r
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST\r
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_RxStsReg__4__POS EQU 4\r
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20\r
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40\r
SDCard_BSPIM_RxStsReg__6__POS EQU 6\r
SDCard_BSPIM_RxStsReg__MASK EQU 0x70\r
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
-SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB05_ST_CTL\r
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB05_MSK\r
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL\r
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB05_ST\r
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01\r
SDCard_BSPIM_TxStsReg__0__POS EQU 0\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST\r
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02\r
SDCard_BSPIM_TxStsReg__1__POS EQU 1\r
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04\r
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10\r
SDCard_BSPIM_TxStsReg__4__POS EQU 4\r
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F\r
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK\r
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB05_06_A0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB05_06_A1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB05_06_D0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB05_06_D1\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB05_06_F0\r
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB05_06_F1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB05_A0_A1\r
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB05_A0\r
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB05_A1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB05_D0_D1\r
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB05_D0\r
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB05_D1\r
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB05_F0_F1\r
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB05_F0\r
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB05_F1\r
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL\r
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK\r
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL\r
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB06_07_A0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB06_07_A1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB06_07_D0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB06_07_D1\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB06_07_F0\r
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB06_07_F1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB06_A0_A1\r
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB06_A0\r
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB06_A1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB06_D0_D1\r
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB06_D0\r
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB06_D1\r
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL\r
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB06_F0_F1\r
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB06_F0\r
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB06_F1\r
\r
; USBFS_dp_int\r
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
; scsiTarget\r
scsiTarget_StatusReg__0__MASK EQU 0x01\r
scsiTarget_StatusReg__0__POS EQU 0\r
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL\r
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST\r
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL\r
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST\r
scsiTarget_StatusReg__1__MASK EQU 0x02\r
scsiTarget_StatusReg__1__POS EQU 1\r
scsiTarget_StatusReg__2__MASK EQU 0x04\r
scsiTarget_StatusReg__4__MASK EQU 0x10\r
scsiTarget_StatusReg__4__POS EQU 4\r
scsiTarget_StatusReg__MASK EQU 0x1F\r
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB00_MSK\r
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL\r
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB00_ST\r
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST\r
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB03_ST\r
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL\r
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK\r
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB03_CTL\r
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB03_CTL\r
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL\r
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB03_MSK\r
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB03_04_A0\r
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB03_04_A1\r
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB03_04_D0\r
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB03_04_D1\r
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL\r
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB03_04_F0\r
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB03_04_F1\r
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB03_A0_A1\r
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB03_A0\r
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB03_A1\r
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB03_D0_D1\r
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB03_D0\r
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB03_D1\r
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL\r
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB03_F0_F1\r
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB03_F0\r
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB03_F1\r
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL\r
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB11_MSK\r
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL\r
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL\r
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL\r
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL\r
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB11_ST\r
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST\r
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB04_MSK\r
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB04_ST\r
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL\r
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK\r
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB04_CTL\r
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB04_CTL\r
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL\r
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB04_MSK\r
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0\r
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1\r
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0\r
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1\r
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL\r
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0\r
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1\r
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1\r
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB04_A0\r
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB04_A1\r
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1\r
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB04_D0\r
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB04_D1\r
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL\r
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1\r
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB04_F0\r
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB04_F1\r
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL\r
\r
; USBFS_ep_0\r
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0\r
const uint8 cy_meta_loadable[] = {\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
- 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x52u, 0x03u,\r
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x60u, 0x03u,\r
0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,\r
#include <SD_TX_DMA_COMPLETE.h>\r
#include <SCSI_RX_DMA_dma.h>\r
#include <SCSI_RX_DMA_COMPLETE.h>\r
+#include <SCSI_Parity_Error.h>\r
#include <USBFS_Dm_aliases.h>\r
#include <USBFS_Dm.h>\r
#include <USBFS_Dp_aliases.h>\r
--- /dev/null
+<?xml version="1.0" encoding="utf-8"?>
+<!--DO NOT EDIT. This document is generated by PSoC Creator design builds.-->
+<PSoCCreatorIdeExport Version="1">
+ <Device Part="CY8C5267AXI-LP051" Processor="CortexM3" DeviceID="2E133069" />
+ <Toolchains>
+ <Toolchain Name="ARM GCC" Selected="True">
+ <Tool Name="prebuild" Command="" Options="" />
+ <Tool Name="assembler" Command="arm-none-eabi-as.exe" Options="-I. -I./Generated_Source/PSoC5 -mcpu=cortex-m3 -mthumb -g -alh=${OutputDir}/${CompileFile}.lst " />
+ <Tool Name="compiler" Command="arm-none-eabi-gcc.exe" Options="-I. -I./Generated_Source/PSoC5 -Wno-main -mcpu=cortex-m3 -mthumb -Wall -g -D NDEBUG -Wa,-alh=${OutputDir}\${CompileFile}.lst -Os -ffunction-sections " />
+ <Tool Name="linker" Command="arm-none-eabi-gcc.exe" Options="-mthumb -march=armv7-m -mfix-cortex-m3-ldrd -T .\Generated_Source\PSoC5\cm3gcc.ld -g -Wl,-Map,${OutputDir}\${ProjectShortName}.map -specs=nano.specs -Wl,--gc-sections " />
+ <Tool Name="postbuild" Command="" Options="" />
+ </Toolchain>
+ <Toolchain Name="ARM Keil MDK" Selected="False">
+ <Tool Name="prebuild" Command="" Options="" />
+ <Tool Name="assembler" Command="armasm.exe" Options="-i. -iGenerated_Source/PSoC5 --diag_style=gnu --thumb --cpu=Cortex-M3 -g --list=${OutputDir}/${CompileFile}.lst " />
+ <Tool Name="compiler" Command="armcc.exe" Options="-I. -I./Generated_Source/PSoC5 --diag_suppress=951 --diag_style=gnu --cpu=Cortex-M3 -g -D NDEBUG --signed_chars --list -Ospace --split_sections " />
+ <Tool Name="linker" Command="armlink.exe" Options="--diag_style=gnu --no_startup --cpu=Cortex-M3 --scatter .\Generated_Source\PSoC5\Cm3RealView.scat --map --list ${OutputDir}\${ProjectShortName}.map " />
+ <Tool Name="postbuild" Command="" Options="" />
+ </Toolchain>
+ </Toolchains>
+ <Project Name="SCSI2SD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" Version="4.0" Type="Bootloadable">
+ <CMSIS_SVD_File>SCSI2SD.svd</CMSIS_SVD_File>
+ <Datasheet />
+ <LinkerFiles>
+ <LinkerFile Toolchain="ARM GCC">.\Generated_Source\PSoC5\cm3gcc.ld</LinkerFile>
+ <LinkerFile Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\Cm3RealView.scat</LinkerFile>
+ <LinkerFile Toolchain="IAR EWARM">.\Generated_Source\PSoC5\Cm3Iar.icf</LinkerFile>
+ </LinkerFiles>
+ <Folders>
+ <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\src">
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
+ <File BuildType="BUILD" Toolchain="">..\..\src\main.c</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\diagnostic.c</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\disk.c</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\geometry.c</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\inquiry.c</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\mode.c</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\scsi.c</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\scsiPhy.c</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\bits.c</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\sd.c</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\config.c</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\led.c</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\diagnostic.h</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\disk.h</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\geometry.h</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\inquiry.h</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\led.h</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\mode.h</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\scsi.h</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\scsiPhy.h</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\sense.h</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\bits.h</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\sd.h</File>
+ <File BuildType="BUILD" Toolchain="">..\..\src\config.h</File>
+ </Files>
+ </Folder>
+ <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
+ <File BuildType="BUILD" Toolchain="">.\device.h</File>
+ </Files>
+ </Folder>
+ <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn\Generated_Source\PSoC5">
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevice.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevicegnu.inc</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevicerv.inc</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevice_trm.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevicegnu_trm.inc</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevicerv_trm.inc</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfittergnu.inc</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitterrv.inc</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_In_DBx_aliases.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Out_DBx_aliases.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MISO_aliases.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MISO.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MISO.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MOSI_aliases.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MOSI.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MOSI.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_SCK_aliases.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_SCK.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_SCK.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CS_aliases.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CS.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CS.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT1_aliases.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT1.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT1.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT2_aliases.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT2.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT2.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CD_aliases.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CD.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CD.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_In_aliases.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Out_aliases.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\LED1_aliases.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\LED1.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\LED1.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\Cm3Start.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\core_cm3_psoc5.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\core_cm3.h</File>
+ <File BuildType="BUILD" Toolchain="ARM GCC">.\Generated_Source\PSoC5\CyBootAsmGnu.s</File>
+ <File BuildType="BUILD" Toolchain="ARM RVDS">.\Generated_Source\PSoC5\CyBootAsmRv.s</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyDmac.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyDmac.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyFlash.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyFlash.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyLib.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyLib.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cypins.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyPm.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyPm.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CySpc.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CySpc.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cytypes.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyutils.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\core_cmFunc.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\core_cmInstr.h</File>
+ <File BuildType="BUILD" Toolchain="IAR EWARM">.\Generated_Source\PSoC5\CyBootAsmIar.s</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\project.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_Data_Clk.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_Data_Clk.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard_PM.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard_INT.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SDCard_PVT.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST_aliases.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN_aliases.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ATN.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST_ISR.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RST_ISR.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cymetadata.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydeviceiar.inc</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydeviceiar_trm.inc</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitteriar.inc</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydisabledsheets.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CFG_EEPROM.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CFG_EEPROM.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cybootloader.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\Bootloadable_1.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\Bootloadable_1.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_audio.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_audio.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_boot.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_cdc.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_cdc.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_cls.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_descr.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_drv.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_episr.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_hid.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_hid.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_pm.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_std.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_vnd.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_midi.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_midi.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_pvt.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_Dm_aliases.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_Dm.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_Dm.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_Dp_aliases.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_Dp.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\USBFS_Dp.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_CTL_PHASE.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_CTL_PHASE.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_CLK.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_CLK.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Out_Bits.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Out_Bits.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Out_Ctl.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Out_Ctl.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\Debug_Timer.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\Debug_Timer.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\Debug_Timer_PM.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\timer_clock.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\timer_clock.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\Debug_Timer_Interrupt.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\Debug_Timer_Interrupt.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_TX_DMA_dma.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_TX_DMA_dma.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_TX_DMA_COMPLETE.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_TX_DMA_COMPLETE.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_RX_DMA_dma.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_RX_DMA_dma.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_TX_DMA_dma.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_TX_DMA_dma.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_RX_DMA_COMPLETE.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_RX_DMA_COMPLETE.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_TX_DMA_COMPLETE.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_TX_DMA_COMPLETE.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RX_DMA_dma.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RX_DMA_dma.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RX_DMA_COMPLETE.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_RX_DMA_COMPLETE.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Parity_Error.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Parity_Error.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\prebuild.bat</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\postbuild.bat</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyElfTool.exe</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\libelf.dll</File>
+ </Files>
+ </Folder>
+ <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_GCC">
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
+ <File BuildType="BUILD" Toolchain="ARM GCC">.\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a</File>
+ </Files>
+ </Folder>
+ <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK">
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
+ <File BuildType="BUILD" Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a</File>
+ </Files>
+ </Folder>
+ <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn\Generated_Source\PSoC5\IAR">
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn">
+ <File BuildType="BUILD" Toolchain="IAR">.\Generated_Source\PSoC5\IAR\CyComponentLibrary.a</File>
+ </Files>
+ </Folder>
+ <Folder BuildType="EXCLUDE" Path=".\codegentemp">
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
+ </Folder>
+ <Folder BuildType="EXCLUDE" Path=".\ARM_GCC_441">
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
+ </Folder>
+ <Folder BuildType="EXCLUDE" Path=".\ARM_GCC_473">
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
+ </Folder>
+ <Folder BuildType="EXCLUDE" Path=".\DP8051_Keil_951">
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
+ </Folder>
+ <Folder BuildType="EXCLUDE" Path=".\DP8051">
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
+ </Folder>
+ <Folder BuildType="EXCLUDE" Path=".\CortexM0">
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
+ </Folder>
+ <Folder BuildType="EXCLUDE" Path=".\CortexM3">
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\SCSI2SD.cydsn" />
+ </Folder>
+ </Folders>
+ </Project>
+</PSoCCreatorIdeExport>
\ No newline at end of file
<?xml version="1.0" encoding="utf-8"?>\r
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">\r
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006577" bitWidth="8" desc="" />\r
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x4000647E" bitWidth="8" desc="" />\r
</block>\r
<block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" />\r
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />\r
</block>\r
- <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />\r
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />\r
</block>\r
- <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
</block>\r
- <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">\r
<block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />\r
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />\r
</block>\r
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x4000646A" bitWidth="8" desc="" />\r
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x4000648A" bitWidth="8" desc="" />\r
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x4000649A" bitWidth="8" desc="">\r
+ <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">\r
+ <value name="ENABLED" value="1" desc="Enable counter" />\r
+ <value name="DISABLED" value="0" desc="Disable counter" />\r
+ </field>\r
+ <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">\r
+ <value name="ENABLED" value="1" desc="Interrupt enabled" />\r
+ <value name="DISABLED" value="0" desc="Interrupt disabled" />\r
+ </field>\r
+ <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">\r
+ <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
+ <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
+ </field>\r
+ <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">\r
+ <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />\r
+ <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />\r
+ </field>\r
+ <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">\r
+ <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
+ <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
+ </field>\r
+ <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">\r
+ <value name="ENABLED" value="1" desc="Clear FIFO state" />\r
+ <value name="DISABLED" value="0" desc="Normal FIFO operation" />\r
+ </field>\r
+ </register>\r
+ </block>\r
+ <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">\r
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006475" bitWidth="8" desc="" />\r
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" />\r
</block>\r
<block name="SD_DAT1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_Out" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_DAT2" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
- <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
<block name="SD_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
+ <block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />\r
</blockRegMap>
\ No newline at end of file
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
<filters />\r
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">\r
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Parity_Error" persistent="">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">\r
+<dependencies>\r
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Parity_Error.c" persistent=".\Generated_Source\PSoC5\SCSI_Parity_Error.c">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="ARM_C_FILE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>\r
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">\r
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">\r
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Parity_Error.h" persistent=".\Generated_Source\PSoC5\SCSI_Parity_Error.h">\r
+<Hidden v="False" />\r
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>\r
+<build_action v="NONE" />\r
+<PropertyDeltas />\r
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>\r
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>\r
+</dependencies>\r
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
+<filters />\r
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>\r
</dependencies>\r
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>\r
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>\r
<peripheral>\r
<name>SCSI_Out_Ctl</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006577</baseAddress>\r
+ <baseAddress>0x4000647E</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x1</size>\r
<peripheral>\r
<name>SCSI_Out_Bits</name>\r
<description>No description available</description>\r
- <baseAddress>0x4000647C</baseAddress>\r
+ <baseAddress>0x4000647B</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x1</size>\r
</register>\r
</registers>\r
</peripheral>\r
+ <peripheral>\r
+ <name>SCSI_Parity_Error</name>\r
+ <description>No description available</description>\r
+ <baseAddress>0x4000646A</baseAddress>\r
+ <addressBlock>\r
+ <offset>0</offset>\r
+ <size>0x31</size>\r
+ <usage>registers</usage>\r
+ </addressBlock>\r
+ <registers>\r
+ <register>\r
+ <name>SCSI_Parity_Error_STATUS_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x0</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>SCSI_Parity_Error_MASK_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x20</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ </register>\r
+ <register>\r
+ <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>\r
+ <description>No description available</description>\r
+ <addressOffset>0x30</addressOffset>\r
+ <size>8</size>\r
+ <access>read-write</access>\r
+ <resetValue>0</resetValue>\r
+ <resetMask>0</resetMask>\r
+ <fields>\r
+ <field>\r
+ <name>FIFO0</name>\r
+ <description>FIFO0 clear</description>\r
+ <lsb>5</lsb>\r
+ <msb>5</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Enable counter</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Disable counter</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>INTRENBL</name>\r
+ <description>Enables or disables the Interrupt</description>\r
+ <lsb>4</lsb>\r
+ <msb>4</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Interrupt enabled</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Interrupt disabled</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO1LEVEL</name>\r
+ <description>FIFO level</description>\r
+ <lsb>3</lsb>\r
+ <msb>3</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO0LEVEL</name>\r
+ <description>FIFO level</description>\r
+ <lsb>2</lsb>\r
+ <msb>2</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO1CLEAR</name>\r
+ <description>FIFO clear</description>\r
+ <lsb>1</lsb>\r
+ <msb>1</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Clear FIFO state</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Normal FIFO operation</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ <field>\r
+ <name>FIFO0CLEAR</name>\r
+ <description>FIFO clear</description>\r
+ <lsb>0</lsb>\r
+ <msb>0</msb>\r
+ <access>read-write</access>\r
+ <enumeratedValues>\r
+ <enumeratedValue>\r
+ <name>ENABLED</name>\r
+ <description>Clear FIFO state</description>\r
+ <value>1</value>\r
+ </enumeratedValue>\r
+ <enumeratedValue>\r
+ <name>DISABLED</name>\r
+ <description>Normal FIFO operation</description>\r
+ <value>0</value>\r
+ </enumeratedValue>\r
+ </enumeratedValues>\r
+ </field>\r
+ </fields>\r
+ </register>\r
+ </registers>\r
+ </peripheral>\r
<peripheral>\r
<name>SCSI_CTL_PHASE</name>\r
<description>No description available</description>\r
- <baseAddress>0x40006475</baseAddress>\r
+ <baseAddress>0x40006471</baseAddress>\r
<addressBlock>\r
<offset>0</offset>\r
<size>0x1</size>\r
output REQ, // Active High, connected to SCSI bus via inverter\r
input nACK, // Active LOW, connected directly to SCSI bus.\r
input [7:0] nDBx_in, // Active LOW, connected directly to SCSI bus.\r
+ input nDBP, // Active LOW, connected directly to SCSI bus\r
input IO, // Active High, set by CPU via status register.\r
input nRST, // Active LOW, connected directly to SCSI bus.\r
input clk,\r
output tx_intr,\r
- output rx_intr\r
+ output rx_intr,\r
+ output parityErr\r
);\r
\r
\r
localparam IO_WRITE = 1'b1;\r
localparam IO_READ = 1'b0;\r
\r
+\r
+/////////////////////////////////////////////////////////////////////////////\r
+// Input filter\r
+/////////////////////////////////////////////////////////////////////////////\r
+// Do not respond to glitches in the ACK signal. This will cause us to\r
+// transfer rubbish data, or too many bytes, and generally leads to\r
+// hanging the SCSI bus. Reflected signals can cause the ACK signal\r
+// to be dirty. We don't care so much about the others as we don't\r
+// respond to them on the rising edge.\r
+// 4-stage shifter. Ass\r
+reg safeACK;\r
+reg[3:0] ackShift;\r
+always @(posedge op_clk) begin\r
+ if (ackShift[3:1] == 0) begin\r
+ safeACK <= 0;\r
+ end\r
+ else if (ackShift[3:1] == 1) begin\r
+ safeACK <= 1;\r
+ end\r
+ ackShift <= {ackShift[2:0], ~nACK};\r
+end\r
+\r
/////////////////////////////////////////////////////////////////////////////\r
// STATE MACHINE\r
/////////////////////////////////////////////////////////////////////////////\r
// Parallel output from the selected SRCA value (A0 or A1) to the ALU.\r
wire[7:0] po;\r
\r
-// Set true to trigger storing A1 into F1.\r
-wire fifoStore;\r
+// Set true to trigger storing A1 into F1. Set while in STATE_RX\r
+reg fifoStore;\r
+\r
+// Set to true on detecting a parity input while reading\r
+reg parityErrReg;\r
+// Temp values in parity calcs. We need to do it in 2 steps to avoid\r
+// timing issues and running-out-of resources\r
+reg[2:0] genParity;\r
+\r
+reg REQReg;\r
\r
// Set Output Pins\r
-assign REQ = state[1] & state[2]; // STATE_READY & STATE_RX\r
+assign REQ = REQReg; // STATE_READY & STATE_RX\r
assign DBx_out[7:0] = data;\r
assign pi[7:0] = ~nDBx_in[7:0]; // Invert active low scsi bus\r
-assign fifoStore = (state == STATE_RX) ? 1'b1 : 1'b0;\r
+assign parityErr = parityErrReg;\r
\r
\r
/////////////////////////////////////////////////////////////////////////////\r
wire f0_blk_stat; // Tx FIFO empty\r
wire f1_bus_stat; // Rx FIFO not empty\r
wire f1_blk_stat; // Rx FIFO full\r
-wire txComplete = f0_blk_stat && (state == STATE_IDLE);\r
+wire txComplete = f0_blk_stat && (state == STATE_IDLE) && ~safeACK;\r
cy_psoc3_status #(.cy_force_order(1), .cy_md_select(8'h00)) StatusReg\r
(\r
/* input */ .clock(op_clk),\r
// and output FIFO is not full.\r
// Note that output FIFO is unused in TX mode.\r
if (!nRST) state <= STATE_IDLE;\r
- else if (nACK & !f0_blk_stat)\r
+ else if (~safeACK & !f0_blk_stat && ((IO == IO_WRITE) || !f1_blk_stat))\r
state <= STATE_FIFOLOAD;\r
else\r
state <= STATE_IDLE;\r
\r
// Clear our output pins\r
data <= 8'b0;\r
+ \r
+ REQReg <= 1'b0;\r
+ fifoStore <= 1'b0;\r
+ parityErrReg <= 1'b0;\r
end\r
\r
STATE_FIFOLOAD:\r
if (!nRST) state <= STATE_IDLE;\r
- else state <= IO == IO_WRITE ? STATE_TX : STATE_READY;\r
+ else if (IO == IO_WRITE)\r
+ state <= STATE_TX;\r
+ else begin\r
+ state <= STATE_READY;\r
+ REQReg <= 1'b1;\r
+ end\r
\r
STATE_TX:\r
begin\r
\r
STATE_DESKEW:\r
if (!nRST) state <= STATE_IDLE;\r
- else if(deskewComplete) state <= STATE_READY;\r
- else state <= STATE_DESKEW;\r
+ else if(deskewComplete) begin\r
+ state <= STATE_READY;\r
+ REQReg <= 1'b1;\r
+ end else state <= STATE_DESKEW;\r
\r
STATE_READY:\r
if (!nRST) state <= STATE_IDLE;\r
- else if (~nACK && ((IO == IO_WRITE) || !f1_blk_stat)) state <= STATE_RX;\r
- else state <= STATE_READY;\r
+ else if (safeACK) begin\r
+ state <= STATE_RX;\r
+ fifoStore <= 1'b1;\r
\r
- STATE_RX: // same code here as for the IDLE state, as we make\r
- // a quick run back to the next byte if possible.\r
- if (!nRST) state <= STATE_IDLE;\r
- else if (nACK & !f0_blk_stat)\r
- state <= STATE_FIFOLOAD;\r
- else\r
- state <= STATE_IDLE;\r
+ genParity[0] <= (~nDBP) ^ 1'b1 ^ ~nDBx_in[7] ^ ~nDBx_in[6];\r
+ genParity[1] <= ~nDBx_in[5] ^ ~nDBx_in[4] ^ ~nDBx_in[3];\r
+ genParity[2] <= ~nDBx_in[2] ^ ~nDBx_in[1] ^ ~nDBx_in[0];\r
+ end else state <= STATE_READY;\r
+\r
+ STATE_RX:\r
+ begin\r
+ state <= STATE_IDLE;\r
+ REQReg <= 1'b0;\r
+ fifoStore <= 1'b0;\r
+ parityErrReg <= 1'b0;\r
+ data <= 8'b0;\r
+ if (IO == IO_READ) begin\r
+ parityErrReg <= ^genParity[2:0];\r
+ end\r
+ end\r
\r
default: state <= STATE_IDLE;\r
endcase\r
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<CYPRESSTAG name="CyDsfit arguments...">\r
-cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE</CYPRESSTAG>\r
+cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -p Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE</CYPRESSTAG>\r
<CYPRESSTAG name="Design elaboration results...">\r
</CYPRESSTAG>\r
-Elaboration phase: Elapsed time ==> 7s.623ms\r
+Elaboration phase: Elapsed time ==> 8s.312ms\r
<CYPRESSTAG name="HDL generation results...">\r
</CYPRESSTAG>\r
-HDL generation phase: Elapsed time ==> 0s.655ms\r
+HDL generation phase: Elapsed time ==> 1s.015ms\r
<CYPRESSTAG name="Synthesis results...">\r
\r
| | | | | | |\r
======================================================================\r
Compiling: USB_Bootloader.v\r
Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe\r
-Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
+Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
======================================================================\r
\r
======================================================================\r
Compiling: USB_Bootloader.v\r
Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe\r
-Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
+Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
======================================================================\r
\r
======================================================================\r
Compiling: USB_Bootloader.v\r
Program : vlogfe\r
-Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
+Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
======================================================================\r
\r
vlogfe V6.3 IR 41: Verilog parser\r
-Sun Jul 20 15:00:50 2014\r
+Thu Aug 28 22:24:58 2014\r
\r
\r
======================================================================\r
======================================================================\r
\r
vpp V6.3 IR 41: Verilog Pre-Processor\r
-Sun Jul 20 15:00:50 2014\r
+Thu Aug 28 22:24:59 2014\r
\r
\r
vpp: No errors.\r
======================================================================\r
Compiling: USB_Bootloader.v\r
Program : tovif\r
-Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
+Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
======================================================================\r
\r
tovif V6.3 IR 41: High-level synthesis\r
-Sun Jul 20 15:00:51 2014\r
+Thu Aug 28 22:25:00 2014\r
\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.\r
-Linking 'Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'.\r
-Linking 'Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'.\r
+Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'.\r
+Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'.\r
\r
tovif: No errors.\r
\r
======================================================================\r
Compiling: USB_Bootloader.v\r
Program : topld\r
-Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
+Options : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v\r
======================================================================\r
\r
topld V6.3 IR 41: Synthesis and optimization\r
-Sun Jul 20 15:00:52 2014\r
+Thu Aug 28 22:25:02 2014\r
\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\std.vhd'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\cypress.vhd'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'.\r
-Linking 'Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'.\r
-Linking 'Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'.\r
+Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'.\r
+Linking 'Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'.\r
Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'.\r
\r
----------------------------------------------------------\r
\r
CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\r
Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\warp\bin/warp.exe\r
-Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
+Warp Arguments : -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog\r
</CYPRESSTAG>\r
-Warp synthesis phase: Elapsed time ==> 8s.781ms\r
+Warp synthesis phase: Elapsed time ==> 10s.236ms\r
<CYPRESSTAG name="Fitter results...">\r
<CYPRESSTAG name="Fitter startup details...">\r
-cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Sunday, 20 July 2014 15:00:57\r
-Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog\r
+cyp3fit: V3.0.0.1539, Family: PSoC3, Started at: Thursday, 28 August 2014 22:25:08\r
+Options: -yv2 -v3 -ygs -q10 -o2 -.fftcfgtype=LE -ya -.fftprj=Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v3\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Design parsing">\r
-Design parsing phase: Elapsed time ==> 0s.031ms\r
+Design parsing phase: Elapsed time ==> 0s.344ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Tech mapping">\r
<CYPRESSTAG name="Initial Mapping" icon="FILE_RPT_TECHM">\r
SAR Fixed Blocks : 0 : 1 : 1 : 0.00%\r
</CYPRESSTAG>\r
Technology Mapping: Elapsed time ==> 0s.406ms\r
-Tech mapping phase: Elapsed time ==> 0s.687ms\r
+Tech mapping phase: Elapsed time ==> 0s.702ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Analog Placement">\r
Initial Analog Placement Results:\r
IO_7@[IOP=(15)][IoId=(7)] : \USBFS:Dm(0)\ (fixed)\r
IO_6@[IOP=(15)][IoId=(6)] : \USBFS:Dp(0)\ (fixed)\r
USB[0]@[FFB(USB,0)] : \USBFS:USB\\r
-Analog Placement phase: Elapsed time ==> 0s.094ms\r
+Analog Placement phase: Elapsed time ==> 0s.109ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Analog Routing">\r
Analog Routing phase: Elapsed time ==> 0s.000ms\r
IsVddaHalfUsedForComp = False\r
IsVddaHalfUsedForSar0 = False\r
IsVddaHalfUsedForSar1 = False\r
-Analog Code Generation phase: Elapsed time ==> 1s.405ms\r
+Analog Code Generation phase: Elapsed time ==> 1s.453ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Digital Placement">\r
<CYPRESSTAG name="Detailed placement messages">\r
I2659: No Constrained paths were found. The placer will run in non-timing driven mode.\r
-I2076: Total run-time: 5.3 sec.\r
+I2076: Total run-time: 4.1 sec.\r
\r
</CYPRESSTAG>\r
<CYPRESSTAG name="PLD Packing">\r
Initial Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>\r
<CYPRESSTAG name="Final Partitioning Summary">\r
Final Partitioning Summary not displayed at this verbose level.</CYPRESSTAG>\r
-Partitioning: Elapsed time ==> 0s.079ms\r
+Partitioning: Elapsed time ==> 0s.063ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Simulated Annealing">\r
-Annealing: Elapsed time ==> 0s.000ms\r
+Annealing: Elapsed time ==> 0s.014ms\r
<CYPRESSTAG name="Simulated Annealing Results">\r
The seed used for moves was 114161200.\r
Inital cost was 120, final cost is 120 (0.00% improvement).</CYPRESSTAG>\r
</CYPRESSTAG>\r
</CYPRESSTAG>\r
</CYPRESSTAG>\r
-Digital component placer commit/Report: Elapsed time ==> 0s.373ms\r
-Digital Placement phase: Elapsed time ==> 9s.093ms\r
+Digital component placer commit/Report: Elapsed time ==> 0s.359ms\r
+Digital Placement phase: Elapsed time ==> 7s.578ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Digital Routing">\r
Routing successful.\r
-Digital Routing phase: Elapsed time ==> 8s.703ms\r
+Digital Routing phase: Elapsed time ==> 9s.796ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Bitstream and API generation">\r
-Bitstream and API generation phase: Elapsed time ==> 25s.515ms\r
+Bitstream and API generation phase: Elapsed time ==> 25s.390ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Bitstream verification">\r
-Bitstream verification phase: Elapsed time ==> 0s.125ms\r
+Bitstream verification phase: Elapsed time ==> 0s.158ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Static timing analysis">\r
Timing report is in USB_Bootloader_timing.html.\r
-Static timing analysis phase: Elapsed time ==> 3s.999ms\r
+Static timing analysis phase: Elapsed time ==> 4s.278ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Data reporting">\r
Data reporting phase: Elapsed time ==> 0s.000ms\r
</CYPRESSTAG>\r
<CYPRESSTAG name="Database update...">\r
-Design database save phase: Elapsed time ==> 0s.734ms\r
+Design database save phase: Elapsed time ==> 0s.656ms\r
</CYPRESSTAG>\r
-cydsfit: Elapsed time ==> 50s.735ms\r
+cydsfit: Elapsed time ==> 50s.921ms\r
</CYPRESSTAG>\r
-Fitter phase: Elapsed time ==> 50s.829ms\r
-API generation phase: Elapsed time ==> 23s.686ms\r
+Fitter phase: Elapsed time ==> 50s.997ms\r
+API generation phase: Elapsed time ==> 24s.640ms\r
Dependency generation phase: Elapsed time ==> 0s.859ms\r
-Cleanup phase: Elapsed time ==> 0s.609ms\r
+Cleanup phase: Elapsed time ==> 0s.844ms\r
<tr> <td class="prop"> Project :</td>\r
<td class="proptext"> USB_Bootloader</td></tr>\r
<tr> <td class="prop"> Build Time :</td>\r
-<td class="proptext"> 07/20/14 15:01:46</td></tr>\r
+<td class="proptext"> 08/28/14 22:25:58</td></tr>\r
<tr> <td class="prop"> Device :</td>\r
<td class="proptext"> CY8C5267AXI-LP051</td></tr>\r
<tr> <td class="prop"> Temperature :</td>\r
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_CLK.c
+* Version 2.10
+*
+* Description:
+* This file provides the source code to the API for the clock component.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include <cydevice_trm.h>
+#include "SCSI_CLK.h"
+
+/* Clock Distribution registers. */
+#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD)
+#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2)
+#define BCFG2_MASK (0x80u)
+#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK)
+#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK)
+
+#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_Start
+********************************************************************************
+*
+* Summary:
+* Starts the clock. Note that on startup, clocks may be already running if the
+* "Start on Reset" option is enabled in the DWR.
+*
+* Parameters:
+* None
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void SCSI_CLK_Start(void)
+{
+ /* Set the bit to enable the clock. */
+ SCSI_CLK_CLKEN |= SCSI_CLK_CLKEN_MASK;
+ SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_Stop
+********************************************************************************
+*
+* Summary:
+* Stops the clock and returns immediately. This API does not require the
+* source clock to be running but may return before the hardware is actually
+* disabled. If the settings of the clock are changed after calling this
+* function, the clock may glitch when it is started. To avoid the clock
+* glitch, use the StopBlock function.
+*
+* Parameters:
+* None
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void SCSI_CLK_Stop(void)
+{
+ /* Clear the bit to disable the clock. */
+ SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
+ SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
+}
+
+
+#if(CY_PSOC3 || CY_PSOC5LP)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_StopBlock
+********************************************************************************
+*
+* Summary:
+* Stops the clock and waits for the hardware to actually be disabled before
+* returning. This ensures that the clock is never truncated (high part of the
+* cycle will terminate before the clock is disabled and the API returns).
+* Note that the source clock must be running or this API will never return as
+* a stopped clock cannot be disabled.
+*
+* Parameters:
+* None
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void SCSI_CLK_StopBlock(void)
+{
+ if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u)
+ {
+#if HAS_CLKDIST_LD_DISABLE
+ uint16 oldDivider;
+
+ CLK_DIST_LD = 0u;
+
+ /* Clear all the mask bits except ours. */
+#if defined(SCSI_CLK__CFG3)
+ CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK;
+ CLK_DIST_DMASK = 0x00u;
+#else
+ CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK;
+ CLK_DIST_AMASK = 0x00u;
+#endif /* SCSI_CLK__CFG3 */
+
+ /* Clear mask of bus clock. */
+ CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
+
+ oldDivider = CY_GET_REG16(SCSI_CLK_DIV_PTR);
+ CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
+ CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD;
+
+ /* Wait for clock to be disabled */
+ while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+#endif /* HAS_CLKDIST_LD_DISABLE */
+
+ /* Clear the bit to disable the clock. */
+ SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
+ SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
+
+#if HAS_CLKDIST_LD_DISABLE
+ /* Clear the disable bit */
+ CLK_DIST_LD = 0x00u;
+ CY_SET_REG16(SCSI_CLK_DIV_PTR, oldDivider);
+#endif /* HAS_CLKDIST_LD_DISABLE */
+ }
+}
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_StandbyPower
+********************************************************************************
+*
+* Summary:
+* Sets whether the clock is active in standby mode.
+*
+* Parameters:
+* state: 0 to disable clock during standby, nonzero to enable.
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void SCSI_CLK_StandbyPower(uint8 state)
+{
+ if(state == 0u)
+ {
+ SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK);
+ }
+ else
+ {
+ SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetDividerRegister
+********************************************************************************
+*
+* Summary:
+* Modifies the clock divider and, thus, the frequency. When the clock divider
+* register is set to zero or changed from zero, the clock will be temporarily
+* disabled in order to change the SSS mode bit. If the clock is enabled when
+* SetDividerRegister is called, then the source clock must be running.
+*
+* Parameters:
+* clkDivider: Divider register value (0-65,535). This value is NOT the
+* divider; the clock hardware divides by clkDivider plus one. For example,
+* to divide the clock by 2, this parameter should be set to 1.
+* restart: If nonzero, restarts the clock divider: the current clock cycle
+* will be truncated and the new divide value will take effect immediately. If
+* zero, the new divide value will take effect at the end of the current clock
+* cycle.
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart)
+
+{
+ uint8 enabled;
+
+ uint8 currSrc = SCSI_CLK_GetSourceRegister();
+ uint16 oldDivider = SCSI_CLK_GetDividerRegister();
+
+ if (clkDivider != oldDivider)
+ {
+ enabled = SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK;
+
+ if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u)))
+ {
+ /* Moving to/from SSS requires correct ordering to prevent halting the clock */
+ if (oldDivider == 0u)
+ {
+ /* Moving away from SSS, set the divider first so when SSS is cleared we */
+ /* don't halt the clock. Using the shadow load isn't required as the */
+ /* divider is ignored while SSS is set. */
+ CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
+ SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS);
+ }
+ else
+ {
+ /* Moving to SSS, set SSS which then ignores the divider and we can set */
+ /* it without bothering with the shadow load. */
+ SCSI_CLK_MOD_SRC |= CYCLK_SSS;
+ CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
+ }
+ }
+ else
+ {
+
+ if (enabled != 0u)
+ {
+ CLK_DIST_LD = 0x00u;
+
+ /* Clear all the mask bits except ours. */
+#if defined(SCSI_CLK__CFG3)
+ CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK;
+ CLK_DIST_DMASK = 0x00u;
+#else
+ CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK;
+ CLK_DIST_AMASK = 0x00u;
+#endif /* SCSI_CLK__CFG3 */
+ /* Clear mask of bus clock. */
+ CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK);
+
+ /* If clock is currently enabled, disable it if async or going from N-to-1*/
+ if (((SCSI_CLK_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u))
+ {
+#if HAS_CLKDIST_LD_DISABLE
+ CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider);
+ CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD;
+
+ /* Wait for clock to be disabled */
+ while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+#endif /* HAS_CLKDIST_LD_DISABLE */
+
+ SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK);
+
+#if HAS_CLKDIST_LD_DISABLE
+ /* Clear the disable bit */
+ CLK_DIST_LD = 0x00u;
+#endif /* HAS_CLKDIST_LD_DISABLE */
+ }
+ }
+
+ /* Load divide value. */
+ if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u)
+ {
+ /* If the clock is still enabled, use the shadow registers */
+ CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider);
+
+ CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u));
+ while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { }
+ }
+ else
+ {
+ /* If the clock is disabled, set the divider directly */
+ CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider);
+ SCSI_CLK_CLKEN |= enabled;
+ }
+ }
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetDividerRegister
+********************************************************************************
+*
+* Summary:
+* Gets the clock divider register value.
+*
+* Parameters:
+* None
+*
+* Returns:
+* Divide value of the clock minus 1. For example, if the clock is set to
+* divide by 2, the return value will be 1.
+*
+*******************************************************************************/
+uint16 SCSI_CLK_GetDividerRegister(void)
+{
+ return CY_GET_REG16(SCSI_CLK_DIV_PTR);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetModeRegister
+********************************************************************************
+*
+* Summary:
+* Sets flags that control the operating mode of the clock. This function only
+* changes flags from 0 to 1; flags that are already 1 will remain unchanged.
+* To clear flags, use the ClearModeRegister function. The clock must be
+* disabled before changing the mode.
+*
+* Parameters:
+* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5,
+* clkMode should be a set of the following optional bits or'ed together.
+* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
+* occur when the divider count reaches half of the divide
+* value.
+* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock
+* is asserted for approximately half of its period. When
+* disabled, the output clock is asserted for one period of the
+* source clock.
+* - CYCLK_SYNC Enable output synchronization to master clock. This should
+* be enabled for all synchronous clocks.
+* See the Technical Reference Manual for details about setting the mode of
+* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void SCSI_CLK_SetModeRegister(uint8 modeBitMask)
+{
+ SCSI_CLK_MOD_SRC |= modeBitMask & (uint8)SCSI_CLK_MODE_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_ClearModeRegister
+********************************************************************************
+*
+* Summary:
+* Clears flags that control the operating mode of the clock. This function
+* only changes flags from 1 to 0; flags that are already 0 will remain
+* unchanged. To set flags, use the SetModeRegister function. The clock must be
+* disabled before changing the mode.
+*
+* Parameters:
+* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5,
+* clkMode should be a set of the following optional bits or'ed together.
+* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will
+* occur when the divider count reaches half of the divide
+* value.
+* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock
+* is asserted for approximately half of its period. When
+* disabled, the output clock is asserted for one period of the
+* source clock.
+* - CYCLK_SYNC Enable output synchronization to master clock. This should
+* be enabled for all synchronous clocks.
+* See the Technical Reference Manual for details about setting the mode of
+* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register.
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void SCSI_CLK_ClearModeRegister(uint8 modeBitMask)
+{
+ SCSI_CLK_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SCSI_CLK_MODE_MASK));
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetModeRegister
+********************************************************************************
+*
+* Summary:
+* Gets the clock mode register value.
+*
+* Parameters:
+* None
+*
+* Returns:
+* Bit mask representing the enabled mode bits. See the SetModeRegister and
+* ClearModeRegister descriptions for details about the mode bits.
+*
+*******************************************************************************/
+uint8 SCSI_CLK_GetModeRegister(void)
+{
+ return SCSI_CLK_MOD_SRC & (uint8)(SCSI_CLK_MODE_MASK);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetSourceRegister
+********************************************************************************
+*
+* Summary:
+* Sets the input source of the clock. The clock must be disabled before
+* changing the source. The old and new clock sources must be running.
+*
+* Parameters:
+* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the
+* following input sources:
+* - CYCLK_SRC_SEL_SYNC_DIG
+* - CYCLK_SRC_SEL_IMO
+* - CYCLK_SRC_SEL_XTALM
+* - CYCLK_SRC_SEL_ILO
+* - CYCLK_SRC_SEL_PLL
+* - CYCLK_SRC_SEL_XTALK
+* - CYCLK_SRC_SEL_DSI_G
+* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A
+* See the Technical Reference Manual for details on clock sources.
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void SCSI_CLK_SetSourceRegister(uint8 clkSource)
+{
+ uint16 currDiv = SCSI_CLK_GetDividerRegister();
+ uint8 oldSrc = SCSI_CLK_GetSourceRegister();
+
+ if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) &&
+ (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
+ {
+ /* Switching to Master and divider is 1, set SSS, which will output master, */
+ /* then set the source so we are consistent. */
+ SCSI_CLK_MOD_SRC |= CYCLK_SSS;
+ SCSI_CLK_MOD_SRC =
+ (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
+ }
+ else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) &&
+ (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u))
+ {
+ /* Switching from Master to not and divider is 1, set source, so we don't */
+ /* lock when we clear SSS. */
+ SCSI_CLK_MOD_SRC =
+ (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
+ SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS);
+ }
+ else
+ {
+ SCSI_CLK_MOD_SRC =
+ (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource;
+ }
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetSourceRegister
+********************************************************************************
+*
+* Summary:
+* Gets the input source of the clock.
+*
+* Parameters:
+* None
+*
+* Returns:
+* The input source of the clock. See SetSourceRegister for details.
+*
+*******************************************************************************/
+uint8 SCSI_CLK_GetSourceRegister(void)
+{
+ return SCSI_CLK_MOD_SRC & SCSI_CLK_SRC_SEL_MSK;
+}
+
+
+#if defined(SCSI_CLK__CFG3)
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_SetPhaseRegister
+********************************************************************************
+*
+* Summary:
+* Sets the phase delay of the analog clock. This function is only available
+* for analog clocks. The clock must be disabled before changing the phase
+* delay to avoid glitches.
+*
+* Parameters:
+* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments.
+* clkPhase must be from 1 to 11 inclusive. Other values, including 0,
+* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11
+* produces a 10ns delay.
+*
+* Returns:
+* None
+*
+*******************************************************************************/
+void SCSI_CLK_SetPhaseRegister(uint8 clkPhase)
+{
+ SCSI_CLK_PHASE = clkPhase & SCSI_CLK_PHASE_MASK;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_CLK_GetPhase
+********************************************************************************
+*
+* Summary:
+* Gets the phase delay of the analog clock. This function is only available
+* for analog clocks.
+*
+* Parameters:
+* None
+*
+* Returns:
+* Phase of the analog clock. See SetPhaseRegister for details.
+*
+*******************************************************************************/
+uint8 SCSI_CLK_GetPhaseRegister(void)
+{
+ return SCSI_CLK_PHASE & SCSI_CLK_PHASE_MASK;
+}
+
+#endif /* SCSI_CLK__CFG3 */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_CLK.h
+* Version 2.10
+*
+* Description:
+* Provides the function and constant definitions for the clock component.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_CLOCK_SCSI_CLK_H)
+#define CY_CLOCK_SCSI_CLK_H
+
+#include <cytypes.h>
+#include <cyfitter.h>
+
+
+/***************************************
+* Conditional Compilation Parameters
+***************************************/
+
+/* Check to see if required defines such as CY_PSOC5LP are available */
+/* They are defined starting with cy_boot v3.0 */
+#if !defined (CY_PSOC5LP)
+ #error Component cy_clock_v2_10 requires cy_boot v3.0 or later
+#endif /* (CY_PSOC5LP) */
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+void SCSI_CLK_Start(void) ;
+void SCSI_CLK_Stop(void) ;
+
+#if(CY_PSOC3 || CY_PSOC5LP)
+void SCSI_CLK_StopBlock(void) ;
+#endif /* (CY_PSOC3 || CY_PSOC5LP) */
+
+void SCSI_CLK_StandbyPower(uint8 state) ;
+void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart)
+ ;
+uint16 SCSI_CLK_GetDividerRegister(void) ;
+void SCSI_CLK_SetModeRegister(uint8 modeBitMask) ;
+void SCSI_CLK_ClearModeRegister(uint8 modeBitMask) ;
+uint8 SCSI_CLK_GetModeRegister(void) ;
+void SCSI_CLK_SetSourceRegister(uint8 clkSource) ;
+uint8 SCSI_CLK_GetSourceRegister(void) ;
+#if defined(SCSI_CLK__CFG3)
+void SCSI_CLK_SetPhaseRegister(uint8 clkPhase) ;
+uint8 SCSI_CLK_GetPhaseRegister(void) ;
+#endif /* defined(SCSI_CLK__CFG3) */
+
+#define SCSI_CLK_Enable() SCSI_CLK_Start()
+#define SCSI_CLK_Disable() SCSI_CLK_Stop()
+#define SCSI_CLK_SetDivider(clkDivider) SCSI_CLK_SetDividerRegister(clkDivider, 1u)
+#define SCSI_CLK_SetDividerValue(clkDivider) SCSI_CLK_SetDividerRegister((clkDivider) - 1u, 1u)
+#define SCSI_CLK_SetMode(clkMode) SCSI_CLK_SetModeRegister(clkMode)
+#define SCSI_CLK_SetSource(clkSource) SCSI_CLK_SetSourceRegister(clkSource)
+#if defined(SCSI_CLK__CFG3)
+#define SCSI_CLK_SetPhase(clkPhase) SCSI_CLK_SetPhaseRegister(clkPhase)
+#define SCSI_CLK_SetPhaseValue(clkPhase) SCSI_CLK_SetPhaseRegister((clkPhase) + 1u)
+#endif /* defined(SCSI_CLK__CFG3) */
+
+
+/***************************************
+* Registers
+***************************************/
+
+/* Register to enable or disable the clock */
+#define SCSI_CLK_CLKEN (* (reg8 *) SCSI_CLK__PM_ACT_CFG)
+#define SCSI_CLK_CLKEN_PTR ((reg8 *) SCSI_CLK__PM_ACT_CFG)
+
+/* Register to enable or disable the clock */
+#define SCSI_CLK_CLKSTBY (* (reg8 *) SCSI_CLK__PM_STBY_CFG)
+#define SCSI_CLK_CLKSTBY_PTR ((reg8 *) SCSI_CLK__PM_STBY_CFG)
+
+/* Clock LSB divider configuration register. */
+#define SCSI_CLK_DIV_LSB (* (reg8 *) SCSI_CLK__CFG0)
+#define SCSI_CLK_DIV_LSB_PTR ((reg8 *) SCSI_CLK__CFG0)
+#define SCSI_CLK_DIV_PTR ((reg16 *) SCSI_CLK__CFG0)
+
+/* Clock MSB divider configuration register. */
+#define SCSI_CLK_DIV_MSB (* (reg8 *) SCSI_CLK__CFG1)
+#define SCSI_CLK_DIV_MSB_PTR ((reg8 *) SCSI_CLK__CFG1)
+
+/* Mode and source configuration register */
+#define SCSI_CLK_MOD_SRC (* (reg8 *) SCSI_CLK__CFG2)
+#define SCSI_CLK_MOD_SRC_PTR ((reg8 *) SCSI_CLK__CFG2)
+
+#if defined(SCSI_CLK__CFG3)
+/* Analog clock phase configuration register */
+#define SCSI_CLK_PHASE (* (reg8 *) SCSI_CLK__CFG3)
+#define SCSI_CLK_PHASE_PTR ((reg8 *) SCSI_CLK__CFG3)
+#endif /* defined(SCSI_CLK__CFG3) */
+
+
+/**************************************
+* Register Constants
+**************************************/
+
+/* Power manager register masks */
+#define SCSI_CLK_CLKEN_MASK SCSI_CLK__PM_ACT_MSK
+#define SCSI_CLK_CLKSTBY_MASK SCSI_CLK__PM_STBY_MSK
+
+/* CFG2 field masks */
+#define SCSI_CLK_SRC_SEL_MSK SCSI_CLK__CFG2_SRC_SEL_MASK
+#define SCSI_CLK_MODE_MASK (~(SCSI_CLK_SRC_SEL_MSK))
+
+#if defined(SCSI_CLK__CFG3)
+/* CFG3 phase mask */
+#define SCSI_CLK_PHASE_MASK SCSI_CLK__CFG3_PHASE_DLY_MASK
+#endif /* defined(SCSI_CLK__CFG3) */
+
+#endif /* CY_CLOCK_SCSI_CLK_H */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Parity_Error.c
+* Version 1.80
+*
+* Description:
+* This file contains API to enable firmware to read the value of a Status
+* Register.
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#include "SCSI_Parity_Error.h"
+
+#if !defined(SCSI_Parity_Error_sts_sts_reg__REMOVED) /* Check for removal by optimization */
+
+
+/*******************************************************************************
+* Function Name: SCSI_Parity_Error_Read
+********************************************************************************
+*
+* Summary:
+* Reads the current value assigned to the Status Register.
+*
+* Parameters:
+* None.
+*
+* Return:
+* The current value in the Status Register.
+*
+*******************************************************************************/
+uint8 SCSI_Parity_Error_Read(void)
+{
+ return SCSI_Parity_Error_Status;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Parity_Error_InterruptEnable
+********************************************************************************
+*
+* Summary:
+* Enables the Status Register interrupt.
+*
+* Parameters:
+* None.
+*
+* Return:
+* None.
+*
+*******************************************************************************/
+void SCSI_Parity_Error_InterruptEnable(void)
+{
+ uint8 interruptState;
+ interruptState = CyEnterCriticalSection();
+ SCSI_Parity_Error_Status_Aux_Ctrl |= SCSI_Parity_Error_STATUS_INTR_ENBL;
+ CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Parity_Error_InterruptDisable
+********************************************************************************
+*
+* Summary:
+* Disables the Status Register interrupt.
+*
+* Parameters:
+* None.
+*
+* Return:
+* None.
+*
+*******************************************************************************/
+void SCSI_Parity_Error_InterruptDisable(void)
+{
+ uint8 interruptState;
+ interruptState = CyEnterCriticalSection();
+ SCSI_Parity_Error_Status_Aux_Ctrl &= (uint8)(~SCSI_Parity_Error_STATUS_INTR_ENBL);
+ CyExitCriticalSection(interruptState);
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Parity_Error_WriteMask
+********************************************************************************
+*
+* Summary:
+* Writes the current mask value assigned to the Status Register.
+*
+* Parameters:
+* mask: Value to write into the mask register.
+*
+* Return:
+* None.
+*
+*******************************************************************************/
+void SCSI_Parity_Error_WriteMask(uint8 mask)
+{
+ #if(SCSI_Parity_Error_INPUTS < 8u)
+ mask &= (uint8)((((uint8)1u) << SCSI_Parity_Error_INPUTS) - 1u);
+ #endif /* End SCSI_Parity_Error_INPUTS < 8u */
+ SCSI_Parity_Error_Status_Mask = mask;
+}
+
+
+/*******************************************************************************
+* Function Name: SCSI_Parity_Error_ReadMask
+********************************************************************************
+*
+* Summary:
+* Reads the current interrupt mask assigned to the Status Register.
+*
+* Parameters:
+* None.
+*
+* Return:
+* The value of the interrupt mask of the Status Register.
+*
+*******************************************************************************/
+uint8 SCSI_Parity_Error_ReadMask(void)
+{
+ return SCSI_Parity_Error_Status_Mask;
+}
+
+#endif /* End check for removal by optimization */
+
+
+/* [] END OF FILE */
--- /dev/null
+/*******************************************************************************
+* File Name: SCSI_Parity_Error.h
+* Version 1.80
+*
+* Description:
+* This file containts Status Register function prototypes and register defines
+*
+* Note:
+*
+********************************************************************************
+* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
+* You may use this file only in accordance with the license, terms, conditions,
+* disclaimers, and limitations in the end user license agreement accompanying
+* the software package with which this file was provided.
+*******************************************************************************/
+
+#if !defined(CY_STATUS_REG_SCSI_Parity_Error_H) /* CY_STATUS_REG_SCSI_Parity_Error_H */
+#define CY_STATUS_REG_SCSI_Parity_Error_H
+
+#include "cytypes.h"
+#include "CyLib.h"
+
+
+/***************************************
+* Function Prototypes
+***************************************/
+
+uint8 SCSI_Parity_Error_Read(void) ;
+void SCSI_Parity_Error_InterruptEnable(void) ;
+void SCSI_Parity_Error_InterruptDisable(void) ;
+void SCSI_Parity_Error_WriteMask(uint8 mask) ;
+uint8 SCSI_Parity_Error_ReadMask(void) ;
+
+
+/***************************************
+* API Constants
+***************************************/
+
+#define SCSI_Parity_Error_STATUS_INTR_ENBL 0x10u
+
+
+/***************************************
+* Parameter Constants
+***************************************/
+
+/* Status Register Inputs */
+#define SCSI_Parity_Error_INPUTS 1
+
+
+/***************************************
+* Registers
+***************************************/
+
+/* Status Register */
+#define SCSI_Parity_Error_Status (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG )
+#define SCSI_Parity_Error_Status_PTR ( (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG )
+#define SCSI_Parity_Error_Status_Mask (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__MASK_REG )
+#define SCSI_Parity_Error_Status_Aux_Ctrl (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG )
+
+#endif /* End CY_STATUS_REG_SCSI_Parity_Error_H */
+
+
+/* [] END OF FILE */
0x10u, 0xBDu, 0x82u, 0x18u, 0x03u, 0x46u, 0x93u, 0x42u,
0x02u, 0xD0u, 0x03u, 0xF8u, 0x01u, 0x1Bu, 0xFAu, 0xE7u,
0x70u, 0x47u, 0x00u, 0x00u, 0xA0u, 0x22u, 0x00u, 0x00u,
- 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x32u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x10u, 0x51u, 0x00u, 0x40u, 0x10u, 0x00u, 0xC0u, 0x51u,
0x00u, 0x40u, 0x10u, 0x00u, 0x00u, 0x00u, 0x01u, 0x40u,
0x00u, 0x10u, 0x00u, 0x14u, 0x01u, 0x40u, 0x00u, 0x08u,
#endif
const uint8 cy_metadata[] = {
0x00u, 0x01u, 0x2Eu, 0x13u, 0x30u, 0x69u, 0x00u, 0x01u,
- 0x2Eu, 0x1Fu, 0x9Au, 0x39u};
+ 0x2Eu, 0x1Fu, 0x9Au, 0x6Bu};
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
__attribute__ ((__section__(".cycustnvl"), used))
#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
+/* SCSI_Parity_Error */
+#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
+#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST
+#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK
+#define SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB02_ST_CTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB02_ST_CTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST
+
/* USBFS_bus_reset */
#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
/* SCSI_Out_Bits */
#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB10_11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB10_11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB10_11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB10_11_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB10_11_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB10_11_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB10_11_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB10_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB10_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB10_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB10_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB10_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB11_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB11_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB11_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB10_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB11_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
/* USBFS_arb_int */
#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SDCard_BSPIM */
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB08_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB08_ST
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB08_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB08_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB08_MSK
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB09_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB09_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB09_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB09_ST
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB09_10_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB09_10_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB09_10_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB09_10_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB09_10_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB09_10_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB09_10_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB09_10_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB09_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB09_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB09_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB09_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB09_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB09_MSK
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB10_11_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB11_MSK
-#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
-#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB11_ST
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB10_MSK
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB10_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB10_ST
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
#define SDCard_BSPIM_TxStsReg__0__POS 0
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB08_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB08_ST
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB08_09_A0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB08_09_A1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB08_09_D0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB08_09_D1
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB08_09_F0
-#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB08_09_F1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB08_A0_A1
-#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB08_A0
-#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB08_A1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB08_D0_D1
-#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB08_D0
-#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB08_D1
-#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB08_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB08_F0_F1
-#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB08_F0
-#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB08_F1
-#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
-#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB11_MSK
+#define SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
+#define SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB11_MSK_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB11_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_CNT_REG CYREG_B1_UDB11_ST_CTL
+#define SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB11_ST_CTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB11_ST
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB09_10_A0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB09_10_A1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB09_10_D0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB09_10_D1
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB09_10_F0
+#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB09_10_F1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB09_A0_A1
+#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB09_A0
+#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB09_A1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB09_D0_D1
+#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB09_D0
+#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB09_D1
+#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB09_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB09_F0_F1
+#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB09_F0
+#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB09_F1
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
/* USBFS_dp_int */
#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SD_Data_Clk__PM_STBY_MSK 0x01u
/* timer_clock */
-#define timer_clock__CFG0 CYREG_CLKDIST_DCFG1_CFG0
-#define timer_clock__CFG1 CYREG_CLKDIST_DCFG1_CFG1
-#define timer_clock__CFG2 CYREG_CLKDIST_DCFG1_CFG2
+#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0
+#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1
+#define timer_clock__CFG2 CYREG_CLKDIST_DCFG2_CFG2
#define timer_clock__CFG2_SRC_SEL_MASK 0x07u
-#define timer_clock__INDEX 0x01u
+#define timer_clock__INDEX 0x02u
#define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2
-#define timer_clock__PM_ACT_MSK 0x02u
+#define timer_clock__PM_ACT_MSK 0x04u
#define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2
-#define timer_clock__PM_STBY_MSK 0x02u
+#define timer_clock__PM_STBY_MSK 0x04u
/* scsiTarget */
#define scsiTarget_StatusReg__0__MASK 0x01u
#define scsiTarget_StatusReg__0__POS 0
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB13_14_ST
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
#define scsiTarget_StatusReg__1__MASK 0x02u
#define scsiTarget_StatusReg__1__POS 1
#define scsiTarget_StatusReg__2__MASK 0x04u
#define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB13_MSK
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB13_ACTL
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB13_ST
-#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
-#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB14_15_ST
-#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB14_MSK
-#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
-#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
-#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB14_ACTL
-#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB14_ST_CTL
-#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB14_ST_CTL
-#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB14_ST
-#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
-#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL
-#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL
-#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL
-#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL
-#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK
-#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK
-#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK
-#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK
-#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL
-#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB14_CTL
-#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL
-#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB14_CTL
-#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL
-#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
-#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB14_MSK
-#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
-#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB14_15_A0
-#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB14_15_A1
-#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB14_15_D0
-#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB14_15_D1
-#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
-#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB14_15_F0
-#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB14_15_F1
-#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB14_A0_A1
-#define scsiTarget_datapath__A0_REG CYREG_B0_UDB14_A0
-#define scsiTarget_datapath__A1_REG CYREG_B0_UDB14_A1
-#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB14_D0_D1
-#define scsiTarget_datapath__D0_REG CYREG_B0_UDB14_D0
-#define scsiTarget_datapath__D1_REG CYREG_B0_UDB14_D1
-#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB14_ACTL
-#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB14_F0_F1
-#define scsiTarget_datapath__F0_REG CYREG_B0_UDB14_F0
-#define scsiTarget_datapath__F1_REG CYREG_B0_UDB14_F1
-#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
-#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB04_MSK
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB04_ST
+#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
+#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB11_MSK
+#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB11_ST
+#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
+#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
+#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
+#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
+#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB11_CTL
+#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB11_CTL
+#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
+#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB11_MSK
+#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB11_12_A0
+#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB11_12_A1
+#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB11_12_D0
+#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB11_12_D1
+#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB11_12_F0
+#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB11_12_F1
+#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB11_A0_A1
+#define scsiTarget_datapath__A0_REG CYREG_B0_UDB11_A0
+#define scsiTarget_datapath__A1_REG CYREG_B0_UDB11_A1
+#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB11_D0_D1
+#define scsiTarget_datapath__D0_REG CYREG_B0_UDB11_D0
+#define scsiTarget_datapath__D1_REG CYREG_B0_UDB11_D1
+#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB11_F0_F1
+#define scsiTarget_datapath__F0_REG CYREG_B0_UDB11_F0
+#define scsiTarget_datapath__F1_REG CYREG_B0_UDB11_F1
+#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
+#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
/* USBFS_ep_0 */
#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SCSI_ATN__SHIFT 0
#define SCSI_ATN__SLW CYREG_PRT2_SLW
+/* SCSI_CLK */
+#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0
+#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1
+#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2
+#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u
+#define SCSI_CLK__INDEX 0x01u
+#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2
+#define SCSI_CLK__PM_ACT_MSK 0x02u
+#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2
+#define SCSI_CLK__PM_STBY_MSK 0x02u
+
/* SCSI_Out */
#define SCSI_Out__0__AG CYREG_PRT15_AG
#define SCSI_Out__0__AMUX CYREG_PRT15_AMUX
}
#endif
-#define CY_CFG_BASE_ADDR_COUNT 37u
+#define CY_CFG_BASE_ADDR_COUNT 38u
CYPACKED typedef struct
{
uint8 offset;
/* Configure Digital Clocks based on settings from Clock DWR */
CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0000u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u);
- CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0017u);
- CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x19u);
+ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0000u);
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x58u);
+ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0017u);
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x19u);
/* Configure ILO based on settings from Clock DWR */
CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u);
- CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x03u)));
+ CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x07u)));
}
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x40004502u, /* Base address: 0x40004500 Count: 2 */
0x40004F02u, /* Base address: 0x40004F00 Count: 2 */
- 0x4000520Eu, /* Base address: 0x40005200 Count: 14 */
+ 0x40005210u, /* Base address: 0x40005200 Count: 16 */
0x40006402u, /* Base address: 0x40006400 Count: 2 */
- 0x40010004u, /* Base address: 0x40010000 Count: 4 */
- 0x40010103u, /* Base address: 0x40010100 Count: 3 */
- 0x40010305u, /* Base address: 0x40010300 Count: 5 */
- 0x40010503u, /* Base address: 0x40010500 Count: 3 */
- 0x40010702u, /* Base address: 0x40010700 Count: 2 */
- 0x40010858u, /* Base address: 0x40010800 Count: 88 */
- 0x4001094Du, /* Base address: 0x40010900 Count: 77 */
+ 0x40010104u, /* Base address: 0x40010100 Count: 4 */
+ 0x4001023Du, /* Base address: 0x40010200 Count: 61 */
+ 0x40010340u, /* Base address: 0x40010300 Count: 64 */
+ 0x40010451u, /* Base address: 0x40010400 Count: 81 */
+ 0x4001054Eu, /* Base address: 0x40010500 Count: 78 */
+ 0x40010715u, /* Base address: 0x40010700 Count: 21 */
+ 0x40010818u, /* Base address: 0x40010800 Count: 24 */
+ 0x40010952u, /* Base address: 0x40010900 Count: 82 */
0x40010A4Cu, /* Base address: 0x40010A00 Count: 76 */
- 0x40010B49u, /* Base address: 0x40010B00 Count: 73 */
- 0x40010C4Eu, /* Base address: 0x40010C00 Count: 78 */
- 0x40010D4Cu, /* Base address: 0x40010D00 Count: 76 */
- 0x40010E3Au, /* Base address: 0x40010E00 Count: 58 */
- 0x40010F38u, /* Base address: 0x40010F00 Count: 56 */
- 0x40011503u, /* Base address: 0x40011500 Count: 3 */
- 0x40011702u, /* Base address: 0x40011700 Count: 2 */
- 0x40011853u, /* Base address: 0x40011800 Count: 83 */
- 0x40011948u, /* Base address: 0x40011900 Count: 72 */
- 0x40011A4Fu, /* Base address: 0x40011A00 Count: 79 */
- 0x40011B4Au, /* Base address: 0x40011B00 Count: 74 */
- 0x40014015u, /* Base address: 0x40014000 Count: 21 */
+ 0x40010B57u, /* Base address: 0x40010B00 Count: 87 */
+ 0x40010C48u, /* Base address: 0x40010C00 Count: 72 */
+ 0x40010D4Du, /* Base address: 0x40010D00 Count: 77 */
+ 0x40010E53u, /* Base address: 0x40010E00 Count: 83 */
+ 0x40010F3Cu, /* Base address: 0x40010F00 Count: 60 */
+ 0x4001150Bu, /* Base address: 0x40011500 Count: 11 */
+ 0x4001170Fu, /* Base address: 0x40011700 Count: 15 */
+ 0x4001184Eu, /* Base address: 0x40011800 Count: 78 */
+ 0x40011947u, /* Base address: 0x40011900 Count: 71 */
+ 0x40011A48u, /* Base address: 0x40011A00 Count: 72 */
+ 0x40011B57u, /* Base address: 0x40011B00 Count: 87 */
+ 0x40014016u, /* Base address: 0x40014000 Count: 22 */
0x40014114u, /* Base address: 0x40014100 Count: 20 */
- 0x40014213u, /* Base address: 0x40014200 Count: 19 */
- 0x40014305u, /* Base address: 0x40014300 Count: 5 */
- 0x4001440Du, /* Base address: 0x40014400 Count: 13 */
- 0x40014515u, /* Base address: 0x40014500 Count: 21 */
+ 0x40014211u, /* Base address: 0x40014200 Count: 17 */
+ 0x40014306u, /* Base address: 0x40014300 Count: 6 */
+ 0x40014411u, /* Base address: 0x40014400 Count: 17 */
+ 0x40014513u, /* Base address: 0x40014500 Count: 19 */
0x40014610u, /* Base address: 0x40014600 Count: 16 */
- 0x40014717u, /* Base address: 0x40014700 Count: 23 */
- 0x40014804u, /* Base address: 0x40014800 Count: 4 */
+ 0x4001470Bu, /* Base address: 0x40014700 Count: 11 */
+ 0x40014806u, /* Base address: 0x40014800 Count: 6 */
0x4001490Du, /* Base address: 0x40014900 Count: 13 */
- 0x40014C09u, /* Base address: 0x40014C00 Count: 9 */
- 0x40014D0Eu, /* Base address: 0x40014D00 Count: 14 */
- 0x40015007u, /* Base address: 0x40015000 Count: 7 */
+ 0x40014C07u, /* Base address: 0x40014C00 Count: 7 */
+ 0x40014D0Fu, /* Base address: 0x40014D00 Count: 15 */
+ 0x40015004u, /* Base address: 0x40015000 Count: 4 */
0x40015104u, /* Base address: 0x40015100 Count: 4 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x27u, 0x02u},
{0x7Eu, 0x02u},
- {0x01u, 0x10u},
+ {0x01u, 0x20u},
{0x0Au, 0x4Bu},
- {0x00u, 0x40u},
- {0x01u, 0x04u},
- {0x04u, 0x01u},
- {0x10u, 0x04u},
- {0x11u, 0x88u},
- {0x18u, 0x0Cu},
- {0x19u, 0x08u},
+ {0x00u, 0x08u},
+ {0x01u, 0x40u},
+ {0x04u, 0x31u},
+ {0x10u, 0x84u},
+ {0x11u, 0x08u},
+ {0x14u, 0x01u},
+ {0x18u, 0x08u},
+ {0x19u, 0x0Cu},
{0x1Cu, 0x20u},
{0x21u, 0x10u},
- {0x28u, 0x03u},
- {0x29u, 0x01u},
- {0x30u, 0x20u},
+ {0x24u, 0x4Cu},
+ {0x28u, 0x02u},
+ {0x31u, 0x20u},
+ {0x34u, 0x08u},
{0x78u, 0x20u},
{0x7Cu, 0x40u},
- {0x2Eu, 0x02u},
- {0x88u, 0x0Fu},
- {0xB8u, 0x80u},
- {0xBEu, 0x40u},
- {0xD8u, 0x04u},
- {0xDFu, 0x01u},
- {0x1Eu, 0x02u},
- {0xE0u, 0x40u},
- {0xE2u, 0x81u},
- {0x8Eu, 0x01u},
- {0xA2u, 0x01u},
- {0xE2u, 0x10u},
- {0xE6u, 0x04u},
- {0xEEu, 0x10u},
- {0xE2u, 0x18u},
- {0xE6u, 0x01u},
- {0xEEu, 0x04u},
- {0xEAu, 0x40u},
- {0xEEu, 0x08u},
- {0x01u, 0x01u},
- {0x04u, 0x04u},
- {0x06u, 0x03u},
- {0x08u, 0x85u},
- {0x09u, 0x01u},
- {0x0Au, 0x02u},
- {0x10u, 0x83u},
- {0x11u, 0x01u},
- {0x12u, 0x04u},
- {0x14u, 0x81u},
- {0x16u, 0x06u},
- {0x1Au, 0x08u},
- {0x1Cu, 0x28u},
- {0x1Du, 0x01u},
- {0x1Eu, 0x50u},
- {0x26u, 0x40u},
- {0x2Au, 0x10u},
- {0x2Eu, 0x20u},
- {0x30u, 0x80u},
- {0x31u, 0x01u},
- {0x32u, 0x07u},
- {0x34u, 0x18u},
- {0x36u, 0x60u},
- {0x39u, 0x02u},
- {0x3Au, 0x08u},
- {0x3Eu, 0x51u},
+ {0x2Bu, 0x02u},
+ {0x89u, 0x0Fu},
+ {0x8Bu, 0x01u},
+ {0x8Eu, 0x40u},
+ {0xE4u, 0x04u},
+ {0xE6u, 0x22u},
+ {0x04u, 0x01u},
+ {0x07u, 0x02u},
+ {0x0Fu, 0x01u},
+ {0x15u, 0x01u},
+ {0x17u, 0x02u},
+ {0x1Cu, 0x01u},
+ {0x28u, 0x01u},
+ {0x2Cu, 0x01u},
+ {0x31u, 0x03u},
+ {0x32u, 0x01u},
+ {0x38u, 0x08u},
+ {0x3Eu, 0x04u},
{0x3Fu, 0x01u},
- {0x40u, 0x43u},
- {0x41u, 0x02u},
- {0x42u, 0x10u},
- {0x44u, 0x05u},
- {0x45u, 0x0Eu},
- {0x46u, 0xBFu},
- {0x47u, 0xDCu},
- {0x48u, 0x3Du},
- {0x49u, 0xFFu},
- {0x4Au, 0xFFu},
- {0x4Bu, 0xFFu},
- {0x4Cu, 0x22u},
- {0x4Eu, 0xF0u},
- {0x4Fu, 0x08u},
- {0x50u, 0x04u},
- {0x56u, 0x02u},
- {0x57u, 0x28u},
+ {0x54u, 0x01u},
{0x58u, 0x04u},
{0x59u, 0x04u},
- {0x5Au, 0x04u},
{0x5Bu, 0x04u},
+ {0x5Du, 0x10u},
{0x5Fu, 0x01u},
- {0x62u, 0xC0u},
- {0x64u, 0x40u},
- {0x65u, 0x01u},
- {0x66u, 0x10u},
- {0x67u, 0x11u},
- {0x68u, 0xC0u},
- {0x69u, 0x01u},
- {0x6Bu, 0x11u},
- {0x6Cu, 0x40u},
- {0x6Du, 0x01u},
- {0x6Eu, 0x40u},
- {0x6Fu, 0x01u},
- {0x81u, 0x01u},
- {0x82u, 0x06u},
- {0x84u, 0x09u},
- {0x85u, 0x04u},
- {0x86u, 0x12u},
- {0x8Au, 0x09u},
- {0x8Eu, 0x08u},
- {0x90u, 0x09u},
- {0x92u, 0x24u},
- {0x9Au, 0x70u},
- {0x9Cu, 0x40u},
- {0x9Eu, 0x80u},
- {0xA1u, 0x02u},
- {0xA2u, 0x80u},
- {0xAEu, 0x01u},
- {0xB0u, 0x07u},
- {0xB3u, 0x02u},
- {0xB4u, 0x38u},
- {0xB5u, 0x01u},
- {0xB6u, 0xC0u},
- {0xB7u, 0x04u},
- {0xBEu, 0x40u},
- {0xBFu, 0x54u},
- {0xD8u, 0x04u},
- {0xD9u, 0x04u},
- {0xDCu, 0x09u},
- {0xDFu, 0x01u},
- {0x00u, 0x80u},
- {0x01u, 0x2Au},
- {0x04u, 0x20u},
- {0x05u, 0x04u},
- {0x08u, 0x44u},
- {0x09u, 0x08u},
- {0x0Au, 0x48u},
- {0x0Cu, 0x40u},
- {0x0Du, 0x42u},
- {0x0Eu, 0x20u},
- {0x0Fu, 0x04u},
- {0x11u, 0x01u},
- {0x13u, 0x40u},
- {0x14u, 0x01u},
- {0x15u, 0x18u},
- {0x16u, 0x01u},
- {0x17u, 0x08u},
- {0x19u, 0x02u},
- {0x1Au, 0x0Au},
- {0x1Du, 0x04u},
- {0x1Eu, 0x08u},
- {0x1Fu, 0x41u},
- {0x20u, 0x04u},
- {0x22u, 0x40u},
- {0x23u, 0x20u},
- {0x25u, 0x01u},
- {0x2Bu, 0x80u},
- {0x36u, 0x82u},
- {0x38u, 0x0Au},
- {0x3Cu, 0x22u},
- {0x44u, 0x02u},
- {0x45u, 0x16u},
- {0x4Du, 0x84u},
- {0x56u, 0x18u},
- {0x57u, 0x59u},
- {0x65u, 0x04u},
- {0x6Fu, 0x55u},
- {0x76u, 0x02u},
- {0x82u, 0x04u},
- {0x86u, 0x01u},
- {0x8Bu, 0xC0u},
- {0x90u, 0x40u},
+ {0x81u, 0x04u},
+ {0x85u, 0x08u},
+ {0x86u, 0x0Eu},
+ {0x88u, 0x14u},
+ {0x89u, 0x01u},
+ {0x8Au, 0x0Au},
+ {0x8Bu, 0x02u},
+ {0x8Eu, 0x10u},
+ {0x8Fu, 0x38u},
{0x92u, 0x40u},
- {0x93u, 0x4Cu},
- {0x94u, 0x24u},
- {0x95u, 0x90u},
- {0x96u, 0x80u},
- {0x98u, 0x1Au},
+ {0x93u, 0x40u},
+ {0x94u, 0x08u},
+ {0x96u, 0x10u},
+ {0x97u, 0x01u},
+ {0x98u, 0x01u},
{0x99u, 0x38u},
- {0x9Au, 0x01u},
- {0x9Cu, 0x64u},
- {0x9Du, 0x41u},
- {0x9Eu, 0x0Au},
- {0x9Fu, 0x7Du},
- {0xA0u, 0x41u},
- {0xA1u, 0x42u},
- {0xA2u, 0x81u},
- {0xA3u, 0x22u},
- {0xA5u, 0x35u},
- {0xA6u, 0x10u},
- {0xA7u, 0x41u},
- {0xB0u, 0x08u},
- {0xB5u, 0x41u},
- {0xB6u, 0x20u},
- {0xB7u, 0x40u},
- {0xC0u, 0x6Fu},
- {0xC2u, 0xFBu},
- {0xC4u, 0xE9u},
- {0xCAu, 0x01u},
- {0xCCu, 0x90u},
- {0xCEu, 0xA3u},
- {0xD0u, 0xF0u},
- {0xD2u, 0x10u},
- {0xD8u, 0x40u},
- {0xE4u, 0x06u},
- {0xEAu, 0x40u},
- {0xEEu, 0x08u},
- {0x04u, 0x09u},
- {0x05u, 0x04u},
- {0x06u, 0x12u},
- {0x0Au, 0x09u},
- {0x0Eu, 0x30u},
- {0x10u, 0x09u},
- {0x12u, 0x24u},
- {0x15u, 0x02u},
- {0x16u, 0x46u},
- {0x1Au, 0x80u},
- {0x1Eu, 0x08u},
- {0x20u, 0x40u},
- {0x21u, 0x01u},
- {0x22u, 0x80u},
- {0x26u, 0x01u},
- {0x30u, 0x38u},
- {0x31u, 0x02u},
- {0x32u, 0x07u},
- {0x33u, 0x04u},
- {0x34u, 0xC0u},
- {0x35u, 0x01u},
- {0x3Eu, 0x10u},
- {0x3Fu, 0x15u},
- {0x58u, 0x04u},
- {0x59u, 0x04u},
- {0x5Cu, 0x09u},
- {0x5Fu, 0x01u},
- {0x80u, 0xD6u},
- {0x81u, 0x0Du},
- {0x84u, 0xD2u},
- {0x85u, 0x22u},
- {0x86u, 0x04u},
- {0x87u, 0x18u},
- {0x88u, 0x31u},
- {0x89u, 0x11u},
- {0x8Au, 0x0Eu},
- {0x8Bu, 0x22u},
- {0x8Du, 0x60u},
- {0x90u, 0x29u},
- {0x91u, 0x02u},
- {0x92u, 0x16u},
- {0x93u, 0x0Du},
- {0x94u, 0x17u},
- {0x95u, 0x0Du},
- {0x96u, 0x28u},
- {0x98u, 0x22u},
- {0x99u, 0x0Du},
- {0x9Au, 0x10u},
- {0x9Du, 0x0Du},
- {0x9Eu, 0x80u},
- {0xA0u, 0x06u},
- {0xA1u, 0x0Du},
- {0xA2u, 0xD0u},
- {0xA4u, 0xD0u},
- {0xA6u, 0x06u},
- {0xA8u, 0x04u},
- {0xACu, 0xD6u},
- {0xADu, 0x12u},
- {0xAFu, 0x44u},
- {0xB0u, 0x0Fu},
- {0xB1u, 0x0Fu},
- {0xB2u, 0x80u},
- {0xB4u, 0x30u},
- {0xB6u, 0x40u},
- {0xB7u, 0x70u},
- {0xB8u, 0x02u},
- {0xB9u, 0x80u},
- {0xBAu, 0x20u},
- {0xBBu, 0x02u},
- {0xBEu, 0x44u},
- {0xD4u, 0x40u},
- {0xD6u, 0x04u},
+ {0x9Cu, 0x12u},
+ {0x9Eu, 0x04u},
+ {0x9Fu, 0x10u},
+ {0xA0u, 0x01u},
+ {0xA1u, 0x20u},
+ {0xA4u, 0x20u},
+ {0xA6u, 0x40u},
+ {0xAAu, 0x20u},
+ {0xABu, 0x02u},
+ {0xACu, 0x01u},
+ {0xB1u, 0x04u},
+ {0xB2u, 0x1Eu},
+ {0xB3u, 0x38u},
+ {0xB4u, 0x60u},
+ {0xB5u, 0x40u},
+ {0xB6u, 0x01u},
+ {0xB7u, 0x03u},
+ {0xBEu, 0x50u},
+ {0xBFu, 0x44u},
+ {0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
+ {0xDCu, 0x11u},
+ {0xDDu, 0x90u},
{0xDFu, 0x01u},
{0x01u, 0x28u},
- {0x03u, 0x02u},
- {0x04u, 0x20u},
- {0x07u, 0x50u},
- {0x08u, 0x08u},
- {0x09u, 0x20u},
- {0x0Au, 0x61u},
- {0x0Du, 0x02u},
- {0x0Eu, 0x28u},
- {0x0Fu, 0x03u},
- {0x10u, 0x60u},
- {0x15u, 0x01u},
- {0x16u, 0x0Au},
- {0x17u, 0x05u},
- {0x1Au, 0x28u},
- {0x1Bu, 0x02u},
- {0x1Cu, 0x40u},
- {0x1Du, 0x16u},
- {0x1Eu, 0x0Au},
- {0x1Fu, 0x01u},
- {0x21u, 0x08u},
- {0x22u, 0x21u},
- {0x25u, 0x40u},
- {0x26u, 0x02u},
- {0x29u, 0x02u},
- {0x2Du, 0x01u},
- {0x2Fu, 0x01u},
- {0x30u, 0x08u},
- {0x36u, 0x02u},
- {0x37u, 0x54u},
- {0x3Au, 0x04u},
- {0x3Du, 0xA8u},
- {0x3Eu, 0x02u},
- {0x5Cu, 0x02u},
- {0x5Eu, 0x02u},
- {0x64u, 0x80u},
- {0x65u, 0x04u},
- {0x66u, 0x20u},
- {0x67u, 0x01u},
- {0x6Du, 0x40u},
- {0x6Fu, 0x28u},
- {0x80u, 0x80u},
- {0x8Au, 0x04u},
+ {0x02u, 0x02u},
+ {0x04u, 0x04u},
+ {0x08u, 0x40u},
+ {0x09u, 0x04u},
+ {0x0Au, 0x40u},
+ {0x0Bu, 0x04u},
+ {0x0Eu, 0x01u},
+ {0x12u, 0x81u},
+ {0x13u, 0x28u},
+ {0x14u, 0x01u},
+ {0x17u, 0x10u},
+ {0x18u, 0x02u},
+ {0x19u, 0x0Cu},
+ {0x1Bu, 0x20u},
+ {0x1Cu, 0x20u},
+ {0x21u, 0x50u},
+ {0x22u, 0x05u},
+ {0x24u, 0x80u},
+ {0x2Au, 0x11u},
+ {0x2Bu, 0x80u},
+ {0x31u, 0x14u},
+ {0x32u, 0x81u},
+ {0x33u, 0x40u},
+ {0x37u, 0x08u},
+ {0x38u, 0x40u},
+ {0x3Au, 0x20u},
+ {0x3Bu, 0x05u},
+ {0x3Du, 0x80u},
+ {0x3Eu, 0x04u},
+ {0x5Au, 0x80u},
+ {0x5Fu, 0x80u},
+ {0x63u, 0x01u},
+ {0x6Cu, 0x20u},
+ {0x6Fu, 0x09u},
+ {0x80u, 0x40u},
+ {0x85u, 0x10u},
+ {0x87u, 0x80u},
+ {0x88u, 0x20u},
+ {0x8Bu, 0x20u},
+ {0x8Du, 0x10u},
+ {0x8Eu, 0x10u},
{0x8Fu, 0x08u},
- {0x92u, 0x41u},
- {0x93u, 0x4Cu},
- {0x94u, 0x04u},
- {0x95u, 0x90u},
- {0x96u, 0x82u},
- {0x98u, 0x10u},
- {0x99u, 0x2Au},
- {0x9Au, 0x05u},
- {0x9Cu, 0x24u},
- {0x9Du, 0x41u},
- {0x9Fu, 0x28u},
- {0xA0u, 0x61u},
- {0xA2u, 0x80u},
- {0xA5u, 0x08u},
- {0xA6u, 0x20u},
- {0xA7u, 0x20u},
- {0xAAu, 0x04u},
- {0xB5u, 0x02u},
- {0xB7u, 0x48u},
- {0xC0u, 0x77u},
- {0xC2u, 0xFFu},
- {0xC4u, 0xFCu},
- {0xCAu, 0x91u},
- {0xCCu, 0xF2u},
- {0xCEu, 0xF2u},
- {0xD8u, 0xF0u},
+ {0x92u, 0x80u},
+ {0x93u, 0x40u},
+ {0x95u, 0x20u},
+ {0x9Fu, 0x01u},
+ {0xA0u, 0x08u},
+ {0xA8u, 0x08u},
+ {0xADu, 0x10u},
+ {0xB3u, 0x40u},
+ {0xC0u, 0x27u},
+ {0xC2u, 0x8Fu},
+ {0xC4u, 0xCFu},
+ {0xCAu, 0x05u},
+ {0xCCu, 0x4Fu},
+ {0xCEu, 0x5Fu},
+ {0xD6u, 0x18u},
+ {0xD8u, 0x08u},
+ {0xE0u, 0x03u},
{0xE2u, 0x18u},
+ {0xE6u, 0x38u},
+ {0xE8u, 0x02u},
{0xEAu, 0x01u},
- {0xEEu, 0x04u},
- {0x00u, 0xFFu},
- {0x04u, 0x50u},
- {0x05u, 0x05u},
- {0x06u, 0xA0u},
- {0x07u, 0x0Au},
- {0x08u, 0x30u},
- {0x09u, 0x06u},
- {0x0Au, 0xC0u},
- {0x0Bu, 0x09u},
- {0x0Cu, 0x90u},
+ {0x01u, 0x05u},
+ {0x03u, 0x0Au},
+ {0x04u, 0x05u},
+ {0x06u, 0x0Au},
+ {0x09u, 0xA0u},
+ {0x0Bu, 0x4Fu},
{0x0Du, 0x03u},
- {0x0Eu, 0x60u},
{0x0Fu, 0x0Cu},
- {0x11u, 0xFFu},
- {0x14u, 0xFFu},
- {0x15u, 0x30u},
- {0x17u, 0xC0u},
- {0x18u, 0x05u},
- {0x1Au, 0x0Au},
- {0x1Bu, 0xFFu},
- {0x1Du, 0x60u},
- {0x1Fu, 0x90u},
- {0x20u, 0x03u},
- {0x21u, 0x0Fu},
- {0x22u, 0x0Cu},
- {0x23u, 0xF0u},
- {0x24u, 0x09u},
- {0x26u, 0x06u},
- {0x27u, 0xFFu},
- {0x29u, 0x50u},
- {0x2Au, 0xFFu},
- {0x2Bu, 0xA0u},
+ {0x10u, 0x60u},
+ {0x12u, 0x90u},
+ {0x13u, 0x70u},
+ {0x15u, 0x06u},
+ {0x17u, 0x09u},
+ {0x18u, 0x30u},
+ {0x19u, 0x0Fu},
+ {0x1Au, 0xC0u},
+ {0x1Cu, 0x03u},
+ {0x1Du, 0x90u},
+ {0x1Eu, 0x0Cu},
+ {0x1Fu, 0x2Fu},
+ {0x21u, 0x80u},
+ {0x24u, 0x50u},
+ {0x26u, 0xA0u},
+ {0x27u, 0x80u},
+ {0x28u, 0x06u},
+ {0x29u, 0xC0u},
+ {0x2Au, 0x09u},
+ {0x2Bu, 0x1Fu},
{0x2Cu, 0x0Fu},
{0x2Eu, 0xF0u},
- {0x36u, 0xFFu},
- {0x37u, 0xFFu},
- {0x3Eu, 0x40u},
+ {0x30u, 0xFFu},
+ {0x31u, 0x7Fu},
+ {0x37u, 0x80u},
+ {0x3Eu, 0x01u},
{0x3Fu, 0x40u},
{0x58u, 0x04u},
{0x59u, 0x04u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x10u},
{0x5Fu, 0x01u},
- {0x81u, 0x09u},
- {0x83u, 0x24u},
- {0x84u, 0x09u},
- {0x86u, 0x12u},
- {0x87u, 0x46u},
- {0x8Bu, 0x08u},
- {0x8Du, 0x40u},
- {0x8Eu, 0x06u},
- {0x8Fu, 0x80u},
- {0x90u, 0x09u},
- {0x92u, 0x24u},
- {0x96u, 0x80u},
- {0x9Au, 0x70u},
- {0x9Bu, 0x30u},
- {0xA2u, 0x09u},
- {0xA3u, 0x01u},
- {0xA5u, 0x09u},
- {0xA6u, 0x01u},
- {0xA7u, 0x12u},
- {0xAAu, 0x08u},
- {0xABu, 0x09u},
- {0xACu, 0x40u},
- {0xAEu, 0x80u},
- {0xAFu, 0x80u},
- {0xB0u, 0x07u},
- {0xB1u, 0xC0u},
- {0xB2u, 0xC0u},
- {0xB3u, 0x07u},
- {0xB4u, 0x38u},
- {0xB5u, 0x38u},
- {0xBEu, 0x04u},
- {0xBFu, 0x01u},
+ {0x81u, 0x03u},
+ {0x83u, 0x0Cu},
+ {0x85u, 0x09u},
+ {0x87u, 0x06u},
+ {0x89u, 0x50u},
+ {0x8Au, 0xFFu},
+ {0x8Bu, 0xA0u},
+ {0x8Cu, 0xFFu},
+ {0x8Du, 0x0Fu},
+ {0x8Fu, 0xF0u},
+ {0x90u, 0x05u},
+ {0x92u, 0x0Au},
+ {0x93u, 0xFFu},
+ {0x94u, 0x50u},
+ {0x95u, 0x90u},
+ {0x96u, 0xA0u},
+ {0x97u, 0x60u},
+ {0x98u, 0x06u},
+ {0x9Au, 0x09u},
+ {0x9Bu, 0xFFu},
+ {0x9Cu, 0x30u},
+ {0x9Du, 0x05u},
+ {0x9Eu, 0xC0u},
+ {0x9Fu, 0x0Au},
+ {0xA0u, 0x03u},
+ {0xA1u, 0x30u},
+ {0xA2u, 0x0Cu},
+ {0xA3u, 0xC0u},
+ {0xA6u, 0xFFu},
+ {0xA7u, 0xFFu},
+ {0xA8u, 0x60u},
+ {0xAAu, 0x90u},
+ {0xACu, 0x0Fu},
+ {0xAEu, 0xF0u},
+ {0xB3u, 0xFFu},
+ {0xB6u, 0xFFu},
+ {0xBEu, 0x40u},
+ {0xBFu, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
- {0xDBu, 0x04u},
- {0xDCu, 0x99u},
{0xDFu, 0x01u},
- {0x00u, 0x40u},
{0x01u, 0x08u},
- {0x02u, 0x01u},
- {0x05u, 0x41u},
- {0x06u, 0x20u},
- {0x07u, 0x08u},
- {0x08u, 0x14u},
+ {0x04u, 0x80u},
+ {0x06u, 0x08u},
+ {0x09u, 0x40u},
{0x0Au, 0x44u},
- {0x0Eu, 0x20u},
- {0x0Fu, 0x04u},
- {0x11u, 0x46u},
- {0x13u, 0x10u},
- {0x15u, 0x88u},
- {0x16u, 0x88u},
- {0x18u, 0x60u},
- {0x1Au, 0x04u},
- {0x1Cu, 0x02u},
- {0x20u, 0x20u},
- {0x21u, 0x24u},
- {0x23u, 0x84u},
- {0x26u, 0x80u},
- {0x28u, 0x80u},
- {0x29u, 0x68u},
- {0x2Du, 0x10u},
- {0x2Eu, 0x28u},
- {0x2Fu, 0x60u},
- {0x31u, 0x20u},
- {0x34u, 0x20u},
- {0x35u, 0x41u},
- {0x36u, 0x10u},
- {0x37u, 0x08u},
- {0x39u, 0xCAu},
- {0x3Bu, 0xA8u},
- {0x3Cu, 0x60u},
- {0x3Eu, 0x80u},
- {0x3Fu, 0x04u},
- {0x59u, 0x04u},
- {0x5Au, 0x20u},
- {0x5Bu, 0x41u},
- {0x63u, 0x01u},
- {0x78u, 0x08u},
- {0x7Au, 0x20u},
- {0x83u, 0xA0u},
- {0x8Cu, 0x10u},
- {0x8Eu, 0x10u},
+ {0x0Cu, 0x80u},
+ {0x0Eu, 0x80u},
+ {0x0Fu, 0x14u},
+ {0x11u, 0x40u},
+ {0x12u, 0x10u},
+ {0x13u, 0x20u},
+ {0x14u, 0x14u},
+ {0x15u, 0x41u},
+ {0x18u, 0x80u},
+ {0x19u, 0x02u},
+ {0x1Eu, 0x01u},
+ {0x21u, 0x02u},
+ {0x22u, 0x80u},
+ {0x23u, 0x80u},
+ {0x27u, 0x10u},
+ {0x29u, 0x04u},
+ {0x2Au, 0x20u},
+ {0x2Bu, 0x80u},
+ {0x2Cu, 0x80u},
+ {0x2Eu, 0x08u},
+ {0x2Fu, 0x20u},
+ {0x30u, 0x78u},
+ {0x31u, 0x02u},
+ {0x32u, 0x20u},
+ {0x34u, 0x84u},
+ {0x35u, 0x02u},
+ {0x36u, 0x64u},
+ {0x3Au, 0x01u},
+ {0x3Bu, 0x60u},
+ {0x3Du, 0x41u},
+ {0x3Fu, 0x96u},
+ {0x59u, 0x85u},
+ {0x5Au, 0x10u},
+ {0x62u, 0x80u},
+ {0x80u, 0x80u},
+ {0x83u, 0x40u},
+ {0x84u, 0x40u},
+ {0x86u, 0x02u},
+ {0x8Eu, 0x01u},
{0x8Fu, 0x80u},
- {0x91u, 0x06u},
- {0x92u, 0x41u},
- {0x93u, 0x71u},
- {0x94u, 0x04u},
- {0x96u, 0x82u},
- {0x98u, 0x80u},
- {0x99u, 0x2Cu},
- {0x9Bu, 0x01u},
- {0x9Cu, 0x08u},
- {0x9Fu, 0x20u},
- {0xA0u, 0x60u},
- {0xA1u, 0x01u},
- {0xA3u, 0x88u},
- {0xA5u, 0x08u},
- {0xA7u, 0x20u},
- {0xABu, 0x02u},
- {0xAEu, 0x40u},
- {0xB4u, 0x40u},
- {0xB5u, 0x21u},
- {0xC0u, 0xF5u},
- {0xC2u, 0x6Eu},
- {0xC4u, 0xFFu},
- {0xCAu, 0xEFu},
- {0xCCu, 0xF4u},
- {0xCEu, 0x7Fu},
+ {0x92u, 0x10u},
+ {0x93u, 0x40u},
+ {0x94u, 0x44u},
+ {0x96u, 0x45u},
+ {0x99u, 0x08u},
+ {0x9Bu, 0x20u},
+ {0x9Cu, 0x41u},
+ {0x9Du, 0x20u},
+ {0x9Eu, 0x10u},
+ {0x9Fu, 0xD0u},
+ {0xA0u, 0x28u},
+ {0xA3u, 0x40u},
+ {0xA5u, 0x44u},
+ {0xA6u, 0x02u},
+ {0xA9u, 0x40u},
+ {0xAEu, 0x04u},
+ {0xAFu, 0x04u},
+ {0xB0u, 0x10u},
+ {0xB4u, 0x01u},
+ {0xB6u, 0x20u},
+ {0xB7u, 0x68u},
+ {0xC0u, 0xC4u},
+ {0xC2u, 0xFBu},
+ {0xC4u, 0xF7u},
+ {0xCAu, 0xC7u},
+ {0xCCu, 0xFFu},
+ {0xCEu, 0xFDu},
{0xD6u, 0x0Fu},
{0xD8u, 0x08u},
- {0xE0u, 0x01u},
- {0xEAu, 0x0Cu},
- {0xEEu, 0x10u},
- {0x01u, 0x5Bu},
- {0x03u, 0x24u},
- {0x04u, 0x01u},
- {0x08u, 0x08u},
- {0x09u, 0x58u},
- {0x0Au, 0x12u},
- {0x0Bu, 0xA4u},
- {0x0Cu, 0x40u},
- {0x11u, 0x02u},
- {0x14u, 0x0Bu},
- {0x15u, 0x0Cu},
- {0x16u, 0x24u},
- {0x17u, 0x40u},
- {0x1Bu, 0x01u},
- {0x1Eu, 0x3Fu},
- {0x20u, 0x80u},
- {0x23u, 0x1Fu},
- {0x26u, 0x20u},
- {0x29u, 0x40u},
- {0x2Bu, 0xB7u},
- {0x2Cu, 0x34u},
- {0x2Du, 0x03u},
- {0x2Eu, 0x0Bu},
- {0x2Fu, 0x0Cu},
- {0x30u, 0x80u},
- {0x31u, 0x1Fu},
- {0x32u, 0x07u},
- {0x33u, 0x80u},
- {0x34u, 0x38u},
- {0x35u, 0x20u},
- {0x36u, 0x40u},
- {0x37u, 0x40u},
- {0x3Eu, 0x41u},
- {0x3Fu, 0x54u},
- {0x40u, 0x64u},
- {0x41u, 0x03u},
- {0x42u, 0x20u},
- {0x45u, 0xDCu},
- {0x46u, 0x2Fu},
- {0x47u, 0x0Eu},
- {0x48u, 0x1Fu},
- {0x49u, 0xFFu},
- {0x4Au, 0xFFu},
- {0x4Bu, 0xFFu},
- {0x4Fu, 0x2Cu},
- {0x56u, 0x01u},
+ {0xE2u, 0x0Eu},
+ {0xE6u, 0x39u},
+ {0xE8u, 0x01u},
+ {0xEAu, 0x02u},
+ {0x81u, 0x04u},
+ {0x82u, 0x20u},
+ {0x89u, 0x40u},
+ {0x90u, 0x80u},
+ {0x94u, 0x44u},
+ {0x96u, 0x44u},
+ {0x97u, 0x10u},
+ {0x9Cu, 0x81u},
+ {0x9Eu, 0x30u},
+ {0xA5u, 0x44u},
+ {0xA6u, 0x04u},
+ {0xA7u, 0x20u},
+ {0xA9u, 0x80u},
+ {0xADu, 0x20u},
+ {0xAFu, 0x10u},
+ {0xB3u, 0x05u},
+ {0xB5u, 0x05u},
+ {0xE2u, 0x04u},
+ {0xE4u, 0x80u},
+ {0xEAu, 0x04u},
+ {0xEEu, 0x82u},
+ {0x03u, 0x08u},
+ {0x13u, 0x07u},
+ {0x15u, 0x19u},
+ {0x17u, 0x22u},
+ {0x19u, 0x14u},
+ {0x1Bu, 0x48u},
+ {0x1Du, 0x80u},
+ {0x21u, 0x6Au},
+ {0x23u, 0x15u},
+ {0x24u, 0x02u},
+ {0x27u, 0x20u},
+ {0x28u, 0x01u},
+ {0x2Fu, 0x70u},
+ {0x32u, 0x02u},
+ {0x33u, 0x70u},
+ {0x34u, 0x01u},
+ {0x35u, 0x80u},
+ {0x37u, 0x0Fu},
+ {0x3Eu, 0x14u},
+ {0x3Fu, 0x10u},
{0x58u, 0x04u},
{0x59u, 0x04u},
- {0x5Au, 0x04u},
- {0x5Bu, 0x04u},
- {0x5Cu, 0x99u},
- {0x5Du, 0x09u},
+ {0x5Cu, 0x10u},
{0x5Fu, 0x01u},
- {0x62u, 0xC0u},
- {0x66u, 0x80u},
- {0x68u, 0x40u},
- {0x69u, 0x40u},
- {0x6Eu, 0x08u},
- {0x01u, 0x20u},
- {0x03u, 0x22u},
- {0x0Au, 0x10u},
- {0x0Bu, 0x02u},
- {0x11u, 0x01u},
- {0x12u, 0x22u},
- {0x18u, 0x60u},
- {0x19u, 0x78u},
- {0x1Au, 0x10u},
- {0x21u, 0x11u},
- {0x22u, 0x06u},
- {0x23u, 0x01u},
- {0x29u, 0x12u},
+ {0x00u, 0xA0u},
+ {0x01u, 0x01u},
+ {0x0Au, 0xAAu},
+ {0x11u, 0x40u},
+ {0x12u, 0x60u},
+ {0x13u, 0x02u},
+ {0x14u, 0x28u},
+ {0x17u, 0x08u},
+ {0x19u, 0x02u},
+ {0x1Cu, 0x10u},
+ {0x1Fu, 0x10u},
+ {0x20u, 0x04u},
+ {0x21u, 0x10u},
+ {0x22u, 0x15u},
+ {0x23u, 0x10u},
+ {0x27u, 0x15u},
+ {0x29u, 0x20u},
{0x2Au, 0x40u},
- {0x31u, 0x05u},
- {0x33u, 0x21u},
- {0x38u, 0x20u},
- {0x39u, 0x02u},
- {0x41u, 0x11u},
- {0x42u, 0x50u},
- {0x49u, 0x15u},
- {0x50u, 0x48u},
- {0x52u, 0x20u},
- {0x53u, 0x88u},
- {0x58u, 0x08u},
- {0x5Au, 0x82u},
- {0x5Bu, 0x20u},
- {0x5Cu, 0x80u},
- {0x5Du, 0x40u},
- {0x60u, 0x44u},
- {0x61u, 0x48u},
- {0x68u, 0x40u},
- {0x69u, 0x44u},
- {0x6Au, 0x20u},
- {0x70u, 0x20u},
- {0x72u, 0x01u},
- {0x73u, 0x50u},
- {0x7Eu, 0x10u},
- {0x7Fu, 0x10u},
- {0x80u, 0x08u},
- {0x89u, 0x01u},
- {0x8Au, 0x04u},
- {0x8Du, 0x02u},
- {0x8Fu, 0x01u},
- {0xC0u, 0x07u},
- {0xC2u, 0x05u},
- {0xC4u, 0x0Du},
- {0xCAu, 0x0Du},
- {0xCCu, 0x07u},
- {0xCEu, 0x05u},
+ {0x2Bu, 0x08u},
+ {0x2Cu, 0x40u},
+ {0x2Du, 0x88u},
+ {0x2Fu, 0x40u},
+ {0x32u, 0x55u},
+ {0x34u, 0x80u},
+ {0x35u, 0x04u},
+ {0x37u, 0x11u},
+ {0x39u, 0x55u},
+ {0x3Cu, 0x02u},
+ {0x40u, 0x40u},
+ {0x41u, 0x14u},
+ {0x46u, 0x20u},
+ {0x47u, 0x04u},
+ {0x48u, 0x40u},
+ {0x49u, 0x41u},
+ {0x4Bu, 0x14u},
+ {0x52u, 0x11u},
+ {0x53u, 0x0Cu},
+ {0x62u, 0x08u},
+ {0x68u, 0x1Cu},
+ {0x69u, 0x55u},
+ {0x73u, 0x02u},
+ {0x83u, 0x10u},
+ {0x89u, 0x04u},
+ {0x8Bu, 0x01u},
+ {0x90u, 0x08u},
+ {0x92u, 0x04u},
+ {0x93u, 0x82u},
+ {0x94u, 0x10u},
+ {0x95u, 0x65u},
+ {0x96u, 0xEAu},
+ {0x97u, 0x20u},
+ {0x98u, 0x12u},
+ {0x99u, 0x8Cu},
+ {0x9Au, 0x82u},
+ {0x9Cu, 0x88u},
+ {0x9Du, 0x02u},
+ {0x9Eu, 0x20u},
+ {0x9Fu, 0x1Au},
+ {0xA0u, 0x81u},
+ {0xA1u, 0x08u},
+ {0xA2u, 0x30u},
+ {0xA4u, 0x54u},
+ {0xA5u, 0x04u},
+ {0xA6u, 0x02u},
+ {0xA7u, 0x01u},
+ {0xA9u, 0x20u},
+ {0xADu, 0x80u},
+ {0xB2u, 0x15u},
+ {0xB6u, 0x09u},
+ {0xC0u, 0x0Bu},
+ {0xC2u, 0x0Fu},
+ {0xC4u, 0x6Du},
+ {0xCAu, 0xDCu},
+ {0xCCu, 0xFFu},
+ {0xCEu, 0x8Fu},
{0xD0u, 0x07u},
- {0xD2u, 0x04u},
- {0xD6u, 0x0Fu},
- {0xD8u, 0x0Fu},
- {0xE0u, 0x40u},
- {0xE2u, 0x80u},
- {0xE6u, 0x01u},
- {0xECu, 0x40u},
- {0xEEu, 0x02u},
- {0xE2u, 0x20u},
- {0xEEu, 0x08u},
+ {0xD2u, 0x0Cu},
+ {0xD8u, 0x02u},
+ {0xE4u, 0x80u},
+ {0xE6u, 0x20u},
+ {0xEAu, 0x90u},
+ {0xEEu, 0xE0u},
{0x00u, 0xC0u},
- {0x01u, 0x64u},
{0x02u, 0x02u},
- {0x06u, 0x9Fu},
- {0x07u, 0xF5u},
- {0x08u, 0x80u},
- {0x09u, 0x07u},
- {0x0Bu, 0x90u},
- {0x0Cu, 0xC0u},
- {0x0Du, 0x83u},
- {0x0Eu, 0x01u},
- {0x0Fu, 0x70u},
- {0x11u, 0x64u},
+ {0x04u, 0xC0u},
+ {0x06u, 0x08u},
+ {0x08u, 0xC0u},
+ {0x0Au, 0x04u},
+ {0x0Eu, 0x9Fu},
+ {0x11u, 0x01u},
{0x12u, 0xFFu},
{0x14u, 0x1Fu},
{0x16u, 0x20u},
- {0x17u, 0x64u},
{0x18u, 0x7Fu},
- {0x19u, 0x24u},
{0x1Au, 0x80u},
- {0x1Du, 0x64u},
- {0x1Eu, 0x60u},
- {0x20u, 0x90u},
- {0x21u, 0x08u},
- {0x22u, 0x40u},
- {0x24u, 0xC0u},
- {0x25u, 0x24u},
- {0x26u, 0x08u},
- {0x27u, 0x40u},
- {0x28u, 0xC0u},
- {0x29u, 0x40u},
- {0x2Au, 0x04u},
- {0x2Bu, 0x02u},
- {0x2Du, 0x08u},
- {0x30u, 0xFFu},
- {0x31u, 0x80u},
- {0x33u, 0x07u},
- {0x35u, 0x71u},
- {0x37u, 0x08u},
- {0x39u, 0x80u},
- {0x3Bu, 0x0Cu},
- {0x3Eu, 0x01u},
- {0x3Fu, 0x01u},
- {0x54u, 0x09u},
- {0x56u, 0x04u},
+ {0x1Cu, 0x80u},
+ {0x20u, 0xC0u},
+ {0x21u, 0x02u},
+ {0x22u, 0x01u},
+ {0x26u, 0x60u},
+ {0x29u, 0x02u},
+ {0x2Cu, 0x90u},
+ {0x2Du, 0x04u},
+ {0x2Eu, 0x40u},
+ {0x31u, 0x01u},
+ {0x34u, 0xFFu},
+ {0x35u, 0x02u},
+ {0x37u, 0x04u},
+ {0x39u, 0x20u},
+ {0x3Eu, 0x10u},
+ {0x3Fu, 0x41u},
{0x58u, 0x04u},
{0x59u, 0x04u},
- {0x5Bu, 0x04u},
{0x5Fu, 0x01u},
- {0x86u, 0x01u},
- {0x90u, 0x04u},
- {0x92u, 0x43u},
- {0x94u, 0x88u},
- {0x95u, 0x50u},
- {0x96u, 0x03u},
- {0x97u, 0xA0u},
+ {0x80u, 0x01u},
+ {0x86u, 0x58u},
+ {0x89u, 0x01u},
+ {0x8Eu, 0xFEu},
+ {0x94u, 0x76u},
+ {0x96u, 0x80u},
+ {0x98u, 0x06u},
+ {0x9Au, 0x08u},
+ {0x9Cu, 0x9Eu},
+ {0x9Eu, 0x60u},
+ {0xA0u, 0x20u},
+ {0xA2u, 0x02u},
+ {0xA8u, 0x06u},
+ {0xACu, 0x04u},
+ {0xB0u, 0x01u},
+ {0xB2u, 0xE0u},
+ {0xB5u, 0x01u},
+ {0xB6u, 0x1Eu},
+ {0xBEu, 0x01u},
+ {0xBFu, 0x10u},
+ {0xC0u, 0x21u},
+ {0xC1u, 0x03u},
+ {0xC2u, 0x60u},
+ {0xC5u, 0xF2u},
+ {0xC6u, 0xE0u},
+ {0xC7u, 0xDCu},
+ {0xC8u, 0x3Bu},
+ {0xC9u, 0xFFu},
+ {0xCAu, 0xFFu},
+ {0xCBu, 0xFFu},
+ {0xCFu, 0x2Cu},
+ {0xD6u, 0x01u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDAu, 0x04u},
+ {0xDBu, 0x04u},
+ {0xDCu, 0x01u},
+ {0xDDu, 0x01u},
+ {0xDFu, 0x01u},
+ {0xE2u, 0xC0u},
+ {0xE6u, 0x80u},
+ {0xE8u, 0x40u},
+ {0xE9u, 0x40u},
+ {0xEEu, 0x08u},
+ {0x00u, 0xA8u},
+ {0x01u, 0x01u},
+ {0x03u, 0x20u},
+ {0x05u, 0x80u},
+ {0x06u, 0x40u},
+ {0x07u, 0x10u},
+ {0x08u, 0x01u},
+ {0x0Au, 0xAAu},
+ {0x0Du, 0x08u},
+ {0x0Eu, 0x0Au},
+ {0x10u, 0x40u},
+ {0x11u, 0x40u},
+ {0x12u, 0x20u},
+ {0x13u, 0x02u},
+ {0x16u, 0x89u},
+ {0x17u, 0x01u},
+ {0x19u, 0x20u},
+ {0x1Cu, 0x40u},
+ {0x1Du, 0x8Cu},
+ {0x1Eu, 0x02u},
+ {0x1Fu, 0x4Cu},
+ {0x22u, 0x20u},
+ {0x23u, 0x41u},
+ {0x24u, 0x04u},
+ {0x29u, 0x62u},
+ {0x31u, 0x01u},
+ {0x3Fu, 0x10u},
+ {0x45u, 0x88u},
+ {0x47u, 0x10u},
+ {0x4Cu, 0x40u},
+ {0x4Du, 0x18u},
+ {0x4Fu, 0x04u},
+ {0x55u, 0x20u},
+ {0x56u, 0x09u},
+ {0x5Cu, 0x55u},
+ {0x66u, 0x20u},
+ {0x67u, 0x61u},
+ {0x6Cu, 0x95u},
+ {0x74u, 0x29u},
+ {0x76u, 0x02u},
+ {0x81u, 0x04u},
+ {0x82u, 0x40u},
+ {0x84u, 0x08u},
+ {0x87u, 0x04u},
+ {0x8Eu, 0x06u},
+ {0x8Fu, 0x02u},
+ {0x90u, 0x01u},
+ {0x91u, 0x10u},
+ {0x92u, 0x05u},
+ {0x93u, 0x12u},
+ {0x94u, 0xA2u},
+ {0x95u, 0x65u},
+ {0x96u, 0x48u},
+ {0x97u, 0x84u},
+ {0x98u, 0x12u},
+ {0x99u, 0xC1u},
+ {0x9Au, 0x40u},
+ {0x9Bu, 0x01u},
+ {0x9Cu, 0xC9u},
+ {0x9Du, 0x04u},
+ {0x9Fu, 0x18u},
+ {0xA2u, 0x14u},
+ {0xA3u, 0x02u},
+ {0xA4u, 0x20u},
+ {0xA5u, 0x2Cu},
+ {0xA6u, 0x01u},
+ {0xA7u, 0x29u},
+ {0xADu, 0x10u},
+ {0xB0u, 0x10u},
+ {0xB4u, 0x02u},
+ {0xB6u, 0x42u},
+ {0xB7u, 0x01u},
+ {0xC0u, 0xBFu},
+ {0xC2u, 0xEFu},
+ {0xC4u, 0xDDu},
+ {0xCAu, 0x0Du},
+ {0xCCu, 0x01u},
+ {0xCEu, 0x20u},
+ {0xD0u, 0x70u},
+ {0xD2u, 0x20u},
+ {0xD6u, 0xF0u},
+ {0xD8u, 0xF0u},
+ {0xE2u, 0x48u},
+ {0xE6u, 0x70u},
+ {0xE8u, 0x41u},
+ {0xECu, 0x80u},
+ {0xEEu, 0x50u},
+ {0x02u, 0x08u},
+ {0x04u, 0x99u},
+ {0x05u, 0x20u},
+ {0x06u, 0x22u},
+ {0x0Au, 0x80u},
+ {0x0Fu, 0x01u},
+ {0x13u, 0x0Eu},
+ {0x16u, 0x70u},
+ {0x19u, 0x08u},
+ {0x1Au, 0x07u},
+ {0x1Bu, 0x10u},
+ {0x1Cu, 0xAAu},
+ {0x1Eu, 0x55u},
+ {0x21u, 0x14u},
+ {0x23u, 0x0Au},
+ {0x27u, 0x10u},
+ {0x28u, 0x44u},
+ {0x29u, 0x12u},
+ {0x2Au, 0x88u},
+ {0x2Bu, 0x04u},
+ {0x31u, 0x1Eu},
+ {0x32u, 0xF0u},
+ {0x34u, 0x0Fu},
+ {0x35u, 0x01u},
+ {0x37u, 0x20u},
+ {0x3Fu, 0x40u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Cu, 0x11u},
+ {0x5Fu, 0x01u},
+ {0x80u, 0x55u},
+ {0x81u, 0x0Du},
+ {0x82u, 0xAAu},
+ {0x85u, 0x0Du},
+ {0x86u, 0xFFu},
+ {0x89u, 0x11u},
+ {0x8Au, 0xFFu},
+ {0x8Bu, 0x22u},
+ {0x8Du, 0x0Du},
+ {0x8Eu, 0xFFu},
+ {0x90u, 0xFFu},
+ {0x95u, 0x22u},
+ {0x97u, 0x18u},
{0x99u, 0x60u},
- {0x9Au, 0xECu},
- {0x9Bu, 0x90u},
- {0x9Cu, 0xE0u},
- {0x9Du, 0x0Fu},
- {0x9Fu, 0xF0u},
- {0xA1u, 0x03u},
- {0xA3u, 0x0Cu},
- {0xA5u, 0x05u},
- {0xA6u, 0x12u},
- {0xA7u, 0x0Au},
- {0xA8u, 0x21u},
- {0xA9u, 0x06u},
- {0xAAu, 0x02u},
- {0xABu, 0x09u},
- {0xADu, 0x30u},
- {0xAFu, 0xC0u},
- {0xB2u, 0x10u},
- {0xB3u, 0xFFu},
- {0xB4u, 0x0Fu},
- {0xB6u, 0xE0u},
+ {0x9Cu, 0x69u},
+ {0x9Du, 0x02u},
+ {0x9Eu, 0x96u},
+ {0x9Fu, 0x0Du},
+ {0xA1u, 0x0Du},
+ {0xA4u, 0x33u},
+ {0xA5u, 0x0Du},
+ {0xA6u, 0xCCu},
+ {0xAAu, 0xFFu},
+ {0xACu, 0x0Fu},
+ {0xADu, 0x12u},
+ {0xAEu, 0xF0u},
+ {0xAFu, 0x44u},
+ {0xB0u, 0xFFu},
+ {0xB5u, 0x70u},
+ {0xB7u, 0x0Fu},
+ {0xB8u, 0x80u},
+ {0xB9u, 0x20u},
+ {0xBAu, 0x02u},
+ {0xBBu, 0x80u},
{0xBEu, 0x40u},
- {0xBFu, 0x04u},
+ {0xD6u, 0x08u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDBu, 0x04u},
+ {0xDCu, 0x01u},
+ {0xDDu, 0x90u},
+ {0xDFu, 0x01u},
+ {0x01u, 0x80u},
+ {0x02u, 0x80u},
+ {0x03u, 0x18u},
+ {0x04u, 0x22u},
+ {0x05u, 0x04u},
+ {0x08u, 0x80u},
+ {0x0Bu, 0x80u},
+ {0x0Eu, 0x26u},
+ {0x10u, 0x02u},
+ {0x12u, 0x18u},
+ {0x17u, 0x10u},
+ {0x1Au, 0x01u},
+ {0x1Bu, 0x02u},
+ {0x1Eu, 0x24u},
+ {0x1Fu, 0x04u},
+ {0x22u, 0x50u},
+ {0x24u, 0x01u},
+ {0x25u, 0x10u},
+ {0x26u, 0x02u},
+ {0x28u, 0x41u},
+ {0x2Bu, 0x20u},
+ {0x2Cu, 0x22u},
+ {0x2Fu, 0x4Au},
+ {0x32u, 0x54u},
+ {0x36u, 0x02u},
+ {0x37u, 0x10u},
+ {0x39u, 0x65u},
+ {0x3Cu, 0x04u},
+ {0x3Du, 0x80u},
+ {0x58u, 0x04u},
+ {0x59u, 0x12u},
+ {0x5Bu, 0x40u},
+ {0x60u, 0x04u},
+ {0x61u, 0x01u},
+ {0x62u, 0x50u},
+ {0x63u, 0x10u},
+ {0x80u, 0x80u},
+ {0x81u, 0x02u},
+ {0x83u, 0x50u},
+ {0x85u, 0x60u},
+ {0x86u, 0x04u},
+ {0x8Bu, 0x01u},
+ {0x8Cu, 0x40u},
+ {0x8Eu, 0x10u},
+ {0x91u, 0x10u},
+ {0x96u, 0x40u},
+ {0x97u, 0x1Cu},
+ {0x98u, 0x04u},
+ {0x99u, 0xD0u},
+ {0x9Cu, 0x08u},
+ {0x9Du, 0x01u},
+ {0x9Eu, 0x40u},
+ {0x9Fu, 0x19u},
+ {0xA2u, 0x8Cu},
+ {0xA4u, 0x80u},
+ {0xA5u, 0x1Cu},
+ {0xA6u, 0x01u},
+ {0xA7u, 0x01u},
+ {0xA9u, 0x40u},
+ {0xABu, 0x40u},
+ {0xACu, 0x20u},
+ {0xB1u, 0x20u},
+ {0xB7u, 0x02u},
+ {0xC0u, 0x7Fu},
+ {0xC2u, 0xE9u},
+ {0xC4u, 0x47u},
+ {0xCAu, 0xEBu},
+ {0xCCu, 0xAEu},
+ {0xCEu, 0x5Fu},
+ {0xD6u, 0x0Fu},
+ {0xD8u, 0x0Fu},
+ {0xE0u, 0x81u},
+ {0xE2u, 0x40u},
+ {0xE4u, 0x20u},
+ {0xE6u, 0x15u},
+ {0xEAu, 0x20u},
+ {0xEEu, 0x01u},
+ {0x03u, 0xFFu},
+ {0x06u, 0xFFu},
+ {0x0Au, 0xFFu},
+ {0x0Du, 0x0Fu},
+ {0x0Eu, 0xFFu},
+ {0x0Fu, 0xF0u},
+ {0x11u, 0xFFu},
+ {0x16u, 0xFFu},
+ {0x17u, 0xFFu},
+ {0x18u, 0x0Fu},
+ {0x1Au, 0xF0u},
+ {0x1Bu, 0xFFu},
+ {0x20u, 0x33u},
+ {0x21u, 0x96u},
+ {0x22u, 0xCCu},
+ {0x23u, 0x69u},
+ {0x24u, 0x55u},
+ {0x26u, 0xAAu},
+ {0x27u, 0xFFu},
+ {0x28u, 0x69u},
+ {0x29u, 0x55u},
+ {0x2Au, 0x96u},
+ {0x2Bu, 0xAAu},
+ {0x2Cu, 0xFFu},
+ {0x2Du, 0x33u},
+ {0x2Fu, 0xCCu},
+ {0x34u, 0xFFu},
+ {0x37u, 0xFFu},
+ {0x3Au, 0x20u},
+ {0x3Bu, 0x80u},
+ {0x56u, 0x08u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x11u},
+ {0x5Du, 0x90u},
+ {0x5Fu, 0x01u},
+ {0x83u, 0x02u},
+ {0x87u, 0x80u},
+ {0x89u, 0x30u},
+ {0x8Bu, 0x01u},
+ {0x8Du, 0x30u},
+ {0x8Eu, 0x03u},
+ {0x90u, 0x03u},
+ {0x91u, 0x06u},
+ {0x92u, 0x0Cu},
+ {0x93u, 0x08u},
+ {0x94u, 0x05u},
+ {0x95u, 0x10u},
+ {0x96u, 0x0Au},
+ {0x97u, 0x22u},
+ {0x99u, 0x02u},
+ {0x9Au, 0x02u},
+ {0x9Bu, 0x0Cu},
+ {0x9Cu, 0x06u},
+ {0x9Du, 0x04u},
+ {0x9Eu, 0x09u},
+ {0x9Fu, 0x0Au},
+ {0xA0u, 0x01u},
+ {0xA1u, 0x04u},
+ {0xA3u, 0x0Au},
+ {0xA5u, 0x20u},
+ {0xA7u, 0x10u},
+ {0xA8u, 0x07u},
+ {0xAAu, 0x08u},
+ {0xABu, 0x40u},
+ {0xADu, 0x40u},
+ {0xAFu, 0x80u},
+ {0xB0u, 0x0Fu},
+ {0xB1u, 0x01u},
+ {0xB3u, 0x30u},
+ {0xB5u, 0x0Eu},
+ {0xB7u, 0xC0u},
+ {0xBAu, 0x02u},
+ {0xBBu, 0x28u},
+ {0xBFu, 0x40u},
+ {0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
+ {0xDCu, 0x11u},
+ {0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x01u, 0x08u},
- {0x05u, 0x10u},
- {0x06u, 0x12u},
- {0x07u, 0x40u},
- {0x09u, 0x46u},
+ {0x01u, 0x80u},
+ {0x02u, 0x08u},
+ {0x03u, 0x10u},
+ {0x05u, 0x80u},
+ {0x09u, 0x08u},
{0x0Au, 0x04u},
- {0x0Du, 0x82u},
- {0x0Eu, 0x28u},
- {0x11u, 0x20u},
- {0x12u, 0x10u},
- {0x16u, 0x08u},
- {0x17u, 0x15u},
- {0x19u, 0x08u},
- {0x1Au, 0x06u},
- {0x1Eu, 0x40u},
- {0x22u, 0x08u},
- {0x24u, 0x20u},
- {0x25u, 0x94u},
- {0x26u, 0x14u},
- {0x27u, 0x88u},
- {0x28u, 0x18u},
- {0x29u, 0x02u},
- {0x2Au, 0x80u},
- {0x2Du, 0x20u},
- {0x2Eu, 0x48u},
- {0x2Fu, 0x88u},
- {0x31u, 0x28u},
- {0x32u, 0x40u},
- {0x35u, 0x10u},
- {0x37u, 0x45u},
+ {0x0Du, 0x08u},
+ {0x0Eu, 0x82u},
+ {0x0Fu, 0x24u},
+ {0x10u, 0x01u},
+ {0x12u, 0x40u},
+ {0x13u, 0x18u},
+ {0x17u, 0x11u},
+ {0x19u, 0x20u},
+ {0x1Au, 0x04u},
+ {0x1Eu, 0x80u},
+ {0x21u, 0x40u},
+ {0x24u, 0x48u},
+ {0x26u, 0x2Cu},
+ {0x27u, 0x02u},
+ {0x28u, 0x08u},
+ {0x29u, 0x01u},
+ {0x2Bu, 0x11u},
+ {0x2Cu, 0xA0u},
+ {0x2Eu, 0x40u},
+ {0x2Fu, 0x04u},
+ {0x30u, 0x01u},
+ {0x32u, 0x08u},
+ {0x33u, 0x10u},
+ {0x34u, 0x01u},
+ {0x36u, 0x29u},
+ {0x37u, 0x80u},
+ {0x39u, 0x80u},
+ {0x3Bu, 0x01u},
{0x3Cu, 0x40u},
{0x3Du, 0x28u},
- {0x3Eu, 0x02u},
- {0x5Du, 0x24u},
- {0x5Eu, 0x02u},
- {0x5Fu, 0x80u},
- {0x67u, 0x42u},
- {0x69u, 0x80u},
- {0x6Au, 0x80u},
- {0x78u, 0x20u},
- {0x7Au, 0x08u},
- {0x8Bu, 0x40u},
- {0x8Cu, 0x04u},
- {0x90u, 0x40u},
- {0x91u, 0x04u},
- {0x92u, 0x08u},
- {0x93u, 0x0Eu},
- {0x94u, 0x28u},
- {0x95u, 0x99u},
- {0x98u, 0x19u},
- {0x99u, 0x12u},
- {0x9Au, 0x12u},
- {0x9Bu, 0x55u},
- {0x9Cu, 0x20u},
- {0x9Du, 0xC1u},
- {0xA1u, 0x42u},
- {0xA2u, 0x01u},
- {0xA3u, 0x3Au},
- {0xA4u, 0x10u},
- {0xA5u, 0x3Cu},
- {0xA6u, 0x12u},
- {0xA8u, 0x01u},
- {0xC0u, 0xF4u},
- {0xC2u, 0xFFu},
- {0xC4u, 0x76u},
+ {0x3Fu, 0x01u},
+ {0x4Cu, 0x04u},
+ {0x4Du, 0x10u},
+ {0x5Bu, 0x40u},
+ {0x5Du, 0x40u},
+ {0x61u, 0x40u},
+ {0x62u, 0x80u},
+ {0x65u, 0x80u},
+ {0x67u, 0x01u},
+ {0x81u, 0x40u},
+ {0x86u, 0x40u},
+ {0x88u, 0x04u},
+ {0x89u, 0x08u},
+ {0x8Bu, 0x80u},
+ {0x8Du, 0x10u},
+ {0xC0u, 0x87u},
+ {0xC2u, 0xF6u},
+ {0xC4u, 0x5Fu},
{0xCAu, 0xFFu},
- {0xCCu, 0xFEu},
- {0xCEu, 0xF0u},
- {0xD6u, 0xF0u},
- {0xD8u, 0x90u},
- {0xE2u, 0x20u},
- {0xEEu, 0x0Cu},
- {0x02u, 0x40u},
+ {0xCCu, 0xF7u},
+ {0xCEu, 0xF9u},
+ {0xD6u, 0x18u},
+ {0xD8u, 0x18u},
+ {0xE2u, 0x10u},
+ {0x86u, 0x04u},
+ {0x8Au, 0x10u},
+ {0x96u, 0x04u},
+ {0x9Eu, 0x10u},
+ {0xA8u, 0xC0u},
+ {0xB3u, 0x30u},
+ {0xB6u, 0x44u},
+ {0xE2u, 0x06u},
+ {0xE6u, 0x01u},
+ {0xE8u, 0x01u},
+ {0xEEu, 0x01u},
+ {0x80u, 0x40u},
+ {0x84u, 0x01u},
+ {0x90u, 0x80u},
+ {0x94u, 0x40u},
+ {0x96u, 0x44u},
+ {0x97u, 0x10u},
+ {0x9Cu, 0x81u},
+ {0x9Eu, 0x10u},
+ {0xA6u, 0x04u},
+ {0xA7u, 0x20u},
+ {0xA8u, 0x04u},
+ {0xE2u, 0x02u},
+ {0xE6u, 0x04u},
+ {0xEAu, 0x06u},
+ {0xEEu, 0x08u},
+ {0x01u, 0xFFu},
{0x05u, 0x30u},
+ {0x06u, 0x80u},
{0x07u, 0xC0u},
{0x09u, 0x50u},
{0x0Bu, 0xA0u},
- {0x0Cu, 0x01u},
- {0x0Eu, 0x12u},
- {0x10u, 0x53u},
- {0x12u, 0xACu},
- {0x13u, 0xFFu},
- {0x15u, 0xFFu},
- {0x18u, 0x02u},
- {0x1Au, 0x01u},
- {0x1Bu, 0xFFu},
- {0x1Cu, 0x08u},
+ {0x0Eu, 0x08u},
+ {0x0Fu, 0xFFu},
+ {0x11u, 0x05u},
+ {0x13u, 0x0Au},
+ {0x14u, 0x99u},
+ {0x16u, 0x22u},
+ {0x19u, 0x03u},
+ {0x1Au, 0x07u},
+ {0x1Bu, 0x0Cu},
{0x1Du, 0x0Fu},
- {0x1Eu, 0x04u},
+ {0x1Eu, 0x70u},
{0x1Fu, 0xF0u},
- {0x20u, 0x04u},
- {0x21u, 0x60u},
- {0x22u, 0x28u},
- {0x23u, 0x90u},
- {0x25u, 0x05u},
- {0x27u, 0x0Au},
- {0x29u, 0x06u},
- {0x2Bu, 0x09u},
- {0x2Du, 0x03u},
- {0x2Eu, 0x80u},
- {0x2Fu, 0x0Cu},
- {0x30u, 0x0Fu},
- {0x32u, 0x30u},
+ {0x20u, 0xAAu},
+ {0x22u, 0x55u},
+ {0x25u, 0x06u},
+ {0x27u, 0x09u},
+ {0x28u, 0x44u},
+ {0x2Au, 0x88u},
+ {0x2Bu, 0xFFu},
+ {0x2Du, 0x60u},
+ {0x2Fu, 0x90u},
{0x33u, 0xFFu},
- {0x34u, 0xC0u},
- {0x3Eu, 0x15u},
+ {0x34u, 0x0Fu},
+ {0x36u, 0xF0u},
{0x3Fu, 0x04u},
{0x58u, 0x04u},
{0x59u, 0x04u},
+ {0x5Cu, 0x01u},
+ {0x5Fu, 0x01u},
+ {0x80u, 0x36u},
+ {0x84u, 0x07u},
+ {0x85u, 0x11u},
+ {0x86u, 0x08u},
+ {0x87u, 0x62u},
+ {0x88u, 0x32u},
+ {0x89u, 0x58u},
+ {0x8Au, 0x04u},
+ {0x8Bu, 0x23u},
+ {0x8Cu, 0x06u},
+ {0x8Du, 0x34u},
+ {0x8Eu, 0x30u},
+ {0x8Fu, 0x43u},
+ {0x90u, 0x09u},
+ {0x92u, 0x06u},
+ {0x94u, 0x01u},
+ {0x95u, 0x40u},
+ {0x96u, 0x0Eu},
+ {0x97u, 0x30u},
+ {0x98u, 0x04u},
+ {0x9Bu, 0x0Cu},
+ {0x9Cu, 0x02u},
+ {0x9Fu, 0x01u},
+ {0xA0u, 0x36u},
+ {0xA3u, 0x82u},
+ {0xA8u, 0x30u},
+ {0xAAu, 0x06u},
+ {0xAEu, 0x20u},
+ {0xB0u, 0x0Fu},
+ {0xB3u, 0x70u},
+ {0xB4u, 0x20u},
+ {0xB5u, 0x0Fu},
+ {0xB6u, 0x10u},
+ {0xB7u, 0x80u},
+ {0xB8u, 0x02u},
+ {0xBBu, 0x08u},
+ {0xBEu, 0x50u},
+ {0xD6u, 0x08u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDBu, 0x04u},
+ {0xDDu, 0x90u},
+ {0xDFu, 0x01u},
+ {0x00u, 0x24u},
+ {0x01u, 0x41u},
+ {0x04u, 0x08u},
+ {0x06u, 0x02u},
+ {0x0Au, 0x82u},
+ {0x0Bu, 0x18u},
+ {0x0Du, 0x08u},
+ {0x0Eu, 0x0Au},
+ {0x10u, 0x08u},
+ {0x12u, 0x01u},
+ {0x13u, 0x02u},
+ {0x14u, 0x40u},
+ {0x17u, 0x10u},
+ {0x18u, 0x40u},
+ {0x19u, 0x40u},
+ {0x1Au, 0x81u},
+ {0x1Bu, 0x10u},
+ {0x1Eu, 0x0Au},
+ {0x1Fu, 0x10u},
+ {0x22u, 0x98u},
+ {0x24u, 0x20u},
+ {0x29u, 0x01u},
+ {0x2Eu, 0x14u},
+ {0x2Fu, 0x02u},
+ {0x32u, 0x98u},
+ {0x36u, 0x11u},
+ {0x37u, 0x40u},
+ {0x38u, 0x44u},
+ {0x3Bu, 0x10u},
+ {0x3Cu, 0x02u},
+ {0x3Du, 0x08u},
+ {0x3Eu, 0xA0u},
+ {0x58u, 0x16u},
+ {0x59u, 0x80u},
+ {0x60u, 0xA8u},
+ {0x63u, 0x02u},
+ {0x69u, 0x80u},
+ {0x6Au, 0x40u},
+ {0x81u, 0x80u},
+ {0x82u, 0x10u},
+ {0x87u, 0x01u},
+ {0x90u, 0x0Cu},
+ {0x91u, 0x61u},
+ {0x92u, 0x06u},
+ {0x93u, 0x9Eu},
+ {0x94u, 0x60u},
+ {0x96u, 0xC0u},
+ {0x98u, 0x52u},
+ {0x99u, 0x21u},
+ {0x9Au, 0x93u},
+ {0x9Bu, 0x12u},
+ {0x9Cu, 0xA8u},
+ {0x9Du, 0x40u},
+ {0xA0u, 0x98u},
+ {0xA1u, 0x08u},
+ {0xA2u, 0x10u},
+ {0xA5u, 0x04u},
+ {0xA6u, 0x0Au},
+ {0xA7u, 0x01u},
+ {0xA8u, 0x10u},
+ {0xC0u, 0xAFu},
+ {0xC2u, 0xEFu},
+ {0xC4u, 0x5Bu},
+ {0xCAu, 0x71u},
+ {0xCCu, 0xBEu},
+ {0xCEu, 0xFEu},
+ {0xD6u, 0x0Fu},
+ {0xD8u, 0x0Fu},
+ {0xE2u, 0x04u},
+ {0xEAu, 0x02u},
+ {0xEEu, 0x08u},
+ {0x02u, 0x07u},
+ {0x04u, 0x04u},
+ {0x06u, 0x08u},
+ {0x09u, 0x01u},
+ {0x0Bu, 0x12u},
+ {0x0Du, 0x08u},
+ {0x0Fu, 0x84u},
+ {0x10u, 0x0Au},
+ {0x12u, 0x05u},
+ {0x14u, 0x09u},
+ {0x16u, 0x02u},
+ {0x1Du, 0x53u},
+ {0x1Fu, 0xACu},
+ {0x21u, 0x02u},
+ {0x22u, 0x08u},
+ {0x23u, 0x41u},
+ {0x2Du, 0x04u},
+ {0x2Fu, 0x28u},
+ {0x30u, 0x0Fu},
+ {0x31u, 0xC0u},
+ {0x33u, 0x30u},
+ {0x37u, 0x0Fu},
+ {0x3Fu, 0x45u},
+ {0x54u, 0x40u},
+ {0x56u, 0x04u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
{0x5Bu, 0x04u},
+ {0x5Cu, 0x01u},
{0x5Fu, 0x01u},
- {0x80u, 0x01u},
- {0x85u, 0x05u},
- {0x86u, 0x40u},
- {0x87u, 0x0Au},
- {0x88u, 0x01u},
- {0x89u, 0x50u},
- {0x8Bu, 0xA0u},
- {0x8Cu, 0x01u},
- {0x8Du, 0x0Fu},
- {0x8Fu, 0xF0u},
- {0x90u, 0x08u},
- {0x92u, 0x61u},
- {0x93u, 0xFFu},
- {0x94u, 0x10u},
- {0x97u, 0xFFu},
- {0x98u, 0xA2u},
- {0x99u, 0x30u},
+ {0x81u, 0xFFu},
+ {0x82u, 0x10u},
+ {0x85u, 0x30u},
+ {0x86u, 0x01u},
+ {0x87u, 0xC0u},
+ {0x8Cu, 0x80u},
+ {0x8Du, 0x90u},
+ {0x8Eu, 0x05u},
+ {0x8Fu, 0x60u},
+ {0x91u, 0x05u},
+ {0x93u, 0x0Au},
+ {0x94u, 0x06u},
+ {0x95u, 0x50u},
+ {0x96u, 0x80u},
+ {0x97u, 0xA0u},
+ {0x99u, 0x03u},
{0x9Au, 0x08u},
- {0x9Bu, 0xC0u},
- {0x9Cu, 0x04u},
- {0xA0u, 0x01u},
- {0xA1u, 0x90u},
- {0xA3u, 0x60u},
- {0xA4u, 0x07u},
- {0xA6u, 0xD8u},
- {0xA7u, 0xFFu},
- {0xA8u, 0x01u},
- {0xA9u, 0x09u},
- {0xABu, 0x06u},
- {0xADu, 0x03u},
- {0xAFu, 0x0Cu},
- {0xB1u, 0xFFu},
- {0xB2u, 0xE0u},
- {0xB6u, 0x3Fu},
- {0xB8u, 0x80u},
- {0xBEu, 0x40u},
- {0xBFu, 0x01u},
+ {0x9Bu, 0x0Cu},
+ {0x9Du, 0x0Fu},
+ {0x9Eu, 0x20u},
+ {0x9Fu, 0xF0u},
+ {0xA5u, 0x09u},
+ {0xA6u, 0x40u},
+ {0xA7u, 0x06u},
+ {0xA9u, 0xFFu},
+ {0xAAu, 0x83u},
+ {0xACu, 0x28u},
+ {0xAEu, 0x50u},
+ {0xAFu, 0xFFu},
+ {0xB0u, 0x80u},
+ {0xB2u, 0x07u},
+ {0xB4u, 0x60u},
+ {0xB6u, 0x18u},
+ {0xB7u, 0xFFu},
+ {0xBEu, 0x51u},
+ {0xBFu, 0x40u},
+ {0xD4u, 0x09u},
+ {0xD6u, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
+ {0xDBu, 0x04u},
{0xDFu, 0x01u},
{0x01u, 0x02u},
- {0x03u, 0x02u},
- {0x05u, 0x14u},
- {0x06u, 0x02u},
- {0x07u, 0x40u},
- {0x0Au, 0xCAu},
- {0x0Du, 0x82u},
- {0x0Eu, 0x08u},
- {0x0Fu, 0x20u},
- {0x13u, 0x42u},
- {0x17u, 0x19u},
- {0x18u, 0x04u},
- {0x19u, 0x01u},
- {0x1Au, 0x10u},
+ {0x03u, 0x10u},
+ {0x04u, 0x42u},
+ {0x05u, 0x04u},
+ {0x09u, 0x08u},
+ {0x0Bu, 0x80u},
+ {0x0Eu, 0x06u},
+ {0x0Fu, 0x10u},
+ {0x10u, 0x80u},
+ {0x15u, 0xA0u},
+ {0x16u, 0x20u},
+ {0x17u, 0x44u},
+ {0x19u, 0x02u},
+ {0x1Cu, 0x01u},
{0x1Du, 0x04u},
- {0x1Fu, 0x80u},
- {0x20u, 0x20u},
- {0x26u, 0x02u},
- {0x28u, 0x41u},
- {0x29u, 0x20u},
- {0x2Au, 0x08u},
- {0x2Cu, 0x41u},
- {0x2Du, 0x20u},
- {0x2Fu, 0x64u},
- {0x31u, 0x01u},
- {0x32u, 0x48u},
- {0x33u, 0x20u},
- {0x35u, 0x01u},
- {0x36u, 0x08u},
- {0x37u, 0x20u},
- {0x39u, 0x18u},
- {0x3Du, 0x10u},
- {0x3Eu, 0x48u},
- {0x3Fu, 0x04u},
- {0x48u, 0x01u},
- {0x49u, 0x40u},
- {0x4Bu, 0x80u},
- {0x68u, 0x01u},
- {0x69u, 0x19u},
- {0x6Au, 0x02u},
- {0x6Bu, 0x20u},
- {0x71u, 0x28u},
- {0x72u, 0x80u},
- {0x73u, 0x42u},
- {0x81u, 0x04u},
- {0x82u, 0x10u},
- {0x8Cu, 0x04u},
- {0x92u, 0x88u},
- {0x93u, 0x0Cu},
- {0x94u, 0x0Cu},
- {0x95u, 0x19u},
- {0x98u, 0x01u},
- {0x99u, 0x12u},
- {0x9Au, 0x02u},
- {0x9Bu, 0x59u},
- {0x9Du, 0x41u},
- {0x9Eu, 0x80u},
- {0xA1u, 0x82u},
- {0xA2u, 0x0Cu},
- {0xA3u, 0x32u},
- {0xA4u, 0x10u},
- {0xA5u, 0x28u},
+ {0x1Eu, 0x48u},
+ {0x20u, 0x82u},
+ {0x22u, 0x04u},
+ {0x27u, 0x01u},
+ {0x29u, 0x42u},
+ {0x2Eu, 0x94u},
+ {0x33u, 0x40u},
+ {0x36u, 0x11u},
+ {0x37u, 0x44u},
+ {0x38u, 0x80u},
+ {0x3Bu, 0x20u},
+ {0x3Cu, 0x02u},
+ {0x3Du, 0x88u},
+ {0x44u, 0x02u},
+ {0x46u, 0x01u},
+ {0x5Du, 0x20u},
+ {0x5Eu, 0x41u},
+ {0x5Fu, 0x04u},
+ {0x60u, 0x02u},
+ {0x62u, 0x12u},
+ {0x63u, 0x20u},
+ {0x65u, 0x01u},
+ {0x67u, 0x02u},
+ {0x6Cu, 0x41u},
+ {0x6Du, 0x88u},
+ {0x6Fu, 0x06u},
+ {0x74u, 0x08u},
+ {0x75u, 0x40u},
+ {0x77u, 0x88u},
+ {0x80u, 0x01u},
+ {0x81u, 0x05u},
+ {0x82u, 0x04u},
+ {0x86u, 0x04u},
+ {0x87u, 0x80u},
+ {0x88u, 0x08u},
+ {0x90u, 0x40u},
+ {0x91u, 0xA0u},
+ {0x92u, 0x15u},
+ {0x93u, 0xB6u},
+ {0x94u, 0x02u},
+ {0x99u, 0x20u},
+ {0x9Au, 0x91u},
+ {0x9Bu, 0x10u},
+ {0x9Eu, 0x20u},
+ {0x9Fu, 0x49u},
+ {0xA0u, 0x80u},
+ {0xA1u, 0x08u},
+ {0xA2u, 0x11u},
+ {0xA3u, 0x10u},
+ {0xA4u, 0x41u},
+ {0xA5u, 0x04u},
{0xA6u, 0x02u},
- {0xA7u, 0x80u},
- {0xAEu, 0x01u},
- {0xB5u, 0x80u},
- {0xC0u, 0xF9u},
- {0xC2u, 0xFBu},
- {0xC4u, 0x79u},
- {0xCAu, 0xFFu},
- {0xCCu, 0xEFu},
- {0xCEu, 0x76u},
+ {0xA7u, 0x02u},
+ {0xAAu, 0x11u},
+ {0xACu, 0x04u},
+ {0xB0u, 0x41u},
+ {0xB2u, 0x20u},
+ {0xB4u, 0x01u},
+ {0xB7u, 0x08u},
+ {0xC0u, 0xBCu},
+ {0xC2u, 0xECu},
+ {0xC4u, 0xE8u},
+ {0xCAu, 0x79u},
+ {0xCCu, 0xF8u},
+ {0xCEu, 0xDCu},
+ {0xD6u, 0xF0u},
+ {0xD8u, 0x9Fu},
{0xE0u, 0x01u},
- {0xECu, 0x40u},
- {0x0Eu, 0x08u},
+ {0xE4u, 0x0Cu},
+ {0xE6u, 0x20u},
+ {0xEAu, 0xC8u},
+ {0xEEu, 0xC0u},
+ {0x0Fu, 0x08u},
{0x12u, 0x08u},
{0x15u, 0x80u},
{0x17u, 0x04u},
{0x33u, 0x04u},
{0x36u, 0x88u},
- {0x39u, 0x80u},
- {0x3Bu, 0x01u},
- {0x3Eu, 0x88u},
- {0x41u, 0x80u},
- {0x60u, 0x20u},
- {0x83u, 0x01u},
- {0x8Bu, 0x20u},
- {0x8Eu, 0x04u},
+ {0x39u, 0x81u},
+ {0x3Cu, 0x01u},
+ {0x3Du, 0x20u},
+ {0x40u, 0x04u},
+ {0x62u, 0x02u},
+ {0x83u, 0x04u},
+ {0x86u, 0x08u},
+ {0x8Au, 0x02u},
{0xC2u, 0x80u},
{0xC4u, 0xE0u},
{0xCCu, 0xE0u},
{0xCEu, 0xF0u},
{0xD0u, 0x10u},
{0xD8u, 0x40u},
- {0xE2u, 0x80u},
- {0x32u, 0x04u},
- {0x33u, 0x80u},
+ {0xE4u, 0x20u},
+ {0xE6u, 0x40u},
+ {0x33u, 0x81u},
{0x35u, 0x80u},
- {0x39u, 0x40u},
- {0x53u, 0x20u},
- {0x59u, 0x10u},
- {0x5Cu, 0x02u},
- {0x81u, 0x10u},
- {0x8Fu, 0x02u},
- {0x9Cu, 0x20u},
- {0x9Eu, 0x08u},
- {0xA3u, 0x20u},
- {0xA5u, 0x80u},
+ {0x3Au, 0x10u},
+ {0x50u, 0x08u},
+ {0x56u, 0x08u},
+ {0x63u, 0x20u},
+ {0x85u, 0x01u},
+ {0x88u, 0x08u},
+ {0x8Du, 0x10u},
+ {0x8Fu, 0x10u},
+ {0x94u, 0x05u},
+ {0x95u, 0x01u},
+ {0x9Au, 0x08u},
+ {0xA5u, 0x10u},
{0xA6u, 0x80u},
- {0xB6u, 0x80u},
{0xCCu, 0x70u},
{0xCEu, 0x10u},
- {0xD4u, 0xA0u},
- {0xD6u, 0x80u},
- {0xE6u, 0x20u},
+ {0xD4u, 0x60u},
+ {0xD8u, 0x40u},
+ {0xE2u, 0x10u},
{0x12u, 0x80u},
- {0x5Bu, 0x02u},
- {0x82u, 0x08u},
+ {0x5Bu, 0x08u},
{0x85u, 0x80u},
- {0x8Cu, 0x02u},
- {0x96u, 0x08u},
- {0x9Bu, 0x02u},
- {0x9Cu, 0x22u},
+ {0x8Au, 0x10u},
+ {0x8Cu, 0x01u},
+ {0x94u, 0x05u},
{0x9Du, 0x80u},
- {0x9Eu, 0x08u},
- {0xA5u, 0x80u},
+ {0x9Eu, 0x10u},
+ {0x9Fu, 0x01u},
+ {0xA2u, 0x10u},
{0xA6u, 0x80u},
{0xA7u, 0x80u},
- {0xA9u, 0x40u},
+ {0xAEu, 0x10u},
{0xC4u, 0x10u},
{0xD6u, 0x40u},
{0xE2u, 0x10u},
- {0xE6u, 0x80u},
- {0xEEu, 0x20u},
- {0xA5u, 0x80u},
- {0xA7u, 0x80u},
- {0xAEu, 0x04u},
- {0xB4u, 0x20u},
{0xEEu, 0x10u},
- {0x00u, 0x20u},
- {0x09u, 0x40u},
- {0x0Fu, 0x08u},
- {0x12u, 0x80u},
- {0x17u, 0x08u},
- {0x5Bu, 0x02u},
- {0x66u, 0x40u},
- {0x8Bu, 0x40u},
+ {0x8Au, 0x20u},
+ {0x94u, 0x04u},
+ {0x9Fu, 0x01u},
+ {0xA2u, 0x10u},
+ {0xA7u, 0x80u},
+ {0xB3u, 0x08u},
+ {0x01u, 0x20u},
+ {0x08u, 0x20u},
+ {0x0Eu, 0x01u},
+ {0x13u, 0x02u},
+ {0x14u, 0x80u},
+ {0x58u, 0x01u},
+ {0x60u, 0x10u},
+ {0x8Au, 0x01u},
+ {0x8Cu, 0x20u},
+ {0x8Du, 0x20u},
{0xC0u, 0x02u},
{0xC2u, 0x03u},
{0xC4u, 0x0Cu},
- {0xD6u, 0x03u},
+ {0xD6u, 0x02u},
+ {0xD8u, 0x02u},
+ {0xE2u, 0x0Au},
{0xE6u, 0x01u},
- {0x0Bu, 0x80u},
- {0x0Du, 0x08u},
- {0x53u, 0x02u},
- {0x57u, 0x40u},
- {0x61u, 0x40u},
- {0x62u, 0x04u},
- {0x81u, 0x10u},
- {0x8Fu, 0x02u},
- {0x97u, 0x80u},
- {0x9Eu, 0x40u},
- {0x9Fu, 0x02u},
- {0xA1u, 0x40u},
- {0xA2u, 0x80u},
- {0xA3u, 0x04u},
- {0xABu, 0x08u},
- {0xACu, 0x10u},
+ {0x04u, 0x04u},
+ {0x0Au, 0x20u},
+ {0x0Du, 0x01u},
+ {0x52u, 0x02u},
+ {0x56u, 0x80u},
+ {0x63u, 0x02u},
+ {0x65u, 0x40u},
+ {0x82u, 0x98u},
+ {0x8Bu, 0x01u},
+ {0x9Bu, 0x02u},
+ {0x9Cu, 0x01u},
+ {0xA8u, 0x80u},
+ {0xB4u, 0x10u},
+ {0xC0u, 0x04u},
{0xC2u, 0x0Cu},
{0xD4u, 0x03u},
- {0xD6u, 0x02u},
- {0xD8u, 0x02u},
- {0xE4u, 0x02u},
- {0x57u, 0x08u},
+ {0xD6u, 0x03u},
+ {0xE0u, 0x01u},
+ {0xE8u, 0x08u},
+ {0x54u, 0x10u},
{0x87u, 0x10u},
- {0x89u, 0x40u},
+ {0x8Au, 0x04u},
+ {0x90u, 0x04u},
+ {0x9Cu, 0x01u},
{0x9Du, 0x40u},
- {0x9Eu, 0x44u},
- {0x9Fu, 0x02u},
- {0xA1u, 0x50u},
- {0xA2u, 0x80u},
- {0xA6u, 0x04u},
- {0xA7u, 0x40u},
- {0xA9u, 0x08u},
- {0xAAu, 0x04u},
- {0xB7u, 0x04u},
+ {0x9Eu, 0x08u},
+ {0xA0u, 0x10u},
+ {0xAAu, 0x02u},
+ {0xB0u, 0x10u},
+ {0xB1u, 0x01u},
+ {0xB7u, 0x02u},
{0xD4u, 0x02u},
- {0xE0u, 0x01u},
- {0xEAu, 0x02u},
+ {0xE6u, 0x04u},
+ {0xEAu, 0x0Cu},
+ {0xECu, 0x01u},
{0x08u, 0x08u},
- {0x0Bu, 0x08u},
- {0x0Eu, 0x08u},
+ {0x0Bu, 0x04u},
+ {0x0Eu, 0x04u},
{0x0Fu, 0x10u},
- {0x82u, 0x02u},
- {0x87u, 0x02u},
- {0x89u, 0x10u},
- {0x8Au, 0x40u},
- {0x97u, 0x18u},
- {0x9Eu, 0x44u},
- {0x9Fu, 0x02u},
- {0xA1u, 0x10u},
- {0xA2u, 0x80u},
- {0xA6u, 0x04u},
- {0xA7u, 0x40u},
- {0xAFu, 0x04u},
- {0xB1u, 0x40u},
- {0xB7u, 0x08u},
+ {0x90u, 0x04u},
+ {0x96u, 0x04u},
+ {0x97u, 0x10u},
+ {0x9Cu, 0x01u},
+ {0x9Du, 0x40u},
+ {0x9Eu, 0x08u},
{0xC2u, 0x0Fu},
- {0xE2u, 0x01u},
- {0xE4u, 0x01u},
- {0xE8u, 0x08u},
- {0xEEu, 0x04u},
- {0x89u, 0x80u},
- {0xA5u, 0x80u},
- {0xAFu, 0x80u},
+ {0x94u, 0x04u},
+ {0x9Eu, 0x20u},
+ {0xA2u, 0x10u},
+ {0xAFu, 0x81u},
+ {0xEAu, 0x40u},
{0xEEu, 0x10u},
{0x06u, 0x20u},
- {0x57u, 0x08u},
- {0x5Fu, 0x40u},
- {0x83u, 0x08u},
- {0x93u, 0x40u},
+ {0x5Bu, 0x40u},
+ {0x5Eu, 0x20u},
+ {0x80u, 0x04u},
+ {0x83u, 0x40u},
+ {0x94u, 0x04u},
{0x9Eu, 0x20u},
- {0xAFu, 0x40u},
- {0xB6u, 0x20u},
+ {0xA2u, 0x10u},
{0xC0u, 0x20u},
- {0xD4u, 0x40u},
+ {0xD4u, 0x80u},
{0xD6u, 0x20u},
+ {0xE2u, 0x20u},
{0xE6u, 0x80u},
- {0xEEu, 0x40u},
- {0x8Fu, 0x40u},
- {0x95u, 0x10u},
- {0x9Au, 0x02u},
- {0x9Eu, 0x04u},
- {0xA1u, 0x10u},
- {0xA7u, 0x40u},
- {0xAAu, 0x80u},
+ {0x80u, 0x04u},
+ {0x90u, 0x04u},
+ {0x9Cu, 0x01u},
+ {0x9Du, 0x40u},
+ {0x9Eu, 0x08u},
{0xACu, 0x08u},
- {0xE4u, 0x02u},
- {0x01u, 0x10u},
- {0x04u, 0x10u},
- {0x55u, 0x10u},
- {0x56u, 0x02u},
- {0x82u, 0x04u},
- {0x8Cu, 0x10u},
- {0x95u, 0x10u},
- {0x9Au, 0x02u},
- {0x9Eu, 0x04u},
- {0xA1u, 0x10u},
+ {0xAFu, 0x04u},
+ {0x00u, 0x20u},
+ {0x06u, 0x08u},
+ {0x53u, 0x80u},
+ {0x56u, 0x80u},
+ {0x82u, 0x80u},
+ {0x83u, 0x80u},
+ {0x85u, 0x40u},
+ {0x9Du, 0x40u},
+ {0x9Eu, 0x08u},
+ {0xA4u, 0x10u},
+ {0xACu, 0x10u},
+ {0xB0u, 0x01u},
{0xC0u, 0x03u},
- {0xD4u, 0x02u},
- {0xD6u, 0x04u},
- {0xE2u, 0x08u},
- {0x00u, 0x01u},
- {0x01u, 0x01u},
- {0x0Cu, 0x01u},
- {0x0Du, 0x01u},
- {0x0Fu, 0x01u},
- {0x10u, 0x01u},
- {0x1Cu, 0x01u},
+ {0xD4u, 0x06u},
+ {0xECu, 0x04u},
+ {0x10u, 0x03u},
+ {0x11u, 0x01u},
+ {0x1Cu, 0x03u},
+ {0x1Du, 0x01u},
{0x00u, 0xFDu},
{0x01u, 0xABu},
{0x02u, 0x08u},
uint16 size;
} CYPACKED_ATTR cfg_memset_t;
+
+ CYPACKED typedef struct {
+ void CYFAR *dest;
+ const void CYCODE *src;
+ uint16 size;
+ } CYPACKED_ATTR cfg_memcpy_t;
+
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},
{(void CYFAR *)(CYREG_PRT1_DR), 16u},
- {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},
+ {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 2176u},
+ {(void CYFAR *)(CYDEV_UCFG_B0_P4_ROUTE_BASE), 1792u},
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
- {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},
+ {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},
+ };
+
+ /* UDB_0_2_0_CONFIG Address: CYDEV_UCFG_B0_P4_U1_BASE Size (bytes): 128 */
+ static const uint8 CYCODE BS_UDB_0_2_0_CONFIG_VAL[] = {
+ 0x01u, 0x74u, 0x00u, 0x00u, 0x00u, 0x54u, 0x00u, 0x20u, 0x01u, 0x40u, 0x00u, 0x34u, 0x10u, 0x34u, 0x00u, 0x40u,
+ 0x08u, 0x94u, 0x21u, 0x40u, 0x07u, 0xC0u, 0x18u, 0x3Du, 0x22u, 0x47u, 0x08u, 0x88u, 0x01u, 0x83u, 0x00u, 0x78u,
+ 0x01u, 0x00u, 0x00u, 0x00u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x00u, 0x02u, 0x01u, 0x74u, 0x00u, 0x00u,
+ 0x3Fu, 0xC0u, 0x00u, 0x07u, 0x00u, 0x39u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x0Eu, 0x00u, 0x00u, 0x01u, 0x00u,
+ 0x46u, 0x02u, 0x50u, 0x00u, 0x03u, 0xBEu, 0xF0u, 0xDCu, 0x3Bu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x28u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u,
+ 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
+
+ /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */
+ static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x02u, 0x00u, 0x03u, 0x00u, 0x03u, 0x01u};
+
+ static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
+ /* dest, src, size */
+ {(void CYFAR *)(CYDEV_UCFG_B0_P4_U1_BASE), BS_UDB_0_2_0_CONFIG_VAL, 128u},
+ {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},
};
uint8 CYDATA i;
CYMEMZERO(ms->address, (uint32)(ms->size));
}
+ /* Copy device configuration data into registers */
+ for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++)
+ {
+ const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i];
+ void * CYDATA destPtr = mc->dest;
+ const void CYCODE * CYDATA srcPtr = mc->src;
+ uint16 CYDATA numBytes = mc->size;
+ CYCONFIGCPYCODE(destPtr, srcPtr, numBytes);
+ }
+
cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table);
/* Perform normal device configuration. Order is not critical for these items. */
.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
+/* SCSI_Parity_Error */
+.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
+.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST
+.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK
+.set SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB02_ST_CTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB02_ST_CTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST
+
/* USBFS_bus_reset */
.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
/* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
/* SCSI_Out_Bits */
.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB10_11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB10_11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB10_11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB10_11_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB10_11_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB10_11_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB10_11_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB10_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB10_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB10_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB10_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB11_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB11_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB10_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB11_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
/* USBFS_arb_int */
.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SDCard_BSPIM */
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB08_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB08_ST
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB08_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB08_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB08_MSK
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB09_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB09_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB09_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB09_ST
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB09_10_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB09_10_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB09_10_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB09_10_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB09_10_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB09_10_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB09_10_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB09_10_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB09_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB09_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB09_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB09_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB09_MSK
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB10_11_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB11_MSK
-.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL
-.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB11_ST
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB10_MSK
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB10_ST
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
.set SDCard_BSPIM_TxStsReg__0__POS, 0
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB08_MSK
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB08_ST
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB08_09_A0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB08_09_A1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB08_09_D0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB08_09_D1
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB08_09_F0
-.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB08_09_F1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB08_A0_A1
-.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB08_A0
-.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB08_A1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB08_D0_D1
-.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB08_D0
-.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB08_D1
-.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB08_F0_F1
-.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB08_F0
-.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB08_F1
-.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
-.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB11_MSK
+.set SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
+.set SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB11_MSK_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB11_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_CNT_REG, CYREG_B1_UDB11_ST_CTL
+.set SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB11_ST_CTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB11_ST
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB09_10_A0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB09_10_A1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB09_10_D0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB09_10_D1
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB09_10_F0
+.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB09_10_F1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB09_A0_A1
+.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB09_A0
+.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB09_A1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB09_D0_D1
+.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB09_D0
+.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB09_D1
+.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB09_F0_F1
+.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB09_F0
+.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB09_F1
+.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
/* USBFS_dp_int */
.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SD_Data_Clk__PM_STBY_MSK, 0x01
/* timer_clock */
-.set timer_clock__CFG0, CYREG_CLKDIST_DCFG1_CFG0
-.set timer_clock__CFG1, CYREG_CLKDIST_DCFG1_CFG1
-.set timer_clock__CFG2, CYREG_CLKDIST_DCFG1_CFG2
+.set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0
+.set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1
+.set timer_clock__CFG2, CYREG_CLKDIST_DCFG2_CFG2
.set timer_clock__CFG2_SRC_SEL_MASK, 0x07
-.set timer_clock__INDEX, 0x01
+.set timer_clock__INDEX, 0x02
.set timer_clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2
-.set timer_clock__PM_ACT_MSK, 0x02
+.set timer_clock__PM_ACT_MSK, 0x04
.set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2
-.set timer_clock__PM_STBY_MSK, 0x02
+.set timer_clock__PM_STBY_MSK, 0x04
/* scsiTarget */
.set scsiTarget_StatusReg__0__MASK, 0x01
.set scsiTarget_StatusReg__0__POS, 0
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB13_14_ST
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
.set scsiTarget_StatusReg__1__MASK, 0x02
.set scsiTarget_StatusReg__1__POS, 1
.set scsiTarget_StatusReg__2__MASK, 0x04
.set scsiTarget_StatusReg__4__MASK, 0x10
.set scsiTarget_StatusReg__4__POS, 4
.set scsiTarget_StatusReg__MASK, 0x1F
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB13_MSK
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB13_ST
-.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
-.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB14_15_ST
-.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB14_MSK
-.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
-.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
-.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
-.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB14_ST_CTL
-.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB14_ST_CTL
-.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB14_ST
-.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
-.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL
-.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL
-.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL
-.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL
-.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK
-.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK
-.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK
-.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK
-.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
-.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB14_CTL
-.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL
-.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB14_CTL
-.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL
-.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
-.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB14_MSK
-.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
-.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB14_15_A0
-.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB14_15_A1
-.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB14_15_D0
-.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB14_15_D1
-.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
-.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB14_15_F0
-.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB14_15_F1
-.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB14_A0_A1
-.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB14_A0
-.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB14_A1
-.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB14_D0_D1
-.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB14_D0
-.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB14_D1
-.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
-.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB14_F0_F1
-.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB14_F0
-.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB14_F1
-.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
-.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB04_MSK
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB04_ST
+.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
+.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB11_MSK
+.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB11_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB11_ST_CTL
+.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB11_ST
+.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
+.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
+.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
+.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB11_CTL
+.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB11_CTL
+.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB11_MSK
+.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB11_12_A0
+.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB11_12_A1
+.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB11_12_D0
+.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB11_12_D1
+.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB11_12_F0
+.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB11_12_F1
+.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB11_A0_A1
+.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB11_A0
+.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB11_A1
+.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB11_D0_D1
+.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB11_D0
+.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB11_D1
+.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB11_F0_F1
+.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB11_F0
+.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB11_F1
+.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
+.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
/* USBFS_ep_0 */
.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SCSI_ATN__SHIFT, 0
.set SCSI_ATN__SLW, CYREG_PRT2_SLW
+/* SCSI_CLK */
+.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0
+.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1
+.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2
+.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07
+.set SCSI_CLK__INDEX, 0x01
+.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2
+.set SCSI_CLK__PM_ACT_MSK, 0x02
+.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2
+.set SCSI_CLK__PM_STBY_MSK, 0x02
+
/* SCSI_Out */
.set SCSI_Out__0__AG, CYREG_PRT15_AG
.set SCSI_Out__0__AMUX, CYREG_PRT15_AMUX
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+/* SCSI_Parity_Error */
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
+SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
+
/* USBFS_bus_reset */
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
/* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
/* SCSI_Out_Bits */
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB10_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB10_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB10_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
/* USBFS_arb_int */
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
/* SDCard_BSPIM */
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB08_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB08_ST
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB08_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB08_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB08_MSK
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB09_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB09_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB09_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB09_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB09_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB09_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB09_MSK
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB11_MSK
-SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
-SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB11_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB08_09_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB08_09_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB08_09_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB08_09_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB08_09_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB08_09_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB08_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB08_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB08_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB08_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB08_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB08_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB08_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB08_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB08_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
+SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
+SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB11_ST_CTL
+SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB11_ST_CTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB09_10_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB09_10_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB09_10_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB09_10_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB09_10_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB09_10_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB09_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB09_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB09_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB09_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB09_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB09_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB09_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB09_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB09_F1
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
/* USBFS_dp_int */
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_Data_Clk__PM_STBY_MSK EQU 0x01
/* timer_clock */
-timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
-timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
-timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
+timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
+timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
+timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
-timer_clock__INDEX EQU 0x01
+timer_clock__INDEX EQU 0x02
timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-timer_clock__PM_ACT_MSK EQU 0x02
+timer_clock__PM_ACT_MSK EQU 0x04
timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-timer_clock__PM_STBY_MSK EQU 0x02
+timer_clock__PM_STBY_MSK EQU 0x04
/* scsiTarget */
scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB13_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB13_ST
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB14_MSK
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB14_ST_CTL
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB14_ST_CTL
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB14_ST
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB14_CTL
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB14_CTL
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB14_MSK
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB14_15_A0
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB14_15_A1
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB14_15_D0
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB14_15_D1
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB14_15_F0
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB14_15_F1
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB14_A0_A1
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB14_A0
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB14_A1
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB14_D0_D1
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB14_D0
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB14_D1
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB14_F0_F1
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB14_F0
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB14_F1
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
/* USBFS_ep_0 */
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_ATN__SHIFT EQU 0
SCSI_ATN__SLW EQU CYREG_PRT2_SLW
+/* SCSI_CLK */
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
+SCSI_CLK__INDEX EQU 0x01
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SCSI_CLK__PM_ACT_MSK EQU 0x02
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SCSI_CLK__PM_STBY_MSK EQU 0x02
+
/* SCSI_Out */
SCSI_Out__0__AG EQU CYREG_PRT15_AG
SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX
SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
+; SCSI_Parity_Error
+SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
+SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
+SCSI_Parity_Error_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_Parity_Error_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
+
; USBFS_bus_reset
USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
; SCSI_Out_Bits
SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB10_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB10_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB11_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB11_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB10_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
; USBFS_arb_int
USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SDCard_BSPIM
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB08_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB08_ST
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB08_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB08_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB08_MSK
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB09_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB09_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB09_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB09_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB09_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB09_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB09_MSK
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB10_11_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB11_MSK
-SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
-SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB11_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB10_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB10_ST
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB08_09_A0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB08_09_A1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB08_09_D0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB08_09_D1
-SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB08_09_F0
-SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB08_09_F1
-SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB08_A0_A1
-SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB08_A0
-SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB08_A1
-SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB08_D0_D1
-SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB08_D0
-SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB08_D1
-SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
-SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB08_F0_F1
-SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB08_F0
-SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB08_F1
-SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
-SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB11_MSK
+SDCard_BSPIM_TxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
+SDCard_BSPIM_TxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB11_MSK_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB11_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB11_ST_CTL
+SDCard_BSPIM_TxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB11_ST_CTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB11_ST
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB09_10_A0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB09_10_A1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB09_10_D0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB09_10_D1
+SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB09_10_F0
+SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB09_10_F1
+SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB09_A0_A1
+SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB09_A0
+SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB09_A1
+SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB09_D0_D1
+SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB09_D0
+SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB09_D1
+SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
+SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB09_F0_F1
+SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB09_F0
+SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB09_F1
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
; USBFS_dp_int
USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SD_Data_Clk__PM_STBY_MSK EQU 0x01
; timer_clock
-timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
-timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
-timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
+timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0
+timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1
+timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2
timer_clock__CFG2_SRC_SEL_MASK EQU 0x07
-timer_clock__INDEX EQU 0x01
+timer_clock__INDEX EQU 0x02
timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
-timer_clock__PM_ACT_MSK EQU 0x02
+timer_clock__PM_ACT_MSK EQU 0x04
timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
-timer_clock__PM_STBY_MSK EQU 0x02
+timer_clock__PM_STBY_MSK EQU 0x04
; scsiTarget
scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB13_14_ST
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB13_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB13_ST
-scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
-scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST
-scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB14_MSK
-scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
-scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB14_ST_CTL
-scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB14_ST_CTL
-scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB14_ST
-scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
-scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
-scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
-scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
-scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
-scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
-scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
-scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
-scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB14_CTL
-scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
-scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB14_CTL
-scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
-scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB14_MSK
-scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB14_15_A0
-scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB14_15_A1
-scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB14_15_D0
-scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB14_15_D1
-scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
-scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB14_15_F0
-scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB14_15_F1
-scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB14_A0_A1
-scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB14_A0
-scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB14_A1
-scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB14_D0_D1
-scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB14_D0
-scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB14_D1
-scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
-scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB14_F0_F1
-scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB14_F0
-scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB14_F1
-scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
-scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST
+scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB11_ST
+scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
+scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB11_CTL
+scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB11_CTL
+scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB11_12_A0
+scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB11_12_A1
+scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB11_12_D0
+scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB11_12_D1
+scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB11_12_F0
+scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB11_12_F1
+scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB11_A0_A1
+scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB11_A0
+scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB11_A1
+scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB11_D0_D1
+scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB11_D0
+scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB11_D1
+scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB11_F0_F1
+scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB11_F0
+scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB11_F1
+scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
+scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
; USBFS_ep_0
USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_ATN__SHIFT EQU 0
SCSI_ATN__SLW EQU CYREG_PRT2_SLW
+; SCSI_CLK
+SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0
+SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1
+SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2
+SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07
+SCSI_CLK__INDEX EQU 0x01
+SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2
+SCSI_CLK__PM_ACT_MSK EQU 0x02
+SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2
+SCSI_CLK__PM_STBY_MSK EQU 0x02
+
; SCSI_Out
SCSI_Out__0__AG EQU CYREG_PRT15_AG
SCSI_Out__0__AMUX EQU CYREG_PRT15_AMUX
const uint8 cy_meta_loadable[] = {
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
- 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x52u, 0x03u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x60u, 0x03u,
0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
#include <SD_SCK.h>
#include <SD_MOSI_aliases.h>
#include <SD_MOSI.h>
+#include <SCSI_CLK.h>
#include <SCSI_RST_aliases.h>
#include <SCSI_RST.h>
#include <SCSI_ATN_aliases.h>
#include <Debug_Timer_Interrupt.h>
#include <EXTLED_aliases.h>
#include <EXTLED.h>
+#include <SCSI_Parity_Error.h>
#include <USBFS_Dm_aliases.h>
#include <USBFS_Dm.h>
#include <USBFS_Dp_aliases.h>
<Tool Name="postbuild" Command="" Options="" />
</Toolchain>
</Toolchains>
- <Project Name="SCSI2SD" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" Version="4.0" Type="Bootloadable">
+ <Project Name="SCSI2SD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" Version="4.0" Type="Bootloadable">
<CMSIS_SVD_File>SCSI2SD.svd</CMSIS_SVD_File>
<Datasheet />
<LinkerFiles>
<LinkerFile Toolchain="IAR EWARM">.\Generated_Source\PSoC5\Cm3Iar.icf</LinkerFile>
</LinkerFiles>
<Folders>
- <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\src">
- <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+ <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\src">
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="">..\..\src\main.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\diagnostic.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\disk.c</File>
<File BuildType="BUILD" Toolchain="">..\..\src\config.h</File>
</Files>
</Folder>
- <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
- <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+ <Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="">.\device.h</File>
</Files>
</Folder>
- <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5">
- <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+ <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5">
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cybootloader.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\EXTLED_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\EXTLED.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\EXTLED.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Parity_Error.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Parity_Error.h</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_CLK.c</File>
+ <File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_CLK.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\prebuild.bat</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\postbuild.bat</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\CyElfTool.exe</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\libelf.dll</File>
</Files>
</Folder>
- <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_GCC">
- <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+ <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_GCC">
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="ARM GCC">.\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a</File>
</Files>
</Folder>
- <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK">
- <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+ <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\ARM_Keil_MDK">
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a</File>
</Files>
</Folder>
- <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\IAR">
- <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
+ <Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn\Generated_Source\PSoC5\IAR">
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="IAR">.\Generated_Source\PSoC5\IAR\CyComponentLibrary.a</File>
</Files>
</Folder>
<Folder BuildType="EXCLUDE" Path=".\codegentemp">
- <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder>
<Folder BuildType="EXCLUDE" Path=".\ARM_GCC_441">
- <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder>
<Folder BuildType="EXCLUDE" Path=".\ARM_GCC_473">
- <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder>
<Folder BuildType="EXCLUDE" Path=".\DP8051_Keil_951">
- <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder>
<Folder BuildType="EXCLUDE" Path=".\DP8051">
- <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder>
<Folder BuildType="EXCLUDE" Path=".\CortexM0">
- <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder>
<Folder BuildType="EXCLUDE" Path=".\CortexM3">
- <Files Root="Z:\projects\SCSI2SD\git\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
+ <Files Root="Z:\projects\SCSI2SD\git-parity\SCSI2SD\software\SCSI2SD\v4\SCSI2SD.cydsn" />
</Folder>
</Folders>
</Project>
<?xml version="1.0" encoding="utf-8"?>
<blockRegMap version="1" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://cypress.com/xsd/cyblockregmap cyblockregmap.xsd" xmlns="http://cypress.com/xsd/cyblockregmap">
+ <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ </block>
+ <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true">
<block name="bus_reset" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ep_0" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<register name="USBFS_EP_TYPE" address="0x4000608F" bitWidth="8" desc="Endpoint Type (IN/OUT) Indication" />
<register name="USBFS_USB_CLK_EN" address="0x4000609D" bitWidth="8" desc="USB Block Clock Enable Register" />
</block>
- <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- </block>
- <block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true">
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006462" bitWidth="8" desc="" />
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x40006482" bitWidth="8" desc="" />
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006492" bitWidth="8" desc="">
+ <field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear">
+ <value name="ENABLED" value="1" desc="Enable counter" />
+ <value name="DISABLED" value="0" desc="Disable counter" />
+ </field>
+ <field name="INTRENBL" from="4" to="4" access="RW" resetVal="" desc="Enables or disables the Interrupt">
+ <value name="ENABLED" value="1" desc="Interrupt enabled" />
+ <value name="DISABLED" value="0" desc="Interrupt disabled" />
+ </field>
+ <field name="FIFO1LEVEL" from="3" to="3" access="RW" resetVal="" desc="FIFO level">
+ <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
+ <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
+ </field>
+ <field name="FIFO0LEVEL" from="2" to="2" access="RW" resetVal="" desc="FIFO level">
+ <value name="ENABLED" value="1" desc="FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full" />
+ <value name="DISABLED" value="0" desc="FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty" />
+ </field>
+ <field name="FIFO1CLEAR" from="1" to="1" access="RW" resetVal="" desc="FIFO clear">
+ <value name="ENABLED" value="1" desc="Clear FIFO state" />
+ <value name="DISABLED" value="0" desc="Normal FIFO operation" />
+ </field>
+ <field name="FIFO0CLEAR" from="0" to="0" access="RW" resetVal="" desc="FIFO clear">
+ <value name="ENABLED" value="1" desc="Clear FIFO state" />
+ <value name="DISABLED" value="0" desc="Normal FIFO operation" />
+ </field>
+ </register>
+ </block>
<block name="EXTLED" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000657B" bitWidth="8" desc="" />
+ </block>
+ <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true">
<block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" />
<register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" />
</block>
- <block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true">
<register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006579" bitWidth="8" desc="" />
</block>
- <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000657A" bitWidth="8" desc="" />
- </block>
+ <block name="scsiTarget" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_CD" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true">
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647B" bitWidth="8" desc="" />
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x40006472" bitWidth="8" desc="" />
</block>
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RST" BASE="0x0" SIZE="0x0" desc="" visible="true" />
- <block name="Clock_1" BASE="0x0" SIZE="0x0" desc="" visible="true" />
+ <block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_RST_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SCSI_ATN" BASE="0x0" SIZE="0x0" desc="" visible="true" />
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" />
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
<filters />
</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Parity_Error" persistent="">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
+<dependencies>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Parity_Error.c" persistent=".\Generated_Source\PSoC5\SCSI_Parity_Error.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_Parity_Error.h" persistent=".\Generated_Source\PSoC5\SCSI_Parity_Error.h">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
+<CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFolder" version="2">
+<CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtBaseContainer" version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CLK" persistent="">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<CyGuid_0820c2e7-528d-4137-9a08-97257b946089 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemList" version="2">
+<dependencies>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CLK.c" persistent=".\Generated_Source\PSoC5\SCSI_CLK.c">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="ARM_C_FILE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+<CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileGenerated" version="1">
+<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFile" version="3" xml_contents_version="1">
+<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItem" version="2" name="SCSI_CLK.h" persistent=".\Generated_Source\PSoC5\SCSI_CLK.h">
+<Hidden v="False" />
+</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
+<build_action v="NONE" />
+<PropertyDeltas />
+</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
+</CyGuid_405e30c3-81d4-4133-98d6-c3ecf21fec0d>
+</dependencies>
+</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
+</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
+<filters />
+</CyGuid_ebc4f06d-207f-49c2-a540-72acf4adabc0>
</dependencies>
</CyGuid_0820c2e7-528d-4137-9a08-97257b946089>
</CyGuid_2f73275c-45bf-46ba-b3b1-00a2fe0c8dd8>
</register>
</registers>
</peripheral>
+ <peripheral>
+ <name>SCSI_Parity_Error</name>
+ <description>No description available</description>
+ <baseAddress>0x40006462</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x31</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>SCSI_Parity_Error_STATUS_REG</name>
+ <description>No description available</description>
+ <addressOffset>0x0</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>SCSI_Parity_Error_MASK_REG</name>
+ <description>No description available</description>
+ <addressOffset>0x20</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ <register>
+ <name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
+ <description>No description available</description>
+ <addressOffset>0x30</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>FIFO0</name>
+ <description>FIFO0 clear</description>
+ <lsb>5</lsb>
+ <msb>5</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>Enable counter</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Disable counter</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>INTRENBL</name>
+ <description>Enables or disables the Interrupt</description>
+ <lsb>4</lsb>
+ <msb>4</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>Interrupt enabled</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Interrupt disabled</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>FIFO1LEVEL</name>
+ <description>FIFO level</description>
+ <lsb>3</lsb>
+ <msb>3</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>FIFO0LEVEL</name>
+ <description>FIFO level</description>
+ <lsb>2</lsb>
+ <msb>2</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>FIFO1CLEAR</name>
+ <description>FIFO clear</description>
+ <lsb>1</lsb>
+ <msb>1</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>Clear FIFO state</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Normal FIFO operation</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>FIFO0CLEAR</name>
+ <description>FIFO clear</description>
+ <lsb>0</lsb>
+ <msb>0</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>ENABLED</name>
+ <description>Clear FIFO state</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>DISABLED</name>
+ <description>Normal FIFO operation</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>SCSI_Out_Bits</name>
+ <description>No description available</description>
+ <baseAddress>0x4000657B</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x1</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>SCSI_Out_Bits_CONTROL_REG</name>
+ <description>No description available</description>
+ <addressOffset>0x0</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ </registers>
+ </peripheral>
<peripheral>
<name>Debug_Timer</name>
<description>No description available</description>
</register>
</registers>
</peripheral>
- <peripheral>
- <name>SCSI_Out_Bits</name>
- <description>No description available</description>
- <baseAddress>0x4000657A</baseAddress>
- <addressBlock>
- <offset>0</offset>
- <size>0x1</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>SCSI_Out_Bits_CONTROL_REG</name>
- <description>No description available</description>
- <addressOffset>0x0</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- </registers>
- </peripheral>
<peripheral>
<name>SCSI_CTL_PHASE</name>
<description>No description available</description>
- <baseAddress>0x4000647B</baseAddress>
+ <baseAddress>0x40006472</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1</size>
projects / SCSI2SD.git / commitdiff