CyDelayUs(1);
nNOR_CS_Write(0); // Select
+ CyDelayCycles(4); // Tiny delay
// JEDEC standard "Read Identification" command
// returns CFI information
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB04_MSK
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB04_ST
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
#define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
#define SDCard_BSPIM_TxStsReg__2__POS 2
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST
/* SD_SCK */
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE1
#define NOR_SCK__SLW CYREG_PRT3_SLW
/* NOR_SPI */
-#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
-#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL
-#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL
-#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL
-#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL
-#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK
-#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK
-#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK
-#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK
-#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL
-#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL
-#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL
-#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL
-#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL
-#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
-#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
-#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK
-#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
-#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
-#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK
-#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
-#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
-#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
-#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL
-#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL
-#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST
-#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
-#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
+#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
+#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
+#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
+#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
+#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
+#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB04_CTL
+#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
+#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB04_CTL
+#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
+#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB04_MSK
+#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
+#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB04_MSK
+#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL
+#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL
+#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB04_ST
+#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
+#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
#define NOR_SPI_BSPIM_RxStsReg__4__MASK 0x10u
#define NOR_SPI_BSPIM_RxStsReg__4__POS 4
#define NOR_SPI_BSPIM_RxStsReg__5__MASK 0x20u
#define NOR_SPI_BSPIM_RxStsReg__6__MASK 0x40u
#define NOR_SPI_BSPIM_RxStsReg__6__POS 6
#define NOR_SPI_BSPIM_RxStsReg__MASK 0x70u
-#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK
-#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
-#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST
-#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0
-#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1
-#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0
-#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB06_07_D1
-#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
-#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB06_07_F0
-#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB06_07_F1
-#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB06_A0_A1
-#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB06_A0
-#define NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB06_A1
-#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB06_D0_D1
-#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB06_D0
-#define NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB06_D1
-#define NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB06_ACTL
-#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB06_F0_F1
-#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB06_F0
-#define NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB06_F1
-#define NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
-#define NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
+#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB11_MSK
+#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
+#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB11_ST
+#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0
+#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1
+#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0
+#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB04_05_D1
+#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB04_05_F0
+#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB04_05_F1
+#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB04_A0_A1
+#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB04_A0
+#define NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB04_A1
+#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB04_D0_D1
+#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB04_D0
+#define NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB04_D1
+#define NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB04_F0_F1
+#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB04_F0
+#define NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB04_F1
+#define NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
#define NOR_SPI_BSPIM_TxStsReg__0__MASK 0x01u
#define NOR_SPI_BSPIM_TxStsReg__0__POS 0
#define NOR_SPI_BSPIM_TxStsReg__1__MASK 0x02u
#define NOR_SPI_BSPIM_TxStsReg__1__POS 1
-#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
-#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
+#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
+#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
#define NOR_SPI_BSPIM_TxStsReg__2__MASK 0x04u
#define NOR_SPI_BSPIM_TxStsReg__2__POS 2
#define NOR_SPI_BSPIM_TxStsReg__3__MASK 0x08u
#define NOR_SPI_BSPIM_TxStsReg__4__MASK 0x10u
#define NOR_SPI_BSPIM_TxStsReg__4__POS 4
#define NOR_SPI_BSPIM_TxStsReg__MASK 0x1Fu
-#define NOR_SPI_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK
-#define NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
-#define NOR_SPI_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST
+#define NOR_SPI_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB03_MSK
+#define NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
+#define NOR_SPI_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB03_ST
/* SCSI_In */
#define SCSI_In__0__INTTYPE CYREG_PICU6_INTTYPE1
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB10_11_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB10_11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB10_11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB10_11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB10_11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB10_11_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB10_11_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB10_11_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB10_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB10_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB10_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB10_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB10_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB10_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB10_MSK
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB08_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB08_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB08_MSK
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX
#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE
#define scsiTarget_StatusReg__0__POS 0
#define scsiTarget_StatusReg__1__MASK 0x02u
#define scsiTarget_StatusReg__1__POS 1
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
#define scsiTarget_StatusReg__2__MASK 0x04u
#define scsiTarget_StatusReg__2__POS 2
#define scsiTarget_StatusReg__3__MASK 0x08u
#define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB03_MSK
-#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
-#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
-#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL
-#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB03_ST
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK
+#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
+#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL
+#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB15_ST_CTL
+#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB15_ST_CTL
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST
/* Debug_Timer */
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SCSI_Filtered_sts_sts_reg__0__POS 0
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
#define SCSI_Filtered_sts_sts_reg__1__POS 1
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
#define SCSI_Filtered_sts_sts_reg__2__POS 2
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
#define SCSI_Filtered_sts_sts_reg__4__POS 4
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB15_MSK
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB15_ST
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B1_UDB08_MSK
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B1_UDB08_ST
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB15_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB15_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB15_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB15_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB15_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB15_MSK
/* SCSI_Glitch_Ctl */
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB09_10_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB09_10_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB09_10_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB09_10_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB09_10_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB09_10_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB09_10_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB09_10_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB09_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB09_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB09_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB09_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB09_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB09_MSK
/* SCSI_Parity_Error */
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B1_UDB08_MSK
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B1_UDB08_ST
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB12_MSK
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB12_ST
/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 50000000U
}
#endif
-#define CY_CFG_BASE_ADDR_COUNT 42u
+#define CY_CFG_BASE_ADDR_COUNT 43u
CYPACKED typedef struct
{
uint8 offset;
static const uint32 CYCODE cy_cfg_addr_table[] = {
0x40004501u, /* Base address: 0x40004500 Count: 1 */
0x40004F02u, /* Base address: 0x40004F00 Count: 2 */
- 0x4000520Bu, /* Base address: 0x40005200 Count: 11 */
+ 0x4000520Cu, /* Base address: 0x40005200 Count: 12 */
0x40006402u, /* Base address: 0x40006400 Count: 2 */
0x40006501u, /* Base address: 0x40006500 Count: 1 */
- 0x4001003Eu, /* Base address: 0x40010000 Count: 62 */
- 0x40010147u, /* Base address: 0x40010100 Count: 71 */
- 0x40010245u, /* Base address: 0x40010200 Count: 69 */
- 0x40010350u, /* Base address: 0x40010300 Count: 80 */
- 0x40010455u, /* Base address: 0x40010400 Count: 85 */
- 0x4001054Eu, /* Base address: 0x40010500 Count: 78 */
- 0x4001066Bu, /* Base address: 0x40010600 Count: 107 */
- 0x40010757u, /* Base address: 0x40010700 Count: 87 */
- 0x4001084Au, /* Base address: 0x40010800 Count: 74 */
- 0x40010952u, /* Base address: 0x40010900 Count: 82 */
- 0x40010A52u, /* Base address: 0x40010A00 Count: 82 */
+ 0x40010041u, /* Base address: 0x40010000 Count: 65 */
+ 0x4001013Fu, /* Base address: 0x40010100 Count: 63 */
+ 0x4001024Du, /* Base address: 0x40010200 Count: 77 */
+ 0x40010348u, /* Base address: 0x40010300 Count: 72 */
+ 0x40010418u, /* Base address: 0x40010400 Count: 24 */
+ 0x40010556u, /* Base address: 0x40010500 Count: 86 */
+ 0x4001064Fu, /* Base address: 0x40010600 Count: 79 */
+ 0x40010751u, /* Base address: 0x40010700 Count: 81 */
+ 0x40010848u, /* Base address: 0x40010800 Count: 72 */
+ 0x40010955u, /* Base address: 0x40010900 Count: 85 */
+ 0x40010A5Fu, /* Base address: 0x40010A00 Count: 95 */
0x40010B56u, /* Base address: 0x40010B00 Count: 86 */
- 0x40010C4Fu, /* Base address: 0x40010C00 Count: 79 */
- 0x40010D57u, /* Base address: 0x40010D00 Count: 87 */
- 0x40010E4Cu, /* Base address: 0x40010E00 Count: 76 */
- 0x40010F3Cu, /* Base address: 0x40010F00 Count: 60 */
- 0x4001141Cu, /* Base address: 0x40011400 Count: 28 */
- 0x4001155Cu, /* Base address: 0x40011500 Count: 92 */
- 0x40011653u, /* Base address: 0x40011600 Count: 83 */
- 0x40011755u, /* Base address: 0x40011700 Count: 85 */
- 0x40011857u, /* Base address: 0x40011800 Count: 87 */
- 0x4001194Cu, /* Base address: 0x40011900 Count: 76 */
- 0x40011B09u, /* Base address: 0x40011B00 Count: 9 */
- 0x4001401Du, /* Base address: 0x40014000 Count: 29 */
- 0x40014121u, /* Base address: 0x40014100 Count: 33 */
- 0x40014215u, /* Base address: 0x40014200 Count: 21 */
- 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */
- 0x40014410u, /* Base address: 0x40014400 Count: 16 */
- 0x40014519u, /* Base address: 0x40014500 Count: 25 */
- 0x40014614u, /* Base address: 0x40014600 Count: 20 */
- 0x40014715u, /* Base address: 0x40014700 Count: 21 */
- 0x4001480Du, /* Base address: 0x40014800 Count: 13 */
- 0x40014913u, /* Base address: 0x40014900 Count: 19 */
- 0x40014C08u, /* Base address: 0x40014C00 Count: 8 */
- 0x40014D03u, /* Base address: 0x40014D00 Count: 3 */
+ 0x40010C50u, /* Base address: 0x40010C00 Count: 80 */
+ 0x40010D55u, /* Base address: 0x40010D00 Count: 85 */
+ 0x40010E49u, /* Base address: 0x40010E00 Count: 73 */
+ 0x40010F37u, /* Base address: 0x40010F00 Count: 55 */
+ 0x4001141Au, /* Base address: 0x40011400 Count: 26 */
+ 0x40011553u, /* Base address: 0x40011500 Count: 83 */
+ 0x40011656u, /* Base address: 0x40011600 Count: 86 */
+ 0x40011753u, /* Base address: 0x40011700 Count: 83 */
+ 0x4001184Bu, /* Base address: 0x40011800 Count: 75 */
+ 0x40011954u, /* Base address: 0x40011900 Count: 84 */
+ 0x40011A47u, /* Base address: 0x40011A00 Count: 71 */
+ 0x40011B52u, /* Base address: 0x40011B00 Count: 82 */
+ 0x4001401Au, /* Base address: 0x40014000 Count: 26 */
+ 0x40014125u, /* Base address: 0x40014100 Count: 37 */
+ 0x40014212u, /* Base address: 0x40014200 Count: 18 */
+ 0x4001430Cu, /* Base address: 0x40014300 Count: 12 */
+ 0x4001440Fu, /* Base address: 0x40014400 Count: 15 */
+ 0x4001451Du, /* Base address: 0x40014500 Count: 29 */
+ 0x40014611u, /* Base address: 0x40014600 Count: 17 */
+ 0x40014716u, /* Base address: 0x40014700 Count: 22 */
+ 0x4001480Fu, /* Base address: 0x40014800 Count: 15 */
+ 0x4001491Au, /* Base address: 0x40014900 Count: 26 */
+ 0x40014C03u, /* Base address: 0x40014C00 Count: 3 */
+ 0x40014D05u, /* Base address: 0x40014D00 Count: 5 */
0x40015005u, /* Base address: 0x40015000 Count: 5 */
0x40015104u, /* Base address: 0x40015100 Count: 4 */
};
static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = {
{0x7Eu, 0x02u},
{0x01u, 0x30u},
- {0x0Au, 0x27u},
+ {0x0Au, 0x36u},
{0x01u, 0x22u},
- {0x10u, 0x0Au},
- {0x11u, 0x88u},
- {0x18u, 0x8Au},
+ {0x10u, 0xA8u},
+ {0x11u, 0x2Au},
+ {0x18u, 0x84u},
{0x19u, 0x82u},
{0x1Cu, 0x08u},
- {0x20u, 0x01u},
+ {0x20u, 0x02u},
{0x21u, 0x03u},
- {0x31u, 0x80u},
+ {0x30u, 0x84u},
+ {0x60u, 0x02u},
{0x78u, 0x20u},
{0x7Cu, 0x40u},
{0x20u, 0x01u},
- {0x86u, 0x0Fu},
{0x84u, 0x0Fu},
- {0x01u, 0x08u},
- {0x03u, 0x10u},
- {0x06u, 0x24u},
- {0x07u, 0x03u},
- {0x0Bu, 0x84u},
- {0x0Cu, 0x24u},
- {0x0Eu, 0x12u},
- {0x0Fu, 0x80u},
- {0x12u, 0x18u},
+ {0x84u, 0x0Fu},
+ {0x01u, 0x6Du},
+ {0x02u, 0x20u},
+ {0x05u, 0x12u},
+ {0x06u, 0x03u},
+ {0x07u, 0xE8u},
+ {0x09u, 0x0Du},
+ {0x0Bu, 0x60u},
+ {0x0Du, 0x6Du},
+ {0x11u, 0x71u},
+ {0x12u, 0x24u},
+ {0x13u, 0x82u},
{0x14u, 0x24u},
+ {0x15u, 0x02u},
{0x16u, 0x09u},
- {0x19u, 0x08u},
- {0x1Au, 0x03u},
- {0x1Bu, 0x60u},
- {0x1Fu, 0x04u},
- {0x21u, 0x10u},
- {0x22u, 0x20u},
- {0x29u, 0x84u},
- {0x2Au, 0x04u},
- {0x2Bu, 0x21u},
- {0x2Du, 0x84u},
- {0x2Fu, 0x42u},
- {0x30u, 0x38u},
- {0x33u, 0x07u},
+ {0x17u, 0x0Du},
+ {0x19u, 0x92u},
+ {0x1Bu, 0x64u},
+ {0x1Du, 0x20u},
+ {0x1Eu, 0x18u},
+ {0x21u, 0x40u},
+ {0x22u, 0x04u},
+ {0x24u, 0x24u},
+ {0x26u, 0x12u},
+ {0x28u, 0x40u},
+ {0x29u, 0x2Du},
+ {0x2Bu, 0x40u},
+ {0x2Du, 0x6Du},
+ {0x30u, 0x40u},
+ {0x33u, 0x0Fu},
{0x34u, 0x07u},
- {0x35u, 0xE0u},
- {0x37u, 0x18u},
- {0x3Fu, 0x40u},
- {0x40u, 0x63u},
+ {0x35u, 0xF0u},
+ {0x36u, 0x38u},
+ {0x39u, 0x20u},
+ {0x3Bu, 0x08u},
+ {0x3Eu, 0x01u},
+ {0x40u, 0x13u},
{0x41u, 0x02u},
- {0x42u, 0x10u},
- {0x45u, 0xECu},
- {0x46u, 0x2Du},
- {0x47u, 0x0Fu},
+ {0x42u, 0x60u},
+ {0x45u, 0x2Cu},
+ {0x46u, 0xFDu},
+ {0x47u, 0x0Eu},
{0x48u, 0x1Fu},
{0x49u, 0xFFu},
{0x4Au, 0xFFu},
{0x59u, 0x04u},
{0x5Au, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x22u},
+ {0x5Cu, 0x02u},
{0x5Du, 0x02u},
{0x5Fu, 0x01u},
{0x60u, 0x08u},
{0x68u, 0x40u},
{0x69u, 0x40u},
{0x6Eu, 0x08u},
- {0x88u, 0x02u},
- {0xA4u, 0x01u},
- {0xB0u, 0x01u},
- {0xB4u, 0x02u},
- {0xBEu, 0x01u},
- {0xD8u, 0x04u},
- {0xDBu, 0x04u},
- {0xDCu, 0x09u},
+ {0xADu, 0x01u},
+ {0xB3u, 0x01u},
+ {0xBFu, 0x04u},
+ {0xD9u, 0x04u},
{0xDFu, 0x01u},
- {0x00u, 0x08u},
- {0x01u, 0x80u},
- {0x05u, 0x10u},
- {0x07u, 0x04u},
- {0x08u, 0x08u},
- {0x0Au, 0x44u},
+ {0x00u, 0x06u},
+ {0x08u, 0x0Au},
+ {0x0Au, 0x01u},
{0x10u, 0x80u},
- {0x11u, 0x10u},
- {0x16u, 0x10u},
- {0x1Au, 0xC4u},
- {0x1Cu, 0x04u},
- {0x1Fu, 0x01u},
- {0x21u, 0x44u},
- {0x22u, 0x10u},
- {0x28u, 0x08u},
- {0x29u, 0x80u},
- {0x2Au, 0x01u},
- {0x32u, 0x10u},
- {0x33u, 0x40u},
- {0x35u, 0x40u},
- {0x36u, 0x40u},
- {0x38u, 0x02u},
- {0x39u, 0x48u},
- {0x3Bu, 0x10u},
- {0x40u, 0x08u},
- {0x41u, 0x10u},
- {0x42u, 0x21u},
- {0x48u, 0x14u},
- {0x49u, 0x04u},
- {0x4Au, 0x40u},
- {0x4Bu, 0x10u},
- {0x50u, 0x20u},
- {0x51u, 0xA0u},
- {0x52u, 0x80u},
- {0x53u, 0x04u},
- {0x58u, 0x42u},
- {0x5Bu, 0x28u},
- {0x60u, 0x20u},
- {0x62u, 0x20u},
- {0x63u, 0x81u},
- {0x65u, 0x20u},
- {0x67u, 0x08u},
- {0x69u, 0x50u},
- {0x6Au, 0x08u},
- {0x6Bu, 0x40u},
- {0x6Cu, 0x01u},
- {0x6Fu, 0x02u},
+ {0x11u, 0x28u},
+ {0x18u, 0x04u},
+ {0x1Au, 0x01u},
+ {0x1Bu, 0x81u},
+ {0x20u, 0x08u},
+ {0x21u, 0x20u},
+ {0x22u, 0x14u},
+ {0x23u, 0x04u},
+ {0x24u, 0x20u},
+ {0x29u, 0x42u},
+ {0x2Au, 0x10u},
+ {0x2Fu, 0x02u},
+ {0x31u, 0x22u},
+ {0x32u, 0x44u},
+ {0x39u, 0x61u},
+ {0x3Au, 0x04u},
+ {0x40u, 0x0Au},
+ {0x41u, 0x04u},
+ {0x49u, 0x20u},
+ {0x4Au, 0x90u},
+ {0x4Bu, 0x02u},
+ {0x51u, 0x80u},
+ {0x52u, 0x48u},
+ {0x53u, 0x20u},
+ {0x58u, 0x04u},
+ {0x59u, 0x01u},
+ {0x5Au, 0x40u},
+ {0x5Bu, 0x10u},
+ {0x61u, 0x18u},
+ {0x62u, 0x02u},
+ {0x63u, 0x01u},
+ {0x68u, 0x01u},
+ {0x69u, 0x14u},
+ {0x6Bu, 0x80u},
{0x70u, 0x80u},
- {0x71u, 0x08u},
- {0x72u, 0x08u},
- {0x73u, 0x40u},
- {0x80u, 0x04u},
- {0x81u, 0x18u},
- {0x84u, 0x60u},
- {0x87u, 0x40u},
- {0x88u, 0x20u},
- {0x8Au, 0x08u},
- {0x8Bu, 0x20u},
- {0xC0u, 0x45u},
- {0xC2u, 0x0Eu},
- {0xC4u, 0x2Au},
- {0xCAu, 0x0Du},
- {0xCCu, 0x0Cu},
+ {0x72u, 0x04u},
+ {0x73u, 0x50u},
+ {0x81u, 0x90u},
+ {0x82u, 0x08u},
+ {0x83u, 0x80u},
+ {0x86u, 0x02u},
+ {0x87u, 0x22u},
+ {0x8Au, 0x10u},
+ {0x8Du, 0x14u},
+ {0x8Eu, 0x01u},
+ {0xC0u, 0x0Cu},
+ {0xC2u, 0x0Du},
+ {0xC4u, 0x0Eu},
+ {0xCAu, 0x1Du},
+ {0xCCu, 0x0Fu},
{0xCEu, 0x0Fu},
{0xD0u, 0x0Eu},
{0xD2u, 0x04u},
{0xD6u, 0x0Fu},
{0xD8u, 0x0Fu},
- {0xE0u, 0x03u},
- {0xE4u, 0x06u},
- {0xE6u, 0x08u},
- {0x08u, 0x02u},
- {0x0Du, 0x02u},
- {0x0Fu, 0x01u},
- {0x10u, 0x01u},
- {0x11u, 0x02u},
- {0x13u, 0x11u},
- {0x15u, 0x01u},
+ {0xE0u, 0x05u},
+ {0xE2u, 0x0Au},
+ {0xE4u, 0x09u},
+ {0xE6u, 0x04u},
+ {0x05u, 0x02u},
+ {0x0Fu, 0x02u},
+ {0x14u, 0x02u},
+ {0x16u, 0x05u},
{0x17u, 0x02u},
- {0x19u, 0x02u},
- {0x1Bu, 0x05u},
+ {0x18u, 0x02u},
+ {0x1Au, 0x09u},
+ {0x1Cu, 0x02u},
+ {0x1Eu, 0x01u},
{0x20u, 0x02u},
- {0x2Du, 0x02u},
- {0x2Fu, 0x09u},
- {0x31u, 0x10u},
- {0x33u, 0x08u},
- {0x34u, 0x01u},
- {0x35u, 0x03u},
- {0x36u, 0x02u},
- {0x37u, 0x04u},
- {0x38u, 0x80u},
- {0x3Bu, 0x20u},
- {0x3Eu, 0x10u},
+ {0x22u, 0x11u},
+ {0x2Cu, 0x01u},
+ {0x2Du, 0x01u},
+ {0x2Eu, 0x02u},
+ {0x30u, 0x03u},
+ {0x31u, 0x02u},
+ {0x32u, 0x10u},
+ {0x34u, 0x04u},
+ {0x36u, 0x08u},
+ {0x37u, 0x01u},
+ {0x3Au, 0x02u},
+ {0x3Fu, 0x01u},
{0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x20u},
+ {0x5Cu, 0x92u},
{0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x80u, 0x04u},
{0x81u, 0x28u},
- {0x82u, 0x10u},
- {0x83u, 0x04u},
- {0x84u, 0x2Bu},
- {0x85u, 0x12u},
- {0x86u, 0x14u},
- {0x87u, 0x01u},
- {0x88u, 0x43u},
- {0x8Au, 0x0Cu},
- {0x8Cu, 0x28u},
- {0x8Du, 0x04u},
- {0x8Eu, 0x17u},
- {0x8Fu, 0x08u},
- {0x91u, 0x13u},
- {0x93u, 0x2Cu},
- {0x94u, 0x0Du},
- {0x96u, 0x12u},
- {0x9Au, 0x01u},
- {0x9Bu, 0x40u},
- {0x9Cu, 0x10u},
- {0x9Du, 0x01u},
- {0x9Eu, 0x20u},
- {0x9Fu, 0x02u},
- {0xA0u, 0x02u},
- {0xAAu, 0x17u},
- {0xB0u, 0x40u},
- {0xB1u, 0x0Fu},
- {0xB2u, 0x0Fu},
- {0xB3u, 0x30u},
- {0xB5u, 0x40u},
- {0xB6u, 0x30u},
- {0xBAu, 0x88u},
- {0xBEu, 0x01u},
+ {0x85u, 0x28u},
+ {0x86u, 0xFFu},
+ {0x88u, 0xC0u},
+ {0x89u, 0x28u},
+ {0x8Au, 0x08u},
+ {0x8Cu, 0x1Fu},
+ {0x8Eu, 0x20u},
+ {0x8Fu, 0x28u},
+ {0x90u, 0x80u},
+ {0x93u, 0x20u},
+ {0x95u, 0x05u},
+ {0x96u, 0x9Fu},
+ {0x97u, 0x02u},
+ {0x99u, 0x03u},
+ {0x9Au, 0x60u},
+ {0x9Bu, 0x04u},
+ {0x9Cu, 0xC0u},
+ {0x9Du, 0x04u},
+ {0x9Eu, 0x01u},
+ {0x9Fu, 0x03u},
+ {0xA0u, 0xC0u},
+ {0xA1u, 0x28u},
+ {0xA2u, 0x02u},
+ {0xA4u, 0xC0u},
+ {0xA5u, 0x10u},
+ {0xA6u, 0x04u},
+ {0xA8u, 0x7Fu},
+ {0xA9u, 0x10u},
+ {0xAAu, 0x80u},
+ {0xACu, 0x90u},
+ {0xADu, 0x01u},
+ {0xAEu, 0x40u},
+ {0xAFu, 0x06u},
+ {0xB1u, 0x08u},
+ {0xB2u, 0xFFu},
+ {0xB3u, 0x20u},
+ {0xB5u, 0x10u},
+ {0xB7u, 0x07u},
+ {0xB9u, 0x20u},
+ {0xBBu, 0x80u},
+ {0xBEu, 0x04u},
{0xBFu, 0x05u},
+ {0xD4u, 0x09u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x22u},
{0xDFu, 0x01u},
- {0x00u, 0x89u},
- {0x03u, 0x08u},
- {0x04u, 0x20u},
- {0x09u, 0x24u},
- {0x0Au, 0x01u},
- {0x0Fu, 0x40u},
- {0x12u, 0x88u},
- {0x15u, 0x40u},
- {0x16u, 0x01u},
- {0x17u, 0x02u},
- {0x1Au, 0x01u},
- {0x1Bu, 0x09u},
- {0x1Cu, 0x02u},
- {0x1Fu, 0x20u},
- {0x20u, 0x14u},
- {0x21u, 0x01u},
- {0x24u, 0x40u},
- {0x27u, 0x15u},
- {0x2Fu, 0x01u},
- {0x30u, 0x80u},
- {0x32u, 0x50u},
- {0x33u, 0x02u},
- {0x37u, 0x15u},
- {0x38u, 0x80u},
- {0x39u, 0x09u},
- {0x3Cu, 0x40u},
- {0x59u, 0x64u},
+ {0x00u, 0x88u},
+ {0x03u, 0x04u},
+ {0x09u, 0x20u},
+ {0x0Au, 0x81u},
+ {0x0Bu, 0x20u},
+ {0x0Eu, 0x2Au},
+ {0x10u, 0x20u},
+ {0x11u, 0x41u},
+ {0x12u, 0x18u},
+ {0x14u, 0x01u},
+ {0x16u, 0x80u},
+ {0x1Bu, 0x04u},
+ {0x1Eu, 0x2Au},
+ {0x1Fu, 0x02u},
+ {0x20u, 0x20u},
+ {0x21u, 0x20u},
+ {0x22u, 0x83u},
+ {0x27u, 0x41u},
+ {0x29u, 0x80u},
+ {0x2Au, 0x02u},
+ {0x2Bu, 0x14u},
+ {0x2Cu, 0x01u},
+ {0x2Fu, 0x02u},
+ {0x30u, 0x02u},
+ {0x32u, 0x98u},
+ {0x36u, 0x08u},
+ {0x39u, 0x69u},
+ {0x3Cu, 0x80u},
+ {0x3Fu, 0x04u},
+ {0x59u, 0x14u},
{0x5Au, 0x02u},
- {0x5Du, 0x80u},
- {0x5Fu, 0x10u},
- {0x62u, 0x40u},
- {0x64u, 0x04u},
- {0x67u, 0x02u},
- {0x68u, 0x10u},
- {0x69u, 0x51u},
- {0x70u, 0x40u},
- {0x71u, 0x10u},
- {0x72u, 0x62u},
- {0x82u, 0x20u},
- {0x84u, 0x10u},
- {0x86u, 0x04u},
- {0x8Au, 0x40u},
- {0x8Du, 0x10u},
- {0x8Eu, 0x40u},
- {0x90u, 0x02u},
- {0x91u, 0x88u},
- {0x92u, 0x86u},
- {0x95u, 0x20u},
- {0x96u, 0x01u},
+ {0x5Bu, 0x40u},
+ {0x5Cu, 0x80u},
+ {0x61u, 0x80u},
+ {0x66u, 0x80u},
+ {0x83u, 0x01u},
+ {0x87u, 0x01u},
+ {0x8Bu, 0x01u},
+ {0x8Cu, 0x04u},
+ {0x90u, 0x04u},
+ {0x91u, 0x14u},
+ {0x92u, 0x24u},
+ {0x93u, 0x06u},
+ {0x95u, 0x61u},
+ {0x96u, 0xC0u},
{0x97u, 0x01u},
- {0x99u, 0x64u},
+ {0x9Au, 0x41u},
+ {0x9Cu, 0x0Eu},
+ {0x9Du, 0x63u},
+ {0x9Eu, 0x14u},
+ {0x9Fu, 0x10u},
+ {0xA0u, 0x04u},
+ {0xA1u, 0x04u},
+ {0xA3u, 0x81u},
+ {0xA5u, 0x0Au},
+ {0xA8u, 0x10u},
+ {0xADu, 0x04u},
+ {0xB2u, 0x80u},
+ {0xB3u, 0x50u},
+ {0xB5u, 0x20u},
+ {0xB7u, 0x20u},
+ {0xC0u, 0x07u},
+ {0xC2u, 0xEFu},
+ {0xC4u, 0x9Fu},
+ {0xCAu, 0x1Fu},
+ {0xCCu, 0x4Fu},
+ {0xCEu, 0x5Fu},
+ {0xD6u, 0x1Fu},
+ {0xD8u, 0x18u},
+ {0xE2u, 0x85u},
+ {0xE6u, 0x20u},
+ {0xEAu, 0x48u},
+ {0x80u, 0x04u},
+ {0x82u, 0x02u},
+ {0x94u, 0x04u},
+ {0x96u, 0x0Au},
+ {0x98u, 0x04u},
+ {0x99u, 0x01u},
+ {0x9Au, 0x12u},
{0x9Cu, 0x02u},
- {0x9Eu, 0x01u},
- {0x9Fu, 0x0Cu},
+ {0x9Eu, 0x04u},
+ {0xA0u, 0x04u},
+ {0xA2u, 0x03u},
+ {0xB0u, 0x10u},
+ {0xB2u, 0x01u},
+ {0xB4u, 0x08u},
+ {0xB6u, 0x06u},
+ {0xB7u, 0x01u},
+ {0xBAu, 0x80u},
+ {0xD6u, 0x08u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDBu, 0x04u},
+ {0xDCu, 0x92u},
+ {0xDDu, 0x90u},
+ {0xDFu, 0x01u},
+ {0x00u, 0x98u},
+ {0x01u, 0x80u},
+ {0x05u, 0x01u},
+ {0x09u, 0x20u},
+ {0x0Au, 0x81u},
+ {0x0Bu, 0x20u},
+ {0x0Eu, 0x2Au},
+ {0x10u, 0x20u},
+ {0x11u, 0x41u},
+ {0x12u, 0x0Cu},
+ {0x16u, 0x80u},
+ {0x18u, 0x10u},
+ {0x1Bu, 0x10u},
+ {0x1Du, 0x01u},
+ {0x1Eu, 0x2Au},
+ {0x22u, 0x14u},
+ {0x27u, 0x02u},
+ {0x28u, 0x08u},
+ {0x32u, 0x14u},
+ {0x37u, 0x20u},
+ {0x39u, 0x14u},
+ {0x3Au, 0x01u},
+ {0x3Bu, 0x40u},
+ {0x40u, 0x04u},
+ {0x41u, 0x02u},
+ {0x43u, 0x08u},
+ {0x48u, 0x04u},
+ {0x49u, 0x06u},
+ {0x4Au, 0x02u},
+ {0x50u, 0x02u},
+ {0x53u, 0x52u},
+ {0x5Cu, 0x80u},
+ {0x62u, 0x80u},
+ {0x66u, 0x80u},
+ {0x68u, 0x20u},
+ {0x69u, 0x69u},
+ {0x6Bu, 0x04u},
+ {0x71u, 0x40u},
+ {0x72u, 0x03u},
+ {0x80u, 0x10u},
+ {0x83u, 0x10u},
+ {0x84u, 0x04u},
+ {0x88u, 0x80u},
+ {0x8Eu, 0x10u},
+ {0x8Fu, 0x02u},
+ {0x91u, 0x14u},
+ {0x93u, 0x46u},
+ {0x95u, 0x69u},
+ {0x96u, 0xC1u},
+ {0x97u, 0x20u},
+ {0x98u, 0x01u},
+ {0x9Au, 0x41u},
+ {0x9Cu, 0x0Cu},
+ {0x9Du, 0xE6u},
+ {0x9Eu, 0x06u},
+ {0x9Fu, 0x14u},
+ {0xA0u, 0x04u},
{0xA1u, 0x24u},
- {0xA2u, 0x80u},
- {0xA3u, 0x02u},
- {0xA4u, 0x04u},
- {0xA6u, 0x20u},
- {0xA7u, 0x40u},
- {0xA9u, 0xA4u},
+ {0xA2u, 0x82u},
+ {0xA4u, 0x62u},
+ {0xA5u, 0x0Au},
+ {0xA6u, 0x28u},
+ {0xA7u, 0x10u},
+ {0xA9u, 0x93u},
{0xAAu, 0x20u},
- {0xACu, 0x10u},
- {0xAEu, 0x40u},
- {0xB1u, 0x80u},
- {0xB2u, 0x15u},
- {0xB5u, 0x40u},
- {0xB7u, 0x01u},
- {0xC0u, 0x4Fu},
- {0xC2u, 0x17u},
- {0xC4u, 0x1Au},
- {0xCAu, 0x10u},
- {0xCCu, 0xEDu},
- {0xCEu, 0x1Bu},
- {0xD6u, 0x3Fu},
- {0xD8u, 0x38u},
- {0xE0u, 0x2Eu},
- {0xE6u, 0x02u},
- {0xE8u, 0x08u},
- {0xEAu, 0x44u},
- {0x00u, 0x04u},
- {0x04u, 0x01u},
- {0x05u, 0x02u},
- {0x07u, 0x01u},
- {0x08u, 0x22u},
+ {0xACu, 0x02u},
+ {0xAFu, 0x40u},
+ {0xB0u, 0x10u},
+ {0xB2u, 0x04u},
+ {0xB3u, 0x80u},
+ {0xB4u, 0x80u},
+ {0xC0u, 0x17u},
+ {0xC2u, 0xEFu},
+ {0xC4u, 0x1Fu},
+ {0xCAu, 0x04u},
+ {0xCCu, 0x26u},
+ {0xCEu, 0x0Fu},
+ {0xD0u, 0x07u},
+ {0xD2u, 0x0Cu},
+ {0xD6u, 0x10u},
+ {0xD8u, 0x18u},
+ {0xE0u, 0x20u},
+ {0xE2u, 0x1Cu},
+ {0xE8u, 0x10u},
+ {0xEAu, 0x04u},
+ {0xEEu, 0x42u},
+ {0x04u, 0x0Du},
+ {0x08u, 0x02u},
+ {0x09u, 0x02u},
{0x0Au, 0x08u},
+ {0x0Bu, 0x01u},
{0x0Cu, 0x01u},
- {0x10u, 0x01u},
- {0x14u, 0x07u},
- {0x15u, 0x01u},
- {0x16u, 0x18u},
- {0x17u, 0x02u},
- {0x18u, 0x08u},
- {0x19u, 0x02u},
- {0x1Au, 0x21u},
- {0x1Bu, 0x01u},
- {0x1Du, 0x02u},
- {0x1Fu, 0x09u},
- {0x20u, 0x01u},
- {0x24u, 0x10u},
- {0x28u, 0x40u},
- {0x29u, 0x02u},
- {0x2Bu, 0x05u},
- {0x2Cu, 0x01u},
- {0x32u, 0x3Fu},
+ {0x0Du, 0x02u},
+ {0x0Eu, 0x02u},
+ {0x0Fu, 0x05u},
+ {0x10u, 0x0Du},
+ {0x11u, 0x02u},
+ {0x13u, 0x09u},
+ {0x15u, 0x02u},
+ {0x17u, 0x01u},
+ {0x18u, 0x02u},
+ {0x19u, 0x01u},
+ {0x1Au, 0x0Du},
+ {0x1Bu, 0x02u},
+ {0x1Cu, 0x02u},
+ {0x1Eu, 0x04u},
+ {0x20u, 0x0Du},
+ {0x28u, 0x0Du},
+ {0x2Cu, 0x0Du},
{0x33u, 0x03u},
- {0x34u, 0x40u},
- {0x35u, 0x08u},
- {0x37u, 0x04u},
- {0x38u, 0x08u},
+ {0x34u, 0x0Fu},
+ {0x35u, 0x04u},
+ {0x37u, 0x08u},
+ {0x3Au, 0x20u},
{0x3Bu, 0x08u},
- {0x3Eu, 0x04u},
- {0x54u, 0x40u},
- {0x56u, 0x04u},
+ {0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x29u},
- {0x5Du, 0x10u},
+ {0x5Cu, 0x21u},
+ {0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x80u, 0x84u},
- {0x83u, 0x60u},
- {0x84u, 0x42u},
- {0x86u, 0x84u},
- {0x87u, 0x9Fu},
- {0x88u, 0x01u},
- {0x89u, 0xC0u},
- {0x8Au, 0xFEu},
- {0x8Bu, 0x08u},
- {0x8Du, 0x90u},
- {0x8Fu, 0x40u},
- {0x90u, 0x42u},
- {0x91u, 0x80u},
- {0x94u, 0x17u},
- {0x95u, 0x1Fu},
- {0x96u, 0x28u},
- {0x97u, 0x20u},
- {0x98u, 0x19u},
- {0x99u, 0xC0u},
- {0x9Au, 0xE6u},
- {0x9Bu, 0x04u},
- {0x9Cu, 0xC6u},
- {0x9Du, 0xC0u},
- {0x9Fu, 0x01u},
- {0xA0u, 0xC6u},
- {0xA1u, 0xC0u},
- {0xA3u, 0x02u},
- {0xA6u, 0xC6u},
- {0xA7u, 0xFFu},
- {0xA9u, 0x7Fu},
- {0xABu, 0x80u},
- {0xACu, 0xC6u},
- {0xB0u, 0x08u},
- {0xB2u, 0xF0u},
+ {0x80u, 0x02u},
+ {0x85u, 0x18u},
+ {0x8Cu, 0x10u},
+ {0x8Du, 0x05u},
+ {0x8Eu, 0x20u},
+ {0x8Fu, 0x28u},
+ {0x90u, 0x10u},
+ {0x91u, 0x02u},
+ {0x92u, 0x20u},
+ {0x94u, 0x34u},
+ {0x95u, 0x02u},
+ {0x98u, 0x03u},
+ {0x99u, 0x09u},
+ {0x9Au, 0x0Cu},
+ {0x9Bu, 0x24u},
+ {0x9Eu, 0x01u},
+ {0xA0u, 0x08u},
+ {0xA2u, 0x37u},
+ {0xA4u, 0x3Du},
+ {0xA6u, 0x02u},
+ {0xA9u, 0x02u},
+ {0xAAu, 0x37u},
+ {0xACu, 0x0Bu},
+ {0xADu, 0x25u},
+ {0xAEu, 0x34u},
+ {0xAFu, 0x10u},
+ {0xB0u, 0x30u},
+ {0xB1u, 0x20u},
+ {0xB3u, 0x1Cu},
{0xB4u, 0x0Fu},
- {0xB6u, 0x01u},
- {0xB7u, 0xFFu},
- {0xB8u, 0x20u},
- {0xBEu, 0x41u},
- {0xBFu, 0x40u},
+ {0xB5u, 0x02u},
+ {0xB7u, 0x01u},
+ {0xB9u, 0x08u},
+ {0xBAu, 0x22u},
+ {0xBFu, 0x51u},
{0xD4u, 0x09u},
+ {0xD6u, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
+ {0xDCu, 0x12u},
+ {0xDDu, 0x10u},
{0xDFu, 0x01u},
- {0x00u, 0x22u},
{0x01u, 0x80u},
- {0x03u, 0x10u},
- {0x04u, 0x10u},
- {0x06u, 0x80u},
- {0x07u, 0x10u},
+ {0x02u, 0x40u},
+ {0x04u, 0x80u},
+ {0x05u, 0x10u},
+ {0x06u, 0x20u},
{0x08u, 0x08u},
- {0x09u, 0x28u},
- {0x0Au, 0x40u},
- {0x0Du, 0x08u},
- {0x0Eu, 0x49u},
- {0x11u, 0x89u},
- {0x12u, 0x08u},
- {0x16u, 0x01u},
- {0x17u, 0x05u},
- {0x18u, 0x28u},
- {0x1Cu, 0x40u},
- {0x1Du, 0x6Cu},
+ {0x0Au, 0x44u},
+ {0x0Bu, 0x02u},
+ {0x0Du, 0x01u},
+ {0x0Eu, 0x08u},
+ {0x0Fu, 0x02u},
+ {0x10u, 0x40u},
+ {0x11u, 0x08u},
+ {0x13u, 0x60u},
+ {0x16u, 0x0Au},
+ {0x17u, 0x01u},
+ {0x1Au, 0x44u},
{0x1Eu, 0x08u},
- {0x1Fu, 0x10u},
- {0x22u, 0x58u},
- {0x27u, 0x02u},
- {0x28u, 0x04u},
- {0x2Du, 0x01u},
- {0x2Fu, 0x14u},
- {0x32u, 0x58u},
- {0x35u, 0x85u},
- {0x37u, 0x10u},
- {0x38u, 0x04u},
- {0x3Cu, 0x02u},
- {0x3Du, 0xA0u},
- {0x3Eu, 0x08u},
- {0x5Cu, 0x40u},
- {0x5Eu, 0x02u},
- {0x5Fu, 0x24u},
- {0x62u, 0x92u},
- {0x63u, 0x20u},
- {0x65u, 0x40u},
- {0x82u, 0x20u},
- {0x85u, 0x10u},
- {0x89u, 0x01u},
- {0x8Fu, 0x41u},
- {0x90u, 0x06u},
- {0x91u, 0x92u},
- {0x94u, 0x28u},
- {0x95u, 0x20u},
- {0x96u, 0x20u},
- {0x97u, 0x01u},
- {0x98u, 0x04u},
- {0x9Au, 0x02u},
- {0x9Cu, 0x02u},
- {0x9Fu, 0x0Au},
- {0xA0u, 0x81u},
- {0xA4u, 0x44u},
- {0xA6u, 0x2Au},
- {0xA7u, 0x40u},
- {0xA8u, 0x11u},
- {0xAAu, 0x08u},
- {0xABu, 0x20u},
- {0xAEu, 0x02u},
- {0xAFu, 0x51u},
- {0xB1u, 0x80u},
- {0xB4u, 0x05u},
- {0xC0u, 0x7Fu},
- {0xC2u, 0xFEu},
- {0xC4u, 0xBFu},
- {0xCAu, 0xE4u},
- {0xCCu, 0xFEu},
- {0xCEu, 0xF2u},
- {0xD6u, 0xF0u},
- {0xD8u, 0x1Fu},
- {0xE2u, 0x06u},
- {0xE4u, 0x08u},
- {0xE6u, 0x01u},
- {0xE8u, 0x04u},
- {0xEAu, 0x11u},
- {0xECu, 0x81u},
- {0xEEu, 0x02u},
- {0x02u, 0x40u},
- {0x04u, 0x04u},
- {0x06u, 0x03u},
- {0x08u, 0x1Du},
- {0x0Au, 0xA2u},
- {0x0Cu, 0x80u},
- {0x0Eu, 0x08u},
- {0x10u, 0x90u},
- {0x12u, 0x08u},
- {0x14u, 0xE9u},
- {0x16u, 0x16u},
- {0x18u, 0x73u},
- {0x1Au, 0x0Cu},
- {0x1Cu, 0x88u},
- {0x20u, 0x88u},
- {0x24u, 0x08u},
- {0x26u, 0x80u},
- {0x28u, 0x88u},
- {0x30u, 0x18u},
- {0x32u, 0xE0u},
- {0x34u, 0x07u},
- {0x39u, 0x02u},
- {0x3Au, 0x2Eu},
- {0x3Fu, 0x01u},
- {0x40u, 0x26u},
- {0x41u, 0x03u},
- {0x42u, 0x40u},
- {0x44u, 0x05u},
- {0x45u, 0xDEu},
- {0x46u, 0xFCu},
- {0x47u, 0x0Bu},
- {0x48u, 0x1Fu},
- {0x49u, 0xFFu},
- {0x4Au, 0xFFu},
- {0x4Bu, 0xFFu},
- {0x4Cu, 0x22u},
- {0x4Eu, 0xF0u},
- {0x4Fu, 0x08u},
- {0x50u, 0x04u},
- {0x56u, 0x02u},
- {0x57u, 0x28u},
- {0x58u, 0x04u},
+ {0x21u, 0x04u},
+ {0x22u, 0xA0u},
+ {0x23u, 0x90u},
+ {0x24u, 0x20u},
+ {0x25u, 0x50u},
+ {0x27u, 0x20u},
+ {0x2Au, 0x10u},
+ {0x2Bu, 0x01u},
+ {0x31u, 0x12u},
+ {0x32u, 0x08u},
+ {0x34u, 0x02u},
+ {0x37u, 0x24u},
+ {0x38u, 0x80u},
+ {0x39u, 0x08u},
+ {0x3Du, 0xA0u},
{0x59u, 0x04u},
- {0x5Au, 0x04u},
- {0x5Bu, 0x04u},
- {0x5Fu, 0x01u},
- {0x62u, 0xC0u},
- {0x64u, 0x40u},
- {0x65u, 0x01u},
- {0x66u, 0x10u},
- {0x67u, 0x11u},
- {0x68u, 0xC0u},
- {0x69u, 0x01u},
- {0x6Bu, 0x11u},
- {0x6Cu, 0x40u},
- {0x6Du, 0x01u},
- {0x6Eu, 0x40u},
- {0x6Fu, 0x01u},
- {0x81u, 0xC0u},
- {0x82u, 0x80u},
- {0x84u, 0x8Du},
- {0x88u, 0x32u},
- {0x89u, 0x10u},
- {0x8Au, 0x44u},
- {0x8Bu, 0x0Cu},
- {0x8Cu, 0x8Du},
- {0x8Du, 0x0Cu},
- {0x8Fu, 0x10u},
- {0x90u, 0x40u},
- {0x91u, 0x24u},
- {0x92u, 0x30u},
- {0x93u, 0x10u},
- {0x95u, 0x21u},
- {0x97u, 0x9Eu},
- {0x98u, 0x52u},
- {0x99u, 0x14u},
- {0x9Au, 0x28u},
- {0x9Bu, 0x08u},
- {0x9Cu, 0x02u},
- {0x9Du, 0x1Cu},
- {0x9Eu, 0x0Du},
- {0xA0u, 0x8Du},
- {0xA1u, 0x1Cu},
- {0xA4u, 0x8Du},
- {0xA5u, 0x08u},
- {0xA8u, 0x11u},
- {0xA9u, 0x70u},
- {0xAAu, 0x62u},
- {0xABu, 0x0Fu},
- {0xACu, 0x0Du},
- {0xADu, 0x11u},
- {0xAEu, 0x80u},
- {0xAFu, 0x62u},
- {0xB0u, 0x70u},
- {0xB1u, 0xC1u},
- {0xB3u, 0x0Fu},
- {0xB4u, 0x80u},
- {0xB6u, 0x0Fu},
- {0xB7u, 0x30u},
- {0xB9u, 0x02u},
- {0xBAu, 0x82u},
- {0xBBu, 0x80u},
- {0xBEu, 0x10u},
- {0xD8u, 0x04u},
- {0xD9u, 0x04u},
- {0xDCu, 0x11u},
- {0xDFu, 0x01u},
- {0x00u, 0x88u},
- {0x02u, 0x80u},
- {0x03u, 0x08u},
- {0x04u, 0x14u},
- {0x06u, 0x80u},
- {0x07u, 0x09u},
- {0x0Au, 0x86u},
- {0x0Du, 0x08u},
- {0x0Eu, 0x49u},
- {0x10u, 0x20u},
- {0x11u, 0x40u},
- {0x12u, 0x08u},
- {0x13u, 0x01u},
- {0x17u, 0x16u},
- {0x1Au, 0x82u},
- {0x1Bu, 0x11u},
- {0x1Cu, 0x34u},
- {0x1Du, 0x01u},
- {0x1Eu, 0x60u},
- {0x1Fu, 0x14u},
- {0x20u, 0x03u},
- {0x21u, 0x01u},
- {0x22u, 0x0Cu},
- {0x23u, 0x40u},
- {0x27u, 0x80u},
- {0x28u, 0x40u},
+ {0x5Au, 0x12u},
+ {0x5Bu, 0x80u},
+ {0x5Eu, 0x80u},
+ {0x62u, 0x81u},
+ {0x64u, 0x02u},
+ {0x7Eu, 0x08u},
+ {0x7Fu, 0x08u},
+ {0x81u, 0x80u},
+ {0x86u, 0x40u},
+ {0x8Au, 0x04u},
+ {0x8Cu, 0x04u},
+ {0x91u, 0x61u},
+ {0x92u, 0x28u},
+ {0x93u, 0x46u},
+ {0x94u, 0x24u},
+ {0x96u, 0xC0u},
+ {0x98u, 0x41u},
+ {0x99u, 0x42u},
+ {0x9Au, 0x40u},
+ {0x9Fu, 0x20u},
+ {0xA0u, 0x20u},
+ {0xA1u, 0x04u},
+ {0xA2u, 0x01u},
+ {0xA4u, 0x40u},
+ {0xA5u, 0x02u},
+ {0xA6u, 0x28u},
+ {0xA7u, 0x08u},
+ {0xA8u, 0x10u},
+ {0xA9u, 0x20u},
+ {0xAFu, 0x50u},
+ {0xB0u, 0x48u},
+ {0xB1u, 0x08u},
+ {0xB3u, 0x02u},
+ {0xC0u, 0xE9u},
+ {0xC2u, 0xDFu},
+ {0xC4u, 0xDFu},
+ {0xCAu, 0x0Cu},
+ {0xCCu, 0xE7u},
+ {0xCEu, 0x3Au},
+ {0xD6u, 0x1Fu},
+ {0xD8u, 0x19u},
+ {0xE2u, 0x04u},
+ {0xE4u, 0x40u},
+ {0xE8u, 0x0Cu},
+ {0xEAu, 0x01u},
+ {0xECu, 0x02u},
+ {0xEEu, 0x01u},
+ {0x00u, 0x11u},
+ {0x02u, 0x22u},
+ {0x03u, 0x0Cu},
+ {0x06u, 0xFFu},
+ {0x07u, 0x10u},
+ {0x08u, 0x0Fu},
+ {0x09u, 0x01u},
+ {0x0Au, 0xF0u},
+ {0x0Cu, 0x21u},
+ {0x0Eu, 0x12u},
+ {0x0Fu, 0x10u},
+ {0x12u, 0xFFu},
+ {0x13u, 0x02u},
+ {0x14u, 0x84u},
+ {0x15u, 0x10u},
+ {0x16u, 0x48u},
+ {0x17u, 0x08u},
+ {0x18u, 0xFFu},
+ {0x19u, 0x01u},
+ {0x20u, 0x33u},
+ {0x22u, 0xCCu},
+ {0x24u, 0x44u},
+ {0x25u, 0x01u},
+ {0x26u, 0x88u},
{0x29u, 0x10u},
- {0x2Au, 0x44u},
- {0x30u, 0x22u},
- {0x33u, 0x48u},
- {0x39u, 0x52u},
- {0x3Cu, 0x20u},
+ {0x2Bu, 0x04u},
+ {0x2Du, 0x01u},
+ {0x31u, 0x1Cu},
+ {0x32u, 0xFFu},
+ {0x33u, 0x02u},
+ {0x35u, 0x01u},
+ {0x3Eu, 0x04u},
{0x3Fu, 0x10u},
- {0x45u, 0x2Au},
- {0x48u, 0x03u},
- {0x4Du, 0x02u},
- {0x4Eu, 0x02u},
- {0x4Fu, 0x14u},
- {0x55u, 0x04u},
- {0x56u, 0xA8u},
- {0x67u, 0x20u},
- {0x6Du, 0xA1u},
- {0x6Eu, 0x01u},
- {0x6Fu, 0x15u},
- {0x75u, 0x80u},
- {0x76u, 0x01u},
- {0x77u, 0x02u},
- {0x8Du, 0x40u},
- {0x90u, 0x02u},
- {0x91u, 0x80u},
- {0x94u, 0x10u},
- {0x95u, 0x01u},
- {0x96u, 0x41u},
- {0x97u, 0x0Cu},
- {0x98u, 0x08u},
- {0x9Au, 0x02u},
- {0x9Cu, 0x02u},
- {0x9Du, 0x81u},
- {0x9Eu, 0x99u},
- {0x9Fu, 0x15u},
- {0xA0u, 0x80u},
- {0xA1u, 0x28u},
- {0xA2u, 0x04u},
- {0xA4u, 0x10u},
- {0xA5u, 0x54u},
- {0xA6u, 0x81u},
- {0xA7u, 0x10u},
- {0xAAu, 0x80u},
- {0xABu, 0x20u},
- {0xACu, 0x44u},
- {0xADu, 0x10u},
- {0xAFu, 0x08u},
- {0xB2u, 0x08u},
- {0xC0u, 0xFFu},
- {0xC2u, 0xFBu},
- {0xC4u, 0x7Fu},
- {0xCAu, 0x0Fu},
- {0xCCu, 0x0Fu},
- {0xCEu, 0x0Du},
- {0xD0u, 0xE0u},
- {0xD2u, 0x30u},
- {0xD8u, 0x40u},
- {0xE0u, 0x02u},
- {0xE2u, 0x08u},
- {0xE8u, 0x80u},
- {0xEAu, 0x0Au},
- {0xEEu, 0x02u},
- {0x00u, 0x02u},
- {0x02u, 0x01u},
- {0x05u, 0xFFu},
- {0x09u, 0x55u},
- {0x0Bu, 0xAAu},
- {0x0Cu, 0x02u},
- {0x0Eu, 0x11u},
- {0x0Fu, 0xFFu},
- {0x11u, 0x69u},
- {0x13u, 0x96u},
- {0x14u, 0x02u},
- {0x16u, 0x09u},
- {0x18u, 0x02u},
- {0x1Au, 0x05u},
- {0x1Cu, 0x01u},
- {0x1Du, 0x0Fu},
- {0x1Eu, 0x02u},
- {0x1Fu, 0xF0u},
- {0x23u, 0xFFu},
- {0x25u, 0xFFu},
- {0x2Bu, 0xFFu},
- {0x2Du, 0x33u},
- {0x2Fu, 0xCCu},
- {0x30u, 0x04u},
- {0x31u, 0xFFu},
- {0x32u, 0x10u},
- {0x34u, 0x08u},
- {0x36u, 0x03u},
- {0x3Au, 0x80u},
- {0x3Bu, 0x02u},
- {0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x22u},
- {0x5Du, 0x90u},
+ {0x5Cu, 0x20u},
{0x5Fu, 0x01u},
- {0x80u, 0x0Fu},
- {0x81u, 0x96u},
- {0x82u, 0xF0u},
- {0x83u, 0x69u},
- {0x84u, 0xFFu},
- {0x85u, 0xFFu},
- {0x89u, 0xFFu},
- {0x8Au, 0xFFu},
- {0x8Fu, 0xFFu},
- {0x92u, 0xFFu},
- {0x93u, 0xFFu},
- {0x94u, 0x55u},
- {0x96u, 0xAAu},
- {0x97u, 0xFFu},
- {0x98u, 0x33u},
- {0x99u, 0x55u},
- {0x9Au, 0xCCu},
- {0x9Bu, 0xAAu},
- {0x9Du, 0x0Fu},
- {0x9Eu, 0xFFu},
- {0x9Fu, 0xF0u},
- {0xA4u, 0xFFu},
- {0xACu, 0x69u},
- {0xADu, 0x33u},
- {0xAEu, 0x96u},
- {0xAFu, 0xCCu},
- {0xB6u, 0xFFu},
- {0xB7u, 0xFFu},
- {0xBAu, 0x80u},
- {0xBBu, 0x80u},
+ {0x80u, 0x01u},
+ {0x82u, 0x02u},
+ {0x84u, 0x04u},
+ {0x86u, 0x09u},
+ {0x89u, 0x01u},
+ {0x8Cu, 0x08u},
+ {0x8Du, 0x01u},
+ {0x8Eu, 0x04u},
+ {0x8Fu, 0x02u},
+ {0x91u, 0x02u},
+ {0x98u, 0x08u},
+ {0x9Au, 0x04u},
+ {0x9Cu, 0x08u},
+ {0x9Eu, 0x04u},
+ {0xA0u, 0x08u},
+ {0xA2u, 0x16u},
+ {0xA3u, 0x04u},
+ {0xAFu, 0x08u},
+ {0xB0u, 0x10u},
+ {0xB1u, 0x08u},
+ {0xB3u, 0x04u},
+ {0xB4u, 0x0Cu},
+ {0xB6u, 0x03u},
+ {0xB7u, 0x03u},
+ {0xBAu, 0x20u},
+ {0xBEu, 0x40u},
+ {0xBFu, 0x40u},
{0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDCu, 0x22u},
{0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x04u},
- {0x01u, 0x08u},
- {0x03u, 0x88u},
- {0x05u, 0x81u},
- {0x09u, 0x60u},
- {0x0Bu, 0x90u},
- {0x0Eu, 0x29u},
- {0x11u, 0x08u},
- {0x12u, 0x02u},
- {0x18u, 0x02u},
- {0x1Bu, 0x80u},
- {0x1Du, 0x01u},
- {0x1Eu, 0x29u},
- {0x21u, 0x40u},
- {0x22u, 0x40u},
- {0x26u, 0x01u},
- {0x27u, 0x40u},
+ {0x00u, 0x02u},
+ {0x03u, 0x22u},
+ {0x04u, 0x02u},
+ {0x05u, 0x28u},
+ {0x06u, 0x02u},
+ {0x08u, 0x40u},
+ {0x0Au, 0x0Au},
+ {0x0Eu, 0x80u},
+ {0x0Fu, 0x28u},
+ {0x13u, 0x01u},
+ {0x15u, 0x04u},
+ {0x17u, 0x01u},
+ {0x1Au, 0x01u},
+ {0x1Bu, 0xA3u},
+ {0x1Cu, 0x20u},
+ {0x22u, 0x85u},
+ {0x25u, 0x01u},
+ {0x27u, 0x14u},
+ {0x28u, 0x40u},
{0x2Bu, 0x01u},
- {0x2Du, 0x08u},
- {0x2Eu, 0x80u},
- {0x2Fu, 0x48u},
- {0x30u, 0x01u},
- {0x32u, 0x60u},
- {0x33u, 0x08u},
- {0x34u, 0x02u},
- {0x37u, 0x40u},
- {0x38u, 0x24u},
- {0x3Bu, 0x81u},
- {0x3Du, 0x88u},
- {0x3Eu, 0x20u},
- {0x58u, 0x50u},
- {0x5Bu, 0x09u},
- {0x5Fu, 0x80u},
- {0x62u, 0x2Au},
+ {0x2Eu, 0x40u},
+ {0x2Fu, 0x14u},
+ {0x30u, 0x02u},
+ {0x36u, 0x09u},
+ {0x37u, 0x20u},
+ {0x39u, 0x50u},
+ {0x3Cu, 0x28u},
+ {0x3Du, 0x82u},
+ {0x58u, 0x24u},
+ {0x5Au, 0x80u},
+ {0x5Bu, 0x02u},
+ {0x5Du, 0x08u},
+ {0x5Eu, 0x08u},
+ {0x60u, 0x84u},
+ {0x61u, 0x04u},
+ {0x62u, 0x01u},
{0x63u, 0x11u},
- {0x65u, 0x80u},
- {0x84u, 0x10u},
- {0x87u, 0x80u},
- {0x8Bu, 0x01u},
- {0x8Du, 0x02u},
- {0x90u, 0x64u},
- {0x91u, 0x41u},
- {0x92u, 0x02u},
- {0x93u, 0xC8u},
- {0x94u, 0x02u},
- {0x95u, 0x80u},
+ {0x68u, 0x01u},
+ {0x6Du, 0x40u},
+ {0x6Fu, 0x01u},
+ {0x80u, 0x04u},
+ {0x83u, 0x04u},
+ {0x84u, 0x04u},
+ {0x86u, 0x80u},
+ {0x8Au, 0x02u},
+ {0x8Bu, 0x02u},
+ {0x8Cu, 0x20u},
+ {0x91u, 0x10u},
+ {0x93u, 0x28u},
+ {0x94u, 0x20u},
+ {0x95u, 0x4Eu},
{0x96u, 0x01u},
- {0x97u, 0x02u},
- {0x98u, 0x01u},
- {0x99u, 0x30u},
- {0x9Au, 0xB0u},
- {0x9Eu, 0x40u},
- {0x9Fu, 0x04u},
- {0xA0u, 0x21u},
- {0xA1u, 0x64u},
- {0xA3u, 0x09u},
- {0xA4u, 0x40u},
- {0xA5u, 0x08u},
- {0xA6u, 0xA3u},
- {0xA7u, 0x20u},
- {0xA8u, 0x04u},
+ {0x98u, 0x12u},
+ {0x99u, 0x20u},
+ {0x9Au, 0x40u},
+ {0x9Cu, 0x80u},
+ {0x9Du, 0x55u},
+ {0x9Eu, 0x0Eu},
+ {0xA0u, 0x0Cu},
+ {0xA1u, 0x40u},
+ {0xA2u, 0x2Cu},
+ {0xA3u, 0x44u},
+ {0xA4u, 0x80u},
+ {0xA5u, 0x2Bu},
+ {0xA7u, 0x90u},
{0xAAu, 0x40u},
- {0xACu, 0x81u},
- {0xADu, 0x40u},
- {0xAFu, 0x0Au},
- {0xB1u, 0x40u},
- {0xB3u, 0x48u},
- {0xB5u, 0x80u},
- {0xB7u, 0x10u},
- {0xC0u, 0x9Eu},
- {0xC2u, 0xEFu},
- {0xC4u, 0x05u},
- {0xCAu, 0xF8u},
- {0xCCu, 0x9Fu},
- {0xCEu, 0x7Fu},
- {0xD6u, 0x1Fu},
- {0xD8u, 0x1Fu},
+ {0xABu, 0x42u},
+ {0xACu, 0x14u},
+ {0xB1u, 0x80u},
+ {0xB2u, 0x04u},
+ {0xB3u, 0x05u},
+ {0xC0u, 0xFDu},
+ {0xC2u, 0x73u},
+ {0xC4u, 0x38u},
+ {0xCAu, 0x79u},
+ {0xCCu, 0xE1u},
+ {0xCEu, 0xFCu},
+ {0xD6u, 0x0Fu},
+ {0xD8u, 0x0Fu},
+ {0xE0u, 0x81u},
{0xE2u, 0x08u},
- {0xE4u, 0x10u},
- {0xE6u, 0x02u},
- {0xE8u, 0x80u},
+ {0xE4u, 0x08u},
+ {0xEAu, 0x81u},
{0xECu, 0x80u},
- {0x04u, 0x02u},
- {0x08u, 0x02u},
- {0x0Cu, 0x02u},
- {0x12u, 0x04u},
- {0x15u, 0x01u},
- {0x17u, 0x02u},
+ {0xEEu, 0x20u},
+ {0x03u, 0x4Cu},
+ {0x05u, 0x01u},
+ {0x07u, 0x30u},
+ {0x08u, 0x05u},
+ {0x09u, 0x40u},
+ {0x0Au, 0x0Au},
+ {0x0Bu, 0x1Cu},
+ {0x0Du, 0x04u},
+ {0x0Fu, 0x08u},
+ {0x10u, 0x30u},
+ {0x12u, 0xC0u},
+ {0x13u, 0x0Cu},
+ {0x14u, 0x50u},
+ {0x15u, 0x4Cu},
+ {0x16u, 0xA0u},
+ {0x17u, 0x20u},
+ {0x18u, 0x60u},
{0x19u, 0x02u},
- {0x1Bu, 0x01u},
- {0x1Cu, 0x02u},
- {0x1Du, 0x02u},
- {0x1Fu, 0x01u},
- {0x25u, 0x02u},
- {0x27u, 0x05u},
- {0x2Cu, 0x01u},
- {0x2Du, 0x02u},
- {0x2Fu, 0x09u},
- {0x32u, 0x04u},
- {0x33u, 0x03u},
- {0x34u, 0x02u},
- {0x35u, 0x04u},
- {0x36u, 0x01u},
- {0x37u, 0x08u},
- {0x3Bu, 0x08u},
- {0x3Eu, 0x50u},
- {0x56u, 0x08u},
+ {0x1Au, 0x90u},
+ {0x1Du, 0x0Cu},
+ {0x20u, 0x03u},
+ {0x21u, 0x01u},
+ {0x22u, 0x0Cu},
+ {0x23u, 0x02u},
+ {0x24u, 0x06u},
+ {0x26u, 0x09u},
+ {0x2Bu, 0x40u},
+ {0x2Cu, 0x0Fu},
+ {0x2Du, 0x04u},
+ {0x2Eu, 0xF0u},
+ {0x2Fu, 0x08u},
+ {0x31u, 0x0Cu},
+ {0x34u, 0xFFu},
+ {0x35u, 0x70u},
+ {0x37u, 0x03u},
+ {0x3Bu, 0x02u},
+ {0x3Eu, 0x10u},
+ {0x3Fu, 0x40u},
{0x58u, 0x04u},
{0x59u, 0x04u},
- {0x5Bu, 0x04u},
- {0x5Cu, 0x22u},
- {0x5Du, 0x90u},
+ {0x5Cu, 0x20u},
{0x5Fu, 0x01u},
- {0x82u, 0x20u},
- {0x84u, 0xD8u},
- {0x85u, 0x0Fu},
- {0x86u, 0x03u},
- {0x87u, 0x80u},
- {0x88u, 0xC4u},
+ {0x80u, 0x01u},
+ {0x81u, 0x01u},
+ {0x82u, 0xF8u},
+ {0x83u, 0x02u},
+ {0x84u, 0x40u},
+ {0x85u, 0x01u},
+ {0x86u, 0x80u},
+ {0x87u, 0x02u},
+ {0x88u, 0x10u},
{0x89u, 0x04u},
+ {0x8Au, 0x20u},
{0x8Bu, 0x08u},
- {0x8Cu, 0x01u},
- {0x8Du, 0x50u},
- {0x8Eu, 0xCEu},
- {0x8Fu, 0x8Fu},
+ {0x8Cu, 0x10u},
+ {0x8Du, 0x20u},
+ {0x8Eu, 0x20u},
+ {0x8Fu, 0x1Fu},
{0x90u, 0x02u},
- {0x91u, 0x04u},
- {0x93u, 0x08u},
- {0x94u, 0x03u},
- {0x95u, 0x01u},
- {0x96u, 0xD4u},
- {0x97u, 0x02u},
- {0x99u, 0x01u},
+ {0x92u, 0xF0u},
+ {0x94u, 0x05u},
+ {0x95u, 0x04u},
+ {0x96u, 0xF8u},
+ {0x97u, 0x08u},
+ {0x99u, 0x0Fu},
{0x9Au, 0x01u},
- {0x9Bu, 0x02u},
- {0x9Cu, 0x40u},
- {0x9Eu, 0x80u},
+ {0x9Bu, 0x10u},
+ {0x9Cu, 0xF0u},
+ {0x9Du, 0x10u},
+ {0x9Eu, 0x08u},
+ {0x9Fu, 0x20u},
{0xA0u, 0x40u},
- {0xA1u, 0x20u},
+ {0xA1u, 0x0Fu},
{0xA2u, 0x80u},
- {0xA3u, 0x0Fu},
- {0xA6u, 0xDFu},
- {0xA7u, 0x10u},
- {0xA9u, 0x10u},
+ {0xA3u, 0x10u},
+ {0xA8u, 0xF4u},
+ {0xA9u, 0x20u},
{0xAAu, 0x08u},
- {0xABu, 0x8Fu},
- {0xADu, 0x4Fu},
- {0xAFu, 0x80u},
- {0xB0u, 0xC0u},
- {0xB2u, 0x1Fu},
+ {0xABu, 0x1Fu},
+ {0xAFu, 0x1Fu},
+ {0xB1u, 0x30u},
+ {0xB2u, 0x0Fu},
{0xB3u, 0x03u},
+ {0xB4u, 0x30u},
{0xB5u, 0x0Cu},
- {0xB6u, 0x20u},
- {0xB7u, 0xF0u},
- {0xB9u, 0x80u},
- {0xBAu, 0x02u},
- {0xBBu, 0x28u},
- {0xD6u, 0x08u},
+ {0xB6u, 0xC0u},
+ {0xB8u, 0x08u},
+ {0xBAu, 0xA0u},
+ {0xBBu, 0x2Au},
+ {0xD4u, 0x40u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
{0xDCu, 0x22u},
- {0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x90u},
- {0x03u, 0x20u},
- {0x04u, 0x24u},
- {0x07u, 0x41u},
- {0x0Au, 0x80u},
- {0x0Bu, 0x02u},
- {0x0Cu, 0xA0u},
- {0x0Du, 0x01u},
- {0x0Eu, 0x14u},
- {0x10u, 0x02u},
+ {0x03u, 0x04u},
+ {0x04u, 0x02u},
+ {0x05u, 0x10u},
+ {0x06u, 0x20u},
+ {0x07u, 0x01u},
+ {0x08u, 0x01u},
+ {0x09u, 0x2Au},
+ {0x0Eu, 0x69u},
+ {0x11u, 0x43u},
+ {0x12u, 0x01u},
+ {0x13u, 0x04u},
+ {0x14u, 0x80u},
{0x15u, 0x20u},
- {0x16u, 0x40u},
- {0x17u, 0x08u},
- {0x19u, 0x08u},
- {0x1Bu, 0x50u},
- {0x1Cu, 0x02u},
- {0x1Eu, 0x10u},
- {0x1Fu, 0x0Au},
- {0x22u, 0x54u},
- {0x23u, 0x10u},
- {0x24u, 0x08u},
- {0x25u, 0x50u},
- {0x26u, 0x08u},
- {0x27u, 0x01u},
- {0x28u, 0x02u},
- {0x29u, 0x08u},
- {0x2Eu, 0x44u},
- {0x2Fu, 0x48u},
- {0x32u, 0x54u},
- {0x36u, 0x2Au},
- {0x3Du, 0xA8u},
- {0x58u, 0x10u},
- {0x59u, 0x40u},
- {0x5Du, 0x80u},
- {0x60u, 0x02u},
- {0x61u, 0x30u},
- {0x66u, 0x80u},
- {0x7Bu, 0x0Cu},
- {0x80u, 0x04u},
- {0x83u, 0x40u},
- {0x87u, 0x04u},
- {0x8Au, 0x01u},
- {0x8Du, 0x08u},
- {0x8Eu, 0x08u},
- {0x90u, 0x74u},
- {0x91u, 0x63u},
- {0x92u, 0x04u},
- {0x93u, 0x40u},
- {0x94u, 0x02u},
- {0x95u, 0x80u},
- {0x96u, 0x13u},
- {0x97u, 0x18u},
- {0x98u, 0x10u},
- {0x99u, 0x20u},
- {0x9Au, 0x30u},
- {0x9Bu, 0x40u},
- {0x9Cu, 0x01u},
- {0x9Eu, 0x80u},
- {0x9Fu, 0x05u},
- {0xA0u, 0x02u},
- {0xA1u, 0x04u},
- {0xA3u, 0x01u},
- {0xA4u, 0x01u},
- {0xA6u, 0x81u},
- {0xA7u, 0x04u},
- {0xABu, 0x68u},
- {0xACu, 0x04u},
- {0xADu, 0x82u},
- {0xAEu, 0x11u},
- {0xB0u, 0x50u},
- {0xB1u, 0x20u},
- {0xB7u, 0x20u},
- {0xC0u, 0xF7u},
- {0xC2u, 0xF9u},
- {0xC4u, 0x71u},
- {0xCAu, 0xFAu},
- {0xCCu, 0xEEu},
- {0xCEu, 0x70u},
- {0xD6u, 0x1Cu},
- {0xD8u, 0x1Cu},
- {0xE0u, 0x20u},
- {0xE2u, 0x02u},
- {0xE6u, 0x50u},
- {0xE8u, 0x42u},
- {0xECu, 0x01u},
- {0xEEu, 0x08u},
- {0x00u, 0x05u},
- {0x01u, 0x02u},
- {0x02u, 0x0Au},
- {0x03u, 0x01u},
- {0x08u, 0xA0u},
- {0x0Au, 0x4Fu},
- {0x0Du, 0x04u},
+ {0x18u, 0x08u},
+ {0x19u, 0x20u},
+ {0x1Cu, 0x30u},
+ {0x1Eu, 0x24u},
+ {0x1Fu, 0x44u},
+ {0x20u, 0x82u},
+ {0x23u, 0x44u},
+ {0x25u, 0x14u},
+ {0x27u, 0x48u},
+ {0x29u, 0x40u},
+ {0x2Au, 0x11u},
+ {0x2Fu, 0x86u},
+ {0x31u, 0x20u},
+ {0x32u, 0x08u},
+ {0x33u, 0x82u},
+ {0x34u, 0x20u},
+ {0x35u, 0x04u},
+ {0x37u, 0x40u},
+ {0x38u, 0x12u},
+ {0x3Bu, 0x44u},
+ {0x3Du, 0xA8u},
+ {0x3Fu, 0x01u},
+ {0x64u, 0x04u},
+ {0x65u, 0x80u},
+ {0x67u, 0x10u},
+ {0x78u, 0x20u},
+ {0x79u, 0x20u},
+ {0x7Au, 0x08u},
+ {0x81u, 0x04u},
+ {0x84u, 0x01u},
+ {0x86u, 0x20u},
+ {0x87u, 0x40u},
+ {0x8Fu, 0x01u},
+ {0x90u, 0x02u},
+ {0x91u, 0x10u},
+ {0x93u, 0x31u},
+ {0x94u, 0x28u},
+ {0x95u, 0x4Fu},
+ {0x97u, 0x02u},
+ {0x98u, 0x02u},
+ {0x9Au, 0x50u},
+ {0x9Bu, 0x04u},
+ {0x9Cu, 0x21u},
+ {0x9Du, 0x01u},
+ {0x9Eu, 0x0Eu},
+ {0x9Fu, 0x08u},
+ {0xA0u, 0x0Cu},
+ {0xA1u, 0x40u},
+ {0xA2u, 0x2Cu},
+ {0xA3u, 0x44u},
+ {0xA4u, 0xD0u},
+ {0xA5u, 0x08u},
+ {0xA6u, 0x10u},
+ {0xA7u, 0x92u},
+ {0xABu, 0x08u},
+ {0xAEu, 0x40u},
+ {0xAFu, 0x20u},
+ {0xB1u, 0x10u},
+ {0xB2u, 0x10u},
+ {0xB3u, 0x10u},
+ {0xB5u, 0x30u},
+ {0xC0u, 0xF2u},
+ {0xC2u, 0xFEu},
+ {0xC4u, 0x5Du},
+ {0xCAu, 0xBDu},
+ {0xCCu, 0x7Fu},
+ {0xCEu, 0xFFu},
+ {0xD8u, 0x70u},
+ {0xE0u, 0x40u},
+ {0xE4u, 0x08u},
+ {0xE8u, 0x82u},
+ {0xECu, 0xA0u},
+ {0xEEu, 0x40u},
+ {0x00u, 0x03u},
+ {0x01u, 0x20u},
+ {0x02u, 0x0Cu},
+ {0x03u, 0x40u},
+ {0x06u, 0x80u},
+ {0x08u, 0x06u},
+ {0x09u, 0x01u},
+ {0x0Au, 0x09u},
+ {0x0Bu, 0x6Eu},
+ {0x0Du, 0x03u},
{0x0Eu, 0x70u},
- {0x0Fu, 0x08u},
- {0x14u, 0xC0u},
- {0x15u, 0x02u},
- {0x16u, 0x1Fu},
- {0x17u, 0x01u},
+ {0x0Fu, 0x74u},
+ {0x10u, 0xC0u},
+ {0x11u, 0x20u},
+ {0x12u, 0x1Fu},
+ {0x13u, 0x40u},
+ {0x14u, 0x90u},
+ {0x15u, 0x78u},
+ {0x16u, 0x2Fu},
+ {0x17u, 0x03u},
{0x18u, 0x0Fu},
- {0x19u, 0x01u},
- {0x1Bu, 0x06u},
- {0x1Cu, 0x03u},
- {0x1Du, 0x02u},
- {0x1Eu, 0x0Cu},
- {0x1Fu, 0x01u},
- {0x20u, 0x90u},
- {0x22u, 0x2Fu},
- {0x2Au, 0x80u},
- {0x2Cu, 0x06u},
- {0x2Du, 0x02u},
- {0x2Eu, 0x09u},
- {0x2Fu, 0x19u},
+ {0x19u, 0x02u},
+ {0x20u, 0x05u},
+ {0x21u, 0x64u},
+ {0x22u, 0x0Au},
+ {0x24u, 0xA0u},
+ {0x25u, 0x80u},
+ {0x26u, 0x4Fu},
+ {0x27u, 0x01u},
+ {0x2Bu, 0x08u},
+ {0x2Fu, 0x7Fu},
{0x30u, 0x7Fu},
- {0x31u, 0x10u},
- {0x33u, 0x0Cu},
- {0x35u, 0x03u},
+ {0x31u, 0x60u},
+ {0x35u, 0x80u},
{0x36u, 0x80u},
- {0x3Bu, 0x20u},
+ {0x37u, 0x1Fu},
+ {0x3Bu, 0x02u},
{0x3Eu, 0x40u},
- {0x3Fu, 0x04u},
- {0x56u, 0x08u},
+ {0x3Fu, 0x10u},
+ {0x54u, 0x01u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
{0x5Cu, 0x22u},
- {0x5Du, 0x90u},
+ {0x5Du, 0x20u},
{0x5Fu, 0x01u},
- {0x80u, 0x06u},
- {0x82u, 0x09u},
- {0x84u, 0x0Fu},
- {0x86u, 0xF0u},
- {0x88u, 0x05u},
- {0x89u, 0x04u},
- {0x8Au, 0x0Au},
- {0x8Cu, 0x30u},
- {0x8Du, 0x40u},
- {0x8Eu, 0xC0u},
- {0x91u, 0x10u},
- {0x94u, 0x60u},
- {0x95u, 0x08u},
- {0x96u, 0x90u},
- {0x99u, 0x02u},
- {0x9Du, 0x01u},
- {0xA0u, 0x50u},
- {0xA1u, 0x20u},
- {0xA2u, 0xA0u},
- {0xA4u, 0x03u},
- {0xA5u, 0x55u},
- {0xA6u, 0x0Cu},
- {0xA7u, 0xAAu},
- {0xADu, 0x80u},
- {0xB1u, 0x30u},
- {0xB3u, 0x03u},
- {0xB4u, 0xFFu},
- {0xB5u, 0x0Cu},
- {0xB7u, 0xC0u},
- {0xBEu, 0x10u},
- {0xBFu, 0x55u},
+ {0x81u, 0x10u},
+ {0x88u, 0x40u},
+ {0x8Cu, 0x53u},
+ {0x8Du, 0x01u},
+ {0x8Eu, 0xACu},
+ {0x90u, 0x02u},
+ {0x91u, 0x15u},
+ {0x92u, 0x01u},
+ {0x93u, 0x2Au},
+ {0x94u, 0x80u},
+ {0x9Du, 0x02u},
+ {0xA0u, 0x08u},
+ {0xA1u, 0x04u},
+ {0xA2u, 0x04u},
+ {0xA5u, 0x08u},
+ {0xA8u, 0x24u},
+ {0xAAu, 0x08u},
+ {0xACu, 0x11u},
+ {0xADu, 0x20u},
+ {0xAEu, 0x02u},
+ {0xB0u, 0xC0u},
+ {0xB1u, 0x0Cu},
+ {0xB2u, 0x0Fu},
+ {0xB3u, 0x30u},
+ {0xB4u, 0x30u},
+ {0xB5u, 0x03u},
+ {0xBEu, 0x15u},
+ {0xBFu, 0x15u},
{0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
{0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x20u},
- {0x01u, 0x14u},
- {0x02u, 0x81u},
- {0x03u, 0x20u},
- {0x04u, 0x42u},
- {0x06u, 0x08u},
- {0x0Au, 0x20u},
- {0x0Eu, 0x16u},
- {0x10u, 0xA0u},
- {0x14u, 0x04u},
- {0x15u, 0x80u},
- {0x17u, 0x01u},
- {0x19u, 0x20u},
+ {0x01u, 0x40u},
+ {0x03u, 0x05u},
+ {0x04u, 0x60u},
+ {0x05u, 0x09u},
+ {0x09u, 0x08u},
+ {0x0Au, 0x80u},
+ {0x0Bu, 0x40u},
+ {0x0Eu, 0xA8u},
+ {0x10u, 0x80u},
+ {0x12u, 0x05u},
+ {0x14u, 0x20u},
+ {0x15u, 0x02u},
+ {0x18u, 0x80u},
+ {0x1Bu, 0x24u},
{0x1Cu, 0x40u},
- {0x1Fu, 0x40u},
- {0x21u, 0x22u},
- {0x22u, 0x44u},
- {0x24u, 0x20u},
- {0x25u, 0x04u},
- {0x26u, 0x24u},
- {0x27u, 0x60u},
- {0x2Au, 0x41u},
- {0x2Bu, 0x20u},
- {0x2Fu, 0x01u},
- {0x32u, 0x9Au},
- {0x35u, 0x10u},
- {0x36u, 0x20u},
- {0x37u, 0x44u},
- {0x39u, 0x50u},
- {0x3Cu, 0x06u},
- {0x3Eu, 0x48u},
- {0x58u, 0x40u},
- {0x5Eu, 0xA0u},
- {0x60u, 0x02u},
- {0x63u, 0x02u},
- {0x66u, 0x20u},
- {0x67u, 0x02u},
- {0x68u, 0x06u},
- {0x6Au, 0x04u},
- {0x6Eu, 0x40u},
- {0x7Du, 0x20u},
- {0x7Fu, 0x04u},
- {0x80u, 0xA0u},
- {0x82u, 0x0Au},
- {0x85u, 0x01u},
- {0x86u, 0x54u},
- {0x8Au, 0x40u},
- {0x8Bu, 0x40u},
- {0x8Eu, 0x51u},
- {0x90u, 0x14u},
- {0x91u, 0x62u},
- {0x93u, 0x40u},
- {0x94u, 0x20u},
- {0x95u, 0x04u},
- {0x96u, 0x06u},
- {0x97u, 0x10u},
- {0x98u, 0x04u},
- {0x9Cu, 0x03u},
- {0x9Du, 0xB0u},
- {0x9Eu, 0xF0u},
- {0x9Fu, 0x08u},
- {0xA0u, 0x30u},
- {0xA5u, 0x10u},
- {0xA6u, 0x04u},
- {0xA7u, 0x44u},
- {0xA8u, 0x04u},
- {0xA9u, 0x11u},
- {0xABu, 0x01u},
- {0xACu, 0x84u},
- {0xB0u, 0x80u},
- {0xB1u, 0x01u},
- {0xB2u, 0x14u},
- {0xB5u, 0x02u},
- {0xC0u, 0xDFu},
- {0xC2u, 0xE4u},
- {0xC4u, 0xDCu},
- {0xCAu, 0x1Bu},
- {0xCCu, 0x7Fu},
- {0xCEu, 0x9Cu},
- {0xD6u, 0x38u},
- {0xD8u, 0x38u},
- {0xE0u, 0x60u},
- {0xE4u, 0x48u},
- {0xE6u, 0x82u},
+ {0x1Du, 0x40u},
+ {0x22u, 0x01u},
+ {0x23u, 0x24u},
+ {0x24u, 0x02u},
+ {0x25u, 0x61u},
+ {0x26u, 0x42u},
+ {0x28u, 0x01u},
+ {0x2Au, 0x02u},
+ {0x2Bu, 0x10u},
+ {0x2Cu, 0x20u},
+ {0x2Fu, 0x86u},
+ {0x30u, 0x80u},
+ {0x33u, 0x01u},
+ {0x34u, 0x02u},
+ {0x35u, 0x20u},
+ {0x36u, 0x08u},
+ {0x39u, 0x01u},
+ {0x3Bu, 0x40u},
+ {0x3Cu, 0x20u},
+ {0x3Du, 0x82u},
+ {0x59u, 0x10u},
+ {0x5Bu, 0x40u},
+ {0x5Cu, 0x40u},
+ {0x62u, 0x60u},
+ {0x63u, 0x01u},
+ {0x82u, 0x02u},
+ {0x86u, 0x01u},
+ {0x87u, 0x24u},
+ {0x8Cu, 0x40u},
+ {0x8Eu, 0x01u},
+ {0x92u, 0x80u},
+ {0x93u, 0x28u},
+ {0x94u, 0x08u},
+ {0x95u, 0x4Cu},
+ {0x97u, 0x02u},
+ {0x98u, 0x02u},
+ {0x99u, 0x28u},
+ {0x9Bu, 0x44u},
+ {0x9Du, 0x40u},
+ {0x9Eu, 0x0Au},
+ {0xA0u, 0x2Cu},
+ {0xA2u, 0x0Cu},
+ {0xA3u, 0x40u},
+ {0xA4u, 0x50u},
+ {0xA5u, 0x40u},
+ {0xA6u, 0x20u},
+ {0xA7u, 0x96u},
+ {0xAAu, 0x40u},
+ {0xABu, 0x40u},
+ {0xAEu, 0x09u},
+ {0xAFu, 0x01u},
+ {0xB0u, 0x04u},
+ {0xB3u, 0x0Cu},
+ {0xB7u, 0x40u},
+ {0xC0u, 0xF3u},
+ {0xC2u, 0x7Cu},
+ {0xC4u, 0x3Bu},
+ {0xCAu, 0xFBu},
+ {0xCCu, 0xE9u},
+ {0xCEu, 0xB9u},
+ {0xD6u, 0x1Cu},
+ {0xD8u, 0x0Cu},
+ {0xE0u, 0x02u},
+ {0xE2u, 0x04u},
+ {0xE4u, 0x4Au},
+ {0xE6u, 0x20u},
{0xE8u, 0xA0u},
- {0xECu, 0x10u},
- {0xEEu, 0x20u},
- {0x04u, 0x21u},
- {0x05u, 0x24u},
- {0x06u, 0x12u},
- {0x07u, 0x12u},
- {0x08u, 0x0Fu},
- {0x0Au, 0xF0u},
- {0x0Bu, 0x04u},
- {0x0Cu, 0x11u},
- {0x0Eu, 0x22u},
- {0x0Fu, 0x20u},
- {0x12u, 0xFFu},
- {0x17u, 0x18u},
- {0x1Au, 0xFFu},
- {0x1Bu, 0x03u},
- {0x1Cu, 0xFFu},
- {0x20u, 0x44u},
- {0x22u, 0x88u},
- {0x24u, 0x33u},
- {0x26u, 0xCCu},
- {0x28u, 0x84u},
- {0x2Au, 0x48u},
- {0x2Bu, 0x24u},
- {0x2Du, 0x24u},
- {0x2Fu, 0x09u},
- {0x32u, 0xFFu},
- {0x33u, 0x38u},
- {0x35u, 0x07u},
- {0x3Eu, 0x04u},
+ {0xEAu, 0x04u},
+ {0xECu, 0xC2u},
+ {0xEEu, 0x09u},
+ {0x04u, 0x80u},
+ {0x05u, 0x02u},
+ {0x07u, 0x01u},
+ {0x08u, 0x24u},
+ {0x0Au, 0x09u},
+ {0x0Cu, 0x40u},
+ {0x0Eu, 0x80u},
+ {0x12u, 0x18u},
+ {0x15u, 0x06u},
+ {0x1Au, 0x03u},
+ {0x1Cu, 0x40u},
+ {0x21u, 0x01u},
+ {0x22u, 0x20u},
+ {0x23u, 0x04u},
+ {0x25u, 0x01u},
+ {0x26u, 0x04u},
+ {0x27u, 0x02u},
+ {0x28u, 0x24u},
+ {0x2Au, 0x12u},
+ {0x2Eu, 0x24u},
+ {0x30u, 0x38u},
+ {0x33u, 0x07u},
+ {0x34u, 0x07u},
+ {0x36u, 0xC0u},
+ {0x39u, 0x08u},
+ {0x3Eu, 0x40u},
+ {0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
- {0x5Cu, 0x20u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x02u},
+ {0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x80u, 0x73u},
- {0x82u, 0x08u},
- {0x84u, 0x20u},
+ {0x81u, 0x40u},
+ {0x83u, 0x80u},
+ {0x84u, 0x0Fu},
{0x85u, 0xCAu},
- {0x86u, 0x40u},
+ {0x86u, 0xF0u},
{0x87u, 0x15u},
- {0x88u, 0x63u},
- {0x89u, 0x40u},
- {0x8Bu, 0x80u},
- {0x8Fu, 0xFFu},
- {0x90u, 0x10u},
- {0x91u, 0x40u},
- {0x92u, 0x67u},
- {0x93u, 0x80u},
- {0x95u, 0xE0u},
- {0x96u, 0x10u},
- {0x99u, 0x11u},
- {0x9Au, 0x73u},
- {0x9Bu, 0xECu},
- {0x9Eu, 0x0Cu},
- {0x9Fu, 0x10u},
- {0xA0u, 0x20u},
- {0xA1u, 0x06u},
- {0xA2u, 0x40u},
- {0xA5u, 0x01u},
- {0xA6u, 0x63u},
- {0xA8u, 0x01u},
- {0xAAu, 0x02u},
- {0xACu, 0x01u},
- {0xADu, 0x0Bu},
- {0xAEu, 0x02u},
- {0xAFu, 0xF4u},
- {0xB2u, 0x60u},
- {0xB3u, 0xC0u},
- {0xB4u, 0x03u},
- {0xB5u, 0x3Fu},
- {0xB6u, 0x1Cu},
- {0xBAu, 0x28u},
- {0xBBu, 0x08u},
+ {0x89u, 0x0Bu},
+ {0x8Au, 0xFFu},
+ {0x8Bu, 0xF4u},
+ {0x8Cu, 0x21u},
+ {0x8Du, 0x11u},
+ {0x8Eu, 0x12u},
+ {0x8Fu, 0xECu},
+ {0x94u, 0x84u},
+ {0x95u, 0x01u},
+ {0x96u, 0x48u},
+ {0x99u, 0x40u},
+ {0x9Au, 0xFFu},
+ {0x9Bu, 0x80u},
+ {0x9Cu, 0xFFu},
+ {0xA0u, 0x11u},
+ {0xA1u, 0xE0u},
+ {0xA2u, 0x22u},
+ {0xA4u, 0x44u},
+ {0xA5u, 0x06u},
+ {0xA6u, 0x88u},
+ {0xABu, 0x10u},
+ {0xACu, 0x33u},
+ {0xAEu, 0xCCu},
+ {0xAFu, 0xFFu},
+ {0xB3u, 0x3Fu},
+ {0xB4u, 0xFFu},
+ {0xB7u, 0xC0u},
+ {0xBBu, 0x80u},
+ {0xBEu, 0x10u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x22u},
+ {0xDCu, 0x20u},
{0xDFu, 0x01u},
- {0x01u, 0x60u},
- {0x02u, 0x10u},
- {0x04u, 0x20u},
- {0x05u, 0x05u},
- {0x09u, 0x02u},
- {0x0Au, 0x06u},
- {0x0Cu, 0x11u},
- {0x0Eu, 0x22u},
- {0x0Fu, 0x08u},
- {0x11u, 0x24u},
- {0x12u, 0x40u},
- {0x14u, 0x02u},
- {0x15u, 0x10u},
- {0x16u, 0x80u},
- {0x17u, 0x08u},
- {0x18u, 0x10u},
- {0x1Du, 0x04u},
- {0x1Eu, 0x02u},
- {0x1Fu, 0x24u},
- {0x20u, 0x20u},
- {0x22u, 0x14u},
- {0x24u, 0x04u},
- {0x25u, 0x08u},
- {0x28u, 0x01u},
- {0x29u, 0x02u},
- {0x2Bu, 0x44u},
- {0x2Cu, 0x81u},
- {0x2Eu, 0x04u},
- {0x30u, 0x20u},
- {0x32u, 0x14u},
- {0x34u, 0x90u},
- {0x36u, 0x06u},
- {0x38u, 0x84u},
- {0x3Bu, 0x20u},
- {0x3Cu, 0x04u},
- {0x3Eu, 0x20u},
- {0x3Fu, 0x80u},
- {0x5Du, 0x8Au},
- {0x5Fu, 0x10u},
- {0x67u, 0x02u},
- {0x79u, 0x40u},
- {0x7Au, 0x01u},
- {0x80u, 0x40u},
- {0x81u, 0x08u},
- {0x85u, 0x10u},
- {0x87u, 0x14u},
- {0x89u, 0x18u},
- {0x8Au, 0x02u},
- {0x8Bu, 0x60u},
- {0xC0u, 0x77u},
- {0xC2u, 0xFBu},
- {0xC4u, 0xFEu},
- {0xCAu, 0xDCu},
- {0xCCu, 0xF6u},
- {0xCEu, 0x7Eu},
- {0xD6u, 0xF0u},
- {0xD8u, 0x10u},
- {0xE0u, 0x20u},
- {0xE2u, 0x80u},
- {0xE6u, 0x20u},
- {0x83u, 0x01u},
- {0x87u, 0x12u},
- {0x88u, 0x06u},
- {0x89u, 0xE0u},
- {0x93u, 0xECu},
- {0x94u, 0x32u},
- {0x95u, 0x04u},
- {0x96u, 0x01u},
- {0x97u, 0x43u},
- {0x98u, 0x01u},
- {0x99u, 0x88u},
- {0x9Au, 0x2Cu},
- {0x9Bu, 0x03u},
- {0x9Eu, 0x08u},
- {0xA8u, 0x01u},
- {0xA9u, 0x21u},
- {0xAAu, 0x1Au},
- {0xABu, 0x02u},
- {0xB1u, 0x10u},
- {0xB2u, 0x07u},
- {0xB5u, 0xE0u},
- {0xB6u, 0x38u},
- {0xB7u, 0x0Fu},
- {0xB8u, 0x08u},
- {0xBFu, 0x10u},
+ {0x00u, 0x20u},
+ {0x01u, 0x44u},
+ {0x04u, 0x28u},
+ {0x06u, 0x02u},
+ {0x08u, 0x40u},
+ {0x0Au, 0x84u},
+ {0x0Bu, 0x02u},
+ {0x0Fu, 0x2Au},
+ {0x11u, 0x80u},
+ {0x12u, 0x08u},
+ {0x13u, 0x09u},
+ {0x14u, 0x40u},
+ {0x15u, 0x44u},
+ {0x1Au, 0x86u},
+ {0x1Fu, 0x10u},
+ {0x21u, 0x08u},
+ {0x24u, 0x03u},
+ {0x25u, 0x04u},
+ {0x26u, 0x08u},
+ {0x2Au, 0x08u},
+ {0x2Bu, 0x40u},
+ {0x2Du, 0x28u},
+ {0x2Fu, 0xA2u},
+ {0x30u, 0x08u},
+ {0x31u, 0x08u},
+ {0x36u, 0x24u},
+ {0x39u, 0x08u},
+ {0x3Cu, 0x21u},
+ {0x3Du, 0x88u},
+ {0x5Au, 0x44u},
+ {0x5Bu, 0x04u},
+ {0x5Du, 0x88u},
+ {0x5Eu, 0x20u},
+ {0x5Fu, 0x02u},
+ {0x60u, 0x02u},
+ {0x65u, 0x40u},
+ {0x6Cu, 0x32u},
+ {0x6Eu, 0x18u},
+ {0x80u, 0x01u},
+ {0x81u, 0xA0u},
+ {0x83u, 0x03u},
+ {0x84u, 0x42u},
+ {0x86u, 0x10u},
+ {0x8Bu, 0x20u},
+ {0x8Eu, 0x18u},
+ {0xC0u, 0xE7u},
+ {0xC2u, 0xEBu},
+ {0xC4u, 0xBFu},
+ {0xCAu, 0xF3u},
+ {0xCCu, 0x62u},
+ {0xCEu, 0xF2u},
+ {0xD6u, 0xF8u},
+ {0xD8u, 0x18u},
+ {0xE0u, 0x80u},
+ {0xE6u, 0x50u},
+ {0x80u, 0x10u},
+ {0x84u, 0x01u},
+ {0x88u, 0xA2u},
+ {0x8Au, 0x08u},
+ {0x8Cu, 0x07u},
+ {0x8Eu, 0xD8u},
+ {0x90u, 0x01u},
+ {0x96u, 0x40u},
+ {0x99u, 0x01u},
+ {0x9Cu, 0x08u},
+ {0x9Eu, 0x61u},
+ {0xA0u, 0x01u},
+ {0xA4u, 0x01u},
+ {0xA5u, 0x01u},
+ {0xA8u, 0x04u},
+ {0xACu, 0x01u},
+ {0xB2u, 0xE0u},
+ {0xB3u, 0x01u},
+ {0xB4u, 0x3Fu},
+ {0xB8u, 0x20u},
+ {0xB9u, 0x08u},
+ {0xBEu, 0x10u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
+ {0xDCu, 0x11u},
{0xDFu, 0x01u},
- {0x00u, 0x80u},
+ {0x00u, 0x04u},
{0x01u, 0x01u},
- {0x02u, 0x04u},
- {0x03u, 0x20u},
- {0x04u, 0x10u},
- {0x08u, 0x02u},
- {0x0Au, 0x04u},
+ {0x03u, 0x01u},
+ {0x04u, 0x88u},
+ {0x05u, 0x11u},
+ {0x07u, 0x20u},
+ {0x08u, 0x08u},
+ {0x0Au, 0x84u},
{0x0Bu, 0x01u},
- {0x0Cu, 0x40u},
- {0x0Eu, 0x2Au},
- {0x10u, 0x20u},
- {0x11u, 0x50u},
- {0x14u, 0x0Cu},
- {0x18u, 0x04u},
- {0x19u, 0x15u},
- {0x1Au, 0x04u},
- {0x1Bu, 0x0Au},
- {0x1Cu, 0x10u},
- {0x1Eu, 0x02u},
- {0x20u, 0x40u},
- {0x25u, 0x01u},
- {0x26u, 0x20u},
- {0x27u, 0x02u},
- {0x29u, 0x14u},
- {0x2Au, 0x02u},
- {0x2Bu, 0x20u},
- {0x2Cu, 0x04u},
- {0x30u, 0x20u},
- {0x32u, 0x04u},
- {0x33u, 0x41u},
- {0x36u, 0x14u},
- {0x37u, 0x02u},
- {0x38u, 0x81u},
- {0x39u, 0x18u},
- {0x3Cu, 0x10u},
- {0x3Du, 0x02u},
- {0x3Eu, 0x08u},
- {0x40u, 0x04u},
- {0x43u, 0x0Au},
+ {0x0Du, 0x41u},
+ {0x0Eu, 0x10u},
+ {0x0Fu, 0x02u},
+ {0x12u, 0x01u},
+ {0x13u, 0x28u},
+ {0x15u, 0x08u},
+ {0x16u, 0x02u},
+ {0x17u, 0x11u},
+ {0x18u, 0xC8u},
+ {0x1Au, 0x82u},
+ {0x1Bu, 0x08u},
+ {0x1Eu, 0x10u},
+ {0x1Fu, 0x10u},
+ {0x21u, 0x02u},
+ {0x27u, 0x10u},
+ {0x2Bu, 0x01u},
+ {0x2Fu, 0x10u},
+ {0x31u, 0x02u},
+ {0x36u, 0x10u},
+ {0x38u, 0x44u},
+ {0x40u, 0x40u},
+ {0x41u, 0x40u},
+ {0x43u, 0x08u},
{0x48u, 0x01u},
- {0x49u, 0x08u},
- {0x4Au, 0x88u},
- {0x50u, 0x40u},
- {0x52u, 0x54u},
- {0x53u, 0x80u},
- {0x5Cu, 0x03u},
- {0x63u, 0x02u},
- {0x68u, 0x64u},
- {0x69u, 0x50u},
- {0x6Bu, 0x41u},
+ {0x49u, 0x15u},
+ {0x4Au, 0x80u},
+ {0x51u, 0x28u},
+ {0x52u, 0x01u},
+ {0x61u, 0x02u},
+ {0x68u, 0x80u},
+ {0x69u, 0x0Bu},
+ {0x6Au, 0x4Cu},
+ {0x6Bu, 0x09u},
{0x72u, 0x02u},
{0x73u, 0x01u},
- {0x81u, 0x10u},
+ {0x80u, 0x40u},
{0x84u, 0x01u},
- {0x88u, 0x40u},
- {0x8Au, 0x20u},
- {0x8Cu, 0x10u},
- {0x90u, 0x01u},
- {0x91u, 0x09u},
- {0x92u, 0x08u},
- {0x94u, 0x44u},
- {0x95u, 0x50u},
- {0x96u, 0x04u},
+ {0x8Au, 0x80u},
+ {0x8Bu, 0x10u},
+ {0x8Eu, 0x10u},
+ {0x90u, 0x04u},
+ {0x93u, 0x10u},
+ {0x94u, 0xC8u},
+ {0x95u, 0x0Au},
+ {0x96u, 0x4Au},
{0x97u, 0x01u},
{0x98u, 0x08u},
- {0x9Au, 0x08u},
- {0x9Du, 0x19u},
- {0x9Eu, 0x54u},
- {0x9Fu, 0x40u},
- {0xA1u, 0x10u},
- {0xA2u, 0x1Cu},
+ {0x99u, 0x10u},
+ {0x9Du, 0x05u},
+ {0x9Eu, 0x03u},
+ {0x9Fu, 0x19u},
+ {0xA2u, 0x10u},
{0xA3u, 0x01u},
- {0xA4u, 0x64u},
- {0xA6u, 0x80u},
- {0xA7u, 0x88u},
- {0xA8u, 0x01u},
- {0xABu, 0x04u},
- {0xACu, 0x08u},
- {0xB2u, 0x20u},
- {0xB3u, 0x20u},
- {0xC0u, 0x4Fu},
- {0xC2u, 0xEBu},
- {0xC4u, 0x47u},
- {0xCAu, 0x27u},
- {0xCCu, 0xEFu},
- {0xCEu, 0xEFu},
- {0xD0u, 0x07u},
+ {0xA4u, 0x80u},
+ {0xA5u, 0x28u},
+ {0xA9u, 0x05u},
+ {0xACu, 0x80u},
+ {0xB0u, 0x08u},
+ {0xB1u, 0x10u},
+ {0xB2u, 0x08u},
+ {0xB3u, 0x41u},
+ {0xB6u, 0x01u},
+ {0xC0u, 0xFDu},
+ {0xC2u, 0xBFu},
+ {0xC4u, 0xF7u},
+ {0xCAu, 0x48u},
+ {0xCCu, 0x21u},
+ {0xCEu, 0x0Au},
+ {0xD0u, 0x0Bu},
{0xD2u, 0x0Cu},
- {0xD8u, 0x08u},
- {0xE2u, 0xB0u},
- {0xEAu, 0x02u},
- {0xECu, 0x04u},
- {0x02u, 0x10u},
- {0x04u, 0x02u},
- {0x06u, 0x0Du},
- {0x08u, 0x3Du},
- {0x0Cu, 0x0Du},
- {0x0Du, 0xE0u},
- {0x0Eu, 0x30u},
- {0x13u, 0x01u},
- {0x14u, 0x01u},
- {0x15u, 0x31u},
- {0x16u, 0x02u},
- {0x17u, 0x02u},
- {0x18u, 0x02u},
- {0x19u, 0x98u},
- {0x1Au, 0x04u},
- {0x1Bu, 0x03u},
- {0x1Cu, 0x3Du},
- {0x1Fu, 0xECu},
- {0x20u, 0x3Du},
- {0x23u, 0x02u},
- {0x24u, 0x02u},
- {0x26u, 0x08u},
- {0x28u, 0x3Du},
- {0x29u, 0x14u},
- {0x2Bu, 0x43u},
- {0x30u, 0x20u},
- {0x31u, 0x0Fu},
- {0x32u, 0x0Fu},
- {0x34u, 0x10u},
- {0x35u, 0xE0u},
- {0x36u, 0x20u},
- {0x37u, 0x10u},
- {0x3Au, 0x08u},
- {0x3Eu, 0x51u},
- {0x3Fu, 0x50u},
- {0x54u, 0x40u},
+ {0xD8u, 0x01u},
+ {0xE0u, 0x05u},
+ {0xE2u, 0x10u},
+ {0xE6u, 0x50u},
+ {0x02u, 0x9Fu},
+ {0x04u, 0x80u},
+ {0x05u, 0x02u},
+ {0x08u, 0xC0u},
+ {0x0Au, 0x08u},
+ {0x0Bu, 0x01u},
+ {0x0Cu, 0x1Fu},
+ {0x0Eu, 0x20u},
+ {0x10u, 0xC0u},
+ {0x12u, 0x02u},
+ {0x14u, 0x7Fu},
+ {0x16u, 0x80u},
+ {0x1Du, 0x04u},
+ {0x1Eu, 0xFFu},
+ {0x20u, 0x90u},
+ {0x22u, 0x40u},
+ {0x24u, 0xC0u},
+ {0x26u, 0x04u},
+ {0x2Au, 0x60u},
+ {0x2Cu, 0xC0u},
+ {0x2Eu, 0x01u},
+ {0x32u, 0xFFu},
+ {0x33u, 0x04u},
+ {0x35u, 0x01u},
+ {0x37u, 0x02u},
+ {0x39u, 0x02u},
+ {0x3Eu, 0x04u},
+ {0x3Fu, 0x45u},
{0x58u, 0x04u},
{0x59u, 0x04u},
- {0x5Bu, 0x04u},
- {0x5Cu, 0x10u},
+ {0x5Cu, 0x20u},
{0x5Fu, 0x01u},
- {0x80u, 0x01u},
- {0x84u, 0xA2u},
- {0x86u, 0x08u},
- {0x88u, 0x08u},
- {0x8Au, 0x61u},
- {0x8Cu, 0x01u},
- {0x8Du, 0x08u},
- {0x92u, 0x40u},
- {0x95u, 0x01u},
- {0x98u, 0x07u},
- {0x99u, 0x02u},
- {0x9Au, 0xD8u},
- {0x9Cu, 0x01u},
- {0x9Du, 0x10u},
- {0xA0u, 0x10u},
- {0xA1u, 0x20u},
- {0xA4u, 0x01u},
- {0xA5u, 0x08u},
- {0xA8u, 0x04u},
- {0xA9u, 0x11u},
- {0xABu, 0x22u},
- {0xACu, 0x01u},
- {0xAFu, 0x04u},
- {0xB0u, 0xE0u},
- {0xB1u, 0x04u},
- {0xB3u, 0x08u},
- {0xB4u, 0x3Fu},
- {0xB5u, 0x03u},
- {0xB6u, 0x08u},
+ {0x81u, 0x9Cu},
+ {0x84u, 0x01u},
+ {0x85u, 0x61u},
+ {0x86u, 0x5Eu},
+ {0x87u, 0x1Eu},
+ {0x88u, 0x39u},
+ {0x89u, 0x10u},
+ {0x8Au, 0x06u},
+ {0x8Bu, 0x8Cu},
+ {0x8Cu, 0x77u},
+ {0x8Du, 0x8Cu},
+ {0x8Eu, 0x08u},
+ {0x8Fu, 0x10u},
+ {0x90u, 0x46u},
+ {0x91u, 0xD1u},
+ {0x92u, 0x80u},
+ {0x93u, 0x22u},
+ {0x95u, 0x30u},
+ {0x96u, 0x80u},
+ {0x97u, 0x8Fu},
+ {0x98u, 0xC2u},
+ {0x99u, 0x94u},
+ {0x9Au, 0x04u},
+ {0x9Bu, 0x08u},
+ {0x9Cu, 0xC6u},
+ {0x9Du, 0xA4u},
+ {0x9Fu, 0x10u},
+ {0xA0u, 0xC6u},
+ {0xA1u, 0x08u},
+ {0xA3u, 0x40u},
+ {0xA4u, 0x80u},
+ {0xA6u, 0x46u},
+ {0xA8u, 0x42u},
+ {0xACu, 0x04u},
+ {0xADu, 0x9Cu},
+ {0xAEu, 0x20u},
+ {0xB0u, 0x0Fu},
+ {0xB1u, 0x0Fu},
+ {0xB2u, 0x80u},
+ {0xB3u, 0xC1u},
+ {0xB4u, 0x70u},
{0xB7u, 0x30u},
- {0xB8u, 0x20u},
- {0xB9u, 0x08u},
- {0xBEu, 0x50u},
- {0xBFu, 0x50u},
- {0xD4u, 0x09u},
+ {0xB8u, 0x02u},
+ {0xBAu, 0x30u},
+ {0xBBu, 0x8Cu},
+ {0xBEu, 0x04u},
+ {0xD4u, 0x40u},
{0xD6u, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x11u},
+ {0xDCu, 0x01u},
{0xDDu, 0x10u},
{0xDFu, 0x01u},
- {0x00u, 0x85u},
- {0x03u, 0x08u},
- {0x05u, 0x06u},
- {0x06u, 0x80u},
- {0x07u, 0x05u},
- {0x08u, 0x40u},
+ {0x00u, 0x44u},
+ {0x01u, 0x10u},
+ {0x04u, 0x88u},
+ {0x05u, 0x01u},
+ {0x06u, 0x08u},
+ {0x07u, 0x28u},
+ {0x08u, 0x04u},
+ {0x09u, 0x08u},
{0x0Au, 0x48u},
{0x0Bu, 0x01u},
- {0x0Du, 0x08u},
- {0x0Eu, 0x09u},
- {0x10u, 0x20u},
- {0x11u, 0x40u},
- {0x12u, 0x40u},
- {0x13u, 0x10u},
- {0x17u, 0x1Au},
- {0x19u, 0x80u},
- {0x1Au, 0x40u},
- {0x1Bu, 0x10u},
- {0x1Du, 0x06u},
- {0x1Eu, 0x02u},
- {0x1Fu, 0x10u},
- {0x21u, 0x44u},
- {0x22u, 0x22u},
- {0x23u, 0x10u},
- {0x25u, 0x90u},
- {0x27u, 0x80u},
- {0x2Au, 0x42u},
- {0x2Bu, 0x14u},
- {0x2Fu, 0x88u},
- {0x30u, 0x88u},
- {0x33u, 0x20u},
- {0x35u, 0x10u},
- {0x36u, 0x0Au},
+ {0x0Du, 0x01u},
+ {0x0Fu, 0x22u},
+ {0x10u, 0x80u},
+ {0x12u, 0x03u},
+ {0x13u, 0x28u},
+ {0x15u, 0x08u},
+ {0x16u, 0x22u},
+ {0x17u, 0x11u},
+ {0x18u, 0x14u},
+ {0x19u, 0x10u},
+ {0x1Bu, 0x11u},
+ {0x1Eu, 0x20u},
+ {0x20u, 0x80u},
+ {0x21u, 0x02u},
+ {0x22u, 0x48u},
+ {0x23u, 0x40u},
+ {0x25u, 0x05u},
+ {0x26u, 0x40u},
+ {0x27u, 0x04u},
+ {0x29u, 0x42u},
+ {0x30u, 0x20u},
+ {0x31u, 0x02u},
+ {0x32u, 0x48u},
{0x37u, 0x80u},
- {0x38u, 0x40u},
- {0x3Fu, 0x40u},
- {0x58u, 0x20u},
- {0x59u, 0x89u},
- {0x60u, 0x20u},
- {0x61u, 0x80u},
- {0x62u, 0x05u},
- {0x66u, 0xA0u},
- {0x67u, 0x20u},
- {0x80u, 0x02u},
- {0x81u, 0x40u},
- {0x82u, 0x40u},
- {0x85u, 0x01u},
- {0x86u, 0x08u},
- {0x8Eu, 0x01u},
- {0x90u, 0x03u},
- {0x92u, 0x09u},
- {0x93u, 0x40u},
- {0x95u, 0x50u},
- {0x96u, 0x04u},
- {0x97u, 0x01u},
- {0x98u, 0x08u},
- {0x99u, 0x02u},
- {0x9Au, 0x2Au},
- {0x9Bu, 0x1Fu},
- {0x9Cu, 0x42u},
- {0x9Du, 0x10u},
- {0x9Eu, 0x14u},
- {0x9Fu, 0x40u},
- {0xA0u, 0x80u},
- {0xA1u, 0x08u},
- {0xA2u, 0x1Cu},
- {0xA3u, 0x01u},
- {0xA4u, 0x64u},
+ {0x39u, 0x61u},
+ {0x3Bu, 0x04u},
+ {0x3Du, 0x20u},
+ {0x3Eu, 0x04u},
+ {0x60u, 0x90u},
+ {0x61u, 0x20u},
+ {0x62u, 0x40u},
+ {0x83u, 0x80u},
+ {0x84u, 0x05u},
+ {0x86u, 0x40u},
+ {0x8Au, 0x40u},
+ {0x8Cu, 0x10u},
+ {0x8Eu, 0x10u},
+ {0x8Fu, 0x10u},
+ {0x90u, 0x20u},
+ {0x91u, 0x61u},
+ {0x92u, 0x24u},
+ {0x93u, 0x14u},
+ {0x94u, 0x80u},
+ {0x95u, 0x02u},
+ {0x96u, 0x82u},
+ {0x98u, 0x01u},
+ {0x99u, 0x42u},
+ {0x9Du, 0x14u},
+ {0x9Eu, 0x2Au},
+ {0x9Fu, 0x05u},
+ {0xA0u, 0x20u},
+ {0xA1u, 0x10u},
+ {0xA2u, 0x01u},
+ {0xA4u, 0x40u},
{0xA5u, 0x02u},
- {0xA6u, 0x81u},
- {0xA7u, 0x08u},
- {0xAAu, 0x02u},
- {0xAEu, 0x48u},
- {0xAFu, 0x80u},
- {0xC0u, 0xFFu},
- {0xC2u, 0xEBu},
- {0xC4u, 0x7Fu},
- {0xCAu, 0xAFu},
- {0xCCu, 0xFEu},
- {0xCEu, 0x18u},
- {0xD6u, 0x0Fu},
- {0xD8u, 0x79u},
- {0xE0u, 0x01u},
- {0xE6u, 0x41u},
- {0xEEu, 0x08u},
- {0x00u, 0x33u},
- {0x02u, 0xCCu},
- {0x03u, 0x80u},
- {0x04u, 0x12u},
- {0x05u, 0x0Fu},
- {0x06u, 0x21u},
+ {0xA6u, 0x0Au},
+ {0xA7u, 0x01u},
+ {0xA8u, 0x08u},
+ {0xAAu, 0x12u},
+ {0xAEu, 0x10u},
+ {0xAFu, 0x04u},
+ {0xB6u, 0x01u},
+ {0xC0u, 0xF7u},
+ {0xC2u, 0xBFu},
+ {0xC4u, 0xFFu},
+ {0xCAu, 0x09u},
+ {0xCCu, 0x1Fu},
+ {0xCEu, 0x6Fu},
+ {0xD8u, 0x0Fu},
+ {0xE0u, 0x02u},
+ {0xE2u, 0x21u},
+ {0xECu, 0x01u},
+ {0xEEu, 0x4Cu},
+ {0x00u, 0x11u},
+ {0x02u, 0x22u},
+ {0x07u, 0xFFu},
{0x08u, 0x0Fu},
- {0x09u, 0x01u},
+ {0x09u, 0x48u},
{0x0Au, 0xF0u},
- {0x0Bu, 0x02u},
- {0x0Cu, 0x48u},
- {0x0Eu, 0x84u},
- {0x0Fu, 0x40u},
+ {0x0Bu, 0x84u},
+ {0x0Cu, 0x12u},
+ {0x0Du, 0x11u},
+ {0x0Eu, 0x21u},
+ {0x0Fu, 0x22u},
{0x10u, 0xFFu},
- {0x11u, 0x04u},
- {0x13u, 0x08u},
- {0x15u, 0x01u},
- {0x17u, 0x02u},
- {0x19u, 0x04u},
- {0x1Au, 0xFFu},
- {0x1Bu, 0x08u},
- {0x1Cu, 0xFFu},
- {0x1Fu, 0x30u},
- {0x20u, 0x44u},
- {0x22u, 0x88u},
- {0x23u, 0x0Fu},
- {0x25u, 0x4Fu},
- {0x27u, 0x20u},
- {0x2Bu, 0x4Fu},
- {0x2Cu, 0x11u},
- {0x2Du, 0x40u},
- {0x2Eu, 0x22u},
- {0x2Fu, 0x1Fu},
+ {0x11u, 0x33u},
+ {0x13u, 0xCCu},
+ {0x14u, 0x48u},
+ {0x16u, 0x84u},
+ {0x17u, 0xFFu},
+ {0x18u, 0xFFu},
+ {0x1Fu, 0xFFu},
+ {0x20u, 0x33u},
+ {0x21u, 0x12u},
+ {0x22u, 0xCCu},
+ {0x23u, 0x21u},
+ {0x24u, 0x44u},
+ {0x25u, 0x44u},
+ {0x26u, 0x88u},
+ {0x27u, 0x88u},
+ {0x29u, 0x0Fu},
+ {0x2Au, 0xFFu},
+ {0x2Bu, 0xF0u},
{0x30u, 0xFFu},
- {0x31u, 0x0Cu},
- {0x33u, 0x03u},
- {0x35u, 0x80u},
- {0x37u, 0x70u},
- {0x3Bu, 0x0Au},
+ {0x33u, 0xFFu},
{0x3Eu, 0x01u},
- {0x54u, 0x01u},
+ {0x3Fu, 0x04u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Bu, 0x04u},
+ {0x5Fu, 0x01u},
+ {0x80u, 0x55u},
+ {0x81u, 0x0Fu},
+ {0x82u, 0xAAu},
+ {0x83u, 0xF0u},
+ {0x84u, 0x33u},
+ {0x86u, 0xCCu},
+ {0x87u, 0xFFu},
+ {0x89u, 0x33u},
+ {0x8Bu, 0xCCu},
+ {0x8Eu, 0xFFu},
+ {0x90u, 0x0Fu},
+ {0x92u, 0xF0u},
+ {0x93u, 0xFFu},
+ {0x95u, 0xFFu},
+ {0x99u, 0x69u},
+ {0x9Au, 0xFFu},
+ {0x9Bu, 0x96u},
+ {0x9Cu, 0xFFu},
+ {0x9Du, 0xFFu},
+ {0xA6u, 0xFFu},
+ {0xA8u, 0xFFu},
+ {0xABu, 0xFFu},
+ {0xACu, 0x69u},
+ {0xADu, 0x55u},
+ {0xAEu, 0x96u},
+ {0xAFu, 0xAAu},
+ {0xB0u, 0xFFu},
+ {0xB1u, 0xFFu},
+ {0xBAu, 0x02u},
+ {0xBBu, 0x02u},
+ {0xD6u, 0x08u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDBu, 0x04u},
+ {0xDCu, 0x22u},
+ {0xDDu, 0x90u},
+ {0xDFu, 0x01u},
+ {0x00u, 0x04u},
+ {0x02u, 0x40u},
+ {0x03u, 0x02u},
+ {0x04u, 0x02u},
+ {0x05u, 0x22u},
+ {0x06u, 0x02u},
+ {0x0Au, 0x81u},
+ {0x0Bu, 0x08u},
+ {0x0Eu, 0x80u},
+ {0x0Fu, 0x28u},
+ {0x12u, 0x19u},
+ {0x14u, 0x04u},
+ {0x15u, 0x04u},
+ {0x17u, 0x01u},
+ {0x19u, 0x01u},
+ {0x1Au, 0x80u},
+ {0x1Eu, 0x40u},
+ {0x21u, 0x01u},
+ {0x27u, 0x20u},
+ {0x28u, 0x02u},
+ {0x2Au, 0x10u},
+ {0x2Du, 0x24u},
+ {0x2Eu, 0x02u},
+ {0x32u, 0x28u},
+ {0x33u, 0x82u},
+ {0x34u, 0x04u},
+ {0x36u, 0xC4u},
+ {0x37u, 0x01u},
+ {0x39u, 0x02u},
+ {0x3Bu, 0x18u},
+ {0x3Cu, 0x40u},
+ {0x3Du, 0x10u},
+ {0x3Fu, 0x28u},
+ {0x49u, 0x40u},
+ {0x4Bu, 0x80u},
+ {0x58u, 0x20u},
+ {0x5Bu, 0x40u},
+ {0x5Cu, 0x80u},
+ {0x5Du, 0x01u},
+ {0x5Eu, 0x24u},
+ {0x60u, 0x08u},
+ {0x61u, 0x50u},
+ {0x67u, 0x02u},
+ {0x80u, 0x08u},
+ {0x86u, 0x04u},
+ {0x8Cu, 0x40u},
+ {0x8Du, 0x06u},
+ {0x8Fu, 0x02u},
+ {0x90u, 0x04u},
+ {0x92u, 0x01u},
+ {0x93u, 0x1Au},
+ {0x94u, 0x22u},
+ {0x95u, 0x0Eu},
+ {0x96u, 0x40u},
+ {0x98u, 0x12u},
+ {0x99u, 0x20u},
+ {0x9Au, 0x53u},
+ {0x9Bu, 0x11u},
+ {0x9Du, 0x51u},
+ {0x9Eu, 0x0Cu},
+ {0x9Fu, 0x20u},
+ {0xA0u, 0x08u},
+ {0xA2u, 0xACu},
+ {0xA3u, 0xC4u},
+ {0xA4u, 0x82u},
+ {0xA5u, 0x2Au},
+ {0xA6u, 0x41u},
+ {0xA7u, 0x10u},
+ {0xAAu, 0x40u},
+ {0xABu, 0x80u},
+ {0xB1u, 0x40u},
+ {0xB2u, 0x10u},
+ {0xB7u, 0x21u},
+ {0xC0u, 0xDDu},
+ {0xC2u, 0x7Bu},
+ {0xC4u, 0x77u},
+ {0xCAu, 0xECu},
+ {0xCCu, 0xDFu},
+ {0xCEu, 0x77u},
+ {0xD6u, 0xFCu},
+ {0xD8u, 0x1Cu},
+ {0xE0u, 0x50u},
+ {0xE4u, 0x40u},
+ {0xEEu, 0x08u},
+ {0x00u, 0x96u},
+ {0x02u, 0x69u},
+ {0x05u, 0x88u},
+ {0x07u, 0x03u},
+ {0x08u, 0x0Fu},
+ {0x09u, 0x21u},
+ {0x0Au, 0xF0u},
+ {0x0Bu, 0x02u},
+ {0x0Eu, 0xFFu},
+ {0x10u, 0x55u},
+ {0x12u, 0xAAu},
+ {0x13u, 0x01u},
+ {0x14u, 0x33u},
+ {0x15u, 0xE0u},
+ {0x16u, 0xCCu},
+ {0x1Au, 0xFFu},
+ {0x1Bu, 0xECu},
+ {0x1Cu, 0xFFu},
+ {0x21u, 0x04u},
+ {0x23u, 0x43u},
+ {0x26u, 0xFFu},
+ {0x27u, 0x12u},
+ {0x28u, 0xFFu},
+ {0x31u, 0x10u},
+ {0x32u, 0xFFu},
+ {0x35u, 0x0Fu},
+ {0x37u, 0xE0u},
+ {0x3Au, 0x08u},
+ {0x3Fu, 0x40u},
+ {0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x20u},
- {0x5Du, 0x20u},
+ {0x5Cu, 0x02u},
+ {0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x80u, 0x44u},
- {0x82u, 0x88u},
- {0x84u, 0x12u},
- {0x86u, 0x21u},
- {0x88u, 0x0Fu},
- {0x89u, 0x0Fu},
- {0x8Au, 0xF0u},
- {0x8Bu, 0xF0u},
- {0x8Cu, 0x11u},
- {0x8Du, 0x11u},
- {0x8Eu, 0x22u},
- {0x8Fu, 0x22u},
- {0x91u, 0x33u},
- {0x92u, 0xFFu},
- {0x93u, 0xCCu},
- {0x94u, 0x33u},
- {0x96u, 0xCCu},
- {0x98u, 0x48u},
- {0x9Au, 0x84u},
- {0x9Bu, 0xFFu},
- {0x9Du, 0xFFu},
- {0x9Eu, 0xFFu},
- {0xA1u, 0x44u},
- {0xA3u, 0x88u},
- {0xA5u, 0x84u},
- {0xA6u, 0xFFu},
- {0xA7u, 0x48u},
+ {0x84u, 0x02u},
+ {0x86u, 0x09u},
+ {0x87u, 0x01u},
+ {0x89u, 0xE0u},
+ {0x8Cu, 0x02u},
+ {0x8Eu, 0x05u},
+ {0x93u, 0xECu},
+ {0x94u, 0x01u},
+ {0x95u, 0x88u},
+ {0x96u, 0x02u},
+ {0x97u, 0x03u},
+ {0x98u, 0x02u},
+ {0x9Au, 0x01u},
+ {0x9Cu, 0x02u},
+ {0x9Eu, 0x01u},
+ {0xA3u, 0x12u},
+ {0xA5u, 0x04u},
+ {0xA7u, 0x43u},
{0xA9u, 0x21u},
- {0xABu, 0x12u},
- {0xAFu, 0xFFu},
- {0xB1u, 0xFFu},
- {0xB4u, 0xFFu},
- {0xBEu, 0x10u},
- {0xBFu, 0x01u},
+ {0xABu, 0x02u},
+ {0xB2u, 0x03u},
+ {0xB3u, 0xE0u},
+ {0xB4u, 0x08u},
+ {0xB5u, 0x10u},
+ {0xB6u, 0x04u},
+ {0xB7u, 0x0Fu},
+ {0xBAu, 0x08u},
+ {0xBFu, 0x04u},
{0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
+ {0xDCu, 0x12u},
{0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x01u, 0x71u},
- {0x02u, 0x10u},
- {0x05u, 0x23u},
- {0x06u, 0x12u},
- {0x08u, 0x18u},
- {0x09u, 0x02u},
- {0x0Au, 0x83u},
- {0x0Bu, 0x08u},
- {0x0Cu, 0x20u},
- {0x0Du, 0x02u},
- {0x0Eu, 0x01u},
- {0x0Fu, 0x02u},
- {0x10u, 0x20u},
- {0x14u, 0x40u},
- {0x15u, 0x41u},
- {0x1Bu, 0x20u},
- {0x1Fu, 0x01u},
- {0x20u, 0x80u},
- {0x25u, 0x09u},
- {0x26u, 0x82u},
- {0x27u, 0x04u},
- {0x28u, 0x50u},
- {0x2Au, 0x10u},
- {0x2Bu, 0x01u},
- {0x2Cu, 0x01u},
+ {0x00u, 0x01u},
+ {0x03u, 0x0Au},
+ {0x05u, 0x80u},
+ {0x07u, 0x10u},
+ {0x08u, 0x08u},
+ {0x0Au, 0x01u},
+ {0x0Bu, 0x88u},
+ {0x0Eu, 0x2Au},
+ {0x12u, 0x18u},
+ {0x18u, 0x20u},
+ {0x1Bu, 0x08u},
+ {0x1Eu, 0x2Au},
+ {0x22u, 0x11u},
+ {0x23u, 0x02u},
+ {0x24u, 0x04u},
+ {0x25u, 0x04u},
+ {0x27u, 0x01u},
+ {0x28u, 0x10u},
+ {0x2Bu, 0x40u},
{0x2Du, 0x08u},
- {0x2Fu, 0x48u},
- {0x30u, 0x20u},
- {0x31u, 0x01u},
- {0x32u, 0x40u},
- {0x35u, 0x10u},
- {0x36u, 0x8Au},
- {0x39u, 0x50u},
- {0x3Cu, 0x02u},
- {0x3Du, 0x08u},
- {0x3Eu, 0x20u},
- {0x3Fu, 0x40u},
- {0x41u, 0x08u},
- {0x42u, 0x20u},
- {0x5Bu, 0x40u},
- {0x5Cu, 0x40u},
- {0x60u, 0x02u},
- {0x62u, 0x40u},
- {0x81u, 0x01u},
- {0x90u, 0x40u},
- {0x91u, 0x41u},
- {0x92u, 0x02u},
- {0x93u, 0xC8u},
- {0x97u, 0x02u},
- {0x98u, 0x01u},
- {0x99u, 0x38u},
+ {0x2Eu, 0x10u},
+ {0x2Fu, 0x80u},
+ {0x30u, 0x08u},
+ {0x32u, 0x11u},
+ {0x35u, 0x04u},
+ {0x37u, 0x01u},
+ {0x39u, 0x08u},
+ {0x3Bu, 0x20u},
+ {0x3Cu, 0x24u},
+ {0x58u, 0x40u},
+ {0x5Eu, 0x40u},
+ {0x60u, 0x01u},
+ {0x65u, 0x80u},
+ {0x68u, 0x82u},
+ {0x69u, 0x14u},
+ {0x71u, 0x2Au},
+ {0x73u, 0x01u},
+ {0x82u, 0x50u},
+ {0x84u, 0x40u},
+ {0x88u, 0x10u},
+ {0x8Bu, 0x80u},
+ {0x8Du, 0x04u},
+ {0x8Eu, 0x04u},
+ {0x8Fu, 0x03u},
+ {0x91u, 0x08u},
+ {0x92u, 0x01u},
+ {0x93u, 0xA8u},
+ {0x94u, 0x20u},
+ {0x95u, 0x14u},
+ {0x98u, 0x18u},
+ {0x99u, 0x0Cu},
{0x9Au, 0x10u},
- {0x9Cu, 0x02u},
- {0x9Eu, 0x40u},
- {0x9Fu, 0x04u},
- {0xA0u, 0x21u},
- {0xA1u, 0x06u},
+ {0x9Bu, 0x10u},
+ {0x9Eu, 0x04u},
+ {0xA0u, 0x08u},
{0xA2u, 0x08u},
- {0xA3u, 0x08u},
- {0xA4u, 0x40u},
- {0xA5u, 0x08u},
- {0xA6u, 0x80u},
- {0xA7u, 0x20u},
- {0xAFu, 0x08u},
- {0xB0u, 0x40u},
- {0xC0u, 0xFFu},
- {0xC2u, 0xDFu},
- {0xC4u, 0x94u},
- {0xCAu, 0xFFu},
- {0xCCu, 0xFDu},
- {0xCEu, 0xFCu},
- {0xD6u, 0x18u},
- {0xD8u, 0x08u},
- {0xE0u, 0x01u},
- {0xEAu, 0x08u},
- {0xEEu, 0x08u},
- {0xA8u, 0x08u},
- {0xA9u, 0x02u},
+ {0xA3u, 0x42u},
+ {0xA4u, 0x82u},
+ {0xA5u, 0x2Au},
+ {0xA6u, 0x11u},
{0xABu, 0x40u},
- {0xAEu, 0x10u},
- {0xB2u, 0x02u},
- {0xB3u, 0x04u},
- {0xE8u, 0x20u},
- {0xEAu, 0x80u},
+ {0xADu, 0x01u},
+ {0xAFu, 0x02u},
+ {0xB1u, 0x0Cu},
+ {0xB2u, 0x08u},
+ {0xB3u, 0x10u},
+ {0xB4u, 0xA0u},
+ {0xC0u, 0xABu},
+ {0xC2u, 0xEFu},
+ {0xC4u, 0x06u},
+ {0xCAu, 0xE3u},
+ {0xCCu, 0xC7u},
+ {0xCEu, 0x66u},
+ {0xD6u, 0x18u},
+ {0xD8u, 0x18u},
+ {0xE0u, 0x80u},
+ {0xE2u, 0x10u},
+ {0xE4u, 0x80u},
+ {0xE6u, 0x48u},
+ {0xE8u, 0xB0u},
+ {0xECu, 0x80u},
{0xEEu, 0x01u},
- {0x05u, 0x20u},
- {0x0Eu, 0x20u},
- {0x0Fu, 0x04u},
- {0x12u, 0x08u},
- {0x13u, 0x02u},
+ {0x06u, 0x08u},
+ {0x0Cu, 0x10u},
+ {0x0Eu, 0x40u},
+ {0x11u, 0x10u},
+ {0x13u, 0x08u},
{0x16u, 0x80u},
- {0x17u, 0x80u},
- {0x30u, 0x10u},
+ {0x17u, 0x40u},
+ {0x30u, 0x40u},
{0x33u, 0x01u},
- {0x36u, 0x20u},
- {0x37u, 0x08u},
- {0x39u, 0x04u},
- {0x3Au, 0x80u},
- {0x3Cu, 0x10u},
- {0x3Eu, 0x04u},
+ {0x36u, 0x22u},
+ {0x3Au, 0x81u},
+ {0x3Du, 0x44u},
{0x40u, 0x04u},
- {0x56u, 0x02u},
- {0x59u, 0x40u},
- {0x6Bu, 0x03u},
- {0x83u, 0x08u},
+ {0x53u, 0x02u},
+ {0x5Fu, 0x40u},
+ {0x6Bu, 0x09u},
+ {0x82u, 0x01u},
{0xC0u, 0x80u},
{0xC2u, 0xA0u},
{0xC4u, 0xF0u},
{0xD4u, 0x80u},
{0xD6u, 0x20u},
{0xE2u, 0x20u},
- {0x03u, 0x02u},
- {0x0Au, 0x01u},
- {0x30u, 0x04u},
- {0x33u, 0x10u},
- {0x34u, 0x02u},
- {0x37u, 0x80u},
- {0x3Au, 0x80u},
- {0x5Au, 0x20u},
- {0x63u, 0x80u},
- {0x84u, 0x02u},
- {0x89u, 0x20u},
- {0x93u, 0x04u},
+ {0x00u, 0x10u},
+ {0x0Au, 0x02u},
+ {0x30u, 0x08u},
+ {0x33u, 0x20u},
+ {0x36u, 0x08u},
+ {0x37u, 0x40u},
+ {0x39u, 0x80u},
+ {0x59u, 0x40u},
+ {0x61u, 0x20u},
+ {0x82u, 0x08u},
+ {0x85u, 0x10u},
+ {0x86u, 0x02u},
+ {0x87u, 0x20u},
+ {0x88u, 0x08u},
+ {0x89u, 0x40u},
+ {0x91u, 0x10u},
+ {0x92u, 0x40u},
{0x94u, 0x04u},
- {0x96u, 0x04u},
- {0x99u, 0x20u},
- {0x9Bu, 0x90u},
- {0x9Cu, 0x10u},
- {0x9Du, 0x40u},
- {0xA2u, 0x10u},
- {0xA6u, 0x20u},
- {0xA8u, 0x10u},
- {0xAAu, 0x08u},
- {0xABu, 0x10u},
- {0xADu, 0x04u},
- {0xB6u, 0x02u},
+ {0x95u, 0x04u},
+ {0x97u, 0x40u},
+ {0x98u, 0x10u},
+ {0x9Au, 0x08u},
+ {0x9Bu, 0x40u},
+ {0x9Cu, 0x40u},
+ {0xA1u, 0x20u},
+ {0xA6u, 0x22u},
+ {0xA7u, 0x02u},
+ {0xA9u, 0x20u},
+ {0xB5u, 0x40u},
{0xC0u, 0x40u},
{0xC2u, 0x40u},
{0xCCu, 0xF0u},
{0xCEu, 0x10u},
{0xD4u, 0x80u},
{0xD8u, 0x40u},
- {0xE6u, 0x40u},
- {0xEEu, 0xC0u},
- {0x10u, 0x10u},
+ {0xE2u, 0x60u},
+ {0xEAu, 0x20u},
+ {0x10u, 0x40u},
{0x33u, 0x80u},
- {0x83u, 0x40u},
- {0x86u, 0x80u},
- {0x93u, 0x04u},
+ {0x81u, 0x20u},
+ {0x88u, 0x10u},
+ {0x8Eu, 0x20u},
+ {0x92u, 0x42u},
{0x94u, 0x04u},
- {0x9Cu, 0x14u},
- {0x9Eu, 0x80u},
- {0xA2u, 0x10u},
- {0xA7u, 0x40u},
- {0xAAu, 0x10u},
- {0xADu, 0x40u},
- {0xAEu, 0x05u},
- {0xB3u, 0x02u},
- {0xB6u, 0x20u},
+ {0x95u, 0x84u},
+ {0x97u, 0x40u},
+ {0x98u, 0x10u},
+ {0x9Au, 0x08u},
+ {0x9Cu, 0x40u},
+ {0xA6u, 0x20u},
+ {0xB4u, 0x10u},
+ {0xB7u, 0x02u},
{0xC4u, 0x10u},
{0xCCu, 0x10u},
- {0xE2u, 0x60u},
- {0xE8u, 0x10u},
- {0xEAu, 0x40u},
- {0xEEu, 0x30u},
- {0x68u, 0x40u},
- {0x84u, 0x04u},
- {0x87u, 0x04u},
- {0x93u, 0x04u},
+ {0xE6u, 0x80u},
+ {0x86u, 0x01u},
+ {0x8Du, 0x80u},
+ {0x92u, 0x42u},
{0x94u, 0x04u},
- {0x9Cu, 0x04u},
+ {0x95u, 0x04u},
+ {0x97u, 0x40u},
+ {0x99u, 0x20u},
+ {0x9Au, 0x08u},
{0xA7u, 0x80u},
- {0xB2u, 0x10u},
- {0xDCu, 0x20u},
- {0xE0u, 0x40u},
- {0xE2u, 0x10u},
+ {0xA9u, 0x40u},
+ {0xE4u, 0x40u},
+ {0xEAu, 0x80u},
{0x05u, 0x08u},
{0x06u, 0x08u},
- {0x08u, 0x08u},
- {0x09u, 0x20u},
- {0x13u, 0x02u},
- {0x52u, 0x20u},
- {0x58u, 0x02u},
- {0x62u, 0x02u},
- {0x71u, 0x04u},
+ {0x09u, 0x01u},
+ {0x0Bu, 0x02u},
+ {0x11u, 0x04u},
+ {0x56u, 0x04u},
+ {0x5Bu, 0x02u},
+ {0x65u, 0x40u},
+ {0x78u, 0x80u},
{0xC0u, 0x05u},
{0xC2u, 0x0Au},
{0xC4u, 0x08u},
- {0xD4u, 0x04u},
- {0xD6u, 0x02u},
- {0xD8u, 0x02u},
+ {0xD4u, 0x02u},
+ {0xD6u, 0x03u},
{0xDCu, 0x01u},
- {0x00u, 0x02u},
- {0x02u, 0x02u},
- {0x08u, 0x84u},
- {0x56u, 0x22u},
- {0x5Bu, 0x04u},
- {0x60u, 0x10u},
- {0x85u, 0x01u},
- {0x86u, 0x02u},
- {0x8Du, 0x04u},
- {0x98u, 0x08u},
+ {0x01u, 0x42u},
+ {0x09u, 0x04u},
+ {0x0Au, 0x01u},
+ {0x52u, 0x02u},
+ {0x57u, 0x01u},
+ {0x66u, 0x82u},
+ {0x80u, 0x02u},
+ {0x86u, 0x82u},
+ {0x87u, 0x02u},
+ {0x89u, 0x08u},
+ {0x8Eu, 0x02u},
+ {0x91u, 0x04u},
+ {0x93u, 0x02u},
{0x99u, 0x08u},
{0x9Au, 0x08u},
- {0x9Bu, 0x02u},
- {0x9Cu, 0x02u},
- {0x9Du, 0x04u},
- {0xA1u, 0x20u},
- {0xA6u, 0x20u},
- {0xB6u, 0x02u},
+ {0x9Du, 0x40u},
+ {0x9Eu, 0x04u},
+ {0x9Fu, 0x02u},
+ {0xA5u, 0x04u},
+ {0xA9u, 0x05u},
+ {0xACu, 0x80u},
+ {0xADu, 0x40u},
{0xC0u, 0x0Au},
{0xC2u, 0x0Au},
- {0xD4u, 0x02u},
- {0xD6u, 0x06u},
- {0xD8u, 0x02u},
- {0xE0u, 0x08u},
- {0xECu, 0x08u},
+ {0xD4u, 0x01u},
+ {0xD6u, 0x05u},
+ {0xD8u, 0x01u},
+ {0xE4u, 0x08u},
+ {0xE6u, 0x04u},
{0x54u, 0x20u},
- {0x87u, 0x04u},
- {0x95u, 0x02u},
- {0x98u, 0x04u},
- {0x99u, 0x08u},
+ {0x87u, 0x01u},
+ {0x91u, 0x04u},
+ {0x92u, 0x01u},
+ {0x93u, 0x02u},
+ {0x99u, 0x0Au},
{0x9Au, 0x08u},
- {0x9Bu, 0x02u},
- {0x9Cu, 0x02u},
- {0x9Fu, 0x04u},
+ {0x9Du, 0x40u},
+ {0x9Eu, 0x04u},
{0xA0u, 0x20u},
- {0xA1u, 0x20u},
- {0xA2u, 0x02u},
- {0xA6u, 0x20u},
- {0xA8u, 0x10u},
- {0xACu, 0x28u},
- {0xB0u, 0x81u},
- {0xB2u, 0x20u},
+ {0xA4u, 0x02u},
+ {0xA5u, 0x08u},
+ {0xA7u, 0x01u},
+ {0xACu, 0x20u},
+ {0xB5u, 0x40u},
{0xD4u, 0x02u},
- {0xEAu, 0x05u},
- {0xECu, 0x01u},
- {0x0Bu, 0x84u},
- {0x0Du, 0x01u},
+ {0xEAu, 0x02u},
+ {0x09u, 0x08u},
+ {0x0Bu, 0x01u},
+ {0x0Cu, 0x02u},
{0x0Fu, 0x02u},
- {0x86u, 0x08u},
- {0x87u, 0x40u},
- {0x8Au, 0x02u},
- {0x95u, 0x02u},
- {0x97u, 0x04u},
- {0x98u, 0x04u},
- {0x99u, 0x08u},
+ {0x82u, 0x04u},
+ {0x85u, 0x40u},
+ {0x86u, 0x01u},
+ {0x89u, 0x04u},
+ {0x8Fu, 0x01u},
+ {0x91u, 0x04u},
+ {0x92u, 0x01u},
+ {0x93u, 0x02u},
+ {0x97u, 0x01u},
+ {0x99u, 0x0Au},
{0x9Au, 0x08u},
- {0x9Bu, 0x02u},
- {0x9Cu, 0x02u},
- {0x9Fu, 0x04u},
- {0xA2u, 0x02u},
- {0xB5u, 0x20u},
- {0xB6u, 0x20u},
- {0xC2u, 0x0Fu},
- {0xE6u, 0x04u},
- {0xE8u, 0x08u},
- {0xEEu, 0x02u},
- {0x02u, 0x04u},
- {0x80u, 0x02u},
- {0x8Cu, 0x04u},
- {0x94u, 0x04u},
+ {0x9Du, 0x40u},
{0x9Eu, 0x04u},
- {0xAAu, 0x04u},
- {0xACu, 0x40u},
+ {0xA4u, 0x02u},
+ {0xA5u, 0x08u},
+ {0xABu, 0x01u},
+ {0xC2u, 0x0Fu},
+ {0xE2u, 0x06u},
+ {0x01u, 0x80u},
+ {0x65u, 0x04u},
+ {0x8Bu, 0x40u},
+ {0x92u, 0x40u},
+ {0x95u, 0x04u},
+ {0x97u, 0x40u},
+ {0x99u, 0x20u},
+ {0x9Du, 0x80u},
+ {0xAAu, 0x08u},
{0xAFu, 0x80u},
+ {0xB4u, 0x04u},
{0xC0u, 0x40u},
- {0xE2u, 0x20u},
- {0xE8u, 0x80u},
- {0xEAu, 0x40u},
+ {0xD8u, 0x80u},
+ {0xECu, 0x80u},
{0xEEu, 0x10u},
- {0x01u, 0x02u},
- {0x50u, 0x20u},
- {0x54u, 0x02u},
+ {0x03u, 0x20u},
+ {0x51u, 0x02u},
+ {0x56u, 0x20u},
{0x5Bu, 0x02u},
- {0x66u, 0x02u},
- {0x70u, 0x04u},
- {0x80u, 0x20u},
- {0x85u, 0x02u},
- {0x8Au, 0x02u},
- {0x8Bu, 0x02u},
- {0x8Cu, 0x04u},
- {0xA0u, 0x02u},
+ {0x65u, 0x20u},
+ {0x77u, 0x10u},
+ {0x82u, 0x40u},
+ {0x87u, 0x20u},
+ {0x8Du, 0x02u},
+ {0x8Eu, 0x20u},
+ {0x8Fu, 0x02u},
+ {0x92u, 0x40u},
+ {0x99u, 0x20u},
+ {0x9Bu, 0x10u},
+ {0xA9u, 0x04u},
+ {0xABu, 0x10u},
+ {0xADu, 0x04u},
{0xC0u, 0x10u},
- {0xD4u, 0x20u},
- {0xD6u, 0x60u},
+ {0xD4u, 0xC0u},
+ {0xD6u, 0x40u},
{0xD8u, 0x80u},
- {0xDCu, 0x80u},
- {0xE2u, 0x80u},
+ {0xDEu, 0x20u},
+ {0xE0u, 0x20u},
{0xE4u, 0x10u},
- {0x83u, 0x04u},
- {0x9Bu, 0x02u},
- {0x9Cu, 0x02u},
- {0x9Fu, 0x04u},
- {0xACu, 0x04u},
+ {0xEAu, 0x20u},
+ {0xEEu, 0xC0u},
+ {0x99u, 0x0Au},
+ {0x9Au, 0x08u},
{0xAFu, 0x01u},
- {0xB1u, 0x08u},
- {0xEAu, 0x01u},
- {0xABu, 0x02u},
- {0xB0u, 0x02u},
- {0xE8u, 0x04u},
+ {0x85u, 0x08u},
+ {0x99u, 0x08u},
+ {0xAAu, 0x08u},
+ {0xB5u, 0x02u},
+ {0xEAu, 0x02u},
{0x10u, 0x07u},
{0x11u, 0x01u},
- {0x1Au, 0x03u},
- {0x1Cu, 0x04u},
+ {0x1Au, 0x07u},
+ {0x1Cu, 0x07u},
{0x1Du, 0x01u},
{0x00u, 0xFFu},
{0x01u, 0xBFu},
/* address, size */
{(void CYFAR *)(CYREG_TMR0_CFG0), 12u},
{(void CYFAR *)(CYREG_PRT5_DR), 16u},
- {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},
+ {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1024u},
+ {(void CYFAR *)(CYDEV_UCFG_B0_P2_U1_BASE), 2944u},
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u},
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
{(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u},
};
+ /* UDB_1_3_0_CONFIG Address: CYDEV_UCFG_B0_P2_U0_BASE Size (bytes): 128 */
+ static const uint8 CYCODE BS_UDB_1_3_0_CONFIG_VAL[] = {
+ 0x00u, 0x24u, 0x00u, 0x12u, 0x08u, 0x00u, 0x61u, 0x20u, 0x00u, 0x00u, 0x40u, 0x04u, 0x07u, 0x00u, 0xD8u, 0x24u,
+ 0x01u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0x03u, 0x04u, 0x00u, 0x00u, 0x18u, 0x01u, 0x00u, 0x00u, 0x00u,
+ 0x01u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0xA2u, 0x24u, 0x08u, 0x09u, 0x01u, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0xE0u, 0x07u, 0x3Fu, 0x38u, 0x00u, 0x00u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x10u, 0x00u,
+ 0x63u, 0x04u, 0x50u, 0x00u, 0x02u, 0xCEu, 0xBFu, 0xD0u, 0x2Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x04u, 0x04u, 0x04u, 0x20u, 0x00u, 0x00u, 0x01u,
+ 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
+
/* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */
static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {
- 0x77u, 0x80u, 0x08u, 0x00u, 0x39u, 0x00u, 0x06u, 0x60u, 0x04u, 0xC0u, 0x20u, 0x08u, 0xC6u, 0x00u, 0x00u, 0x9Fu,
- 0x42u, 0x90u, 0x00u, 0x40u, 0x00u, 0x1Fu, 0x00u, 0x20u, 0x01u, 0xC0u, 0x5Eu, 0x04u, 0xC6u, 0xC0u, 0x00u, 0x02u,
- 0x00u, 0xC0u, 0x00u, 0x01u, 0xC2u, 0x00u, 0x04u, 0xFFu, 0x80u, 0x7Fu, 0x46u, 0x80u, 0x46u, 0x00u, 0x80u, 0x00u,
- 0x80u, 0xFFu, 0x0Fu, 0x00u, 0x70u, 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x30u, 0x00u, 0x00u, 0x00u, 0x01u, 0x01u,
- 0x32u, 0x06u, 0x40u, 0x00u, 0x05u, 0xDEu, 0xFBu, 0x0Cu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x20u, 0x04u, 0x04u, 0x04u, 0x04u, 0x01u, 0x11u, 0x00u, 0x01u,
+ 0x5Cu, 0x00u, 0x00u, 0x00u, 0x30u, 0x05u, 0x0Fu, 0x02u, 0x00u, 0x00u, 0x00u, 0x00u, 0x0Cu, 0x01u, 0x50u, 0x06u,
+ 0x11u, 0x04u, 0x22u, 0x03u, 0x21u, 0x00u, 0x1Eu, 0x00u, 0x54u, 0x00u, 0x08u, 0x00u, 0x5Cu, 0x00u, 0x00u, 0x00u,
+ 0x00u, 0x00u, 0x00u, 0x00u, 0x50u, 0x00u, 0x0Cu, 0x00u, 0x24u, 0x00u, 0x10u, 0x00u, 0x08u, 0x03u, 0x00u, 0x04u,
+ 0x0Fu, 0x07u, 0x40u, 0x00u, 0x30u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, 0x20u, 0x02u, 0x00u, 0x00u, 0x44u, 0x00u,
+ 0x16u, 0x04u, 0x30u, 0x00u, 0x05u, 0xBEu, 0xF0u, 0xCDu, 0x3Bu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x2Cu, 0x04u, 0x04u, 0x04u, 0x04u, 0x11u, 0x11u, 0x00u, 0x01u,
0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {
- 0x07u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x05u, 0x01u, 0x07u, 0x01u, 0x04u, 0x01u, 0x04u, 0x01u};
+ 0x07u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x05u, 0x01u, 0x07u, 0x01u, 0x05u, 0x01u, 0x05u, 0x01u};
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
/* dest, src, size */
+ {(void CYFAR *)(CYDEV_UCFG_B0_P2_U0_BASE), BS_UDB_1_3_0_CONFIG_VAL, 128u},
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u},
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u},
};
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB04_MSK
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB04_ST
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
.set SDCard_BSPIM_TxStsReg__0__POS, 0
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
.set SDCard_BSPIM_TxStsReg__2__POS, 2
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
/* SD_SCK */
.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE1
.set NOR_SCK__SLW, CYREG_PRT3_SLW
/* NOR_SPI */
-.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
-.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL
-.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL
-.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL
-.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL
-.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK
-.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK
-.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK
-.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK
-.set NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
-.set NOR_SPI_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL
-.set NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL
-.set NOR_SPI_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL
-.set NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL
-.set NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
-.set NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
-.set NOR_SPI_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK
-.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
-.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
-.set NOR_SPI_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK
-.set NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
-.set NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
-.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
-.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL
-.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL
-.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST
-.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
-.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
+.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
+.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
+.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
+.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
+.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
+.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
+.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
+.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
+.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
+.set NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
+.set NOR_SPI_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB04_CTL
+.set NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
+.set NOR_SPI_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB04_CTL
+.set NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
+.set NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set NOR_SPI_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB04_MSK
+.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
+.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
+.set NOR_SPI_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB04_MSK
+.set NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
+.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL
+.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL
+.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB04_ST
+.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
+.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
.set NOR_SPI_BSPIM_RxStsReg__4__MASK, 0x10
.set NOR_SPI_BSPIM_RxStsReg__4__POS, 4
.set NOR_SPI_BSPIM_RxStsReg__5__MASK, 0x20
.set NOR_SPI_BSPIM_RxStsReg__6__MASK, 0x40
.set NOR_SPI_BSPIM_RxStsReg__6__POS, 6
.set NOR_SPI_BSPIM_RxStsReg__MASK, 0x70
-.set NOR_SPI_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK
-.set NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
-.set NOR_SPI_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST
-.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0
-.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1
-.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0
-.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1
-.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
-.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0
-.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1
-.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1
-.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0
-.set NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1
-.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1
-.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0
-.set NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1
-.set NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
-.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1
-.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0
-.set NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1
-.set NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
-.set NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
+.set NOR_SPI_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB11_MSK
+.set NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
+.set NOR_SPI_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB11_ST
+.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0
+.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1
+.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0
+.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB04_05_D1
+.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
+.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB04_05_F0
+.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB04_05_F1
+.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB04_A0_A1
+.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB04_A0
+.set NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB04_A1
+.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB04_D0_D1
+.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB04_D0
+.set NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB04_D1
+.set NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
+.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB04_F0_F1
+.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB04_F0
+.set NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB04_F1
+.set NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
.set NOR_SPI_BSPIM_TxStsReg__0__MASK, 0x01
.set NOR_SPI_BSPIM_TxStsReg__0__POS, 0
.set NOR_SPI_BSPIM_TxStsReg__1__MASK, 0x02
.set NOR_SPI_BSPIM_TxStsReg__1__POS, 1
-.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
-.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
+.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
+.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
.set NOR_SPI_BSPIM_TxStsReg__2__MASK, 0x04
.set NOR_SPI_BSPIM_TxStsReg__2__POS, 2
.set NOR_SPI_BSPIM_TxStsReg__3__MASK, 0x08
.set NOR_SPI_BSPIM_TxStsReg__4__MASK, 0x10
.set NOR_SPI_BSPIM_TxStsReg__4__POS, 4
.set NOR_SPI_BSPIM_TxStsReg__MASK, 0x1F
-.set NOR_SPI_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK
-.set NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
-.set NOR_SPI_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST
+.set NOR_SPI_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB03_MSK
+.set NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
+.set NOR_SPI_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB03_ST
/* SCSI_In */
.set SCSI_In__0__INTTYPE, CYREG_PICU6_INTTYPE1
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_11_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB10_11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB10_11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB10_11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB10_11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB10_11_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB10_11_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB10_11_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB10_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB10_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB10_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB10_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB10_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB10_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB10_MSK
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB08_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB08_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB08_MSK
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX
.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE
.set scsiTarget_StatusReg__0__POS, 0
.set scsiTarget_StatusReg__1__MASK, 0x02
.set scsiTarget_StatusReg__1__POS, 1
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
.set scsiTarget_StatusReg__2__MASK, 0x04
.set scsiTarget_StatusReg__2__POS, 2
.set scsiTarget_StatusReg__3__MASK, 0x08
.set scsiTarget_StatusReg__4__MASK, 0x10
.set scsiTarget_StatusReg__4__POS, 4
.set scsiTarget_StatusReg__MASK, 0x1F
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB03_MSK
-.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
-.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
-.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL
-.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB03_ST
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK
+.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
+.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
+.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB15_ST_CTL
+.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB15_ST_CTL
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST
/* Debug_Timer */
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SCSI_Filtered_sts_sts_reg__0__POS, 0
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
.set SCSI_Filtered_sts_sts_reg__1__POS, 1
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
.set SCSI_Filtered_sts_sts_reg__2__POS, 2
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
.set SCSI_Filtered_sts_sts_reg__4__POS, 4
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB15_MSK
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB15_ST
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B1_UDB08_MSK
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B1_UDB08_ST
/* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB15_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB15_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB15_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB15_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB15_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB15_MSK
/* SCSI_Glitch_Ctl */
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB09_10_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB09_10_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB09_10_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB09_10_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB09_10_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB09_10_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB09_10_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB09_10_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB09_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB09_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB09_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB09_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB09_MSK
/* SCSI_Parity_Error */
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B1_UDB08_MSK
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B1_UDB08_ST
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB12_MSK
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB12_ST
/* Miscellaneous */
.set BCLK__BUS_CLK__HZ, 50000000
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
/* SD_SCK */
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1
NOR_SCK__SLW EQU CYREG_PRT3_SLW
/* NOR_SPI */
-NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
-NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
-NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
-NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
-NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
-NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
-NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
-NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
-NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL
-NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
-NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL
-NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
-NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
-NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
-NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK
-NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL
-NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL
-NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST
-NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
-NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
+NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB04_CTL
+NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB04_CTL
+NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB04_MSK
+NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB04_MSK
+NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB04_ST
+NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10
NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4
NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20
NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40
NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6
NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70
-NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
-NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
-NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
-NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0
-NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1
-NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0
-NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1
-NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0
-NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1
-NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1
-NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0
-NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1
-NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1
-NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0
-NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1
-NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1
-NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0
-NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1
-NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB11_MSK
+NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB11_ST
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1
+NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1
+NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0
+NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1
+NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1
+NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0
+NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1
+NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1
+NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0
+NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1
+NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
NOR_SPI_BSPIM_TxStsReg__0__MASK EQU 0x01
NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0
NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02
NOR_SPI_BSPIM_TxStsReg__1__POS EQU 1
-NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
+NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
+NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
NOR_SPI_BSPIM_TxStsReg__2__MASK EQU 0x04
NOR_SPI_BSPIM_TxStsReg__2__POS EQU 2
NOR_SPI_BSPIM_TxStsReg__3__MASK EQU 0x08
NOR_SPI_BSPIM_TxStsReg__4__MASK EQU 0x10
NOR_SPI_BSPIM_TxStsReg__4__POS EQU 4
NOR_SPI_BSPIM_TxStsReg__MASK EQU 0x1F
-NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
-NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
+NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB03_MSK
+NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
+NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB03_ST
/* SCSI_In */
SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB10_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK
-scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
-scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL
-scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB15_ST_CTL
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB15_ST_CTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
/* Debug_Timer */
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB15_MSK
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB15_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST
/* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
/* SCSI_Glitch_Ctl */
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK
/* SCSI_Parity_Error */
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST
/* Miscellaneous */
BCLK__BUS_CLK__HZ EQU 50000000
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
; SD_SCK
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1
NOR_SCK__SLW EQU CYREG_PRT3_SLW
; NOR_SPI
-NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
-NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
-NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
-NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
-NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
-NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
-NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
-NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
-NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL
-NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
-NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL
-NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
-NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
-NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
-NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK
-NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL
-NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL
-NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST
-NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
-NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
+NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB04_CTL
+NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB04_CTL
+NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB04_MSK
+NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB04_MSK
+NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL
+NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB04_ST
+NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
+NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10
NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4
NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20
NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40
NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6
NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70
-NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
-NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
-NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
-NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0
-NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1
-NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0
-NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1
-NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
-NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0
-NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1
-NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1
-NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0
-NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1
-NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1
-NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0
-NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1
-NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
-NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1
-NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0
-NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1
-NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
-NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
+NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB11_MSK
+NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
+NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB11_ST
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0
+NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1
+NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1
+NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0
+NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1
+NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1
+NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0
+NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1
+NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1
+NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0
+NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1
+NOR_SPI_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+NOR_SPI_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
NOR_SPI_BSPIM_TxStsReg__0__MASK EQU 0x01
NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0
NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02
NOR_SPI_BSPIM_TxStsReg__1__POS EQU 1
-NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
+NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
+NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
NOR_SPI_BSPIM_TxStsReg__2__MASK EQU 0x04
NOR_SPI_BSPIM_TxStsReg__2__POS EQU 2
NOR_SPI_BSPIM_TxStsReg__3__MASK EQU 0x08
NOR_SPI_BSPIM_TxStsReg__4__MASK EQU 0x10
NOR_SPI_BSPIM_TxStsReg__4__POS EQU 4
NOR_SPI_BSPIM_TxStsReg__MASK EQU 0x1F
-NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
-NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
+NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB03_MSK
+NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
+NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB03_ST
; SCSI_In
SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_11_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB10_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB10_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB10_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB10_MSK
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB08_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB08_MSK
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX
SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK
-scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
-scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL
-scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB15_ST_CTL
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB15_ST_CTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST
; Debug_Timer
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB15_MSK
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB15_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST
; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK
; SCSI_Glitch_Ctl
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK
; SCSI_Parity_Error
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B1_UDB08_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B1_UDB08_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB12_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB12_ST
; Miscellaneous
BCLK__BUS_CLK__HZ EQU 50000000
<block name="Clock_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Glitch_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
- <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x4000647C" bitWidth="8" desc="" hidden="false" />
+ <register name="SCSI_Glitch_Ctl_CONTROL_REG" address="0x40006479" bitWidth="8" desc="" hidden="false" />
</block>
<block name="TERM_EN" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_SEL_ISR" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="mux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Parity_Error" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
- <register name="SCSI_Parity_Error_STATUS_REG" address="0x40006568" bitWidth="8" desc="" hidden="false" />
- <register name="SCSI_Parity_Error_MASK_REG" address="0x40006588" bitWidth="8" desc="" hidden="false" />
- <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x40006598" bitWidth="8" desc="" hidden="false">
+ <register name="SCSI_Parity_Error_STATUS_REG" address="0x4000646C" bitWidth="8" desc="" hidden="false" />
+ <register name="SCSI_Parity_Error_MASK_REG" address="0x4000648C" bitWidth="8" desc="" hidden="false" />
+ <register name="SCSI_Parity_Error_STATUS_AUX_CTL_REG" address="0x4000649C" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
<block name="cy_constant_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cydff_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Filtered" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
- <register name="SCSI_Filtered_STATUS_REG" address="0x4000646F" bitWidth="8" desc="" hidden="false" />
- <register name="SCSI_Filtered_MASK_REG" address="0x4000648F" bitWidth="8" desc="" hidden="false" />
- <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x4000649F" bitWidth="8" desc="" hidden="false">
+ <register name="SCSI_Filtered_STATUS_REG" address="0x40006568" bitWidth="8" desc="" hidden="false" />
+ <register name="SCSI_Filtered_MASK_REG" address="0x40006588" bitWidth="8" desc="" hidden="false" />
+ <register name="SCSI_Filtered_STATUS_AUX_CTL_REG" address="0x40006598" bitWidth="8" desc="" hidden="false">
<field name="FIFO0" from="5" to="5" access="RW" resetVal="" desc="FIFO0 clear" hidden="false">
<value name="ENABLED" value="1" desc="Enable counter" />
<value name="DISABLED" value="0" desc="Disable counter" />
</register>
</block>
<block name="GlitchFilter_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="nNOR_HOLD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="not_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="NOR_SI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="NOR_SPI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
- <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- </block>
+ <block name="nNOR_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="NOR_SCK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="nNOR_HOLD" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="cy_boot" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Em_EEPROM_Dynamic" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="nNOR_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="nNOR_WP" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="not_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="not_9" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_5" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="not_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="not_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="not_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="NOR_Clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="not_8" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="NOR_SO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="not_7" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="NOR_SPI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ </block>
<block name="not_6" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="NOR_Clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_MOSI" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_CLK" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_CS" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Noise" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_Data_Clk" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_CTL_PHASE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
- <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647D" bitWidth="8" desc="" hidden="false" />
+ <register name="SCSI_CTL_PHASE_CONTROL_REG" address="0x4000647F" bitWidth="8" desc="" hidden="false" />
</block>
<block name="SCSI_In_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_DBx" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="CFG_EEPROM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="OddParityGen_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_In" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="Debug_Timer_Interrupt" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
- <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG" hidden="false">
- <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." hidden="false" />
- </register>
- <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0" hidden="false">
- <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." hidden="false" />
- <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)" hidden="false">
- <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
- <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
- </field>
- <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." hidden="false" />
- <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." hidden="false" />
- <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" hidden="false" />
- <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively." hidden="false">
- <value name="Timer" value="0" desc="CMP and TC are output." />
- <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
- </field>
- <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" hidden="false" />
- </register>
- <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1" hidden="false">
- <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" hidden="false" />
- <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled." hidden="false">
- <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
- <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
- </field>
- <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." hidden="false" />
- <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." hidden="false" />
- <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." hidden="false" />
- <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." hidden="false" />
- </register>
- <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2" hidden="false">
- <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ" hidden="false">
- <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
- <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
- <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
- <value name="Irq" value="11" desc="Timer runs until IRQ." />
- </field>
- <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." hidden="false" />
- <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" hidden="false" />
- <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations" hidden="false">
- <value name="Equal" value="0" desc="Compare Equal " />
- <value name="Less than" value="1" desc="Compare Less Than " />
- <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
- <value name="Greater" value="11" desc="Compare Greater Than ." />
- <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
- </field>
- <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." hidden="false" />
- </register>
- <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />
- <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />
- </block>
+ <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="timer_clock" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SD_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="SCSI_TX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="SD_RX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_TX_DMA_COMPLETE" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
- <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="SD_RX_DMA" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="USBFS" BASE="0x0" SIZE="0x0" desc="USBFS" visible="true" hidden="false">
<block name="ep_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ep_4" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<field name="RA9" from="0" to="0" access="RW" resetVal="" desc="Read Address for EP MSB." hidden="false" />
</register>
</block>
- <block name="LED1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SDCard" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
<block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="BSPIM" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
</block>
- <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
- <register name="SCSI_Out_Bits_CONTROL_REG" address="0x40006473" bitWidth="8" desc="" hidden="false" />
- </block>
+ <block name="SD_MISO" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_Ctl" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
- <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006471" bitWidth="8" desc="" hidden="false" />
+ <register name="SCSI_Out_Ctl_CONTROL_REG" address="0x40006478" bitWidth="8" desc="" hidden="false" />
+ </block>
+ <block name="Debug_Timer" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
+ <block name="VirtualMux_2" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="ZeroTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="TimerHW" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="OneTerminal_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="VirtualMux_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="VirtualMux_3" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <register name="Debug_Timer_GLOBAL_ENABLE" address="0x400043A3" bitWidth="8" desc="PM.ACT.CFG" hidden="false">
+ <field name="en_timer" from="3" to="0" access="RW" resetVal="" desc="Enable timer/counters." hidden="false" />
+ </register>
+ <register name="Debug_Timer_CONTROL" address="0x40004F00" bitWidth="8" desc="TMRx.CFG0" hidden="false">
+ <field name="EN" from="0" to="0" access="RW" resetVal="" desc="Enables timer/comparator." hidden="false" />
+ <field name="MODE" from="1" to="1" access="RW" resetVal="" desc="Mode. (0 = Timer; 1 = Comparator)" hidden="false">
+ <value name="Timer" value="0" desc="Timer mode. CNT/CMP register holds timer count value." />
+ <value name="Comparator" value="1" desc="Comparator mode. CNT/CMP register holds comparator threshold value." />
+ </field>
+ <field name="ONESHOT" from="2" to="2" access="RW" resetVal="" desc="Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block." hidden="false" />
+ <field name="CMP_BUFF" from="3" to="3" access="RW" resetVal="" desc="Buffer compare register. Compare register updates only on timer terminal count." hidden="false" />
+ <field name="INV" from="4" to="4" access="RW" resetVal="" desc="Invert sense of TIMEREN signal" hidden="false" />
+ <field name="DB" from="5" to="5" access="RW" resetVal="" desc="Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively." hidden="false">
+ <value name="Timer" value="0" desc="CMP and TC are output." />
+ <value name="Deadband" value="1" desc="PHI1 (instead of CMP) and PHI2 (instead of TC) are output." />
+ </field>
+ <field name="DEADBAND_PERIOD" from="7" to="6" access="RW" resetVal="" desc="Deadband Period" hidden="false" />
+ </register>
+ <register name="Debug_Timer_CONTROL2" address="0x40004F01" bitWidth="8" desc="TMRx.CFG1" hidden="false">
+ <field name="IRQ_SEL" from="0" to="0" access="RW" resetVal="" desc="Irq selection. (0 = raw interrupts; 1 = status register interrupts)" hidden="false" />
+ <field name="FTC" from="1" to="1" access="RW" resetVal="" desc="First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled." hidden="false">
+ <value name="Disable FTC" value="0" desc="Disable the single cycle pulse, which signifies the timer is starting." />
+ <value name="Enable FTC" value="1" desc="Enable the single cycle pulse, which signifies the timer is starting." />
+ </field>
+ <field name="DCOR" from="2" to="2" access="RW" resetVal="" desc="Disable Clear on Read (DCOR) of Status Register SR0." hidden="false" />
+ <field name="DBMODE" from="3" to="3" access="RW" resetVal="" desc="Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND)." hidden="false" />
+ <field name="CLK_BUS_EN_SEL" from="6" to="4" access="RW" resetVal="" desc="Digital Global Clock selection." hidden="false" />
+ <field name="BUS_CLK_SEL" from="7" to="7" access="RW" resetVal="" desc="Bus Clock selection." hidden="false" />
+ </register>
+ <register name="Debug_Timer_CONTROL3_" address="0x40004F02" bitWidth="8" desc="TMRx.CFG2" hidden="false">
+ <field name="TMR_CFG" from="1" to="0" access="RW" resetVal="" desc="Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ" hidden="false">
+ <value name="Continuous" value="0" desc="Timer runs while EN bit of CFG0 register is set to '1'." />
+ <value name="Pulsewidth" value="1" desc="Timer runs from positive to negative edge of TIMEREN." />
+ <value name="Period" value="10" desc="Timer runs from positive to positive edge of TIMEREN." />
+ <value name="Irq" value="11" desc="Timer runs until IRQ." />
+ </field>
+ <field name="COD" from="2" to="2" access="RW" resetVal="" desc="Clear On Disable (COD). Clears or gates outputs to zero." hidden="false" />
+ <field name="ROD" from="3" to="3" access="RW" resetVal="" desc="Reset On Disable (ROD). Resets internal state of output logic" hidden="false" />
+ <field name="CMP_CFG" from="6" to="4" access="RW" resetVal="" desc="Comparator configurations" hidden="false">
+ <value name="Equal" value="0" desc="Compare Equal " />
+ <value name="Less than" value="1" desc="Compare Less Than " />
+ <value name="Less than or equal" value="10" desc="Compare Less Than or Equal ." />
+ <value name="Greater" value="11" desc="Compare Greater Than ." />
+ <value name="Greater than or equal" value="100" desc="Compare Greater Than or Equal " />
+ </field>
+ <field name="HW_EN" from="7" to="7" access="RW" resetVal="" desc="When set Timer Enable controls counting." hidden="false" />
+ </register>
+ <register name="Debug_Timer_PERIOD" address="0x40004F04" bitWidth="16" desc="TMRx.PER0 - Assigned Period" hidden="false" />
+ <register name="Debug_Timer_COUNTER" address="0x40004F06" bitWidth="16" desc="TMRx.CNT_CMP0 - Current Down Counter Value" hidden="false" />
</block>
- <block name="Bootloadable_1" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
<block name="SCSI_Out_Mux" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false" />
+ <block name="SCSI_Out_Bits" BASE="0x0" SIZE="0x0" desc="" visible="true" hidden="false">
+ <register name="SCSI_Out_Bits_CONTROL_REG" address="0x4000657A" bitWidth="8" desc="" hidden="false" />
+ </block>
</blockRegMap>
\ No newline at end of file
<register>
<name>SCSI_Glitch_Ctl_CONTROL_REG</name>
<description>No description available</description>
- <addressOffset>0x4000647C</addressOffset>
+ <addressOffset>0x40006479</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>SCSI_Parity_Error_STATUS_REG</name>
<description>No description available</description>
- <addressOffset>0x40006568</addressOffset>
+ <addressOffset>0x4000646C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>SCSI_Parity_Error_MASK_REG</name>
<description>No description available</description>
- <addressOffset>0x40006588</addressOffset>
+ <addressOffset>0x4000648C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>SCSI_Parity_Error_STATUS_AUX_CTL_REG</name>
<description>No description available</description>
- <addressOffset>0x40006598</addressOffset>
+ <addressOffset>0x4000649C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>SCSI_Filtered_STATUS_REG</name>
<description>No description available</description>
- <addressOffset>0x4000646F</addressOffset>
+ <addressOffset>0x40006568</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>SCSI_Filtered_MASK_REG</name>
<description>No description available</description>
- <addressOffset>0x4000648F</addressOffset>
+ <addressOffset>0x40006588</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>SCSI_Filtered_STATUS_AUX_CTL_REG</name>
<description>No description available</description>
- <addressOffset>0x4000649F</addressOffset>
+ <addressOffset>0x40006598</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<register>
<name>SCSI_CTL_PHASE_CONTROL_REG</name>
<description>No description available</description>
- <addressOffset>0x4000647D</addressOffset>
+ <addressOffset>0x4000647F</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
</registers>
</peripheral>
<peripheral>
- <name>Debug_Timer</name>
- <description>No description available</description>
+ <name>USBFS</name>
+ <description>USBFS</description>
<baseAddress>0x0</baseAddress>
<addressBlock>
<offset>0</offset>
</addressBlock>
<registers>
<register>
- <name>Debug_Timer_GLOBAL_ENABLE</name>
- <description>PM.ACT.CFG</description>
- <addressOffset>0x400043A3</addressOffset>
+ <name>CR0</name>
+ <description>USB Control 0 Register</description>
+ <addressOffset>0x40006008</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
- <name>en_timer</name>
- <description>Enable timer/counters.</description>
+ <name>DEVICE_ADDRESS</name>
+ <description>These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware.</description>
<lsb>0</lsb>
- <msb>3</msb>
+ <msb>6</msb>
+ <access>read-only</access>
+ </field>
+ <field>
+ <name>USB_ENABLE</name>
+ <description>This bit enables the device to respond to USB traffic.</description>
+ <lsb>7</lsb>
+ <msb>7</msb>
<access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Disabled</name>
+ <description>Block responds to USB traffic.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Enabled</name>
+ <description>Block does not respond to USB traffic.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
</field>
</fields>
</register>
<register>
- <name>Debug_Timer_CONTROL</name>
- <description>TMRx.CFG0</description>
- <addressOffset>0x40004F00</addressOffset>
+ <name>CR1</name>
+ <description>USB Control 1 Register</description>
+ <addressOffset>0x40006009</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
- <name>EN</name>
- <description>Enables timer/comparator.</description>
+ <name>REG_ENABLE</name>
+ <description>This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply.</description>
<lsb>0</lsb>
<msb>0</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>MODE</name>
- <description>Mode. (0 = Timer; 1 = Comparator)</description>
- <lsb>1</lsb>
- <msb>1</msb>
- <access>read-write</access>
+ <access>read-only</access>
<enumeratedValues>
<enumeratedValue>
- <name>Timer</name>
- <description>Timer mode. CNT/CMP register holds timer count value.</description>
+ <name>Disabled</name>
+ <description>Regulator for 5V is disabled.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
- <name>Comparator</name>
- <description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>
+ <name>Enabled</name>
+ <description>Regulator for 5V is enabled.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
<field>
- <name>ONESHOT</name>
- <description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>
+ <name>ENABLE_LOCK</name>
+ <description>This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation.</description>
+ <lsb>1</lsb>
+ <msb>1</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>BUS_ACTIVITY</name>
+ <description>The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High value until firmware clears it.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
- <name>CMP_BUFF</name>
- <description>Buffer compare register. Compare register updates only on timer terminal count.</description>
+ <name>TRIM_OFFSET_MSB</name>
+ <description>This bit enables trim bit[7].</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
+ </fields>
+ </register>
+ <register>
+ <name>SIE_EP_INT_EN</name>
+ <description>USB SIE Data Endpoints Interrupt Enable Register</description>
+ <addressOffset>0x4000600A</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
<field>
- <name>INV</name>
- <description>Invert sense of TIMEREN signal</description>
+ <name>EP1_INTR_EN</name>
+ <description>Enables interrupt for EP1.</description>
+ <lsb>0</lsb>
+ <msb>0</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EP2_INTR_EN</name>
+ <description>Enables interrupt for EP2.</description>
+ <lsb>1</lsb>
+ <msb>1</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EP3_INTR_EN</name>
+ <description>Enables interrupt for EP3.</description>
+ <lsb>2</lsb>
+ <msb>2</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EP4_INTR_EN</name>
+ <description>Enables interrupt for EP4.</description>
+ <lsb>3</lsb>
+ <msb>3</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EP5_INTR_EN</name>
+ <description>Enables interrupt for EP5.</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
- <name>DB</name>
- <description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>
+ <name>EP6_INTR_EN</name>
+ <description>Enables interrupt for EP6.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>Timer</name>
- <description>CMP and TC are output.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Deadband</name>
- <description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
</field>
<field>
- <name>DEADBAND_PERIOD</name>
- <description>Deadband Period</description>
+ <name>EP7_INTR_EN</name>
+ <description>Enables interrupt for EP7.</description>
<lsb>6</lsb>
+ <msb>6</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EP8_INTR_EN</name>
+ <description>Enables interrupt for EP8.</description>
+ <lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
- <name>Debug_Timer_CONTROL2</name>
- <description>TMRx.CFG1</description>
- <addressOffset>0x40004F01</addressOffset>
+ <name>SIE_EP_INT_SR</name>
+ <description>SIE Data Endpoint Interrupt Status Register</description>
+ <addressOffset>0x4000600B</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
- <name>IRQ_SEL</name>
- <description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>
+ <name>EP1_INTR</name>
+ <description>Interrupt status for EP1.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
- <name>FTC</name>
- <description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>
+ <name>EP2_INTR</name>
+ <description>Interrupt status for EP2.</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>Disable_FTC</name>
- <description>Disable the single cycle pulse, which signifies the timer is starting.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Enable_FTC</name>
- <description>Enable the single cycle pulse, which signifies the timer is starting.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
</field>
<field>
- <name>DCOR</name>
- <description>Disable Clear on Read (DCOR) of Status Register SR0.</description>
+ <name>EP3_INTR</name>
+ <description>Interrupt status for EP3.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
- <name>DBMODE</name>
- <description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>
+ <name>EP4_INTR</name>
+ <description>Interrupt status for EP4.</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
- <name>CLK_BUS_EN_SEL</name>
- <description>Digital Global Clock selection.</description>
+ <name>EP5_INTR</name>
+ <description>Interrupt status for EP5.</description>
<lsb>4</lsb>
+ <msb>4</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EP6_INTR</name>
+ <description>Interrupt status for EP6.</description>
+ <lsb>5</lsb>
+ <msb>5</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>EP7_INTR</name>
+ <description>Interrupt status for EP7.</description>
+ <lsb>6</lsb>
<msb>6</msb>
<access>read-write</access>
</field>
<field>
- <name>BUS_CLK_SEL</name>
- <description>Bus Clock selection.</description>
+ <name>EP8_INTR</name>
+ <description>Interrupt status for EP8.</description>
<lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</fields>
</register>
<register>
- <name>Debug_Timer_CONTROL3_</name>
- <description>TMRx.CFG2</description>
- <addressOffset>0x40004F02</addressOffset>
+ <name>SIE_EP1_CNT0</name>
+ <description>SIE Endpoint 1 Count0 Register</description>
+ <addressOffset>0x4000600C</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
- <name>TMR_CFG</name>
- <description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>
+ <name>DATA_COUNT_MSB</name>
+ <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
<lsb>0</lsb>
- <msb>1</msb>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>Continuous</name>
- <description>Timer runs while EN bit of CFG0 register is set to '1'.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Pulsewidth</name>
- <description>Timer runs from positive to negative edge of TIMEREN.</description>
- <value>1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Period</name>
- <description>Timer runs from positive to positive edge of TIMEREN.</description>
- <value>2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Irq</name>
- <description>Timer runs until IRQ.</description>
- <value>3</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>COD</name>
- <description>Clear On Disable (COD). Clears or gates outputs to zero.</description>
- <lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
- <name>ROD</name>
- <description>Reset On Disable (ROD). Resets internal state of output logic</description>
- <lsb>3</lsb>
- <msb>3</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>CMP_CFG</name>
- <description>Comparator configurations</description>
- <lsb>4</lsb>
- <msb>6</msb>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>Equal</name>
- <description>Compare Equal </description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Less_than</name>
- <description>Compare Less Than </description>
- <value>1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Less_than_or_equal</name>
- <description>Compare Less Than or Equal .</description>
- <value>2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Greater</name>
- <description>Compare Greater Than .</description>
- <value>3</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Greater_than_or_equal</name>
- <description>Compare Greater Than or Equal </description>
- <value>4</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>HW_EN</name>
- <description>When set Timer Enable controls counting.</description>
- <lsb>7</lsb>
- <msb>7</msb>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>Debug_Timer_PERIOD</name>
- <description>TMRx.PER0 - Assigned Period</description>
- <addressOffset>0x40004F04</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- <register>
- <name>Debug_Timer_COUNTER</name>
- <description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
- <addressOffset>0x40004F06</addressOffset>
- <size>16</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- </register>
- </registers>
- </peripheral>
- <peripheral>
- <name>USBFS</name>
- <description>USBFS</description>
- <baseAddress>0x0</baseAddress>
- <addressBlock>
- <offset>0</offset>
- <size>0x0</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>CR0</name>
- <description>USB Control 0 Register</description>
- <addressOffset>0x40006008</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- <fields>
- <field>
- <name>DEVICE_ADDRESS</name>
- <description>These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware.</description>
- <lsb>0</lsb>
- <msb>6</msb>
- <access>read-only</access>
- </field>
- <field>
- <name>USB_ENABLE</name>
- <description>This bit enables the device to respond to USB traffic.</description>
- <lsb>7</lsb>
- <msb>7</msb>
- <access>read-write</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>Disabled</name>
- <description>Block responds to USB traffic.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Enabled</name>
- <description>Block does not respond to USB traffic.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
- <register>
- <name>CR1</name>
- <description>USB Control 1 Register</description>
- <addressOffset>0x40006009</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- <fields>
- <field>
- <name>REG_ENABLE</name>
- <description>This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply.</description>
- <lsb>0</lsb>
- <msb>0</msb>
- <access>read-only</access>
- <enumeratedValues>
- <enumeratedValue>
- <name>Disabled</name>
- <description>Regulator for 5V is disabled.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Enabled</name>
- <description>Regulator for 5V is enabled.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>ENABLE_LOCK</name>
- <description>This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation.</description>
- <lsb>1</lsb>
- <msb>1</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>BUS_ACTIVITY</name>
- <description>The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High value until firmware clears it.</description>
- <lsb>2</lsb>
- <msb>2</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>TRIM_OFFSET_MSB</name>
- <description>This bit enables trim bit[7].</description>
- <lsb>3</lsb>
- <msb>3</msb>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>SIE_EP_INT_EN</name>
- <description>USB SIE Data Endpoints Interrupt Enable Register</description>
- <addressOffset>0x4000600A</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- <fields>
- <field>
- <name>EP1_INTR_EN</name>
- <description>Enables interrupt for EP1.</description>
- <lsb>0</lsb>
- <msb>0</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>EP2_INTR_EN</name>
- <description>Enables interrupt for EP2.</description>
- <lsb>1</lsb>
- <msb>1</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>EP3_INTR_EN</name>
- <description>Enables interrupt for EP3.</description>
- <lsb>2</lsb>
- <msb>2</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>EP4_INTR_EN</name>
- <description>Enables interrupt for EP4.</description>
- <lsb>3</lsb>
- <msb>3</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>EP5_INTR_EN</name>
- <description>Enables interrupt for EP5.</description>
- <lsb>4</lsb>
- <msb>4</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>EP6_INTR_EN</name>
- <description>Enables interrupt for EP6.</description>
- <lsb>5</lsb>
- <msb>5</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>EP7_INTR_EN</name>
- <description>Enables interrupt for EP7.</description>
- <lsb>6</lsb>
- <msb>6</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>EP8_INTR_EN</name>
- <description>Enables interrupt for EP8.</description>
- <lsb>7</lsb>
- <msb>7</msb>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>SIE_EP_INT_SR</name>
- <description>SIE Data Endpoint Interrupt Status Register</description>
- <addressOffset>0x4000600B</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- <fields>
- <field>
- <name>EP1_INTR</name>
- <description>Interrupt status for EP1.</description>
- <lsb>0</lsb>
- <msb>0</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>EP2_INTR</name>
- <description>Interrupt status for EP2.</description>
- <lsb>1</lsb>
- <msb>1</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>EP3_INTR</name>
- <description>Interrupt status for EP3.</description>
- <lsb>2</lsb>
- <msb>2</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>EP4_INTR</name>
- <description>Interrupt status for EP4.</description>
- <lsb>3</lsb>
- <msb>3</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>EP5_INTR</name>
- <description>Interrupt status for EP5.</description>
- <lsb>4</lsb>
- <msb>4</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>EP6_INTR</name>
- <description>Interrupt status for EP6.</description>
- <lsb>5</lsb>
- <msb>5</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>EP7_INTR</name>
- <description>Interrupt status for EP7.</description>
- <lsb>6</lsb>
- <msb>6</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>EP8_INTR</name>
- <description>Interrupt status for EP8.</description>
- <lsb>7</lsb>
- <msb>7</msb>
- <access>read-write</access>
- </field>
- </fields>
- </register>
- <register>
- <name>SIE_EP1_CNT0</name>
- <description>SIE Endpoint 1 Count0 Register</description>
- <addressOffset>0x4000600C</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- <fields>
- <field>
- <name>DATA_COUNT_MSB</name>
- <description>These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information.</description>
- <lsb>0</lsb>
- <msb>2</msb>
- <access>read-write</access>
- </field>
- <field>
- <name>DATA_VALID</name>
- <description>DATA_ERROR - 0, DATA_VALID - 1.</description>
- <lsb>4</lsb>
- <msb>4</msb>
+ <name>DATA_VALID</name>
+ <description>DATA_ERROR - 0, DATA_VALID - 1.</description>
+ <lsb>4</lsb>
+ <msb>4</msb>
<access>read-write</access>
</field>
<field>
<resetMask>0</resetMask>
<fields>
<field>
- <name>IN_BUF_FULL_EN</name>
- <description>IN Endpoint Local Buffer Full</description>
+ <name>IN_BUF_FULL_EN</name>
+ <description>IN Endpoint Local Buffer Full</description>
+ <lsb>0</lsb>
+ <msb>0</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>DMA_GNT_EN</name>
+ <description>Endpoint DMA Grant</description>
+ <lsb>1</lsb>
+ <msb>1</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>BUF_OVER_EN</name>
+ <description>Endpoint Buffer Overflow</description>
+ <lsb>2</lsb>
+ <msb>2</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>BUF_UNDER_EN</name>
+ <description>Endpoint Buffer Underflow</description>
+ <lsb>3</lsb>
+ <msb>3</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ERR_INT_EN</name>
+ <description>Endpoint Error in Transaction Interrupt</description>
+ <lsb>4</lsb>
+ <msb>4</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>DMA_TERMIN_EN</name>
+ <description>Endpoint DMA Terminated Enable</description>
+ <lsb>5</lsb>
+ <msb>5</msb>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ARB_EP4_INT_SR</name>
+ <description>Arbiter Endpoint 1 Interrupt Status Register</description>
+ <addressOffset>0x400060B2</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>IN_BUF_FULL_EN</name>
+ <description>IN Endpoint Local Buffer Full</description>
+ <lsb>0</lsb>
+ <msb>0</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>DMA_GNT_EN</name>
+ <description>Endpoint DMA Grant</description>
+ <lsb>1</lsb>
+ <msb>1</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>BUF_OVER_EN</name>
+ <description>Endpoint Buffer Overflow</description>
+ <lsb>2</lsb>
+ <msb>2</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>BUF_UNDER_EN</name>
+ <description>Endpoint Buffer Underflow</description>
+ <lsb>3</lsb>
+ <msb>3</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>ERR_INT_EN</name>
+ <description>Endpoint Error in Transaction Interrupt</description>
+ <lsb>4</lsb>
+ <msb>4</msb>
+ <access>read-write</access>
+ </field>
+ <field>
+ <name>DMA_TERMIN_EN</name>
+ <description>Endpoint DMA Terminated Enable</description>
+ <lsb>5</lsb>
+ <msb>5</msb>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ARB_RW4_WA</name>
+ <description>Arbiter Endpoint 1 Write Address LSB Register</description>
+ <addressOffset>0x400060B4</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>WA8</name>
+ <description>Write Address for EP.</description>
+ <lsb>0</lsb>
+ <msb>7</msb>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ARB_RW4_WA_MSB</name>
+ <description>Arbiter Endpoint 1 Write Address MSB Register</description>
+ <addressOffset>0x400060B5</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>WA9</name>
+ <description>Write Address for EP MSB.</description>
+ <lsb>0</lsb>
+ <msb>0</msb>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ARB_RW4_RA</name>
+ <description>Arbiter Endpoint 1 Read Address LSB Register</description>
+ <addressOffset>0x400060B6</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>RA8</name>
+ <description>Read Address for EP MSB.</description>
+ <lsb>0</lsb>
+ <msb>7</msb>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>ARB_RW4_RA_MSB</name>
+ <description>Arbiter Endpoint 1 Read Address MSB Register</description>
+ <addressOffset>0x400060B7</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>RA9</name>
+ <description>Read Address for EP MSB.</description>
+ <lsb>0</lsb>
+ <msb>0</msb>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>SCSI_Out_Ctl</name>
+ <description>No description available</description>
+ <baseAddress>0x0</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x0</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>SCSI_Out_Ctl_CONTROL_REG</name>
+ <description>No description available</description>
+ <addressOffset>0x40006478</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ </register>
+ </registers>
+ </peripheral>
+ <peripheral>
+ <name>Debug_Timer</name>
+ <description>No description available</description>
+ <baseAddress>0x0</baseAddress>
+ <addressBlock>
+ <offset>0</offset>
+ <size>0x0</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>Debug_Timer_GLOBAL_ENABLE</name>
+ <description>PM.ACT.CFG</description>
+ <addressOffset>0x400043A3</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>en_timer</name>
+ <description>Enable timer/counters.</description>
+ <lsb>0</lsb>
+ <msb>3</msb>
+ <access>read-write</access>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>Debug_Timer_CONTROL</name>
+ <description>TMRx.CFG0</description>
+ <addressOffset>0x40004F00</addressOffset>
+ <size>8</size>
+ <access>read-write</access>
+ <resetValue>0</resetValue>
+ <resetMask>0</resetMask>
+ <fields>
+ <field>
+ <name>EN</name>
+ <description>Enables timer/comparator.</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
- <name>DMA_GNT_EN</name>
- <description>Endpoint DMA Grant</description>
+ <name>MODE</name>
+ <description>Mode. (0 = Timer; 1 = Comparator)</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Timer</name>
+ <description>Timer mode. CNT/CMP register holds timer count value.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Comparator</name>
+ <description>Comparator mode. CNT/CMP register holds comparator threshold value.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
</field>
<field>
- <name>BUF_OVER_EN</name>
- <description>Endpoint Buffer Overflow</description>
+ <name>ONESHOT</name>
+ <description>Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
- <name>BUF_UNDER_EN</name>
- <description>Endpoint Buffer Underflow</description>
+ <name>CMP_BUFF</name>
+ <description>Buffer compare register. Compare register updates only on timer terminal count.</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
- <name>ERR_INT_EN</name>
- <description>Endpoint Error in Transaction Interrupt</description>
+ <name>INV</name>
+ <description>Invert sense of TIMEREN signal</description>
<lsb>4</lsb>
<msb>4</msb>
<access>read-write</access>
</field>
<field>
- <name>DMA_TERMIN_EN</name>
- <description>Endpoint DMA Terminated Enable</description>
+ <name>DB</name>
+ <description>Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.</description>
<lsb>5</lsb>
<msb>5</msb>
<access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Timer</name>
+ <description>CMP and TC are output.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Deadband</name>
+ <description>PHI1 (instead of CMP) and PHI2 (instead of TC) are output.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>DEADBAND_PERIOD</name>
+ <description>Deadband Period</description>
+ <lsb>6</lsb>
+ <msb>7</msb>
+ <access>read-write</access>
</field>
</fields>
</register>
<register>
- <name>ARB_EP4_INT_SR</name>
- <description>Arbiter Endpoint 1 Interrupt Status Register</description>
- <addressOffset>0x400060B2</addressOffset>
+ <name>Debug_Timer_CONTROL2</name>
+ <description>TMRx.CFG1</description>
+ <addressOffset>0x40004F01</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
- <name>IN_BUF_FULL_EN</name>
- <description>IN Endpoint Local Buffer Full</description>
+ <name>IRQ_SEL</name>
+ <description>Irq selection. (0 = raw interrupts; 1 = status register interrupts)</description>
<lsb>0</lsb>
<msb>0</msb>
<access>read-write</access>
</field>
<field>
- <name>DMA_GNT_EN</name>
- <description>Endpoint DMA Grant</description>
+ <name>FTC</name>
+ <description>First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.</description>
<lsb>1</lsb>
<msb>1</msb>
<access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Disable_FTC</name>
+ <description>Disable the single cycle pulse, which signifies the timer is starting.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Enable_FTC</name>
+ <description>Enable the single cycle pulse, which signifies the timer is starting.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
</field>
<field>
- <name>BUF_OVER_EN</name>
- <description>Endpoint Buffer Overflow</description>
+ <name>DCOR</name>
+ <description>Disable Clear on Read (DCOR) of Status Register SR0.</description>
<lsb>2</lsb>
<msb>2</msb>
<access>read-write</access>
</field>
<field>
- <name>BUF_UNDER_EN</name>
- <description>Endpoint Buffer Underflow</description>
+ <name>DBMODE</name>
+ <description>Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).</description>
<lsb>3</lsb>
<msb>3</msb>
<access>read-write</access>
</field>
<field>
- <name>ERR_INT_EN</name>
- <description>Endpoint Error in Transaction Interrupt</description>
+ <name>CLK_BUS_EN_SEL</name>
+ <description>Digital Global Clock selection.</description>
<lsb>4</lsb>
- <msb>4</msb>
+ <msb>6</msb>
<access>read-write</access>
</field>
<field>
- <name>DMA_TERMIN_EN</name>
- <description>Endpoint DMA Terminated Enable</description>
- <lsb>5</lsb>
- <msb>5</msb>
+ <name>BUS_CLK_SEL</name>
+ <description>Bus Clock selection.</description>
+ <lsb>7</lsb>
+ <msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
- <name>ARB_RW4_WA</name>
- <description>Arbiter Endpoint 1 Write Address LSB Register</description>
- <addressOffset>0x400060B4</addressOffset>
+ <name>Debug_Timer_CONTROL3_</name>
+ <description>TMRx.CFG2</description>
+ <addressOffset>0x40004F02</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
<fields>
<field>
- <name>WA8</name>
- <description>Write Address for EP.</description>
+ <name>TMR_CFG</name>
+ <description>Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ</description>
<lsb>0</lsb>
- <msb>7</msb>
+ <msb>1</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Continuous</name>
+ <description>Timer runs while EN bit of CFG0 register is set to '1'.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Pulsewidth</name>
+ <description>Timer runs from positive to negative edge of TIMEREN.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Period</name>
+ <description>Timer runs from positive to positive edge of TIMEREN.</description>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Irq</name>
+ <description>Timer runs until IRQ.</description>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>COD</name>
+ <description>Clear On Disable (COD). Clears or gates outputs to zero.</description>
+ <lsb>2</lsb>
+ <msb>2</msb>
<access>read-write</access>
</field>
- </fields>
- </register>
- <register>
- <name>ARB_RW4_WA_MSB</name>
- <description>Arbiter Endpoint 1 Write Address MSB Register</description>
- <addressOffset>0x400060B5</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- <fields>
<field>
- <name>WA9</name>
- <description>Write Address for EP MSB.</description>
- <lsb>0</lsb>
- <msb>0</msb>
+ <name>ROD</name>
+ <description>Reset On Disable (ROD). Resets internal state of output logic</description>
+ <lsb>3</lsb>
+ <msb>3</msb>
<access>read-write</access>
</field>
- </fields>
- </register>
- <register>
- <name>ARB_RW4_RA</name>
- <description>Arbiter Endpoint 1 Read Address LSB Register</description>
- <addressOffset>0x400060B6</addressOffset>
- <size>8</size>
- <access>read-write</access>
- <resetValue>0</resetValue>
- <resetMask>0</resetMask>
- <fields>
<field>
- <name>RA8</name>
- <description>Read Address for EP MSB.</description>
- <lsb>0</lsb>
+ <name>CMP_CFG</name>
+ <description>Comparator configurations</description>
+ <lsb>4</lsb>
+ <msb>6</msb>
+ <access>read-write</access>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Equal</name>
+ <description>Compare Equal </description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Less_than</name>
+ <description>Compare Less Than </description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Less_than_or_equal</name>
+ <description>Compare Less Than or Equal .</description>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Greater</name>
+ <description>Compare Greater Than .</description>
+ <value>3</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>Greater_than_or_equal</name>
+ <description>Compare Greater Than or Equal </description>
+ <value>4</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>HW_EN</name>
+ <description>When set Timer Enable controls counting.</description>
+ <lsb>7</lsb>
<msb>7</msb>
<access>read-write</access>
</field>
</fields>
</register>
<register>
- <name>ARB_RW4_RA_MSB</name>
- <description>Arbiter Endpoint 1 Read Address MSB Register</description>
- <addressOffset>0x400060B7</addressOffset>
- <size>8</size>
+ <name>Debug_Timer_PERIOD</name>
+ <description>TMRx.PER0 - Assigned Period</description>
+ <addressOffset>0x40004F04</addressOffset>
+ <size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
- <fields>
- <field>
- <name>RA9</name>
- <description>Read Address for EP MSB.</description>
- <lsb>0</lsb>
- <msb>0</msb>
- <access>read-write</access>
- </field>
- </fields>
</register>
- </registers>
- </peripheral>
- <peripheral>
- <name>SCSI_Out_Bits</name>
- <description>No description available</description>
- <baseAddress>0x0</baseAddress>
- <addressBlock>
- <offset>0</offset>
- <size>0x0</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
<register>
- <name>SCSI_Out_Bits_CONTROL_REG</name>
- <description>No description available</description>
- <addressOffset>0x40006473</addressOffset>
- <size>8</size>
+ <name>Debug_Timer_COUNTER</name>
+ <description>TMRx.CNT_CMP0 - Current Down Counter Value</description>
+ <addressOffset>0x40004F06</addressOffset>
+ <size>16</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</registers>
</peripheral>
<peripheral>
- <name>SCSI_Out_Ctl</name>
+ <name>SCSI_Out_Bits</name>
<description>No description available</description>
<baseAddress>0x0</baseAddress>
<addressBlock>
</addressBlock>
<registers>
<register>
- <name>SCSI_Out_Ctl_CONTROL_REG</name>
+ <name>SCSI_Out_Bits_CONTROL_REG</name>
<description>No description available</description>
- <addressOffset>0x40006471</addressOffset>
+ <addressOffset>0x4000657A</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
projects / SCSI2SD.git / commitdiff